[PATCH] Support for perf on AMD family17h processors

[PATCH] Support for perf on AMD family17h processors

[Janakarajan Natarajan]

This patch enables perf core PMU support for AMD family17h processors.
In family17h, there is no PMC-event constraint. All events, irrespective
of the type, can be measured using any of the performance counters.

Signed-off-by: Janakarajan Natarajan <Janakarajan.Natarajan@amd.com>
---
 arch/x86/events/amd/core.c | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
index f5f4b3f..849688d 100644
--- a/arch/x86/events/amd/core.c
+++ b/arch/x86/events/amd/core.c
@@ -652,7 +652,11 @@ static __initconst const struct x86_pmu amd_pmu = {
 	.amd_nb_constraints	= 1,
 };
 
-static int __init amd_core_pmu_init(void)
+/*
+ * This function initializes core PMU to enable support
+ * for AMD Core PMC Extension.
+ */
+static int __init amd_core_pmc_ext_init(void)
 {
 	if (!boot_cpu_has(X86_FEATURE_PERFCTR_CORE))
 		return 0;
@@ -662,7 +666,12 @@ static int __init amd_core_pmu_init(void)
 		pr_cont("Fam15h ");
 		x86_pmu.get_event_constraints = amd_get_event_constraints_f15h;
 		break;
-
+	case 0x17:
+		pr_cont("Fam17h ");
+		/* In family 17h, there are no event constraints in the PMC hardware.
+		 * We fallback to using default amd_get_event_constraints.
+		 */
+		break;
 	default:
 		pr_err("core perfctr but no constraints; unknown hardware!\n");
 		return -ENODEV;
@@ -696,7 +705,7 @@ __init int amd_pmu_init(void)
 
 	x86_pmu = amd_pmu;
 
-	ret = amd_core_pmu_init();
+	ret = amd_core_pmc_ext_init();
 	if (ret)
 		return ret;
 
-- 
2.7.4

Re: [PATCH] Support for perf on AMD family17h processors

[Peter Zijlstra]

On Wed, Nov 16, 2016 at 11:01:53AM -0600, Janakarajan Natarajan wrote:
> This patch enables perf core PMU support for AMD family17h processors.
> In family17h, there is no PMC-event constraint. All events, irrespective
> of the type, can be measured using any of the performance counters.
> 

Is there a public document describing this thing about already?

> +	case 0x17:
> +		pr_cont("Fam17h ");
> +		/* In family 17h, there are no event constraints in the PMC hardware.
> +		 * We fallback to using default amd_get_event_constraints.
> +		 */
> +		break;

 http://lkml.kernel.org/r/CA+55aFyQYJerovMsSoSKS7PessZBr4vNp-3QUUwhqk4A4_jcbg@mail.gmail.com

Re: [PATCH] Support for perf on AMD family17h processors

[Natarajan, Janakarajan]

On 11/16/2016 11:30 AM, Peter Zijlstra wrote:
> On Wed, Nov 16, 2016 at 11:01:53AM -0600, Janakarajan Natarajan wrote:
>> This patch enables perf core PMU support for AMD family17h processors.
>> In family17h, there is no PMC-event constraint. All events, irrespective
>> of the type, can be measured using any of the performance counters.
>>
> Is there a public document describing this thing about already?
There is no document published as of now.
>
>> +	case 0x17:
>> +		pr_cont("Fam17h ");
>> +		/* In family 17h, there are no event constraints in the PMC hardware.
>> +		 * We fallback to using default amd_get_event_constraints.
>> +		 */
>> +		break;
>   http://lkml.kernel.org/r/CA+55aFyQYJerovMsSoSKS7PessZBr4vNp-3QUUwhqk4A4_jcbg@mail.gmail.com
I'll send out a v2 patch for the comment following the guidelines.

Re: [PATCH] Support for perf on AMD family17h processors

[Borislav Petkov]

On Wed, Nov 16, 2016 at 11:01:53AM -0600, Janakarajan Natarajan wrote:
> This patch enables perf core PMU support for AMD family17h processors.
> In family17h, there is no PMC-event constraint. All events, irrespective
> of the type, can be measured using any of the performance counters.
> 
> Signed-off-by: Janakarajan Natarajan <Janakarajan.Natarajan@amd.com>
> ---
>  arch/x86/events/amd/core.c | 15 ++++++++++++---
>  1 file changed, 12 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
> index f5f4b3f..849688d 100644
> --- a/arch/x86/events/amd/core.c
> +++ b/arch/x86/events/amd/core.c
> @@ -652,7 +652,11 @@ static __initconst const struct x86_pmu amd_pmu = {
>  	.amd_nb_constraints	= 1,
>  };
>  
> -static int __init amd_core_pmu_init(void)
> +/*
> + * This function initializes core PMU to enable support
> + * for AMD Core PMC Extension.
> + */
> +static int __init amd_core_pmc_ext_init(void)
>  {
>  	if (!boot_cpu_has(X86_FEATURE_PERFCTR_CORE))
>  		return 0;

This renaming looks pretty useless to me. So does the comment.

-- 
Regards/Gruss,
    Boris.

Good mailing practices for 400: avoid top-posting and trim the reply.

Re: [PATCH] Support for perf on AMD family17h processors

[Natarajan, Janakarajan]

On 11/16/2016 12:47 PM, Borislav Petkov wrote:
> On Wed, Nov 16, 2016 at 11:01:53AM -0600, Janakarajan Natarajan wrote:
>> This patch enables perf core PMU support for AMD family17h processors.
>> In family17h, there is no PMC-event constraint. All events, irrespective
>> of the type, can be measured using any of the performance counters.
>>
>> Signed-off-by: Janakarajan Natarajan <Janakarajan.Natarajan@amd.com>
>> ---
>>   arch/x86/events/amd/core.c | 15 ++++++++++++---
>>   1 file changed, 12 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
>> index f5f4b3f..849688d 100644
>> --- a/arch/x86/events/amd/core.c
>> +++ b/arch/x86/events/amd/core.c
>> @@ -652,7 +652,11 @@ static __initconst const struct x86_pmu amd_pmu = {
>>   	.amd_nb_constraints	= 1,
>>   };
>>   
>> -static int __init amd_core_pmu_init(void)
>> +/*
>> + * This function initializes core PMU to enable support
>> + * for AMD Core PMC Extension.
>> + */
>> +static int __init amd_core_pmc_ext_init(void)
>>   {
>>   	if (!boot_cpu_has(X86_FEATURE_PERFCTR_CORE))
>>   		return 0;
> This renaming looks pretty useless to me. So does the comment.
I'll remove the renaming and comment in a v2 patch.
>

Re: [PATCH] Support for perf on AMD family17h processors

[Ingo Molnar]

* Janakarajan Natarajan <Janakarajan.Natarajan@amd.com> wrote:

> This patch enables perf core PMU support for AMD family17h processors. In 
> family17h, there is no PMC-event constraint. All events, irrespective of the 
> type, can be measured using any of the performance counters.

BTW., that's a very nice hardware design that simplifies counter constraints and 
scheduling!

Does Fam17h have 6 generic counters per core, like Fam15h?

Thanks,

	Ingo

Re: [PATCH] Support for perf on AMD family17h processors

[Natarajan, Janakarajan]

On 11/17/2016 12:46 AM, Ingo Molnar wrote:
> * Janakarajan Natarajan <Janakarajan.Natarajan@amd.com> wrote:
>
>> This patch enables perf core PMU support for AMD family17h processors. In
>> family17h, there is no PMC-event constraint. All events, irrespective of the
>> type, can be measured using any of the performance counters.
> BTW., that's a very nice hardware design that simplifies counter constraints and
> scheduling!
>
> Does Fam17h have 6 generic counters per core, like Fam15h?
Yes. Fam17h has 6 generic core counters.
>
> Thanks,
>
> 	Ingo