* [Qemu-devel] [PATCH RFC v3 00/21] Introduce QOM CPU and use it for ARM
@ 2012-02-03 2:59 Andreas Färber
2012-02-03 2:59 ` [Qemu-devel] [PATCH v3 01/21] qom: Register QOM infrastructure early Andreas Färber
` (20 more replies)
0 siblings, 21 replies; 47+ messages in thread
From: Andreas Färber @ 2012-02-03 2:59 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Andreas Färber
Hello,
Here's an improved and extended series on incrementally converting CPUState
to QOM, rebased onto Anthony's qom-upstream.14 plus some master updates.
The general idea behind the series is to cease having CPU-dependent code
in generic functions, in favor of storing constant data in CPU classes and
letting instance methods either be dumb initializations or overwritten.
After the initial introduction of the types, this series is mainly mechanical
code movement. This series does NOT yet...
...model ARM CPU has-a cp15 register,
...introduce SoCs (child<CPU> plus devices),
...touch machines.
Patch 1 rearranges module init for QOM, so that objects can really be used
beyond devices. Introduces a neutral type_init() macro for new types.
Does not depend on 3rd QOM series and could be cherry-picked.
Patch 2 adds QOM support to the user emulators. Note that more dependencies
and some stubs were now needed to successfully compile.
Patch 3 introduces the QOM CPU base class.
Patches 4-19 derive and start using a QOM CPU for ARM.
Patch 5 integrates legacy CPUARMState into QOM.
Patch 7 is a proof of concept for CPUState -> CPU lookup.
Patch 19 completes freeing cpu_reset() and cpu_arm_init() of any model logic.
Patch 20 adds a sample read-only property accessing legacy CPUState.
Patch 21 is a hack to allow inspecting this using
QMP/qmp qom-list --path=/cpu --property=halted
For some reason the logic seems inverted (False for -S, True while running)...
Available at:
http://repo.or.cz/w/qemu/afaerber.git/shortlog/refs/heads/qom-cpu.v3
TODO: We might want to sort -cpu ? alphabetically; object_class_foreach()
prints them in hash table order.
Agenda:
AF: Convert one other target as proof of concept.
Once Anthony's 3rd QOM series is merged, sort out and merge (what is now) 1-19.
all: Incrementally (hopefully in parallel) derive QOM CPUs for all targets.
Only when all targets are converted will it be possible to move fields from
CPU_COMMON into CPU, to add properties in common code, to simplify some
function names and to eliminate CPUState *env in core code!
Regards,
Andreas
Cc: Anthony Liguori <anthony@codemonkey.ws>
Cc: Peter Maydell <peter.maydell@linaro.org>
v2 -> v3:
* Rebased against qom-upstream.14 branch (and that against master).
* Build common dependencies for user emulators in libuser/.
* New dependencies needed after moving properties into object.c.
* Add a qemu-user.c with stubs needed for successful linking.
* Move cpu.c from hw/ to qom/ (built only once).
* Use proper GPL headers.
* Rename target-arm/cpu-core.c to cpu.c now that we no longer need VPATH.
* Leave cpu-core.h as is to separate from legacy cpu.h.
* Fix -cpu alias "pxa270": handled in cpu_arm_init().
* Use proper GPL headers.
* Start removing CPUID uses in cpu_reset_model_id() and cpu.h.
* Fully convert cpu_reset_model_id() to ARMCPUInfo or per-model code.
* Experiment with adding properties.
v1 -> v2:
* Cherry-pick Anthony's object_class_foreach() patch.
* Don't introduce extra early_init(), just relocate former MODULE_INIT_DEVICE.
* Provide new type_init() macro to be used instead of device_init().
* Drop processor_init() and MODULE_INIT_CPU in favor of MODULE_INIT_DEVICE.
* Prepare cast macros for CPU.
* Add documentation.
* Fix ARMCPUClass type name (arm-cpu-core -> arm-cpu).
* Add documentation.
* Rename ARMCPUDef to ARMCPUInfo.
* Use a C99-style table for initializing the classes through class_data
instead of individual class_init functions (suggested by Anthony).
* Prepare reset callback.
* Make ENV_GET_OBJECT() use an inline function for readability.
* Invoke the CPU's reset method from cpu_reset().
* Do feature initialization via table where sensible.
* Add feature flags to ARMCPU as well (suggested by PMM for future tweaking,
also simplifies load/save a bit) and initialize them from ARMCPUClass.
* Make feature inference work for ARMCPU as well by not passing the ARMCPUClass.
Use function-local macros to avoid the ugliness of deferencing the features pointer.
Andreas Färber (21):
qom: Register QOM infrastructure early
qom: Add QOM support to user emulators
qom: Introduce CPU class
target-arm: Introduce QOM CPU and use it for CPUID lookup
target-arm: Embed CPUARMState in QOM ARMCPU
target-arm: Prepare model-specific class_init function
target-arm: Overwrite reset handler for ti925t
target-arm: Move CPU feature flags out of CPUState
target-arm: No longer abort on unhandled CPUIDs on reset
target-arm: Store cp15 c0_c1 and c0_c2 in ARMCPUClass
target-arm: Store cp15 c0_cachetype register in ARMCPUClass
target-arm: Move cp15 c1_sys register to ARMCPUClass
target-arm: Store JTAG_ID in ARMCPUClass
target-arm: Move the PXA270's iwMMXt reset to pxa270_reset()
target-arm: Store VFP FPSID register in ARMCPUClass
target-arm: Store VFP MVFR0 and MVFR1 in ARMCPUClass
target-arm: Store CLIDR in ARMCPUClass
target-arm: Store CCSIDRs in ARMCPUClass
target-arm: Kill off cpu_reset_model_id()
target-arm: Prepare halted property for CPU
target-arm: Just for testing!
Makefile.objs | 6 +
Makefile.target | 1 +
Makefile.user | 1 +
bsd-user/main.c | 2 +
configure | 2 +
darwin-user/main.c | 3 +
include/qemu/cpu.h | 73 ++++++
linux-user/main.c | 2 +
module.h | 5 +-
qemu-user.c | 37 +++
qom/Makefile | 1 +
qom/cpu.c | 50 ++++
target-arm/cpu-core.h | 93 ++++++++
target-arm/cpu.c | 631 +++++++++++++++++++++++++++++++++++++++++++++++++
target-arm/cpu.h | 27 +--
target-arm/helper.c | 425 +++------------------------------
target-arm/machine.c | 6 +-
vl.c | 4 +-
18 files changed, 944 insertions(+), 425 deletions(-)
create mode 100644 include/qemu/cpu.h
create mode 100644 qemu-user.c
create mode 100644 qom/cpu.c
create mode 100644 target-arm/cpu-core.h
create mode 100644 target-arm/cpu.c
--
1.7.7
^ permalink raw reply [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH v3 01/21] qom: Register QOM infrastructure early
2012-02-03 2:59 [Qemu-devel] [PATCH RFC v3 00/21] Introduce QOM CPU and use it for ARM Andreas Färber
@ 2012-02-03 2:59 ` Andreas Färber
2012-02-06 19:14 ` Anthony Liguori
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 02/21] qom: Add QOM support to user emulators Andreas Färber
` (19 subsequent siblings)
20 siblings, 1 reply; 47+ messages in thread
From: Andreas Färber @ 2012-02-03 2:59 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
QOM TYPE_INTERFACE was registered with device_init(), whose
constructors are executed rather late in vl.c's main().
Rename the module init type from DEVICE to QOM and call it very early
so that QOM can safely be used for machines and CPUs.
device_init() is left for legacy types. New ones should use type_init().
Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Anthony Liguori <anthony@codemonkey.ws>
---
module.h | 5 +++--
vl.c | 4 ++--
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/module.h b/module.h
index ef66730..56391a5 100644
--- a/module.h
+++ b/module.h
@@ -21,15 +21,16 @@ static void __attribute__((constructor)) do_qemu_init_ ## function(void) { \
}
typedef enum {
+ MODULE_INIT_QOM,
MODULE_INIT_BLOCK,
- MODULE_INIT_DEVICE,
MODULE_INIT_MACHINE,
MODULE_INIT_QAPI,
MODULE_INIT_MAX
} module_init_type;
+#define type_init(function) module_init(function, MODULE_INIT_QOM)
#define block_init(function) module_init(function, MODULE_INIT_BLOCK)
-#define device_init(function) module_init(function, MODULE_INIT_DEVICE)
+#define device_init(function) module_init(function, MODULE_INIT_QOM)
#define machine_init(function) module_init(function, MODULE_INIT_MACHINE)
#define qapi_init(function) module_init(function, MODULE_INIT_QAPI)
diff --git a/vl.c b/vl.c
index 2d464cf..8f2fc3c 100644
--- a/vl.c
+++ b/vl.c
@@ -2221,6 +2221,8 @@ int main(int argc, char **argv, char **envp)
#endif
}
+ module_call_init(MODULE_INIT_QOM);
+
runstate_init();
init_clocks();
@@ -3357,8 +3359,6 @@ int main(int argc, char **argv, char **envp)
if (foreach_device_config(DEV_DEBUGCON, debugcon_parse) < 0)
exit(1);
- module_call_init(MODULE_INIT_DEVICE);
-
/* must be after qdev registration but before machine init */
if (vga_model) {
select_vgahw(vga_model);
--
1.7.7
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH RFC v3 02/21] qom: Add QOM support to user emulators
2012-02-03 2:59 [Qemu-devel] [PATCH RFC v3 00/21] Introduce QOM CPU and use it for ARM Andreas Färber
2012-02-03 2:59 ` [Qemu-devel] [PATCH v3 01/21] qom: Register QOM infrastructure early Andreas Färber
@ 2012-02-03 2:59 ` Andreas Färber
2012-02-06 19:16 ` Anthony Liguori
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 03/21] qom: Introduce CPU class Andreas Färber
` (18 subsequent siblings)
20 siblings, 1 reply; 47+ messages in thread
From: Andreas Färber @ 2012-02-03 2:59 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Link the Object base class and the module infrastructure for class
registration. Call QOM module init.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Anthony Liguori <anthony@codemonkey.ws>
---
Makefile.objs | 6 ++++++
Makefile.user | 1 +
bsd-user/main.c | 2 ++
configure | 2 ++
darwin-user/main.c | 3 +++
linux-user/main.c | 2 ++
qemu-user.c | 37 +++++++++++++++++++++++++++++++++++++
7 files changed, 53 insertions(+), 0 deletions(-)
create mode 100644 qemu-user.c
diff --git a/Makefile.objs b/Makefile.objs
index ec35320..1155cc0 100644
--- a/Makefile.objs
+++ b/Makefile.objs
@@ -182,7 +182,11 @@ user-obj-y =
user-obj-y += envlist.o path.o
user-obj-y += tcg-runtime.o host-utils.o
user-obj-y += cutils.o cache-utils.o
+user-obj-y += module.o
+user-obj-y += qemu-user.o
user-obj-y += $(trace-obj-y)
+user-obj-y += $(qobject-obj-y)
+user-obj-y += $(addprefix qom/, $(qom-y))
######################################################################
# libhw
@@ -421,6 +425,8 @@ qapi-obj-y = $(addprefix qapi/, $(qapi-nested-y))
common-obj-y += qmp-marshal.o qapi-visit.o qapi-types.o $(qapi-obj-y)
common-obj-y += qmp.o hmp.o
+user-obj-y += $(qapi-obj-y)
+
######################################################################
# guest agent
diff --git a/Makefile.user b/Makefile.user
index 2b1e4d1..72d01c1 100644
--- a/Makefile.user
+++ b/Makefile.user
@@ -9,6 +9,7 @@ include $(SRC_PATH)/rules.mak
$(call set-vpath, $(SRC_PATH))
QEMU_CFLAGS+=-I..
+QEMU_CFLAGS+=-I$(SRC_PATH)/include
include $(SRC_PATH)/Makefile.objs
diff --git a/bsd-user/main.c b/bsd-user/main.c
index cc7d4a3..cdb0d0a 100644
--- a/bsd-user/main.c
+++ b/bsd-user/main.c
@@ -748,6 +748,8 @@ int main(int argc, char **argv)
if (argc <= 1)
usage();
+ module_call_init(MODULE_INIT_QOM);
+
if ((envlist = envlist_create()) == NULL) {
(void) fprintf(stderr, "Unable to allocate envlist\n");
exit(1);
diff --git a/configure b/configure
index 3b0b300..ee1140e 100755
--- a/configure
+++ b/configure
@@ -3849,6 +3849,8 @@ fi
d=libuser
mkdir -p $d
mkdir -p $d/trace
+mkdir -p $d/qapi
+mkdir -p $d/qom
symlink $source_path/Makefile.user $d/Makefile
if test "$docs" = "yes" ; then
diff --git a/darwin-user/main.c b/darwin-user/main.c
index 9b57c20..e1519c7 100644
--- a/darwin-user/main.c
+++ b/darwin-user/main.c
@@ -28,6 +28,7 @@
#include <sys/mman.h>
#include "qemu.h"
+#include "qemu-common.h"
#define DEBUG_LOGFILE "/tmp/qemu.log"
@@ -749,6 +750,8 @@ int main(int argc, char **argv)
if (argc <= 1)
usage();
+ module_call_init(MODULE_INIT_QOM);
+
optind = 1;
for(;;) {
if (optind >= argc)
diff --git a/linux-user/main.c b/linux-user/main.c
index 64d2208..f55109c 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -3278,6 +3278,8 @@ int main(int argc, char **argv, char **envp)
int i;
int ret;
+ module_call_init(MODULE_INIT_QOM);
+
qemu_cache_utils_init(envp);
if ((envlist = envlist_create()) == NULL) {
diff --git a/qemu-user.c b/qemu-user.c
new file mode 100644
index 0000000..51b2649
--- /dev/null
+++ b/qemu-user.c
@@ -0,0 +1,37 @@
+/*
+ * Stubs for QEMU user emulation
+ *
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see
+ * <http://www.gnu.org/licenses/old-licenses/gpl-2.0>
+ */
+
+#include "qemu-common.h"
+#include "monitor.h"
+
+Monitor *cur_mon;
+
+int monitor_cur_is_qmp(void)
+{
+ return 0;
+}
+
+void monitor_vprintf(Monitor *mon, const char *fmt, va_list ap)
+{
+}
+
+void monitor_set_error(Monitor *mon, QError *qerror)
+{
+}
--
1.7.7
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH RFC v3 03/21] qom: Introduce CPU class
2012-02-03 2:59 [Qemu-devel] [PATCH RFC v3 00/21] Introduce QOM CPU and use it for ARM Andreas Färber
2012-02-03 2:59 ` [Qemu-devel] [PATCH v3 01/21] qom: Register QOM infrastructure early Andreas Färber
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 02/21] qom: Add QOM support to user emulators Andreas Färber
@ 2012-02-03 2:59 ` Andreas Färber
2012-02-06 19:24 ` Anthony Liguori
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 04/21] target-arm: Introduce QOM CPU and use it for CPUID lookup Andreas Färber
` (17 subsequent siblings)
20 siblings, 1 reply; 47+ messages in thread
From: Andreas Färber @ 2012-02-03 2:59 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Andreas Färber
It's abstract and derived directly from TYPE_OBJECT.
Prepare a virtual reset method.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Anthony Liguori <anthony@codemonkey.ws>
Cc: Peter Maydell <peter.maydell@linaro.org>
---
include/qemu/cpu.h | 73 ++++++++++++++++++++++++++++++++++++++++++++++++++++
qom/Makefile | 1 +
qom/cpu.c | 50 +++++++++++++++++++++++++++++++++++
3 files changed, 124 insertions(+), 0 deletions(-)
create mode 100644 include/qemu/cpu.h
create mode 100644 qom/cpu.c
diff --git a/include/qemu/cpu.h b/include/qemu/cpu.h
new file mode 100644
index 0000000..22c7404
--- /dev/null
+++ b/include/qemu/cpu.h
@@ -0,0 +1,73 @@
+/*
+ * QEMU CPU model
+ *
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see
+ * <http://www.gnu.org/licenses/old-licenses/gpl-2.0>
+ */
+#ifndef QEMU_CPU_H
+#define QEMU_CPU_H
+
+#include "qemu/object.h"
+
+#define TYPE_CPU "cpu"
+
+#define CPU(obj) OBJECT_CHECK(CPU, (obj), TYPE_CPU)
+#define CPU_CLASS(class) OBJECT_CLASS_CHECK(CPUClass, (class), TYPE_CPU)
+#define CPU_GET_CLASS(obj) OBJECT_GET_CLASS(CPUClass, (obj), TYPE_CPU)
+
+typedef struct CPU CPU;
+
+/**
+ * CPUClass:
+ * @reset: Callback to reset the #CPU to its initial state.
+ *
+ * Represents a CPU family or model.
+ */
+typedef struct CPUClass {
+ ObjectClass parent_class;
+
+ void (*reset)(CPU *cpu);
+} CPUClass;
+
+/**
+ * CPU:
+ *
+ * State of one CPU core or thread.
+ */
+struct CPU {
+ Object parent_obj;
+
+ /* TODO Move common fields from CPUState here. */
+};
+
+
+/* TODO Rename to cpu_reset once all CPUState is converted to QOM. */
+/**
+ * cpu_do_reset:
+ * @cpu: The CPU whose state is to be reset.
+ */
+void cpu_do_reset(CPU *cpu);
+
+/**
+ * cpu_common_reset:
+ * @cpu: The CPU whose common state is to be reset.
+ *
+ * To be used by derived classes.
+ */
+void cpu_common_reset(CPU *cpu);
+
+
+#endif
diff --git a/qom/Makefile b/qom/Makefile
index f33f0be..0a1c8e0 100644
--- a/qom/Makefile
+++ b/qom/Makefile
@@ -1 +1,2 @@
qom-y = object.o container.o
+qom-y += cpu.o
diff --git a/qom/cpu.c b/qom/cpu.c
new file mode 100644
index 0000000..a60823f
--- /dev/null
+++ b/qom/cpu.c
@@ -0,0 +1,50 @@
+/*
+ * QEMU CPU model
+ *
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see
+ * <http://www.gnu.org/licenses/old-licenses/gpl-2.0>
+ */
+
+#include "qemu/cpu.h"
+#include "qemu-common.h"
+
+void cpu_do_reset(CPU *cpu)
+{
+ CPUClass *klass = CPU_GET_CLASS(cpu);
+
+ if (klass->reset != NULL) {
+ (*klass->reset)(cpu);
+ }
+}
+
+void cpu_common_reset(CPU *cpu)
+{
+}
+
+static TypeInfo cpu_type_info = {
+ .name = TYPE_CPU,
+ .parent = TYPE_OBJECT,
+ .instance_size = sizeof(CPU),
+ .abstract = true,
+ .class_size = sizeof(CPUClass),
+};
+
+static void cpu_register_types(void)
+{
+ type_register_static(&cpu_type_info);
+}
+
+type_init(cpu_register_types)
--
1.7.7
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH RFC v3 04/21] target-arm: Introduce QOM CPU and use it for CPUID lookup
2012-02-03 2:59 [Qemu-devel] [PATCH RFC v3 00/21] Introduce QOM CPU and use it for ARM Andreas Färber
` (2 preceding siblings ...)
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 03/21] qom: Introduce CPU class Andreas Färber
@ 2012-02-03 2:59 ` Andreas Färber
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 05/21] target-arm: Embed CPUARMState in QOM ARMCPU Andreas Färber
` (16 subsequent siblings)
20 siblings, 0 replies; 47+ messages in thread
From: Andreas Färber @ 2012-02-03 2:59 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Andreas Färber, Paul Brook
Create a CPU subclass, and register classes matching all CPU models
except for "pxa270", which is an alias for "pxa270-a0".
Make arm_cpu_list() enumerate CPU subclasses.
Replace cpu_arm_find_by_name()'s string -> CPUID lookup by storing the
CPUID in the class.
NB: CPUIDs were first introduced by Paul Brook in r1765 (2006).
Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Anthony Liguori <anthony@codemonkey.ws>
Cc: Paul Brook <paul@codesourcery.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
---
Makefile.target | 1 +
target-arm/cpu-core.h | 59 +++++++++++++++
target-arm/cpu.c | 190 +++++++++++++++++++++++++++++++++++++++++++++++++
target-arm/cpu.h | 1 -
target-arm/helper.c | 85 +++++++---------------
5 files changed, 277 insertions(+), 59 deletions(-)
create mode 100644 target-arm/cpu-core.h
create mode 100644 target-arm/cpu.c
diff --git a/Makefile.target b/Makefile.target
index 68481a3..5c139be 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -80,6 +80,7 @@ endif
libobj-$(TARGET_SPARC64) += vis_helper.o
libobj-$(CONFIG_NEED_MMU) += mmu.o
libobj-$(TARGET_ARM) += neon_helper.o iwmmxt_helper.o
+libobj-$(TARGET_ARM) += cpu.o
ifeq ($(TARGET_BASE_ARCH), sparc)
libobj-y += fop_helper.o cc_helper.o win_helper.o mmu_helper.o ldst_helper.o
libobj-y += cpu_init.o
diff --git a/target-arm/cpu-core.h b/target-arm/cpu-core.h
new file mode 100644
index 0000000..3e8f046
--- /dev/null
+++ b/target-arm/cpu-core.h
@@ -0,0 +1,59 @@
+/*
+ * QEMU ARM CPU
+ *
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see
+ * <http://www.gnu.org/licenses/old-licenses/gpl-2.0>
+ */
+#ifndef QEMU_ARM_CPU_CORE_H
+#define QEMU_ARM_CPU_CORE_H
+
+#include "qemu/cpu.h"
+
+#define TYPE_ARM_CPU "arm-cpu"
+
+#define ARM_CPU_CLASS(klass) \
+ OBJECT_CLASS_CHECK(ARMCPUClass, (klass), TYPE_ARM_CPU)
+#define ARM_CPU(obj) \
+ OBJECT_CHECK(ARMCPU, (obj), TYPE_ARM_CPU)
+#define ARM_CPU_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(ARMCPUClass, (obj), TYPE_ARM_CPU)
+
+/**
+ * ARMCPUClass:
+ *
+ * An ARM CPU model.
+ */
+typedef struct ARMCPUClass {
+ /*< private >*/
+ CPUClass parent_class;
+
+ struct {
+ uint32_t c0_cpuid;
+ } cp15;
+} ARMCPUClass;
+
+/**
+ * ARMCPU:
+ *
+ * An ARM CPU core.
+ */
+typedef struct ARMCPU {
+ /*< private >*/
+ CPU parent_obj;
+} ARMCPU;
+
+
+#endif
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
new file mode 100644
index 0000000..9255a19
--- /dev/null
+++ b/target-arm/cpu.c
@@ -0,0 +1,190 @@
+/*
+ * QEMU ARM CPU
+ *
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see
+ * <http://www.gnu.org/licenses/old-licenses/gpl-2.0>
+ */
+
+#include "cpu-core.h"
+#include "qemu-common.h"
+
+static void arm_cpu_reset(CPU *c)
+{
+ cpu_common_reset(c);
+}
+
+/* CPU models */
+
+typedef struct ARMCPUInfo {
+ const char *name;
+ uint32_t id;
+} ARMCPUInfo;
+
+static const ARMCPUInfo arm_cpus[] = {
+ {
+ .name = "arm926",
+ .id = 0x41069265,
+ },
+ {
+ .name = "arm946",
+ .id = 0x41059461,
+ },
+ {
+ .name = "arm1026",
+ .id = 0x4106a262,
+ },
+ /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
+ * older core than plain "arm1136". In particular this does not
+ * have the v6K features.
+ */
+ {
+ .name = "arm1136-r2",
+ .id = 0x4107b362,
+ },
+ {
+ .name = "arm1136",
+ .id = 0x4117b363,
+ },
+ {
+ .name = "arm1176",
+ .id = 0x410fb767,
+ },
+ {
+ .name = "arm11mpcore",
+ .id = 0x410fb022,
+ },
+ {
+ .name = "cortex-m3",
+ .id = 0x410fc231,
+ },
+ {
+ .name = "cortex-a8",
+ .id = 0x410fc080,
+ },
+ {
+ .name = "cortex-a9",
+ .id = 0x410fc090,
+ },
+ {
+ .name = "cortex-a15",
+ .id = 0x412fc0f1,
+ },
+ {
+ .name = "ti925t",
+ .id = 0x54029252,
+ },
+ {
+ .name = "sa1100",
+ .id = 0x4401A11B,
+ },
+ {
+ .name = "sa1110",
+ .id = 0x6901B119,
+ },
+ {
+ .name = "pxa250",
+ .id = 0x69052100,
+ },
+ {
+ .name = "pxa255",
+ .id = 0x69052d00,
+ },
+ {
+ .name = "pxa260",
+ .id = 0x69052903,
+ },
+ {
+ .name = "pxa261",
+ .id = 0x69052d05,
+ },
+ {
+ .name = "pxa262",
+ .id = 0x69052d06,
+ },
+ {
+ .name = "pxa270-a0",
+ .id = 0x69054110,
+ },
+ {
+ .name = "pxa270-a1",
+ .id = 0x69054111,
+ },
+ {
+ .name = "pxa270-b0",
+ .id = 0x69054112,
+ },
+ {
+ .name = "pxa270-b1",
+ .id = 0x69054113,
+ },
+ {
+ .name = "pxa270-c0",
+ .id = 0x69054114,
+ },
+ {
+ .name = "pxa270-c5",
+ .id = 0x69054117,
+ },
+ {
+ .name = "any",
+ .id = 0xffffffff,
+ },
+};
+
+static void arm_cpu_class_init(ObjectClass *klass, void *data)
+{
+ ARMCPUClass *k = ARM_CPU_CLASS(klass);
+ CPUClass *cpu_class = CPU_CLASS(klass);
+ const ARMCPUInfo *info = data;
+
+ cpu_class->reset = arm_cpu_reset;
+
+ k->cp15.c0_cpuid = info->id;
+}
+
+static void cpu_register(const ARMCPUInfo *info)
+{
+ TypeInfo type = {
+ .name = info->name,
+ .parent = TYPE_ARM_CPU,
+ .instance_size = sizeof(ARMCPU),
+ .class_size = sizeof(ARMCPUClass),
+ .class_init = arm_cpu_class_init,
+ .class_data = (void *)info,
+ };
+
+ type_register_static(&type);
+}
+
+static TypeInfo arm_cpu_type_info = {
+ .name = TYPE_ARM_CPU,
+ .parent = TYPE_CPU,
+ .instance_size = sizeof(ARMCPU),
+ .abstract = true,
+ .class_size = sizeof(ARMCPUClass),
+};
+
+static void arm_cpu_types_init(void)
+{
+ int i;
+
+ type_register_static(&arm_cpu_type_info);
+ for (i = 0; i < ARRAY_SIZE(arm_cpus); i++) {
+ cpu_register(&arm_cpus[i]);
+ }
+}
+
+type_init(arm_cpu_types_init)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 0d9b39c..5905ef2 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -420,7 +420,6 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
#define ARM_CPUID_PXA260 0x69052903
#define ARM_CPUID_PXA261 0x69052d05
#define ARM_CPUID_PXA262 0x69052d06
-#define ARM_CPUID_PXA270 0x69054110
#define ARM_CPUID_PXA270_A0 0x69054110
#define ARM_CPUID_PXA270_A1 0x69054111
#define ARM_CPUID_PXA270_B0 0x69054112
diff --git a/target-arm/helper.c b/target-arm/helper.c
index ea4f35f..d8425db 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -11,6 +11,7 @@
#include "hw/loader.h"
#endif
#include "sysemu.h"
+#include "cpu-core.h"
static uint32_t cortexa15_cp15_c0_c1[8] = {
0x00001131, 0x00011011, 0x02010555, 0x00000000,
@@ -51,8 +52,6 @@ static uint32_t arm1176_cp15_c0_c1[8] =
static uint32_t arm1176_cp15_c0_c2[8] =
{ 0x0140011, 0x12002111, 0x11231121, 0x01102131, 0x01141, 0, 0, 0 };
-static uint32_t cpu_arm_find_by_name(const char *name);
-
static inline void set_feature(CPUARMState *env, int feature)
{
env->features |= 1u << feature;
@@ -400,13 +399,21 @@ static int vfp_gdb_set_reg(CPUState *env, uint8_t *buf, int reg)
CPUARMState *cpu_arm_init(const char *cpu_model)
{
+ ObjectClass *klass;
+ ARMCPUClass *cpu_class;
CPUARMState *env;
- uint32_t id;
static int inited = 0;
- id = cpu_arm_find_by_name(cpu_model);
- if (id == 0)
+ /* One legacy alias to check */
+ if (strcmp(cpu_model, "pxa270") == 0) {
+ cpu_model = "pxa270-a0";
+ }
+
+ klass = object_class_by_name(cpu_model);
+ if (klass == NULL) {
return NULL;
+ }
+ cpu_class = ARM_CPU_CLASS(klass);
env = g_malloc0(sizeof(CPUARMState));
cpu_exec_init(env);
if (tcg_enabled() && !inited) {
@@ -415,7 +422,7 @@ CPUARMState *cpu_arm_init(const char *cpu_model)
}
env->cpu_model_str = cpu_model;
- env->cp15.c0_cpuid = id;
+ env->cp15.c0_cpuid = cpu_class->cp15.c0_cpuid;
cpu_reset(env);
if (arm_feature(env, ARM_FEATURE_NEON)) {
gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
@@ -431,66 +438,28 @@ CPUARMState *cpu_arm_init(const char *cpu_model)
return env;
}
-struct arm_cpu_t {
- uint32_t id;
- const char *name;
+struct ARMCPUListState {
+ fprintf_function cpu_fprintf;
+ FILE *file;
};
-static const struct arm_cpu_t arm_cpu_names[] = {
- { ARM_CPUID_ARM926, "arm926"},
- { ARM_CPUID_ARM946, "arm946"},
- { ARM_CPUID_ARM1026, "arm1026"},
- { ARM_CPUID_ARM1136, "arm1136"},
- { ARM_CPUID_ARM1136_R2, "arm1136-r2"},
- { ARM_CPUID_ARM1176, "arm1176"},
- { ARM_CPUID_ARM11MPCORE, "arm11mpcore"},
- { ARM_CPUID_CORTEXM3, "cortex-m3"},
- { ARM_CPUID_CORTEXA8, "cortex-a8"},
- { ARM_CPUID_CORTEXA9, "cortex-a9"},
- { ARM_CPUID_CORTEXA15, "cortex-a15" },
- { ARM_CPUID_TI925T, "ti925t" },
- { ARM_CPUID_PXA250, "pxa250" },
- { ARM_CPUID_SA1100, "sa1100" },
- { ARM_CPUID_SA1110, "sa1110" },
- { ARM_CPUID_PXA255, "pxa255" },
- { ARM_CPUID_PXA260, "pxa260" },
- { ARM_CPUID_PXA261, "pxa261" },
- { ARM_CPUID_PXA262, "pxa262" },
- { ARM_CPUID_PXA270, "pxa270" },
- { ARM_CPUID_PXA270_A0, "pxa270-a0" },
- { ARM_CPUID_PXA270_A1, "pxa270-a1" },
- { ARM_CPUID_PXA270_B0, "pxa270-b0" },
- { ARM_CPUID_PXA270_B1, "pxa270-b1" },
- { ARM_CPUID_PXA270_C0, "pxa270-c0" },
- { ARM_CPUID_PXA270_C5, "pxa270-c5" },
- { ARM_CPUID_ANY, "any"},
- { 0, NULL}
-};
-
-void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
+static void arm_cpu_list_entry(ObjectClass *klass, void *opaque)
{
- int i;
+ struct ARMCPUListState *s = opaque;
- (*cpu_fprintf)(f, "Available CPUs:\n");
- for (i = 0; arm_cpu_names[i].name; i++) {
- (*cpu_fprintf)(f, " %s\n", arm_cpu_names[i].name);
- }
+ (*s->cpu_fprintf)(s->file, " %s\n",
+ object_class_get_name(klass));
}
-/* return 0 if not found */
-static uint32_t cpu_arm_find_by_name(const char *name)
+void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
{
- int i;
- uint32_t id;
+ struct ARMCPUListState s = {
+ .cpu_fprintf = cpu_fprintf,
+ .file = f,
+ };
- id = 0;
- for (i = 0; arm_cpu_names[i].name; i++) {
- if (strcmp(name, arm_cpu_names[i].name) == 0) {
- id = arm_cpu_names[i].id;
- break;
- }
- }
- return id;
+ (*cpu_fprintf)(f, "Available CPUs:\n");
+ object_class_foreach(arm_cpu_list_entry, TYPE_CPU, false, &s);
}
void cpu_arm_close(CPUARMState *env)
--
1.7.7
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH RFC v3 05/21] target-arm: Embed CPUARMState in QOM ARMCPU
2012-02-03 2:59 [Qemu-devel] [PATCH RFC v3 00/21] Introduce QOM CPU and use it for ARM Andreas Färber
` (3 preceding siblings ...)
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 04/21] target-arm: Introduce QOM CPU and use it for CPUID lookup Andreas Färber
@ 2012-02-03 2:59 ` Andreas Färber
2012-02-06 23:00 ` Anthony Liguori
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 06/21] target-arm: Prepare model-specific class_init function Andreas Färber
` (15 subsequent siblings)
20 siblings, 1 reply; 47+ messages in thread
From: Andreas Färber @ 2012-02-03 2:59 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Richard Henderson, Andreas Färber, Paul Brook
We g_malloc0()'ed CPUARMState ourself, and exec.c's cpu_copy() runs
through cpu_init() as well, so we are at liberty to supply the CPUState
any way we see fit. Having CPUARMState as field in the QOM CPU allows
both to access env from an ARMCPU object and to access the QOM Object
and its ObjectClass from an env pointer, in ARM code for now.
The goal is to convert all CPUs to QOM and to use CPU objects in central
places, especially once we have property support for Object.
This will then allow to have TCG AREG0 point to target-specific fields
where small immediate offsets are desired (as pointed out by rth) while
allowing for common fields at known offsets from the base class.
Having the CPUID in ARMCPUClass, we can set it from the instance_init
function. Same for cpu_model_str, which is now the QOM class name.
Make cpu_reset() call cpu_do_reset() and move most of its code to
arm_cpu_reset().
Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Anthony Liguori <anthony@codemonkey.ws>
Cc: Paul Brook <paul@codesourcery.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Richard Henderson <rth@twiddle.net>
---
target-arm/cpu-core.h | 11 +++++++
target-arm/cpu.c | 78 +++++++++++++++++++++++++++++++++++++++++++++++++
target-arm/helper.c | 71 ++++----------------------------------------
3 files changed, 96 insertions(+), 64 deletions(-)
diff --git a/target-arm/cpu-core.h b/target-arm/cpu-core.h
index 3e8f046..4ba5ee0 100644
--- a/target-arm/cpu-core.h
+++ b/target-arm/cpu-core.h
@@ -21,6 +21,7 @@
#define QEMU_ARM_CPU_CORE_H
#include "qemu/cpu.h"
+#include "cpu.h"
#define TYPE_ARM_CPU "arm-cpu"
@@ -53,7 +54,17 @@ typedef struct ARMCPUClass {
typedef struct ARMCPU {
/*< private >*/
CPU parent_obj;
+
+ /* TODO Inline this and split off common state */
+ CPUARMState env;
} ARMCPU;
+static inline Object *arm_env_get_object(CPUARMState *env)
+{
+ return OBJECT((void *)(env) - offsetof(ARMCPU, env));
+}
+
+#define ENV_GET_OBJECT(e) arm_env_get_object(e)
+
#endif
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 9255a19..43231c9 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -20,10 +20,75 @@
#include "cpu-core.h"
#include "qemu-common.h"
+#if !defined(CONFIG_USER_ONLY)
+#include "hw/loader.h"
+#endif
static void arm_cpu_reset(CPU *c)
{
+ ARMCPU *cpu = ARM_CPU(c);
+ CPUARMState *env = &cpu->env;
+ uint32_t id;
+ uint32_t tmp;
+
+ if (qemu_loglevel_mask(CPU_LOG_RESET)) {
+ qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
+ log_cpu_state(env, 0);
+ }
+
cpu_common_reset(c);
+
+ id = env->cp15.c0_cpuid;
+ tmp = env->cp15.c15_config_base_address;
+ memset(env, 0, offsetof(CPUARMState, breakpoints));
+ env->cp15.c0_cpuid = id;
+ env->cp15.c15_config_base_address = tmp;
+
+#if defined(CONFIG_USER_ONLY)
+ env->uncached_cpsr = ARM_CPU_MODE_USR;
+ /* For user mode we must enable access to coprocessors */
+ env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
+ if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
+ env->cp15.c15_cpar = 3;
+ } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
+ env->cp15.c15_cpar = 1;
+ }
+#else
+ /* SVC mode with interrupts disabled. */
+ env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
+ /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
+ clear at reset. Initial SP and PC are loaded from ROM. */
+ if (IS_M(env)) {
+ uint32_t pc;
+ uint8_t *rom;
+ env->uncached_cpsr &= ~CPSR_I;
+ rom = rom_ptr(0);
+ if (rom) {
+ /* We should really use ldl_phys here, in case the guest
+ modified flash and reset itself. However images
+ loaded via -kernel have not been copied yet, so load the
+ values directly from there. */
+ env->regs[13] = ldl_p(rom);
+ pc = ldl_p(rom + 4);
+ env->thumb = pc & 1;
+ env->regs[15] = pc & ~1;
+ }
+ }
+ env->vfp.xregs[ARM_VFP_FPEXC] = 0;
+ env->cp15.c2_base_mask = 0xffffc000u;
+ /* v7 performance monitor control register: same implementor
+ * field as main ID register, and we implement no event counters.
+ */
+ env->cp15.c9_pmcr = (id & 0xff000000);
+#endif
+ set_flush_to_zero(1, &env->vfp.standard_fp_status);
+ set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
+ set_default_nan_mode(1, &env->vfp.standard_fp_status);
+ set_float_detect_tininess(float_tininess_before_rounding,
+ &env->vfp.fp_status);
+ set_float_detect_tininess(float_tininess_before_rounding,
+ &env->vfp.standard_fp_status);
+ tlb_flush(env, 1);
}
/* CPU models */
@@ -144,6 +209,18 @@ static const ARMCPUInfo arm_cpus[] = {
},
};
+static void arm_cpu_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ ARMCPUClass *cpu_class = ARM_CPU_GET_CLASS(obj);
+
+ memset(&cpu->env, 0, sizeof(CPUARMState));
+ cpu_exec_init(&cpu->env);
+
+ cpu->env.cpu_model_str = object_get_typename(obj);
+ cpu->env.cp15.c0_cpuid = cpu_class->cp15.c0_cpuid;
+}
+
static void arm_cpu_class_init(ObjectClass *klass, void *data)
{
ARMCPUClass *k = ARM_CPU_CLASS(klass);
@@ -161,6 +238,7 @@ static void cpu_register(const ARMCPUInfo *info)
.name = info->name,
.parent = TYPE_ARM_CPU,
.instance_size = sizeof(ARMCPU),
+ .instance_init = arm_cpu_initfn,
.class_size = sizeof(ARMCPUClass),
.class_init = arm_cpu_class_init,
.class_data = (void *)info,
diff --git a/target-arm/helper.c b/target-arm/helper.c
index d8425db..c5ba7fd 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -7,9 +7,6 @@
#include "helper.h"
#include "qemu-common.h"
#include "host-utils.h"
-#if !defined(CONFIG_USER_ONLY)
-#include "hw/loader.h"
-#endif
#include "sysemu.h"
#include "cpu-core.h"
@@ -59,7 +56,6 @@ static inline void set_feature(CPUARMState *env, int feature)
static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
{
- env->cp15.c0_cpuid = id;
switch (id) {
case ARM_CPUID_ARM926:
set_feature(env, ARM_FEATURE_V5);
@@ -285,64 +281,12 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
void cpu_reset(CPUARMState *env)
{
uint32_t id;
- uint32_t tmp = 0;
- if (qemu_loglevel_mask(CPU_LOG_RESET)) {
- qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
- log_cpu_state(env, 0);
- }
+ cpu_do_reset(CPU(ENV_GET_OBJECT(env)));
id = env->cp15.c0_cpuid;
- tmp = env->cp15.c15_config_base_address;
- memset(env, 0, offsetof(CPUARMState, breakpoints));
if (id)
cpu_reset_model_id(env, id);
- env->cp15.c15_config_base_address = tmp;
-#if defined (CONFIG_USER_ONLY)
- env->uncached_cpsr = ARM_CPU_MODE_USR;
- /* For user mode we must enable access to coprocessors */
- env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
- if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
- env->cp15.c15_cpar = 3;
- } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
- env->cp15.c15_cpar = 1;
- }
-#else
- /* SVC mode with interrupts disabled. */
- env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
- /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
- clear at reset. Initial SP and PC are loaded from ROM. */
- if (IS_M(env)) {
- uint32_t pc;
- uint8_t *rom;
- env->uncached_cpsr &= ~CPSR_I;
- rom = rom_ptr(0);
- if (rom) {
- /* We should really use ldl_phys here, in case the guest
- modified flash and reset itself. However images
- loaded via -kernel have not been copied yet, so load the
- values directly from there. */
- env->regs[13] = ldl_p(rom);
- pc = ldl_p(rom + 4);
- env->thumb = pc & 1;
- env->regs[15] = pc & ~1;
- }
- }
- env->vfp.xregs[ARM_VFP_FPEXC] = 0;
- env->cp15.c2_base_mask = 0xffffc000u;
- /* v7 performance monitor control register: same implementor
- * field as main ID register, and we implement no event counters.
- */
- env->cp15.c9_pmcr = (id & 0xff000000);
-#endif
- set_flush_to_zero(1, &env->vfp.standard_fp_status);
- set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
- set_default_nan_mode(1, &env->vfp.standard_fp_status);
- set_float_detect_tininess(float_tininess_before_rounding,
- &env->vfp.fp_status);
- set_float_detect_tininess(float_tininess_before_rounding,
- &env->vfp.standard_fp_status);
- tlb_flush(env, 1);
}
static int vfp_gdb_get_reg(CPUState *env, uint8_t *buf, int reg)
@@ -400,7 +344,7 @@ static int vfp_gdb_set_reg(CPUState *env, uint8_t *buf, int reg)
CPUARMState *cpu_arm_init(const char *cpu_model)
{
ObjectClass *klass;
- ARMCPUClass *cpu_class;
+ ARMCPU *cpu;
CPUARMState *env;
static int inited = 0;
@@ -413,16 +357,14 @@ CPUARMState *cpu_arm_init(const char *cpu_model)
if (klass == NULL) {
return NULL;
}
- cpu_class = ARM_CPU_CLASS(klass);
- env = g_malloc0(sizeof(CPUARMState));
- cpu_exec_init(env);
+ cpu = ARM_CPU(object_new(cpu_model));
+ env = &cpu->env;
+
if (tcg_enabled() && !inited) {
inited = 1;
arm_translate_init();
}
- env->cpu_model_str = cpu_model;
- env->cp15.c0_cpuid = cpu_class->cp15.c0_cpuid;
cpu_reset(env);
if (arm_feature(env, ARM_FEATURE_NEON)) {
gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
@@ -464,7 +406,8 @@ void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
void cpu_arm_close(CPUARMState *env)
{
- g_free(env);
+ Object *obj = ENV_GET_OBJECT(env);
+ object_delete(obj);
}
static int bad_mode_switch(CPUState *env, int mode)
--
1.7.7
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH RFC v3 06/21] target-arm: Prepare model-specific class_init function
2012-02-03 2:59 [Qemu-devel] [PATCH RFC v3 00/21] Introduce QOM CPU and use it for ARM Andreas Färber
` (4 preceding siblings ...)
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 05/21] target-arm: Embed CPUARMState in QOM ARMCPU Andreas Färber
@ 2012-02-03 2:59 ` Andreas Färber
2012-02-06 23:03 ` Anthony Liguori
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 07/21] target-arm: Overwrite reset handler for ti925t Andreas Färber
` (14 subsequent siblings)
20 siblings, 1 reply; 47+ messages in thread
From: Andreas Färber @ 2012-02-03 2:59 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
This allows to share initialization between CPU models.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
target-arm/cpu.c | 5 +++++
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 43231c9..b794ec1 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -96,6 +96,7 @@ static void arm_cpu_reset(CPU *c)
typedef struct ARMCPUInfo {
const char *name;
uint32_t id;
+ void (*class_init)(ARMCPUClass *klass, const struct ARMCPUInfo *info);
} ARMCPUInfo;
static const ARMCPUInfo arm_cpus[] = {
@@ -230,6 +231,10 @@ static void arm_cpu_class_init(ObjectClass *klass, void *data)
cpu_class->reset = arm_cpu_reset;
k->cp15.c0_cpuid = info->id;
+
+ if (info->class_init != NULL) {
+ (*info->class_init)(k, info);
+ }
}
static void cpu_register(const ARMCPUInfo *info)
--
1.7.7
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH RFC v3 07/21] target-arm: Overwrite reset handler for ti925t
2012-02-03 2:59 [Qemu-devel] [PATCH RFC v3 00/21] Introduce QOM CPU and use it for ARM Andreas Färber
` (5 preceding siblings ...)
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 06/21] target-arm: Prepare model-specific class_init function Andreas Färber
@ 2012-02-03 2:59 ` Andreas Färber
2012-02-07 17:30 ` Peter Maydell
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 08/21] target-arm: Move CPU feature flags out of CPUState Andreas Färber
` (13 subsequent siblings)
20 siblings, 1 reply; 47+ messages in thread
From: Andreas Färber @ 2012-02-03 2:59 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Andreas Färber
The OMAPCP feature allows to switch between TI915T and TI925T via
cp15 c15_ticonfig register. Move reset into ti925t-specific callback.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/cpu.c | 18 ++++++++++++++++++
target-arm/helper.c | 1 -
2 files changed, 18 insertions(+), 1 deletions(-)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index b794ec1..a6dbad3 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -99,6 +99,23 @@ typedef struct ARMCPUInfo {
void (*class_init)(ARMCPUClass *klass, const struct ARMCPUInfo *info);
} ARMCPUInfo;
+static void ti925t_reset(CPU *c)
+{
+ ARMCPU *cpu = ARM_CPU(c);
+ CPUARMState *env = &cpu->env;
+
+ arm_cpu_reset(c);
+
+ env->cp15.c0_cpuid = ARM_CPUID_TI925T; /* Depends on wiring. */
+}
+
+static void ti925t_class_init(ARMCPUClass *klass, const ARMCPUInfo *info)
+{
+ CPUClass *cpu_class = CPU_CLASS(klass);
+
+ cpu_class->reset = ti925t_reset;
+}
+
static const ARMCPUInfo arm_cpus[] = {
{
.name = "arm926",
@@ -151,6 +168,7 @@ static const ARMCPUInfo arm_cpus[] = {
{
.name = "ti925t",
.id = 0x54029252,
+ .class_init = ti925t_class_init,
},
{
.name = "sa1100",
diff --git a/target-arm/helper.c b/target-arm/helper.c
index c5ba7fd..e877c3f 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -201,7 +201,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
case ARM_CPUID_TI925T:
set_feature(env, ARM_FEATURE_V4T);
set_feature(env, ARM_FEATURE_OMAPCP);
- env->cp15.c0_cpuid = ARM_CPUID_TI925T; /* Depends on wiring. */
env->cp15.c0_cachetype = 0x5109149;
env->cp15.c1_sys = 0x00000070;
env->cp15.c15_i_max = 0x000;
--
1.7.7
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH RFC v3 08/21] target-arm: Move CPU feature flags out of CPUState
2012-02-03 2:59 [Qemu-devel] [PATCH RFC v3 00/21] Introduce QOM CPU and use it for ARM Andreas Färber
` (6 preceding siblings ...)
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 07/21] target-arm: Overwrite reset handler for ti925t Andreas Färber
@ 2012-02-03 2:59 ` Andreas Färber
2012-02-07 17:28 ` Peter Maydell
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 09/21] target-arm: No longer abort on unhandled CPUIDs on reset Andreas Färber
` (12 subsequent siblings)
20 siblings, 1 reply; 47+ messages in thread
From: Andreas Färber @ 2012-02-03 2:59 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Andreas Färber
The internal CPU feature flags were only ever set in
cpu_reset_model_id(). Therefore move their initialization into
ARMCPUClass. We might want to tweak them in the future though (e.g.,
-cpu cortex-r4,+fpu), so keep a copy in ARMCPU. This in turn means we
need to infer features for both ARMCPUClass and ARMCPU, so move feature
inference to arm_infer_features() and use macros to simplify it.
Since cpu.h defines ARMCPUState, which has been incorporated into
ARMCPU, and tries to use arm_feature() in cpu_get_tb_cpu_state(),
move arm_feature() to cpu-core.h and add a forward declaration.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/cpu-core.h | 12 ++++
target-arm/cpu.c | 159 +++++++++++++++++++++++++++++++++++++++++++++++++
target-arm/cpu.h | 9 +--
target-arm/helper.c | 95 -----------------------------
target-arm/machine.c | 6 +-
5 files changed, 177 insertions(+), 104 deletions(-)
diff --git a/target-arm/cpu-core.h b/target-arm/cpu-core.h
index 4ba5ee0..9f090a8 100644
--- a/target-arm/cpu-core.h
+++ b/target-arm/cpu-core.h
@@ -44,6 +44,9 @@ typedef struct ARMCPUClass {
struct {
uint32_t c0_cpuid;
} cp15;
+
+ /* Internal CPU feature flags. */
+ uint32_t features;
} ARMCPUClass;
/**
@@ -55,6 +58,9 @@ typedef struct ARMCPU {
/*< private >*/
CPU parent_obj;
+ /* Internal CPU feature flags. */
+ uint32_t features;
+
/* TODO Inline this and split off common state */
CPUARMState env;
} ARMCPU;
@@ -66,5 +72,11 @@ static inline Object *arm_env_get_object(CPUARMState *env)
#define ENV_GET_OBJECT(e) arm_env_get_object(e)
+static inline int arm_feature(CPUARMState *env, int feature)
+{
+ ARMCPU *cpu = ARM_CPU(ENV_GET_OBJECT(env));
+ return (cpu->features & (1u << feature)) != 0;
+}
+
#endif
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index a6dbad3..07cbfe6 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -91,14 +91,88 @@ static void arm_cpu_reset(CPU *c)
tlb_flush(env, 1);
}
+/* CPU feature flags */
+
+#define ARM_FEATURE(x) (1u << ARM_FEATURE_ ## x)
+
+#define has_feature(x) ((*features & ARM_FEATURE(x)) != 0)
+#define set_feature(x) (*features |= ARM_FEATURE(x))
+
+/**
+ * arm_infer_features:
+ * @features: Pointer to the feature flags of #ARMCPUClass or #ARMCPU.
+ *
+ * Some features automatically imply others.
+ */
+static void arm_infer_features(uint32_t *features)
+{
+ if (has_feature(V7)) {
+ set_feature(VAPA);
+ set_feature(THUMB2);
+ if (!has_feature(M)) {
+ set_feature(V6K);
+ } else {
+ set_feature(V6);
+ }
+ }
+ if (has_feature(V6K)) {
+ set_feature(V6);
+ }
+ if (has_feature(V6)) {
+ set_feature(V5);
+ if (!has_feature(M)) {
+ set_feature(AUXCR);
+ }
+ }
+ if (has_feature(V5)) {
+ set_feature(V4T);
+ }
+ if (has_feature(M)) {
+ set_feature(THUMB_DIV);
+ }
+ if (has_feature(ARM_DIV)) {
+ set_feature(THUMB_DIV);
+ }
+ if (has_feature(VFP4)) {
+ set_feature(VFP3);
+ }
+ if (has_feature(VFP3)) {
+ set_feature(VFP);
+ }
+}
+
+#undef has_feature
+#undef set_feature
+
+static inline void set_class_feature(ARMCPUClass *klass, int feature)
+{
+ klass->features |= 1u << feature;
+}
+
+static inline void unset_class_feature(ARMCPUClass *klass, int feature)
+{
+ klass->features &= ~(1u << feature);
+}
+
/* CPU models */
typedef struct ARMCPUInfo {
const char *name;
uint32_t id;
+ uint32_t features;
void (*class_init)(ARMCPUClass *klass, const struct ARMCPUInfo *info);
} ARMCPUInfo;
+static void arm1136_r0_class_init(ARMCPUClass *k, const ARMCPUInfo *info)
+{
+ ARMCPUClass *r1_class;
+
+ r1_class = ARM_CPU_CLASS(object_class_by_name("arm1136"));
+
+ k->features = r1_class->features;
+ unset_class_feature(k, ARM_FEATURE_V6K);
+}
+
static void ti925t_reset(CPU *c)
{
ARMCPU *cpu = ARM_CPU(c);
@@ -116,18 +190,43 @@ static void ti925t_class_init(ARMCPUClass *klass, const ARMCPUInfo *info)
cpu_class->reset = ti925t_reset;
}
+static void sa11xx_class_init(ARMCPUClass *k, const ARMCPUInfo *info)
+{
+ set_class_feature(k, ARM_FEATURE_STRONGARM);
+}
+
+static void pxa25x_class_init(ARMCPUClass *k, const ARMCPUInfo *info)
+{
+ set_class_feature(k, ARM_FEATURE_V5);
+ set_class_feature(k, ARM_FEATURE_XSCALE);
+}
+
+static void pxa270_class_init(ARMCPUClass *k, const ARMCPUInfo *info)
+{
+ set_class_feature(k, ARM_FEATURE_V5);
+ set_class_feature(k, ARM_FEATURE_XSCALE);
+ set_class_feature(k, ARM_FEATURE_IWMMXT);
+}
+
static const ARMCPUInfo arm_cpus[] = {
{
.name = "arm926",
.id = 0x41069265,
+ .features = ARM_FEATURE(V5) |
+ ARM_FEATURE(VFP),
},
{
.name = "arm946",
.id = 0x41059461,
+ .features = ARM_FEATURE(V5) |
+ ARM_FEATURE(MPU),
},
{
.name = "arm1026",
.id = 0x4106a262,
+ .features = ARM_FEATURE(V5) |
+ ARM_FEATURE(VFP) |
+ ARM_FEATURE(AUXCR),
},
/* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
* older core than plain "arm1136". In particular this does not
@@ -136,95 +235,150 @@ static const ARMCPUInfo arm_cpus[] = {
{
.name = "arm1136-r2",
.id = 0x4107b362,
+ .class_init = arm1136_r0_class_init,
},
{
.name = "arm1136",
.id = 0x4117b363,
+ .features = ARM_FEATURE(V6) |
+ ARM_FEATURE(VFP),
},
{
.name = "arm1176",
.id = 0x410fb767,
+ .features = ARM_FEATURE(V6K) |
+ ARM_FEATURE(VFP) |
+ ARM_FEATURE(VAPA),
},
{
.name = "arm11mpcore",
.id = 0x410fb022,
+ .features = ARM_FEATURE(V6K) |
+ ARM_FEATURE(VFP) |
+ ARM_FEATURE(VAPA),
},
{
.name = "cortex-m3",
.id = 0x410fc231,
+ .features = ARM_FEATURE(V7) |
+ ARM_FEATURE(M),
},
{
.name = "cortex-a8",
.id = 0x410fc080,
+ .features = ARM_FEATURE(V7) |
+ ARM_FEATURE(VFP3) |
+ ARM_FEATURE(NEON) |
+ ARM_FEATURE(THUMB2EE),
},
{
.name = "cortex-a9",
.id = 0x410fc090,
+ .features = ARM_FEATURE(V7) |
+ ARM_FEATURE(VFP3) |
+ ARM_FEATURE(VFP_FP16) |
+ ARM_FEATURE(NEON) |
+ ARM_FEATURE(THUMB2EE) |
+ /* Note that A9 supports the MP extensions even for
+ * A9UP and single-core A9MP (which are both different
+ * and valid configurations; we don't model A9UP).
+ */
+ ARM_FEATURE(V7MP),
},
{
.name = "cortex-a15",
.id = 0x412fc0f1,
+ .features = ARM_FEATURE(V7) |
+ ARM_FEATURE(VFP4) |
+ ARM_FEATURE(VFP_FP16) |
+ ARM_FEATURE(NEON) |
+ ARM_FEATURE(THUMB2EE) |
+ ARM_FEATURE(ARM_DIV) |
+ ARM_FEATURE(V7MP) |
+ ARM_FEATURE(GENERIC_TIMER),
},
{
.name = "ti925t",
.id = 0x54029252,
+ .features = ARM_FEATURE(V4T) |
+ ARM_FEATURE(OMAPCP),
.class_init = ti925t_class_init,
},
{
.name = "sa1100",
.id = 0x4401A11B,
+ .class_init = sa11xx_class_init,
},
{
.name = "sa1110",
.id = 0x6901B119,
+ .class_init = sa11xx_class_init,
},
{
.name = "pxa250",
.id = 0x69052100,
+ .class_init = pxa25x_class_init,
},
{
.name = "pxa255",
.id = 0x69052d00,
+ .class_init = pxa25x_class_init,
},
{
.name = "pxa260",
.id = 0x69052903,
+ .class_init = pxa25x_class_init,
},
{
.name = "pxa261",
.id = 0x69052d05,
+ .class_init = pxa25x_class_init,
},
{
.name = "pxa262",
.id = 0x69052d06,
+ .class_init = pxa25x_class_init,
},
{
.name = "pxa270-a0",
.id = 0x69054110,
+ .class_init = pxa270_class_init,
},
{
.name = "pxa270-a1",
.id = 0x69054111,
+ .class_init = pxa270_class_init,
},
{
.name = "pxa270-b0",
.id = 0x69054112,
+ .class_init = pxa270_class_init,
},
{
.name = "pxa270-b1",
.id = 0x69054113,
+ .class_init = pxa270_class_init,
},
{
.name = "pxa270-c0",
.id = 0x69054114,
+ .class_init = pxa270_class_init,
},
{
.name = "pxa270-c5",
.id = 0x69054117,
+ .class_init = pxa270_class_init,
},
{
.name = "any",
.id = 0xffffffff,
+ .features = ARM_FEATURE(V7) |
+ ARM_FEATURE(VFP4) |
+ ARM_FEATURE(VFP_FP16) |
+ ARM_FEATURE(NEON) |
+ ARM_FEATURE(THUMB2EE) |
+ ARM_FEATURE(ARM_DIV) |
+ ARM_FEATURE(V7MP),
},
};
@@ -233,6 +387,8 @@ static void arm_cpu_initfn(Object *obj)
ARMCPU *cpu = ARM_CPU(obj);
ARMCPUClass *cpu_class = ARM_CPU_GET_CLASS(obj);
+ cpu->features = cpu_class->features;
+
memset(&cpu->env, 0, sizeof(CPUARMState));
cpu_exec_init(&cpu->env);
@@ -249,10 +405,13 @@ static void arm_cpu_class_init(ObjectClass *klass, void *data)
cpu_class->reset = arm_cpu_reset;
k->cp15.c0_cpuid = info->id;
+ k->features = info->features;
if (info->class_init != NULL) {
(*info->class_init)(k, info);
}
+
+ arm_infer_features(&k->features);
}
static void cpu_register(const ARMCPUInfo *info)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 5905ef2..bf8c911 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -170,9 +170,6 @@ typedef struct CPUARMState {
uint32_t teecr;
uint32_t teehbr;
- /* Internal CPU feature flags. */
- uint32_t features;
-
/* VFP coprocessor state. */
struct {
float64 regs[32];
@@ -385,10 +382,7 @@ enum arm_features {
ARM_FEATURE_GENERIC_TIMER,
};
-static inline int arm_feature(CPUARMState *env, int feature)
-{
- return (env->features & (1u << feature)) != 0;
-}
+static inline int arm_feature(CPUARMState *env, int feature);
void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf);
@@ -475,6 +469,7 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
#endif
#include "cpu-all.h"
+#include "cpu-core.h"
/* Bit usage in the TB flags field: */
#define ARM_TBFLAG_THUMB_SHIFT 0
diff --git a/target-arm/helper.c b/target-arm/helper.c
index e877c3f..4fd8ba8 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -49,46 +49,31 @@ static uint32_t arm1176_cp15_c0_c1[8] =
static uint32_t arm1176_cp15_c0_c2[8] =
{ 0x0140011, 0x12002111, 0x11231121, 0x01102131, 0x01141, 0, 0, 0 };
-static inline void set_feature(CPUARMState *env, int feature)
-{
- env->features |= 1u << feature;
-}
-
static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
{
switch (id) {
case ARM_CPUID_ARM926:
- set_feature(env, ARM_FEATURE_V5);
- set_feature(env, ARM_FEATURE_VFP);
env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090;
env->cp15.c0_cachetype = 0x1dd20d2;
env->cp15.c1_sys = 0x00090078;
break;
case ARM_CPUID_ARM946:
- set_feature(env, ARM_FEATURE_V5);
- set_feature(env, ARM_FEATURE_MPU);
env->cp15.c0_cachetype = 0x0f004006;
env->cp15.c1_sys = 0x00000078;
break;
case ARM_CPUID_ARM1026:
- set_feature(env, ARM_FEATURE_V5);
- set_feature(env, ARM_FEATURE_VFP);
- set_feature(env, ARM_FEATURE_AUXCR);
env->vfp.xregs[ARM_VFP_FPSID] = 0x410110a0;
env->cp15.c0_cachetype = 0x1dd20d2;
env->cp15.c1_sys = 0x00090078;
break;
case ARM_CPUID_ARM1136:
/* This is the 1136 r1, which is a v6K core */
- set_feature(env, ARM_FEATURE_V6K);
/* Fall through */
case ARM_CPUID_ARM1136_R2:
/* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
* older core than plain "arm1136". In particular this does not
* have the v6K features.
*/
- set_feature(env, ARM_FEATURE_V6);
- set_feature(env, ARM_FEATURE_VFP);
/* These ID register values are correct for 1136 but may be wrong
* for 1136_r2 (in particular r0p2 does not actually implement most
* of the ID registers).
@@ -102,9 +87,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c1_sys = 0x00050078;
break;
case ARM_CPUID_ARM1176:
- set_feature(env, ARM_FEATURE_V6K);
- set_feature(env, ARM_FEATURE_VFP);
- set_feature(env, ARM_FEATURE_VAPA);
env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b5;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
@@ -114,9 +96,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c1_sys = 0x00050078;
break;
case ARM_CPUID_ARM11MPCORE:
- set_feature(env, ARM_FEATURE_V6K);
- set_feature(env, ARM_FEATURE_VFP);
- set_feature(env, ARM_FEATURE_VAPA);
env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
@@ -125,10 +104,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c0_cachetype = 0x1dd20d2;
break;
case ARM_CPUID_CORTEXA8:
- set_feature(env, ARM_FEATURE_V7);
- set_feature(env, ARM_FEATURE_VFP3);
- set_feature(env, ARM_FEATURE_NEON);
- set_feature(env, ARM_FEATURE_THUMB2EE);
env->vfp.xregs[ARM_VFP_FPSID] = 0x410330c0;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100;
@@ -142,16 +117,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c1_sys = 0x00c50078;
break;
case ARM_CPUID_CORTEXA9:
- set_feature(env, ARM_FEATURE_V7);
- set_feature(env, ARM_FEATURE_VFP3);
- set_feature(env, ARM_FEATURE_VFP_FP16);
- set_feature(env, ARM_FEATURE_NEON);
- set_feature(env, ARM_FEATURE_THUMB2EE);
- /* Note that A9 supports the MP extensions even for
- * A9UP and single-core A9MP (which are both different
- * and valid configurations; we don't model A9UP).
- */
- set_feature(env, ARM_FEATURE_V7MP);
env->vfp.xregs[ARM_VFP_FPSID] = 0x41034000; /* Guess */
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x01111111;
@@ -164,14 +129,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c1_sys = 0x00c50078;
break;
case ARM_CPUID_CORTEXA15:
- set_feature(env, ARM_FEATURE_V7);
- set_feature(env, ARM_FEATURE_VFP4);
- set_feature(env, ARM_FEATURE_VFP_FP16);
- set_feature(env, ARM_FEATURE_NEON);
- set_feature(env, ARM_FEATURE_THUMB2EE);
- set_feature(env, ARM_FEATURE_ARM_DIV);
- set_feature(env, ARM_FEATURE_V7MP);
- set_feature(env, ARM_FEATURE_GENERIC_TIMER);
env->vfp.xregs[ARM_VFP_FPSID] = 0x410430f0;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x10110222;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x11111111;
@@ -185,22 +142,11 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c1_sys = 0x00c50078;
break;
case ARM_CPUID_CORTEXM3:
- set_feature(env, ARM_FEATURE_V7);
- set_feature(env, ARM_FEATURE_M);
break;
case ARM_CPUID_ANY: /* For userspace emulation. */
- set_feature(env, ARM_FEATURE_V7);
- set_feature(env, ARM_FEATURE_VFP4);
- set_feature(env, ARM_FEATURE_VFP_FP16);
- set_feature(env, ARM_FEATURE_NEON);
- set_feature(env, ARM_FEATURE_THUMB2EE);
- set_feature(env, ARM_FEATURE_ARM_DIV);
- set_feature(env, ARM_FEATURE_V7MP);
break;
case ARM_CPUID_TI915T:
case ARM_CPUID_TI925T:
- set_feature(env, ARM_FEATURE_V4T);
- set_feature(env, ARM_FEATURE_OMAPCP);
env->cp15.c0_cachetype = 0x5109149;
env->cp15.c1_sys = 0x00000070;
env->cp15.c15_i_max = 0x000;
@@ -211,8 +157,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
case ARM_CPUID_PXA260:
case ARM_CPUID_PXA261:
case ARM_CPUID_PXA262:
- set_feature(env, ARM_FEATURE_V5);
- set_feature(env, ARM_FEATURE_XSCALE);
/* JTAG_ID is ((id << 28) | 0x09265013) */
env->cp15.c0_cachetype = 0xd172172;
env->cp15.c1_sys = 0x00000078;
@@ -223,58 +167,19 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
case ARM_CPUID_PXA270_B1:
case ARM_CPUID_PXA270_C0:
case ARM_CPUID_PXA270_C5:
- set_feature(env, ARM_FEATURE_V5);
- set_feature(env, ARM_FEATURE_XSCALE);
/* JTAG_ID is ((id << 28) | 0x09265013) */
- set_feature(env, ARM_FEATURE_IWMMXT);
env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
env->cp15.c0_cachetype = 0xd172172;
env->cp15.c1_sys = 0x00000078;
break;
case ARM_CPUID_SA1100:
case ARM_CPUID_SA1110:
- set_feature(env, ARM_FEATURE_STRONGARM);
env->cp15.c1_sys = 0x00000070;
break;
default:
cpu_abort(env, "Bad CPU ID: %x\n", id);
break;
}
-
- /* Some features automatically imply others: */
- if (arm_feature(env, ARM_FEATURE_V7)) {
- set_feature(env, ARM_FEATURE_VAPA);
- set_feature(env, ARM_FEATURE_THUMB2);
- if (!arm_feature(env, ARM_FEATURE_M)) {
- set_feature(env, ARM_FEATURE_V6K);
- } else {
- set_feature(env, ARM_FEATURE_V6);
- }
- }
- if (arm_feature(env, ARM_FEATURE_V6K)) {
- set_feature(env, ARM_FEATURE_V6);
- }
- if (arm_feature(env, ARM_FEATURE_V6)) {
- set_feature(env, ARM_FEATURE_V5);
- if (!arm_feature(env, ARM_FEATURE_M)) {
- set_feature(env, ARM_FEATURE_AUXCR);
- }
- }
- if (arm_feature(env, ARM_FEATURE_V5)) {
- set_feature(env, ARM_FEATURE_V4T);
- }
- if (arm_feature(env, ARM_FEATURE_M)) {
- set_feature(env, ARM_FEATURE_THUMB_DIV);
- }
- if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
- set_feature(env, ARM_FEATURE_THUMB_DIV);
- }
- if (arm_feature(env, ARM_FEATURE_VFP4)) {
- set_feature(env, ARM_FEATURE_VFP3);
- }
- if (arm_feature(env, ARM_FEATURE_VFP3)) {
- set_feature(env, ARM_FEATURE_VFP);
- }
}
void cpu_reset(CPUARMState *env)
diff --git a/target-arm/machine.c b/target-arm/machine.c
index f66b8df..c93fded 100644
--- a/target-arm/machine.c
+++ b/target-arm/machine.c
@@ -5,6 +5,7 @@ void cpu_save(QEMUFile *f, void *opaque)
{
int i;
CPUARMState *env = (CPUARMState *)opaque;
+ ARMCPU *cpu = ARM_CPU(ENV_GET_OBJECT(env));
for (i = 0; i < 16; i++) {
qemu_put_be32(f, env->regs[i]);
@@ -61,7 +62,7 @@ void cpu_save(QEMUFile *f, void *opaque)
qemu_put_be32(f, env->cp15.c15_diagnostic);
qemu_put_be32(f, env->cp15.c15_power_diagnostic);
- qemu_put_be32(f, env->features);
+ qemu_put_be32(f, cpu->features);
if (arm_feature(env, ARM_FEATURE_VFP)) {
for (i = 0; i < 16; i++) {
@@ -115,6 +116,7 @@ void cpu_save(QEMUFile *f, void *opaque)
int cpu_load(QEMUFile *f, void *opaque, int version_id)
{
CPUARMState *env = (CPUARMState *)opaque;
+ ARMCPU *cpu = ARM_CPU(ENV_GET_OBJECT(env));
int i;
uint32_t val;
@@ -179,7 +181,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
env->cp15.c15_diagnostic = qemu_get_be32(f);
env->cp15.c15_power_diagnostic = qemu_get_be32(f);
- env->features = qemu_get_be32(f);
+ cpu->features = qemu_get_be32(f);
if (arm_feature(env, ARM_FEATURE_VFP)) {
for (i = 0; i < 16; i++) {
--
1.7.7
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH RFC v3 09/21] target-arm: No longer abort on unhandled CPUIDs on reset
2012-02-03 2:59 [Qemu-devel] [PATCH RFC v3 00/21] Introduce QOM CPU and use it for ARM Andreas Färber
` (7 preceding siblings ...)
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 08/21] target-arm: Move CPU feature flags out of CPUState Andreas Färber
@ 2012-02-03 2:59 ` Andreas Färber
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 10/21] target-arm: Store cp15 c0_c1 and c0_c2 in ARMCPUClass Andreas Färber
` (11 subsequent siblings)
20 siblings, 0 replies; 47+ messages in thread
From: Andreas Färber @ 2012-02-03 2:59 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Andreas Färber
Having moved the reset code for some CPUs to class_init, we can drop
some of the cases in the switch.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/cpu.h | 2 --
target-arm/helper.c | 5 -----
2 files changed, 0 insertions(+), 7 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index bf8c911..6731256 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -427,8 +427,6 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
#define ARM_CPUID_CORTEXA8 0x410fc080
#define ARM_CPUID_CORTEXA9 0x410fc090
#define ARM_CPUID_CORTEXA15 0x412fc0f1
-#define ARM_CPUID_CORTEXM3 0x410fc231
-#define ARM_CPUID_ANY 0xffffffff
#if defined(CONFIG_USER_ONLY)
#define TARGET_PAGE_BITS 12
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 4fd8ba8..67e18cc 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -141,10 +141,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c0_ccsid[2] = 0x711fe07a; /* 4096K L2 unified cache */
env->cp15.c1_sys = 0x00c50078;
break;
- case ARM_CPUID_CORTEXM3:
- break;
- case ARM_CPUID_ANY: /* For userspace emulation. */
- break;
case ARM_CPUID_TI915T:
case ARM_CPUID_TI925T:
env->cp15.c0_cachetype = 0x5109149;
@@ -177,7 +173,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c1_sys = 0x00000070;
break;
default:
- cpu_abort(env, "Bad CPU ID: %x\n", id);
break;
}
}
--
1.7.7
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH RFC v3 10/21] target-arm: Store cp15 c0_c1 and c0_c2 in ARMCPUClass
2012-02-03 2:59 [Qemu-devel] [PATCH RFC v3 00/21] Introduce QOM CPU and use it for ARM Andreas Färber
` (8 preceding siblings ...)
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 09/21] target-arm: No longer abort on unhandled CPUIDs on reset Andreas Färber
@ 2012-02-03 2:59 ` Andreas Färber
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 11/21] target-arm: Store cp15 c0_cachetype register " Andreas Färber
` (10 subsequent siblings)
20 siblings, 0 replies; 47+ messages in thread
From: Andreas Färber @ 2012-02-03 2:59 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Andreas Färber
For now set them in the reset function.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/cpu-core.h | 2 +
target-arm/cpu.c | 64 +++++++++++++++++++++++++++++++++++++++++++++++++
target-arm/helper.c | 51 ---------------------------------------
3 files changed, 66 insertions(+), 51 deletions(-)
diff --git a/target-arm/cpu-core.h b/target-arm/cpu-core.h
index 9f090a8..bb59f8d 100644
--- a/target-arm/cpu-core.h
+++ b/target-arm/cpu-core.h
@@ -43,6 +43,8 @@ typedef struct ARMCPUClass {
struct {
uint32_t c0_cpuid;
+ uint32_t c0_c1[8];
+ uint32_t c0_c2[8];
} cp15;
/* Internal CPU feature flags. */
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 07cbfe6..909eb1a 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -27,6 +27,7 @@
static void arm_cpu_reset(CPU *c)
{
ARMCPU *cpu = ARM_CPU(c);
+ ARMCPUClass *cpu_class = ARM_CPU_GET_CLASS(cpu);
CPUARMState *env = &cpu->env;
uint32_t id;
uint32_t tmp;
@@ -44,6 +45,10 @@ static void arm_cpu_reset(CPU *c)
env->cp15.c0_cpuid = id;
env->cp15.c15_config_base_address = tmp;
+ /* TODO Move these into arm_cpu_initfn() once no longer zeroed above. */
+ memcpy(env->cp15.c0_c1, cpu_class->cp15.c0_c1, 8 * sizeof(uint32_t));
+ memcpy(env->cp15.c0_c2, cpu_class->cp15.c0_c2, 8 * sizeof(uint32_t));
+
#if defined(CONFIG_USER_ONLY)
env->uncached_cpsr = ARM_CPU_MODE_USR;
/* For user mode we must enable access to coprocessors */
@@ -159,6 +164,8 @@ static inline void unset_class_feature(ARMCPUClass *klass, int feature)
typedef struct ARMCPUInfo {
const char *name;
uint32_t id;
+ uint32_t cp15_c0_c1[8];
+ uint32_t cp15_c0_c2[8];
uint32_t features;
void (*class_init)(ARMCPUClass *klass, const struct ARMCPUInfo *info);
} ARMCPUInfo;
@@ -171,6 +178,13 @@ static void arm1136_r0_class_init(ARMCPUClass *k, const ARMCPUInfo *info)
k->features = r1_class->features;
unset_class_feature(k, ARM_FEATURE_V6K);
+
+ /* These ID register values are correct for 1136 but may be wrong
+ * for 1136_r2 (in particular r0p2 does not actually implement most
+ * of the ID registers).
+ */
+ memcpy(k->cp15.c0_c1, r1_class->cp15.c0_c1, 8 * sizeof(uint32_t));
+ memcpy(k->cp15.c0_c2, r1_class->cp15.c0_c2, 8 * sizeof(uint32_t));
}
static void ti925t_reset(CPU *c)
@@ -240,12 +254,28 @@ static const ARMCPUInfo arm_cpus[] = {
{
.name = "arm1136",
.id = 0x4117b363,
+ .cp15_c0_c1 = {
+ 0x111, 0x1, 0x2, 0x3,
+ 0x01130003, 0x10030302, 0x01222110, 0
+ },
+ .cp15_c0_c2 = {
+ 0x00140011, 0x12002111, 0x11231111, 0x01102131,
+ 0x141, 0, 0, 0
+ },
.features = ARM_FEATURE(V6) |
ARM_FEATURE(VFP),
},
{
.name = "arm1176",
.id = 0x410fb767,
+ .cp15_c0_c1 = {
+ 0x111, 0x11, 0x33, 0,
+ 0x01130003, 0x10030302, 0x01222100, 0
+ },
+ .cp15_c0_c2 = {
+ 0x0140011, 0x12002111, 0x11231121, 0x01102131,
+ 0x01141, 0, 0, 0
+ },
.features = ARM_FEATURE(V6K) |
ARM_FEATURE(VFP) |
ARM_FEATURE(VAPA),
@@ -253,6 +283,14 @@ static const ARMCPUInfo arm_cpus[] = {
{
.name = "arm11mpcore",
.id = 0x410fb022,
+ .cp15_c0_c1 = {
+ 0x111, 0x1, 0, 0x2,
+ 0x01100103, 0x10020302, 0x01222000, 0
+ },
+ .cp15_c0_c2 = {
+ 0x00100011, 0x12002111, 0x11221011, 0x01102131,
+ 0x141, 0, 0, 0
+ },
.features = ARM_FEATURE(V6K) |
ARM_FEATURE(VFP) |
ARM_FEATURE(VAPA),
@@ -266,6 +304,14 @@ static const ARMCPUInfo arm_cpus[] = {
{
.name = "cortex-a8",
.id = 0x410fc080,
+ .cp15_c0_c1 = {
+ 0x1031, 0x11, 0x400, 0,
+ 0x31100003, 0x20000000, 0x01202000, 0x11
+ },
+ .cp15_c0_c2 = {
+ 0x00101111, 0x12112111, 0x21232031, 0x11112131,
+ 0x00111142, 0, 0, 0
+ },
.features = ARM_FEATURE(V7) |
ARM_FEATURE(VFP3) |
ARM_FEATURE(NEON) |
@@ -274,6 +320,14 @@ static const ARMCPUInfo arm_cpus[] = {
{
.name = "cortex-a9",
.id = 0x410fc090,
+ .cp15_c0_c1 = {
+ 0x1031, 0x11, 0x000, 0,
+ 0x00100103, 0x20000000, 0x01230000, 0x00002111
+ },
+ .cp15_c0_c2 = {
+ 0x00101111, 0x13112111, 0x21232041, 0x11112131,
+ 0x00111142, 0, 0, 0
+ },
.features = ARM_FEATURE(V7) |
ARM_FEATURE(VFP3) |
ARM_FEATURE(VFP_FP16) |
@@ -288,6 +342,14 @@ static const ARMCPUInfo arm_cpus[] = {
{
.name = "cortex-a15",
.id = 0x412fc0f1,
+ .cp15_c0_c1 = {
+ 0x00001131, 0x00011011, 0x02010555, 0x00000000,
+ 0x10201105, 0x20000000, 0x01240000, 0x02102211
+ },
+ .cp15_c0_c2 = {
+ 0x02101110, 0x13112111, 0x21232041, 0x11112131,
+ 0x10011142, 0, 0, 0
+ },
.features = ARM_FEATURE(V7) |
ARM_FEATURE(VFP4) |
ARM_FEATURE(VFP_FP16) |
@@ -405,6 +467,8 @@ static void arm_cpu_class_init(ObjectClass *klass, void *data)
cpu_class->reset = arm_cpu_reset;
k->cp15.c0_cpuid = info->id;
+ memcpy(k->cp15.c0_c1, info->cp15_c0_c1, 8 * sizeof(uint32_t));
+ memcpy(k->cp15.c0_c2, info->cp15_c0_c2, 8 * sizeof(uint32_t));
k->features = info->features;
if (info->class_init != NULL) {
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 67e18cc..2af8df4 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -10,45 +10,6 @@
#include "sysemu.h"
#include "cpu-core.h"
-static uint32_t cortexa15_cp15_c0_c1[8] = {
- 0x00001131, 0x00011011, 0x02010555, 0x00000000,
- 0x10201105, 0x20000000, 0x01240000, 0x02102211
-};
-
-static uint32_t cortexa15_cp15_c0_c2[8] = {
- 0x02101110, 0x13112111, 0x21232041, 0x11112131, 0x10011142, 0, 0, 0
-};
-
-static uint32_t cortexa9_cp15_c0_c1[8] =
-{ 0x1031, 0x11, 0x000, 0, 0x00100103, 0x20000000, 0x01230000, 0x00002111 };
-
-static uint32_t cortexa9_cp15_c0_c2[8] =
-{ 0x00101111, 0x13112111, 0x21232041, 0x11112131, 0x00111142, 0, 0, 0 };
-
-static uint32_t cortexa8_cp15_c0_c1[8] =
-{ 0x1031, 0x11, 0x400, 0, 0x31100003, 0x20000000, 0x01202000, 0x11 };
-
-static uint32_t cortexa8_cp15_c0_c2[8] =
-{ 0x00101111, 0x12112111, 0x21232031, 0x11112131, 0x00111142, 0, 0, 0 };
-
-static uint32_t mpcore_cp15_c0_c1[8] =
-{ 0x111, 0x1, 0, 0x2, 0x01100103, 0x10020302, 0x01222000, 0 };
-
-static uint32_t mpcore_cp15_c0_c2[8] =
-{ 0x00100011, 0x12002111, 0x11221011, 0x01102131, 0x141, 0, 0, 0 };
-
-static uint32_t arm1136_cp15_c0_c1[8] =
-{ 0x111, 0x1, 0x2, 0x3, 0x01130003, 0x10030302, 0x01222110, 0 };
-
-static uint32_t arm1136_cp15_c0_c2[8] =
-{ 0x00140011, 0x12002111, 0x11231111, 0x01102131, 0x141, 0, 0, 0 };
-
-static uint32_t arm1176_cp15_c0_c1[8] =
-{ 0x111, 0x11, 0x33, 0, 0x01130003, 0x10030302, 0x01222100, 0 };
-
-static uint32_t arm1176_cp15_c0_c2[8] =
-{ 0x0140011, 0x12002111, 0x11231121, 0x01102131, 0x01141, 0, 0, 0 };
-
static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
{
switch (id) {
@@ -81,8 +42,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
- memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t));
- memcpy(env->cp15.c0_c2, arm1136_cp15_c0_c2, 8 * sizeof(uint32_t));
env->cp15.c0_cachetype = 0x1dd20d2;
env->cp15.c1_sys = 0x00050078;
break;
@@ -90,8 +49,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b5;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
- memcpy(env->cp15.c0_c1, arm1176_cp15_c0_c1, 8 * sizeof(uint32_t));
- memcpy(env->cp15.c0_c2, arm1176_cp15_c0_c2, 8 * sizeof(uint32_t));
env->cp15.c0_cachetype = 0x1dd20d2;
env->cp15.c1_sys = 0x00050078;
break;
@@ -99,16 +56,12 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
- memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t));
- memcpy(env->cp15.c0_c2, mpcore_cp15_c0_c2, 8 * sizeof(uint32_t));
env->cp15.c0_cachetype = 0x1dd20d2;
break;
case ARM_CPUID_CORTEXA8:
env->vfp.xregs[ARM_VFP_FPSID] = 0x410330c0;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100;
- memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t));
- memcpy(env->cp15.c0_c2, cortexa8_cp15_c0_c2, 8 * sizeof(uint32_t));
env->cp15.c0_cachetype = 0x82048004;
env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3;
env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */
@@ -120,8 +73,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->vfp.xregs[ARM_VFP_FPSID] = 0x41034000; /* Guess */
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x01111111;
- memcpy(env->cp15.c0_c1, cortexa9_cp15_c0_c1, 8 * sizeof(uint32_t));
- memcpy(env->cp15.c0_c2, cortexa9_cp15_c0_c2, 8 * sizeof(uint32_t));
env->cp15.c0_cachetype = 0x80038003;
env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3;
env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */
@@ -132,8 +83,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->vfp.xregs[ARM_VFP_FPSID] = 0x410430f0;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x10110222;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x11111111;
- memcpy(env->cp15.c0_c1, cortexa15_cp15_c0_c1, 8 * sizeof(uint32_t));
- memcpy(env->cp15.c0_c2, cortexa15_cp15_c0_c2, 8 * sizeof(uint32_t));
env->cp15.c0_cachetype = 0x8444c004;
env->cp15.c0_clid = 0x0a200023;
env->cp15.c0_ccsid[0] = 0x701fe00a; /* 32K L1 dcache */
--
1.7.7
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH RFC v3 11/21] target-arm: Store cp15 c0_cachetype register in ARMCPUClass
2012-02-03 2:59 [Qemu-devel] [PATCH RFC v3 00/21] Introduce QOM CPU and use it for ARM Andreas Färber
` (9 preceding siblings ...)
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 10/21] target-arm: Store cp15 c0_c1 and c0_c2 in ARMCPUClass Andreas Färber
@ 2012-02-03 2:59 ` Andreas Färber
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 12/21] target-arm: Move cp15 c1_sys register to ARMCPUClass Andreas Färber
` (9 subsequent siblings)
20 siblings, 0 replies; 47+ messages in thread
From: Andreas Färber @ 2012-02-03 2:59 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Andreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/cpu-core.h | 1 +
target-arm/cpu.c | 18 ++++++++++++++++++
target-arm/helper.c | 12 ------------
3 files changed, 19 insertions(+), 12 deletions(-)
diff --git a/target-arm/cpu-core.h b/target-arm/cpu-core.h
index bb59f8d..1d5adc8 100644
--- a/target-arm/cpu-core.h
+++ b/target-arm/cpu-core.h
@@ -43,6 +43,7 @@ typedef struct ARMCPUClass {
struct {
uint32_t c0_cpuid;
+ uint32_t c0_cachetype;
uint32_t c0_c1[8];
uint32_t c0_c2[8];
} cp15;
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 909eb1a..fe34b31 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -46,6 +46,7 @@ static void arm_cpu_reset(CPU *c)
env->cp15.c15_config_base_address = tmp;
/* TODO Move these into arm_cpu_initfn() once no longer zeroed above. */
+ env->cp15.c0_cachetype = cpu_class->cp15.c0_cachetype;
memcpy(env->cp15.c0_c1, cpu_class->cp15.c0_c1, 8 * sizeof(uint32_t));
memcpy(env->cp15.c0_c2, cpu_class->cp15.c0_c2, 8 * sizeof(uint32_t));
@@ -164,6 +165,7 @@ static inline void unset_class_feature(ARMCPUClass *klass, int feature)
typedef struct ARMCPUInfo {
const char *name;
uint32_t id;
+ uint32_t cp15_c0_cachetype;
uint32_t cp15_c0_c1[8];
uint32_t cp15_c0_c2[8];
uint32_t features;
@@ -183,6 +185,7 @@ static void arm1136_r0_class_init(ARMCPUClass *k, const ARMCPUInfo *info)
* for 1136_r2 (in particular r0p2 does not actually implement most
* of the ID registers).
*/
+ k->cp15.c0_cachetype = r1_class->cp15.c0_cachetype;
memcpy(k->cp15.c0_c1, r1_class->cp15.c0_c1, 8 * sizeof(uint32_t));
memcpy(k->cp15.c0_c2, r1_class->cp15.c0_c2, 8 * sizeof(uint32_t));
}
@@ -211,12 +214,16 @@ static void sa11xx_class_init(ARMCPUClass *k, const ARMCPUInfo *info)
static void pxa25x_class_init(ARMCPUClass *k, const ARMCPUInfo *info)
{
+ k->cp15.c0_cachetype = 0xd172172;
+
set_class_feature(k, ARM_FEATURE_V5);
set_class_feature(k, ARM_FEATURE_XSCALE);
}
static void pxa270_class_init(ARMCPUClass *k, const ARMCPUInfo *info)
{
+ k->cp15.c0_cachetype = 0xd172172;
+
set_class_feature(k, ARM_FEATURE_V5);
set_class_feature(k, ARM_FEATURE_XSCALE);
set_class_feature(k, ARM_FEATURE_IWMMXT);
@@ -226,18 +233,21 @@ static const ARMCPUInfo arm_cpus[] = {
{
.name = "arm926",
.id = 0x41069265,
+ .cp15_c0_cachetype = 0x1dd20d2,
.features = ARM_FEATURE(V5) |
ARM_FEATURE(VFP),
},
{
.name = "arm946",
.id = 0x41059461,
+ .cp15_c0_cachetype = 0x0f004006,
.features = ARM_FEATURE(V5) |
ARM_FEATURE(MPU),
},
{
.name = "arm1026",
.id = 0x4106a262,
+ .cp15_c0_cachetype = 0x1dd20d2,
.features = ARM_FEATURE(V5) |
ARM_FEATURE(VFP) |
ARM_FEATURE(AUXCR),
@@ -254,6 +264,7 @@ static const ARMCPUInfo arm_cpus[] = {
{
.name = "arm1136",
.id = 0x4117b363,
+ .cp15_c0_cachetype = 0x1dd20d2,
.cp15_c0_c1 = {
0x111, 0x1, 0x2, 0x3,
0x01130003, 0x10030302, 0x01222110, 0
@@ -268,6 +279,7 @@ static const ARMCPUInfo arm_cpus[] = {
{
.name = "arm1176",
.id = 0x410fb767,
+ .cp15_c0_cachetype = 0x1dd20d2,
.cp15_c0_c1 = {
0x111, 0x11, 0x33, 0,
0x01130003, 0x10030302, 0x01222100, 0
@@ -283,6 +295,7 @@ static const ARMCPUInfo arm_cpus[] = {
{
.name = "arm11mpcore",
.id = 0x410fb022,
+ .cp15_c0_cachetype = 0x1dd20d2,
.cp15_c0_c1 = {
0x111, 0x1, 0, 0x2,
0x01100103, 0x10020302, 0x01222000, 0
@@ -304,6 +317,7 @@ static const ARMCPUInfo arm_cpus[] = {
{
.name = "cortex-a8",
.id = 0x410fc080,
+ .cp15_c0_cachetype = 0x82048004,
.cp15_c0_c1 = {
0x1031, 0x11, 0x400, 0,
0x31100003, 0x20000000, 0x01202000, 0x11
@@ -320,6 +334,7 @@ static const ARMCPUInfo arm_cpus[] = {
{
.name = "cortex-a9",
.id = 0x410fc090,
+ .cp15_c0_cachetype = 0x80038003,
.cp15_c0_c1 = {
0x1031, 0x11, 0x000, 0,
0x00100103, 0x20000000, 0x01230000, 0x00002111
@@ -342,6 +357,7 @@ static const ARMCPUInfo arm_cpus[] = {
{
.name = "cortex-a15",
.id = 0x412fc0f1,
+ .cp15_c0_cachetype = 0x8444c004,
.cp15_c0_c1 = {
0x00001131, 0x00011011, 0x02010555, 0x00000000,
0x10201105, 0x20000000, 0x01240000, 0x02102211
@@ -362,6 +378,7 @@ static const ARMCPUInfo arm_cpus[] = {
{
.name = "ti925t",
.id = 0x54029252,
+ .cp15_c0_cachetype = 0x5109149,
.features = ARM_FEATURE(V4T) |
ARM_FEATURE(OMAPCP),
.class_init = ti925t_class_init,
@@ -467,6 +484,7 @@ static void arm_cpu_class_init(ObjectClass *klass, void *data)
cpu_class->reset = arm_cpu_reset;
k->cp15.c0_cpuid = info->id;
+ k->cp15.c0_cachetype = info->cp15_c0_cachetype;
memcpy(k->cp15.c0_c1, info->cp15_c0_c1, 8 * sizeof(uint32_t));
memcpy(k->cp15.c0_c2, info->cp15_c0_c2, 8 * sizeof(uint32_t));
k->features = info->features;
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 2af8df4..9a4afad 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -15,16 +15,13 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
switch (id) {
case ARM_CPUID_ARM926:
env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090;
- env->cp15.c0_cachetype = 0x1dd20d2;
env->cp15.c1_sys = 0x00090078;
break;
case ARM_CPUID_ARM946:
- env->cp15.c0_cachetype = 0x0f004006;
env->cp15.c1_sys = 0x00000078;
break;
case ARM_CPUID_ARM1026:
env->vfp.xregs[ARM_VFP_FPSID] = 0x410110a0;
- env->cp15.c0_cachetype = 0x1dd20d2;
env->cp15.c1_sys = 0x00090078;
break;
case ARM_CPUID_ARM1136:
@@ -42,27 +39,23 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
- env->cp15.c0_cachetype = 0x1dd20d2;
env->cp15.c1_sys = 0x00050078;
break;
case ARM_CPUID_ARM1176:
env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b5;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
- env->cp15.c0_cachetype = 0x1dd20d2;
env->cp15.c1_sys = 0x00050078;
break;
case ARM_CPUID_ARM11MPCORE:
env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
- env->cp15.c0_cachetype = 0x1dd20d2;
break;
case ARM_CPUID_CORTEXA8:
env->vfp.xregs[ARM_VFP_FPSID] = 0x410330c0;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100;
- env->cp15.c0_cachetype = 0x82048004;
env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3;
env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */
env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */
@@ -73,7 +66,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->vfp.xregs[ARM_VFP_FPSID] = 0x41034000; /* Guess */
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x01111111;
- env->cp15.c0_cachetype = 0x80038003;
env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3;
env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */
env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */
@@ -83,7 +75,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->vfp.xregs[ARM_VFP_FPSID] = 0x410430f0;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x10110222;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x11111111;
- env->cp15.c0_cachetype = 0x8444c004;
env->cp15.c0_clid = 0x0a200023;
env->cp15.c0_ccsid[0] = 0x701fe00a; /* 32K L1 dcache */
env->cp15.c0_ccsid[1] = 0x201fe00a; /* 32K L1 icache */
@@ -92,7 +83,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
break;
case ARM_CPUID_TI915T:
case ARM_CPUID_TI925T:
- env->cp15.c0_cachetype = 0x5109149;
env->cp15.c1_sys = 0x00000070;
env->cp15.c15_i_max = 0x000;
env->cp15.c15_i_min = 0xff0;
@@ -103,7 +93,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
case ARM_CPUID_PXA261:
case ARM_CPUID_PXA262:
/* JTAG_ID is ((id << 28) | 0x09265013) */
- env->cp15.c0_cachetype = 0xd172172;
env->cp15.c1_sys = 0x00000078;
break;
case ARM_CPUID_PXA270_A0:
@@ -114,7 +103,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
case ARM_CPUID_PXA270_C5:
/* JTAG_ID is ((id << 28) | 0x09265013) */
env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
- env->cp15.c0_cachetype = 0xd172172;
env->cp15.c1_sys = 0x00000078;
break;
case ARM_CPUID_SA1100:
--
1.7.7
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH RFC v3 12/21] target-arm: Move cp15 c1_sys register to ARMCPUClass
2012-02-03 2:59 [Qemu-devel] [PATCH RFC v3 00/21] Introduce QOM CPU and use it for ARM Andreas Färber
` (10 preceding siblings ...)
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 11/21] target-arm: Store cp15 c0_cachetype register " Andreas Färber
@ 2012-02-03 2:59 ` Andreas Färber
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 13/21] target-arm: Store JTAG_ID in ARMCPUClass Andreas Färber
` (8 subsequent siblings)
20 siblings, 0 replies; 47+ messages in thread
From: Andreas Färber @ 2012-02-03 2:59 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Andreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/cpu-core.h | 1 +
target-arm/cpu.c | 19 +++++++++++++++++++
target-arm/cpu.h | 3 ---
target-arm/helper.c | 17 -----------------
4 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/target-arm/cpu-core.h b/target-arm/cpu-core.h
index 1d5adc8..3e7dfae 100644
--- a/target-arm/cpu-core.h
+++ b/target-arm/cpu-core.h
@@ -46,6 +46,7 @@ typedef struct ARMCPUClass {
uint32_t c0_cachetype;
uint32_t c0_c1[8];
uint32_t c0_c2[8];
+ uint32_t c1_sys;
} cp15;
/* Internal CPU feature flags. */
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index fe34b31..2c1e1a6 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -50,6 +50,9 @@ static void arm_cpu_reset(CPU *c)
memcpy(env->cp15.c0_c1, cpu_class->cp15.c0_c1, 8 * sizeof(uint32_t));
memcpy(env->cp15.c0_c2, cpu_class->cp15.c0_c2, 8 * sizeof(uint32_t));
+ /* Genuine reset */
+ env->cp15.c1_sys = cpu_class->cp15.c1_sys;
+
#if defined(CONFIG_USER_ONLY)
env->uncached_cpsr = ARM_CPU_MODE_USR;
/* For user mode we must enable access to coprocessors */
@@ -168,6 +171,7 @@ typedef struct ARMCPUInfo {
uint32_t cp15_c0_cachetype;
uint32_t cp15_c0_c1[8];
uint32_t cp15_c0_c2[8];
+ uint32_t cp15_c1_sys;
uint32_t features;
void (*class_init)(ARMCPUClass *klass, const struct ARMCPUInfo *info);
} ARMCPUInfo;
@@ -188,6 +192,7 @@ static void arm1136_r0_class_init(ARMCPUClass *k, const ARMCPUInfo *info)
k->cp15.c0_cachetype = r1_class->cp15.c0_cachetype;
memcpy(k->cp15.c0_c1, r1_class->cp15.c0_c1, 8 * sizeof(uint32_t));
memcpy(k->cp15.c0_c2, r1_class->cp15.c0_c2, 8 * sizeof(uint32_t));
+ k->cp15.c1_sys = r1_class->cp15.c1_sys;
}
static void ti925t_reset(CPU *c)
@@ -209,12 +214,15 @@ static void ti925t_class_init(ARMCPUClass *klass, const ARMCPUInfo *info)
static void sa11xx_class_init(ARMCPUClass *k, const ARMCPUInfo *info)
{
+ k->cp15.c1_sys = 0x00000070;
+
set_class_feature(k, ARM_FEATURE_STRONGARM);
}
static void pxa25x_class_init(ARMCPUClass *k, const ARMCPUInfo *info)
{
k->cp15.c0_cachetype = 0xd172172;
+ k->cp15.c1_sys = 0x00000078;
set_class_feature(k, ARM_FEATURE_V5);
set_class_feature(k, ARM_FEATURE_XSCALE);
@@ -223,6 +231,7 @@ static void pxa25x_class_init(ARMCPUClass *k, const ARMCPUInfo *info)
static void pxa270_class_init(ARMCPUClass *k, const ARMCPUInfo *info)
{
k->cp15.c0_cachetype = 0xd172172;
+ k->cp15.c1_sys = 0x00000078;
set_class_feature(k, ARM_FEATURE_V5);
set_class_feature(k, ARM_FEATURE_XSCALE);
@@ -234,6 +243,7 @@ static const ARMCPUInfo arm_cpus[] = {
.name = "arm926",
.id = 0x41069265,
.cp15_c0_cachetype = 0x1dd20d2,
+ .cp15_c1_sys = 0x00090078,
.features = ARM_FEATURE(V5) |
ARM_FEATURE(VFP),
},
@@ -241,6 +251,7 @@ static const ARMCPUInfo arm_cpus[] = {
.name = "arm946",
.id = 0x41059461,
.cp15_c0_cachetype = 0x0f004006,
+ .cp15_c1_sys = 0x00000078,
.features = ARM_FEATURE(V5) |
ARM_FEATURE(MPU),
},
@@ -248,6 +259,7 @@ static const ARMCPUInfo arm_cpus[] = {
.name = "arm1026",
.id = 0x4106a262,
.cp15_c0_cachetype = 0x1dd20d2,
+ .cp15_c1_sys = 0x00090078,
.features = ARM_FEATURE(V5) |
ARM_FEATURE(VFP) |
ARM_FEATURE(AUXCR),
@@ -273,6 +285,7 @@ static const ARMCPUInfo arm_cpus[] = {
0x00140011, 0x12002111, 0x11231111, 0x01102131,
0x141, 0, 0, 0
},
+ .cp15_c1_sys = 0x00050078,
.features = ARM_FEATURE(V6) |
ARM_FEATURE(VFP),
},
@@ -288,6 +301,7 @@ static const ARMCPUInfo arm_cpus[] = {
0x0140011, 0x12002111, 0x11231121, 0x01102131,
0x01141, 0, 0, 0
},
+ .cp15_c1_sys = 0x00050078,
.features = ARM_FEATURE(V6K) |
ARM_FEATURE(VFP) |
ARM_FEATURE(VAPA),
@@ -326,6 +340,7 @@ static const ARMCPUInfo arm_cpus[] = {
0x00101111, 0x12112111, 0x21232031, 0x11112131,
0x00111142, 0, 0, 0
},
+ .cp15_c1_sys = 0x00c50078,
.features = ARM_FEATURE(V7) |
ARM_FEATURE(VFP3) |
ARM_FEATURE(NEON) |
@@ -343,6 +358,7 @@ static const ARMCPUInfo arm_cpus[] = {
0x00101111, 0x13112111, 0x21232041, 0x11112131,
0x00111142, 0, 0, 0
},
+ .cp15_c1_sys = 0x00c50078,
.features = ARM_FEATURE(V7) |
ARM_FEATURE(VFP3) |
ARM_FEATURE(VFP_FP16) |
@@ -366,6 +382,7 @@ static const ARMCPUInfo arm_cpus[] = {
0x02101110, 0x13112111, 0x21232041, 0x11112131,
0x10011142, 0, 0, 0
},
+ .cp15_c1_sys = 0x00c50078,
.features = ARM_FEATURE(V7) |
ARM_FEATURE(VFP4) |
ARM_FEATURE(VFP_FP16) |
@@ -379,6 +396,7 @@ static const ARMCPUInfo arm_cpus[] = {
.name = "ti925t",
.id = 0x54029252,
.cp15_c0_cachetype = 0x5109149,
+ .cp15_c1_sys = 0x00000070,
.features = ARM_FEATURE(V4T) |
ARM_FEATURE(OMAPCP),
.class_init = ti925t_class_init,
@@ -487,6 +505,7 @@ static void arm_cpu_class_init(ObjectClass *klass, void *data)
k->cp15.c0_cachetype = info->cp15_c0_cachetype;
memcpy(k->cp15.c0_c1, info->cp15_c0_c1, 8 * sizeof(uint32_t));
memcpy(k->cp15.c0_c2, info->cp15_c0_c2, 8 * sizeof(uint32_t));
+ k->cp15.c1_sys = info->cp15_c1_sys;
k->features = info->features;
if (info->class_init != NULL) {
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 6731256..e16befd 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -404,11 +404,8 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
#define ARM_CPUID_ARM1026 0x4106a262
#define ARM_CPUID_ARM926 0x41069265
-#define ARM_CPUID_ARM946 0x41059461
#define ARM_CPUID_TI915T 0x54029152
#define ARM_CPUID_TI925T 0x54029252
-#define ARM_CPUID_SA1100 0x4401A11B
-#define ARM_CPUID_SA1110 0x6901B119
#define ARM_CPUID_PXA250 0x69052100
#define ARM_CPUID_PXA255 0x69052d00
#define ARM_CPUID_PXA260 0x69052903
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 9a4afad..32319e4 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -15,14 +15,9 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
switch (id) {
case ARM_CPUID_ARM926:
env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090;
- env->cp15.c1_sys = 0x00090078;
- break;
- case ARM_CPUID_ARM946:
- env->cp15.c1_sys = 0x00000078;
break;
case ARM_CPUID_ARM1026:
env->vfp.xregs[ARM_VFP_FPSID] = 0x410110a0;
- env->cp15.c1_sys = 0x00090078;
break;
case ARM_CPUID_ARM1136:
/* This is the 1136 r1, which is a v6K core */
@@ -39,13 +34,11 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
- env->cp15.c1_sys = 0x00050078;
break;
case ARM_CPUID_ARM1176:
env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b5;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
- env->cp15.c1_sys = 0x00050078;
break;
case ARM_CPUID_ARM11MPCORE:
env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
@@ -60,7 +53,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */
env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */
env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */
- env->cp15.c1_sys = 0x00c50078;
break;
case ARM_CPUID_CORTEXA9:
env->vfp.xregs[ARM_VFP_FPSID] = 0x41034000; /* Guess */
@@ -69,7 +61,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3;
env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */
env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */
- env->cp15.c1_sys = 0x00c50078;
break;
case ARM_CPUID_CORTEXA15:
env->vfp.xregs[ARM_VFP_FPSID] = 0x410430f0;
@@ -79,11 +70,9 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c0_ccsid[0] = 0x701fe00a; /* 32K L1 dcache */
env->cp15.c0_ccsid[1] = 0x201fe00a; /* 32K L1 icache */
env->cp15.c0_ccsid[2] = 0x711fe07a; /* 4096K L2 unified cache */
- env->cp15.c1_sys = 0x00c50078;
break;
case ARM_CPUID_TI915T:
case ARM_CPUID_TI925T:
- env->cp15.c1_sys = 0x00000070;
env->cp15.c15_i_max = 0x000;
env->cp15.c15_i_min = 0xff0;
break;
@@ -93,7 +82,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
case ARM_CPUID_PXA261:
case ARM_CPUID_PXA262:
/* JTAG_ID is ((id << 28) | 0x09265013) */
- env->cp15.c1_sys = 0x00000078;
break;
case ARM_CPUID_PXA270_A0:
case ARM_CPUID_PXA270_A1:
@@ -103,11 +91,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
case ARM_CPUID_PXA270_C5:
/* JTAG_ID is ((id << 28) | 0x09265013) */
env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
- env->cp15.c1_sys = 0x00000078;
- break;
- case ARM_CPUID_SA1100:
- case ARM_CPUID_SA1110:
- env->cp15.c1_sys = 0x00000070;
break;
default:
break;
--
1.7.7
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH RFC v3 13/21] target-arm: Store JTAG_ID in ARMCPUClass
2012-02-03 2:59 [Qemu-devel] [PATCH RFC v3 00/21] Introduce QOM CPU and use it for ARM Andreas Färber
` (11 preceding siblings ...)
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 12/21] target-arm: Move cp15 c1_sys register to ARMCPUClass Andreas Färber
@ 2012-02-03 2:59 ` Andreas Färber
2012-02-07 17:47 ` Peter Maydell
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 14/21] target-arm: Move the PXA270's iwMMXt reset to pxa270_reset() Andreas Färber
` (7 subsequent siblings)
20 siblings, 1 reply; 47+ messages in thread
From: Andreas Färber @ 2012-02-03 2:59 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Andreas Färber
That way we can remove some more CPUID cases without losing info.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Andrzej Zaborowski <balrogg@gmail.com>
---
target-arm/cpu-core.h | 1 +
target-arm/cpu.c | 2 ++
target-arm/cpu.h | 5 -----
target-arm/helper.c | 8 --------
4 files changed, 3 insertions(+), 13 deletions(-)
diff --git a/target-arm/cpu-core.h b/target-arm/cpu-core.h
index 3e7dfae..eac1a03 100644
--- a/target-arm/cpu-core.h
+++ b/target-arm/cpu-core.h
@@ -48,6 +48,7 @@ typedef struct ARMCPUClass {
uint32_t c0_c2[8];
uint32_t c1_sys;
} cp15;
+ uint64_t jtag_id;
/* Internal CPU feature flags. */
uint32_t features;
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 2c1e1a6..7d4f0f6 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -223,6 +223,7 @@ static void pxa25x_class_init(ARMCPUClass *k, const ARMCPUInfo *info)
{
k->cp15.c0_cachetype = 0xd172172;
k->cp15.c1_sys = 0x00000078;
+ k->jtag_id = ((uint64_t)k->cp15.c0_cpuid << 28) | 0x09265013;
set_class_feature(k, ARM_FEATURE_V5);
set_class_feature(k, ARM_FEATURE_XSCALE);
@@ -232,6 +233,7 @@ static void pxa270_class_init(ARMCPUClass *k, const ARMCPUInfo *info)
{
k->cp15.c0_cachetype = 0xd172172;
k->cp15.c1_sys = 0x00000078;
+ k->jtag_id = ((uint64_t)k->cp15.c0_cpuid << 28) | 0x09265013;
set_class_feature(k, ARM_FEATURE_V5);
set_class_feature(k, ARM_FEATURE_XSCALE);
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index e16befd..351b057 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -406,11 +406,6 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
#define ARM_CPUID_ARM926 0x41069265
#define ARM_CPUID_TI915T 0x54029152
#define ARM_CPUID_TI925T 0x54029252
-#define ARM_CPUID_PXA250 0x69052100
-#define ARM_CPUID_PXA255 0x69052d00
-#define ARM_CPUID_PXA260 0x69052903
-#define ARM_CPUID_PXA261 0x69052d05
-#define ARM_CPUID_PXA262 0x69052d06
#define ARM_CPUID_PXA270_A0 0x69054110
#define ARM_CPUID_PXA270_A1 0x69054111
#define ARM_CPUID_PXA270_B0 0x69054112
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 32319e4..bf28fea 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -76,20 +76,12 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c15_i_max = 0x000;
env->cp15.c15_i_min = 0xff0;
break;
- case ARM_CPUID_PXA250:
- case ARM_CPUID_PXA255:
- case ARM_CPUID_PXA260:
- case ARM_CPUID_PXA261:
- case ARM_CPUID_PXA262:
- /* JTAG_ID is ((id << 28) | 0x09265013) */
- break;
case ARM_CPUID_PXA270_A0:
case ARM_CPUID_PXA270_A1:
case ARM_CPUID_PXA270_B0:
case ARM_CPUID_PXA270_B1:
case ARM_CPUID_PXA270_C0:
case ARM_CPUID_PXA270_C5:
- /* JTAG_ID is ((id << 28) | 0x09265013) */
env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
break;
default:
--
1.7.7
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH RFC v3 14/21] target-arm: Move the PXA270's iwMMXt reset to pxa270_reset()
2012-02-03 2:59 [Qemu-devel] [PATCH RFC v3 00/21] Introduce QOM CPU and use it for ARM Andreas Färber
` (12 preceding siblings ...)
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 13/21] target-arm: Store JTAG_ID in ARMCPUClass Andreas Färber
@ 2012-02-03 2:59 ` Andreas Färber
2012-02-17 9:59 ` andrzej zaborowski
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 15/21] target-arm: Store VFP FPSID register in ARMCPUClass Andreas Färber
` (6 subsequent siblings)
20 siblings, 1 reply; 47+ messages in thread
From: Andreas Färber @ 2012-02-03 2:59 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Andreas Färber
No other emulated CPU uses this at this time.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Andrzej Zaborowski <balrogg@gmail.com>
---
target-arm/cpu.c | 14 ++++++++++++++
target-arm/cpu.h | 6 ------
target-arm/helper.c | 8 --------
3 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 7d4f0f6..bf4b272 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -229,8 +229,22 @@ static void pxa25x_class_init(ARMCPUClass *k, const ARMCPUInfo *info)
set_class_feature(k, ARM_FEATURE_XSCALE);
}
+static void pxa270_reset(CPU *c)
+{
+ ARMCPU *cpu = ARM_CPU(c);
+ CPUARMState *env = &cpu->env;
+
+ arm_cpu_reset(c);
+
+ env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
+}
+
static void pxa270_class_init(ARMCPUClass *k, const ARMCPUInfo *info)
{
+ CPUClass *cpu_class = CPU_CLASS(k);
+
+ cpu_class->reset = pxa270_reset;
+
k->cp15.c0_cachetype = 0xd172172;
k->cp15.c1_sys = 0x00000078;
k->jtag_id = ((uint64_t)k->cp15.c0_cpuid << 28) | 0x09265013;
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 351b057..32aaa4e 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -406,12 +406,6 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
#define ARM_CPUID_ARM926 0x41069265
#define ARM_CPUID_TI915T 0x54029152
#define ARM_CPUID_TI925T 0x54029252
-#define ARM_CPUID_PXA270_A0 0x69054110
-#define ARM_CPUID_PXA270_A1 0x69054111
-#define ARM_CPUID_PXA270_B0 0x69054112
-#define ARM_CPUID_PXA270_B1 0x69054113
-#define ARM_CPUID_PXA270_C0 0x69054114
-#define ARM_CPUID_PXA270_C5 0x69054117
#define ARM_CPUID_ARM1136 0x4117b363
#define ARM_CPUID_ARM1136_R2 0x4107b362
#define ARM_CPUID_ARM1176 0x410fb767
diff --git a/target-arm/helper.c b/target-arm/helper.c
index bf28fea..4a531b8 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -76,14 +76,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c15_i_max = 0x000;
env->cp15.c15_i_min = 0xff0;
break;
- case ARM_CPUID_PXA270_A0:
- case ARM_CPUID_PXA270_A1:
- case ARM_CPUID_PXA270_B0:
- case ARM_CPUID_PXA270_B1:
- case ARM_CPUID_PXA270_C0:
- case ARM_CPUID_PXA270_C5:
- env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
- break;
default:
break;
}
--
1.7.7
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH RFC v3 15/21] target-arm: Store VFP FPSID register in ARMCPUClass
2012-02-03 2:59 [Qemu-devel] [PATCH RFC v3 00/21] Introduce QOM CPU and use it for ARM Andreas Färber
` (13 preceding siblings ...)
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 14/21] target-arm: Move the PXA270's iwMMXt reset to pxa270_reset() Andreas Färber
@ 2012-02-03 2:59 ` Andreas Färber
2012-02-07 17:44 ` Peter Maydell
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 16/21] target-arm: Store VFP MVFR0 and MVFR1 " Andreas Färber
` (5 subsequent siblings)
20 siblings, 1 reply; 47+ messages in thread
From: Andreas Färber @ 2012-02-03 2:59 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Andreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/cpu-core.h | 3 +++
target-arm/cpu.c | 11 +++++++++++
target-arm/cpu.h | 1 -
target-arm/helper.c | 12 ------------
4 files changed, 14 insertions(+), 13 deletions(-)
diff --git a/target-arm/cpu-core.h b/target-arm/cpu-core.h
index eac1a03..0b2eb0a 100644
--- a/target-arm/cpu-core.h
+++ b/target-arm/cpu-core.h
@@ -48,6 +48,9 @@ typedef struct ARMCPUClass {
uint32_t c0_c2[8];
uint32_t c1_sys;
} cp15;
+ struct {
+ uint32_t fpsid;
+ } vfp;
uint64_t jtag_id;
/* Internal CPU feature flags. */
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index bf4b272..7893fa8 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -52,6 +52,7 @@ static void arm_cpu_reset(CPU *c)
/* Genuine reset */
env->cp15.c1_sys = cpu_class->cp15.c1_sys;
+ env->vfp.xregs[ARM_VFP_FPSID] = cpu_class->vfp.fpsid;
#if defined(CONFIG_USER_ONLY)
env->uncached_cpsr = ARM_CPU_MODE_USR;
@@ -172,6 +173,7 @@ typedef struct ARMCPUInfo {
uint32_t cp15_c0_c1[8];
uint32_t cp15_c0_c2[8];
uint32_t cp15_c1_sys;
+ uint32_t vfp_fpsid;
uint32_t features;
void (*class_init)(ARMCPUClass *klass, const struct ARMCPUInfo *info);
} ARMCPUInfo;
@@ -260,6 +262,7 @@ static const ARMCPUInfo arm_cpus[] = {
.id = 0x41069265,
.cp15_c0_cachetype = 0x1dd20d2,
.cp15_c1_sys = 0x00090078,
+ .vfp_fpsid = 0x41011090,
.features = ARM_FEATURE(V5) |
ARM_FEATURE(VFP),
},
@@ -276,6 +279,7 @@ static const ARMCPUInfo arm_cpus[] = {
.id = 0x4106a262,
.cp15_c0_cachetype = 0x1dd20d2,
.cp15_c1_sys = 0x00090078,
+ .vfp_fpsid = 0x410110a0,
.features = ARM_FEATURE(V5) |
ARM_FEATURE(VFP) |
ARM_FEATURE(AUXCR),
@@ -302,6 +306,7 @@ static const ARMCPUInfo arm_cpus[] = {
0x141, 0, 0, 0
},
.cp15_c1_sys = 0x00050078,
+ .vfp_fpsid = 0x410120b4,
.features = ARM_FEATURE(V6) |
ARM_FEATURE(VFP),
},
@@ -318,6 +323,7 @@ static const ARMCPUInfo arm_cpus[] = {
0x01141, 0, 0, 0
},
.cp15_c1_sys = 0x00050078,
+ .vfp_fpsid = 0x410120b5,
.features = ARM_FEATURE(V6K) |
ARM_FEATURE(VFP) |
ARM_FEATURE(VAPA),
@@ -334,6 +340,7 @@ static const ARMCPUInfo arm_cpus[] = {
0x00100011, 0x12002111, 0x11221011, 0x01102131,
0x141, 0, 0, 0
},
+ .vfp_fpsid = 0x410120b4,
.features = ARM_FEATURE(V6K) |
ARM_FEATURE(VFP) |
ARM_FEATURE(VAPA),
@@ -357,6 +364,7 @@ static const ARMCPUInfo arm_cpus[] = {
0x00111142, 0, 0, 0
},
.cp15_c1_sys = 0x00c50078,
+ .vfp_fpsid = 0x410330c0,
.features = ARM_FEATURE(V7) |
ARM_FEATURE(VFP3) |
ARM_FEATURE(NEON) |
@@ -375,6 +383,7 @@ static const ARMCPUInfo arm_cpus[] = {
0x00111142, 0, 0, 0
},
.cp15_c1_sys = 0x00c50078,
+ .vfp_fpsid = 0x41034000, /* Guess */
.features = ARM_FEATURE(V7) |
ARM_FEATURE(VFP3) |
ARM_FEATURE(VFP_FP16) |
@@ -399,6 +408,7 @@ static const ARMCPUInfo arm_cpus[] = {
0x10011142, 0, 0, 0
},
.cp15_c1_sys = 0x00c50078,
+ .vfp_fpsid = 0x410430f0,
.features = ARM_FEATURE(V7) |
ARM_FEATURE(VFP4) |
ARM_FEATURE(VFP_FP16) |
@@ -522,6 +532,7 @@ static void arm_cpu_class_init(ObjectClass *klass, void *data)
memcpy(k->cp15.c0_c1, info->cp15_c0_c1, 8 * sizeof(uint32_t));
memcpy(k->cp15.c0_c2, info->cp15_c0_c2, 8 * sizeof(uint32_t));
k->cp15.c1_sys = info->cp15_c1_sys;
+ k->vfp.fpsid = info->vfp_fpsid;
k->features = info->features;
if (info->class_init != NULL) {
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 32aaa4e..a1630b0 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -403,7 +403,6 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
#define ARM_CPUID(env) (env->cp15.c0_cpuid)
#define ARM_CPUID_ARM1026 0x4106a262
-#define ARM_CPUID_ARM926 0x41069265
#define ARM_CPUID_TI915T 0x54029152
#define ARM_CPUID_TI925T 0x54029252
#define ARM_CPUID_ARM1136 0x4117b363
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 4a531b8..466519a 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -13,12 +13,6 @@
static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
{
switch (id) {
- case ARM_CPUID_ARM926:
- env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090;
- break;
- case ARM_CPUID_ARM1026:
- env->vfp.xregs[ARM_VFP_FPSID] = 0x410110a0;
- break;
case ARM_CPUID_ARM1136:
/* This is the 1136 r1, which is a v6K core */
/* Fall through */
@@ -31,22 +25,18 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
* for 1136_r2 (in particular r0p2 does not actually implement most
* of the ID registers).
*/
- env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
break;
case ARM_CPUID_ARM1176:
- env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b5;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
break;
case ARM_CPUID_ARM11MPCORE:
- env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
break;
case ARM_CPUID_CORTEXA8:
- env->vfp.xregs[ARM_VFP_FPSID] = 0x410330c0;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100;
env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3;
@@ -55,7 +45,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */
break;
case ARM_CPUID_CORTEXA9:
- env->vfp.xregs[ARM_VFP_FPSID] = 0x41034000; /* Guess */
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x01111111;
env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3;
@@ -63,7 +52,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */
break;
case ARM_CPUID_CORTEXA15:
- env->vfp.xregs[ARM_VFP_FPSID] = 0x410430f0;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x10110222;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x11111111;
env->cp15.c0_clid = 0x0a200023;
--
1.7.7
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH RFC v3 16/21] target-arm: Store VFP MVFR0 and MVFR1 in ARMCPUClass
2012-02-03 2:59 [Qemu-devel] [PATCH RFC v3 00/21] Introduce QOM CPU and use it for ARM Andreas Färber
` (14 preceding siblings ...)
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 15/21] target-arm: Store VFP FPSID register in ARMCPUClass Andreas Färber
@ 2012-02-03 2:59 ` Andreas Färber
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 17/21] target-arm: Store CLIDR " Andreas Färber
` (4 subsequent siblings)
20 siblings, 0 replies; 47+ messages in thread
From: Andreas Färber @ 2012-02-03 2:59 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Andreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/cpu-core.h | 1 +
target-arm/cpu.c | 11 +++++++++++
target-arm/helper.c | 29 -----------------------------
3 files changed, 12 insertions(+), 29 deletions(-)
diff --git a/target-arm/cpu-core.h b/target-arm/cpu-core.h
index 0b2eb0a..53fac1a 100644
--- a/target-arm/cpu-core.h
+++ b/target-arm/cpu-core.h
@@ -50,6 +50,7 @@ typedef struct ARMCPUClass {
} cp15;
struct {
uint32_t fpsid;
+ uint32_t mvfr[2];
} vfp;
uint64_t jtag_id;
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 7893fa8..d004cfd 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -49,6 +49,8 @@ static void arm_cpu_reset(CPU *c)
env->cp15.c0_cachetype = cpu_class->cp15.c0_cachetype;
memcpy(env->cp15.c0_c1, cpu_class->cp15.c0_c1, 8 * sizeof(uint32_t));
memcpy(env->cp15.c0_c2, cpu_class->cp15.c0_c2, 8 * sizeof(uint32_t));
+ env->vfp.xregs[ARM_VFP_MVFR0] = cpu_class->vfp.mvfr[0];
+ env->vfp.xregs[ARM_VFP_MVFR1] = cpu_class->vfp.mvfr[1];
/* Genuine reset */
env->cp15.c1_sys = cpu_class->cp15.c1_sys;
@@ -174,6 +176,7 @@ typedef struct ARMCPUInfo {
uint32_t cp15_c0_c2[8];
uint32_t cp15_c1_sys;
uint32_t vfp_fpsid;
+ uint32_t vfp_mvfr[2];
uint32_t features;
void (*class_init)(ARMCPUClass *klass, const struct ARMCPUInfo *info);
} ARMCPUInfo;
@@ -307,6 +310,7 @@ static const ARMCPUInfo arm_cpus[] = {
},
.cp15_c1_sys = 0x00050078,
.vfp_fpsid = 0x410120b4,
+ .vfp_mvfr = { 0x11111111, 0x00000000 },
.features = ARM_FEATURE(V6) |
ARM_FEATURE(VFP),
},
@@ -324,6 +328,7 @@ static const ARMCPUInfo arm_cpus[] = {
},
.cp15_c1_sys = 0x00050078,
.vfp_fpsid = 0x410120b5,
+ .vfp_mvfr = { 0x11111111, 0x00000000 },
.features = ARM_FEATURE(V6K) |
ARM_FEATURE(VFP) |
ARM_FEATURE(VAPA),
@@ -341,6 +346,7 @@ static const ARMCPUInfo arm_cpus[] = {
0x141, 0, 0, 0
},
.vfp_fpsid = 0x410120b4,
+ .vfp_mvfr = { 0x11111111, 0x00000000 },
.features = ARM_FEATURE(V6K) |
ARM_FEATURE(VFP) |
ARM_FEATURE(VAPA),
@@ -365,6 +371,7 @@ static const ARMCPUInfo arm_cpus[] = {
},
.cp15_c1_sys = 0x00c50078,
.vfp_fpsid = 0x410330c0,
+ .vfp_mvfr = { 0x11110222, 0x00011100 },
.features = ARM_FEATURE(V7) |
ARM_FEATURE(VFP3) |
ARM_FEATURE(NEON) |
@@ -384,6 +391,7 @@ static const ARMCPUInfo arm_cpus[] = {
},
.cp15_c1_sys = 0x00c50078,
.vfp_fpsid = 0x41034000, /* Guess */
+ .vfp_mvfr = { 0x11110222, 0x01111111 },
.features = ARM_FEATURE(V7) |
ARM_FEATURE(VFP3) |
ARM_FEATURE(VFP_FP16) |
@@ -409,6 +417,7 @@ static const ARMCPUInfo arm_cpus[] = {
},
.cp15_c1_sys = 0x00c50078,
.vfp_fpsid = 0x410430f0,
+ .vfp_mvfr = { 0x10110222, 0x11111111 },
.features = ARM_FEATURE(V7) |
ARM_FEATURE(VFP4) |
ARM_FEATURE(VFP_FP16) |
@@ -533,6 +542,8 @@ static void arm_cpu_class_init(ObjectClass *klass, void *data)
memcpy(k->cp15.c0_c2, info->cp15_c0_c2, 8 * sizeof(uint32_t));
k->cp15.c1_sys = info->cp15_c1_sys;
k->vfp.fpsid = info->vfp_fpsid;
+ k->vfp.mvfr[0] = info->vfp_mvfr[0];
+ k->vfp.mvfr[1] = info->vfp_mvfr[1];
k->features = info->features;
if (info->class_init != NULL) {
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 466519a..4ec375c 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -13,47 +13,18 @@
static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
{
switch (id) {
- case ARM_CPUID_ARM1136:
- /* This is the 1136 r1, which is a v6K core */
- /* Fall through */
- case ARM_CPUID_ARM1136_R2:
- /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
- * older core than plain "arm1136". In particular this does not
- * have the v6K features.
- */
- /* These ID register values are correct for 1136 but may be wrong
- * for 1136_r2 (in particular r0p2 does not actually implement most
- * of the ID registers).
- */
- env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
- env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
- break;
- case ARM_CPUID_ARM1176:
- env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
- env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
- break;
- case ARM_CPUID_ARM11MPCORE:
- env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
- env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
- break;
case ARM_CPUID_CORTEXA8:
- env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
- env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100;
env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3;
env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */
env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */
env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */
break;
case ARM_CPUID_CORTEXA9:
- env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
- env->vfp.xregs[ARM_VFP_MVFR1] = 0x01111111;
env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3;
env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */
env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */
break;
case ARM_CPUID_CORTEXA15:
- env->vfp.xregs[ARM_VFP_MVFR0] = 0x10110222;
- env->vfp.xregs[ARM_VFP_MVFR1] = 0x11111111;
env->cp15.c0_clid = 0x0a200023;
env->cp15.c0_ccsid[0] = 0x701fe00a; /* 32K L1 dcache */
env->cp15.c0_ccsid[1] = 0x201fe00a; /* 32K L1 icache */
--
1.7.7
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH RFC v3 17/21] target-arm: Store CLIDR in ARMCPUClass
2012-02-03 2:59 [Qemu-devel] [PATCH RFC v3 00/21] Introduce QOM CPU and use it for ARM Andreas Färber
` (15 preceding siblings ...)
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 16/21] target-arm: Store VFP MVFR0 and MVFR1 " Andreas Färber
@ 2012-02-03 2:59 ` Andreas Färber
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 18/21] target-arm: Store CCSIDRs " Andreas Färber
` (3 subsequent siblings)
20 siblings, 0 replies; 47+ messages in thread
From: Andreas Färber @ 2012-02-03 2:59 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Andreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/cpu-core.h | 1 +
target-arm/cpu.c | 6 ++++++
target-arm/helper.c | 3 ---
3 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/target-arm/cpu-core.h b/target-arm/cpu-core.h
index 53fac1a..0ed92ce 100644
--- a/target-arm/cpu-core.h
+++ b/target-arm/cpu-core.h
@@ -44,6 +44,7 @@ typedef struct ARMCPUClass {
struct {
uint32_t c0_cpuid;
uint32_t c0_cachetype;
+ uint32_t c0_clid;
uint32_t c0_c1[8];
uint32_t c0_c2[8];
uint32_t c1_sys;
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index d004cfd..8333ca4 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -47,6 +47,7 @@ static void arm_cpu_reset(CPU *c)
/* TODO Move these into arm_cpu_initfn() once no longer zeroed above. */
env->cp15.c0_cachetype = cpu_class->cp15.c0_cachetype;
+ env->cp15.c0_clid = cpu_class->cp15.c0_clid;
memcpy(env->cp15.c0_c1, cpu_class->cp15.c0_c1, 8 * sizeof(uint32_t));
memcpy(env->cp15.c0_c2, cpu_class->cp15.c0_c2, 8 * sizeof(uint32_t));
env->vfp.xregs[ARM_VFP_MVFR0] = cpu_class->vfp.mvfr[0];
@@ -172,6 +173,7 @@ typedef struct ARMCPUInfo {
const char *name;
uint32_t id;
uint32_t cp15_c0_cachetype;
+ uint32_t cp15_c0_clid;
uint32_t cp15_c0_c1[8];
uint32_t cp15_c0_c2[8];
uint32_t cp15_c1_sys;
@@ -361,6 +363,7 @@ static const ARMCPUInfo arm_cpus[] = {
.name = "cortex-a8",
.id = 0x410fc080,
.cp15_c0_cachetype = 0x82048004,
+ .cp15_c0_clid = (1 << 27) | (2 << 24) | 3,
.cp15_c0_c1 = {
0x1031, 0x11, 0x400, 0,
0x31100003, 0x20000000, 0x01202000, 0x11
@@ -381,6 +384,7 @@ static const ARMCPUInfo arm_cpus[] = {
.name = "cortex-a9",
.id = 0x410fc090,
.cp15_c0_cachetype = 0x80038003,
+ .cp15_c0_clid = (1 << 27) | (1 << 24) | 3,
.cp15_c0_c1 = {
0x1031, 0x11, 0x000, 0,
0x00100103, 0x20000000, 0x01230000, 0x00002111
@@ -407,6 +411,7 @@ static const ARMCPUInfo arm_cpus[] = {
.name = "cortex-a15",
.id = 0x412fc0f1,
.cp15_c0_cachetype = 0x8444c004,
+ .cp15_c0_clid = 0x0a200023,
.cp15_c0_c1 = {
0x00001131, 0x00011011, 0x02010555, 0x00000000,
0x10201105, 0x20000000, 0x01240000, 0x02102211
@@ -538,6 +543,7 @@ static void arm_cpu_class_init(ObjectClass *klass, void *data)
k->cp15.c0_cpuid = info->id;
k->cp15.c0_cachetype = info->cp15_c0_cachetype;
+ k->cp15.c0_clid = info->cp15_c0_clid;
memcpy(k->cp15.c0_c1, info->cp15_c0_c1, 8 * sizeof(uint32_t));
memcpy(k->cp15.c0_c2, info->cp15_c0_c2, 8 * sizeof(uint32_t));
k->cp15.c1_sys = info->cp15_c1_sys;
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 4ec375c..6f2c9a0 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -14,18 +14,15 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
{
switch (id) {
case ARM_CPUID_CORTEXA8:
- env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3;
env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */
env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */
env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */
break;
case ARM_CPUID_CORTEXA9:
- env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3;
env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */
env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */
break;
case ARM_CPUID_CORTEXA15:
- env->cp15.c0_clid = 0x0a200023;
env->cp15.c0_ccsid[0] = 0x701fe00a; /* 32K L1 dcache */
env->cp15.c0_ccsid[1] = 0x201fe00a; /* 32K L1 icache */
env->cp15.c0_ccsid[2] = 0x711fe07a; /* 4096K L2 unified cache */
--
1.7.7
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH RFC v3 18/21] target-arm: Store CCSIDRs in ARMCPUClass
2012-02-03 2:59 [Qemu-devel] [PATCH RFC v3 00/21] Introduce QOM CPU and use it for ARM Andreas Färber
` (16 preceding siblings ...)
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 17/21] target-arm: Store CLIDR " Andreas Färber
@ 2012-02-03 2:59 ` Andreas Färber
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 19/21] target-arm: Kill off cpu_reset_model_id() Andreas Färber
` (2 subsequent siblings)
20 siblings, 0 replies; 47+ messages in thread
From: Andreas Färber @ 2012-02-03 2:59 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Andreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/cpu-core.h | 1 +
target-arm/cpu.c | 18 ++++++++++++++++++
target-arm/helper.c | 14 --------------
3 files changed, 19 insertions(+), 14 deletions(-)
diff --git a/target-arm/cpu-core.h b/target-arm/cpu-core.h
index 0ed92ce..a58e62b 100644
--- a/target-arm/cpu-core.h
+++ b/target-arm/cpu-core.h
@@ -44,6 +44,7 @@ typedef struct ARMCPUClass {
struct {
uint32_t c0_cpuid;
uint32_t c0_cachetype;
+ uint32_t c0_ccsid[16];
uint32_t c0_clid;
uint32_t c0_c1[8];
uint32_t c0_c2[8];
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 8333ca4..8186a96 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -47,6 +47,8 @@ static void arm_cpu_reset(CPU *c)
/* TODO Move these into arm_cpu_initfn() once no longer zeroed above. */
env->cp15.c0_cachetype = cpu_class->cp15.c0_cachetype;
+ memcpy(env->cp15.c0_ccsid, cpu_class->cp15.c0_ccsid,
+ 16 * sizeof(uint32_t));
env->cp15.c0_clid = cpu_class->cp15.c0_clid;
memcpy(env->cp15.c0_c1, cpu_class->cp15.c0_c1, 8 * sizeof(uint32_t));
memcpy(env->cp15.c0_c2, cpu_class->cp15.c0_c2, 8 * sizeof(uint32_t));
@@ -173,6 +175,7 @@ typedef struct ARMCPUInfo {
const char *name;
uint32_t id;
uint32_t cp15_c0_cachetype;
+ uint32_t cp15_c0_ccsid[16];
uint32_t cp15_c0_clid;
uint32_t cp15_c0_c1[8];
uint32_t cp15_c0_c2[8];
@@ -363,6 +366,11 @@ static const ARMCPUInfo arm_cpus[] = {
.name = "cortex-a8",
.id = 0x410fc080,
.cp15_c0_cachetype = 0x82048004,
+ .cp15_c0_ccsid = {
+ 0xe007e01a, /* 16k L1 dcache. */
+ 0x2007e01a, /* 16k L1 icache. */
+ 0xf0000000, /* No L2 icache. */
+ },
.cp15_c0_clid = (1 << 27) | (2 << 24) | 3,
.cp15_c0_c1 = {
0x1031, 0x11, 0x400, 0,
@@ -384,6 +392,10 @@ static const ARMCPUInfo arm_cpus[] = {
.name = "cortex-a9",
.id = 0x410fc090,
.cp15_c0_cachetype = 0x80038003,
+ .cp15_c0_ccsid = {
+ 0xe00fe015, /* 16k L1 dcache. */
+ 0x200fe015, /* 16k L1 icache. */
+ },
.cp15_c0_clid = (1 << 27) | (1 << 24) | 3,
.cp15_c0_c1 = {
0x1031, 0x11, 0x000, 0,
@@ -411,6 +423,11 @@ static const ARMCPUInfo arm_cpus[] = {
.name = "cortex-a15",
.id = 0x412fc0f1,
.cp15_c0_cachetype = 0x8444c004,
+ .cp15_c0_ccsid = {
+ 0x701fe00a, /* 32K L1 dcache */
+ 0x201fe00a, /* 32K L1 icache */
+ 0x711fe07a, /* 4096K L2 unified cache */
+ },
.cp15_c0_clid = 0x0a200023,
.cp15_c0_c1 = {
0x00001131, 0x00011011, 0x02010555, 0x00000000,
@@ -543,6 +560,7 @@ static void arm_cpu_class_init(ObjectClass *klass, void *data)
k->cp15.c0_cpuid = info->id;
k->cp15.c0_cachetype = info->cp15_c0_cachetype;
+ memcpy(k->cp15.c0_ccsid, info->cp15_c0_ccsid, 16 * sizeof(uint32_t));
k->cp15.c0_clid = info->cp15_c0_clid;
memcpy(k->cp15.c0_c1, info->cp15_c0_c1, 8 * sizeof(uint32_t));
memcpy(k->cp15.c0_c2, info->cp15_c0_c2, 8 * sizeof(uint32_t));
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 6f2c9a0..6ecae15 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -13,20 +13,6 @@
static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
{
switch (id) {
- case ARM_CPUID_CORTEXA8:
- env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */
- env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */
- env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */
- break;
- case ARM_CPUID_CORTEXA9:
- env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */
- env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */
- break;
- case ARM_CPUID_CORTEXA15:
- env->cp15.c0_ccsid[0] = 0x701fe00a; /* 32K L1 dcache */
- env->cp15.c0_ccsid[1] = 0x201fe00a; /* 32K L1 icache */
- env->cp15.c0_ccsid[2] = 0x711fe07a; /* 4096K L2 unified cache */
- break;
case ARM_CPUID_TI915T:
case ARM_CPUID_TI925T:
env->cp15.c15_i_max = 0x000;
--
1.7.7
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH RFC v3 19/21] target-arm: Kill off cpu_reset_model_id()
2012-02-03 2:59 [Qemu-devel] [PATCH RFC v3 00/21] Introduce QOM CPU and use it for ARM Andreas Färber
` (17 preceding siblings ...)
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 18/21] target-arm: Store CCSIDRs " Andreas Färber
@ 2012-02-03 2:59 ` Andreas Färber
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 20/21] target-arm: Prepare halted property for CPU Andreas Färber
2012-02-03 2:59 ` [Qemu-devel] [FYI v3 21/21] target-arm: Just for testing! Andreas Färber
20 siblings, 0 replies; 47+ messages in thread
From: Andreas Färber @ 2012-02-03 2:59 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Andreas Färber
Move last remaining TI925T bits to ti925t_reset().
This reduces cpu_reset() to triviality and lets us reset the CPU
directly from arm_cpu_initfn().
Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/cpu.c | 4 ++++
target-arm/helper.c | 20 --------------------
2 files changed, 4 insertions(+), 20 deletions(-)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 8186a96..74f4e9b 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -213,6 +213,8 @@ static void ti925t_reset(CPU *c)
arm_cpu_reset(c);
env->cp15.c0_cpuid = ARM_CPUID_TI925T; /* Depends on wiring. */
+ env->cp15.c15_i_max = 0x000;
+ env->cp15.c15_i_min = 0xff0;
}
static void ti925t_class_init(ARMCPUClass *klass, const ARMCPUInfo *info)
@@ -548,6 +550,8 @@ static void arm_cpu_initfn(Object *obj)
cpu->env.cpu_model_str = object_get_typename(obj);
cpu->env.cp15.c0_cpuid = cpu_class->cp15.c0_cpuid;
+
+ cpu_do_reset(CPU(cpu));
}
static void arm_cpu_class_init(ObjectClass *klass, void *data)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 6ecae15..cb98661 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -10,28 +10,9 @@
#include "sysemu.h"
#include "cpu-core.h"
-static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
-{
- switch (id) {
- case ARM_CPUID_TI915T:
- case ARM_CPUID_TI925T:
- env->cp15.c15_i_max = 0x000;
- env->cp15.c15_i_min = 0xff0;
- break;
- default:
- break;
- }
-}
-
void cpu_reset(CPUARMState *env)
{
- uint32_t id;
-
cpu_do_reset(CPU(ENV_GET_OBJECT(env)));
-
- id = env->cp15.c0_cpuid;
- if (id)
- cpu_reset_model_id(env, id);
}
static int vfp_gdb_get_reg(CPUState *env, uint8_t *buf, int reg)
@@ -110,7 +91,6 @@ CPUARMState *cpu_arm_init(const char *cpu_model)
arm_translate_init();
}
- cpu_reset(env);
if (arm_feature(env, ARM_FEATURE_NEON)) {
gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
51, "arm-neon.xml", 0);
--
1.7.7
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH RFC v3 20/21] target-arm: Prepare halted property for CPU
2012-02-03 2:59 [Qemu-devel] [PATCH RFC v3 00/21] Introduce QOM CPU and use it for ARM Andreas Färber
` (18 preceding siblings ...)
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 19/21] target-arm: Kill off cpu_reset_model_id() Andreas Färber
@ 2012-02-03 2:59 ` Andreas Färber
2012-02-03 2:59 ` [Qemu-devel] [FYI v3 21/21] target-arm: Just for testing! Andreas Färber
20 siblings, 0 replies; 47+ messages in thread
From: Andreas Färber @ 2012-02-03 2:59 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Andreas Färber
Read-only and ARM-specific for now.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Anthony Liguori <anthony@codemonkey.ws>
---
target-arm/cpu.c | 12 ++++++++++++
1 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 74f4e9b..4dfec15 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -20,6 +20,7 @@
#include "cpu-core.h"
#include "qemu-common.h"
+#include "qapi/qapi-visit-core.h"
#if !defined(CONFIG_USER_ONLY)
#include "hw/loader.h"
#endif
@@ -538,6 +539,14 @@ static const ARMCPUInfo arm_cpus[] = {
},
};
+static void arm_cpu_get_halted(Object *obj, Visitor *v, void *opaque,
+ const char *name, Error **errp)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ bool halted = cpu->env.halted != 0;
+ visit_type_bool(v, &halted, name, errp);
+}
+
static void arm_cpu_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
@@ -552,6 +561,9 @@ static void arm_cpu_initfn(Object *obj)
cpu->env.cp15.c0_cpuid = cpu_class->cp15.c0_cpuid;
cpu_do_reset(CPU(cpu));
+
+ object_property_add(obj, "halted", "boolean",
+ arm_cpu_get_halted, NULL, NULL, NULL, NULL);
}
static void arm_cpu_class_init(ObjectClass *klass, void *data)
--
1.7.7
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [FYI v3 21/21] target-arm: Just for testing!
2012-02-03 2:59 [Qemu-devel] [PATCH RFC v3 00/21] Introduce QOM CPU and use it for ARM Andreas Färber
` (19 preceding siblings ...)
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 20/21] target-arm: Prepare halted property for CPU Andreas Färber
@ 2012-02-03 2:59 ` Andreas Färber
20 siblings, 0 replies; 47+ messages in thread
From: Andreas Färber @ 2012-02-03 2:59 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Add the CPU as child<> of / so that it can be inspected with qom-get.
---
target-arm/cpu.c | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 4dfec15..ad8e317 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -564,6 +564,8 @@ static void arm_cpu_initfn(Object *obj)
object_property_add(obj, "halted", "boolean",
arm_cpu_get_halted, NULL, NULL, NULL, NULL);
+
+ object_property_add_child(object_get_root(), "cpu", obj, NULL); /* XXX */
}
static void arm_cpu_class_init(ObjectClass *klass, void *data)
--
1.7.7
^ permalink raw reply related [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH v3 01/21] qom: Register QOM infrastructure early
2012-02-03 2:59 ` [Qemu-devel] [PATCH v3 01/21] qom: Register QOM infrastructure early Andreas Färber
@ 2012-02-06 19:14 ` Anthony Liguori
0 siblings, 0 replies; 47+ messages in thread
From: Anthony Liguori @ 2012-02-06 19:14 UTC (permalink / raw)
To: Andreas Färber; +Cc: qemu-devel
On 02/02/2012 08:59 PM, Andreas Färber wrote:
> QOM TYPE_INTERFACE was registered with device_init(), whose
> constructors are executed rather late in vl.c's main().
>
> Rename the module init type from DEVICE to QOM and call it very early
> so that QOM can safely be used for machines and CPUs.
>
> device_init() is left for legacy types. New ones should use type_init().
There are no legacy device_init users. Everything can (and should) be converted
to type_init() and MODULE_INIT_QOM can be invoked very early.
Regards,
Anthony Liguori
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v3 02/21] qom: Add QOM support to user emulators
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 02/21] qom: Add QOM support to user emulators Andreas Färber
@ 2012-02-06 19:16 ` Anthony Liguori
2012-02-06 23:23 ` Andreas Färber
2012-02-07 17:25 ` Peter Maydell
0 siblings, 2 replies; 47+ messages in thread
From: Anthony Liguori @ 2012-02-06 19:16 UTC (permalink / raw)
To: Andreas Färber; +Cc: qemu-devel
On 02/02/2012 08:59 PM, Andreas Färber wrote:
> Link the Object base class and the module infrastructure for class
> registration. Call QOM module init.
>
> Signed-off-by: Andreas Färber<afaerber@suse.de>
> Cc: Anthony Liguori<anthony@codemonkey.ws>
If we're going to go down this road, then I have a hard requirement. We need to
build the common infrastructure only once.
Otherwise build times are going to explode and we'll end up with
CONFIG_USER_ONLY #defines all over the place.
Regards,
Anthony Liguori
> ---
> Makefile.objs | 6 ++++++
> Makefile.user | 1 +
> bsd-user/main.c | 2 ++
> configure | 2 ++
> darwin-user/main.c | 3 +++
> linux-user/main.c | 2 ++
> qemu-user.c | 37 +++++++++++++++++++++++++++++++++++++
> 7 files changed, 53 insertions(+), 0 deletions(-)
> create mode 100644 qemu-user.c
>
> diff --git a/Makefile.objs b/Makefile.objs
> index ec35320..1155cc0 100644
> --- a/Makefile.objs
> +++ b/Makefile.objs
> @@ -182,7 +182,11 @@ user-obj-y =
> user-obj-y += envlist.o path.o
> user-obj-y += tcg-runtime.o host-utils.o
> user-obj-y += cutils.o cache-utils.o
> +user-obj-y += module.o
> +user-obj-y += qemu-user.o
> user-obj-y += $(trace-obj-y)
> +user-obj-y += $(qobject-obj-y)
> +user-obj-y += $(addprefix qom/, $(qom-y))
>
> ######################################################################
> # libhw
> @@ -421,6 +425,8 @@ qapi-obj-y = $(addprefix qapi/, $(qapi-nested-y))
> common-obj-y += qmp-marshal.o qapi-visit.o qapi-types.o $(qapi-obj-y)
> common-obj-y += qmp.o hmp.o
>
> +user-obj-y += $(qapi-obj-y)
> +
> ######################################################################
> # guest agent
>
> diff --git a/Makefile.user b/Makefile.user
> index 2b1e4d1..72d01c1 100644
> --- a/Makefile.user
> +++ b/Makefile.user
> @@ -9,6 +9,7 @@ include $(SRC_PATH)/rules.mak
> $(call set-vpath, $(SRC_PATH))
>
> QEMU_CFLAGS+=-I..
> +QEMU_CFLAGS+=-I$(SRC_PATH)/include
>
> include $(SRC_PATH)/Makefile.objs
>
> diff --git a/bsd-user/main.c b/bsd-user/main.c
> index cc7d4a3..cdb0d0a 100644
> --- a/bsd-user/main.c
> +++ b/bsd-user/main.c
> @@ -748,6 +748,8 @@ int main(int argc, char **argv)
> if (argc<= 1)
> usage();
>
> + module_call_init(MODULE_INIT_QOM);
> +
> if ((envlist = envlist_create()) == NULL) {
> (void) fprintf(stderr, "Unable to allocate envlist\n");
> exit(1);
> diff --git a/configure b/configure
> index 3b0b300..ee1140e 100755
> --- a/configure
> +++ b/configure
> @@ -3849,6 +3849,8 @@ fi
> d=libuser
> mkdir -p $d
> mkdir -p $d/trace
> +mkdir -p $d/qapi
> +mkdir -p $d/qom
> symlink $source_path/Makefile.user $d/Makefile
>
> if test "$docs" = "yes" ; then
> diff --git a/darwin-user/main.c b/darwin-user/main.c
> index 9b57c20..e1519c7 100644
> --- a/darwin-user/main.c
> +++ b/darwin-user/main.c
> @@ -28,6 +28,7 @@
> #include<sys/mman.h>
>
> #include "qemu.h"
> +#include "qemu-common.h"
>
> #define DEBUG_LOGFILE "/tmp/qemu.log"
>
> @@ -749,6 +750,8 @@ int main(int argc, char **argv)
> if (argc<= 1)
> usage();
>
> + module_call_init(MODULE_INIT_QOM);
> +
> optind = 1;
> for(;;) {
> if (optind>= argc)
> diff --git a/linux-user/main.c b/linux-user/main.c
> index 64d2208..f55109c 100644
> --- a/linux-user/main.c
> +++ b/linux-user/main.c
> @@ -3278,6 +3278,8 @@ int main(int argc, char **argv, char **envp)
> int i;
> int ret;
>
> + module_call_init(MODULE_INIT_QOM);
> +
> qemu_cache_utils_init(envp);
>
> if ((envlist = envlist_create()) == NULL) {
> diff --git a/qemu-user.c b/qemu-user.c
> new file mode 100644
> index 0000000..51b2649
> --- /dev/null
> +++ b/qemu-user.c
> @@ -0,0 +1,37 @@
> +/*
> + * Stubs for QEMU user emulation
> + *
> + * Copyright (c) 2012 SUSE LINUX Products GmbH
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version 2
> + * of the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, see
> + *<http://www.gnu.org/licenses/old-licenses/gpl-2.0>
> + */
> +
> +#include "qemu-common.h"
> +#include "monitor.h"
> +
> +Monitor *cur_mon;
> +
> +int monitor_cur_is_qmp(void)
> +{
> + return 0;
> +}
> +
> +void monitor_vprintf(Monitor *mon, const char *fmt, va_list ap)
> +{
> +}
> +
> +void monitor_set_error(Monitor *mon, QError *qerror)
> +{
> +}
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v3 03/21] qom: Introduce CPU class
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 03/21] qom: Introduce CPU class Andreas Färber
@ 2012-02-06 19:24 ` Anthony Liguori
2012-02-06 20:01 ` Peter Maydell
2012-02-06 20:14 ` Andreas Färber
0 siblings, 2 replies; 47+ messages in thread
From: Anthony Liguori @ 2012-02-06 19:24 UTC (permalink / raw)
To: Andreas Färber; +Cc: Peter Maydell, qemu-devel, Paolo Bonzini
On 02/02/2012 08:59 PM, Andreas Färber wrote:
> It's abstract and derived directly from TYPE_OBJECT.
> Prepare a virtual reset method.
>
> Signed-off-by: Andreas Färber<afaerber@suse.de>
> Cc: Anthony Liguori<anthony@codemonkey.ws>
> Cc: Peter Maydell<peter.maydell@linaro.org>
> ---
> include/qemu/cpu.h | 73 ++++++++++++++++++++++++++++++++++++++++++++++++++++
> qom/Makefile | 1 +
> qom/cpu.c | 50 +++++++++++++++++++++++++++++++++++
> 3 files changed, 124 insertions(+), 0 deletions(-)
> create mode 100644 include/qemu/cpu.h
> create mode 100644 qom/cpu.c
>
> diff --git a/include/qemu/cpu.h b/include/qemu/cpu.h
> new file mode 100644
> index 0000000..22c7404
> --- /dev/null
> +++ b/include/qemu/cpu.h
> @@ -0,0 +1,73 @@
> +/*
> + * QEMU CPU model
> + *
> + * Copyright (c) 2012 SUSE LINUX Products GmbH
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version 2
> + * of the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, see
> + *<http://www.gnu.org/licenses/old-licenses/gpl-2.0>
> + */
> +#ifndef QEMU_CPU_H
> +#define QEMU_CPU_H
> +
> +#include "qemu/object.h"
> +
> +#define TYPE_CPU "cpu"
> +
> +#define CPU(obj) OBJECT_CHECK(CPU, (obj), TYPE_CPU)
> +#define CPU_CLASS(class) OBJECT_CLASS_CHECK(CPUClass, (class), TYPE_CPU)
> +#define CPU_GET_CLASS(obj) OBJECT_GET_CLASS(CPUClass, (obj), TYPE_CPU)
> +
> +typedef struct CPU CPU;
If this doesn't result in a build error, then C is a worse language than I
thought it was :-/
But we definitely shouldn't have a typename and macro name of the same thing and
expect it to work...
> +
> +/**
> + * CPUClass:
> + * @reset: Callback to reset the #CPU to its initial state.
> + *
> + * Represents a CPU family or model.
> + */
> +typedef struct CPUClass {
> + ObjectClass parent_class;
> +
> + void (*reset)(CPU *cpu);
> +} CPUClass;
> +
> +/**
> + * CPU:
> + *
> + * State of one CPU core or thread.
> + */
> +struct CPU {
> + Object parent_obj;
> +
> + /* TODO Move common fields from CPUState here. */
> +};
> +
> +
> +/* TODO Rename to cpu_reset once all CPUState is converted to QOM. */
> +/**
> + * cpu_do_reset:
> + * @cpu: The CPU whose state is to be reset.
> + */
> +void cpu_do_reset(CPU *cpu);
Better to sed-away the current cpu_reset() callers to cpu_reset_legacy() and
then make this cpu_reset(). Otherwise, you're introducing new code that has the
wrong usage which is never a good strategy.
> +
> +/**
> + * cpu_common_reset:
> + * @cpu: The CPU whose common state is to be reset.
> + *
> + * To be used by derived classes.
> + */
> +void cpu_common_reset(CPU *cpu);
Make this static, initialize reset = cpu_common_reset in cpu_class_initfn, then
in the derived class initfn, save the pointer to the parent reset function so it
can be called later.
At some point, I had an:
ObjectClass *object_get_super_class(Object *obj);
Such that you could do:
CPUClass *super = CPU_CLASS(object_get_super_class(OBJECT(s)));
super->reset(CPU(s));
But my fear was that the subtle semantic of the object representing the class of
your super class (which is different than a casted form of your class) would
lead to confusion.
Regards,
Anthony Liguori
> +
> +
> +#endif
> diff --git a/qom/Makefile b/qom/Makefile
> index f33f0be..0a1c8e0 100644
> --- a/qom/Makefile
> +++ b/qom/Makefile
> @@ -1 +1,2 @@
> qom-y = object.o container.o
> +qom-y += cpu.o
> diff --git a/qom/cpu.c b/qom/cpu.c
> new file mode 100644
> index 0000000..a60823f
> --- /dev/null
> +++ b/qom/cpu.c
> @@ -0,0 +1,50 @@
> +/*
> + * QEMU CPU model
> + *
> + * Copyright (c) 2012 SUSE LINUX Products GmbH
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version 2
> + * of the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, see
> + *<http://www.gnu.org/licenses/old-licenses/gpl-2.0>
> + */
> +
> +#include "qemu/cpu.h"
> +#include "qemu-common.h"
> +
> +void cpu_do_reset(CPU *cpu)
> +{
> + CPUClass *klass = CPU_GET_CLASS(cpu);
> +
> + if (klass->reset != NULL) {
> + (*klass->reset)(cpu);
> + }
> +}
> +
> +void cpu_common_reset(CPU *cpu)
> +{
> +}
> +
> +static TypeInfo cpu_type_info = {
> + .name = TYPE_CPU,
> + .parent = TYPE_OBJECT,
> + .instance_size = sizeof(CPU),
> + .abstract = true,
> + .class_size = sizeof(CPUClass),
> +};
> +
> +static void cpu_register_types(void)
> +{
> + type_register_static(&cpu_type_info);
> +}
> +
> +type_init(cpu_register_types)
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v3 03/21] qom: Introduce CPU class
2012-02-06 19:24 ` Anthony Liguori
@ 2012-02-06 20:01 ` Peter Maydell
2012-02-06 20:14 ` Andreas Färber
1 sibling, 0 replies; 47+ messages in thread
From: Peter Maydell @ 2012-02-06 20:01 UTC (permalink / raw)
To: Anthony Liguori; +Cc: Paolo Bonzini, Andreas Färber, qemu-devel
On 6 February 2012 19:24, Anthony Liguori <anthony@codemonkey.ws> wrote:
> On 02/02/2012 08:59 PM, Andreas Färber wrote:
>> +#define CPU(obj) OBJECT_CHECK(CPU, (obj), TYPE_CPU)
>> +#define CPU_CLASS(class) OBJECT_CLASS_CHECK(CPUClass, (class), TYPE_CPU)
>> +#define CPU_GET_CLASS(obj) OBJECT_GET_CLASS(CPUClass, (obj), TYPE_CPU)
>> +
>> +typedef struct CPU CPU;
>
> If this doesn't result in a build error, then C is a worse language than I
> thought it was :-/
>
> But we definitely shouldn't have a typename and macro name of the same thing
> and expect it to work...
The C standard says that function-like macros are only applied when
the function-like
macro name is followed by a '(' as the next preprocessing token, so this isn't
relying on any kind of gcc-specific behaviour.
Whether we *want* to do it is largely a style issue :-)
-- PMM
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v3 03/21] qom: Introduce CPU class
2012-02-06 19:24 ` Anthony Liguori
2012-02-06 20:01 ` Peter Maydell
@ 2012-02-06 20:14 ` Andreas Färber
2012-02-06 21:22 ` Anthony Liguori
1 sibling, 1 reply; 47+ messages in thread
From: Andreas Färber @ 2012-02-06 20:14 UTC (permalink / raw)
To: Anthony Liguori; +Cc: Peter Maydell, qemu-devel, Paolo Bonzini
Am 06.02.2012 20:24, schrieb Anthony Liguori:
> On 02/02/2012 08:59 PM, Andreas Färber wrote:
>> +/**
>> + * cpu_common_reset:
>> + * @cpu: The CPU whose common state is to be reset.
>> + *
>> + * To be used by derived classes.
>> + */
>> +void cpu_common_reset(CPU *cpu);
>
> Make this static, initialize reset = cpu_common_reset in
> cpu_class_initfn, then in the derived class initfn, save the pointer to
> the parent reset function so it can be called later.
I don't see how that would work. To initialize, e.g., the ARMCPUClass
with additional class fields I'm overriding the .class_init. So in order
to let CPUClass initialize the reset callback to its static one I'd need
to make CPU's class_init function non-static so that I can call that
from my derived class' class_init function, no?
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v3 03/21] qom: Introduce CPU class
2012-02-06 20:14 ` Andreas Färber
@ 2012-02-06 21:22 ` Anthony Liguori
0 siblings, 0 replies; 47+ messages in thread
From: Anthony Liguori @ 2012-02-06 21:22 UTC (permalink / raw)
To: Andreas Färber; +Cc: Peter Maydell, qemu-devel, Paolo Bonzini
On 02/06/2012 02:14 PM, Andreas Färber wrote:
> Am 06.02.2012 20:24, schrieb Anthony Liguori:
>> On 02/02/2012 08:59 PM, Andreas Färber wrote:
>>> +/**
>>> + * cpu_common_reset:
>>> + * @cpu: The CPU whose common state is to be reset.
>>> + *
>>> + * To be used by derived classes.
>>> + */
>>> +void cpu_common_reset(CPU *cpu);
>>
>> Make this static, initialize reset = cpu_common_reset in
>> cpu_class_initfn, then in the derived class initfn, save the pointer to
>> the parent reset function so it can be called later.
>
> I don't see how that would work. To initialize, e.g., the ARMCPUClass
> with additional class fields I'm overriding the .class_init.
You're not overriding the class_init. The class init for a type is called when
that class is initialized for the first time. See the documentation in object.h.
When class_init is called, the parent class type's class_init has already been
called and the default values are set. So:
static void arm_cpu_reset(CPUCommon *cpu)
{
ARMCPU *s = ARM_CPU(cpu);
ARMCPUClass *ac = ARM_CPU_GET_CLASS(s);
// do arm specific reset
// call super class reset
ac->super_reset(cpu);
}
static void arm_cpu_class_initfn(ObjectClass *klass, void *data)
{
CPUCommonClass *cc = CPU_COMMON_CLASS(klass);
ARMCPUClass *ac = ARM_CPU_CLASS(klass);
// cc->reset was set in CPUCommonClass's class_init
ac->super_reset = cc->reset;
cc->reset = arm_cpu_reset;
}
It's admittedly a little funky but this is the common idiom in gobject. I'm not
sure there's a better way.
Regards,
Anthony Liguori
So in order
> to let CPUClass initialize the reset callback to its static one I'd need
> to make CPU's class_init function non-static so that I can call that
> from my derived class' class_init function, no?
>
> Andreas
>
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v3 05/21] target-arm: Embed CPUARMState in QOM ARMCPU
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 05/21] target-arm: Embed CPUARMState in QOM ARMCPU Andreas Färber
@ 2012-02-06 23:00 ` Anthony Liguori
2012-02-06 23:05 ` Andreas Färber
0 siblings, 1 reply; 47+ messages in thread
From: Anthony Liguori @ 2012-02-06 23:00 UTC (permalink / raw)
To: Andreas Färber
Cc: Peter Maydell, Paul Brook, qemu-devel, Richard Henderson
On 02/02/2012 08:59 PM, Andreas Färber wrote:
> We g_malloc0()'ed CPUARMState ourself, and exec.c's cpu_copy() runs
> through cpu_init() as well, so we are at liberty to supply the CPUState
> any way we see fit. Having CPUARMState as field in the QOM CPU allows
> both to access env from an ARMCPU object and to access the QOM Object
> and its ObjectClass from an env pointer, in ARM code for now.
>
> The goal is to convert all CPUs to QOM and to use CPU objects in central
> places, especially once we have property support for Object.
> This will then allow to have TCG AREG0 point to target-specific fields
> where small immediate offsets are desired (as pointed out by rth) while
> allowing for common fields at known offsets from the base class.
>
> Having the CPUID in ARMCPUClass, we can set it from the instance_init
> function. Same for cpu_model_str, which is now the QOM class name.
>
> Make cpu_reset() call cpu_do_reset() and move most of its code to
> arm_cpu_reset().
>
> Signed-off-by: Andreas Färber<afaerber@suse.de>
> Cc: Anthony Liguori<anthony@codemonkey.ws>
> Cc: Paul Brook<paul@codesourcery.com>
> Cc: Peter Maydell<peter.maydell@linaro.org>
> Cc: Richard Henderson<rth@twiddle.net>
> ---
> target-arm/cpu-core.h | 11 +++++++
> target-arm/cpu.c | 78 +++++++++++++++++++++++++++++++++++++++++++++++++
> target-arm/helper.c | 71 ++++----------------------------------------
> 3 files changed, 96 insertions(+), 64 deletions(-)
>
> diff --git a/target-arm/cpu-core.h b/target-arm/cpu-core.h
> index 3e8f046..4ba5ee0 100644
> --- a/target-arm/cpu-core.h
> +++ b/target-arm/cpu-core.h
> @@ -21,6 +21,7 @@
> #define QEMU_ARM_CPU_CORE_H
>
> #include "qemu/cpu.h"
> +#include "cpu.h"
>
> #define TYPE_ARM_CPU "arm-cpu"
>
> @@ -53,7 +54,17 @@ typedef struct ARMCPUClass {
> typedef struct ARMCPU {
> /*< private>*/
> CPU parent_obj;
> +
> + /* TODO Inline this and split off common state */
> + CPUARMState env;
> } ARMCPU;
>
> +static inline Object *arm_env_get_object(CPUARMState *env)
> +{
> + return OBJECT((void *)(env) - offsetof(ARMCPU, env));
> +}
> +
> +#define ENV_GET_OBJECT(e) arm_env_get_object(e)
I'd prefer:
ARMCPU *arm_cpu_from_cpu_state(CPUState *env)
{
return ARM_CPU(container_of(env, ARMCPU, env));
}
Regards,
Anthony Liguori
>
> #endif
> diff --git a/target-arm/cpu.c b/target-arm/cpu.c
> index 9255a19..43231c9 100644
> --- a/target-arm/cpu.c
> +++ b/target-arm/cpu.c
> @@ -20,10 +20,75 @@
>
> #include "cpu-core.h"
> #include "qemu-common.h"
> +#if !defined(CONFIG_USER_ONLY)
> +#include "hw/loader.h"
> +#endif
>
> static void arm_cpu_reset(CPU *c)
> {
> + ARMCPU *cpu = ARM_CPU(c);
> + CPUARMState *env =&cpu->env;
> + uint32_t id;
> + uint32_t tmp;
> +
> + if (qemu_loglevel_mask(CPU_LOG_RESET)) {
> + qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
> + log_cpu_state(env, 0);
> + }
> +
> cpu_common_reset(c);
> +
> + id = env->cp15.c0_cpuid;
> + tmp = env->cp15.c15_config_base_address;
> + memset(env, 0, offsetof(CPUARMState, breakpoints));
> + env->cp15.c0_cpuid = id;
> + env->cp15.c15_config_base_address = tmp;
> +
> +#if defined(CONFIG_USER_ONLY)
> + env->uncached_cpsr = ARM_CPU_MODE_USR;
> + /* For user mode we must enable access to coprocessors */
> + env->vfp.xregs[ARM_VFP_FPEXC] = 1<< 30;
> + if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
> + env->cp15.c15_cpar = 3;
> + } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
> + env->cp15.c15_cpar = 1;
> + }
> +#else
> + /* SVC mode with interrupts disabled. */
> + env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
> + /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
> + clear at reset. Initial SP and PC are loaded from ROM. */
> + if (IS_M(env)) {
> + uint32_t pc;
> + uint8_t *rom;
> + env->uncached_cpsr&= ~CPSR_I;
> + rom = rom_ptr(0);
> + if (rom) {
> + /* We should really use ldl_phys here, in case the guest
> + modified flash and reset itself. However images
> + loaded via -kernel have not been copied yet, so load the
> + values directly from there. */
> + env->regs[13] = ldl_p(rom);
> + pc = ldl_p(rom + 4);
> + env->thumb = pc& 1;
> + env->regs[15] = pc& ~1;
> + }
> + }
> + env->vfp.xregs[ARM_VFP_FPEXC] = 0;
> + env->cp15.c2_base_mask = 0xffffc000u;
> + /* v7 performance monitor control register: same implementor
> + * field as main ID register, and we implement no event counters.
> + */
> + env->cp15.c9_pmcr = (id& 0xff000000);
> +#endif
> + set_flush_to_zero(1,&env->vfp.standard_fp_status);
> + set_flush_inputs_to_zero(1,&env->vfp.standard_fp_status);
> + set_default_nan_mode(1,&env->vfp.standard_fp_status);
> + set_float_detect_tininess(float_tininess_before_rounding,
> +&env->vfp.fp_status);
> + set_float_detect_tininess(float_tininess_before_rounding,
> +&env->vfp.standard_fp_status);
> + tlb_flush(env, 1);
> }
>
> /* CPU models */
> @@ -144,6 +209,18 @@ static const ARMCPUInfo arm_cpus[] = {
> },
> };
>
> +static void arm_cpu_initfn(Object *obj)
> +{
> + ARMCPU *cpu = ARM_CPU(obj);
> + ARMCPUClass *cpu_class = ARM_CPU_GET_CLASS(obj);
> +
> + memset(&cpu->env, 0, sizeof(CPUARMState));
> + cpu_exec_init(&cpu->env);
> +
> + cpu->env.cpu_model_str = object_get_typename(obj);
> + cpu->env.cp15.c0_cpuid = cpu_class->cp15.c0_cpuid;
> +}
> +
> static void arm_cpu_class_init(ObjectClass *klass, void *data)
> {
> ARMCPUClass *k = ARM_CPU_CLASS(klass);
> @@ -161,6 +238,7 @@ static void cpu_register(const ARMCPUInfo *info)
> .name = info->name,
> .parent = TYPE_ARM_CPU,
> .instance_size = sizeof(ARMCPU),
> + .instance_init = arm_cpu_initfn,
> .class_size = sizeof(ARMCPUClass),
> .class_init = arm_cpu_class_init,
> .class_data = (void *)info,
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index d8425db..c5ba7fd 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -7,9 +7,6 @@
> #include "helper.h"
> #include "qemu-common.h"
> #include "host-utils.h"
> -#if !defined(CONFIG_USER_ONLY)
> -#include "hw/loader.h"
> -#endif
> #include "sysemu.h"
> #include "cpu-core.h"
>
> @@ -59,7 +56,6 @@ static inline void set_feature(CPUARMState *env, int feature)
>
> static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
> {
> - env->cp15.c0_cpuid = id;
> switch (id) {
> case ARM_CPUID_ARM926:
> set_feature(env, ARM_FEATURE_V5);
> @@ -285,64 +281,12 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
> void cpu_reset(CPUARMState *env)
> {
> uint32_t id;
> - uint32_t tmp = 0;
>
> - if (qemu_loglevel_mask(CPU_LOG_RESET)) {
> - qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
> - log_cpu_state(env, 0);
> - }
> + cpu_do_reset(CPU(ENV_GET_OBJECT(env)));
>
> id = env->cp15.c0_cpuid;
> - tmp = env->cp15.c15_config_base_address;
> - memset(env, 0, offsetof(CPUARMState, breakpoints));
> if (id)
> cpu_reset_model_id(env, id);
> - env->cp15.c15_config_base_address = tmp;
> -#if defined (CONFIG_USER_ONLY)
> - env->uncached_cpsr = ARM_CPU_MODE_USR;
> - /* For user mode we must enable access to coprocessors */
> - env->vfp.xregs[ARM_VFP_FPEXC] = 1<< 30;
> - if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
> - env->cp15.c15_cpar = 3;
> - } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
> - env->cp15.c15_cpar = 1;
> - }
> -#else
> - /* SVC mode with interrupts disabled. */
> - env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
> - /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
> - clear at reset. Initial SP and PC are loaded from ROM. */
> - if (IS_M(env)) {
> - uint32_t pc;
> - uint8_t *rom;
> - env->uncached_cpsr&= ~CPSR_I;
> - rom = rom_ptr(0);
> - if (rom) {
> - /* We should really use ldl_phys here, in case the guest
> - modified flash and reset itself. However images
> - loaded via -kernel have not been copied yet, so load the
> - values directly from there. */
> - env->regs[13] = ldl_p(rom);
> - pc = ldl_p(rom + 4);
> - env->thumb = pc& 1;
> - env->regs[15] = pc& ~1;
> - }
> - }
> - env->vfp.xregs[ARM_VFP_FPEXC] = 0;
> - env->cp15.c2_base_mask = 0xffffc000u;
> - /* v7 performance monitor control register: same implementor
> - * field as main ID register, and we implement no event counters.
> - */
> - env->cp15.c9_pmcr = (id& 0xff000000);
> -#endif
> - set_flush_to_zero(1,&env->vfp.standard_fp_status);
> - set_flush_inputs_to_zero(1,&env->vfp.standard_fp_status);
> - set_default_nan_mode(1,&env->vfp.standard_fp_status);
> - set_float_detect_tininess(float_tininess_before_rounding,
> -&env->vfp.fp_status);
> - set_float_detect_tininess(float_tininess_before_rounding,
> -&env->vfp.standard_fp_status);
> - tlb_flush(env, 1);
> }
>
> static int vfp_gdb_get_reg(CPUState *env, uint8_t *buf, int reg)
> @@ -400,7 +344,7 @@ static int vfp_gdb_set_reg(CPUState *env, uint8_t *buf, int reg)
> CPUARMState *cpu_arm_init(const char *cpu_model)
> {
> ObjectClass *klass;
> - ARMCPUClass *cpu_class;
> + ARMCPU *cpu;
> CPUARMState *env;
> static int inited = 0;
>
> @@ -413,16 +357,14 @@ CPUARMState *cpu_arm_init(const char *cpu_model)
> if (klass == NULL) {
> return NULL;
> }
> - cpu_class = ARM_CPU_CLASS(klass);
> - env = g_malloc0(sizeof(CPUARMState));
> - cpu_exec_init(env);
> + cpu = ARM_CPU(object_new(cpu_model));
> + env =&cpu->env;
> +
> if (tcg_enabled()&& !inited) {
> inited = 1;
> arm_translate_init();
> }
>
> - env->cpu_model_str = cpu_model;
> - env->cp15.c0_cpuid = cpu_class->cp15.c0_cpuid;
> cpu_reset(env);
> if (arm_feature(env, ARM_FEATURE_NEON)) {
> gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
> @@ -464,7 +406,8 @@ void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
>
> void cpu_arm_close(CPUARMState *env)
> {
> - g_free(env);
> + Object *obj = ENV_GET_OBJECT(env);
> + object_delete(obj);
> }
>
> static int bad_mode_switch(CPUState *env, int mode)
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v3 06/21] target-arm: Prepare model-specific class_init function
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 06/21] target-arm: Prepare model-specific class_init function Andreas Färber
@ 2012-02-06 23:03 ` Anthony Liguori
2012-02-06 23:08 ` Andreas Färber
0 siblings, 1 reply; 47+ messages in thread
From: Anthony Liguori @ 2012-02-06 23:03 UTC (permalink / raw)
To: Andreas Färber; +Cc: qemu-devel
On 02/02/2012 08:59 PM, Andreas Färber wrote:
> This allows to share initialization between CPU models.
>
> Signed-off-by: Andreas Färber<afaerber@suse.de>
> ---
> target-arm/cpu.c | 5 +++++
> 1 files changed, 5 insertions(+), 0 deletions(-)
>
> diff --git a/target-arm/cpu.c b/target-arm/cpu.c
> index 43231c9..b794ec1 100644
> --- a/target-arm/cpu.c
> +++ b/target-arm/cpu.c
> @@ -96,6 +96,7 @@ static void arm_cpu_reset(CPU *c)
> typedef struct ARMCPUInfo {
> const char *name;
> uint32_t id;
> + void (*class_init)(ARMCPUClass *klass, const struct ARMCPUInfo *info);
> } ARMCPUInfo;
So could you do:
TypeInfo arm_cpus[] = {
{
.name = "arm-cpu-model",
.parent = TYPE_ARM_CPU,
.class_data = (void *)(intptr_t)0x2342342,
.class_init = arm_generic_init,
}
It's roughly the same code but then there isn't redirection. You can do this in
general by having something like:
.class_data = (SpecialInfo[]){ .id = 0x23423423 },
Regards,
Anthony Liguori
>
> static const ARMCPUInfo arm_cpus[] = {
> @@ -230,6 +231,10 @@ static void arm_cpu_class_init(ObjectClass *klass, void *data)
> cpu_class->reset = arm_cpu_reset;
>
> k->cp15.c0_cpuid = info->id;
> +
> + if (info->class_init != NULL) {
> + (*info->class_init)(k, info);
> + }
> }
>
> static void cpu_register(const ARMCPUInfo *info)
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v3 05/21] target-arm: Embed CPUARMState in QOM ARMCPU
2012-02-06 23:00 ` Anthony Liguori
@ 2012-02-06 23:05 ` Andreas Färber
0 siblings, 0 replies; 47+ messages in thread
From: Andreas Färber @ 2012-02-06 23:05 UTC (permalink / raw)
To: Anthony Liguori; +Cc: Peter Maydell, Paul Brook, qemu-devel, Richard Henderson
Am 07.02.2012 00:00, schrieb Anthony Liguori:
> On 02/02/2012 08:59 PM, Andreas Färber wrote:
>> +static inline Object *arm_env_get_object(CPUARMState *env)
>> +{
>> + return OBJECT((void *)(env) - offsetof(ARMCPU, env));
>> +}
>> +
>> +#define ENV_GET_OBJECT(e) arm_env_get_object(e)
>
> I'd prefer:
>
> ARMCPU *arm_cpu_from_cpu_state(CPUState *env)
> {
> return ARM_CPU(container_of(env, ARMCPU, env));
> }
container_of() is a nice suggestion. However I deliberately decided
against ARMCPU to be able to use it from common code; CPU would work though.
e.g.
#ifdef ENV_GET_OBJECT
// new code
#else
// legacy code
#endif
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v3 06/21] target-arm: Prepare model-specific class_init function
2012-02-06 23:03 ` Anthony Liguori
@ 2012-02-06 23:08 ` Andreas Färber
0 siblings, 0 replies; 47+ messages in thread
From: Andreas Färber @ 2012-02-06 23:08 UTC (permalink / raw)
To: Anthony Liguori; +Cc: qemu-devel
Am 07.02.2012 00:03, schrieb Anthony Liguori:
> On 02/02/2012 08:59 PM, Andreas Färber wrote:
>> This allows to share initialization between CPU models.
>>
>> Signed-off-by: Andreas Färber<afaerber@suse.de>
>> ---
>> target-arm/cpu.c | 5 +++++
>> 1 files changed, 5 insertions(+), 0 deletions(-)
>>
>> diff --git a/target-arm/cpu.c b/target-arm/cpu.c
>> index 43231c9..b794ec1 100644
>> --- a/target-arm/cpu.c
>> +++ b/target-arm/cpu.c
>> @@ -96,6 +96,7 @@ static void arm_cpu_reset(CPU *c)
>> typedef struct ARMCPUInfo {
>> const char *name;
>> uint32_t id;
>> + void (*class_init)(ARMCPUClass *klass, const struct ARMCPUInfo
>> *info);
>> } ARMCPUInfo;
>
> So could you do:
>
> TypeInfo arm_cpus[] = {
> {
> .name = "arm-cpu-model",
> .parent = TYPE_ARM_CPU,
> .class_data = (void *)(intptr_t)0x2342342,
> .class_init = arm_generic_init,
> }
>
> It's roughly the same code but then there isn't redirection. You can do
> this in general by having something like:
>
> .class_data = (SpecialInfo[]){ .id = 0x23423423 },
Have you reviewed the users of this? More fields are being added, and
the specific users of this facility initialize fields not shared by many
CPUs so I wanted to keep ARMCPUInfo small. The shared fields are already
being initialized by arm_cpu_class_init() via .class_data.
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v3 02/21] qom: Add QOM support to user emulators
2012-02-06 19:16 ` Anthony Liguori
@ 2012-02-06 23:23 ` Andreas Färber
2012-02-07 17:25 ` Peter Maydell
1 sibling, 0 replies; 47+ messages in thread
From: Andreas Färber @ 2012-02-06 23:23 UTC (permalink / raw)
To: Anthony Liguori; +Cc: qemu-devel
Am 06.02.2012 20:16, schrieb Anthony Liguori:
> On 02/02/2012 08:59 PM, Andreas Färber wrote:
>> Link the Object base class and the module infrastructure for class
>> registration. Call QOM module init.
>>
>> Signed-off-by: Andreas Färber<afaerber@suse.de>
>> Cc: Anthony Liguori<anthony@codemonkey.ws>
>
> If we're going to go down this road, then I have a hard requirement. We
> need to build the common infrastructure only once.
>
> Otherwise build times are going to explode and we'll end up with
> CONFIG_USER_ONLY #defines all over the place.
v3 builds it once as before plus once for the user emulators. If that is
really too much already, please advise where to move the objects to.
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v3 02/21] qom: Add QOM support to user emulators
2012-02-06 19:16 ` Anthony Liguori
2012-02-06 23:23 ` Andreas Färber
@ 2012-02-07 17:25 ` Peter Maydell
2012-02-07 17:51 ` Anthony Liguori
1 sibling, 1 reply; 47+ messages in thread
From: Peter Maydell @ 2012-02-07 17:25 UTC (permalink / raw)
To: Anthony Liguori; +Cc: Andreas Färber, qemu-devel
On 6 February 2012 19:16, Anthony Liguori <anthony@codemonkey.ws> wrote:
> If we're going to go down this road, then I have a hard requirement. We
> need to build the common infrastructure only once.
>
> Otherwise build times are going to explode and we'll end up with
> CONFIG_USER_ONLY #defines all over the place.
You already have to build twice, because you can't say "build the
user emulators with --static and the system emulators without", so
one of the standard use cases requires doing two configure-and-build
runs anyhow.
-- PMM
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v3 08/21] target-arm: Move CPU feature flags out of CPUState
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 08/21] target-arm: Move CPU feature flags out of CPUState Andreas Färber
@ 2012-02-07 17:28 ` Peter Maydell
2012-02-07 17:43 ` Andreas Färber
0 siblings, 1 reply; 47+ messages in thread
From: Peter Maydell @ 2012-02-07 17:28 UTC (permalink / raw)
To: Andreas Färber; +Cc: qemu-devel
On 3 February 2012 02:59, Andreas Färber <afaerber@suse.de> wrote:
> +static void sa11xx_class_init(ARMCPUClass *k, const ARMCPUInfo *info)
> +{
> + set_class_feature(k, ARM_FEATURE_STRONGARM);
> +}
> static const ARMCPUInfo arm_cpus[] = {
> {
> .name = "arm926",
> .id = 0x41069265,
> + .features = ARM_FEATURE(V5) |
> + ARM_FEATURE(VFP),
> },
> {
> .name = "sa1100",
> .id = 0x4401A11B,
> + .class_init = sa11xx_class_init,
> },
So why are we handling some of these feature bits by setting them
in .features, and some of them via a .class_init which sets the
feature bit?
-- PMM
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v3 07/21] target-arm: Overwrite reset handler for ti925t
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 07/21] target-arm: Overwrite reset handler for ti925t Andreas Färber
@ 2012-02-07 17:30 ` Peter Maydell
0 siblings, 0 replies; 47+ messages in thread
From: Peter Maydell @ 2012-02-07 17:30 UTC (permalink / raw)
To: Andreas Färber; +Cc: qemu-devel
On 3 February 2012 02:59, Andreas Färber <afaerber@suse.de> wrote:
> The OMAPCP feature allows to switch between TI915T and TI925T via
> cp15 c15_ticonfig register. Move reset into ti925t-specific callback.
>
> Signed-off-by: Andreas Färber <afaerber@suse.de>
> Cc: Peter Maydell <peter.maydell@linaro.org>
> ---
> target-arm/cpu.c | 18 ++++++++++++++++++
> target-arm/helper.c | 1 -
> 2 files changed, 18 insertions(+), 1 deletions(-)
>
> diff --git a/target-arm/cpu.c b/target-arm/cpu.c
> index b794ec1..a6dbad3 100644
> --- a/target-arm/cpu.c
> +++ b/target-arm/cpu.c
> @@ -99,6 +99,23 @@ typedef struct ARMCPUInfo {
> void (*class_init)(ARMCPUClass *klass, const struct ARMCPUInfo *info);
> } ARMCPUInfo;
>
> +static void ti925t_reset(CPU *c)
> +{
> + ARMCPU *cpu = ARM_CPU(c);
> + CPUARMState *env = &cpu->env;
> +
> + arm_cpu_reset(c);
> +
> + env->cp15.c0_cpuid = ARM_CPUID_TI925T; /* Depends on wiring. */
> +}
If/when I finish my cp15 cleanup series this will become unnecessary, because
c0_cpuid will just be another cp15 register among many which the CPU defines
in its init function somewhere (and the cp15 register struct will include
"reset value for this cp15 register" and arm_cpu_reset() will just enumerate
them all and set them to their reset values).
-- PMM
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v3 08/21] target-arm: Move CPU feature flags out of CPUState
2012-02-07 17:28 ` Peter Maydell
@ 2012-02-07 17:43 ` Andreas Färber
0 siblings, 0 replies; 47+ messages in thread
From: Andreas Färber @ 2012-02-07 17:43 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel
Am 07.02.2012 18:28, schrieb Peter Maydell:
> On 3 February 2012 02:59, Andreas Färber <afaerber@suse.de> wrote:
>> +static void sa11xx_class_init(ARMCPUClass *k, const ARMCPUInfo *info)
>> +{
>> + set_class_feature(k, ARM_FEATURE_STRONGARM);
>> +}
>
>> static const ARMCPUInfo arm_cpus[] = {
>> {
>> .name = "arm926",
>> .id = 0x41069265,
>> + .features = ARM_FEATURE(V5) |
>> + ARM_FEATURE(VFP),
>> },
>
>> {
>> .name = "sa1100",
>> .id = 0x4401A11B,
>> + .class_init = sa11xx_class_init,
>> },
>
> So why are we handling some of these feature bits by setting them
> in .features, and some of them via a .class_init which sets the
> feature bit?
To avoid duplication. This corresponds to fall-throughs in the switch.
Eventually as suggested by you we would get rid of some of these
duplicate models and let the user (or an alias-like compatibility
mechanism) set the desired revision numbers on one base class via QOM
properties. Then those class_inits would no longer be needed.
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v3 15/21] target-arm: Store VFP FPSID register in ARMCPUClass
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 15/21] target-arm: Store VFP FPSID register in ARMCPUClass Andreas Färber
@ 2012-02-07 17:44 ` Peter Maydell
0 siblings, 0 replies; 47+ messages in thread
From: Peter Maydell @ 2012-02-07 17:44 UTC (permalink / raw)
To: Andreas Färber; +Cc: qemu-devel
On 3 February 2012 02:59, Andreas Färber <afaerber@suse.de> wrote:
> @@ -375,6 +383,7 @@ static const ARMCPUInfo arm_cpus[] = {
> 0x00111142, 0, 0, 0
> },
> .cp15_c1_sys = 0x00c50078,
> + .vfp_fpsid = 0x41034000, /* Guess */
> .features = ARM_FEATURE(V7) |
> ARM_FEATURE(VFP3) |
> ARM_FEATURE(VFP_FP16) |
> @@ -55,7 +45,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
> env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */
> break;
> case ARM_CPUID_CORTEXA9:
> - env->vfp.xregs[ARM_VFP_FPSID] = 0x41034000; /* Guess */
> env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
> env->vfp.xregs[ARM_VFP_MVFR1] = 0x01111111;
> env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3;
Incidentally, this guess for FPSID is wrong -- it should be 0x41033090 for
the r0p0 we're claiming to model (later revs the bottom nibble is bumped).
I'll send a patch...
-- PMM
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v3 13/21] target-arm: Store JTAG_ID in ARMCPUClass
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 13/21] target-arm: Store JTAG_ID in ARMCPUClass Andreas Färber
@ 2012-02-07 17:47 ` Peter Maydell
2012-02-07 18:41 ` Andreas Färber
0 siblings, 1 reply; 47+ messages in thread
From: Peter Maydell @ 2012-02-07 17:47 UTC (permalink / raw)
To: Andreas Färber; +Cc: qemu-devel
On 3 February 2012 02:59, Andreas Färber <afaerber@suse.de> wrote:
> That way we can remove some more CPUID cases without losing info.
>
> Signed-off-by: Andreas Färber <afaerber@suse.de>
> Cc: Peter Maydell <peter.maydell@linaro.org>
> Cc: Andrzej Zaborowski <balrogg@gmail.com>
> ---
> target-arm/cpu-core.h | 1 +
> target-arm/cpu.c | 2 ++
> target-arm/cpu.h | 5 -----
> target-arm/helper.c | 8 --------
> 4 files changed, 3 insertions(+), 13 deletions(-)
>
> diff --git a/target-arm/cpu-core.h b/target-arm/cpu-core.h
> index 3e7dfae..eac1a03 100644
> --- a/target-arm/cpu-core.h
> +++ b/target-arm/cpu-core.h
> @@ -48,6 +48,7 @@ typedef struct ARMCPUClass {
> uint32_t c0_c2[8];
> uint32_t c1_sys;
> } cp15;
> + uint64_t jtag_id;
If we're not using this anywhere we should just not have it.
-- PMM
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v3 02/21] qom: Add QOM support to user emulators
2012-02-07 17:25 ` Peter Maydell
@ 2012-02-07 17:51 ` Anthony Liguori
0 siblings, 0 replies; 47+ messages in thread
From: Anthony Liguori @ 2012-02-07 17:51 UTC (permalink / raw)
To: Peter Maydell; +Cc: Andreas Färber, qemu-devel
On 02/07/2012 11:25 AM, Peter Maydell wrote:
> On 6 February 2012 19:16, Anthony Liguori<anthony@codemonkey.ws> wrote:
>> If we're going to go down this road, then I have a hard requirement. We
>> need to build the common infrastructure only once.
>>
>> Otherwise build times are going to explode and we'll end up with
>> CONFIG_USER_ONLY #defines all over the place.
>
> You already have to build twice, because you can't say "build the
> user emulators with --static and the system emulators without", so
> one of the standard use cases requires doing two configure-and-build
> runs anyhow.
So does it make sense to build both user and system emulators by default?
QOM has a lot of dependencies. Rebuilding it for user means that we're goign to
end up rebuilding a lot of user code which sucks.
Regards,
Anthony Liguori
>
> -- PMM
>
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v3 13/21] target-arm: Store JTAG_ID in ARMCPUClass
2012-02-07 17:47 ` Peter Maydell
@ 2012-02-07 18:41 ` Andreas Färber
2012-02-07 19:06 ` Peter Maydell
0 siblings, 1 reply; 47+ messages in thread
From: Andreas Färber @ 2012-02-07 18:41 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel
Am 07.02.2012 18:47, schrieb Peter Maydell:
> On 3 February 2012 02:59, Andreas Färber <afaerber@suse.de> wrote:
>> That way we can remove some more CPUID cases without losing info.
>>
>> Signed-off-by: Andreas Färber <afaerber@suse.de>
>> Cc: Peter Maydell <peter.maydell@linaro.org>
>> Cc: Andrzej Zaborowski <balrogg@gmail.com>
>> ---
>> target-arm/cpu-core.h | 1 +
>> target-arm/cpu.c | 2 ++
>> target-arm/cpu.h | 5 -----
>> target-arm/helper.c | 8 --------
>> 4 files changed, 3 insertions(+), 13 deletions(-)
>>
>> diff --git a/target-arm/cpu-core.h b/target-arm/cpu-core.h
>> index 3e7dfae..eac1a03 100644
>> --- a/target-arm/cpu-core.h
>> +++ b/target-arm/cpu-core.h
>> @@ -48,6 +48,7 @@ typedef struct ARMCPUClass {
>> uint32_t c0_c2[8];
>> uint32_t c1_sys;
>> } cp15;
>> + uint64_t jtag_id;
>
> If we're not using this anywhere we should just not have it.
Andrzej will have had his reasons to put it in the code. This series
just moves code around so I don't want to remove it without his ack. I
cc'ed him in the hopes of getting an explanation. :)
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v3 13/21] target-arm: Store JTAG_ID in ARMCPUClass
2012-02-07 18:41 ` Andreas Färber
@ 2012-02-07 19:06 ` Peter Maydell
2012-02-07 22:07 ` Andreas Färber
0 siblings, 1 reply; 47+ messages in thread
From: Peter Maydell @ 2012-02-07 19:06 UTC (permalink / raw)
To: Andreas Färber; +Cc: qemu-devel
On 7 February 2012 18:41, Andreas Färber <afaerber@suse.de> wrote:
> Am 07.02.2012 18:47, schrieb Peter Maydell:
>> On 3 February 2012 02:59, Andreas Färber <afaerber@suse.de> wrote:
>>> + uint64_t jtag_id;
>>
>> If we're not using this anywhere we should just not have it.
>
> Andrzej will have had his reasons to put it in the code. This series
> just moves code around so I don't want to remove it without his ack.
That was my point -- as far as I can see this patch *is* adding code
and a struct field that wasn't there before.
-- PMM
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v3 13/21] target-arm: Store JTAG_ID in ARMCPUClass
2012-02-07 19:06 ` Peter Maydell
@ 2012-02-07 22:07 ` Andreas Färber
2012-02-07 23:30 ` Peter Maydell
0 siblings, 1 reply; 47+ messages in thread
From: Andreas Färber @ 2012-02-07 22:07 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel
Am 07.02.2012 20:06, schrieb Peter Maydell:
> On 7 February 2012 18:41, Andreas Färber <afaerber@suse.de> wrote:
>> Am 07.02.2012 18:47, schrieb Peter Maydell:
>>> On 3 February 2012 02:59, Andreas Färber <afaerber@suse.de> wrote:
>>>> + uint64_t jtag_id;
>>>
>>> If we're not using this anywhere we should just not have it.
>>
>> Andrzej will have had his reasons to put it in the code. This series
>> just moves code around so I don't want to remove it without his ack.
>
> That was my point -- as far as I can see this patch *is* adding code
> and a struct field that wasn't there before.
Huh? Look closely, it *was* a comment in the original code. And I don't
want to *move* that comment over into my new code. Therefore I'm adding
a class field where such informational data can properly be stored and
inspected - per class, not per CPUState instance.
I can imagine storing much more information in a CPU class such as
vendor name*, description, logo, link to docs and chip color ;) to allow
for a nice lspci-like inspection.
* Yeah, in case of ARM the vendor can be inferred from CPUID so a getter
would be sufficient but you get the idea.
Again, I don't specifically need a jtag_id field, but this data is
definitely coming from existing code. If Andrzej doesn't respond here,
feel free to send a trivial patch to remove it from there.
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v3 13/21] target-arm: Store JTAG_ID in ARMCPUClass
2012-02-07 22:07 ` Andreas Färber
@ 2012-02-07 23:30 ` Peter Maydell
0 siblings, 0 replies; 47+ messages in thread
From: Peter Maydell @ 2012-02-07 23:30 UTC (permalink / raw)
To: Andreas Färber; +Cc: qemu-devel
On 7 February 2012 22:07, Andreas Färber <afaerber@suse.de> wrote:
> Am 07.02.2012 20:06, schrieb Peter Maydell:
>> On 7 February 2012 18:41, Andreas Färber <afaerber@suse.de> wrote:
>>> Andrzej will have had his reasons to put it in the code. This series
>>> just moves code around so I don't want to remove it without his ack.
>>
>> That was my point -- as far as I can see this patch *is* adding code
>> and a struct field that wasn't there before.
>
> Huh? Look closely, it *was* a comment in the original code.
Exactly. It was a comment; now it's code. I don't think we should
be adding code.
> And I don't want to *move* that comment over into my new code.
You can move the comment, or you can just drop it; I'm happy with
either. I don't want new code/struct fields we don't use.
-- PMM
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v3 14/21] target-arm: Move the PXA270's iwMMXt reset to pxa270_reset()
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 14/21] target-arm: Move the PXA270's iwMMXt reset to pxa270_reset() Andreas Färber
@ 2012-02-17 9:59 ` andrzej zaborowski
2012-02-17 12:03 ` Andreas Färber
0 siblings, 1 reply; 47+ messages in thread
From: andrzej zaborowski @ 2012-02-17 9:59 UTC (permalink / raw)
To: Andreas Färber; +Cc: Peter Maydell, qemu-devel
On 3 February 2012 03:59, Andreas Färber <afaerber@suse.de> wrote:
> No other emulated CPU uses this at this time.
But why does this code better fit in hw/ than target-arm? The iwMMXt
registers are core registers after all.
Also the defines let the board code request a cpu revision by name
instead of using a magic number, so I think they're useful.
Cheers
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v3 14/21] target-arm: Move the PXA270's iwMMXt reset to pxa270_reset()
2012-02-17 9:59 ` andrzej zaborowski
@ 2012-02-17 12:03 ` Andreas Färber
2012-02-17 12:44 ` andrzej zaborowski
0 siblings, 1 reply; 47+ messages in thread
From: Andreas Färber @ 2012-02-17 12:03 UTC (permalink / raw)
To: andrzej zaborowski; +Cc: Peter Maydell, qemu-devel, Paul Brook
Am 17.02.2012 10:59, schrieb andrzej zaborowski:
> On 3 February 2012 03:59, Andreas Färber <afaerber@suse.de> wrote:
>> No other emulated CPU uses this at this time.
>
> But why does this code better fit in hw/ than target-arm? The iwMMXt
> registers are core registers after all.
It seems you've misread something here. This is all in target-arm. :)
> Also the defines let the board code request a cpu revision by name
> instead of using a magic number, so I think they're useful.
No, the boards request a CPU by type name, which is not magic either.
The whole point of QOM'ification is to have the CPU provide the
necessary fields and methods, not logic spread across the code in an
if-this-cpu-then fashion. I plan to tackle cp15 (the last remainder of
CPUID code dependencies) when I'm through with all other targets.
If someone really needs the CPUID they can access it through ARMCPU
(CPUARMState).
The final plan for rnpn is to have two QOM properties and to request a
"pxa270" CPU, then set the revision since there are no functional
dependencies on the revision at all. (cc'ing Paul)
I've actually compile-tested and grep'ed this.
Please note also the following v4 that came out of an IRC discussion:
http://repo.or.cz/w/qemu/afaerber.git/commitdiff/1262acf06308cf2bde46520d0238548cb73c79fe
If you need the JTAG_ID somewhere please let us know soon.
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v3 14/21] target-arm: Move the PXA270's iwMMXt reset to pxa270_reset()
2012-02-17 12:03 ` Andreas Färber
@ 2012-02-17 12:44 ` andrzej zaborowski
0 siblings, 0 replies; 47+ messages in thread
From: andrzej zaborowski @ 2012-02-17 12:44 UTC (permalink / raw)
To: Andreas Färber; +Cc: Peter Maydell, qemu-devel, Paul Brook
On 17 February 2012 13:03, Andreas Färber <afaerber@suse.de> wrote:
> Am 17.02.2012 10:59, schrieb andrzej zaborowski:
>> On 3 February 2012 03:59, Andreas Färber <afaerber@suse.de> wrote:
>>> No other emulated CPU uses this at this time.
>>
>> But why does this code better fit in hw/ than target-arm? The iwMMXt
>> registers are core registers after all.
>
> It seems you've misread something here. This is all in target-arm. :)
Yes, I did, sorry. I had looked at the whole series previously,
forgotten it, then looked at this patch that was still in my inbox
without any of the context.
...
> The final plan for rnpn is to have two QOM properties and to request a
> "pxa270" CPU, then set the revision since there are no functional
> dependencies on the revision at all. (cc'ing Paul)
> I've actually compile-tested and grep'ed this.
>
Sounds reasonable.
>
> Please note also the following v4 that came out of an IRC discussion:
> http://repo.or.cz/w/qemu/afaerber.git/commitdiff/1262acf06308cf2bde46520d0238548cb73c79fe
> If you need the JTAG_ID somewhere please let us know soon.
No, it's not used anywhere (obviously otherwise it wouldn't be a comment)
Cheers
^ permalink raw reply [flat|nested] 47+ messages in thread
end of thread, other threads:[~2012-02-17 12:44 UTC | newest]
Thread overview: 47+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2012-02-03 2:59 [Qemu-devel] [PATCH RFC v3 00/21] Introduce QOM CPU and use it for ARM Andreas Färber
2012-02-03 2:59 ` [Qemu-devel] [PATCH v3 01/21] qom: Register QOM infrastructure early Andreas Färber
2012-02-06 19:14 ` Anthony Liguori
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 02/21] qom: Add QOM support to user emulators Andreas Färber
2012-02-06 19:16 ` Anthony Liguori
2012-02-06 23:23 ` Andreas Färber
2012-02-07 17:25 ` Peter Maydell
2012-02-07 17:51 ` Anthony Liguori
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 03/21] qom: Introduce CPU class Andreas Färber
2012-02-06 19:24 ` Anthony Liguori
2012-02-06 20:01 ` Peter Maydell
2012-02-06 20:14 ` Andreas Färber
2012-02-06 21:22 ` Anthony Liguori
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 04/21] target-arm: Introduce QOM CPU and use it for CPUID lookup Andreas Färber
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 05/21] target-arm: Embed CPUARMState in QOM ARMCPU Andreas Färber
2012-02-06 23:00 ` Anthony Liguori
2012-02-06 23:05 ` Andreas Färber
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 06/21] target-arm: Prepare model-specific class_init function Andreas Färber
2012-02-06 23:03 ` Anthony Liguori
2012-02-06 23:08 ` Andreas Färber
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 07/21] target-arm: Overwrite reset handler for ti925t Andreas Färber
2012-02-07 17:30 ` Peter Maydell
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 08/21] target-arm: Move CPU feature flags out of CPUState Andreas Färber
2012-02-07 17:28 ` Peter Maydell
2012-02-07 17:43 ` Andreas Färber
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 09/21] target-arm: No longer abort on unhandled CPUIDs on reset Andreas Färber
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 10/21] target-arm: Store cp15 c0_c1 and c0_c2 in ARMCPUClass Andreas Färber
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 11/21] target-arm: Store cp15 c0_cachetype register " Andreas Färber
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 12/21] target-arm: Move cp15 c1_sys register to ARMCPUClass Andreas Färber
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 13/21] target-arm: Store JTAG_ID in ARMCPUClass Andreas Färber
2012-02-07 17:47 ` Peter Maydell
2012-02-07 18:41 ` Andreas Färber
2012-02-07 19:06 ` Peter Maydell
2012-02-07 22:07 ` Andreas Färber
2012-02-07 23:30 ` Peter Maydell
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 14/21] target-arm: Move the PXA270's iwMMXt reset to pxa270_reset() Andreas Färber
2012-02-17 9:59 ` andrzej zaborowski
2012-02-17 12:03 ` Andreas Färber
2012-02-17 12:44 ` andrzej zaborowski
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 15/21] target-arm: Store VFP FPSID register in ARMCPUClass Andreas Färber
2012-02-07 17:44 ` Peter Maydell
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 16/21] target-arm: Store VFP MVFR0 and MVFR1 " Andreas Färber
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 17/21] target-arm: Store CLIDR " Andreas Färber
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 18/21] target-arm: Store CCSIDRs " Andreas Färber
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 19/21] target-arm: Kill off cpu_reset_model_id() Andreas Färber
2012-02-03 2:59 ` [Qemu-devel] [PATCH RFC v3 20/21] target-arm: Prepare halted property for CPU Andreas Färber
2012-02-03 2:59 ` [Qemu-devel] [FYI v3 21/21] target-arm: Just for testing! Andreas Färber
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