* [PATCH 01/11] board: freescale: p1_p2_rdb_pc: Do not hang in checkboard()
2022-04-07 10:16 [PATCH 00/11] board: freescale: p1_p2_rdb_pc: Various cleanups and fixes Pali Rohár
@ 2022-04-07 10:16 ` Pali Rohár
2022-04-07 10:16 ` [PATCH 02/11] board: freescale: p1_p2_rdb_pc: Detect both P2020 SD switch configurations Pali Rohár
` (9 subsequent siblings)
10 siblings, 0 replies; 32+ messages in thread
From: Pali Rohár @ 2022-04-07 10:16 UTC (permalink / raw)
To: Priyanka Jain, Qiang Zhao, Shengzhou Liu, Sinan Akman; +Cc: u-boot
Like in all other checks in checkboard() function, do not hang on error.
Signed-off-by: Pali Rohár <pali@kernel.org>
---
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 19ece1229631..186887336354 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -182,7 +182,7 @@ int checkboard(void)
if (ret) {
printf("%s: Cannot find udev for a bus %d\n", __func__,
bus_num);
- return -ENXIO;
+ return 0; /* Don't want to hang() on this error */
}
if (dm_i2c_read(dev, 0, &in, 1) < 0 ||
--
2.20.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 02/11] board: freescale: p1_p2_rdb_pc: Detect both P2020 SD switch configurations
2022-04-07 10:16 [PATCH 00/11] board: freescale: p1_p2_rdb_pc: Various cleanups and fixes Pali Rohár
2022-04-07 10:16 ` [PATCH 01/11] board: freescale: p1_p2_rdb_pc: Do not hang in checkboard() Pali Rohár
@ 2022-04-07 10:16 ` Pali Rohár
2022-04-07 10:16 ` [PATCH 03/11] board: freescale: p1_p2_rdb_pc: Fix parsing negated upper 4 bits from boot input data Pali Rohár
` (8 subsequent siblings)
10 siblings, 0 replies; 32+ messages in thread
From: Pali Rohár @ 2022-04-07 10:16 UTC (permalink / raw)
To: Priyanka Jain, Qiang Zhao, Shengzhou Liu, Sinan Akman; +Cc: u-boot
As written in comment, P2020 has two possible SD switch configurations.
Extend code to detect both of them.
Signed-off-by: Pali Rohár <pali@kernel.org>
---
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 4 ++++
include/configs/p1_p2_rdb_pc.h | 3 ++-
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 186887336354..29502a5c05c2 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -207,6 +207,10 @@ int checkboard(void)
puts("rom_loc: ");
if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD) {
puts("sd");
+#ifdef __SW_BOOT_SD2
+ } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD2) {
+ puts("sd");
+#endif
#ifdef __SW_BOOT_SPI
} else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SPI) {
puts("spi");
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 370772053e63..ecc6e0c644bf 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -60,7 +60,8 @@
#define __SW_BOOT_MASK 0x03
#define __SW_BOOT_NOR 0xc8
#define __SW_BOOT_SPI 0x28
-#define __SW_BOOT_SD 0x68 /* or 0x18 */
+#define __SW_BOOT_SD 0x68
+#define __SW_BOOT_SD2 0x18
#define __SW_BOOT_NAND 0xe8
#define __SW_BOOT_PCIE 0xa8
#define CONFIG_SYS_L2_SIZE (512 << 10)
--
2.20.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 03/11] board: freescale: p1_p2_rdb_pc: Fix parsing negated upper 4 bits from boot input data
2022-04-07 10:16 [PATCH 00/11] board: freescale: p1_p2_rdb_pc: Various cleanups and fixes Pali Rohár
2022-04-07 10:16 ` [PATCH 01/11] board: freescale: p1_p2_rdb_pc: Do not hang in checkboard() Pali Rohár
2022-04-07 10:16 ` [PATCH 02/11] board: freescale: p1_p2_rdb_pc: Detect both P2020 SD switch configurations Pali Rohár
@ 2022-04-07 10:16 ` Pali Rohár
2022-04-25 14:12 ` [PATCH v2] board: freescale: p1_p2_rdb_pc: Fix parsing inverted " Pali Rohár
2022-04-07 10:16 ` [PATCH 04/11] board: freescale: p1_p2_rdb_pc: Do not set MPC85xx_PMUXCR_SDHC_WP bit when SDHC_WP is used as GPIO Pali Rohár
` (7 subsequent siblings)
10 siblings, 1 reply; 32+ messages in thread
From: Pali Rohár @ 2022-04-07 10:16 UTC (permalink / raw)
To: Priyanka Jain, Qiang Zhao, Shengzhou Liu, Sinan Akman; +Cc: u-boot
On some boards upper 4 bits of i2c boot input data (register 0) are
negated. So negate read input data back prior processing them.
Fixes printing correct rom_loc: value.
Signed-off-by: Pali Rohár <pali@kernel.org>
---
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 29502a5c05c2..766a82386079 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -202,6 +202,10 @@ int checkboard(void)
}
#endif
+#ifdef __SW_BOOT_IN_NEG_UPPER4
+ in = (~in & 0xf0) | (in & 0x0f);
+#endif
+
val = (in & io_config) | (out & (~io_config));
puts("rom_loc: ");
--
2.20.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v2] board: freescale: p1_p2_rdb_pc: Fix parsing inverted bits from boot input data
2022-04-07 10:16 ` [PATCH 03/11] board: freescale: p1_p2_rdb_pc: Fix parsing negated upper 4 bits from boot input data Pali Rohár
@ 2022-04-25 14:12 ` Pali Rohár
2022-06-16 9:00 ` Peng Fan (OSS)
0 siblings, 1 reply; 32+ messages in thread
From: Pali Rohár @ 2022-04-25 14:12 UTC (permalink / raw)
To: Priyanka Jain, Qiang Zhao, Shengzhou Liu, Sinan Akman; +Cc: u-boot
On some boards upper 4 bits of i2c boot input data (register 0) are
inverted. Information which bits are inverted is stored in register 2.
So invert read input data back according to register 2 prior processing
them. This fixes printing "rom_loc: value" line during booting.
Signed-off-by: Pali Rohár <pali@kernel.org>
---
Changes in v2:
* Use register 2 for detecting which bits needs to be inverted
---
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 29502a5c05c2..cdbff03ac45c 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -164,7 +164,7 @@ int checkboard(void)
{
struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u8 in, out, io_config, val;
+ u8 in, out, invert, io_config, val;
int bus_num = CONFIG_SYS_SPD_BUS_NUM;
printf("Board: %s CPLD: V%d.%d PCBA: V%d.0\n", CONFIG_BOARDNAME,
@@ -187,6 +187,7 @@ int checkboard(void)
if (dm_i2c_read(dev, 0, &in, 1) < 0 ||
dm_i2c_read(dev, 1, &out, 1) < 0 ||
+ dm_i2c_read(dev, 2, &invert, 1) < 0 ||
dm_i2c_read(dev, 3, &io_config, 1) < 0) {
printf("Error reading i2c boot information!\n");
return 0; /* Don't want to hang() on this error */
@@ -196,13 +197,14 @@ int checkboard(void)
if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 ||
i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 ||
+ i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 2, 1, &invert, 1) < 0 ||
i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 3, 1, &io_config, 1) < 0) {
printf("Error reading i2c boot information!\n");
return 0; /* Don't want to hang() on this error */
}
#endif
- val = (in & io_config) | (out & (~io_config));
+ val = ((in ^ invert) & io_config) | (out & (~io_config));
puts("rom_loc: ");
if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD) {
--
2.20.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* Re: [PATCH v2] board: freescale: p1_p2_rdb_pc: Fix parsing inverted bits from boot input data
2022-04-25 14:12 ` [PATCH v2] board: freescale: p1_p2_rdb_pc: Fix parsing inverted " Pali Rohár
@ 2022-06-16 9:00 ` Peng Fan (OSS)
2022-06-16 12:37 ` [PATCH v3] " Pali Rohár
0 siblings, 1 reply; 32+ messages in thread
From: Peng Fan (OSS) @ 2022-06-16 9:00 UTC (permalink / raw)
To: Pali Rohár, Priyanka Jain, Qiang Zhao, Shengzhou Liu, Sinan Akman
Cc: u-boot
在 2022/4/25 22:12, Pali Rohár 写道:
> On some boards upper 4 bits of i2c boot input data (register 0) are
> inverted. Information which bits are inverted is stored in register 2.
>
> So invert read input data back according to register 2 prior processing
> them. This fixes printing "rom_loc: value" line during booting.
>
> Signed-off-by: Pali Rohár <pali@kernel.org>
Not able to apply this with next branch. Please rebase.
Thanks,
Peng.
> ---
> Changes in v2:
> * Use register 2 for detecting which bits needs to be inverted
> ---
> board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
> index 29502a5c05c2..cdbff03ac45c 100644
> --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
> +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
> @@ -164,7 +164,7 @@ int checkboard(void)
> {
> struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
> ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
> - u8 in, out, io_config, val;
> + u8 in, out, invert, io_config, val;
> int bus_num = CONFIG_SYS_SPD_BUS_NUM;
>
> printf("Board: %s CPLD: V%d.%d PCBA: V%d.0\n", CONFIG_BOARDNAME,
> @@ -187,6 +187,7 @@ int checkboard(void)
>
> if (dm_i2c_read(dev, 0, &in, 1) < 0 ||
> dm_i2c_read(dev, 1, &out, 1) < 0 ||
> + dm_i2c_read(dev, 2, &invert, 1) < 0 ||
> dm_i2c_read(dev, 3, &io_config, 1) < 0) {
> printf("Error reading i2c boot information!\n");
> return 0; /* Don't want to hang() on this error */
> @@ -196,13 +197,14 @@ int checkboard(void)
>
> if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 ||
> i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 ||
> + i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 2, 1, &invert, 1) < 0 ||
> i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 3, 1, &io_config, 1) < 0) {
> printf("Error reading i2c boot information!\n");
> return 0; /* Don't want to hang() on this error */
> }
> #endif
>
> - val = (in & io_config) | (out & (~io_config));
> + val = ((in ^ invert) & io_config) | (out & (~io_config));
>
> puts("rom_loc: ");
> if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD) {
^ permalink raw reply [flat|nested] 32+ messages in thread* [PATCH v3] board: freescale: p1_p2_rdb_pc: Fix parsing inverted bits from boot input data
2022-06-16 9:00 ` Peng Fan (OSS)
@ 2022-06-16 12:37 ` Pali Rohár
2022-06-23 13:04 ` Pali Rohár
0 siblings, 1 reply; 32+ messages in thread
From: Pali Rohár @ 2022-06-16 12:37 UTC (permalink / raw)
To: Peng Fan (OSS), Priyanka Jain, Qiang Zhao, Shengzhou Liu, Sinan Akman
Cc: u-boot
On some boards upper 4 bits of i2c boot input data (register 0) are
inverted. Information which bits are inverted is stored in register 2.
So invert read input data back according to register 2 prior processing
them. This fixes printing "rom_loc: value" line during booting.
Signed-off-by: Pali Rohár <pali@kernel.org>
---
Changes in v3:
* Rebased on top of the U-Boot next branch, commit a87a6fcd20c0e29fe55bfbb6917c4aa1f1bbce74
Changes in v2:
* Use register 2 for detecting which bits needs to be inverted
---
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 6665aa4ba94e..d36306f35427 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -174,7 +174,7 @@ int checkboard(void)
{
struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u8 in, out, io_config, val;
+ u8 in, out, invert, io_config, val;
int bus_num = CONFIG_SYS_SPD_BUS_NUM;
/* FIXME: This should just use the model from the device tree or similar */
@@ -198,6 +198,7 @@ int checkboard(void)
if (dm_i2c_read(dev, 0, &in, 1) < 0 ||
dm_i2c_read(dev, 1, &out, 1) < 0 ||
+ dm_i2c_read(dev, 2, &invert, 1) < 0 ||
dm_i2c_read(dev, 3, &io_config, 1) < 0) {
printf("Error reading i2c boot information!\n");
return 0; /* Don't want to hang() on this error */
@@ -207,13 +208,14 @@ int checkboard(void)
if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 ||
i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 ||
+ i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 2, 1, &invert, 1) < 0 ||
i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 3, 1, &io_config, 1) < 0) {
printf("Error reading i2c boot information!\n");
return 0; /* Don't want to hang() on this error */
}
#endif
- val = (in & io_config) | (out & (~io_config));
+ val = ((in ^ invert) & io_config) | (out & (~io_config));
puts("rom_loc: ");
if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD) {
--
2.20.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* Re: [PATCH v3] board: freescale: p1_p2_rdb_pc: Fix parsing inverted bits from boot input data
2022-06-16 12:37 ` [PATCH v3] " Pali Rohár
@ 2022-06-23 13:04 ` Pali Rohár
2022-07-03 12:39 ` Pali Rohár
0 siblings, 1 reply; 32+ messages in thread
From: Pali Rohár @ 2022-06-23 13:04 UTC (permalink / raw)
To: Peng Fan (OSS), Priyanka Jain, Qiang Zhao, Shengzhou Liu, Sinan Akman
Cc: u-boot
On Thursday 16 June 2022 14:37:07 Pali Rohár wrote:
> On some boards upper 4 bits of i2c boot input data (register 0) are
> inverted. Information which bits are inverted is stored in register 2.
>
> So invert read input data back according to register 2 prior processing
> them. This fixes printing "rom_loc: value" line during booting.
>
> Signed-off-by: Pali Rohár <pali@kernel.org>
> ---
> Changes in v3:
> * Rebased on top of the U-Boot next branch, commit a87a6fcd20c0e29fe55bfbb6917c4aa1f1bbce74
PING?
> Changes in v2:
> * Use register 2 for detecting which bits needs to be inverted
> ---
> board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
> index 6665aa4ba94e..d36306f35427 100644
> --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
> +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
> @@ -174,7 +174,7 @@ int checkboard(void)
> {
> struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
> ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
> - u8 in, out, io_config, val;
> + u8 in, out, invert, io_config, val;
> int bus_num = CONFIG_SYS_SPD_BUS_NUM;
>
> /* FIXME: This should just use the model from the device tree or similar */
> @@ -198,6 +198,7 @@ int checkboard(void)
>
> if (dm_i2c_read(dev, 0, &in, 1) < 0 ||
> dm_i2c_read(dev, 1, &out, 1) < 0 ||
> + dm_i2c_read(dev, 2, &invert, 1) < 0 ||
> dm_i2c_read(dev, 3, &io_config, 1) < 0) {
> printf("Error reading i2c boot information!\n");
> return 0; /* Don't want to hang() on this error */
> @@ -207,13 +208,14 @@ int checkboard(void)
>
> if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 ||
> i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 ||
> + i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 2, 1, &invert, 1) < 0 ||
> i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 3, 1, &io_config, 1) < 0) {
> printf("Error reading i2c boot information!\n");
> return 0; /* Don't want to hang() on this error */
> }
> #endif
>
> - val = (in & io_config) | (out & (~io_config));
> + val = ((in ^ invert) & io_config) | (out & (~io_config));
>
> puts("rom_loc: ");
> if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD) {
> --
> 2.20.1
>
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH v3] board: freescale: p1_p2_rdb_pc: Fix parsing inverted bits from boot input data
2022-06-23 13:04 ` Pali Rohár
@ 2022-07-03 12:39 ` Pali Rohár
2022-07-08 22:49 ` Pali Rohár
0 siblings, 1 reply; 32+ messages in thread
From: Pali Rohár @ 2022-07-03 12:39 UTC (permalink / raw)
To: Peng Fan (OSS), Priyanka Jain, Qiang Zhao, Shengzhou Liu, Sinan Akman
Cc: u-boot
On Thursday 23 June 2022 15:04:08 Pali Rohár wrote:
> On Thursday 16 June 2022 14:37:07 Pali Rohár wrote:
> > On some boards upper 4 bits of i2c boot input data (register 0) are
> > inverted. Information which bits are inverted is stored in register 2.
> >
> > So invert read input data back according to register 2 prior processing
> > them. This fixes printing "rom_loc: value" line during booting.
> >
> > Signed-off-by: Pali Rohár <pali@kernel.org>
> > ---
> > Changes in v3:
> > * Rebased on top of the U-Boot next branch, commit a87a6fcd20c0e29fe55bfbb6917c4aa1f1bbce74
>
> PING?
PING?
> > Changes in v2:
> > * Use register 2 for detecting which bits needs to be inverted
> > ---
> > board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 6 ++++--
> > 1 file changed, 4 insertions(+), 2 deletions(-)
> >
> > diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
> > index 6665aa4ba94e..d36306f35427 100644
> > --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
> > +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
> > @@ -174,7 +174,7 @@ int checkboard(void)
> > {
> > struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
> > ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
> > - u8 in, out, io_config, val;
> > + u8 in, out, invert, io_config, val;
> > int bus_num = CONFIG_SYS_SPD_BUS_NUM;
> >
> > /* FIXME: This should just use the model from the device tree or similar */
> > @@ -198,6 +198,7 @@ int checkboard(void)
> >
> > if (dm_i2c_read(dev, 0, &in, 1) < 0 ||
> > dm_i2c_read(dev, 1, &out, 1) < 0 ||
> > + dm_i2c_read(dev, 2, &invert, 1) < 0 ||
> > dm_i2c_read(dev, 3, &io_config, 1) < 0) {
> > printf("Error reading i2c boot information!\n");
> > return 0; /* Don't want to hang() on this error */
> > @@ -207,13 +208,14 @@ int checkboard(void)
> >
> > if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 ||
> > i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 ||
> > + i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 2, 1, &invert, 1) < 0 ||
> > i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 3, 1, &io_config, 1) < 0) {
> > printf("Error reading i2c boot information!\n");
> > return 0; /* Don't want to hang() on this error */
> > }
> > #endif
> >
> > - val = (in & io_config) | (out & (~io_config));
> > + val = ((in ^ invert) & io_config) | (out & (~io_config));
> >
> > puts("rom_loc: ");
> > if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD) {
> > --
> > 2.20.1
> >
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH v3] board: freescale: p1_p2_rdb_pc: Fix parsing inverted bits from boot input data
2022-07-03 12:39 ` Pali Rohár
@ 2022-07-08 22:49 ` Pali Rohár
2022-07-08 23:10 ` Tom Rini
0 siblings, 1 reply; 32+ messages in thread
From: Pali Rohár @ 2022-07-08 22:49 UTC (permalink / raw)
To: Peng Fan (OSS),
Priyanka Jain, Qiang Zhao, Shengzhou Liu, Sinan Akman, Tom Rini
Cc: u-boot
PING?
How many times you would ask me to again rebase this patch??
On Sunday 03 July 2022 14:39:13 Pali Rohár wrote:
> On Thursday 23 June 2022 15:04:08 Pali Rohár wrote:
> > On Thursday 16 June 2022 14:37:07 Pali Rohár wrote:
> > > On some boards upper 4 bits of i2c boot input data (register 0) are
> > > inverted. Information which bits are inverted is stored in register 2.
> > >
> > > So invert read input data back according to register 2 prior processing
> > > them. This fixes printing "rom_loc: value" line during booting.
> > >
> > > Signed-off-by: Pali Rohár <pali@kernel.org>
> > > ---
> > > Changes in v3:
> > > * Rebased on top of the U-Boot next branch, commit a87a6fcd20c0e29fe55bfbb6917c4aa1f1bbce74
> >
> > PING?
>
> PING?
>
> > > Changes in v2:
> > > * Use register 2 for detecting which bits needs to be inverted
> > > ---
> > > board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 6 ++++--
> > > 1 file changed, 4 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
> > > index 6665aa4ba94e..d36306f35427 100644
> > > --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
> > > +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
> > > @@ -174,7 +174,7 @@ int checkboard(void)
> > > {
> > > struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
> > > ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
> > > - u8 in, out, io_config, val;
> > > + u8 in, out, invert, io_config, val;
> > > int bus_num = CONFIG_SYS_SPD_BUS_NUM;
> > >
> > > /* FIXME: This should just use the model from the device tree or similar */
> > > @@ -198,6 +198,7 @@ int checkboard(void)
> > >
> > > if (dm_i2c_read(dev, 0, &in, 1) < 0 ||
> > > dm_i2c_read(dev, 1, &out, 1) < 0 ||
> > > + dm_i2c_read(dev, 2, &invert, 1) < 0 ||
> > > dm_i2c_read(dev, 3, &io_config, 1) < 0) {
> > > printf("Error reading i2c boot information!\n");
> > > return 0; /* Don't want to hang() on this error */
> > > @@ -207,13 +208,14 @@ int checkboard(void)
> > >
> > > if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 ||
> > > i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 ||
> > > + i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 2, 1, &invert, 1) < 0 ||
> > > i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 3, 1, &io_config, 1) < 0) {
> > > printf("Error reading i2c boot information!\n");
> > > return 0; /* Don't want to hang() on this error */
> > > }
> > > #endif
> > >
> > > - val = (in & io_config) | (out & (~io_config));
> > > + val = ((in ^ invert) & io_config) | (out & (~io_config));
> > >
> > > puts("rom_loc: ");
> > > if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD) {
> > > --
> > > 2.20.1
> > >
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH v3] board: freescale: p1_p2_rdb_pc: Fix parsing inverted bits from boot input data
2022-07-08 22:49 ` Pali Rohár
@ 2022-07-08 23:10 ` Tom Rini
2022-07-23 9:48 ` Pali Rohár
0 siblings, 1 reply; 32+ messages in thread
From: Tom Rini @ 2022-07-08 23:10 UTC (permalink / raw)
To: Pali Rohár, Peng Fan (OSS)
Cc: Peng Fan (OSS),
Priyanka Jain, Qiang Zhao, Shengzhou Liu, Sinan Akman, u-boot
[-- Attachment #1: Type: text/plain, Size: 3168 bytes --]
On Sat, Jul 09, 2022 at 12:49:27AM +0200, Pali Rohár wrote:
> PING?
>
> How many times you would ask me to again rebase this patch??
>
> On Sunday 03 July 2022 14:39:13 Pali Rohár wrote:
> > On Thursday 23 June 2022 15:04:08 Pali Rohár wrote:
> > > On Thursday 16 June 2022 14:37:07 Pali Rohár wrote:
> > > > On some boards upper 4 bits of i2c boot input data (register 0) are
> > > > inverted. Information which bits are inverted is stored in register 2.
> > > >
> > > > So invert read input data back according to register 2 prior processing
> > > > them. This fixes printing "rom_loc: value" line during booting.
> > > >
> > > > Signed-off-by: Pali Rohár <pali@kernel.org>
> > > > ---
> > > > Changes in v3:
> > > > * Rebased on top of the U-Boot next branch, commit a87a6fcd20c0e29fe55bfbb6917c4aa1f1bbce74
> > >
> > > PING?
> >
> > PING?
> >
> > > > Changes in v2:
> > > > * Use register 2 for detecting which bits needs to be inverted
> > > > ---
> > > > board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 6 ++++--
> > > > 1 file changed, 4 insertions(+), 2 deletions(-)
> > > >
> > > > diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
> > > > index 6665aa4ba94e..d36306f35427 100644
> > > > --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
> > > > +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
> > > > @@ -174,7 +174,7 @@ int checkboard(void)
> > > > {
> > > > struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
> > > > ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
> > > > - u8 in, out, io_config, val;
> > > > + u8 in, out, invert, io_config, val;
> > > > int bus_num = CONFIG_SYS_SPD_BUS_NUM;
> > > >
> > > > /* FIXME: This should just use the model from the device tree or similar */
> > > > @@ -198,6 +198,7 @@ int checkboard(void)
> > > >
> > > > if (dm_i2c_read(dev, 0, &in, 1) < 0 ||
> > > > dm_i2c_read(dev, 1, &out, 1) < 0 ||
> > > > + dm_i2c_read(dev, 2, &invert, 1) < 0 ||
> > > > dm_i2c_read(dev, 3, &io_config, 1) < 0) {
> > > > printf("Error reading i2c boot information!\n");
> > > > return 0; /* Don't want to hang() on this error */
> > > > @@ -207,13 +208,14 @@ int checkboard(void)
> > > >
> > > > if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 ||
> > > > i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 ||
> > > > + i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 2, 1, &invert, 1) < 0 ||
> > > > i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 3, 1, &io_config, 1) < 0) {
> > > > printf("Error reading i2c boot information!\n");
> > > > return 0; /* Don't want to hang() on this error */
> > > > }
> > > > #endif
> > > >
> > > > - val = (in & io_config) | (out & (~io_config));
> > > > + val = ((in ^ invert) & io_config) | (out & (~io_config));
> > > >
> > > > puts("rom_loc: ");
> > > > if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD) {
Peng, this patch doesn't apply currently but also looks fairly obvious
to adapt to top of tree. Please just make it apply when you pick this
up, thanks.
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH v3] board: freescale: p1_p2_rdb_pc: Fix parsing inverted bits from boot input data
2022-07-08 23:10 ` Tom Rini
@ 2022-07-23 9:48 ` Pali Rohár
0 siblings, 0 replies; 32+ messages in thread
From: Pali Rohár @ 2022-07-23 9:48 UTC (permalink / raw)
To: Tom Rini, Peng Fan (OSS)
Cc: Priyanka Jain, Qiang Zhao, Shengzhou Liu, Sinan Akman, u-boot
On Friday 08 July 2022 19:10:26 Tom Rini wrote:
> On Sat, Jul 09, 2022 at 12:49:27AM +0200, Pali Rohár wrote:
> > PING?
> >
> > How many times you would ask me to again rebase this patch??
> >
> > On Sunday 03 July 2022 14:39:13 Pali Rohár wrote:
> > > On Thursday 23 June 2022 15:04:08 Pali Rohár wrote:
> > > > On Thursday 16 June 2022 14:37:07 Pali Rohár wrote:
> > > > > On some boards upper 4 bits of i2c boot input data (register 0) are
> > > > > inverted. Information which bits are inverted is stored in register 2.
> > > > >
> > > > > So invert read input data back according to register 2 prior processing
> > > > > them. This fixes printing "rom_loc: value" line during booting.
> > > > >
> > > > > Signed-off-by: Pali Rohár <pali@kernel.org>
> > > > > ---
> > > > > Changes in v3:
> > > > > * Rebased on top of the U-Boot next branch, commit a87a6fcd20c0e29fe55bfbb6917c4aa1f1bbce74
> > > >
> > > > PING?
> > >
> > > PING?
> > >
> > > > > Changes in v2:
> > > > > * Use register 2 for detecting which bits needs to be inverted
> > > > > ---
> > > > > board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 6 ++++--
> > > > > 1 file changed, 4 insertions(+), 2 deletions(-)
> > > > >
> > > > > diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
> > > > > index 6665aa4ba94e..d36306f35427 100644
> > > > > --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
> > > > > +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
> > > > > @@ -174,7 +174,7 @@ int checkboard(void)
> > > > > {
> > > > > struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
> > > > > ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
> > > > > - u8 in, out, io_config, val;
> > > > > + u8 in, out, invert, io_config, val;
> > > > > int bus_num = CONFIG_SYS_SPD_BUS_NUM;
> > > > >
> > > > > /* FIXME: This should just use the model from the device tree or similar */
> > > > > @@ -198,6 +198,7 @@ int checkboard(void)
> > > > >
> > > > > if (dm_i2c_read(dev, 0, &in, 1) < 0 ||
> > > > > dm_i2c_read(dev, 1, &out, 1) < 0 ||
> > > > > + dm_i2c_read(dev, 2, &invert, 1) < 0 ||
> > > > > dm_i2c_read(dev, 3, &io_config, 1) < 0) {
> > > > > printf("Error reading i2c boot information!\n");
> > > > > return 0; /* Don't want to hang() on this error */
> > > > > @@ -207,13 +208,14 @@ int checkboard(void)
> > > > >
> > > > > if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 ||
> > > > > i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 ||
> > > > > + i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 2, 1, &invert, 1) < 0 ||
> > > > > i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 3, 1, &io_config, 1) < 0) {
> > > > > printf("Error reading i2c boot information!\n");
> > > > > return 0; /* Don't want to hang() on this error */
> > > > > }
> > > > > #endif
> > > > >
> > > > > - val = (in & io_config) | (out & (~io_config));
> > > > > + val = ((in ^ invert) & io_config) | (out & (~io_config));
> > > > >
> > > > > puts("rom_loc: ");
> > > > > if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD) {
>
> Peng, this patch doesn't apply currently but also looks fairly obvious
> to adapt to top of tree. Please just make it apply when you pick this
> up, thanks.
>
> --
> Tom
June 16 I got message that this patch does not apply:
https://lore.kernel.org/u-boot/8d8a6be1-6033-5771-0e0e-f51de1488e69@oss.nxp.com/
Just few hours later I sent rebased patch which applied cleanly:
https://lore.kernel.org/u-boot/20220616123707.8562-1-pali@kernel.org/
And since June 16 I have not received any reply.
Guys, why you are asking me for rebasing patches and then you do not
care about them and wait until they do not apply again?
I was asked to remind pending patches -- I have did it more times and I
got absolutely no response. Now is July 23.
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 04/11] board: freescale: p1_p2_rdb_pc: Do not set MPC85xx_PMUXCR_SDHC_WP bit when SDHC_WP is used as GPIO
2022-04-07 10:16 [PATCH 00/11] board: freescale: p1_p2_rdb_pc: Various cleanups and fixes Pali Rohár
` (2 preceding siblings ...)
2022-04-07 10:16 ` [PATCH 03/11] board: freescale: p1_p2_rdb_pc: Fix parsing negated upper 4 bits from boot input data Pali Rohár
@ 2022-04-07 10:16 ` Pali Rohár
2022-04-07 10:16 ` [PATCH 05/11] board: freescale: p1_p2_rdb_pc: Fix page attributes for second 1G SDRAM map Pali Rohár
` (6 subsequent siblings)
10 siblings, 0 replies; 32+ messages in thread
From: Pali Rohár @ 2022-04-07 10:16 UTC (permalink / raw)
To: Priyanka Jain, Qiang Zhao, Shengzhou Liu, Sinan Akman; +Cc: u-boot
When MPC85xx_PMUXCR_SDHC_WP is set then SDHC controller automatically makes
inserted SD card readonly if GPIO[9] is active.
In some design GPIO[9] pin does not have to be connected to SD card
write-protect pin and can be used as GPIO.
So do not set MPC85xx_PMUXCR_SDHC_WP bit when GPIO[9] is not used for
SDHC_WP functionality.
Signed-off-by: Pali Rohár <pali@kernel.org>
---
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 766a82386079..fc581bdb2a40 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -147,8 +147,10 @@ int board_early_init_f(void)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- setbits_be32(&gur->pmuxcr,
- (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
+ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SDHC_CD);
+#ifndef SDHC_WP_IS_GPIO
+ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SDHC_WP);
+#endif
clrbits_be32(&gur->sdhcdcr, SDHCDCR_CD_INV);
clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
--
2.20.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 05/11] board: freescale: p1_p2_rdb_pc: Fix page attributes for second 1G SDRAM map
2022-04-07 10:16 [PATCH 00/11] board: freescale: p1_p2_rdb_pc: Various cleanups and fixes Pali Rohár
` (3 preceding siblings ...)
2022-04-07 10:16 ` [PATCH 04/11] board: freescale: p1_p2_rdb_pc: Do not set MPC85xx_PMUXCR_SDHC_WP bit when SDHC_WP is used as GPIO Pali Rohár
@ 2022-04-07 10:16 ` Pali Rohár
2022-04-07 10:16 ` [PATCH 06/11] board: freescale: p1_p2_rdb_pc: Move ifdef for USB/eLBC check to correct place Pali Rohár
` (5 subsequent siblings)
10 siblings, 0 replies; 32+ messages in thread
From: Pali Rohár @ 2022-04-07 10:16 UTC (permalink / raw)
To: Priyanka Jain, Qiang Zhao, Shengzhou Liu, Sinan Akman; +Cc: u-boot
Like for first 1G SDRAM map, do not enable Caching-inhibited nor Guarded
attribute for second 1G SDRAM mapping. Whole 2G SDRAM should use caches and
also allow speculative loading (by not setting Guarded attribute).
Also enable Memory Coherency attribute for second 1G SDRAM map. In commit
316f0d0f8f3c ("powerpc: mpc85xx: Fix static TLB table for SDRAM") it was
enabled for all SDRAM maps on all other boards, just missed this one case.
As a last thing, first 1G SDRAM map has wrong comment, so adjust it.
Signed-off-by: Pali Rohár <pali@kernel.org>
---
board/freescale/p1_p2_rdb_pc/tlb.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c
index fcd7a55199f0..5931ec650bd8 100644
--- a/board/freescale/p1_p2_rdb_pc/tlb.c
+++ b/board/freescale/p1_p2_rdb_pc/tlb.c
@@ -79,16 +79,16 @@ struct fsl_e_tlb_entry tlb_table[] = {
#if defined(CONFIG_SYS_RAMBOOT) || \
(defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
- /* *I*G - eSDHC/eSPI/NAND boot */
+ /* **M** - 1G DDR for eSDHC/eSPI/NAND boot */
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 8, BOOKE_PAGESZ_1G, 1),
#if defined(CONFIG_TARGET_P1020RDB_PD)
- /* 2G DDR on P1020MBG, map the second 1G */
+ /* **M** - 2G DDR on P1020MBG, map the second 1G */
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 9, BOOKE_PAGESZ_1G, 1),
#endif
#endif /* RAMBOOT/SPL */
--
2.20.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 06/11] board: freescale: p1_p2_rdb_pc: Move ifdef for USB/eLBC check to correct place
2022-04-07 10:16 [PATCH 00/11] board: freescale: p1_p2_rdb_pc: Various cleanups and fixes Pali Rohár
` (4 preceding siblings ...)
2022-04-07 10:16 ` [PATCH 05/11] board: freescale: p1_p2_rdb_pc: Fix page attributes for second 1G SDRAM map Pali Rohár
@ 2022-04-07 10:16 ` Pali Rohár
2022-04-07 10:16 ` [PATCH 07/11] board: freescale: p1_p2_rdb_pc: Fix env $vscfw_addr Pali Rohár
` (4 subsequent siblings)
10 siblings, 0 replies; 32+ messages in thread
From: Pali Rohár @ 2022-04-07 10:16 UTC (permalink / raw)
To: Priyanka Jain, Qiang Zhao, Shengzhou Liu, Sinan Akman; +Cc: u-boot
Whole section about USB/eLBC configuration seems to be P1020 specific. So
add ifdefs to not compile it on other platforms (e.g. P2020).
Signed-off-by: Pali Rohár <pali@kernel.org>
---
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index fc581bdb2a40..1b28f1bbc776 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -354,9 +354,9 @@ int ft_board_setup(void *blob, struct bd_info *bd)
#if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC)
const char *soc_usb_compat = "fsl-usb2-dr";
int usb_err, usb1_off, usb2_off;
-#endif
#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
int err;
+#endif
#endif
ft_cpu_setup(blob, bd);
@@ -375,6 +375,7 @@ int ft_board_setup(void *blob, struct bd_info *bd)
fsl_fdt_fixup_dr_usb(blob, bd);
#endif
+#if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC)
#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
/* Delete eLBC node as it is muxed with USB2 controller */
if (hwconfig("usb2")) {
@@ -396,7 +397,6 @@ int ft_board_setup(void *blob, struct bd_info *bd)
}
#endif
-#if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC)
/* Delete USB2 node as it is muxed with eLBC */
usb1_off = fdt_node_offset_by_compatible(blob, -1,
soc_usb_compat);
--
2.20.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 07/11] board: freescale: p1_p2_rdb_pc: Fix env $vscfw_addr
2022-04-07 10:16 [PATCH 00/11] board: freescale: p1_p2_rdb_pc: Various cleanups and fixes Pali Rohár
` (5 preceding siblings ...)
2022-04-07 10:16 ` [PATCH 06/11] board: freescale: p1_p2_rdb_pc: Move ifdef for USB/eLBC check to correct place Pali Rohár
@ 2022-04-07 10:16 ` Pali Rohár
2022-04-07 10:16 ` [PATCH 08/11] board: freescale: p1_p2_rdb_pc: Use named macros for i2c bus num and address Pali Rohár
` (3 subsequent siblings)
10 siblings, 0 replies; 32+ messages in thread
From: Pali Rohár @ 2022-04-07 10:16 UTC (permalink / raw)
To: Priyanka Jain, Qiang Zhao, Shengzhou Liu, Sinan Akman; +Cc: u-boot
Do not stringify env $vscfw_addr two times (once implicitly via string
operator "" and second time explicitly via __stringify() macro) and allow
to compile U-Boot without CONFIG_VSC7385_ENET (when __VSCFW_ADDR was not
defined and so macro name was stringified into CONFIG_EXTRA_ENV_SETTINGS).
Signed-off-by: Pali Rohár <pali@kernel.org>
---
include/configs/p1_p2_rdb_pc.h | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index ecc6e0c644bf..7b5a8dd9e509 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -351,7 +351,7 @@
/* Vsc7385 switch */
#ifdef CONFIG_VSC7385_ENET
-#define __VSCFW_ADDR "vscfw_addr=ef000000"
+#define __VSCFW_ADDR "vscfw_addr=ef000000\0"
#define CONFIG_SYS_VSC7385_BASE 0xffb00000
#ifdef CONFIG_PHYS_64BIT
@@ -370,6 +370,10 @@
#define CONFIG_VSC7385_IMAGE_SIZE 8192
#endif
+#ifndef __VSCFW_ADDR
+#define __VSCFW_ADDR ""
+#endif
+
/*
* Config the L2 Cache as L2 SRAM
*/
@@ -614,7 +618,7 @@ i2c mw 18 3 __SW_BOOT_MASK 1; reset
"ramdisk_size=120000\0" \
"map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
"map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
-__stringify(__VSCFW_ADDR)"\0" \
+__VSCFW_ADDR \
__stringify(__NOR_RST_CMD)"\0" \
__stringify(__SPI_RST_CMD)"\0" \
__stringify(__SD_RST_CMD)"\0" \
--
2.20.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 08/11] board: freescale: p1_p2_rdb_pc: Use named macros for i2c bus num and address
2022-04-07 10:16 [PATCH 00/11] board: freescale: p1_p2_rdb_pc: Various cleanups and fixes Pali Rohár
` (6 preceding siblings ...)
2022-04-07 10:16 ` [PATCH 07/11] board: freescale: p1_p2_rdb_pc: Fix env $vscfw_addr Pali Rohár
@ 2022-04-07 10:16 ` Pali Rohár
2022-04-07 10:16 ` [PATCH 09/11] board: freescale: p1_p2_rdb_pc: Define SW macros for lower and upper NOR banks Pali Rohár
` (2 subsequent siblings)
10 siblings, 0 replies; 32+ messages in thread
From: Pali Rohár @ 2022-04-07 10:16 UTC (permalink / raw)
To: Priyanka Jain, Qiang Zhao, Shengzhou Liu, Sinan Akman; +Cc: u-boot
Replace hardcoded boot i2c bus num and address by existing macros when
generating env for CONFIG_EXTRA_ENV_SETTINGS.
Same macros are used in U-Boot board code when reading information from
boot i2c data.
Signed-off-by: Pali Rohár <pali@kernel.org>
---
include/configs/p1_p2_rdb_pc.h | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 7b5a8dd9e509..cb3b1a1da05d 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -568,28 +568,28 @@
#ifdef __SW_BOOT_NOR
#define __NOR_RST_CMD \
-norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
-i2c mw 18 3 __SW_BOOT_MASK 1; reset
+norboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_NOR 1; \
+i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
#endif
#ifdef __SW_BOOT_SPI
#define __SPI_RST_CMD \
-spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
-i2c mw 18 3 __SW_BOOT_MASK 1; reset
+spiboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_SPI 1; \
+i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
#endif
#ifdef __SW_BOOT_SD
#define __SD_RST_CMD \
-sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
-i2c mw 18 3 __SW_BOOT_MASK 1; reset
+sdboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_SD 1; \
+i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
#endif
#ifdef __SW_BOOT_NAND
#define __NAND_RST_CMD \
-nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
-i2c mw 18 3 __SW_BOOT_MASK 1; reset
+nandboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_NAND 1; \
+i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
#endif
#ifdef __SW_BOOT_PCIE
#define __PCIE_RST_CMD \
-pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
-i2c mw 18 3 __SW_BOOT_MASK 1; reset
+pciboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_PCIE 1; \
+i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
@@ -616,9 +616,9 @@ i2c mw 18 3 __SW_BOOT_MASK 1; reset
"nandbootaddr=100000\0" \
"nandfdtaddr=80000\0" \
"ramdisk_size=120000\0" \
-"map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
-"map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
__VSCFW_ADDR \
+"map_lowernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 02 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 fd 1\0" \
+"map_uppernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 00 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 fd 1\0" \
__stringify(__NOR_RST_CMD)"\0" \
__stringify(__SPI_RST_CMD)"\0" \
__stringify(__SD_RST_CMD)"\0" \
--
2.20.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 09/11] board: freescale: p1_p2_rdb_pc: Define SW macros for lower and upper NOR banks
2022-04-07 10:16 [PATCH 00/11] board: freescale: p1_p2_rdb_pc: Various cleanups and fixes Pali Rohár
` (7 preceding siblings ...)
2022-04-07 10:16 ` [PATCH 08/11] board: freescale: p1_p2_rdb_pc: Use named macros for i2c bus num and address Pali Rohár
@ 2022-04-07 10:16 ` Pali Rohár
2022-04-07 10:16 ` [PATCH 10/11] board: freescale: p1_p2_rdb_pc: Move BootROM change source macros to p1_p2_bootrom.h Pali Rohár
2022-04-07 10:16 ` [PATCH 11/11] board: freescale: p1_p2_rdb_pc: Add env commands norlowerboot, norupperboot, sd2boot and defboot Pali Rohár
10 siblings, 0 replies; 32+ messages in thread
From: Pali Rohár @ 2022-04-07 10:16 UTC (permalink / raw)
To: Priyanka Jain, Qiang Zhao, Shengzhou Liu, Sinan Akman; +Cc: u-boot
Replace hardcoded i2c hex values for NOR banks by named SW macros in
map_lowernorbank/map_uppernorbank env commands.
Signed-off-by: Pali Rohár <pali@kernel.org>
---
include/configs/p1_p2_rdb_pc.h | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index cb3b1a1da05d..995bd983cef1 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -22,6 +22,9 @@
#define __SW_BOOT_SD 0x9c
#define __SW_BOOT_NAND 0xec
#define __SW_BOOT_PCIE 0x6c
+#define __SW_NOR_BANK_MASK 0xfd
+#define __SW_NOR_BANK_UP 0x00
+#define __SW_NOR_BANK_LO 0x02
#define CONFIG_SYS_L2_SIZE (256 << 10)
#endif
@@ -48,6 +51,9 @@
#define __SW_BOOT_SD 0x24
#define __SW_BOOT_NAND 0x44
#define __SW_BOOT_PCIE 0x74
+#define __SW_NOR_BANK_MASK 0xfd
+#define __SW_NOR_BANK_UP 0x00
+#define __SW_NOR_BANK_LO 0x02
#define CONFIG_SYS_L2_SIZE (256 << 10)
/*
* Dynamic MTD Partition support with mtdparts
@@ -64,6 +70,9 @@
#define __SW_BOOT_SD2 0x18
#define __SW_BOOT_NAND 0xe8
#define __SW_BOOT_PCIE 0xa8
+#define __SW_NOR_BANK_MASK 0xfd
+#define __SW_NOR_BANK_UP 0x00
+#define __SW_NOR_BANK_LO 0x02
#define CONFIG_SYS_L2_SIZE (512 << 10)
/*
* Dynamic MTD Partition support with mtdparts
@@ -617,8 +626,8 @@ i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
"nandfdtaddr=80000\0" \
"ramdisk_size=120000\0" \
__VSCFW_ADDR \
-"map_lowernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 02 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 fd 1\0" \
-"map_uppernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 00 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 fd 1\0" \
+"map_lowernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 "__stringify(__SW_NOR_BANK_LO)" 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 "__stringify(__SW_NOR_BANK_MASK)" 1\0" \
+"map_uppernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 "__stringify(__SW_NOR_BANK_UP)" 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 "__stringify(__SW_NOR_BANK_MASK)" 1\0" \
__stringify(__NOR_RST_CMD)"\0" \
__stringify(__SPI_RST_CMD)"\0" \
__stringify(__SD_RST_CMD)"\0" \
--
2.20.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 10/11] board: freescale: p1_p2_rdb_pc: Move BootROM change source macros to p1_p2_bootrom.h
2022-04-07 10:16 [PATCH 00/11] board: freescale: p1_p2_rdb_pc: Various cleanups and fixes Pali Rohár
` (8 preceding siblings ...)
2022-04-07 10:16 ` [PATCH 09/11] board: freescale: p1_p2_rdb_pc: Define SW macros for lower and upper NOR banks Pali Rohár
@ 2022-04-07 10:16 ` Pali Rohár
2022-04-25 14:48 ` [PATCH v2] board: freescale: p1_p2_rdb_pc: Move boot reset macros to p1_p2_bootsrc.h Pali Rohár
2022-04-07 10:16 ` [PATCH 11/11] board: freescale: p1_p2_rdb_pc: Add env commands norlowerboot, norupperboot, sd2boot and defboot Pali Rohár
10 siblings, 1 reply; 32+ messages in thread
From: Pali Rohár @ 2022-04-07 10:16 UTC (permalink / raw)
To: Priyanka Jain, Qiang Zhao, Shengzhou Liu, Sinan Akman; +Cc: u-boot
Code for changing BootROM source is platform generic and can be used by any
P1* and P2* compatible board. Not only by RDB boards which use config
header file p1_p2_rdb_pc.h.
So move this code from p1_p2_rdb_pc.h to p1_p2_bootrom.h and cleanup macros
for generating boot source env variables in CONFIG_EXTRA_ENV_SETTINGS.
This allows to use code for changing BootROM source also by other boards in
future.
Signed-off-by: Pali Rohár <pali@kernel.org>
---
include/configs/p1_p2_bootrom.h | 32 +++++++++++++++
include/configs/p1_p2_rdb_pc.h | 73 +++++++++++++++++++++------------
2 files changed, 78 insertions(+), 27 deletions(-)
create mode 100644 include/configs/p1_p2_bootrom.h
diff --git a/include/configs/p1_p2_bootrom.h b/include/configs/p1_p2_bootrom.h
new file mode 100644
index 000000000000..a1f61b788cf7
--- /dev/null
+++ b/include/configs/p1_p2_bootrom.h
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0+
+// (C) 2022 Pali Rohár <pali@kernel.org>
+
+#define CHANGE_BOOTROM_SOURCE_CMD(SOURCE, MASK) i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 SOURCE 1; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 MASK 1
+
+#ifdef __SW_NOR_BANK_LO
+#define CHANGE_BOOTROM_LOWER_NOR_BANK_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_NOR_BANK_LO, __SW_NOR_BANK_MASK)
+#endif
+
+#ifdef __SW_NOR_BANK_UP
+#define CHANGE_BOOTROM_UPPER_NOR_BANK_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_NOR_BANK_UP, __SW_NOR_BANK_MASK)
+#endif
+
+#ifdef __SW_BOOT_NOR
+#define CHANGE_BOOTROM_SOURCE_DEF_NOR_BANK_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_NOR, __SW_BOOT_MASK)
+#endif
+
+#ifdef __SW_BOOT_SPI
+#define CHANGE_BOOTROM_SOURCE_SPI_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_SPI, __SW_BOOT_MASK)
+#endif
+
+#ifdef __SW_BOOT_SD
+#define CHANGE_BOOTROM_SOURCE_SD_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_SD, __SW_BOOT_MASK)
+#endif
+
+#ifdef __SW_BOOT_NAND
+#define CHANGE_BOOTROM_SOURCE_NAND_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_NAND, __SW_BOOT_MASK)
+#endif
+
+#ifdef __SW_BOOT_PCIE
+#define CHANGE_BOOTROM_SOURCE_PCIE_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_PCIE, __SW_BOOT_MASK)
+#endif
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 995bd983cef1..d41b31081017 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -79,6 +79,8 @@
*/
#endif
+#include "p1_p2_bootrom.h"
+
#ifdef CONFIG_SDCARD
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
@@ -575,30 +577,46 @@
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
-#ifdef __SW_BOOT_NOR
-#define __NOR_RST_CMD \
-norboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_NOR 1; \
-i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
+#ifdef CHANGE_BOOTROM_LOWER_NOR_BANK_CMD
+#define __MAP_NOR_LOWER_CMD "map_lowernorbank="__stringify(CHANGE_BOOTROM_LOWER_NOR_BANK_CMD)"\0"
+#else
+#define __MAP_NOR_LOWER_CMD ""
+#endif
+
+#ifdef CHANGE_BOOTROM_UPPER_NOR_BANK_CMD
+#define __MAP_NOR_UPPER_CMD "map_uppernorbank="__stringify(CHANGE_BOOTROM_UPPER_NOR_BANK_CMD)"\0"
+#else
+#define __MAP_NOR_UPPER_CMD ""
+#endif
+
+#ifdef CHANGE_BOOTROM_SOURCE_DEF_NOR_BANK_CMD
+#define __NOR_RST_CMD "norboot="__stringify(CHANGE_BOOTROM_SOURCE_DEF_NOR_BANK_CMD)"; reset\0"
+#else
+#define __NOR_RST_CMD ""
#endif
-#ifdef __SW_BOOT_SPI
-#define __SPI_RST_CMD \
-spiboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_SPI 1; \
-i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
+
+#ifdef CHANGE_BOOTROM_SOURCE_SPI_CMD
+#define __SPI_RST_CMD "spiboot="__stringify(CHANGE_BOOTROM_SOURCE_SPI_CMD)"; reset\0"
+#else
+#define __SPI_RST_CMD ""
#endif
-#ifdef __SW_BOOT_SD
-#define __SD_RST_CMD \
-sdboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_SD 1; \
-i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
+
+#ifdef CHANGE_BOOTROM_SOURCE_SD_CMD
+#define __SD_RST_CMD "sdboot="__stringify(CHANGE_BOOTROM_SOURCE_SD_CMD)"; reset\0"
+#else
+#define __SD_RST_CMD ""
#endif
-#ifdef __SW_BOOT_NAND
-#define __NAND_RST_CMD \
-nandboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_NAND 1; \
-i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
+
+#ifdef CHANGE_BOOTROM_SOURCE_NAND_CMD
+#define __NAND_RST_CMD "nandboot="__stringify(CHANGE_BOOTROM_SOURCE_NAND_CMD)"; reset\0"
+#else
+#define __NAND_RST_CMD ""
#endif
-#ifdef __SW_BOOT_PCIE
-#define __PCIE_RST_CMD \
-pciboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_PCIE 1; \
-i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
+
+#ifdef CHANGE_BOOTROM_SOURCE_PCIE_CMD
+#define __PCIE_RST_CMD "pciboot="__stringify(CHANGE_BOOTROM_SOURCE_PCIE_CMD)"; reset\0"
+#else
+#define __PCIE_RST_CMD ""
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
@@ -626,13 +644,14 @@ i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
"nandfdtaddr=80000\0" \
"ramdisk_size=120000\0" \
__VSCFW_ADDR \
-"map_lowernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 "__stringify(__SW_NOR_BANK_LO)" 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 "__stringify(__SW_NOR_BANK_MASK)" 1\0" \
-"map_uppernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 "__stringify(__SW_NOR_BANK_UP)" 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 "__stringify(__SW_NOR_BANK_MASK)" 1\0" \
-__stringify(__NOR_RST_CMD)"\0" \
-__stringify(__SPI_RST_CMD)"\0" \
-__stringify(__SD_RST_CMD)"\0" \
-__stringify(__NAND_RST_CMD)"\0" \
-__stringify(__PCIE_RST_CMD)"\0"
+__MAP_NOR_LOWER_CMD \
+__MAP_NOR_UPPER_CMD \
+__NOR_RST_CMD \
+__SPI_RST_CMD \
+__SD_RST_CMD \
+__NAND_RST_CMD \
+__PCIE_RST_CMD \
+""
#define CONFIG_USB_FAT_BOOT \
"setenv bootargs root=/dev/ram rw " \
--
2.20.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v2] board: freescale: p1_p2_rdb_pc: Move boot reset macros to p1_p2_bootsrc.h
2022-04-07 10:16 ` [PATCH 10/11] board: freescale: p1_p2_rdb_pc: Move BootROM change source macros to p1_p2_bootrom.h Pali Rohár
@ 2022-04-25 14:48 ` Pali Rohár
2022-05-26 6:08 ` Priyanka Jain (OSS)
0 siblings, 1 reply; 32+ messages in thread
From: Pali Rohár @ 2022-04-25 14:48 UTC (permalink / raw)
To: Priyanka Jain, Qiang Zhao, Shengzhou Liu, Sinan Akman; +Cc: u-boot
Code for changing boot source is platform generic and can be used by any
P1* and P2* compatible RDB board. Not only by boards which use config
header file p1_p2_rdb_pc.h.
So move this code from p1_p2_rdb_pc.h to p1_p2_bootsrc.h and cleanup macros
for generating boot source env variables in CONFIG_EXTRA_ENV_SETTINGS.
This allows to use code for resetting board and rebooting to other boot
source also by other boards in future.
Signed-off-by: Pali Rohár <pali@kernel.org>
---
Changes in v2:
* Fix commit message
* Move macros to file p1_p2_bootsrc.h
* Rewrite macros even more to be more generic and use them without custom
macros in p1_p2_rdb_pc.h
---
include/configs/p1_p2_bootsrc.h | 55 +++++++++++++++++++++++++++++++++
include/configs/p1_p2_rdb_pc.h | 41 ++++++------------------
2 files changed, 64 insertions(+), 32 deletions(-)
create mode 100644 include/configs/p1_p2_bootsrc.h
diff --git a/include/configs/p1_p2_bootsrc.h b/include/configs/p1_p2_bootsrc.h
new file mode 100644
index 000000000000..a274c57786f5
--- /dev/null
+++ b/include/configs/p1_p2_bootsrc.h
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+
+// (C) 2022 Pali Rohár <pali@kernel.org>
+
+#include <linux/stringify.h>
+
+#if !defined(CONFIG_SYS_SPD_BUS_NUM) || !defined(CONFIG_SYS_I2C_PCA9557_ADDR)
+#error "CONFIG_SYS_SPD_BUS_NUM and CONFIG_SYS_I2C_PCA9557_ADDR are required"
+#endif
+
+#define __BOOTSRC_CMD(src, msk) i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 src 1; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 msk 1
+
+#define __VAR_CMD(var, cmd) __stringify(var=cmd\0)
+#define __VAR_CMD_RST(var, cmd) __VAR_CMD(var, cmd; reset)
+
+#ifdef __SW_NOR_BANK_LO
+#define MAP_NOR_LO_CMD(var, ...) __VAR_CMD(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_NOR_BANK_LO, __SW_NOR_BANK_MASK))
+#else
+#define MAP_NOR_LO_CMD(var, ...) ""
+#endif
+
+#ifdef __SW_NOR_BANK_UP
+#define MAP_NOR_UP_CMD(var, ...) __VAR_CMD(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_NOR_BANK_UP, __SW_NOR_BANK_MASK))
+#else
+#define MAP_NOR_UP_CMD(var, ...) ""
+#endif
+
+#ifdef __SW_BOOT_NOR
+#define RST_NOR_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_NOR, __SW_BOOT_MASK))
+#else
+#define RST_NOR_CMD(var, ...) ""
+#endif
+
+#ifdef __SW_BOOT_SPI
+#define RST_SPI_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_SPI, __SW_BOOT_MASK))
+#else
+#define RST_SPI_CMD(var, ...) ""
+#endif
+
+#ifdef __SW_BOOT_SD
+#define RST_SD_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_SD, __SW_BOOT_MASK))
+#else
+#define RST_SD_CMD(var, ...) ""
+#endif
+
+#ifdef __SW_BOOT_NAND
+#define RST_NAND_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_NAND, __SW_BOOT_MASK))
+#else
+#define RST_NAND_CMD(var, ...) ""
+#endif
+
+#ifdef __SW_BOOT_PCIE
+#define RST_PCIE_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_PCIE, __SW_BOOT_MASK))
+#else
+#define RST_PCIE_CMD(var, ...) ""
+#endif
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 995bd983cef1..47bd20eeeafb 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -575,31 +575,7 @@
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
-#ifdef __SW_BOOT_NOR
-#define __NOR_RST_CMD \
-norboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_NOR 1; \
-i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
-#endif
-#ifdef __SW_BOOT_SPI
-#define __SPI_RST_CMD \
-spiboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_SPI 1; \
-i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
-#endif
-#ifdef __SW_BOOT_SD
-#define __SD_RST_CMD \
-sdboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_SD 1; \
-i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
-#endif
-#ifdef __SW_BOOT_NAND
-#define __NAND_RST_CMD \
-nandboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_NAND 1; \
-i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
-#endif
-#ifdef __SW_BOOT_PCIE
-#define __PCIE_RST_CMD \
-pciboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_PCIE 1; \
-i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
-#endif
+#include "p1_p2_bootsrc.h"
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
@@ -626,13 +602,14 @@ i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
"nandfdtaddr=80000\0" \
"ramdisk_size=120000\0" \
__VSCFW_ADDR \
-"map_lowernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 "__stringify(__SW_NOR_BANK_LO)" 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 "__stringify(__SW_NOR_BANK_MASK)" 1\0" \
-"map_uppernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 "__stringify(__SW_NOR_BANK_UP)" 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 "__stringify(__SW_NOR_BANK_MASK)" 1\0" \
-__stringify(__NOR_RST_CMD)"\0" \
-__stringify(__SPI_RST_CMD)"\0" \
-__stringify(__SD_RST_CMD)"\0" \
-__stringify(__NAND_RST_CMD)"\0" \
-__stringify(__PCIE_RST_CMD)"\0"
+MAP_NOR_LO_CMD(map_lowernorbank) \
+MAP_NOR_UP_CMD(map_uppernorbank) \
+RST_NOR_CMD(norboot) \
+RST_SPI_CMD(spiboot) \
+RST_SD_CMD(sdboot) \
+RST_NAND_CMD(nandboot) \
+RST_PCIE_CMD(pciboot) \
+""
#define CONFIG_USB_FAT_BOOT \
"setenv bootargs root=/dev/ram rw " \
--
2.20.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* RE: [PATCH v2] board: freescale: p1_p2_rdb_pc: Move boot reset macros to p1_p2_bootsrc.h
2022-04-25 14:48 ` [PATCH v2] board: freescale: p1_p2_rdb_pc: Move boot reset macros to p1_p2_bootsrc.h Pali Rohár
@ 2022-05-26 6:08 ` Priyanka Jain (OSS)
2022-05-26 8:32 ` Pali Rohár
0 siblings, 1 reply; 32+ messages in thread
From: Priyanka Jain (OSS) @ 2022-05-26 6:08 UTC (permalink / raw)
To: Pali Rohár, Qiang Zhao, Shengzhou Liu, Sinan Akman; +Cc: u-boot
>-----Original Message-----
>From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Pali Rohár
>Sent: Monday, April 25, 2022 8:18 PM
>To: Priyanka Jain <priyanka.jain@nxp.com>; Qiang Zhao <qiang.zhao@nxp.com>;
>Shengzhou Liu <shengzhou.liu@nxp.com>; Sinan Akman <sinan@writeme.com>
>Cc: u-boot@lists.denx.de
>Subject: [PATCH v2] board: freescale: p1_p2_rdb_pc: Move boot reset macros to
>p1_p2_bootsrc.h
>
>Code for changing boot source is platform generic and can be used by any
>P1* and P2* compatible RDB board. Not only by boards which use config header
>file p1_p2_rdb_pc.h.
>
>So move this code from p1_p2_rdb_pc.h to p1_p2_bootsrc.h and cleanup macros
>for generating boot source env variables in CONFIG_EXTRA_ENV_SETTINGS.
>
>This allows to use code for resetting board and rebooting to other boot source
>also by other boards in future.
>
>Signed-off-by: Pali Rohár <pali@kernel.org>
>---
>Changes in v2:
>* Fix commit message
>* Move macros to file p1_p2_bootsrc.h
>* Rewrite macros even more to be more generic and use them without custom
> macros in p1_p2_rdb_pc.h
>---
> include/configs/p1_p2_bootsrc.h | 55 +++++++++++++++++++++++++++++++++
>include/configs/p1_p2_rdb_pc.h | 41 ++++++------------------
> 2 files changed, 64 insertions(+), 32 deletions(-) create mode 100644
>include/configs/p1_p2_bootsrc.h
>
>diff --git a/include/configs/p1_p2_bootsrc.h b/include/configs/p1_p2_bootsrc.h
>new file mode 100644 index 000000000000..a274c57786f5
>--- /dev/null
>+++ b/include/configs/p1_p2_bootsrc.h
>@@ -0,0 +1,55 @@
>+// SPDX-License-Identifier: GPL-2.0+
>+// (C) 2022 Pali Rohár <pali@kernel.org>
>+
Code is copied from one file to another. Please don’t remove original copyright
<snip>
Regards
Priyanka
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2] board: freescale: p1_p2_rdb_pc: Move boot reset macros to p1_p2_bootsrc.h
2022-05-26 6:08 ` Priyanka Jain (OSS)
@ 2022-05-26 8:32 ` Pali Rohár
2022-05-26 8:52 ` [PATCH v3] " Pali Rohár
0 siblings, 1 reply; 32+ messages in thread
From: Pali Rohár @ 2022-05-26 8:32 UTC (permalink / raw)
To: Priyanka Jain (OSS); +Cc: Qiang Zhao, Shengzhou Liu, Sinan Akman, u-boot
On Thursday 26 May 2022 06:08:04 Priyanka Jain (OSS) wrote:
> >-----Original Message-----
> >From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Pali Rohár
> >Sent: Monday, April 25, 2022 8:18 PM
> >To: Priyanka Jain <priyanka.jain@nxp.com>; Qiang Zhao <qiang.zhao@nxp.com>;
> >Shengzhou Liu <shengzhou.liu@nxp.com>; Sinan Akman <sinan@writeme.com>
> >Cc: u-boot@lists.denx.de
> >Subject: [PATCH v2] board: freescale: p1_p2_rdb_pc: Move boot reset macros to
> >p1_p2_bootsrc.h
> >
> >Code for changing boot source is platform generic and can be used by any
> >P1* and P2* compatible RDB board. Not only by boards which use config header
> >file p1_p2_rdb_pc.h.
> >
> >So move this code from p1_p2_rdb_pc.h to p1_p2_bootsrc.h and cleanup macros
> >for generating boot source env variables in CONFIG_EXTRA_ENV_SETTINGS.
> >
> >This allows to use code for resetting board and rebooting to other boot source
> >also by other boards in future.
> >
> >Signed-off-by: Pali Rohár <pali@kernel.org>
> >---
> >Changes in v2:
> >* Fix commit message
> >* Move macros to file p1_p2_bootsrc.h
> >* Rewrite macros even more to be more generic and use them without custom
> > macros in p1_p2_rdb_pc.h
> >---
> > include/configs/p1_p2_bootsrc.h | 55 +++++++++++++++++++++++++++++++++
> >include/configs/p1_p2_rdb_pc.h | 41 ++++++------------------
> > 2 files changed, 64 insertions(+), 32 deletions(-) create mode 100644
> >include/configs/p1_p2_bootsrc.h
> >
> >diff --git a/include/configs/p1_p2_bootsrc.h b/include/configs/p1_p2_bootsrc.h
> >new file mode 100644 index 000000000000..a274c57786f5
> >--- /dev/null
> >+++ b/include/configs/p1_p2_bootsrc.h
> >@@ -0,0 +1,55 @@
> >+// SPDX-License-Identifier: GPL-2.0+
> >+// (C) 2022 Pali Rohár <pali@kernel.org>
> >+
> Code is copied from one file to another. Please don’t remove original copyright
I rewritten all those macros from scratch during moving and I therefore
I have thought about copyright header (I just put default one here).
But I can copy+paste copyright header from old file, no problem.
> <snip>
>
> Regards
> Priyanka
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v3] board: freescale: p1_p2_rdb_pc: Move boot reset macros to p1_p2_bootsrc.h
2022-05-26 8:32 ` Pali Rohár
@ 2022-05-26 8:52 ` Pali Rohár
2022-06-02 22:02 ` Pali Rohár
0 siblings, 1 reply; 32+ messages in thread
From: Pali Rohár @ 2022-05-26 8:52 UTC (permalink / raw)
To: Priyanka Jain (OSS); +Cc: Qiang Zhao, Shengzhou Liu, Sinan Akman, u-boot
Code for changing boot source is platform generic and can be used by any
P1* and P2* compatible RDB board. Not only by boards which use config
header file p1_p2_rdb_pc.h.
So move this code from p1_p2_rdb_pc.h to p1_p2_bootsrc.h and cleanup macros
for generating boot source env variables in CONFIG_EXTRA_ENV_SETTINGS.
This allows to use code for resetting board and rebooting to other boot
source also by other boards in future.
Signed-off-by: Pali Rohár <pali@kernel.org>
---
Changes in v3:
* Fix copyright header
Changes in v2:
* Fix commit message
* Move macros to file p1_p2_bootsrc.h
* Rewrite macros even more to be more generic and use them without custom
macros in p1_p2_rdb_pc.h
---
include/configs/p1_p2_bootsrc.h | 59 +++++++++++++++++++++++++++++++++
include/configs/p1_p2_rdb_pc.h | 41 +++++------------------
2 files changed, 68 insertions(+), 32 deletions(-)
create mode 100644 include/configs/p1_p2_bootsrc.h
diff --git a/include/configs/p1_p2_bootsrc.h b/include/configs/p1_p2_bootsrc.h
new file mode 100644
index 000000000000..13e4fdb4fdf6
--- /dev/null
+++ b/include/configs/p1_p2_bootsrc.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
+ * Copyright 2022 Pali Rohár <pali@kernel.org>
+ */
+
+#include <linux/stringify.h>
+
+#if !defined(CONFIG_SYS_SPD_BUS_NUM) || !defined(CONFIG_SYS_I2C_PCA9557_ADDR)
+#error "CONFIG_SYS_SPD_BUS_NUM and CONFIG_SYS_I2C_PCA9557_ADDR are required"
+#endif
+
+#define __BOOTSRC_CMD(src, msk) i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 src 1; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 msk 1
+
+#define __VAR_CMD(var, cmd) __stringify(var=cmd\0)
+#define __VAR_CMD_RST(var, cmd) __VAR_CMD(var, cmd; reset)
+
+#ifdef __SW_NOR_BANK_LO
+#define MAP_NOR_LO_CMD(var, ...) __VAR_CMD(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_NOR_BANK_LO, __SW_NOR_BANK_MASK))
+#else
+#define MAP_NOR_LO_CMD(var, ...) ""
+#endif
+
+#ifdef __SW_NOR_BANK_UP
+#define MAP_NOR_UP_CMD(var, ...) __VAR_CMD(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_NOR_BANK_UP, __SW_NOR_BANK_MASK))
+#else
+#define MAP_NOR_UP_CMD(var, ...) ""
+#endif
+
+#ifdef __SW_BOOT_NOR
+#define RST_NOR_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_NOR, __SW_BOOT_MASK))
+#else
+#define RST_NOR_CMD(var, ...) ""
+#endif
+
+#ifdef __SW_BOOT_SPI
+#define RST_SPI_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_SPI, __SW_BOOT_MASK))
+#else
+#define RST_SPI_CMD(var, ...) ""
+#endif
+
+#ifdef __SW_BOOT_SD
+#define RST_SD_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_SD, __SW_BOOT_MASK))
+#else
+#define RST_SD_CMD(var, ...) ""
+#endif
+
+#ifdef __SW_BOOT_NAND
+#define RST_NAND_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_NAND, __SW_BOOT_MASK))
+#else
+#define RST_NAND_CMD(var, ...) ""
+#endif
+
+#ifdef __SW_BOOT_PCIE
+#define RST_PCIE_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_PCIE, __SW_BOOT_MASK))
+#else
+#define RST_PCIE_CMD(var, ...) ""
+#endif
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index f6ecf2a7a8b8..0d655818a924 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -542,31 +542,7 @@
#define CONFIG_ROOTPATH "/opt/nfsroot"
#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
-#ifdef __SW_BOOT_NOR
-#define __NOR_RST_CMD \
-norboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_NOR 1; \
-i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
-#endif
-#ifdef __SW_BOOT_SPI
-#define __SPI_RST_CMD \
-spiboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_SPI 1; \
-i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
-#endif
-#ifdef __SW_BOOT_SD
-#define __SD_RST_CMD \
-sdboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_SD 1; \
-i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
-#endif
-#ifdef __SW_BOOT_NAND
-#define __NAND_RST_CMD \
-nandboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_NAND 1; \
-i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
-#endif
-#ifdef __SW_BOOT_PCIE
-#define __PCIE_RST_CMD \
-pciboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_PCIE 1; \
-i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
-#endif
+#include "p1_p2_bootsrc.h"
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
@@ -593,13 +569,14 @@ i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
"nandfdtaddr=80000\0" \
"ramdisk_size=120000\0" \
__VSCFW_ADDR \
-"map_lowernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 "__stringify(__SW_NOR_BANK_LO)" 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 "__stringify(__SW_NOR_BANK_MASK)" 1\0" \
-"map_uppernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 "__stringify(__SW_NOR_BANK_UP)" 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 "__stringify(__SW_NOR_BANK_MASK)" 1\0" \
-__stringify(__NOR_RST_CMD)"\0" \
-__stringify(__SPI_RST_CMD)"\0" \
-__stringify(__SD_RST_CMD)"\0" \
-__stringify(__NAND_RST_CMD)"\0" \
-__stringify(__PCIE_RST_CMD)"\0"
+MAP_NOR_LO_CMD(map_lowernorbank) \
+MAP_NOR_UP_CMD(map_uppernorbank) \
+RST_NOR_CMD(norboot) \
+RST_SPI_CMD(spiboot) \
+RST_SD_CMD(sdboot) \
+RST_NAND_CMD(nandboot) \
+RST_PCIE_CMD(pciboot) \
+""
#define CONFIG_USB_FAT_BOOT \
"setenv bootargs root=/dev/ram rw " \
--
2.20.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* Re: [PATCH v3] board: freescale: p1_p2_rdb_pc: Move boot reset macros to p1_p2_bootsrc.h
2022-05-26 8:52 ` [PATCH v3] " Pali Rohár
@ 2022-06-02 22:02 ` Pali Rohár
0 siblings, 0 replies; 32+ messages in thread
From: Pali Rohár @ 2022-06-02 22:02 UTC (permalink / raw)
To: Priyanka Jain (OSS); +Cc: Qiang Zhao, Shengzhou Liu, Sinan Akman, u-boot
On Thursday 26 May 2022 10:52:27 Pali Rohár wrote:
> Code for changing boot source is platform generic and can be used by any
> P1* and P2* compatible RDB board. Not only by boards which use config
> header file p1_p2_rdb_pc.h.
>
> So move this code from p1_p2_rdb_pc.h to p1_p2_bootsrc.h and cleanup macros
> for generating boot source env variables in CONFIG_EXTRA_ENV_SETTINGS.
>
> This allows to use code for resetting board and rebooting to other boot
> source also by other boards in future.
>
> Signed-off-by: Pali Rohár <pali@kernel.org>
> ---
> Changes in v3:
> * Fix copyright header
Priyanka: It is OK now?
> Changes in v2:
> * Fix commit message
> * Move macros to file p1_p2_bootsrc.h
> * Rewrite macros even more to be more generic and use them without custom
> macros in p1_p2_rdb_pc.h
> ---
> include/configs/p1_p2_bootsrc.h | 59 +++++++++++++++++++++++++++++++++
> include/configs/p1_p2_rdb_pc.h | 41 +++++------------------
> 2 files changed, 68 insertions(+), 32 deletions(-)
> create mode 100644 include/configs/p1_p2_bootsrc.h
>
> diff --git a/include/configs/p1_p2_bootsrc.h b/include/configs/p1_p2_bootsrc.h
> new file mode 100644
> index 000000000000..13e4fdb4fdf6
> --- /dev/null
> +++ b/include/configs/p1_p2_bootsrc.h
> @@ -0,0 +1,59 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2010-2011 Freescale Semiconductor, Inc.
> + * Copyright 2020 NXP
> + * Copyright 2022 Pali Rohár <pali@kernel.org>
> + */
> +
> +#include <linux/stringify.h>
> +
> +#if !defined(CONFIG_SYS_SPD_BUS_NUM) || !defined(CONFIG_SYS_I2C_PCA9557_ADDR)
> +#error "CONFIG_SYS_SPD_BUS_NUM and CONFIG_SYS_I2C_PCA9557_ADDR are required"
> +#endif
> +
> +#define __BOOTSRC_CMD(src, msk) i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 src 1; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 msk 1
> +
> +#define __VAR_CMD(var, cmd) __stringify(var=cmd\0)
> +#define __VAR_CMD_RST(var, cmd) __VAR_CMD(var, cmd; reset)
> +
> +#ifdef __SW_NOR_BANK_LO
> +#define MAP_NOR_LO_CMD(var, ...) __VAR_CMD(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_NOR_BANK_LO, __SW_NOR_BANK_MASK))
> +#else
> +#define MAP_NOR_LO_CMD(var, ...) ""
> +#endif
> +
> +#ifdef __SW_NOR_BANK_UP
> +#define MAP_NOR_UP_CMD(var, ...) __VAR_CMD(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_NOR_BANK_UP, __SW_NOR_BANK_MASK))
> +#else
> +#define MAP_NOR_UP_CMD(var, ...) ""
> +#endif
> +
> +#ifdef __SW_BOOT_NOR
> +#define RST_NOR_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_NOR, __SW_BOOT_MASK))
> +#else
> +#define RST_NOR_CMD(var, ...) ""
> +#endif
> +
> +#ifdef __SW_BOOT_SPI
> +#define RST_SPI_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_SPI, __SW_BOOT_MASK))
> +#else
> +#define RST_SPI_CMD(var, ...) ""
> +#endif
> +
> +#ifdef __SW_BOOT_SD
> +#define RST_SD_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_SD, __SW_BOOT_MASK))
> +#else
> +#define RST_SD_CMD(var, ...) ""
> +#endif
> +
> +#ifdef __SW_BOOT_NAND
> +#define RST_NAND_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_NAND, __SW_BOOT_MASK))
> +#else
> +#define RST_NAND_CMD(var, ...) ""
> +#endif
> +
> +#ifdef __SW_BOOT_PCIE
> +#define RST_PCIE_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_PCIE, __SW_BOOT_MASK))
> +#else
> +#define RST_PCIE_CMD(var, ...) ""
> +#endif
> diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
> index f6ecf2a7a8b8..0d655818a924 100644
> --- a/include/configs/p1_p2_rdb_pc.h
> +++ b/include/configs/p1_p2_rdb_pc.h
> @@ -542,31 +542,7 @@
> #define CONFIG_ROOTPATH "/opt/nfsroot"
> #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
>
> -#ifdef __SW_BOOT_NOR
> -#define __NOR_RST_CMD \
> -norboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_NOR 1; \
> -i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
> -#endif
> -#ifdef __SW_BOOT_SPI
> -#define __SPI_RST_CMD \
> -spiboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_SPI 1; \
> -i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
> -#endif
> -#ifdef __SW_BOOT_SD
> -#define __SD_RST_CMD \
> -sdboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_SD 1; \
> -i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
> -#endif
> -#ifdef __SW_BOOT_NAND
> -#define __NAND_RST_CMD \
> -nandboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_NAND 1; \
> -i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
> -#endif
> -#ifdef __SW_BOOT_PCIE
> -#define __PCIE_RST_CMD \
> -pciboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_PCIE 1; \
> -i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
> -#endif
> +#include "p1_p2_bootsrc.h"
>
> #define CONFIG_EXTRA_ENV_SETTINGS \
> "netdev=eth0\0" \
> @@ -593,13 +569,14 @@ i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
> "nandfdtaddr=80000\0" \
> "ramdisk_size=120000\0" \
> __VSCFW_ADDR \
> -"map_lowernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 "__stringify(__SW_NOR_BANK_LO)" 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 "__stringify(__SW_NOR_BANK_MASK)" 1\0" \
> -"map_uppernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 "__stringify(__SW_NOR_BANK_UP)" 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 "__stringify(__SW_NOR_BANK_MASK)" 1\0" \
> -__stringify(__NOR_RST_CMD)"\0" \
> -__stringify(__SPI_RST_CMD)"\0" \
> -__stringify(__SD_RST_CMD)"\0" \
> -__stringify(__NAND_RST_CMD)"\0" \
> -__stringify(__PCIE_RST_CMD)"\0"
> +MAP_NOR_LO_CMD(map_lowernorbank) \
> +MAP_NOR_UP_CMD(map_uppernorbank) \
> +RST_NOR_CMD(norboot) \
> +RST_SPI_CMD(spiboot) \
> +RST_SD_CMD(sdboot) \
> +RST_NAND_CMD(nandboot) \
> +RST_PCIE_CMD(pciboot) \
> +""
>
> #define CONFIG_USB_FAT_BOOT \
> "setenv bootargs root=/dev/ram rw " \
> --
> 2.20.1
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 11/11] board: freescale: p1_p2_rdb_pc: Add env commands norlowerboot, norupperboot, sd2boot and defboot
2022-04-07 10:16 [PATCH 00/11] board: freescale: p1_p2_rdb_pc: Various cleanups and fixes Pali Rohár
` (9 preceding siblings ...)
2022-04-07 10:16 ` [PATCH 10/11] board: freescale: p1_p2_rdb_pc: Move BootROM change source macros to p1_p2_bootrom.h Pali Rohár
@ 2022-04-07 10:16 ` Pali Rohár
2022-04-25 14:50 ` [PATCH v2] " Pali Rohár
10 siblings, 1 reply; 32+ messages in thread
From: Pali Rohár @ 2022-04-07 10:16 UTC (permalink / raw)
To: Priyanka Jain, Qiang Zhao, Shengzhou Liu, Sinan Akman; +Cc: u-boot
All *boot env commands overrides default BootROM boot location via i2c.
BootROM then starts booting U-Boot from this specified location instead of
the default one.
Add new env command defboot which reverts BootROM boot location to the
default value, which in most cases is configurable by HW DIP switches.
And add new env commands norlowerboot, norupperboot, sd2boot to boot from
other locations. norlowerboot would instruct BootROM to boot from lower NOR
bank, norupperboot from upper NOR bank and sd2boot from SD card with
alternative configuration.
Signed-off-by: Pali Rohár <pali@kernel.org>
---
include/configs/p1_p2_bootrom.h | 14 +++++++++++++
include/configs/p1_p2_rdb_pc.h | 37 +++++++++++++++++++++++++++++++++
2 files changed, 51 insertions(+)
diff --git a/include/configs/p1_p2_bootrom.h b/include/configs/p1_p2_bootrom.h
index a1f61b788cf7..d1e91049606b 100644
--- a/include/configs/p1_p2_bootrom.h
+++ b/include/configs/p1_p2_bootrom.h
@@ -15,6 +15,14 @@
#define CHANGE_BOOTROM_SOURCE_DEF_NOR_BANK_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_NOR, __SW_BOOT_MASK)
#endif
+#ifdef __SW_BOOT_NOR_BANK_LO
+#define CHANGE_BOOTROM_SOURCE_LOWER_NOR_BANK_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_NOR_BANK_LO, __SW_BOOT_NOR_BANK_MASK)
+#endif
+
+#ifdef __SW_BOOT_NOR_BANK_UP
+#define CHANGE_BOOTROM_SOURCE_UPPER_NOR_BANK_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_NOR_BANK_UP, __SW_BOOT_NOR_BANK_MASK)
+#endif
+
#ifdef __SW_BOOT_SPI
#define CHANGE_BOOTROM_SOURCE_SPI_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_SPI, __SW_BOOT_MASK)
#endif
@@ -23,6 +31,10 @@
#define CHANGE_BOOTROM_SOURCE_SD_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_SD, __SW_BOOT_MASK)
#endif
+#ifdef __SW_BOOT_SD2
+#define CHANGE_BOOTROM_SOURCE_SD2_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_SD2, __SW_BOOT_MASK)
+#endif
+
#ifdef __SW_BOOT_NAND
#define CHANGE_BOOTROM_SOURCE_NAND_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_NAND, __SW_BOOT_MASK)
#endif
@@ -30,3 +42,5 @@
#ifdef __SW_BOOT_PCIE
#define CHANGE_BOOTROM_SOURCE_PCIE_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_PCIE, __SW_BOOT_MASK)
#endif
+
+#define CHANGE_BOOTROM_SOURCE_DEF_CMD CHANGE_BOOTROM_SOURCE_CMD(0x00, 0xff)
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index d41b31081017..ac8199a88aa0 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -25,6 +25,9 @@
#define __SW_NOR_BANK_MASK 0xfd
#define __SW_NOR_BANK_UP 0x00
#define __SW_NOR_BANK_LO 0x02
+#define __SW_BOOT_NOR_BANK_UP 0x5c /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */
+#define __SW_BOOT_NOR_BANK_LO 0x5e /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */
+#define __SW_BOOT_NOR_BANK_MASK 0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */
#define CONFIG_SYS_L2_SIZE (256 << 10)
#endif
@@ -54,6 +57,9 @@
#define __SW_NOR_BANK_MASK 0xfd
#define __SW_NOR_BANK_UP 0x00
#define __SW_NOR_BANK_LO 0x02
+#define __SW_BOOT_NOR_BANK_UP 0x64 /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */
+#define __SW_BOOT_NOR_BANK_LO 0x66 /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */
+#define __SW_BOOT_NOR_BANK_MASK 0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */
#define CONFIG_SYS_L2_SIZE (256 << 10)
/*
* Dynamic MTD Partition support with mtdparts
@@ -73,6 +79,9 @@
#define __SW_NOR_BANK_MASK 0xfd
#define __SW_NOR_BANK_UP 0x00
#define __SW_NOR_BANK_LO 0x02
+#define __SW_BOOT_NOR_BANK_UP 0xc8 /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */
+#define __SW_BOOT_NOR_BANK_LO 0xca /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */
+#define __SW_BOOT_NOR_BANK_MASK 0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */
#define CONFIG_SYS_L2_SIZE (512 << 10)
/*
* Dynamic MTD Partition support with mtdparts
@@ -595,6 +604,18 @@
#define __NOR_RST_CMD ""
#endif
+#ifdef CHANGE_BOOTROM_SOURCE_LOWER_NOR_BANK_CMD
+#define __NOR_LOWER_RST_CMD "norlowerboot="__stringify(CHANGE_BOOTROM_SOURCE_LOWER_NOR_BANK_CMD)"; reset\0"
+#else
+#define __NOR_LOWER_RST_CMD ""
+#endif
+
+#ifdef CHANGE_BOOTROM_SOURCE_UPPER_NOR_BANK_CMD
+#define __NOR_UPPER_RST_CMD "norupperboot="__stringify(CHANGE_BOOTROM_SOURCE_UPPER_NOR_BANK_CMD)"; reset\0"
+#else
+#define __NOR_UPPER_RST_CMD ""
+#endif
+
#ifdef CHANGE_BOOTROM_SOURCE_SPI_CMD
#define __SPI_RST_CMD "spiboot="__stringify(CHANGE_BOOTROM_SOURCE_SPI_CMD)"; reset\0"
#else
@@ -607,6 +628,12 @@
#define __SD_RST_CMD ""
#endif
+#ifdef CHANGE_BOOTROM_SOURCE_SD2_CMD
+#define __SD2_RST_CMD "sd2boot="__stringify(CHANGE_BOOTROM_SOURCE_SD2_CMD)"; reset\0"
+#else
+#define __SD2_RST_CMD ""
+#endif
+
#ifdef CHANGE_BOOTROM_SOURCE_NAND_CMD
#define __NAND_RST_CMD "nandboot="__stringify(CHANGE_BOOTROM_SOURCE_NAND_CMD)"; reset\0"
#else
@@ -619,6 +646,12 @@
#define __PCIE_RST_CMD ""
#endif
+#ifdef CHANGE_BOOTROM_SOURCE_DEF_CMD
+#define __DEF_RST_CMD "defboot="__stringify(CHANGE_BOOTROM_SOURCE_DEF_CMD)"; reset\0"
+#else
+#define __DEF_RST_CMD ""
+#endif
+
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
@@ -647,10 +680,14 @@ __VSCFW_ADDR \
__MAP_NOR_LOWER_CMD \
__MAP_NOR_UPPER_CMD \
__NOR_RST_CMD \
+__NOR_LOWER_RST_CMD \
+__NOR_UPPER_RST_CMD \
__SPI_RST_CMD \
__SD_RST_CMD \
+__SD2_RST_CMD \
__NAND_RST_CMD \
__PCIE_RST_CMD \
+__DEF_RST_CMD \
""
#define CONFIG_USB_FAT_BOOT \
--
2.20.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v2] board: freescale: p1_p2_rdb_pc: Add env commands norlowerboot, norupperboot, sd2boot and defboot
2022-04-07 10:16 ` [PATCH 11/11] board: freescale: p1_p2_rdb_pc: Add env commands norlowerboot, norupperboot, sd2boot and defboot Pali Rohár
@ 2022-04-25 14:50 ` Pali Rohár
2022-06-16 9:01 ` Peng Fan (OSS)
0 siblings, 1 reply; 32+ messages in thread
From: Pali Rohár @ 2022-04-25 14:50 UTC (permalink / raw)
To: Priyanka Jain, Qiang Zhao, Shengzhou Liu, Sinan Akman; +Cc: u-boot
All *boot env commands overrides default boot source location via i2c.
After board reset without power off, BootROM then starts booting U-Boot
from this specified location instead of the default one.
Add new env command defboot which reverts boot location to the default
value, which in most cases is configurable by HW DIP switches.
And add new env commands norlowerboot, norupperboot, sd2boot to boot from
other locations. norlowerboot would instruct BootROM to boot from lower NOR
bank, norupperboot from upper NOR bank and sd2boot from SD card with
alternative configuration.
Signed-off-by: Pali Rohár <pali@kernel.org>
---
Changes in v2:
* Fix commit message
* Adapt code to use p1_p2_bootsrc.h
---
include/configs/p1_p2_bootsrc.h | 20 ++++++++++++++++++++
include/configs/p1_p2_rdb_pc.h | 13 +++++++++++++
2 files changed, 33 insertions(+)
diff --git a/include/configs/p1_p2_bootsrc.h b/include/configs/p1_p2_bootsrc.h
index a274c57786f5..60741ef544c0 100644
--- a/include/configs/p1_p2_bootsrc.h
+++ b/include/configs/p1_p2_bootsrc.h
@@ -30,6 +30,18 @@
#define RST_NOR_CMD(var, ...) ""
#endif
+#ifdef __SW_BOOT_NOR_BANK_LO
+#define RST_NOR_LO_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_NOR_BANK_LO, __SW_BOOT_MASK))
+#else
+#define RST_NOR_LO_CMD(var, ...) ""
+#endif
+
+#ifdef __SW_BOOT_NOR_BANK_UP
+#define RST_NOR_UP_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_NOR_BANK_UP, __SW_BOOT_MASK))
+#else
+#define RST_NOR_UP_CMD(var, ...) ""
+#endif
+
#ifdef __SW_BOOT_SPI
#define RST_SPI_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_SPI, __SW_BOOT_MASK))
#else
@@ -42,6 +54,12 @@
#define RST_SD_CMD(var, ...) ""
#endif
+#ifdef __SW_BOOT_SD2
+#define RST_SD2_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_SD2, __SW_BOOT_MASK))
+#else
+#define RST_SD2_CMD(var, ...) ""
+#endif
+
#ifdef __SW_BOOT_NAND
#define RST_NAND_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_NAND, __SW_BOOT_MASK))
#else
@@ -53,3 +71,5 @@
#else
#define RST_PCIE_CMD(var, ...) ""
#endif
+
+#define RST_DEF_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(0x00, 0xff))
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 47bd20eeeafb..50ce2d9aaed4 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -25,6 +25,9 @@
#define __SW_NOR_BANK_MASK 0xfd
#define __SW_NOR_BANK_UP 0x00
#define __SW_NOR_BANK_LO 0x02
+#define __SW_BOOT_NOR_BANK_UP 0x5c /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */
+#define __SW_BOOT_NOR_BANK_LO 0x5e /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */
+#define __SW_BOOT_NOR_BANK_MASK 0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */
#define CONFIG_SYS_L2_SIZE (256 << 10)
#endif
@@ -54,6 +57,9 @@
#define __SW_NOR_BANK_MASK 0xfd
#define __SW_NOR_BANK_UP 0x00
#define __SW_NOR_BANK_LO 0x02
+#define __SW_BOOT_NOR_BANK_UP 0x64 /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */
+#define __SW_BOOT_NOR_BANK_LO 0x66 /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */
+#define __SW_BOOT_NOR_BANK_MASK 0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */
#define CONFIG_SYS_L2_SIZE (256 << 10)
/*
* Dynamic MTD Partition support with mtdparts
@@ -73,6 +79,9 @@
#define __SW_NOR_BANK_MASK 0xfd
#define __SW_NOR_BANK_UP 0x00
#define __SW_NOR_BANK_LO 0x02
+#define __SW_BOOT_NOR_BANK_UP 0xc8 /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */
+#define __SW_BOOT_NOR_BANK_LO 0xca /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */
+#define __SW_BOOT_NOR_BANK_MASK 0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */
#define CONFIG_SYS_L2_SIZE (512 << 10)
/*
* Dynamic MTD Partition support with mtdparts
@@ -605,10 +614,14 @@ __VSCFW_ADDR \
MAP_NOR_LO_CMD(map_lowernorbank) \
MAP_NOR_UP_CMD(map_uppernorbank) \
RST_NOR_CMD(norboot) \
+RST_NOR_LO_CMD(norlowerboot) \
+RST_NOR_UP_CMD(norupperboot) \
RST_SPI_CMD(spiboot) \
RST_SD_CMD(sdboot) \
+RST_SD2_CMD(sd2boot) \
RST_NAND_CMD(nandboot) \
RST_PCIE_CMD(pciboot) \
+RST_DEF_CMD(defboot) \
""
#define CONFIG_USB_FAT_BOOT \
--
2.20.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* Re: [PATCH v2] board: freescale: p1_p2_rdb_pc: Add env commands norlowerboot, norupperboot, sd2boot and defboot
2022-04-25 14:50 ` [PATCH v2] " Pali Rohár
@ 2022-06-16 9:01 ` Peng Fan (OSS)
2022-06-23 13:43 ` Pali Rohár
0 siblings, 1 reply; 32+ messages in thread
From: Peng Fan (OSS) @ 2022-06-16 9:01 UTC (permalink / raw)
To: Pali Rohár, Priyanka Jain, Qiang Zhao, Shengzhou Liu, Sinan Akman
Cc: u-boot
在 2022/4/25 22:50, Pali Rohár 写道:
> All *boot env commands overrides default boot source location via i2c.
> After board reset without power off, BootROM then starts booting U-Boot
> from this specified location instead of the default one.
>
> Add new env command defboot which reverts boot location to the default
> value, which in most cases is configurable by HW DIP switches.
>
> And add new env commands norlowerboot, norupperboot, sd2boot to boot from
> other locations. norlowerboot would instruct BootROM to boot from lower NOR
> bank, norupperboot from upper NOR bank and sd2boot from SD card with
> alternative configuration.
>
> Signed-off-by: Pali Rohár <pali@kernel.org>
Not able to apply this patch. Please new version.
Thanks,
Peng.
> ---
> Changes in v2:
> * Fix commit message
> * Adapt code to use p1_p2_bootsrc.h
> ---
> include/configs/p1_p2_bootsrc.h | 20 ++++++++++++++++++++
> include/configs/p1_p2_rdb_pc.h | 13 +++++++++++++
> 2 files changed, 33 insertions(+)
>
> diff --git a/include/configs/p1_p2_bootsrc.h b/include/configs/p1_p2_bootsrc.h
> index a274c57786f5..60741ef544c0 100644
> --- a/include/configs/p1_p2_bootsrc.h
> +++ b/include/configs/p1_p2_bootsrc.h
> @@ -30,6 +30,18 @@
> #define RST_NOR_CMD(var, ...) ""
> #endif
>
> +#ifdef __SW_BOOT_NOR_BANK_LO
> +#define RST_NOR_LO_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_NOR_BANK_LO, __SW_BOOT_MASK))
> +#else
> +#define RST_NOR_LO_CMD(var, ...) ""
> +#endif
> +
> +#ifdef __SW_BOOT_NOR_BANK_UP
> +#define RST_NOR_UP_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_NOR_BANK_UP, __SW_BOOT_MASK))
> +#else
> +#define RST_NOR_UP_CMD(var, ...) ""
> +#endif
> +
> #ifdef __SW_BOOT_SPI
> #define RST_SPI_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_SPI, __SW_BOOT_MASK))
> #else
> @@ -42,6 +54,12 @@
> #define RST_SD_CMD(var, ...) ""
> #endif
>
> +#ifdef __SW_BOOT_SD2
> +#define RST_SD2_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_SD2, __SW_BOOT_MASK))
> +#else
> +#define RST_SD2_CMD(var, ...) ""
> +#endif
> +
> #ifdef __SW_BOOT_NAND
> #define RST_NAND_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_NAND, __SW_BOOT_MASK))
> #else
> @@ -53,3 +71,5 @@
> #else
> #define RST_PCIE_CMD(var, ...) ""
> #endif
> +
> +#define RST_DEF_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(0x00, 0xff))
> diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
> index 47bd20eeeafb..50ce2d9aaed4 100644
> --- a/include/configs/p1_p2_rdb_pc.h
> +++ b/include/configs/p1_p2_rdb_pc.h
> @@ -25,6 +25,9 @@
> #define __SW_NOR_BANK_MASK 0xfd
> #define __SW_NOR_BANK_UP 0x00
> #define __SW_NOR_BANK_LO 0x02
> +#define __SW_BOOT_NOR_BANK_UP 0x5c /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */
> +#define __SW_BOOT_NOR_BANK_LO 0x5e /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */
> +#define __SW_BOOT_NOR_BANK_MASK 0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */
> #define CONFIG_SYS_L2_SIZE (256 << 10)
> #endif
>
> @@ -54,6 +57,9 @@
> #define __SW_NOR_BANK_MASK 0xfd
> #define __SW_NOR_BANK_UP 0x00
> #define __SW_NOR_BANK_LO 0x02
> +#define __SW_BOOT_NOR_BANK_UP 0x64 /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */
> +#define __SW_BOOT_NOR_BANK_LO 0x66 /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */
> +#define __SW_BOOT_NOR_BANK_MASK 0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */
> #define CONFIG_SYS_L2_SIZE (256 << 10)
> /*
> * Dynamic MTD Partition support with mtdparts
> @@ -73,6 +79,9 @@
> #define __SW_NOR_BANK_MASK 0xfd
> #define __SW_NOR_BANK_UP 0x00
> #define __SW_NOR_BANK_LO 0x02
> +#define __SW_BOOT_NOR_BANK_UP 0xc8 /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */
> +#define __SW_BOOT_NOR_BANK_LO 0xca /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */
> +#define __SW_BOOT_NOR_BANK_MASK 0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */
> #define CONFIG_SYS_L2_SIZE (512 << 10)
> /*
> * Dynamic MTD Partition support with mtdparts
> @@ -605,10 +614,14 @@ __VSCFW_ADDR \
> MAP_NOR_LO_CMD(map_lowernorbank) \
> MAP_NOR_UP_CMD(map_uppernorbank) \
> RST_NOR_CMD(norboot) \
> +RST_NOR_LO_CMD(norlowerboot) \
> +RST_NOR_UP_CMD(norupperboot) \
> RST_SPI_CMD(spiboot) \
> RST_SD_CMD(sdboot) \
> +RST_SD2_CMD(sd2boot) \
> RST_NAND_CMD(nandboot) \
> RST_PCIE_CMD(pciboot) \
> +RST_DEF_CMD(defboot) \
> ""
>
> #define CONFIG_USB_FAT_BOOT \
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2] board: freescale: p1_p2_rdb_pc: Add env commands norlowerboot, norupperboot, sd2boot and defboot
2022-06-16 9:01 ` Peng Fan (OSS)
@ 2022-06-23 13:43 ` Pali Rohár
2022-07-03 12:38 ` Pali Rohár
0 siblings, 1 reply; 32+ messages in thread
From: Pali Rohár @ 2022-06-23 13:43 UTC (permalink / raw)
To: Peng Fan (OSS)
Cc: Priyanka Jain, Qiang Zhao, Shengzhou Liu, Sinan Akman, u-boot
On Thursday 16 June 2022 17:01:50 Peng Fan (OSS) wrote:
> 在 2022/4/25 22:50, Pali Rohár 写道:
> > All *boot env commands overrides default boot source location via i2c.
> > After board reset without power off, BootROM then starts booting U-Boot
> > from this specified location instead of the default one.
> >
> > Add new env command defboot which reverts boot location to the default
> > value, which in most cases is configurable by HW DIP switches.
> >
> > And add new env commands norlowerboot, norupperboot, sd2boot to boot from
> > other locations. norlowerboot would instruct BootROM to boot from lower NOR
> > bank, norupperboot from upper NOR bank and sd2boot from SD card with
> > alternative configuration.
> >
> > Signed-off-by: Pali Rohár <pali@kernel.org>
>
> Not able to apply this patch.
And what is the reason? It applies cleanly on top of next branch, which
is today at commit 9121478ee6f2aee381f8fe49d8997d43527d351a.
See my steps and output:
$ git clone https://source.denx.de/u-boot/u-boot.git -b next
Cloning into 'u-boot'...
remote: Enumerating objects: 861911, done.
remote: Counting objects: 100% (15749/15749), done.
remote: Compressing objects: 100% (3457/3457), done.
remote: Total 861911 (delta 12303), reused 15650 (delta 12234), pack-reused 846162
Receiving objects: 100% (861911/861911), 171.30 MiB | 38.97 MiB/s, done.
Resolving deltas: 100% (721111/721111), done.
$ cd u-boot
$ wget https://patchwork.ozlabs.org/project/uboot/patch/20220425145043.9945-1-pali@kernel.org/mbox/ -O patch
--2022-06-23 15:39:52-- https://patchwork.ozlabs.org/project/uboot/patch/20220425145043.9945-1-pali@kernel.org/mbox/
Resolving patchwork.ozlabs.org (patchwork.ozlabs.org)... 2401:3900:2:1::2, 203.11.71.1
Connecting to patchwork.ozlabs.org (patchwork.ozlabs.org)|2401:3900:2:1::2|:443... connected.
HTTP request sent, awaiting response... 200 OK
Length: 8916 (8.7K) [text/plain]
Saving to: 'patch'
patch 100%[===============================>] 8.71K --.-KB/s in 0s
2022-06-23 15:39:53 (57.2 MB/s) - 'patch' saved [8916/8916]
$ git am patch
Applying: board: freescale: p1_p2_rdb_pc: Add env commands norlowerboot, norupperboot, sd2boot and defboot
$ git log --oneline | head -4
b94d5df9eb49 board: freescale: p1_p2_rdb_pc: Add env commands norlowerboot, norupperboot, sd2boot and defboot
9121478ee6f2 Merge branch '2022-06-22-platform-updates-and-additions' into next
929e581a620f corstone1000: Convert to text file environment
781a144a7a7e gxp: Convert to text file environment
> Please new version.
>
> Thanks,
> Peng.
> > ---
> > Changes in v2:
> > * Fix commit message
> > * Adapt code to use p1_p2_bootsrc.h
> > ---
> > include/configs/p1_p2_bootsrc.h | 20 ++++++++++++++++++++
> > include/configs/p1_p2_rdb_pc.h | 13 +++++++++++++
> > 2 files changed, 33 insertions(+)
> >
> > diff --git a/include/configs/p1_p2_bootsrc.h b/include/configs/p1_p2_bootsrc.h
> > index a274c57786f5..60741ef544c0 100644
> > --- a/include/configs/p1_p2_bootsrc.h
> > +++ b/include/configs/p1_p2_bootsrc.h
> > @@ -30,6 +30,18 @@
> > #define RST_NOR_CMD(var, ...) ""
> > #endif
> > +#ifdef __SW_BOOT_NOR_BANK_LO
> > +#define RST_NOR_LO_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_NOR_BANK_LO, __SW_BOOT_MASK))
> > +#else
> > +#define RST_NOR_LO_CMD(var, ...) ""
> > +#endif
> > +
> > +#ifdef __SW_BOOT_NOR_BANK_UP
> > +#define RST_NOR_UP_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_NOR_BANK_UP, __SW_BOOT_MASK))
> > +#else
> > +#define RST_NOR_UP_CMD(var, ...) ""
> > +#endif
> > +
> > #ifdef __SW_BOOT_SPI
> > #define RST_SPI_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_SPI, __SW_BOOT_MASK))
> > #else
> > @@ -42,6 +54,12 @@
> > #define RST_SD_CMD(var, ...) ""
> > #endif
> > +#ifdef __SW_BOOT_SD2
> > +#define RST_SD2_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_SD2, __SW_BOOT_MASK))
> > +#else
> > +#define RST_SD2_CMD(var, ...) ""
> > +#endif
> > +
> > #ifdef __SW_BOOT_NAND
> > #define RST_NAND_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_NAND, __SW_BOOT_MASK))
> > #else
> > @@ -53,3 +71,5 @@
> > #else
> > #define RST_PCIE_CMD(var, ...) ""
> > #endif
> > +
> > +#define RST_DEF_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(0x00, 0xff))
> > diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
> > index 47bd20eeeafb..50ce2d9aaed4 100644
> > --- a/include/configs/p1_p2_rdb_pc.h
> > +++ b/include/configs/p1_p2_rdb_pc.h
> > @@ -25,6 +25,9 @@
> > #define __SW_NOR_BANK_MASK 0xfd
> > #define __SW_NOR_BANK_UP 0x00
> > #define __SW_NOR_BANK_LO 0x02
> > +#define __SW_BOOT_NOR_BANK_UP 0x5c /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */
> > +#define __SW_BOOT_NOR_BANK_LO 0x5e /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */
> > +#define __SW_BOOT_NOR_BANK_MASK 0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */
> > #define CONFIG_SYS_L2_SIZE (256 << 10)
> > #endif
> > @@ -54,6 +57,9 @@
> > #define __SW_NOR_BANK_MASK 0xfd
> > #define __SW_NOR_BANK_UP 0x00
> > #define __SW_NOR_BANK_LO 0x02
> > +#define __SW_BOOT_NOR_BANK_UP 0x64 /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */
> > +#define __SW_BOOT_NOR_BANK_LO 0x66 /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */
> > +#define __SW_BOOT_NOR_BANK_MASK 0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */
> > #define CONFIG_SYS_L2_SIZE (256 << 10)
> > /*
> > * Dynamic MTD Partition support with mtdparts
> > @@ -73,6 +79,9 @@
> > #define __SW_NOR_BANK_MASK 0xfd
> > #define __SW_NOR_BANK_UP 0x00
> > #define __SW_NOR_BANK_LO 0x02
> > +#define __SW_BOOT_NOR_BANK_UP 0xc8 /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */
> > +#define __SW_BOOT_NOR_BANK_LO 0xca /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */
> > +#define __SW_BOOT_NOR_BANK_MASK 0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */
> > #define CONFIG_SYS_L2_SIZE (512 << 10)
> > /*
> > * Dynamic MTD Partition support with mtdparts
> > @@ -605,10 +614,14 @@ __VSCFW_ADDR \
> > MAP_NOR_LO_CMD(map_lowernorbank) \
> > MAP_NOR_UP_CMD(map_uppernorbank) \
> > RST_NOR_CMD(norboot) \
> > +RST_NOR_LO_CMD(norlowerboot) \
> > +RST_NOR_UP_CMD(norupperboot) \
> > RST_SPI_CMD(spiboot) \
> > RST_SD_CMD(sdboot) \
> > +RST_SD2_CMD(sd2boot) \
> > RST_NAND_CMD(nandboot) \
> > RST_PCIE_CMD(pciboot) \
> > +RST_DEF_CMD(defboot) \
> > ""
> > #define CONFIG_USB_FAT_BOOT \
>
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH v2] board: freescale: p1_p2_rdb_pc: Add env commands norlowerboot, norupperboot, sd2boot and defboot
2022-06-23 13:43 ` Pali Rohár
@ 2022-07-03 12:38 ` Pali Rohár
[not found] ` <20220708224344.jswbjxp3tdnfnmlp@pali>
0 siblings, 1 reply; 32+ messages in thread
From: Pali Rohár @ 2022-07-03 12:38 UTC (permalink / raw)
To: Peng Fan (OSS)
Cc: Priyanka Jain, Qiang Zhao, Shengzhou Liu, Sinan Akman, u-boot
PING!
On Thursday 23 June 2022 15:43:45 Pali Rohár wrote:
> On Thursday 16 June 2022 17:01:50 Peng Fan (OSS) wrote:
> > 在 2022/4/25 22:50, Pali Rohár 写道:
> > > All *boot env commands overrides default boot source location via i2c.
> > > After board reset without power off, BootROM then starts booting U-Boot
> > > from this specified location instead of the default one.
> > >
> > > Add new env command defboot which reverts boot location to the default
> > > value, which in most cases is configurable by HW DIP switches.
> > >
> > > And add new env commands norlowerboot, norupperboot, sd2boot to boot from
> > > other locations. norlowerboot would instruct BootROM to boot from lower NOR
> > > bank, norupperboot from upper NOR bank and sd2boot from SD card with
> > > alternative configuration.
> > >
> > > Signed-off-by: Pali Rohár <pali@kernel.org>
> >
> > Not able to apply this patch.
>
> And what is the reason? It applies cleanly on top of next branch, which
> is today at commit 9121478ee6f2aee381f8fe49d8997d43527d351a.
>
> See my steps and output:
>
> $ git clone https://source.denx.de/u-boot/u-boot.git -b next
> Cloning into 'u-boot'...
> remote: Enumerating objects: 861911, done.
> remote: Counting objects: 100% (15749/15749), done.
> remote: Compressing objects: 100% (3457/3457), done.
> remote: Total 861911 (delta 12303), reused 15650 (delta 12234), pack-reused 846162
> Receiving objects: 100% (861911/861911), 171.30 MiB | 38.97 MiB/s, done.
> Resolving deltas: 100% (721111/721111), done.
>
> $ cd u-boot
>
> $ wget https://patchwork.ozlabs.org/project/uboot/patch/20220425145043.9945-1-pali@kernel.org/mbox/ -O patch
> --2022-06-23 15:39:52-- https://patchwork.ozlabs.org/project/uboot/patch/20220425145043.9945-1-pali@kernel.org/mbox/
> Resolving patchwork.ozlabs.org (patchwork.ozlabs.org)... 2401:3900:2:1::2, 203.11.71.1
> Connecting to patchwork.ozlabs.org (patchwork.ozlabs.org)|2401:3900:2:1::2|:443... connected.
> HTTP request sent, awaiting response... 200 OK
> Length: 8916 (8.7K) [text/plain]
> Saving to: 'patch'
>
> patch 100%[===============================>] 8.71K --.-KB/s in 0s
>
> 2022-06-23 15:39:53 (57.2 MB/s) - 'patch' saved [8916/8916]
>
> $ git am patch
> Applying: board: freescale: p1_p2_rdb_pc: Add env commands norlowerboot, norupperboot, sd2boot and defboot
>
> $ git log --oneline | head -4
> b94d5df9eb49 board: freescale: p1_p2_rdb_pc: Add env commands norlowerboot, norupperboot, sd2boot and defboot
> 9121478ee6f2 Merge branch '2022-06-22-platform-updates-and-additions' into next
> 929e581a620f corstone1000: Convert to text file environment
> 781a144a7a7e gxp: Convert to text file environment
>
> > Please new version.
Could you please say something what you want in new version?
> > Thanks,
> > Peng.
> > > ---
> > > Changes in v2:
> > > * Fix commit message
> > > * Adapt code to use p1_p2_bootsrc.h
> > > ---
> > > include/configs/p1_p2_bootsrc.h | 20 ++++++++++++++++++++
> > > include/configs/p1_p2_rdb_pc.h | 13 +++++++++++++
> > > 2 files changed, 33 insertions(+)
> > >
> > > diff --git a/include/configs/p1_p2_bootsrc.h b/include/configs/p1_p2_bootsrc.h
> > > index a274c57786f5..60741ef544c0 100644
> > > --- a/include/configs/p1_p2_bootsrc.h
> > > +++ b/include/configs/p1_p2_bootsrc.h
> > > @@ -30,6 +30,18 @@
> > > #define RST_NOR_CMD(var, ...) ""
> > > #endif
> > > +#ifdef __SW_BOOT_NOR_BANK_LO
> > > +#define RST_NOR_LO_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_NOR_BANK_LO, __SW_BOOT_MASK))
> > > +#else
> > > +#define RST_NOR_LO_CMD(var, ...) ""
> > > +#endif
> > > +
> > > +#ifdef __SW_BOOT_NOR_BANK_UP
> > > +#define RST_NOR_UP_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_NOR_BANK_UP, __SW_BOOT_MASK))
> > > +#else
> > > +#define RST_NOR_UP_CMD(var, ...) ""
> > > +#endif
> > > +
> > > #ifdef __SW_BOOT_SPI
> > > #define RST_SPI_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_SPI, __SW_BOOT_MASK))
> > > #else
> > > @@ -42,6 +54,12 @@
> > > #define RST_SD_CMD(var, ...) ""
> > > #endif
> > > +#ifdef __SW_BOOT_SD2
> > > +#define RST_SD2_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_SD2, __SW_BOOT_MASK))
> > > +#else
> > > +#define RST_SD2_CMD(var, ...) ""
> > > +#endif
> > > +
> > > #ifdef __SW_BOOT_NAND
> > > #define RST_NAND_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_NAND, __SW_BOOT_MASK))
> > > #else
> > > @@ -53,3 +71,5 @@
> > > #else
> > > #define RST_PCIE_CMD(var, ...) ""
> > > #endif
> > > +
> > > +#define RST_DEF_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(0x00, 0xff))
> > > diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
> > > index 47bd20eeeafb..50ce2d9aaed4 100644
> > > --- a/include/configs/p1_p2_rdb_pc.h
> > > +++ b/include/configs/p1_p2_rdb_pc.h
> > > @@ -25,6 +25,9 @@
> > > #define __SW_NOR_BANK_MASK 0xfd
> > > #define __SW_NOR_BANK_UP 0x00
> > > #define __SW_NOR_BANK_LO 0x02
> > > +#define __SW_BOOT_NOR_BANK_UP 0x5c /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */
> > > +#define __SW_BOOT_NOR_BANK_LO 0x5e /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */
> > > +#define __SW_BOOT_NOR_BANK_MASK 0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */
> > > #define CONFIG_SYS_L2_SIZE (256 << 10)
> > > #endif
> > > @@ -54,6 +57,9 @@
> > > #define __SW_NOR_BANK_MASK 0xfd
> > > #define __SW_NOR_BANK_UP 0x00
> > > #define __SW_NOR_BANK_LO 0x02
> > > +#define __SW_BOOT_NOR_BANK_UP 0x64 /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */
> > > +#define __SW_BOOT_NOR_BANK_LO 0x66 /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */
> > > +#define __SW_BOOT_NOR_BANK_MASK 0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */
> > > #define CONFIG_SYS_L2_SIZE (256 << 10)
> > > /*
> > > * Dynamic MTD Partition support with mtdparts
> > > @@ -73,6 +79,9 @@
> > > #define __SW_NOR_BANK_MASK 0xfd
> > > #define __SW_NOR_BANK_UP 0x00
> > > #define __SW_NOR_BANK_LO 0x02
> > > +#define __SW_BOOT_NOR_BANK_UP 0xc8 /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */
> > > +#define __SW_BOOT_NOR_BANK_LO 0xca /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */
> > > +#define __SW_BOOT_NOR_BANK_MASK 0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */
> > > #define CONFIG_SYS_L2_SIZE (512 << 10)
> > > /*
> > > * Dynamic MTD Partition support with mtdparts
> > > @@ -605,10 +614,14 @@ __VSCFW_ADDR \
> > > MAP_NOR_LO_CMD(map_lowernorbank) \
> > > MAP_NOR_UP_CMD(map_uppernorbank) \
> > > RST_NOR_CMD(norboot) \
> > > +RST_NOR_LO_CMD(norlowerboot) \
> > > +RST_NOR_UP_CMD(norupperboot) \
> > > RST_SPI_CMD(spiboot) \
> > > RST_SD_CMD(sdboot) \
> > > +RST_SD2_CMD(sd2boot) \
> > > RST_NAND_CMD(nandboot) \
> > > RST_PCIE_CMD(pciboot) \
> > > +RST_DEF_CMD(defboot) \
> > > ""
> > > #define CONFIG_USB_FAT_BOOT \
> >
^ permalink raw reply [flat|nested] 32+ messages in thread