* [PATCH 00/21] Add minimal Tensor/GS101 SoC support and Oriole/Pixel6 board
@ 2023-10-05 15:55 ` Peter Griffin
0 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-05 15:55 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi
Cc: peter.griffin, tudor.ambarus, andre.draszik, semen.protsenko,
soc, devicetree, linux-arm-kernel, linux-samsung-soc, linux-clk,
linux-gpio, linux-watchdog
Hi folks,
This series adds initial SoC support for the GS101 SoC and also initial board
support for Pixel 6 phone (Oriole).
The gs101 / Tensor SoC is also used in Pixel6a (bluejay) and Pixel 6 Pro (raven).
Currently DT is just added for the gs101 SoC and Oriole.
The support added in this series consists of:
* cpus
* pinctrl
* some CCF clock implementation
* watchdog
* uart
* gpio
This is enough to boot through to a busybox initramfs and shell using an upstream
kernel though :) More platform support will be added over the following weeks
and months. Currently we boot with clk_ignore_unused parameter but this will be
updated as more clocks and platform support lands.
For further information on how to build and flash the upstream kernel on your
Pixel 6, with a prebuilt busybox initramfs please refer to the script and
README.md here:
https://git.codelinaro.org/linaro/googlelt/pixelscripts
I've also included the dtbo overlay containing board_id and board_rev in this
series as otherwise the LK bootloader will bootloop if this is not present in
the dtbo partition. It seems like it would be nicer for the upstream kernel to
build all the DT required to boot upstream kernel on a production phone rather
than having to obtain this dtbo from some other place, but if it is a pain point
then I can remove it.
Many thanks,
Peter.
Peter Griffin (21):
dt-bindings: interrupt-controller: Add gs101 interrupt controller
dt-bindings: soc: samsung: exynos-pmu: Add gs101 compatible
dt-bindings: clock: Add Google gs101 clock management unit bindings
dt-bindings: soc: google: exynos-sysreg: add dedicated SYSREG
compatibles to GS101
dt-bindings: watchdog: Document Google gs101 & gs201 watchdog bindings
dt-bindings: arm: google: Add bindings for Google ARM platforms
dt-bindings: pinctrl: samsung: add google,gs101-pinctrl compatible
dt-bindings: pinctrl: samsung: add gs101-wakeup-eint compatible
dt-bindings: clock: gs101: Add cmu_top clock indices
dt-bindings: clock: gs101: Add cmu_apm clock indices
dt-bindings: clock: gs101: Add cmu_misc clock indices
clk: samsung: clk-pll: Add support for pll_{0516,0517,518}
clk: samsung: clk-gs101: Add cmu_top registers, plls, mux and gates
clk: samsung: clk-gs101: add CMU_APM support
clk: google: gs101: Add support for CMU_MISC clock unit
pinctrl: samsung: Add gs101 SoC pinctrl configuration
watchdog: s3c2410_wdt: Add support for Google tensor SoCs
arm64: dts: google: Add initial Google gs101 SoC support
google/gs101: Add dt overlay for oriole board
arm64: defconfig: Enable Google Tensor SoC
MAINTAINERS: add entry for Google Tensor SoC
.../devicetree/bindings/arm/google.yaml | 46 +
.../bindings/clock/google,gs101-clock.yaml | 109 +
.../samsung,pinctrl-wakeup-interrupt.yaml | 2 +
.../bindings/pinctrl/samsung,pinctrl.yaml | 4 +-
.../bindings/soc/samsung/exynos-pmu.yaml | 2 +
.../soc/samsung/samsung,exynos-sysreg.yaml | 7 +
.../bindings/watchdog/samsung-wdt.yaml | 10 +-
MAINTAINERS | 11 +
arch/arm64/Kconfig.platforms | 6 +
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/google/Makefile | 7 +
arch/arm64/boot/dts/google/gs101-oriole.dts | 68 +
arch/arm64/boot/dts/google/gs101-oriole.dtso | 21 +
arch/arm64/boot/dts/google/gs101-pinctrl.dtsi | 1134 +++++++++
arch/arm64/boot/dts/google/gs101-pinctrl.h | 17 +
arch/arm64/boot/dts/google/gs101.dtsi | 501 ++++
arch/arm64/configs/defconfig | 1 +
drivers/clk/samsung/Kconfig | 9 +
drivers/clk/samsung/Makefile | 1 +
drivers/clk/samsung/clk-gs101.c | 2171 +++++++++++++++++
drivers/clk/samsung/clk-pll.c | 9 +-
drivers/clk/samsung/clk-pll.h | 3 +
.../pinctrl/samsung/pinctrl-exynos-arm64.c | 163 ++
drivers/pinctrl/samsung/pinctrl-exynos.c | 68 +-
drivers/pinctrl/samsung/pinctrl-exynos.h | 44 +
drivers/pinctrl/samsung/pinctrl-samsung.c | 4 +
drivers/pinctrl/samsung/pinctrl-samsung.h | 24 +
drivers/watchdog/s3c2410_wdt.c | 116 +-
include/dt-bindings/clock/gs101.h | 232 ++
.../dt-bindings/interrupt-controller/gs101.h | 758 ++++++
30 files changed, 5533 insertions(+), 16 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/google.yaml
create mode 100644 Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
create mode 100644 arch/arm64/boot/dts/google/Makefile
create mode 100644 arch/arm64/boot/dts/google/gs101-oriole.dts
create mode 100644 arch/arm64/boot/dts/google/gs101-oriole.dtso
create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.dtsi
create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.h
create mode 100644 arch/arm64/boot/dts/google/gs101.dtsi
create mode 100644 drivers/clk/samsung/clk-gs101.c
create mode 100644 include/dt-bindings/clock/gs101.h
create mode 100644 include/dt-bindings/interrupt-controller/gs101.h
--
2.42.0.582.g8ccd20d70d-goog
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 150+ messages in thread* [PATCH 01/21] dt-bindings: interrupt-controller: Add gs101 interrupt controller
2023-10-05 15:55 ` Peter Griffin
@ 2023-10-05 15:55 ` Peter Griffin
-1 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-05 15:55 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi
Cc: peter.griffin, tudor.ambarus, andre.draszik, semen.protsenko,
soc, devicetree, linux-arm-kernel, linux-samsung-soc, linux-clk,
linux-gpio, linux-watchdog
Add the gs101 SoC interrupt header that provides human readable
constants for all the IRQs in the SoC.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
.../dt-bindings/interrupt-controller/gs101.h | 758 ++++++++++++++++++
1 file changed, 758 insertions(+)
create mode 100644 include/dt-bindings/interrupt-controller/gs101.h
diff --git a/include/dt-bindings/interrupt-controller/gs101.h b/include/dt-bindings/interrupt-controller/gs101.h
new file mode 100644
index 000000000000..51c8eb54eca2
--- /dev/null
+++ b/include/dt-bindings/interrupt-controller/gs101.h
@@ -0,0 +1,758 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * This header provides constants for gs101 interrupt controller.
+ *
+ * Copyright 2019-2023 Google LLC
+ *
+ */
+
+#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_GS101_H
+#define _DT_BINDINGS_INTERRUPT_CONTROLLER_GS101_H
+
+#define ITNO IRQ_TYPE_NONE
+#define ITER IRQ_TYPE_EDGE_RISING
+#define ITEF IRQ_TYPE_EDGE_FALLING
+#define ITEB IRQ_TYPE_EDGE_BOTH
+#define ITLH IRQ_TYPE_LEVEL_HIGH
+#define ITLL IRQ_TYPE_LEVEL_LOW
+
+#define IRQ_ALIVE_EINT0 0
+#define IRQ_ALIVE_EINT1 1
+#define IRQ_ALIVE_EINT2 2
+#define IRQ_ALIVE_EINT3 3
+#define IRQ_ALIVE_EINT4 4
+#define IRQ_ALIVE_EINT5 5
+#define IRQ_ALIVE_EINT6 6
+#define IRQ_ALIVE_EINT7 7
+#define IRQ_ALIVE_EINT8 8
+#define IRQ_ALIVE_EINT9 9
+#define IRQ_ALIVE_EINT10 10
+#define IRQ_ALIVE_EINT11 11
+#define IRQ_ALIVE_EINT12 12
+#define IRQ_ALIVE_EINT13 13
+#define IRQ_ALIVE_EINT14 14
+#define IRQ_ALIVE_EINT15 15
+#define IRQ_ALIVE_EINT16 16
+#define IRQ_ALIVE_EINT17 17
+#define IRQ_ALIVE_EINT18 18
+#define IRQ_ALIVE_EINT19 19
+#define IRQ_ALIVE_EINT20 20
+#define IRQ_ALIVE_EINT21 21
+#define IRQ_ALIVE_EINT22 22
+#define IRQ_ALIVE_EINT23 23
+#define IRQ_ALIVE_EINT24 24
+#define IRQ_ALIVE_EINT25 25
+#define IRQ_ALIVE_EINT26 26
+#define IRQ_ALIVE_EINT27 27
+#define IRQ_ALIVE_EINT28 28
+#define IRQ_ALIVE_EINT29 29
+#define IRQ_ALIVE_EINT30 30
+#define IRQ_ALIVE_EINT31 31
+#define IRQ_ALIVE_EINT32 32
+#define IRQ_ALIVE_EINT33 33
+#define IRQ_ALIVE_EINT34 34
+#define IRQ_ALIVE_EINT35 35
+#define IRQ_ALIVE_EINT36 36
+#define IRQ_ALIVE_EINT37 37
+#define IRQ_ALIVE_EINT38 38
+#define IRQ_ALIVE_EINT39 39
+#define IRQ_ALIVE_EINT40 40
+#define IRQ_ALIVE_EINT41 41
+#define IRQ_ALIVE_EINT42 42
+#define IRQ_ALIVE_EINT43 43
+#define IRQ_ALIVE_EINT44 44
+#define IRQ_ALIVE_EINT45 45
+#define IRQ_ALIVE_EINT46 46
+#define IRQ_ALIVE_EINT47 47
+#define IRQ_ALIVE_EINT48 48
+#define IRQ_ALIVE_EINT49 49
+#define IRQ_ALIVE_EINT50 50
+#define IRQ_ALIVE_EINT51 51
+#define IRQ_ALIVE_EINT52 52
+#define IRQ_ALIVE_EINT53 53
+#define IRQ_ALIVE_EINT54 54
+#define IRQ_ALIVE_EINT55 55
+#define IRQ_ALIVE_EINT56 56
+#define IRQ_ALIVE_EINT57 57
+#define IRQ_ALIVE_EINT58 58
+#define IRQ_ALIVE_EINT59 59
+#define IRQ_ALIVE_EINT60 60
+#define IRQ_ALIVE_EINT61 61
+#define IRQ_ALIVE_EINT62 62
+#define IRQ_ALIVE_EINT63 63
+#define IRQ_ALIVE_EINT64 64
+#define IRQ_ALIVE_EINT65 65
+#define IRQ_ALIVE_EINT66 66
+#define IRQ_APM_USI0_UART_ALIVE 67
+#define IRQ_APM_USI0_USI_ALIVE 68
+#define IRQ_APM_USI1_UART_ALIVE 69
+#define IRQ_COMB_SFI_CE_NONSECURE_SYSREG_APM_ALIVE 70
+#define IRQ_COMB_SFI_UCE_NONSECURE_SYSREG_APM_ALIVE 71
+#define IRQ_MAILBOX_AOC2AP_ALIVE 72
+#define IRQ_MAILBOX_APM2AP_ALIVE 73
+#define IRQ_MAILBOX_DBGCORE2AP_ALIVE 74
+#define IRQ_OCP_WARN_CPUCL1_ALIVE 75
+#define IRQ_OCP_WARN_CPUCL2_ALIVE 76
+#define IRQ_OCP_WARN_GPU_ALIVE 77
+#define IRQ_OCP_WARN_TPU_ALIVE 78
+#define IRQ_RTC_ALARM_INT_ALIVE 79
+#define IRQ_RTC_TIC_INT_0_ALIVE 80
+#define IRQ_SMPL_WARN_ALIVE 81
+#define IRQ_SOFT_OCP_WARN_CPUCL1_ALIVE 82
+#define IRQ_SOFT_OCP_WARN_CPUCL2_ALIVE 83
+#define IRQ_SOFT_OCP_WARN_GPU_ALIVE 84
+#define IRQ_SOFT_OCP_WARN_TPU_ALIVE 85
+#define IRQ_SPEEDY_APM_ALIVE 86
+#define IRQ_SPEEDY_SUB_APM_ALIVE 87
+#define IRQ_TRTC_ALARM_INT_ALIVE 88
+#define IRQ_TRTC_TIC_INT_0_ALIVE 89
+#define IRQ_VDROOP1_ALIVE 90
+#define IRQ_VDROOP2_ALIVE 91
+#define IRQ_WDT_APM_ALIVE 92
+#define IRQ_WDT_DBGCORE_ALIVE 93
+#define NONSEQINT__UASC_APM_ALIVE 94
+#define NONSEQINT__UASC_DBGCORE_ALIVE 95
+#define NONSEQINT__UASC_G_SWD_ALIVE 96
+#define NONSEQINT__UASC_P_AOCAPM_ALIVE 97
+#define NONSEQINT__UASC_P_APM_ALIVE 98
+#define O_INTERRUPT_S2__SYSMMU_D_APM_ALIVE 99
+#define TZINT__UASC_APM_ALIVE 100
+#define TZINT__UASC_DBGCORE_ALIVE 101
+#define TZINT__UASC_G_SWD_ALIVE 102
+#define TZINT__UASC_P_AOCAPM_ALIVE 103
+#define TZINT__UASC_P_APM_ALIVE 104
+#define INTR_AOC_PPMU_AOC 105
+#define INTR_AOCUSB_PPMU_AOC 106
+#define IRQ_AOC_TIMER0_AOC 107
+#define IRQ_AOC_Watchdog_CPU_AOC 108
+#define INTREQ_AOCPLL_LOCK_STATUS_AOC 109
+#define IRQ_SYSMMU_AOC_S1_NS_AOC 110
+#define IRQ_SYSMMU_AOC_S1_S_AOC 111
+#define IRQ_SYSMMU_AOC_S2_AOC 112
+#define IRQ_UASC_NS_AOC_AOC 113
+#define IRQ_UASC_S_AOC_AOC 114
+#define IRQ_BO_XINT_BO 115
+#define IRQ_PPMU_UPPER_OR_NORMAL_BO 116
+#define IRQ_SSMT_BO_BO 117
+#define IRQ_SYSMMU_S1_NS_BO_BO 118
+#define IRQ_SYSMMU_S1_S_BO_BO 119
+#define IRQ_SYSMMU_S2_BO_BO 120
+#define IRQ_UASC_NS_BO_BO 121
+#define IRQ_UASC_S_BO_BO 122
+#define IRQ_PPC_CYCLE_AOC_L_BUS0 123
+#define IRQ_PPC_CYCLE_AOC_UON_BUS0 124
+#define IRQ_PPC_EVENT_AOC_L_BUS0 125
+#define IRQ_PPC_EVENT_AOC_UON_BUS0 126
+#define IRQ_TREX_D_BUS0_debugInterrupt_BUS0 127
+#define IRQ_TREX_P_BUS0_debugInterrupt_BUS0 128
+#define IRQ_TREX_PPMU_BUS0M0_BUS0 129
+#define IRQ_TREX_D0_BUS1_debugInterrupt_BUS1 130
+#define IRQ_TREX_P_BUS1_debugInterrupt_BUS1 131
+#define IRQ_TREX_PPMU_BUS1M0_BUS1 132
+#define IRQ_TREX_PPMU_BUS1M1_BUS1 133
+#define IRQ_TREX_PPMU_BUS1M2_BUS1 134
+#define IRQ_TREX_PPMU_BUS1M3_BUS1 135
+#define IRQ_PPC_CYCLE_BUS2_L_BUS2 136
+#define IRQ_PPC_CYCLE_BUS2_UON_BUS2 137
+#define IRQ_PPC_CYCLE_G3D_L_BUS2 138
+#define IRQ_PPC_CYCLE_G3D_UON_BUS2 139
+#define IRQ_PPC_CYCLE_TPU_L_BUS2 140
+#define IRQ_PPC_CYCLE_TPU_UON_BUS2 141
+#define IRQ_PPC_EVENT_BUS2_L_AND_BUS2 142
+#define IRQ_PPC_EVENT_BUS2_L_OR_BUS2 143
+#define IRQ_PPC_EVENT_BUS2_UON_AND_BUS2 144
+#define IRQ_PPC_EVENT_BUS2_UON_OR_BUS2 145
+#define IRQ_PPC_EVENT_G3D_L_AND_BUS2 146
+#define IRQ_PPC_EVENT_G3D_L_OR_BUS2 147
+#define IRQ_PPC_EVENT_G3D_UON_AND_BUS2 148
+#define IRQ_PPC_EVENT_G3D_UON_OR_BUS2 149
+#define IRQ_PPC_EVENT_TPU_L_BUS2 150
+#define IRQ_PPC_EVENT_TPU_UON_BUS2 151
+#define IRQ_PPCFW_G3D_BUS2 152
+#define IRQ_SYSMMU_G3D0_BUS2 153
+#define IRQ_SYSMMU_G3D1_BUS2 154
+#define IRQ_SYSMMU_G3D2_BUS2 155
+#define IRQ_SYSMMU_G3D3_BUS2 156
+#define IRQ_TREX_D_BUS2_debugInterrupt_BUS2 157
+#define IRQ_TREX_P_BUS2_debugInterrupt_BUS2 158
+#define IRQ_TREX_PPMU_BUS2M0_BUS2 159
+#define IRQ_TREX_PPMU_BUS2M1_BUS2 160
+#define IRQ_TREX_PPMU_BUS2M2_BUS2 161
+#define IRQ_TREX_PPMU_BUS2M3_BUS2 162
+#define IRQ_TREX_PPMU_GPU0_BUS2 163
+#define IRQ_TREX_PPMU_GPU1_BUS2 164
+#define IRQ_TREX_PPMU_GPU2_BUS2 165
+#define IRQ_TREX_PPMU_GPU3_BUS2 166
+#define IRQ_BDU_O_INT_CORE 167
+#define IRQ_CCI_nERRIRQ_CORE 168
+#define IRQ_CCI_nEVNTCNTOVERFLOW_0_CORE 169
+#define IRQ_CCI_nEVNTCNTOVERFLOW_1_CORE 170
+#define IRQ_CCI_nEVNTCNTOVERFLOW_2_CORE 171
+#define IRQ_CCI_nEVNTCNTOVERFLOW_3_CORE 172
+#define IRQ_CCI_nEVNTCNTOVERFLOW_4_CORE 173
+#define IRQ_CCI_nEVNTCNTOVERFLOW_5_CORE 174
+#define IRQ_CCI_nEVNTCNTOVERFLOW_6_CORE 175
+#define IRQ_CCI_nEVNTCNTOVERFLOW_7_CORE 176
+#define IRQ_CORE_PPC_CON_O_IL_AND_PPC_BUS2_EVENT_CORE 177
+#define IRQ_CORE_PPC_CON_O_IL_AND_PPC_CCI_EVENT_CORE 178
+#define IRQ_CORE_PPC_CON_O_IL_AND_PPC_CPUCL0_EVENT_CORE 179
+#define IRQ_CORE_PPC_CON_O_IL_OR_PPC_BUS2_EVENT_CORE 180
+#define IRQ_CORE_PPC_CON_O_IL_OR_PPC_CCI_EVENT_CORE 181
+#define IRQ_CORE_PPC_CON_O_IL_OR_PPC_CPUCL0_EVENT_CORE 182
+#define IRQ_CORE_PPC_CON_O_IUON_AND_PPC_BUS2_EVENT_CORE 183
+#define IRQ_CORE_PPC_CON_O_IUON_AND_PPC_CCI_EVENT_CORE 184
+#define IRQ_CORE_PPC_CON_O_IUON_AND_PPC_CPUCL0_EVENT_CORE 185
+#define IRQ_CORE_PPC_CON_O_IUON_OR_PPC_BUS2_EVENT_CORE 186
+#define IRQ_CORE_PPC_CON_O_IUON_OR_PPC_CCI_EVENT_CORE 187
+#define IRQ_CORE_PPC_CON_O_IUON_OR_PPC_CPUCL0_EVENT_CORE 188
+#define IRQ_LD_SLC_CH0_O_APC_NS_IRQ_CORE 189
+#define IRQ_LD_SLC_CH0_O_APC_S_IRQ_CORE 190
+#define IRQ_LD_SLC_CH0_O_PPMPU_IRQ_CORE 191
+#define IRQ_LD_SLC_CH0_O_UASC_GSA_IRQ_CORE 192
+#define IRQ_LD_SLC_CH0_O_UASC_NS_IRQ_CORE 193
+#define IRQ_LD_SLC_CH0_O_UASC_TZ_IRQ_CORE 194
+#define IRQ_LD_SLC_CH1_O_APC_NS_IRQ_CORE 195
+#define IRQ_LD_SLC_CH1_O_APC_S_IRQ_CORE 196
+#define IRQ_LD_SLC_CH1_O_PPMPU_IRQ_CORE 197
+#define IRQ_LD_SLC_CH1_O_UASC_GSA_IRQ_CORE 198
+#define IRQ_LD_SLC_CH1_O_UASC_NS_IRQ_CORE 199
+#define IRQ_LD_SLC_CH1_O_UASC_TZ_IRQ_CORE 200
+#define IRQ_LD_SLC_CH2_O_APC_NS_IRQ_CORE 201
+#define IRQ_LD_SLC_CH2_O_APC_S_IRQ_CORE 202
+#define IRQ_LD_SLC_CH2_O_PPMPU_IRQ_CORE 203
+#define IRQ_LD_SLC_CH2_O_UASC_GSA_IRQ_CORE 204
+#define IRQ_LD_SLC_CH2_O_UASC_NS_IRQ_CORE 205
+#define IRQ_LD_SLC_CH2_O_UASC_TZ_IRQ_CORE 206
+#define IRQ_LD_SLC_CH3_O_APC_NS_IRQ_CORE 207
+#define IRQ_LD_SLC_CH3_O_APC_S_IRQ_CORE 208
+#define IRQ_LD_SLC_CH3_O_PPMPU_IRQ_CORE 209
+#define IRQ_LD_SLC_CH3_O_UASC_GSA_IRQ_CORE 210
+#define IRQ_LD_SLC_CH3_O_UASC_NS_IRQ_CORE 211
+#define IRQ_LD_SLC_CH3_O_UASC_TZ_IRQ_CORE 212
+#define IRQ_PPC_BUS0_M0_CYCLE_O_IL_CORE 213
+#define IRQ_PPC_BUS0_M0_CYCLE_O_IUON_CORE 214
+#define IRQ_PPC_BUS0_M0_EVENT_O_IL_CORE 215
+#define IRQ_PPC_BUS0_M0_EVENT_O_IUON_CORE 216
+#define IRQ_PPC_BUS2_M0_CYCLE_O_IL_CORE 217
+#define IRQ_PPC_BUS2_M0_CYCLE_O_IUON_CORE 218
+#define IRQ_PPC_CCI_M1_CYCLE_O_IL_CORE 219
+#define IRQ_PPC_CCI_M1_CYCLE_O_IUON_CORE 220
+#define IRQ_PPC_CPUCL0_D0_CYCLE_O_IL_CORE 221
+#define INTREQ__SECURE_LOG 224
+#define IRQ_PPC_CPUCL0_D0_CYCLE_O_IUON_CORE 227
+#define IRQ_PPC_DEBUG_O_IL_CORE 228
+#define IRQ_PPC_DEBUG_O_IUON_CORE 229
+#define IRQ_PPC_EH_CYCLE_O_IL_CORE 230
+#define IRQ_PPC_EH_CYCLE_O_IUON_CORE 231
+#define IRQ_PPC_EH_EVENT_O_IL_CORE 232
+#define IRQ_PPC_EH_EVENT_O_IUON_CORE 233
+#define IRQ_PPC_IO_CYCLE_O_IL_CORE 234
+#define IRQ_PPC_IO_CYCLE_O_IUON_CORE 235
+#define IRQ_PPC_IO_EVENT_O_IL_CORE 236
+#define IRQ_PPC_IO_EVENT_O_IUON_CORE 237
+#define IRQ_PPMU_ACE_CPUCL0_O_IL_CORE 238
+#define IRQ_PPMU_ACE_CPUCL0_O_IUON_CORE 239
+#define IRQ_PPMU_ACE_CPUCL1_O_IL_CORE 240
+#define IRQ_PPMU_ACE_CPUCL1_O_IUON_CORE 241
+#define IRQ_TREX_D_CORE_debugInterrupt_CORE 242
+#define IRQ_TREX_D_CORE_ppcInterrupt_CORE_CCI_CORE 243
+#define IRQ_TREX_D_CORE_ppcInterrupt_CORE_DP_CORE 244
+#define IRQ_TREX_D_CORE_ppcInterrupt_CORE_M0_CORE 245
+#define IRQ_TREX_D_CORE_ppcInterrupt_CORE_M1_CORE 246
+#define IRQ_TREX_D_CORE_ppcInterrupt_CORE_M2_CORE 247
+#define IRQ_TREX_D_CORE_ppcInterrupt_CORE_M3_CORE 248
+#define IRQ_TREX_D_CORE_ppcInterrupt_CPU0_CORE 249
+#define IRQ_TREX_D_CORE_ppcInterrupt_CPU1_CORE 250
+#define IRQ_TREX_D_CORE_ppcInterrupt_CPU2_CORE 251
+#define IRQ_TREX_D_CORE_ppcInterrupt_CPU3_CORE 252
+#define IRQ_TREX_P_CORE_debugInterrupt_CORE 253
+#define IRQ_TREX_P_CORE_ppcInterrupt_CCI_CORE 254
+#define IRQ_TREX_P_CORE_ppcInterrupt_CORE_ALIVE_CORE 255
+#define IRQ_TREX_P_CORE_ppcInterrupt_CORE_DP_CORE 256
+#define IRQ_CPUCL0_CLUSTERPMUIRQ_CPUCL0 257
+#define IRQ_CPUCL0_DDD_APBIF0_FAST_PEND_CPUCL0 258
+#define IRQ_CPUCL0_DDD_APBIF0_HIGH_PEND_CPUCL0 259
+#define IRQ_CPUCL0_DDD_APBIF0_LOW_PEND_CPUCL0 260
+#define IRQ_CPUCL0_DDD_APBIF0_SLOW_PEND_CPUCL0 261
+#define IRQ_CPUCL0_DDD_APBIF1_FAST_PEND_CPUCL0 262
+#define IRQ_CPUCL0_DDD_APBIF1_HIGH_PEND_CPUCL0 263
+#define IRQ_CPUCL0_DDD_APBIF1_LOW_PEND_CPUCL0 264
+#define IRQ_CPUCL0_DDD_APBIF1_SLOW_PEND_CPUCL0 265
+#define IRQ_CPUCL0_DDD_APBIF2_FAST_PEND_CPUCL0 266
+#define IRQ_CPUCL0_DDD_APBIF2_HIGH_PEND_CPUCL0 267
+#define IRQ_CPUCL0_DDD_APBIF2_LOW_PEND_CPUCL0 268
+#define IRQ_CPUCL0_DDD_APBIF2_SLOW_PEND_CPUCL0 269
+#define IRQ_CPUCL0_DDD_APBIF3_FAST_PEND_CPUCL0 270
+#define IRQ_CPUCL0_DDD_APBIF3_HIGH_PEND_CPUCL0 271
+#define IRQ_CPUCL0_DDD_APBIF3_LOW_PEND_CPUCL0 272
+#define IRQ_CPUCL0_DDD_APBIF3_SLOW_PEND_CPUCL0 273
+#define IRQ_CPUCL0_ERRIRQ_0_CPUCL0 274
+#define IRQ_CPUCL0_ERRIRQ_1_CPUCL0 275
+#define IRQ_CPUCL0_ERRIRQ_2_CPUCL0 276
+#define IRQ_CPUCL0_ERRIRQ_3_CPUCL0 277
+#define IRQ_CPUCL0_ERRIRQ_4_CPUCL0 278
+#define IRQ_CPUCL0_ERRIRQ_5_CPUCL0 279
+#define IRQ_CPUCL0_ERRIRQ_6_CPUCL0 280
+#define IRQ_CPUCL0_ERRIRQ_7_CPUCL0 281
+#define IRQ_CPUCL0_ERRIRQ_8_CPUCL0 282
+#define IRQ_CPUCL0_FAULTIRQ_0_CPUCL0 283
+#define IRQ_CPUCL0_FAULTIRQ_1_CPUCL0 284
+#define IRQ_CPUCL0_FAULTIRQ_2_CPUCL0 285
+#define IRQ_CPUCL0_FAULTIRQ_3_CPUCL0 286
+#define IRQ_CPUCL0_FAULTIRQ_4_CPUCL0 287
+#define IRQ_CPUCL0_FAULTIRQ_5_CPUCL0 288
+#define IRQ_CPUCL0_FAULTIRQ_6_CPUCL0 289
+#define IRQ_CPUCL0_FAULTIRQ_7_CPUCL0 290
+#define IRQ_CPUCL0_FAULTIRQ_8_CPUCL0 291
+#define O_HPM_IRQ_CPUCL0_CPUCL0 292
+#define IRQ_CPUCL0_S2MPU_IRQ_CPUCL0 293
+#define IRQ_CSIS0_CSIS 294
+#define IRQ_CSIS1_CSIS 295
+#define IRQ_CSIS2_CSIS 296
+#define IRQ_CSIS3_CSIS 297
+#define IRQ_CSIS4_CSIS 298
+#define IRQ_CSIS5_CSIS 299
+#define IRQ_CSIS6_CSIS 300
+#define IRQ_CSIS7_CSIS 301
+#define IRQ_CSIS_DMA0_CSIS 302
+#define IRQ_CSIS_DMA1_CSIS 303
+#define IRQ_CSIS_DMA2_CSIS 304
+#define IRQ_CSIS_DMA3_CSIS 305
+#define IRQ_EBUF_OVERFLOW0_CSIS 306
+#define IRQ_EBUF_OVERFLOW1_CSIS 307
+#define IRQ_EBUF_OVERFLOW2_CSIS 308
+#define IRQ_EBUF_OVERFLOW3_CSIS 309
+#define IRQ_MUTE_CSIS0_CSIS 310
+#define IRQ_MUTE_CSIS1_CSIS 311
+#define IRQ_MUTE_CSIS2_CSIS 312
+#define IRQ_MUTE_CSIS3_CSIS 313
+#define IRQ_MUTE_STRP0_CSIS 314
+#define IRQ_MUTE_STRP1_CSIS 315
+#define IRQ_MUTE_STRP2_CSIS 316
+#define IRQ_MUTE_ZSL0_CSIS 317
+#define IRQ_MUTE_ZSL1_CSIS 318
+#define IRQ_MUTE_ZSL2_CSIS 319
+#define IRQ_PPMU_D0_CSIS_UPPER_OR_NORMAL_CSIS 320
+#define IRQ_PPMU_D1_CSIS_UPPER_OR_NORMAL_CSIS 321
+#define IRQ_STRP_DMA0_CSIS 322
+#define IRQ_STRP_DMA1_CSIS 323
+#define IRQ_STRP_DMA2_CSIS 324
+#define IRQ_SYSMMU_D0_CSIS_S1_NS_CSIS 325
+#define IRQ_SYSMMU_D0_CSIS_S1_S_CSIS 326
+#define IRQ_SYSMMU_D0_CSIS_S2_CSIS 327
+#define IRQ_SYSMMU_D1_CSIS_S1_NS_CSIS 328
+#define IRQ_SYSMMU_D1_CSIS_S1_S_CSIS 329
+#define IRQ_SYSMMU_D1_CSIS_S2_CSIS 330
+#define IRQ_ZSL_DMA0_CSIS 331
+#define IRQ_ZSL_DMA1_CSIS 332
+#define IRQ_ZSL_DMA2_CSIS 333
+#define IRQ_DISP_DECON0_DQE_DIMMING_END_DISP 334
+#define IRQ_DISP_DECON0_DQE_DIMMING_START_DISP 335
+#define IRQ_DISP_DECON0_EXTRA_DISP 336
+#define IRQ_DISP_DECON0_FRAME_DONE_DISP 337
+#define IRQ_DISP_DECON0_FRAME_START_DISP 338
+#define IRQ_DISP_DECON1_EXTRA_DISP 339
+#define IRQ_DISP_DECON1_FRAME_DONE_DISP 340
+#define IRQ_DISP_DECON1_FRAME_START_DISP 341
+#define IRQ_DISP_DECON2_EXTRA_DISP 342
+#define IRQ_DISP_DECON2_FRAME_DONE_DISP 343
+#define IRQ_DISP_DECON2_FRAME_START_DISP 344
+#define IRQ_DISP_DSIM0_DISP 345
+#define IRQ_DISP_DSIM1_DISP 346
+#define IRQ_DNS_0_DNS 347
+#define IRQ_DNS_1_DNS 348
+#define IRQ_DNS_MUTE_DNS 349
+#define IRQ_PPMU_DNS_UPPER_OR_NORMAL_DNS 350
+#define IRQ_SYSMMU_DNS_S1_NS_DNS 351
+#define IRQ_SYSMMU_DNS_S1_S_DNS 352
+#define IRQ_SYSMMU_DNS_S2_DNS 353
+#define IRQ_DPU_DMA_L0_DPU 354
+#define IRQ_DPU_DMA_L1_DPU 355
+#define IRQ_DPU_DMA_L2_DPU 356
+#define IRQ_DPU_DMA_L3_DPU 357
+#define IRQ_DPU_DMA_L4_DPU 358
+#define IRQ_DPU_DMA_L5_DPU 359
+#define IRQ_DPU_DMA_WB_DPU 360
+#define IRQ_DPU_DPP_L0_DPU 361
+#define IRQ_DPU_DPP_L1_DPU 362
+#define IRQ_DPU_DPP_L2_DPU 363
+#define IRQ_DPU_DPP_L3_DPU 364
+#define IRQ_DPU_DPP_L4_DPU 365
+#define IRQ_DPU_DPP_L5_DPU 366
+#define IRQ_PPMU_DPUD0_UPPER_OR_NORMAL_DPU 367
+#define IRQ_PPMU_DPUD1_UPPER_OR_NORMAL_DPU 368
+#define IRQ_PPMU_DPUD2_UPPER_OR_NORMAL_DPU 369
+#define IRQ_SYSMMU_DPUD0_S1_NS_DPU 370
+#define IRQ_SYSMMU_DPUD0_S1_S_DPU 371
+#define IRQ_SYSMMU_DPUD0_S2_DPU 372
+#define IRQ_SYSMMU_DPUD1_S1_NS_DPU 373
+#define IRQ_SYSMMU_DPUD1_S1_S_DPU 374
+#define IRQ_SYSMMU_DPUD1_S2_DPU 375
+#define IRQ_SYSMMU_DPUD2_S1_NS_DPU 376
+#define IRQ_SYSMMU_DPUD2_S1_S_DPU 377
+#define IRQ_SYSMMU_DPUD2_S2_DPU 378
+#define IRQ_EH_0_EH 379
+#define IRQ_EH_1_EH 380
+#define IRQ_EH_2_EH 381
+#define IRQ_EH_3_EH 382
+#define IRQ_EH_4_EH 383
+#define IRQ_EH_5_EH 384
+#define IRQ_EH_6_EH 385
+#define IRQ_EH_7_EH 386
+#define IRQ_EH_8_EH 387
+#define IRQ_EH_9_EH 388
+#define IRQ_PPMU_UPPER_OR_NORMAL_EH 389
+#define IRQ_SSMT_EH_EH 390
+#define IRQ_SYSMMU_S2_EH_EH 391
+#define IRQ_UASC_GSA_EH_EH 392
+#define IRQ_UASC_NS_EH_EH 393
+#define IRQ_UASC_S_EH_EH 394
+#define IRQ_G2D_G2D 395
+#define IRQ_JPEG_G2D 396
+#define IRQ_PPMU_D0_G2D_interrupt_upper_or_normal_G2D 397
+#define IRQ_PPMU_D1_G2D_interrupt_upper_or_normal_G2D 398
+#define IRQ_PPMU_D2_G2D_interrupt_upper_or_normal_G2D 399
+#define IRQ_SSMT_D0_G2D_intreq_G2D 400
+#define IRQ_SSMT_D1_G2D_intreq_G2D 401
+#define IRQ_SSMT_D2_G2D_intreq_G2D 402
+#define IRQ_SYSMMU_D0_G2D_interrupt_s1_ns_G2D 403
+#define IRQ_SYSMMU_D0_G2D_interrupt_s2_G2D 404
+#define IRQ_SYSMMU_D0_G2D_interrupt_s1_s_G2D 405
+#define IRQ_SYSMMU_D1_G2D_interrupt_s1_ns_G2D 406
+#define IRQ_SYSMMU_D1_G2D_interrupt_s2_G2D 407
+#define IRQ_SYSMMU_D1_G2D_interrupt_s1_s_G2D 408
+#define IRQ_SYSMMU_D2_G2D_interrupt_s1_ns_G2D 409
+#define IRQ_SYSMMU_D2_G2D_interrupt_s2_G2D 410
+#define IRQ_SYSMMU_D2_G2D_interrupt_s1_s_G2D 411
+#define IRQ_G3AA_G3AA 412
+#define IRQ_PPMU_G3AA_UPPER_OR_NORMAL_G3AA 413
+#define IRQ_SSMT_G3AA_G3AA 414
+#define IRQ_SYSMMU_G3AA_S1_NS_G3AA 415
+#define IRQ_SYSMMU_G3AA_S1_S_G3AA 416
+#define IRQ_SYSMMU_G3AA_S2_G3AA 417
+#define IRQ_G3D_IRQEVENT_G3D 418
+#define IRQ_G3D_IRQGPU_G3D 419
+#define IRQ_G3D_IRQJOB_G3D 420
+#define IRQ_G3D_IRQMMU_G3D 421
+#define IRQ_UASC_GSA_G3D_G3D 422
+#define IRQ_UASC_NS_G3D_G3D 423
+#define IRQ_UASC_S_G3D_G3D 424
+#define O_ADD_APBIF_G3D_FLAG_IRQ_PEND_G3D 425
+#define O_DDD_APBIF_G3D_DD_ERR_IRQ_FAST_PEND_G3D 426
+#define O_DDD_APBIF_G3D_DD_ERR_IRQ_SLOW_PEND_G3D 427
+#define O_HPM_IRQ_G3D 428
+#define IRQ_GDC0_IRQ_GDC 429
+#define IRQ_GDC0_Mute_IRQ_GDC 430
+#define IRQ_GDC1_IRQ_GDC 431
+#define IRQ_GDC1_Mute_IRQ_GDC 432
+#define IRQ_PPMU_D0_GDC_UPPER_OR_NORMAL_GDC 433
+#define IRQ_PPMU_D1_GDC_UPPER_OR_NORMAL_GDC 434
+#define IRQ_PPMU_D_SCSC_UPPER_OR_NORMAL_GDC 435
+#define IRQ_SCSC_IRQ_GDC 436
+#define IRQ_SCSC_NonSecu_Mute_IRQ_GDC 437
+#define IRQ_SYSMMU_D0_GDC_S1_NS_GDC 438
+#define IRQ_SYSMMU_D0_GDC_S1_S_GDC 439
+#define IRQ_SYSMMU_D0_GDC_S2_GDC 440
+#define IRQ_SYSMMU_D1_GDC_S1_NS_GDC 441
+#define IRQ_SYSMMU_D1_GDC_S1_S_GDC 442
+#define IRQ_SYSMMU_D1_GDC_S2_GDC 443
+#define IRQ_SYSMMU_D2_GDC_S1_NS_GDC 444
+#define IRQ_SYSMMU_D2_GDC_S1_S_GDC 445
+#define IRQ_SYSMMU_D2_GDC_S2_GDC 446
+#define IRQ_MAILBOX_GSA2NONTZ_GSA 447
+#define IRQ_MAILBOX_GSA2OSCAR_GSA 448
+#define IRQ_MAILBOX_GSA2PAINTBOX_GSA 449
+#define IRQ_MAILBOX_GSA2TZ_GSA 450
+#define SYSMMU_NS__INTERRUPT_GSA 451
+#define SYSMMU_S2MPU__INTERRUPT_GSA 452
+#define SYSMMU_S__INTERRUPT_GSA 453
+#define IRQ_DP_LINK_HSI0 454
+#define IRQ_PPMU_HSI0_AOC_UPPER_OR_NORMAL_HSI0 455
+#define IRQ_PPMU_HSI0_BUS0_UPPER_OR_NORMAL_HSI0 456
+#define IRQ_SYSMMU_USB_HSI0 457
+#define IRQ_USB2_REMOTE_CONNECT_GIC_HSI0 458
+#define IRQ_USB2_REMOTE_TIMER_GIC_HSI0 459
+#define IRQ_USB2_REMOTE_WAKEUP_GIC_HSI0 460
+#define IRQ_USB31DRD_FSVMINUS_GIC_HSI0 461
+#define IRQ_USB31DRD_FSVPLUS_GIC_HSI0 462
+#define IRQ_USB31DRD_GIC_0_HSI0 463
+#define IRQ_USB31DRD_GIC_1_HSI0 464
+#define IRQ_USB_UDBG_HSI0 465
+#define IRQ_USB_WAKEUP_HSI0 466
+#define NONSEQINT__UASC_HSI0_CTRL_HSI0 467
+#define NONSEQINT__UASC_HSI0_LINK_HSI0 468
+#define TZINT__UASC_HSI0_CTRL_HSI0 469
+#define TZINT__UASC_HSI0_LINK_HSI0 470
+#define IRQ_GPIO_HSI1_HSI1 471
+#define IRQ_PCIE_GEN4A_0_HSI1 472
+#define IRQ_PCIE_GEN4A_MSI_0_HSI1 473
+#define IRQ_PCIE_GEN4A_MSI_1_HSI1 474
+#define IRQ_PCIE_GEN4A_MSI_2_HSI1 475
+#define IRQ_PCIE_GEN4A_MSI_3_HSI1 476
+#define IRQ_PCIE_GEN4A_MSI_4_HSI1 477
+#define IRQ_PCIE_GEN4B_0_HSI1 478
+#define IRQ_PCIE_GEN4B_MSI_0_HSI1 479
+#define IRQ_PCIE_GEN4B_MSI_1_HSI1 480
+#define IRQ_PCIE_GEN4B_MSI_2_HSI1 481
+#define IRQ_PCIE_GEN4B_MSI_3_HSI1 482
+#define IRQ_PCIE_GEN4B_MSI_4_HSI1 483
+#define IRQ_PCIE_IA_GEN4A_0_HSI1 484
+#define IRQ_PCIE_IA_GEN4B_0_HSI1 485
+#define IRQ_PCIE_PCS_GEN4_0_HSI1 486
+#define IRQ_PCIE_PCS_GEN4B_0_HSI1 487
+#define IRQ_PPMU_HSI1_UPPER_OR_NORMAL_HSI1 488
+#define IRQ_SSMT_HSI1_HSI1 489
+#define IRQ_SYSMMU_HSI1_S2MPU_HSI1 490
+#define IRQ_UASC_GSA_PCIE_GEN4A_DBI_0_HSI1 491
+#define IRQ_UASC_GSA_PCIE_GEN4A_SLV_0_HSI1 492
+#define IRQ_UASC_GSA_PCIE_GEN4B_DBI_0_HSI1 493
+#define IRQ_UASC_GSA_PCIE_GEN4B_SLV_0_HSI1 494
+#define IRQ_UASC_NS_PCIE_GEN4A_DBI_0_HSI1 495
+#define IRQ_UASC_NS_PCIE_GEN4A_SLV_0_HSI1 496
+#define IRQ_UASC_NS_PCIE_GEN4B_DBI_0_HSI1 497
+#define IRQ_UASC_NS_PCIE_GEN4B_SLV_0_HSI1 498
+#define IRQ_UASC_S_PCIE_GEN4A_DBI_0_HSI1 499
+#define IRQ_UASC_S_PCIE_GEN4A_SLV_0_HSI1 500
+#define IRQ_UASC_S_PCIE_GEN4B_DBI_0_HSI1 501
+#define IRQ_UASC_S_PCIE_GEN4B_SLV_0_HSI1 502
+#define IRQ_GPIO_HSI2_HSI2 503
+#define IRQ_MMC_CARD_HSI2 504
+#define IRQ_NONSEQINT_PCIE_GEN4A_DBI_1_HSI2 505
+#define IRQ_NONSEQINT_PCIE_GEN4A_SLV_1_HSI2 506
+#define IRQ_NONSEQINT_PCIE_GEN4B_DBI_1_HSI2 507
+#define IRQ_NONSEQINT_PCIE_GEN4B_SLV_1_HSI2 508
+#define IRQ_PCIE_GEN4A_1_HSI2 509
+#define IRQ_PCIE_GEN4A_1_MSI_0_HSI2 510
+#define IRQ_PCIE_GEN4A_1_MSI_1_HSI2 511
+#define IRQ_PCIE_GEN4A_1_MSI_2_HSI2 512
+#define IRQ_PCIE_GEN4A_1_MSI_3_HSI2 513
+#define IRQ_PCIE_GEN4A_1_MSI_4_HSI2 514
+#define IRQ_PCIE_GEN4B_1_HSI2 515
+#define IRQ_PCIE_GEN4B_1_MSI_0_HSI2 516
+#define IRQ_PCIE_GEN4B_1_MSI_1_HSI2 517
+#define IRQ_PCIE_GEN4B_1_MSI_2_HSI2 518
+#define IRQ_PCIE_GEN4B_1_MSI_3_HSI2 519
+#define IRQ_PCIE_GEN4B_1_MSI_4_HSI2 520
+#define IRQ_PCIE_IA_GEN4A_1_HSI2 521
+#define IRQ_PCIE_IA_GEN4B_1_HSI2 522
+#define IRQ_PCIE_PCS_GEN4_1_HSI2 523
+#define IRQ_PCIE_PCS_GEN4B_1_HSI2 524
+#define IRQ_PPMU_HSI2_UPPER_OR_NORMAL_HSI2 525
+#define IRQ_SSMT_HSI2_HSI2 526
+#define IRQ_SYSMMU_HSI2_S2_HSI2 527
+#define IRQ_TZINT_PCIE_GEN4A_DBI_1_HSI2 528
+#define IRQ_TZINT_PCIE_GEN4A_SLV_1_HSI2 529
+#define IRQ_TZINT_PCIE_GEN4B_DBI_1_HSI2 530
+#define IRQ_TZINT_PCIE_GEN4B_SLV_1_HSI2 531
+#define IRQ_UFS_EMBD_HSI2 532
+#define IRQ_IPP_CH0_0_IPP 533
+#define IRQ_IPP_CH0_1_IPP 534
+#define IRQ_IPP_CH1_0_IPP 535
+#define IRQ_IPP_CH1_1_IPP 536
+#define IRQ_IPP_CH2_0_IPP 537
+#define IRQ_IPP_CH2_1_IPP 538
+#define IRQ_MUTE_GTNR_ALIGN_IPP 539
+#define IRQ_MUTE_IPP0_IPP 540
+#define IRQ_MUTE_IPP1_IPP 541
+#define IRQ_MUTE_IPP2_IPP 542
+#define IRQ_PPMU_IPP_UPPER_OR_NORMAL_IPP 543
+#define IRQ_PPMU_MSA_UPPER_OR_NORMAL_IPP 544
+#define IRQ_SYSMMU_IPP_S1_NS_IPP 545
+#define IRQ_SYSMMU_IPP_S1_S_IPP 546
+#define IRQ_SYSMMU_IPP_S2_IPP 547
+#define IRQ_TNR_A_IPP 548
+#define IRQ_C2COM_MCSC_MCSC 549
+#define IRQ_C2R_MCSC_MCSC 550
+#define IRQ_ITSC_NonSecu_Mute_MCSC 551
+#define IRQ_ITSC_OTF0_MCSC 552
+#define IRQ_MCSC_NonSecu_Mute_MCSC 553
+#define IRQ_MCSC_OTF0_MCSC 554
+#define IRQ_PPMU_D0_ITSC_UPPER_OR_NORMAL_MCSC 555
+#define IRQ_PPMU_D0_MCSC_UPPER_OR_NORMAL_MCSC 556
+#define IRQ_PPMU_D1_ITSC_UPPER_OR_NORMAL_MCSC 557
+#define IRQ_PPMU_D1_MCSC_UPPER_OR_NORMAL_MCSC 558
+#define IRQ_SYSMMU_D0_MCSC_S1_NS_MCSC 559
+#define IRQ_SYSMMU_D0_MCSC_S1_S_MCSC 560
+#define IRQ_SYSMMU_D0_MCSC_S2_MCSC 561
+#define IRQ_SYSMMU_D1_MCSC_S1_NS_MCSC 562
+#define IRQ_SYSMMU_D1_MCSC_S1_S_MCSC 563
+#define IRQ_SYSMMU_D1_MCSC_S2_MCSC 564
+#define IRQ_SYSMMU_D2_MCSC_S1_NS_MCSC 565
+#define IRQ_SYSMMU_D2_MCSC_S1_S_MCSC 566
+#define IRQ_SYSMMU_D2_MCSC_S2_MCSC 567
+#define IRQ_MFC_MFC 568
+#define IRQ_PPMU_D0_MFC_interrupt_upper_or_normal_MFC 569
+#define IRQ_PPMU_D1_MFC_interrupt_upper_or_normal_MFC 570
+#define IRQ_SYSMMU_D0_MFC_interrupt_s1_ns_MFC 571
+#define IRQ_SYSMMU_D0_MFC_interrupt_s1_s_MFC 572
+#define IRQ_SYSMMU_D0_MFC_interrupt_s2_MFC 573
+#define IRQ_SYSMMU_D1_MFC_interrupt_s1_ns_MFC 574
+#define IRQ_SYSMMU_D1_MFC_interrupt_s1_s_MFC 575
+#define IRQ_SYSMMU_D1_MFC_interrupt_s2_MFC 576
+#define IRQ_DMC_APBACCESSINT_MIF0 577
+#define IRQ_DMC_ECC_CORERR_MIF0 578
+#define IRQ_DMC_ECC_UNCORERR_MIF0 579
+#define IRQ_DMC_PPMPINT_MIF0 580
+#define IRQ_DMC_SWZQ0_MIF0 581
+#define IRQ_DMC_SWZQ1_MIF0 582
+#define IRQ_DMC_TEMPERR_MIF0 583
+#define IRQ_DMC_TEMPHOT_MIF0 584
+#define IRQ_DMC_TZCINT_MIF0 585
+#define IRQ_DMC_APBACCESSINT_MIF1 586
+#define IRQ_DMC_ECC_CORERR_MIF1 587
+#define IRQ_DMC_ECC_UNCORERR_MIF1 588
+#define IRQ_DMC_PPMPINT_MIF1 589
+#define IRQ_DMC_SWZQ0_MIF1 590
+#define IRQ_DMC_SWZQ1_MIF1 591
+#define IRQ_DMC_TEMPERR_MIF1 592
+#define IRQ_DMC_TEMPHOT_MIF1 593
+#define IRQ_DMC_TZCINT_MIF1 594
+#define IRQ_DMC_APBACCESSINT_MIF2 595
+#define IRQ_DMC_ECC_CORERR_MIF2 596
+#define IRQ_DMC_ECC_UNCORERR_MIF2 597
+#define IRQ_DMC_PPMPINT_MIF2 598
+#define IRQ_DMC_SWZQ0_MIF2 599
+#define IRQ_DMC_SWZQ1_MIF2 600
+#define IRQ_DMC_TEMPERR_MIF2 601
+#define IRQ_DMC_TEMPHOT_MIF2 602
+#define IRQ_DMC_TZCINT_MIF2 603
+#define IRQ_DMC_APBACCESSINT_MIF3 604
+#define IRQ_DMC_ECC_CORERR_MIF3 605
+#define IRQ_DMC_ECC_UNCORERR_MIF3 606
+#define IRQ_DMC_PPMPINT_MIF3 607
+#define IRQ_DMC_SWZQ0_MIF3 608
+#define IRQ_DMC_SWZQ1_MIF3 609
+#define IRQ_DMC_TEMPERR_MIF3 610
+#define IRQ_DMC_TEMPHOT_MIF3 611
+#define IRQ_DMC_TZCINT_MIF3 612
+#define IRQ_PDP_MUTE0_PDP 613
+#define IRQ_PDP_MUTE1_PDP 614
+#define IRQ_PDP_MUTE2_PDP 615
+#define IRQ_PDP_TOP0_PDP 616
+#define IRQ_PDP_TOP1_PDP 617
+#define IRQ_PDP_TOP2_PDP 618
+#define IRQ_PDP_TOP3_PDP 619
+#define IRQ_PDP_TOP4_PDP 620
+#define IRQ_PDP_TOP5_PDP 621
+#define IRQ_PPMU_VRA_UPPER_OR_NORMAL_PDP 622
+#define IRQ_SSMT_VRA_PDP 623
+#define IRQ_VRA_PDP 624
+#define IRQ_GPIO_PERIC0_PERIC0 625
+#define IRQ_I3C1_PERIC0 626
+#define IRQ_I3C2_PERIC0 627
+#define IRQ_I3C3_PERIC0 628
+#define IRQ_I3C4_PERIC0 629
+#define IRQ_I3C5_PERIC0 630
+#define IRQ_I3C6_PERIC0 631
+#define IRQ_I3C7_PERIC0 632
+#define IRQ_I3C8_PERIC0 633
+#define IRQ_USI0_UART_PERIC0 634
+#define IRQ_USI1_USI_PERIC0 635
+#define IRQ_USI2_USI_PERIC0 636
+#define IRQ_USI3_USI_PERIC0 637
+#define IRQ_USI4_USI_PERIC0 638
+#define IRQ_USI5_USI_PERIC0 639
+#define IRQ_USI6_USI_PERIC0 640
+#define IRQ_USI7_USI_PERIC0 641
+#define IRQ_USI8_USI_PERIC0 642
+#define IRQ_USI14_USI_PERIC0 643
+#define IRQ_GPIO_PERIC1_PERIC1 644
+#define IRQ_I3C0_PERIC1 645
+#define IRQ_PWM0_PERIC1 646
+#define IRQ_PWM1_PERIC1 647
+#define IRQ_PWM2_PERIC1 648
+#define IRQ_PWM3_PERIC1 649
+#define IRQ_PWM4_PERIC1 650
+#define IRQ_USI0_USI_PERIC1 651
+#define IRQ_USI9_USI_PERIC1 652
+#define IRQ_USI10_USI_PERIC1 653
+#define IRQ_USI11_USI_PERIC1 654
+#define IRQ_USI12_USI_PERIC1 655
+#define IRQ_USI13_USI_PERIC1 656
+#define IRQ_PPMU_D0_TNR_UPPER_OR_NORMAL_TNR 657
+#define IRQ_PPMU_D1_TNR_UPPER_OR_NORMAL_TNR 658
+#define IRQ_PPMU_D2_TNR_UPPER_OR_NORMAL_TNR 659
+#define IRQ_PPMU_D3_TNR_UPPER_OR_NORMAL_TNR 660
+#define IRQ_PPMU_D4_TNR_UPPER_OR_NORMAL_TNR 661
+#define IRQ_PPMU_D5_TNR_UPPER_OR_NORMAL_TNR 662
+#define IRQ_PPMU_D6_TNR_UPPER_OR_NORMAL_TNR 663
+#define IRQ_PPMU_D7_TNR_UPPER_OR_NORMAL_TNR 664
+#define IRQ_SYSMMU_D0_TNR_S1_NS_TNR 665
+#define IRQ_SYSMMU_D0_TNR_S1_S_TNR 666
+#define IRQ_SYSMMU_D0_TNR_S2_TNR 667
+#define IRQ_SYSMMU_D1_TNR_S1_NS_TNR 668
+#define IRQ_SYSMMU_D1_TNR_S1_S_TNR 669
+#define IRQ_SYSMMU_D1_TNR_S2_TNR 670
+#define IRQ_SYSMMU_D2_TNR_S1_NS_TNR 671
+#define IRQ_SYSMMU_D2_TNR_S1_S_TNR 672
+#define IRQ_SYSMMU_D2_TNR_S2_TNR 673
+#define IRQ_SYSMMU_D3_TNR_S1_NS_TNR 674
+#define IRQ_SYSMMU_D3_TNR_S1_S_TNR 675
+#define IRQ_SYSMMU_D3_TNR_S2_TNR 676
+#define IRQ_SYSMMU_D4_TNR_S1_NS_TNR 677
+#define IRQ_SYSMMU_D4_TNR_S1_S_TNR 678
+#define IRQ_SYSMMU_D4_TNR_S2_TNR 679
+#define IRQ_TNR_TNR 680
+#define IRQ_TNR_MUTE_TNR 681
+#define IRQ_DDD_IRQ_0_TPU 682
+#define IRQ_DDD_IRQ_1_TPU 683
+#define IRQ_DDD_IRQ_2_TPU 684
+#define IRQ_DDD_IRQ_3_TPU 685
+#define IRQ_HPM_IRQ_TPU 686
+#define IRQ_NS_TPU_TPU 687
+#define IRQ_PPMU_UPPER_OR_NORMAL_TPU 688
+#define IRQ_S_TPU_TPU 689
+#define IRQ_SSMT_TPU_TPU 690
+#define IRQ_SYSMMU_S1_NS_TPU_TPU 691
+#define IRQ_SYSMMU_S1_S_TPU_TPU 692
+#define IRQ_SYSMMU_S2_TPU_TPU 693
+#define IRQ_OTP_CON_TOP_MISC 752
+#define IRQ_MCT_G0_MISC 753
+#define IRQ_MCT_G1_MISC 754
+#define IRQ_MCT_G2_MISC 755
+#define IRQ_MCT_G3_MISC 756
+#define IRQ_MCT_L0_MISC 757
+#define IRQ_MCT_L1_MISC 758
+#define IRQ_MCT_L2_MISC 759
+#define IRQ_MCT_L3_MISC 760
+#define IRQ_MCT_L4_MISC 761
+#define IRQ_MCT_L5_MISC 762
+#define IRQ_MCT_L6_MISC 763
+#define IRQ_MCT_L7_MISC 764
+#define IRQ_WDT_CLUSTER0_MISC 765
+#define IRQ_WDT_CLUSTER1_MISC 766
+#define IRQ_OTP_CON_BISR_MISC 767
+#define IRQ_OTP_CON_BIRA_MISC 768
+#define IRQ_TMU_TMU_TOP_MISC 769
+#define IRQ_TMU_TMU_SUB_MISC 770
+#define IRQ_SPDMA_MISC 771
+#define IRQ_PDMA_MISC 772
+#define IRQ_PPMU_DMA_0_MISC 773
+#define IRQ_PPMU_DMA_1_MISC 774
+#define IRQ_PPMU_DMA_2_MISC 775
+#define IRQ_PPMU_DMA_3_MISC 776
+#define IRQ_PPMU_DMA_IRQ_ABORT_MISC 777
+#define IRQ_SSS_MISC 778
+#define IRQ_SSS_NS_MB_MISC 779
+#define IRQ_SSS_S_MB_MISC 780
+#define IRQ_SSS_KM_MISC 781
+#define IRQ_SSS_DMAINT_MISC 782
+#define IRQ_SSS_SWDT1_MISC 783
+#define IRQ_SSS_SWDT2_MISC 784
+#define IRQ_PUF_SEC_MISC 785
+#define IRQ_PUF_UNCOREECT_MISC 786
+#define IRQ_RTIC_MISC 787
+#define IRQ_DIT_RxDst0_MISC 788
+#define IRQ_DIT_RxDst1_MISC 789
+#define IRQ_DIT_RxDst2_MISC 790
+#define IRQ_DIT_Tx_MISC 791
+#define IRQ_DIT_Err_MISC 792
+#define IRQ_PPMU_MISC_UPPER_OR_NORMAL_MISC 793
+#define IRQ_SYSMMU_NS_SSS_MISC 794
+#define IRQ_SYSMMU_S_SSS_MISC 795
+#define IRQ_SYSMMU_S2_MISC_MISC 796
+#define IRQ_GIC_FAULT_MISC 797
+#define IRQ_GIC_ERR_MISC 798
+#define IRQ_GIC_PMU_MISC 799
+
+#endif/*_DT_BINDINGS_INTERRUPT_CONTROLLER_GS101_H*/
--
2.42.0.582.g8ccd20d70d-goog
^ permalink raw reply related [flat|nested] 150+ messages in thread
* [PATCH 01/21] dt-bindings: interrupt-controller: Add gs101 interrupt controller
@ 2023-10-05 15:55 ` Peter Griffin
0 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-05 15:55 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi
Cc: peter.griffin, tudor.ambarus, andre.draszik, semen.protsenko,
soc, devicetree, linux-arm-kernel, linux-samsung-soc, linux-clk,
linux-gpio, linux-watchdog
Add the gs101 SoC interrupt header that provides human readable
constants for all the IRQs in the SoC.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
.../dt-bindings/interrupt-controller/gs101.h | 758 ++++++++++++++++++
1 file changed, 758 insertions(+)
create mode 100644 include/dt-bindings/interrupt-controller/gs101.h
diff --git a/include/dt-bindings/interrupt-controller/gs101.h b/include/dt-bindings/interrupt-controller/gs101.h
new file mode 100644
index 000000000000..51c8eb54eca2
--- /dev/null
+++ b/include/dt-bindings/interrupt-controller/gs101.h
@@ -0,0 +1,758 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * This header provides constants for gs101 interrupt controller.
+ *
+ * Copyright 2019-2023 Google LLC
+ *
+ */
+
+#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_GS101_H
+#define _DT_BINDINGS_INTERRUPT_CONTROLLER_GS101_H
+
+#define ITNO IRQ_TYPE_NONE
+#define ITER IRQ_TYPE_EDGE_RISING
+#define ITEF IRQ_TYPE_EDGE_FALLING
+#define ITEB IRQ_TYPE_EDGE_BOTH
+#define ITLH IRQ_TYPE_LEVEL_HIGH
+#define ITLL IRQ_TYPE_LEVEL_LOW
+
+#define IRQ_ALIVE_EINT0 0
+#define IRQ_ALIVE_EINT1 1
+#define IRQ_ALIVE_EINT2 2
+#define IRQ_ALIVE_EINT3 3
+#define IRQ_ALIVE_EINT4 4
+#define IRQ_ALIVE_EINT5 5
+#define IRQ_ALIVE_EINT6 6
+#define IRQ_ALIVE_EINT7 7
+#define IRQ_ALIVE_EINT8 8
+#define IRQ_ALIVE_EINT9 9
+#define IRQ_ALIVE_EINT10 10
+#define IRQ_ALIVE_EINT11 11
+#define IRQ_ALIVE_EINT12 12
+#define IRQ_ALIVE_EINT13 13
+#define IRQ_ALIVE_EINT14 14
+#define IRQ_ALIVE_EINT15 15
+#define IRQ_ALIVE_EINT16 16
+#define IRQ_ALIVE_EINT17 17
+#define IRQ_ALIVE_EINT18 18
+#define IRQ_ALIVE_EINT19 19
+#define IRQ_ALIVE_EINT20 20
+#define IRQ_ALIVE_EINT21 21
+#define IRQ_ALIVE_EINT22 22
+#define IRQ_ALIVE_EINT23 23
+#define IRQ_ALIVE_EINT24 24
+#define IRQ_ALIVE_EINT25 25
+#define IRQ_ALIVE_EINT26 26
+#define IRQ_ALIVE_EINT27 27
+#define IRQ_ALIVE_EINT28 28
+#define IRQ_ALIVE_EINT29 29
+#define IRQ_ALIVE_EINT30 30
+#define IRQ_ALIVE_EINT31 31
+#define IRQ_ALIVE_EINT32 32
+#define IRQ_ALIVE_EINT33 33
+#define IRQ_ALIVE_EINT34 34
+#define IRQ_ALIVE_EINT35 35
+#define IRQ_ALIVE_EINT36 36
+#define IRQ_ALIVE_EINT37 37
+#define IRQ_ALIVE_EINT38 38
+#define IRQ_ALIVE_EINT39 39
+#define IRQ_ALIVE_EINT40 40
+#define IRQ_ALIVE_EINT41 41
+#define IRQ_ALIVE_EINT42 42
+#define IRQ_ALIVE_EINT43 43
+#define IRQ_ALIVE_EINT44 44
+#define IRQ_ALIVE_EINT45 45
+#define IRQ_ALIVE_EINT46 46
+#define IRQ_ALIVE_EINT47 47
+#define IRQ_ALIVE_EINT48 48
+#define IRQ_ALIVE_EINT49 49
+#define IRQ_ALIVE_EINT50 50
+#define IRQ_ALIVE_EINT51 51
+#define IRQ_ALIVE_EINT52 52
+#define IRQ_ALIVE_EINT53 53
+#define IRQ_ALIVE_EINT54 54
+#define IRQ_ALIVE_EINT55 55
+#define IRQ_ALIVE_EINT56 56
+#define IRQ_ALIVE_EINT57 57
+#define IRQ_ALIVE_EINT58 58
+#define IRQ_ALIVE_EINT59 59
+#define IRQ_ALIVE_EINT60 60
+#define IRQ_ALIVE_EINT61 61
+#define IRQ_ALIVE_EINT62 62
+#define IRQ_ALIVE_EINT63 63
+#define IRQ_ALIVE_EINT64 64
+#define IRQ_ALIVE_EINT65 65
+#define IRQ_ALIVE_EINT66 66
+#define IRQ_APM_USI0_UART_ALIVE 67
+#define IRQ_APM_USI0_USI_ALIVE 68
+#define IRQ_APM_USI1_UART_ALIVE 69
+#define IRQ_COMB_SFI_CE_NONSECURE_SYSREG_APM_ALIVE 70
+#define IRQ_COMB_SFI_UCE_NONSECURE_SYSREG_APM_ALIVE 71
+#define IRQ_MAILBOX_AOC2AP_ALIVE 72
+#define IRQ_MAILBOX_APM2AP_ALIVE 73
+#define IRQ_MAILBOX_DBGCORE2AP_ALIVE 74
+#define IRQ_OCP_WARN_CPUCL1_ALIVE 75
+#define IRQ_OCP_WARN_CPUCL2_ALIVE 76
+#define IRQ_OCP_WARN_GPU_ALIVE 77
+#define IRQ_OCP_WARN_TPU_ALIVE 78
+#define IRQ_RTC_ALARM_INT_ALIVE 79
+#define IRQ_RTC_TIC_INT_0_ALIVE 80
+#define IRQ_SMPL_WARN_ALIVE 81
+#define IRQ_SOFT_OCP_WARN_CPUCL1_ALIVE 82
+#define IRQ_SOFT_OCP_WARN_CPUCL2_ALIVE 83
+#define IRQ_SOFT_OCP_WARN_GPU_ALIVE 84
+#define IRQ_SOFT_OCP_WARN_TPU_ALIVE 85
+#define IRQ_SPEEDY_APM_ALIVE 86
+#define IRQ_SPEEDY_SUB_APM_ALIVE 87
+#define IRQ_TRTC_ALARM_INT_ALIVE 88
+#define IRQ_TRTC_TIC_INT_0_ALIVE 89
+#define IRQ_VDROOP1_ALIVE 90
+#define IRQ_VDROOP2_ALIVE 91
+#define IRQ_WDT_APM_ALIVE 92
+#define IRQ_WDT_DBGCORE_ALIVE 93
+#define NONSEQINT__UASC_APM_ALIVE 94
+#define NONSEQINT__UASC_DBGCORE_ALIVE 95
+#define NONSEQINT__UASC_G_SWD_ALIVE 96
+#define NONSEQINT__UASC_P_AOCAPM_ALIVE 97
+#define NONSEQINT__UASC_P_APM_ALIVE 98
+#define O_INTERRUPT_S2__SYSMMU_D_APM_ALIVE 99
+#define TZINT__UASC_APM_ALIVE 100
+#define TZINT__UASC_DBGCORE_ALIVE 101
+#define TZINT__UASC_G_SWD_ALIVE 102
+#define TZINT__UASC_P_AOCAPM_ALIVE 103
+#define TZINT__UASC_P_APM_ALIVE 104
+#define INTR_AOC_PPMU_AOC 105
+#define INTR_AOCUSB_PPMU_AOC 106
+#define IRQ_AOC_TIMER0_AOC 107
+#define IRQ_AOC_Watchdog_CPU_AOC 108
+#define INTREQ_AOCPLL_LOCK_STATUS_AOC 109
+#define IRQ_SYSMMU_AOC_S1_NS_AOC 110
+#define IRQ_SYSMMU_AOC_S1_S_AOC 111
+#define IRQ_SYSMMU_AOC_S2_AOC 112
+#define IRQ_UASC_NS_AOC_AOC 113
+#define IRQ_UASC_S_AOC_AOC 114
+#define IRQ_BO_XINT_BO 115
+#define IRQ_PPMU_UPPER_OR_NORMAL_BO 116
+#define IRQ_SSMT_BO_BO 117
+#define IRQ_SYSMMU_S1_NS_BO_BO 118
+#define IRQ_SYSMMU_S1_S_BO_BO 119
+#define IRQ_SYSMMU_S2_BO_BO 120
+#define IRQ_UASC_NS_BO_BO 121
+#define IRQ_UASC_S_BO_BO 122
+#define IRQ_PPC_CYCLE_AOC_L_BUS0 123
+#define IRQ_PPC_CYCLE_AOC_UON_BUS0 124
+#define IRQ_PPC_EVENT_AOC_L_BUS0 125
+#define IRQ_PPC_EVENT_AOC_UON_BUS0 126
+#define IRQ_TREX_D_BUS0_debugInterrupt_BUS0 127
+#define IRQ_TREX_P_BUS0_debugInterrupt_BUS0 128
+#define IRQ_TREX_PPMU_BUS0M0_BUS0 129
+#define IRQ_TREX_D0_BUS1_debugInterrupt_BUS1 130
+#define IRQ_TREX_P_BUS1_debugInterrupt_BUS1 131
+#define IRQ_TREX_PPMU_BUS1M0_BUS1 132
+#define IRQ_TREX_PPMU_BUS1M1_BUS1 133
+#define IRQ_TREX_PPMU_BUS1M2_BUS1 134
+#define IRQ_TREX_PPMU_BUS1M3_BUS1 135
+#define IRQ_PPC_CYCLE_BUS2_L_BUS2 136
+#define IRQ_PPC_CYCLE_BUS2_UON_BUS2 137
+#define IRQ_PPC_CYCLE_G3D_L_BUS2 138
+#define IRQ_PPC_CYCLE_G3D_UON_BUS2 139
+#define IRQ_PPC_CYCLE_TPU_L_BUS2 140
+#define IRQ_PPC_CYCLE_TPU_UON_BUS2 141
+#define IRQ_PPC_EVENT_BUS2_L_AND_BUS2 142
+#define IRQ_PPC_EVENT_BUS2_L_OR_BUS2 143
+#define IRQ_PPC_EVENT_BUS2_UON_AND_BUS2 144
+#define IRQ_PPC_EVENT_BUS2_UON_OR_BUS2 145
+#define IRQ_PPC_EVENT_G3D_L_AND_BUS2 146
+#define IRQ_PPC_EVENT_G3D_L_OR_BUS2 147
+#define IRQ_PPC_EVENT_G3D_UON_AND_BUS2 148
+#define IRQ_PPC_EVENT_G3D_UON_OR_BUS2 149
+#define IRQ_PPC_EVENT_TPU_L_BUS2 150
+#define IRQ_PPC_EVENT_TPU_UON_BUS2 151
+#define IRQ_PPCFW_G3D_BUS2 152
+#define IRQ_SYSMMU_G3D0_BUS2 153
+#define IRQ_SYSMMU_G3D1_BUS2 154
+#define IRQ_SYSMMU_G3D2_BUS2 155
+#define IRQ_SYSMMU_G3D3_BUS2 156
+#define IRQ_TREX_D_BUS2_debugInterrupt_BUS2 157
+#define IRQ_TREX_P_BUS2_debugInterrupt_BUS2 158
+#define IRQ_TREX_PPMU_BUS2M0_BUS2 159
+#define IRQ_TREX_PPMU_BUS2M1_BUS2 160
+#define IRQ_TREX_PPMU_BUS2M2_BUS2 161
+#define IRQ_TREX_PPMU_BUS2M3_BUS2 162
+#define IRQ_TREX_PPMU_GPU0_BUS2 163
+#define IRQ_TREX_PPMU_GPU1_BUS2 164
+#define IRQ_TREX_PPMU_GPU2_BUS2 165
+#define IRQ_TREX_PPMU_GPU3_BUS2 166
+#define IRQ_BDU_O_INT_CORE 167
+#define IRQ_CCI_nERRIRQ_CORE 168
+#define IRQ_CCI_nEVNTCNTOVERFLOW_0_CORE 169
+#define IRQ_CCI_nEVNTCNTOVERFLOW_1_CORE 170
+#define IRQ_CCI_nEVNTCNTOVERFLOW_2_CORE 171
+#define IRQ_CCI_nEVNTCNTOVERFLOW_3_CORE 172
+#define IRQ_CCI_nEVNTCNTOVERFLOW_4_CORE 173
+#define IRQ_CCI_nEVNTCNTOVERFLOW_5_CORE 174
+#define IRQ_CCI_nEVNTCNTOVERFLOW_6_CORE 175
+#define IRQ_CCI_nEVNTCNTOVERFLOW_7_CORE 176
+#define IRQ_CORE_PPC_CON_O_IL_AND_PPC_BUS2_EVENT_CORE 177
+#define IRQ_CORE_PPC_CON_O_IL_AND_PPC_CCI_EVENT_CORE 178
+#define IRQ_CORE_PPC_CON_O_IL_AND_PPC_CPUCL0_EVENT_CORE 179
+#define IRQ_CORE_PPC_CON_O_IL_OR_PPC_BUS2_EVENT_CORE 180
+#define IRQ_CORE_PPC_CON_O_IL_OR_PPC_CCI_EVENT_CORE 181
+#define IRQ_CORE_PPC_CON_O_IL_OR_PPC_CPUCL0_EVENT_CORE 182
+#define IRQ_CORE_PPC_CON_O_IUON_AND_PPC_BUS2_EVENT_CORE 183
+#define IRQ_CORE_PPC_CON_O_IUON_AND_PPC_CCI_EVENT_CORE 184
+#define IRQ_CORE_PPC_CON_O_IUON_AND_PPC_CPUCL0_EVENT_CORE 185
+#define IRQ_CORE_PPC_CON_O_IUON_OR_PPC_BUS2_EVENT_CORE 186
+#define IRQ_CORE_PPC_CON_O_IUON_OR_PPC_CCI_EVENT_CORE 187
+#define IRQ_CORE_PPC_CON_O_IUON_OR_PPC_CPUCL0_EVENT_CORE 188
+#define IRQ_LD_SLC_CH0_O_APC_NS_IRQ_CORE 189
+#define IRQ_LD_SLC_CH0_O_APC_S_IRQ_CORE 190
+#define IRQ_LD_SLC_CH0_O_PPMPU_IRQ_CORE 191
+#define IRQ_LD_SLC_CH0_O_UASC_GSA_IRQ_CORE 192
+#define IRQ_LD_SLC_CH0_O_UASC_NS_IRQ_CORE 193
+#define IRQ_LD_SLC_CH0_O_UASC_TZ_IRQ_CORE 194
+#define IRQ_LD_SLC_CH1_O_APC_NS_IRQ_CORE 195
+#define IRQ_LD_SLC_CH1_O_APC_S_IRQ_CORE 196
+#define IRQ_LD_SLC_CH1_O_PPMPU_IRQ_CORE 197
+#define IRQ_LD_SLC_CH1_O_UASC_GSA_IRQ_CORE 198
+#define IRQ_LD_SLC_CH1_O_UASC_NS_IRQ_CORE 199
+#define IRQ_LD_SLC_CH1_O_UASC_TZ_IRQ_CORE 200
+#define IRQ_LD_SLC_CH2_O_APC_NS_IRQ_CORE 201
+#define IRQ_LD_SLC_CH2_O_APC_S_IRQ_CORE 202
+#define IRQ_LD_SLC_CH2_O_PPMPU_IRQ_CORE 203
+#define IRQ_LD_SLC_CH2_O_UASC_GSA_IRQ_CORE 204
+#define IRQ_LD_SLC_CH2_O_UASC_NS_IRQ_CORE 205
+#define IRQ_LD_SLC_CH2_O_UASC_TZ_IRQ_CORE 206
+#define IRQ_LD_SLC_CH3_O_APC_NS_IRQ_CORE 207
+#define IRQ_LD_SLC_CH3_O_APC_S_IRQ_CORE 208
+#define IRQ_LD_SLC_CH3_O_PPMPU_IRQ_CORE 209
+#define IRQ_LD_SLC_CH3_O_UASC_GSA_IRQ_CORE 210
+#define IRQ_LD_SLC_CH3_O_UASC_NS_IRQ_CORE 211
+#define IRQ_LD_SLC_CH3_O_UASC_TZ_IRQ_CORE 212
+#define IRQ_PPC_BUS0_M0_CYCLE_O_IL_CORE 213
+#define IRQ_PPC_BUS0_M0_CYCLE_O_IUON_CORE 214
+#define IRQ_PPC_BUS0_M0_EVENT_O_IL_CORE 215
+#define IRQ_PPC_BUS0_M0_EVENT_O_IUON_CORE 216
+#define IRQ_PPC_BUS2_M0_CYCLE_O_IL_CORE 217
+#define IRQ_PPC_BUS2_M0_CYCLE_O_IUON_CORE 218
+#define IRQ_PPC_CCI_M1_CYCLE_O_IL_CORE 219
+#define IRQ_PPC_CCI_M1_CYCLE_O_IUON_CORE 220
+#define IRQ_PPC_CPUCL0_D0_CYCLE_O_IL_CORE 221
+#define INTREQ__SECURE_LOG 224
+#define IRQ_PPC_CPUCL0_D0_CYCLE_O_IUON_CORE 227
+#define IRQ_PPC_DEBUG_O_IL_CORE 228
+#define IRQ_PPC_DEBUG_O_IUON_CORE 229
+#define IRQ_PPC_EH_CYCLE_O_IL_CORE 230
+#define IRQ_PPC_EH_CYCLE_O_IUON_CORE 231
+#define IRQ_PPC_EH_EVENT_O_IL_CORE 232
+#define IRQ_PPC_EH_EVENT_O_IUON_CORE 233
+#define IRQ_PPC_IO_CYCLE_O_IL_CORE 234
+#define IRQ_PPC_IO_CYCLE_O_IUON_CORE 235
+#define IRQ_PPC_IO_EVENT_O_IL_CORE 236
+#define IRQ_PPC_IO_EVENT_O_IUON_CORE 237
+#define IRQ_PPMU_ACE_CPUCL0_O_IL_CORE 238
+#define IRQ_PPMU_ACE_CPUCL0_O_IUON_CORE 239
+#define IRQ_PPMU_ACE_CPUCL1_O_IL_CORE 240
+#define IRQ_PPMU_ACE_CPUCL1_O_IUON_CORE 241
+#define IRQ_TREX_D_CORE_debugInterrupt_CORE 242
+#define IRQ_TREX_D_CORE_ppcInterrupt_CORE_CCI_CORE 243
+#define IRQ_TREX_D_CORE_ppcInterrupt_CORE_DP_CORE 244
+#define IRQ_TREX_D_CORE_ppcInterrupt_CORE_M0_CORE 245
+#define IRQ_TREX_D_CORE_ppcInterrupt_CORE_M1_CORE 246
+#define IRQ_TREX_D_CORE_ppcInterrupt_CORE_M2_CORE 247
+#define IRQ_TREX_D_CORE_ppcInterrupt_CORE_M3_CORE 248
+#define IRQ_TREX_D_CORE_ppcInterrupt_CPU0_CORE 249
+#define IRQ_TREX_D_CORE_ppcInterrupt_CPU1_CORE 250
+#define IRQ_TREX_D_CORE_ppcInterrupt_CPU2_CORE 251
+#define IRQ_TREX_D_CORE_ppcInterrupt_CPU3_CORE 252
+#define IRQ_TREX_P_CORE_debugInterrupt_CORE 253
+#define IRQ_TREX_P_CORE_ppcInterrupt_CCI_CORE 254
+#define IRQ_TREX_P_CORE_ppcInterrupt_CORE_ALIVE_CORE 255
+#define IRQ_TREX_P_CORE_ppcInterrupt_CORE_DP_CORE 256
+#define IRQ_CPUCL0_CLUSTERPMUIRQ_CPUCL0 257
+#define IRQ_CPUCL0_DDD_APBIF0_FAST_PEND_CPUCL0 258
+#define IRQ_CPUCL0_DDD_APBIF0_HIGH_PEND_CPUCL0 259
+#define IRQ_CPUCL0_DDD_APBIF0_LOW_PEND_CPUCL0 260
+#define IRQ_CPUCL0_DDD_APBIF0_SLOW_PEND_CPUCL0 261
+#define IRQ_CPUCL0_DDD_APBIF1_FAST_PEND_CPUCL0 262
+#define IRQ_CPUCL0_DDD_APBIF1_HIGH_PEND_CPUCL0 263
+#define IRQ_CPUCL0_DDD_APBIF1_LOW_PEND_CPUCL0 264
+#define IRQ_CPUCL0_DDD_APBIF1_SLOW_PEND_CPUCL0 265
+#define IRQ_CPUCL0_DDD_APBIF2_FAST_PEND_CPUCL0 266
+#define IRQ_CPUCL0_DDD_APBIF2_HIGH_PEND_CPUCL0 267
+#define IRQ_CPUCL0_DDD_APBIF2_LOW_PEND_CPUCL0 268
+#define IRQ_CPUCL0_DDD_APBIF2_SLOW_PEND_CPUCL0 269
+#define IRQ_CPUCL0_DDD_APBIF3_FAST_PEND_CPUCL0 270
+#define IRQ_CPUCL0_DDD_APBIF3_HIGH_PEND_CPUCL0 271
+#define IRQ_CPUCL0_DDD_APBIF3_LOW_PEND_CPUCL0 272
+#define IRQ_CPUCL0_DDD_APBIF3_SLOW_PEND_CPUCL0 273
+#define IRQ_CPUCL0_ERRIRQ_0_CPUCL0 274
+#define IRQ_CPUCL0_ERRIRQ_1_CPUCL0 275
+#define IRQ_CPUCL0_ERRIRQ_2_CPUCL0 276
+#define IRQ_CPUCL0_ERRIRQ_3_CPUCL0 277
+#define IRQ_CPUCL0_ERRIRQ_4_CPUCL0 278
+#define IRQ_CPUCL0_ERRIRQ_5_CPUCL0 279
+#define IRQ_CPUCL0_ERRIRQ_6_CPUCL0 280
+#define IRQ_CPUCL0_ERRIRQ_7_CPUCL0 281
+#define IRQ_CPUCL0_ERRIRQ_8_CPUCL0 282
+#define IRQ_CPUCL0_FAULTIRQ_0_CPUCL0 283
+#define IRQ_CPUCL0_FAULTIRQ_1_CPUCL0 284
+#define IRQ_CPUCL0_FAULTIRQ_2_CPUCL0 285
+#define IRQ_CPUCL0_FAULTIRQ_3_CPUCL0 286
+#define IRQ_CPUCL0_FAULTIRQ_4_CPUCL0 287
+#define IRQ_CPUCL0_FAULTIRQ_5_CPUCL0 288
+#define IRQ_CPUCL0_FAULTIRQ_6_CPUCL0 289
+#define IRQ_CPUCL0_FAULTIRQ_7_CPUCL0 290
+#define IRQ_CPUCL0_FAULTIRQ_8_CPUCL0 291
+#define O_HPM_IRQ_CPUCL0_CPUCL0 292
+#define IRQ_CPUCL0_S2MPU_IRQ_CPUCL0 293
+#define IRQ_CSIS0_CSIS 294
+#define IRQ_CSIS1_CSIS 295
+#define IRQ_CSIS2_CSIS 296
+#define IRQ_CSIS3_CSIS 297
+#define IRQ_CSIS4_CSIS 298
+#define IRQ_CSIS5_CSIS 299
+#define IRQ_CSIS6_CSIS 300
+#define IRQ_CSIS7_CSIS 301
+#define IRQ_CSIS_DMA0_CSIS 302
+#define IRQ_CSIS_DMA1_CSIS 303
+#define IRQ_CSIS_DMA2_CSIS 304
+#define IRQ_CSIS_DMA3_CSIS 305
+#define IRQ_EBUF_OVERFLOW0_CSIS 306
+#define IRQ_EBUF_OVERFLOW1_CSIS 307
+#define IRQ_EBUF_OVERFLOW2_CSIS 308
+#define IRQ_EBUF_OVERFLOW3_CSIS 309
+#define IRQ_MUTE_CSIS0_CSIS 310
+#define IRQ_MUTE_CSIS1_CSIS 311
+#define IRQ_MUTE_CSIS2_CSIS 312
+#define IRQ_MUTE_CSIS3_CSIS 313
+#define IRQ_MUTE_STRP0_CSIS 314
+#define IRQ_MUTE_STRP1_CSIS 315
+#define IRQ_MUTE_STRP2_CSIS 316
+#define IRQ_MUTE_ZSL0_CSIS 317
+#define IRQ_MUTE_ZSL1_CSIS 318
+#define IRQ_MUTE_ZSL2_CSIS 319
+#define IRQ_PPMU_D0_CSIS_UPPER_OR_NORMAL_CSIS 320
+#define IRQ_PPMU_D1_CSIS_UPPER_OR_NORMAL_CSIS 321
+#define IRQ_STRP_DMA0_CSIS 322
+#define IRQ_STRP_DMA1_CSIS 323
+#define IRQ_STRP_DMA2_CSIS 324
+#define IRQ_SYSMMU_D0_CSIS_S1_NS_CSIS 325
+#define IRQ_SYSMMU_D0_CSIS_S1_S_CSIS 326
+#define IRQ_SYSMMU_D0_CSIS_S2_CSIS 327
+#define IRQ_SYSMMU_D1_CSIS_S1_NS_CSIS 328
+#define IRQ_SYSMMU_D1_CSIS_S1_S_CSIS 329
+#define IRQ_SYSMMU_D1_CSIS_S2_CSIS 330
+#define IRQ_ZSL_DMA0_CSIS 331
+#define IRQ_ZSL_DMA1_CSIS 332
+#define IRQ_ZSL_DMA2_CSIS 333
+#define IRQ_DISP_DECON0_DQE_DIMMING_END_DISP 334
+#define IRQ_DISP_DECON0_DQE_DIMMING_START_DISP 335
+#define IRQ_DISP_DECON0_EXTRA_DISP 336
+#define IRQ_DISP_DECON0_FRAME_DONE_DISP 337
+#define IRQ_DISP_DECON0_FRAME_START_DISP 338
+#define IRQ_DISP_DECON1_EXTRA_DISP 339
+#define IRQ_DISP_DECON1_FRAME_DONE_DISP 340
+#define IRQ_DISP_DECON1_FRAME_START_DISP 341
+#define IRQ_DISP_DECON2_EXTRA_DISP 342
+#define IRQ_DISP_DECON2_FRAME_DONE_DISP 343
+#define IRQ_DISP_DECON2_FRAME_START_DISP 344
+#define IRQ_DISP_DSIM0_DISP 345
+#define IRQ_DISP_DSIM1_DISP 346
+#define IRQ_DNS_0_DNS 347
+#define IRQ_DNS_1_DNS 348
+#define IRQ_DNS_MUTE_DNS 349
+#define IRQ_PPMU_DNS_UPPER_OR_NORMAL_DNS 350
+#define IRQ_SYSMMU_DNS_S1_NS_DNS 351
+#define IRQ_SYSMMU_DNS_S1_S_DNS 352
+#define IRQ_SYSMMU_DNS_S2_DNS 353
+#define IRQ_DPU_DMA_L0_DPU 354
+#define IRQ_DPU_DMA_L1_DPU 355
+#define IRQ_DPU_DMA_L2_DPU 356
+#define IRQ_DPU_DMA_L3_DPU 357
+#define IRQ_DPU_DMA_L4_DPU 358
+#define IRQ_DPU_DMA_L5_DPU 359
+#define IRQ_DPU_DMA_WB_DPU 360
+#define IRQ_DPU_DPP_L0_DPU 361
+#define IRQ_DPU_DPP_L1_DPU 362
+#define IRQ_DPU_DPP_L2_DPU 363
+#define IRQ_DPU_DPP_L3_DPU 364
+#define IRQ_DPU_DPP_L4_DPU 365
+#define IRQ_DPU_DPP_L5_DPU 366
+#define IRQ_PPMU_DPUD0_UPPER_OR_NORMAL_DPU 367
+#define IRQ_PPMU_DPUD1_UPPER_OR_NORMAL_DPU 368
+#define IRQ_PPMU_DPUD2_UPPER_OR_NORMAL_DPU 369
+#define IRQ_SYSMMU_DPUD0_S1_NS_DPU 370
+#define IRQ_SYSMMU_DPUD0_S1_S_DPU 371
+#define IRQ_SYSMMU_DPUD0_S2_DPU 372
+#define IRQ_SYSMMU_DPUD1_S1_NS_DPU 373
+#define IRQ_SYSMMU_DPUD1_S1_S_DPU 374
+#define IRQ_SYSMMU_DPUD1_S2_DPU 375
+#define IRQ_SYSMMU_DPUD2_S1_NS_DPU 376
+#define IRQ_SYSMMU_DPUD2_S1_S_DPU 377
+#define IRQ_SYSMMU_DPUD2_S2_DPU 378
+#define IRQ_EH_0_EH 379
+#define IRQ_EH_1_EH 380
+#define IRQ_EH_2_EH 381
+#define IRQ_EH_3_EH 382
+#define IRQ_EH_4_EH 383
+#define IRQ_EH_5_EH 384
+#define IRQ_EH_6_EH 385
+#define IRQ_EH_7_EH 386
+#define IRQ_EH_8_EH 387
+#define IRQ_EH_9_EH 388
+#define IRQ_PPMU_UPPER_OR_NORMAL_EH 389
+#define IRQ_SSMT_EH_EH 390
+#define IRQ_SYSMMU_S2_EH_EH 391
+#define IRQ_UASC_GSA_EH_EH 392
+#define IRQ_UASC_NS_EH_EH 393
+#define IRQ_UASC_S_EH_EH 394
+#define IRQ_G2D_G2D 395
+#define IRQ_JPEG_G2D 396
+#define IRQ_PPMU_D0_G2D_interrupt_upper_or_normal_G2D 397
+#define IRQ_PPMU_D1_G2D_interrupt_upper_or_normal_G2D 398
+#define IRQ_PPMU_D2_G2D_interrupt_upper_or_normal_G2D 399
+#define IRQ_SSMT_D0_G2D_intreq_G2D 400
+#define IRQ_SSMT_D1_G2D_intreq_G2D 401
+#define IRQ_SSMT_D2_G2D_intreq_G2D 402
+#define IRQ_SYSMMU_D0_G2D_interrupt_s1_ns_G2D 403
+#define IRQ_SYSMMU_D0_G2D_interrupt_s2_G2D 404
+#define IRQ_SYSMMU_D0_G2D_interrupt_s1_s_G2D 405
+#define IRQ_SYSMMU_D1_G2D_interrupt_s1_ns_G2D 406
+#define IRQ_SYSMMU_D1_G2D_interrupt_s2_G2D 407
+#define IRQ_SYSMMU_D1_G2D_interrupt_s1_s_G2D 408
+#define IRQ_SYSMMU_D2_G2D_interrupt_s1_ns_G2D 409
+#define IRQ_SYSMMU_D2_G2D_interrupt_s2_G2D 410
+#define IRQ_SYSMMU_D2_G2D_interrupt_s1_s_G2D 411
+#define IRQ_G3AA_G3AA 412
+#define IRQ_PPMU_G3AA_UPPER_OR_NORMAL_G3AA 413
+#define IRQ_SSMT_G3AA_G3AA 414
+#define IRQ_SYSMMU_G3AA_S1_NS_G3AA 415
+#define IRQ_SYSMMU_G3AA_S1_S_G3AA 416
+#define IRQ_SYSMMU_G3AA_S2_G3AA 417
+#define IRQ_G3D_IRQEVENT_G3D 418
+#define IRQ_G3D_IRQGPU_G3D 419
+#define IRQ_G3D_IRQJOB_G3D 420
+#define IRQ_G3D_IRQMMU_G3D 421
+#define IRQ_UASC_GSA_G3D_G3D 422
+#define IRQ_UASC_NS_G3D_G3D 423
+#define IRQ_UASC_S_G3D_G3D 424
+#define O_ADD_APBIF_G3D_FLAG_IRQ_PEND_G3D 425
+#define O_DDD_APBIF_G3D_DD_ERR_IRQ_FAST_PEND_G3D 426
+#define O_DDD_APBIF_G3D_DD_ERR_IRQ_SLOW_PEND_G3D 427
+#define O_HPM_IRQ_G3D 428
+#define IRQ_GDC0_IRQ_GDC 429
+#define IRQ_GDC0_Mute_IRQ_GDC 430
+#define IRQ_GDC1_IRQ_GDC 431
+#define IRQ_GDC1_Mute_IRQ_GDC 432
+#define IRQ_PPMU_D0_GDC_UPPER_OR_NORMAL_GDC 433
+#define IRQ_PPMU_D1_GDC_UPPER_OR_NORMAL_GDC 434
+#define IRQ_PPMU_D_SCSC_UPPER_OR_NORMAL_GDC 435
+#define IRQ_SCSC_IRQ_GDC 436
+#define IRQ_SCSC_NonSecu_Mute_IRQ_GDC 437
+#define IRQ_SYSMMU_D0_GDC_S1_NS_GDC 438
+#define IRQ_SYSMMU_D0_GDC_S1_S_GDC 439
+#define IRQ_SYSMMU_D0_GDC_S2_GDC 440
+#define IRQ_SYSMMU_D1_GDC_S1_NS_GDC 441
+#define IRQ_SYSMMU_D1_GDC_S1_S_GDC 442
+#define IRQ_SYSMMU_D1_GDC_S2_GDC 443
+#define IRQ_SYSMMU_D2_GDC_S1_NS_GDC 444
+#define IRQ_SYSMMU_D2_GDC_S1_S_GDC 445
+#define IRQ_SYSMMU_D2_GDC_S2_GDC 446
+#define IRQ_MAILBOX_GSA2NONTZ_GSA 447
+#define IRQ_MAILBOX_GSA2OSCAR_GSA 448
+#define IRQ_MAILBOX_GSA2PAINTBOX_GSA 449
+#define IRQ_MAILBOX_GSA2TZ_GSA 450
+#define SYSMMU_NS__INTERRUPT_GSA 451
+#define SYSMMU_S2MPU__INTERRUPT_GSA 452
+#define SYSMMU_S__INTERRUPT_GSA 453
+#define IRQ_DP_LINK_HSI0 454
+#define IRQ_PPMU_HSI0_AOC_UPPER_OR_NORMAL_HSI0 455
+#define IRQ_PPMU_HSI0_BUS0_UPPER_OR_NORMAL_HSI0 456
+#define IRQ_SYSMMU_USB_HSI0 457
+#define IRQ_USB2_REMOTE_CONNECT_GIC_HSI0 458
+#define IRQ_USB2_REMOTE_TIMER_GIC_HSI0 459
+#define IRQ_USB2_REMOTE_WAKEUP_GIC_HSI0 460
+#define IRQ_USB31DRD_FSVMINUS_GIC_HSI0 461
+#define IRQ_USB31DRD_FSVPLUS_GIC_HSI0 462
+#define IRQ_USB31DRD_GIC_0_HSI0 463
+#define IRQ_USB31DRD_GIC_1_HSI0 464
+#define IRQ_USB_UDBG_HSI0 465
+#define IRQ_USB_WAKEUP_HSI0 466
+#define NONSEQINT__UASC_HSI0_CTRL_HSI0 467
+#define NONSEQINT__UASC_HSI0_LINK_HSI0 468
+#define TZINT__UASC_HSI0_CTRL_HSI0 469
+#define TZINT__UASC_HSI0_LINK_HSI0 470
+#define IRQ_GPIO_HSI1_HSI1 471
+#define IRQ_PCIE_GEN4A_0_HSI1 472
+#define IRQ_PCIE_GEN4A_MSI_0_HSI1 473
+#define IRQ_PCIE_GEN4A_MSI_1_HSI1 474
+#define IRQ_PCIE_GEN4A_MSI_2_HSI1 475
+#define IRQ_PCIE_GEN4A_MSI_3_HSI1 476
+#define IRQ_PCIE_GEN4A_MSI_4_HSI1 477
+#define IRQ_PCIE_GEN4B_0_HSI1 478
+#define IRQ_PCIE_GEN4B_MSI_0_HSI1 479
+#define IRQ_PCIE_GEN4B_MSI_1_HSI1 480
+#define IRQ_PCIE_GEN4B_MSI_2_HSI1 481
+#define IRQ_PCIE_GEN4B_MSI_3_HSI1 482
+#define IRQ_PCIE_GEN4B_MSI_4_HSI1 483
+#define IRQ_PCIE_IA_GEN4A_0_HSI1 484
+#define IRQ_PCIE_IA_GEN4B_0_HSI1 485
+#define IRQ_PCIE_PCS_GEN4_0_HSI1 486
+#define IRQ_PCIE_PCS_GEN4B_0_HSI1 487
+#define IRQ_PPMU_HSI1_UPPER_OR_NORMAL_HSI1 488
+#define IRQ_SSMT_HSI1_HSI1 489
+#define IRQ_SYSMMU_HSI1_S2MPU_HSI1 490
+#define IRQ_UASC_GSA_PCIE_GEN4A_DBI_0_HSI1 491
+#define IRQ_UASC_GSA_PCIE_GEN4A_SLV_0_HSI1 492
+#define IRQ_UASC_GSA_PCIE_GEN4B_DBI_0_HSI1 493
+#define IRQ_UASC_GSA_PCIE_GEN4B_SLV_0_HSI1 494
+#define IRQ_UASC_NS_PCIE_GEN4A_DBI_0_HSI1 495
+#define IRQ_UASC_NS_PCIE_GEN4A_SLV_0_HSI1 496
+#define IRQ_UASC_NS_PCIE_GEN4B_DBI_0_HSI1 497
+#define IRQ_UASC_NS_PCIE_GEN4B_SLV_0_HSI1 498
+#define IRQ_UASC_S_PCIE_GEN4A_DBI_0_HSI1 499
+#define IRQ_UASC_S_PCIE_GEN4A_SLV_0_HSI1 500
+#define IRQ_UASC_S_PCIE_GEN4B_DBI_0_HSI1 501
+#define IRQ_UASC_S_PCIE_GEN4B_SLV_0_HSI1 502
+#define IRQ_GPIO_HSI2_HSI2 503
+#define IRQ_MMC_CARD_HSI2 504
+#define IRQ_NONSEQINT_PCIE_GEN4A_DBI_1_HSI2 505
+#define IRQ_NONSEQINT_PCIE_GEN4A_SLV_1_HSI2 506
+#define IRQ_NONSEQINT_PCIE_GEN4B_DBI_1_HSI2 507
+#define IRQ_NONSEQINT_PCIE_GEN4B_SLV_1_HSI2 508
+#define IRQ_PCIE_GEN4A_1_HSI2 509
+#define IRQ_PCIE_GEN4A_1_MSI_0_HSI2 510
+#define IRQ_PCIE_GEN4A_1_MSI_1_HSI2 511
+#define IRQ_PCIE_GEN4A_1_MSI_2_HSI2 512
+#define IRQ_PCIE_GEN4A_1_MSI_3_HSI2 513
+#define IRQ_PCIE_GEN4A_1_MSI_4_HSI2 514
+#define IRQ_PCIE_GEN4B_1_HSI2 515
+#define IRQ_PCIE_GEN4B_1_MSI_0_HSI2 516
+#define IRQ_PCIE_GEN4B_1_MSI_1_HSI2 517
+#define IRQ_PCIE_GEN4B_1_MSI_2_HSI2 518
+#define IRQ_PCIE_GEN4B_1_MSI_3_HSI2 519
+#define IRQ_PCIE_GEN4B_1_MSI_4_HSI2 520
+#define IRQ_PCIE_IA_GEN4A_1_HSI2 521
+#define IRQ_PCIE_IA_GEN4B_1_HSI2 522
+#define IRQ_PCIE_PCS_GEN4_1_HSI2 523
+#define IRQ_PCIE_PCS_GEN4B_1_HSI2 524
+#define IRQ_PPMU_HSI2_UPPER_OR_NORMAL_HSI2 525
+#define IRQ_SSMT_HSI2_HSI2 526
+#define IRQ_SYSMMU_HSI2_S2_HSI2 527
+#define IRQ_TZINT_PCIE_GEN4A_DBI_1_HSI2 528
+#define IRQ_TZINT_PCIE_GEN4A_SLV_1_HSI2 529
+#define IRQ_TZINT_PCIE_GEN4B_DBI_1_HSI2 530
+#define IRQ_TZINT_PCIE_GEN4B_SLV_1_HSI2 531
+#define IRQ_UFS_EMBD_HSI2 532
+#define IRQ_IPP_CH0_0_IPP 533
+#define IRQ_IPP_CH0_1_IPP 534
+#define IRQ_IPP_CH1_0_IPP 535
+#define IRQ_IPP_CH1_1_IPP 536
+#define IRQ_IPP_CH2_0_IPP 537
+#define IRQ_IPP_CH2_1_IPP 538
+#define IRQ_MUTE_GTNR_ALIGN_IPP 539
+#define IRQ_MUTE_IPP0_IPP 540
+#define IRQ_MUTE_IPP1_IPP 541
+#define IRQ_MUTE_IPP2_IPP 542
+#define IRQ_PPMU_IPP_UPPER_OR_NORMAL_IPP 543
+#define IRQ_PPMU_MSA_UPPER_OR_NORMAL_IPP 544
+#define IRQ_SYSMMU_IPP_S1_NS_IPP 545
+#define IRQ_SYSMMU_IPP_S1_S_IPP 546
+#define IRQ_SYSMMU_IPP_S2_IPP 547
+#define IRQ_TNR_A_IPP 548
+#define IRQ_C2COM_MCSC_MCSC 549
+#define IRQ_C2R_MCSC_MCSC 550
+#define IRQ_ITSC_NonSecu_Mute_MCSC 551
+#define IRQ_ITSC_OTF0_MCSC 552
+#define IRQ_MCSC_NonSecu_Mute_MCSC 553
+#define IRQ_MCSC_OTF0_MCSC 554
+#define IRQ_PPMU_D0_ITSC_UPPER_OR_NORMAL_MCSC 555
+#define IRQ_PPMU_D0_MCSC_UPPER_OR_NORMAL_MCSC 556
+#define IRQ_PPMU_D1_ITSC_UPPER_OR_NORMAL_MCSC 557
+#define IRQ_PPMU_D1_MCSC_UPPER_OR_NORMAL_MCSC 558
+#define IRQ_SYSMMU_D0_MCSC_S1_NS_MCSC 559
+#define IRQ_SYSMMU_D0_MCSC_S1_S_MCSC 560
+#define IRQ_SYSMMU_D0_MCSC_S2_MCSC 561
+#define IRQ_SYSMMU_D1_MCSC_S1_NS_MCSC 562
+#define IRQ_SYSMMU_D1_MCSC_S1_S_MCSC 563
+#define IRQ_SYSMMU_D1_MCSC_S2_MCSC 564
+#define IRQ_SYSMMU_D2_MCSC_S1_NS_MCSC 565
+#define IRQ_SYSMMU_D2_MCSC_S1_S_MCSC 566
+#define IRQ_SYSMMU_D2_MCSC_S2_MCSC 567
+#define IRQ_MFC_MFC 568
+#define IRQ_PPMU_D0_MFC_interrupt_upper_or_normal_MFC 569
+#define IRQ_PPMU_D1_MFC_interrupt_upper_or_normal_MFC 570
+#define IRQ_SYSMMU_D0_MFC_interrupt_s1_ns_MFC 571
+#define IRQ_SYSMMU_D0_MFC_interrupt_s1_s_MFC 572
+#define IRQ_SYSMMU_D0_MFC_interrupt_s2_MFC 573
+#define IRQ_SYSMMU_D1_MFC_interrupt_s1_ns_MFC 574
+#define IRQ_SYSMMU_D1_MFC_interrupt_s1_s_MFC 575
+#define IRQ_SYSMMU_D1_MFC_interrupt_s2_MFC 576
+#define IRQ_DMC_APBACCESSINT_MIF0 577
+#define IRQ_DMC_ECC_CORERR_MIF0 578
+#define IRQ_DMC_ECC_UNCORERR_MIF0 579
+#define IRQ_DMC_PPMPINT_MIF0 580
+#define IRQ_DMC_SWZQ0_MIF0 581
+#define IRQ_DMC_SWZQ1_MIF0 582
+#define IRQ_DMC_TEMPERR_MIF0 583
+#define IRQ_DMC_TEMPHOT_MIF0 584
+#define IRQ_DMC_TZCINT_MIF0 585
+#define IRQ_DMC_APBACCESSINT_MIF1 586
+#define IRQ_DMC_ECC_CORERR_MIF1 587
+#define IRQ_DMC_ECC_UNCORERR_MIF1 588
+#define IRQ_DMC_PPMPINT_MIF1 589
+#define IRQ_DMC_SWZQ0_MIF1 590
+#define IRQ_DMC_SWZQ1_MIF1 591
+#define IRQ_DMC_TEMPERR_MIF1 592
+#define IRQ_DMC_TEMPHOT_MIF1 593
+#define IRQ_DMC_TZCINT_MIF1 594
+#define IRQ_DMC_APBACCESSINT_MIF2 595
+#define IRQ_DMC_ECC_CORERR_MIF2 596
+#define IRQ_DMC_ECC_UNCORERR_MIF2 597
+#define IRQ_DMC_PPMPINT_MIF2 598
+#define IRQ_DMC_SWZQ0_MIF2 599
+#define IRQ_DMC_SWZQ1_MIF2 600
+#define IRQ_DMC_TEMPERR_MIF2 601
+#define IRQ_DMC_TEMPHOT_MIF2 602
+#define IRQ_DMC_TZCINT_MIF2 603
+#define IRQ_DMC_APBACCESSINT_MIF3 604
+#define IRQ_DMC_ECC_CORERR_MIF3 605
+#define IRQ_DMC_ECC_UNCORERR_MIF3 606
+#define IRQ_DMC_PPMPINT_MIF3 607
+#define IRQ_DMC_SWZQ0_MIF3 608
+#define IRQ_DMC_SWZQ1_MIF3 609
+#define IRQ_DMC_TEMPERR_MIF3 610
+#define IRQ_DMC_TEMPHOT_MIF3 611
+#define IRQ_DMC_TZCINT_MIF3 612
+#define IRQ_PDP_MUTE0_PDP 613
+#define IRQ_PDP_MUTE1_PDP 614
+#define IRQ_PDP_MUTE2_PDP 615
+#define IRQ_PDP_TOP0_PDP 616
+#define IRQ_PDP_TOP1_PDP 617
+#define IRQ_PDP_TOP2_PDP 618
+#define IRQ_PDP_TOP3_PDP 619
+#define IRQ_PDP_TOP4_PDP 620
+#define IRQ_PDP_TOP5_PDP 621
+#define IRQ_PPMU_VRA_UPPER_OR_NORMAL_PDP 622
+#define IRQ_SSMT_VRA_PDP 623
+#define IRQ_VRA_PDP 624
+#define IRQ_GPIO_PERIC0_PERIC0 625
+#define IRQ_I3C1_PERIC0 626
+#define IRQ_I3C2_PERIC0 627
+#define IRQ_I3C3_PERIC0 628
+#define IRQ_I3C4_PERIC0 629
+#define IRQ_I3C5_PERIC0 630
+#define IRQ_I3C6_PERIC0 631
+#define IRQ_I3C7_PERIC0 632
+#define IRQ_I3C8_PERIC0 633
+#define IRQ_USI0_UART_PERIC0 634
+#define IRQ_USI1_USI_PERIC0 635
+#define IRQ_USI2_USI_PERIC0 636
+#define IRQ_USI3_USI_PERIC0 637
+#define IRQ_USI4_USI_PERIC0 638
+#define IRQ_USI5_USI_PERIC0 639
+#define IRQ_USI6_USI_PERIC0 640
+#define IRQ_USI7_USI_PERIC0 641
+#define IRQ_USI8_USI_PERIC0 642
+#define IRQ_USI14_USI_PERIC0 643
+#define IRQ_GPIO_PERIC1_PERIC1 644
+#define IRQ_I3C0_PERIC1 645
+#define IRQ_PWM0_PERIC1 646
+#define IRQ_PWM1_PERIC1 647
+#define IRQ_PWM2_PERIC1 648
+#define IRQ_PWM3_PERIC1 649
+#define IRQ_PWM4_PERIC1 650
+#define IRQ_USI0_USI_PERIC1 651
+#define IRQ_USI9_USI_PERIC1 652
+#define IRQ_USI10_USI_PERIC1 653
+#define IRQ_USI11_USI_PERIC1 654
+#define IRQ_USI12_USI_PERIC1 655
+#define IRQ_USI13_USI_PERIC1 656
+#define IRQ_PPMU_D0_TNR_UPPER_OR_NORMAL_TNR 657
+#define IRQ_PPMU_D1_TNR_UPPER_OR_NORMAL_TNR 658
+#define IRQ_PPMU_D2_TNR_UPPER_OR_NORMAL_TNR 659
+#define IRQ_PPMU_D3_TNR_UPPER_OR_NORMAL_TNR 660
+#define IRQ_PPMU_D4_TNR_UPPER_OR_NORMAL_TNR 661
+#define IRQ_PPMU_D5_TNR_UPPER_OR_NORMAL_TNR 662
+#define IRQ_PPMU_D6_TNR_UPPER_OR_NORMAL_TNR 663
+#define IRQ_PPMU_D7_TNR_UPPER_OR_NORMAL_TNR 664
+#define IRQ_SYSMMU_D0_TNR_S1_NS_TNR 665
+#define IRQ_SYSMMU_D0_TNR_S1_S_TNR 666
+#define IRQ_SYSMMU_D0_TNR_S2_TNR 667
+#define IRQ_SYSMMU_D1_TNR_S1_NS_TNR 668
+#define IRQ_SYSMMU_D1_TNR_S1_S_TNR 669
+#define IRQ_SYSMMU_D1_TNR_S2_TNR 670
+#define IRQ_SYSMMU_D2_TNR_S1_NS_TNR 671
+#define IRQ_SYSMMU_D2_TNR_S1_S_TNR 672
+#define IRQ_SYSMMU_D2_TNR_S2_TNR 673
+#define IRQ_SYSMMU_D3_TNR_S1_NS_TNR 674
+#define IRQ_SYSMMU_D3_TNR_S1_S_TNR 675
+#define IRQ_SYSMMU_D3_TNR_S2_TNR 676
+#define IRQ_SYSMMU_D4_TNR_S1_NS_TNR 677
+#define IRQ_SYSMMU_D4_TNR_S1_S_TNR 678
+#define IRQ_SYSMMU_D4_TNR_S2_TNR 679
+#define IRQ_TNR_TNR 680
+#define IRQ_TNR_MUTE_TNR 681
+#define IRQ_DDD_IRQ_0_TPU 682
+#define IRQ_DDD_IRQ_1_TPU 683
+#define IRQ_DDD_IRQ_2_TPU 684
+#define IRQ_DDD_IRQ_3_TPU 685
+#define IRQ_HPM_IRQ_TPU 686
+#define IRQ_NS_TPU_TPU 687
+#define IRQ_PPMU_UPPER_OR_NORMAL_TPU 688
+#define IRQ_S_TPU_TPU 689
+#define IRQ_SSMT_TPU_TPU 690
+#define IRQ_SYSMMU_S1_NS_TPU_TPU 691
+#define IRQ_SYSMMU_S1_S_TPU_TPU 692
+#define IRQ_SYSMMU_S2_TPU_TPU 693
+#define IRQ_OTP_CON_TOP_MISC 752
+#define IRQ_MCT_G0_MISC 753
+#define IRQ_MCT_G1_MISC 754
+#define IRQ_MCT_G2_MISC 755
+#define IRQ_MCT_G3_MISC 756
+#define IRQ_MCT_L0_MISC 757
+#define IRQ_MCT_L1_MISC 758
+#define IRQ_MCT_L2_MISC 759
+#define IRQ_MCT_L3_MISC 760
+#define IRQ_MCT_L4_MISC 761
+#define IRQ_MCT_L5_MISC 762
+#define IRQ_MCT_L6_MISC 763
+#define IRQ_MCT_L7_MISC 764
+#define IRQ_WDT_CLUSTER0_MISC 765
+#define IRQ_WDT_CLUSTER1_MISC 766
+#define IRQ_OTP_CON_BISR_MISC 767
+#define IRQ_OTP_CON_BIRA_MISC 768
+#define IRQ_TMU_TMU_TOP_MISC 769
+#define IRQ_TMU_TMU_SUB_MISC 770
+#define IRQ_SPDMA_MISC 771
+#define IRQ_PDMA_MISC 772
+#define IRQ_PPMU_DMA_0_MISC 773
+#define IRQ_PPMU_DMA_1_MISC 774
+#define IRQ_PPMU_DMA_2_MISC 775
+#define IRQ_PPMU_DMA_3_MISC 776
+#define IRQ_PPMU_DMA_IRQ_ABORT_MISC 777
+#define IRQ_SSS_MISC 778
+#define IRQ_SSS_NS_MB_MISC 779
+#define IRQ_SSS_S_MB_MISC 780
+#define IRQ_SSS_KM_MISC 781
+#define IRQ_SSS_DMAINT_MISC 782
+#define IRQ_SSS_SWDT1_MISC 783
+#define IRQ_SSS_SWDT2_MISC 784
+#define IRQ_PUF_SEC_MISC 785
+#define IRQ_PUF_UNCOREECT_MISC 786
+#define IRQ_RTIC_MISC 787
+#define IRQ_DIT_RxDst0_MISC 788
+#define IRQ_DIT_RxDst1_MISC 789
+#define IRQ_DIT_RxDst2_MISC 790
+#define IRQ_DIT_Tx_MISC 791
+#define IRQ_DIT_Err_MISC 792
+#define IRQ_PPMU_MISC_UPPER_OR_NORMAL_MISC 793
+#define IRQ_SYSMMU_NS_SSS_MISC 794
+#define IRQ_SYSMMU_S_SSS_MISC 795
+#define IRQ_SYSMMU_S2_MISC_MISC 796
+#define IRQ_GIC_FAULT_MISC 797
+#define IRQ_GIC_ERR_MISC 798
+#define IRQ_GIC_PMU_MISC 799
+
+#endif/*_DT_BINDINGS_INTERRUPT_CONTROLLER_GS101_H*/
--
2.42.0.582.g8ccd20d70d-goog
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 150+ messages in thread
* Re: [PATCH 01/21] dt-bindings: interrupt-controller: Add gs101 interrupt controller
2023-10-05 15:55 ` Peter Griffin
@ 2023-10-05 16:04 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 150+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-05 16:04 UTC (permalink / raw)
To: Peter Griffin, robh+dt, krzysztof.kozlowski+dt, mturquette,
conor+dt, sboyd, tomasz.figa, s.nawrocki, linus.walleij, wim,
linux, catalin.marinas, will, arnd, olof, cw00.choi
Cc: tudor.ambarus, andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog
On 05/10/2023 17:55, Peter Griffin wrote:
> Add the gs101 SoC interrupt header that provides human readable
> constants for all the IRQs in the SoC.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> .../dt-bindings/interrupt-controller/gs101.h | 758 ++++++++++++++++++
> 1 file changed, 758 insertions(+)
> create mode 100644 include/dt-bindings/interrupt-controller/gs101.h
>
> diff --git a/include/dt-bindings/interrupt-controller/gs101.h b/include/dt-bindings/interrupt-controller/gs101.h
> new file mode 100644
> index 000000000000..51c8eb54eca2
> --- /dev/null
> +++ b/include/dt-bindings/interrupt-controller/gs101.h
> @@ -0,0 +1,758 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * This header provides constants for gs101 interrupt controller.
> + *
> + * Copyright 2019-2023 Google LLC
> + *
> + */
> +
> +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_GS101_H
> +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_GS101_H
> +
> +#define ITNO IRQ_TYPE_NONE
> +#define ITER IRQ_TYPE_EDGE_RISING
> +#define ITEF IRQ_TYPE_EDGE_FALLING
> +#define ITEB IRQ_TYPE_EDGE_BOTH
> +#define ITLH IRQ_TYPE_LEVEL_HIGH
> +#define ITLL IRQ_TYPE_LEVEL_LOW
No, these are not bindings.
> +
> +#define IRQ_ALIVE_EINT0 0
> +#define IRQ_ALIVE_EINT1 1
We do not keep interrupt numbers as bindings. Please drop entire file.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 01/21] dt-bindings: interrupt-controller: Add gs101 interrupt controller
@ 2023-10-05 16:04 ` Krzysztof Kozlowski
0 siblings, 0 replies; 150+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-05 16:04 UTC (permalink / raw)
To: Peter Griffin, robh+dt, krzysztof.kozlowski+dt, mturquette,
conor+dt, sboyd, tomasz.figa, s.nawrocki, linus.walleij, wim,
linux, catalin.marinas, will, arnd, olof, cw00.choi
Cc: tudor.ambarus, andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog
On 05/10/2023 17:55, Peter Griffin wrote:
> Add the gs101 SoC interrupt header that provides human readable
> constants for all the IRQs in the SoC.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> .../dt-bindings/interrupt-controller/gs101.h | 758 ++++++++++++++++++
> 1 file changed, 758 insertions(+)
> create mode 100644 include/dt-bindings/interrupt-controller/gs101.h
>
> diff --git a/include/dt-bindings/interrupt-controller/gs101.h b/include/dt-bindings/interrupt-controller/gs101.h
> new file mode 100644
> index 000000000000..51c8eb54eca2
> --- /dev/null
> +++ b/include/dt-bindings/interrupt-controller/gs101.h
> @@ -0,0 +1,758 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * This header provides constants for gs101 interrupt controller.
> + *
> + * Copyright 2019-2023 Google LLC
> + *
> + */
> +
> +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_GS101_H
> +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_GS101_H
> +
> +#define ITNO IRQ_TYPE_NONE
> +#define ITER IRQ_TYPE_EDGE_RISING
> +#define ITEF IRQ_TYPE_EDGE_FALLING
> +#define ITEB IRQ_TYPE_EDGE_BOTH
> +#define ITLH IRQ_TYPE_LEVEL_HIGH
> +#define ITLL IRQ_TYPE_LEVEL_LOW
No, these are not bindings.
> +
> +#define IRQ_ALIVE_EINT0 0
> +#define IRQ_ALIVE_EINT1 1
We do not keep interrupt numbers as bindings. Please drop entire file.
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 01/21] dt-bindings: interrupt-controller: Add gs101 interrupt controller
2023-10-05 16:04 ` Krzysztof Kozlowski
@ 2023-10-06 21:52 ` Linus Walleij
-1 siblings, 0 replies; 150+ messages in thread
From: Linus Walleij @ 2023-10-06 21:52 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Peter Griffin, robh+dt, krzysztof.kozlowski+dt, mturquette,
conor+dt, sboyd, tomasz.figa, s.nawrocki, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi, tudor.ambarus,
andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog
On Thu, Oct 5, 2023 at 6:04 PM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
> On 05/10/2023 17:55, Peter Griffin wrote:
> > Add the gs101 SoC interrupt header that provides human readable
> > constants for all the IRQs in the SoC.
> >
> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> > +#define ITNO IRQ_TYPE_NONE
> > +#define ITER IRQ_TYPE_EDGE_RISING
> > +#define ITEF IRQ_TYPE_EDGE_FALLING
> > +#define ITEB IRQ_TYPE_EDGE_BOTH
> > +#define ITLH IRQ_TYPE_LEVEL_HIGH
> > +#define ITLL IRQ_TYPE_LEVEL_LOW
>
> No, these are not bindings.
>
> > +
> > +#define IRQ_ALIVE_EINT0 0
> > +#define IRQ_ALIVE_EINT1 1
>
> We do not keep interrupt numbers as bindings. Please drop entire file.
Agree, but it should be fine to have as a SoC-specific .dtsi under
arch/.../google/gs101-irq.dtsi though!
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 01/21] dt-bindings: interrupt-controller: Add gs101 interrupt controller
@ 2023-10-06 21:52 ` Linus Walleij
0 siblings, 0 replies; 150+ messages in thread
From: Linus Walleij @ 2023-10-06 21:52 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Peter Griffin, robh+dt, krzysztof.kozlowski+dt, mturquette,
conor+dt, sboyd, tomasz.figa, s.nawrocki, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi, tudor.ambarus,
andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog
On Thu, Oct 5, 2023 at 6:04 PM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
> On 05/10/2023 17:55, Peter Griffin wrote:
> > Add the gs101 SoC interrupt header that provides human readable
> > constants for all the IRQs in the SoC.
> >
> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> > +#define ITNO IRQ_TYPE_NONE
> > +#define ITER IRQ_TYPE_EDGE_RISING
> > +#define ITEF IRQ_TYPE_EDGE_FALLING
> > +#define ITEB IRQ_TYPE_EDGE_BOTH
> > +#define ITLH IRQ_TYPE_LEVEL_HIGH
> > +#define ITLL IRQ_TYPE_LEVEL_LOW
>
> No, these are not bindings.
>
> > +
> > +#define IRQ_ALIVE_EINT0 0
> > +#define IRQ_ALIVE_EINT1 1
>
> We do not keep interrupt numbers as bindings. Please drop entire file.
Agree, but it should be fine to have as a SoC-specific .dtsi under
arch/.../google/gs101-irq.dtsi though!
Yours,
Linus Walleij
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 150+ messages in thread
* [PATCH 02/21] dt-bindings: soc: samsung: exynos-pmu: Add gs101 compatible
2023-10-05 15:55 ` Peter Griffin
@ 2023-10-05 15:55 ` Peter Griffin
-1 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-05 15:55 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi
Cc: peter.griffin, tudor.ambarus, andre.draszik, semen.protsenko,
soc, devicetree, linux-arm-kernel, linux-samsung-soc, linux-clk,
linux-gpio, linux-watchdog
Add gs101-pmu compatible to the bindings documentation.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml
index e1d716df5dfa..e6abf7b55909 100644
--- a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml
+++ b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml
@@ -27,6 +27,7 @@ select:
- samsung,exynos7-pmu
- samsung,exynos850-pmu
- samsung-s5pv210-pmu
+ - google,gs101-pmu
required:
- compatible
@@ -47,6 +48,7 @@ properties:
- samsung,exynos7-pmu
- samsung,exynos850-pmu
- samsung-s5pv210-pmu
+ - google,gs101-pmu
- const: syscon
- items:
- enum:
--
2.42.0.582.g8ccd20d70d-goog
^ permalink raw reply related [flat|nested] 150+ messages in thread* [PATCH 02/21] dt-bindings: soc: samsung: exynos-pmu: Add gs101 compatible
@ 2023-10-05 15:55 ` Peter Griffin
0 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-05 15:55 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi
Cc: peter.griffin, tudor.ambarus, andre.draszik, semen.protsenko,
soc, devicetree, linux-arm-kernel, linux-samsung-soc, linux-clk,
linux-gpio, linux-watchdog
Add gs101-pmu compatible to the bindings documentation.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml
index e1d716df5dfa..e6abf7b55909 100644
--- a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml
+++ b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml
@@ -27,6 +27,7 @@ select:
- samsung,exynos7-pmu
- samsung,exynos850-pmu
- samsung-s5pv210-pmu
+ - google,gs101-pmu
required:
- compatible
@@ -47,6 +48,7 @@ properties:
- samsung,exynos7-pmu
- samsung,exynos850-pmu
- samsung-s5pv210-pmu
+ - google,gs101-pmu
- const: syscon
- items:
- enum:
--
2.42.0.582.g8ccd20d70d-goog
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 150+ messages in thread* Re: [PATCH 02/21] dt-bindings: soc: samsung: exynos-pmu: Add gs101 compatible
2023-10-05 15:55 ` Peter Griffin
@ 2023-10-05 16:05 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 150+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-05 16:05 UTC (permalink / raw)
To: Peter Griffin, robh+dt, krzysztof.kozlowski+dt, mturquette,
conor+dt, sboyd, tomasz.figa, s.nawrocki, linus.walleij, wim,
linux, catalin.marinas, will, arnd, olof, cw00.choi
Cc: tudor.ambarus, andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog
On 05/10/2023 17:55, Peter Griffin wrote:
> Add gs101-pmu compatible to the bindings documentation.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml
> index e1d716df5dfa..e6abf7b55909 100644
> --- a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml
> +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml
> @@ -27,6 +27,7 @@ select:
> - samsung,exynos7-pmu
> - samsung,exynos850-pmu
> - samsung-s5pv210-pmu
> + - google,gs101-pmu
Keep alphabetical order.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 02/21] dt-bindings: soc: samsung: exynos-pmu: Add gs101 compatible
@ 2023-10-05 16:05 ` Krzysztof Kozlowski
0 siblings, 0 replies; 150+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-05 16:05 UTC (permalink / raw)
To: Peter Griffin, robh+dt, krzysztof.kozlowski+dt, mturquette,
conor+dt, sboyd, tomasz.figa, s.nawrocki, linus.walleij, wim,
linux, catalin.marinas, will, arnd, olof, cw00.choi
Cc: tudor.ambarus, andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog
On 05/10/2023 17:55, Peter Griffin wrote:
> Add gs101-pmu compatible to the bindings documentation.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml
> index e1d716df5dfa..e6abf7b55909 100644
> --- a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml
> +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml
> @@ -27,6 +27,7 @@ select:
> - samsung,exynos7-pmu
> - samsung,exynos850-pmu
> - samsung-s5pv210-pmu
> + - google,gs101-pmu
Keep alphabetical order.
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 150+ messages in thread
* [PATCH 03/21] dt-bindings: clock: Add Google gs101 clock management unit bindings
2023-10-05 15:55 ` Peter Griffin
@ 2023-10-05 15:56 ` Peter Griffin
-1 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-05 15:56 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi
Cc: peter.griffin, tudor.ambarus, andre.draszik, semen.protsenko,
soc, devicetree, linux-arm-kernel, linux-samsung-soc, linux-clk,
linux-gpio, linux-watchdog
Provide dt-schema documentation for Google gs101 SoC clock controller.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
.../bindings/clock/google,gs101-clock.yaml | 109 ++++++++++++++++++
1 file changed, 109 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
new file mode 100644
index 000000000000..a28d05d88afe
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
@@ -0,0 +1,109 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/google,gs101-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Google GS101 SoC clock controller
+
+maintainers:
+ - Peter Griffin <peter.griffin@linaro.org>
+
+description: |
+ Google GS101 clock controller is comprised of several CMU units, generating
+ clocks for different domains. Those CMU units are modeled as separate device
+ tree nodes, and might depend on each other. The root clock in that clock tree
+ is OSCCLK (24.576 MHz). That external clock must be defined as a fixed-rate
+ clock in dts.
+
+ CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
+ dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
+
+ Each clock is assigned an identifier and client nodes can use this identifier
+ to specify the clock which they consume. All clocks available for usage
+ in clock consumer nodes are defined as preprocessor macros in
+ 'dt-bindings/clock/gs101.h' header.
+
+properties:
+ compatible:
+ enum:
+ - google,gs101-cmu-top
+ - google,gs101-cmu-apm
+ - google,gs101-cmu-misc
+
+ clocks:
+ minItems: 1
+ maxItems: 5
+
+ clock-names:
+ minItems: 1
+ maxItems: 5
+
+ "#clock-cells":
+ const: 1
+
+ reg:
+ maxItems: 1
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: google,gs101-cmu-top
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (24.576 MHz)
+
+ clock-names:
+ items:
+ - const: oscclk
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: google,gs101-cmu-misc
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (24.576 MHz)
+ - description: Misc bus clock (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: dout_cmu_misc_bus
+
+required:
+ - compatible
+ - "#clock-cells"
+ - clocks
+ - clock-names
+ - reg
+
+additionalProperties: false
+
+examples:
+ # Clock controller node for CMU_TOP
+ - |
+ #include <dt-bindings/interrupt-controller/gs101.h>
+ soc {
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ cmu_top: clock-controller@1e080000 {
+ compatible = "google,gs101-cmu-top";
+ reg = <0x0 0x1e080000 0x8000>;
+ #clock-cells = <1>;
+ clocks = <&ext_24_5m>;
+ clock-names = "oscclk";
+ };
+ };
+
+...
--
2.42.0.582.g8ccd20d70d-goog
^ permalink raw reply related [flat|nested] 150+ messages in thread* [PATCH 03/21] dt-bindings: clock: Add Google gs101 clock management unit bindings
@ 2023-10-05 15:56 ` Peter Griffin
0 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-05 15:56 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi
Cc: peter.griffin, tudor.ambarus, andre.draszik, semen.protsenko,
soc, devicetree, linux-arm-kernel, linux-samsung-soc, linux-clk,
linux-gpio, linux-watchdog
Provide dt-schema documentation for Google gs101 SoC clock controller.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
.../bindings/clock/google,gs101-clock.yaml | 109 ++++++++++++++++++
1 file changed, 109 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
new file mode 100644
index 000000000000..a28d05d88afe
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
@@ -0,0 +1,109 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/google,gs101-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Google GS101 SoC clock controller
+
+maintainers:
+ - Peter Griffin <peter.griffin@linaro.org>
+
+description: |
+ Google GS101 clock controller is comprised of several CMU units, generating
+ clocks for different domains. Those CMU units are modeled as separate device
+ tree nodes, and might depend on each other. The root clock in that clock tree
+ is OSCCLK (24.576 MHz). That external clock must be defined as a fixed-rate
+ clock in dts.
+
+ CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
+ dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
+
+ Each clock is assigned an identifier and client nodes can use this identifier
+ to specify the clock which they consume. All clocks available for usage
+ in clock consumer nodes are defined as preprocessor macros in
+ 'dt-bindings/clock/gs101.h' header.
+
+properties:
+ compatible:
+ enum:
+ - google,gs101-cmu-top
+ - google,gs101-cmu-apm
+ - google,gs101-cmu-misc
+
+ clocks:
+ minItems: 1
+ maxItems: 5
+
+ clock-names:
+ minItems: 1
+ maxItems: 5
+
+ "#clock-cells":
+ const: 1
+
+ reg:
+ maxItems: 1
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: google,gs101-cmu-top
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (24.576 MHz)
+
+ clock-names:
+ items:
+ - const: oscclk
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: google,gs101-cmu-misc
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (24.576 MHz)
+ - description: Misc bus clock (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: dout_cmu_misc_bus
+
+required:
+ - compatible
+ - "#clock-cells"
+ - clocks
+ - clock-names
+ - reg
+
+additionalProperties: false
+
+examples:
+ # Clock controller node for CMU_TOP
+ - |
+ #include <dt-bindings/interrupt-controller/gs101.h>
+ soc {
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ cmu_top: clock-controller@1e080000 {
+ compatible = "google,gs101-cmu-top";
+ reg = <0x0 0x1e080000 0x8000>;
+ #clock-cells = <1>;
+ clocks = <&ext_24_5m>;
+ clock-names = "oscclk";
+ };
+ };
+
+...
--
2.42.0.582.g8ccd20d70d-goog
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 150+ messages in thread* Re: [PATCH 03/21] dt-bindings: clock: Add Google gs101 clock management unit bindings
2023-10-05 15:56 ` Peter Griffin
@ 2023-10-05 16:06 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 150+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-05 16:06 UTC (permalink / raw)
To: Peter Griffin, robh+dt, krzysztof.kozlowski+dt, mturquette,
conor+dt, sboyd, tomasz.figa, s.nawrocki, linus.walleij, wim,
linux, catalin.marinas, will, arnd, olof, cw00.choi
Cc: tudor.ambarus, andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog
On 05/10/2023 17:56, Peter Griffin wrote:
> Provide dt-schema documentation for Google gs101 SoC clock controller.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> .../bindings/clock/google,gs101-clock.yaml | 109 ++++++++++++++++++
> 1 file changed, 109 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
>
> diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
> new file mode 100644
> index 000000000000..a28d05d88afe
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
> @@ -0,0 +1,109 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/google,gs101-clock.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Google GS101 SoC clock controller
> +
> +maintainers:
> + - Peter Griffin <peter.griffin@linaro.org>
> +
> +description: |
> + Google GS101 clock controller is comprised of several CMU units, generating
> + clocks for different domains. Those CMU units are modeled as separate device
> + tree nodes, and might depend on each other. The root clock in that clock tree
> + is OSCCLK (24.576 MHz). That external clock must be defined as a fixed-rate
> + clock in dts.
> +
> + CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
> + dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
> +
> + Each clock is assigned an identifier and client nodes can use this identifier
> + to specify the clock which they consume. All clocks available for usage
> + in clock consumer nodes are defined as preprocessor macros in
> + 'dt-bindings/clock/gs101.h' header.
> +
> +properties:
> + compatible:
> + enum:
> + - google,gs101-cmu-top
> + - google,gs101-cmu-apm
> + - google,gs101-cmu-misc
> +
> + clocks:
> + minItems: 1
> + maxItems: 5
I see max 2 clocks.
> +
> + clock-names:
> + minItems: 1
> + maxItems: 5
> +
> + "#clock-cells":
> + const: 1
> +
> + reg:
> + maxItems: 1
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: google,gs101-cmu-top
> +
> + then:
> + properties:
> + clocks:
> + items:
> + - description: External reference clock (24.576 MHz)
> +
> + clock-names:
> + items:
> + - const: oscclk
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: google,gs101-cmu-misc
> +
> + then:
> + properties:
> + clocks:
> + items:
> + - description: External reference clock (24.576 MHz)
> + - description: Misc bus clock (from CMU_TOP)
> +
> + clock-names:
> + items:
> + - const: oscclk
> + - const: dout_cmu_misc_bus
What about google,gs101-cmu-apm?
> +
> +required:
"required:" go before "allOf:"
> + - compatible
> + - "#clock-cells"
> + - clocks
> + - clock-names
> + - reg
> +
> +additionalProperties: false
> +
> +examples:
> + # Clock controller node for CMU_TOP
> + - |
> + #include <dt-bindings/interrupt-controller/gs101.h>
> + soc {
> + #address-cells = <2>;
> + #size-cells = <1>;
Messed indentation.
> +
> +...
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 150+ messages in thread* Re: [PATCH 03/21] dt-bindings: clock: Add Google gs101 clock management unit bindings
@ 2023-10-05 16:06 ` Krzysztof Kozlowski
0 siblings, 0 replies; 150+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-05 16:06 UTC (permalink / raw)
To: Peter Griffin, robh+dt, krzysztof.kozlowski+dt, mturquette,
conor+dt, sboyd, tomasz.figa, s.nawrocki, linus.walleij, wim,
linux, catalin.marinas, will, arnd, olof, cw00.choi
Cc: tudor.ambarus, andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog
On 05/10/2023 17:56, Peter Griffin wrote:
> Provide dt-schema documentation for Google gs101 SoC clock controller.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> .../bindings/clock/google,gs101-clock.yaml | 109 ++++++++++++++++++
> 1 file changed, 109 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
>
> diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
> new file mode 100644
> index 000000000000..a28d05d88afe
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
> @@ -0,0 +1,109 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/google,gs101-clock.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Google GS101 SoC clock controller
> +
> +maintainers:
> + - Peter Griffin <peter.griffin@linaro.org>
> +
> +description: |
> + Google GS101 clock controller is comprised of several CMU units, generating
> + clocks for different domains. Those CMU units are modeled as separate device
> + tree nodes, and might depend on each other. The root clock in that clock tree
> + is OSCCLK (24.576 MHz). That external clock must be defined as a fixed-rate
> + clock in dts.
> +
> + CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
> + dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
> +
> + Each clock is assigned an identifier and client nodes can use this identifier
> + to specify the clock which they consume. All clocks available for usage
> + in clock consumer nodes are defined as preprocessor macros in
> + 'dt-bindings/clock/gs101.h' header.
> +
> +properties:
> + compatible:
> + enum:
> + - google,gs101-cmu-top
> + - google,gs101-cmu-apm
> + - google,gs101-cmu-misc
> +
> + clocks:
> + minItems: 1
> + maxItems: 5
I see max 2 clocks.
> +
> + clock-names:
> + minItems: 1
> + maxItems: 5
> +
> + "#clock-cells":
> + const: 1
> +
> + reg:
> + maxItems: 1
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: google,gs101-cmu-top
> +
> + then:
> + properties:
> + clocks:
> + items:
> + - description: External reference clock (24.576 MHz)
> +
> + clock-names:
> + items:
> + - const: oscclk
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: google,gs101-cmu-misc
> +
> + then:
> + properties:
> + clocks:
> + items:
> + - description: External reference clock (24.576 MHz)
> + - description: Misc bus clock (from CMU_TOP)
> +
> + clock-names:
> + items:
> + - const: oscclk
> + - const: dout_cmu_misc_bus
What about google,gs101-cmu-apm?
> +
> +required:
"required:" go before "allOf:"
> + - compatible
> + - "#clock-cells"
> + - clocks
> + - clock-names
> + - reg
> +
> +additionalProperties: false
> +
> +examples:
> + # Clock controller node for CMU_TOP
> + - |
> + #include <dt-bindings/interrupt-controller/gs101.h>
> + soc {
> + #address-cells = <2>;
> + #size-cells = <1>;
Messed indentation.
> +
> +...
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 150+ messages in thread
* [PATCH 04/21] dt-bindings: soc: google: exynos-sysreg: add dedicated SYSREG compatibles to GS101
2023-10-05 15:55 ` Peter Griffin
@ 2023-10-05 15:56 ` Peter Griffin
-1 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-05 15:56 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi
Cc: peter.griffin, tudor.ambarus, andre.draszik, semen.protsenko,
soc, devicetree, linux-arm-kernel, linux-samsung-soc, linux-clk,
linux-gpio, linux-watchdog
GS101 has three different SYSREG controllers, add dedicated
compatibles for them to the documentation.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
.../bindings/soc/samsung/samsung,exynos-sysreg.yaml | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml
index 163e912e9cad..02f580d6489b 100644
--- a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml
+++ b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml
@@ -50,6 +50,13 @@ properties:
- samsung,exynosautov9-peric1-sysreg
- const: samsung,exynosautov9-sysreg
- const: syscon
+ - items:
+ - enum:
+ - google,gs101-peric0-sysreg
+ - google,gs101-peric1-sysreg
+ - google,gs101-apm-sysreg
+ - const: google,gs101-sysreg
+ - const: syscon
reg:
maxItems: 1
--
2.42.0.582.g8ccd20d70d-goog
^ permalink raw reply related [flat|nested] 150+ messages in thread* [PATCH 04/21] dt-bindings: soc: google: exynos-sysreg: add dedicated SYSREG compatibles to GS101
@ 2023-10-05 15:56 ` Peter Griffin
0 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-05 15:56 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi
Cc: peter.griffin, tudor.ambarus, andre.draszik, semen.protsenko,
soc, devicetree, linux-arm-kernel, linux-samsung-soc, linux-clk,
linux-gpio, linux-watchdog
GS101 has three different SYSREG controllers, add dedicated
compatibles for them to the documentation.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
.../bindings/soc/samsung/samsung,exynos-sysreg.yaml | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml
index 163e912e9cad..02f580d6489b 100644
--- a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml
+++ b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml
@@ -50,6 +50,13 @@ properties:
- samsung,exynosautov9-peric1-sysreg
- const: samsung,exynosautov9-sysreg
- const: syscon
+ - items:
+ - enum:
+ - google,gs101-peric0-sysreg
+ - google,gs101-peric1-sysreg
+ - google,gs101-apm-sysreg
+ - const: google,gs101-sysreg
+ - const: syscon
reg:
maxItems: 1
--
2.42.0.582.g8ccd20d70d-goog
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 150+ messages in thread* Re: [PATCH 04/21] dt-bindings: soc: google: exynos-sysreg: add dedicated SYSREG compatibles to GS101
2023-10-05 15:56 ` Peter Griffin
@ 2023-10-05 16:07 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 150+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-05 16:07 UTC (permalink / raw)
To: Peter Griffin, robh+dt, krzysztof.kozlowski+dt, mturquette,
conor+dt, sboyd, tomasz.figa, s.nawrocki, linus.walleij, wim,
linux, catalin.marinas, will, arnd, olof, cw00.choi
Cc: tudor.ambarus, andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog
On 05/10/2023 17:56, Peter Griffin wrote:
> GS101 has three different SYSREG controllers, add dedicated
> compatibles for them to the documentation.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> .../bindings/soc/samsung/samsung,exynos-sysreg.yaml | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml
> index 163e912e9cad..02f580d6489b 100644
> --- a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml
> +++ b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml
> @@ -50,6 +50,13 @@ properties:
> - samsung,exynosautov9-peric1-sysreg
> - const: samsung,exynosautov9-sysreg
> - const: syscon
> + - items:
> + - enum:
> + - google,gs101-peric0-sysreg
> + - google,gs101-peric1-sysreg
> + - google,gs101-apm-sysreg
> + - const: google,gs101-sysreg
Please drop this one compatible. Exynos has it only for backwards
compatibility.
Also, please put entire list ("items") before such entry for
samsung,exynos5433-sysreg, so everything is more-or-less ordered
alphabetically, by the fallback compatible.
> + - const: syscon
>
> reg:
> maxItems: 1
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 150+ messages in thread* Re: [PATCH 04/21] dt-bindings: soc: google: exynos-sysreg: add dedicated SYSREG compatibles to GS101
@ 2023-10-05 16:07 ` Krzysztof Kozlowski
0 siblings, 0 replies; 150+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-05 16:07 UTC (permalink / raw)
To: Peter Griffin, robh+dt, krzysztof.kozlowski+dt, mturquette,
conor+dt, sboyd, tomasz.figa, s.nawrocki, linus.walleij, wim,
linux, catalin.marinas, will, arnd, olof, cw00.choi
Cc: tudor.ambarus, andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog
On 05/10/2023 17:56, Peter Griffin wrote:
> GS101 has three different SYSREG controllers, add dedicated
> compatibles for them to the documentation.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> .../bindings/soc/samsung/samsung,exynos-sysreg.yaml | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml
> index 163e912e9cad..02f580d6489b 100644
> --- a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml
> +++ b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml
> @@ -50,6 +50,13 @@ properties:
> - samsung,exynosautov9-peric1-sysreg
> - const: samsung,exynosautov9-sysreg
> - const: syscon
> + - items:
> + - enum:
> + - google,gs101-peric0-sysreg
> + - google,gs101-peric1-sysreg
> + - google,gs101-apm-sysreg
> + - const: google,gs101-sysreg
Please drop this one compatible. Exynos has it only for backwards
compatibility.
Also, please put entire list ("items") before such entry for
samsung,exynos5433-sysreg, so everything is more-or-less ordered
alphabetically, by the fallback compatible.
> + - const: syscon
>
> reg:
> maxItems: 1
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 150+ messages in thread* Re: [PATCH 04/21] dt-bindings: soc: google: exynos-sysreg: add dedicated SYSREG compatibles to GS101
2023-10-05 16:07 ` Krzysztof Kozlowski
@ 2023-10-06 12:41 ` Peter Griffin
-1 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-06 12:41 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi, tudor.ambarus,
andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog
Hi Krzysztof,
Many thanks for reviewing the series :)
On Thu, 5 Oct 2023 at 17:07, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 05/10/2023 17:56, Peter Griffin wrote:
> > GS101 has three different SYSREG controllers, add dedicated
> > compatibles for them to the documentation.
> >
> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> > ---
> > .../bindings/soc/samsung/samsung,exynos-sysreg.yaml | 7 +++++++
> > 1 file changed, 7 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml
> > index 163e912e9cad..02f580d6489b 100644
> > --- a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml
> > +++ b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml
> > @@ -50,6 +50,13 @@ properties:
> > - samsung,exynosautov9-peric1-sysreg
> > - const: samsung,exynosautov9-sysreg
> > - const: syscon
> > + - items:
> > + - enum:
> > + - google,gs101-peric0-sysreg
> > + - google,gs101-peric1-sysreg
> > + - google,gs101-apm-sysreg
> > + - const: google,gs101-sysreg
>
> Please drop this one compatible. Exynos has it only for backwards
> compatibility.
Just double checking, you mean I should drop this one compatible?
+ - const: google,gs101-sysreg
>
> Also, please put entire list ("items") before such entry for
> samsung,exynos5433-sysreg, so everything is more-or-less ordered
> alphabetically, by the fallback compatible.
Will do!
regards,
Peter
^ permalink raw reply [flat|nested] 150+ messages in thread* Re: [PATCH 04/21] dt-bindings: soc: google: exynos-sysreg: add dedicated SYSREG compatibles to GS101
@ 2023-10-06 12:41 ` Peter Griffin
0 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-06 12:41 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi, tudor.ambarus,
andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog
Hi Krzysztof,
Many thanks for reviewing the series :)
On Thu, 5 Oct 2023 at 17:07, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 05/10/2023 17:56, Peter Griffin wrote:
> > GS101 has three different SYSREG controllers, add dedicated
> > compatibles for them to the documentation.
> >
> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> > ---
> > .../bindings/soc/samsung/samsung,exynos-sysreg.yaml | 7 +++++++
> > 1 file changed, 7 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml
> > index 163e912e9cad..02f580d6489b 100644
> > --- a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml
> > +++ b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml
> > @@ -50,6 +50,13 @@ properties:
> > - samsung,exynosautov9-peric1-sysreg
> > - const: samsung,exynosautov9-sysreg
> > - const: syscon
> > + - items:
> > + - enum:
> > + - google,gs101-peric0-sysreg
> > + - google,gs101-peric1-sysreg
> > + - google,gs101-apm-sysreg
> > + - const: google,gs101-sysreg
>
> Please drop this one compatible. Exynos has it only for backwards
> compatibility.
Just double checking, you mean I should drop this one compatible?
+ - const: google,gs101-sysreg
>
> Also, please put entire list ("items") before such entry for
> samsung,exynos5433-sysreg, so everything is more-or-less ordered
> alphabetically, by the fallback compatible.
Will do!
regards,
Peter
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 150+ messages in thread* Re: [PATCH 04/21] dt-bindings: soc: google: exynos-sysreg: add dedicated SYSREG compatibles to GS101
2023-10-06 12:41 ` Peter Griffin
@ 2023-10-06 12:43 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 150+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-06 12:43 UTC (permalink / raw)
To: Peter Griffin
Cc: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi, tudor.ambarus,
andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog
On 06/10/2023 14:41, Peter Griffin wrote:
>>> + - enum:
>>> + - google,gs101-peric0-sysreg
>>> + - google,gs101-peric1-sysreg
>>> + - google,gs101-apm-sysreg
>>> + - const: google,gs101-sysreg
>>
>> Please drop this one compatible. Exynos has it only for backwards
>> compatibility.
>
> Just double checking, you mean I should drop this one compatible?
> + - const: google,gs101-sysreg
Yes.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 04/21] dt-bindings: soc: google: exynos-sysreg: add dedicated SYSREG compatibles to GS101
@ 2023-10-06 12:43 ` Krzysztof Kozlowski
0 siblings, 0 replies; 150+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-06 12:43 UTC (permalink / raw)
To: Peter Griffin
Cc: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi, tudor.ambarus,
andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog
On 06/10/2023 14:41, Peter Griffin wrote:
>>> + - enum:
>>> + - google,gs101-peric0-sysreg
>>> + - google,gs101-peric1-sysreg
>>> + - google,gs101-apm-sysreg
>>> + - const: google,gs101-sysreg
>>
>> Please drop this one compatible. Exynos has it only for backwards
>> compatibility.
>
> Just double checking, you mean I should drop this one compatible?
> + - const: google,gs101-sysreg
Yes.
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 150+ messages in thread
* [PATCH 05/21] dt-bindings: watchdog: Document Google gs101 & gs201 watchdog bindings
2023-10-05 15:55 ` Peter Griffin
@ 2023-10-05 15:56 ` Peter Griffin
-1 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-05 15:56 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi
Cc: peter.griffin, tudor.ambarus, andre.draszik, semen.protsenko,
soc, devicetree, linux-arm-kernel, linux-samsung-soc, linux-clk,
linux-gpio, linux-watchdog
Add the "google,gs101-wdt" and "google,gs201-wdt" compatibles to the
dt-schema documentation.
gs101 SoC has two CPU clusters and each cluster has its own dedicated
watchdog timer (similar to exynos850 and exynosautov9 SoCs).
These WDT instances are controlled using different bits in PMU
registers.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
.../devicetree/bindings/watchdog/samsung-wdt.yaml | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
index 8fb6656ba0c2..30f5949037fc 100644
--- a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
+++ b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
@@ -24,6 +24,8 @@ properties:
- samsung,exynos7-wdt # for Exynos7
- samsung,exynos850-wdt # for Exynos850
- samsung,exynosautov9-wdt # for Exynosautov9
+ - google,gs101-wdt # for Google gs101
+ - google,gs201-wdt # for Google gs101
reg:
maxItems: 1
@@ -42,13 +44,13 @@ properties:
samsung,cluster-index:
$ref: /schemas/types.yaml#/definitions/uint32
description:
- Index of CPU cluster on which watchdog is running (in case of Exynos850)
+ Index of CPU cluster on which watchdog is running (in case of Exynos850 or Google gsx01)
samsung,syscon-phandle:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to the PMU system controller node (in case of Exynos5250,
- Exynos5420, Exynos7 and Exynos850).
+ Exynos5420, Exynos7, Exynos850 and gsx01).
required:
- compatible
@@ -69,6 +71,8 @@ allOf:
- samsung,exynos7-wdt
- samsung,exynos850-wdt
- samsung,exynosautov9-wdt
+ - google,gs101-wdt
+ - google,gs201-wdt
then:
required:
- samsung,syscon-phandle
@@ -79,6 +83,8 @@ allOf:
enum:
- samsung,exynos850-wdt
- samsung,exynosautov9-wdt
+ - google,gs101-wdt
+ - google,gs201-wdt
then:
properties:
clocks:
--
2.42.0.582.g8ccd20d70d-goog
^ permalink raw reply related [flat|nested] 150+ messages in thread* [PATCH 05/21] dt-bindings: watchdog: Document Google gs101 & gs201 watchdog bindings
@ 2023-10-05 15:56 ` Peter Griffin
0 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-05 15:56 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi
Cc: peter.griffin, tudor.ambarus, andre.draszik, semen.protsenko,
soc, devicetree, linux-arm-kernel, linux-samsung-soc, linux-clk,
linux-gpio, linux-watchdog
Add the "google,gs101-wdt" and "google,gs201-wdt" compatibles to the
dt-schema documentation.
gs101 SoC has two CPU clusters and each cluster has its own dedicated
watchdog timer (similar to exynos850 and exynosautov9 SoCs).
These WDT instances are controlled using different bits in PMU
registers.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
.../devicetree/bindings/watchdog/samsung-wdt.yaml | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
index 8fb6656ba0c2..30f5949037fc 100644
--- a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
+++ b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
@@ -24,6 +24,8 @@ properties:
- samsung,exynos7-wdt # for Exynos7
- samsung,exynos850-wdt # for Exynos850
- samsung,exynosautov9-wdt # for Exynosautov9
+ - google,gs101-wdt # for Google gs101
+ - google,gs201-wdt # for Google gs101
reg:
maxItems: 1
@@ -42,13 +44,13 @@ properties:
samsung,cluster-index:
$ref: /schemas/types.yaml#/definitions/uint32
description:
- Index of CPU cluster on which watchdog is running (in case of Exynos850)
+ Index of CPU cluster on which watchdog is running (in case of Exynos850 or Google gsx01)
samsung,syscon-phandle:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to the PMU system controller node (in case of Exynos5250,
- Exynos5420, Exynos7 and Exynos850).
+ Exynos5420, Exynos7, Exynos850 and gsx01).
required:
- compatible
@@ -69,6 +71,8 @@ allOf:
- samsung,exynos7-wdt
- samsung,exynos850-wdt
- samsung,exynosautov9-wdt
+ - google,gs101-wdt
+ - google,gs201-wdt
then:
required:
- samsung,syscon-phandle
@@ -79,6 +83,8 @@ allOf:
enum:
- samsung,exynos850-wdt
- samsung,exynosautov9-wdt
+ - google,gs101-wdt
+ - google,gs201-wdt
then:
properties:
clocks:
--
2.42.0.582.g8ccd20d70d-goog
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 150+ messages in thread* Re: [PATCH 05/21] dt-bindings: watchdog: Document Google gs101 & gs201 watchdog bindings
2023-10-05 15:56 ` Peter Griffin
@ 2023-10-05 16:08 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 150+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-05 16:08 UTC (permalink / raw)
To: Peter Griffin, robh+dt, krzysztof.kozlowski+dt, mturquette,
conor+dt, sboyd, tomasz.figa, s.nawrocki, linus.walleij, wim,
linux, catalin.marinas, will, arnd, olof, cw00.choi
Cc: tudor.ambarus, andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog
On 05/10/2023 17:56, Peter Griffin wrote:
> Add the "google,gs101-wdt" and "google,gs201-wdt" compatibles to the
> dt-schema documentation.
>
> gs101 SoC has two CPU clusters and each cluster has its own dedicated
> watchdog timer (similar to exynos850 and exynosautov9 SoCs).
>
> These WDT instances are controlled using different bits in PMU
> registers.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> .../devicetree/bindings/watchdog/samsung-wdt.yaml | 10 ++++++++--
> 1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
> index 8fb6656ba0c2..30f5949037fc 100644
> --- a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
> +++ b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
> @@ -24,6 +24,8 @@ properties:
> - samsung,exynos7-wdt # for Exynos7
> - samsung,exynos850-wdt # for Exynos850
> - samsung,exynosautov9-wdt # for Exynosautov9
> + - google,gs101-wdt # for Google gs101
> + - google,gs201-wdt # for Google gs101
Alphanumerical order.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 05/21] dt-bindings: watchdog: Document Google gs101 & gs201 watchdog bindings
@ 2023-10-05 16:08 ` Krzysztof Kozlowski
0 siblings, 0 replies; 150+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-05 16:08 UTC (permalink / raw)
To: Peter Griffin, robh+dt, krzysztof.kozlowski+dt, mturquette,
conor+dt, sboyd, tomasz.figa, s.nawrocki, linus.walleij, wim,
linux, catalin.marinas, will, arnd, olof, cw00.choi
Cc: tudor.ambarus, andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog
On 05/10/2023 17:56, Peter Griffin wrote:
> Add the "google,gs101-wdt" and "google,gs201-wdt" compatibles to the
> dt-schema documentation.
>
> gs101 SoC has two CPU clusters and each cluster has its own dedicated
> watchdog timer (similar to exynos850 and exynosautov9 SoCs).
>
> These WDT instances are controlled using different bits in PMU
> registers.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> .../devicetree/bindings/watchdog/samsung-wdt.yaml | 10 ++++++++--
> 1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
> index 8fb6656ba0c2..30f5949037fc 100644
> --- a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
> +++ b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
> @@ -24,6 +24,8 @@ properties:
> - samsung,exynos7-wdt # for Exynos7
> - samsung,exynos850-wdt # for Exynos850
> - samsung,exynosautov9-wdt # for Exynosautov9
> + - google,gs101-wdt # for Google gs101
> + - google,gs201-wdt # for Google gs101
Alphanumerical order.
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 05/21] dt-bindings: watchdog: Document Google gs101 & gs201 watchdog bindings
2023-10-05 15:56 ` Peter Griffin
@ 2023-10-05 17:37 ` William McVicker
-1 siblings, 0 replies; 150+ messages in thread
From: William McVicker @ 2023-10-05 17:37 UTC (permalink / raw)
To: Peter Griffin
Cc: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi, tudor.ambarus,
andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog, kernel-team
On 10/05/2023, Peter Griffin wrote:
> Add the "google,gs101-wdt" and "google,gs201-wdt" compatibles to the
> dt-schema documentation.
>
> gs101 SoC has two CPU clusters and each cluster has its own dedicated
> watchdog timer (similar to exynos850 and exynosautov9 SoCs).
>
> These WDT instances are controlled using different bits in PMU
> registers.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> .../devicetree/bindings/watchdog/samsung-wdt.yaml | 10 ++++++++--
> 1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
> index 8fb6656ba0c2..30f5949037fc 100644
> --- a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
> +++ b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
> @@ -24,6 +24,8 @@ properties:
> - samsung,exynos7-wdt # for Exynos7
> - samsung,exynos850-wdt # for Exynos850
> - samsung,exynosautov9-wdt # for Exynosautov9
> + - google,gs101-wdt # for Google gs101
> + - google,gs201-wdt # for Google gs101
For "google,gs201-wdt the comment should be "for Google gs201".
Regards,
Will
>
> reg:
> maxItems: 1
> @@ -42,13 +44,13 @@ properties:
> samsung,cluster-index:
> $ref: /schemas/types.yaml#/definitions/uint32
> description:
> - Index of CPU cluster on which watchdog is running (in case of Exynos850)
> + Index of CPU cluster on which watchdog is running (in case of Exynos850 or Google gsx01)
>
> samsung,syscon-phandle:
> $ref: /schemas/types.yaml#/definitions/phandle
> description:
> Phandle to the PMU system controller node (in case of Exynos5250,
> - Exynos5420, Exynos7 and Exynos850).
> + Exynos5420, Exynos7, Exynos850 and gsx01).
>
> required:
> - compatible
> @@ -69,6 +71,8 @@ allOf:
> - samsung,exynos7-wdt
> - samsung,exynos850-wdt
> - samsung,exynosautov9-wdt
> + - google,gs101-wdt
> + - google,gs201-wdt
> then:
> required:
> - samsung,syscon-phandle
> @@ -79,6 +83,8 @@ allOf:
> enum:
> - samsung,exynos850-wdt
> - samsung,exynosautov9-wdt
> + - google,gs101-wdt
> + - google,gs201-wdt
> then:
> properties:
> clocks:
> --
> 2.42.0.582.g8ccd20d70d-goog
>
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 05/21] dt-bindings: watchdog: Document Google gs101 & gs201 watchdog bindings
@ 2023-10-05 17:37 ` William McVicker
0 siblings, 0 replies; 150+ messages in thread
From: William McVicker @ 2023-10-05 17:37 UTC (permalink / raw)
To: Peter Griffin
Cc: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi, tudor.ambarus,
andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog, kernel-team
On 10/05/2023, Peter Griffin wrote:
> Add the "google,gs101-wdt" and "google,gs201-wdt" compatibles to the
> dt-schema documentation.
>
> gs101 SoC has two CPU clusters and each cluster has its own dedicated
> watchdog timer (similar to exynos850 and exynosautov9 SoCs).
>
> These WDT instances are controlled using different bits in PMU
> registers.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> .../devicetree/bindings/watchdog/samsung-wdt.yaml | 10 ++++++++--
> 1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
> index 8fb6656ba0c2..30f5949037fc 100644
> --- a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
> +++ b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
> @@ -24,6 +24,8 @@ properties:
> - samsung,exynos7-wdt # for Exynos7
> - samsung,exynos850-wdt # for Exynos850
> - samsung,exynosautov9-wdt # for Exynosautov9
> + - google,gs101-wdt # for Google gs101
> + - google,gs201-wdt # for Google gs101
For "google,gs201-wdt the comment should be "for Google gs201".
Regards,
Will
>
> reg:
> maxItems: 1
> @@ -42,13 +44,13 @@ properties:
> samsung,cluster-index:
> $ref: /schemas/types.yaml#/definitions/uint32
> description:
> - Index of CPU cluster on which watchdog is running (in case of Exynos850)
> + Index of CPU cluster on which watchdog is running (in case of Exynos850 or Google gsx01)
>
> samsung,syscon-phandle:
> $ref: /schemas/types.yaml#/definitions/phandle
> description:
> Phandle to the PMU system controller node (in case of Exynos5250,
> - Exynos5420, Exynos7 and Exynos850).
> + Exynos5420, Exynos7, Exynos850 and gsx01).
>
> required:
> - compatible
> @@ -69,6 +71,8 @@ allOf:
> - samsung,exynos7-wdt
> - samsung,exynos850-wdt
> - samsung,exynosautov9-wdt
> + - google,gs101-wdt
> + - google,gs201-wdt
> then:
> required:
> - samsung,syscon-phandle
> @@ -79,6 +83,8 @@ allOf:
> enum:
> - samsung,exynos850-wdt
> - samsung,exynosautov9-wdt
> + - google,gs101-wdt
> + - google,gs201-wdt
> then:
> properties:
> clocks:
> --
> 2.42.0.582.g8ccd20d70d-goog
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 150+ messages in thread
* [PATCH 06/21] dt-bindings: arm: google: Add bindings for Google ARM platforms
2023-10-05 15:55 ` Peter Griffin
@ 2023-10-05 15:56 ` Peter Griffin
-1 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-05 15:56 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi
Cc: peter.griffin, tudor.ambarus, andre.draszik, semen.protsenko,
soc, devicetree, linux-arm-kernel, linux-samsung-soc, linux-clk,
linux-gpio, linux-watchdog
This introduces bindings and dt-schema for the Google tensor SoCs.
Currently just gs101 and pixel 6 are supported.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
.../devicetree/bindings/arm/google.yaml | 46 +++++++++++++++++++
1 file changed, 46 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/google.yaml
diff --git a/Documentation/devicetree/bindings/arm/google.yaml b/Documentation/devicetree/bindings/arm/google.yaml
new file mode 100644
index 000000000000..3759d423d9cb
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/google.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/google.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Google Tensor platforms
+
+maintainers:
+ - Peter Griffin <peter.griffin@linaro.org>
+
+description: |
+ ARM platforms using SoCs designed by Google branded "Tensor"
+ used in Pixel devices.
+
+ Currently upstream this is devices using "gs101" SoC which
+ is found in Pixel 6, Pixel 6 Pro and Pixel 6a.
+
+ Google have a few different names for the SoC.
+ - Marketing name ("Tensor")
+ - Codename ("Whitechapel")
+ - SoC ID ("gs101")
+ - Die ID ("S5P9845");
+
+ Likewise there are a couple of names for the actual device
+ - Marketing name ("Pixel 6")
+ - Codename ("Oriole")
+
+ Devicetrees should use the lowercased SoC ID and lowercased
+ board codename. e.g. gs101 and gs101-oriole
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+
+ - description: Google Pixel 6 / Oriole
+ items:
+ - enum:
+ - google,gs101-oriole
+ - const: google,gs101
+
+additionalProperties: true
+
+...
--
2.42.0.582.g8ccd20d70d-goog
^ permalink raw reply related [flat|nested] 150+ messages in thread* [PATCH 06/21] dt-bindings: arm: google: Add bindings for Google ARM platforms
@ 2023-10-05 15:56 ` Peter Griffin
0 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-05 15:56 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi
Cc: peter.griffin, tudor.ambarus, andre.draszik, semen.protsenko,
soc, devicetree, linux-arm-kernel, linux-samsung-soc, linux-clk,
linux-gpio, linux-watchdog
This introduces bindings and dt-schema for the Google tensor SoCs.
Currently just gs101 and pixel 6 are supported.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
.../devicetree/bindings/arm/google.yaml | 46 +++++++++++++++++++
1 file changed, 46 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/google.yaml
diff --git a/Documentation/devicetree/bindings/arm/google.yaml b/Documentation/devicetree/bindings/arm/google.yaml
new file mode 100644
index 000000000000..3759d423d9cb
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/google.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/google.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Google Tensor platforms
+
+maintainers:
+ - Peter Griffin <peter.griffin@linaro.org>
+
+description: |
+ ARM platforms using SoCs designed by Google branded "Tensor"
+ used in Pixel devices.
+
+ Currently upstream this is devices using "gs101" SoC which
+ is found in Pixel 6, Pixel 6 Pro and Pixel 6a.
+
+ Google have a few different names for the SoC.
+ - Marketing name ("Tensor")
+ - Codename ("Whitechapel")
+ - SoC ID ("gs101")
+ - Die ID ("S5P9845");
+
+ Likewise there are a couple of names for the actual device
+ - Marketing name ("Pixel 6")
+ - Codename ("Oriole")
+
+ Devicetrees should use the lowercased SoC ID and lowercased
+ board codename. e.g. gs101 and gs101-oriole
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+
+ - description: Google Pixel 6 / Oriole
+ items:
+ - enum:
+ - google,gs101-oriole
+ - const: google,gs101
+
+additionalProperties: true
+
+...
--
2.42.0.582.g8ccd20d70d-goog
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 150+ messages in thread* Re: [PATCH 06/21] dt-bindings: arm: google: Add bindings for Google ARM platforms
2023-10-05 15:56 ` Peter Griffin
@ 2023-10-06 20:44 ` Rob Herring
-1 siblings, 0 replies; 150+ messages in thread
From: Rob Herring @ 2023-10-06 20:44 UTC (permalink / raw)
To: Peter Griffin
Cc: krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd, tomasz.figa,
s.nawrocki, linus.walleij, wim, linux, catalin.marinas, will,
arnd, olof, cw00.choi, tudor.ambarus, andre.draszik,
semen.protsenko, soc, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-clk, linux-gpio, linux-watchdog
On Thu, Oct 05, 2023 at 04:56:03PM +0100, Peter Griffin wrote:
> This introduces bindings and dt-schema for the Google tensor SoCs.
> Currently just gs101 and pixel 6 are supported.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> .../devicetree/bindings/arm/google.yaml | 46 +++++++++++++++++++
> 1 file changed, 46 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/google.yaml
>
> diff --git a/Documentation/devicetree/bindings/arm/google.yaml b/Documentation/devicetree/bindings/arm/google.yaml
> new file mode 100644
> index 000000000000..3759d423d9cb
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/google.yaml
> @@ -0,0 +1,46 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/google.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Google Tensor platforms
> +
> +maintainers:
> + - Peter Griffin <peter.griffin@linaro.org>
> +
> +description: |
> + ARM platforms using SoCs designed by Google branded "Tensor"
> + used in Pixel devices.
> +
> + Currently upstream this is devices using "gs101" SoC which
> + is found in Pixel 6, Pixel 6 Pro and Pixel 6a.
> +
> + Google have a few different names for the SoC.
> + - Marketing name ("Tensor")
> + - Codename ("Whitechapel")
> + - SoC ID ("gs101")
> + - Die ID ("S5P9845");
> +
> + Likewise there are a couple of names for the actual device
> + - Marketing name ("Pixel 6")
> + - Codename ("Oriole")
> +
> + Devicetrees should use the lowercased SoC ID and lowercased
> + board codename. e.g. gs101 and gs101-oriole
Wrap lines at 80 char.
Otherwise,
Reviewed-by: Rob Herring <robh@kernel.org>
> +
> +properties:
> + $nodename:
> + const: '/'
> + compatible:
> + oneOf:
> +
> + - description: Google Pixel 6 / Oriole
> + items:
> + - enum:
> + - google,gs101-oriole
> + - const: google,gs101
> +
> +additionalProperties: true
> +
> +...
> --
> 2.42.0.582.g8ccd20d70d-goog
>
^ permalink raw reply [flat|nested] 150+ messages in thread* Re: [PATCH 06/21] dt-bindings: arm: google: Add bindings for Google ARM platforms
@ 2023-10-06 20:44 ` Rob Herring
0 siblings, 0 replies; 150+ messages in thread
From: Rob Herring @ 2023-10-06 20:44 UTC (permalink / raw)
To: Peter Griffin
Cc: krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd, tomasz.figa,
s.nawrocki, linus.walleij, wim, linux, catalin.marinas, will,
arnd, olof, cw00.choi, tudor.ambarus, andre.draszik,
semen.protsenko, soc, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-clk, linux-gpio, linux-watchdog
On Thu, Oct 05, 2023 at 04:56:03PM +0100, Peter Griffin wrote:
> This introduces bindings and dt-schema for the Google tensor SoCs.
> Currently just gs101 and pixel 6 are supported.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> .../devicetree/bindings/arm/google.yaml | 46 +++++++++++++++++++
> 1 file changed, 46 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/google.yaml
>
> diff --git a/Documentation/devicetree/bindings/arm/google.yaml b/Documentation/devicetree/bindings/arm/google.yaml
> new file mode 100644
> index 000000000000..3759d423d9cb
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/google.yaml
> @@ -0,0 +1,46 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/google.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Google Tensor platforms
> +
> +maintainers:
> + - Peter Griffin <peter.griffin@linaro.org>
> +
> +description: |
> + ARM platforms using SoCs designed by Google branded "Tensor"
> + used in Pixel devices.
> +
> + Currently upstream this is devices using "gs101" SoC which
> + is found in Pixel 6, Pixel 6 Pro and Pixel 6a.
> +
> + Google have a few different names for the SoC.
> + - Marketing name ("Tensor")
> + - Codename ("Whitechapel")
> + - SoC ID ("gs101")
> + - Die ID ("S5P9845");
> +
> + Likewise there are a couple of names for the actual device
> + - Marketing name ("Pixel 6")
> + - Codename ("Oriole")
> +
> + Devicetrees should use the lowercased SoC ID and lowercased
> + board codename. e.g. gs101 and gs101-oriole
Wrap lines at 80 char.
Otherwise,
Reviewed-by: Rob Herring <robh@kernel.org>
> +
> +properties:
> + $nodename:
> + const: '/'
> + compatible:
> + oneOf:
> +
> + - description: Google Pixel 6 / Oriole
> + items:
> + - enum:
> + - google,gs101-oriole
> + - const: google,gs101
> +
> +additionalProperties: true
> +
> +...
> --
> 2.42.0.582.g8ccd20d70d-goog
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 150+ messages in thread
* [PATCH 07/21] dt-bindings: pinctrl: samsung: add google,gs101-pinctrl compatible
2023-10-05 15:55 ` Peter Griffin
@ 2023-10-05 15:56 ` Peter Griffin
-1 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-05 15:56 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi
Cc: peter.griffin, tudor.ambarus, andre.draszik, semen.protsenko,
soc, devicetree, linux-arm-kernel, linux-samsung-soc, linux-clk,
linux-gpio, linux-watchdog
Add the "google,gs101-pinctrl" compatible to the dt-schema bindings
documentation.
Add maxItems of 50 for the interrupts property as gs101 can have
multiple irqs.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
.../devicetree/bindings/pinctrl/samsung,pinctrl.yaml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
index 26614621774a..e0f37f8ae8e7 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
@@ -54,11 +54,13 @@ properties:
- samsung,exynos850-pinctrl
- samsung,exynosautov9-pinctrl
- tesla,fsd-pinctrl
+ - google,gs101-pinctrl
interrupts:
description:
Required for GPIO banks supporting external GPIO interrupts.
- maxItems: 1
+ minItems: 1
+ maxItems: 50
power-domains:
maxItems: 1
--
2.42.0.582.g8ccd20d70d-goog
^ permalink raw reply related [flat|nested] 150+ messages in thread* [PATCH 07/21] dt-bindings: pinctrl: samsung: add google,gs101-pinctrl compatible
@ 2023-10-05 15:56 ` Peter Griffin
0 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-05 15:56 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi
Cc: peter.griffin, tudor.ambarus, andre.draszik, semen.protsenko,
soc, devicetree, linux-arm-kernel, linux-samsung-soc, linux-clk,
linux-gpio, linux-watchdog
Add the "google,gs101-pinctrl" compatible to the dt-schema bindings
documentation.
Add maxItems of 50 for the interrupts property as gs101 can have
multiple irqs.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
.../devicetree/bindings/pinctrl/samsung,pinctrl.yaml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
index 26614621774a..e0f37f8ae8e7 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
@@ -54,11 +54,13 @@ properties:
- samsung,exynos850-pinctrl
- samsung,exynosautov9-pinctrl
- tesla,fsd-pinctrl
+ - google,gs101-pinctrl
interrupts:
description:
Required for GPIO banks supporting external GPIO interrupts.
- maxItems: 1
+ minItems: 1
+ maxItems: 50
power-domains:
maxItems: 1
--
2.42.0.582.g8ccd20d70d-goog
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 150+ messages in thread* Re: [PATCH 07/21] dt-bindings: pinctrl: samsung: add google,gs101-pinctrl compatible
2023-10-05 15:56 ` Peter Griffin
@ 2023-10-05 16:10 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 150+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-05 16:10 UTC (permalink / raw)
To: Peter Griffin, robh+dt, krzysztof.kozlowski+dt, mturquette,
conor+dt, sboyd, tomasz.figa, s.nawrocki, linus.walleij, wim,
linux, catalin.marinas, will, arnd, olof, cw00.choi
Cc: tudor.ambarus, andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog
On 05/10/2023 17:56, Peter Griffin wrote:
> Add the "google,gs101-pinctrl" compatible to the dt-schema bindings
> documentation.
>
> Add maxItems of 50 for the interrupts property as gs101 can have
> multiple irqs.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> .../devicetree/bindings/pinctrl/samsung,pinctrl.yaml | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
> index 26614621774a..e0f37f8ae8e7 100644
> --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
> +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
> @@ -54,11 +54,13 @@ properties:
> - samsung,exynos850-pinctrl
> - samsung,exynosautov9-pinctrl
> - tesla,fsd-pinctrl
> + - google,gs101-pinctrl
Alphanumerical order
>
> interrupts:
> description:
> Required for GPIO banks supporting external GPIO interrupts.
> - maxItems: 1
> + minItems: 1
> + maxItems: 50
You need to add to allOf: a new "if:then:else:" which will:
1. narrow this for Google (with some description - is it interrupt per
GPIO? per bank?)
2. else: maxItems: 1
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 07/21] dt-bindings: pinctrl: samsung: add google,gs101-pinctrl compatible
@ 2023-10-05 16:10 ` Krzysztof Kozlowski
0 siblings, 0 replies; 150+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-05 16:10 UTC (permalink / raw)
To: Peter Griffin, robh+dt, krzysztof.kozlowski+dt, mturquette,
conor+dt, sboyd, tomasz.figa, s.nawrocki, linus.walleij, wim,
linux, catalin.marinas, will, arnd, olof, cw00.choi
Cc: tudor.ambarus, andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog
On 05/10/2023 17:56, Peter Griffin wrote:
> Add the "google,gs101-pinctrl" compatible to the dt-schema bindings
> documentation.
>
> Add maxItems of 50 for the interrupts property as gs101 can have
> multiple irqs.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> .../devicetree/bindings/pinctrl/samsung,pinctrl.yaml | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
> index 26614621774a..e0f37f8ae8e7 100644
> --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
> +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
> @@ -54,11 +54,13 @@ properties:
> - samsung,exynos850-pinctrl
> - samsung,exynosautov9-pinctrl
> - tesla,fsd-pinctrl
> + - google,gs101-pinctrl
Alphanumerical order
>
> interrupts:
> description:
> Required for GPIO banks supporting external GPIO interrupts.
> - maxItems: 1
> + minItems: 1
> + maxItems: 50
You need to add to allOf: a new "if:then:else:" which will:
1. narrow this for Google (with some description - is it interrupt per
GPIO? per bank?)
2. else: maxItems: 1
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 150+ messages in thread
* [PATCH 08/21] dt-bindings: pinctrl: samsung: add gs101-wakeup-eint compatible
2023-10-05 15:55 ` Peter Griffin
@ 2023-10-05 15:56 ` Peter Griffin
-1 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-05 15:56 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi
Cc: peter.griffin, tudor.ambarus, andre.draszik, semen.protsenko,
soc, devicetree, linux-arm-kernel, linux-samsung-soc, linux-clk,
linux-gpio, linux-watchdog
gs101 is similar to newer Exynos SoCs like Exynos850 and ExynosAutov9
where more than one pin controller can do external wake-up interrupt.
So add a dedicated compatible for it.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
.../bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml
index 1de91a51234d..668fd903d06f 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml
@@ -37,6 +37,7 @@ properties:
- samsung,exynos7-wakeup-eint
- samsung,exynos850-wakeup-eint
- samsung,exynosautov9-wakeup-eint
+ - google,gs101-wakeup-eint
interrupts:
description:
@@ -99,6 +100,7 @@ allOf:
enum:
- samsung,exynos850-wakeup-eint
- samsung,exynosautov9-wakeup-eint
+ - google,gs101-wakeup-eint
then:
properties:
interrupts: false
--
2.42.0.582.g8ccd20d70d-goog
^ permalink raw reply related [flat|nested] 150+ messages in thread* [PATCH 08/21] dt-bindings: pinctrl: samsung: add gs101-wakeup-eint compatible
@ 2023-10-05 15:56 ` Peter Griffin
0 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-05 15:56 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi
Cc: peter.griffin, tudor.ambarus, andre.draszik, semen.protsenko,
soc, devicetree, linux-arm-kernel, linux-samsung-soc, linux-clk,
linux-gpio, linux-watchdog
gs101 is similar to newer Exynos SoCs like Exynos850 and ExynosAutov9
where more than one pin controller can do external wake-up interrupt.
So add a dedicated compatible for it.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
.../bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml
index 1de91a51234d..668fd903d06f 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml
@@ -37,6 +37,7 @@ properties:
- samsung,exynos7-wakeup-eint
- samsung,exynos850-wakeup-eint
- samsung,exynosautov9-wakeup-eint
+ - google,gs101-wakeup-eint
interrupts:
description:
@@ -99,6 +100,7 @@ allOf:
enum:
- samsung,exynos850-wakeup-eint
- samsung,exynosautov9-wakeup-eint
+ - google,gs101-wakeup-eint
then:
properties:
interrupts: false
--
2.42.0.582.g8ccd20d70d-goog
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 150+ messages in thread* Re: [PATCH 08/21] dt-bindings: pinctrl: samsung: add gs101-wakeup-eint compatible
2023-10-05 15:56 ` Peter Griffin
@ 2023-10-05 16:10 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 150+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-05 16:10 UTC (permalink / raw)
To: Peter Griffin, robh+dt, krzysztof.kozlowski+dt, mturquette,
conor+dt, sboyd, tomasz.figa, s.nawrocki, linus.walleij, wim,
linux, catalin.marinas, will, arnd, olof, cw00.choi
Cc: tudor.ambarus, andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog
On 05/10/2023 17:56, Peter Griffin wrote:
> gs101 is similar to newer Exynos SoCs like Exynos850 and ExynosAutov9
> where more than one pin controller can do external wake-up interrupt.
> So add a dedicated compatible for it.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> .../bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml
> index 1de91a51234d..668fd903d06f 100644
> --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml
> +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml
> @@ -37,6 +37,7 @@ properties:
> - samsung,exynos7-wakeup-eint
> - samsung,exynos850-wakeup-eint
> - samsung,exynosautov9-wakeup-eint
> + - google,gs101-wakeup-eint
Alphanumerical order, if possible.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 08/21] dt-bindings: pinctrl: samsung: add gs101-wakeup-eint compatible
@ 2023-10-05 16:10 ` Krzysztof Kozlowski
0 siblings, 0 replies; 150+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-05 16:10 UTC (permalink / raw)
To: Peter Griffin, robh+dt, krzysztof.kozlowski+dt, mturquette,
conor+dt, sboyd, tomasz.figa, s.nawrocki, linus.walleij, wim,
linux, catalin.marinas, will, arnd, olof, cw00.choi
Cc: tudor.ambarus, andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog
On 05/10/2023 17:56, Peter Griffin wrote:
> gs101 is similar to newer Exynos SoCs like Exynos850 and ExynosAutov9
> where more than one pin controller can do external wake-up interrupt.
> So add a dedicated compatible for it.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> .../bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml
> index 1de91a51234d..668fd903d06f 100644
> --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml
> +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml
> @@ -37,6 +37,7 @@ properties:
> - samsung,exynos7-wakeup-eint
> - samsung,exynos850-wakeup-eint
> - samsung,exynosautov9-wakeup-eint
> + - google,gs101-wakeup-eint
Alphanumerical order, if possible.
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 150+ messages in thread
* [PATCH 09/21] dt-bindings: clock: gs101: Add cmu_top clock indices
2023-10-05 15:55 ` Peter Griffin
@ 2023-10-05 15:56 ` Peter Griffin
-1 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-05 15:56 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi
Cc: peter.griffin, tudor.ambarus, andre.draszik, semen.protsenko,
soc, devicetree, linux-arm-kernel, linux-samsung-soc, linux-clk,
linux-gpio, linux-watchdog
CMU_TOP geneerates clocks for all the other CMU units. Add clock
indices for those PLLs, muxes, dividers and gates.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
include/dt-bindings/clock/gs101.h | 204 ++++++++++++++++++++++++++++++
1 file changed, 204 insertions(+)
create mode 100644 include/dt-bindings/clock/gs101.h
diff --git a/include/dt-bindings/clock/gs101.h b/include/dt-bindings/clock/gs101.h
new file mode 100644
index 000000000000..d1e216a33aeb
--- /dev/null
+++ b/include/dt-bindings/clock/gs101.h
@@ -0,0 +1,204 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2023 Linaro Ltd.
+ * Author: Peter Griffin <peter.griffin@linaro.org>
+ *
+ * Device Tree binding constants for Google gs101 clock controller.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_GOOGLE_GS101_H
+#define _DT_BINDINGS_CLOCK_GOOGLE_GS101_H
+
+/* CMU_TOP PLL*/
+#define CLK_FOUT_SHARED0_PLL 1
+#define CLK_FOUT_SHARED1_PLL 2
+#define CLK_FOUT_SHARED2_PLL 3
+#define CLK_FOUT_SHARED3_PLL 4
+#define CLK_FOUT_SPARE_PLL 5
+
+/* CMU_TOP MUX*/
+#define CLK_MOUT_SHARED0_PLL 6
+#define CLK_MOUT_SHARED1_PLL 7
+#define CLK_MOUT_SHARED2_PLL 8
+#define CLK_MOUT_SHARED3_PLL 9
+#define CLK_MOUT_SPARE_PLL 10
+#define CLK_MOUT_BUS0_BUS 11
+#define CLK_MOUT_CMU_BOOST 12
+#define CLK_MOUT_BUS1_BUS 13
+#define CLK_MOUT_BUS2_BUS 14
+#define CLK_MOUT_CORE_BUS 15
+#define CLK_MOUT_EH_BUS 16
+#define CLK_MOUT_CPUCL2_SWITCH 17
+#define CLK_MOUT_CPUCL1_SWITCH 18
+#define CLK_MOUT_CPUCL0_SWITCH 19
+#define CLK_MOUT_CPUCL0_DBG 20
+#define CLK_MOUT_CMU_HPM 21
+#define CLK_MOUT_G3D_SWITCH 22
+#define CLK_MOUT_G3D_GLB 23
+#define CLK_MOUT_DPU_BUS 24
+#define CLK_MOUT_DISP_BUS 25
+#define CLK_MOUT_G2D_G2D 26
+#define CLK_MOUT_G2D_MSCL 27
+#define CLK_MOUT_HSI0_USB31DRD 28
+#define CLK_MOUT_HSI0_BUS 29
+#define CLK_MOUT_HSI0_DPGTC 30
+#define CLK_MOUT_HSI0_USBDPDGB 31
+#define CLK_MOUT_HSI1_BUS 32
+#define CLK_MOUT_HSI1_PCIE 33
+#define CLK_MOUT_HSI2_BUS 34
+#define CLK_MOUT_HSI2_PCIE 35
+#define CLK_MOUT_HSI2_UFS_EMBD 36
+#define CLK_MOUT_HSI2_MMC_CARD 37
+#define CLK_MOUT_CSIS 38
+#define CLK_MOUT_PDP_BUS 39
+#define CLK_MOUT_PDP_VRA 40
+#define CLK_MOUT_IPP_BUS 41
+#define CLK_MOUT_G3AA 42
+#define CLK_MOUT_ITP 43
+#define CLK_MOUT_DNS_BUS 44
+#define CLK_MOUT_TNR_BUS 45
+#define CLK_MOUT_MCSC_ITSC 46
+#define CLK_MOUT_MCSC_MCSC 47
+#define CLK_MOUT_GDC_SCSC 48
+#define CLK_MOUT_GDC_GDC0 49
+#define CLK_MOUT_GDC_GDC1 50
+#define CLK_MOUT_MFC_MFC 51
+#define CLK_MOUT_MIF_SWITCH 52
+#define CLK_MOUT_MIF_BUS 53
+#define CLK_MOUT_MISC_BUS 54
+#define CLK_MOUT_MISC_SSS 55
+#define CLK_MOUT_PERIC0_IP 56
+#define CLK_MOUT_PERIC0_BUS 57
+#define CLK_MOUT_PERIC1_IP 58
+#define CLK_MOUT_PERIC1_BUS 59
+#define CLK_MOUT_TPU_TPU 60
+#define CLK_MOUT_TPU_TPUCTL 61
+#define CLK_MOUT_TPU_BUS 62
+#define CLK_MOUT_TPU_UART 63
+#define CLK_MOUT_TPU_HPM 64
+#define CLK_MOUT_BO_BUS 65
+#define CLK_MOUT_G3D_BUSD 66
+
+/* CMU_TOP Dividers*/
+#define CLK_DOUT_SHARED0_DIV3 67
+#define CLK_DOUT_SHARED0_DIV2 68
+#define CLK_DOUT_SHARED0_DIV4 69
+#define CLK_DOUT_SHARED0_DIV5 70
+#define CLK_DOUT_SHARED1_DIV3 71
+#define CLK_DOUT_SHARED1_DIV2 72
+#define CLK_DOUT_SHARED1_DIV4 73
+#define CLK_DOUT_SHARED2_DIV2 74
+#define CLK_DOUT_SHARED3_DIV2 75
+#define CLK_DOUT_BUS0_BUS 76
+#define CLK_DOUT_CMU_BOOST 77
+#define CLK_DOUT_BUS1_BUS 78
+#define CLK_DOUT_BUS2_BUS 79
+#define CLK_DOUT_CORE_BUS 80
+#define CLK_DOUT_EH_BUS 81
+#define CLK_DOUT_CPUCL2_SWITCH 82
+#define CLK_DOUT_CPUCL1_SWITCH 83
+#define CLK_DOUT_CPUCL0_SWITCH 84
+#define CLK_DOUT_CPUCL0_DBG 85
+#define CLK_DOUT_CMU_HPM 86
+#define CLK_DOUT_G3D_SWITCH 87
+#define CLK_DOUT_G3D_GLB 88
+#define CLK_DOUT_DPU_BUS 89
+#define CLK_DOUT_DISP_BUS 90
+#define CLK_DOUT_G2D_G2D 91
+#define CLK_DOUT_G2D_MSCL 92
+#define CLK_DOUT_HSI0_USB31DRD 93
+#define CLK_DOUT_HSI0_BUS 94
+#define CLK_DOUT_HSI0_DPGTC 95
+#define CLK_DOUT_HSI0_USBDPDGB 96
+#define CLK_DOUT_HSI1_BUS 97
+#define CLK_DOUT_HSI1_PCIE 98
+#define CLK_DOUT_HSI2_BUS 100
+#define CLK_DOUT_HSI2_PCIE 101
+#define CLK_DOUT_HSI2_UFS_EMBD 102
+#define CLK_DOUT_HSI2_MMC_CARD 103
+#define CLK_DOUT_CSIS 104
+#define CLK_DOUT_PDP_BUS 105
+#define CLK_DOUT_PDP_VRA 106
+#define CLK_DOUT_IPP_BUS 107
+#define CLK_DOUT_G3AA 108
+#define CLK_DOUT_ITP 109
+#define CLK_DOUT_DNS_BUS 110
+#define CLK_DOUT_TNR_BUS 111
+#define CLK_DOUT_MCSC_ITSC 112
+#define CLK_DOUT_MCSC_MCSC 113
+#define CLK_DOUT_GDC_SCSC 114
+#define CLK_DOUT_GDC_GDC0 115
+#define CLK_DOUT_GDC_GDC1 116
+#define CLK_DOUT_MFC_MFC 117
+#define CLK_DOUT_MIF_BUS 118
+#define CLK_DOUT_MISC_BUS 119
+#define CLK_DOUT_MISC_SSS 120
+#define CLK_DOUT_PERIC0_BUS 121
+#define CLK_DOUT_PERIC0_IP 122
+#define CLK_DOUT_PERIC1_BUS 123
+#define CLK_DOUT_PERIC1_IP 124
+#define CLK_DOUT_TPU_TPU 125
+#define CLK_DOUT_TPU_TPUCTL 126
+#define CLK_DOUT_TPU_BUS 127
+#define CLK_DOUT_TPU_UART 128
+#define CLK_DOUT_TPU_HPM 129
+#define CLK_DOUT_BO_BUS 130
+
+/* CMU_TOP Gates*/
+#define CLK_GOUT_BUS0_BUS 131
+#define CLK_GOUT_BUS1_BUS 132
+#define CLK_GOUT_BUS2_BUS 133
+#define CLK_GOUT_CORE_BUS 134
+#define CLK_GOUT_EH_BUS 135
+#define CLK_GOUT_CPUCL2_SWITCH 136
+#define CLK_GOUT_CPUCL1_SWITCH 137
+#define CLK_GOUT_CPUCL0_SWITCH 138
+#define CLK_GOUT_CPUCL0_DBG 139
+#define CLK_GOUT_CMU_HPM 140
+#define CLK_GOUT_G3D_SWITCH 141
+#define CLK_GOUT_G3D_GLB 142
+#define CLK_GOUT_DPU_BUS 143
+#define CLK_GOUT_DISP_BUS 144
+#define CLK_GOUT_G2D_G2D 145
+#define CLK_GOUT_G2D_MSCL 146
+#define CLK_GOUT_HSI0_USB31DRD 147
+#define CLK_GOUT_HSI0_BUS 148
+#define CLK_GOUT_HSI0_DPGTC 149
+#define CLK_GOUT_HSI0_USBDPDGB 150
+#define CLK_GOUT_HSI1_BUS 151
+#define CLK_GOUT_HSI1_PCIE 152
+#define CLK_GOUT_HSI2_BUS 153
+#define CLK_GOUT_HSI2_PCIE 154
+#define CLK_GOUT_HSI2_UFS_EMBD 155
+#define CLK_GOUT_HSI2_MMC_CARD 156
+#define CLK_GOUT_CSIS 157
+#define CLK_GOUT_PDP_BUS 158
+#define CLK_GOUT_PDP_VRA 159
+#define CLK_GOUT_IPP_BUS 160
+#define CLK_GOUT_G3AA 161
+#define CLK_GOUT_ITP 162
+#define CLK_GOUT_DNS_BUS 163
+#define CLK_GOUT_TNR_BUS 164
+#define CLK_GOUT_MCSC_ITSC 165
+#define CLK_GOUT_MCSC_MCSC 166
+#define CLK_GOUT_GDC_SCSC 167
+#define CLK_GOUT_GDC_GDC0 168
+#define CLK_GOUT_GDC_GDC1 169
+#define CLK_GOUT_MFC_MFC 170
+#define CLK_GOUT_MIF_SWITCH 171
+#define CLK_GOUT_MIF_BUS 172
+#define CLK_GOUT_MISC_BUS 173
+#define CLK_GOUT_MISC_SSS 174
+#define CLK_GOUT_PERIC0_BUS 175
+#define CLK_GOUT_PERIC0_IP 176
+#define CLK_GOUT_PERIC1_BUS 177
+#define CLK_GOUT_PERIC1_IP 178
+#define CLK_GOUT_TPU_TPU 179
+#define CLK_GOUT_TPU_TPUCTL 180
+#define CLK_GOUT_TPU_BUS 181
+#define CLK_GOUT_TPU_UART 182
+#define CLK_GOUT_TPU_HPM 183
+#define CLK_GOUT_BO_BUS 184
+#define CLK_GOUT_CMU_BOOST 185
+
+#endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */
--
2.42.0.582.g8ccd20d70d-goog
^ permalink raw reply related [flat|nested] 150+ messages in thread
* [PATCH 09/21] dt-bindings: clock: gs101: Add cmu_top clock indices
@ 2023-10-05 15:56 ` Peter Griffin
0 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-05 15:56 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi
Cc: peter.griffin, tudor.ambarus, andre.draszik, semen.protsenko,
soc, devicetree, linux-arm-kernel, linux-samsung-soc, linux-clk,
linux-gpio, linux-watchdog
CMU_TOP geneerates clocks for all the other CMU units. Add clock
indices for those PLLs, muxes, dividers and gates.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
include/dt-bindings/clock/gs101.h | 204 ++++++++++++++++++++++++++++++
1 file changed, 204 insertions(+)
create mode 100644 include/dt-bindings/clock/gs101.h
diff --git a/include/dt-bindings/clock/gs101.h b/include/dt-bindings/clock/gs101.h
new file mode 100644
index 000000000000..d1e216a33aeb
--- /dev/null
+++ b/include/dt-bindings/clock/gs101.h
@@ -0,0 +1,204 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2023 Linaro Ltd.
+ * Author: Peter Griffin <peter.griffin@linaro.org>
+ *
+ * Device Tree binding constants for Google gs101 clock controller.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_GOOGLE_GS101_H
+#define _DT_BINDINGS_CLOCK_GOOGLE_GS101_H
+
+/* CMU_TOP PLL*/
+#define CLK_FOUT_SHARED0_PLL 1
+#define CLK_FOUT_SHARED1_PLL 2
+#define CLK_FOUT_SHARED2_PLL 3
+#define CLK_FOUT_SHARED3_PLL 4
+#define CLK_FOUT_SPARE_PLL 5
+
+/* CMU_TOP MUX*/
+#define CLK_MOUT_SHARED0_PLL 6
+#define CLK_MOUT_SHARED1_PLL 7
+#define CLK_MOUT_SHARED2_PLL 8
+#define CLK_MOUT_SHARED3_PLL 9
+#define CLK_MOUT_SPARE_PLL 10
+#define CLK_MOUT_BUS0_BUS 11
+#define CLK_MOUT_CMU_BOOST 12
+#define CLK_MOUT_BUS1_BUS 13
+#define CLK_MOUT_BUS2_BUS 14
+#define CLK_MOUT_CORE_BUS 15
+#define CLK_MOUT_EH_BUS 16
+#define CLK_MOUT_CPUCL2_SWITCH 17
+#define CLK_MOUT_CPUCL1_SWITCH 18
+#define CLK_MOUT_CPUCL0_SWITCH 19
+#define CLK_MOUT_CPUCL0_DBG 20
+#define CLK_MOUT_CMU_HPM 21
+#define CLK_MOUT_G3D_SWITCH 22
+#define CLK_MOUT_G3D_GLB 23
+#define CLK_MOUT_DPU_BUS 24
+#define CLK_MOUT_DISP_BUS 25
+#define CLK_MOUT_G2D_G2D 26
+#define CLK_MOUT_G2D_MSCL 27
+#define CLK_MOUT_HSI0_USB31DRD 28
+#define CLK_MOUT_HSI0_BUS 29
+#define CLK_MOUT_HSI0_DPGTC 30
+#define CLK_MOUT_HSI0_USBDPDGB 31
+#define CLK_MOUT_HSI1_BUS 32
+#define CLK_MOUT_HSI1_PCIE 33
+#define CLK_MOUT_HSI2_BUS 34
+#define CLK_MOUT_HSI2_PCIE 35
+#define CLK_MOUT_HSI2_UFS_EMBD 36
+#define CLK_MOUT_HSI2_MMC_CARD 37
+#define CLK_MOUT_CSIS 38
+#define CLK_MOUT_PDP_BUS 39
+#define CLK_MOUT_PDP_VRA 40
+#define CLK_MOUT_IPP_BUS 41
+#define CLK_MOUT_G3AA 42
+#define CLK_MOUT_ITP 43
+#define CLK_MOUT_DNS_BUS 44
+#define CLK_MOUT_TNR_BUS 45
+#define CLK_MOUT_MCSC_ITSC 46
+#define CLK_MOUT_MCSC_MCSC 47
+#define CLK_MOUT_GDC_SCSC 48
+#define CLK_MOUT_GDC_GDC0 49
+#define CLK_MOUT_GDC_GDC1 50
+#define CLK_MOUT_MFC_MFC 51
+#define CLK_MOUT_MIF_SWITCH 52
+#define CLK_MOUT_MIF_BUS 53
+#define CLK_MOUT_MISC_BUS 54
+#define CLK_MOUT_MISC_SSS 55
+#define CLK_MOUT_PERIC0_IP 56
+#define CLK_MOUT_PERIC0_BUS 57
+#define CLK_MOUT_PERIC1_IP 58
+#define CLK_MOUT_PERIC1_BUS 59
+#define CLK_MOUT_TPU_TPU 60
+#define CLK_MOUT_TPU_TPUCTL 61
+#define CLK_MOUT_TPU_BUS 62
+#define CLK_MOUT_TPU_UART 63
+#define CLK_MOUT_TPU_HPM 64
+#define CLK_MOUT_BO_BUS 65
+#define CLK_MOUT_G3D_BUSD 66
+
+/* CMU_TOP Dividers*/
+#define CLK_DOUT_SHARED0_DIV3 67
+#define CLK_DOUT_SHARED0_DIV2 68
+#define CLK_DOUT_SHARED0_DIV4 69
+#define CLK_DOUT_SHARED0_DIV5 70
+#define CLK_DOUT_SHARED1_DIV3 71
+#define CLK_DOUT_SHARED1_DIV2 72
+#define CLK_DOUT_SHARED1_DIV4 73
+#define CLK_DOUT_SHARED2_DIV2 74
+#define CLK_DOUT_SHARED3_DIV2 75
+#define CLK_DOUT_BUS0_BUS 76
+#define CLK_DOUT_CMU_BOOST 77
+#define CLK_DOUT_BUS1_BUS 78
+#define CLK_DOUT_BUS2_BUS 79
+#define CLK_DOUT_CORE_BUS 80
+#define CLK_DOUT_EH_BUS 81
+#define CLK_DOUT_CPUCL2_SWITCH 82
+#define CLK_DOUT_CPUCL1_SWITCH 83
+#define CLK_DOUT_CPUCL0_SWITCH 84
+#define CLK_DOUT_CPUCL0_DBG 85
+#define CLK_DOUT_CMU_HPM 86
+#define CLK_DOUT_G3D_SWITCH 87
+#define CLK_DOUT_G3D_GLB 88
+#define CLK_DOUT_DPU_BUS 89
+#define CLK_DOUT_DISP_BUS 90
+#define CLK_DOUT_G2D_G2D 91
+#define CLK_DOUT_G2D_MSCL 92
+#define CLK_DOUT_HSI0_USB31DRD 93
+#define CLK_DOUT_HSI0_BUS 94
+#define CLK_DOUT_HSI0_DPGTC 95
+#define CLK_DOUT_HSI0_USBDPDGB 96
+#define CLK_DOUT_HSI1_BUS 97
+#define CLK_DOUT_HSI1_PCIE 98
+#define CLK_DOUT_HSI2_BUS 100
+#define CLK_DOUT_HSI2_PCIE 101
+#define CLK_DOUT_HSI2_UFS_EMBD 102
+#define CLK_DOUT_HSI2_MMC_CARD 103
+#define CLK_DOUT_CSIS 104
+#define CLK_DOUT_PDP_BUS 105
+#define CLK_DOUT_PDP_VRA 106
+#define CLK_DOUT_IPP_BUS 107
+#define CLK_DOUT_G3AA 108
+#define CLK_DOUT_ITP 109
+#define CLK_DOUT_DNS_BUS 110
+#define CLK_DOUT_TNR_BUS 111
+#define CLK_DOUT_MCSC_ITSC 112
+#define CLK_DOUT_MCSC_MCSC 113
+#define CLK_DOUT_GDC_SCSC 114
+#define CLK_DOUT_GDC_GDC0 115
+#define CLK_DOUT_GDC_GDC1 116
+#define CLK_DOUT_MFC_MFC 117
+#define CLK_DOUT_MIF_BUS 118
+#define CLK_DOUT_MISC_BUS 119
+#define CLK_DOUT_MISC_SSS 120
+#define CLK_DOUT_PERIC0_BUS 121
+#define CLK_DOUT_PERIC0_IP 122
+#define CLK_DOUT_PERIC1_BUS 123
+#define CLK_DOUT_PERIC1_IP 124
+#define CLK_DOUT_TPU_TPU 125
+#define CLK_DOUT_TPU_TPUCTL 126
+#define CLK_DOUT_TPU_BUS 127
+#define CLK_DOUT_TPU_UART 128
+#define CLK_DOUT_TPU_HPM 129
+#define CLK_DOUT_BO_BUS 130
+
+/* CMU_TOP Gates*/
+#define CLK_GOUT_BUS0_BUS 131
+#define CLK_GOUT_BUS1_BUS 132
+#define CLK_GOUT_BUS2_BUS 133
+#define CLK_GOUT_CORE_BUS 134
+#define CLK_GOUT_EH_BUS 135
+#define CLK_GOUT_CPUCL2_SWITCH 136
+#define CLK_GOUT_CPUCL1_SWITCH 137
+#define CLK_GOUT_CPUCL0_SWITCH 138
+#define CLK_GOUT_CPUCL0_DBG 139
+#define CLK_GOUT_CMU_HPM 140
+#define CLK_GOUT_G3D_SWITCH 141
+#define CLK_GOUT_G3D_GLB 142
+#define CLK_GOUT_DPU_BUS 143
+#define CLK_GOUT_DISP_BUS 144
+#define CLK_GOUT_G2D_G2D 145
+#define CLK_GOUT_G2D_MSCL 146
+#define CLK_GOUT_HSI0_USB31DRD 147
+#define CLK_GOUT_HSI0_BUS 148
+#define CLK_GOUT_HSI0_DPGTC 149
+#define CLK_GOUT_HSI0_USBDPDGB 150
+#define CLK_GOUT_HSI1_BUS 151
+#define CLK_GOUT_HSI1_PCIE 152
+#define CLK_GOUT_HSI2_BUS 153
+#define CLK_GOUT_HSI2_PCIE 154
+#define CLK_GOUT_HSI2_UFS_EMBD 155
+#define CLK_GOUT_HSI2_MMC_CARD 156
+#define CLK_GOUT_CSIS 157
+#define CLK_GOUT_PDP_BUS 158
+#define CLK_GOUT_PDP_VRA 159
+#define CLK_GOUT_IPP_BUS 160
+#define CLK_GOUT_G3AA 161
+#define CLK_GOUT_ITP 162
+#define CLK_GOUT_DNS_BUS 163
+#define CLK_GOUT_TNR_BUS 164
+#define CLK_GOUT_MCSC_ITSC 165
+#define CLK_GOUT_MCSC_MCSC 166
+#define CLK_GOUT_GDC_SCSC 167
+#define CLK_GOUT_GDC_GDC0 168
+#define CLK_GOUT_GDC_GDC1 169
+#define CLK_GOUT_MFC_MFC 170
+#define CLK_GOUT_MIF_SWITCH 171
+#define CLK_GOUT_MIF_BUS 172
+#define CLK_GOUT_MISC_BUS 173
+#define CLK_GOUT_MISC_SSS 174
+#define CLK_GOUT_PERIC0_BUS 175
+#define CLK_GOUT_PERIC0_IP 176
+#define CLK_GOUT_PERIC1_BUS 177
+#define CLK_GOUT_PERIC1_IP 178
+#define CLK_GOUT_TPU_TPU 179
+#define CLK_GOUT_TPU_TPUCTL 180
+#define CLK_GOUT_TPU_BUS 181
+#define CLK_GOUT_TPU_UART 182
+#define CLK_GOUT_TPU_HPM 183
+#define CLK_GOUT_BO_BUS 184
+#define CLK_GOUT_CMU_BOOST 185
+
+#endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */
--
2.42.0.582.g8ccd20d70d-goog
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 150+ messages in thread
* Re: [PATCH 09/21] dt-bindings: clock: gs101: Add cmu_top clock indices
2023-10-05 15:56 ` Peter Griffin
@ 2023-10-05 16:11 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 150+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-05 16:11 UTC (permalink / raw)
To: Peter Griffin, robh+dt, krzysztof.kozlowski+dt, mturquette,
conor+dt, sboyd, tomasz.figa, s.nawrocki, linus.walleij, wim,
linux, catalin.marinas, will, arnd, olof, cw00.choi
Cc: tudor.ambarus, andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog
On 05/10/2023 17:56, Peter Griffin wrote:
> CMU_TOP geneerates clocks for all the other CMU units. Add clock
> indices for those PLLs, muxes, dividers and gates.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> include/dt-bindings/clock/gs101.h | 204 ++++++++++++++++++++++++++++++
> 1 file changed, 204 insertions(+)
> create mode 100644 include/dt-bindings/clock/gs101.h
This patch should be squashed with bindings for this clock. Header on
its own makes little sense.
Also, filename should match compatible (vendor prefix, Soc-clock etc).
>
> diff --git a/include/dt-bindings/clock/gs101.h b/include/dt-bindings/clock/gs101.h
> new file mode 100644
> index 000000000000..d1e216a33aeb
> --- /dev/null
> +++ b/include/dt-bindings/clock/gs101.h
> @@ -0,0 +1,204 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 09/21] dt-bindings: clock: gs101: Add cmu_top clock indices
@ 2023-10-05 16:11 ` Krzysztof Kozlowski
0 siblings, 0 replies; 150+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-05 16:11 UTC (permalink / raw)
To: Peter Griffin, robh+dt, krzysztof.kozlowski+dt, mturquette,
conor+dt, sboyd, tomasz.figa, s.nawrocki, linus.walleij, wim,
linux, catalin.marinas, will, arnd, olof, cw00.choi
Cc: tudor.ambarus, andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog
On 05/10/2023 17:56, Peter Griffin wrote:
> CMU_TOP geneerates clocks for all the other CMU units. Add clock
> indices for those PLLs, muxes, dividers and gates.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> include/dt-bindings/clock/gs101.h | 204 ++++++++++++++++++++++++++++++
> 1 file changed, 204 insertions(+)
> create mode 100644 include/dt-bindings/clock/gs101.h
This patch should be squashed with bindings for this clock. Header on
its own makes little sense.
Also, filename should match compatible (vendor prefix, Soc-clock etc).
>
> diff --git a/include/dt-bindings/clock/gs101.h b/include/dt-bindings/clock/gs101.h
> new file mode 100644
> index 000000000000..d1e216a33aeb
> --- /dev/null
> +++ b/include/dt-bindings/clock/gs101.h
> @@ -0,0 +1,204 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 09/21] dt-bindings: clock: gs101: Add cmu_top clock indices
2023-10-05 15:56 ` Peter Griffin
@ 2023-10-08 22:48 ` Chanwoo Choi
-1 siblings, 0 replies; 150+ messages in thread
From: Chanwoo Choi @ 2023-10-08 22:48 UTC (permalink / raw)
To: Peter Griffin, robh+dt, krzysztof.kozlowski+dt, mturquette,
conor+dt, sboyd, tomasz.figa, s.nawrocki, linus.walleij, wim,
linux, catalin.marinas, will, arnd, olof, cw00.choi
Cc: tudor.ambarus, andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog
On 23. 10. 6. 00:56, Peter Griffin wrote:
> CMU_TOP geneerates clocks for all the other CMU units. Add clock
s/geneerates/generates
> indices for those PLLs, muxes, dividers and gates.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> include/dt-bindings/clock/gs101.h | 204 ++++++++++++++++++++++++++++++
> 1 file changed, 204 insertions(+)
> create mode 100644 include/dt-bindings/clock/gs101.h
>
> diff --git a/include/dt-bindings/clock/gs101.h b/include/dt-bindings/clock/gs101.h
> new file mode 100644
> index 000000000000..d1e216a33aeb
> --- /dev/null
> +++ b/include/dt-bindings/clock/gs101.h
> @@ -0,0 +1,204 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * Copyright (C) 2023 Linaro Ltd.
> + * Author: Peter Griffin <peter.griffin@linaro.org>
> + *
> + * Device Tree binding constants for Google gs101 clock controller.
> + */
> +
> +#ifndef _DT_BINDINGS_CLOCK_GOOGLE_GS101_H
> +#define _DT_BINDINGS_CLOCK_GOOGLE_GS101_H
> +
> +/* CMU_TOP PLL*/
> +#define CLK_FOUT_SHARED0_PLL 1
> +#define CLK_FOUT_SHARED1_PLL 2
> +#define CLK_FOUT_SHARED2_PLL 3
> +#define CLK_FOUT_SHARED3_PLL 4
> +#define CLK_FOUT_SPARE_PLL 5
> +
> +/* CMU_TOP MUX*/
> +#define CLK_MOUT_SHARED0_PLL 6
> +#define CLK_MOUT_SHARED1_PLL 7
> +#define CLK_MOUT_SHARED2_PLL 8
> +#define CLK_MOUT_SHARED3_PLL 9
> +#define CLK_MOUT_SPARE_PLL 10
> +#define CLK_MOUT_BUS0_BUS 11
> +#define CLK_MOUT_CMU_BOOST 12
> +#define CLK_MOUT_BUS1_BUS 13
> +#define CLK_MOUT_BUS2_BUS 14
> +#define CLK_MOUT_CORE_BUS 15
> +#define CLK_MOUT_EH_BUS 16
> +#define CLK_MOUT_CPUCL2_SWITCH 17
> +#define CLK_MOUT_CPUCL1_SWITCH 18
> +#define CLK_MOUT_CPUCL0_SWITCH 19
> +#define CLK_MOUT_CPUCL0_DBG 20
> +#define CLK_MOUT_CMU_HPM 21
> +#define CLK_MOUT_G3D_SWITCH 22
> +#define CLK_MOUT_G3D_GLB 23
> +#define CLK_MOUT_DPU_BUS 24
> +#define CLK_MOUT_DISP_BUS 25
> +#define CLK_MOUT_G2D_G2D 26
> +#define CLK_MOUT_G2D_MSCL 27
> +#define CLK_MOUT_HSI0_USB31DRD 28
> +#define CLK_MOUT_HSI0_BUS 29
> +#define CLK_MOUT_HSI0_DPGTC 30
> +#define CLK_MOUT_HSI0_USBDPDGB 31
> +#define CLK_MOUT_HSI1_BUS 32
> +#define CLK_MOUT_HSI1_PCIE 33
> +#define CLK_MOUT_HSI2_BUS 34
> +#define CLK_MOUT_HSI2_PCIE 35
> +#define CLK_MOUT_HSI2_UFS_EMBD 36
> +#define CLK_MOUT_HSI2_MMC_CARD 37
> +#define CLK_MOUT_CSIS 38
> +#define CLK_MOUT_PDP_BUS 39
> +#define CLK_MOUT_PDP_VRA 40
> +#define CLK_MOUT_IPP_BUS 41
> +#define CLK_MOUT_G3AA 42
> +#define CLK_MOUT_ITP 43
> +#define CLK_MOUT_DNS_BUS 44
> +#define CLK_MOUT_TNR_BUS 45
> +#define CLK_MOUT_MCSC_ITSC 46
> +#define CLK_MOUT_MCSC_MCSC 47
> +#define CLK_MOUT_GDC_SCSC 48
> +#define CLK_MOUT_GDC_GDC0 49
> +#define CLK_MOUT_GDC_GDC1 50
> +#define CLK_MOUT_MFC_MFC 51
> +#define CLK_MOUT_MIF_SWITCH 52
> +#define CLK_MOUT_MIF_BUS 53
> +#define CLK_MOUT_MISC_BUS 54
> +#define CLK_MOUT_MISC_SSS 55
> +#define CLK_MOUT_PERIC0_IP 56
> +#define CLK_MOUT_PERIC0_BUS 57
> +#define CLK_MOUT_PERIC1_IP 58
> +#define CLK_MOUT_PERIC1_BUS 59
> +#define CLK_MOUT_TPU_TPU 60
> +#define CLK_MOUT_TPU_TPUCTL 61
> +#define CLK_MOUT_TPU_BUS 62
> +#define CLK_MOUT_TPU_UART 63
> +#define CLK_MOUT_TPU_HPM 64
> +#define CLK_MOUT_BO_BUS 65
> +#define CLK_MOUT_G3D_BUSD 66
> +
> +/* CMU_TOP Dividers*/
> +#define CLK_DOUT_SHARED0_DIV3 67
> +#define CLK_DOUT_SHARED0_DIV2 68
> +#define CLK_DOUT_SHARED0_DIV4 69
> +#define CLK_DOUT_SHARED0_DIV5 70
> +#define CLK_DOUT_SHARED1_DIV3 71
> +#define CLK_DOUT_SHARED1_DIV2 72
> +#define CLK_DOUT_SHARED1_DIV4 73
> +#define CLK_DOUT_SHARED2_DIV2 74
> +#define CLK_DOUT_SHARED3_DIV2 75
> +#define CLK_DOUT_BUS0_BUS 76
> +#define CLK_DOUT_CMU_BOOST 77
> +#define CLK_DOUT_BUS1_BUS 78
> +#define CLK_DOUT_BUS2_BUS 79
> +#define CLK_DOUT_CORE_BUS 80
> +#define CLK_DOUT_EH_BUS 81
> +#define CLK_DOUT_CPUCL2_SWITCH 82
> +#define CLK_DOUT_CPUCL1_SWITCH 83
> +#define CLK_DOUT_CPUCL0_SWITCH 84
> +#define CLK_DOUT_CPUCL0_DBG 85
> +#define CLK_DOUT_CMU_HPM 86
> +#define CLK_DOUT_G3D_SWITCH 87
> +#define CLK_DOUT_G3D_GLB 88
> +#define CLK_DOUT_DPU_BUS 89
> +#define CLK_DOUT_DISP_BUS 90
> +#define CLK_DOUT_G2D_G2D 91
> +#define CLK_DOUT_G2D_MSCL 92
> +#define CLK_DOUT_HSI0_USB31DRD 93
> +#define CLK_DOUT_HSI0_BUS 94
> +#define CLK_DOUT_HSI0_DPGTC 95
> +#define CLK_DOUT_HSI0_USBDPDGB 96
> +#define CLK_DOUT_HSI1_BUS 97
> +#define CLK_DOUT_HSI1_PCIE 98
> +#define CLK_DOUT_HSI2_BUS 100
> +#define CLK_DOUT_HSI2_PCIE 101
> +#define CLK_DOUT_HSI2_UFS_EMBD 102
> +#define CLK_DOUT_HSI2_MMC_CARD 103
> +#define CLK_DOUT_CSIS 104
> +#define CLK_DOUT_PDP_BUS 105
> +#define CLK_DOUT_PDP_VRA 106
> +#define CLK_DOUT_IPP_BUS 107
> +#define CLK_DOUT_G3AA 108
> +#define CLK_DOUT_ITP 109
> +#define CLK_DOUT_DNS_BUS 110
> +#define CLK_DOUT_TNR_BUS 111
> +#define CLK_DOUT_MCSC_ITSC 112
> +#define CLK_DOUT_MCSC_MCSC 113
> +#define CLK_DOUT_GDC_SCSC 114
> +#define CLK_DOUT_GDC_GDC0 115
> +#define CLK_DOUT_GDC_GDC1 116
> +#define CLK_DOUT_MFC_MFC 117
> +#define CLK_DOUT_MIF_BUS 118
> +#define CLK_DOUT_MISC_BUS 119
> +#define CLK_DOUT_MISC_SSS 120
> +#define CLK_DOUT_PERIC0_BUS 121
> +#define CLK_DOUT_PERIC0_IP 122
> +#define CLK_DOUT_PERIC1_BUS 123
> +#define CLK_DOUT_PERIC1_IP 124
> +#define CLK_DOUT_TPU_TPU 125
> +#define CLK_DOUT_TPU_TPUCTL 126
> +#define CLK_DOUT_TPU_BUS 127
> +#define CLK_DOUT_TPU_UART 128
> +#define CLK_DOUT_TPU_HPM 129
> +#define CLK_DOUT_BO_BUS 130
> +
> +/* CMU_TOP Gates*/
> +#define CLK_GOUT_BUS0_BUS 131
> +#define CLK_GOUT_BUS1_BUS 132
> +#define CLK_GOUT_BUS2_BUS 133
> +#define CLK_GOUT_CORE_BUS 134
> +#define CLK_GOUT_EH_BUS 135
> +#define CLK_GOUT_CPUCL2_SWITCH 136
> +#define CLK_GOUT_CPUCL1_SWITCH 137
> +#define CLK_GOUT_CPUCL0_SWITCH 138
> +#define CLK_GOUT_CPUCL0_DBG 139
> +#define CLK_GOUT_CMU_HPM 140
> +#define CLK_GOUT_G3D_SWITCH 141
> +#define CLK_GOUT_G3D_GLB 142
> +#define CLK_GOUT_DPU_BUS 143
> +#define CLK_GOUT_DISP_BUS 144
> +#define CLK_GOUT_G2D_G2D 145
> +#define CLK_GOUT_G2D_MSCL 146
> +#define CLK_GOUT_HSI0_USB31DRD 147
> +#define CLK_GOUT_HSI0_BUS 148
> +#define CLK_GOUT_HSI0_DPGTC 149
> +#define CLK_GOUT_HSI0_USBDPDGB 150
> +#define CLK_GOUT_HSI1_BUS 151
> +#define CLK_GOUT_HSI1_PCIE 152
> +#define CLK_GOUT_HSI2_BUS 153
> +#define CLK_GOUT_HSI2_PCIE 154
> +#define CLK_GOUT_HSI2_UFS_EMBD 155
> +#define CLK_GOUT_HSI2_MMC_CARD 156
> +#define CLK_GOUT_CSIS 157
> +#define CLK_GOUT_PDP_BUS 158
> +#define CLK_GOUT_PDP_VRA 159
> +#define CLK_GOUT_IPP_BUS 160
> +#define CLK_GOUT_G3AA 161
> +#define CLK_GOUT_ITP 162
> +#define CLK_GOUT_DNS_BUS 163
> +#define CLK_GOUT_TNR_BUS 164
> +#define CLK_GOUT_MCSC_ITSC 165
> +#define CLK_GOUT_MCSC_MCSC 166
> +#define CLK_GOUT_GDC_SCSC 167
> +#define CLK_GOUT_GDC_GDC0 168
> +#define CLK_GOUT_GDC_GDC1 169
> +#define CLK_GOUT_MFC_MFC 170
> +#define CLK_GOUT_MIF_SWITCH 171
> +#define CLK_GOUT_MIF_BUS 172
> +#define CLK_GOUT_MISC_BUS 173
> +#define CLK_GOUT_MISC_SSS 174
> +#define CLK_GOUT_PERIC0_BUS 175
> +#define CLK_GOUT_PERIC0_IP 176
> +#define CLK_GOUT_PERIC1_BUS 177
> +#define CLK_GOUT_PERIC1_IP 178
> +#define CLK_GOUT_TPU_TPU 179
> +#define CLK_GOUT_TPU_TPUCTL 180
> +#define CLK_GOUT_TPU_BUS 181
> +#define CLK_GOUT_TPU_UART 182
> +#define CLK_GOUT_TPU_HPM 183
> +#define CLK_GOUT_BO_BUS 184
> +#define CLK_GOUT_CMU_BOOST 185
> +
> +#endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */
--
Best Regards,
Samsung Electronics
Chanwoo Choi
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 09/21] dt-bindings: clock: gs101: Add cmu_top clock indices
@ 2023-10-08 22:48 ` Chanwoo Choi
0 siblings, 0 replies; 150+ messages in thread
From: Chanwoo Choi @ 2023-10-08 22:48 UTC (permalink / raw)
To: Peter Griffin, robh+dt, krzysztof.kozlowski+dt, mturquette,
conor+dt, sboyd, tomasz.figa, s.nawrocki, linus.walleij, wim,
linux, catalin.marinas, will, arnd, olof, cw00.choi
Cc: tudor.ambarus, andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog
On 23. 10. 6. 00:56, Peter Griffin wrote:
> CMU_TOP geneerates clocks for all the other CMU units. Add clock
s/geneerates/generates
> indices for those PLLs, muxes, dividers and gates.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> include/dt-bindings/clock/gs101.h | 204 ++++++++++++++++++++++++++++++
> 1 file changed, 204 insertions(+)
> create mode 100644 include/dt-bindings/clock/gs101.h
>
> diff --git a/include/dt-bindings/clock/gs101.h b/include/dt-bindings/clock/gs101.h
> new file mode 100644
> index 000000000000..d1e216a33aeb
> --- /dev/null
> +++ b/include/dt-bindings/clock/gs101.h
> @@ -0,0 +1,204 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * Copyright (C) 2023 Linaro Ltd.
> + * Author: Peter Griffin <peter.griffin@linaro.org>
> + *
> + * Device Tree binding constants for Google gs101 clock controller.
> + */
> +
> +#ifndef _DT_BINDINGS_CLOCK_GOOGLE_GS101_H
> +#define _DT_BINDINGS_CLOCK_GOOGLE_GS101_H
> +
> +/* CMU_TOP PLL*/
> +#define CLK_FOUT_SHARED0_PLL 1
> +#define CLK_FOUT_SHARED1_PLL 2
> +#define CLK_FOUT_SHARED2_PLL 3
> +#define CLK_FOUT_SHARED3_PLL 4
> +#define CLK_FOUT_SPARE_PLL 5
> +
> +/* CMU_TOP MUX*/
> +#define CLK_MOUT_SHARED0_PLL 6
> +#define CLK_MOUT_SHARED1_PLL 7
> +#define CLK_MOUT_SHARED2_PLL 8
> +#define CLK_MOUT_SHARED3_PLL 9
> +#define CLK_MOUT_SPARE_PLL 10
> +#define CLK_MOUT_BUS0_BUS 11
> +#define CLK_MOUT_CMU_BOOST 12
> +#define CLK_MOUT_BUS1_BUS 13
> +#define CLK_MOUT_BUS2_BUS 14
> +#define CLK_MOUT_CORE_BUS 15
> +#define CLK_MOUT_EH_BUS 16
> +#define CLK_MOUT_CPUCL2_SWITCH 17
> +#define CLK_MOUT_CPUCL1_SWITCH 18
> +#define CLK_MOUT_CPUCL0_SWITCH 19
> +#define CLK_MOUT_CPUCL0_DBG 20
> +#define CLK_MOUT_CMU_HPM 21
> +#define CLK_MOUT_G3D_SWITCH 22
> +#define CLK_MOUT_G3D_GLB 23
> +#define CLK_MOUT_DPU_BUS 24
> +#define CLK_MOUT_DISP_BUS 25
> +#define CLK_MOUT_G2D_G2D 26
> +#define CLK_MOUT_G2D_MSCL 27
> +#define CLK_MOUT_HSI0_USB31DRD 28
> +#define CLK_MOUT_HSI0_BUS 29
> +#define CLK_MOUT_HSI0_DPGTC 30
> +#define CLK_MOUT_HSI0_USBDPDGB 31
> +#define CLK_MOUT_HSI1_BUS 32
> +#define CLK_MOUT_HSI1_PCIE 33
> +#define CLK_MOUT_HSI2_BUS 34
> +#define CLK_MOUT_HSI2_PCIE 35
> +#define CLK_MOUT_HSI2_UFS_EMBD 36
> +#define CLK_MOUT_HSI2_MMC_CARD 37
> +#define CLK_MOUT_CSIS 38
> +#define CLK_MOUT_PDP_BUS 39
> +#define CLK_MOUT_PDP_VRA 40
> +#define CLK_MOUT_IPP_BUS 41
> +#define CLK_MOUT_G3AA 42
> +#define CLK_MOUT_ITP 43
> +#define CLK_MOUT_DNS_BUS 44
> +#define CLK_MOUT_TNR_BUS 45
> +#define CLK_MOUT_MCSC_ITSC 46
> +#define CLK_MOUT_MCSC_MCSC 47
> +#define CLK_MOUT_GDC_SCSC 48
> +#define CLK_MOUT_GDC_GDC0 49
> +#define CLK_MOUT_GDC_GDC1 50
> +#define CLK_MOUT_MFC_MFC 51
> +#define CLK_MOUT_MIF_SWITCH 52
> +#define CLK_MOUT_MIF_BUS 53
> +#define CLK_MOUT_MISC_BUS 54
> +#define CLK_MOUT_MISC_SSS 55
> +#define CLK_MOUT_PERIC0_IP 56
> +#define CLK_MOUT_PERIC0_BUS 57
> +#define CLK_MOUT_PERIC1_IP 58
> +#define CLK_MOUT_PERIC1_BUS 59
> +#define CLK_MOUT_TPU_TPU 60
> +#define CLK_MOUT_TPU_TPUCTL 61
> +#define CLK_MOUT_TPU_BUS 62
> +#define CLK_MOUT_TPU_UART 63
> +#define CLK_MOUT_TPU_HPM 64
> +#define CLK_MOUT_BO_BUS 65
> +#define CLK_MOUT_G3D_BUSD 66
> +
> +/* CMU_TOP Dividers*/
> +#define CLK_DOUT_SHARED0_DIV3 67
> +#define CLK_DOUT_SHARED0_DIV2 68
> +#define CLK_DOUT_SHARED0_DIV4 69
> +#define CLK_DOUT_SHARED0_DIV5 70
> +#define CLK_DOUT_SHARED1_DIV3 71
> +#define CLK_DOUT_SHARED1_DIV2 72
> +#define CLK_DOUT_SHARED1_DIV4 73
> +#define CLK_DOUT_SHARED2_DIV2 74
> +#define CLK_DOUT_SHARED3_DIV2 75
> +#define CLK_DOUT_BUS0_BUS 76
> +#define CLK_DOUT_CMU_BOOST 77
> +#define CLK_DOUT_BUS1_BUS 78
> +#define CLK_DOUT_BUS2_BUS 79
> +#define CLK_DOUT_CORE_BUS 80
> +#define CLK_DOUT_EH_BUS 81
> +#define CLK_DOUT_CPUCL2_SWITCH 82
> +#define CLK_DOUT_CPUCL1_SWITCH 83
> +#define CLK_DOUT_CPUCL0_SWITCH 84
> +#define CLK_DOUT_CPUCL0_DBG 85
> +#define CLK_DOUT_CMU_HPM 86
> +#define CLK_DOUT_G3D_SWITCH 87
> +#define CLK_DOUT_G3D_GLB 88
> +#define CLK_DOUT_DPU_BUS 89
> +#define CLK_DOUT_DISP_BUS 90
> +#define CLK_DOUT_G2D_G2D 91
> +#define CLK_DOUT_G2D_MSCL 92
> +#define CLK_DOUT_HSI0_USB31DRD 93
> +#define CLK_DOUT_HSI0_BUS 94
> +#define CLK_DOUT_HSI0_DPGTC 95
> +#define CLK_DOUT_HSI0_USBDPDGB 96
> +#define CLK_DOUT_HSI1_BUS 97
> +#define CLK_DOUT_HSI1_PCIE 98
> +#define CLK_DOUT_HSI2_BUS 100
> +#define CLK_DOUT_HSI2_PCIE 101
> +#define CLK_DOUT_HSI2_UFS_EMBD 102
> +#define CLK_DOUT_HSI2_MMC_CARD 103
> +#define CLK_DOUT_CSIS 104
> +#define CLK_DOUT_PDP_BUS 105
> +#define CLK_DOUT_PDP_VRA 106
> +#define CLK_DOUT_IPP_BUS 107
> +#define CLK_DOUT_G3AA 108
> +#define CLK_DOUT_ITP 109
> +#define CLK_DOUT_DNS_BUS 110
> +#define CLK_DOUT_TNR_BUS 111
> +#define CLK_DOUT_MCSC_ITSC 112
> +#define CLK_DOUT_MCSC_MCSC 113
> +#define CLK_DOUT_GDC_SCSC 114
> +#define CLK_DOUT_GDC_GDC0 115
> +#define CLK_DOUT_GDC_GDC1 116
> +#define CLK_DOUT_MFC_MFC 117
> +#define CLK_DOUT_MIF_BUS 118
> +#define CLK_DOUT_MISC_BUS 119
> +#define CLK_DOUT_MISC_SSS 120
> +#define CLK_DOUT_PERIC0_BUS 121
> +#define CLK_DOUT_PERIC0_IP 122
> +#define CLK_DOUT_PERIC1_BUS 123
> +#define CLK_DOUT_PERIC1_IP 124
> +#define CLK_DOUT_TPU_TPU 125
> +#define CLK_DOUT_TPU_TPUCTL 126
> +#define CLK_DOUT_TPU_BUS 127
> +#define CLK_DOUT_TPU_UART 128
> +#define CLK_DOUT_TPU_HPM 129
> +#define CLK_DOUT_BO_BUS 130
> +
> +/* CMU_TOP Gates*/
> +#define CLK_GOUT_BUS0_BUS 131
> +#define CLK_GOUT_BUS1_BUS 132
> +#define CLK_GOUT_BUS2_BUS 133
> +#define CLK_GOUT_CORE_BUS 134
> +#define CLK_GOUT_EH_BUS 135
> +#define CLK_GOUT_CPUCL2_SWITCH 136
> +#define CLK_GOUT_CPUCL1_SWITCH 137
> +#define CLK_GOUT_CPUCL0_SWITCH 138
> +#define CLK_GOUT_CPUCL0_DBG 139
> +#define CLK_GOUT_CMU_HPM 140
> +#define CLK_GOUT_G3D_SWITCH 141
> +#define CLK_GOUT_G3D_GLB 142
> +#define CLK_GOUT_DPU_BUS 143
> +#define CLK_GOUT_DISP_BUS 144
> +#define CLK_GOUT_G2D_G2D 145
> +#define CLK_GOUT_G2D_MSCL 146
> +#define CLK_GOUT_HSI0_USB31DRD 147
> +#define CLK_GOUT_HSI0_BUS 148
> +#define CLK_GOUT_HSI0_DPGTC 149
> +#define CLK_GOUT_HSI0_USBDPDGB 150
> +#define CLK_GOUT_HSI1_BUS 151
> +#define CLK_GOUT_HSI1_PCIE 152
> +#define CLK_GOUT_HSI2_BUS 153
> +#define CLK_GOUT_HSI2_PCIE 154
> +#define CLK_GOUT_HSI2_UFS_EMBD 155
> +#define CLK_GOUT_HSI2_MMC_CARD 156
> +#define CLK_GOUT_CSIS 157
> +#define CLK_GOUT_PDP_BUS 158
> +#define CLK_GOUT_PDP_VRA 159
> +#define CLK_GOUT_IPP_BUS 160
> +#define CLK_GOUT_G3AA 161
> +#define CLK_GOUT_ITP 162
> +#define CLK_GOUT_DNS_BUS 163
> +#define CLK_GOUT_TNR_BUS 164
> +#define CLK_GOUT_MCSC_ITSC 165
> +#define CLK_GOUT_MCSC_MCSC 166
> +#define CLK_GOUT_GDC_SCSC 167
> +#define CLK_GOUT_GDC_GDC0 168
> +#define CLK_GOUT_GDC_GDC1 169
> +#define CLK_GOUT_MFC_MFC 170
> +#define CLK_GOUT_MIF_SWITCH 171
> +#define CLK_GOUT_MIF_BUS 172
> +#define CLK_GOUT_MISC_BUS 173
> +#define CLK_GOUT_MISC_SSS 174
> +#define CLK_GOUT_PERIC0_BUS 175
> +#define CLK_GOUT_PERIC0_IP 176
> +#define CLK_GOUT_PERIC1_BUS 177
> +#define CLK_GOUT_PERIC1_IP 178
> +#define CLK_GOUT_TPU_TPU 179
> +#define CLK_GOUT_TPU_TPUCTL 180
> +#define CLK_GOUT_TPU_BUS 181
> +#define CLK_GOUT_TPU_UART 182
> +#define CLK_GOUT_TPU_HPM 183
> +#define CLK_GOUT_BO_BUS 184
> +#define CLK_GOUT_CMU_BOOST 185
> +
> +#endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */
--
Best Regards,
Samsung Electronics
Chanwoo Choi
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 150+ messages in thread
* [PATCH 10/21] dt-bindings: clock: gs101: Add cmu_apm clock indices
2023-10-05 15:55 ` Peter Griffin
@ 2023-10-05 15:56 ` Peter Griffin
-1 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-05 15:56 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi
Cc: peter.griffin, tudor.ambarus, andre.draszik, semen.protsenko,
soc, devicetree, linux-arm-kernel, linux-samsung-soc, linux-clk,
linux-gpio, linux-watchdog
CMU_APM generates clocks for the Active Power Management
controller. Add clock indices for those muxs, dividers and
gates.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
include/dt-bindings/clock/gs101.h | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/include/dt-bindings/clock/gs101.h b/include/dt-bindings/clock/gs101.h
index d1e216a33aeb..d9b8299fcc0b 100644
--- a/include/dt-bindings/clock/gs101.h
+++ b/include/dt-bindings/clock/gs101.h
@@ -201,4 +201,21 @@
#define CLK_GOUT_BO_BUS 184
#define CLK_GOUT_CMU_BOOST 185
+/* CMU_APM */
+
+#define CLK_MOUT_APM_FUNC 1
+#define CLK_MOUT_APM_FUNCSRC 2
+#define CLK_DOUT_APM_BOOST 3
+#define CLK_DOUT_APM_USI0_UART 4
+#define CLK_DOUT_APM_USI0_USI 5
+#define CLK_DOUT_APM_USI1_UART 6
+#define CLK_GOUT_APM_FUNC 7
+#define CLK_GOUT_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK 8
+#define CLK_GOUT_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK 9
+#define CLK_GOUT_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK 10
+#define CLK_GOUT_APM_UID_SYSREG_APM_IPCLKPORT_PCLK 11
+#define CLK_APM_PLL_DIV2_APM 12
+#define CLK_APM_PLL_DIV4_APM 13
+#define CLK_APM_PLL_DIV16_APM 14
+
#endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */
--
2.42.0.582.g8ccd20d70d-goog
^ permalink raw reply related [flat|nested] 150+ messages in thread
* [PATCH 10/21] dt-bindings: clock: gs101: Add cmu_apm clock indices
@ 2023-10-05 15:56 ` Peter Griffin
0 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-05 15:56 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi
Cc: peter.griffin, tudor.ambarus, andre.draszik, semen.protsenko,
soc, devicetree, linux-arm-kernel, linux-samsung-soc, linux-clk,
linux-gpio, linux-watchdog
CMU_APM generates clocks for the Active Power Management
controller. Add clock indices for those muxs, dividers and
gates.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
include/dt-bindings/clock/gs101.h | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/include/dt-bindings/clock/gs101.h b/include/dt-bindings/clock/gs101.h
index d1e216a33aeb..d9b8299fcc0b 100644
--- a/include/dt-bindings/clock/gs101.h
+++ b/include/dt-bindings/clock/gs101.h
@@ -201,4 +201,21 @@
#define CLK_GOUT_BO_BUS 184
#define CLK_GOUT_CMU_BOOST 185
+/* CMU_APM */
+
+#define CLK_MOUT_APM_FUNC 1
+#define CLK_MOUT_APM_FUNCSRC 2
+#define CLK_DOUT_APM_BOOST 3
+#define CLK_DOUT_APM_USI0_UART 4
+#define CLK_DOUT_APM_USI0_USI 5
+#define CLK_DOUT_APM_USI1_UART 6
+#define CLK_GOUT_APM_FUNC 7
+#define CLK_GOUT_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK 8
+#define CLK_GOUT_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK 9
+#define CLK_GOUT_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK 10
+#define CLK_GOUT_APM_UID_SYSREG_APM_IPCLKPORT_PCLK 11
+#define CLK_APM_PLL_DIV2_APM 12
+#define CLK_APM_PLL_DIV4_APM 13
+#define CLK_APM_PLL_DIV16_APM 14
+
#endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */
--
2.42.0.582.g8ccd20d70d-goog
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 150+ messages in thread
* Re: [PATCH 10/21] dt-bindings: clock: gs101: Add cmu_apm clock indices
2023-10-05 15:56 ` Peter Griffin
@ 2023-10-05 16:11 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 150+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-05 16:11 UTC (permalink / raw)
To: Peter Griffin, robh+dt, krzysztof.kozlowski+dt, mturquette,
conor+dt, sboyd, tomasz.figa, s.nawrocki, linus.walleij, wim,
linux, catalin.marinas, will, arnd, olof, cw00.choi
Cc: tudor.ambarus, andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog
On 05/10/2023 17:56, Peter Griffin wrote:
> CMU_APM generates clocks for the Active Power Management
> controller. Add clock indices for those muxs, dividers and
> gates.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> include/dt-bindings/clock/gs101.h | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
Please squash it with previous patch.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 10/21] dt-bindings: clock: gs101: Add cmu_apm clock indices
@ 2023-10-05 16:11 ` Krzysztof Kozlowski
0 siblings, 0 replies; 150+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-05 16:11 UTC (permalink / raw)
To: Peter Griffin, robh+dt, krzysztof.kozlowski+dt, mturquette,
conor+dt, sboyd, tomasz.figa, s.nawrocki, linus.walleij, wim,
linux, catalin.marinas, will, arnd, olof, cw00.choi
Cc: tudor.ambarus, andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog
On 05/10/2023 17:56, Peter Griffin wrote:
> CMU_APM generates clocks for the Active Power Management
> controller. Add clock indices for those muxs, dividers and
> gates.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> include/dt-bindings/clock/gs101.h | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
Please squash it with previous patch.
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 150+ messages in thread
* [PATCH 11/21] dt-bindings: clock: gs101: Add cmu_misc clock indices
2023-10-05 15:55 ` Peter Griffin
@ 2023-10-05 15:56 ` Peter Griffin
-1 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-05 15:56 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi
Cc: peter.griffin, tudor.ambarus, andre.draszik, semen.protsenko,
soc, devicetree, linux-arm-kernel, linux-samsung-soc, linux-clk,
linux-gpio, linux-watchdog
CMU_MISC generates clocks for IPs such as Watchdog. Add
clock indices for the PLLs, Muxes, dividers and gates
in this clock management unit.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
include/dt-bindings/clock/gs101.h | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/include/dt-bindings/clock/gs101.h b/include/dt-bindings/clock/gs101.h
index d9b8299fcc0b..7765ba68f734 100644
--- a/include/dt-bindings/clock/gs101.h
+++ b/include/dt-bindings/clock/gs101.h
@@ -218,4 +218,15 @@
#define CLK_APM_PLL_DIV4_APM 13
#define CLK_APM_PLL_DIV16_APM 14
+/* CMU_MISC */
+
+#define CLK_MOUT_MISC_BUS_USER 1
+#define CLK_MOUT_MISC_SSS_USER 2
+#define CLK_DOUT_MISC_BUSP 3
+#define CLK_DOUT_MISC_GIC 4
+#define CLK_GOUT_MISC_PCLK 5
+#define CLK_GOUT_MISC_SYSREG_PCLK 6
+#define CLK_GOUT_MISC_WDT_CLUSTER0 7
+#define CLK_GOUT_MISC_WDT_CLUSTER1 8
+
#endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */
--
2.42.0.582.g8ccd20d70d-goog
^ permalink raw reply related [flat|nested] 150+ messages in thread
* [PATCH 11/21] dt-bindings: clock: gs101: Add cmu_misc clock indices
@ 2023-10-05 15:56 ` Peter Griffin
0 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-05 15:56 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi
Cc: peter.griffin, tudor.ambarus, andre.draszik, semen.protsenko,
soc, devicetree, linux-arm-kernel, linux-samsung-soc, linux-clk,
linux-gpio, linux-watchdog
CMU_MISC generates clocks for IPs such as Watchdog. Add
clock indices for the PLLs, Muxes, dividers and gates
in this clock management unit.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
include/dt-bindings/clock/gs101.h | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/include/dt-bindings/clock/gs101.h b/include/dt-bindings/clock/gs101.h
index d9b8299fcc0b..7765ba68f734 100644
--- a/include/dt-bindings/clock/gs101.h
+++ b/include/dt-bindings/clock/gs101.h
@@ -218,4 +218,15 @@
#define CLK_APM_PLL_DIV4_APM 13
#define CLK_APM_PLL_DIV16_APM 14
+/* CMU_MISC */
+
+#define CLK_MOUT_MISC_BUS_USER 1
+#define CLK_MOUT_MISC_SSS_USER 2
+#define CLK_DOUT_MISC_BUSP 3
+#define CLK_DOUT_MISC_GIC 4
+#define CLK_GOUT_MISC_PCLK 5
+#define CLK_GOUT_MISC_SYSREG_PCLK 6
+#define CLK_GOUT_MISC_WDT_CLUSTER0 7
+#define CLK_GOUT_MISC_WDT_CLUSTER1 8
+
#endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */
--
2.42.0.582.g8ccd20d70d-goog
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 150+ messages in thread
* [PATCH 12/21] clk: samsung: clk-pll: Add support for pll_{0516,0517,518}
2023-10-05 15:55 ` Peter Griffin
@ 2023-10-05 15:56 ` Peter Griffin
-1 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-05 15:56 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi
Cc: peter.griffin, tudor.ambarus, andre.draszik, semen.protsenko,
soc, devicetree, linux-arm-kernel, linux-samsung-soc, linux-clk,
linux-gpio, linux-watchdog
Thesee plls are found in the Tensor gs101 SoC found in the Pixel 6.
pll0516x: Integrer PLL with high frequency
pll0517x: Integrer PLL with middle frequency
pll0518x: Integrer PLL with low frequency
PLL0516x
FOUT = (MDIV * 2 * FIN)/PDIV * 2^SDIV)
PLL0517x and PLL0518x
FOUT = (MDIV * FIN)/PDIV*2^SDIV)
The PLLs are similar enough to pll_0822x that the same code can handle
both. The main difference is the change in the fout formula for the
high frequency 0516 pll.
Locktime for 516,517 & 518 is 150 the same as the pll_0822x lock factor.
MDIV, SDIV PDIV masks and bit shifts are also the same as 0822x.
When defining the PLL the "con" parameter should be set to CON3
register, like this
PLL(pll_0517x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0,
NULL),
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
drivers/clk/samsung/clk-pll.c | 9 ++++++++-
drivers/clk/samsung/clk-pll.h | 3 +++
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 74934c6182ce..4ef9fea2a425 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -442,7 +442,11 @@ static unsigned long samsung_pll0822x_recalc_rate(struct clk_hw *hw,
pdiv = (pll_con3 >> PLL0822X_PDIV_SHIFT) & PLL0822X_PDIV_MASK;
sdiv = (pll_con3 >> PLL0822X_SDIV_SHIFT) & PLL0822X_SDIV_MASK;
- fvco *= mdiv;
+ if (pll->type == pll_0516x)
+ fvco = fvco * 2 * mdiv;
+ else
+ fvco *= mdiv;
+
do_div(fvco, (pdiv << sdiv));
return (unsigned long)fvco;
@@ -1316,6 +1320,9 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
case pll_1417x:
case pll_0818x:
case pll_0822x:
+ case pll_0516x:
+ case pll_0517x:
+ case pll_0518x:
pll->enable_offs = PLL0822X_ENABLE_SHIFT;
pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT;
if (!pll->rate_table)
diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
index 0725d485c6ee..ffd3d52c0dec 100644
--- a/drivers/clk/samsung/clk-pll.h
+++ b/drivers/clk/samsung/clk-pll.h
@@ -38,6 +38,9 @@ enum samsung_pll_type {
pll_0822x,
pll_0831x,
pll_142xx,
+ pll_0516x,
+ pll_0517x,
+ pll_0518x,
};
#define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \
--
2.42.0.582.g8ccd20d70d-goog
^ permalink raw reply related [flat|nested] 150+ messages in thread* [PATCH 12/21] clk: samsung: clk-pll: Add support for pll_{0516,0517,518}
@ 2023-10-05 15:56 ` Peter Griffin
0 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-05 15:56 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi
Cc: peter.griffin, tudor.ambarus, andre.draszik, semen.protsenko,
soc, devicetree, linux-arm-kernel, linux-samsung-soc, linux-clk,
linux-gpio, linux-watchdog
Thesee plls are found in the Tensor gs101 SoC found in the Pixel 6.
pll0516x: Integrer PLL with high frequency
pll0517x: Integrer PLL with middle frequency
pll0518x: Integrer PLL with low frequency
PLL0516x
FOUT = (MDIV * 2 * FIN)/PDIV * 2^SDIV)
PLL0517x and PLL0518x
FOUT = (MDIV * FIN)/PDIV*2^SDIV)
The PLLs are similar enough to pll_0822x that the same code can handle
both. The main difference is the change in the fout formula for the
high frequency 0516 pll.
Locktime for 516,517 & 518 is 150 the same as the pll_0822x lock factor.
MDIV, SDIV PDIV masks and bit shifts are also the same as 0822x.
When defining the PLL the "con" parameter should be set to CON3
register, like this
PLL(pll_0517x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0,
NULL),
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
drivers/clk/samsung/clk-pll.c | 9 ++++++++-
drivers/clk/samsung/clk-pll.h | 3 +++
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 74934c6182ce..4ef9fea2a425 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -442,7 +442,11 @@ static unsigned long samsung_pll0822x_recalc_rate(struct clk_hw *hw,
pdiv = (pll_con3 >> PLL0822X_PDIV_SHIFT) & PLL0822X_PDIV_MASK;
sdiv = (pll_con3 >> PLL0822X_SDIV_SHIFT) & PLL0822X_SDIV_MASK;
- fvco *= mdiv;
+ if (pll->type == pll_0516x)
+ fvco = fvco * 2 * mdiv;
+ else
+ fvco *= mdiv;
+
do_div(fvco, (pdiv << sdiv));
return (unsigned long)fvco;
@@ -1316,6 +1320,9 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
case pll_1417x:
case pll_0818x:
case pll_0822x:
+ case pll_0516x:
+ case pll_0517x:
+ case pll_0518x:
pll->enable_offs = PLL0822X_ENABLE_SHIFT;
pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT;
if (!pll->rate_table)
diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
index 0725d485c6ee..ffd3d52c0dec 100644
--- a/drivers/clk/samsung/clk-pll.h
+++ b/drivers/clk/samsung/clk-pll.h
@@ -38,6 +38,9 @@ enum samsung_pll_type {
pll_0822x,
pll_0831x,
pll_142xx,
+ pll_0516x,
+ pll_0517x,
+ pll_0518x,
};
#define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \
--
2.42.0.582.g8ccd20d70d-goog
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 150+ messages in thread* Re: [PATCH 12/21] clk: samsung: clk-pll: Add support for pll_{0516,0517,518}
2023-10-05 15:56 ` Peter Griffin
@ 2023-10-05 17:39 ` William McVicker
-1 siblings, 0 replies; 150+ messages in thread
From: William McVicker @ 2023-10-05 17:39 UTC (permalink / raw)
To: Peter Griffin
Cc: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi, tudor.ambarus,
andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog, kernel-team
On 10/05/2023, Peter Griffin wrote:
> Thesee plls are found in the Tensor gs101 SoC found in the Pixel 6.
nit: Thesee -> These
>
> pll0516x: Integrer PLL with high frequency
> pll0517x: Integrer PLL with middle frequency
> pll0518x: Integrer PLL with low frequency
nit: Integrer -> Integer?
Regards,
Will
>
> PLL0516x
> FOUT = (MDIV * 2 * FIN)/PDIV * 2^SDIV)
>
> PLL0517x and PLL0518x
> FOUT = (MDIV * FIN)/PDIV*2^SDIV)
>
> The PLLs are similar enough to pll_0822x that the same code can handle
> both. The main difference is the change in the fout formula for the
> high frequency 0516 pll.
>
> Locktime for 516,517 & 518 is 150 the same as the pll_0822x lock factor.
> MDIV, SDIV PDIV masks and bit shifts are also the same as 0822x.
>
> When defining the PLL the "con" parameter should be set to CON3
> register, like this
>
> PLL(pll_0517x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
> PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0,
> NULL),
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> drivers/clk/samsung/clk-pll.c | 9 ++++++++-
> drivers/clk/samsung/clk-pll.h | 3 +++
> 2 files changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
> index 74934c6182ce..4ef9fea2a425 100644
> --- a/drivers/clk/samsung/clk-pll.c
> +++ b/drivers/clk/samsung/clk-pll.c
> @@ -442,7 +442,11 @@ static unsigned long samsung_pll0822x_recalc_rate(struct clk_hw *hw,
> pdiv = (pll_con3 >> PLL0822X_PDIV_SHIFT) & PLL0822X_PDIV_MASK;
> sdiv = (pll_con3 >> PLL0822X_SDIV_SHIFT) & PLL0822X_SDIV_MASK;
>
> - fvco *= mdiv;
> + if (pll->type == pll_0516x)
> + fvco = fvco * 2 * mdiv;
> + else
> + fvco *= mdiv;
> +
> do_div(fvco, (pdiv << sdiv));
>
> return (unsigned long)fvco;
> @@ -1316,6 +1320,9 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
> case pll_1417x:
> case pll_0818x:
> case pll_0822x:
> + case pll_0516x:
> + case pll_0517x:
> + case pll_0518x:
> pll->enable_offs = PLL0822X_ENABLE_SHIFT;
> pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT;
> if (!pll->rate_table)
> diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
> index 0725d485c6ee..ffd3d52c0dec 100644
> --- a/drivers/clk/samsung/clk-pll.h
> +++ b/drivers/clk/samsung/clk-pll.h
> @@ -38,6 +38,9 @@ enum samsung_pll_type {
> pll_0822x,
> pll_0831x,
> pll_142xx,
> + pll_0516x,
> + pll_0517x,
> + pll_0518x,
> };
>
> #define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \
> --
> 2.42.0.582.g8ccd20d70d-goog
>
^ permalink raw reply [flat|nested] 150+ messages in thread* Re: [PATCH 12/21] clk: samsung: clk-pll: Add support for pll_{0516,0517,518}
@ 2023-10-05 17:39 ` William McVicker
0 siblings, 0 replies; 150+ messages in thread
From: William McVicker @ 2023-10-05 17:39 UTC (permalink / raw)
To: Peter Griffin
Cc: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi, tudor.ambarus,
andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog, kernel-team
On 10/05/2023, Peter Griffin wrote:
> Thesee plls are found in the Tensor gs101 SoC found in the Pixel 6.
nit: Thesee -> These
>
> pll0516x: Integrer PLL with high frequency
> pll0517x: Integrer PLL with middle frequency
> pll0518x: Integrer PLL with low frequency
nit: Integrer -> Integer?
Regards,
Will
>
> PLL0516x
> FOUT = (MDIV * 2 * FIN)/PDIV * 2^SDIV)
>
> PLL0517x and PLL0518x
> FOUT = (MDIV * FIN)/PDIV*2^SDIV)
>
> The PLLs are similar enough to pll_0822x that the same code can handle
> both. The main difference is the change in the fout formula for the
> high frequency 0516 pll.
>
> Locktime for 516,517 & 518 is 150 the same as the pll_0822x lock factor.
> MDIV, SDIV PDIV masks and bit shifts are also the same as 0822x.
>
> When defining the PLL the "con" parameter should be set to CON3
> register, like this
>
> PLL(pll_0517x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
> PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0,
> NULL),
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> drivers/clk/samsung/clk-pll.c | 9 ++++++++-
> drivers/clk/samsung/clk-pll.h | 3 +++
> 2 files changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
> index 74934c6182ce..4ef9fea2a425 100644
> --- a/drivers/clk/samsung/clk-pll.c
> +++ b/drivers/clk/samsung/clk-pll.c
> @@ -442,7 +442,11 @@ static unsigned long samsung_pll0822x_recalc_rate(struct clk_hw *hw,
> pdiv = (pll_con3 >> PLL0822X_PDIV_SHIFT) & PLL0822X_PDIV_MASK;
> sdiv = (pll_con3 >> PLL0822X_SDIV_SHIFT) & PLL0822X_SDIV_MASK;
>
> - fvco *= mdiv;
> + if (pll->type == pll_0516x)
> + fvco = fvco * 2 * mdiv;
> + else
> + fvco *= mdiv;
> +
> do_div(fvco, (pdiv << sdiv));
>
> return (unsigned long)fvco;
> @@ -1316,6 +1320,9 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
> case pll_1417x:
> case pll_0818x:
> case pll_0822x:
> + case pll_0516x:
> + case pll_0517x:
> + case pll_0518x:
> pll->enable_offs = PLL0822X_ENABLE_SHIFT;
> pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT;
> if (!pll->rate_table)
> diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
> index 0725d485c6ee..ffd3d52c0dec 100644
> --- a/drivers/clk/samsung/clk-pll.h
> +++ b/drivers/clk/samsung/clk-pll.h
> @@ -38,6 +38,9 @@ enum samsung_pll_type {
> pll_0822x,
> pll_0831x,
> pll_142xx,
> + pll_0516x,
> + pll_0517x,
> + pll_0518x,
> };
>
> #define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \
> --
> 2.42.0.582.g8ccd20d70d-goog
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 12/21] clk: samsung: clk-pll: Add support for pll_{0516,0517,518}
2023-10-05 15:56 ` Peter Griffin
@ 2023-10-08 22:51 ` Chanwoo Choi
-1 siblings, 0 replies; 150+ messages in thread
From: Chanwoo Choi @ 2023-10-08 22:51 UTC (permalink / raw)
To: Peter Griffin, robh+dt, krzysztof.kozlowski+dt, mturquette,
conor+dt, sboyd, tomasz.figa, s.nawrocki, linus.walleij, wim,
linux, catalin.marinas, will, arnd, olof, cw00.choi
Cc: tudor.ambarus, andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog
Hi,
On 23. 10. 6. 00:56, Peter Griffin wrote:
> Thesee plls are found in the Tensor gs101 SoC found in the Pixel 6.
>
> pll0516x: Integrer PLL with high frequency
> pll0517x: Integrer PLL with middle frequency
> pll0518x: Integrer PLL with low frequency
>
> PLL0516x
> FOUT = (MDIV * 2 * FIN)/PDIV * 2^SDIV)
>
> PLL0517x and PLL0518x
> FOUT = (MDIV * FIN)/PDIV*2^SDIV)
>
> The PLLs are similar enough to pll_0822x that the same code can handle
> both. The main difference is the change in the fout formula for the
> high frequency 0516 pll.
>
> Locktime for 516,517 & 518 is 150 the same as the pll_0822x lock factor.
> MDIV, SDIV PDIV masks and bit shifts are also the same as 0822x.
>
> When defining the PLL the "con" parameter should be set to CON3
> register, like this
>
> PLL(pll_0517x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
> PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0,
> NULL),
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Thanks for the detailed description about h/w spec.
> ---
> drivers/clk/samsung/clk-pll.c | 9 ++++++++-
> drivers/clk/samsung/clk-pll.h | 3 +++
> 2 files changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
> index 74934c6182ce..4ef9fea2a425 100644
> --- a/drivers/clk/samsung/clk-pll.c
> +++ b/drivers/clk/samsung/clk-pll.c
> @@ -442,7 +442,11 @@ static unsigned long samsung_pll0822x_recalc_rate(struct clk_hw *hw,
> pdiv = (pll_con3 >> PLL0822X_PDIV_SHIFT) & PLL0822X_PDIV_MASK;
> sdiv = (pll_con3 >> PLL0822X_SDIV_SHIFT) & PLL0822X_SDIV_MASK;
>
> - fvco *= mdiv;
> + if (pll->type == pll_0516x)
> + fvco = fvco * 2 * mdiv;
> + else
> + fvco *= mdiv;
> +
> do_div(fvco, (pdiv << sdiv));
>
> return (unsigned long)fvco;
> @@ -1316,6 +1320,9 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
> case pll_1417x:
> case pll_0818x:
> case pll_0822x:
> + case pll_0516x:
> + case pll_0517x:
> + case pll_0518x:
> pll->enable_offs = PLL0822X_ENABLE_SHIFT;
> pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT;
> if (!pll->rate_table)
> diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
> index 0725d485c6ee..ffd3d52c0dec 100644
> --- a/drivers/clk/samsung/clk-pll.h
> +++ b/drivers/clk/samsung/clk-pll.h
> @@ -38,6 +38,9 @@ enum samsung_pll_type {
> pll_0822x,
> pll_0831x,
> pll_142xx,
> + pll_0516x,
> + pll_0517x,
> + pll_0518x,
> };
>
> #define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
--
Best Regards,
Samsung Electronics
Chanwoo Choi
^ permalink raw reply [flat|nested] 150+ messages in thread* Re: [PATCH 12/21] clk: samsung: clk-pll: Add support for pll_{0516,0517,518}
@ 2023-10-08 22:51 ` Chanwoo Choi
0 siblings, 0 replies; 150+ messages in thread
From: Chanwoo Choi @ 2023-10-08 22:51 UTC (permalink / raw)
To: Peter Griffin, robh+dt, krzysztof.kozlowski+dt, mturquette,
conor+dt, sboyd, tomasz.figa, s.nawrocki, linus.walleij, wim,
linux, catalin.marinas, will, arnd, olof, cw00.choi
Cc: tudor.ambarus, andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog
Hi,
On 23. 10. 6. 00:56, Peter Griffin wrote:
> Thesee plls are found in the Tensor gs101 SoC found in the Pixel 6.
>
> pll0516x: Integrer PLL with high frequency
> pll0517x: Integrer PLL with middle frequency
> pll0518x: Integrer PLL with low frequency
>
> PLL0516x
> FOUT = (MDIV * 2 * FIN)/PDIV * 2^SDIV)
>
> PLL0517x and PLL0518x
> FOUT = (MDIV * FIN)/PDIV*2^SDIV)
>
> The PLLs are similar enough to pll_0822x that the same code can handle
> both. The main difference is the change in the fout formula for the
> high frequency 0516 pll.
>
> Locktime for 516,517 & 518 is 150 the same as the pll_0822x lock factor.
> MDIV, SDIV PDIV masks and bit shifts are also the same as 0822x.
>
> When defining the PLL the "con" parameter should be set to CON3
> register, like this
>
> PLL(pll_0517x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
> PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0,
> NULL),
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Thanks for the detailed description about h/w spec.
> ---
> drivers/clk/samsung/clk-pll.c | 9 ++++++++-
> drivers/clk/samsung/clk-pll.h | 3 +++
> 2 files changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
> index 74934c6182ce..4ef9fea2a425 100644
> --- a/drivers/clk/samsung/clk-pll.c
> +++ b/drivers/clk/samsung/clk-pll.c
> @@ -442,7 +442,11 @@ static unsigned long samsung_pll0822x_recalc_rate(struct clk_hw *hw,
> pdiv = (pll_con3 >> PLL0822X_PDIV_SHIFT) & PLL0822X_PDIV_MASK;
> sdiv = (pll_con3 >> PLL0822X_SDIV_SHIFT) & PLL0822X_SDIV_MASK;
>
> - fvco *= mdiv;
> + if (pll->type == pll_0516x)
> + fvco = fvco * 2 * mdiv;
> + else
> + fvco *= mdiv;
> +
> do_div(fvco, (pdiv << sdiv));
>
> return (unsigned long)fvco;
> @@ -1316,6 +1320,9 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
> case pll_1417x:
> case pll_0818x:
> case pll_0822x:
> + case pll_0516x:
> + case pll_0517x:
> + case pll_0518x:
> pll->enable_offs = PLL0822X_ENABLE_SHIFT;
> pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT;
> if (!pll->rate_table)
> diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
> index 0725d485c6ee..ffd3d52c0dec 100644
> --- a/drivers/clk/samsung/clk-pll.h
> +++ b/drivers/clk/samsung/clk-pll.h
> @@ -38,6 +38,9 @@ enum samsung_pll_type {
> pll_0822x,
> pll_0831x,
> pll_142xx,
> + pll_0516x,
> + pll_0517x,
> + pll_0518x,
> };
>
> #define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
--
Best Regards,
Samsung Electronics
Chanwoo Choi
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 150+ messages in thread
* [PATCH 13/21] clk: samsung: clk-gs101: Add cmu_top registers, plls, mux and gates
2023-10-05 15:55 ` Peter Griffin
@ 2023-10-05 15:56 ` Peter Griffin
-1 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-05 15:56 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi
Cc: peter.griffin, tudor.ambarus, andre.draszik, semen.protsenko,
soc, devicetree, linux-arm-kernel, linux-samsung-soc, linux-clk,
linux-gpio, linux-watchdog
CMU_TOP is the top level clock management unit which contains PLLs, muxes
and gates that feed the other clock management units.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
drivers/clk/samsung/Kconfig | 9 +
drivers/clk/samsung/Makefile | 1 +
drivers/clk/samsung/clk-gs101.c | 1558 +++++++++++++++++++++++++++++++
3 files changed, 1568 insertions(+)
create mode 100644 drivers/clk/samsung/clk-gs101.c
diff --git a/drivers/clk/samsung/Kconfig b/drivers/clk/samsung/Kconfig
index 76a494e95027..4c8f173c4dec 100644
--- a/drivers/clk/samsung/Kconfig
+++ b/drivers/clk/samsung/Kconfig
@@ -13,6 +13,7 @@ config COMMON_CLK_SAMSUNG
select EXYNOS_5420_COMMON_CLK if ARM && SOC_EXYNOS5420
select EXYNOS_ARM64_COMMON_CLK if ARM64 && ARCH_EXYNOS
select TESLA_FSD_COMMON_CLK if ARM64 && ARCH_TESLA_FSD
+ select GOOGLE_GS101_COMMON_CLK if ARM64 && ARCH_GOOGLE_TENSOR
config S3C64XX_COMMON_CLK
bool "Samsung S3C64xx clock controller support" if COMPILE_TEST
@@ -102,3 +103,11 @@ config TESLA_FSD_COMMON_CLK
help
Support for the clock controller present on the Tesla FSD SoC.
Choose Y here only if you build for this SoC.
+
+config GOOGLE_GS101_COMMON_CLK
+ bool "Google gs101 clock controller support" if COMPILE_TEST
+ depends on COMMON_CLK_SAMSUNG
+ depends on EXYNOS_ARM64_COMMON_CLK
+ help
+ Support for the clock controller present on the Google gs101 SoC.
+ Choose Y here only if you build for this SoC.
\ No newline at end of file
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index ebbeacabe88f..1e69b8e14324 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -24,3 +24,4 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov9.o
obj-$(CONFIG_S3C64XX_COMMON_CLK) += clk-s3c64xx.o
obj-$(CONFIG_S5PV210_COMMON_CLK) += clk-s5pv210.o clk-s5pv210-audss.o
obj-$(CONFIG_TESLA_FSD_COMMON_CLK) += clk-fsd.o
+obj-$(CONFIG_GOOGLE_GS101_COMMON_CLK) += clk-gs101.o
diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
new file mode 100644
index 000000000000..4c58fcc899be
--- /dev/null
+++ b/drivers/clk/samsung/clk-gs101.c
@@ -0,0 +1,1558 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2023 Linaro Ltd.
+ * Author: Peter Griffin <peter.griffin@linaro.org>
+ *
+ * Common Clock Framework support for GS101.
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include <dt-bindings/clock/gs101.h>
+
+#include "clk.h"
+#include "clk-exynos-arm64.h"
+
+/* NOTE: Must be equal to the last clock ID increased by one */
+#define TOP_NR_CLK (CLK_GOUT_CMU_BOOST + 1)
+
+/* ---- CMU_TOP ------------------------------------------------------------- */
+
+/* Register Offset definitions for CMU_TOP (0x1e080000) */
+
+#define PLL_LOCKTIME_PLL_SHARED0 0x0000
+#define PLL_LOCKTIME_PLL_SHARED1 0x0004
+#define PLL_LOCKTIME_PLL_SHARED2 0x0008
+#define PLL_LOCKTIME_PLL_SHARED3 0x000c
+#define PLL_LOCKTIME_PLL_SPARE 0x0010
+#define PLL_CON0_PLL_SHARED0 0x0100
+#define PLL_CON1_PLL_SHARED0 0x0104
+#define PLL_CON2_PLL_SHARED0 0x0108
+#define PLL_CON3_PLL_SHARED0 0x010c
+#define PLL_CON4_PLL_SHARED0 0x0110
+#define PLL_CON0_PLL_SHARED1 0x0140
+#define PLL_CON1_PLL_SHARED1 0x0144
+#define PLL_CON2_PLL_SHARED1 0x0148
+#define PLL_CON3_PLL_SHARED1 0x014c
+#define PLL_CON4_PLL_SHARED1 0x0150
+#define PLL_CON0_PLL_SHARED2 0x0180
+#define PLL_CON1_PLL_SHARED2 0x0184
+#define PLL_CON2_PLL_SHARED2 0x0188
+#define PLL_CON3_PLL_SHARED2 0x018c
+#define PLL_CON4_PLL_SHARED2 0x0190
+#define PLL_CON0_PLL_SHARED3 0x01c0
+#define PLL_CON1_PLL_SHARED3 0x01c4
+#define PLL_CON2_PLL_SHARED3 0x01c8
+#define PLL_CON3_PLL_SHARED3 0x01cc
+#define PLL_CON4_PLL_SHARED3 0x01d0
+#define PLL_CON0_PLL_SPARE 0x0200
+#define PLL_CON1_PLL_SPARE 0x0204
+#define PLL_CON2_PLL_SPARE 0x0208
+#define PLL_CON3_PLL_SPARE 0x020c
+#define PLL_CON4_PLL_SPARE 0x0210
+#define CMU_CMU_TOP_CONTROLLER_OPTION 0x0800
+#define CLKOUT_CON_BLK_CMU_CMU_TOP_CLKOUT0 0x0810
+#define CMU_HCHGEN_CLKMUX_CMU_BOOST 0x0840
+#define CMU_HCHGEN_CLKMUX_TOP_BOOST 0x0844
+#define CMU_HCHGEN_CLKMUX 0x0850
+#define POWER_FAIL_DETECT_PLL 0x0864
+#define EARLY_WAKEUP_FORCED_0_ENABLE 0x0870
+#define EARLY_WAKEUP_FORCED_1_ENABLE 0x0874
+#define EARLY_WAKEUP_APM_CTRL 0x0878
+#define EARLY_WAKEUP_CLUSTER0_CTRL 0x087c
+#define EARLY_WAKEUP_DPU_CTRL 0x0880
+#define EARLY_WAKEUP_CSIS_CTRL 0x0884
+#define EARLY_WAKEUP_APM_DEST 0x0890
+#define EARLY_WAKEUP_CLUSTER0_DEST 0x0894
+#define EARLY_WAKEUP_DPU_DEST 0x0898
+#define EARLY_WAKEUP_CSIS_DEST 0x089c
+#define EARLY_WAKEUP_SW_TRIG_APM 0x08c0
+#define EARLY_WAKEUP_SW_TRIG_APM_SET 0x08c4
+#define EARLY_WAKEUP_SW_TRIG_APM_CLEAR 0x08c8
+#define EARLY_WAKEUP_SW_TRIG_CLUSTER0 0x08d0
+#define EARLY_WAKEUP_SW_TRIG_CLUSTER0_SET 0x08d4
+#define EARLY_WAKEUP_SW_TRIG_CLUSTER0_CLEAR 0x08d8
+#define EARLY_WAKEUP_SW_TRIG_DPU 0x08e0
+#define EARLY_WAKEUP_SW_TRIG_DPU_SET 0x08e4
+#define EARLY_WAKEUP_SW_TRIG_DPU_CLEAR 0x08e8
+#define EARLY_WAKEUP_SW_TRIG_CSIS 0x08f0
+#define EARLY_WAKEUP_SW_TRIG_CSIS_SET 0x08f4
+#define EARLY_WAKEUP_SW_TRIG_CSIS_CLEAR 0x08f8
+
+#define CLK_CON_MUX_MUX_CLKCMU_BO_BUS 0x1000
+#define CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS 0x1004
+#define CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS 0x1008
+#define CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS 0x100c
+#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0 0x1010
+#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1 0x1014
+#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2 0x1018
+#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3 0x101c
+#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4 0x1020
+#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5 0x1024
+#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6 0x1028
+#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7 0x102c
+#define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST 0x1030
+#define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1 0x1034
+#define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1038
+#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG 0x103c
+#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH 0x1040
+#define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH 0x1044
+#define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH 0x1048
+#define CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS 0x104c
+#define CLK_CON_MUX_MUX_CLKCMU_DISP_BUS 0x1050
+#define CLK_CON_MUX_MUX_CLKCMU_DNS_BUS 0x1054
+#define CLK_CON_MUX_MUX_CLKCMU_DPU_BUS 0x1058
+#define CLK_CON_MUX_MUX_CLKCMU_EH_BUS 0x105c
+#define CLK_CON_MUX_MUX_CLKCMU_G2D_G2D 0x1060
+#define CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL 0x1064
+#define CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA 0x1068
+#define CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD 0x106c
+#define CLK_CON_MUX_MUX_CLKCMU_G3D_GLB 0x1070
+#define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH 0x1074
+#define CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0 0x1078
+#define CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1 0x107c
+#define CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC 0x1080
+#define CLK_CON_MUX_MUX_CLKCMU_HPM 0x1084
+#define CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS 0x1088
+#define CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC 0x108c
+#define CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD 0x1090
+#define CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG 0x1094
+#define CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS 0x1098
+#define CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE 0x109c
+#define CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS 0x10a0
+#define CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD 0x10a4
+#define CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE 0x10a8
+#define CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD 0x10ac
+#define CLK_CON_MUX_MUX_CLKCMU_IPP_BUS 0x10b0
+#define CLK_CON_MUX_MUX_CLKCMU_ITP_BUS 0x10b4
+#define CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC 0x10b8
+#define CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC 0x10bc
+#define CLK_CON_MUX_MUX_CLKCMU_MFC_MFC 0x10c0
+#define CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP 0x10c4
+#define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0x10c8
+#define CLK_CON_MUX_MUX_CLKCMU_MISC_BUS 0x10cc
+#define CLK_CON_MUX_MUX_CLKCMU_MISC_SSS 0x10d0
+#define CLK_CON_MUX_MUX_CLKCMU_PDP_BUS 0x10d4
+#define CLK_CON_MUX_MUX_CLKCMU_PDP_VRA 0x10d8
+#define CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS 0x10dc
+#define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP 0x10e0
+#define CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS 0x10e4
+#define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP 0x10e8
+#define CLK_CON_MUX_MUX_CLKCMU_TNR_BUS 0x10ec
+#define CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1 0x10f0
+#define CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF 0x10f4
+#define CLK_CON_MUX_MUX_CLKCMU_TPU_BUS 0x10f8
+#define CLK_CON_MUX_MUX_CLKCMU_TPU_TPU 0x10fc
+#define CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL 0x1100
+#define CLK_CON_MUX_MUX_CLKCMU_TPU_UART 0x1104
+#define CLK_CON_MUX_MUX_CMU_CMUREF 0x1108
+
+#define CLK_CON_DIV_CLKCMU_BO_BUS 0x1800
+#define CLK_CON_DIV_CLKCMU_BUS0_BUS 0x1804
+#define CLK_CON_DIV_CLKCMU_BUS1_BUS 0x1808
+#define CLK_CON_DIV_CLKCMU_BUS2_BUS 0x180c
+#define CLK_CON_DIV_CLKCMU_CIS_CLK0 0x1810
+#define CLK_CON_DIV_CLKCMU_CIS_CLK1 0x1814
+#define CLK_CON_DIV_CLKCMU_CIS_CLK2 0x1818
+#define CLK_CON_DIV_CLKCMU_CIS_CLK3 0x181c
+#define CLK_CON_DIV_CLKCMU_CIS_CLK4 0x1820
+#define CLK_CON_DIV_CLKCMU_CIS_CLK5 0x1824
+#define CLK_CON_DIV_CLKCMU_CIS_CLK6 0x1828
+#define CLK_CON_DIV_CLKCMU_CIS_CLK7 0x182c
+#define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1830
+#define CLK_CON_DIV_CLKCMU_CPUCL0_DBG 0x1834
+#define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH 0x1838
+#define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH 0x183c
+#define CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH 0x1840
+#define CLK_CON_DIV_CLKCMU_CSIS_BUS 0x1844
+#define CLK_CON_DIV_CLKCMU_DISP_BUS 0x1848
+#define CLK_CON_DIV_CLKCMU_DNS_BUS 0x184c
+#define CLK_CON_DIV_CLKCMU_DPU_BUS 0x1850
+#define CLK_CON_DIV_CLKCMU_EH_BUS 0x1854
+#define CLK_CON_DIV_CLKCMU_G2D_G2D 0x1858
+#define CLK_CON_DIV_CLKCMU_G2D_MSCL 0x185c
+#define CLK_CON_DIV_CLKCMU_G3AA_G3AA 0x1860
+#define CLK_CON_DIV_CLKCMU_G3D_BUSD 0x1864
+#define CLK_CON_DIV_CLKCMU_G3D_GLB 0x1868
+#define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x186c
+#define CLK_CON_DIV_CLKCMU_GDC_GDC0 0x1870
+#define CLK_CON_DIV_CLKCMU_GDC_GDC1 0x1874
+#define CLK_CON_DIV_CLKCMU_GDC_SCSC 0x1878
+#define CLK_CON_DIV_CLKCMU_HPM 0x187c
+#define CLK_CON_DIV_CLKCMU_HSI0_BUS 0x1880
+#define CLK_CON_DIV_CLKCMU_HSI0_DPGTC 0x1884
+#define CLK_CON_DIV_CLKCMU_HSI0_USB31DRD 0x1888
+#define CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG 0x188c
+#define CLK_CON_DIV_CLKCMU_HSI1_BUS 0x1890
+#define CLK_CON_DIV_CLKCMU_HSI1_PCIE 0x1894
+#define CLK_CON_DIV_CLKCMU_HSI2_BUS 0x1898
+#define CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD 0x189c
+#define CLK_CON_DIV_CLKCMU_HSI2_PCIE 0x18a0
+#define CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD 0x18a4
+#define CLK_CON_DIV_CLKCMU_IPP_BUS 0x18a8
+#define CLK_CON_DIV_CLKCMU_ITP_BUS 0x18ac
+#define CLK_CON_DIV_CLKCMU_MCSC_ITSC 0x18b0
+#define CLK_CON_DIV_CLKCMU_MCSC_MCSC 0x18b4
+#define CLK_CON_DIV_CLKCMU_MFC_MFC 0x18b8
+#define CLK_CON_DIV_CLKCMU_MIF_BUSP 0x18bc
+#define CLK_CON_DIV_CLKCMU_MISC_BUS 0x18c0
+#define CLK_CON_DIV_CLKCMU_MISC_SSS 0x18c4
+#define CLK_CON_DIV_CLKCMU_OTP 0x18c8
+#define CLK_CON_DIV_CLKCMU_PDP_BUS 0x18cc
+#define CLK_CON_DIV_CLKCMU_PDP_VRA 0x18d0
+#define CLK_CON_DIV_CLKCMU_PERIC0_BUS 0x18d4
+#define CLK_CON_DIV_CLKCMU_PERIC0_IP 0x18d8
+#define CLK_CON_DIV_CLKCMU_PERIC1_BUS 0x18dc
+#define CLK_CON_DIV_CLKCMU_PERIC1_IP 0x18e0
+#define CLK_CON_DIV_CLKCMU_TNR_BUS 0x18e4
+#define CLK_CON_DIV_CLKCMU_TPU_BUS 0x18e8
+#define CLK_CON_DIV_CLKCMU_TPU_TPU 0x18ec
+#define CLK_CON_DIV_CLKCMU_TPU_TPUCTL 0x18f0
+#define CLK_CON_DIV_CLKCMU_TPU_UART 0x18f4
+#define CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST 0x18f8
+#define CLK_CON_DIV_DIV_CLK_CMU_CMUREF 0x18fc
+#define CLK_CON_DIV_PLL_SHARED0_DIV2 0x1900
+#define CLK_CON_DIV_PLL_SHARED0_DIV3 0x1904
+#define CLK_CON_DIV_PLL_SHARED0_DIV4 0x1908
+#define CLK_CON_DIV_PLL_SHARED0_DIV5 0x190c
+#define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1910
+#define CLK_CON_DIV_PLL_SHARED1_DIV3 0x1914
+#define CLK_CON_DIV_PLL_SHARED1_DIV4 0x1918
+#define CLK_CON_DIV_PLL_SHARED2_DIV2 0x191c
+#define CLK_CON_DIV_PLL_SHARED3_DIV2 0x1920
+
+/* CLK_CON_GAT_UPDATES */
+#define CLK_CON_GAT_CLKCMU_BUS0_BOOST 0x2000
+#define CLK_CON_GAT_CLKCMU_BUS1_BOOST 0x2004
+#define CLK_CON_GAT_CLKCMU_BUS2_BOOST 0x2008
+#define CLK_CON_GAT_CLKCMU_CORE_BOOST 0x200c
+#define CLK_CON_GAT_CLKCMU_CPUCL0_BOOST 0x2010
+#define CLK_CON_GAT_CLKCMU_CPUCL1_BOOST 0x2014
+#define CLK_CON_GAT_CLKCMU_CPUCL2_BOOST 0x2018
+#define CLK_CON_GAT_CLKCMU_MIF_BOOST 0x201c
+#define CLK_CON_GAT_CLKCMU_MIF_SWITCH 0x2020
+#define CLK_CON_GAT_GATE_CLKCMU_BO_BUS 0x2024
+#define CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS 0x2028
+#define CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS 0x202c
+#define CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS 0x2030
+#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0 0x2034
+#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1 0x2038
+#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2 0x203c
+#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3 0x2040
+#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4 0x2044
+#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5 0x2048
+#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6 0x204c
+#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7 0x2050
+#define CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST 0x2054
+#define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x2058
+#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS 0x205c
+#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH 0x2060
+#define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH 0x2064
+#define CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH 0x2068
+#define CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS 0x206c
+#define CLK_CON_GAT_GATE_CLKCMU_DISP_BUS 0x2070
+#define CLK_CON_GAT_GATE_CLKCMU_DNS_BUS 0x2074
+#define CLK_CON_GAT_GATE_CLKCMU_DPU_BUS 0x2078
+#define CLK_CON_GAT_GATE_CLKCMU_EH_BUS 0x207c
+#define CLK_CON_GAT_GATE_CLKCMU_G2D_G2D 0x2080
+#define CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL 0x2084
+#define CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA 0x2088
+#define CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD 0x208c
+#define CLK_CON_GAT_GATE_CLKCMU_G3D_GLB 0x2090
+#define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH 0x2094
+#define CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0 0x2098
+#define CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1 0x209c
+#define CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC 0x20a0
+#define CLK_CON_GAT_GATE_CLKCMU_HPM 0x20a4
+#define CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS 0x20a8
+#define CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC 0x20ac
+#define CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD 0x20b0
+#define CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG 0x20b4
+#define CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS 0x20b8
+#define CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE 0x20bc
+#define CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS 0x20c0
+#define CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD 0x20c4
+#define CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE 0x20c8
+#define CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD 0x20cc
+#define CLK_CON_GAT_GATE_CLKCMU_IPP_BUS 0x20d0
+#define CLK_CON_GAT_GATE_CLKCMU_ITP_BUS 0x20d4
+#define CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC 0x20d8
+#define CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC 0x20dc
+#define CLK_CON_GAT_GATE_CLKCMU_MFC_MFC 0x20e0
+#define CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP 0x20e4
+#define CLK_CON_GAT_GATE_CLKCMU_MISC_BUS 0x20e8
+#define CLK_CON_GAT_GATE_CLKCMU_MISC_SSS 0x20ec
+#define CLK_CON_GAT_GATE_CLKCMU_PDP_BUS 0x20f0
+#define CLK_CON_GAT_GATE_CLKCMU_PDP_VRA 0x20f4
+#define CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS 0x20f8
+#define CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP 0x20fc
+#define CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS 0x2100
+#define CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP 0x2104
+#define CLK_CON_GAT_GATE_CLKCMU_TNR_BUS 0x2108
+#define CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF 0x210c
+#define CLK_CON_GAT_GATE_CLKCMU_TPU_BUS 0x2110
+#define CLK_CON_GAT_GATE_CLKCMU_TPU_TPU 0x2114
+#define CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL 0x2118
+#define CLK_CON_GAT_GATE_CLKCMU_TPU_UART 0x211c
+
+#define DMYQCH_CON_CMU_TOP_CMUREF_QCH 0x3000
+#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0 0x3004
+#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1 0x3008
+#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2 0x300c
+#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3 0x3010
+#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4 0x3014
+#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5 0x3018
+#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6 0x301c
+#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7 0x3020
+#define DMYQCH_CON_OTP_QCH 0x3024
+#define QUEUE_CTRL_REG_BLK_CMU_CMU_TOP 0x3c00
+#define QUEUE_ENTRY0_BLK_CMU_CMU_TOP 0x3c10
+#define QUEUE_ENTRY1_BLK_CMU_CMU_TOP 0x3c14
+#define QUEUE_ENTRY2_BLK_CMU_CMU_TOP 0x3c18
+#define QUEUE_ENTRY3_BLK_CMU_CMU_TOP 0x3c1c
+#define QUEUE_ENTRY4_BLK_CMU_CMU_TOP 0x3c20
+#define QUEUE_ENTRY5_BLK_CMU_CMU_TOP 0x3c24
+#define QUEUE_ENTRY6_BLK_CMU_CMU_TOP 0x3c28
+#define QUEUE_ENTRY7_BLK_CMU_CMU_TOP 0x3c2c
+#define MIFMIRROR_QUEUE_CTRL_REG 0x3e00
+#define MIFMIRROR_QUEUE_ENTRY0 0x3e10
+#define MIFMIRROR_QUEUE_ENTRY1 0x3e14
+#define MIFMIRROR_QUEUE_ENTRY2 0x3e18
+#define MIFMIRROR_QUEUE_ENTRY3 0x3e1c
+#define MIFMIRROR_QUEUE_ENTRY4 0x3e20
+#define MIFMIRROR_QUEUE_ENTRY5 0x3e24
+#define MIFMIRROR_QUEUE_ENTRY6 0x3e28
+#define MIFMIRROR_QUEUE_ENTRY7 0x3e2c
+#define MIFMIRROR_QUEUE_BUSY 0x3e30
+#define GENERALIO_ACD_CHANNEL_0 0x3f00
+#define GENERALIO_ACD_CHANNEL_1 0x3f04
+#define GENERALIO_ACD_CHANNEL_2 0x3f08
+#define GENERALIO_ACD_CHANNEL_3 0x3f0c
+#define GENERALIO_ACD_MASK 0x3f14
+
+static const unsigned long cmu_top_clk_regs[] __initconst = {
+ PLL_LOCKTIME_PLL_SHARED0,
+ PLL_LOCKTIME_PLL_SHARED1,
+ PLL_LOCKTIME_PLL_SHARED2,
+ PLL_LOCKTIME_PLL_SHARED3,
+ PLL_LOCKTIME_PLL_SPARE,
+ PLL_CON0_PLL_SHARED0,
+ PLL_CON1_PLL_SHARED0,
+ PLL_CON2_PLL_SHARED0,
+ PLL_CON3_PLL_SHARED0,
+ PLL_CON4_PLL_SHARED0,
+ PLL_CON0_PLL_SHARED1,
+ PLL_CON1_PLL_SHARED1,
+ PLL_CON2_PLL_SHARED1,
+ PLL_CON3_PLL_SHARED1,
+ PLL_CON4_PLL_SHARED1,
+ PLL_CON0_PLL_SHARED2,
+ PLL_CON1_PLL_SHARED2,
+ PLL_CON2_PLL_SHARED2,
+ PLL_CON3_PLL_SHARED2,
+ PLL_CON4_PLL_SHARED2,
+ PLL_CON0_PLL_SHARED3,
+ PLL_CON1_PLL_SHARED3,
+ PLL_CON2_PLL_SHARED3,
+ PLL_CON3_PLL_SHARED3,
+ PLL_CON4_PLL_SHARED3,
+ PLL_CON0_PLL_SPARE,
+ PLL_CON1_PLL_SPARE,
+ PLL_CON2_PLL_SPARE,
+ PLL_CON3_PLL_SPARE,
+ PLL_CON4_PLL_SPARE,
+ CMU_CMU_TOP_CONTROLLER_OPTION,
+ CLKOUT_CON_BLK_CMU_CMU_TOP_CLKOUT0,
+ CMU_HCHGEN_CLKMUX_CMU_BOOST,
+ CMU_HCHGEN_CLKMUX_TOP_BOOST,
+ CMU_HCHGEN_CLKMUX,
+ POWER_FAIL_DETECT_PLL,
+ EARLY_WAKEUP_FORCED_0_ENABLE,
+ EARLY_WAKEUP_FORCED_1_ENABLE,
+ EARLY_WAKEUP_APM_CTRL,
+ EARLY_WAKEUP_CLUSTER0_CTRL,
+ EARLY_WAKEUP_DPU_CTRL,
+ EARLY_WAKEUP_CSIS_CTRL,
+ EARLY_WAKEUP_APM_DEST,
+ EARLY_WAKEUP_CLUSTER0_DEST,
+ EARLY_WAKEUP_DPU_DEST,
+ EARLY_WAKEUP_CSIS_DEST,
+ EARLY_WAKEUP_SW_TRIG_APM,
+ EARLY_WAKEUP_SW_TRIG_APM_SET,
+ EARLY_WAKEUP_SW_TRIG_APM_CLEAR,
+ EARLY_WAKEUP_SW_TRIG_CLUSTER0,
+ EARLY_WAKEUP_SW_TRIG_CLUSTER0_SET,
+ EARLY_WAKEUP_SW_TRIG_CLUSTER0_CLEAR,
+ EARLY_WAKEUP_SW_TRIG_DPU,
+ EARLY_WAKEUP_SW_TRIG_DPU_SET,
+ EARLY_WAKEUP_SW_TRIG_DPU_CLEAR,
+ EARLY_WAKEUP_SW_TRIG_CSIS,
+ EARLY_WAKEUP_SW_TRIG_CSIS_SET,
+ EARLY_WAKEUP_SW_TRIG_CSIS_CLEAR,
+ CLK_CON_MUX_MUX_CLKCMU_BO_BUS,
+ CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS,
+ CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS,
+ CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS,
+ CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0,
+ CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1,
+ CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2,
+ CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3,
+ CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4,
+ CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5,
+ CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6,
+ CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7,
+ CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST,
+ CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1,
+ CLK_CON_MUX_MUX_CLKCMU_CORE_BUS,
+ CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG,
+ CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
+ CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
+ CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH,
+ CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS,
+ CLK_CON_MUX_MUX_CLKCMU_DISP_BUS,
+ CLK_CON_MUX_MUX_CLKCMU_DNS_BUS,
+ CLK_CON_MUX_MUX_CLKCMU_DPU_BUS,
+ CLK_CON_MUX_MUX_CLKCMU_EH_BUS,
+ CLK_CON_MUX_MUX_CLKCMU_G2D_G2D,
+ CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL,
+ CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA,
+ CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD,
+ CLK_CON_MUX_MUX_CLKCMU_G3D_GLB,
+ CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH,
+ CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0,
+ CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1,
+ CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC,
+ CLK_CON_MUX_MUX_CLKCMU_HPM,
+ CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS,
+ CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC,
+ CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD,
+ CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG,
+ CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS,
+ CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE,
+ CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS,
+ CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD,
+ CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE,
+ CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD,
+ CLK_CON_MUX_MUX_CLKCMU_IPP_BUS,
+ CLK_CON_MUX_MUX_CLKCMU_ITP_BUS,
+ CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC,
+ CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC,
+ CLK_CON_MUX_MUX_CLKCMU_MFC_MFC,
+ CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP,
+ CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH,
+ CLK_CON_MUX_MUX_CLKCMU_MISC_BUS,
+ CLK_CON_MUX_MUX_CLKCMU_MISC_SSS,
+ CLK_CON_MUX_MUX_CLKCMU_PDP_BUS,
+ CLK_CON_MUX_MUX_CLKCMU_PDP_VRA,
+ CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS,
+ CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP,
+ CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS,
+ CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP,
+ CLK_CON_MUX_MUX_CLKCMU_TNR_BUS,
+ CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1,
+ CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF,
+ CLK_CON_MUX_MUX_CLKCMU_TPU_BUS,
+ CLK_CON_MUX_MUX_CLKCMU_TPU_TPU,
+ CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL,
+ CLK_CON_MUX_MUX_CLKCMU_TPU_UART,
+ CLK_CON_MUX_MUX_CMU_CMUREF,
+ CLK_CON_DIV_CLKCMU_BO_BUS,
+ CLK_CON_DIV_CLKCMU_BUS0_BUS,
+ CLK_CON_DIV_CLKCMU_BUS1_BUS,
+ CLK_CON_DIV_CLKCMU_BUS2_BUS,
+ CLK_CON_DIV_CLKCMU_CIS_CLK0,
+ CLK_CON_DIV_CLKCMU_CIS_CLK1,
+ CLK_CON_DIV_CLKCMU_CIS_CLK2,
+ CLK_CON_DIV_CLKCMU_CIS_CLK3,
+ CLK_CON_DIV_CLKCMU_CIS_CLK4,
+ CLK_CON_DIV_CLKCMU_CIS_CLK5,
+ CLK_CON_DIV_CLKCMU_CIS_CLK6,
+ CLK_CON_DIV_CLKCMU_CIS_CLK7,
+ CLK_CON_DIV_CLKCMU_CORE_BUS,
+ CLK_CON_DIV_CLKCMU_CPUCL0_DBG,
+ CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH,
+ CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH,
+ CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH,
+ CLK_CON_DIV_CLKCMU_CSIS_BUS,
+ CLK_CON_DIV_CLKCMU_DISP_BUS,
+ CLK_CON_DIV_CLKCMU_DNS_BUS,
+ CLK_CON_DIV_CLKCMU_DPU_BUS,
+ CLK_CON_DIV_CLKCMU_EH_BUS,
+ CLK_CON_DIV_CLKCMU_G2D_G2D,
+ CLK_CON_DIV_CLKCMU_G2D_MSCL,
+ CLK_CON_DIV_CLKCMU_G3AA_G3AA,
+ CLK_CON_DIV_CLKCMU_G3D_BUSD,
+ CLK_CON_DIV_CLKCMU_G3D_GLB,
+ CLK_CON_DIV_CLKCMU_G3D_SWITCH,
+ CLK_CON_DIV_CLKCMU_GDC_GDC0,
+ CLK_CON_DIV_CLKCMU_GDC_GDC1,
+ CLK_CON_DIV_CLKCMU_GDC_SCSC,
+ CLK_CON_DIV_CLKCMU_HPM,
+ CLK_CON_DIV_CLKCMU_HSI0_BUS,
+ CLK_CON_DIV_CLKCMU_HSI0_DPGTC,
+ CLK_CON_DIV_CLKCMU_HSI0_USB31DRD,
+ CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG,
+ CLK_CON_DIV_CLKCMU_HSI1_BUS,
+ CLK_CON_DIV_CLKCMU_HSI1_PCIE,
+ CLK_CON_DIV_CLKCMU_HSI2_BUS,
+ CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD,
+ CLK_CON_DIV_CLKCMU_HSI2_PCIE,
+ CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD,
+ CLK_CON_DIV_CLKCMU_IPP_BUS,
+ CLK_CON_DIV_CLKCMU_ITP_BUS,
+ CLK_CON_DIV_CLKCMU_MCSC_ITSC,
+ CLK_CON_DIV_CLKCMU_MCSC_MCSC,
+ CLK_CON_DIV_CLKCMU_MFC_MFC,
+ CLK_CON_DIV_CLKCMU_MIF_BUSP,
+ CLK_CON_DIV_CLKCMU_MISC_BUS,
+ CLK_CON_DIV_CLKCMU_MISC_SSS,
+ CLK_CON_DIV_CLKCMU_OTP,
+ CLK_CON_DIV_CLKCMU_PDP_BUS,
+ CLK_CON_DIV_CLKCMU_PDP_VRA,
+ CLK_CON_DIV_CLKCMU_PERIC0_BUS,
+ CLK_CON_DIV_CLKCMU_PERIC0_IP,
+ CLK_CON_DIV_CLKCMU_PERIC1_BUS,
+ CLK_CON_DIV_CLKCMU_PERIC1_IP,
+ CLK_CON_DIV_CLKCMU_TNR_BUS,
+ CLK_CON_DIV_CLKCMU_TPU_BUS,
+ CLK_CON_DIV_CLKCMU_TPU_TPU,
+ CLK_CON_DIV_CLKCMU_TPU_TPUCTL,
+ CLK_CON_DIV_CLKCMU_TPU_UART,
+ CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST,
+ CLK_CON_DIV_DIV_CLK_CMU_CMUREF,
+ CLK_CON_DIV_PLL_SHARED0_DIV2,
+ CLK_CON_DIV_PLL_SHARED0_DIV3,
+ CLK_CON_DIV_PLL_SHARED0_DIV4,
+ CLK_CON_DIV_PLL_SHARED0_DIV5,
+ CLK_CON_DIV_PLL_SHARED1_DIV2,
+ CLK_CON_DIV_PLL_SHARED1_DIV3,
+ CLK_CON_DIV_PLL_SHARED1_DIV4,
+ CLK_CON_DIV_PLL_SHARED2_DIV2,
+ CLK_CON_DIV_PLL_SHARED3_DIV2,
+ CLK_CON_GAT_CLKCMU_BUS0_BOOST,
+ CLK_CON_GAT_CLKCMU_BUS1_BOOST,
+ CLK_CON_GAT_CLKCMU_BUS2_BOOST,
+ CLK_CON_GAT_CLKCMU_CORE_BOOST,
+ CLK_CON_GAT_CLKCMU_CPUCL0_BOOST,
+ CLK_CON_GAT_CLKCMU_CPUCL1_BOOST,
+ CLK_CON_GAT_CLKCMU_CPUCL2_BOOST,
+ CLK_CON_GAT_CLKCMU_MIF_BOOST,
+ CLK_CON_GAT_CLKCMU_MIF_SWITCH,
+ CLK_CON_GAT_GATE_CLKCMU_BO_BUS,
+ CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS,
+ CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS,
+ CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS,
+ CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0,
+ CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1,
+ CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2,
+ CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3,
+ CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4,
+ CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5,
+ CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6,
+ CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7,
+ CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST,
+ CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
+ CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS,
+ CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH,
+ CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH,
+ CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH,
+ CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS,
+ CLK_CON_GAT_GATE_CLKCMU_DISP_BUS,
+ CLK_CON_GAT_GATE_CLKCMU_DNS_BUS,
+ CLK_CON_GAT_GATE_CLKCMU_DPU_BUS,
+ CLK_CON_GAT_GATE_CLKCMU_EH_BUS,
+ CLK_CON_GAT_GATE_CLKCMU_G2D_G2D,
+ CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL,
+ CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA,
+ CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD,
+ CLK_CON_GAT_GATE_CLKCMU_G3D_GLB,
+ CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH,
+ CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0,
+ CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1,
+ CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC,
+ CLK_CON_GAT_GATE_CLKCMU_HPM,
+ CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS,
+ CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC,
+ CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD,
+ CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG,
+ CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS,
+ CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE,
+ CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS,
+ CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD,
+ CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE,
+ CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD,
+ CLK_CON_GAT_GATE_CLKCMU_IPP_BUS,
+ CLK_CON_GAT_GATE_CLKCMU_ITP_BUS,
+ CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC,
+ CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC,
+ CLK_CON_GAT_GATE_CLKCMU_MFC_MFC,
+ CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP,
+ CLK_CON_GAT_GATE_CLKCMU_MISC_BUS,
+ CLK_CON_GAT_GATE_CLKCMU_MISC_SSS,
+ CLK_CON_GAT_GATE_CLKCMU_PDP_BUS,
+ CLK_CON_GAT_GATE_CLKCMU_PDP_VRA,
+ CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS,
+ CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP,
+ CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS,
+ CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP,
+ CLK_CON_GAT_GATE_CLKCMU_TNR_BUS,
+ CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF,
+ CLK_CON_GAT_GATE_CLKCMU_TPU_BUS,
+ CLK_CON_GAT_GATE_CLKCMU_TPU_TPU,
+ CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL,
+ CLK_CON_GAT_GATE_CLKCMU_TPU_UART,
+ DMYQCH_CON_CMU_TOP_CMUREF_QCH,
+ DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0,
+ DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1,
+ DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2,
+ DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3,
+ DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4,
+ DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5,
+ DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6,
+ DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7,
+ DMYQCH_CON_OTP_QCH,
+ QUEUE_CTRL_REG_BLK_CMU_CMU_TOP,
+ QUEUE_ENTRY0_BLK_CMU_CMU_TOP,
+ QUEUE_ENTRY1_BLK_CMU_CMU_TOP,
+ QUEUE_ENTRY2_BLK_CMU_CMU_TOP,
+ QUEUE_ENTRY3_BLK_CMU_CMU_TOP,
+ QUEUE_ENTRY4_BLK_CMU_CMU_TOP,
+ QUEUE_ENTRY5_BLK_CMU_CMU_TOP,
+ QUEUE_ENTRY6_BLK_CMU_CMU_TOP,
+ QUEUE_ENTRY7_BLK_CMU_CMU_TOP,
+ MIFMIRROR_QUEUE_CTRL_REG,
+ MIFMIRROR_QUEUE_ENTRY0,
+ MIFMIRROR_QUEUE_ENTRY1,
+ MIFMIRROR_QUEUE_ENTRY2,
+ MIFMIRROR_QUEUE_ENTRY3,
+ MIFMIRROR_QUEUE_ENTRY4,
+ MIFMIRROR_QUEUE_ENTRY5,
+ MIFMIRROR_QUEUE_ENTRY6,
+ MIFMIRROR_QUEUE_ENTRY7,
+ MIFMIRROR_QUEUE_BUSY,
+ GENERALIO_ACD_CHANNEL_0,
+ GENERALIO_ACD_CHANNEL_1,
+ GENERALIO_ACD_CHANNEL_2,
+ GENERALIO_ACD_CHANNEL_3,
+ GENERALIO_ACD_MASK,
+};
+
+static const struct samsung_pll_clock cmu_top_pll_clks[] __initconst = {
+ /* CMU_TOP_PURECLKCOMP */
+ PLL(pll_0517x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
+ PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0,
+ NULL),
+ PLL(pll_0517x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
+ PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1,
+ NULL),
+ PLL(pll_0518x, CLK_FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk",
+ PLL_LOCKTIME_PLL_SHARED2, PLL_CON3_PLL_SHARED2,
+ NULL),
+ PLL(pll_0518x, CLK_FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk",
+ PLL_LOCKTIME_PLL_SHARED3, PLL_CON3_PLL_SHARED3,
+ NULL),
+ PLL(pll_0518x, CLK_FOUT_SPARE_PLL, "fout_spare_pll", "oscclk",
+ PLL_LOCKTIME_PLL_SPARE, PLL_CON3_PLL_SPARE,
+ NULL),
+};
+
+/* List of parent clocks for Muxes in CMU_TOP */
+PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" };
+PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" };
+PNAME(mout_shared2_pll_p) = { "oscclk", "fout_shared2_pll" };
+PNAME(mout_shared3_pll_p) = { "oscclk", "fout_shared3_pll" };
+PNAME(mout_spare_pll_p) = { "oscclk", "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_BUS0 */
+PNAME(mout_cmu_bus0_bus_p) = { "dout_shared0_div4", "dout_shared1_div4",
+ "dout_shared2_div2", "dout_shared3_div2",
+ "fout_spare_pll" };
+
+PNAME(mout_cmu_cmu_boost_p) = { "dout_shared0_div4", "dout_shared1_div4",
+ "dout_shared2_div2", "dout_shared3_div2" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_BUS1 */
+PNAME(mout_cmu_bus1_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
+ "dout_shared1_div3", "dout_shared0_div4",
+ "dout_shared1_div4", "dout_shared2_div2",
+ "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_BUS2 */
+PNAME(mout_cmu_bus2_bus_p) = { "dout_shared0_div2", "dout_shared1_div2",
+ "fout_shared2_pll", "fout_shared3_pll",
+ "dout_shared0_div3", "dout_shared1_div3",
+ "dout_shared0_div5", "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */
+PNAME(mout_cmu_core_bus_p) = { "dout_shared0_div2", "dout_shared1_div2",
+ "fout_shared2_pll", "fout_shared3_pll",
+ "dout_shared0_div3", "dout_shared1_div3",
+ "dout_shared0_div5", "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_EH */
+PNAME(mout_cmu_eh_bus_p) = { "dout_shared0_div2", "dout_shared1_div2",
+ "fout_shared2_pll", "fout_shared3_pll",
+ "dout_shared0_div3", "dout_shared1_div3",
+ "dout_shared0_div5", "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_CPUCL2 */
+PNAME(mout_cmu_cpucl2_switch_p) = { "fout_shared1_pll", "dout_shared0_div2",
+ "dout_shared1_div2", "fout_shared2_pll",
+ "fout_shared3_pll", "dout_shared0_div3",
+ "dout_shared1_div3", "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_CPUCL1 */
+PNAME(mout_cmu_cpucl1_switch_p) = { "fout_shared1_pll", "dout_shared0_div2",
+ "dout_shared1_div2", "fout_shared2_pll",
+ "fout_shared3_pll", "dout_shared0_div3",
+ "dout_shared1_div3", "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_CPUCL0 */
+PNAME(mout_cmu_cpucl0_switch_p) = { "fout_shared1_pll", "dout_shared0_div2",
+ "dout_shared1_div2", "fout_shared2_pll",
+ "fout_shared3_pll", "dout_shared0_div3",
+ "dout_shared1_div3", "fout_spare_pll" };
+
+PNAME(mout_cmu_cpucl0_dbg_p) = { "fout_shared2_pll", "fout_shared3_pll",
+ "dout_shared0_div4", "dout_shared1_div4",
+ "dout_shared2_div2", "fout_spare_pll" };
+
+PNAME(mout_cmu_hpm_p) = { "oscclk", "dout_shared1_div3",
+ "dout_shared0_div4", "dout_shared2_div2" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_G3D */
+PNAME(mout_cmu_g3d_switch_p) = { "fout_shared2_pll", "dout_shared0_div3",
+ "fout_shared3_pll", "dout_shared1_div3",
+ "dout_shared0_div4", "dout_shared1_div4",
+ "fout_spare_pll" };
+
+PNAME(mout_cmu_g3d_busd_p) = { "dout_shared0_div2", "dout_shared1_div2",
+ "fout_shared2_pll", "fout_shared3_pll",
+ "dout_shared0_div3", "dout_shared1_div3",
+ "dout_shared0_div4", "fout_spare_pll" };
+
+PNAME(mout_cmu_g3d_glb_p) = { "dout_shared0_div2", "dout_shared1_div2",
+ "fout_shared2_pll", "fout_shared3_pll",
+ "dout_shared0_div3", "dout_shared1_div3",
+ "dout_shared0_div4", "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_DPU */
+PNAME(mout_cmu_dpu_p) = { "dout_shared0_div3", "fout_shared3_pll",
+ "dout_shared1_div3", "dout_shared0_div4",
+ "dout_shared1_div4", "dout_shared2_div2",
+ "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_DISP */
+PNAME(mout_cmu_disp_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
+ "dout_shared1_div3", "dout_shared0_div4",
+ "dout_shared1_div4", "dout_shared2_div2",
+ "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_G2D */
+PNAME(mout_cmu_g2d_g2d_p) = { "dout_shared0_div3", "fout_shared3_pll",
+ "dout_shared1_div3", "dout_shared0_div4",
+ "dout_shared1_div4", "dout_shared2_div2",
+ "fout_spare_pll" };
+
+PNAME(mout_cmu_g2d_mscl_p) = { "dout_shared0_div4", "dout_shared1_div4",
+ "dout_shared2_div2", "dout_shared3_div2",
+ "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI0 */
+PNAME(mout_cmu_hsi0_usb31drd_p) = { "oscclk", "dout_shared2_div2" };
+
+PNAME(mout_cmu_hsi0_bus_p) = { "dout_shared0_div4", "dout_shared1_div4",
+ "dout_shared2_div2", "dout_shared3_div2",
+ "fout_spare_pll" };
+
+PNAME(mout_cmu_hsi0_dpgtc_p) = { "oscclk", "dout_shared0_div4",
+ "dout_shared2_div2", "fout_spare_pll" };
+
+PNAME(mout_cmu_hsi0_usbdpdbg_p) = { "oscclk", "dout_shared2_div2" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI1 */
+PNAME(mout_cmu_hsi1_bus_p) = { "dout_shared0_div4", "dout_shared1_div4",
+ "dout_shared2_div2", "dout_shared3_div2",
+ "fout_spare_pll" };
+
+PNAME(mout_cmu_hsi1_pcie_p) = { "oscclk", "dout_shared2_div2" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI2 */
+PNAME(mout_cmu_hsi2_bus_p) = { "dout_shared0_div4", "dout_shared1_div4",
+ "dout_shared2_div2", "dout_shared3_div2",
+ "fout_spare_pll" };
+
+PNAME(mout_cmu_hsi2_pcie0_p) = { "oscclk", "dout_shared2_div2" };
+
+PNAME(mout_cmu_hsi2_ufs_embd_p) = { "oscclk", "dout_shared0_div4",
+ "dout_shared2_div2", "fout_spare_pll" };
+
+PNAME(mout_cmu_hsi2_mmc_card_p) = { "fout_shared2_pll", "fout_shared3_pll",
+ "dout_shared0_div4", "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_CSIS */
+PNAME(mout_cmu_csis_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
+ "dout_shared1_div3", "dout_shared0_div4",
+ "dout_shared1_div4", "dout_shared2_div2",
+ "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_PDP */
+PNAME(mout_cmu_pdp_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
+ "dout_shared1_div3", "dout_shared0_div4",
+ "dout_shared1_div4", "dout_shared2_div2",
+ "fout_spare_pll" };
+
+PNAME(mout_cmu_pdp_vra_p) = { "fout_shared2_pll", "dout_shared0_div3",
+ "fout_shared3_pll", "dout_shared1_div3",
+ "dout_shared0_div4", "dout_shared1_div4",
+ "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_IPP */
+PNAME(mout_cmu_ipp_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
+ "dout_shared1_div3", "dout_shared0_div4",
+ "dout_shared1_div4", "dout_shared2_div2",
+ "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_G3AA */
+PNAME(mout_cmu_g3aa_p) = { "dout_shared0_div3", "fout_shared3_pll",
+ "dout_shared1_div3", "dout_shared0_div4",
+ "dout_shared1_div4", "dout_shared2_div2",
+ "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_ITP */
+PNAME(mout_cmu_itp_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
+ "dout_shared1_div3", "dout_shared0_div4",
+ "dout_shared1_div4", "dout_shared2_div2",
+ "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_DNS */
+PNAME(mout_cmu_dns_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
+ "dout_shared1_div3", "dout_shared0_div4",
+ "dout_shared1_div4", "dout_shared2_div2",
+ "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_TNR */
+PNAME(mout_cmu_tnr_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
+ "dout_shared1_div3", "dout_shared0_div4",
+ "dout_shared1_div4", "dout_shared2_div2",
+ "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_MCSC */
+PNAME(mout_cmu_mcsc_itsc_p) = { "dout_shared0_div3", "fout_shared3_pll",
+ "dout_shared1_div3", "dout_shared0_div4",
+ "dout_shared1_div4", "dout_shared2_div2",
+ "fout_spare_pll" };
+
+PNAME(mout_cmu_mcsc_mcsc_p) = { "dout_shared0_div3", "fout_shared3_pll",
+ "dout_shared1_div3", "dout_shared0_div4",
+ "dout_shared1_div4", "dout_shared2_div2",
+ "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_GDC */
+PNAME(mout_cmu_gdc_scsc_p) = { "dout_shared0_div3", "fout_shared3_pll",
+ "dout_shared1_div3", "dout_shared0_div4",
+ "dout_shared1_div4", "dout_shared2_div2",
+ "fout_spare_pll" };
+
+PNAME(mout_cmu_gdc_gdc0_p) = { "dout_shared0_div3", "fout_shared3_pll",
+ "dout_shared1_div3", "dout_shared0_div4",
+ "dout_shared1_div4", "dout_shared2_div2",
+ "fout_spare_pll" };
+
+PNAME(mout_cmu_gdc_gdc1_p) = { "dout_shared0_div3", "fout_shared3_pll",
+ "dout_shared1_div3", "dout_shared0_div4",
+ "dout_shared1_div4", "dout_shared2_div2",
+ "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_MFC */
+PNAME(mout_cmu_mfc_mfc_p) = { "dout_shared0_div3", "fout_shared3_pll",
+ "dout_shared1_div3", "dout_shared0_div4",
+ "dout_shared1_div4", "dout_shared2_div2",
+ "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for DDRPHY0/1/2/3 */
+
+PNAME(mout_cmu_mif_switch_p) = { "fout_shared0_pll", "fout_shared1_pll",
+ "dout_shared0_div2", "dout_shared1_div2",
+ "fout_shared2_pll", "dout_shared0_div3",
+ "fout_shared3_pll", "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_MIF0/1/2/3 */
+PNAME(mout_cmu_mif_busp_p) = { "dout_shared0_div4", "dout_shared1_div4",
+ "dout_shared0_div5", "fout_spare_pll" };
+
+PNAME(mout_cmu_boost_p) = { "dout_shared0_div4", "dout_shared1_div4",
+ "dout_shared2_div2", "dout_shared3_div2" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_MISC */
+PNAME(mout_cmu_misc_bus_p) = { "dout_shared0_div4", "dout_shared2_div2",
+ "dout_shared3_div2", "fout_spare_pll" };
+PNAME(mout_cmu_misc_sss_p) = { "dout_shared0_div4", "dout_shared2_div2",
+ "dout_shared3_div2", "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_PERIC0 */
+PNAME(mout_cmu_peric0_bus_p) = { "dout_shared0_div4", "dout_shared2_div2",
+ "dout_shared3_div2", "fout_spare_pll" };
+PNAME(mout_cmu_peric0_ip_p) = { "dout_shared0_div4", "dout_shared2_div2",
+ "dout_shared3_div2", "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_PERIC1 */
+PNAME(mout_cmu_peric1_bus_p) = { "dout_shared0_div4", "dout_shared2_div2",
+ "dout_shared3_div2", "fout_spare_pll" };
+PNAME(mout_cmu_peric1_ip_p) = { "dout_shared0_div4", "dout_shared2_div2",
+ "dout_shared3_div2", "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_TPU */
+PNAME(mout_cmu_tpu_tpu_p) = { "dout_shared0_div2", "dout_shared1_div2",
+ "fout_shared2_pll", "fout_shared3_pll",
+ "dout_shared0_div3", "dout_shared1_div3",
+ "dout_shared0_div4", "fout_spare_pll" };
+
+PNAME(mout_cmu_tpu_tpuctl_p) = { "dout_shared0_div2", "dout_shared1_div2",
+ "fout_shared2_pll", "fout_shared3_pll",
+ "dout_shared0_div3", "dout_shared1_div3",
+ "dout_shared0_div4", "fout_spare_pll" };
+
+PNAME(mout_cmu_tpu_bus_p) = { "dout_shared0_div2", "dout_shared1_div2",
+ "fout_shared2_pll", "fout_shared3_pll",
+ "dout_shared0_div3", "dout_shared1_div3",
+ "dout_shared0_div4", "fout_spare_pll" };
+
+PNAME(mout_cmu_tpu_uart_p) = { "dout_shared0_div4", "dout_shared2_div2",
+ "dout_shared3_div2", "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_BO */
+PNAME(mout_cmu_bo_bus_p) = { "fout_shared2_pll", "dout_shared0_div3",
+ "fout_shared3_pll", "dout_shared1_div3",
+ "dout_shared0_div4", "dout_shared1_div4",
+ "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_G2D */
+PNAME(mout_cmu_g2d_p) = { "dout_shared0_div3", "fout_shared3_pll",
+ "dout_shared1_div3", "dout_shared0_div4",
+ "dout_shared1_div4", "dout_shared2_div2",
+ "fout_spare_pll" };
+
+/* gs101 */
+static const struct samsung_mux_clock cmu_top_mux_clks[] __initconst = {
+ /* CMU_TOP_PURECLKCOMP */
+ MUX(CLK_MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p,
+ PLL_CON0_PLL_SHARED0, 4, 1),
+ MUX(CLK_MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p,
+ PLL_CON0_PLL_SHARED1, 4, 1),
+ MUX(CLK_MOUT_SHARED2_PLL, "mout_shared2_pll", mout_shared2_pll_p,
+ PLL_CON0_PLL_SHARED2, 4, 1),
+ MUX(CLK_MOUT_SHARED3_PLL, "mout_shared3_pll", mout_shared3_pll_p,
+ PLL_CON0_PLL_SHARED3, 4, 1),
+ MUX(CLK_MOUT_SPARE_PLL, "mout_spare_pll", mout_spare_pll_p,
+ PLL_CON0_PLL_SPARE, 4, 1),
+
+ /* BUS0 */
+ MUX(CLK_MOUT_BUS0_BUS, "mout_cmu_bus0_bus", mout_cmu_bus0_bus_p,
+ CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS, 0, 2),
+ MUX(CLK_MOUT_CMU_BOOST, "mout_cmu_boost", mout_cmu_cmu_boost_p,
+ CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0, 2),
+
+ /* BUS1 */
+ MUX(CLK_MOUT_BUS1_BUS, "mout_cmu_bus1_bus", mout_cmu_bus1_bus_p,
+ CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS, 0, 2),
+
+ /* BUS2 */
+ MUX(CLK_MOUT_BUS2_BUS, "mout_cmu_bus2_bus", mout_cmu_bus2_bus_p,
+ CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS, 0, 2),
+
+ /* CORE */
+ MUX(CLK_MOUT_CORE_BUS, "mout_cmu_core_bus", mout_cmu_core_bus_p,
+ CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
+
+ /* EH */
+ MUX(CLK_MOUT_EH_BUS, "mout_cmu_eh_bus", mout_cmu_eh_bus_p,
+ CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
+
+ /* CPUCL{0,1,2,} */
+ MUX(CLK_MOUT_CPUCL2_SWITCH, "mout_cmu_cpucl2_switch", mout_cmu_cpucl2_switch_p,
+ CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH, 0, 2),
+
+ MUX(CLK_MOUT_CPUCL1_SWITCH, "mout_cmu_cpucl1_switch", mout_cmu_cpucl1_switch_p,
+ CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, 0, 2),
+
+ MUX(CLK_MOUT_CPUCL0_SWITCH, "mout_cmu_cpucl0_switch", mout_cmu_cpucl0_switch_p,
+ CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, 0, 2),
+
+ MUX(CLK_MOUT_CPUCL0_DBG, "mout_cmu_cpucl0_dbg", mout_cmu_cpucl0_dbg_p,
+ CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 2),
+
+ MUX(CLK_MOUT_CMU_HPM, "mout_cmu_hpm", mout_cmu_hpm_p,
+ CLK_CON_MUX_MUX_CLKCMU_HPM, 0, 2),
+
+ /* G3D */
+ MUX(CLK_MOUT_G3D_SWITCH, "mout_cmu_g3d_switch", mout_cmu_g3d_switch_p,
+ CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0, 2),
+
+ MUX(CLK_MOUT_G3D_BUSD, "mout_cmu_g3d_busd", mout_cmu_g3d_busd_p,
+ CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD, 0, 2),
+
+ MUX(CLK_MOUT_G3D_GLB, "mout_cmu_g3d_glb", mout_cmu_g3d_glb_p,
+ CLK_CON_MUX_MUX_CLKCMU_G3D_GLB, 0, 2),
+ /* DPU */
+ MUX(CLK_MOUT_DPU_BUS, "mout_cmu_dpu_bus", mout_cmu_dpu_p,
+ CLK_CON_MUX_MUX_CLKCMU_DPU_BUS, 0, 2),
+
+ /* DISP */
+ MUX(CLK_MOUT_DISP_BUS, "mout_cmu_disp_bus", mout_cmu_disp_bus_p,
+ CLK_CON_MUX_MUX_CLKCMU_DISP_BUS, 0, 2),
+
+ /* G2D */
+ MUX(CLK_MOUT_G2D_G2D, "mout_cmu_g2d_g2d", mout_cmu_g2d_g2d_p,
+ CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 0, 2),
+
+ MUX(CLK_MOUT_G2D_MSCL, "mout_cmu_g2d_mscl", mout_cmu_g2d_mscl_p,
+ CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0, 2),
+
+ /* HSI0 */
+ MUX(CLK_MOUT_HSI0_USB31DRD, "mout_cmu_hsi0_usb31drd", mout_cmu_hsi0_usb31drd_p,
+ CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD, 0, 2),
+
+ MUX(CLK_MOUT_HSI0_BUS, "mout_cmu_hsi0_bus", mout_cmu_hsi0_bus_p,
+ CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS, 0, 2),
+
+ MUX(CLK_MOUT_HSI0_DPGTC, "mout_cmu_hsi0_dpgtc", mout_cmu_hsi0_dpgtc_p,
+ CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC, 0, 2),
+
+ MUX(CLK_MOUT_HSI0_USBDPDGB, "mout_cmu_hsi0_usbdpdbg", mout_cmu_hsi0_usbdpdbg_p,
+ CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG, 0, 2),
+
+ /* HSI1 */
+ MUX(CLK_MOUT_HSI1_BUS, "mout_cmu_hsi1_bus", mout_cmu_hsi1_bus_p,
+ CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS, 0, 2),
+
+ MUX(CLK_MOUT_HSI1_PCIE, "mout_cmu_hsi1_pcie", mout_cmu_hsi1_pcie_p,
+ CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE, 0, 2),
+ /* HSI2 */
+ MUX(CLK_MOUT_HSI2_BUS, "mout_cmu_hsi2_bus", mout_cmu_hsi2_bus_p,
+ CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS, 0, 2),
+
+ MUX(CLK_MOUT_HSI2_PCIE, "mout_cmu_hsi2_pcie", mout_cmu_hsi2_pcie0_p,
+ CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE, 0, 2),
+
+ MUX(CLK_MOUT_HSI2_UFS_EMBD, "mout_cmu_hsi2_ufs_embd", mout_cmu_hsi2_ufs_embd_p,
+ CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD, 0, 2),
+
+ MUX(CLK_MOUT_HSI2_MMC_CARD, "mout_cmu_hsi2_mmc_card", mout_cmu_hsi2_mmc_card_p,
+ CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD, 0, 2),
+
+ /* CSIS */
+ MUX(CLK_MOUT_CSIS, "mout_cmu_csis_bus", mout_cmu_csis_bus_p,
+ CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS, 0, 2),
+
+ /* PDP */
+ MUX(CLK_MOUT_PDP_BUS, "mout_cmu_pdp_bus", mout_cmu_pdp_bus_p,
+ CLK_CON_MUX_MUX_CLKCMU_PDP_BUS, 0, 2),
+
+ /* IPP */
+ MUX(CLK_MOUT_IPP_BUS, "mout_cmu_ipp_bus", mout_cmu_ipp_bus_p,
+ CLK_CON_MUX_MUX_CLKCMU_IPP_BUS, 0, 2),
+
+ /* G3AA */
+ MUX(CLK_MOUT_G3AA, "mout_cmu_g3aa", mout_cmu_g3aa_p,
+ CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 0, 2),
+
+ /* ITP */
+ MUX(CLK_MOUT_ITP, "mout_cmu_itp_bus", mout_cmu_itp_bus_p,
+ CLK_CON_MUX_MUX_CLKCMU_ITP_BUS, 0, 2),
+
+ /* DNS */
+ MUX(CLK_MOUT_DNS_BUS, "mout_cmu_dns_bus", mout_cmu_dns_bus_p,
+ CLK_CON_MUX_MUX_CLKCMU_DNS_BUS, 0, 2),
+
+ /* TNR */
+ MUX(CLK_MOUT_TNR_BUS, "mout_cmu_tnr_bus", mout_cmu_tnr_bus_p,
+ CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, 0, 2),
+
+ /* MCSC*/
+ MUX(CLK_MOUT_MCSC_ITSC, "mout_cmu_mcsc_itsc", mout_cmu_mcsc_itsc_p,
+ CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC, 0, 2),
+
+ MUX(CLK_MOUT_MCSC_MCSC, "mout_cmu_mcsc_mcsc", mout_cmu_mcsc_mcsc_p,
+ CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC, 0, 2),
+
+ /* GDC */
+ MUX(CLK_MOUT_GDC_SCSC, "mout_cmu_gdc_scsc", mout_cmu_gdc_scsc_p,
+ CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC, 0, 2),
+
+ MUX(CLK_MOUT_GDC_GDC0, "mout_cmu_gdc_gdc0", mout_cmu_gdc_gdc0_p,
+ CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0, 0, 2),
+
+ MUX(CLK_MOUT_GDC_GDC1, "mout_cmu_gdc_gdc1", mout_cmu_gdc_gdc1_p,
+ CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1, 0, 2),
+
+ /* MFC */
+ MUX(CLK_MOUT_MFC_MFC, "mout_cmu_mfc_mfc", mout_cmu_mfc_mfc_p,
+ CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 0, 2),
+
+ /* DDRPHY0/1/2/3 */
+ MUX(CLK_MOUT_MIF_SWITCH, "mout_cmu_mif_switch", mout_cmu_mif_switch_p,
+ CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0, 2),
+
+ /* MIF0/1/2/3 */
+ MUX(CLK_MOUT_MIF_BUS, "mout_cmu_mif_busp", mout_cmu_mif_busp_p,
+ CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, 0, 2),
+
+ /* MISC */
+ MUX(CLK_MOUT_MISC_BUS, "mout_cmu_misc_bus", mout_cmu_misc_bus_p,
+ CLK_CON_MUX_MUX_CLKCMU_MISC_BUS, 0, 2),
+ MUX(CLK_MOUT_MISC_SSS, "mout_cmu_misc_sss", mout_cmu_misc_sss_p,
+ CLK_CON_MUX_MUX_CLKCMU_MISC_SSS, 0, 2),
+
+ /* PERI0 */
+ MUX(CLK_MOUT_PERIC0_IP, "mout_cmu_peric0_ip", mout_cmu_peric0_ip_p,
+ CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 2),
+ MUX(CLK_MOUT_PERIC0_BUS, "mout_cmu_peric0_bus", mout_cmu_peric0_bus_p,
+ CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0, 2),
+ /* PERI1 */
+ MUX(CLK_MOUT_PERIC1_IP, "mout_cmu_peric1_ip", mout_cmu_peric1_ip_p,
+ CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 2),
+ MUX(CLK_MOUT_PERIC1_BUS, "mout_cmu_peric1_bus", mout_cmu_peric1_bus_p,
+ CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0, 2),
+
+ /* TPU */
+ MUX(CLK_MOUT_TPU_TPU, "mout_cmu_tpu_tpu", mout_cmu_tpu_tpu_p,
+ CLK_CON_MUX_MUX_CLKCMU_TPU_TPU, 0, 2),
+
+ MUX(CLK_MOUT_TPU_TPUCTL, "mout_cmu_tpu_tpuctl", mout_cmu_tpu_tpuctl_p,
+ CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL, 0, 2),
+
+ MUX(CLK_MOUT_TPU_BUS, "mout_cmu_tpu_bus", mout_cmu_tpu_bus_p,
+ CLK_CON_MUX_MUX_CLKCMU_TPU_BUS, 0, 2),
+
+ MUX(CLK_MOUT_TPU_UART, "mout_cmu_tpu_uart", mout_cmu_tpu_uart_p,
+ CLK_CON_MUX_MUX_CLKCMU_TPU_UART, 0, 2),
+
+ /* BO */
+ MUX(CLK_MOUT_BO_BUS, "mout_cmu_bo_bus", mout_cmu_bo_bus_p,
+ CLK_CON_MUX_MUX_CLKCMU_BO_BUS, 0, 2),
+};
+
+static const struct samsung_div_clock cmu_top_div_clks[] __initconst = {
+ /* CMU_TOP_PURECLKCOMP */
+ DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "mout_shared0_pll",
+ CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
+ DIV(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2", "mout_shared0_pll",
+ CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
+ DIV(CLK_DOUT_SHARED0_DIV5, "dout_shared0_div5", "mout_shared0_pll",
+ CLK_CON_DIV_PLL_SHARED0_DIV5, 0, 2),
+ DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "dout_shared0_div2",
+ CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
+
+ DIV(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2", "mout_shared1_pll",
+ CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
+ DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "mout_shared1_pll",
+ CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
+ DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "mout_shared1_pll",
+ CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
+
+ DIV(CLK_DOUT_SHARED2_DIV2, "dout_shared2_div2", "mout_shared2_pll",
+ CLK_CON_DIV_PLL_SHARED2_DIV2, 0, 1),
+
+ DIV(CLK_DOUT_SHARED3_DIV2, "dout_shared3_div2", "mout_shared3_pll",
+ CLK_CON_DIV_PLL_SHARED3_DIV2, 0, 1),
+
+ /* BUS0 */
+ DIV(CLK_DOUT_BUS0_BUS, "dout_cmu_bus0_bus_div", "gout_cmu_bus0_bus",
+ CLK_CON_DIV_CLKCMU_BUS0_BUS, 0, 4),
+ DIV(CLK_DOUT_CMU_BOOST, "dout_cmu_boost", "gout_cmu_cmu_boost",
+ CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, 0, 2),
+
+ /* BUS1 */
+ DIV(CLK_DOUT_BUS1_BUS, "dout_cmu_bus1_bus", "gout_cmu_bus1_bus",
+ CLK_CON_DIV_CLKCMU_BUS1_BUS, 0, 4),
+
+ /* BUS2 */
+ DIV(CLK_DOUT_BUS2_BUS, "dout_cmu_bus2_bus", "gout_cmu_bus2_bus",
+ CLK_CON_DIV_CLKCMU_BUS2_BUS, 0, 4),
+
+ /* CORE */
+ DIV(CLK_DOUT_CORE_BUS, "dout_cmu_core_bus", "gout_cmu_core_bus",
+ CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
+
+ /* EH */
+ DIV(CLK_DOUT_EH_BUS, "dout_cmu_eh_bus", "gout_cmu_eh_bus",
+ CLK_CON_DIV_CLKCMU_EH_BUS, 0, 4),
+
+ /* CPUCL{0,1,2,} */
+ DIV(CLK_DOUT_CPUCL2_SWITCH, "dout_cmu_cpucl2_switch", "gout_cmu_cpucl2_switch",
+ CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH, 0, 3),
+
+ DIV(CLK_DOUT_CPUCL1_SWITCH, "dout_cmu_cpucl1_switch", "gout_cmu_cpucl1_switch",
+ CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0, 3),
+
+ DIV(CLK_DOUT_CPUCL0_SWITCH, "dout_cmu_cpucl0_switch", "gout_cmu_cpucl0_switch",
+ CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3),
+
+ DIV(CLK_DOUT_CPUCL0_DBG, "dout_cmu_cpucl0_dbg", "gout_cmu_cpucl0_dbg",
+ CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 4),
+
+ DIV(CLK_DOUT_CMU_HPM, "dout_cmu_hpm", "gout_cmu_hpm",
+ CLK_CON_DIV_CLKCMU_HPM, 0, 2),
+
+ /* G3D */
+ DIV(CLK_DOUT_G3D_SWITCH, "dout_cmu_g3d_switch", "gout_cmu_g3d_switch",
+ CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3),
+
+ DIV(CLK_DOUT_G3D_SWITCH, "dout_cmu_g3d_busd", "gout_cmu_g3d_busd",
+ CLK_CON_DIV_CLKCMU_G3D_BUSD, 0, 4),
+
+ DIV(CLK_DOUT_G3D_GLB, "dout_cmu_g3d_glb", "gout_cmu_g3d_glb",
+ CLK_CON_DIV_CLKCMU_G3D_GLB, 0, 4),
+
+ /* DPU */
+ DIV(CLK_DOUT_DPU_BUS, "dout_cmu_dpu_bus", "gout_cmu_dpu_bus",
+ CLK_CON_DIV_CLKCMU_DPU_BUS, 0, 4),
+
+ /* DISP */
+ DIV(CLK_DOUT_DISP_BUS, "dout_cmu_disp_bus", "gout_cmu_disp_bus",
+ CLK_CON_DIV_CLKCMU_DISP_BUS, 0, 4),
+
+ /* G2D */
+ DIV(CLK_DOUT_G2D_G2D, "dout_cmu_g2d_g2d", "gout_cmu_g2d_g2d",
+ CLK_CON_DIV_CLKCMU_G2D_G2D, 0, 4),
+
+ DIV(CLK_DOUT_G2D_MSCL, "dout_cmu_g2d_mscl", "gout_cmu_g2d_mscl",
+ CLK_CON_DIV_CLKCMU_G2D_MSCL, 0, 4),
+
+ /* HSI0 */
+ DIV(CLK_DOUT_HSI0_USB31DRD, "dout_cmu_hsi0_usb31drd", "gout_cmu_hsi0_usb31drd",
+ CLK_CON_DIV_CLKCMU_HSI0_USB31DRD, 0, 5),
+
+ DIV(CLK_DOUT_HSI0_BUS, "dout_cmu_hsi0_bus", "gout_cmu_hsi0_bus",
+ CLK_CON_DIV_CLKCMU_HSI0_BUS, 0, 4),
+
+ DIV(CLK_DOUT_HSI0_DPGTC, "dout_cmu_hsi0_dpgtc", "gout_cmu_hsi0_dpgtc",
+ CLK_CON_DIV_CLKCMU_HSI0_DPGTC, 0, 4),
+
+ /* TODO register exists but all lower bits are reserved */
+ DIV(CLK_DOUT_HSI0_USBDPDGB, "dout_cmu_hsi0_usbdpdbg", "gout_cmu_hsi0_usbdpdbg",
+ CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG, 0, 0),
+
+ /* HSI1 */
+ DIV(CLK_DOUT_HSI1_BUS, "dout_cmu_hsi1_bus", "gout_cmu_hsi1_bus",
+ CLK_CON_DIV_CLKCMU_HSI1_BUS, 0, 4),
+
+ DIV(CLK_DOUT_HSI1_PCIE, "dout_cmu_hsi1_pcie", "gout_cmu_hsi1_pcie",
+ CLK_CON_DIV_CLKCMU_HSI1_PCIE, 0, 3),
+ /* HSI2 */
+ DIV(CLK_DOUT_HSI2_BUS, "dout_cmu_hsi2_bus", "gout_cmu_hsi2_bus",
+ CLK_CON_DIV_CLKCMU_HSI2_BUS, 0, 4),
+
+ DIV(CLK_DOUT_HSI2_PCIE, "dout_cmu_hsi2_pcie", "gout_cmu_hsi2_pcie",
+ CLK_CON_DIV_CLKCMU_HSI2_PCIE, 0, 3),
+
+ DIV(CLK_DOUT_HSI2_UFS_EMBD, "dout_cmu_hsi2_ufs_embd", "gout_cmu_hsi2_ufs_embd",
+ CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD, 0, 4),
+
+ DIV(CLK_DOUT_HSI2_MMC_CARD, "dout_cmu_hsi2_mmc_card", "gout_cmu_hsi2_mmc_card",
+ CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD, 0, 9),
+
+ /* CSIS */
+ DIV(CLK_DOUT_CSIS, "dout_cmu_csis_bus", "gout_cmu_csis_bus",
+ CLK_CON_DIV_CLKCMU_CSIS_BUS, 0, 4),
+
+ /* PDP */
+ DIV(CLK_DOUT_PDP_BUS, "dout_cmu_pdp_bus", "gout_cmu_pdp_bus",
+ CLK_CON_DIV_CLKCMU_PDP_BUS, 0, 4),
+
+ /* IPP */
+ DIV(CLK_DOUT_IPP_BUS, "dout_cmu_ipp_bus", "gout_cmu_ipp_bus",
+ CLK_CON_DIV_CLKCMU_IPP_BUS, 0, 4),
+
+ /* G3AA */
+ DIV(CLK_DOUT_G3AA, "dout_cmu_g3aa", "gout_cmu_g3aa",
+ CLK_CON_DIV_CLKCMU_G3AA_G3AA, 0, 4),
+
+ /* ITP */
+ DIV(CLK_DOUT_ITP, "dout_cmu_itp_bus", "gout_cmu_itp_bus",
+ CLK_CON_DIV_CLKCMU_ITP_BUS, 0, 4),
+
+ /* DNS */
+ DIV(CLK_DOUT_DNS_BUS, "dout_cmu_dns_bus", "gout_cmu_dns_bus",
+ CLK_CON_DIV_CLKCMU_DNS_BUS, 0, 4),
+
+ /* TNR */
+ DIV(CLK_DOUT_TNR_BUS, "dout_cmu_tnr_bus", "gout_cmu_tnr_bus",
+ CLK_CON_DIV_CLKCMU_TNR_BUS, 0, 4),
+
+ /* MCSC*/
+ DIV(CLK_DOUT_MCSC_ITSC, "dout_cmu_mcsc_itsc", "gout_cmu_mcsc_itsc",
+ CLK_CON_DIV_CLKCMU_MCSC_ITSC, 0, 4),
+
+ DIV(CLK_DOUT_MCSC_MCSC, "dout_cmu_mcsc_mcsc", "gout_cmu_mcsc_mcsc",
+ CLK_CON_DIV_CLKCMU_MCSC_MCSC, 0, 4),
+
+ /* GDC */
+ DIV(CLK_DOUT_GDC_SCSC, "dout_cmu_gdc_scsc", "gout_cmu_gdc_scsc",
+ CLK_CON_DIV_CLKCMU_GDC_SCSC, 0, 4),
+
+ DIV(CLK_DOUT_GDC_GDC0, "dout_cmu_gdc_gdc0", "gout_cmu_gdc_gdc0",
+ CLK_CON_DIV_CLKCMU_GDC_GDC0, 0, 4),
+
+ DIV(CLK_DOUT_GDC_GDC1, "dout_cmu_gdc_gdc1", "gout_cmu_gdc_gdc1",
+ CLK_CON_DIV_CLKCMU_GDC_GDC1, 0, 4),
+
+ /* MFC */
+ DIV(CLK_DOUT_MFC_MFC, "dout_cmu_mfc_mfc", "gout_cmu_mfc_mfc",
+ CLK_CON_DIV_CLKCMU_MFC_MFC, 0, 4),
+
+ /* MIF0/1/2/3 */
+ DIV(CLK_DOUT_MIF_BUS, "dout_cmu_mif_busp", "gout_cmu_mif_busp",
+ CLK_CON_DIV_CLKCMU_MIF_BUSP, 0, 4),
+
+ /* MISC */
+ DIV(CLK_DOUT_MISC_BUS, "dout_cmu_misc_bus", "gout_cmu_misc_bus",
+ CLK_CON_DIV_CLKCMU_MISC_BUS, 0, 4),
+ DIV(CLK_DOUT_MISC_SSS, "dout_cmu_misc_sss", "gout_cmu_misc_sss",
+ CLK_CON_DIV_CLKCMU_MISC_SSS, 0, 4),
+
+ /* PERI0 */
+ DIV(CLK_DOUT_PERIC0_BUS, "dout_cmu_peric0_bus", "gout_cmu_peric0_bus",
+ CLK_CON_DIV_CLKCMU_PERIC0_BUS, 0, 4),
+ DIV(CLK_DOUT_PERIC0_IP, "dout_cmu_peric0_ip", "gout_cmu_peric0_ip",
+ CLK_CON_DIV_CLKCMU_PERIC0_IP, 0, 4),
+
+ /* PERI1 */
+ DIV(CLK_DOUT_PERIC1_BUS, "dout_cmu_peric1_bus", "gout_cmu_peric1_bus",
+ CLK_CON_DIV_CLKCMU_PERIC1_BUS, 0, 4),
+ DIV(CLK_DOUT_PERIC1_IP, "dout_cmu_peric1_ip", "gout_cmu_peric1_ip",
+ CLK_CON_DIV_CLKCMU_PERIC1_IP, 0, 4),
+
+ /* TPU */
+ DIV(CLK_DOUT_TPU_TPU, "dout_cmu_tpu_tpu", "gout_cmu_tpu_tpu",
+ CLK_CON_DIV_CLKCMU_TPU_TPU, 0, 4),
+
+ DIV(CLK_DOUT_TPU_TPUCTL, "dout_cmu_tpu_tpuctl", "gout_cmu_tpu_tpuctl",
+ CLK_CON_DIV_CLKCMU_TPU_TPUCTL, 0, 4),
+
+ DIV(CLK_DOUT_TPU_BUS, "dout_cmu_tpu_bus", "gout_cmu_tpu_bus",
+ CLK_CON_DIV_CLKCMU_TPU_BUS, 0, 4),
+
+ DIV(CLK_DOUT_TPU_UART, "dout_cmu_tpu_uart", "gout_cmu_tpu_uart",
+ CLK_CON_DIV_CLKCMU_TPU_UART, 0, 4),
+
+ /* BO */
+ DIV(CLK_DOUT_BO_BUS, "dout_cmu_bo_bus", "gout_cmu_bo_bus",
+ CLK_CON_DIV_CLKCMU_BO_BUS, 0, 4),
+
+};
+
+static const struct samsung_gate_clock cmu_top_gate_clks[] __initconst = {
+ /* CORE */
+
+ /* MISC */
+ GATE(CLK_GOUT_MISC_BUS, "gout_cmu_misc_bus", "mout_cmu_misc_bus",
+ CLK_CON_GAT_GATE_CLKCMU_MISC_BUS, 21, 0, 0),
+ GATE(CLK_GOUT_MISC_SSS, "gout_cmu_misc_sss", "mout_cmu_misc_sss",
+ CLK_CON_GAT_GATE_CLKCMU_MISC_SSS, 21, 0, 0),
+
+ /* BUS0 */
+ GATE(CLK_GOUT_BUS0_BUS, "gout_cmu_bus0_bus", "mout_cmu_bus0_bus",
+ CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS, 21, 0, 0),
+
+ /* BUS1 */
+ GATE(CLK_GOUT_BUS1_BUS, "gout_cmu_bus1_bus", "mout_cmu_bus1_bus",
+ CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS, 21, 0, 0),
+
+ /* BUS2 */
+ GATE(CLK_GOUT_BUS2_BUS, "gout_cmu_bus2_bus", "mout_cmu_bus2_bus",
+ CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS, 21, 0, 0),
+
+ /* CORE */
+ GATE(CLK_GOUT_CORE_BUS, "gout_cmu_core_bus", "mout_cmu_core_bus",
+ CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0),
+
+ /* EH */
+ GATE(CLK_GOUT_EH_BUS, "gout_cmu_eh_bus", "mout_cmu_eh_bus",
+ CLK_CON_GAT_GATE_CLKCMU_EH_BUS, 21, 0, 0),
+
+ /* CPUCL{0,1,2,} */
+ GATE(CLK_GOUT_CPUCL2_SWITCH, "gout_cmu_cpucl2_switch", "mout_cmu_cpucl2_switch",
+ CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH, 21, 0, 0),
+
+ GATE(CLK_GOUT_CPUCL1_SWITCH, "gout_cmu_cpucl1_switch", "mout_cmu_cpucl1_switch",
+ CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, 21, 0, 0),
+
+ GATE(CLK_GOUT_CPUCL0_SWITCH, "gout_cmu_cpucl0_switch", "mout_cmu_cpucl0_switch",
+ CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, 21, 0, 0),
+
+ GATE(CLK_GOUT_CPUCL0_DBG, "gout_cmu_cpucl0_dbg", "mout_cmu_cpucl0_dbg",
+ CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS, 21, 0, 0),
+
+ GATE(CLK_GOUT_CMU_HPM, "gout_cmu_hpm", "mout_cmu_hpm",
+ CLK_CON_GAT_GATE_CLKCMU_HPM, 21, 0, 0),
+
+ /* G3D */
+ GATE(CLK_GOUT_G3D_SWITCH, "gout_cmu_g3d_switch", "mout_cmu_g3d_switch",
+ CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 21, 0, 0),
+
+ GATE(CLK_GOUT_G3D_SWITCH, "gout_cmu_g3d_busd", "mout_cmu_g3d_busd",
+ CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD, 21, 0, 0),
+
+ GATE(CLK_GOUT_G3D_GLB, "gout_cmu_g3d_glb", "mout_cmu_g3d_glb",
+ CLK_CON_GAT_GATE_CLKCMU_G3D_GLB, 21, 0, 0),
+ /* DPU */
+ GATE(CLK_GOUT_DPU_BUS, "gout_cmu_dpu_bus", "mout_cmu_dpu_bus",
+ CLK_CON_GAT_GATE_CLKCMU_DPU_BUS, 21, 0, 0),
+ /* DISP */
+ GATE(CLK_GOUT_DISP_BUS, "gout_cmu_disp_bus", "mout_cmu_disp_bus",
+ CLK_CON_GAT_GATE_CLKCMU_DISP_BUS, 21, 0, 0),
+
+ /* G2D */
+ GATE(CLK_GOUT_G2D_G2D, "gout_cmu_g2d_g2d", "mout_cmu_g2d_g2d",
+ CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 21, 0, 0),
+
+ GATE(CLK_GOUT_G2D_MSCL, "gout_cmu_g2d_mscl", "mout_cmu_g2d_mscl",
+ CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL, 21, 0, 0),
+ /* HSI0 */
+ GATE(CLK_GOUT_HSI0_USB31DRD, "gout_cmu_hsi0_usb31drd", "mout_cmu_hsi0_usb31drd",
+ CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD, 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI0_BUS, "gout_cmu_hsi0_bus", "mout_cmu_hsi0_bus",
+ CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS, 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI0_DPGTC, "gout_cmu_hsi0_dpgtc", "mout_cmu_hsi0_dpgtc",
+ CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC, 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI0_USBDPDGB, "gout_cmu_hsi0_usbdpdbg", "mout_cmu_hsi0_usbdpdbg",
+ CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG, 21, 0, 0),
+ /* HSI1 */
+ GATE(CLK_GOUT_HSI1_BUS, "gout_cmu_hsi1_bus", "mout_cmu_hsi1_bus",
+ CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS, 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI1_PCIE, "gout_cmu_hsi1_pcie", "mout_cmu_hsi1_pcie",
+ CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE, 21, 0, 0),
+ /* HSI2 */
+ GATE(CLK_GOUT_HSI2_BUS, "gout_cmu_hsi2_bus", "mout_cmu_hsi2_bus",
+ CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS, 21, 0, 0),
+ GATE(CLK_GOUT_HSI2_PCIE, "gout_cmu_hsi2_pcie", "mout_cmu_hsi2_pcie",
+ CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE, 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_UFS_EMBD, "gout_cmu_hsi2_ufs_embd", "mout_cmu_hsi2_ufs_embd",
+ CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD, 21, 0, 0),
+ GATE(CLK_GOUT_HSI2_MMC_CARD, "gout_cmu_hsi2_mmc_card", "mout_cmu_hsi2_mmc_card",
+ CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD, 21, 0, 0),
+ /* CSIS */
+ GATE(CLK_GOUT_CSIS, "gout_cmu_csis_bus", "mout_cmu_csis_bus",
+ CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS, 21, 0, 0),
+ /* PDP */
+ GATE(CLK_GOUT_PDP_BUS, "gout_cmu_pdp_bus", "mout_cmu_pdp_bus",
+ CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 21, 0, 0),
+
+ /* IPP */
+ GATE(CLK_GOUT_IPP_BUS, "gout_cmu_ipp_bus", "mout_cmu_ipp_bus",
+ CLK_CON_GAT_GATE_CLKCMU_IPP_BUS, 21, 0, 0),
+ /* G3AA */
+ GATE(CLK_GOUT_G3AA, "gout_cmu_g3aa", "mout_cmu_g3aa",
+ CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 21, 0, 0),
+
+ /* ITP */
+ GATE(CLK_GOUT_ITP, "gout_cmu_itp_bus", "mout_cmu_itp_bus",
+ CLK_CON_GAT_GATE_CLKCMU_ITP_BUS, 21, 0, 0),
+
+ /* DNS */
+ GATE(CLK_GOUT_DNS_BUS, "gout_cmu_dns_bus", "mout_cmu_dns_bus",
+ CLK_CON_GAT_GATE_CLKCMU_DNS_BUS, 21, 0, 0),
+
+ /* TNR */
+ GATE(CLK_GOUT_TNR_BUS, "gout_cmu_tnr_bus", "mout_cmu_tnr_bus",
+ CLK_CON_GAT_GATE_CLKCMU_TNR_BUS, 21, 0, 0),
+
+ /* MCSC*/
+ GATE(CLK_GOUT_MCSC_ITSC, "gout_cmu_mcsc_itsc", "mout_cmu_mcsc_itsc",
+ CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC, 21, 0, 0),
+
+ GATE(CLK_GOUT_MCSC_MCSC, "gout_cmu_mcsc_mcsc", "mout_cmu_mcsc_mcsc",
+ CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC, 21, 0, 0),
+
+ /* GDC */
+ GATE(CLK_GOUT_GDC_SCSC, "gout_cmu_gdc_scsc", "mout_cmu_gdc_scsc",
+ CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC, 21, 0, 0),
+
+ GATE(CLK_GOUT_GDC_GDC0, "gout_cmu_gdc_gdc0", "mout_cmu_gdc_gdc0",
+ CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0, 21, 0, 0),
+
+ GATE(CLK_GOUT_GDC_GDC1, "gout_cmu_gdc_gdc1", "mout_cmu_gdc_gdc1",
+ CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1, 21, 0, 0),
+
+ /* MFC */
+ GATE(CLK_GOUT_MFC_MFC, "gout_cmu_mfc_mfc", "mout_cmu_mfc_mfc",
+ CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, 21, 0, 0),
+
+ /* DDRPHY0/1/2/3 */
+ GATE(CLK_GOUT_MIF_SWITCH, "gout_cmu_mif_switch", "mout_cmu_mif_switch",
+ CLK_CON_GAT_CLKCMU_MIF_SWITCH, 21, 0, 0),
+
+ /* MIF0/1/2/3 */
+ GATE(CLK_GOUT_MIF_BUS, "gout_cmu_mif_busp", "mout_cmu_mif_busp",
+ CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP, 21, 0, 0),
+
+ GATE(CLK_GOUT_CMU_BOOST, "gout_cmu_cmu_boost", "mout_cmu_boost",
+ CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST, 21, 0, 0),
+
+ /* MISC */
+ GATE(CLK_GOUT_MISC_BUS, "gout_cmu_misc_bus", "mout_cmu_misc_bus",
+ CLK_CON_GAT_GATE_CLKCMU_MISC_BUS, 21, 0, 0),
+ GATE(CLK_GOUT_MISC_SSS, "gout_cmu_misc_sss", "mout_cmu_misc_sss",
+ CLK_CON_GAT_GATE_CLKCMU_MISC_SSS, 21, 0, 0),
+
+ /* PERI0 */
+ GATE(CLK_GOUT_PERIC0_BUS, "gout_cmu_peric0_bus", "mout_cmu_peric0_bus",
+ CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS, 21, 0, 0),
+ GATE(CLK_GOUT_PERIC0_IP, "gout_cmu_peric0_ip", "mout_cmu_peric0_ip",
+ CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP, 21, 0, 0),
+
+ /* PERI1 */
+ GATE(CLK_GOUT_PERIC1_BUS, "gout_cmu_peric1_bus", "mout_cmu_peric1_bus",
+ CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS, 21, 0, 0),
+ GATE(CLK_GOUT_PERIC1_IP, "gout_cmu_peric1_ip", "mout_cmu_peric1_ip",
+ CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP, 21, 0, 0),
+
+ /* TPU */
+ GATE(CLK_GOUT_TPU_TPU, "gout_cmu_tpu_tpu", "mout_cmu_tpu_tpu",
+ CLK_CON_GAT_GATE_CLKCMU_TPU_TPU, 21, 0, 0),
+ GATE(CLK_GOUT_TPU_TPUCTL, "gout_cmu_tpu_tpuctl", "mout_cmu_tpu_tpuctl",
+ CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL, 21, 0, 0),
+ GATE(CLK_GOUT_TPU_BUS, "gout_cmu_tpu_bus", "mout_cmu_tpu_bus",
+ CLK_CON_GAT_GATE_CLKCMU_TPU_BUS, 21, 0, 0),
+ GATE(CLK_GOUT_TPU_UART, "gout_cmu_tpu_uart", "mout_cmu_tpu_uart",
+ CLK_CON_GAT_GATE_CLKCMU_TPU_UART, 21, 0, 0),
+
+ /* BO */
+ GATE(CLK_GOUT_BO_BUS, "gout_cmu_bo_bus", "mout_cmu_bo_bus",
+ CLK_CON_GAT_GATE_CLKCMU_BO_BUS, 21, 0, 0),
+
+};
+
+static const struct samsung_cmu_info top_cmu_info __initconst = {
+ .pll_clks = cmu_top_pll_clks,
+ .nr_pll_clks = ARRAY_SIZE(cmu_top_pll_clks),
+ .mux_clks = cmu_top_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(cmu_top_mux_clks),
+ .div_clks = cmu_top_div_clks,
+ .nr_div_clks = ARRAY_SIZE(cmu_top_div_clks),
+ .gate_clks = cmu_top_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(cmu_top_gate_clks),
+ .nr_clk_ids = TOP_NR_CLK,
+ .clk_regs = cmu_top_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(cmu_top_clk_regs),
+};
+
+static void __init gs101_cmu_top_init(struct device_node *np)
+{
+ exynos_arm64_register_cmu(NULL, np, &top_cmu_info);
+}
+
+/* Register CMU_TOP early, as it's a dependency for other early domains */
+CLK_OF_DECLARE(gs101_cmu_top, "google,gs101-cmu-top",
+ gs101_cmu_top_init);
--
2.42.0.582.g8ccd20d70d-goog
^ permalink raw reply related [flat|nested] 150+ messages in thread* [PATCH 13/21] clk: samsung: clk-gs101: Add cmu_top registers, plls, mux and gates
@ 2023-10-05 15:56 ` Peter Griffin
0 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-05 15:56 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi
Cc: peter.griffin, tudor.ambarus, andre.draszik, semen.protsenko,
soc, devicetree, linux-arm-kernel, linux-samsung-soc, linux-clk,
linux-gpio, linux-watchdog
CMU_TOP is the top level clock management unit which contains PLLs, muxes
and gates that feed the other clock management units.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
drivers/clk/samsung/Kconfig | 9 +
drivers/clk/samsung/Makefile | 1 +
drivers/clk/samsung/clk-gs101.c | 1558 +++++++++++++++++++++++++++++++
3 files changed, 1568 insertions(+)
create mode 100644 drivers/clk/samsung/clk-gs101.c
diff --git a/drivers/clk/samsung/Kconfig b/drivers/clk/samsung/Kconfig
index 76a494e95027..4c8f173c4dec 100644
--- a/drivers/clk/samsung/Kconfig
+++ b/drivers/clk/samsung/Kconfig
@@ -13,6 +13,7 @@ config COMMON_CLK_SAMSUNG
select EXYNOS_5420_COMMON_CLK if ARM && SOC_EXYNOS5420
select EXYNOS_ARM64_COMMON_CLK if ARM64 && ARCH_EXYNOS
select TESLA_FSD_COMMON_CLK if ARM64 && ARCH_TESLA_FSD
+ select GOOGLE_GS101_COMMON_CLK if ARM64 && ARCH_GOOGLE_TENSOR
config S3C64XX_COMMON_CLK
bool "Samsung S3C64xx clock controller support" if COMPILE_TEST
@@ -102,3 +103,11 @@ config TESLA_FSD_COMMON_CLK
help
Support for the clock controller present on the Tesla FSD SoC.
Choose Y here only if you build for this SoC.
+
+config GOOGLE_GS101_COMMON_CLK
+ bool "Google gs101 clock controller support" if COMPILE_TEST
+ depends on COMMON_CLK_SAMSUNG
+ depends on EXYNOS_ARM64_COMMON_CLK
+ help
+ Support for the clock controller present on the Google gs101 SoC.
+ Choose Y here only if you build for this SoC.
\ No newline at end of file
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index ebbeacabe88f..1e69b8e14324 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -24,3 +24,4 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov9.o
obj-$(CONFIG_S3C64XX_COMMON_CLK) += clk-s3c64xx.o
obj-$(CONFIG_S5PV210_COMMON_CLK) += clk-s5pv210.o clk-s5pv210-audss.o
obj-$(CONFIG_TESLA_FSD_COMMON_CLK) += clk-fsd.o
+obj-$(CONFIG_GOOGLE_GS101_COMMON_CLK) += clk-gs101.o
diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
new file mode 100644
index 000000000000..4c58fcc899be
--- /dev/null
+++ b/drivers/clk/samsung/clk-gs101.c
@@ -0,0 +1,1558 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2023 Linaro Ltd.
+ * Author: Peter Griffin <peter.griffin@linaro.org>
+ *
+ * Common Clock Framework support for GS101.
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include <dt-bindings/clock/gs101.h>
+
+#include "clk.h"
+#include "clk-exynos-arm64.h"
+
+/* NOTE: Must be equal to the last clock ID increased by one */
+#define TOP_NR_CLK (CLK_GOUT_CMU_BOOST + 1)
+
+/* ---- CMU_TOP ------------------------------------------------------------- */
+
+/* Register Offset definitions for CMU_TOP (0x1e080000) */
+
+#define PLL_LOCKTIME_PLL_SHARED0 0x0000
+#define PLL_LOCKTIME_PLL_SHARED1 0x0004
+#define PLL_LOCKTIME_PLL_SHARED2 0x0008
+#define PLL_LOCKTIME_PLL_SHARED3 0x000c
+#define PLL_LOCKTIME_PLL_SPARE 0x0010
+#define PLL_CON0_PLL_SHARED0 0x0100
+#define PLL_CON1_PLL_SHARED0 0x0104
+#define PLL_CON2_PLL_SHARED0 0x0108
+#define PLL_CON3_PLL_SHARED0 0x010c
+#define PLL_CON4_PLL_SHARED0 0x0110
+#define PLL_CON0_PLL_SHARED1 0x0140
+#define PLL_CON1_PLL_SHARED1 0x0144
+#define PLL_CON2_PLL_SHARED1 0x0148
+#define PLL_CON3_PLL_SHARED1 0x014c
+#define PLL_CON4_PLL_SHARED1 0x0150
+#define PLL_CON0_PLL_SHARED2 0x0180
+#define PLL_CON1_PLL_SHARED2 0x0184
+#define PLL_CON2_PLL_SHARED2 0x0188
+#define PLL_CON3_PLL_SHARED2 0x018c
+#define PLL_CON4_PLL_SHARED2 0x0190
+#define PLL_CON0_PLL_SHARED3 0x01c0
+#define PLL_CON1_PLL_SHARED3 0x01c4
+#define PLL_CON2_PLL_SHARED3 0x01c8
+#define PLL_CON3_PLL_SHARED3 0x01cc
+#define PLL_CON4_PLL_SHARED3 0x01d0
+#define PLL_CON0_PLL_SPARE 0x0200
+#define PLL_CON1_PLL_SPARE 0x0204
+#define PLL_CON2_PLL_SPARE 0x0208
+#define PLL_CON3_PLL_SPARE 0x020c
+#define PLL_CON4_PLL_SPARE 0x0210
+#define CMU_CMU_TOP_CONTROLLER_OPTION 0x0800
+#define CLKOUT_CON_BLK_CMU_CMU_TOP_CLKOUT0 0x0810
+#define CMU_HCHGEN_CLKMUX_CMU_BOOST 0x0840
+#define CMU_HCHGEN_CLKMUX_TOP_BOOST 0x0844
+#define CMU_HCHGEN_CLKMUX 0x0850
+#define POWER_FAIL_DETECT_PLL 0x0864
+#define EARLY_WAKEUP_FORCED_0_ENABLE 0x0870
+#define EARLY_WAKEUP_FORCED_1_ENABLE 0x0874
+#define EARLY_WAKEUP_APM_CTRL 0x0878
+#define EARLY_WAKEUP_CLUSTER0_CTRL 0x087c
+#define EARLY_WAKEUP_DPU_CTRL 0x0880
+#define EARLY_WAKEUP_CSIS_CTRL 0x0884
+#define EARLY_WAKEUP_APM_DEST 0x0890
+#define EARLY_WAKEUP_CLUSTER0_DEST 0x0894
+#define EARLY_WAKEUP_DPU_DEST 0x0898
+#define EARLY_WAKEUP_CSIS_DEST 0x089c
+#define EARLY_WAKEUP_SW_TRIG_APM 0x08c0
+#define EARLY_WAKEUP_SW_TRIG_APM_SET 0x08c4
+#define EARLY_WAKEUP_SW_TRIG_APM_CLEAR 0x08c8
+#define EARLY_WAKEUP_SW_TRIG_CLUSTER0 0x08d0
+#define EARLY_WAKEUP_SW_TRIG_CLUSTER0_SET 0x08d4
+#define EARLY_WAKEUP_SW_TRIG_CLUSTER0_CLEAR 0x08d8
+#define EARLY_WAKEUP_SW_TRIG_DPU 0x08e0
+#define EARLY_WAKEUP_SW_TRIG_DPU_SET 0x08e4
+#define EARLY_WAKEUP_SW_TRIG_DPU_CLEAR 0x08e8
+#define EARLY_WAKEUP_SW_TRIG_CSIS 0x08f0
+#define EARLY_WAKEUP_SW_TRIG_CSIS_SET 0x08f4
+#define EARLY_WAKEUP_SW_TRIG_CSIS_CLEAR 0x08f8
+
+#define CLK_CON_MUX_MUX_CLKCMU_BO_BUS 0x1000
+#define CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS 0x1004
+#define CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS 0x1008
+#define CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS 0x100c
+#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0 0x1010
+#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1 0x1014
+#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2 0x1018
+#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3 0x101c
+#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4 0x1020
+#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5 0x1024
+#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6 0x1028
+#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7 0x102c
+#define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST 0x1030
+#define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1 0x1034
+#define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1038
+#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG 0x103c
+#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH 0x1040
+#define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH 0x1044
+#define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH 0x1048
+#define CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS 0x104c
+#define CLK_CON_MUX_MUX_CLKCMU_DISP_BUS 0x1050
+#define CLK_CON_MUX_MUX_CLKCMU_DNS_BUS 0x1054
+#define CLK_CON_MUX_MUX_CLKCMU_DPU_BUS 0x1058
+#define CLK_CON_MUX_MUX_CLKCMU_EH_BUS 0x105c
+#define CLK_CON_MUX_MUX_CLKCMU_G2D_G2D 0x1060
+#define CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL 0x1064
+#define CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA 0x1068
+#define CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD 0x106c
+#define CLK_CON_MUX_MUX_CLKCMU_G3D_GLB 0x1070
+#define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH 0x1074
+#define CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0 0x1078
+#define CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1 0x107c
+#define CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC 0x1080
+#define CLK_CON_MUX_MUX_CLKCMU_HPM 0x1084
+#define CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS 0x1088
+#define CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC 0x108c
+#define CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD 0x1090
+#define CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG 0x1094
+#define CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS 0x1098
+#define CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE 0x109c
+#define CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS 0x10a0
+#define CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD 0x10a4
+#define CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE 0x10a8
+#define CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD 0x10ac
+#define CLK_CON_MUX_MUX_CLKCMU_IPP_BUS 0x10b0
+#define CLK_CON_MUX_MUX_CLKCMU_ITP_BUS 0x10b4
+#define CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC 0x10b8
+#define CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC 0x10bc
+#define CLK_CON_MUX_MUX_CLKCMU_MFC_MFC 0x10c0
+#define CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP 0x10c4
+#define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0x10c8
+#define CLK_CON_MUX_MUX_CLKCMU_MISC_BUS 0x10cc
+#define CLK_CON_MUX_MUX_CLKCMU_MISC_SSS 0x10d0
+#define CLK_CON_MUX_MUX_CLKCMU_PDP_BUS 0x10d4
+#define CLK_CON_MUX_MUX_CLKCMU_PDP_VRA 0x10d8
+#define CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS 0x10dc
+#define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP 0x10e0
+#define CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS 0x10e4
+#define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP 0x10e8
+#define CLK_CON_MUX_MUX_CLKCMU_TNR_BUS 0x10ec
+#define CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1 0x10f0
+#define CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF 0x10f4
+#define CLK_CON_MUX_MUX_CLKCMU_TPU_BUS 0x10f8
+#define CLK_CON_MUX_MUX_CLKCMU_TPU_TPU 0x10fc
+#define CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL 0x1100
+#define CLK_CON_MUX_MUX_CLKCMU_TPU_UART 0x1104
+#define CLK_CON_MUX_MUX_CMU_CMUREF 0x1108
+
+#define CLK_CON_DIV_CLKCMU_BO_BUS 0x1800
+#define CLK_CON_DIV_CLKCMU_BUS0_BUS 0x1804
+#define CLK_CON_DIV_CLKCMU_BUS1_BUS 0x1808
+#define CLK_CON_DIV_CLKCMU_BUS2_BUS 0x180c
+#define CLK_CON_DIV_CLKCMU_CIS_CLK0 0x1810
+#define CLK_CON_DIV_CLKCMU_CIS_CLK1 0x1814
+#define CLK_CON_DIV_CLKCMU_CIS_CLK2 0x1818
+#define CLK_CON_DIV_CLKCMU_CIS_CLK3 0x181c
+#define CLK_CON_DIV_CLKCMU_CIS_CLK4 0x1820
+#define CLK_CON_DIV_CLKCMU_CIS_CLK5 0x1824
+#define CLK_CON_DIV_CLKCMU_CIS_CLK6 0x1828
+#define CLK_CON_DIV_CLKCMU_CIS_CLK7 0x182c
+#define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1830
+#define CLK_CON_DIV_CLKCMU_CPUCL0_DBG 0x1834
+#define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH 0x1838
+#define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH 0x183c
+#define CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH 0x1840
+#define CLK_CON_DIV_CLKCMU_CSIS_BUS 0x1844
+#define CLK_CON_DIV_CLKCMU_DISP_BUS 0x1848
+#define CLK_CON_DIV_CLKCMU_DNS_BUS 0x184c
+#define CLK_CON_DIV_CLKCMU_DPU_BUS 0x1850
+#define CLK_CON_DIV_CLKCMU_EH_BUS 0x1854
+#define CLK_CON_DIV_CLKCMU_G2D_G2D 0x1858
+#define CLK_CON_DIV_CLKCMU_G2D_MSCL 0x185c
+#define CLK_CON_DIV_CLKCMU_G3AA_G3AA 0x1860
+#define CLK_CON_DIV_CLKCMU_G3D_BUSD 0x1864
+#define CLK_CON_DIV_CLKCMU_G3D_GLB 0x1868
+#define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x186c
+#define CLK_CON_DIV_CLKCMU_GDC_GDC0 0x1870
+#define CLK_CON_DIV_CLKCMU_GDC_GDC1 0x1874
+#define CLK_CON_DIV_CLKCMU_GDC_SCSC 0x1878
+#define CLK_CON_DIV_CLKCMU_HPM 0x187c
+#define CLK_CON_DIV_CLKCMU_HSI0_BUS 0x1880
+#define CLK_CON_DIV_CLKCMU_HSI0_DPGTC 0x1884
+#define CLK_CON_DIV_CLKCMU_HSI0_USB31DRD 0x1888
+#define CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG 0x188c
+#define CLK_CON_DIV_CLKCMU_HSI1_BUS 0x1890
+#define CLK_CON_DIV_CLKCMU_HSI1_PCIE 0x1894
+#define CLK_CON_DIV_CLKCMU_HSI2_BUS 0x1898
+#define CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD 0x189c
+#define CLK_CON_DIV_CLKCMU_HSI2_PCIE 0x18a0
+#define CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD 0x18a4
+#define CLK_CON_DIV_CLKCMU_IPP_BUS 0x18a8
+#define CLK_CON_DIV_CLKCMU_ITP_BUS 0x18ac
+#define CLK_CON_DIV_CLKCMU_MCSC_ITSC 0x18b0
+#define CLK_CON_DIV_CLKCMU_MCSC_MCSC 0x18b4
+#define CLK_CON_DIV_CLKCMU_MFC_MFC 0x18b8
+#define CLK_CON_DIV_CLKCMU_MIF_BUSP 0x18bc
+#define CLK_CON_DIV_CLKCMU_MISC_BUS 0x18c0
+#define CLK_CON_DIV_CLKCMU_MISC_SSS 0x18c4
+#define CLK_CON_DIV_CLKCMU_OTP 0x18c8
+#define CLK_CON_DIV_CLKCMU_PDP_BUS 0x18cc
+#define CLK_CON_DIV_CLKCMU_PDP_VRA 0x18d0
+#define CLK_CON_DIV_CLKCMU_PERIC0_BUS 0x18d4
+#define CLK_CON_DIV_CLKCMU_PERIC0_IP 0x18d8
+#define CLK_CON_DIV_CLKCMU_PERIC1_BUS 0x18dc
+#define CLK_CON_DIV_CLKCMU_PERIC1_IP 0x18e0
+#define CLK_CON_DIV_CLKCMU_TNR_BUS 0x18e4
+#define CLK_CON_DIV_CLKCMU_TPU_BUS 0x18e8
+#define CLK_CON_DIV_CLKCMU_TPU_TPU 0x18ec
+#define CLK_CON_DIV_CLKCMU_TPU_TPUCTL 0x18f0
+#define CLK_CON_DIV_CLKCMU_TPU_UART 0x18f4
+#define CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST 0x18f8
+#define CLK_CON_DIV_DIV_CLK_CMU_CMUREF 0x18fc
+#define CLK_CON_DIV_PLL_SHARED0_DIV2 0x1900
+#define CLK_CON_DIV_PLL_SHARED0_DIV3 0x1904
+#define CLK_CON_DIV_PLL_SHARED0_DIV4 0x1908
+#define CLK_CON_DIV_PLL_SHARED0_DIV5 0x190c
+#define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1910
+#define CLK_CON_DIV_PLL_SHARED1_DIV3 0x1914
+#define CLK_CON_DIV_PLL_SHARED1_DIV4 0x1918
+#define CLK_CON_DIV_PLL_SHARED2_DIV2 0x191c
+#define CLK_CON_DIV_PLL_SHARED3_DIV2 0x1920
+
+/* CLK_CON_GAT_UPDATES */
+#define CLK_CON_GAT_CLKCMU_BUS0_BOOST 0x2000
+#define CLK_CON_GAT_CLKCMU_BUS1_BOOST 0x2004
+#define CLK_CON_GAT_CLKCMU_BUS2_BOOST 0x2008
+#define CLK_CON_GAT_CLKCMU_CORE_BOOST 0x200c
+#define CLK_CON_GAT_CLKCMU_CPUCL0_BOOST 0x2010
+#define CLK_CON_GAT_CLKCMU_CPUCL1_BOOST 0x2014
+#define CLK_CON_GAT_CLKCMU_CPUCL2_BOOST 0x2018
+#define CLK_CON_GAT_CLKCMU_MIF_BOOST 0x201c
+#define CLK_CON_GAT_CLKCMU_MIF_SWITCH 0x2020
+#define CLK_CON_GAT_GATE_CLKCMU_BO_BUS 0x2024
+#define CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS 0x2028
+#define CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS 0x202c
+#define CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS 0x2030
+#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0 0x2034
+#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1 0x2038
+#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2 0x203c
+#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3 0x2040
+#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4 0x2044
+#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5 0x2048
+#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6 0x204c
+#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7 0x2050
+#define CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST 0x2054
+#define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x2058
+#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS 0x205c
+#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH 0x2060
+#define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH 0x2064
+#define CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH 0x2068
+#define CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS 0x206c
+#define CLK_CON_GAT_GATE_CLKCMU_DISP_BUS 0x2070
+#define CLK_CON_GAT_GATE_CLKCMU_DNS_BUS 0x2074
+#define CLK_CON_GAT_GATE_CLKCMU_DPU_BUS 0x2078
+#define CLK_CON_GAT_GATE_CLKCMU_EH_BUS 0x207c
+#define CLK_CON_GAT_GATE_CLKCMU_G2D_G2D 0x2080
+#define CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL 0x2084
+#define CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA 0x2088
+#define CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD 0x208c
+#define CLK_CON_GAT_GATE_CLKCMU_G3D_GLB 0x2090
+#define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH 0x2094
+#define CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0 0x2098
+#define CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1 0x209c
+#define CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC 0x20a0
+#define CLK_CON_GAT_GATE_CLKCMU_HPM 0x20a4
+#define CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS 0x20a8
+#define CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC 0x20ac
+#define CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD 0x20b0
+#define CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG 0x20b4
+#define CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS 0x20b8
+#define CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE 0x20bc
+#define CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS 0x20c0
+#define CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD 0x20c4
+#define CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE 0x20c8
+#define CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD 0x20cc
+#define CLK_CON_GAT_GATE_CLKCMU_IPP_BUS 0x20d0
+#define CLK_CON_GAT_GATE_CLKCMU_ITP_BUS 0x20d4
+#define CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC 0x20d8
+#define CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC 0x20dc
+#define CLK_CON_GAT_GATE_CLKCMU_MFC_MFC 0x20e0
+#define CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP 0x20e4
+#define CLK_CON_GAT_GATE_CLKCMU_MISC_BUS 0x20e8
+#define CLK_CON_GAT_GATE_CLKCMU_MISC_SSS 0x20ec
+#define CLK_CON_GAT_GATE_CLKCMU_PDP_BUS 0x20f0
+#define CLK_CON_GAT_GATE_CLKCMU_PDP_VRA 0x20f4
+#define CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS 0x20f8
+#define CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP 0x20fc
+#define CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS 0x2100
+#define CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP 0x2104
+#define CLK_CON_GAT_GATE_CLKCMU_TNR_BUS 0x2108
+#define CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF 0x210c
+#define CLK_CON_GAT_GATE_CLKCMU_TPU_BUS 0x2110
+#define CLK_CON_GAT_GATE_CLKCMU_TPU_TPU 0x2114
+#define CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL 0x2118
+#define CLK_CON_GAT_GATE_CLKCMU_TPU_UART 0x211c
+
+#define DMYQCH_CON_CMU_TOP_CMUREF_QCH 0x3000
+#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0 0x3004
+#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1 0x3008
+#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2 0x300c
+#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3 0x3010
+#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4 0x3014
+#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5 0x3018
+#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6 0x301c
+#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7 0x3020
+#define DMYQCH_CON_OTP_QCH 0x3024
+#define QUEUE_CTRL_REG_BLK_CMU_CMU_TOP 0x3c00
+#define QUEUE_ENTRY0_BLK_CMU_CMU_TOP 0x3c10
+#define QUEUE_ENTRY1_BLK_CMU_CMU_TOP 0x3c14
+#define QUEUE_ENTRY2_BLK_CMU_CMU_TOP 0x3c18
+#define QUEUE_ENTRY3_BLK_CMU_CMU_TOP 0x3c1c
+#define QUEUE_ENTRY4_BLK_CMU_CMU_TOP 0x3c20
+#define QUEUE_ENTRY5_BLK_CMU_CMU_TOP 0x3c24
+#define QUEUE_ENTRY6_BLK_CMU_CMU_TOP 0x3c28
+#define QUEUE_ENTRY7_BLK_CMU_CMU_TOP 0x3c2c
+#define MIFMIRROR_QUEUE_CTRL_REG 0x3e00
+#define MIFMIRROR_QUEUE_ENTRY0 0x3e10
+#define MIFMIRROR_QUEUE_ENTRY1 0x3e14
+#define MIFMIRROR_QUEUE_ENTRY2 0x3e18
+#define MIFMIRROR_QUEUE_ENTRY3 0x3e1c
+#define MIFMIRROR_QUEUE_ENTRY4 0x3e20
+#define MIFMIRROR_QUEUE_ENTRY5 0x3e24
+#define MIFMIRROR_QUEUE_ENTRY6 0x3e28
+#define MIFMIRROR_QUEUE_ENTRY7 0x3e2c
+#define MIFMIRROR_QUEUE_BUSY 0x3e30
+#define GENERALIO_ACD_CHANNEL_0 0x3f00
+#define GENERALIO_ACD_CHANNEL_1 0x3f04
+#define GENERALIO_ACD_CHANNEL_2 0x3f08
+#define GENERALIO_ACD_CHANNEL_3 0x3f0c
+#define GENERALIO_ACD_MASK 0x3f14
+
+static const unsigned long cmu_top_clk_regs[] __initconst = {
+ PLL_LOCKTIME_PLL_SHARED0,
+ PLL_LOCKTIME_PLL_SHARED1,
+ PLL_LOCKTIME_PLL_SHARED2,
+ PLL_LOCKTIME_PLL_SHARED3,
+ PLL_LOCKTIME_PLL_SPARE,
+ PLL_CON0_PLL_SHARED0,
+ PLL_CON1_PLL_SHARED0,
+ PLL_CON2_PLL_SHARED0,
+ PLL_CON3_PLL_SHARED0,
+ PLL_CON4_PLL_SHARED0,
+ PLL_CON0_PLL_SHARED1,
+ PLL_CON1_PLL_SHARED1,
+ PLL_CON2_PLL_SHARED1,
+ PLL_CON3_PLL_SHARED1,
+ PLL_CON4_PLL_SHARED1,
+ PLL_CON0_PLL_SHARED2,
+ PLL_CON1_PLL_SHARED2,
+ PLL_CON2_PLL_SHARED2,
+ PLL_CON3_PLL_SHARED2,
+ PLL_CON4_PLL_SHARED2,
+ PLL_CON0_PLL_SHARED3,
+ PLL_CON1_PLL_SHARED3,
+ PLL_CON2_PLL_SHARED3,
+ PLL_CON3_PLL_SHARED3,
+ PLL_CON4_PLL_SHARED3,
+ PLL_CON0_PLL_SPARE,
+ PLL_CON1_PLL_SPARE,
+ PLL_CON2_PLL_SPARE,
+ PLL_CON3_PLL_SPARE,
+ PLL_CON4_PLL_SPARE,
+ CMU_CMU_TOP_CONTROLLER_OPTION,
+ CLKOUT_CON_BLK_CMU_CMU_TOP_CLKOUT0,
+ CMU_HCHGEN_CLKMUX_CMU_BOOST,
+ CMU_HCHGEN_CLKMUX_TOP_BOOST,
+ CMU_HCHGEN_CLKMUX,
+ POWER_FAIL_DETECT_PLL,
+ EARLY_WAKEUP_FORCED_0_ENABLE,
+ EARLY_WAKEUP_FORCED_1_ENABLE,
+ EARLY_WAKEUP_APM_CTRL,
+ EARLY_WAKEUP_CLUSTER0_CTRL,
+ EARLY_WAKEUP_DPU_CTRL,
+ EARLY_WAKEUP_CSIS_CTRL,
+ EARLY_WAKEUP_APM_DEST,
+ EARLY_WAKEUP_CLUSTER0_DEST,
+ EARLY_WAKEUP_DPU_DEST,
+ EARLY_WAKEUP_CSIS_DEST,
+ EARLY_WAKEUP_SW_TRIG_APM,
+ EARLY_WAKEUP_SW_TRIG_APM_SET,
+ EARLY_WAKEUP_SW_TRIG_APM_CLEAR,
+ EARLY_WAKEUP_SW_TRIG_CLUSTER0,
+ EARLY_WAKEUP_SW_TRIG_CLUSTER0_SET,
+ EARLY_WAKEUP_SW_TRIG_CLUSTER0_CLEAR,
+ EARLY_WAKEUP_SW_TRIG_DPU,
+ EARLY_WAKEUP_SW_TRIG_DPU_SET,
+ EARLY_WAKEUP_SW_TRIG_DPU_CLEAR,
+ EARLY_WAKEUP_SW_TRIG_CSIS,
+ EARLY_WAKEUP_SW_TRIG_CSIS_SET,
+ EARLY_WAKEUP_SW_TRIG_CSIS_CLEAR,
+ CLK_CON_MUX_MUX_CLKCMU_BO_BUS,
+ CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS,
+ CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS,
+ CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS,
+ CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0,
+ CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1,
+ CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2,
+ CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3,
+ CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4,
+ CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5,
+ CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6,
+ CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7,
+ CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST,
+ CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1,
+ CLK_CON_MUX_MUX_CLKCMU_CORE_BUS,
+ CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG,
+ CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
+ CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
+ CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH,
+ CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS,
+ CLK_CON_MUX_MUX_CLKCMU_DISP_BUS,
+ CLK_CON_MUX_MUX_CLKCMU_DNS_BUS,
+ CLK_CON_MUX_MUX_CLKCMU_DPU_BUS,
+ CLK_CON_MUX_MUX_CLKCMU_EH_BUS,
+ CLK_CON_MUX_MUX_CLKCMU_G2D_G2D,
+ CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL,
+ CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA,
+ CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD,
+ CLK_CON_MUX_MUX_CLKCMU_G3D_GLB,
+ CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH,
+ CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0,
+ CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1,
+ CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC,
+ CLK_CON_MUX_MUX_CLKCMU_HPM,
+ CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS,
+ CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC,
+ CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD,
+ CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG,
+ CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS,
+ CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE,
+ CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS,
+ CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD,
+ CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE,
+ CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD,
+ CLK_CON_MUX_MUX_CLKCMU_IPP_BUS,
+ CLK_CON_MUX_MUX_CLKCMU_ITP_BUS,
+ CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC,
+ CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC,
+ CLK_CON_MUX_MUX_CLKCMU_MFC_MFC,
+ CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP,
+ CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH,
+ CLK_CON_MUX_MUX_CLKCMU_MISC_BUS,
+ CLK_CON_MUX_MUX_CLKCMU_MISC_SSS,
+ CLK_CON_MUX_MUX_CLKCMU_PDP_BUS,
+ CLK_CON_MUX_MUX_CLKCMU_PDP_VRA,
+ CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS,
+ CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP,
+ CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS,
+ CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP,
+ CLK_CON_MUX_MUX_CLKCMU_TNR_BUS,
+ CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1,
+ CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF,
+ CLK_CON_MUX_MUX_CLKCMU_TPU_BUS,
+ CLK_CON_MUX_MUX_CLKCMU_TPU_TPU,
+ CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL,
+ CLK_CON_MUX_MUX_CLKCMU_TPU_UART,
+ CLK_CON_MUX_MUX_CMU_CMUREF,
+ CLK_CON_DIV_CLKCMU_BO_BUS,
+ CLK_CON_DIV_CLKCMU_BUS0_BUS,
+ CLK_CON_DIV_CLKCMU_BUS1_BUS,
+ CLK_CON_DIV_CLKCMU_BUS2_BUS,
+ CLK_CON_DIV_CLKCMU_CIS_CLK0,
+ CLK_CON_DIV_CLKCMU_CIS_CLK1,
+ CLK_CON_DIV_CLKCMU_CIS_CLK2,
+ CLK_CON_DIV_CLKCMU_CIS_CLK3,
+ CLK_CON_DIV_CLKCMU_CIS_CLK4,
+ CLK_CON_DIV_CLKCMU_CIS_CLK5,
+ CLK_CON_DIV_CLKCMU_CIS_CLK6,
+ CLK_CON_DIV_CLKCMU_CIS_CLK7,
+ CLK_CON_DIV_CLKCMU_CORE_BUS,
+ CLK_CON_DIV_CLKCMU_CPUCL0_DBG,
+ CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH,
+ CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH,
+ CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH,
+ CLK_CON_DIV_CLKCMU_CSIS_BUS,
+ CLK_CON_DIV_CLKCMU_DISP_BUS,
+ CLK_CON_DIV_CLKCMU_DNS_BUS,
+ CLK_CON_DIV_CLKCMU_DPU_BUS,
+ CLK_CON_DIV_CLKCMU_EH_BUS,
+ CLK_CON_DIV_CLKCMU_G2D_G2D,
+ CLK_CON_DIV_CLKCMU_G2D_MSCL,
+ CLK_CON_DIV_CLKCMU_G3AA_G3AA,
+ CLK_CON_DIV_CLKCMU_G3D_BUSD,
+ CLK_CON_DIV_CLKCMU_G3D_GLB,
+ CLK_CON_DIV_CLKCMU_G3D_SWITCH,
+ CLK_CON_DIV_CLKCMU_GDC_GDC0,
+ CLK_CON_DIV_CLKCMU_GDC_GDC1,
+ CLK_CON_DIV_CLKCMU_GDC_SCSC,
+ CLK_CON_DIV_CLKCMU_HPM,
+ CLK_CON_DIV_CLKCMU_HSI0_BUS,
+ CLK_CON_DIV_CLKCMU_HSI0_DPGTC,
+ CLK_CON_DIV_CLKCMU_HSI0_USB31DRD,
+ CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG,
+ CLK_CON_DIV_CLKCMU_HSI1_BUS,
+ CLK_CON_DIV_CLKCMU_HSI1_PCIE,
+ CLK_CON_DIV_CLKCMU_HSI2_BUS,
+ CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD,
+ CLK_CON_DIV_CLKCMU_HSI2_PCIE,
+ CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD,
+ CLK_CON_DIV_CLKCMU_IPP_BUS,
+ CLK_CON_DIV_CLKCMU_ITP_BUS,
+ CLK_CON_DIV_CLKCMU_MCSC_ITSC,
+ CLK_CON_DIV_CLKCMU_MCSC_MCSC,
+ CLK_CON_DIV_CLKCMU_MFC_MFC,
+ CLK_CON_DIV_CLKCMU_MIF_BUSP,
+ CLK_CON_DIV_CLKCMU_MISC_BUS,
+ CLK_CON_DIV_CLKCMU_MISC_SSS,
+ CLK_CON_DIV_CLKCMU_OTP,
+ CLK_CON_DIV_CLKCMU_PDP_BUS,
+ CLK_CON_DIV_CLKCMU_PDP_VRA,
+ CLK_CON_DIV_CLKCMU_PERIC0_BUS,
+ CLK_CON_DIV_CLKCMU_PERIC0_IP,
+ CLK_CON_DIV_CLKCMU_PERIC1_BUS,
+ CLK_CON_DIV_CLKCMU_PERIC1_IP,
+ CLK_CON_DIV_CLKCMU_TNR_BUS,
+ CLK_CON_DIV_CLKCMU_TPU_BUS,
+ CLK_CON_DIV_CLKCMU_TPU_TPU,
+ CLK_CON_DIV_CLKCMU_TPU_TPUCTL,
+ CLK_CON_DIV_CLKCMU_TPU_UART,
+ CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST,
+ CLK_CON_DIV_DIV_CLK_CMU_CMUREF,
+ CLK_CON_DIV_PLL_SHARED0_DIV2,
+ CLK_CON_DIV_PLL_SHARED0_DIV3,
+ CLK_CON_DIV_PLL_SHARED0_DIV4,
+ CLK_CON_DIV_PLL_SHARED0_DIV5,
+ CLK_CON_DIV_PLL_SHARED1_DIV2,
+ CLK_CON_DIV_PLL_SHARED1_DIV3,
+ CLK_CON_DIV_PLL_SHARED1_DIV4,
+ CLK_CON_DIV_PLL_SHARED2_DIV2,
+ CLK_CON_DIV_PLL_SHARED3_DIV2,
+ CLK_CON_GAT_CLKCMU_BUS0_BOOST,
+ CLK_CON_GAT_CLKCMU_BUS1_BOOST,
+ CLK_CON_GAT_CLKCMU_BUS2_BOOST,
+ CLK_CON_GAT_CLKCMU_CORE_BOOST,
+ CLK_CON_GAT_CLKCMU_CPUCL0_BOOST,
+ CLK_CON_GAT_CLKCMU_CPUCL1_BOOST,
+ CLK_CON_GAT_CLKCMU_CPUCL2_BOOST,
+ CLK_CON_GAT_CLKCMU_MIF_BOOST,
+ CLK_CON_GAT_CLKCMU_MIF_SWITCH,
+ CLK_CON_GAT_GATE_CLKCMU_BO_BUS,
+ CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS,
+ CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS,
+ CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS,
+ CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0,
+ CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1,
+ CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2,
+ CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3,
+ CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4,
+ CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5,
+ CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6,
+ CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7,
+ CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST,
+ CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
+ CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS,
+ CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH,
+ CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH,
+ CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH,
+ CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS,
+ CLK_CON_GAT_GATE_CLKCMU_DISP_BUS,
+ CLK_CON_GAT_GATE_CLKCMU_DNS_BUS,
+ CLK_CON_GAT_GATE_CLKCMU_DPU_BUS,
+ CLK_CON_GAT_GATE_CLKCMU_EH_BUS,
+ CLK_CON_GAT_GATE_CLKCMU_G2D_G2D,
+ CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL,
+ CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA,
+ CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD,
+ CLK_CON_GAT_GATE_CLKCMU_G3D_GLB,
+ CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH,
+ CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0,
+ CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1,
+ CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC,
+ CLK_CON_GAT_GATE_CLKCMU_HPM,
+ CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS,
+ CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC,
+ CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD,
+ CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG,
+ CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS,
+ CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE,
+ CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS,
+ CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD,
+ CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE,
+ CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD,
+ CLK_CON_GAT_GATE_CLKCMU_IPP_BUS,
+ CLK_CON_GAT_GATE_CLKCMU_ITP_BUS,
+ CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC,
+ CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC,
+ CLK_CON_GAT_GATE_CLKCMU_MFC_MFC,
+ CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP,
+ CLK_CON_GAT_GATE_CLKCMU_MISC_BUS,
+ CLK_CON_GAT_GATE_CLKCMU_MISC_SSS,
+ CLK_CON_GAT_GATE_CLKCMU_PDP_BUS,
+ CLK_CON_GAT_GATE_CLKCMU_PDP_VRA,
+ CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS,
+ CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP,
+ CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS,
+ CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP,
+ CLK_CON_GAT_GATE_CLKCMU_TNR_BUS,
+ CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF,
+ CLK_CON_GAT_GATE_CLKCMU_TPU_BUS,
+ CLK_CON_GAT_GATE_CLKCMU_TPU_TPU,
+ CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL,
+ CLK_CON_GAT_GATE_CLKCMU_TPU_UART,
+ DMYQCH_CON_CMU_TOP_CMUREF_QCH,
+ DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0,
+ DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1,
+ DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2,
+ DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3,
+ DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4,
+ DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5,
+ DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6,
+ DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7,
+ DMYQCH_CON_OTP_QCH,
+ QUEUE_CTRL_REG_BLK_CMU_CMU_TOP,
+ QUEUE_ENTRY0_BLK_CMU_CMU_TOP,
+ QUEUE_ENTRY1_BLK_CMU_CMU_TOP,
+ QUEUE_ENTRY2_BLK_CMU_CMU_TOP,
+ QUEUE_ENTRY3_BLK_CMU_CMU_TOP,
+ QUEUE_ENTRY4_BLK_CMU_CMU_TOP,
+ QUEUE_ENTRY5_BLK_CMU_CMU_TOP,
+ QUEUE_ENTRY6_BLK_CMU_CMU_TOP,
+ QUEUE_ENTRY7_BLK_CMU_CMU_TOP,
+ MIFMIRROR_QUEUE_CTRL_REG,
+ MIFMIRROR_QUEUE_ENTRY0,
+ MIFMIRROR_QUEUE_ENTRY1,
+ MIFMIRROR_QUEUE_ENTRY2,
+ MIFMIRROR_QUEUE_ENTRY3,
+ MIFMIRROR_QUEUE_ENTRY4,
+ MIFMIRROR_QUEUE_ENTRY5,
+ MIFMIRROR_QUEUE_ENTRY6,
+ MIFMIRROR_QUEUE_ENTRY7,
+ MIFMIRROR_QUEUE_BUSY,
+ GENERALIO_ACD_CHANNEL_0,
+ GENERALIO_ACD_CHANNEL_1,
+ GENERALIO_ACD_CHANNEL_2,
+ GENERALIO_ACD_CHANNEL_3,
+ GENERALIO_ACD_MASK,
+};
+
+static const struct samsung_pll_clock cmu_top_pll_clks[] __initconst = {
+ /* CMU_TOP_PURECLKCOMP */
+ PLL(pll_0517x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
+ PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0,
+ NULL),
+ PLL(pll_0517x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
+ PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1,
+ NULL),
+ PLL(pll_0518x, CLK_FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk",
+ PLL_LOCKTIME_PLL_SHARED2, PLL_CON3_PLL_SHARED2,
+ NULL),
+ PLL(pll_0518x, CLK_FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk",
+ PLL_LOCKTIME_PLL_SHARED3, PLL_CON3_PLL_SHARED3,
+ NULL),
+ PLL(pll_0518x, CLK_FOUT_SPARE_PLL, "fout_spare_pll", "oscclk",
+ PLL_LOCKTIME_PLL_SPARE, PLL_CON3_PLL_SPARE,
+ NULL),
+};
+
+/* List of parent clocks for Muxes in CMU_TOP */
+PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" };
+PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" };
+PNAME(mout_shared2_pll_p) = { "oscclk", "fout_shared2_pll" };
+PNAME(mout_shared3_pll_p) = { "oscclk", "fout_shared3_pll" };
+PNAME(mout_spare_pll_p) = { "oscclk", "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_BUS0 */
+PNAME(mout_cmu_bus0_bus_p) = { "dout_shared0_div4", "dout_shared1_div4",
+ "dout_shared2_div2", "dout_shared3_div2",
+ "fout_spare_pll" };
+
+PNAME(mout_cmu_cmu_boost_p) = { "dout_shared0_div4", "dout_shared1_div4",
+ "dout_shared2_div2", "dout_shared3_div2" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_BUS1 */
+PNAME(mout_cmu_bus1_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
+ "dout_shared1_div3", "dout_shared0_div4",
+ "dout_shared1_div4", "dout_shared2_div2",
+ "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_BUS2 */
+PNAME(mout_cmu_bus2_bus_p) = { "dout_shared0_div2", "dout_shared1_div2",
+ "fout_shared2_pll", "fout_shared3_pll",
+ "dout_shared0_div3", "dout_shared1_div3",
+ "dout_shared0_div5", "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */
+PNAME(mout_cmu_core_bus_p) = { "dout_shared0_div2", "dout_shared1_div2",
+ "fout_shared2_pll", "fout_shared3_pll",
+ "dout_shared0_div3", "dout_shared1_div3",
+ "dout_shared0_div5", "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_EH */
+PNAME(mout_cmu_eh_bus_p) = { "dout_shared0_div2", "dout_shared1_div2",
+ "fout_shared2_pll", "fout_shared3_pll",
+ "dout_shared0_div3", "dout_shared1_div3",
+ "dout_shared0_div5", "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_CPUCL2 */
+PNAME(mout_cmu_cpucl2_switch_p) = { "fout_shared1_pll", "dout_shared0_div2",
+ "dout_shared1_div2", "fout_shared2_pll",
+ "fout_shared3_pll", "dout_shared0_div3",
+ "dout_shared1_div3", "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_CPUCL1 */
+PNAME(mout_cmu_cpucl1_switch_p) = { "fout_shared1_pll", "dout_shared0_div2",
+ "dout_shared1_div2", "fout_shared2_pll",
+ "fout_shared3_pll", "dout_shared0_div3",
+ "dout_shared1_div3", "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_CPUCL0 */
+PNAME(mout_cmu_cpucl0_switch_p) = { "fout_shared1_pll", "dout_shared0_div2",
+ "dout_shared1_div2", "fout_shared2_pll",
+ "fout_shared3_pll", "dout_shared0_div3",
+ "dout_shared1_div3", "fout_spare_pll" };
+
+PNAME(mout_cmu_cpucl0_dbg_p) = { "fout_shared2_pll", "fout_shared3_pll",
+ "dout_shared0_div4", "dout_shared1_div4",
+ "dout_shared2_div2", "fout_spare_pll" };
+
+PNAME(mout_cmu_hpm_p) = { "oscclk", "dout_shared1_div3",
+ "dout_shared0_div4", "dout_shared2_div2" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_G3D */
+PNAME(mout_cmu_g3d_switch_p) = { "fout_shared2_pll", "dout_shared0_div3",
+ "fout_shared3_pll", "dout_shared1_div3",
+ "dout_shared0_div4", "dout_shared1_div4",
+ "fout_spare_pll" };
+
+PNAME(mout_cmu_g3d_busd_p) = { "dout_shared0_div2", "dout_shared1_div2",
+ "fout_shared2_pll", "fout_shared3_pll",
+ "dout_shared0_div3", "dout_shared1_div3",
+ "dout_shared0_div4", "fout_spare_pll" };
+
+PNAME(mout_cmu_g3d_glb_p) = { "dout_shared0_div2", "dout_shared1_div2",
+ "fout_shared2_pll", "fout_shared3_pll",
+ "dout_shared0_div3", "dout_shared1_div3",
+ "dout_shared0_div4", "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_DPU */
+PNAME(mout_cmu_dpu_p) = { "dout_shared0_div3", "fout_shared3_pll",
+ "dout_shared1_div3", "dout_shared0_div4",
+ "dout_shared1_div4", "dout_shared2_div2",
+ "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_DISP */
+PNAME(mout_cmu_disp_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
+ "dout_shared1_div3", "dout_shared0_div4",
+ "dout_shared1_div4", "dout_shared2_div2",
+ "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_G2D */
+PNAME(mout_cmu_g2d_g2d_p) = { "dout_shared0_div3", "fout_shared3_pll",
+ "dout_shared1_div3", "dout_shared0_div4",
+ "dout_shared1_div4", "dout_shared2_div2",
+ "fout_spare_pll" };
+
+PNAME(mout_cmu_g2d_mscl_p) = { "dout_shared0_div4", "dout_shared1_div4",
+ "dout_shared2_div2", "dout_shared3_div2",
+ "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI0 */
+PNAME(mout_cmu_hsi0_usb31drd_p) = { "oscclk", "dout_shared2_div2" };
+
+PNAME(mout_cmu_hsi0_bus_p) = { "dout_shared0_div4", "dout_shared1_div4",
+ "dout_shared2_div2", "dout_shared3_div2",
+ "fout_spare_pll" };
+
+PNAME(mout_cmu_hsi0_dpgtc_p) = { "oscclk", "dout_shared0_div4",
+ "dout_shared2_div2", "fout_spare_pll" };
+
+PNAME(mout_cmu_hsi0_usbdpdbg_p) = { "oscclk", "dout_shared2_div2" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI1 */
+PNAME(mout_cmu_hsi1_bus_p) = { "dout_shared0_div4", "dout_shared1_div4",
+ "dout_shared2_div2", "dout_shared3_div2",
+ "fout_spare_pll" };
+
+PNAME(mout_cmu_hsi1_pcie_p) = { "oscclk", "dout_shared2_div2" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI2 */
+PNAME(mout_cmu_hsi2_bus_p) = { "dout_shared0_div4", "dout_shared1_div4",
+ "dout_shared2_div2", "dout_shared3_div2",
+ "fout_spare_pll" };
+
+PNAME(mout_cmu_hsi2_pcie0_p) = { "oscclk", "dout_shared2_div2" };
+
+PNAME(mout_cmu_hsi2_ufs_embd_p) = { "oscclk", "dout_shared0_div4",
+ "dout_shared2_div2", "fout_spare_pll" };
+
+PNAME(mout_cmu_hsi2_mmc_card_p) = { "fout_shared2_pll", "fout_shared3_pll",
+ "dout_shared0_div4", "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_CSIS */
+PNAME(mout_cmu_csis_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
+ "dout_shared1_div3", "dout_shared0_div4",
+ "dout_shared1_div4", "dout_shared2_div2",
+ "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_PDP */
+PNAME(mout_cmu_pdp_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
+ "dout_shared1_div3", "dout_shared0_div4",
+ "dout_shared1_div4", "dout_shared2_div2",
+ "fout_spare_pll" };
+
+PNAME(mout_cmu_pdp_vra_p) = { "fout_shared2_pll", "dout_shared0_div3",
+ "fout_shared3_pll", "dout_shared1_div3",
+ "dout_shared0_div4", "dout_shared1_div4",
+ "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_IPP */
+PNAME(mout_cmu_ipp_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
+ "dout_shared1_div3", "dout_shared0_div4",
+ "dout_shared1_div4", "dout_shared2_div2",
+ "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_G3AA */
+PNAME(mout_cmu_g3aa_p) = { "dout_shared0_div3", "fout_shared3_pll",
+ "dout_shared1_div3", "dout_shared0_div4",
+ "dout_shared1_div4", "dout_shared2_div2",
+ "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_ITP */
+PNAME(mout_cmu_itp_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
+ "dout_shared1_div3", "dout_shared0_div4",
+ "dout_shared1_div4", "dout_shared2_div2",
+ "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_DNS */
+PNAME(mout_cmu_dns_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
+ "dout_shared1_div3", "dout_shared0_div4",
+ "dout_shared1_div4", "dout_shared2_div2",
+ "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_TNR */
+PNAME(mout_cmu_tnr_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
+ "dout_shared1_div3", "dout_shared0_div4",
+ "dout_shared1_div4", "dout_shared2_div2",
+ "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_MCSC */
+PNAME(mout_cmu_mcsc_itsc_p) = { "dout_shared0_div3", "fout_shared3_pll",
+ "dout_shared1_div3", "dout_shared0_div4",
+ "dout_shared1_div4", "dout_shared2_div2",
+ "fout_spare_pll" };
+
+PNAME(mout_cmu_mcsc_mcsc_p) = { "dout_shared0_div3", "fout_shared3_pll",
+ "dout_shared1_div3", "dout_shared0_div4",
+ "dout_shared1_div4", "dout_shared2_div2",
+ "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_GDC */
+PNAME(mout_cmu_gdc_scsc_p) = { "dout_shared0_div3", "fout_shared3_pll",
+ "dout_shared1_div3", "dout_shared0_div4",
+ "dout_shared1_div4", "dout_shared2_div2",
+ "fout_spare_pll" };
+
+PNAME(mout_cmu_gdc_gdc0_p) = { "dout_shared0_div3", "fout_shared3_pll",
+ "dout_shared1_div3", "dout_shared0_div4",
+ "dout_shared1_div4", "dout_shared2_div2",
+ "fout_spare_pll" };
+
+PNAME(mout_cmu_gdc_gdc1_p) = { "dout_shared0_div3", "fout_shared3_pll",
+ "dout_shared1_div3", "dout_shared0_div4",
+ "dout_shared1_div4", "dout_shared2_div2",
+ "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_MFC */
+PNAME(mout_cmu_mfc_mfc_p) = { "dout_shared0_div3", "fout_shared3_pll",
+ "dout_shared1_div3", "dout_shared0_div4",
+ "dout_shared1_div4", "dout_shared2_div2",
+ "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for DDRPHY0/1/2/3 */
+
+PNAME(mout_cmu_mif_switch_p) = { "fout_shared0_pll", "fout_shared1_pll",
+ "dout_shared0_div2", "dout_shared1_div2",
+ "fout_shared2_pll", "dout_shared0_div3",
+ "fout_shared3_pll", "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_MIF0/1/2/3 */
+PNAME(mout_cmu_mif_busp_p) = { "dout_shared0_div4", "dout_shared1_div4",
+ "dout_shared0_div5", "fout_spare_pll" };
+
+PNAME(mout_cmu_boost_p) = { "dout_shared0_div4", "dout_shared1_div4",
+ "dout_shared2_div2", "dout_shared3_div2" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_MISC */
+PNAME(mout_cmu_misc_bus_p) = { "dout_shared0_div4", "dout_shared2_div2",
+ "dout_shared3_div2", "fout_spare_pll" };
+PNAME(mout_cmu_misc_sss_p) = { "dout_shared0_div4", "dout_shared2_div2",
+ "dout_shared3_div2", "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_PERIC0 */
+PNAME(mout_cmu_peric0_bus_p) = { "dout_shared0_div4", "dout_shared2_div2",
+ "dout_shared3_div2", "fout_spare_pll" };
+PNAME(mout_cmu_peric0_ip_p) = { "dout_shared0_div4", "dout_shared2_div2",
+ "dout_shared3_div2", "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_PERIC1 */
+PNAME(mout_cmu_peric1_bus_p) = { "dout_shared0_div4", "dout_shared2_div2",
+ "dout_shared3_div2", "fout_spare_pll" };
+PNAME(mout_cmu_peric1_ip_p) = { "dout_shared0_div4", "dout_shared2_div2",
+ "dout_shared3_div2", "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_TPU */
+PNAME(mout_cmu_tpu_tpu_p) = { "dout_shared0_div2", "dout_shared1_div2",
+ "fout_shared2_pll", "fout_shared3_pll",
+ "dout_shared0_div3", "dout_shared1_div3",
+ "dout_shared0_div4", "fout_spare_pll" };
+
+PNAME(mout_cmu_tpu_tpuctl_p) = { "dout_shared0_div2", "dout_shared1_div2",
+ "fout_shared2_pll", "fout_shared3_pll",
+ "dout_shared0_div3", "dout_shared1_div3",
+ "dout_shared0_div4", "fout_spare_pll" };
+
+PNAME(mout_cmu_tpu_bus_p) = { "dout_shared0_div2", "dout_shared1_div2",
+ "fout_shared2_pll", "fout_shared3_pll",
+ "dout_shared0_div3", "dout_shared1_div3",
+ "dout_shared0_div4", "fout_spare_pll" };
+
+PNAME(mout_cmu_tpu_uart_p) = { "dout_shared0_div4", "dout_shared2_div2",
+ "dout_shared3_div2", "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_BO */
+PNAME(mout_cmu_bo_bus_p) = { "fout_shared2_pll", "dout_shared0_div3",
+ "fout_shared3_pll", "dout_shared1_div3",
+ "dout_shared0_div4", "dout_shared1_div4",
+ "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_G2D */
+PNAME(mout_cmu_g2d_p) = { "dout_shared0_div3", "fout_shared3_pll",
+ "dout_shared1_div3", "dout_shared0_div4",
+ "dout_shared1_div4", "dout_shared2_div2",
+ "fout_spare_pll" };
+
+/* gs101 */
+static const struct samsung_mux_clock cmu_top_mux_clks[] __initconst = {
+ /* CMU_TOP_PURECLKCOMP */
+ MUX(CLK_MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p,
+ PLL_CON0_PLL_SHARED0, 4, 1),
+ MUX(CLK_MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p,
+ PLL_CON0_PLL_SHARED1, 4, 1),
+ MUX(CLK_MOUT_SHARED2_PLL, "mout_shared2_pll", mout_shared2_pll_p,
+ PLL_CON0_PLL_SHARED2, 4, 1),
+ MUX(CLK_MOUT_SHARED3_PLL, "mout_shared3_pll", mout_shared3_pll_p,
+ PLL_CON0_PLL_SHARED3, 4, 1),
+ MUX(CLK_MOUT_SPARE_PLL, "mout_spare_pll", mout_spare_pll_p,
+ PLL_CON0_PLL_SPARE, 4, 1),
+
+ /* BUS0 */
+ MUX(CLK_MOUT_BUS0_BUS, "mout_cmu_bus0_bus", mout_cmu_bus0_bus_p,
+ CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS, 0, 2),
+ MUX(CLK_MOUT_CMU_BOOST, "mout_cmu_boost", mout_cmu_cmu_boost_p,
+ CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0, 2),
+
+ /* BUS1 */
+ MUX(CLK_MOUT_BUS1_BUS, "mout_cmu_bus1_bus", mout_cmu_bus1_bus_p,
+ CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS, 0, 2),
+
+ /* BUS2 */
+ MUX(CLK_MOUT_BUS2_BUS, "mout_cmu_bus2_bus", mout_cmu_bus2_bus_p,
+ CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS, 0, 2),
+
+ /* CORE */
+ MUX(CLK_MOUT_CORE_BUS, "mout_cmu_core_bus", mout_cmu_core_bus_p,
+ CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
+
+ /* EH */
+ MUX(CLK_MOUT_EH_BUS, "mout_cmu_eh_bus", mout_cmu_eh_bus_p,
+ CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
+
+ /* CPUCL{0,1,2,} */
+ MUX(CLK_MOUT_CPUCL2_SWITCH, "mout_cmu_cpucl2_switch", mout_cmu_cpucl2_switch_p,
+ CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH, 0, 2),
+
+ MUX(CLK_MOUT_CPUCL1_SWITCH, "mout_cmu_cpucl1_switch", mout_cmu_cpucl1_switch_p,
+ CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, 0, 2),
+
+ MUX(CLK_MOUT_CPUCL0_SWITCH, "mout_cmu_cpucl0_switch", mout_cmu_cpucl0_switch_p,
+ CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, 0, 2),
+
+ MUX(CLK_MOUT_CPUCL0_DBG, "mout_cmu_cpucl0_dbg", mout_cmu_cpucl0_dbg_p,
+ CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 2),
+
+ MUX(CLK_MOUT_CMU_HPM, "mout_cmu_hpm", mout_cmu_hpm_p,
+ CLK_CON_MUX_MUX_CLKCMU_HPM, 0, 2),
+
+ /* G3D */
+ MUX(CLK_MOUT_G3D_SWITCH, "mout_cmu_g3d_switch", mout_cmu_g3d_switch_p,
+ CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0, 2),
+
+ MUX(CLK_MOUT_G3D_BUSD, "mout_cmu_g3d_busd", mout_cmu_g3d_busd_p,
+ CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD, 0, 2),
+
+ MUX(CLK_MOUT_G3D_GLB, "mout_cmu_g3d_glb", mout_cmu_g3d_glb_p,
+ CLK_CON_MUX_MUX_CLKCMU_G3D_GLB, 0, 2),
+ /* DPU */
+ MUX(CLK_MOUT_DPU_BUS, "mout_cmu_dpu_bus", mout_cmu_dpu_p,
+ CLK_CON_MUX_MUX_CLKCMU_DPU_BUS, 0, 2),
+
+ /* DISP */
+ MUX(CLK_MOUT_DISP_BUS, "mout_cmu_disp_bus", mout_cmu_disp_bus_p,
+ CLK_CON_MUX_MUX_CLKCMU_DISP_BUS, 0, 2),
+
+ /* G2D */
+ MUX(CLK_MOUT_G2D_G2D, "mout_cmu_g2d_g2d", mout_cmu_g2d_g2d_p,
+ CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 0, 2),
+
+ MUX(CLK_MOUT_G2D_MSCL, "mout_cmu_g2d_mscl", mout_cmu_g2d_mscl_p,
+ CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0, 2),
+
+ /* HSI0 */
+ MUX(CLK_MOUT_HSI0_USB31DRD, "mout_cmu_hsi0_usb31drd", mout_cmu_hsi0_usb31drd_p,
+ CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD, 0, 2),
+
+ MUX(CLK_MOUT_HSI0_BUS, "mout_cmu_hsi0_bus", mout_cmu_hsi0_bus_p,
+ CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS, 0, 2),
+
+ MUX(CLK_MOUT_HSI0_DPGTC, "mout_cmu_hsi0_dpgtc", mout_cmu_hsi0_dpgtc_p,
+ CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC, 0, 2),
+
+ MUX(CLK_MOUT_HSI0_USBDPDGB, "mout_cmu_hsi0_usbdpdbg", mout_cmu_hsi0_usbdpdbg_p,
+ CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG, 0, 2),
+
+ /* HSI1 */
+ MUX(CLK_MOUT_HSI1_BUS, "mout_cmu_hsi1_bus", mout_cmu_hsi1_bus_p,
+ CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS, 0, 2),
+
+ MUX(CLK_MOUT_HSI1_PCIE, "mout_cmu_hsi1_pcie", mout_cmu_hsi1_pcie_p,
+ CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE, 0, 2),
+ /* HSI2 */
+ MUX(CLK_MOUT_HSI2_BUS, "mout_cmu_hsi2_bus", mout_cmu_hsi2_bus_p,
+ CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS, 0, 2),
+
+ MUX(CLK_MOUT_HSI2_PCIE, "mout_cmu_hsi2_pcie", mout_cmu_hsi2_pcie0_p,
+ CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE, 0, 2),
+
+ MUX(CLK_MOUT_HSI2_UFS_EMBD, "mout_cmu_hsi2_ufs_embd", mout_cmu_hsi2_ufs_embd_p,
+ CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD, 0, 2),
+
+ MUX(CLK_MOUT_HSI2_MMC_CARD, "mout_cmu_hsi2_mmc_card", mout_cmu_hsi2_mmc_card_p,
+ CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD, 0, 2),
+
+ /* CSIS */
+ MUX(CLK_MOUT_CSIS, "mout_cmu_csis_bus", mout_cmu_csis_bus_p,
+ CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS, 0, 2),
+
+ /* PDP */
+ MUX(CLK_MOUT_PDP_BUS, "mout_cmu_pdp_bus", mout_cmu_pdp_bus_p,
+ CLK_CON_MUX_MUX_CLKCMU_PDP_BUS, 0, 2),
+
+ /* IPP */
+ MUX(CLK_MOUT_IPP_BUS, "mout_cmu_ipp_bus", mout_cmu_ipp_bus_p,
+ CLK_CON_MUX_MUX_CLKCMU_IPP_BUS, 0, 2),
+
+ /* G3AA */
+ MUX(CLK_MOUT_G3AA, "mout_cmu_g3aa", mout_cmu_g3aa_p,
+ CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 0, 2),
+
+ /* ITP */
+ MUX(CLK_MOUT_ITP, "mout_cmu_itp_bus", mout_cmu_itp_bus_p,
+ CLK_CON_MUX_MUX_CLKCMU_ITP_BUS, 0, 2),
+
+ /* DNS */
+ MUX(CLK_MOUT_DNS_BUS, "mout_cmu_dns_bus", mout_cmu_dns_bus_p,
+ CLK_CON_MUX_MUX_CLKCMU_DNS_BUS, 0, 2),
+
+ /* TNR */
+ MUX(CLK_MOUT_TNR_BUS, "mout_cmu_tnr_bus", mout_cmu_tnr_bus_p,
+ CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, 0, 2),
+
+ /* MCSC*/
+ MUX(CLK_MOUT_MCSC_ITSC, "mout_cmu_mcsc_itsc", mout_cmu_mcsc_itsc_p,
+ CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC, 0, 2),
+
+ MUX(CLK_MOUT_MCSC_MCSC, "mout_cmu_mcsc_mcsc", mout_cmu_mcsc_mcsc_p,
+ CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC, 0, 2),
+
+ /* GDC */
+ MUX(CLK_MOUT_GDC_SCSC, "mout_cmu_gdc_scsc", mout_cmu_gdc_scsc_p,
+ CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC, 0, 2),
+
+ MUX(CLK_MOUT_GDC_GDC0, "mout_cmu_gdc_gdc0", mout_cmu_gdc_gdc0_p,
+ CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0, 0, 2),
+
+ MUX(CLK_MOUT_GDC_GDC1, "mout_cmu_gdc_gdc1", mout_cmu_gdc_gdc1_p,
+ CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1, 0, 2),
+
+ /* MFC */
+ MUX(CLK_MOUT_MFC_MFC, "mout_cmu_mfc_mfc", mout_cmu_mfc_mfc_p,
+ CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 0, 2),
+
+ /* DDRPHY0/1/2/3 */
+ MUX(CLK_MOUT_MIF_SWITCH, "mout_cmu_mif_switch", mout_cmu_mif_switch_p,
+ CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0, 2),
+
+ /* MIF0/1/2/3 */
+ MUX(CLK_MOUT_MIF_BUS, "mout_cmu_mif_busp", mout_cmu_mif_busp_p,
+ CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, 0, 2),
+
+ /* MISC */
+ MUX(CLK_MOUT_MISC_BUS, "mout_cmu_misc_bus", mout_cmu_misc_bus_p,
+ CLK_CON_MUX_MUX_CLKCMU_MISC_BUS, 0, 2),
+ MUX(CLK_MOUT_MISC_SSS, "mout_cmu_misc_sss", mout_cmu_misc_sss_p,
+ CLK_CON_MUX_MUX_CLKCMU_MISC_SSS, 0, 2),
+
+ /* PERI0 */
+ MUX(CLK_MOUT_PERIC0_IP, "mout_cmu_peric0_ip", mout_cmu_peric0_ip_p,
+ CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 2),
+ MUX(CLK_MOUT_PERIC0_BUS, "mout_cmu_peric0_bus", mout_cmu_peric0_bus_p,
+ CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0, 2),
+ /* PERI1 */
+ MUX(CLK_MOUT_PERIC1_IP, "mout_cmu_peric1_ip", mout_cmu_peric1_ip_p,
+ CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 2),
+ MUX(CLK_MOUT_PERIC1_BUS, "mout_cmu_peric1_bus", mout_cmu_peric1_bus_p,
+ CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0, 2),
+
+ /* TPU */
+ MUX(CLK_MOUT_TPU_TPU, "mout_cmu_tpu_tpu", mout_cmu_tpu_tpu_p,
+ CLK_CON_MUX_MUX_CLKCMU_TPU_TPU, 0, 2),
+
+ MUX(CLK_MOUT_TPU_TPUCTL, "mout_cmu_tpu_tpuctl", mout_cmu_tpu_tpuctl_p,
+ CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL, 0, 2),
+
+ MUX(CLK_MOUT_TPU_BUS, "mout_cmu_tpu_bus", mout_cmu_tpu_bus_p,
+ CLK_CON_MUX_MUX_CLKCMU_TPU_BUS, 0, 2),
+
+ MUX(CLK_MOUT_TPU_UART, "mout_cmu_tpu_uart", mout_cmu_tpu_uart_p,
+ CLK_CON_MUX_MUX_CLKCMU_TPU_UART, 0, 2),
+
+ /* BO */
+ MUX(CLK_MOUT_BO_BUS, "mout_cmu_bo_bus", mout_cmu_bo_bus_p,
+ CLK_CON_MUX_MUX_CLKCMU_BO_BUS, 0, 2),
+};
+
+static const struct samsung_div_clock cmu_top_div_clks[] __initconst = {
+ /* CMU_TOP_PURECLKCOMP */
+ DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "mout_shared0_pll",
+ CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
+ DIV(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2", "mout_shared0_pll",
+ CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
+ DIV(CLK_DOUT_SHARED0_DIV5, "dout_shared0_div5", "mout_shared0_pll",
+ CLK_CON_DIV_PLL_SHARED0_DIV5, 0, 2),
+ DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "dout_shared0_div2",
+ CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
+
+ DIV(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2", "mout_shared1_pll",
+ CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
+ DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "mout_shared1_pll",
+ CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
+ DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "mout_shared1_pll",
+ CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
+
+ DIV(CLK_DOUT_SHARED2_DIV2, "dout_shared2_div2", "mout_shared2_pll",
+ CLK_CON_DIV_PLL_SHARED2_DIV2, 0, 1),
+
+ DIV(CLK_DOUT_SHARED3_DIV2, "dout_shared3_div2", "mout_shared3_pll",
+ CLK_CON_DIV_PLL_SHARED3_DIV2, 0, 1),
+
+ /* BUS0 */
+ DIV(CLK_DOUT_BUS0_BUS, "dout_cmu_bus0_bus_div", "gout_cmu_bus0_bus",
+ CLK_CON_DIV_CLKCMU_BUS0_BUS, 0, 4),
+ DIV(CLK_DOUT_CMU_BOOST, "dout_cmu_boost", "gout_cmu_cmu_boost",
+ CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, 0, 2),
+
+ /* BUS1 */
+ DIV(CLK_DOUT_BUS1_BUS, "dout_cmu_bus1_bus", "gout_cmu_bus1_bus",
+ CLK_CON_DIV_CLKCMU_BUS1_BUS, 0, 4),
+
+ /* BUS2 */
+ DIV(CLK_DOUT_BUS2_BUS, "dout_cmu_bus2_bus", "gout_cmu_bus2_bus",
+ CLK_CON_DIV_CLKCMU_BUS2_BUS, 0, 4),
+
+ /* CORE */
+ DIV(CLK_DOUT_CORE_BUS, "dout_cmu_core_bus", "gout_cmu_core_bus",
+ CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
+
+ /* EH */
+ DIV(CLK_DOUT_EH_BUS, "dout_cmu_eh_bus", "gout_cmu_eh_bus",
+ CLK_CON_DIV_CLKCMU_EH_BUS, 0, 4),
+
+ /* CPUCL{0,1,2,} */
+ DIV(CLK_DOUT_CPUCL2_SWITCH, "dout_cmu_cpucl2_switch", "gout_cmu_cpucl2_switch",
+ CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH, 0, 3),
+
+ DIV(CLK_DOUT_CPUCL1_SWITCH, "dout_cmu_cpucl1_switch", "gout_cmu_cpucl1_switch",
+ CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0, 3),
+
+ DIV(CLK_DOUT_CPUCL0_SWITCH, "dout_cmu_cpucl0_switch", "gout_cmu_cpucl0_switch",
+ CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3),
+
+ DIV(CLK_DOUT_CPUCL0_DBG, "dout_cmu_cpucl0_dbg", "gout_cmu_cpucl0_dbg",
+ CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 4),
+
+ DIV(CLK_DOUT_CMU_HPM, "dout_cmu_hpm", "gout_cmu_hpm",
+ CLK_CON_DIV_CLKCMU_HPM, 0, 2),
+
+ /* G3D */
+ DIV(CLK_DOUT_G3D_SWITCH, "dout_cmu_g3d_switch", "gout_cmu_g3d_switch",
+ CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3),
+
+ DIV(CLK_DOUT_G3D_SWITCH, "dout_cmu_g3d_busd", "gout_cmu_g3d_busd",
+ CLK_CON_DIV_CLKCMU_G3D_BUSD, 0, 4),
+
+ DIV(CLK_DOUT_G3D_GLB, "dout_cmu_g3d_glb", "gout_cmu_g3d_glb",
+ CLK_CON_DIV_CLKCMU_G3D_GLB, 0, 4),
+
+ /* DPU */
+ DIV(CLK_DOUT_DPU_BUS, "dout_cmu_dpu_bus", "gout_cmu_dpu_bus",
+ CLK_CON_DIV_CLKCMU_DPU_BUS, 0, 4),
+
+ /* DISP */
+ DIV(CLK_DOUT_DISP_BUS, "dout_cmu_disp_bus", "gout_cmu_disp_bus",
+ CLK_CON_DIV_CLKCMU_DISP_BUS, 0, 4),
+
+ /* G2D */
+ DIV(CLK_DOUT_G2D_G2D, "dout_cmu_g2d_g2d", "gout_cmu_g2d_g2d",
+ CLK_CON_DIV_CLKCMU_G2D_G2D, 0, 4),
+
+ DIV(CLK_DOUT_G2D_MSCL, "dout_cmu_g2d_mscl", "gout_cmu_g2d_mscl",
+ CLK_CON_DIV_CLKCMU_G2D_MSCL, 0, 4),
+
+ /* HSI0 */
+ DIV(CLK_DOUT_HSI0_USB31DRD, "dout_cmu_hsi0_usb31drd", "gout_cmu_hsi0_usb31drd",
+ CLK_CON_DIV_CLKCMU_HSI0_USB31DRD, 0, 5),
+
+ DIV(CLK_DOUT_HSI0_BUS, "dout_cmu_hsi0_bus", "gout_cmu_hsi0_bus",
+ CLK_CON_DIV_CLKCMU_HSI0_BUS, 0, 4),
+
+ DIV(CLK_DOUT_HSI0_DPGTC, "dout_cmu_hsi0_dpgtc", "gout_cmu_hsi0_dpgtc",
+ CLK_CON_DIV_CLKCMU_HSI0_DPGTC, 0, 4),
+
+ /* TODO register exists but all lower bits are reserved */
+ DIV(CLK_DOUT_HSI0_USBDPDGB, "dout_cmu_hsi0_usbdpdbg", "gout_cmu_hsi0_usbdpdbg",
+ CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG, 0, 0),
+
+ /* HSI1 */
+ DIV(CLK_DOUT_HSI1_BUS, "dout_cmu_hsi1_bus", "gout_cmu_hsi1_bus",
+ CLK_CON_DIV_CLKCMU_HSI1_BUS, 0, 4),
+
+ DIV(CLK_DOUT_HSI1_PCIE, "dout_cmu_hsi1_pcie", "gout_cmu_hsi1_pcie",
+ CLK_CON_DIV_CLKCMU_HSI1_PCIE, 0, 3),
+ /* HSI2 */
+ DIV(CLK_DOUT_HSI2_BUS, "dout_cmu_hsi2_bus", "gout_cmu_hsi2_bus",
+ CLK_CON_DIV_CLKCMU_HSI2_BUS, 0, 4),
+
+ DIV(CLK_DOUT_HSI2_PCIE, "dout_cmu_hsi2_pcie", "gout_cmu_hsi2_pcie",
+ CLK_CON_DIV_CLKCMU_HSI2_PCIE, 0, 3),
+
+ DIV(CLK_DOUT_HSI2_UFS_EMBD, "dout_cmu_hsi2_ufs_embd", "gout_cmu_hsi2_ufs_embd",
+ CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD, 0, 4),
+
+ DIV(CLK_DOUT_HSI2_MMC_CARD, "dout_cmu_hsi2_mmc_card", "gout_cmu_hsi2_mmc_card",
+ CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD, 0, 9),
+
+ /* CSIS */
+ DIV(CLK_DOUT_CSIS, "dout_cmu_csis_bus", "gout_cmu_csis_bus",
+ CLK_CON_DIV_CLKCMU_CSIS_BUS, 0, 4),
+
+ /* PDP */
+ DIV(CLK_DOUT_PDP_BUS, "dout_cmu_pdp_bus", "gout_cmu_pdp_bus",
+ CLK_CON_DIV_CLKCMU_PDP_BUS, 0, 4),
+
+ /* IPP */
+ DIV(CLK_DOUT_IPP_BUS, "dout_cmu_ipp_bus", "gout_cmu_ipp_bus",
+ CLK_CON_DIV_CLKCMU_IPP_BUS, 0, 4),
+
+ /* G3AA */
+ DIV(CLK_DOUT_G3AA, "dout_cmu_g3aa", "gout_cmu_g3aa",
+ CLK_CON_DIV_CLKCMU_G3AA_G3AA, 0, 4),
+
+ /* ITP */
+ DIV(CLK_DOUT_ITP, "dout_cmu_itp_bus", "gout_cmu_itp_bus",
+ CLK_CON_DIV_CLKCMU_ITP_BUS, 0, 4),
+
+ /* DNS */
+ DIV(CLK_DOUT_DNS_BUS, "dout_cmu_dns_bus", "gout_cmu_dns_bus",
+ CLK_CON_DIV_CLKCMU_DNS_BUS, 0, 4),
+
+ /* TNR */
+ DIV(CLK_DOUT_TNR_BUS, "dout_cmu_tnr_bus", "gout_cmu_tnr_bus",
+ CLK_CON_DIV_CLKCMU_TNR_BUS, 0, 4),
+
+ /* MCSC*/
+ DIV(CLK_DOUT_MCSC_ITSC, "dout_cmu_mcsc_itsc", "gout_cmu_mcsc_itsc",
+ CLK_CON_DIV_CLKCMU_MCSC_ITSC, 0, 4),
+
+ DIV(CLK_DOUT_MCSC_MCSC, "dout_cmu_mcsc_mcsc", "gout_cmu_mcsc_mcsc",
+ CLK_CON_DIV_CLKCMU_MCSC_MCSC, 0, 4),
+
+ /* GDC */
+ DIV(CLK_DOUT_GDC_SCSC, "dout_cmu_gdc_scsc", "gout_cmu_gdc_scsc",
+ CLK_CON_DIV_CLKCMU_GDC_SCSC, 0, 4),
+
+ DIV(CLK_DOUT_GDC_GDC0, "dout_cmu_gdc_gdc0", "gout_cmu_gdc_gdc0",
+ CLK_CON_DIV_CLKCMU_GDC_GDC0, 0, 4),
+
+ DIV(CLK_DOUT_GDC_GDC1, "dout_cmu_gdc_gdc1", "gout_cmu_gdc_gdc1",
+ CLK_CON_DIV_CLKCMU_GDC_GDC1, 0, 4),
+
+ /* MFC */
+ DIV(CLK_DOUT_MFC_MFC, "dout_cmu_mfc_mfc", "gout_cmu_mfc_mfc",
+ CLK_CON_DIV_CLKCMU_MFC_MFC, 0, 4),
+
+ /* MIF0/1/2/3 */
+ DIV(CLK_DOUT_MIF_BUS, "dout_cmu_mif_busp", "gout_cmu_mif_busp",
+ CLK_CON_DIV_CLKCMU_MIF_BUSP, 0, 4),
+
+ /* MISC */
+ DIV(CLK_DOUT_MISC_BUS, "dout_cmu_misc_bus", "gout_cmu_misc_bus",
+ CLK_CON_DIV_CLKCMU_MISC_BUS, 0, 4),
+ DIV(CLK_DOUT_MISC_SSS, "dout_cmu_misc_sss", "gout_cmu_misc_sss",
+ CLK_CON_DIV_CLKCMU_MISC_SSS, 0, 4),
+
+ /* PERI0 */
+ DIV(CLK_DOUT_PERIC0_BUS, "dout_cmu_peric0_bus", "gout_cmu_peric0_bus",
+ CLK_CON_DIV_CLKCMU_PERIC0_BUS, 0, 4),
+ DIV(CLK_DOUT_PERIC0_IP, "dout_cmu_peric0_ip", "gout_cmu_peric0_ip",
+ CLK_CON_DIV_CLKCMU_PERIC0_IP, 0, 4),
+
+ /* PERI1 */
+ DIV(CLK_DOUT_PERIC1_BUS, "dout_cmu_peric1_bus", "gout_cmu_peric1_bus",
+ CLK_CON_DIV_CLKCMU_PERIC1_BUS, 0, 4),
+ DIV(CLK_DOUT_PERIC1_IP, "dout_cmu_peric1_ip", "gout_cmu_peric1_ip",
+ CLK_CON_DIV_CLKCMU_PERIC1_IP, 0, 4),
+
+ /* TPU */
+ DIV(CLK_DOUT_TPU_TPU, "dout_cmu_tpu_tpu", "gout_cmu_tpu_tpu",
+ CLK_CON_DIV_CLKCMU_TPU_TPU, 0, 4),
+
+ DIV(CLK_DOUT_TPU_TPUCTL, "dout_cmu_tpu_tpuctl", "gout_cmu_tpu_tpuctl",
+ CLK_CON_DIV_CLKCMU_TPU_TPUCTL, 0, 4),
+
+ DIV(CLK_DOUT_TPU_BUS, "dout_cmu_tpu_bus", "gout_cmu_tpu_bus",
+ CLK_CON_DIV_CLKCMU_TPU_BUS, 0, 4),
+
+ DIV(CLK_DOUT_TPU_UART, "dout_cmu_tpu_uart", "gout_cmu_tpu_uart",
+ CLK_CON_DIV_CLKCMU_TPU_UART, 0, 4),
+
+ /* BO */
+ DIV(CLK_DOUT_BO_BUS, "dout_cmu_bo_bus", "gout_cmu_bo_bus",
+ CLK_CON_DIV_CLKCMU_BO_BUS, 0, 4),
+
+};
+
+static const struct samsung_gate_clock cmu_top_gate_clks[] __initconst = {
+ /* CORE */
+
+ /* MISC */
+ GATE(CLK_GOUT_MISC_BUS, "gout_cmu_misc_bus", "mout_cmu_misc_bus",
+ CLK_CON_GAT_GATE_CLKCMU_MISC_BUS, 21, 0, 0),
+ GATE(CLK_GOUT_MISC_SSS, "gout_cmu_misc_sss", "mout_cmu_misc_sss",
+ CLK_CON_GAT_GATE_CLKCMU_MISC_SSS, 21, 0, 0),
+
+ /* BUS0 */
+ GATE(CLK_GOUT_BUS0_BUS, "gout_cmu_bus0_bus", "mout_cmu_bus0_bus",
+ CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS, 21, 0, 0),
+
+ /* BUS1 */
+ GATE(CLK_GOUT_BUS1_BUS, "gout_cmu_bus1_bus", "mout_cmu_bus1_bus",
+ CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS, 21, 0, 0),
+
+ /* BUS2 */
+ GATE(CLK_GOUT_BUS2_BUS, "gout_cmu_bus2_bus", "mout_cmu_bus2_bus",
+ CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS, 21, 0, 0),
+
+ /* CORE */
+ GATE(CLK_GOUT_CORE_BUS, "gout_cmu_core_bus", "mout_cmu_core_bus",
+ CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0),
+
+ /* EH */
+ GATE(CLK_GOUT_EH_BUS, "gout_cmu_eh_bus", "mout_cmu_eh_bus",
+ CLK_CON_GAT_GATE_CLKCMU_EH_BUS, 21, 0, 0),
+
+ /* CPUCL{0,1,2,} */
+ GATE(CLK_GOUT_CPUCL2_SWITCH, "gout_cmu_cpucl2_switch", "mout_cmu_cpucl2_switch",
+ CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH, 21, 0, 0),
+
+ GATE(CLK_GOUT_CPUCL1_SWITCH, "gout_cmu_cpucl1_switch", "mout_cmu_cpucl1_switch",
+ CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, 21, 0, 0),
+
+ GATE(CLK_GOUT_CPUCL0_SWITCH, "gout_cmu_cpucl0_switch", "mout_cmu_cpucl0_switch",
+ CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, 21, 0, 0),
+
+ GATE(CLK_GOUT_CPUCL0_DBG, "gout_cmu_cpucl0_dbg", "mout_cmu_cpucl0_dbg",
+ CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS, 21, 0, 0),
+
+ GATE(CLK_GOUT_CMU_HPM, "gout_cmu_hpm", "mout_cmu_hpm",
+ CLK_CON_GAT_GATE_CLKCMU_HPM, 21, 0, 0),
+
+ /* G3D */
+ GATE(CLK_GOUT_G3D_SWITCH, "gout_cmu_g3d_switch", "mout_cmu_g3d_switch",
+ CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 21, 0, 0),
+
+ GATE(CLK_GOUT_G3D_SWITCH, "gout_cmu_g3d_busd", "mout_cmu_g3d_busd",
+ CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD, 21, 0, 0),
+
+ GATE(CLK_GOUT_G3D_GLB, "gout_cmu_g3d_glb", "mout_cmu_g3d_glb",
+ CLK_CON_GAT_GATE_CLKCMU_G3D_GLB, 21, 0, 0),
+ /* DPU */
+ GATE(CLK_GOUT_DPU_BUS, "gout_cmu_dpu_bus", "mout_cmu_dpu_bus",
+ CLK_CON_GAT_GATE_CLKCMU_DPU_BUS, 21, 0, 0),
+ /* DISP */
+ GATE(CLK_GOUT_DISP_BUS, "gout_cmu_disp_bus", "mout_cmu_disp_bus",
+ CLK_CON_GAT_GATE_CLKCMU_DISP_BUS, 21, 0, 0),
+
+ /* G2D */
+ GATE(CLK_GOUT_G2D_G2D, "gout_cmu_g2d_g2d", "mout_cmu_g2d_g2d",
+ CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 21, 0, 0),
+
+ GATE(CLK_GOUT_G2D_MSCL, "gout_cmu_g2d_mscl", "mout_cmu_g2d_mscl",
+ CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL, 21, 0, 0),
+ /* HSI0 */
+ GATE(CLK_GOUT_HSI0_USB31DRD, "gout_cmu_hsi0_usb31drd", "mout_cmu_hsi0_usb31drd",
+ CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD, 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI0_BUS, "gout_cmu_hsi0_bus", "mout_cmu_hsi0_bus",
+ CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS, 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI0_DPGTC, "gout_cmu_hsi0_dpgtc", "mout_cmu_hsi0_dpgtc",
+ CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC, 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI0_USBDPDGB, "gout_cmu_hsi0_usbdpdbg", "mout_cmu_hsi0_usbdpdbg",
+ CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG, 21, 0, 0),
+ /* HSI1 */
+ GATE(CLK_GOUT_HSI1_BUS, "gout_cmu_hsi1_bus", "mout_cmu_hsi1_bus",
+ CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS, 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI1_PCIE, "gout_cmu_hsi1_pcie", "mout_cmu_hsi1_pcie",
+ CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE, 21, 0, 0),
+ /* HSI2 */
+ GATE(CLK_GOUT_HSI2_BUS, "gout_cmu_hsi2_bus", "mout_cmu_hsi2_bus",
+ CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS, 21, 0, 0),
+ GATE(CLK_GOUT_HSI2_PCIE, "gout_cmu_hsi2_pcie", "mout_cmu_hsi2_pcie",
+ CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE, 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_UFS_EMBD, "gout_cmu_hsi2_ufs_embd", "mout_cmu_hsi2_ufs_embd",
+ CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD, 21, 0, 0),
+ GATE(CLK_GOUT_HSI2_MMC_CARD, "gout_cmu_hsi2_mmc_card", "mout_cmu_hsi2_mmc_card",
+ CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD, 21, 0, 0),
+ /* CSIS */
+ GATE(CLK_GOUT_CSIS, "gout_cmu_csis_bus", "mout_cmu_csis_bus",
+ CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS, 21, 0, 0),
+ /* PDP */
+ GATE(CLK_GOUT_PDP_BUS, "gout_cmu_pdp_bus", "mout_cmu_pdp_bus",
+ CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 21, 0, 0),
+
+ /* IPP */
+ GATE(CLK_GOUT_IPP_BUS, "gout_cmu_ipp_bus", "mout_cmu_ipp_bus",
+ CLK_CON_GAT_GATE_CLKCMU_IPP_BUS, 21, 0, 0),
+ /* G3AA */
+ GATE(CLK_GOUT_G3AA, "gout_cmu_g3aa", "mout_cmu_g3aa",
+ CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 21, 0, 0),
+
+ /* ITP */
+ GATE(CLK_GOUT_ITP, "gout_cmu_itp_bus", "mout_cmu_itp_bus",
+ CLK_CON_GAT_GATE_CLKCMU_ITP_BUS, 21, 0, 0),
+
+ /* DNS */
+ GATE(CLK_GOUT_DNS_BUS, "gout_cmu_dns_bus", "mout_cmu_dns_bus",
+ CLK_CON_GAT_GATE_CLKCMU_DNS_BUS, 21, 0, 0),
+
+ /* TNR */
+ GATE(CLK_GOUT_TNR_BUS, "gout_cmu_tnr_bus", "mout_cmu_tnr_bus",
+ CLK_CON_GAT_GATE_CLKCMU_TNR_BUS, 21, 0, 0),
+
+ /* MCSC*/
+ GATE(CLK_GOUT_MCSC_ITSC, "gout_cmu_mcsc_itsc", "mout_cmu_mcsc_itsc",
+ CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC, 21, 0, 0),
+
+ GATE(CLK_GOUT_MCSC_MCSC, "gout_cmu_mcsc_mcsc", "mout_cmu_mcsc_mcsc",
+ CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC, 21, 0, 0),
+
+ /* GDC */
+ GATE(CLK_GOUT_GDC_SCSC, "gout_cmu_gdc_scsc", "mout_cmu_gdc_scsc",
+ CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC, 21, 0, 0),
+
+ GATE(CLK_GOUT_GDC_GDC0, "gout_cmu_gdc_gdc0", "mout_cmu_gdc_gdc0",
+ CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0, 21, 0, 0),
+
+ GATE(CLK_GOUT_GDC_GDC1, "gout_cmu_gdc_gdc1", "mout_cmu_gdc_gdc1",
+ CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1, 21, 0, 0),
+
+ /* MFC */
+ GATE(CLK_GOUT_MFC_MFC, "gout_cmu_mfc_mfc", "mout_cmu_mfc_mfc",
+ CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, 21, 0, 0),
+
+ /* DDRPHY0/1/2/3 */
+ GATE(CLK_GOUT_MIF_SWITCH, "gout_cmu_mif_switch", "mout_cmu_mif_switch",
+ CLK_CON_GAT_CLKCMU_MIF_SWITCH, 21, 0, 0),
+
+ /* MIF0/1/2/3 */
+ GATE(CLK_GOUT_MIF_BUS, "gout_cmu_mif_busp", "mout_cmu_mif_busp",
+ CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP, 21, 0, 0),
+
+ GATE(CLK_GOUT_CMU_BOOST, "gout_cmu_cmu_boost", "mout_cmu_boost",
+ CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST, 21, 0, 0),
+
+ /* MISC */
+ GATE(CLK_GOUT_MISC_BUS, "gout_cmu_misc_bus", "mout_cmu_misc_bus",
+ CLK_CON_GAT_GATE_CLKCMU_MISC_BUS, 21, 0, 0),
+ GATE(CLK_GOUT_MISC_SSS, "gout_cmu_misc_sss", "mout_cmu_misc_sss",
+ CLK_CON_GAT_GATE_CLKCMU_MISC_SSS, 21, 0, 0),
+
+ /* PERI0 */
+ GATE(CLK_GOUT_PERIC0_BUS, "gout_cmu_peric0_bus", "mout_cmu_peric0_bus",
+ CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS, 21, 0, 0),
+ GATE(CLK_GOUT_PERIC0_IP, "gout_cmu_peric0_ip", "mout_cmu_peric0_ip",
+ CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP, 21, 0, 0),
+
+ /* PERI1 */
+ GATE(CLK_GOUT_PERIC1_BUS, "gout_cmu_peric1_bus", "mout_cmu_peric1_bus",
+ CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS, 21, 0, 0),
+ GATE(CLK_GOUT_PERIC1_IP, "gout_cmu_peric1_ip", "mout_cmu_peric1_ip",
+ CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP, 21, 0, 0),
+
+ /* TPU */
+ GATE(CLK_GOUT_TPU_TPU, "gout_cmu_tpu_tpu", "mout_cmu_tpu_tpu",
+ CLK_CON_GAT_GATE_CLKCMU_TPU_TPU, 21, 0, 0),
+ GATE(CLK_GOUT_TPU_TPUCTL, "gout_cmu_tpu_tpuctl", "mout_cmu_tpu_tpuctl",
+ CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL, 21, 0, 0),
+ GATE(CLK_GOUT_TPU_BUS, "gout_cmu_tpu_bus", "mout_cmu_tpu_bus",
+ CLK_CON_GAT_GATE_CLKCMU_TPU_BUS, 21, 0, 0),
+ GATE(CLK_GOUT_TPU_UART, "gout_cmu_tpu_uart", "mout_cmu_tpu_uart",
+ CLK_CON_GAT_GATE_CLKCMU_TPU_UART, 21, 0, 0),
+
+ /* BO */
+ GATE(CLK_GOUT_BO_BUS, "gout_cmu_bo_bus", "mout_cmu_bo_bus",
+ CLK_CON_GAT_GATE_CLKCMU_BO_BUS, 21, 0, 0),
+
+};
+
+static const struct samsung_cmu_info top_cmu_info __initconst = {
+ .pll_clks = cmu_top_pll_clks,
+ .nr_pll_clks = ARRAY_SIZE(cmu_top_pll_clks),
+ .mux_clks = cmu_top_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(cmu_top_mux_clks),
+ .div_clks = cmu_top_div_clks,
+ .nr_div_clks = ARRAY_SIZE(cmu_top_div_clks),
+ .gate_clks = cmu_top_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(cmu_top_gate_clks),
+ .nr_clk_ids = TOP_NR_CLK,
+ .clk_regs = cmu_top_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(cmu_top_clk_regs),
+};
+
+static void __init gs101_cmu_top_init(struct device_node *np)
+{
+ exynos_arm64_register_cmu(NULL, np, &top_cmu_info);
+}
+
+/* Register CMU_TOP early, as it's a dependency for other early domains */
+CLK_OF_DECLARE(gs101_cmu_top, "google,gs101-cmu-top",
+ gs101_cmu_top_init);
--
2.42.0.582.g8ccd20d70d-goog
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^ permalink raw reply related [flat|nested] 150+ messages in thread* Re: [PATCH 13/21] clk: samsung: clk-gs101: Add cmu_top registers, plls, mux and gates
2023-10-05 15:56 ` Peter Griffin
@ 2023-10-05 17:42 ` William McVicker
-1 siblings, 0 replies; 150+ messages in thread
From: William McVicker @ 2023-10-05 17:42 UTC (permalink / raw)
To: Peter Griffin
Cc: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi, tudor.ambarus,
andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog, kernel-team
On 10/05/2023, Peter Griffin wrote:
> CMU_TOP is the top level clock management unit which contains PLLs, muxes
> and gates that feed the other clock management units.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> drivers/clk/samsung/Kconfig | 9 +
> drivers/clk/samsung/Makefile | 1 +
> drivers/clk/samsung/clk-gs101.c | 1558 +++++++++++++++++++++++++++++++
> 3 files changed, 1568 insertions(+)
> create mode 100644 drivers/clk/samsung/clk-gs101.c
>
> diff --git a/drivers/clk/samsung/Kconfig b/drivers/clk/samsung/Kconfig
> index 76a494e95027..4c8f173c4dec 100644
> --- a/drivers/clk/samsung/Kconfig
> +++ b/drivers/clk/samsung/Kconfig
> @@ -13,6 +13,7 @@ config COMMON_CLK_SAMSUNG
> select EXYNOS_5420_COMMON_CLK if ARM && SOC_EXYNOS5420
> select EXYNOS_ARM64_COMMON_CLK if ARM64 && ARCH_EXYNOS
> select TESLA_FSD_COMMON_CLK if ARM64 && ARCH_TESLA_FSD
> + select GOOGLE_GS101_COMMON_CLK if ARM64 && ARCH_GOOGLE_TENSOR
Is this patch out of order? ARCH_GOOGLE_TENSOR hasn't been defined at this
point in the series (it's defined in 18/21).
Regards,
Will
>
> config S3C64XX_COMMON_CLK
> bool "Samsung S3C64xx clock controller support" if COMPILE_TEST
> @@ -102,3 +103,11 @@ config TESLA_FSD_COMMON_CLK
> help
> Support for the clock controller present on the Tesla FSD SoC.
> Choose Y here only if you build for this SoC.
> +
> +config GOOGLE_GS101_COMMON_CLK
> + bool "Google gs101 clock controller support" if COMPILE_TEST
> + depends on COMMON_CLK_SAMSUNG
> + depends on EXYNOS_ARM64_COMMON_CLK
> + help
> + Support for the clock controller present on the Google gs101 SoC.
> + Choose Y here only if you build for this SoC.
> \ No newline at end of file
> diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
> index ebbeacabe88f..1e69b8e14324 100644
> --- a/drivers/clk/samsung/Makefile
> +++ b/drivers/clk/samsung/Makefile
> @@ -24,3 +24,4 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov9.o
> obj-$(CONFIG_S3C64XX_COMMON_CLK) += clk-s3c64xx.o
> obj-$(CONFIG_S5PV210_COMMON_CLK) += clk-s5pv210.o clk-s5pv210-audss.o
> obj-$(CONFIG_TESLA_FSD_COMMON_CLK) += clk-fsd.o
> +obj-$(CONFIG_GOOGLE_GS101_COMMON_CLK) += clk-gs101.o
> diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
> new file mode 100644
> index 000000000000..4c58fcc899be
> --- /dev/null
> +++ b/drivers/clk/samsung/clk-gs101.c
> @@ -0,0 +1,1558 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (C) 2023 Linaro Ltd.
> + * Author: Peter Griffin <peter.griffin@linaro.org>
> + *
> + * Common Clock Framework support for GS101.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +
> +#include <dt-bindings/clock/gs101.h>
> +
> +#include "clk.h"
> +#include "clk-exynos-arm64.h"
> +
> +/* NOTE: Must be equal to the last clock ID increased by one */
> +#define TOP_NR_CLK (CLK_GOUT_CMU_BOOST + 1)
> +
> +/* ---- CMU_TOP ------------------------------------------------------------- */
> +
> +/* Register Offset definitions for CMU_TOP (0x1e080000) */
> +
> +#define PLL_LOCKTIME_PLL_SHARED0 0x0000
> +#define PLL_LOCKTIME_PLL_SHARED1 0x0004
> +#define PLL_LOCKTIME_PLL_SHARED2 0x0008
> +#define PLL_LOCKTIME_PLL_SHARED3 0x000c
> +#define PLL_LOCKTIME_PLL_SPARE 0x0010
> +#define PLL_CON0_PLL_SHARED0 0x0100
> +#define PLL_CON1_PLL_SHARED0 0x0104
> +#define PLL_CON2_PLL_SHARED0 0x0108
> +#define PLL_CON3_PLL_SHARED0 0x010c
> +#define PLL_CON4_PLL_SHARED0 0x0110
> +#define PLL_CON0_PLL_SHARED1 0x0140
> +#define PLL_CON1_PLL_SHARED1 0x0144
> +#define PLL_CON2_PLL_SHARED1 0x0148
> +#define PLL_CON3_PLL_SHARED1 0x014c
> +#define PLL_CON4_PLL_SHARED1 0x0150
> +#define PLL_CON0_PLL_SHARED2 0x0180
> +#define PLL_CON1_PLL_SHARED2 0x0184
> +#define PLL_CON2_PLL_SHARED2 0x0188
> +#define PLL_CON3_PLL_SHARED2 0x018c
> +#define PLL_CON4_PLL_SHARED2 0x0190
> +#define PLL_CON0_PLL_SHARED3 0x01c0
> +#define PLL_CON1_PLL_SHARED3 0x01c4
> +#define PLL_CON2_PLL_SHARED3 0x01c8
> +#define PLL_CON3_PLL_SHARED3 0x01cc
> +#define PLL_CON4_PLL_SHARED3 0x01d0
> +#define PLL_CON0_PLL_SPARE 0x0200
> +#define PLL_CON1_PLL_SPARE 0x0204
> +#define PLL_CON2_PLL_SPARE 0x0208
> +#define PLL_CON3_PLL_SPARE 0x020c
> +#define PLL_CON4_PLL_SPARE 0x0210
> +#define CMU_CMU_TOP_CONTROLLER_OPTION 0x0800
> +#define CLKOUT_CON_BLK_CMU_CMU_TOP_CLKOUT0 0x0810
> +#define CMU_HCHGEN_CLKMUX_CMU_BOOST 0x0840
> +#define CMU_HCHGEN_CLKMUX_TOP_BOOST 0x0844
> +#define CMU_HCHGEN_CLKMUX 0x0850
> +#define POWER_FAIL_DETECT_PLL 0x0864
> +#define EARLY_WAKEUP_FORCED_0_ENABLE 0x0870
> +#define EARLY_WAKEUP_FORCED_1_ENABLE 0x0874
> +#define EARLY_WAKEUP_APM_CTRL 0x0878
> +#define EARLY_WAKEUP_CLUSTER0_CTRL 0x087c
> +#define EARLY_WAKEUP_DPU_CTRL 0x0880
> +#define EARLY_WAKEUP_CSIS_CTRL 0x0884
> +#define EARLY_WAKEUP_APM_DEST 0x0890
> +#define EARLY_WAKEUP_CLUSTER0_DEST 0x0894
> +#define EARLY_WAKEUP_DPU_DEST 0x0898
> +#define EARLY_WAKEUP_CSIS_DEST 0x089c
> +#define EARLY_WAKEUP_SW_TRIG_APM 0x08c0
> +#define EARLY_WAKEUP_SW_TRIG_APM_SET 0x08c4
> +#define EARLY_WAKEUP_SW_TRIG_APM_CLEAR 0x08c8
> +#define EARLY_WAKEUP_SW_TRIG_CLUSTER0 0x08d0
> +#define EARLY_WAKEUP_SW_TRIG_CLUSTER0_SET 0x08d4
> +#define EARLY_WAKEUP_SW_TRIG_CLUSTER0_CLEAR 0x08d8
> +#define EARLY_WAKEUP_SW_TRIG_DPU 0x08e0
> +#define EARLY_WAKEUP_SW_TRIG_DPU_SET 0x08e4
> +#define EARLY_WAKEUP_SW_TRIG_DPU_CLEAR 0x08e8
> +#define EARLY_WAKEUP_SW_TRIG_CSIS 0x08f0
> +#define EARLY_WAKEUP_SW_TRIG_CSIS_SET 0x08f4
> +#define EARLY_WAKEUP_SW_TRIG_CSIS_CLEAR 0x08f8
> +
> +#define CLK_CON_MUX_MUX_CLKCMU_BO_BUS 0x1000
> +#define CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS 0x1004
> +#define CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS 0x1008
> +#define CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS 0x100c
> +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0 0x1010
> +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1 0x1014
> +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2 0x1018
> +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3 0x101c
> +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4 0x1020
> +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5 0x1024
> +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6 0x1028
> +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7 0x102c
> +#define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST 0x1030
> +#define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1 0x1034
> +#define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1038
> +#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG 0x103c
> +#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH 0x1040
> +#define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH 0x1044
> +#define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH 0x1048
> +#define CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS 0x104c
> +#define CLK_CON_MUX_MUX_CLKCMU_DISP_BUS 0x1050
> +#define CLK_CON_MUX_MUX_CLKCMU_DNS_BUS 0x1054
> +#define CLK_CON_MUX_MUX_CLKCMU_DPU_BUS 0x1058
> +#define CLK_CON_MUX_MUX_CLKCMU_EH_BUS 0x105c
> +#define CLK_CON_MUX_MUX_CLKCMU_G2D_G2D 0x1060
> +#define CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL 0x1064
> +#define CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA 0x1068
> +#define CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD 0x106c
> +#define CLK_CON_MUX_MUX_CLKCMU_G3D_GLB 0x1070
> +#define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH 0x1074
> +#define CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0 0x1078
> +#define CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1 0x107c
> +#define CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC 0x1080
> +#define CLK_CON_MUX_MUX_CLKCMU_HPM 0x1084
> +#define CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS 0x1088
> +#define CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC 0x108c
> +#define CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD 0x1090
> +#define CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG 0x1094
> +#define CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS 0x1098
> +#define CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE 0x109c
> +#define CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS 0x10a0
> +#define CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD 0x10a4
> +#define CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE 0x10a8
> +#define CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD 0x10ac
> +#define CLK_CON_MUX_MUX_CLKCMU_IPP_BUS 0x10b0
> +#define CLK_CON_MUX_MUX_CLKCMU_ITP_BUS 0x10b4
> +#define CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC 0x10b8
> +#define CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC 0x10bc
> +#define CLK_CON_MUX_MUX_CLKCMU_MFC_MFC 0x10c0
> +#define CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP 0x10c4
> +#define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0x10c8
> +#define CLK_CON_MUX_MUX_CLKCMU_MISC_BUS 0x10cc
> +#define CLK_CON_MUX_MUX_CLKCMU_MISC_SSS 0x10d0
> +#define CLK_CON_MUX_MUX_CLKCMU_PDP_BUS 0x10d4
> +#define CLK_CON_MUX_MUX_CLKCMU_PDP_VRA 0x10d8
> +#define CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS 0x10dc
> +#define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP 0x10e0
> +#define CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS 0x10e4
> +#define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP 0x10e8
> +#define CLK_CON_MUX_MUX_CLKCMU_TNR_BUS 0x10ec
> +#define CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1 0x10f0
> +#define CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF 0x10f4
> +#define CLK_CON_MUX_MUX_CLKCMU_TPU_BUS 0x10f8
> +#define CLK_CON_MUX_MUX_CLKCMU_TPU_TPU 0x10fc
> +#define CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL 0x1100
> +#define CLK_CON_MUX_MUX_CLKCMU_TPU_UART 0x1104
> +#define CLK_CON_MUX_MUX_CMU_CMUREF 0x1108
> +
> +#define CLK_CON_DIV_CLKCMU_BO_BUS 0x1800
> +#define CLK_CON_DIV_CLKCMU_BUS0_BUS 0x1804
> +#define CLK_CON_DIV_CLKCMU_BUS1_BUS 0x1808
> +#define CLK_CON_DIV_CLKCMU_BUS2_BUS 0x180c
> +#define CLK_CON_DIV_CLKCMU_CIS_CLK0 0x1810
> +#define CLK_CON_DIV_CLKCMU_CIS_CLK1 0x1814
> +#define CLK_CON_DIV_CLKCMU_CIS_CLK2 0x1818
> +#define CLK_CON_DIV_CLKCMU_CIS_CLK3 0x181c
> +#define CLK_CON_DIV_CLKCMU_CIS_CLK4 0x1820
> +#define CLK_CON_DIV_CLKCMU_CIS_CLK5 0x1824
> +#define CLK_CON_DIV_CLKCMU_CIS_CLK6 0x1828
> +#define CLK_CON_DIV_CLKCMU_CIS_CLK7 0x182c
> +#define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1830
> +#define CLK_CON_DIV_CLKCMU_CPUCL0_DBG 0x1834
> +#define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH 0x1838
> +#define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH 0x183c
> +#define CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH 0x1840
> +#define CLK_CON_DIV_CLKCMU_CSIS_BUS 0x1844
> +#define CLK_CON_DIV_CLKCMU_DISP_BUS 0x1848
> +#define CLK_CON_DIV_CLKCMU_DNS_BUS 0x184c
> +#define CLK_CON_DIV_CLKCMU_DPU_BUS 0x1850
> +#define CLK_CON_DIV_CLKCMU_EH_BUS 0x1854
> +#define CLK_CON_DIV_CLKCMU_G2D_G2D 0x1858
> +#define CLK_CON_DIV_CLKCMU_G2D_MSCL 0x185c
> +#define CLK_CON_DIV_CLKCMU_G3AA_G3AA 0x1860
> +#define CLK_CON_DIV_CLKCMU_G3D_BUSD 0x1864
> +#define CLK_CON_DIV_CLKCMU_G3D_GLB 0x1868
> +#define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x186c
> +#define CLK_CON_DIV_CLKCMU_GDC_GDC0 0x1870
> +#define CLK_CON_DIV_CLKCMU_GDC_GDC1 0x1874
> +#define CLK_CON_DIV_CLKCMU_GDC_SCSC 0x1878
> +#define CLK_CON_DIV_CLKCMU_HPM 0x187c
> +#define CLK_CON_DIV_CLKCMU_HSI0_BUS 0x1880
> +#define CLK_CON_DIV_CLKCMU_HSI0_DPGTC 0x1884
> +#define CLK_CON_DIV_CLKCMU_HSI0_USB31DRD 0x1888
> +#define CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG 0x188c
> +#define CLK_CON_DIV_CLKCMU_HSI1_BUS 0x1890
> +#define CLK_CON_DIV_CLKCMU_HSI1_PCIE 0x1894
> +#define CLK_CON_DIV_CLKCMU_HSI2_BUS 0x1898
> +#define CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD 0x189c
> +#define CLK_CON_DIV_CLKCMU_HSI2_PCIE 0x18a0
> +#define CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD 0x18a4
> +#define CLK_CON_DIV_CLKCMU_IPP_BUS 0x18a8
> +#define CLK_CON_DIV_CLKCMU_ITP_BUS 0x18ac
> +#define CLK_CON_DIV_CLKCMU_MCSC_ITSC 0x18b0
> +#define CLK_CON_DIV_CLKCMU_MCSC_MCSC 0x18b4
> +#define CLK_CON_DIV_CLKCMU_MFC_MFC 0x18b8
> +#define CLK_CON_DIV_CLKCMU_MIF_BUSP 0x18bc
> +#define CLK_CON_DIV_CLKCMU_MISC_BUS 0x18c0
> +#define CLK_CON_DIV_CLKCMU_MISC_SSS 0x18c4
> +#define CLK_CON_DIV_CLKCMU_OTP 0x18c8
> +#define CLK_CON_DIV_CLKCMU_PDP_BUS 0x18cc
> +#define CLK_CON_DIV_CLKCMU_PDP_VRA 0x18d0
> +#define CLK_CON_DIV_CLKCMU_PERIC0_BUS 0x18d4
> +#define CLK_CON_DIV_CLKCMU_PERIC0_IP 0x18d8
> +#define CLK_CON_DIV_CLKCMU_PERIC1_BUS 0x18dc
> +#define CLK_CON_DIV_CLKCMU_PERIC1_IP 0x18e0
> +#define CLK_CON_DIV_CLKCMU_TNR_BUS 0x18e4
> +#define CLK_CON_DIV_CLKCMU_TPU_BUS 0x18e8
> +#define CLK_CON_DIV_CLKCMU_TPU_TPU 0x18ec
> +#define CLK_CON_DIV_CLKCMU_TPU_TPUCTL 0x18f0
> +#define CLK_CON_DIV_CLKCMU_TPU_UART 0x18f4
> +#define CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST 0x18f8
> +#define CLK_CON_DIV_DIV_CLK_CMU_CMUREF 0x18fc
> +#define CLK_CON_DIV_PLL_SHARED0_DIV2 0x1900
> +#define CLK_CON_DIV_PLL_SHARED0_DIV3 0x1904
> +#define CLK_CON_DIV_PLL_SHARED0_DIV4 0x1908
> +#define CLK_CON_DIV_PLL_SHARED0_DIV5 0x190c
> +#define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1910
> +#define CLK_CON_DIV_PLL_SHARED1_DIV3 0x1914
> +#define CLK_CON_DIV_PLL_SHARED1_DIV4 0x1918
> +#define CLK_CON_DIV_PLL_SHARED2_DIV2 0x191c
> +#define CLK_CON_DIV_PLL_SHARED3_DIV2 0x1920
> +
> +/* CLK_CON_GAT_UPDATES */
> +#define CLK_CON_GAT_CLKCMU_BUS0_BOOST 0x2000
> +#define CLK_CON_GAT_CLKCMU_BUS1_BOOST 0x2004
> +#define CLK_CON_GAT_CLKCMU_BUS2_BOOST 0x2008
> +#define CLK_CON_GAT_CLKCMU_CORE_BOOST 0x200c
> +#define CLK_CON_GAT_CLKCMU_CPUCL0_BOOST 0x2010
> +#define CLK_CON_GAT_CLKCMU_CPUCL1_BOOST 0x2014
> +#define CLK_CON_GAT_CLKCMU_CPUCL2_BOOST 0x2018
> +#define CLK_CON_GAT_CLKCMU_MIF_BOOST 0x201c
> +#define CLK_CON_GAT_CLKCMU_MIF_SWITCH 0x2020
> +#define CLK_CON_GAT_GATE_CLKCMU_BO_BUS 0x2024
> +#define CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS 0x2028
> +#define CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS 0x202c
> +#define CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS 0x2030
> +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0 0x2034
> +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1 0x2038
> +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2 0x203c
> +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3 0x2040
> +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4 0x2044
> +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5 0x2048
> +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6 0x204c
> +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7 0x2050
> +#define CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST 0x2054
> +#define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x2058
> +#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS 0x205c
> +#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH 0x2060
> +#define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH 0x2064
> +#define CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH 0x2068
> +#define CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS 0x206c
> +#define CLK_CON_GAT_GATE_CLKCMU_DISP_BUS 0x2070
> +#define CLK_CON_GAT_GATE_CLKCMU_DNS_BUS 0x2074
> +#define CLK_CON_GAT_GATE_CLKCMU_DPU_BUS 0x2078
> +#define CLK_CON_GAT_GATE_CLKCMU_EH_BUS 0x207c
> +#define CLK_CON_GAT_GATE_CLKCMU_G2D_G2D 0x2080
> +#define CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL 0x2084
> +#define CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA 0x2088
> +#define CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD 0x208c
> +#define CLK_CON_GAT_GATE_CLKCMU_G3D_GLB 0x2090
> +#define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH 0x2094
> +#define CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0 0x2098
> +#define CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1 0x209c
> +#define CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC 0x20a0
> +#define CLK_CON_GAT_GATE_CLKCMU_HPM 0x20a4
> +#define CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS 0x20a8
> +#define CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC 0x20ac
> +#define CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD 0x20b0
> +#define CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG 0x20b4
> +#define CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS 0x20b8
> +#define CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE 0x20bc
> +#define CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS 0x20c0
> +#define CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD 0x20c4
> +#define CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE 0x20c8
> +#define CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD 0x20cc
> +#define CLK_CON_GAT_GATE_CLKCMU_IPP_BUS 0x20d0
> +#define CLK_CON_GAT_GATE_CLKCMU_ITP_BUS 0x20d4
> +#define CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC 0x20d8
> +#define CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC 0x20dc
> +#define CLK_CON_GAT_GATE_CLKCMU_MFC_MFC 0x20e0
> +#define CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP 0x20e4
> +#define CLK_CON_GAT_GATE_CLKCMU_MISC_BUS 0x20e8
> +#define CLK_CON_GAT_GATE_CLKCMU_MISC_SSS 0x20ec
> +#define CLK_CON_GAT_GATE_CLKCMU_PDP_BUS 0x20f0
> +#define CLK_CON_GAT_GATE_CLKCMU_PDP_VRA 0x20f4
> +#define CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS 0x20f8
> +#define CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP 0x20fc
> +#define CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS 0x2100
> +#define CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP 0x2104
> +#define CLK_CON_GAT_GATE_CLKCMU_TNR_BUS 0x2108
> +#define CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF 0x210c
> +#define CLK_CON_GAT_GATE_CLKCMU_TPU_BUS 0x2110
> +#define CLK_CON_GAT_GATE_CLKCMU_TPU_TPU 0x2114
> +#define CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL 0x2118
> +#define CLK_CON_GAT_GATE_CLKCMU_TPU_UART 0x211c
> +
> +#define DMYQCH_CON_CMU_TOP_CMUREF_QCH 0x3000
> +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0 0x3004
> +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1 0x3008
> +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2 0x300c
> +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3 0x3010
> +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4 0x3014
> +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5 0x3018
> +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6 0x301c
> +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7 0x3020
> +#define DMYQCH_CON_OTP_QCH 0x3024
> +#define QUEUE_CTRL_REG_BLK_CMU_CMU_TOP 0x3c00
> +#define QUEUE_ENTRY0_BLK_CMU_CMU_TOP 0x3c10
> +#define QUEUE_ENTRY1_BLK_CMU_CMU_TOP 0x3c14
> +#define QUEUE_ENTRY2_BLK_CMU_CMU_TOP 0x3c18
> +#define QUEUE_ENTRY3_BLK_CMU_CMU_TOP 0x3c1c
> +#define QUEUE_ENTRY4_BLK_CMU_CMU_TOP 0x3c20
> +#define QUEUE_ENTRY5_BLK_CMU_CMU_TOP 0x3c24
> +#define QUEUE_ENTRY6_BLK_CMU_CMU_TOP 0x3c28
> +#define QUEUE_ENTRY7_BLK_CMU_CMU_TOP 0x3c2c
> +#define MIFMIRROR_QUEUE_CTRL_REG 0x3e00
> +#define MIFMIRROR_QUEUE_ENTRY0 0x3e10
> +#define MIFMIRROR_QUEUE_ENTRY1 0x3e14
> +#define MIFMIRROR_QUEUE_ENTRY2 0x3e18
> +#define MIFMIRROR_QUEUE_ENTRY3 0x3e1c
> +#define MIFMIRROR_QUEUE_ENTRY4 0x3e20
> +#define MIFMIRROR_QUEUE_ENTRY5 0x3e24
> +#define MIFMIRROR_QUEUE_ENTRY6 0x3e28
> +#define MIFMIRROR_QUEUE_ENTRY7 0x3e2c
> +#define MIFMIRROR_QUEUE_BUSY 0x3e30
> +#define GENERALIO_ACD_CHANNEL_0 0x3f00
> +#define GENERALIO_ACD_CHANNEL_1 0x3f04
> +#define GENERALIO_ACD_CHANNEL_2 0x3f08
> +#define GENERALIO_ACD_CHANNEL_3 0x3f0c
> +#define GENERALIO_ACD_MASK 0x3f14
> +
> +static const unsigned long cmu_top_clk_regs[] __initconst = {
> + PLL_LOCKTIME_PLL_SHARED0,
> + PLL_LOCKTIME_PLL_SHARED1,
> + PLL_LOCKTIME_PLL_SHARED2,
> + PLL_LOCKTIME_PLL_SHARED3,
> + PLL_LOCKTIME_PLL_SPARE,
> + PLL_CON0_PLL_SHARED0,
> + PLL_CON1_PLL_SHARED0,
> + PLL_CON2_PLL_SHARED0,
> + PLL_CON3_PLL_SHARED0,
> + PLL_CON4_PLL_SHARED0,
> + PLL_CON0_PLL_SHARED1,
> + PLL_CON1_PLL_SHARED1,
> + PLL_CON2_PLL_SHARED1,
> + PLL_CON3_PLL_SHARED1,
> + PLL_CON4_PLL_SHARED1,
> + PLL_CON0_PLL_SHARED2,
> + PLL_CON1_PLL_SHARED2,
> + PLL_CON2_PLL_SHARED2,
> + PLL_CON3_PLL_SHARED2,
> + PLL_CON4_PLL_SHARED2,
> + PLL_CON0_PLL_SHARED3,
> + PLL_CON1_PLL_SHARED3,
> + PLL_CON2_PLL_SHARED3,
> + PLL_CON3_PLL_SHARED3,
> + PLL_CON4_PLL_SHARED3,
> + PLL_CON0_PLL_SPARE,
> + PLL_CON1_PLL_SPARE,
> + PLL_CON2_PLL_SPARE,
> + PLL_CON3_PLL_SPARE,
> + PLL_CON4_PLL_SPARE,
> + CMU_CMU_TOP_CONTROLLER_OPTION,
> + CLKOUT_CON_BLK_CMU_CMU_TOP_CLKOUT0,
> + CMU_HCHGEN_CLKMUX_CMU_BOOST,
> + CMU_HCHGEN_CLKMUX_TOP_BOOST,
> + CMU_HCHGEN_CLKMUX,
> + POWER_FAIL_DETECT_PLL,
> + EARLY_WAKEUP_FORCED_0_ENABLE,
> + EARLY_WAKEUP_FORCED_1_ENABLE,
> + EARLY_WAKEUP_APM_CTRL,
> + EARLY_WAKEUP_CLUSTER0_CTRL,
> + EARLY_WAKEUP_DPU_CTRL,
> + EARLY_WAKEUP_CSIS_CTRL,
> + EARLY_WAKEUP_APM_DEST,
> + EARLY_WAKEUP_CLUSTER0_DEST,
> + EARLY_WAKEUP_DPU_DEST,
> + EARLY_WAKEUP_CSIS_DEST,
> + EARLY_WAKEUP_SW_TRIG_APM,
> + EARLY_WAKEUP_SW_TRIG_APM_SET,
> + EARLY_WAKEUP_SW_TRIG_APM_CLEAR,
> + EARLY_WAKEUP_SW_TRIG_CLUSTER0,
> + EARLY_WAKEUP_SW_TRIG_CLUSTER0_SET,
> + EARLY_WAKEUP_SW_TRIG_CLUSTER0_CLEAR,
> + EARLY_WAKEUP_SW_TRIG_DPU,
> + EARLY_WAKEUP_SW_TRIG_DPU_SET,
> + EARLY_WAKEUP_SW_TRIG_DPU_CLEAR,
> + EARLY_WAKEUP_SW_TRIG_CSIS,
> + EARLY_WAKEUP_SW_TRIG_CSIS_SET,
> + EARLY_WAKEUP_SW_TRIG_CSIS_CLEAR,
> + CLK_CON_MUX_MUX_CLKCMU_BO_BUS,
> + CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS,
> + CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS,
> + CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS,
> + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0,
> + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1,
> + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2,
> + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3,
> + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4,
> + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5,
> + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6,
> + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7,
> + CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST,
> + CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1,
> + CLK_CON_MUX_MUX_CLKCMU_CORE_BUS,
> + CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG,
> + CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
> + CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
> + CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH,
> + CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS,
> + CLK_CON_MUX_MUX_CLKCMU_DISP_BUS,
> + CLK_CON_MUX_MUX_CLKCMU_DNS_BUS,
> + CLK_CON_MUX_MUX_CLKCMU_DPU_BUS,
> + CLK_CON_MUX_MUX_CLKCMU_EH_BUS,
> + CLK_CON_MUX_MUX_CLKCMU_G2D_G2D,
> + CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL,
> + CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA,
> + CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD,
> + CLK_CON_MUX_MUX_CLKCMU_G3D_GLB,
> + CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH,
> + CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0,
> + CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1,
> + CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC,
> + CLK_CON_MUX_MUX_CLKCMU_HPM,
> + CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS,
> + CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC,
> + CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD,
> + CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG,
> + CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS,
> + CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE,
> + CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS,
> + CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD,
> + CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE,
> + CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD,
> + CLK_CON_MUX_MUX_CLKCMU_IPP_BUS,
> + CLK_CON_MUX_MUX_CLKCMU_ITP_BUS,
> + CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC,
> + CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC,
> + CLK_CON_MUX_MUX_CLKCMU_MFC_MFC,
> + CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP,
> + CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH,
> + CLK_CON_MUX_MUX_CLKCMU_MISC_BUS,
> + CLK_CON_MUX_MUX_CLKCMU_MISC_SSS,
> + CLK_CON_MUX_MUX_CLKCMU_PDP_BUS,
> + CLK_CON_MUX_MUX_CLKCMU_PDP_VRA,
> + CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS,
> + CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP,
> + CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS,
> + CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP,
> + CLK_CON_MUX_MUX_CLKCMU_TNR_BUS,
> + CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1,
> + CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF,
> + CLK_CON_MUX_MUX_CLKCMU_TPU_BUS,
> + CLK_CON_MUX_MUX_CLKCMU_TPU_TPU,
> + CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL,
> + CLK_CON_MUX_MUX_CLKCMU_TPU_UART,
> + CLK_CON_MUX_MUX_CMU_CMUREF,
> + CLK_CON_DIV_CLKCMU_BO_BUS,
> + CLK_CON_DIV_CLKCMU_BUS0_BUS,
> + CLK_CON_DIV_CLKCMU_BUS1_BUS,
> + CLK_CON_DIV_CLKCMU_BUS2_BUS,
> + CLK_CON_DIV_CLKCMU_CIS_CLK0,
> + CLK_CON_DIV_CLKCMU_CIS_CLK1,
> + CLK_CON_DIV_CLKCMU_CIS_CLK2,
> + CLK_CON_DIV_CLKCMU_CIS_CLK3,
> + CLK_CON_DIV_CLKCMU_CIS_CLK4,
> + CLK_CON_DIV_CLKCMU_CIS_CLK5,
> + CLK_CON_DIV_CLKCMU_CIS_CLK6,
> + CLK_CON_DIV_CLKCMU_CIS_CLK7,
> + CLK_CON_DIV_CLKCMU_CORE_BUS,
> + CLK_CON_DIV_CLKCMU_CPUCL0_DBG,
> + CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH,
> + CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH,
> + CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH,
> + CLK_CON_DIV_CLKCMU_CSIS_BUS,
> + CLK_CON_DIV_CLKCMU_DISP_BUS,
> + CLK_CON_DIV_CLKCMU_DNS_BUS,
> + CLK_CON_DIV_CLKCMU_DPU_BUS,
> + CLK_CON_DIV_CLKCMU_EH_BUS,
> + CLK_CON_DIV_CLKCMU_G2D_G2D,
> + CLK_CON_DIV_CLKCMU_G2D_MSCL,
> + CLK_CON_DIV_CLKCMU_G3AA_G3AA,
> + CLK_CON_DIV_CLKCMU_G3D_BUSD,
> + CLK_CON_DIV_CLKCMU_G3D_GLB,
> + CLK_CON_DIV_CLKCMU_G3D_SWITCH,
> + CLK_CON_DIV_CLKCMU_GDC_GDC0,
> + CLK_CON_DIV_CLKCMU_GDC_GDC1,
> + CLK_CON_DIV_CLKCMU_GDC_SCSC,
> + CLK_CON_DIV_CLKCMU_HPM,
> + CLK_CON_DIV_CLKCMU_HSI0_BUS,
> + CLK_CON_DIV_CLKCMU_HSI0_DPGTC,
> + CLK_CON_DIV_CLKCMU_HSI0_USB31DRD,
> + CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG,
> + CLK_CON_DIV_CLKCMU_HSI1_BUS,
> + CLK_CON_DIV_CLKCMU_HSI1_PCIE,
> + CLK_CON_DIV_CLKCMU_HSI2_BUS,
> + CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD,
> + CLK_CON_DIV_CLKCMU_HSI2_PCIE,
> + CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD,
> + CLK_CON_DIV_CLKCMU_IPP_BUS,
> + CLK_CON_DIV_CLKCMU_ITP_BUS,
> + CLK_CON_DIV_CLKCMU_MCSC_ITSC,
> + CLK_CON_DIV_CLKCMU_MCSC_MCSC,
> + CLK_CON_DIV_CLKCMU_MFC_MFC,
> + CLK_CON_DIV_CLKCMU_MIF_BUSP,
> + CLK_CON_DIV_CLKCMU_MISC_BUS,
> + CLK_CON_DIV_CLKCMU_MISC_SSS,
> + CLK_CON_DIV_CLKCMU_OTP,
> + CLK_CON_DIV_CLKCMU_PDP_BUS,
> + CLK_CON_DIV_CLKCMU_PDP_VRA,
> + CLK_CON_DIV_CLKCMU_PERIC0_BUS,
> + CLK_CON_DIV_CLKCMU_PERIC0_IP,
> + CLK_CON_DIV_CLKCMU_PERIC1_BUS,
> + CLK_CON_DIV_CLKCMU_PERIC1_IP,
> + CLK_CON_DIV_CLKCMU_TNR_BUS,
> + CLK_CON_DIV_CLKCMU_TPU_BUS,
> + CLK_CON_DIV_CLKCMU_TPU_TPU,
> + CLK_CON_DIV_CLKCMU_TPU_TPUCTL,
> + CLK_CON_DIV_CLKCMU_TPU_UART,
> + CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST,
> + CLK_CON_DIV_DIV_CLK_CMU_CMUREF,
> + CLK_CON_DIV_PLL_SHARED0_DIV2,
> + CLK_CON_DIV_PLL_SHARED0_DIV3,
> + CLK_CON_DIV_PLL_SHARED0_DIV4,
> + CLK_CON_DIV_PLL_SHARED0_DIV5,
> + CLK_CON_DIV_PLL_SHARED1_DIV2,
> + CLK_CON_DIV_PLL_SHARED1_DIV3,
> + CLK_CON_DIV_PLL_SHARED1_DIV4,
> + CLK_CON_DIV_PLL_SHARED2_DIV2,
> + CLK_CON_DIV_PLL_SHARED3_DIV2,
> + CLK_CON_GAT_CLKCMU_BUS0_BOOST,
> + CLK_CON_GAT_CLKCMU_BUS1_BOOST,
> + CLK_CON_GAT_CLKCMU_BUS2_BOOST,
> + CLK_CON_GAT_CLKCMU_CORE_BOOST,
> + CLK_CON_GAT_CLKCMU_CPUCL0_BOOST,
> + CLK_CON_GAT_CLKCMU_CPUCL1_BOOST,
> + CLK_CON_GAT_CLKCMU_CPUCL2_BOOST,
> + CLK_CON_GAT_CLKCMU_MIF_BOOST,
> + CLK_CON_GAT_CLKCMU_MIF_SWITCH,
> + CLK_CON_GAT_GATE_CLKCMU_BO_BUS,
> + CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS,
> + CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS,
> + CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS,
> + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0,
> + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1,
> + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2,
> + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3,
> + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4,
> + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5,
> + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6,
> + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7,
> + CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST,
> + CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
> + CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS,
> + CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH,
> + CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH,
> + CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH,
> + CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS,
> + CLK_CON_GAT_GATE_CLKCMU_DISP_BUS,
> + CLK_CON_GAT_GATE_CLKCMU_DNS_BUS,
> + CLK_CON_GAT_GATE_CLKCMU_DPU_BUS,
> + CLK_CON_GAT_GATE_CLKCMU_EH_BUS,
> + CLK_CON_GAT_GATE_CLKCMU_G2D_G2D,
> + CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL,
> + CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA,
> + CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD,
> + CLK_CON_GAT_GATE_CLKCMU_G3D_GLB,
> + CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH,
> + CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0,
> + CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1,
> + CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC,
> + CLK_CON_GAT_GATE_CLKCMU_HPM,
> + CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS,
> + CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC,
> + CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD,
> + CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG,
> + CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS,
> + CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE,
> + CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS,
> + CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD,
> + CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE,
> + CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD,
> + CLK_CON_GAT_GATE_CLKCMU_IPP_BUS,
> + CLK_CON_GAT_GATE_CLKCMU_ITP_BUS,
> + CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC,
> + CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC,
> + CLK_CON_GAT_GATE_CLKCMU_MFC_MFC,
> + CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP,
> + CLK_CON_GAT_GATE_CLKCMU_MISC_BUS,
> + CLK_CON_GAT_GATE_CLKCMU_MISC_SSS,
> + CLK_CON_GAT_GATE_CLKCMU_PDP_BUS,
> + CLK_CON_GAT_GATE_CLKCMU_PDP_VRA,
> + CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS,
> + CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP,
> + CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS,
> + CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP,
> + CLK_CON_GAT_GATE_CLKCMU_TNR_BUS,
> + CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF,
> + CLK_CON_GAT_GATE_CLKCMU_TPU_BUS,
> + CLK_CON_GAT_GATE_CLKCMU_TPU_TPU,
> + CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL,
> + CLK_CON_GAT_GATE_CLKCMU_TPU_UART,
> + DMYQCH_CON_CMU_TOP_CMUREF_QCH,
> + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0,
> + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1,
> + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2,
> + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3,
> + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4,
> + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5,
> + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6,
> + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7,
> + DMYQCH_CON_OTP_QCH,
> + QUEUE_CTRL_REG_BLK_CMU_CMU_TOP,
> + QUEUE_ENTRY0_BLK_CMU_CMU_TOP,
> + QUEUE_ENTRY1_BLK_CMU_CMU_TOP,
> + QUEUE_ENTRY2_BLK_CMU_CMU_TOP,
> + QUEUE_ENTRY3_BLK_CMU_CMU_TOP,
> + QUEUE_ENTRY4_BLK_CMU_CMU_TOP,
> + QUEUE_ENTRY5_BLK_CMU_CMU_TOP,
> + QUEUE_ENTRY6_BLK_CMU_CMU_TOP,
> + QUEUE_ENTRY7_BLK_CMU_CMU_TOP,
> + MIFMIRROR_QUEUE_CTRL_REG,
> + MIFMIRROR_QUEUE_ENTRY0,
> + MIFMIRROR_QUEUE_ENTRY1,
> + MIFMIRROR_QUEUE_ENTRY2,
> + MIFMIRROR_QUEUE_ENTRY3,
> + MIFMIRROR_QUEUE_ENTRY4,
> + MIFMIRROR_QUEUE_ENTRY5,
> + MIFMIRROR_QUEUE_ENTRY6,
> + MIFMIRROR_QUEUE_ENTRY7,
> + MIFMIRROR_QUEUE_BUSY,
> + GENERALIO_ACD_CHANNEL_0,
> + GENERALIO_ACD_CHANNEL_1,
> + GENERALIO_ACD_CHANNEL_2,
> + GENERALIO_ACD_CHANNEL_3,
> + GENERALIO_ACD_MASK,
> +};
> +
> +static const struct samsung_pll_clock cmu_top_pll_clks[] __initconst = {
> + /* CMU_TOP_PURECLKCOMP */
> + PLL(pll_0517x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
> + PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0,
> + NULL),
> + PLL(pll_0517x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
> + PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1,
> + NULL),
> + PLL(pll_0518x, CLK_FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk",
> + PLL_LOCKTIME_PLL_SHARED2, PLL_CON3_PLL_SHARED2,
> + NULL),
> + PLL(pll_0518x, CLK_FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk",
> + PLL_LOCKTIME_PLL_SHARED3, PLL_CON3_PLL_SHARED3,
> + NULL),
> + PLL(pll_0518x, CLK_FOUT_SPARE_PLL, "fout_spare_pll", "oscclk",
> + PLL_LOCKTIME_PLL_SPARE, PLL_CON3_PLL_SPARE,
> + NULL),
> +};
> +
> +/* List of parent clocks for Muxes in CMU_TOP */
> +PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" };
> +PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" };
> +PNAME(mout_shared2_pll_p) = { "oscclk", "fout_shared2_pll" };
> +PNAME(mout_shared3_pll_p) = { "oscclk", "fout_shared3_pll" };
> +PNAME(mout_spare_pll_p) = { "oscclk", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_BUS0 */
> +PNAME(mout_cmu_bus0_bus_p) = { "dout_shared0_div4", "dout_shared1_div4",
> + "dout_shared2_div2", "dout_shared3_div2",
> + "fout_spare_pll" };
> +
> +PNAME(mout_cmu_cmu_boost_p) = { "dout_shared0_div4", "dout_shared1_div4",
> + "dout_shared2_div2", "dout_shared3_div2" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_BUS1 */
> +PNAME(mout_cmu_bus1_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
> + "dout_shared1_div3", "dout_shared0_div4",
> + "dout_shared1_div4", "dout_shared2_div2",
> + "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_BUS2 */
> +PNAME(mout_cmu_bus2_bus_p) = { "dout_shared0_div2", "dout_shared1_div2",
> + "fout_shared2_pll", "fout_shared3_pll",
> + "dout_shared0_div3", "dout_shared1_div3",
> + "dout_shared0_div5", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */
> +PNAME(mout_cmu_core_bus_p) = { "dout_shared0_div2", "dout_shared1_div2",
> + "fout_shared2_pll", "fout_shared3_pll",
> + "dout_shared0_div3", "dout_shared1_div3",
> + "dout_shared0_div5", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_EH */
> +PNAME(mout_cmu_eh_bus_p) = { "dout_shared0_div2", "dout_shared1_div2",
> + "fout_shared2_pll", "fout_shared3_pll",
> + "dout_shared0_div3", "dout_shared1_div3",
> + "dout_shared0_div5", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_CPUCL2 */
> +PNAME(mout_cmu_cpucl2_switch_p) = { "fout_shared1_pll", "dout_shared0_div2",
> + "dout_shared1_div2", "fout_shared2_pll",
> + "fout_shared3_pll", "dout_shared0_div3",
> + "dout_shared1_div3", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_CPUCL1 */
> +PNAME(mout_cmu_cpucl1_switch_p) = { "fout_shared1_pll", "dout_shared0_div2",
> + "dout_shared1_div2", "fout_shared2_pll",
> + "fout_shared3_pll", "dout_shared0_div3",
> + "dout_shared1_div3", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_CPUCL0 */
> +PNAME(mout_cmu_cpucl0_switch_p) = { "fout_shared1_pll", "dout_shared0_div2",
> + "dout_shared1_div2", "fout_shared2_pll",
> + "fout_shared3_pll", "dout_shared0_div3",
> + "dout_shared1_div3", "fout_spare_pll" };
> +
> +PNAME(mout_cmu_cpucl0_dbg_p) = { "fout_shared2_pll", "fout_shared3_pll",
> + "dout_shared0_div4", "dout_shared1_div4",
> + "dout_shared2_div2", "fout_spare_pll" };
> +
> +PNAME(mout_cmu_hpm_p) = { "oscclk", "dout_shared1_div3",
> + "dout_shared0_div4", "dout_shared2_div2" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_G3D */
> +PNAME(mout_cmu_g3d_switch_p) = { "fout_shared2_pll", "dout_shared0_div3",
> + "fout_shared3_pll", "dout_shared1_div3",
> + "dout_shared0_div4", "dout_shared1_div4",
> + "fout_spare_pll" };
> +
> +PNAME(mout_cmu_g3d_busd_p) = { "dout_shared0_div2", "dout_shared1_div2",
> + "fout_shared2_pll", "fout_shared3_pll",
> + "dout_shared0_div3", "dout_shared1_div3",
> + "dout_shared0_div4", "fout_spare_pll" };
> +
> +PNAME(mout_cmu_g3d_glb_p) = { "dout_shared0_div2", "dout_shared1_div2",
> + "fout_shared2_pll", "fout_shared3_pll",
> + "dout_shared0_div3", "dout_shared1_div3",
> + "dout_shared0_div4", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_DPU */
> +PNAME(mout_cmu_dpu_p) = { "dout_shared0_div3", "fout_shared3_pll",
> + "dout_shared1_div3", "dout_shared0_div4",
> + "dout_shared1_div4", "dout_shared2_div2",
> + "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_DISP */
> +PNAME(mout_cmu_disp_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
> + "dout_shared1_div3", "dout_shared0_div4",
> + "dout_shared1_div4", "dout_shared2_div2",
> + "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_G2D */
> +PNAME(mout_cmu_g2d_g2d_p) = { "dout_shared0_div3", "fout_shared3_pll",
> + "dout_shared1_div3", "dout_shared0_div4",
> + "dout_shared1_div4", "dout_shared2_div2",
> + "fout_spare_pll" };
> +
> +PNAME(mout_cmu_g2d_mscl_p) = { "dout_shared0_div4", "dout_shared1_div4",
> + "dout_shared2_div2", "dout_shared3_div2",
> + "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI0 */
> +PNAME(mout_cmu_hsi0_usb31drd_p) = { "oscclk", "dout_shared2_div2" };
> +
> +PNAME(mout_cmu_hsi0_bus_p) = { "dout_shared0_div4", "dout_shared1_div4",
> + "dout_shared2_div2", "dout_shared3_div2",
> + "fout_spare_pll" };
> +
> +PNAME(mout_cmu_hsi0_dpgtc_p) = { "oscclk", "dout_shared0_div4",
> + "dout_shared2_div2", "fout_spare_pll" };
> +
> +PNAME(mout_cmu_hsi0_usbdpdbg_p) = { "oscclk", "dout_shared2_div2" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI1 */
> +PNAME(mout_cmu_hsi1_bus_p) = { "dout_shared0_div4", "dout_shared1_div4",
> + "dout_shared2_div2", "dout_shared3_div2",
> + "fout_spare_pll" };
> +
> +PNAME(mout_cmu_hsi1_pcie_p) = { "oscclk", "dout_shared2_div2" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI2 */
> +PNAME(mout_cmu_hsi2_bus_p) = { "dout_shared0_div4", "dout_shared1_div4",
> + "dout_shared2_div2", "dout_shared3_div2",
> + "fout_spare_pll" };
> +
> +PNAME(mout_cmu_hsi2_pcie0_p) = { "oscclk", "dout_shared2_div2" };
> +
> +PNAME(mout_cmu_hsi2_ufs_embd_p) = { "oscclk", "dout_shared0_div4",
> + "dout_shared2_div2", "fout_spare_pll" };
> +
> +PNAME(mout_cmu_hsi2_mmc_card_p) = { "fout_shared2_pll", "fout_shared3_pll",
> + "dout_shared0_div4", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_CSIS */
> +PNAME(mout_cmu_csis_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
> + "dout_shared1_div3", "dout_shared0_div4",
> + "dout_shared1_div4", "dout_shared2_div2",
> + "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_PDP */
> +PNAME(mout_cmu_pdp_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
> + "dout_shared1_div3", "dout_shared0_div4",
> + "dout_shared1_div4", "dout_shared2_div2",
> + "fout_spare_pll" };
> +
> +PNAME(mout_cmu_pdp_vra_p) = { "fout_shared2_pll", "dout_shared0_div3",
> + "fout_shared3_pll", "dout_shared1_div3",
> + "dout_shared0_div4", "dout_shared1_div4",
> + "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_IPP */
> +PNAME(mout_cmu_ipp_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
> + "dout_shared1_div3", "dout_shared0_div4",
> + "dout_shared1_div4", "dout_shared2_div2",
> + "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_G3AA */
> +PNAME(mout_cmu_g3aa_p) = { "dout_shared0_div3", "fout_shared3_pll",
> + "dout_shared1_div3", "dout_shared0_div4",
> + "dout_shared1_div4", "dout_shared2_div2",
> + "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_ITP */
> +PNAME(mout_cmu_itp_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
> + "dout_shared1_div3", "dout_shared0_div4",
> + "dout_shared1_div4", "dout_shared2_div2",
> + "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_DNS */
> +PNAME(mout_cmu_dns_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
> + "dout_shared1_div3", "dout_shared0_div4",
> + "dout_shared1_div4", "dout_shared2_div2",
> + "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_TNR */
> +PNAME(mout_cmu_tnr_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
> + "dout_shared1_div3", "dout_shared0_div4",
> + "dout_shared1_div4", "dout_shared2_div2",
> + "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_MCSC */
> +PNAME(mout_cmu_mcsc_itsc_p) = { "dout_shared0_div3", "fout_shared3_pll",
> + "dout_shared1_div3", "dout_shared0_div4",
> + "dout_shared1_div4", "dout_shared2_div2",
> + "fout_spare_pll" };
> +
> +PNAME(mout_cmu_mcsc_mcsc_p) = { "dout_shared0_div3", "fout_shared3_pll",
> + "dout_shared1_div3", "dout_shared0_div4",
> + "dout_shared1_div4", "dout_shared2_div2",
> + "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_GDC */
> +PNAME(mout_cmu_gdc_scsc_p) = { "dout_shared0_div3", "fout_shared3_pll",
> + "dout_shared1_div3", "dout_shared0_div4",
> + "dout_shared1_div4", "dout_shared2_div2",
> + "fout_spare_pll" };
> +
> +PNAME(mout_cmu_gdc_gdc0_p) = { "dout_shared0_div3", "fout_shared3_pll",
> + "dout_shared1_div3", "dout_shared0_div4",
> + "dout_shared1_div4", "dout_shared2_div2",
> + "fout_spare_pll" };
> +
> +PNAME(mout_cmu_gdc_gdc1_p) = { "dout_shared0_div3", "fout_shared3_pll",
> + "dout_shared1_div3", "dout_shared0_div4",
> + "dout_shared1_div4", "dout_shared2_div2",
> + "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_MFC */
> +PNAME(mout_cmu_mfc_mfc_p) = { "dout_shared0_div3", "fout_shared3_pll",
> + "dout_shared1_div3", "dout_shared0_div4",
> + "dout_shared1_div4", "dout_shared2_div2",
> + "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for DDRPHY0/1/2/3 */
> +
> +PNAME(mout_cmu_mif_switch_p) = { "fout_shared0_pll", "fout_shared1_pll",
> + "dout_shared0_div2", "dout_shared1_div2",
> + "fout_shared2_pll", "dout_shared0_div3",
> + "fout_shared3_pll", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_MIF0/1/2/3 */
> +PNAME(mout_cmu_mif_busp_p) = { "dout_shared0_div4", "dout_shared1_div4",
> + "dout_shared0_div5", "fout_spare_pll" };
> +
> +PNAME(mout_cmu_boost_p) = { "dout_shared0_div4", "dout_shared1_div4",
> + "dout_shared2_div2", "dout_shared3_div2" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_MISC */
> +PNAME(mout_cmu_misc_bus_p) = { "dout_shared0_div4", "dout_shared2_div2",
> + "dout_shared3_div2", "fout_spare_pll" };
> +PNAME(mout_cmu_misc_sss_p) = { "dout_shared0_div4", "dout_shared2_div2",
> + "dout_shared3_div2", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_PERIC0 */
> +PNAME(mout_cmu_peric0_bus_p) = { "dout_shared0_div4", "dout_shared2_div2",
> + "dout_shared3_div2", "fout_spare_pll" };
> +PNAME(mout_cmu_peric0_ip_p) = { "dout_shared0_div4", "dout_shared2_div2",
> + "dout_shared3_div2", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_PERIC1 */
> +PNAME(mout_cmu_peric1_bus_p) = { "dout_shared0_div4", "dout_shared2_div2",
> + "dout_shared3_div2", "fout_spare_pll" };
> +PNAME(mout_cmu_peric1_ip_p) = { "dout_shared0_div4", "dout_shared2_div2",
> + "dout_shared3_div2", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_TPU */
> +PNAME(mout_cmu_tpu_tpu_p) = { "dout_shared0_div2", "dout_shared1_div2",
> + "fout_shared2_pll", "fout_shared3_pll",
> + "dout_shared0_div3", "dout_shared1_div3",
> + "dout_shared0_div4", "fout_spare_pll" };
> +
> +PNAME(mout_cmu_tpu_tpuctl_p) = { "dout_shared0_div2", "dout_shared1_div2",
> + "fout_shared2_pll", "fout_shared3_pll",
> + "dout_shared0_div3", "dout_shared1_div3",
> + "dout_shared0_div4", "fout_spare_pll" };
> +
> +PNAME(mout_cmu_tpu_bus_p) = { "dout_shared0_div2", "dout_shared1_div2",
> + "fout_shared2_pll", "fout_shared3_pll",
> + "dout_shared0_div3", "dout_shared1_div3",
> + "dout_shared0_div4", "fout_spare_pll" };
> +
> +PNAME(mout_cmu_tpu_uart_p) = { "dout_shared0_div4", "dout_shared2_div2",
> + "dout_shared3_div2", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_BO */
> +PNAME(mout_cmu_bo_bus_p) = { "fout_shared2_pll", "dout_shared0_div3",
> + "fout_shared3_pll", "dout_shared1_div3",
> + "dout_shared0_div4", "dout_shared1_div4",
> + "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_G2D */
> +PNAME(mout_cmu_g2d_p) = { "dout_shared0_div3", "fout_shared3_pll",
> + "dout_shared1_div3", "dout_shared0_div4",
> + "dout_shared1_div4", "dout_shared2_div2",
> + "fout_spare_pll" };
> +
> +/* gs101 */
> +static const struct samsung_mux_clock cmu_top_mux_clks[] __initconst = {
> + /* CMU_TOP_PURECLKCOMP */
> + MUX(CLK_MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p,
> + PLL_CON0_PLL_SHARED0, 4, 1),
> + MUX(CLK_MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p,
> + PLL_CON0_PLL_SHARED1, 4, 1),
> + MUX(CLK_MOUT_SHARED2_PLL, "mout_shared2_pll", mout_shared2_pll_p,
> + PLL_CON0_PLL_SHARED2, 4, 1),
> + MUX(CLK_MOUT_SHARED3_PLL, "mout_shared3_pll", mout_shared3_pll_p,
> + PLL_CON0_PLL_SHARED3, 4, 1),
> + MUX(CLK_MOUT_SPARE_PLL, "mout_spare_pll", mout_spare_pll_p,
> + PLL_CON0_PLL_SPARE, 4, 1),
> +
> + /* BUS0 */
> + MUX(CLK_MOUT_BUS0_BUS, "mout_cmu_bus0_bus", mout_cmu_bus0_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS, 0, 2),
> + MUX(CLK_MOUT_CMU_BOOST, "mout_cmu_boost", mout_cmu_cmu_boost_p,
> + CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0, 2),
> +
> + /* BUS1 */
> + MUX(CLK_MOUT_BUS1_BUS, "mout_cmu_bus1_bus", mout_cmu_bus1_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS, 0, 2),
> +
> + /* BUS2 */
> + MUX(CLK_MOUT_BUS2_BUS, "mout_cmu_bus2_bus", mout_cmu_bus2_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS, 0, 2),
> +
> + /* CORE */
> + MUX(CLK_MOUT_CORE_BUS, "mout_cmu_core_bus", mout_cmu_core_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
> +
> + /* EH */
> + MUX(CLK_MOUT_EH_BUS, "mout_cmu_eh_bus", mout_cmu_eh_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
> +
> + /* CPUCL{0,1,2,} */
> + MUX(CLK_MOUT_CPUCL2_SWITCH, "mout_cmu_cpucl2_switch", mout_cmu_cpucl2_switch_p,
> + CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH, 0, 2),
> +
> + MUX(CLK_MOUT_CPUCL1_SWITCH, "mout_cmu_cpucl1_switch", mout_cmu_cpucl1_switch_p,
> + CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, 0, 2),
> +
> + MUX(CLK_MOUT_CPUCL0_SWITCH, "mout_cmu_cpucl0_switch", mout_cmu_cpucl0_switch_p,
> + CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, 0, 2),
> +
> + MUX(CLK_MOUT_CPUCL0_DBG, "mout_cmu_cpucl0_dbg", mout_cmu_cpucl0_dbg_p,
> + CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 2),
> +
> + MUX(CLK_MOUT_CMU_HPM, "mout_cmu_hpm", mout_cmu_hpm_p,
> + CLK_CON_MUX_MUX_CLKCMU_HPM, 0, 2),
> +
> + /* G3D */
> + MUX(CLK_MOUT_G3D_SWITCH, "mout_cmu_g3d_switch", mout_cmu_g3d_switch_p,
> + CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0, 2),
> +
> + MUX(CLK_MOUT_G3D_BUSD, "mout_cmu_g3d_busd", mout_cmu_g3d_busd_p,
> + CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD, 0, 2),
> +
> + MUX(CLK_MOUT_G3D_GLB, "mout_cmu_g3d_glb", mout_cmu_g3d_glb_p,
> + CLK_CON_MUX_MUX_CLKCMU_G3D_GLB, 0, 2),
> + /* DPU */
> + MUX(CLK_MOUT_DPU_BUS, "mout_cmu_dpu_bus", mout_cmu_dpu_p,
> + CLK_CON_MUX_MUX_CLKCMU_DPU_BUS, 0, 2),
> +
> + /* DISP */
> + MUX(CLK_MOUT_DISP_BUS, "mout_cmu_disp_bus", mout_cmu_disp_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_DISP_BUS, 0, 2),
> +
> + /* G2D */
> + MUX(CLK_MOUT_G2D_G2D, "mout_cmu_g2d_g2d", mout_cmu_g2d_g2d_p,
> + CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 0, 2),
> +
> + MUX(CLK_MOUT_G2D_MSCL, "mout_cmu_g2d_mscl", mout_cmu_g2d_mscl_p,
> + CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0, 2),
> +
> + /* HSI0 */
> + MUX(CLK_MOUT_HSI0_USB31DRD, "mout_cmu_hsi0_usb31drd", mout_cmu_hsi0_usb31drd_p,
> + CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD, 0, 2),
> +
> + MUX(CLK_MOUT_HSI0_BUS, "mout_cmu_hsi0_bus", mout_cmu_hsi0_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS, 0, 2),
> +
> + MUX(CLK_MOUT_HSI0_DPGTC, "mout_cmu_hsi0_dpgtc", mout_cmu_hsi0_dpgtc_p,
> + CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC, 0, 2),
> +
> + MUX(CLK_MOUT_HSI0_USBDPDGB, "mout_cmu_hsi0_usbdpdbg", mout_cmu_hsi0_usbdpdbg_p,
> + CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG, 0, 2),
> +
> + /* HSI1 */
> + MUX(CLK_MOUT_HSI1_BUS, "mout_cmu_hsi1_bus", mout_cmu_hsi1_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS, 0, 2),
> +
> + MUX(CLK_MOUT_HSI1_PCIE, "mout_cmu_hsi1_pcie", mout_cmu_hsi1_pcie_p,
> + CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE, 0, 2),
> + /* HSI2 */
> + MUX(CLK_MOUT_HSI2_BUS, "mout_cmu_hsi2_bus", mout_cmu_hsi2_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS, 0, 2),
> +
> + MUX(CLK_MOUT_HSI2_PCIE, "mout_cmu_hsi2_pcie", mout_cmu_hsi2_pcie0_p,
> + CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE, 0, 2),
> +
> + MUX(CLK_MOUT_HSI2_UFS_EMBD, "mout_cmu_hsi2_ufs_embd", mout_cmu_hsi2_ufs_embd_p,
> + CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD, 0, 2),
> +
> + MUX(CLK_MOUT_HSI2_MMC_CARD, "mout_cmu_hsi2_mmc_card", mout_cmu_hsi2_mmc_card_p,
> + CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD, 0, 2),
> +
> + /* CSIS */
> + MUX(CLK_MOUT_CSIS, "mout_cmu_csis_bus", mout_cmu_csis_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS, 0, 2),
> +
> + /* PDP */
> + MUX(CLK_MOUT_PDP_BUS, "mout_cmu_pdp_bus", mout_cmu_pdp_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_PDP_BUS, 0, 2),
> +
> + /* IPP */
> + MUX(CLK_MOUT_IPP_BUS, "mout_cmu_ipp_bus", mout_cmu_ipp_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_IPP_BUS, 0, 2),
> +
> + /* G3AA */
> + MUX(CLK_MOUT_G3AA, "mout_cmu_g3aa", mout_cmu_g3aa_p,
> + CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 0, 2),
> +
> + /* ITP */
> + MUX(CLK_MOUT_ITP, "mout_cmu_itp_bus", mout_cmu_itp_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_ITP_BUS, 0, 2),
> +
> + /* DNS */
> + MUX(CLK_MOUT_DNS_BUS, "mout_cmu_dns_bus", mout_cmu_dns_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_DNS_BUS, 0, 2),
> +
> + /* TNR */
> + MUX(CLK_MOUT_TNR_BUS, "mout_cmu_tnr_bus", mout_cmu_tnr_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, 0, 2),
> +
> + /* MCSC*/
> + MUX(CLK_MOUT_MCSC_ITSC, "mout_cmu_mcsc_itsc", mout_cmu_mcsc_itsc_p,
> + CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC, 0, 2),
> +
> + MUX(CLK_MOUT_MCSC_MCSC, "mout_cmu_mcsc_mcsc", mout_cmu_mcsc_mcsc_p,
> + CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC, 0, 2),
> +
> + /* GDC */
> + MUX(CLK_MOUT_GDC_SCSC, "mout_cmu_gdc_scsc", mout_cmu_gdc_scsc_p,
> + CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC, 0, 2),
> +
> + MUX(CLK_MOUT_GDC_GDC0, "mout_cmu_gdc_gdc0", mout_cmu_gdc_gdc0_p,
> + CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0, 0, 2),
> +
> + MUX(CLK_MOUT_GDC_GDC1, "mout_cmu_gdc_gdc1", mout_cmu_gdc_gdc1_p,
> + CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1, 0, 2),
> +
> + /* MFC */
> + MUX(CLK_MOUT_MFC_MFC, "mout_cmu_mfc_mfc", mout_cmu_mfc_mfc_p,
> + CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 0, 2),
> +
> + /* DDRPHY0/1/2/3 */
> + MUX(CLK_MOUT_MIF_SWITCH, "mout_cmu_mif_switch", mout_cmu_mif_switch_p,
> + CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0, 2),
> +
> + /* MIF0/1/2/3 */
> + MUX(CLK_MOUT_MIF_BUS, "mout_cmu_mif_busp", mout_cmu_mif_busp_p,
> + CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, 0, 2),
> +
> + /* MISC */
> + MUX(CLK_MOUT_MISC_BUS, "mout_cmu_misc_bus", mout_cmu_misc_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_MISC_BUS, 0, 2),
> + MUX(CLK_MOUT_MISC_SSS, "mout_cmu_misc_sss", mout_cmu_misc_sss_p,
> + CLK_CON_MUX_MUX_CLKCMU_MISC_SSS, 0, 2),
> +
> + /* PERI0 */
> + MUX(CLK_MOUT_PERIC0_IP, "mout_cmu_peric0_ip", mout_cmu_peric0_ip_p,
> + CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 2),
> + MUX(CLK_MOUT_PERIC0_BUS, "mout_cmu_peric0_bus", mout_cmu_peric0_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0, 2),
> + /* PERI1 */
> + MUX(CLK_MOUT_PERIC1_IP, "mout_cmu_peric1_ip", mout_cmu_peric1_ip_p,
> + CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 2),
> + MUX(CLK_MOUT_PERIC1_BUS, "mout_cmu_peric1_bus", mout_cmu_peric1_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0, 2),
> +
> + /* TPU */
> + MUX(CLK_MOUT_TPU_TPU, "mout_cmu_tpu_tpu", mout_cmu_tpu_tpu_p,
> + CLK_CON_MUX_MUX_CLKCMU_TPU_TPU, 0, 2),
> +
> + MUX(CLK_MOUT_TPU_TPUCTL, "mout_cmu_tpu_tpuctl", mout_cmu_tpu_tpuctl_p,
> + CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL, 0, 2),
> +
> + MUX(CLK_MOUT_TPU_BUS, "mout_cmu_tpu_bus", mout_cmu_tpu_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_TPU_BUS, 0, 2),
> +
> + MUX(CLK_MOUT_TPU_UART, "mout_cmu_tpu_uart", mout_cmu_tpu_uart_p,
> + CLK_CON_MUX_MUX_CLKCMU_TPU_UART, 0, 2),
> +
> + /* BO */
> + MUX(CLK_MOUT_BO_BUS, "mout_cmu_bo_bus", mout_cmu_bo_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_BO_BUS, 0, 2),
> +};
> +
> +static const struct samsung_div_clock cmu_top_div_clks[] __initconst = {
> + /* CMU_TOP_PURECLKCOMP */
> + DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "mout_shared0_pll",
> + CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
> + DIV(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2", "mout_shared0_pll",
> + CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
> + DIV(CLK_DOUT_SHARED0_DIV5, "dout_shared0_div5", "mout_shared0_pll",
> + CLK_CON_DIV_PLL_SHARED0_DIV5, 0, 2),
> + DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "dout_shared0_div2",
> + CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
> +
> + DIV(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2", "mout_shared1_pll",
> + CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
> + DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "mout_shared1_pll",
> + CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
> + DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "mout_shared1_pll",
> + CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
> +
> + DIV(CLK_DOUT_SHARED2_DIV2, "dout_shared2_div2", "mout_shared2_pll",
> + CLK_CON_DIV_PLL_SHARED2_DIV2, 0, 1),
> +
> + DIV(CLK_DOUT_SHARED3_DIV2, "dout_shared3_div2", "mout_shared3_pll",
> + CLK_CON_DIV_PLL_SHARED3_DIV2, 0, 1),
> +
> + /* BUS0 */
> + DIV(CLK_DOUT_BUS0_BUS, "dout_cmu_bus0_bus_div", "gout_cmu_bus0_bus",
> + CLK_CON_DIV_CLKCMU_BUS0_BUS, 0, 4),
> + DIV(CLK_DOUT_CMU_BOOST, "dout_cmu_boost", "gout_cmu_cmu_boost",
> + CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, 0, 2),
> +
> + /* BUS1 */
> + DIV(CLK_DOUT_BUS1_BUS, "dout_cmu_bus1_bus", "gout_cmu_bus1_bus",
> + CLK_CON_DIV_CLKCMU_BUS1_BUS, 0, 4),
> +
> + /* BUS2 */
> + DIV(CLK_DOUT_BUS2_BUS, "dout_cmu_bus2_bus", "gout_cmu_bus2_bus",
> + CLK_CON_DIV_CLKCMU_BUS2_BUS, 0, 4),
> +
> + /* CORE */
> + DIV(CLK_DOUT_CORE_BUS, "dout_cmu_core_bus", "gout_cmu_core_bus",
> + CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
> +
> + /* EH */
> + DIV(CLK_DOUT_EH_BUS, "dout_cmu_eh_bus", "gout_cmu_eh_bus",
> + CLK_CON_DIV_CLKCMU_EH_BUS, 0, 4),
> +
> + /* CPUCL{0,1,2,} */
> + DIV(CLK_DOUT_CPUCL2_SWITCH, "dout_cmu_cpucl2_switch", "gout_cmu_cpucl2_switch",
> + CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH, 0, 3),
> +
> + DIV(CLK_DOUT_CPUCL1_SWITCH, "dout_cmu_cpucl1_switch", "gout_cmu_cpucl1_switch",
> + CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0, 3),
> +
> + DIV(CLK_DOUT_CPUCL0_SWITCH, "dout_cmu_cpucl0_switch", "gout_cmu_cpucl0_switch",
> + CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3),
> +
> + DIV(CLK_DOUT_CPUCL0_DBG, "dout_cmu_cpucl0_dbg", "gout_cmu_cpucl0_dbg",
> + CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 4),
> +
> + DIV(CLK_DOUT_CMU_HPM, "dout_cmu_hpm", "gout_cmu_hpm",
> + CLK_CON_DIV_CLKCMU_HPM, 0, 2),
> +
> + /* G3D */
> + DIV(CLK_DOUT_G3D_SWITCH, "dout_cmu_g3d_switch", "gout_cmu_g3d_switch",
> + CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3),
> +
> + DIV(CLK_DOUT_G3D_SWITCH, "dout_cmu_g3d_busd", "gout_cmu_g3d_busd",
> + CLK_CON_DIV_CLKCMU_G3D_BUSD, 0, 4),
> +
> + DIV(CLK_DOUT_G3D_GLB, "dout_cmu_g3d_glb", "gout_cmu_g3d_glb",
> + CLK_CON_DIV_CLKCMU_G3D_GLB, 0, 4),
> +
> + /* DPU */
> + DIV(CLK_DOUT_DPU_BUS, "dout_cmu_dpu_bus", "gout_cmu_dpu_bus",
> + CLK_CON_DIV_CLKCMU_DPU_BUS, 0, 4),
> +
> + /* DISP */
> + DIV(CLK_DOUT_DISP_BUS, "dout_cmu_disp_bus", "gout_cmu_disp_bus",
> + CLK_CON_DIV_CLKCMU_DISP_BUS, 0, 4),
> +
> + /* G2D */
> + DIV(CLK_DOUT_G2D_G2D, "dout_cmu_g2d_g2d", "gout_cmu_g2d_g2d",
> + CLK_CON_DIV_CLKCMU_G2D_G2D, 0, 4),
> +
> + DIV(CLK_DOUT_G2D_MSCL, "dout_cmu_g2d_mscl", "gout_cmu_g2d_mscl",
> + CLK_CON_DIV_CLKCMU_G2D_MSCL, 0, 4),
> +
> + /* HSI0 */
> + DIV(CLK_DOUT_HSI0_USB31DRD, "dout_cmu_hsi0_usb31drd", "gout_cmu_hsi0_usb31drd",
> + CLK_CON_DIV_CLKCMU_HSI0_USB31DRD, 0, 5),
> +
> + DIV(CLK_DOUT_HSI0_BUS, "dout_cmu_hsi0_bus", "gout_cmu_hsi0_bus",
> + CLK_CON_DIV_CLKCMU_HSI0_BUS, 0, 4),
> +
> + DIV(CLK_DOUT_HSI0_DPGTC, "dout_cmu_hsi0_dpgtc", "gout_cmu_hsi0_dpgtc",
> + CLK_CON_DIV_CLKCMU_HSI0_DPGTC, 0, 4),
> +
> + /* TODO register exists but all lower bits are reserved */
> + DIV(CLK_DOUT_HSI0_USBDPDGB, "dout_cmu_hsi0_usbdpdbg", "gout_cmu_hsi0_usbdpdbg",
> + CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG, 0, 0),
> +
> + /* HSI1 */
> + DIV(CLK_DOUT_HSI1_BUS, "dout_cmu_hsi1_bus", "gout_cmu_hsi1_bus",
> + CLK_CON_DIV_CLKCMU_HSI1_BUS, 0, 4),
> +
> + DIV(CLK_DOUT_HSI1_PCIE, "dout_cmu_hsi1_pcie", "gout_cmu_hsi1_pcie",
> + CLK_CON_DIV_CLKCMU_HSI1_PCIE, 0, 3),
> + /* HSI2 */
> + DIV(CLK_DOUT_HSI2_BUS, "dout_cmu_hsi2_bus", "gout_cmu_hsi2_bus",
> + CLK_CON_DIV_CLKCMU_HSI2_BUS, 0, 4),
> +
> + DIV(CLK_DOUT_HSI2_PCIE, "dout_cmu_hsi2_pcie", "gout_cmu_hsi2_pcie",
> + CLK_CON_DIV_CLKCMU_HSI2_PCIE, 0, 3),
> +
> + DIV(CLK_DOUT_HSI2_UFS_EMBD, "dout_cmu_hsi2_ufs_embd", "gout_cmu_hsi2_ufs_embd",
> + CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD, 0, 4),
> +
> + DIV(CLK_DOUT_HSI2_MMC_CARD, "dout_cmu_hsi2_mmc_card", "gout_cmu_hsi2_mmc_card",
> + CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD, 0, 9),
> +
> + /* CSIS */
> + DIV(CLK_DOUT_CSIS, "dout_cmu_csis_bus", "gout_cmu_csis_bus",
> + CLK_CON_DIV_CLKCMU_CSIS_BUS, 0, 4),
> +
> + /* PDP */
> + DIV(CLK_DOUT_PDP_BUS, "dout_cmu_pdp_bus", "gout_cmu_pdp_bus",
> + CLK_CON_DIV_CLKCMU_PDP_BUS, 0, 4),
> +
> + /* IPP */
> + DIV(CLK_DOUT_IPP_BUS, "dout_cmu_ipp_bus", "gout_cmu_ipp_bus",
> + CLK_CON_DIV_CLKCMU_IPP_BUS, 0, 4),
> +
> + /* G3AA */
> + DIV(CLK_DOUT_G3AA, "dout_cmu_g3aa", "gout_cmu_g3aa",
> + CLK_CON_DIV_CLKCMU_G3AA_G3AA, 0, 4),
> +
> + /* ITP */
> + DIV(CLK_DOUT_ITP, "dout_cmu_itp_bus", "gout_cmu_itp_bus",
> + CLK_CON_DIV_CLKCMU_ITP_BUS, 0, 4),
> +
> + /* DNS */
> + DIV(CLK_DOUT_DNS_BUS, "dout_cmu_dns_bus", "gout_cmu_dns_bus",
> + CLK_CON_DIV_CLKCMU_DNS_BUS, 0, 4),
> +
> + /* TNR */
> + DIV(CLK_DOUT_TNR_BUS, "dout_cmu_tnr_bus", "gout_cmu_tnr_bus",
> + CLK_CON_DIV_CLKCMU_TNR_BUS, 0, 4),
> +
> + /* MCSC*/
> + DIV(CLK_DOUT_MCSC_ITSC, "dout_cmu_mcsc_itsc", "gout_cmu_mcsc_itsc",
> + CLK_CON_DIV_CLKCMU_MCSC_ITSC, 0, 4),
> +
> + DIV(CLK_DOUT_MCSC_MCSC, "dout_cmu_mcsc_mcsc", "gout_cmu_mcsc_mcsc",
> + CLK_CON_DIV_CLKCMU_MCSC_MCSC, 0, 4),
> +
> + /* GDC */
> + DIV(CLK_DOUT_GDC_SCSC, "dout_cmu_gdc_scsc", "gout_cmu_gdc_scsc",
> + CLK_CON_DIV_CLKCMU_GDC_SCSC, 0, 4),
> +
> + DIV(CLK_DOUT_GDC_GDC0, "dout_cmu_gdc_gdc0", "gout_cmu_gdc_gdc0",
> + CLK_CON_DIV_CLKCMU_GDC_GDC0, 0, 4),
> +
> + DIV(CLK_DOUT_GDC_GDC1, "dout_cmu_gdc_gdc1", "gout_cmu_gdc_gdc1",
> + CLK_CON_DIV_CLKCMU_GDC_GDC1, 0, 4),
> +
> + /* MFC */
> + DIV(CLK_DOUT_MFC_MFC, "dout_cmu_mfc_mfc", "gout_cmu_mfc_mfc",
> + CLK_CON_DIV_CLKCMU_MFC_MFC, 0, 4),
> +
> + /* MIF0/1/2/3 */
> + DIV(CLK_DOUT_MIF_BUS, "dout_cmu_mif_busp", "gout_cmu_mif_busp",
> + CLK_CON_DIV_CLKCMU_MIF_BUSP, 0, 4),
> +
> + /* MISC */
> + DIV(CLK_DOUT_MISC_BUS, "dout_cmu_misc_bus", "gout_cmu_misc_bus",
> + CLK_CON_DIV_CLKCMU_MISC_BUS, 0, 4),
> + DIV(CLK_DOUT_MISC_SSS, "dout_cmu_misc_sss", "gout_cmu_misc_sss",
> + CLK_CON_DIV_CLKCMU_MISC_SSS, 0, 4),
> +
> + /* PERI0 */
> + DIV(CLK_DOUT_PERIC0_BUS, "dout_cmu_peric0_bus", "gout_cmu_peric0_bus",
> + CLK_CON_DIV_CLKCMU_PERIC0_BUS, 0, 4),
> + DIV(CLK_DOUT_PERIC0_IP, "dout_cmu_peric0_ip", "gout_cmu_peric0_ip",
> + CLK_CON_DIV_CLKCMU_PERIC0_IP, 0, 4),
> +
> + /* PERI1 */
> + DIV(CLK_DOUT_PERIC1_BUS, "dout_cmu_peric1_bus", "gout_cmu_peric1_bus",
> + CLK_CON_DIV_CLKCMU_PERIC1_BUS, 0, 4),
> + DIV(CLK_DOUT_PERIC1_IP, "dout_cmu_peric1_ip", "gout_cmu_peric1_ip",
> + CLK_CON_DIV_CLKCMU_PERIC1_IP, 0, 4),
> +
> + /* TPU */
> + DIV(CLK_DOUT_TPU_TPU, "dout_cmu_tpu_tpu", "gout_cmu_tpu_tpu",
> + CLK_CON_DIV_CLKCMU_TPU_TPU, 0, 4),
> +
> + DIV(CLK_DOUT_TPU_TPUCTL, "dout_cmu_tpu_tpuctl", "gout_cmu_tpu_tpuctl",
> + CLK_CON_DIV_CLKCMU_TPU_TPUCTL, 0, 4),
> +
> + DIV(CLK_DOUT_TPU_BUS, "dout_cmu_tpu_bus", "gout_cmu_tpu_bus",
> + CLK_CON_DIV_CLKCMU_TPU_BUS, 0, 4),
> +
> + DIV(CLK_DOUT_TPU_UART, "dout_cmu_tpu_uart", "gout_cmu_tpu_uart",
> + CLK_CON_DIV_CLKCMU_TPU_UART, 0, 4),
> +
> + /* BO */
> + DIV(CLK_DOUT_BO_BUS, "dout_cmu_bo_bus", "gout_cmu_bo_bus",
> + CLK_CON_DIV_CLKCMU_BO_BUS, 0, 4),
> +
> +};
> +
> +static const struct samsung_gate_clock cmu_top_gate_clks[] __initconst = {
> + /* CORE */
> +
> + /* MISC */
> + GATE(CLK_GOUT_MISC_BUS, "gout_cmu_misc_bus", "mout_cmu_misc_bus",
> + CLK_CON_GAT_GATE_CLKCMU_MISC_BUS, 21, 0, 0),
> + GATE(CLK_GOUT_MISC_SSS, "gout_cmu_misc_sss", "mout_cmu_misc_sss",
> + CLK_CON_GAT_GATE_CLKCMU_MISC_SSS, 21, 0, 0),
> +
> + /* BUS0 */
> + GATE(CLK_GOUT_BUS0_BUS, "gout_cmu_bus0_bus", "mout_cmu_bus0_bus",
> + CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS, 21, 0, 0),
> +
> + /* BUS1 */
> + GATE(CLK_GOUT_BUS1_BUS, "gout_cmu_bus1_bus", "mout_cmu_bus1_bus",
> + CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS, 21, 0, 0),
> +
> + /* BUS2 */
> + GATE(CLK_GOUT_BUS2_BUS, "gout_cmu_bus2_bus", "mout_cmu_bus2_bus",
> + CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS, 21, 0, 0),
> +
> + /* CORE */
> + GATE(CLK_GOUT_CORE_BUS, "gout_cmu_core_bus", "mout_cmu_core_bus",
> + CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0),
> +
> + /* EH */
> + GATE(CLK_GOUT_EH_BUS, "gout_cmu_eh_bus", "mout_cmu_eh_bus",
> + CLK_CON_GAT_GATE_CLKCMU_EH_BUS, 21, 0, 0),
> +
> + /* CPUCL{0,1,2,} */
> + GATE(CLK_GOUT_CPUCL2_SWITCH, "gout_cmu_cpucl2_switch", "mout_cmu_cpucl2_switch",
> + CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH, 21, 0, 0),
> +
> + GATE(CLK_GOUT_CPUCL1_SWITCH, "gout_cmu_cpucl1_switch", "mout_cmu_cpucl1_switch",
> + CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, 21, 0, 0),
> +
> + GATE(CLK_GOUT_CPUCL0_SWITCH, "gout_cmu_cpucl0_switch", "mout_cmu_cpucl0_switch",
> + CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, 21, 0, 0),
> +
> + GATE(CLK_GOUT_CPUCL0_DBG, "gout_cmu_cpucl0_dbg", "mout_cmu_cpucl0_dbg",
> + CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS, 21, 0, 0),
> +
> + GATE(CLK_GOUT_CMU_HPM, "gout_cmu_hpm", "mout_cmu_hpm",
> + CLK_CON_GAT_GATE_CLKCMU_HPM, 21, 0, 0),
> +
> + /* G3D */
> + GATE(CLK_GOUT_G3D_SWITCH, "gout_cmu_g3d_switch", "mout_cmu_g3d_switch",
> + CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 21, 0, 0),
> +
> + GATE(CLK_GOUT_G3D_SWITCH, "gout_cmu_g3d_busd", "mout_cmu_g3d_busd",
> + CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD, 21, 0, 0),
> +
> + GATE(CLK_GOUT_G3D_GLB, "gout_cmu_g3d_glb", "mout_cmu_g3d_glb",
> + CLK_CON_GAT_GATE_CLKCMU_G3D_GLB, 21, 0, 0),
> + /* DPU */
> + GATE(CLK_GOUT_DPU_BUS, "gout_cmu_dpu_bus", "mout_cmu_dpu_bus",
> + CLK_CON_GAT_GATE_CLKCMU_DPU_BUS, 21, 0, 0),
> + /* DISP */
> + GATE(CLK_GOUT_DISP_BUS, "gout_cmu_disp_bus", "mout_cmu_disp_bus",
> + CLK_CON_GAT_GATE_CLKCMU_DISP_BUS, 21, 0, 0),
> +
> + /* G2D */
> + GATE(CLK_GOUT_G2D_G2D, "gout_cmu_g2d_g2d", "mout_cmu_g2d_g2d",
> + CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 21, 0, 0),
> +
> + GATE(CLK_GOUT_G2D_MSCL, "gout_cmu_g2d_mscl", "mout_cmu_g2d_mscl",
> + CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL, 21, 0, 0),
> + /* HSI0 */
> + GATE(CLK_GOUT_HSI0_USB31DRD, "gout_cmu_hsi0_usb31drd", "mout_cmu_hsi0_usb31drd",
> + CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD, 21, 0, 0),
> +
> + GATE(CLK_GOUT_HSI0_BUS, "gout_cmu_hsi0_bus", "mout_cmu_hsi0_bus",
> + CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS, 21, 0, 0),
> +
> + GATE(CLK_GOUT_HSI0_DPGTC, "gout_cmu_hsi0_dpgtc", "mout_cmu_hsi0_dpgtc",
> + CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC, 21, 0, 0),
> +
> + GATE(CLK_GOUT_HSI0_USBDPDGB, "gout_cmu_hsi0_usbdpdbg", "mout_cmu_hsi0_usbdpdbg",
> + CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG, 21, 0, 0),
> + /* HSI1 */
> + GATE(CLK_GOUT_HSI1_BUS, "gout_cmu_hsi1_bus", "mout_cmu_hsi1_bus",
> + CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS, 21, 0, 0),
> +
> + GATE(CLK_GOUT_HSI1_PCIE, "gout_cmu_hsi1_pcie", "mout_cmu_hsi1_pcie",
> + CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE, 21, 0, 0),
> + /* HSI2 */
> + GATE(CLK_GOUT_HSI2_BUS, "gout_cmu_hsi2_bus", "mout_cmu_hsi2_bus",
> + CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS, 21, 0, 0),
> + GATE(CLK_GOUT_HSI2_PCIE, "gout_cmu_hsi2_pcie", "mout_cmu_hsi2_pcie",
> + CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE, 21, 0, 0),
> +
> + GATE(CLK_GOUT_HSI2_UFS_EMBD, "gout_cmu_hsi2_ufs_embd", "mout_cmu_hsi2_ufs_embd",
> + CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD, 21, 0, 0),
> + GATE(CLK_GOUT_HSI2_MMC_CARD, "gout_cmu_hsi2_mmc_card", "mout_cmu_hsi2_mmc_card",
> + CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD, 21, 0, 0),
> + /* CSIS */
> + GATE(CLK_GOUT_CSIS, "gout_cmu_csis_bus", "mout_cmu_csis_bus",
> + CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS, 21, 0, 0),
> + /* PDP */
> + GATE(CLK_GOUT_PDP_BUS, "gout_cmu_pdp_bus", "mout_cmu_pdp_bus",
> + CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 21, 0, 0),
> +
> + /* IPP */
> + GATE(CLK_GOUT_IPP_BUS, "gout_cmu_ipp_bus", "mout_cmu_ipp_bus",
> + CLK_CON_GAT_GATE_CLKCMU_IPP_BUS, 21, 0, 0),
> + /* G3AA */
> + GATE(CLK_GOUT_G3AA, "gout_cmu_g3aa", "mout_cmu_g3aa",
> + CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 21, 0, 0),
> +
> + /* ITP */
> + GATE(CLK_GOUT_ITP, "gout_cmu_itp_bus", "mout_cmu_itp_bus",
> + CLK_CON_GAT_GATE_CLKCMU_ITP_BUS, 21, 0, 0),
> +
> + /* DNS */
> + GATE(CLK_GOUT_DNS_BUS, "gout_cmu_dns_bus", "mout_cmu_dns_bus",
> + CLK_CON_GAT_GATE_CLKCMU_DNS_BUS, 21, 0, 0),
> +
> + /* TNR */
> + GATE(CLK_GOUT_TNR_BUS, "gout_cmu_tnr_bus", "mout_cmu_tnr_bus",
> + CLK_CON_GAT_GATE_CLKCMU_TNR_BUS, 21, 0, 0),
> +
> + /* MCSC*/
> + GATE(CLK_GOUT_MCSC_ITSC, "gout_cmu_mcsc_itsc", "mout_cmu_mcsc_itsc",
> + CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC, 21, 0, 0),
> +
> + GATE(CLK_GOUT_MCSC_MCSC, "gout_cmu_mcsc_mcsc", "mout_cmu_mcsc_mcsc",
> + CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC, 21, 0, 0),
> +
> + /* GDC */
> + GATE(CLK_GOUT_GDC_SCSC, "gout_cmu_gdc_scsc", "mout_cmu_gdc_scsc",
> + CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC, 21, 0, 0),
> +
> + GATE(CLK_GOUT_GDC_GDC0, "gout_cmu_gdc_gdc0", "mout_cmu_gdc_gdc0",
> + CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0, 21, 0, 0),
> +
> + GATE(CLK_GOUT_GDC_GDC1, "gout_cmu_gdc_gdc1", "mout_cmu_gdc_gdc1",
> + CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1, 21, 0, 0),
> +
> + /* MFC */
> + GATE(CLK_GOUT_MFC_MFC, "gout_cmu_mfc_mfc", "mout_cmu_mfc_mfc",
> + CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, 21, 0, 0),
> +
> + /* DDRPHY0/1/2/3 */
> + GATE(CLK_GOUT_MIF_SWITCH, "gout_cmu_mif_switch", "mout_cmu_mif_switch",
> + CLK_CON_GAT_CLKCMU_MIF_SWITCH, 21, 0, 0),
> +
> + /* MIF0/1/2/3 */
> + GATE(CLK_GOUT_MIF_BUS, "gout_cmu_mif_busp", "mout_cmu_mif_busp",
> + CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP, 21, 0, 0),
> +
> + GATE(CLK_GOUT_CMU_BOOST, "gout_cmu_cmu_boost", "mout_cmu_boost",
> + CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST, 21, 0, 0),
> +
> + /* MISC */
> + GATE(CLK_GOUT_MISC_BUS, "gout_cmu_misc_bus", "mout_cmu_misc_bus",
> + CLK_CON_GAT_GATE_CLKCMU_MISC_BUS, 21, 0, 0),
> + GATE(CLK_GOUT_MISC_SSS, "gout_cmu_misc_sss", "mout_cmu_misc_sss",
> + CLK_CON_GAT_GATE_CLKCMU_MISC_SSS, 21, 0, 0),
> +
> + /* PERI0 */
> + GATE(CLK_GOUT_PERIC0_BUS, "gout_cmu_peric0_bus", "mout_cmu_peric0_bus",
> + CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS, 21, 0, 0),
> + GATE(CLK_GOUT_PERIC0_IP, "gout_cmu_peric0_ip", "mout_cmu_peric0_ip",
> + CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP, 21, 0, 0),
> +
> + /* PERI1 */
> + GATE(CLK_GOUT_PERIC1_BUS, "gout_cmu_peric1_bus", "mout_cmu_peric1_bus",
> + CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS, 21, 0, 0),
> + GATE(CLK_GOUT_PERIC1_IP, "gout_cmu_peric1_ip", "mout_cmu_peric1_ip",
> + CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP, 21, 0, 0),
> +
> + /* TPU */
> + GATE(CLK_GOUT_TPU_TPU, "gout_cmu_tpu_tpu", "mout_cmu_tpu_tpu",
> + CLK_CON_GAT_GATE_CLKCMU_TPU_TPU, 21, 0, 0),
> + GATE(CLK_GOUT_TPU_TPUCTL, "gout_cmu_tpu_tpuctl", "mout_cmu_tpu_tpuctl",
> + CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL, 21, 0, 0),
> + GATE(CLK_GOUT_TPU_BUS, "gout_cmu_tpu_bus", "mout_cmu_tpu_bus",
> + CLK_CON_GAT_GATE_CLKCMU_TPU_BUS, 21, 0, 0),
> + GATE(CLK_GOUT_TPU_UART, "gout_cmu_tpu_uart", "mout_cmu_tpu_uart",
> + CLK_CON_GAT_GATE_CLKCMU_TPU_UART, 21, 0, 0),
> +
> + /* BO */
> + GATE(CLK_GOUT_BO_BUS, "gout_cmu_bo_bus", "mout_cmu_bo_bus",
> + CLK_CON_GAT_GATE_CLKCMU_BO_BUS, 21, 0, 0),
> +
> +};
> +
> +static const struct samsung_cmu_info top_cmu_info __initconst = {
> + .pll_clks = cmu_top_pll_clks,
> + .nr_pll_clks = ARRAY_SIZE(cmu_top_pll_clks),
> + .mux_clks = cmu_top_mux_clks,
> + .nr_mux_clks = ARRAY_SIZE(cmu_top_mux_clks),
> + .div_clks = cmu_top_div_clks,
> + .nr_div_clks = ARRAY_SIZE(cmu_top_div_clks),
> + .gate_clks = cmu_top_gate_clks,
> + .nr_gate_clks = ARRAY_SIZE(cmu_top_gate_clks),
> + .nr_clk_ids = TOP_NR_CLK,
> + .clk_regs = cmu_top_clk_regs,
> + .nr_clk_regs = ARRAY_SIZE(cmu_top_clk_regs),
> +};
> +
> +static void __init gs101_cmu_top_init(struct device_node *np)
> +{
> + exynos_arm64_register_cmu(NULL, np, &top_cmu_info);
> +}
> +
> +/* Register CMU_TOP early, as it's a dependency for other early domains */
> +CLK_OF_DECLARE(gs101_cmu_top, "google,gs101-cmu-top",
> + gs101_cmu_top_init);
> --
> 2.42.0.582.g8ccd20d70d-goog
>
^ permalink raw reply [flat|nested] 150+ messages in thread* Re: [PATCH 13/21] clk: samsung: clk-gs101: Add cmu_top registers, plls, mux and gates
@ 2023-10-05 17:42 ` William McVicker
0 siblings, 0 replies; 150+ messages in thread
From: William McVicker @ 2023-10-05 17:42 UTC (permalink / raw)
To: Peter Griffin
Cc: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi, tudor.ambarus,
andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog, kernel-team
On 10/05/2023, Peter Griffin wrote:
> CMU_TOP is the top level clock management unit which contains PLLs, muxes
> and gates that feed the other clock management units.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> drivers/clk/samsung/Kconfig | 9 +
> drivers/clk/samsung/Makefile | 1 +
> drivers/clk/samsung/clk-gs101.c | 1558 +++++++++++++++++++++++++++++++
> 3 files changed, 1568 insertions(+)
> create mode 100644 drivers/clk/samsung/clk-gs101.c
>
> diff --git a/drivers/clk/samsung/Kconfig b/drivers/clk/samsung/Kconfig
> index 76a494e95027..4c8f173c4dec 100644
> --- a/drivers/clk/samsung/Kconfig
> +++ b/drivers/clk/samsung/Kconfig
> @@ -13,6 +13,7 @@ config COMMON_CLK_SAMSUNG
> select EXYNOS_5420_COMMON_CLK if ARM && SOC_EXYNOS5420
> select EXYNOS_ARM64_COMMON_CLK if ARM64 && ARCH_EXYNOS
> select TESLA_FSD_COMMON_CLK if ARM64 && ARCH_TESLA_FSD
> + select GOOGLE_GS101_COMMON_CLK if ARM64 && ARCH_GOOGLE_TENSOR
Is this patch out of order? ARCH_GOOGLE_TENSOR hasn't been defined at this
point in the series (it's defined in 18/21).
Regards,
Will
>
> config S3C64XX_COMMON_CLK
> bool "Samsung S3C64xx clock controller support" if COMPILE_TEST
> @@ -102,3 +103,11 @@ config TESLA_FSD_COMMON_CLK
> help
> Support for the clock controller present on the Tesla FSD SoC.
> Choose Y here only if you build for this SoC.
> +
> +config GOOGLE_GS101_COMMON_CLK
> + bool "Google gs101 clock controller support" if COMPILE_TEST
> + depends on COMMON_CLK_SAMSUNG
> + depends on EXYNOS_ARM64_COMMON_CLK
> + help
> + Support for the clock controller present on the Google gs101 SoC.
> + Choose Y here only if you build for this SoC.
> \ No newline at end of file
> diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
> index ebbeacabe88f..1e69b8e14324 100644
> --- a/drivers/clk/samsung/Makefile
> +++ b/drivers/clk/samsung/Makefile
> @@ -24,3 +24,4 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov9.o
> obj-$(CONFIG_S3C64XX_COMMON_CLK) += clk-s3c64xx.o
> obj-$(CONFIG_S5PV210_COMMON_CLK) += clk-s5pv210.o clk-s5pv210-audss.o
> obj-$(CONFIG_TESLA_FSD_COMMON_CLK) += clk-fsd.o
> +obj-$(CONFIG_GOOGLE_GS101_COMMON_CLK) += clk-gs101.o
> diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
> new file mode 100644
> index 000000000000..4c58fcc899be
> --- /dev/null
> +++ b/drivers/clk/samsung/clk-gs101.c
> @@ -0,0 +1,1558 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (C) 2023 Linaro Ltd.
> + * Author: Peter Griffin <peter.griffin@linaro.org>
> + *
> + * Common Clock Framework support for GS101.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +
> +#include <dt-bindings/clock/gs101.h>
> +
> +#include "clk.h"
> +#include "clk-exynos-arm64.h"
> +
> +/* NOTE: Must be equal to the last clock ID increased by one */
> +#define TOP_NR_CLK (CLK_GOUT_CMU_BOOST + 1)
> +
> +/* ---- CMU_TOP ------------------------------------------------------------- */
> +
> +/* Register Offset definitions for CMU_TOP (0x1e080000) */
> +
> +#define PLL_LOCKTIME_PLL_SHARED0 0x0000
> +#define PLL_LOCKTIME_PLL_SHARED1 0x0004
> +#define PLL_LOCKTIME_PLL_SHARED2 0x0008
> +#define PLL_LOCKTIME_PLL_SHARED3 0x000c
> +#define PLL_LOCKTIME_PLL_SPARE 0x0010
> +#define PLL_CON0_PLL_SHARED0 0x0100
> +#define PLL_CON1_PLL_SHARED0 0x0104
> +#define PLL_CON2_PLL_SHARED0 0x0108
> +#define PLL_CON3_PLL_SHARED0 0x010c
> +#define PLL_CON4_PLL_SHARED0 0x0110
> +#define PLL_CON0_PLL_SHARED1 0x0140
> +#define PLL_CON1_PLL_SHARED1 0x0144
> +#define PLL_CON2_PLL_SHARED1 0x0148
> +#define PLL_CON3_PLL_SHARED1 0x014c
> +#define PLL_CON4_PLL_SHARED1 0x0150
> +#define PLL_CON0_PLL_SHARED2 0x0180
> +#define PLL_CON1_PLL_SHARED2 0x0184
> +#define PLL_CON2_PLL_SHARED2 0x0188
> +#define PLL_CON3_PLL_SHARED2 0x018c
> +#define PLL_CON4_PLL_SHARED2 0x0190
> +#define PLL_CON0_PLL_SHARED3 0x01c0
> +#define PLL_CON1_PLL_SHARED3 0x01c4
> +#define PLL_CON2_PLL_SHARED3 0x01c8
> +#define PLL_CON3_PLL_SHARED3 0x01cc
> +#define PLL_CON4_PLL_SHARED3 0x01d0
> +#define PLL_CON0_PLL_SPARE 0x0200
> +#define PLL_CON1_PLL_SPARE 0x0204
> +#define PLL_CON2_PLL_SPARE 0x0208
> +#define PLL_CON3_PLL_SPARE 0x020c
> +#define PLL_CON4_PLL_SPARE 0x0210
> +#define CMU_CMU_TOP_CONTROLLER_OPTION 0x0800
> +#define CLKOUT_CON_BLK_CMU_CMU_TOP_CLKOUT0 0x0810
> +#define CMU_HCHGEN_CLKMUX_CMU_BOOST 0x0840
> +#define CMU_HCHGEN_CLKMUX_TOP_BOOST 0x0844
> +#define CMU_HCHGEN_CLKMUX 0x0850
> +#define POWER_FAIL_DETECT_PLL 0x0864
> +#define EARLY_WAKEUP_FORCED_0_ENABLE 0x0870
> +#define EARLY_WAKEUP_FORCED_1_ENABLE 0x0874
> +#define EARLY_WAKEUP_APM_CTRL 0x0878
> +#define EARLY_WAKEUP_CLUSTER0_CTRL 0x087c
> +#define EARLY_WAKEUP_DPU_CTRL 0x0880
> +#define EARLY_WAKEUP_CSIS_CTRL 0x0884
> +#define EARLY_WAKEUP_APM_DEST 0x0890
> +#define EARLY_WAKEUP_CLUSTER0_DEST 0x0894
> +#define EARLY_WAKEUP_DPU_DEST 0x0898
> +#define EARLY_WAKEUP_CSIS_DEST 0x089c
> +#define EARLY_WAKEUP_SW_TRIG_APM 0x08c0
> +#define EARLY_WAKEUP_SW_TRIG_APM_SET 0x08c4
> +#define EARLY_WAKEUP_SW_TRIG_APM_CLEAR 0x08c8
> +#define EARLY_WAKEUP_SW_TRIG_CLUSTER0 0x08d0
> +#define EARLY_WAKEUP_SW_TRIG_CLUSTER0_SET 0x08d4
> +#define EARLY_WAKEUP_SW_TRIG_CLUSTER0_CLEAR 0x08d8
> +#define EARLY_WAKEUP_SW_TRIG_DPU 0x08e0
> +#define EARLY_WAKEUP_SW_TRIG_DPU_SET 0x08e4
> +#define EARLY_WAKEUP_SW_TRIG_DPU_CLEAR 0x08e8
> +#define EARLY_WAKEUP_SW_TRIG_CSIS 0x08f0
> +#define EARLY_WAKEUP_SW_TRIG_CSIS_SET 0x08f4
> +#define EARLY_WAKEUP_SW_TRIG_CSIS_CLEAR 0x08f8
> +
> +#define CLK_CON_MUX_MUX_CLKCMU_BO_BUS 0x1000
> +#define CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS 0x1004
> +#define CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS 0x1008
> +#define CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS 0x100c
> +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0 0x1010
> +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1 0x1014
> +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2 0x1018
> +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3 0x101c
> +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4 0x1020
> +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5 0x1024
> +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6 0x1028
> +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7 0x102c
> +#define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST 0x1030
> +#define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1 0x1034
> +#define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1038
> +#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG 0x103c
> +#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH 0x1040
> +#define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH 0x1044
> +#define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH 0x1048
> +#define CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS 0x104c
> +#define CLK_CON_MUX_MUX_CLKCMU_DISP_BUS 0x1050
> +#define CLK_CON_MUX_MUX_CLKCMU_DNS_BUS 0x1054
> +#define CLK_CON_MUX_MUX_CLKCMU_DPU_BUS 0x1058
> +#define CLK_CON_MUX_MUX_CLKCMU_EH_BUS 0x105c
> +#define CLK_CON_MUX_MUX_CLKCMU_G2D_G2D 0x1060
> +#define CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL 0x1064
> +#define CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA 0x1068
> +#define CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD 0x106c
> +#define CLK_CON_MUX_MUX_CLKCMU_G3D_GLB 0x1070
> +#define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH 0x1074
> +#define CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0 0x1078
> +#define CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1 0x107c
> +#define CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC 0x1080
> +#define CLK_CON_MUX_MUX_CLKCMU_HPM 0x1084
> +#define CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS 0x1088
> +#define CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC 0x108c
> +#define CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD 0x1090
> +#define CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG 0x1094
> +#define CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS 0x1098
> +#define CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE 0x109c
> +#define CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS 0x10a0
> +#define CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD 0x10a4
> +#define CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE 0x10a8
> +#define CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD 0x10ac
> +#define CLK_CON_MUX_MUX_CLKCMU_IPP_BUS 0x10b0
> +#define CLK_CON_MUX_MUX_CLKCMU_ITP_BUS 0x10b4
> +#define CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC 0x10b8
> +#define CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC 0x10bc
> +#define CLK_CON_MUX_MUX_CLKCMU_MFC_MFC 0x10c0
> +#define CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP 0x10c4
> +#define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0x10c8
> +#define CLK_CON_MUX_MUX_CLKCMU_MISC_BUS 0x10cc
> +#define CLK_CON_MUX_MUX_CLKCMU_MISC_SSS 0x10d0
> +#define CLK_CON_MUX_MUX_CLKCMU_PDP_BUS 0x10d4
> +#define CLK_CON_MUX_MUX_CLKCMU_PDP_VRA 0x10d8
> +#define CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS 0x10dc
> +#define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP 0x10e0
> +#define CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS 0x10e4
> +#define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP 0x10e8
> +#define CLK_CON_MUX_MUX_CLKCMU_TNR_BUS 0x10ec
> +#define CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1 0x10f0
> +#define CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF 0x10f4
> +#define CLK_CON_MUX_MUX_CLKCMU_TPU_BUS 0x10f8
> +#define CLK_CON_MUX_MUX_CLKCMU_TPU_TPU 0x10fc
> +#define CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL 0x1100
> +#define CLK_CON_MUX_MUX_CLKCMU_TPU_UART 0x1104
> +#define CLK_CON_MUX_MUX_CMU_CMUREF 0x1108
> +
> +#define CLK_CON_DIV_CLKCMU_BO_BUS 0x1800
> +#define CLK_CON_DIV_CLKCMU_BUS0_BUS 0x1804
> +#define CLK_CON_DIV_CLKCMU_BUS1_BUS 0x1808
> +#define CLK_CON_DIV_CLKCMU_BUS2_BUS 0x180c
> +#define CLK_CON_DIV_CLKCMU_CIS_CLK0 0x1810
> +#define CLK_CON_DIV_CLKCMU_CIS_CLK1 0x1814
> +#define CLK_CON_DIV_CLKCMU_CIS_CLK2 0x1818
> +#define CLK_CON_DIV_CLKCMU_CIS_CLK3 0x181c
> +#define CLK_CON_DIV_CLKCMU_CIS_CLK4 0x1820
> +#define CLK_CON_DIV_CLKCMU_CIS_CLK5 0x1824
> +#define CLK_CON_DIV_CLKCMU_CIS_CLK6 0x1828
> +#define CLK_CON_DIV_CLKCMU_CIS_CLK7 0x182c
> +#define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1830
> +#define CLK_CON_DIV_CLKCMU_CPUCL0_DBG 0x1834
> +#define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH 0x1838
> +#define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH 0x183c
> +#define CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH 0x1840
> +#define CLK_CON_DIV_CLKCMU_CSIS_BUS 0x1844
> +#define CLK_CON_DIV_CLKCMU_DISP_BUS 0x1848
> +#define CLK_CON_DIV_CLKCMU_DNS_BUS 0x184c
> +#define CLK_CON_DIV_CLKCMU_DPU_BUS 0x1850
> +#define CLK_CON_DIV_CLKCMU_EH_BUS 0x1854
> +#define CLK_CON_DIV_CLKCMU_G2D_G2D 0x1858
> +#define CLK_CON_DIV_CLKCMU_G2D_MSCL 0x185c
> +#define CLK_CON_DIV_CLKCMU_G3AA_G3AA 0x1860
> +#define CLK_CON_DIV_CLKCMU_G3D_BUSD 0x1864
> +#define CLK_CON_DIV_CLKCMU_G3D_GLB 0x1868
> +#define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x186c
> +#define CLK_CON_DIV_CLKCMU_GDC_GDC0 0x1870
> +#define CLK_CON_DIV_CLKCMU_GDC_GDC1 0x1874
> +#define CLK_CON_DIV_CLKCMU_GDC_SCSC 0x1878
> +#define CLK_CON_DIV_CLKCMU_HPM 0x187c
> +#define CLK_CON_DIV_CLKCMU_HSI0_BUS 0x1880
> +#define CLK_CON_DIV_CLKCMU_HSI0_DPGTC 0x1884
> +#define CLK_CON_DIV_CLKCMU_HSI0_USB31DRD 0x1888
> +#define CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG 0x188c
> +#define CLK_CON_DIV_CLKCMU_HSI1_BUS 0x1890
> +#define CLK_CON_DIV_CLKCMU_HSI1_PCIE 0x1894
> +#define CLK_CON_DIV_CLKCMU_HSI2_BUS 0x1898
> +#define CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD 0x189c
> +#define CLK_CON_DIV_CLKCMU_HSI2_PCIE 0x18a0
> +#define CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD 0x18a4
> +#define CLK_CON_DIV_CLKCMU_IPP_BUS 0x18a8
> +#define CLK_CON_DIV_CLKCMU_ITP_BUS 0x18ac
> +#define CLK_CON_DIV_CLKCMU_MCSC_ITSC 0x18b0
> +#define CLK_CON_DIV_CLKCMU_MCSC_MCSC 0x18b4
> +#define CLK_CON_DIV_CLKCMU_MFC_MFC 0x18b8
> +#define CLK_CON_DIV_CLKCMU_MIF_BUSP 0x18bc
> +#define CLK_CON_DIV_CLKCMU_MISC_BUS 0x18c0
> +#define CLK_CON_DIV_CLKCMU_MISC_SSS 0x18c4
> +#define CLK_CON_DIV_CLKCMU_OTP 0x18c8
> +#define CLK_CON_DIV_CLKCMU_PDP_BUS 0x18cc
> +#define CLK_CON_DIV_CLKCMU_PDP_VRA 0x18d0
> +#define CLK_CON_DIV_CLKCMU_PERIC0_BUS 0x18d4
> +#define CLK_CON_DIV_CLKCMU_PERIC0_IP 0x18d8
> +#define CLK_CON_DIV_CLKCMU_PERIC1_BUS 0x18dc
> +#define CLK_CON_DIV_CLKCMU_PERIC1_IP 0x18e0
> +#define CLK_CON_DIV_CLKCMU_TNR_BUS 0x18e4
> +#define CLK_CON_DIV_CLKCMU_TPU_BUS 0x18e8
> +#define CLK_CON_DIV_CLKCMU_TPU_TPU 0x18ec
> +#define CLK_CON_DIV_CLKCMU_TPU_TPUCTL 0x18f0
> +#define CLK_CON_DIV_CLKCMU_TPU_UART 0x18f4
> +#define CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST 0x18f8
> +#define CLK_CON_DIV_DIV_CLK_CMU_CMUREF 0x18fc
> +#define CLK_CON_DIV_PLL_SHARED0_DIV2 0x1900
> +#define CLK_CON_DIV_PLL_SHARED0_DIV3 0x1904
> +#define CLK_CON_DIV_PLL_SHARED0_DIV4 0x1908
> +#define CLK_CON_DIV_PLL_SHARED0_DIV5 0x190c
> +#define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1910
> +#define CLK_CON_DIV_PLL_SHARED1_DIV3 0x1914
> +#define CLK_CON_DIV_PLL_SHARED1_DIV4 0x1918
> +#define CLK_CON_DIV_PLL_SHARED2_DIV2 0x191c
> +#define CLK_CON_DIV_PLL_SHARED3_DIV2 0x1920
> +
> +/* CLK_CON_GAT_UPDATES */
> +#define CLK_CON_GAT_CLKCMU_BUS0_BOOST 0x2000
> +#define CLK_CON_GAT_CLKCMU_BUS1_BOOST 0x2004
> +#define CLK_CON_GAT_CLKCMU_BUS2_BOOST 0x2008
> +#define CLK_CON_GAT_CLKCMU_CORE_BOOST 0x200c
> +#define CLK_CON_GAT_CLKCMU_CPUCL0_BOOST 0x2010
> +#define CLK_CON_GAT_CLKCMU_CPUCL1_BOOST 0x2014
> +#define CLK_CON_GAT_CLKCMU_CPUCL2_BOOST 0x2018
> +#define CLK_CON_GAT_CLKCMU_MIF_BOOST 0x201c
> +#define CLK_CON_GAT_CLKCMU_MIF_SWITCH 0x2020
> +#define CLK_CON_GAT_GATE_CLKCMU_BO_BUS 0x2024
> +#define CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS 0x2028
> +#define CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS 0x202c
> +#define CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS 0x2030
> +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0 0x2034
> +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1 0x2038
> +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2 0x203c
> +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3 0x2040
> +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4 0x2044
> +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5 0x2048
> +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6 0x204c
> +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7 0x2050
> +#define CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST 0x2054
> +#define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x2058
> +#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS 0x205c
> +#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH 0x2060
> +#define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH 0x2064
> +#define CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH 0x2068
> +#define CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS 0x206c
> +#define CLK_CON_GAT_GATE_CLKCMU_DISP_BUS 0x2070
> +#define CLK_CON_GAT_GATE_CLKCMU_DNS_BUS 0x2074
> +#define CLK_CON_GAT_GATE_CLKCMU_DPU_BUS 0x2078
> +#define CLK_CON_GAT_GATE_CLKCMU_EH_BUS 0x207c
> +#define CLK_CON_GAT_GATE_CLKCMU_G2D_G2D 0x2080
> +#define CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL 0x2084
> +#define CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA 0x2088
> +#define CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD 0x208c
> +#define CLK_CON_GAT_GATE_CLKCMU_G3D_GLB 0x2090
> +#define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH 0x2094
> +#define CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0 0x2098
> +#define CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1 0x209c
> +#define CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC 0x20a0
> +#define CLK_CON_GAT_GATE_CLKCMU_HPM 0x20a4
> +#define CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS 0x20a8
> +#define CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC 0x20ac
> +#define CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD 0x20b0
> +#define CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG 0x20b4
> +#define CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS 0x20b8
> +#define CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE 0x20bc
> +#define CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS 0x20c0
> +#define CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD 0x20c4
> +#define CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE 0x20c8
> +#define CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD 0x20cc
> +#define CLK_CON_GAT_GATE_CLKCMU_IPP_BUS 0x20d0
> +#define CLK_CON_GAT_GATE_CLKCMU_ITP_BUS 0x20d4
> +#define CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC 0x20d8
> +#define CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC 0x20dc
> +#define CLK_CON_GAT_GATE_CLKCMU_MFC_MFC 0x20e0
> +#define CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP 0x20e4
> +#define CLK_CON_GAT_GATE_CLKCMU_MISC_BUS 0x20e8
> +#define CLK_CON_GAT_GATE_CLKCMU_MISC_SSS 0x20ec
> +#define CLK_CON_GAT_GATE_CLKCMU_PDP_BUS 0x20f0
> +#define CLK_CON_GAT_GATE_CLKCMU_PDP_VRA 0x20f4
> +#define CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS 0x20f8
> +#define CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP 0x20fc
> +#define CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS 0x2100
> +#define CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP 0x2104
> +#define CLK_CON_GAT_GATE_CLKCMU_TNR_BUS 0x2108
> +#define CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF 0x210c
> +#define CLK_CON_GAT_GATE_CLKCMU_TPU_BUS 0x2110
> +#define CLK_CON_GAT_GATE_CLKCMU_TPU_TPU 0x2114
> +#define CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL 0x2118
> +#define CLK_CON_GAT_GATE_CLKCMU_TPU_UART 0x211c
> +
> +#define DMYQCH_CON_CMU_TOP_CMUREF_QCH 0x3000
> +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0 0x3004
> +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1 0x3008
> +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2 0x300c
> +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3 0x3010
> +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4 0x3014
> +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5 0x3018
> +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6 0x301c
> +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7 0x3020
> +#define DMYQCH_CON_OTP_QCH 0x3024
> +#define QUEUE_CTRL_REG_BLK_CMU_CMU_TOP 0x3c00
> +#define QUEUE_ENTRY0_BLK_CMU_CMU_TOP 0x3c10
> +#define QUEUE_ENTRY1_BLK_CMU_CMU_TOP 0x3c14
> +#define QUEUE_ENTRY2_BLK_CMU_CMU_TOP 0x3c18
> +#define QUEUE_ENTRY3_BLK_CMU_CMU_TOP 0x3c1c
> +#define QUEUE_ENTRY4_BLK_CMU_CMU_TOP 0x3c20
> +#define QUEUE_ENTRY5_BLK_CMU_CMU_TOP 0x3c24
> +#define QUEUE_ENTRY6_BLK_CMU_CMU_TOP 0x3c28
> +#define QUEUE_ENTRY7_BLK_CMU_CMU_TOP 0x3c2c
> +#define MIFMIRROR_QUEUE_CTRL_REG 0x3e00
> +#define MIFMIRROR_QUEUE_ENTRY0 0x3e10
> +#define MIFMIRROR_QUEUE_ENTRY1 0x3e14
> +#define MIFMIRROR_QUEUE_ENTRY2 0x3e18
> +#define MIFMIRROR_QUEUE_ENTRY3 0x3e1c
> +#define MIFMIRROR_QUEUE_ENTRY4 0x3e20
> +#define MIFMIRROR_QUEUE_ENTRY5 0x3e24
> +#define MIFMIRROR_QUEUE_ENTRY6 0x3e28
> +#define MIFMIRROR_QUEUE_ENTRY7 0x3e2c
> +#define MIFMIRROR_QUEUE_BUSY 0x3e30
> +#define GENERALIO_ACD_CHANNEL_0 0x3f00
> +#define GENERALIO_ACD_CHANNEL_1 0x3f04
> +#define GENERALIO_ACD_CHANNEL_2 0x3f08
> +#define GENERALIO_ACD_CHANNEL_3 0x3f0c
> +#define GENERALIO_ACD_MASK 0x3f14
> +
> +static const unsigned long cmu_top_clk_regs[] __initconst = {
> + PLL_LOCKTIME_PLL_SHARED0,
> + PLL_LOCKTIME_PLL_SHARED1,
> + PLL_LOCKTIME_PLL_SHARED2,
> + PLL_LOCKTIME_PLL_SHARED3,
> + PLL_LOCKTIME_PLL_SPARE,
> + PLL_CON0_PLL_SHARED0,
> + PLL_CON1_PLL_SHARED0,
> + PLL_CON2_PLL_SHARED0,
> + PLL_CON3_PLL_SHARED0,
> + PLL_CON4_PLL_SHARED0,
> + PLL_CON0_PLL_SHARED1,
> + PLL_CON1_PLL_SHARED1,
> + PLL_CON2_PLL_SHARED1,
> + PLL_CON3_PLL_SHARED1,
> + PLL_CON4_PLL_SHARED1,
> + PLL_CON0_PLL_SHARED2,
> + PLL_CON1_PLL_SHARED2,
> + PLL_CON2_PLL_SHARED2,
> + PLL_CON3_PLL_SHARED2,
> + PLL_CON4_PLL_SHARED2,
> + PLL_CON0_PLL_SHARED3,
> + PLL_CON1_PLL_SHARED3,
> + PLL_CON2_PLL_SHARED3,
> + PLL_CON3_PLL_SHARED3,
> + PLL_CON4_PLL_SHARED3,
> + PLL_CON0_PLL_SPARE,
> + PLL_CON1_PLL_SPARE,
> + PLL_CON2_PLL_SPARE,
> + PLL_CON3_PLL_SPARE,
> + PLL_CON4_PLL_SPARE,
> + CMU_CMU_TOP_CONTROLLER_OPTION,
> + CLKOUT_CON_BLK_CMU_CMU_TOP_CLKOUT0,
> + CMU_HCHGEN_CLKMUX_CMU_BOOST,
> + CMU_HCHGEN_CLKMUX_TOP_BOOST,
> + CMU_HCHGEN_CLKMUX,
> + POWER_FAIL_DETECT_PLL,
> + EARLY_WAKEUP_FORCED_0_ENABLE,
> + EARLY_WAKEUP_FORCED_1_ENABLE,
> + EARLY_WAKEUP_APM_CTRL,
> + EARLY_WAKEUP_CLUSTER0_CTRL,
> + EARLY_WAKEUP_DPU_CTRL,
> + EARLY_WAKEUP_CSIS_CTRL,
> + EARLY_WAKEUP_APM_DEST,
> + EARLY_WAKEUP_CLUSTER0_DEST,
> + EARLY_WAKEUP_DPU_DEST,
> + EARLY_WAKEUP_CSIS_DEST,
> + EARLY_WAKEUP_SW_TRIG_APM,
> + EARLY_WAKEUP_SW_TRIG_APM_SET,
> + EARLY_WAKEUP_SW_TRIG_APM_CLEAR,
> + EARLY_WAKEUP_SW_TRIG_CLUSTER0,
> + EARLY_WAKEUP_SW_TRIG_CLUSTER0_SET,
> + EARLY_WAKEUP_SW_TRIG_CLUSTER0_CLEAR,
> + EARLY_WAKEUP_SW_TRIG_DPU,
> + EARLY_WAKEUP_SW_TRIG_DPU_SET,
> + EARLY_WAKEUP_SW_TRIG_DPU_CLEAR,
> + EARLY_WAKEUP_SW_TRIG_CSIS,
> + EARLY_WAKEUP_SW_TRIG_CSIS_SET,
> + EARLY_WAKEUP_SW_TRIG_CSIS_CLEAR,
> + CLK_CON_MUX_MUX_CLKCMU_BO_BUS,
> + CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS,
> + CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS,
> + CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS,
> + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0,
> + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1,
> + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2,
> + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3,
> + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4,
> + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5,
> + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6,
> + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7,
> + CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST,
> + CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1,
> + CLK_CON_MUX_MUX_CLKCMU_CORE_BUS,
> + CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG,
> + CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
> + CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
> + CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH,
> + CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS,
> + CLK_CON_MUX_MUX_CLKCMU_DISP_BUS,
> + CLK_CON_MUX_MUX_CLKCMU_DNS_BUS,
> + CLK_CON_MUX_MUX_CLKCMU_DPU_BUS,
> + CLK_CON_MUX_MUX_CLKCMU_EH_BUS,
> + CLK_CON_MUX_MUX_CLKCMU_G2D_G2D,
> + CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL,
> + CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA,
> + CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD,
> + CLK_CON_MUX_MUX_CLKCMU_G3D_GLB,
> + CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH,
> + CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0,
> + CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1,
> + CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC,
> + CLK_CON_MUX_MUX_CLKCMU_HPM,
> + CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS,
> + CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC,
> + CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD,
> + CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG,
> + CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS,
> + CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE,
> + CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS,
> + CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD,
> + CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE,
> + CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD,
> + CLK_CON_MUX_MUX_CLKCMU_IPP_BUS,
> + CLK_CON_MUX_MUX_CLKCMU_ITP_BUS,
> + CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC,
> + CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC,
> + CLK_CON_MUX_MUX_CLKCMU_MFC_MFC,
> + CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP,
> + CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH,
> + CLK_CON_MUX_MUX_CLKCMU_MISC_BUS,
> + CLK_CON_MUX_MUX_CLKCMU_MISC_SSS,
> + CLK_CON_MUX_MUX_CLKCMU_PDP_BUS,
> + CLK_CON_MUX_MUX_CLKCMU_PDP_VRA,
> + CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS,
> + CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP,
> + CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS,
> + CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP,
> + CLK_CON_MUX_MUX_CLKCMU_TNR_BUS,
> + CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1,
> + CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF,
> + CLK_CON_MUX_MUX_CLKCMU_TPU_BUS,
> + CLK_CON_MUX_MUX_CLKCMU_TPU_TPU,
> + CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL,
> + CLK_CON_MUX_MUX_CLKCMU_TPU_UART,
> + CLK_CON_MUX_MUX_CMU_CMUREF,
> + CLK_CON_DIV_CLKCMU_BO_BUS,
> + CLK_CON_DIV_CLKCMU_BUS0_BUS,
> + CLK_CON_DIV_CLKCMU_BUS1_BUS,
> + CLK_CON_DIV_CLKCMU_BUS2_BUS,
> + CLK_CON_DIV_CLKCMU_CIS_CLK0,
> + CLK_CON_DIV_CLKCMU_CIS_CLK1,
> + CLK_CON_DIV_CLKCMU_CIS_CLK2,
> + CLK_CON_DIV_CLKCMU_CIS_CLK3,
> + CLK_CON_DIV_CLKCMU_CIS_CLK4,
> + CLK_CON_DIV_CLKCMU_CIS_CLK5,
> + CLK_CON_DIV_CLKCMU_CIS_CLK6,
> + CLK_CON_DIV_CLKCMU_CIS_CLK7,
> + CLK_CON_DIV_CLKCMU_CORE_BUS,
> + CLK_CON_DIV_CLKCMU_CPUCL0_DBG,
> + CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH,
> + CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH,
> + CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH,
> + CLK_CON_DIV_CLKCMU_CSIS_BUS,
> + CLK_CON_DIV_CLKCMU_DISP_BUS,
> + CLK_CON_DIV_CLKCMU_DNS_BUS,
> + CLK_CON_DIV_CLKCMU_DPU_BUS,
> + CLK_CON_DIV_CLKCMU_EH_BUS,
> + CLK_CON_DIV_CLKCMU_G2D_G2D,
> + CLK_CON_DIV_CLKCMU_G2D_MSCL,
> + CLK_CON_DIV_CLKCMU_G3AA_G3AA,
> + CLK_CON_DIV_CLKCMU_G3D_BUSD,
> + CLK_CON_DIV_CLKCMU_G3D_GLB,
> + CLK_CON_DIV_CLKCMU_G3D_SWITCH,
> + CLK_CON_DIV_CLKCMU_GDC_GDC0,
> + CLK_CON_DIV_CLKCMU_GDC_GDC1,
> + CLK_CON_DIV_CLKCMU_GDC_SCSC,
> + CLK_CON_DIV_CLKCMU_HPM,
> + CLK_CON_DIV_CLKCMU_HSI0_BUS,
> + CLK_CON_DIV_CLKCMU_HSI0_DPGTC,
> + CLK_CON_DIV_CLKCMU_HSI0_USB31DRD,
> + CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG,
> + CLK_CON_DIV_CLKCMU_HSI1_BUS,
> + CLK_CON_DIV_CLKCMU_HSI1_PCIE,
> + CLK_CON_DIV_CLKCMU_HSI2_BUS,
> + CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD,
> + CLK_CON_DIV_CLKCMU_HSI2_PCIE,
> + CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD,
> + CLK_CON_DIV_CLKCMU_IPP_BUS,
> + CLK_CON_DIV_CLKCMU_ITP_BUS,
> + CLK_CON_DIV_CLKCMU_MCSC_ITSC,
> + CLK_CON_DIV_CLKCMU_MCSC_MCSC,
> + CLK_CON_DIV_CLKCMU_MFC_MFC,
> + CLK_CON_DIV_CLKCMU_MIF_BUSP,
> + CLK_CON_DIV_CLKCMU_MISC_BUS,
> + CLK_CON_DIV_CLKCMU_MISC_SSS,
> + CLK_CON_DIV_CLKCMU_OTP,
> + CLK_CON_DIV_CLKCMU_PDP_BUS,
> + CLK_CON_DIV_CLKCMU_PDP_VRA,
> + CLK_CON_DIV_CLKCMU_PERIC0_BUS,
> + CLK_CON_DIV_CLKCMU_PERIC0_IP,
> + CLK_CON_DIV_CLKCMU_PERIC1_BUS,
> + CLK_CON_DIV_CLKCMU_PERIC1_IP,
> + CLK_CON_DIV_CLKCMU_TNR_BUS,
> + CLK_CON_DIV_CLKCMU_TPU_BUS,
> + CLK_CON_DIV_CLKCMU_TPU_TPU,
> + CLK_CON_DIV_CLKCMU_TPU_TPUCTL,
> + CLK_CON_DIV_CLKCMU_TPU_UART,
> + CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST,
> + CLK_CON_DIV_DIV_CLK_CMU_CMUREF,
> + CLK_CON_DIV_PLL_SHARED0_DIV2,
> + CLK_CON_DIV_PLL_SHARED0_DIV3,
> + CLK_CON_DIV_PLL_SHARED0_DIV4,
> + CLK_CON_DIV_PLL_SHARED0_DIV5,
> + CLK_CON_DIV_PLL_SHARED1_DIV2,
> + CLK_CON_DIV_PLL_SHARED1_DIV3,
> + CLK_CON_DIV_PLL_SHARED1_DIV4,
> + CLK_CON_DIV_PLL_SHARED2_DIV2,
> + CLK_CON_DIV_PLL_SHARED3_DIV2,
> + CLK_CON_GAT_CLKCMU_BUS0_BOOST,
> + CLK_CON_GAT_CLKCMU_BUS1_BOOST,
> + CLK_CON_GAT_CLKCMU_BUS2_BOOST,
> + CLK_CON_GAT_CLKCMU_CORE_BOOST,
> + CLK_CON_GAT_CLKCMU_CPUCL0_BOOST,
> + CLK_CON_GAT_CLKCMU_CPUCL1_BOOST,
> + CLK_CON_GAT_CLKCMU_CPUCL2_BOOST,
> + CLK_CON_GAT_CLKCMU_MIF_BOOST,
> + CLK_CON_GAT_CLKCMU_MIF_SWITCH,
> + CLK_CON_GAT_GATE_CLKCMU_BO_BUS,
> + CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS,
> + CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS,
> + CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS,
> + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0,
> + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1,
> + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2,
> + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3,
> + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4,
> + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5,
> + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6,
> + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7,
> + CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST,
> + CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
> + CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS,
> + CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH,
> + CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH,
> + CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH,
> + CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS,
> + CLK_CON_GAT_GATE_CLKCMU_DISP_BUS,
> + CLK_CON_GAT_GATE_CLKCMU_DNS_BUS,
> + CLK_CON_GAT_GATE_CLKCMU_DPU_BUS,
> + CLK_CON_GAT_GATE_CLKCMU_EH_BUS,
> + CLK_CON_GAT_GATE_CLKCMU_G2D_G2D,
> + CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL,
> + CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA,
> + CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD,
> + CLK_CON_GAT_GATE_CLKCMU_G3D_GLB,
> + CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH,
> + CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0,
> + CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1,
> + CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC,
> + CLK_CON_GAT_GATE_CLKCMU_HPM,
> + CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS,
> + CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC,
> + CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD,
> + CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG,
> + CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS,
> + CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE,
> + CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS,
> + CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD,
> + CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE,
> + CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD,
> + CLK_CON_GAT_GATE_CLKCMU_IPP_BUS,
> + CLK_CON_GAT_GATE_CLKCMU_ITP_BUS,
> + CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC,
> + CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC,
> + CLK_CON_GAT_GATE_CLKCMU_MFC_MFC,
> + CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP,
> + CLK_CON_GAT_GATE_CLKCMU_MISC_BUS,
> + CLK_CON_GAT_GATE_CLKCMU_MISC_SSS,
> + CLK_CON_GAT_GATE_CLKCMU_PDP_BUS,
> + CLK_CON_GAT_GATE_CLKCMU_PDP_VRA,
> + CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS,
> + CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP,
> + CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS,
> + CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP,
> + CLK_CON_GAT_GATE_CLKCMU_TNR_BUS,
> + CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF,
> + CLK_CON_GAT_GATE_CLKCMU_TPU_BUS,
> + CLK_CON_GAT_GATE_CLKCMU_TPU_TPU,
> + CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL,
> + CLK_CON_GAT_GATE_CLKCMU_TPU_UART,
> + DMYQCH_CON_CMU_TOP_CMUREF_QCH,
> + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0,
> + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1,
> + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2,
> + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3,
> + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4,
> + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5,
> + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6,
> + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7,
> + DMYQCH_CON_OTP_QCH,
> + QUEUE_CTRL_REG_BLK_CMU_CMU_TOP,
> + QUEUE_ENTRY0_BLK_CMU_CMU_TOP,
> + QUEUE_ENTRY1_BLK_CMU_CMU_TOP,
> + QUEUE_ENTRY2_BLK_CMU_CMU_TOP,
> + QUEUE_ENTRY3_BLK_CMU_CMU_TOP,
> + QUEUE_ENTRY4_BLK_CMU_CMU_TOP,
> + QUEUE_ENTRY5_BLK_CMU_CMU_TOP,
> + QUEUE_ENTRY6_BLK_CMU_CMU_TOP,
> + QUEUE_ENTRY7_BLK_CMU_CMU_TOP,
> + MIFMIRROR_QUEUE_CTRL_REG,
> + MIFMIRROR_QUEUE_ENTRY0,
> + MIFMIRROR_QUEUE_ENTRY1,
> + MIFMIRROR_QUEUE_ENTRY2,
> + MIFMIRROR_QUEUE_ENTRY3,
> + MIFMIRROR_QUEUE_ENTRY4,
> + MIFMIRROR_QUEUE_ENTRY5,
> + MIFMIRROR_QUEUE_ENTRY6,
> + MIFMIRROR_QUEUE_ENTRY7,
> + MIFMIRROR_QUEUE_BUSY,
> + GENERALIO_ACD_CHANNEL_0,
> + GENERALIO_ACD_CHANNEL_1,
> + GENERALIO_ACD_CHANNEL_2,
> + GENERALIO_ACD_CHANNEL_3,
> + GENERALIO_ACD_MASK,
> +};
> +
> +static const struct samsung_pll_clock cmu_top_pll_clks[] __initconst = {
> + /* CMU_TOP_PURECLKCOMP */
> + PLL(pll_0517x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
> + PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0,
> + NULL),
> + PLL(pll_0517x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
> + PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1,
> + NULL),
> + PLL(pll_0518x, CLK_FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk",
> + PLL_LOCKTIME_PLL_SHARED2, PLL_CON3_PLL_SHARED2,
> + NULL),
> + PLL(pll_0518x, CLK_FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk",
> + PLL_LOCKTIME_PLL_SHARED3, PLL_CON3_PLL_SHARED3,
> + NULL),
> + PLL(pll_0518x, CLK_FOUT_SPARE_PLL, "fout_spare_pll", "oscclk",
> + PLL_LOCKTIME_PLL_SPARE, PLL_CON3_PLL_SPARE,
> + NULL),
> +};
> +
> +/* List of parent clocks for Muxes in CMU_TOP */
> +PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" };
> +PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" };
> +PNAME(mout_shared2_pll_p) = { "oscclk", "fout_shared2_pll" };
> +PNAME(mout_shared3_pll_p) = { "oscclk", "fout_shared3_pll" };
> +PNAME(mout_spare_pll_p) = { "oscclk", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_BUS0 */
> +PNAME(mout_cmu_bus0_bus_p) = { "dout_shared0_div4", "dout_shared1_div4",
> + "dout_shared2_div2", "dout_shared3_div2",
> + "fout_spare_pll" };
> +
> +PNAME(mout_cmu_cmu_boost_p) = { "dout_shared0_div4", "dout_shared1_div4",
> + "dout_shared2_div2", "dout_shared3_div2" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_BUS1 */
> +PNAME(mout_cmu_bus1_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
> + "dout_shared1_div3", "dout_shared0_div4",
> + "dout_shared1_div4", "dout_shared2_div2",
> + "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_BUS2 */
> +PNAME(mout_cmu_bus2_bus_p) = { "dout_shared0_div2", "dout_shared1_div2",
> + "fout_shared2_pll", "fout_shared3_pll",
> + "dout_shared0_div3", "dout_shared1_div3",
> + "dout_shared0_div5", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */
> +PNAME(mout_cmu_core_bus_p) = { "dout_shared0_div2", "dout_shared1_div2",
> + "fout_shared2_pll", "fout_shared3_pll",
> + "dout_shared0_div3", "dout_shared1_div3",
> + "dout_shared0_div5", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_EH */
> +PNAME(mout_cmu_eh_bus_p) = { "dout_shared0_div2", "dout_shared1_div2",
> + "fout_shared2_pll", "fout_shared3_pll",
> + "dout_shared0_div3", "dout_shared1_div3",
> + "dout_shared0_div5", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_CPUCL2 */
> +PNAME(mout_cmu_cpucl2_switch_p) = { "fout_shared1_pll", "dout_shared0_div2",
> + "dout_shared1_div2", "fout_shared2_pll",
> + "fout_shared3_pll", "dout_shared0_div3",
> + "dout_shared1_div3", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_CPUCL1 */
> +PNAME(mout_cmu_cpucl1_switch_p) = { "fout_shared1_pll", "dout_shared0_div2",
> + "dout_shared1_div2", "fout_shared2_pll",
> + "fout_shared3_pll", "dout_shared0_div3",
> + "dout_shared1_div3", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_CPUCL0 */
> +PNAME(mout_cmu_cpucl0_switch_p) = { "fout_shared1_pll", "dout_shared0_div2",
> + "dout_shared1_div2", "fout_shared2_pll",
> + "fout_shared3_pll", "dout_shared0_div3",
> + "dout_shared1_div3", "fout_spare_pll" };
> +
> +PNAME(mout_cmu_cpucl0_dbg_p) = { "fout_shared2_pll", "fout_shared3_pll",
> + "dout_shared0_div4", "dout_shared1_div4",
> + "dout_shared2_div2", "fout_spare_pll" };
> +
> +PNAME(mout_cmu_hpm_p) = { "oscclk", "dout_shared1_div3",
> + "dout_shared0_div4", "dout_shared2_div2" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_G3D */
> +PNAME(mout_cmu_g3d_switch_p) = { "fout_shared2_pll", "dout_shared0_div3",
> + "fout_shared3_pll", "dout_shared1_div3",
> + "dout_shared0_div4", "dout_shared1_div4",
> + "fout_spare_pll" };
> +
> +PNAME(mout_cmu_g3d_busd_p) = { "dout_shared0_div2", "dout_shared1_div2",
> + "fout_shared2_pll", "fout_shared3_pll",
> + "dout_shared0_div3", "dout_shared1_div3",
> + "dout_shared0_div4", "fout_spare_pll" };
> +
> +PNAME(mout_cmu_g3d_glb_p) = { "dout_shared0_div2", "dout_shared1_div2",
> + "fout_shared2_pll", "fout_shared3_pll",
> + "dout_shared0_div3", "dout_shared1_div3",
> + "dout_shared0_div4", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_DPU */
> +PNAME(mout_cmu_dpu_p) = { "dout_shared0_div3", "fout_shared3_pll",
> + "dout_shared1_div3", "dout_shared0_div4",
> + "dout_shared1_div4", "dout_shared2_div2",
> + "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_DISP */
> +PNAME(mout_cmu_disp_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
> + "dout_shared1_div3", "dout_shared0_div4",
> + "dout_shared1_div4", "dout_shared2_div2",
> + "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_G2D */
> +PNAME(mout_cmu_g2d_g2d_p) = { "dout_shared0_div3", "fout_shared3_pll",
> + "dout_shared1_div3", "dout_shared0_div4",
> + "dout_shared1_div4", "dout_shared2_div2",
> + "fout_spare_pll" };
> +
> +PNAME(mout_cmu_g2d_mscl_p) = { "dout_shared0_div4", "dout_shared1_div4",
> + "dout_shared2_div2", "dout_shared3_div2",
> + "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI0 */
> +PNAME(mout_cmu_hsi0_usb31drd_p) = { "oscclk", "dout_shared2_div2" };
> +
> +PNAME(mout_cmu_hsi0_bus_p) = { "dout_shared0_div4", "dout_shared1_div4",
> + "dout_shared2_div2", "dout_shared3_div2",
> + "fout_spare_pll" };
> +
> +PNAME(mout_cmu_hsi0_dpgtc_p) = { "oscclk", "dout_shared0_div4",
> + "dout_shared2_div2", "fout_spare_pll" };
> +
> +PNAME(mout_cmu_hsi0_usbdpdbg_p) = { "oscclk", "dout_shared2_div2" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI1 */
> +PNAME(mout_cmu_hsi1_bus_p) = { "dout_shared0_div4", "dout_shared1_div4",
> + "dout_shared2_div2", "dout_shared3_div2",
> + "fout_spare_pll" };
> +
> +PNAME(mout_cmu_hsi1_pcie_p) = { "oscclk", "dout_shared2_div2" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI2 */
> +PNAME(mout_cmu_hsi2_bus_p) = { "dout_shared0_div4", "dout_shared1_div4",
> + "dout_shared2_div2", "dout_shared3_div2",
> + "fout_spare_pll" };
> +
> +PNAME(mout_cmu_hsi2_pcie0_p) = { "oscclk", "dout_shared2_div2" };
> +
> +PNAME(mout_cmu_hsi2_ufs_embd_p) = { "oscclk", "dout_shared0_div4",
> + "dout_shared2_div2", "fout_spare_pll" };
> +
> +PNAME(mout_cmu_hsi2_mmc_card_p) = { "fout_shared2_pll", "fout_shared3_pll",
> + "dout_shared0_div4", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_CSIS */
> +PNAME(mout_cmu_csis_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
> + "dout_shared1_div3", "dout_shared0_div4",
> + "dout_shared1_div4", "dout_shared2_div2",
> + "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_PDP */
> +PNAME(mout_cmu_pdp_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
> + "dout_shared1_div3", "dout_shared0_div4",
> + "dout_shared1_div4", "dout_shared2_div2",
> + "fout_spare_pll" };
> +
> +PNAME(mout_cmu_pdp_vra_p) = { "fout_shared2_pll", "dout_shared0_div3",
> + "fout_shared3_pll", "dout_shared1_div3",
> + "dout_shared0_div4", "dout_shared1_div4",
> + "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_IPP */
> +PNAME(mout_cmu_ipp_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
> + "dout_shared1_div3", "dout_shared0_div4",
> + "dout_shared1_div4", "dout_shared2_div2",
> + "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_G3AA */
> +PNAME(mout_cmu_g3aa_p) = { "dout_shared0_div3", "fout_shared3_pll",
> + "dout_shared1_div3", "dout_shared0_div4",
> + "dout_shared1_div4", "dout_shared2_div2",
> + "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_ITP */
> +PNAME(mout_cmu_itp_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
> + "dout_shared1_div3", "dout_shared0_div4",
> + "dout_shared1_div4", "dout_shared2_div2",
> + "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_DNS */
> +PNAME(mout_cmu_dns_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
> + "dout_shared1_div3", "dout_shared0_div4",
> + "dout_shared1_div4", "dout_shared2_div2",
> + "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_TNR */
> +PNAME(mout_cmu_tnr_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
> + "dout_shared1_div3", "dout_shared0_div4",
> + "dout_shared1_div4", "dout_shared2_div2",
> + "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_MCSC */
> +PNAME(mout_cmu_mcsc_itsc_p) = { "dout_shared0_div3", "fout_shared3_pll",
> + "dout_shared1_div3", "dout_shared0_div4",
> + "dout_shared1_div4", "dout_shared2_div2",
> + "fout_spare_pll" };
> +
> +PNAME(mout_cmu_mcsc_mcsc_p) = { "dout_shared0_div3", "fout_shared3_pll",
> + "dout_shared1_div3", "dout_shared0_div4",
> + "dout_shared1_div4", "dout_shared2_div2",
> + "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_GDC */
> +PNAME(mout_cmu_gdc_scsc_p) = { "dout_shared0_div3", "fout_shared3_pll",
> + "dout_shared1_div3", "dout_shared0_div4",
> + "dout_shared1_div4", "dout_shared2_div2",
> + "fout_spare_pll" };
> +
> +PNAME(mout_cmu_gdc_gdc0_p) = { "dout_shared0_div3", "fout_shared3_pll",
> + "dout_shared1_div3", "dout_shared0_div4",
> + "dout_shared1_div4", "dout_shared2_div2",
> + "fout_spare_pll" };
> +
> +PNAME(mout_cmu_gdc_gdc1_p) = { "dout_shared0_div3", "fout_shared3_pll",
> + "dout_shared1_div3", "dout_shared0_div4",
> + "dout_shared1_div4", "dout_shared2_div2",
> + "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_MFC */
> +PNAME(mout_cmu_mfc_mfc_p) = { "dout_shared0_div3", "fout_shared3_pll",
> + "dout_shared1_div3", "dout_shared0_div4",
> + "dout_shared1_div4", "dout_shared2_div2",
> + "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for DDRPHY0/1/2/3 */
> +
> +PNAME(mout_cmu_mif_switch_p) = { "fout_shared0_pll", "fout_shared1_pll",
> + "dout_shared0_div2", "dout_shared1_div2",
> + "fout_shared2_pll", "dout_shared0_div3",
> + "fout_shared3_pll", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_MIF0/1/2/3 */
> +PNAME(mout_cmu_mif_busp_p) = { "dout_shared0_div4", "dout_shared1_div4",
> + "dout_shared0_div5", "fout_spare_pll" };
> +
> +PNAME(mout_cmu_boost_p) = { "dout_shared0_div4", "dout_shared1_div4",
> + "dout_shared2_div2", "dout_shared3_div2" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_MISC */
> +PNAME(mout_cmu_misc_bus_p) = { "dout_shared0_div4", "dout_shared2_div2",
> + "dout_shared3_div2", "fout_spare_pll" };
> +PNAME(mout_cmu_misc_sss_p) = { "dout_shared0_div4", "dout_shared2_div2",
> + "dout_shared3_div2", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_PERIC0 */
> +PNAME(mout_cmu_peric0_bus_p) = { "dout_shared0_div4", "dout_shared2_div2",
> + "dout_shared3_div2", "fout_spare_pll" };
> +PNAME(mout_cmu_peric0_ip_p) = { "dout_shared0_div4", "dout_shared2_div2",
> + "dout_shared3_div2", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_PERIC1 */
> +PNAME(mout_cmu_peric1_bus_p) = { "dout_shared0_div4", "dout_shared2_div2",
> + "dout_shared3_div2", "fout_spare_pll" };
> +PNAME(mout_cmu_peric1_ip_p) = { "dout_shared0_div4", "dout_shared2_div2",
> + "dout_shared3_div2", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_TPU */
> +PNAME(mout_cmu_tpu_tpu_p) = { "dout_shared0_div2", "dout_shared1_div2",
> + "fout_shared2_pll", "fout_shared3_pll",
> + "dout_shared0_div3", "dout_shared1_div3",
> + "dout_shared0_div4", "fout_spare_pll" };
> +
> +PNAME(mout_cmu_tpu_tpuctl_p) = { "dout_shared0_div2", "dout_shared1_div2",
> + "fout_shared2_pll", "fout_shared3_pll",
> + "dout_shared0_div3", "dout_shared1_div3",
> + "dout_shared0_div4", "fout_spare_pll" };
> +
> +PNAME(mout_cmu_tpu_bus_p) = { "dout_shared0_div2", "dout_shared1_div2",
> + "fout_shared2_pll", "fout_shared3_pll",
> + "dout_shared0_div3", "dout_shared1_div3",
> + "dout_shared0_div4", "fout_spare_pll" };
> +
> +PNAME(mout_cmu_tpu_uart_p) = { "dout_shared0_div4", "dout_shared2_div2",
> + "dout_shared3_div2", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_BO */
> +PNAME(mout_cmu_bo_bus_p) = { "fout_shared2_pll", "dout_shared0_div3",
> + "fout_shared3_pll", "dout_shared1_div3",
> + "dout_shared0_div4", "dout_shared1_div4",
> + "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_G2D */
> +PNAME(mout_cmu_g2d_p) = { "dout_shared0_div3", "fout_shared3_pll",
> + "dout_shared1_div3", "dout_shared0_div4",
> + "dout_shared1_div4", "dout_shared2_div2",
> + "fout_spare_pll" };
> +
> +/* gs101 */
> +static const struct samsung_mux_clock cmu_top_mux_clks[] __initconst = {
> + /* CMU_TOP_PURECLKCOMP */
> + MUX(CLK_MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p,
> + PLL_CON0_PLL_SHARED0, 4, 1),
> + MUX(CLK_MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p,
> + PLL_CON0_PLL_SHARED1, 4, 1),
> + MUX(CLK_MOUT_SHARED2_PLL, "mout_shared2_pll", mout_shared2_pll_p,
> + PLL_CON0_PLL_SHARED2, 4, 1),
> + MUX(CLK_MOUT_SHARED3_PLL, "mout_shared3_pll", mout_shared3_pll_p,
> + PLL_CON0_PLL_SHARED3, 4, 1),
> + MUX(CLK_MOUT_SPARE_PLL, "mout_spare_pll", mout_spare_pll_p,
> + PLL_CON0_PLL_SPARE, 4, 1),
> +
> + /* BUS0 */
> + MUX(CLK_MOUT_BUS0_BUS, "mout_cmu_bus0_bus", mout_cmu_bus0_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS, 0, 2),
> + MUX(CLK_MOUT_CMU_BOOST, "mout_cmu_boost", mout_cmu_cmu_boost_p,
> + CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0, 2),
> +
> + /* BUS1 */
> + MUX(CLK_MOUT_BUS1_BUS, "mout_cmu_bus1_bus", mout_cmu_bus1_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS, 0, 2),
> +
> + /* BUS2 */
> + MUX(CLK_MOUT_BUS2_BUS, "mout_cmu_bus2_bus", mout_cmu_bus2_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS, 0, 2),
> +
> + /* CORE */
> + MUX(CLK_MOUT_CORE_BUS, "mout_cmu_core_bus", mout_cmu_core_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
> +
> + /* EH */
> + MUX(CLK_MOUT_EH_BUS, "mout_cmu_eh_bus", mout_cmu_eh_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
> +
> + /* CPUCL{0,1,2,} */
> + MUX(CLK_MOUT_CPUCL2_SWITCH, "mout_cmu_cpucl2_switch", mout_cmu_cpucl2_switch_p,
> + CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH, 0, 2),
> +
> + MUX(CLK_MOUT_CPUCL1_SWITCH, "mout_cmu_cpucl1_switch", mout_cmu_cpucl1_switch_p,
> + CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, 0, 2),
> +
> + MUX(CLK_MOUT_CPUCL0_SWITCH, "mout_cmu_cpucl0_switch", mout_cmu_cpucl0_switch_p,
> + CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, 0, 2),
> +
> + MUX(CLK_MOUT_CPUCL0_DBG, "mout_cmu_cpucl0_dbg", mout_cmu_cpucl0_dbg_p,
> + CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 2),
> +
> + MUX(CLK_MOUT_CMU_HPM, "mout_cmu_hpm", mout_cmu_hpm_p,
> + CLK_CON_MUX_MUX_CLKCMU_HPM, 0, 2),
> +
> + /* G3D */
> + MUX(CLK_MOUT_G3D_SWITCH, "mout_cmu_g3d_switch", mout_cmu_g3d_switch_p,
> + CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0, 2),
> +
> + MUX(CLK_MOUT_G3D_BUSD, "mout_cmu_g3d_busd", mout_cmu_g3d_busd_p,
> + CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD, 0, 2),
> +
> + MUX(CLK_MOUT_G3D_GLB, "mout_cmu_g3d_glb", mout_cmu_g3d_glb_p,
> + CLK_CON_MUX_MUX_CLKCMU_G3D_GLB, 0, 2),
> + /* DPU */
> + MUX(CLK_MOUT_DPU_BUS, "mout_cmu_dpu_bus", mout_cmu_dpu_p,
> + CLK_CON_MUX_MUX_CLKCMU_DPU_BUS, 0, 2),
> +
> + /* DISP */
> + MUX(CLK_MOUT_DISP_BUS, "mout_cmu_disp_bus", mout_cmu_disp_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_DISP_BUS, 0, 2),
> +
> + /* G2D */
> + MUX(CLK_MOUT_G2D_G2D, "mout_cmu_g2d_g2d", mout_cmu_g2d_g2d_p,
> + CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 0, 2),
> +
> + MUX(CLK_MOUT_G2D_MSCL, "mout_cmu_g2d_mscl", mout_cmu_g2d_mscl_p,
> + CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0, 2),
> +
> + /* HSI0 */
> + MUX(CLK_MOUT_HSI0_USB31DRD, "mout_cmu_hsi0_usb31drd", mout_cmu_hsi0_usb31drd_p,
> + CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD, 0, 2),
> +
> + MUX(CLK_MOUT_HSI0_BUS, "mout_cmu_hsi0_bus", mout_cmu_hsi0_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS, 0, 2),
> +
> + MUX(CLK_MOUT_HSI0_DPGTC, "mout_cmu_hsi0_dpgtc", mout_cmu_hsi0_dpgtc_p,
> + CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC, 0, 2),
> +
> + MUX(CLK_MOUT_HSI0_USBDPDGB, "mout_cmu_hsi0_usbdpdbg", mout_cmu_hsi0_usbdpdbg_p,
> + CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG, 0, 2),
> +
> + /* HSI1 */
> + MUX(CLK_MOUT_HSI1_BUS, "mout_cmu_hsi1_bus", mout_cmu_hsi1_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS, 0, 2),
> +
> + MUX(CLK_MOUT_HSI1_PCIE, "mout_cmu_hsi1_pcie", mout_cmu_hsi1_pcie_p,
> + CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE, 0, 2),
> + /* HSI2 */
> + MUX(CLK_MOUT_HSI2_BUS, "mout_cmu_hsi2_bus", mout_cmu_hsi2_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS, 0, 2),
> +
> + MUX(CLK_MOUT_HSI2_PCIE, "mout_cmu_hsi2_pcie", mout_cmu_hsi2_pcie0_p,
> + CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE, 0, 2),
> +
> + MUX(CLK_MOUT_HSI2_UFS_EMBD, "mout_cmu_hsi2_ufs_embd", mout_cmu_hsi2_ufs_embd_p,
> + CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD, 0, 2),
> +
> + MUX(CLK_MOUT_HSI2_MMC_CARD, "mout_cmu_hsi2_mmc_card", mout_cmu_hsi2_mmc_card_p,
> + CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD, 0, 2),
> +
> + /* CSIS */
> + MUX(CLK_MOUT_CSIS, "mout_cmu_csis_bus", mout_cmu_csis_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS, 0, 2),
> +
> + /* PDP */
> + MUX(CLK_MOUT_PDP_BUS, "mout_cmu_pdp_bus", mout_cmu_pdp_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_PDP_BUS, 0, 2),
> +
> + /* IPP */
> + MUX(CLK_MOUT_IPP_BUS, "mout_cmu_ipp_bus", mout_cmu_ipp_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_IPP_BUS, 0, 2),
> +
> + /* G3AA */
> + MUX(CLK_MOUT_G3AA, "mout_cmu_g3aa", mout_cmu_g3aa_p,
> + CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 0, 2),
> +
> + /* ITP */
> + MUX(CLK_MOUT_ITP, "mout_cmu_itp_bus", mout_cmu_itp_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_ITP_BUS, 0, 2),
> +
> + /* DNS */
> + MUX(CLK_MOUT_DNS_BUS, "mout_cmu_dns_bus", mout_cmu_dns_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_DNS_BUS, 0, 2),
> +
> + /* TNR */
> + MUX(CLK_MOUT_TNR_BUS, "mout_cmu_tnr_bus", mout_cmu_tnr_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, 0, 2),
> +
> + /* MCSC*/
> + MUX(CLK_MOUT_MCSC_ITSC, "mout_cmu_mcsc_itsc", mout_cmu_mcsc_itsc_p,
> + CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC, 0, 2),
> +
> + MUX(CLK_MOUT_MCSC_MCSC, "mout_cmu_mcsc_mcsc", mout_cmu_mcsc_mcsc_p,
> + CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC, 0, 2),
> +
> + /* GDC */
> + MUX(CLK_MOUT_GDC_SCSC, "mout_cmu_gdc_scsc", mout_cmu_gdc_scsc_p,
> + CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC, 0, 2),
> +
> + MUX(CLK_MOUT_GDC_GDC0, "mout_cmu_gdc_gdc0", mout_cmu_gdc_gdc0_p,
> + CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0, 0, 2),
> +
> + MUX(CLK_MOUT_GDC_GDC1, "mout_cmu_gdc_gdc1", mout_cmu_gdc_gdc1_p,
> + CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1, 0, 2),
> +
> + /* MFC */
> + MUX(CLK_MOUT_MFC_MFC, "mout_cmu_mfc_mfc", mout_cmu_mfc_mfc_p,
> + CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 0, 2),
> +
> + /* DDRPHY0/1/2/3 */
> + MUX(CLK_MOUT_MIF_SWITCH, "mout_cmu_mif_switch", mout_cmu_mif_switch_p,
> + CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0, 2),
> +
> + /* MIF0/1/2/3 */
> + MUX(CLK_MOUT_MIF_BUS, "mout_cmu_mif_busp", mout_cmu_mif_busp_p,
> + CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, 0, 2),
> +
> + /* MISC */
> + MUX(CLK_MOUT_MISC_BUS, "mout_cmu_misc_bus", mout_cmu_misc_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_MISC_BUS, 0, 2),
> + MUX(CLK_MOUT_MISC_SSS, "mout_cmu_misc_sss", mout_cmu_misc_sss_p,
> + CLK_CON_MUX_MUX_CLKCMU_MISC_SSS, 0, 2),
> +
> + /* PERI0 */
> + MUX(CLK_MOUT_PERIC0_IP, "mout_cmu_peric0_ip", mout_cmu_peric0_ip_p,
> + CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 2),
> + MUX(CLK_MOUT_PERIC0_BUS, "mout_cmu_peric0_bus", mout_cmu_peric0_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0, 2),
> + /* PERI1 */
> + MUX(CLK_MOUT_PERIC1_IP, "mout_cmu_peric1_ip", mout_cmu_peric1_ip_p,
> + CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 2),
> + MUX(CLK_MOUT_PERIC1_BUS, "mout_cmu_peric1_bus", mout_cmu_peric1_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0, 2),
> +
> + /* TPU */
> + MUX(CLK_MOUT_TPU_TPU, "mout_cmu_tpu_tpu", mout_cmu_tpu_tpu_p,
> + CLK_CON_MUX_MUX_CLKCMU_TPU_TPU, 0, 2),
> +
> + MUX(CLK_MOUT_TPU_TPUCTL, "mout_cmu_tpu_tpuctl", mout_cmu_tpu_tpuctl_p,
> + CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL, 0, 2),
> +
> + MUX(CLK_MOUT_TPU_BUS, "mout_cmu_tpu_bus", mout_cmu_tpu_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_TPU_BUS, 0, 2),
> +
> + MUX(CLK_MOUT_TPU_UART, "mout_cmu_tpu_uart", mout_cmu_tpu_uart_p,
> + CLK_CON_MUX_MUX_CLKCMU_TPU_UART, 0, 2),
> +
> + /* BO */
> + MUX(CLK_MOUT_BO_BUS, "mout_cmu_bo_bus", mout_cmu_bo_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_BO_BUS, 0, 2),
> +};
> +
> +static const struct samsung_div_clock cmu_top_div_clks[] __initconst = {
> + /* CMU_TOP_PURECLKCOMP */
> + DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "mout_shared0_pll",
> + CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
> + DIV(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2", "mout_shared0_pll",
> + CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
> + DIV(CLK_DOUT_SHARED0_DIV5, "dout_shared0_div5", "mout_shared0_pll",
> + CLK_CON_DIV_PLL_SHARED0_DIV5, 0, 2),
> + DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "dout_shared0_div2",
> + CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
> +
> + DIV(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2", "mout_shared1_pll",
> + CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
> + DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "mout_shared1_pll",
> + CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
> + DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "mout_shared1_pll",
> + CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
> +
> + DIV(CLK_DOUT_SHARED2_DIV2, "dout_shared2_div2", "mout_shared2_pll",
> + CLK_CON_DIV_PLL_SHARED2_DIV2, 0, 1),
> +
> + DIV(CLK_DOUT_SHARED3_DIV2, "dout_shared3_div2", "mout_shared3_pll",
> + CLK_CON_DIV_PLL_SHARED3_DIV2, 0, 1),
> +
> + /* BUS0 */
> + DIV(CLK_DOUT_BUS0_BUS, "dout_cmu_bus0_bus_div", "gout_cmu_bus0_bus",
> + CLK_CON_DIV_CLKCMU_BUS0_BUS, 0, 4),
> + DIV(CLK_DOUT_CMU_BOOST, "dout_cmu_boost", "gout_cmu_cmu_boost",
> + CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, 0, 2),
> +
> + /* BUS1 */
> + DIV(CLK_DOUT_BUS1_BUS, "dout_cmu_bus1_bus", "gout_cmu_bus1_bus",
> + CLK_CON_DIV_CLKCMU_BUS1_BUS, 0, 4),
> +
> + /* BUS2 */
> + DIV(CLK_DOUT_BUS2_BUS, "dout_cmu_bus2_bus", "gout_cmu_bus2_bus",
> + CLK_CON_DIV_CLKCMU_BUS2_BUS, 0, 4),
> +
> + /* CORE */
> + DIV(CLK_DOUT_CORE_BUS, "dout_cmu_core_bus", "gout_cmu_core_bus",
> + CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
> +
> + /* EH */
> + DIV(CLK_DOUT_EH_BUS, "dout_cmu_eh_bus", "gout_cmu_eh_bus",
> + CLK_CON_DIV_CLKCMU_EH_BUS, 0, 4),
> +
> + /* CPUCL{0,1,2,} */
> + DIV(CLK_DOUT_CPUCL2_SWITCH, "dout_cmu_cpucl2_switch", "gout_cmu_cpucl2_switch",
> + CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH, 0, 3),
> +
> + DIV(CLK_DOUT_CPUCL1_SWITCH, "dout_cmu_cpucl1_switch", "gout_cmu_cpucl1_switch",
> + CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0, 3),
> +
> + DIV(CLK_DOUT_CPUCL0_SWITCH, "dout_cmu_cpucl0_switch", "gout_cmu_cpucl0_switch",
> + CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3),
> +
> + DIV(CLK_DOUT_CPUCL0_DBG, "dout_cmu_cpucl0_dbg", "gout_cmu_cpucl0_dbg",
> + CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 4),
> +
> + DIV(CLK_DOUT_CMU_HPM, "dout_cmu_hpm", "gout_cmu_hpm",
> + CLK_CON_DIV_CLKCMU_HPM, 0, 2),
> +
> + /* G3D */
> + DIV(CLK_DOUT_G3D_SWITCH, "dout_cmu_g3d_switch", "gout_cmu_g3d_switch",
> + CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3),
> +
> + DIV(CLK_DOUT_G3D_SWITCH, "dout_cmu_g3d_busd", "gout_cmu_g3d_busd",
> + CLK_CON_DIV_CLKCMU_G3D_BUSD, 0, 4),
> +
> + DIV(CLK_DOUT_G3D_GLB, "dout_cmu_g3d_glb", "gout_cmu_g3d_glb",
> + CLK_CON_DIV_CLKCMU_G3D_GLB, 0, 4),
> +
> + /* DPU */
> + DIV(CLK_DOUT_DPU_BUS, "dout_cmu_dpu_bus", "gout_cmu_dpu_bus",
> + CLK_CON_DIV_CLKCMU_DPU_BUS, 0, 4),
> +
> + /* DISP */
> + DIV(CLK_DOUT_DISP_BUS, "dout_cmu_disp_bus", "gout_cmu_disp_bus",
> + CLK_CON_DIV_CLKCMU_DISP_BUS, 0, 4),
> +
> + /* G2D */
> + DIV(CLK_DOUT_G2D_G2D, "dout_cmu_g2d_g2d", "gout_cmu_g2d_g2d",
> + CLK_CON_DIV_CLKCMU_G2D_G2D, 0, 4),
> +
> + DIV(CLK_DOUT_G2D_MSCL, "dout_cmu_g2d_mscl", "gout_cmu_g2d_mscl",
> + CLK_CON_DIV_CLKCMU_G2D_MSCL, 0, 4),
> +
> + /* HSI0 */
> + DIV(CLK_DOUT_HSI0_USB31DRD, "dout_cmu_hsi0_usb31drd", "gout_cmu_hsi0_usb31drd",
> + CLK_CON_DIV_CLKCMU_HSI0_USB31DRD, 0, 5),
> +
> + DIV(CLK_DOUT_HSI0_BUS, "dout_cmu_hsi0_bus", "gout_cmu_hsi0_bus",
> + CLK_CON_DIV_CLKCMU_HSI0_BUS, 0, 4),
> +
> + DIV(CLK_DOUT_HSI0_DPGTC, "dout_cmu_hsi0_dpgtc", "gout_cmu_hsi0_dpgtc",
> + CLK_CON_DIV_CLKCMU_HSI0_DPGTC, 0, 4),
> +
> + /* TODO register exists but all lower bits are reserved */
> + DIV(CLK_DOUT_HSI0_USBDPDGB, "dout_cmu_hsi0_usbdpdbg", "gout_cmu_hsi0_usbdpdbg",
> + CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG, 0, 0),
> +
> + /* HSI1 */
> + DIV(CLK_DOUT_HSI1_BUS, "dout_cmu_hsi1_bus", "gout_cmu_hsi1_bus",
> + CLK_CON_DIV_CLKCMU_HSI1_BUS, 0, 4),
> +
> + DIV(CLK_DOUT_HSI1_PCIE, "dout_cmu_hsi1_pcie", "gout_cmu_hsi1_pcie",
> + CLK_CON_DIV_CLKCMU_HSI1_PCIE, 0, 3),
> + /* HSI2 */
> + DIV(CLK_DOUT_HSI2_BUS, "dout_cmu_hsi2_bus", "gout_cmu_hsi2_bus",
> + CLK_CON_DIV_CLKCMU_HSI2_BUS, 0, 4),
> +
> + DIV(CLK_DOUT_HSI2_PCIE, "dout_cmu_hsi2_pcie", "gout_cmu_hsi2_pcie",
> + CLK_CON_DIV_CLKCMU_HSI2_PCIE, 0, 3),
> +
> + DIV(CLK_DOUT_HSI2_UFS_EMBD, "dout_cmu_hsi2_ufs_embd", "gout_cmu_hsi2_ufs_embd",
> + CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD, 0, 4),
> +
> + DIV(CLK_DOUT_HSI2_MMC_CARD, "dout_cmu_hsi2_mmc_card", "gout_cmu_hsi2_mmc_card",
> + CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD, 0, 9),
> +
> + /* CSIS */
> + DIV(CLK_DOUT_CSIS, "dout_cmu_csis_bus", "gout_cmu_csis_bus",
> + CLK_CON_DIV_CLKCMU_CSIS_BUS, 0, 4),
> +
> + /* PDP */
> + DIV(CLK_DOUT_PDP_BUS, "dout_cmu_pdp_bus", "gout_cmu_pdp_bus",
> + CLK_CON_DIV_CLKCMU_PDP_BUS, 0, 4),
> +
> + /* IPP */
> + DIV(CLK_DOUT_IPP_BUS, "dout_cmu_ipp_bus", "gout_cmu_ipp_bus",
> + CLK_CON_DIV_CLKCMU_IPP_BUS, 0, 4),
> +
> + /* G3AA */
> + DIV(CLK_DOUT_G3AA, "dout_cmu_g3aa", "gout_cmu_g3aa",
> + CLK_CON_DIV_CLKCMU_G3AA_G3AA, 0, 4),
> +
> + /* ITP */
> + DIV(CLK_DOUT_ITP, "dout_cmu_itp_bus", "gout_cmu_itp_bus",
> + CLK_CON_DIV_CLKCMU_ITP_BUS, 0, 4),
> +
> + /* DNS */
> + DIV(CLK_DOUT_DNS_BUS, "dout_cmu_dns_bus", "gout_cmu_dns_bus",
> + CLK_CON_DIV_CLKCMU_DNS_BUS, 0, 4),
> +
> + /* TNR */
> + DIV(CLK_DOUT_TNR_BUS, "dout_cmu_tnr_bus", "gout_cmu_tnr_bus",
> + CLK_CON_DIV_CLKCMU_TNR_BUS, 0, 4),
> +
> + /* MCSC*/
> + DIV(CLK_DOUT_MCSC_ITSC, "dout_cmu_mcsc_itsc", "gout_cmu_mcsc_itsc",
> + CLK_CON_DIV_CLKCMU_MCSC_ITSC, 0, 4),
> +
> + DIV(CLK_DOUT_MCSC_MCSC, "dout_cmu_mcsc_mcsc", "gout_cmu_mcsc_mcsc",
> + CLK_CON_DIV_CLKCMU_MCSC_MCSC, 0, 4),
> +
> + /* GDC */
> + DIV(CLK_DOUT_GDC_SCSC, "dout_cmu_gdc_scsc", "gout_cmu_gdc_scsc",
> + CLK_CON_DIV_CLKCMU_GDC_SCSC, 0, 4),
> +
> + DIV(CLK_DOUT_GDC_GDC0, "dout_cmu_gdc_gdc0", "gout_cmu_gdc_gdc0",
> + CLK_CON_DIV_CLKCMU_GDC_GDC0, 0, 4),
> +
> + DIV(CLK_DOUT_GDC_GDC1, "dout_cmu_gdc_gdc1", "gout_cmu_gdc_gdc1",
> + CLK_CON_DIV_CLKCMU_GDC_GDC1, 0, 4),
> +
> + /* MFC */
> + DIV(CLK_DOUT_MFC_MFC, "dout_cmu_mfc_mfc", "gout_cmu_mfc_mfc",
> + CLK_CON_DIV_CLKCMU_MFC_MFC, 0, 4),
> +
> + /* MIF0/1/2/3 */
> + DIV(CLK_DOUT_MIF_BUS, "dout_cmu_mif_busp", "gout_cmu_mif_busp",
> + CLK_CON_DIV_CLKCMU_MIF_BUSP, 0, 4),
> +
> + /* MISC */
> + DIV(CLK_DOUT_MISC_BUS, "dout_cmu_misc_bus", "gout_cmu_misc_bus",
> + CLK_CON_DIV_CLKCMU_MISC_BUS, 0, 4),
> + DIV(CLK_DOUT_MISC_SSS, "dout_cmu_misc_sss", "gout_cmu_misc_sss",
> + CLK_CON_DIV_CLKCMU_MISC_SSS, 0, 4),
> +
> + /* PERI0 */
> + DIV(CLK_DOUT_PERIC0_BUS, "dout_cmu_peric0_bus", "gout_cmu_peric0_bus",
> + CLK_CON_DIV_CLKCMU_PERIC0_BUS, 0, 4),
> + DIV(CLK_DOUT_PERIC0_IP, "dout_cmu_peric0_ip", "gout_cmu_peric0_ip",
> + CLK_CON_DIV_CLKCMU_PERIC0_IP, 0, 4),
> +
> + /* PERI1 */
> + DIV(CLK_DOUT_PERIC1_BUS, "dout_cmu_peric1_bus", "gout_cmu_peric1_bus",
> + CLK_CON_DIV_CLKCMU_PERIC1_BUS, 0, 4),
> + DIV(CLK_DOUT_PERIC1_IP, "dout_cmu_peric1_ip", "gout_cmu_peric1_ip",
> + CLK_CON_DIV_CLKCMU_PERIC1_IP, 0, 4),
> +
> + /* TPU */
> + DIV(CLK_DOUT_TPU_TPU, "dout_cmu_tpu_tpu", "gout_cmu_tpu_tpu",
> + CLK_CON_DIV_CLKCMU_TPU_TPU, 0, 4),
> +
> + DIV(CLK_DOUT_TPU_TPUCTL, "dout_cmu_tpu_tpuctl", "gout_cmu_tpu_tpuctl",
> + CLK_CON_DIV_CLKCMU_TPU_TPUCTL, 0, 4),
> +
> + DIV(CLK_DOUT_TPU_BUS, "dout_cmu_tpu_bus", "gout_cmu_tpu_bus",
> + CLK_CON_DIV_CLKCMU_TPU_BUS, 0, 4),
> +
> + DIV(CLK_DOUT_TPU_UART, "dout_cmu_tpu_uart", "gout_cmu_tpu_uart",
> + CLK_CON_DIV_CLKCMU_TPU_UART, 0, 4),
> +
> + /* BO */
> + DIV(CLK_DOUT_BO_BUS, "dout_cmu_bo_bus", "gout_cmu_bo_bus",
> + CLK_CON_DIV_CLKCMU_BO_BUS, 0, 4),
> +
> +};
> +
> +static const struct samsung_gate_clock cmu_top_gate_clks[] __initconst = {
> + /* CORE */
> +
> + /* MISC */
> + GATE(CLK_GOUT_MISC_BUS, "gout_cmu_misc_bus", "mout_cmu_misc_bus",
> + CLK_CON_GAT_GATE_CLKCMU_MISC_BUS, 21, 0, 0),
> + GATE(CLK_GOUT_MISC_SSS, "gout_cmu_misc_sss", "mout_cmu_misc_sss",
> + CLK_CON_GAT_GATE_CLKCMU_MISC_SSS, 21, 0, 0),
> +
> + /* BUS0 */
> + GATE(CLK_GOUT_BUS0_BUS, "gout_cmu_bus0_bus", "mout_cmu_bus0_bus",
> + CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS, 21, 0, 0),
> +
> + /* BUS1 */
> + GATE(CLK_GOUT_BUS1_BUS, "gout_cmu_bus1_bus", "mout_cmu_bus1_bus",
> + CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS, 21, 0, 0),
> +
> + /* BUS2 */
> + GATE(CLK_GOUT_BUS2_BUS, "gout_cmu_bus2_bus", "mout_cmu_bus2_bus",
> + CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS, 21, 0, 0),
> +
> + /* CORE */
> + GATE(CLK_GOUT_CORE_BUS, "gout_cmu_core_bus", "mout_cmu_core_bus",
> + CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0),
> +
> + /* EH */
> + GATE(CLK_GOUT_EH_BUS, "gout_cmu_eh_bus", "mout_cmu_eh_bus",
> + CLK_CON_GAT_GATE_CLKCMU_EH_BUS, 21, 0, 0),
> +
> + /* CPUCL{0,1,2,} */
> + GATE(CLK_GOUT_CPUCL2_SWITCH, "gout_cmu_cpucl2_switch", "mout_cmu_cpucl2_switch",
> + CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH, 21, 0, 0),
> +
> + GATE(CLK_GOUT_CPUCL1_SWITCH, "gout_cmu_cpucl1_switch", "mout_cmu_cpucl1_switch",
> + CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, 21, 0, 0),
> +
> + GATE(CLK_GOUT_CPUCL0_SWITCH, "gout_cmu_cpucl0_switch", "mout_cmu_cpucl0_switch",
> + CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, 21, 0, 0),
> +
> + GATE(CLK_GOUT_CPUCL0_DBG, "gout_cmu_cpucl0_dbg", "mout_cmu_cpucl0_dbg",
> + CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS, 21, 0, 0),
> +
> + GATE(CLK_GOUT_CMU_HPM, "gout_cmu_hpm", "mout_cmu_hpm",
> + CLK_CON_GAT_GATE_CLKCMU_HPM, 21, 0, 0),
> +
> + /* G3D */
> + GATE(CLK_GOUT_G3D_SWITCH, "gout_cmu_g3d_switch", "mout_cmu_g3d_switch",
> + CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 21, 0, 0),
> +
> + GATE(CLK_GOUT_G3D_SWITCH, "gout_cmu_g3d_busd", "mout_cmu_g3d_busd",
> + CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD, 21, 0, 0),
> +
> + GATE(CLK_GOUT_G3D_GLB, "gout_cmu_g3d_glb", "mout_cmu_g3d_glb",
> + CLK_CON_GAT_GATE_CLKCMU_G3D_GLB, 21, 0, 0),
> + /* DPU */
> + GATE(CLK_GOUT_DPU_BUS, "gout_cmu_dpu_bus", "mout_cmu_dpu_bus",
> + CLK_CON_GAT_GATE_CLKCMU_DPU_BUS, 21, 0, 0),
> + /* DISP */
> + GATE(CLK_GOUT_DISP_BUS, "gout_cmu_disp_bus", "mout_cmu_disp_bus",
> + CLK_CON_GAT_GATE_CLKCMU_DISP_BUS, 21, 0, 0),
> +
> + /* G2D */
> + GATE(CLK_GOUT_G2D_G2D, "gout_cmu_g2d_g2d", "mout_cmu_g2d_g2d",
> + CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 21, 0, 0),
> +
> + GATE(CLK_GOUT_G2D_MSCL, "gout_cmu_g2d_mscl", "mout_cmu_g2d_mscl",
> + CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL, 21, 0, 0),
> + /* HSI0 */
> + GATE(CLK_GOUT_HSI0_USB31DRD, "gout_cmu_hsi0_usb31drd", "mout_cmu_hsi0_usb31drd",
> + CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD, 21, 0, 0),
> +
> + GATE(CLK_GOUT_HSI0_BUS, "gout_cmu_hsi0_bus", "mout_cmu_hsi0_bus",
> + CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS, 21, 0, 0),
> +
> + GATE(CLK_GOUT_HSI0_DPGTC, "gout_cmu_hsi0_dpgtc", "mout_cmu_hsi0_dpgtc",
> + CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC, 21, 0, 0),
> +
> + GATE(CLK_GOUT_HSI0_USBDPDGB, "gout_cmu_hsi0_usbdpdbg", "mout_cmu_hsi0_usbdpdbg",
> + CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG, 21, 0, 0),
> + /* HSI1 */
> + GATE(CLK_GOUT_HSI1_BUS, "gout_cmu_hsi1_bus", "mout_cmu_hsi1_bus",
> + CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS, 21, 0, 0),
> +
> + GATE(CLK_GOUT_HSI1_PCIE, "gout_cmu_hsi1_pcie", "mout_cmu_hsi1_pcie",
> + CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE, 21, 0, 0),
> + /* HSI2 */
> + GATE(CLK_GOUT_HSI2_BUS, "gout_cmu_hsi2_bus", "mout_cmu_hsi2_bus",
> + CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS, 21, 0, 0),
> + GATE(CLK_GOUT_HSI2_PCIE, "gout_cmu_hsi2_pcie", "mout_cmu_hsi2_pcie",
> + CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE, 21, 0, 0),
> +
> + GATE(CLK_GOUT_HSI2_UFS_EMBD, "gout_cmu_hsi2_ufs_embd", "mout_cmu_hsi2_ufs_embd",
> + CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD, 21, 0, 0),
> + GATE(CLK_GOUT_HSI2_MMC_CARD, "gout_cmu_hsi2_mmc_card", "mout_cmu_hsi2_mmc_card",
> + CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD, 21, 0, 0),
> + /* CSIS */
> + GATE(CLK_GOUT_CSIS, "gout_cmu_csis_bus", "mout_cmu_csis_bus",
> + CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS, 21, 0, 0),
> + /* PDP */
> + GATE(CLK_GOUT_PDP_BUS, "gout_cmu_pdp_bus", "mout_cmu_pdp_bus",
> + CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 21, 0, 0),
> +
> + /* IPP */
> + GATE(CLK_GOUT_IPP_BUS, "gout_cmu_ipp_bus", "mout_cmu_ipp_bus",
> + CLK_CON_GAT_GATE_CLKCMU_IPP_BUS, 21, 0, 0),
> + /* G3AA */
> + GATE(CLK_GOUT_G3AA, "gout_cmu_g3aa", "mout_cmu_g3aa",
> + CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 21, 0, 0),
> +
> + /* ITP */
> + GATE(CLK_GOUT_ITP, "gout_cmu_itp_bus", "mout_cmu_itp_bus",
> + CLK_CON_GAT_GATE_CLKCMU_ITP_BUS, 21, 0, 0),
> +
> + /* DNS */
> + GATE(CLK_GOUT_DNS_BUS, "gout_cmu_dns_bus", "mout_cmu_dns_bus",
> + CLK_CON_GAT_GATE_CLKCMU_DNS_BUS, 21, 0, 0),
> +
> + /* TNR */
> + GATE(CLK_GOUT_TNR_BUS, "gout_cmu_tnr_bus", "mout_cmu_tnr_bus",
> + CLK_CON_GAT_GATE_CLKCMU_TNR_BUS, 21, 0, 0),
> +
> + /* MCSC*/
> + GATE(CLK_GOUT_MCSC_ITSC, "gout_cmu_mcsc_itsc", "mout_cmu_mcsc_itsc",
> + CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC, 21, 0, 0),
> +
> + GATE(CLK_GOUT_MCSC_MCSC, "gout_cmu_mcsc_mcsc", "mout_cmu_mcsc_mcsc",
> + CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC, 21, 0, 0),
> +
> + /* GDC */
> + GATE(CLK_GOUT_GDC_SCSC, "gout_cmu_gdc_scsc", "mout_cmu_gdc_scsc",
> + CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC, 21, 0, 0),
> +
> + GATE(CLK_GOUT_GDC_GDC0, "gout_cmu_gdc_gdc0", "mout_cmu_gdc_gdc0",
> + CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0, 21, 0, 0),
> +
> + GATE(CLK_GOUT_GDC_GDC1, "gout_cmu_gdc_gdc1", "mout_cmu_gdc_gdc1",
> + CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1, 21, 0, 0),
> +
> + /* MFC */
> + GATE(CLK_GOUT_MFC_MFC, "gout_cmu_mfc_mfc", "mout_cmu_mfc_mfc",
> + CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, 21, 0, 0),
> +
> + /* DDRPHY0/1/2/3 */
> + GATE(CLK_GOUT_MIF_SWITCH, "gout_cmu_mif_switch", "mout_cmu_mif_switch",
> + CLK_CON_GAT_CLKCMU_MIF_SWITCH, 21, 0, 0),
> +
> + /* MIF0/1/2/3 */
> + GATE(CLK_GOUT_MIF_BUS, "gout_cmu_mif_busp", "mout_cmu_mif_busp",
> + CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP, 21, 0, 0),
> +
> + GATE(CLK_GOUT_CMU_BOOST, "gout_cmu_cmu_boost", "mout_cmu_boost",
> + CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST, 21, 0, 0),
> +
> + /* MISC */
> + GATE(CLK_GOUT_MISC_BUS, "gout_cmu_misc_bus", "mout_cmu_misc_bus",
> + CLK_CON_GAT_GATE_CLKCMU_MISC_BUS, 21, 0, 0),
> + GATE(CLK_GOUT_MISC_SSS, "gout_cmu_misc_sss", "mout_cmu_misc_sss",
> + CLK_CON_GAT_GATE_CLKCMU_MISC_SSS, 21, 0, 0),
> +
> + /* PERI0 */
> + GATE(CLK_GOUT_PERIC0_BUS, "gout_cmu_peric0_bus", "mout_cmu_peric0_bus",
> + CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS, 21, 0, 0),
> + GATE(CLK_GOUT_PERIC0_IP, "gout_cmu_peric0_ip", "mout_cmu_peric0_ip",
> + CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP, 21, 0, 0),
> +
> + /* PERI1 */
> + GATE(CLK_GOUT_PERIC1_BUS, "gout_cmu_peric1_bus", "mout_cmu_peric1_bus",
> + CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS, 21, 0, 0),
> + GATE(CLK_GOUT_PERIC1_IP, "gout_cmu_peric1_ip", "mout_cmu_peric1_ip",
> + CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP, 21, 0, 0),
> +
> + /* TPU */
> + GATE(CLK_GOUT_TPU_TPU, "gout_cmu_tpu_tpu", "mout_cmu_tpu_tpu",
> + CLK_CON_GAT_GATE_CLKCMU_TPU_TPU, 21, 0, 0),
> + GATE(CLK_GOUT_TPU_TPUCTL, "gout_cmu_tpu_tpuctl", "mout_cmu_tpu_tpuctl",
> + CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL, 21, 0, 0),
> + GATE(CLK_GOUT_TPU_BUS, "gout_cmu_tpu_bus", "mout_cmu_tpu_bus",
> + CLK_CON_GAT_GATE_CLKCMU_TPU_BUS, 21, 0, 0),
> + GATE(CLK_GOUT_TPU_UART, "gout_cmu_tpu_uart", "mout_cmu_tpu_uart",
> + CLK_CON_GAT_GATE_CLKCMU_TPU_UART, 21, 0, 0),
> +
> + /* BO */
> + GATE(CLK_GOUT_BO_BUS, "gout_cmu_bo_bus", "mout_cmu_bo_bus",
> + CLK_CON_GAT_GATE_CLKCMU_BO_BUS, 21, 0, 0),
> +
> +};
> +
> +static const struct samsung_cmu_info top_cmu_info __initconst = {
> + .pll_clks = cmu_top_pll_clks,
> + .nr_pll_clks = ARRAY_SIZE(cmu_top_pll_clks),
> + .mux_clks = cmu_top_mux_clks,
> + .nr_mux_clks = ARRAY_SIZE(cmu_top_mux_clks),
> + .div_clks = cmu_top_div_clks,
> + .nr_div_clks = ARRAY_SIZE(cmu_top_div_clks),
> + .gate_clks = cmu_top_gate_clks,
> + .nr_gate_clks = ARRAY_SIZE(cmu_top_gate_clks),
> + .nr_clk_ids = TOP_NR_CLK,
> + .clk_regs = cmu_top_clk_regs,
> + .nr_clk_regs = ARRAY_SIZE(cmu_top_clk_regs),
> +};
> +
> +static void __init gs101_cmu_top_init(struct device_node *np)
> +{
> + exynos_arm64_register_cmu(NULL, np, &top_cmu_info);
> +}
> +
> +/* Register CMU_TOP early, as it's a dependency for other early domains */
> +CLK_OF_DECLARE(gs101_cmu_top, "google,gs101-cmu-top",
> + gs101_cmu_top_init);
> --
> 2.42.0.582.g8ccd20d70d-goog
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 13/21] clk: samsung: clk-gs101: Add cmu_top registers, plls, mux and gates
2023-10-05 15:56 ` Peter Griffin
@ 2023-10-05 17:45 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 150+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-05 17:45 UTC (permalink / raw)
To: Peter Griffin, robh+dt, krzysztof.kozlowski+dt, mturquette,
conor+dt, sboyd, tomasz.figa, s.nawrocki, linus.walleij, wim,
linux, catalin.marinas, will, arnd, olof, cw00.choi
Cc: tudor.ambarus, andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog
On 05/10/2023 17:56, Peter Griffin wrote:
> CMU_TOP is the top level clock management unit which contains PLLs, muxes
> and gates that feed the other clock management units.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> drivers/clk/samsung/Kconfig | 9 +
> drivers/clk/samsung/Makefile | 1 +
> drivers/clk/samsung/clk-gs101.c | 1558 +++++++++++++++++++++++++++++++
> 3 files changed, 1568 insertions(+)
> create mode 100644 drivers/clk/samsung/clk-gs101.c
>
> diff --git a/drivers/clk/samsung/Kconfig b/drivers/clk/samsung/Kconfig
> index 76a494e95027..4c8f173c4dec 100644
> --- a/drivers/clk/samsung/Kconfig
> +++ b/drivers/clk/samsung/Kconfig
> @@ -13,6 +13,7 @@ config COMMON_CLK_SAMSUNG
> select EXYNOS_5420_COMMON_CLK if ARM && SOC_EXYNOS5420
> select EXYNOS_ARM64_COMMON_CLK if ARM64 && ARCH_EXYNOS
> select TESLA_FSD_COMMON_CLK if ARM64 && ARCH_TESLA_FSD
> + select GOOGLE_GS101_COMMON_CLK if ARM64 && ARCH_GOOGLE_TENSOR
Let's put it before Tesla. There's not much order, but maybe one day we
will fix it.
>
> config S3C64XX_COMMON_CLK
> bool "Samsung S3C64xx clock controller support" if COMPILE_TEST
> @@ -102,3 +103,11 @@ config TESLA_FSD_COMMON_CLK
> help
> Support for the clock controller present on the Tesla FSD SoC.
> Choose Y here only if you build for this SoC.
> +
> +config GOOGLE_GS101_COMMON_CLK
Let's put it before Tesla.
> + bool "Google gs101 clock controller support" if COMPILE_TEST
> + depends on COMMON_CLK_SAMSUNG
> + depends on EXYNOS_ARM64_COMMON_CLK
> + help
> + Support for the clock controller present on the Google gs101 SoC.
> + Choose Y here only if you build for this SoC.
> \ No newline at end of file
Missing newline
> diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
> index ebbeacabe88f..1e69b8e14324 100644
> --- a/drivers/clk/samsung/Makefile
> +++ b/drivers/clk/samsung/Makefile
> @@ -24,3 +24,4 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov9.o
> obj-$(CONFIG_S3C64XX_COMMON_CLK) += clk-s3c64xx.o
> obj-$(CONFIG_S5PV210_COMMON_CLK) += clk-s5pv210.o clk-s5pv210-audss.o
> obj-$(CONFIG_TESLA_FSD_COMMON_CLK) += clk-fsd.o
> +obj-$(CONFIG_GOOGLE_GS101_COMMON_CLK) += clk-gs101.o
Before S3C64xx
> diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
> new file mode 100644
> index 000000000000..4c58fcc899be
> --- /dev/null
> +++ b/drivers/clk/samsung/clk-gs101.c
> @@ -0,0 +1,1558 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (C) 2023 Linaro Ltd.
> + * Author: Peter Griffin <peter.griffin@linaro.org>
> + *
> + * Common Clock Framework support for GS101.
> + */
> +
...
> + /* PERI1 */
> + GATE(CLK_GOUT_PERIC1_BUS, "gout_cmu_peric1_bus", "mout_cmu_peric1_bus",
> + CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS, 21, 0, 0),
> + GATE(CLK_GOUT_PERIC1_IP, "gout_cmu_peric1_ip", "mout_cmu_peric1_ip",
> + CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP, 21, 0, 0),
> +
> + /* TPU */
> + GATE(CLK_GOUT_TPU_TPU, "gout_cmu_tpu_tpu", "mout_cmu_tpu_tpu",
> + CLK_CON_GAT_GATE_CLKCMU_TPU_TPU, 21, 0, 0),
> + GATE(CLK_GOUT_TPU_TPUCTL, "gout_cmu_tpu_tpuctl", "mout_cmu_tpu_tpuctl",
> + CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL, 21, 0, 0),
> + GATE(CLK_GOUT_TPU_BUS, "gout_cmu_tpu_bus", "mout_cmu_tpu_bus",
> + CLK_CON_GAT_GATE_CLKCMU_TPU_BUS, 21, 0, 0),
> + GATE(CLK_GOUT_TPU_UART, "gout_cmu_tpu_uart", "mout_cmu_tpu_uart",
> + CLK_CON_GAT_GATE_CLKCMU_TPU_UART, 21, 0, 0),
> +
> + /* BO */
> + GATE(CLK_GOUT_BO_BUS, "gout_cmu_bo_bus", "mout_cmu_bo_bus",
> + CLK_CON_GAT_GATE_CLKCMU_BO_BUS, 21, 0, 0),
> +
stray blank line
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 13/21] clk: samsung: clk-gs101: Add cmu_top registers, plls, mux and gates
@ 2023-10-05 17:45 ` Krzysztof Kozlowski
0 siblings, 0 replies; 150+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-05 17:45 UTC (permalink / raw)
To: Peter Griffin, robh+dt, krzysztof.kozlowski+dt, mturquette,
conor+dt, sboyd, tomasz.figa, s.nawrocki, linus.walleij, wim,
linux, catalin.marinas, will, arnd, olof, cw00.choi
Cc: tudor.ambarus, andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog
On 05/10/2023 17:56, Peter Griffin wrote:
> CMU_TOP is the top level clock management unit which contains PLLs, muxes
> and gates that feed the other clock management units.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> drivers/clk/samsung/Kconfig | 9 +
> drivers/clk/samsung/Makefile | 1 +
> drivers/clk/samsung/clk-gs101.c | 1558 +++++++++++++++++++++++++++++++
> 3 files changed, 1568 insertions(+)
> create mode 100644 drivers/clk/samsung/clk-gs101.c
>
> diff --git a/drivers/clk/samsung/Kconfig b/drivers/clk/samsung/Kconfig
> index 76a494e95027..4c8f173c4dec 100644
> --- a/drivers/clk/samsung/Kconfig
> +++ b/drivers/clk/samsung/Kconfig
> @@ -13,6 +13,7 @@ config COMMON_CLK_SAMSUNG
> select EXYNOS_5420_COMMON_CLK if ARM && SOC_EXYNOS5420
> select EXYNOS_ARM64_COMMON_CLK if ARM64 && ARCH_EXYNOS
> select TESLA_FSD_COMMON_CLK if ARM64 && ARCH_TESLA_FSD
> + select GOOGLE_GS101_COMMON_CLK if ARM64 && ARCH_GOOGLE_TENSOR
Let's put it before Tesla. There's not much order, but maybe one day we
will fix it.
>
> config S3C64XX_COMMON_CLK
> bool "Samsung S3C64xx clock controller support" if COMPILE_TEST
> @@ -102,3 +103,11 @@ config TESLA_FSD_COMMON_CLK
> help
> Support for the clock controller present on the Tesla FSD SoC.
> Choose Y here only if you build for this SoC.
> +
> +config GOOGLE_GS101_COMMON_CLK
Let's put it before Tesla.
> + bool "Google gs101 clock controller support" if COMPILE_TEST
> + depends on COMMON_CLK_SAMSUNG
> + depends on EXYNOS_ARM64_COMMON_CLK
> + help
> + Support for the clock controller present on the Google gs101 SoC.
> + Choose Y here only if you build for this SoC.
> \ No newline at end of file
Missing newline
> diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
> index ebbeacabe88f..1e69b8e14324 100644
> --- a/drivers/clk/samsung/Makefile
> +++ b/drivers/clk/samsung/Makefile
> @@ -24,3 +24,4 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov9.o
> obj-$(CONFIG_S3C64XX_COMMON_CLK) += clk-s3c64xx.o
> obj-$(CONFIG_S5PV210_COMMON_CLK) += clk-s5pv210.o clk-s5pv210-audss.o
> obj-$(CONFIG_TESLA_FSD_COMMON_CLK) += clk-fsd.o
> +obj-$(CONFIG_GOOGLE_GS101_COMMON_CLK) += clk-gs101.o
Before S3C64xx
> diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
> new file mode 100644
> index 000000000000..4c58fcc899be
> --- /dev/null
> +++ b/drivers/clk/samsung/clk-gs101.c
> @@ -0,0 +1,1558 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (C) 2023 Linaro Ltd.
> + * Author: Peter Griffin <peter.griffin@linaro.org>
> + *
> + * Common Clock Framework support for GS101.
> + */
> +
...
> + /* PERI1 */
> + GATE(CLK_GOUT_PERIC1_BUS, "gout_cmu_peric1_bus", "mout_cmu_peric1_bus",
> + CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS, 21, 0, 0),
> + GATE(CLK_GOUT_PERIC1_IP, "gout_cmu_peric1_ip", "mout_cmu_peric1_ip",
> + CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP, 21, 0, 0),
> +
> + /* TPU */
> + GATE(CLK_GOUT_TPU_TPU, "gout_cmu_tpu_tpu", "mout_cmu_tpu_tpu",
> + CLK_CON_GAT_GATE_CLKCMU_TPU_TPU, 21, 0, 0),
> + GATE(CLK_GOUT_TPU_TPUCTL, "gout_cmu_tpu_tpuctl", "mout_cmu_tpu_tpuctl",
> + CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL, 21, 0, 0),
> + GATE(CLK_GOUT_TPU_BUS, "gout_cmu_tpu_bus", "mout_cmu_tpu_bus",
> + CLK_CON_GAT_GATE_CLKCMU_TPU_BUS, 21, 0, 0),
> + GATE(CLK_GOUT_TPU_UART, "gout_cmu_tpu_uart", "mout_cmu_tpu_uart",
> + CLK_CON_GAT_GATE_CLKCMU_TPU_UART, 21, 0, 0),
> +
> + /* BO */
> + GATE(CLK_GOUT_BO_BUS, "gout_cmu_bo_bus", "mout_cmu_bo_bus",
> + CLK_CON_GAT_GATE_CLKCMU_BO_BUS, 21, 0, 0),
> +
stray blank line
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 13/21] clk: samsung: clk-gs101: Add cmu_top registers, plls, mux and gates
2023-10-05 15:56 ` Peter Griffin
@ 2023-10-06 4:16 ` kernel test robot
-1 siblings, 0 replies; 150+ messages in thread
From: kernel test robot @ 2023-10-06 4:16 UTC (permalink / raw)
To: Peter Griffin, robh+dt, krzysztof.kozlowski+dt, mturquette,
conor+dt, sboyd, tomasz.figa, s.nawrocki, linus.walleij, wim,
linux, catalin.marinas, will, arnd, olof, cw00.choi
Cc: oe-kbuild-all, peter.griffin, tudor.ambarus, andre.draszik,
semen.protsenko, soc, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-clk, linux-gpio, linux-watchdog
Hi Peter,
kernel test robot noticed the following build warnings:
[auto build test WARNING on krzk/for-next]
[also build test WARNING on robh/for-next linus/master v6.6-rc4 next-20231005]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Peter-Griffin/dt-bindings-interrupt-controller-Add-gs101-interrupt-controller/20231005-235922
base: https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git for-next
patch link: https://lore.kernel.org/r/20231005155618.700312-14-peter.griffin%40linaro.org
patch subject: [PATCH 13/21] clk: samsung: clk-gs101: Add cmu_top registers, plls, mux and gates
config: nios2-allyesconfig (https://download.01.org/0day-ci/archive/20231006/202310061231.Awh3otY7-lkp@intel.com/config)
compiler: nios2-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20231006/202310061231.Awh3otY7-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202310061231.Awh3otY7-lkp@intel.com/
All warnings (new ones prefixed by >>):
In file included from drivers/clk/samsung/clk-gs101.c:17:
>> drivers/clk/samsung/clk-gs101.c:935:7: warning: 'mout_cmu_g2d_p' defined but not used [-Wunused-const-variable=]
935 | PNAME(mout_cmu_g2d_p) = { "dout_shared0_div3", "fout_shared3_pll",
| ^~~~~~~~~~~~~~
drivers/clk/samsung/clk.h:226:44: note: in definition of macro 'PNAME'
226 | #define PNAME(x) static const char * const x[] __initconst
| ^
>> drivers/clk/samsung/clk-gs101.c:888:7: warning: 'mout_cmu_boost_p' defined but not used [-Wunused-const-variable=]
888 | PNAME(mout_cmu_boost_p) = { "dout_shared0_div4", "dout_shared1_div4",
| ^~~~~~~~~~~~~~~~
drivers/clk/samsung/clk.h:226:44: note: in definition of macro 'PNAME'
226 | #define PNAME(x) static const char * const x[] __initconst
| ^
>> drivers/clk/samsung/clk-gs101.c:809:7: warning: 'mout_cmu_pdp_vra_p' defined but not used [-Wunused-const-variable=]
809 | PNAME(mout_cmu_pdp_vra_p) = { "fout_shared2_pll", "dout_shared0_div3",
| ^~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk.h:226:44: note: in definition of macro 'PNAME'
226 | #define PNAME(x) static const char * const x[] __initconst
| ^
vim +/mout_cmu_g2d_p +935 drivers/clk/samsung/clk-gs101.c
790
791 PNAME(mout_cmu_hsi2_ufs_embd_p) = { "oscclk", "dout_shared0_div4",
792 "dout_shared2_div2", "fout_spare_pll" };
793
794 PNAME(mout_cmu_hsi2_mmc_card_p) = { "fout_shared2_pll", "fout_shared3_pll",
795 "dout_shared0_div4", "fout_spare_pll" };
796
797 /* List of parent clocks for Muxes in CMU_TOP: for CMU_CSIS */
798 PNAME(mout_cmu_csis_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
799 "dout_shared1_div3", "dout_shared0_div4",
800 "dout_shared1_div4", "dout_shared2_div2",
801 "fout_spare_pll" };
802
803 /* List of parent clocks for Muxes in CMU_TOP: for CMU_PDP */
804 PNAME(mout_cmu_pdp_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
805 "dout_shared1_div3", "dout_shared0_div4",
806 "dout_shared1_div4", "dout_shared2_div2",
807 "fout_spare_pll" };
808
> 809 PNAME(mout_cmu_pdp_vra_p) = { "fout_shared2_pll", "dout_shared0_div3",
810 "fout_shared3_pll", "dout_shared1_div3",
811 "dout_shared0_div4", "dout_shared1_div4",
812 "fout_spare_pll" };
813
814 /* List of parent clocks for Muxes in CMU_TOP: for CMU_IPP */
815 PNAME(mout_cmu_ipp_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
816 "dout_shared1_div3", "dout_shared0_div4",
817 "dout_shared1_div4", "dout_shared2_div2",
818 "fout_spare_pll" };
819
820 /* List of parent clocks for Muxes in CMU_TOP: for CMU_G3AA */
821 PNAME(mout_cmu_g3aa_p) = { "dout_shared0_div3", "fout_shared3_pll",
822 "dout_shared1_div3", "dout_shared0_div4",
823 "dout_shared1_div4", "dout_shared2_div2",
824 "fout_spare_pll" };
825
826 /* List of parent clocks for Muxes in CMU_TOP: for CMU_ITP */
827 PNAME(mout_cmu_itp_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
828 "dout_shared1_div3", "dout_shared0_div4",
829 "dout_shared1_div4", "dout_shared2_div2",
830 "fout_spare_pll" };
831
832 /* List of parent clocks for Muxes in CMU_TOP: for CMU_DNS */
833 PNAME(mout_cmu_dns_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
834 "dout_shared1_div3", "dout_shared0_div4",
835 "dout_shared1_div4", "dout_shared2_div2",
836 "fout_spare_pll" };
837
838 /* List of parent clocks for Muxes in CMU_TOP: for CMU_TNR */
839 PNAME(mout_cmu_tnr_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
840 "dout_shared1_div3", "dout_shared0_div4",
841 "dout_shared1_div4", "dout_shared2_div2",
842 "fout_spare_pll" };
843
844 /* List of parent clocks for Muxes in CMU_TOP: for CMU_MCSC */
845 PNAME(mout_cmu_mcsc_itsc_p) = { "dout_shared0_div3", "fout_shared3_pll",
846 "dout_shared1_div3", "dout_shared0_div4",
847 "dout_shared1_div4", "dout_shared2_div2",
848 "fout_spare_pll" };
849
850 PNAME(mout_cmu_mcsc_mcsc_p) = { "dout_shared0_div3", "fout_shared3_pll",
851 "dout_shared1_div3", "dout_shared0_div4",
852 "dout_shared1_div4", "dout_shared2_div2",
853 "fout_spare_pll" };
854
855 /* List of parent clocks for Muxes in CMU_TOP: for CMU_GDC */
856 PNAME(mout_cmu_gdc_scsc_p) = { "dout_shared0_div3", "fout_shared3_pll",
857 "dout_shared1_div3", "dout_shared0_div4",
858 "dout_shared1_div4", "dout_shared2_div2",
859 "fout_spare_pll" };
860
861 PNAME(mout_cmu_gdc_gdc0_p) = { "dout_shared0_div3", "fout_shared3_pll",
862 "dout_shared1_div3", "dout_shared0_div4",
863 "dout_shared1_div4", "dout_shared2_div2",
864 "fout_spare_pll" };
865
866 PNAME(mout_cmu_gdc_gdc1_p) = { "dout_shared0_div3", "fout_shared3_pll",
867 "dout_shared1_div3", "dout_shared0_div4",
868 "dout_shared1_div4", "dout_shared2_div2",
869 "fout_spare_pll" };
870
871 /* List of parent clocks for Muxes in CMU_TOP: for CMU_MFC */
872 PNAME(mout_cmu_mfc_mfc_p) = { "dout_shared0_div3", "fout_shared3_pll",
873 "dout_shared1_div3", "dout_shared0_div4",
874 "dout_shared1_div4", "dout_shared2_div2",
875 "fout_spare_pll" };
876
877 /* List of parent clocks for Muxes in CMU_TOP: for DDRPHY0/1/2/3 */
878
879 PNAME(mout_cmu_mif_switch_p) = { "fout_shared0_pll", "fout_shared1_pll",
880 "dout_shared0_div2", "dout_shared1_div2",
881 "fout_shared2_pll", "dout_shared0_div3",
882 "fout_shared3_pll", "fout_spare_pll" };
883
884 /* List of parent clocks for Muxes in CMU_TOP: for CMU_MIF0/1/2/3 */
885 PNAME(mout_cmu_mif_busp_p) = { "dout_shared0_div4", "dout_shared1_div4",
886 "dout_shared0_div5", "fout_spare_pll" };
887
> 888 PNAME(mout_cmu_boost_p) = { "dout_shared0_div4", "dout_shared1_div4",
889 "dout_shared2_div2", "dout_shared3_div2" };
890
891 /* List of parent clocks for Muxes in CMU_TOP: for CMU_MISC */
892 PNAME(mout_cmu_misc_bus_p) = { "dout_shared0_div4", "dout_shared2_div2",
893 "dout_shared3_div2", "fout_spare_pll" };
894 PNAME(mout_cmu_misc_sss_p) = { "dout_shared0_div4", "dout_shared2_div2",
895 "dout_shared3_div2", "fout_spare_pll" };
896
897 /* List of parent clocks for Muxes in CMU_TOP: for CMU_PERIC0 */
898 PNAME(mout_cmu_peric0_bus_p) = { "dout_shared0_div4", "dout_shared2_div2",
899 "dout_shared3_div2", "fout_spare_pll" };
900 PNAME(mout_cmu_peric0_ip_p) = { "dout_shared0_div4", "dout_shared2_div2",
901 "dout_shared3_div2", "fout_spare_pll" };
902
903 /* List of parent clocks for Muxes in CMU_TOP: for CMU_PERIC1 */
904 PNAME(mout_cmu_peric1_bus_p) = { "dout_shared0_div4", "dout_shared2_div2",
905 "dout_shared3_div2", "fout_spare_pll" };
906 PNAME(mout_cmu_peric1_ip_p) = { "dout_shared0_div4", "dout_shared2_div2",
907 "dout_shared3_div2", "fout_spare_pll" };
908
909 /* List of parent clocks for Muxes in CMU_TOP: for CMU_TPU */
910 PNAME(mout_cmu_tpu_tpu_p) = { "dout_shared0_div2", "dout_shared1_div2",
911 "fout_shared2_pll", "fout_shared3_pll",
912 "dout_shared0_div3", "dout_shared1_div3",
913 "dout_shared0_div4", "fout_spare_pll" };
914
915 PNAME(mout_cmu_tpu_tpuctl_p) = { "dout_shared0_div2", "dout_shared1_div2",
916 "fout_shared2_pll", "fout_shared3_pll",
917 "dout_shared0_div3", "dout_shared1_div3",
918 "dout_shared0_div4", "fout_spare_pll" };
919
920 PNAME(mout_cmu_tpu_bus_p) = { "dout_shared0_div2", "dout_shared1_div2",
921 "fout_shared2_pll", "fout_shared3_pll",
922 "dout_shared0_div3", "dout_shared1_div3",
923 "dout_shared0_div4", "fout_spare_pll" };
924
925 PNAME(mout_cmu_tpu_uart_p) = { "dout_shared0_div4", "dout_shared2_div2",
926 "dout_shared3_div2", "fout_spare_pll" };
927
928 /* List of parent clocks for Muxes in CMU_TOP: for CMU_BO */
929 PNAME(mout_cmu_bo_bus_p) = { "fout_shared2_pll", "dout_shared0_div3",
930 "fout_shared3_pll", "dout_shared1_div3",
931 "dout_shared0_div4", "dout_shared1_div4",
932 "fout_spare_pll" };
933
934 /* List of parent clocks for Muxes in CMU_TOP: for CMU_G2D */
> 935 PNAME(mout_cmu_g2d_p) = { "dout_shared0_div3", "fout_shared3_pll",
936 "dout_shared1_div3", "dout_shared0_div4",
937 "dout_shared1_div4", "dout_shared2_div2",
938 "fout_spare_pll" };
939
--
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https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 150+ messages in thread* Re: [PATCH 13/21] clk: samsung: clk-gs101: Add cmu_top registers, plls, mux and gates
@ 2023-10-06 4:16 ` kernel test robot
0 siblings, 0 replies; 150+ messages in thread
From: kernel test robot @ 2023-10-06 4:16 UTC (permalink / raw)
To: Peter Griffin, robh+dt, krzysztof.kozlowski+dt, mturquette,
conor+dt, sboyd, tomasz.figa, s.nawrocki, linus.walleij, wim,
linux, catalin.marinas, will, arnd, olof, cw00.choi
Cc: oe-kbuild-all, peter.griffin, tudor.ambarus, andre.draszik,
semen.protsenko, soc, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-clk, linux-gpio, linux-watchdog
Hi Peter,
kernel test robot noticed the following build warnings:
[auto build test WARNING on krzk/for-next]
[also build test WARNING on robh/for-next linus/master v6.6-rc4 next-20231005]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Peter-Griffin/dt-bindings-interrupt-controller-Add-gs101-interrupt-controller/20231005-235922
base: https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git for-next
patch link: https://lore.kernel.org/r/20231005155618.700312-14-peter.griffin%40linaro.org
patch subject: [PATCH 13/21] clk: samsung: clk-gs101: Add cmu_top registers, plls, mux and gates
config: nios2-allyesconfig (https://download.01.org/0day-ci/archive/20231006/202310061231.Awh3otY7-lkp@intel.com/config)
compiler: nios2-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20231006/202310061231.Awh3otY7-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202310061231.Awh3otY7-lkp@intel.com/
All warnings (new ones prefixed by >>):
In file included from drivers/clk/samsung/clk-gs101.c:17:
>> drivers/clk/samsung/clk-gs101.c:935:7: warning: 'mout_cmu_g2d_p' defined but not used [-Wunused-const-variable=]
935 | PNAME(mout_cmu_g2d_p) = { "dout_shared0_div3", "fout_shared3_pll",
| ^~~~~~~~~~~~~~
drivers/clk/samsung/clk.h:226:44: note: in definition of macro 'PNAME'
226 | #define PNAME(x) static const char * const x[] __initconst
| ^
>> drivers/clk/samsung/clk-gs101.c:888:7: warning: 'mout_cmu_boost_p' defined but not used [-Wunused-const-variable=]
888 | PNAME(mout_cmu_boost_p) = { "dout_shared0_div4", "dout_shared1_div4",
| ^~~~~~~~~~~~~~~~
drivers/clk/samsung/clk.h:226:44: note: in definition of macro 'PNAME'
226 | #define PNAME(x) static const char * const x[] __initconst
| ^
>> drivers/clk/samsung/clk-gs101.c:809:7: warning: 'mout_cmu_pdp_vra_p' defined but not used [-Wunused-const-variable=]
809 | PNAME(mout_cmu_pdp_vra_p) = { "fout_shared2_pll", "dout_shared0_div3",
| ^~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk.h:226:44: note: in definition of macro 'PNAME'
226 | #define PNAME(x) static const char * const x[] __initconst
| ^
vim +/mout_cmu_g2d_p +935 drivers/clk/samsung/clk-gs101.c
790
791 PNAME(mout_cmu_hsi2_ufs_embd_p) = { "oscclk", "dout_shared0_div4",
792 "dout_shared2_div2", "fout_spare_pll" };
793
794 PNAME(mout_cmu_hsi2_mmc_card_p) = { "fout_shared2_pll", "fout_shared3_pll",
795 "dout_shared0_div4", "fout_spare_pll" };
796
797 /* List of parent clocks for Muxes in CMU_TOP: for CMU_CSIS */
798 PNAME(mout_cmu_csis_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
799 "dout_shared1_div3", "dout_shared0_div4",
800 "dout_shared1_div4", "dout_shared2_div2",
801 "fout_spare_pll" };
802
803 /* List of parent clocks for Muxes in CMU_TOP: for CMU_PDP */
804 PNAME(mout_cmu_pdp_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
805 "dout_shared1_div3", "dout_shared0_div4",
806 "dout_shared1_div4", "dout_shared2_div2",
807 "fout_spare_pll" };
808
> 809 PNAME(mout_cmu_pdp_vra_p) = { "fout_shared2_pll", "dout_shared0_div3",
810 "fout_shared3_pll", "dout_shared1_div3",
811 "dout_shared0_div4", "dout_shared1_div4",
812 "fout_spare_pll" };
813
814 /* List of parent clocks for Muxes in CMU_TOP: for CMU_IPP */
815 PNAME(mout_cmu_ipp_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
816 "dout_shared1_div3", "dout_shared0_div4",
817 "dout_shared1_div4", "dout_shared2_div2",
818 "fout_spare_pll" };
819
820 /* List of parent clocks for Muxes in CMU_TOP: for CMU_G3AA */
821 PNAME(mout_cmu_g3aa_p) = { "dout_shared0_div3", "fout_shared3_pll",
822 "dout_shared1_div3", "dout_shared0_div4",
823 "dout_shared1_div4", "dout_shared2_div2",
824 "fout_spare_pll" };
825
826 /* List of parent clocks for Muxes in CMU_TOP: for CMU_ITP */
827 PNAME(mout_cmu_itp_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
828 "dout_shared1_div3", "dout_shared0_div4",
829 "dout_shared1_div4", "dout_shared2_div2",
830 "fout_spare_pll" };
831
832 /* List of parent clocks for Muxes in CMU_TOP: for CMU_DNS */
833 PNAME(mout_cmu_dns_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
834 "dout_shared1_div3", "dout_shared0_div4",
835 "dout_shared1_div4", "dout_shared2_div2",
836 "fout_spare_pll" };
837
838 /* List of parent clocks for Muxes in CMU_TOP: for CMU_TNR */
839 PNAME(mout_cmu_tnr_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
840 "dout_shared1_div3", "dout_shared0_div4",
841 "dout_shared1_div4", "dout_shared2_div2",
842 "fout_spare_pll" };
843
844 /* List of parent clocks for Muxes in CMU_TOP: for CMU_MCSC */
845 PNAME(mout_cmu_mcsc_itsc_p) = { "dout_shared0_div3", "fout_shared3_pll",
846 "dout_shared1_div3", "dout_shared0_div4",
847 "dout_shared1_div4", "dout_shared2_div2",
848 "fout_spare_pll" };
849
850 PNAME(mout_cmu_mcsc_mcsc_p) = { "dout_shared0_div3", "fout_shared3_pll",
851 "dout_shared1_div3", "dout_shared0_div4",
852 "dout_shared1_div4", "dout_shared2_div2",
853 "fout_spare_pll" };
854
855 /* List of parent clocks for Muxes in CMU_TOP: for CMU_GDC */
856 PNAME(mout_cmu_gdc_scsc_p) = { "dout_shared0_div3", "fout_shared3_pll",
857 "dout_shared1_div3", "dout_shared0_div4",
858 "dout_shared1_div4", "dout_shared2_div2",
859 "fout_spare_pll" };
860
861 PNAME(mout_cmu_gdc_gdc0_p) = { "dout_shared0_div3", "fout_shared3_pll",
862 "dout_shared1_div3", "dout_shared0_div4",
863 "dout_shared1_div4", "dout_shared2_div2",
864 "fout_spare_pll" };
865
866 PNAME(mout_cmu_gdc_gdc1_p) = { "dout_shared0_div3", "fout_shared3_pll",
867 "dout_shared1_div3", "dout_shared0_div4",
868 "dout_shared1_div4", "dout_shared2_div2",
869 "fout_spare_pll" };
870
871 /* List of parent clocks for Muxes in CMU_TOP: for CMU_MFC */
872 PNAME(mout_cmu_mfc_mfc_p) = { "dout_shared0_div3", "fout_shared3_pll",
873 "dout_shared1_div3", "dout_shared0_div4",
874 "dout_shared1_div4", "dout_shared2_div2",
875 "fout_spare_pll" };
876
877 /* List of parent clocks for Muxes in CMU_TOP: for DDRPHY0/1/2/3 */
878
879 PNAME(mout_cmu_mif_switch_p) = { "fout_shared0_pll", "fout_shared1_pll",
880 "dout_shared0_div2", "dout_shared1_div2",
881 "fout_shared2_pll", "dout_shared0_div3",
882 "fout_shared3_pll", "fout_spare_pll" };
883
884 /* List of parent clocks for Muxes in CMU_TOP: for CMU_MIF0/1/2/3 */
885 PNAME(mout_cmu_mif_busp_p) = { "dout_shared0_div4", "dout_shared1_div4",
886 "dout_shared0_div5", "fout_spare_pll" };
887
> 888 PNAME(mout_cmu_boost_p) = { "dout_shared0_div4", "dout_shared1_div4",
889 "dout_shared2_div2", "dout_shared3_div2" };
890
891 /* List of parent clocks for Muxes in CMU_TOP: for CMU_MISC */
892 PNAME(mout_cmu_misc_bus_p) = { "dout_shared0_div4", "dout_shared2_div2",
893 "dout_shared3_div2", "fout_spare_pll" };
894 PNAME(mout_cmu_misc_sss_p) = { "dout_shared0_div4", "dout_shared2_div2",
895 "dout_shared3_div2", "fout_spare_pll" };
896
897 /* List of parent clocks for Muxes in CMU_TOP: for CMU_PERIC0 */
898 PNAME(mout_cmu_peric0_bus_p) = { "dout_shared0_div4", "dout_shared2_div2",
899 "dout_shared3_div2", "fout_spare_pll" };
900 PNAME(mout_cmu_peric0_ip_p) = { "dout_shared0_div4", "dout_shared2_div2",
901 "dout_shared3_div2", "fout_spare_pll" };
902
903 /* List of parent clocks for Muxes in CMU_TOP: for CMU_PERIC1 */
904 PNAME(mout_cmu_peric1_bus_p) = { "dout_shared0_div4", "dout_shared2_div2",
905 "dout_shared3_div2", "fout_spare_pll" };
906 PNAME(mout_cmu_peric1_ip_p) = { "dout_shared0_div4", "dout_shared2_div2",
907 "dout_shared3_div2", "fout_spare_pll" };
908
909 /* List of parent clocks for Muxes in CMU_TOP: for CMU_TPU */
910 PNAME(mout_cmu_tpu_tpu_p) = { "dout_shared0_div2", "dout_shared1_div2",
911 "fout_shared2_pll", "fout_shared3_pll",
912 "dout_shared0_div3", "dout_shared1_div3",
913 "dout_shared0_div4", "fout_spare_pll" };
914
915 PNAME(mout_cmu_tpu_tpuctl_p) = { "dout_shared0_div2", "dout_shared1_div2",
916 "fout_shared2_pll", "fout_shared3_pll",
917 "dout_shared0_div3", "dout_shared1_div3",
918 "dout_shared0_div4", "fout_spare_pll" };
919
920 PNAME(mout_cmu_tpu_bus_p) = { "dout_shared0_div2", "dout_shared1_div2",
921 "fout_shared2_pll", "fout_shared3_pll",
922 "dout_shared0_div3", "dout_shared1_div3",
923 "dout_shared0_div4", "fout_spare_pll" };
924
925 PNAME(mout_cmu_tpu_uart_p) = { "dout_shared0_div4", "dout_shared2_div2",
926 "dout_shared3_div2", "fout_spare_pll" };
927
928 /* List of parent clocks for Muxes in CMU_TOP: for CMU_BO */
929 PNAME(mout_cmu_bo_bus_p) = { "fout_shared2_pll", "dout_shared0_div3",
930 "fout_shared3_pll", "dout_shared1_div3",
931 "dout_shared0_div4", "dout_shared1_div4",
932 "fout_spare_pll" };
933
934 /* List of parent clocks for Muxes in CMU_TOP: for CMU_G2D */
> 935 PNAME(mout_cmu_g2d_p) = { "dout_shared0_div3", "fout_shared3_pll",
936 "dout_shared1_div3", "dout_shared0_div4",
937 "dout_shared1_div4", "dout_shared2_div2",
938 "fout_spare_pll" };
939
--
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https://github.com/intel/lkp-tests/wiki
_______________________________________________
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^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 13/21] clk: samsung: clk-gs101: Add cmu_top registers, plls, mux and gates
2023-10-05 15:56 ` Peter Griffin
@ 2023-10-14 6:37 ` kernel test robot
-1 siblings, 0 replies; 150+ messages in thread
From: kernel test robot @ 2023-10-14 6:37 UTC (permalink / raw)
To: Peter Griffin, robh+dt, krzysztof.kozlowski+dt, mturquette,
conor+dt, sboyd, tomasz.figa, s.nawrocki, linus.walleij, wim,
linux, catalin.marinas, will, arnd, olof, cw00.choi
Cc: llvm, oe-kbuild-all, peter.griffin, tudor.ambarus, andre.draszik,
semen.protsenko, soc, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-clk, linux-gpio, linux-watchdog
Hi Peter,
kernel test robot noticed the following build warnings:
[auto build test WARNING on krzk/for-next]
[also build test WARNING on robh/for-next linus/master pinctrl-samsung/for-next v6.6-rc5 next-20231013]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Peter-Griffin/dt-bindings-interrupt-controller-Add-gs101-interrupt-controller/20231005-235922
base: https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git for-next
patch link: https://lore.kernel.org/r/20231005155618.700312-14-peter.griffin%40linaro.org
patch subject: [PATCH 13/21] clk: samsung: clk-gs101: Add cmu_top registers, plls, mux and gates
config: arm64-allyesconfig (https://download.01.org/0day-ci/archive/20231014/202310141437.xBrLtPIH-lkp@intel.com/config)
compiler: clang version 17.0.0 (https://github.com/llvm/llvm-project.git 4a5ac14ee968ff0ad5d2cc1ffa0299048db4c88a)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20231014/202310141437.xBrLtPIH-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202310141437.xBrLtPIH-lkp@intel.com/
All warnings (new ones prefixed by >>):
>> drivers/clk/samsung/clk-gs101.c:809:7: warning: unused variable 'mout_cmu_pdp_vra_p' [-Wunused-const-variable]
809 | PNAME(mout_cmu_pdp_vra_p) = { "fout_shared2_pll", "dout_shared0_div3",
| ^
>> drivers/clk/samsung/clk-gs101.c:888:7: warning: unused variable 'mout_cmu_boost_p' [-Wunused-const-variable]
888 | PNAME(mout_cmu_boost_p) = { "dout_shared0_div4", "dout_shared1_div4",
| ^
>> drivers/clk/samsung/clk-gs101.c:935:7: warning: unused variable 'mout_cmu_g2d_p' [-Wunused-const-variable]
935 | PNAME(mout_cmu_g2d_p) = { "dout_shared0_div3", "fout_shared3_pll",
| ^
3 warnings generated.
vim +/mout_cmu_pdp_vra_p +809 drivers/clk/samsung/clk-gs101.c
790
791 PNAME(mout_cmu_hsi2_ufs_embd_p) = { "oscclk", "dout_shared0_div4",
792 "dout_shared2_div2", "fout_spare_pll" };
793
794 PNAME(mout_cmu_hsi2_mmc_card_p) = { "fout_shared2_pll", "fout_shared3_pll",
795 "dout_shared0_div4", "fout_spare_pll" };
796
797 /* List of parent clocks for Muxes in CMU_TOP: for CMU_CSIS */
798 PNAME(mout_cmu_csis_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
799 "dout_shared1_div3", "dout_shared0_div4",
800 "dout_shared1_div4", "dout_shared2_div2",
801 "fout_spare_pll" };
802
803 /* List of parent clocks for Muxes in CMU_TOP: for CMU_PDP */
804 PNAME(mout_cmu_pdp_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
805 "dout_shared1_div3", "dout_shared0_div4",
806 "dout_shared1_div4", "dout_shared2_div2",
807 "fout_spare_pll" };
808
> 809 PNAME(mout_cmu_pdp_vra_p) = { "fout_shared2_pll", "dout_shared0_div3",
810 "fout_shared3_pll", "dout_shared1_div3",
811 "dout_shared0_div4", "dout_shared1_div4",
812 "fout_spare_pll" };
813
814 /* List of parent clocks for Muxes in CMU_TOP: for CMU_IPP */
815 PNAME(mout_cmu_ipp_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
816 "dout_shared1_div3", "dout_shared0_div4",
817 "dout_shared1_div4", "dout_shared2_div2",
818 "fout_spare_pll" };
819
820 /* List of parent clocks for Muxes in CMU_TOP: for CMU_G3AA */
821 PNAME(mout_cmu_g3aa_p) = { "dout_shared0_div3", "fout_shared3_pll",
822 "dout_shared1_div3", "dout_shared0_div4",
823 "dout_shared1_div4", "dout_shared2_div2",
824 "fout_spare_pll" };
825
826 /* List of parent clocks for Muxes in CMU_TOP: for CMU_ITP */
827 PNAME(mout_cmu_itp_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
828 "dout_shared1_div3", "dout_shared0_div4",
829 "dout_shared1_div4", "dout_shared2_div2",
830 "fout_spare_pll" };
831
832 /* List of parent clocks for Muxes in CMU_TOP: for CMU_DNS */
833 PNAME(mout_cmu_dns_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
834 "dout_shared1_div3", "dout_shared0_div4",
835 "dout_shared1_div4", "dout_shared2_div2",
836 "fout_spare_pll" };
837
838 /* List of parent clocks for Muxes in CMU_TOP: for CMU_TNR */
839 PNAME(mout_cmu_tnr_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
840 "dout_shared1_div3", "dout_shared0_div4",
841 "dout_shared1_div4", "dout_shared2_div2",
842 "fout_spare_pll" };
843
844 /* List of parent clocks for Muxes in CMU_TOP: for CMU_MCSC */
845 PNAME(mout_cmu_mcsc_itsc_p) = { "dout_shared0_div3", "fout_shared3_pll",
846 "dout_shared1_div3", "dout_shared0_div4",
847 "dout_shared1_div4", "dout_shared2_div2",
848 "fout_spare_pll" };
849
850 PNAME(mout_cmu_mcsc_mcsc_p) = { "dout_shared0_div3", "fout_shared3_pll",
851 "dout_shared1_div3", "dout_shared0_div4",
852 "dout_shared1_div4", "dout_shared2_div2",
853 "fout_spare_pll" };
854
855 /* List of parent clocks for Muxes in CMU_TOP: for CMU_GDC */
856 PNAME(mout_cmu_gdc_scsc_p) = { "dout_shared0_div3", "fout_shared3_pll",
857 "dout_shared1_div3", "dout_shared0_div4",
858 "dout_shared1_div4", "dout_shared2_div2",
859 "fout_spare_pll" };
860
861 PNAME(mout_cmu_gdc_gdc0_p) = { "dout_shared0_div3", "fout_shared3_pll",
862 "dout_shared1_div3", "dout_shared0_div4",
863 "dout_shared1_div4", "dout_shared2_div2",
864 "fout_spare_pll" };
865
866 PNAME(mout_cmu_gdc_gdc1_p) = { "dout_shared0_div3", "fout_shared3_pll",
867 "dout_shared1_div3", "dout_shared0_div4",
868 "dout_shared1_div4", "dout_shared2_div2",
869 "fout_spare_pll" };
870
871 /* List of parent clocks for Muxes in CMU_TOP: for CMU_MFC */
872 PNAME(mout_cmu_mfc_mfc_p) = { "dout_shared0_div3", "fout_shared3_pll",
873 "dout_shared1_div3", "dout_shared0_div4",
874 "dout_shared1_div4", "dout_shared2_div2",
875 "fout_spare_pll" };
876
877 /* List of parent clocks for Muxes in CMU_TOP: for DDRPHY0/1/2/3 */
878
879 PNAME(mout_cmu_mif_switch_p) = { "fout_shared0_pll", "fout_shared1_pll",
880 "dout_shared0_div2", "dout_shared1_div2",
881 "fout_shared2_pll", "dout_shared0_div3",
882 "fout_shared3_pll", "fout_spare_pll" };
883
884 /* List of parent clocks for Muxes in CMU_TOP: for CMU_MIF0/1/2/3 */
885 PNAME(mout_cmu_mif_busp_p) = { "dout_shared0_div4", "dout_shared1_div4",
886 "dout_shared0_div5", "fout_spare_pll" };
887
> 888 PNAME(mout_cmu_boost_p) = { "dout_shared0_div4", "dout_shared1_div4",
889 "dout_shared2_div2", "dout_shared3_div2" };
890
891 /* List of parent clocks for Muxes in CMU_TOP: for CMU_MISC */
892 PNAME(mout_cmu_misc_bus_p) = { "dout_shared0_div4", "dout_shared2_div2",
893 "dout_shared3_div2", "fout_spare_pll" };
894 PNAME(mout_cmu_misc_sss_p) = { "dout_shared0_div4", "dout_shared2_div2",
895 "dout_shared3_div2", "fout_spare_pll" };
896
897 /* List of parent clocks for Muxes in CMU_TOP: for CMU_PERIC0 */
898 PNAME(mout_cmu_peric0_bus_p) = { "dout_shared0_div4", "dout_shared2_div2",
899 "dout_shared3_div2", "fout_spare_pll" };
900 PNAME(mout_cmu_peric0_ip_p) = { "dout_shared0_div4", "dout_shared2_div2",
901 "dout_shared3_div2", "fout_spare_pll" };
902
903 /* List of parent clocks for Muxes in CMU_TOP: for CMU_PERIC1 */
904 PNAME(mout_cmu_peric1_bus_p) = { "dout_shared0_div4", "dout_shared2_div2",
905 "dout_shared3_div2", "fout_spare_pll" };
906 PNAME(mout_cmu_peric1_ip_p) = { "dout_shared0_div4", "dout_shared2_div2",
907 "dout_shared3_div2", "fout_spare_pll" };
908
909 /* List of parent clocks for Muxes in CMU_TOP: for CMU_TPU */
910 PNAME(mout_cmu_tpu_tpu_p) = { "dout_shared0_div2", "dout_shared1_div2",
911 "fout_shared2_pll", "fout_shared3_pll",
912 "dout_shared0_div3", "dout_shared1_div3",
913 "dout_shared0_div4", "fout_spare_pll" };
914
915 PNAME(mout_cmu_tpu_tpuctl_p) = { "dout_shared0_div2", "dout_shared1_div2",
916 "fout_shared2_pll", "fout_shared3_pll",
917 "dout_shared0_div3", "dout_shared1_div3",
918 "dout_shared0_div4", "fout_spare_pll" };
919
920 PNAME(mout_cmu_tpu_bus_p) = { "dout_shared0_div2", "dout_shared1_div2",
921 "fout_shared2_pll", "fout_shared3_pll",
922 "dout_shared0_div3", "dout_shared1_div3",
923 "dout_shared0_div4", "fout_spare_pll" };
924
925 PNAME(mout_cmu_tpu_uart_p) = { "dout_shared0_div4", "dout_shared2_div2",
926 "dout_shared3_div2", "fout_spare_pll" };
927
928 /* List of parent clocks for Muxes in CMU_TOP: for CMU_BO */
929 PNAME(mout_cmu_bo_bus_p) = { "fout_shared2_pll", "dout_shared0_div3",
930 "fout_shared3_pll", "dout_shared1_div3",
931 "dout_shared0_div4", "dout_shared1_div4",
932 "fout_spare_pll" };
933
934 /* List of parent clocks for Muxes in CMU_TOP: for CMU_G2D */
> 935 PNAME(mout_cmu_g2d_p) = { "dout_shared0_div3", "fout_shared3_pll",
936 "dout_shared1_div3", "dout_shared0_div4",
937 "dout_shared1_div4", "dout_shared2_div2",
938 "fout_spare_pll" };
939
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 150+ messages in thread* Re: [PATCH 13/21] clk: samsung: clk-gs101: Add cmu_top registers, plls, mux and gates
@ 2023-10-14 6:37 ` kernel test robot
0 siblings, 0 replies; 150+ messages in thread
From: kernel test robot @ 2023-10-14 6:37 UTC (permalink / raw)
To: Peter Griffin, robh+dt, krzysztof.kozlowski+dt, mturquette,
conor+dt, sboyd, tomasz.figa, s.nawrocki, linus.walleij, wim,
linux, catalin.marinas, will, arnd, olof, cw00.choi
Cc: llvm, oe-kbuild-all, peter.griffin, tudor.ambarus, andre.draszik,
semen.protsenko, soc, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-clk, linux-gpio, linux-watchdog
Hi Peter,
kernel test robot noticed the following build warnings:
[auto build test WARNING on krzk/for-next]
[also build test WARNING on robh/for-next linus/master pinctrl-samsung/for-next v6.6-rc5 next-20231013]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Peter-Griffin/dt-bindings-interrupt-controller-Add-gs101-interrupt-controller/20231005-235922
base: https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git for-next
patch link: https://lore.kernel.org/r/20231005155618.700312-14-peter.griffin%40linaro.org
patch subject: [PATCH 13/21] clk: samsung: clk-gs101: Add cmu_top registers, plls, mux and gates
config: arm64-allyesconfig (https://download.01.org/0day-ci/archive/20231014/202310141437.xBrLtPIH-lkp@intel.com/config)
compiler: clang version 17.0.0 (https://github.com/llvm/llvm-project.git 4a5ac14ee968ff0ad5d2cc1ffa0299048db4c88a)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20231014/202310141437.xBrLtPIH-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202310141437.xBrLtPIH-lkp@intel.com/
All warnings (new ones prefixed by >>):
>> drivers/clk/samsung/clk-gs101.c:809:7: warning: unused variable 'mout_cmu_pdp_vra_p' [-Wunused-const-variable]
809 | PNAME(mout_cmu_pdp_vra_p) = { "fout_shared2_pll", "dout_shared0_div3",
| ^
>> drivers/clk/samsung/clk-gs101.c:888:7: warning: unused variable 'mout_cmu_boost_p' [-Wunused-const-variable]
888 | PNAME(mout_cmu_boost_p) = { "dout_shared0_div4", "dout_shared1_div4",
| ^
>> drivers/clk/samsung/clk-gs101.c:935:7: warning: unused variable 'mout_cmu_g2d_p' [-Wunused-const-variable]
935 | PNAME(mout_cmu_g2d_p) = { "dout_shared0_div3", "fout_shared3_pll",
| ^
3 warnings generated.
vim +/mout_cmu_pdp_vra_p +809 drivers/clk/samsung/clk-gs101.c
790
791 PNAME(mout_cmu_hsi2_ufs_embd_p) = { "oscclk", "dout_shared0_div4",
792 "dout_shared2_div2", "fout_spare_pll" };
793
794 PNAME(mout_cmu_hsi2_mmc_card_p) = { "fout_shared2_pll", "fout_shared3_pll",
795 "dout_shared0_div4", "fout_spare_pll" };
796
797 /* List of parent clocks for Muxes in CMU_TOP: for CMU_CSIS */
798 PNAME(mout_cmu_csis_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
799 "dout_shared1_div3", "dout_shared0_div4",
800 "dout_shared1_div4", "dout_shared2_div2",
801 "fout_spare_pll" };
802
803 /* List of parent clocks for Muxes in CMU_TOP: for CMU_PDP */
804 PNAME(mout_cmu_pdp_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
805 "dout_shared1_div3", "dout_shared0_div4",
806 "dout_shared1_div4", "dout_shared2_div2",
807 "fout_spare_pll" };
808
> 809 PNAME(mout_cmu_pdp_vra_p) = { "fout_shared2_pll", "dout_shared0_div3",
810 "fout_shared3_pll", "dout_shared1_div3",
811 "dout_shared0_div4", "dout_shared1_div4",
812 "fout_spare_pll" };
813
814 /* List of parent clocks for Muxes in CMU_TOP: for CMU_IPP */
815 PNAME(mout_cmu_ipp_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
816 "dout_shared1_div3", "dout_shared0_div4",
817 "dout_shared1_div4", "dout_shared2_div2",
818 "fout_spare_pll" };
819
820 /* List of parent clocks for Muxes in CMU_TOP: for CMU_G3AA */
821 PNAME(mout_cmu_g3aa_p) = { "dout_shared0_div3", "fout_shared3_pll",
822 "dout_shared1_div3", "dout_shared0_div4",
823 "dout_shared1_div4", "dout_shared2_div2",
824 "fout_spare_pll" };
825
826 /* List of parent clocks for Muxes in CMU_TOP: for CMU_ITP */
827 PNAME(mout_cmu_itp_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
828 "dout_shared1_div3", "dout_shared0_div4",
829 "dout_shared1_div4", "dout_shared2_div2",
830 "fout_spare_pll" };
831
832 /* List of parent clocks for Muxes in CMU_TOP: for CMU_DNS */
833 PNAME(mout_cmu_dns_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
834 "dout_shared1_div3", "dout_shared0_div4",
835 "dout_shared1_div4", "dout_shared2_div2",
836 "fout_spare_pll" };
837
838 /* List of parent clocks for Muxes in CMU_TOP: for CMU_TNR */
839 PNAME(mout_cmu_tnr_bus_p) = { "dout_shared0_div3", "fout_shared3_pll",
840 "dout_shared1_div3", "dout_shared0_div4",
841 "dout_shared1_div4", "dout_shared2_div2",
842 "fout_spare_pll" };
843
844 /* List of parent clocks for Muxes in CMU_TOP: for CMU_MCSC */
845 PNAME(mout_cmu_mcsc_itsc_p) = { "dout_shared0_div3", "fout_shared3_pll",
846 "dout_shared1_div3", "dout_shared0_div4",
847 "dout_shared1_div4", "dout_shared2_div2",
848 "fout_spare_pll" };
849
850 PNAME(mout_cmu_mcsc_mcsc_p) = { "dout_shared0_div3", "fout_shared3_pll",
851 "dout_shared1_div3", "dout_shared0_div4",
852 "dout_shared1_div4", "dout_shared2_div2",
853 "fout_spare_pll" };
854
855 /* List of parent clocks for Muxes in CMU_TOP: for CMU_GDC */
856 PNAME(mout_cmu_gdc_scsc_p) = { "dout_shared0_div3", "fout_shared3_pll",
857 "dout_shared1_div3", "dout_shared0_div4",
858 "dout_shared1_div4", "dout_shared2_div2",
859 "fout_spare_pll" };
860
861 PNAME(mout_cmu_gdc_gdc0_p) = { "dout_shared0_div3", "fout_shared3_pll",
862 "dout_shared1_div3", "dout_shared0_div4",
863 "dout_shared1_div4", "dout_shared2_div2",
864 "fout_spare_pll" };
865
866 PNAME(mout_cmu_gdc_gdc1_p) = { "dout_shared0_div3", "fout_shared3_pll",
867 "dout_shared1_div3", "dout_shared0_div4",
868 "dout_shared1_div4", "dout_shared2_div2",
869 "fout_spare_pll" };
870
871 /* List of parent clocks for Muxes in CMU_TOP: for CMU_MFC */
872 PNAME(mout_cmu_mfc_mfc_p) = { "dout_shared0_div3", "fout_shared3_pll",
873 "dout_shared1_div3", "dout_shared0_div4",
874 "dout_shared1_div4", "dout_shared2_div2",
875 "fout_spare_pll" };
876
877 /* List of parent clocks for Muxes in CMU_TOP: for DDRPHY0/1/2/3 */
878
879 PNAME(mout_cmu_mif_switch_p) = { "fout_shared0_pll", "fout_shared1_pll",
880 "dout_shared0_div2", "dout_shared1_div2",
881 "fout_shared2_pll", "dout_shared0_div3",
882 "fout_shared3_pll", "fout_spare_pll" };
883
884 /* List of parent clocks for Muxes in CMU_TOP: for CMU_MIF0/1/2/3 */
885 PNAME(mout_cmu_mif_busp_p) = { "dout_shared0_div4", "dout_shared1_div4",
886 "dout_shared0_div5", "fout_spare_pll" };
887
> 888 PNAME(mout_cmu_boost_p) = { "dout_shared0_div4", "dout_shared1_div4",
889 "dout_shared2_div2", "dout_shared3_div2" };
890
891 /* List of parent clocks for Muxes in CMU_TOP: for CMU_MISC */
892 PNAME(mout_cmu_misc_bus_p) = { "dout_shared0_div4", "dout_shared2_div2",
893 "dout_shared3_div2", "fout_spare_pll" };
894 PNAME(mout_cmu_misc_sss_p) = { "dout_shared0_div4", "dout_shared2_div2",
895 "dout_shared3_div2", "fout_spare_pll" };
896
897 /* List of parent clocks for Muxes in CMU_TOP: for CMU_PERIC0 */
898 PNAME(mout_cmu_peric0_bus_p) = { "dout_shared0_div4", "dout_shared2_div2",
899 "dout_shared3_div2", "fout_spare_pll" };
900 PNAME(mout_cmu_peric0_ip_p) = { "dout_shared0_div4", "dout_shared2_div2",
901 "dout_shared3_div2", "fout_spare_pll" };
902
903 /* List of parent clocks for Muxes in CMU_TOP: for CMU_PERIC1 */
904 PNAME(mout_cmu_peric1_bus_p) = { "dout_shared0_div4", "dout_shared2_div2",
905 "dout_shared3_div2", "fout_spare_pll" };
906 PNAME(mout_cmu_peric1_ip_p) = { "dout_shared0_div4", "dout_shared2_div2",
907 "dout_shared3_div2", "fout_spare_pll" };
908
909 /* List of parent clocks for Muxes in CMU_TOP: for CMU_TPU */
910 PNAME(mout_cmu_tpu_tpu_p) = { "dout_shared0_div2", "dout_shared1_div2",
911 "fout_shared2_pll", "fout_shared3_pll",
912 "dout_shared0_div3", "dout_shared1_div3",
913 "dout_shared0_div4", "fout_spare_pll" };
914
915 PNAME(mout_cmu_tpu_tpuctl_p) = { "dout_shared0_div2", "dout_shared1_div2",
916 "fout_shared2_pll", "fout_shared3_pll",
917 "dout_shared0_div3", "dout_shared1_div3",
918 "dout_shared0_div4", "fout_spare_pll" };
919
920 PNAME(mout_cmu_tpu_bus_p) = { "dout_shared0_div2", "dout_shared1_div2",
921 "fout_shared2_pll", "fout_shared3_pll",
922 "dout_shared0_div3", "dout_shared1_div3",
923 "dout_shared0_div4", "fout_spare_pll" };
924
925 PNAME(mout_cmu_tpu_uart_p) = { "dout_shared0_div4", "dout_shared2_div2",
926 "dout_shared3_div2", "fout_spare_pll" };
927
928 /* List of parent clocks for Muxes in CMU_TOP: for CMU_BO */
929 PNAME(mout_cmu_bo_bus_p) = { "fout_shared2_pll", "dout_shared0_div3",
930 "fout_shared3_pll", "dout_shared1_div3",
931 "dout_shared0_div4", "dout_shared1_div4",
932 "fout_spare_pll" };
933
934 /* List of parent clocks for Muxes in CMU_TOP: for CMU_G2D */
> 935 PNAME(mout_cmu_g2d_p) = { "dout_shared0_div3", "fout_shared3_pll",
936 "dout_shared1_div3", "dout_shared0_div4",
937 "dout_shared1_div4", "dout_shared2_div2",
938 "fout_spare_pll" };
939
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
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^ permalink raw reply [flat|nested] 150+ messages in thread
* [PATCH 14/21] clk: samsung: clk-gs101: add CMU_APM support
2023-10-05 15:55 ` Peter Griffin
@ 2023-10-05 15:56 ` Peter Griffin
-1 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-05 15:56 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi
Cc: peter.griffin, tudor.ambarus, andre.draszik, semen.protsenko,
soc, devicetree, linux-arm-kernel, linux-samsung-soc, linux-clk,
linux-gpio, linux-watchdog
This patch adds all the registers for the APM clock controller unit.
We register all the muxes and dividers, but only a few of the
gates currently for PMU and GPIO.
One clock is marked CLK_IS_CRITICAL because the system
hangs is this clock is disabled.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
drivers/clk/samsung/clk-gs101.c | 300 ++++++++++++++++++++++++++++++++
1 file changed, 300 insertions(+)
diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
index 4c58fcc899be..b98b42f54949 100644
--- a/drivers/clk/samsung/clk-gs101.c
+++ b/drivers/clk/samsung/clk-gs101.c
@@ -19,6 +19,7 @@
/* NOTE: Must be equal to the last clock ID increased by one */
#define TOP_NR_CLK (CLK_GOUT_CMU_BOOST + 1)
+#define APM_NR_CLK (CLK_APM_PLL_DIV16_APM + 1)
/* ---- CMU_TOP ------------------------------------------------------------- */
@@ -1556,3 +1557,302 @@ static void __init gs101_cmu_top_init(struct device_node *np)
/* Register CMU_TOP early, as it's a dependency for other early domains */
CLK_OF_DECLARE(gs101_cmu_top, "google,gs101-cmu-top",
gs101_cmu_top_init);
+
+/* ---- CMU_APM ------------------------------------------------------------- */
+/* Register Offset definitions for CMU_APM (0x17400000) */
+#define APM_CMU_APM_CONTROLLER_OPTION 0x0800
+#define CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0 0x0810
+#define CLK_CON_MUX_MUX_CLKCMU_APM_FUNC 0x1000
+#define CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC 0x1004
+#define CLK_CON_DIV_DIV_CLK_APM_BOOST 0x1800
+#define CLK_CON_DIV_DIV_CLK_APM_USI0_UART 0x1804
+#define CLK_CON_DIV_DIV_CLK_APM_USI0_USI 0x1808
+#define CLK_CON_DIV_DIV_CLK_APM_USI1_UART 0x180c
+#define CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK 0x2000
+#define CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1 0x2004
+#define CLK_CON_GAT_CLK_CMU_BOOST_OPTION1 0x2008
+#define CLK_CON_GAT_CLK_CORE_BOOST_OPTION1 0x200c
+#define CLK_CON_GAT_GATE_CLKCMU_APM_FUNC 0x2010
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK 0x2014
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK 0x2018
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK 0x201c
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK 0x2020
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK 0x2024
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK 0x2028
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK 0x202c
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK 0x2030
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK 0x2034
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK 0x2038
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK 0x203c
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK 0x2040
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK 0x2044
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK 0x2048
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK 0x204c
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK 0x2050
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK 0x2054
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK 0x2058
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK 0x205c
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK 0x2060
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK 0x2064
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK 0x2068
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK 0x206c
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK 0x2070
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK 0x2074
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK 0x207c
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK 0x2080
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK 0x2084
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK 0x2088
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK 0x208c
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK 0x2090
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK 0x2094
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK 0x2098
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK 0x209c
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK 0x20a0
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK 0x20a4
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK 0x20a8
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK 0x20ac
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK 0x20b0
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK 0x20b4
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK 0x20b8
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK 0x20bc
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK 0x20c0
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2 0x20c4
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK 0x20cc
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK 0x20d0
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK 0x20d4
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK 0x20d8
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK 0x20dc
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK 0x20e0
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK 0x20e4
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK 0x20e8
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_PCLK 0x20ec
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK 0x20f0
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK 0x20f4
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK 0x20f8
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK 0x20fc
+#define PCH_CON_LHM_AXI_G_SWD_PCH 0x3000
+#define PCH_CON_LHM_AXI_P_AOCAPM_PCH 0x3004
+#define PCH_CON_LHM_AXI_P_APM_PCH 0x3008
+#define PCH_CON_LHS_AXI_D_APM_PCH 0x300c
+#define PCH_CON_LHS_AXI_G_DBGCORE_PCH 0x3010
+#define PCH_CON_LHS_AXI_G_SCAN2DRAM_PCH 0x3014
+#define QCH_CON_APBIF_GPIO_ALIVE_QCH 0x3018
+#define QCH_CON_APBIF_GPIO_FAR_ALIVE_QCH 0x301c
+#define QCH_CON_APBIF_PMU_ALIVE_QCH 0x3020
+#define QCH_CON_APBIF_RTC_QCH 0x3024
+#define QCH_CON_APBIF_TRTC_QCH 0x3028
+#define QCH_CON_APM_CMU_APM_QCH 0x302c
+#define QCH_CON_APM_USI0_UART_QCH 0x3030
+#define QCH_CON_APM_USI0_USI_QCH 0x3034
+#define QCH_CON_APM_USI1_UART_QCH 0x3038
+#define QCH_CON_D_TZPC_APM_QCH 0x303c
+#define QCH_CON_GPC_APM_QCH 0x3040
+#define QCH_CON_GREBEINTEGRATION_QCH_DBG 0x3044
+#define QCH_CON_GREBEINTEGRATION_QCH_GREBE 0x3048
+#define QCH_CON_INTMEM_QCH 0x304c
+#define QCH_CON_LHM_AXI_G_SWD_QCH 0x3050
+#define QCH_CON_LHM_AXI_P_AOCAPM_QCH 0x3054
+#define QCH_CON_LHM_AXI_P_APM_QCH 0x3058
+#define QCH_CON_LHS_AXI_D_APM_QCH 0x305c
+#define QCH_CON_LHS_AXI_G_DBGCORE_QCH 0x3060
+#define QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH 0x3064
+#define QCH_CON_MAILBOX_APM_AOC_QCH 0x3068
+#define QCH_CON_MAILBOX_APM_AP_QCH 0x306c
+#define QCH_CON_MAILBOX_APM_GSA_QCH 0x3070
+#define QCH_CON_MAILBOX_APM_SWD_QCH 0x3078
+#define QCH_CON_MAILBOX_APM_TPU_QCH 0x307c
+#define QCH_CON_MAILBOX_AP_AOC_QCH 0x3080
+#define QCH_CON_MAILBOX_AP_DBGCORE_QCH 0x3084
+#define QCH_CON_PMU_INTR_GEN_QCH 0x3088
+#define QCH_CON_ROM_CRC32_HOST_QCH 0x308c
+#define QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE 0x3090
+#define QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE_DBG 0x3094
+#define QCH_CON_SPEEDY_APM_QCH 0x3098
+#define QCH_CON_SPEEDY_SUB_APM_QCH 0x309c
+#define QCH_CON_SSMT_D_APM_QCH 0x30a0
+#define QCH_CON_SSMT_G_DBGCORE_QCH 0x30a4
+#define QCH_CON_SS_DBGCORE_QCH_DBG 0x30a8
+#define QCH_CON_SS_DBGCORE_QCH_GREBE 0x30ac
+#define QCH_CON_SYSMMU_D_APM_QCH 0x30b0
+#define QCH_CON_SYSREG_APM_QCH 0x30b8
+#define QCH_CON_UASC_APM_QCH 0x30bc
+#define QCH_CON_UASC_DBGCORE_QCH 0x30c0
+#define QCH_CON_UASC_G_SWD_QCH 0x30c4
+#define QCH_CON_UASC_P_AOCAPM_QCH 0x30c8
+#define QCH_CON_UASC_P_APM_QCH 0x30cc
+#define QCH_CON_WDT_APM_QCH 0x30d0
+#define QUEUE_CTRL_REG_BLK_APM_CMU_APM 0x3c00
+
+static const unsigned long apm_clk_regs[] __initconst = {
+ APM_CMU_APM_CONTROLLER_OPTION,
+ CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0,
+ CLK_CON_MUX_MUX_CLKCMU_APM_FUNC,
+ CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC,
+ CLK_CON_DIV_DIV_CLK_APM_BOOST,
+ CLK_CON_DIV_DIV_CLK_APM_USI0_UART,
+ CLK_CON_DIV_DIV_CLK_APM_USI0_USI,
+ CLK_CON_DIV_DIV_CLK_APM_USI1_UART,
+ CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK,
+ CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1,
+ CLK_CON_GAT_CLK_CMU_BOOST_OPTION1,
+ CLK_CON_GAT_CLK_CORE_BOOST_OPTION1,
+ CLK_CON_GAT_GATE_CLKCMU_APM_FUNC,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK,
+};
+
+PNAME(mout_apm_func_p) = { "oscclk_apm", "mout_apm_funcsrc", "pad_clk_apm", "oscclk_apm" };
+PNAME(mout_apm_funcsrc_p) = { "pll_alv_div2_apm", "pll_alv_div4_apm", "pll_alv_div16_apm" };
+
+static const struct samsung_fixed_rate_clock apm_fixed_clks[] __initconst = {
+ FRATE(CLK_APM_PLL_DIV2_APM, "clk_apm_pll_div2_apm", NULL, 0, 393216000),
+ FRATE(CLK_APM_PLL_DIV4_APM, "clk_apm_pll_div4_apm", NULL, 0, 196608000),
+ FRATE(CLK_APM_PLL_DIV16_APM, "clk_apm_pll_div16_apm", NULL, 0, 49152000),
+};
+
+static const struct samsung_mux_clock apm_mux_clks[] __initconst = {
+ MUX(CLK_MOUT_APM_FUNC, "mout_apm_func", mout_apm_func_p,
+ CLK_CON_MUX_MUX_CLKCMU_APM_FUNC, 4, 1),
+ MUX(CLK_MOUT_APM_FUNCSRC, "mout_apm_funcsrc", mout_apm_funcsrc_p,
+ CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC, 3, 1),
+};
+
+static const struct samsung_div_clock apm_div_clks[] __initconst = {
+ DIV(CLK_DOUT_APM_BOOST, "dout_apm_boost", "gout_apm_func",
+ CLK_CON_DIV_DIV_CLK_APM_BOOST, 0, 1),
+ DIV(CLK_DOUT_APM_USI0_UART, "dout_apm_usi0_uart", "gout_apm_func",
+ CLK_CON_DIV_DIV_CLK_APM_USI0_UART, 0, 7),
+ DIV(CLK_DOUT_APM_USI0_USI, "dout_apm_usi0_usi", "gout_apm_func",
+ CLK_CON_DIV_DIV_CLK_APM_USI0_USI, 0, 7),
+ DIV(CLK_DOUT_APM_USI1_UART, "dout_apm_usi1_uart", "gout_apm_func",
+ CLK_CON_DIV_DIV_CLK_APM_USI1_UART, 0, 7),
+};
+
+static const struct samsung_gate_clock apm_gate_clks[] __initconst = {
+ GATE(CLK_GOUT_APM_FUNC, "gout_apm_func", "mout_apm_func",
+ CLK_CON_GAT_GATE_CLKCMU_APM_FUNC, 21, 0, 0),
+
+ GATE(CLK_GOUT_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK,
+ "gout_apm_gpio_alive_ipclkport_pclk", "gout_apm_func",
+ CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK,
+ "gout_apm_gpio_far_alive_ipclkport_pclk", "gout_apm_func",
+ CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK,
+ "gout_apm_pmu_alive_ipclkport_pclk", "gout_apm_func",
+ CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK,
+ 21, CLK_IS_CRITICAL, 0),
+
+ GATE(CLK_GOUT_APM_UID_SYSREG_APM_IPCLKPORT_PCLK,
+ "gout_apm_sysreg_apm_ipclkport_pclk", "gout_apm_func",
+ CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK,
+ 21, 0, 0),
+};
+
+static const struct samsung_cmu_info apm_cmu_info __initconst = {
+ .mux_clks = apm_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(apm_mux_clks),
+ .div_clks = apm_div_clks,
+ .nr_div_clks = ARRAY_SIZE(apm_div_clks),
+ .gate_clks = apm_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(apm_gate_clks),
+ .fixed_clks = apm_fixed_clks,
+ .nr_fixed_clks = ARRAY_SIZE(apm_fixed_clks),
+ .nr_clk_ids = APM_NR_CLK,
+ .clk_regs = apm_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(apm_clk_regs),
+};
+
+/* ---- platform_driver ----------------------------------------------------- */
+
+static int __init gs101_cmu_probe(struct platform_device *pdev)
+{
+ const struct samsung_cmu_info *info;
+ struct device *dev = &pdev->dev;
+
+ info = of_device_get_match_data(dev);
+ exynos_arm64_register_cmu(dev, dev->of_node, info);
+
+ return 0;
+}
+
+static const struct of_device_id gs101_cmu_of_match[] = {
+ {
+ .compatible = "google,gs101-cmu-apm",
+ .data = &apm_cmu_info,
+ },
+};
+
+static struct platform_driver gs101_cmu_driver __refdata = {
+ .driver = {
+ .name = "gs101-cmu",
+ .of_match_table = gs101_cmu_of_match,
+ .suppress_bind_attrs = true,
+ },
+ .probe = gs101_cmu_probe,
+};
+
+static int __init gs101_cmu_init(void)
+{
+ return platform_driver_register(&gs101_cmu_driver);
+}
+core_initcall(gs101_cmu_init);
--
2.42.0.582.g8ccd20d70d-goog
^ permalink raw reply related [flat|nested] 150+ messages in thread* [PATCH 14/21] clk: samsung: clk-gs101: add CMU_APM support
@ 2023-10-05 15:56 ` Peter Griffin
0 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-05 15:56 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi
Cc: peter.griffin, tudor.ambarus, andre.draszik, semen.protsenko,
soc, devicetree, linux-arm-kernel, linux-samsung-soc, linux-clk,
linux-gpio, linux-watchdog
This patch adds all the registers for the APM clock controller unit.
We register all the muxes and dividers, but only a few of the
gates currently for PMU and GPIO.
One clock is marked CLK_IS_CRITICAL because the system
hangs is this clock is disabled.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
drivers/clk/samsung/clk-gs101.c | 300 ++++++++++++++++++++++++++++++++
1 file changed, 300 insertions(+)
diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
index 4c58fcc899be..b98b42f54949 100644
--- a/drivers/clk/samsung/clk-gs101.c
+++ b/drivers/clk/samsung/clk-gs101.c
@@ -19,6 +19,7 @@
/* NOTE: Must be equal to the last clock ID increased by one */
#define TOP_NR_CLK (CLK_GOUT_CMU_BOOST + 1)
+#define APM_NR_CLK (CLK_APM_PLL_DIV16_APM + 1)
/* ---- CMU_TOP ------------------------------------------------------------- */
@@ -1556,3 +1557,302 @@ static void __init gs101_cmu_top_init(struct device_node *np)
/* Register CMU_TOP early, as it's a dependency for other early domains */
CLK_OF_DECLARE(gs101_cmu_top, "google,gs101-cmu-top",
gs101_cmu_top_init);
+
+/* ---- CMU_APM ------------------------------------------------------------- */
+/* Register Offset definitions for CMU_APM (0x17400000) */
+#define APM_CMU_APM_CONTROLLER_OPTION 0x0800
+#define CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0 0x0810
+#define CLK_CON_MUX_MUX_CLKCMU_APM_FUNC 0x1000
+#define CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC 0x1004
+#define CLK_CON_DIV_DIV_CLK_APM_BOOST 0x1800
+#define CLK_CON_DIV_DIV_CLK_APM_USI0_UART 0x1804
+#define CLK_CON_DIV_DIV_CLK_APM_USI0_USI 0x1808
+#define CLK_CON_DIV_DIV_CLK_APM_USI1_UART 0x180c
+#define CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK 0x2000
+#define CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1 0x2004
+#define CLK_CON_GAT_CLK_CMU_BOOST_OPTION1 0x2008
+#define CLK_CON_GAT_CLK_CORE_BOOST_OPTION1 0x200c
+#define CLK_CON_GAT_GATE_CLKCMU_APM_FUNC 0x2010
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK 0x2014
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK 0x2018
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK 0x201c
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK 0x2020
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK 0x2024
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK 0x2028
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK 0x202c
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK 0x2030
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK 0x2034
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK 0x2038
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK 0x203c
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK 0x2040
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK 0x2044
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK 0x2048
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK 0x204c
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK 0x2050
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK 0x2054
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK 0x2058
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK 0x205c
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK 0x2060
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK 0x2064
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK 0x2068
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK 0x206c
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK 0x2070
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK 0x2074
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK 0x207c
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK 0x2080
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK 0x2084
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK 0x2088
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK 0x208c
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK 0x2090
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK 0x2094
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK 0x2098
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK 0x209c
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK 0x20a0
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK 0x20a4
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK 0x20a8
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK 0x20ac
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK 0x20b0
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK 0x20b4
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK 0x20b8
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK 0x20bc
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK 0x20c0
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2 0x20c4
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK 0x20cc
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK 0x20d0
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK 0x20d4
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK 0x20d8
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK 0x20dc
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK 0x20e0
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK 0x20e4
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK 0x20e8
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_PCLK 0x20ec
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK 0x20f0
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK 0x20f4
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK 0x20f8
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK 0x20fc
+#define PCH_CON_LHM_AXI_G_SWD_PCH 0x3000
+#define PCH_CON_LHM_AXI_P_AOCAPM_PCH 0x3004
+#define PCH_CON_LHM_AXI_P_APM_PCH 0x3008
+#define PCH_CON_LHS_AXI_D_APM_PCH 0x300c
+#define PCH_CON_LHS_AXI_G_DBGCORE_PCH 0x3010
+#define PCH_CON_LHS_AXI_G_SCAN2DRAM_PCH 0x3014
+#define QCH_CON_APBIF_GPIO_ALIVE_QCH 0x3018
+#define QCH_CON_APBIF_GPIO_FAR_ALIVE_QCH 0x301c
+#define QCH_CON_APBIF_PMU_ALIVE_QCH 0x3020
+#define QCH_CON_APBIF_RTC_QCH 0x3024
+#define QCH_CON_APBIF_TRTC_QCH 0x3028
+#define QCH_CON_APM_CMU_APM_QCH 0x302c
+#define QCH_CON_APM_USI0_UART_QCH 0x3030
+#define QCH_CON_APM_USI0_USI_QCH 0x3034
+#define QCH_CON_APM_USI1_UART_QCH 0x3038
+#define QCH_CON_D_TZPC_APM_QCH 0x303c
+#define QCH_CON_GPC_APM_QCH 0x3040
+#define QCH_CON_GREBEINTEGRATION_QCH_DBG 0x3044
+#define QCH_CON_GREBEINTEGRATION_QCH_GREBE 0x3048
+#define QCH_CON_INTMEM_QCH 0x304c
+#define QCH_CON_LHM_AXI_G_SWD_QCH 0x3050
+#define QCH_CON_LHM_AXI_P_AOCAPM_QCH 0x3054
+#define QCH_CON_LHM_AXI_P_APM_QCH 0x3058
+#define QCH_CON_LHS_AXI_D_APM_QCH 0x305c
+#define QCH_CON_LHS_AXI_G_DBGCORE_QCH 0x3060
+#define QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH 0x3064
+#define QCH_CON_MAILBOX_APM_AOC_QCH 0x3068
+#define QCH_CON_MAILBOX_APM_AP_QCH 0x306c
+#define QCH_CON_MAILBOX_APM_GSA_QCH 0x3070
+#define QCH_CON_MAILBOX_APM_SWD_QCH 0x3078
+#define QCH_CON_MAILBOX_APM_TPU_QCH 0x307c
+#define QCH_CON_MAILBOX_AP_AOC_QCH 0x3080
+#define QCH_CON_MAILBOX_AP_DBGCORE_QCH 0x3084
+#define QCH_CON_PMU_INTR_GEN_QCH 0x3088
+#define QCH_CON_ROM_CRC32_HOST_QCH 0x308c
+#define QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE 0x3090
+#define QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE_DBG 0x3094
+#define QCH_CON_SPEEDY_APM_QCH 0x3098
+#define QCH_CON_SPEEDY_SUB_APM_QCH 0x309c
+#define QCH_CON_SSMT_D_APM_QCH 0x30a0
+#define QCH_CON_SSMT_G_DBGCORE_QCH 0x30a4
+#define QCH_CON_SS_DBGCORE_QCH_DBG 0x30a8
+#define QCH_CON_SS_DBGCORE_QCH_GREBE 0x30ac
+#define QCH_CON_SYSMMU_D_APM_QCH 0x30b0
+#define QCH_CON_SYSREG_APM_QCH 0x30b8
+#define QCH_CON_UASC_APM_QCH 0x30bc
+#define QCH_CON_UASC_DBGCORE_QCH 0x30c0
+#define QCH_CON_UASC_G_SWD_QCH 0x30c4
+#define QCH_CON_UASC_P_AOCAPM_QCH 0x30c8
+#define QCH_CON_UASC_P_APM_QCH 0x30cc
+#define QCH_CON_WDT_APM_QCH 0x30d0
+#define QUEUE_CTRL_REG_BLK_APM_CMU_APM 0x3c00
+
+static const unsigned long apm_clk_regs[] __initconst = {
+ APM_CMU_APM_CONTROLLER_OPTION,
+ CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0,
+ CLK_CON_MUX_MUX_CLKCMU_APM_FUNC,
+ CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC,
+ CLK_CON_DIV_DIV_CLK_APM_BOOST,
+ CLK_CON_DIV_DIV_CLK_APM_USI0_UART,
+ CLK_CON_DIV_DIV_CLK_APM_USI0_USI,
+ CLK_CON_DIV_DIV_CLK_APM_USI1_UART,
+ CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK,
+ CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1,
+ CLK_CON_GAT_CLK_CMU_BOOST_OPTION1,
+ CLK_CON_GAT_CLK_CORE_BOOST_OPTION1,
+ CLK_CON_GAT_GATE_CLKCMU_APM_FUNC,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK,
+};
+
+PNAME(mout_apm_func_p) = { "oscclk_apm", "mout_apm_funcsrc", "pad_clk_apm", "oscclk_apm" };
+PNAME(mout_apm_funcsrc_p) = { "pll_alv_div2_apm", "pll_alv_div4_apm", "pll_alv_div16_apm" };
+
+static const struct samsung_fixed_rate_clock apm_fixed_clks[] __initconst = {
+ FRATE(CLK_APM_PLL_DIV2_APM, "clk_apm_pll_div2_apm", NULL, 0, 393216000),
+ FRATE(CLK_APM_PLL_DIV4_APM, "clk_apm_pll_div4_apm", NULL, 0, 196608000),
+ FRATE(CLK_APM_PLL_DIV16_APM, "clk_apm_pll_div16_apm", NULL, 0, 49152000),
+};
+
+static const struct samsung_mux_clock apm_mux_clks[] __initconst = {
+ MUX(CLK_MOUT_APM_FUNC, "mout_apm_func", mout_apm_func_p,
+ CLK_CON_MUX_MUX_CLKCMU_APM_FUNC, 4, 1),
+ MUX(CLK_MOUT_APM_FUNCSRC, "mout_apm_funcsrc", mout_apm_funcsrc_p,
+ CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC, 3, 1),
+};
+
+static const struct samsung_div_clock apm_div_clks[] __initconst = {
+ DIV(CLK_DOUT_APM_BOOST, "dout_apm_boost", "gout_apm_func",
+ CLK_CON_DIV_DIV_CLK_APM_BOOST, 0, 1),
+ DIV(CLK_DOUT_APM_USI0_UART, "dout_apm_usi0_uart", "gout_apm_func",
+ CLK_CON_DIV_DIV_CLK_APM_USI0_UART, 0, 7),
+ DIV(CLK_DOUT_APM_USI0_USI, "dout_apm_usi0_usi", "gout_apm_func",
+ CLK_CON_DIV_DIV_CLK_APM_USI0_USI, 0, 7),
+ DIV(CLK_DOUT_APM_USI1_UART, "dout_apm_usi1_uart", "gout_apm_func",
+ CLK_CON_DIV_DIV_CLK_APM_USI1_UART, 0, 7),
+};
+
+static const struct samsung_gate_clock apm_gate_clks[] __initconst = {
+ GATE(CLK_GOUT_APM_FUNC, "gout_apm_func", "mout_apm_func",
+ CLK_CON_GAT_GATE_CLKCMU_APM_FUNC, 21, 0, 0),
+
+ GATE(CLK_GOUT_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK,
+ "gout_apm_gpio_alive_ipclkport_pclk", "gout_apm_func",
+ CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK,
+ "gout_apm_gpio_far_alive_ipclkport_pclk", "gout_apm_func",
+ CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK,
+ "gout_apm_pmu_alive_ipclkport_pclk", "gout_apm_func",
+ CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK,
+ 21, CLK_IS_CRITICAL, 0),
+
+ GATE(CLK_GOUT_APM_UID_SYSREG_APM_IPCLKPORT_PCLK,
+ "gout_apm_sysreg_apm_ipclkport_pclk", "gout_apm_func",
+ CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK,
+ 21, 0, 0),
+};
+
+static const struct samsung_cmu_info apm_cmu_info __initconst = {
+ .mux_clks = apm_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(apm_mux_clks),
+ .div_clks = apm_div_clks,
+ .nr_div_clks = ARRAY_SIZE(apm_div_clks),
+ .gate_clks = apm_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(apm_gate_clks),
+ .fixed_clks = apm_fixed_clks,
+ .nr_fixed_clks = ARRAY_SIZE(apm_fixed_clks),
+ .nr_clk_ids = APM_NR_CLK,
+ .clk_regs = apm_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(apm_clk_regs),
+};
+
+/* ---- platform_driver ----------------------------------------------------- */
+
+static int __init gs101_cmu_probe(struct platform_device *pdev)
+{
+ const struct samsung_cmu_info *info;
+ struct device *dev = &pdev->dev;
+
+ info = of_device_get_match_data(dev);
+ exynos_arm64_register_cmu(dev, dev->of_node, info);
+
+ return 0;
+}
+
+static const struct of_device_id gs101_cmu_of_match[] = {
+ {
+ .compatible = "google,gs101-cmu-apm",
+ .data = &apm_cmu_info,
+ },
+};
+
+static struct platform_driver gs101_cmu_driver __refdata = {
+ .driver = {
+ .name = "gs101-cmu",
+ .of_match_table = gs101_cmu_of_match,
+ .suppress_bind_attrs = true,
+ },
+ .probe = gs101_cmu_probe,
+};
+
+static int __init gs101_cmu_init(void)
+{
+ return platform_driver_register(&gs101_cmu_driver);
+}
+core_initcall(gs101_cmu_init);
--
2.42.0.582.g8ccd20d70d-goog
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^ permalink raw reply related [flat|nested] 150+ messages in thread* Re: [PATCH 14/21] clk: samsung: clk-gs101: add CMU_APM support
2023-10-05 15:56 ` Peter Griffin
@ 2023-10-05 17:43 ` William McVicker
-1 siblings, 0 replies; 150+ messages in thread
From: William McVicker @ 2023-10-05 17:43 UTC (permalink / raw)
To: Peter Griffin
Cc: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi, tudor.ambarus,
andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog, kernel-team
On 10/05/2023, Peter Griffin wrote:
> This patch adds all the registers for the APM clock controller unit.
>
> We register all the muxes and dividers, but only a few of the
> gates currently for PMU and GPIO.
>
> One clock is marked CLK_IS_CRITICAL because the system
> hangs is this clock is disabled.
nit: hangs if this clock...
Regards,
Will
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> drivers/clk/samsung/clk-gs101.c | 300 ++++++++++++++++++++++++++++++++
> 1 file changed, 300 insertions(+)
>
> diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
> index 4c58fcc899be..b98b42f54949 100644
> --- a/drivers/clk/samsung/clk-gs101.c
> +++ b/drivers/clk/samsung/clk-gs101.c
> @@ -19,6 +19,7 @@
>
> /* NOTE: Must be equal to the last clock ID increased by one */
> #define TOP_NR_CLK (CLK_GOUT_CMU_BOOST + 1)
> +#define APM_NR_CLK (CLK_APM_PLL_DIV16_APM + 1)
>
> /* ---- CMU_TOP ------------------------------------------------------------- */
>
> @@ -1556,3 +1557,302 @@ static void __init gs101_cmu_top_init(struct device_node *np)
> /* Register CMU_TOP early, as it's a dependency for other early domains */
> CLK_OF_DECLARE(gs101_cmu_top, "google,gs101-cmu-top",
> gs101_cmu_top_init);
> +
> +/* ---- CMU_APM ------------------------------------------------------------- */
> +/* Register Offset definitions for CMU_APM (0x17400000) */
> +#define APM_CMU_APM_CONTROLLER_OPTION 0x0800
> +#define CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0 0x0810
> +#define CLK_CON_MUX_MUX_CLKCMU_APM_FUNC 0x1000
> +#define CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC 0x1004
> +#define CLK_CON_DIV_DIV_CLK_APM_BOOST 0x1800
> +#define CLK_CON_DIV_DIV_CLK_APM_USI0_UART 0x1804
> +#define CLK_CON_DIV_DIV_CLK_APM_USI0_USI 0x1808
> +#define CLK_CON_DIV_DIV_CLK_APM_USI1_UART 0x180c
> +#define CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK 0x2000
> +#define CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1 0x2004
> +#define CLK_CON_GAT_CLK_CMU_BOOST_OPTION1 0x2008
> +#define CLK_CON_GAT_CLK_CORE_BOOST_OPTION1 0x200c
> +#define CLK_CON_GAT_GATE_CLKCMU_APM_FUNC 0x2010
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK 0x2014
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK 0x2018
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK 0x201c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK 0x2020
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK 0x2024
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK 0x2028
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK 0x202c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK 0x2030
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK 0x2034
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK 0x2038
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK 0x203c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK 0x2040
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK 0x2044
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK 0x2048
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK 0x204c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK 0x2050
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK 0x2054
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK 0x2058
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK 0x205c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK 0x2060
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK 0x2064
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK 0x2068
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK 0x206c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK 0x2070
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK 0x2074
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK 0x207c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK 0x2080
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK 0x2084
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK 0x2088
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK 0x208c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK 0x2090
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK 0x2094
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK 0x2098
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK 0x209c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK 0x20a0
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK 0x20a4
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK 0x20a8
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK 0x20ac
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK 0x20b0
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK 0x20b4
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK 0x20b8
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK 0x20bc
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK 0x20c0
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2 0x20c4
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK 0x20cc
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK 0x20d0
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK 0x20d4
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK 0x20d8
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK 0x20dc
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK 0x20e0
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK 0x20e4
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK 0x20e8
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_PCLK 0x20ec
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK 0x20f0
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK 0x20f4
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK 0x20f8
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK 0x20fc
> +#define PCH_CON_LHM_AXI_G_SWD_PCH 0x3000
> +#define PCH_CON_LHM_AXI_P_AOCAPM_PCH 0x3004
> +#define PCH_CON_LHM_AXI_P_APM_PCH 0x3008
> +#define PCH_CON_LHS_AXI_D_APM_PCH 0x300c
> +#define PCH_CON_LHS_AXI_G_DBGCORE_PCH 0x3010
> +#define PCH_CON_LHS_AXI_G_SCAN2DRAM_PCH 0x3014
> +#define QCH_CON_APBIF_GPIO_ALIVE_QCH 0x3018
> +#define QCH_CON_APBIF_GPIO_FAR_ALIVE_QCH 0x301c
> +#define QCH_CON_APBIF_PMU_ALIVE_QCH 0x3020
> +#define QCH_CON_APBIF_RTC_QCH 0x3024
> +#define QCH_CON_APBIF_TRTC_QCH 0x3028
> +#define QCH_CON_APM_CMU_APM_QCH 0x302c
> +#define QCH_CON_APM_USI0_UART_QCH 0x3030
> +#define QCH_CON_APM_USI0_USI_QCH 0x3034
> +#define QCH_CON_APM_USI1_UART_QCH 0x3038
> +#define QCH_CON_D_TZPC_APM_QCH 0x303c
> +#define QCH_CON_GPC_APM_QCH 0x3040
> +#define QCH_CON_GREBEINTEGRATION_QCH_DBG 0x3044
> +#define QCH_CON_GREBEINTEGRATION_QCH_GREBE 0x3048
> +#define QCH_CON_INTMEM_QCH 0x304c
> +#define QCH_CON_LHM_AXI_G_SWD_QCH 0x3050
> +#define QCH_CON_LHM_AXI_P_AOCAPM_QCH 0x3054
> +#define QCH_CON_LHM_AXI_P_APM_QCH 0x3058
> +#define QCH_CON_LHS_AXI_D_APM_QCH 0x305c
> +#define QCH_CON_LHS_AXI_G_DBGCORE_QCH 0x3060
> +#define QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH 0x3064
> +#define QCH_CON_MAILBOX_APM_AOC_QCH 0x3068
> +#define QCH_CON_MAILBOX_APM_AP_QCH 0x306c
> +#define QCH_CON_MAILBOX_APM_GSA_QCH 0x3070
> +#define QCH_CON_MAILBOX_APM_SWD_QCH 0x3078
> +#define QCH_CON_MAILBOX_APM_TPU_QCH 0x307c
> +#define QCH_CON_MAILBOX_AP_AOC_QCH 0x3080
> +#define QCH_CON_MAILBOX_AP_DBGCORE_QCH 0x3084
> +#define QCH_CON_PMU_INTR_GEN_QCH 0x3088
> +#define QCH_CON_ROM_CRC32_HOST_QCH 0x308c
> +#define QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE 0x3090
> +#define QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE_DBG 0x3094
> +#define QCH_CON_SPEEDY_APM_QCH 0x3098
> +#define QCH_CON_SPEEDY_SUB_APM_QCH 0x309c
> +#define QCH_CON_SSMT_D_APM_QCH 0x30a0
> +#define QCH_CON_SSMT_G_DBGCORE_QCH 0x30a4
> +#define QCH_CON_SS_DBGCORE_QCH_DBG 0x30a8
> +#define QCH_CON_SS_DBGCORE_QCH_GREBE 0x30ac
> +#define QCH_CON_SYSMMU_D_APM_QCH 0x30b0
> +#define QCH_CON_SYSREG_APM_QCH 0x30b8
> +#define QCH_CON_UASC_APM_QCH 0x30bc
> +#define QCH_CON_UASC_DBGCORE_QCH 0x30c0
> +#define QCH_CON_UASC_G_SWD_QCH 0x30c4
> +#define QCH_CON_UASC_P_AOCAPM_QCH 0x30c8
> +#define QCH_CON_UASC_P_APM_QCH 0x30cc
> +#define QCH_CON_WDT_APM_QCH 0x30d0
> +#define QUEUE_CTRL_REG_BLK_APM_CMU_APM 0x3c00
> +
> +static const unsigned long apm_clk_regs[] __initconst = {
> + APM_CMU_APM_CONTROLLER_OPTION,
> + CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0,
> + CLK_CON_MUX_MUX_CLKCMU_APM_FUNC,
> + CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC,
> + CLK_CON_DIV_DIV_CLK_APM_BOOST,
> + CLK_CON_DIV_DIV_CLK_APM_USI0_UART,
> + CLK_CON_DIV_DIV_CLK_APM_USI0_USI,
> + CLK_CON_DIV_DIV_CLK_APM_USI1_UART,
> + CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK,
> + CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1,
> + CLK_CON_GAT_CLK_CMU_BOOST_OPTION1,
> + CLK_CON_GAT_CLK_CORE_BOOST_OPTION1,
> + CLK_CON_GAT_GATE_CLKCMU_APM_FUNC,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK,
> +};
> +
> +PNAME(mout_apm_func_p) = { "oscclk_apm", "mout_apm_funcsrc", "pad_clk_apm", "oscclk_apm" };
> +PNAME(mout_apm_funcsrc_p) = { "pll_alv_div2_apm", "pll_alv_div4_apm", "pll_alv_div16_apm" };
> +
> +static const struct samsung_fixed_rate_clock apm_fixed_clks[] __initconst = {
> + FRATE(CLK_APM_PLL_DIV2_APM, "clk_apm_pll_div2_apm", NULL, 0, 393216000),
> + FRATE(CLK_APM_PLL_DIV4_APM, "clk_apm_pll_div4_apm", NULL, 0, 196608000),
> + FRATE(CLK_APM_PLL_DIV16_APM, "clk_apm_pll_div16_apm", NULL, 0, 49152000),
> +};
> +
> +static const struct samsung_mux_clock apm_mux_clks[] __initconst = {
> + MUX(CLK_MOUT_APM_FUNC, "mout_apm_func", mout_apm_func_p,
> + CLK_CON_MUX_MUX_CLKCMU_APM_FUNC, 4, 1),
> + MUX(CLK_MOUT_APM_FUNCSRC, "mout_apm_funcsrc", mout_apm_funcsrc_p,
> + CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC, 3, 1),
> +};
> +
> +static const struct samsung_div_clock apm_div_clks[] __initconst = {
> + DIV(CLK_DOUT_APM_BOOST, "dout_apm_boost", "gout_apm_func",
> + CLK_CON_DIV_DIV_CLK_APM_BOOST, 0, 1),
> + DIV(CLK_DOUT_APM_USI0_UART, "dout_apm_usi0_uart", "gout_apm_func",
> + CLK_CON_DIV_DIV_CLK_APM_USI0_UART, 0, 7),
> + DIV(CLK_DOUT_APM_USI0_USI, "dout_apm_usi0_usi", "gout_apm_func",
> + CLK_CON_DIV_DIV_CLK_APM_USI0_USI, 0, 7),
> + DIV(CLK_DOUT_APM_USI1_UART, "dout_apm_usi1_uart", "gout_apm_func",
> + CLK_CON_DIV_DIV_CLK_APM_USI1_UART, 0, 7),
> +};
> +
> +static const struct samsung_gate_clock apm_gate_clks[] __initconst = {
> + GATE(CLK_GOUT_APM_FUNC, "gout_apm_func", "mout_apm_func",
> + CLK_CON_GAT_GATE_CLKCMU_APM_FUNC, 21, 0, 0),
> +
> + GATE(CLK_GOUT_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK,
> + "gout_apm_gpio_alive_ipclkport_pclk", "gout_apm_func",
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK,
> + 21, 0, 0),
> +
> + GATE(CLK_GOUT_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK,
> + "gout_apm_gpio_far_alive_ipclkport_pclk", "gout_apm_func",
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK,
> + 21, 0, 0),
> +
> + GATE(CLK_GOUT_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK,
> + "gout_apm_pmu_alive_ipclkport_pclk", "gout_apm_func",
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK,
> + 21, CLK_IS_CRITICAL, 0),
> +
> + GATE(CLK_GOUT_APM_UID_SYSREG_APM_IPCLKPORT_PCLK,
> + "gout_apm_sysreg_apm_ipclkport_pclk", "gout_apm_func",
> + CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK,
> + 21, 0, 0),
> +};
> +
> +static const struct samsung_cmu_info apm_cmu_info __initconst = {
> + .mux_clks = apm_mux_clks,
> + .nr_mux_clks = ARRAY_SIZE(apm_mux_clks),
> + .div_clks = apm_div_clks,
> + .nr_div_clks = ARRAY_SIZE(apm_div_clks),
> + .gate_clks = apm_gate_clks,
> + .nr_gate_clks = ARRAY_SIZE(apm_gate_clks),
> + .fixed_clks = apm_fixed_clks,
> + .nr_fixed_clks = ARRAY_SIZE(apm_fixed_clks),
> + .nr_clk_ids = APM_NR_CLK,
> + .clk_regs = apm_clk_regs,
> + .nr_clk_regs = ARRAY_SIZE(apm_clk_regs),
> +};
> +
> +/* ---- platform_driver ----------------------------------------------------- */
> +
> +static int __init gs101_cmu_probe(struct platform_device *pdev)
> +{
> + const struct samsung_cmu_info *info;
> + struct device *dev = &pdev->dev;
> +
> + info = of_device_get_match_data(dev);
> + exynos_arm64_register_cmu(dev, dev->of_node, info);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id gs101_cmu_of_match[] = {
> + {
> + .compatible = "google,gs101-cmu-apm",
> + .data = &apm_cmu_info,
> + },
> +};
> +
> +static struct platform_driver gs101_cmu_driver __refdata = {
> + .driver = {
> + .name = "gs101-cmu",
> + .of_match_table = gs101_cmu_of_match,
> + .suppress_bind_attrs = true,
> + },
> + .probe = gs101_cmu_probe,
> +};
> +
> +static int __init gs101_cmu_init(void)
> +{
> + return platform_driver_register(&gs101_cmu_driver);
> +}
> +core_initcall(gs101_cmu_init);
> --
> 2.42.0.582.g8ccd20d70d-goog
>
^ permalink raw reply [flat|nested] 150+ messages in thread* Re: [PATCH 14/21] clk: samsung: clk-gs101: add CMU_APM support
@ 2023-10-05 17:43 ` William McVicker
0 siblings, 0 replies; 150+ messages in thread
From: William McVicker @ 2023-10-05 17:43 UTC (permalink / raw)
To: Peter Griffin
Cc: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi, tudor.ambarus,
andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog, kernel-team
On 10/05/2023, Peter Griffin wrote:
> This patch adds all the registers for the APM clock controller unit.
>
> We register all the muxes and dividers, but only a few of the
> gates currently for PMU and GPIO.
>
> One clock is marked CLK_IS_CRITICAL because the system
> hangs is this clock is disabled.
nit: hangs if this clock...
Regards,
Will
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> drivers/clk/samsung/clk-gs101.c | 300 ++++++++++++++++++++++++++++++++
> 1 file changed, 300 insertions(+)
>
> diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
> index 4c58fcc899be..b98b42f54949 100644
> --- a/drivers/clk/samsung/clk-gs101.c
> +++ b/drivers/clk/samsung/clk-gs101.c
> @@ -19,6 +19,7 @@
>
> /* NOTE: Must be equal to the last clock ID increased by one */
> #define TOP_NR_CLK (CLK_GOUT_CMU_BOOST + 1)
> +#define APM_NR_CLK (CLK_APM_PLL_DIV16_APM + 1)
>
> /* ---- CMU_TOP ------------------------------------------------------------- */
>
> @@ -1556,3 +1557,302 @@ static void __init gs101_cmu_top_init(struct device_node *np)
> /* Register CMU_TOP early, as it's a dependency for other early domains */
> CLK_OF_DECLARE(gs101_cmu_top, "google,gs101-cmu-top",
> gs101_cmu_top_init);
> +
> +/* ---- CMU_APM ------------------------------------------------------------- */
> +/* Register Offset definitions for CMU_APM (0x17400000) */
> +#define APM_CMU_APM_CONTROLLER_OPTION 0x0800
> +#define CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0 0x0810
> +#define CLK_CON_MUX_MUX_CLKCMU_APM_FUNC 0x1000
> +#define CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC 0x1004
> +#define CLK_CON_DIV_DIV_CLK_APM_BOOST 0x1800
> +#define CLK_CON_DIV_DIV_CLK_APM_USI0_UART 0x1804
> +#define CLK_CON_DIV_DIV_CLK_APM_USI0_USI 0x1808
> +#define CLK_CON_DIV_DIV_CLK_APM_USI1_UART 0x180c
> +#define CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK 0x2000
> +#define CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1 0x2004
> +#define CLK_CON_GAT_CLK_CMU_BOOST_OPTION1 0x2008
> +#define CLK_CON_GAT_CLK_CORE_BOOST_OPTION1 0x200c
> +#define CLK_CON_GAT_GATE_CLKCMU_APM_FUNC 0x2010
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK 0x2014
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK 0x2018
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK 0x201c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK 0x2020
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK 0x2024
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK 0x2028
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK 0x202c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK 0x2030
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK 0x2034
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK 0x2038
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK 0x203c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK 0x2040
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK 0x2044
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK 0x2048
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK 0x204c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK 0x2050
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK 0x2054
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK 0x2058
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK 0x205c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK 0x2060
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK 0x2064
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK 0x2068
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK 0x206c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK 0x2070
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK 0x2074
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK 0x207c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK 0x2080
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK 0x2084
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK 0x2088
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK 0x208c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK 0x2090
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK 0x2094
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK 0x2098
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK 0x209c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK 0x20a0
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK 0x20a4
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK 0x20a8
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK 0x20ac
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK 0x20b0
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK 0x20b4
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK 0x20b8
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK 0x20bc
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK 0x20c0
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2 0x20c4
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK 0x20cc
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK 0x20d0
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK 0x20d4
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK 0x20d8
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK 0x20dc
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK 0x20e0
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK 0x20e4
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK 0x20e8
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_PCLK 0x20ec
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK 0x20f0
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK 0x20f4
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK 0x20f8
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK 0x20fc
> +#define PCH_CON_LHM_AXI_G_SWD_PCH 0x3000
> +#define PCH_CON_LHM_AXI_P_AOCAPM_PCH 0x3004
> +#define PCH_CON_LHM_AXI_P_APM_PCH 0x3008
> +#define PCH_CON_LHS_AXI_D_APM_PCH 0x300c
> +#define PCH_CON_LHS_AXI_G_DBGCORE_PCH 0x3010
> +#define PCH_CON_LHS_AXI_G_SCAN2DRAM_PCH 0x3014
> +#define QCH_CON_APBIF_GPIO_ALIVE_QCH 0x3018
> +#define QCH_CON_APBIF_GPIO_FAR_ALIVE_QCH 0x301c
> +#define QCH_CON_APBIF_PMU_ALIVE_QCH 0x3020
> +#define QCH_CON_APBIF_RTC_QCH 0x3024
> +#define QCH_CON_APBIF_TRTC_QCH 0x3028
> +#define QCH_CON_APM_CMU_APM_QCH 0x302c
> +#define QCH_CON_APM_USI0_UART_QCH 0x3030
> +#define QCH_CON_APM_USI0_USI_QCH 0x3034
> +#define QCH_CON_APM_USI1_UART_QCH 0x3038
> +#define QCH_CON_D_TZPC_APM_QCH 0x303c
> +#define QCH_CON_GPC_APM_QCH 0x3040
> +#define QCH_CON_GREBEINTEGRATION_QCH_DBG 0x3044
> +#define QCH_CON_GREBEINTEGRATION_QCH_GREBE 0x3048
> +#define QCH_CON_INTMEM_QCH 0x304c
> +#define QCH_CON_LHM_AXI_G_SWD_QCH 0x3050
> +#define QCH_CON_LHM_AXI_P_AOCAPM_QCH 0x3054
> +#define QCH_CON_LHM_AXI_P_APM_QCH 0x3058
> +#define QCH_CON_LHS_AXI_D_APM_QCH 0x305c
> +#define QCH_CON_LHS_AXI_G_DBGCORE_QCH 0x3060
> +#define QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH 0x3064
> +#define QCH_CON_MAILBOX_APM_AOC_QCH 0x3068
> +#define QCH_CON_MAILBOX_APM_AP_QCH 0x306c
> +#define QCH_CON_MAILBOX_APM_GSA_QCH 0x3070
> +#define QCH_CON_MAILBOX_APM_SWD_QCH 0x3078
> +#define QCH_CON_MAILBOX_APM_TPU_QCH 0x307c
> +#define QCH_CON_MAILBOX_AP_AOC_QCH 0x3080
> +#define QCH_CON_MAILBOX_AP_DBGCORE_QCH 0x3084
> +#define QCH_CON_PMU_INTR_GEN_QCH 0x3088
> +#define QCH_CON_ROM_CRC32_HOST_QCH 0x308c
> +#define QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE 0x3090
> +#define QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE_DBG 0x3094
> +#define QCH_CON_SPEEDY_APM_QCH 0x3098
> +#define QCH_CON_SPEEDY_SUB_APM_QCH 0x309c
> +#define QCH_CON_SSMT_D_APM_QCH 0x30a0
> +#define QCH_CON_SSMT_G_DBGCORE_QCH 0x30a4
> +#define QCH_CON_SS_DBGCORE_QCH_DBG 0x30a8
> +#define QCH_CON_SS_DBGCORE_QCH_GREBE 0x30ac
> +#define QCH_CON_SYSMMU_D_APM_QCH 0x30b0
> +#define QCH_CON_SYSREG_APM_QCH 0x30b8
> +#define QCH_CON_UASC_APM_QCH 0x30bc
> +#define QCH_CON_UASC_DBGCORE_QCH 0x30c0
> +#define QCH_CON_UASC_G_SWD_QCH 0x30c4
> +#define QCH_CON_UASC_P_AOCAPM_QCH 0x30c8
> +#define QCH_CON_UASC_P_APM_QCH 0x30cc
> +#define QCH_CON_WDT_APM_QCH 0x30d0
> +#define QUEUE_CTRL_REG_BLK_APM_CMU_APM 0x3c00
> +
> +static const unsigned long apm_clk_regs[] __initconst = {
> + APM_CMU_APM_CONTROLLER_OPTION,
> + CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0,
> + CLK_CON_MUX_MUX_CLKCMU_APM_FUNC,
> + CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC,
> + CLK_CON_DIV_DIV_CLK_APM_BOOST,
> + CLK_CON_DIV_DIV_CLK_APM_USI0_UART,
> + CLK_CON_DIV_DIV_CLK_APM_USI0_USI,
> + CLK_CON_DIV_DIV_CLK_APM_USI1_UART,
> + CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK,
> + CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1,
> + CLK_CON_GAT_CLK_CMU_BOOST_OPTION1,
> + CLK_CON_GAT_CLK_CORE_BOOST_OPTION1,
> + CLK_CON_GAT_GATE_CLKCMU_APM_FUNC,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK,
> +};
> +
> +PNAME(mout_apm_func_p) = { "oscclk_apm", "mout_apm_funcsrc", "pad_clk_apm", "oscclk_apm" };
> +PNAME(mout_apm_funcsrc_p) = { "pll_alv_div2_apm", "pll_alv_div4_apm", "pll_alv_div16_apm" };
> +
> +static const struct samsung_fixed_rate_clock apm_fixed_clks[] __initconst = {
> + FRATE(CLK_APM_PLL_DIV2_APM, "clk_apm_pll_div2_apm", NULL, 0, 393216000),
> + FRATE(CLK_APM_PLL_DIV4_APM, "clk_apm_pll_div4_apm", NULL, 0, 196608000),
> + FRATE(CLK_APM_PLL_DIV16_APM, "clk_apm_pll_div16_apm", NULL, 0, 49152000),
> +};
> +
> +static const struct samsung_mux_clock apm_mux_clks[] __initconst = {
> + MUX(CLK_MOUT_APM_FUNC, "mout_apm_func", mout_apm_func_p,
> + CLK_CON_MUX_MUX_CLKCMU_APM_FUNC, 4, 1),
> + MUX(CLK_MOUT_APM_FUNCSRC, "mout_apm_funcsrc", mout_apm_funcsrc_p,
> + CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC, 3, 1),
> +};
> +
> +static const struct samsung_div_clock apm_div_clks[] __initconst = {
> + DIV(CLK_DOUT_APM_BOOST, "dout_apm_boost", "gout_apm_func",
> + CLK_CON_DIV_DIV_CLK_APM_BOOST, 0, 1),
> + DIV(CLK_DOUT_APM_USI0_UART, "dout_apm_usi0_uart", "gout_apm_func",
> + CLK_CON_DIV_DIV_CLK_APM_USI0_UART, 0, 7),
> + DIV(CLK_DOUT_APM_USI0_USI, "dout_apm_usi0_usi", "gout_apm_func",
> + CLK_CON_DIV_DIV_CLK_APM_USI0_USI, 0, 7),
> + DIV(CLK_DOUT_APM_USI1_UART, "dout_apm_usi1_uart", "gout_apm_func",
> + CLK_CON_DIV_DIV_CLK_APM_USI1_UART, 0, 7),
> +};
> +
> +static const struct samsung_gate_clock apm_gate_clks[] __initconst = {
> + GATE(CLK_GOUT_APM_FUNC, "gout_apm_func", "mout_apm_func",
> + CLK_CON_GAT_GATE_CLKCMU_APM_FUNC, 21, 0, 0),
> +
> + GATE(CLK_GOUT_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK,
> + "gout_apm_gpio_alive_ipclkport_pclk", "gout_apm_func",
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK,
> + 21, 0, 0),
> +
> + GATE(CLK_GOUT_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK,
> + "gout_apm_gpio_far_alive_ipclkport_pclk", "gout_apm_func",
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK,
> + 21, 0, 0),
> +
> + GATE(CLK_GOUT_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK,
> + "gout_apm_pmu_alive_ipclkport_pclk", "gout_apm_func",
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK,
> + 21, CLK_IS_CRITICAL, 0),
> +
> + GATE(CLK_GOUT_APM_UID_SYSREG_APM_IPCLKPORT_PCLK,
> + "gout_apm_sysreg_apm_ipclkport_pclk", "gout_apm_func",
> + CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK,
> + 21, 0, 0),
> +};
> +
> +static const struct samsung_cmu_info apm_cmu_info __initconst = {
> + .mux_clks = apm_mux_clks,
> + .nr_mux_clks = ARRAY_SIZE(apm_mux_clks),
> + .div_clks = apm_div_clks,
> + .nr_div_clks = ARRAY_SIZE(apm_div_clks),
> + .gate_clks = apm_gate_clks,
> + .nr_gate_clks = ARRAY_SIZE(apm_gate_clks),
> + .fixed_clks = apm_fixed_clks,
> + .nr_fixed_clks = ARRAY_SIZE(apm_fixed_clks),
> + .nr_clk_ids = APM_NR_CLK,
> + .clk_regs = apm_clk_regs,
> + .nr_clk_regs = ARRAY_SIZE(apm_clk_regs),
> +};
> +
> +/* ---- platform_driver ----------------------------------------------------- */
> +
> +static int __init gs101_cmu_probe(struct platform_device *pdev)
> +{
> + const struct samsung_cmu_info *info;
> + struct device *dev = &pdev->dev;
> +
> + info = of_device_get_match_data(dev);
> + exynos_arm64_register_cmu(dev, dev->of_node, info);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id gs101_cmu_of_match[] = {
> + {
> + .compatible = "google,gs101-cmu-apm",
> + .data = &apm_cmu_info,
> + },
> +};
> +
> +static struct platform_driver gs101_cmu_driver __refdata = {
> + .driver = {
> + .name = "gs101-cmu",
> + .of_match_table = gs101_cmu_of_match,
> + .suppress_bind_attrs = true,
> + },
> + .probe = gs101_cmu_probe,
> +};
> +
> +static int __init gs101_cmu_init(void)
> +{
> + return platform_driver_register(&gs101_cmu_driver);
> +}
> +core_initcall(gs101_cmu_init);
> --
> 2.42.0.582.g8ccd20d70d-goog
>
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^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 14/21] clk: samsung: clk-gs101: add CMU_APM support
2023-10-05 15:56 ` Peter Griffin
@ 2023-10-05 17:45 ` William McVicker
-1 siblings, 0 replies; 150+ messages in thread
From: William McVicker @ 2023-10-05 17:45 UTC (permalink / raw)
To: Peter Griffin
Cc: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi, tudor.ambarus,
andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog, kernel-team
On 10/05/2023, Peter Griffin wrote:
> This patch adds all the registers for the APM clock controller unit.
>
> We register all the muxes and dividers, but only a few of the
> gates currently for PMU and GPIO.
>
> One clock is marked CLK_IS_CRITICAL because the system
> hangs is this clock is disabled.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> drivers/clk/samsung/clk-gs101.c | 300 ++++++++++++++++++++++++++++++++
> 1 file changed, 300 insertions(+)
>
> diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
> index 4c58fcc899be..b98b42f54949 100644
> --- a/drivers/clk/samsung/clk-gs101.c
> +++ b/drivers/clk/samsung/clk-gs101.c
> @@ -19,6 +19,7 @@
>
> /* NOTE: Must be equal to the last clock ID increased by one */
> #define TOP_NR_CLK (CLK_GOUT_CMU_BOOST + 1)
> +#define APM_NR_CLK (CLK_APM_PLL_DIV16_APM + 1)
>
> /* ---- CMU_TOP ------------------------------------------------------------- */
>
> @@ -1556,3 +1557,302 @@ static void __init gs101_cmu_top_init(struct device_node *np)
> /* Register CMU_TOP early, as it's a dependency for other early domains */
> CLK_OF_DECLARE(gs101_cmu_top, "google,gs101-cmu-top",
> gs101_cmu_top_init);
> +
> +/* ---- CMU_APM ------------------------------------------------------------- */
> +/* Register Offset definitions for CMU_APM (0x17400000) */
> +#define APM_CMU_APM_CONTROLLER_OPTION 0x0800
> +#define CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0 0x0810
> +#define CLK_CON_MUX_MUX_CLKCMU_APM_FUNC 0x1000
> +#define CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC 0x1004
> +#define CLK_CON_DIV_DIV_CLK_APM_BOOST 0x1800
> +#define CLK_CON_DIV_DIV_CLK_APM_USI0_UART 0x1804
> +#define CLK_CON_DIV_DIV_CLK_APM_USI0_USI 0x1808
> +#define CLK_CON_DIV_DIV_CLK_APM_USI1_UART 0x180c
> +#define CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK 0x2000
> +#define CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1 0x2004
> +#define CLK_CON_GAT_CLK_CMU_BOOST_OPTION1 0x2008
> +#define CLK_CON_GAT_CLK_CORE_BOOST_OPTION1 0x200c
> +#define CLK_CON_GAT_GATE_CLKCMU_APM_FUNC 0x2010
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK 0x2014
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK 0x2018
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK 0x201c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK 0x2020
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK 0x2024
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK 0x2028
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK 0x202c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK 0x2030
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK 0x2034
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK 0x2038
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK 0x203c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK 0x2040
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK 0x2044
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK 0x2048
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK 0x204c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK 0x2050
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK 0x2054
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK 0x2058
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK 0x205c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK 0x2060
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK 0x2064
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK 0x2068
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK 0x206c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK 0x2070
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK 0x2074
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK 0x207c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK 0x2080
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK 0x2084
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK 0x2088
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK 0x208c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK 0x2090
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK 0x2094
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK 0x2098
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK 0x209c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK 0x20a0
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK 0x20a4
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK 0x20a8
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK 0x20ac
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK 0x20b0
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK 0x20b4
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK 0x20b8
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK 0x20bc
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK 0x20c0
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2 0x20c4
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK 0x20cc
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK 0x20d0
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK 0x20d4
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK 0x20d8
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK 0x20dc
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK 0x20e0
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK 0x20e4
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK 0x20e8
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_PCLK 0x20ec
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK 0x20f0
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK 0x20f4
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK 0x20f8
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK 0x20fc
> +#define PCH_CON_LHM_AXI_G_SWD_PCH 0x3000
> +#define PCH_CON_LHM_AXI_P_AOCAPM_PCH 0x3004
> +#define PCH_CON_LHM_AXI_P_APM_PCH 0x3008
> +#define PCH_CON_LHS_AXI_D_APM_PCH 0x300c
> +#define PCH_CON_LHS_AXI_G_DBGCORE_PCH 0x3010
> +#define PCH_CON_LHS_AXI_G_SCAN2DRAM_PCH 0x3014
> +#define QCH_CON_APBIF_GPIO_ALIVE_QCH 0x3018
> +#define QCH_CON_APBIF_GPIO_FAR_ALIVE_QCH 0x301c
> +#define QCH_CON_APBIF_PMU_ALIVE_QCH 0x3020
> +#define QCH_CON_APBIF_RTC_QCH 0x3024
> +#define QCH_CON_APBIF_TRTC_QCH 0x3028
> +#define QCH_CON_APM_CMU_APM_QCH 0x302c
> +#define QCH_CON_APM_USI0_UART_QCH 0x3030
> +#define QCH_CON_APM_USI0_USI_QCH 0x3034
> +#define QCH_CON_APM_USI1_UART_QCH 0x3038
> +#define QCH_CON_D_TZPC_APM_QCH 0x303c
> +#define QCH_CON_GPC_APM_QCH 0x3040
> +#define QCH_CON_GREBEINTEGRATION_QCH_DBG 0x3044
> +#define QCH_CON_GREBEINTEGRATION_QCH_GREBE 0x3048
> +#define QCH_CON_INTMEM_QCH 0x304c
> +#define QCH_CON_LHM_AXI_G_SWD_QCH 0x3050
> +#define QCH_CON_LHM_AXI_P_AOCAPM_QCH 0x3054
> +#define QCH_CON_LHM_AXI_P_APM_QCH 0x3058
> +#define QCH_CON_LHS_AXI_D_APM_QCH 0x305c
> +#define QCH_CON_LHS_AXI_G_DBGCORE_QCH 0x3060
> +#define QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH 0x3064
> +#define QCH_CON_MAILBOX_APM_AOC_QCH 0x3068
> +#define QCH_CON_MAILBOX_APM_AP_QCH 0x306c
> +#define QCH_CON_MAILBOX_APM_GSA_QCH 0x3070
> +#define QCH_CON_MAILBOX_APM_SWD_QCH 0x3078
> +#define QCH_CON_MAILBOX_APM_TPU_QCH 0x307c
> +#define QCH_CON_MAILBOX_AP_AOC_QCH 0x3080
> +#define QCH_CON_MAILBOX_AP_DBGCORE_QCH 0x3084
> +#define QCH_CON_PMU_INTR_GEN_QCH 0x3088
> +#define QCH_CON_ROM_CRC32_HOST_QCH 0x308c
> +#define QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE 0x3090
> +#define QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE_DBG 0x3094
> +#define QCH_CON_SPEEDY_APM_QCH 0x3098
> +#define QCH_CON_SPEEDY_SUB_APM_QCH 0x309c
> +#define QCH_CON_SSMT_D_APM_QCH 0x30a0
> +#define QCH_CON_SSMT_G_DBGCORE_QCH 0x30a4
> +#define QCH_CON_SS_DBGCORE_QCH_DBG 0x30a8
> +#define QCH_CON_SS_DBGCORE_QCH_GREBE 0x30ac
> +#define QCH_CON_SYSMMU_D_APM_QCH 0x30b0
> +#define QCH_CON_SYSREG_APM_QCH 0x30b8
> +#define QCH_CON_UASC_APM_QCH 0x30bc
> +#define QCH_CON_UASC_DBGCORE_QCH 0x30c0
> +#define QCH_CON_UASC_G_SWD_QCH 0x30c4
> +#define QCH_CON_UASC_P_AOCAPM_QCH 0x30c8
> +#define QCH_CON_UASC_P_APM_QCH 0x30cc
> +#define QCH_CON_WDT_APM_QCH 0x30d0
> +#define QUEUE_CTRL_REG_BLK_APM_CMU_APM 0x3c00
> +
> +static const unsigned long apm_clk_regs[] __initconst = {
> + APM_CMU_APM_CONTROLLER_OPTION,
> + CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0,
> + CLK_CON_MUX_MUX_CLKCMU_APM_FUNC,
> + CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC,
> + CLK_CON_DIV_DIV_CLK_APM_BOOST,
> + CLK_CON_DIV_DIV_CLK_APM_USI0_UART,
> + CLK_CON_DIV_DIV_CLK_APM_USI0_USI,
> + CLK_CON_DIV_DIV_CLK_APM_USI1_UART,
> + CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK,
> + CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1,
> + CLK_CON_GAT_CLK_CMU_BOOST_OPTION1,
> + CLK_CON_GAT_CLK_CORE_BOOST_OPTION1,
> + CLK_CON_GAT_GATE_CLKCMU_APM_FUNC,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK,
> +};
> +
> +PNAME(mout_apm_func_p) = { "oscclk_apm", "mout_apm_funcsrc", "pad_clk_apm", "oscclk_apm" };
> +PNAME(mout_apm_funcsrc_p) = { "pll_alv_div2_apm", "pll_alv_div4_apm", "pll_alv_div16_apm" };
> +
> +static const struct samsung_fixed_rate_clock apm_fixed_clks[] __initconst = {
> + FRATE(CLK_APM_PLL_DIV2_APM, "clk_apm_pll_div2_apm", NULL, 0, 393216000),
> + FRATE(CLK_APM_PLL_DIV4_APM, "clk_apm_pll_div4_apm", NULL, 0, 196608000),
> + FRATE(CLK_APM_PLL_DIV16_APM, "clk_apm_pll_div16_apm", NULL, 0, 49152000),
> +};
> +
> +static const struct samsung_mux_clock apm_mux_clks[] __initconst = {
> + MUX(CLK_MOUT_APM_FUNC, "mout_apm_func", mout_apm_func_p,
> + CLK_CON_MUX_MUX_CLKCMU_APM_FUNC, 4, 1),
> + MUX(CLK_MOUT_APM_FUNCSRC, "mout_apm_funcsrc", mout_apm_funcsrc_p,
> + CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC, 3, 1),
> +};
> +
> +static const struct samsung_div_clock apm_div_clks[] __initconst = {
> + DIV(CLK_DOUT_APM_BOOST, "dout_apm_boost", "gout_apm_func",
> + CLK_CON_DIV_DIV_CLK_APM_BOOST, 0, 1),
> + DIV(CLK_DOUT_APM_USI0_UART, "dout_apm_usi0_uart", "gout_apm_func",
> + CLK_CON_DIV_DIV_CLK_APM_USI0_UART, 0, 7),
> + DIV(CLK_DOUT_APM_USI0_USI, "dout_apm_usi0_usi", "gout_apm_func",
> + CLK_CON_DIV_DIV_CLK_APM_USI0_USI, 0, 7),
> + DIV(CLK_DOUT_APM_USI1_UART, "dout_apm_usi1_uart", "gout_apm_func",
> + CLK_CON_DIV_DIV_CLK_APM_USI1_UART, 0, 7),
> +};
> +
> +static const struct samsung_gate_clock apm_gate_clks[] __initconst = {
> + GATE(CLK_GOUT_APM_FUNC, "gout_apm_func", "mout_apm_func",
> + CLK_CON_GAT_GATE_CLKCMU_APM_FUNC, 21, 0, 0),
> +
> + GATE(CLK_GOUT_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK,
> + "gout_apm_gpio_alive_ipclkport_pclk", "gout_apm_func",
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK,
> + 21, 0, 0),
> +
> + GATE(CLK_GOUT_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK,
> + "gout_apm_gpio_far_alive_ipclkport_pclk", "gout_apm_func",
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK,
> + 21, 0, 0),
> +
> + GATE(CLK_GOUT_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK,
> + "gout_apm_pmu_alive_ipclkport_pclk", "gout_apm_func",
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK,
> + 21, CLK_IS_CRITICAL, 0),
> +
> + GATE(CLK_GOUT_APM_UID_SYSREG_APM_IPCLKPORT_PCLK,
> + "gout_apm_sysreg_apm_ipclkport_pclk", "gout_apm_func",
> + CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK,
> + 21, 0, 0),
> +};
> +
> +static const struct samsung_cmu_info apm_cmu_info __initconst = {
> + .mux_clks = apm_mux_clks,
> + .nr_mux_clks = ARRAY_SIZE(apm_mux_clks),
> + .div_clks = apm_div_clks,
> + .nr_div_clks = ARRAY_SIZE(apm_div_clks),
> + .gate_clks = apm_gate_clks,
> + .nr_gate_clks = ARRAY_SIZE(apm_gate_clks),
> + .fixed_clks = apm_fixed_clks,
> + .nr_fixed_clks = ARRAY_SIZE(apm_fixed_clks),
> + .nr_clk_ids = APM_NR_CLK,
> + .clk_regs = apm_clk_regs,
> + .nr_clk_regs = ARRAY_SIZE(apm_clk_regs),
> +};
> +
> +/* ---- platform_driver ----------------------------------------------------- */
> +
> +static int __init gs101_cmu_probe(struct platform_device *pdev)
> +{
> + const struct samsung_cmu_info *info;
> + struct device *dev = &pdev->dev;
> +
> + info = of_device_get_match_data(dev);
> + exynos_arm64_register_cmu(dev, dev->of_node, info);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id gs101_cmu_of_match[] = {
> + {
> + .compatible = "google,gs101-cmu-apm",
> + .data = &apm_cmu_info,
> + },
Missing terminating empty entry {}.
Regards,
Will
> +};
> +
> +static struct platform_driver gs101_cmu_driver __refdata = {
> + .driver = {
> + .name = "gs101-cmu",
> + .of_match_table = gs101_cmu_of_match,
> + .suppress_bind_attrs = true,
> + },
> + .probe = gs101_cmu_probe,
> +};
> +
> +static int __init gs101_cmu_init(void)
> +{
> + return platform_driver_register(&gs101_cmu_driver);
> +}
> +core_initcall(gs101_cmu_init);
> --
> 2.42.0.582.g8ccd20d70d-goog
>
^ permalink raw reply [flat|nested] 150+ messages in thread* Re: [PATCH 14/21] clk: samsung: clk-gs101: add CMU_APM support
@ 2023-10-05 17:45 ` William McVicker
0 siblings, 0 replies; 150+ messages in thread
From: William McVicker @ 2023-10-05 17:45 UTC (permalink / raw)
To: Peter Griffin
Cc: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi, tudor.ambarus,
andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog, kernel-team
On 10/05/2023, Peter Griffin wrote:
> This patch adds all the registers for the APM clock controller unit.
>
> We register all the muxes and dividers, but only a few of the
> gates currently for PMU and GPIO.
>
> One clock is marked CLK_IS_CRITICAL because the system
> hangs is this clock is disabled.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> drivers/clk/samsung/clk-gs101.c | 300 ++++++++++++++++++++++++++++++++
> 1 file changed, 300 insertions(+)
>
> diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
> index 4c58fcc899be..b98b42f54949 100644
> --- a/drivers/clk/samsung/clk-gs101.c
> +++ b/drivers/clk/samsung/clk-gs101.c
> @@ -19,6 +19,7 @@
>
> /* NOTE: Must be equal to the last clock ID increased by one */
> #define TOP_NR_CLK (CLK_GOUT_CMU_BOOST + 1)
> +#define APM_NR_CLK (CLK_APM_PLL_DIV16_APM + 1)
>
> /* ---- CMU_TOP ------------------------------------------------------------- */
>
> @@ -1556,3 +1557,302 @@ static void __init gs101_cmu_top_init(struct device_node *np)
> /* Register CMU_TOP early, as it's a dependency for other early domains */
> CLK_OF_DECLARE(gs101_cmu_top, "google,gs101-cmu-top",
> gs101_cmu_top_init);
> +
> +/* ---- CMU_APM ------------------------------------------------------------- */
> +/* Register Offset definitions for CMU_APM (0x17400000) */
> +#define APM_CMU_APM_CONTROLLER_OPTION 0x0800
> +#define CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0 0x0810
> +#define CLK_CON_MUX_MUX_CLKCMU_APM_FUNC 0x1000
> +#define CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC 0x1004
> +#define CLK_CON_DIV_DIV_CLK_APM_BOOST 0x1800
> +#define CLK_CON_DIV_DIV_CLK_APM_USI0_UART 0x1804
> +#define CLK_CON_DIV_DIV_CLK_APM_USI0_USI 0x1808
> +#define CLK_CON_DIV_DIV_CLK_APM_USI1_UART 0x180c
> +#define CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK 0x2000
> +#define CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1 0x2004
> +#define CLK_CON_GAT_CLK_CMU_BOOST_OPTION1 0x2008
> +#define CLK_CON_GAT_CLK_CORE_BOOST_OPTION1 0x200c
> +#define CLK_CON_GAT_GATE_CLKCMU_APM_FUNC 0x2010
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK 0x2014
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK 0x2018
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK 0x201c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK 0x2020
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK 0x2024
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK 0x2028
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK 0x202c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK 0x2030
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK 0x2034
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK 0x2038
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK 0x203c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK 0x2040
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK 0x2044
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK 0x2048
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK 0x204c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK 0x2050
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK 0x2054
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK 0x2058
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK 0x205c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK 0x2060
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK 0x2064
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK 0x2068
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK 0x206c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK 0x2070
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK 0x2074
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK 0x207c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK 0x2080
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK 0x2084
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK 0x2088
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK 0x208c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK 0x2090
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK 0x2094
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK 0x2098
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK 0x209c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK 0x20a0
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK 0x20a4
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK 0x20a8
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK 0x20ac
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK 0x20b0
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK 0x20b4
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK 0x20b8
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK 0x20bc
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK 0x20c0
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2 0x20c4
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK 0x20cc
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK 0x20d0
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK 0x20d4
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK 0x20d8
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK 0x20dc
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK 0x20e0
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK 0x20e4
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK 0x20e8
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_PCLK 0x20ec
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK 0x20f0
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK 0x20f4
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK 0x20f8
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK 0x20fc
> +#define PCH_CON_LHM_AXI_G_SWD_PCH 0x3000
> +#define PCH_CON_LHM_AXI_P_AOCAPM_PCH 0x3004
> +#define PCH_CON_LHM_AXI_P_APM_PCH 0x3008
> +#define PCH_CON_LHS_AXI_D_APM_PCH 0x300c
> +#define PCH_CON_LHS_AXI_G_DBGCORE_PCH 0x3010
> +#define PCH_CON_LHS_AXI_G_SCAN2DRAM_PCH 0x3014
> +#define QCH_CON_APBIF_GPIO_ALIVE_QCH 0x3018
> +#define QCH_CON_APBIF_GPIO_FAR_ALIVE_QCH 0x301c
> +#define QCH_CON_APBIF_PMU_ALIVE_QCH 0x3020
> +#define QCH_CON_APBIF_RTC_QCH 0x3024
> +#define QCH_CON_APBIF_TRTC_QCH 0x3028
> +#define QCH_CON_APM_CMU_APM_QCH 0x302c
> +#define QCH_CON_APM_USI0_UART_QCH 0x3030
> +#define QCH_CON_APM_USI0_USI_QCH 0x3034
> +#define QCH_CON_APM_USI1_UART_QCH 0x3038
> +#define QCH_CON_D_TZPC_APM_QCH 0x303c
> +#define QCH_CON_GPC_APM_QCH 0x3040
> +#define QCH_CON_GREBEINTEGRATION_QCH_DBG 0x3044
> +#define QCH_CON_GREBEINTEGRATION_QCH_GREBE 0x3048
> +#define QCH_CON_INTMEM_QCH 0x304c
> +#define QCH_CON_LHM_AXI_G_SWD_QCH 0x3050
> +#define QCH_CON_LHM_AXI_P_AOCAPM_QCH 0x3054
> +#define QCH_CON_LHM_AXI_P_APM_QCH 0x3058
> +#define QCH_CON_LHS_AXI_D_APM_QCH 0x305c
> +#define QCH_CON_LHS_AXI_G_DBGCORE_QCH 0x3060
> +#define QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH 0x3064
> +#define QCH_CON_MAILBOX_APM_AOC_QCH 0x3068
> +#define QCH_CON_MAILBOX_APM_AP_QCH 0x306c
> +#define QCH_CON_MAILBOX_APM_GSA_QCH 0x3070
> +#define QCH_CON_MAILBOX_APM_SWD_QCH 0x3078
> +#define QCH_CON_MAILBOX_APM_TPU_QCH 0x307c
> +#define QCH_CON_MAILBOX_AP_AOC_QCH 0x3080
> +#define QCH_CON_MAILBOX_AP_DBGCORE_QCH 0x3084
> +#define QCH_CON_PMU_INTR_GEN_QCH 0x3088
> +#define QCH_CON_ROM_CRC32_HOST_QCH 0x308c
> +#define QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE 0x3090
> +#define QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE_DBG 0x3094
> +#define QCH_CON_SPEEDY_APM_QCH 0x3098
> +#define QCH_CON_SPEEDY_SUB_APM_QCH 0x309c
> +#define QCH_CON_SSMT_D_APM_QCH 0x30a0
> +#define QCH_CON_SSMT_G_DBGCORE_QCH 0x30a4
> +#define QCH_CON_SS_DBGCORE_QCH_DBG 0x30a8
> +#define QCH_CON_SS_DBGCORE_QCH_GREBE 0x30ac
> +#define QCH_CON_SYSMMU_D_APM_QCH 0x30b0
> +#define QCH_CON_SYSREG_APM_QCH 0x30b8
> +#define QCH_CON_UASC_APM_QCH 0x30bc
> +#define QCH_CON_UASC_DBGCORE_QCH 0x30c0
> +#define QCH_CON_UASC_G_SWD_QCH 0x30c4
> +#define QCH_CON_UASC_P_AOCAPM_QCH 0x30c8
> +#define QCH_CON_UASC_P_APM_QCH 0x30cc
> +#define QCH_CON_WDT_APM_QCH 0x30d0
> +#define QUEUE_CTRL_REG_BLK_APM_CMU_APM 0x3c00
> +
> +static const unsigned long apm_clk_regs[] __initconst = {
> + APM_CMU_APM_CONTROLLER_OPTION,
> + CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0,
> + CLK_CON_MUX_MUX_CLKCMU_APM_FUNC,
> + CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC,
> + CLK_CON_DIV_DIV_CLK_APM_BOOST,
> + CLK_CON_DIV_DIV_CLK_APM_USI0_UART,
> + CLK_CON_DIV_DIV_CLK_APM_USI0_USI,
> + CLK_CON_DIV_DIV_CLK_APM_USI1_UART,
> + CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK,
> + CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1,
> + CLK_CON_GAT_CLK_CMU_BOOST_OPTION1,
> + CLK_CON_GAT_CLK_CORE_BOOST_OPTION1,
> + CLK_CON_GAT_GATE_CLKCMU_APM_FUNC,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK,
> +};
> +
> +PNAME(mout_apm_func_p) = { "oscclk_apm", "mout_apm_funcsrc", "pad_clk_apm", "oscclk_apm" };
> +PNAME(mout_apm_funcsrc_p) = { "pll_alv_div2_apm", "pll_alv_div4_apm", "pll_alv_div16_apm" };
> +
> +static const struct samsung_fixed_rate_clock apm_fixed_clks[] __initconst = {
> + FRATE(CLK_APM_PLL_DIV2_APM, "clk_apm_pll_div2_apm", NULL, 0, 393216000),
> + FRATE(CLK_APM_PLL_DIV4_APM, "clk_apm_pll_div4_apm", NULL, 0, 196608000),
> + FRATE(CLK_APM_PLL_DIV16_APM, "clk_apm_pll_div16_apm", NULL, 0, 49152000),
> +};
> +
> +static const struct samsung_mux_clock apm_mux_clks[] __initconst = {
> + MUX(CLK_MOUT_APM_FUNC, "mout_apm_func", mout_apm_func_p,
> + CLK_CON_MUX_MUX_CLKCMU_APM_FUNC, 4, 1),
> + MUX(CLK_MOUT_APM_FUNCSRC, "mout_apm_funcsrc", mout_apm_funcsrc_p,
> + CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC, 3, 1),
> +};
> +
> +static const struct samsung_div_clock apm_div_clks[] __initconst = {
> + DIV(CLK_DOUT_APM_BOOST, "dout_apm_boost", "gout_apm_func",
> + CLK_CON_DIV_DIV_CLK_APM_BOOST, 0, 1),
> + DIV(CLK_DOUT_APM_USI0_UART, "dout_apm_usi0_uart", "gout_apm_func",
> + CLK_CON_DIV_DIV_CLK_APM_USI0_UART, 0, 7),
> + DIV(CLK_DOUT_APM_USI0_USI, "dout_apm_usi0_usi", "gout_apm_func",
> + CLK_CON_DIV_DIV_CLK_APM_USI0_USI, 0, 7),
> + DIV(CLK_DOUT_APM_USI1_UART, "dout_apm_usi1_uart", "gout_apm_func",
> + CLK_CON_DIV_DIV_CLK_APM_USI1_UART, 0, 7),
> +};
> +
> +static const struct samsung_gate_clock apm_gate_clks[] __initconst = {
> + GATE(CLK_GOUT_APM_FUNC, "gout_apm_func", "mout_apm_func",
> + CLK_CON_GAT_GATE_CLKCMU_APM_FUNC, 21, 0, 0),
> +
> + GATE(CLK_GOUT_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK,
> + "gout_apm_gpio_alive_ipclkport_pclk", "gout_apm_func",
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK,
> + 21, 0, 0),
> +
> + GATE(CLK_GOUT_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK,
> + "gout_apm_gpio_far_alive_ipclkport_pclk", "gout_apm_func",
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK,
> + 21, 0, 0),
> +
> + GATE(CLK_GOUT_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK,
> + "gout_apm_pmu_alive_ipclkport_pclk", "gout_apm_func",
> + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK,
> + 21, CLK_IS_CRITICAL, 0),
> +
> + GATE(CLK_GOUT_APM_UID_SYSREG_APM_IPCLKPORT_PCLK,
> + "gout_apm_sysreg_apm_ipclkport_pclk", "gout_apm_func",
> + CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK,
> + 21, 0, 0),
> +};
> +
> +static const struct samsung_cmu_info apm_cmu_info __initconst = {
> + .mux_clks = apm_mux_clks,
> + .nr_mux_clks = ARRAY_SIZE(apm_mux_clks),
> + .div_clks = apm_div_clks,
> + .nr_div_clks = ARRAY_SIZE(apm_div_clks),
> + .gate_clks = apm_gate_clks,
> + .nr_gate_clks = ARRAY_SIZE(apm_gate_clks),
> + .fixed_clks = apm_fixed_clks,
> + .nr_fixed_clks = ARRAY_SIZE(apm_fixed_clks),
> + .nr_clk_ids = APM_NR_CLK,
> + .clk_regs = apm_clk_regs,
> + .nr_clk_regs = ARRAY_SIZE(apm_clk_regs),
> +};
> +
> +/* ---- platform_driver ----------------------------------------------------- */
> +
> +static int __init gs101_cmu_probe(struct platform_device *pdev)
> +{
> + const struct samsung_cmu_info *info;
> + struct device *dev = &pdev->dev;
> +
> + info = of_device_get_match_data(dev);
> + exynos_arm64_register_cmu(dev, dev->of_node, info);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id gs101_cmu_of_match[] = {
> + {
> + .compatible = "google,gs101-cmu-apm",
> + .data = &apm_cmu_info,
> + },
Missing terminating empty entry {}.
Regards,
Will
> +};
> +
> +static struct platform_driver gs101_cmu_driver __refdata = {
> + .driver = {
> + .name = "gs101-cmu",
> + .of_match_table = gs101_cmu_of_match,
> + .suppress_bind_attrs = true,
> + },
> + .probe = gs101_cmu_probe,
> +};
> +
> +static int __init gs101_cmu_init(void)
> +{
> + return platform_driver_register(&gs101_cmu_driver);
> +}
> +core_initcall(gs101_cmu_init);
> --
> 2.42.0.582.g8ccd20d70d-goog
>
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 150+ messages in thread
* [PATCH 15/21] clk: google: gs101: Add support for CMU_MISC clock unit
2023-10-05 15:55 ` Peter Griffin
@ 2023-10-05 15:56 ` Peter Griffin
-1 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-05 15:56 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi
Cc: peter.griffin, tudor.ambarus, andre.draszik, semen.protsenko,
soc, devicetree, linux-arm-kernel, linux-samsung-soc, linux-clk,
linux-gpio, linux-watchdog
CMU Misc clocks IPs such as Watchdog. Add support for the
muxes, dividers and gates in this CMU.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
drivers/clk/samsung/clk-gs101.c | 313 ++++++++++++++++++++++++++++++++
1 file changed, 313 insertions(+)
diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
index b98b42f54949..29b6e681d95c 100644
--- a/drivers/clk/samsung/clk-gs101.c
+++ b/drivers/clk/samsung/clk-gs101.c
@@ -20,6 +20,7 @@
/* NOTE: Must be equal to the last clock ID increased by one */
#define TOP_NR_CLK (CLK_GOUT_CMU_BOOST + 1)
#define APM_NR_CLK (CLK_APM_PLL_DIV16_APM + 1)
+#define MISC_NR_CLK (CLK_GOUT_MISC_WDT_CLUSTER1 + 1)
/* ---- CMU_TOP ------------------------------------------------------------- */
@@ -1822,6 +1823,315 @@ static const struct samsung_cmu_info apm_cmu_info __initconst = {
.nr_clk_regs = ARRAY_SIZE(apm_clk_regs),
};
+/* ---- CMU_MISC ------------------------------------------------------------- */
+/* Register Offset definitions for CMU_MISC (0x10010000) */
+#define PLL_CON0_MUX_CLKCMU_MISC_BUS_USER 0x0600
+#define PLL_CON1_MUX_CLKCMU_MISC_BUS_USER 0x0604
+#define PLL_CON0_MUX_CLKCMU_MISC_SSS_USER 0x0610
+#define PLL_CON1_MUX_CLKCMU_MISC_SSS_USER 0x0614
+#define MISC_CMU_MISC_CONTROLLER_OPTION 0x0800
+#define CLKOUT_CON_BLK_MISC_CMU_MISC_CLKOUT0 0x0810
+#define CLK_CON_MUX_MUX_CLK_MISC_GIC 0x1000
+#define CLK_CON_DIV_DIV_CLK_MISC_BUSP 0x1800
+#define CLK_CON_DIV_DIV_CLK_MISC_GIC 0x1804
+#define CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK 0x2000
+#define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK 0x2004
+#define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK 0x2008
+#define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK 0x200c
+#define CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK 0x2010
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM 0x2014
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM 0x2018
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM 0x201c
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A 0x2020
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK 0x2024
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK 0x2028
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK 0x202c
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK 0x2030
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_D_SSS_IPCLKPORT_I_CLK 0x2034
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_GIC_IPCLKPORT_I_CLK 0x2038
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_MISC_IPCLKPORT_I_CLK 0x203c
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK 0x2040
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK 0x2044
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AXI_D_SSS_IPCLKPORT_I_CLK 0x2048
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK 0x204c
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK 0x2050
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK 0x2054
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK 0x2058
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA_IPCLKPORT_ACLK 0x205c
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_DMA_IPCLKPORT_ACLK 0x2060
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK 0x2064
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK 0x2068
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK 0x206c
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK 0x2070
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK 0x2074
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_ACLK 0x2078
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_PCLK 0x207c
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_ACLK 0x2080
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_PCLK 0x2084
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK 0x2088
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK 0x208c
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_ACLK 0x2090
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_PCLK 0x2094
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK 0x2098
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK 0x209c
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK 0x20a0
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK 0x20a4
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK 0x20a8
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK 0x20ac
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK 0x20b0
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK 0x20b4
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA_IPCLKPORT_ACLK 0x20b8
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK 0x20bc
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK 0x20c0
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_ACLK 0x20c4
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_PCLK 0x20c8
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_ACLK 0x20cc
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_PCLK 0x20d0
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK 0x20d4
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK 0x20d8
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_ACLK 0x20dc
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_PCLK 0x20e0
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK 0x20e4
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK 0x20e8
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK 0x20ec
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK 0x20f0
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2 0x20f4
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1 0x20f8
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK 0x20fc
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK 0x2100
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK 0x2104
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK 0x2108
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK 0x210c
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK 0x2110
+#define DMYQCH_CON_PPMU_DMA_QCH 0x3000
+#define DMYQCH_CON_PUF_QCH 0x3004
+#define PCH_CON_LHM_AXI_D_SSS_PCH 0x300c
+#define PCH_CON_LHM_AXI_P_GIC_PCH 0x3010
+#define PCH_CON_LHM_AXI_P_MISC_PCH 0x3014
+#define PCH_CON_LHS_ACEL_D_MISC_PCH 0x3018
+#define PCH_CON_LHS_AST_IRI_GICCPU_PCH 0x301c
+#define PCH_CON_LHS_AXI_D_SSS_PCH 0x3020
+#define QCH_CON_ADM_AHB_SSS_QCH 0x3024
+#define QCH_CON_DIT_QCH 0x3028
+#define QCH_CON_GIC_QCH 0x3030
+#define QCH_CON_LHM_AST_ICC_CPUGIC_QCH 0x3038
+#define QCH_CON_LHM_AXI_D_SSS_QCH 0x303c
+#define QCH_CON_LHM_AXI_P_GIC_QCH 0x3040
+#define QCH_CON_LHM_AXI_P_MISC_QCH 0x3044
+#define QCH_CON_LHS_ACEL_D_MISC_QCH 0x3048
+#define QCH_CON_LHS_AST_IRI_GICCPU_QCH 0x304c
+#define QCH_CON_LHS_AXI_D_SSS_QCH 0x3050
+#define QCH_CON_MCT_QCH 0x3054
+#define QCH_CON_MISC_CMU_MISC_QCH 0x3058
+#define QCH_CON_OTP_CON_BIRA_QCH 0x305c
+#define QCH_CON_OTP_CON_BISR_QCH 0x3060
+#define QCH_CON_OTP_CON_TOP_QCH 0x3064
+#define QCH_CON_PDMA_QCH 0x3068
+#define QCH_CON_PPMU_MISC_QCH 0x306c
+#define QCH_CON_QE_DIT_QCH 0x3070
+#define QCH_CON_QE_PDMA_QCH 0x3074
+#define QCH_CON_QE_PPMU_DMA_QCH 0x3078
+#define QCH_CON_QE_RTIC_QCH 0x307c
+#define QCH_CON_QE_SPDMA_QCH 0x3080
+#define QCH_CON_QE_SSS_QCH 0x3084
+#define QCH_CON_RTIC_QCH 0x3088
+#define QCH_CON_SPDMA_QCH 0x308c
+#define QCH_CON_SSMT_DIT_QCH 0x3090
+#define QCH_CON_SSMT_PDMA_QCH 0x3094
+#define QCH_CON_SSMT_PPMU_DMA_QCH 0x3098
+#define QCH_CON_SSMT_RTIC_QCH 0x309c
+#define QCH_CON_SSMT_SPDMA_QCH 0x30a0
+#define QCH_CON_SSMT_SSS_QCH 0x30a4
+#define QCH_CON_SSS_QCH 0x30a8
+#define QCH_CON_SYSMMU_MISC_QCH 0x30ac
+#define QCH_CON_SYSMMU_SSS_QCH 0x30b0
+#define QCH_CON_SYSREG_MISC_QCH 0x30b4
+#define QCH_CON_TMU_SUB_QCH 0x30b8
+#define QCH_CON_TMU_TOP_QCH 0x30bc
+#define QCH_CON_WDT_CLUSTER0_QCH 0x30c0
+#define QCH_CON_WDT_CLUSTER1_QCH 0x30c4
+#define QUEUE_CTRL_REG_BLK_MISC_CMU_MISC 0x3c00
+
+static const unsigned long misc_clk_regs[] __initconst = {
+ PLL_CON0_MUX_CLKCMU_MISC_BUS_USER,
+ PLL_CON1_MUX_CLKCMU_MISC_BUS_USER,
+ PLL_CON0_MUX_CLKCMU_MISC_SSS_USER,
+ PLL_CON1_MUX_CLKCMU_MISC_SSS_USER,
+ MISC_CMU_MISC_CONTROLLER_OPTION,
+ CLKOUT_CON_BLK_MISC_CMU_MISC_CLKOUT0,
+ CLK_CON_MUX_MUX_CLK_MISC_GIC,
+ CLK_CON_DIV_DIV_CLK_MISC_BUSP,
+ CLK_CON_DIV_DIV_CLK_MISC_GIC,
+ CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK,
+ CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK,
+ CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK,
+ CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK,
+ CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_D_SSS_IPCLKPORT_I_CLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_GIC_IPCLKPORT_I_CLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_MISC_IPCLKPORT_I_CLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AXI_D_SSS_IPCLKPORT_I_CLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_DMA_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK,
+ DMYQCH_CON_PPMU_DMA_QCH,
+ DMYQCH_CON_PUF_QCH,
+ PCH_CON_LHM_AXI_D_SSS_PCH,
+ PCH_CON_LHM_AXI_P_GIC_PCH,
+ PCH_CON_LHM_AXI_P_MISC_PCH,
+ PCH_CON_LHS_ACEL_D_MISC_PCH,
+ PCH_CON_LHS_AST_IRI_GICCPU_PCH,
+ PCH_CON_LHS_AXI_D_SSS_PCH,
+ QCH_CON_ADM_AHB_SSS_QCH,
+ QCH_CON_DIT_QCH,
+ QCH_CON_GIC_QCH,
+ QCH_CON_LHM_AST_ICC_CPUGIC_QCH,
+ QCH_CON_LHM_AXI_D_SSS_QCH,
+ QCH_CON_LHM_AXI_P_GIC_QCH,
+ QCH_CON_LHM_AXI_P_MISC_QCH,
+ QCH_CON_LHS_ACEL_D_MISC_QCH,
+ QCH_CON_LHS_AST_IRI_GICCPU_QCH,
+ QCH_CON_LHS_AXI_D_SSS_QCH,
+ QCH_CON_MCT_QCH,
+ QCH_CON_MISC_CMU_MISC_QCH,
+ QCH_CON_OTP_CON_BIRA_QCH,
+ QCH_CON_OTP_CON_BISR_QCH,
+ QCH_CON_OTP_CON_TOP_QCH,
+ QCH_CON_PDMA_QCH,
+ QCH_CON_PPMU_MISC_QCH,
+ QCH_CON_QE_DIT_QCH,
+ QCH_CON_QE_PDMA_QCH,
+ QCH_CON_QE_PPMU_DMA_QCH,
+ QCH_CON_QE_RTIC_QCH,
+ QCH_CON_QE_SPDMA_QCH,
+ QCH_CON_QE_SSS_QCH,
+ QCH_CON_RTIC_QCH,
+ QCH_CON_SPDMA_QCH,
+ QCH_CON_SSMT_DIT_QCH,
+ QCH_CON_SSMT_PDMA_QCH,
+ QCH_CON_SSMT_PPMU_DMA_QCH,
+ QCH_CON_SSMT_RTIC_QCH,
+ QCH_CON_SSMT_SPDMA_QCH,
+ QCH_CON_SSMT_SSS_QCH,
+ QCH_CON_SSS_QCH,
+ QCH_CON_SYSMMU_MISC_QCH,
+ QCH_CON_SYSMMU_SSS_QCH,
+ QCH_CON_SYSREG_MISC_QCH,
+ QCH_CON_TMU_SUB_QCH,
+ QCH_CON_TMU_TOP_QCH,
+ QCH_CON_WDT_CLUSTER0_QCH,
+ QCH_CON_WDT_CLUSTER1_QCH,
+ QUEUE_CTRL_REG_BLK_MISC_CMU_MISC,
+};
+
+/* List of parent clocks for Muxes in CMU_MISC */
+PNAME(mout_misc_bus_user_p) = { "oscclk", "dout_cmu_misc_bus" };
+PNAME(mout_misc_sss_user_p) = { "oscclk", "dout_cmu_misc_sss" };
+PNAME(mout_misc_gic_p) = { "oscclk", "dout_cmu_misc_sss" };
+
+static const struct samsung_mux_clock misc_mux_clks[] __initconst = {
+ MUX(CLK_MOUT_MISC_BUS_USER, "mout_misc_bus_user", mout_misc_bus_user_p,
+ PLL_CON0_MUX_CLKCMU_MISC_BUS_USER, 4, 1),
+ MUX(CLK_MOUT_MISC_SSS_USER, "mout_misc_sss_user", mout_misc_sss_user_p,
+ PLL_CON0_MUX_CLKCMU_MISC_SSS_USER, 4, 1),
+};
+
+static const struct samsung_div_clock misc_div_clks[] __initconst = {
+ DIV(CLK_DOUT_MISC_BUSP, "dout_misc_busp", "mout_misc_bus_user",
+ CLK_CON_DIV_DIV_CLK_MISC_BUSP, 0, 3),
+ DIV(CLK_DOUT_MISC_GIC, "dout_misc_gic", "mout_misc_bus_user",
+ CLK_CON_DIV_DIV_CLK_MISC_GIC, 0, 3),
+};
+
+static const struct samsung_gate_clock misc_gate_clks[] __initconst = {
+ GATE(CLK_GOUT_MISC_PCLK, "gout_misc_pclk", "dout_misc_busp",
+ CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_MISC_SYSREG_PCLK, "gout_misc_sysreg_pclk", "dout_misc_busp",
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_MISC_WDT_CLUSTER0, "gout_misc_wdt_cluster0", "dout_misc_busp",
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_MISC_WDT_CLUSTER1, "gout_misc_wdt_cluster1", "dout_misc_busp",
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK,
+ 21, 0, 0),
+
+};
+
+static const struct samsung_cmu_info misc_cmu_info __initconst = {
+ .mux_clks = misc_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(misc_mux_clks),
+ .div_clks = misc_div_clks,
+ .nr_div_clks = ARRAY_SIZE(misc_div_clks),
+ .gate_clks = misc_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(misc_gate_clks),
+ .nr_clk_ids = MISC_NR_CLK,
+ .clk_regs = misc_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(misc_clk_regs),
+ .clk_name = "dout_misc_bus",
+};
+
/* ---- platform_driver ----------------------------------------------------- */
static int __init gs101_cmu_probe(struct platform_device *pdev)
@@ -1839,6 +2149,9 @@ static const struct of_device_id gs101_cmu_of_match[] = {
{
.compatible = "google,gs101-cmu-apm",
.data = &apm_cmu_info,
+ }, {
+ .compatible = "google,gs101-cmu-misc",
+ .data = &misc_cmu_info,
},
};
--
2.42.0.582.g8ccd20d70d-goog
^ permalink raw reply related [flat|nested] 150+ messages in thread* [PATCH 15/21] clk: google: gs101: Add support for CMU_MISC clock unit
@ 2023-10-05 15:56 ` Peter Griffin
0 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-05 15:56 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi
Cc: peter.griffin, tudor.ambarus, andre.draszik, semen.protsenko,
soc, devicetree, linux-arm-kernel, linux-samsung-soc, linux-clk,
linux-gpio, linux-watchdog
CMU Misc clocks IPs such as Watchdog. Add support for the
muxes, dividers and gates in this CMU.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
drivers/clk/samsung/clk-gs101.c | 313 ++++++++++++++++++++++++++++++++
1 file changed, 313 insertions(+)
diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
index b98b42f54949..29b6e681d95c 100644
--- a/drivers/clk/samsung/clk-gs101.c
+++ b/drivers/clk/samsung/clk-gs101.c
@@ -20,6 +20,7 @@
/* NOTE: Must be equal to the last clock ID increased by one */
#define TOP_NR_CLK (CLK_GOUT_CMU_BOOST + 1)
#define APM_NR_CLK (CLK_APM_PLL_DIV16_APM + 1)
+#define MISC_NR_CLK (CLK_GOUT_MISC_WDT_CLUSTER1 + 1)
/* ---- CMU_TOP ------------------------------------------------------------- */
@@ -1822,6 +1823,315 @@ static const struct samsung_cmu_info apm_cmu_info __initconst = {
.nr_clk_regs = ARRAY_SIZE(apm_clk_regs),
};
+/* ---- CMU_MISC ------------------------------------------------------------- */
+/* Register Offset definitions for CMU_MISC (0x10010000) */
+#define PLL_CON0_MUX_CLKCMU_MISC_BUS_USER 0x0600
+#define PLL_CON1_MUX_CLKCMU_MISC_BUS_USER 0x0604
+#define PLL_CON0_MUX_CLKCMU_MISC_SSS_USER 0x0610
+#define PLL_CON1_MUX_CLKCMU_MISC_SSS_USER 0x0614
+#define MISC_CMU_MISC_CONTROLLER_OPTION 0x0800
+#define CLKOUT_CON_BLK_MISC_CMU_MISC_CLKOUT0 0x0810
+#define CLK_CON_MUX_MUX_CLK_MISC_GIC 0x1000
+#define CLK_CON_DIV_DIV_CLK_MISC_BUSP 0x1800
+#define CLK_CON_DIV_DIV_CLK_MISC_GIC 0x1804
+#define CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK 0x2000
+#define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK 0x2004
+#define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK 0x2008
+#define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK 0x200c
+#define CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK 0x2010
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM 0x2014
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM 0x2018
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM 0x201c
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A 0x2020
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK 0x2024
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK 0x2028
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK 0x202c
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK 0x2030
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_D_SSS_IPCLKPORT_I_CLK 0x2034
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_GIC_IPCLKPORT_I_CLK 0x2038
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_MISC_IPCLKPORT_I_CLK 0x203c
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK 0x2040
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK 0x2044
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AXI_D_SSS_IPCLKPORT_I_CLK 0x2048
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK 0x204c
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK 0x2050
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK 0x2054
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK 0x2058
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA_IPCLKPORT_ACLK 0x205c
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_DMA_IPCLKPORT_ACLK 0x2060
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK 0x2064
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK 0x2068
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK 0x206c
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK 0x2070
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK 0x2074
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_ACLK 0x2078
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_PCLK 0x207c
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_ACLK 0x2080
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_PCLK 0x2084
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK 0x2088
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK 0x208c
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_ACLK 0x2090
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_PCLK 0x2094
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK 0x2098
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK 0x209c
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK 0x20a0
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK 0x20a4
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK 0x20a8
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK 0x20ac
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK 0x20b0
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK 0x20b4
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA_IPCLKPORT_ACLK 0x20b8
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK 0x20bc
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK 0x20c0
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_ACLK 0x20c4
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_PCLK 0x20c8
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_ACLK 0x20cc
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_PCLK 0x20d0
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK 0x20d4
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK 0x20d8
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_ACLK 0x20dc
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_PCLK 0x20e0
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK 0x20e4
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK 0x20e8
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK 0x20ec
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK 0x20f0
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2 0x20f4
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1 0x20f8
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK 0x20fc
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK 0x2100
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK 0x2104
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK 0x2108
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK 0x210c
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK 0x2110
+#define DMYQCH_CON_PPMU_DMA_QCH 0x3000
+#define DMYQCH_CON_PUF_QCH 0x3004
+#define PCH_CON_LHM_AXI_D_SSS_PCH 0x300c
+#define PCH_CON_LHM_AXI_P_GIC_PCH 0x3010
+#define PCH_CON_LHM_AXI_P_MISC_PCH 0x3014
+#define PCH_CON_LHS_ACEL_D_MISC_PCH 0x3018
+#define PCH_CON_LHS_AST_IRI_GICCPU_PCH 0x301c
+#define PCH_CON_LHS_AXI_D_SSS_PCH 0x3020
+#define QCH_CON_ADM_AHB_SSS_QCH 0x3024
+#define QCH_CON_DIT_QCH 0x3028
+#define QCH_CON_GIC_QCH 0x3030
+#define QCH_CON_LHM_AST_ICC_CPUGIC_QCH 0x3038
+#define QCH_CON_LHM_AXI_D_SSS_QCH 0x303c
+#define QCH_CON_LHM_AXI_P_GIC_QCH 0x3040
+#define QCH_CON_LHM_AXI_P_MISC_QCH 0x3044
+#define QCH_CON_LHS_ACEL_D_MISC_QCH 0x3048
+#define QCH_CON_LHS_AST_IRI_GICCPU_QCH 0x304c
+#define QCH_CON_LHS_AXI_D_SSS_QCH 0x3050
+#define QCH_CON_MCT_QCH 0x3054
+#define QCH_CON_MISC_CMU_MISC_QCH 0x3058
+#define QCH_CON_OTP_CON_BIRA_QCH 0x305c
+#define QCH_CON_OTP_CON_BISR_QCH 0x3060
+#define QCH_CON_OTP_CON_TOP_QCH 0x3064
+#define QCH_CON_PDMA_QCH 0x3068
+#define QCH_CON_PPMU_MISC_QCH 0x306c
+#define QCH_CON_QE_DIT_QCH 0x3070
+#define QCH_CON_QE_PDMA_QCH 0x3074
+#define QCH_CON_QE_PPMU_DMA_QCH 0x3078
+#define QCH_CON_QE_RTIC_QCH 0x307c
+#define QCH_CON_QE_SPDMA_QCH 0x3080
+#define QCH_CON_QE_SSS_QCH 0x3084
+#define QCH_CON_RTIC_QCH 0x3088
+#define QCH_CON_SPDMA_QCH 0x308c
+#define QCH_CON_SSMT_DIT_QCH 0x3090
+#define QCH_CON_SSMT_PDMA_QCH 0x3094
+#define QCH_CON_SSMT_PPMU_DMA_QCH 0x3098
+#define QCH_CON_SSMT_RTIC_QCH 0x309c
+#define QCH_CON_SSMT_SPDMA_QCH 0x30a0
+#define QCH_CON_SSMT_SSS_QCH 0x30a4
+#define QCH_CON_SSS_QCH 0x30a8
+#define QCH_CON_SYSMMU_MISC_QCH 0x30ac
+#define QCH_CON_SYSMMU_SSS_QCH 0x30b0
+#define QCH_CON_SYSREG_MISC_QCH 0x30b4
+#define QCH_CON_TMU_SUB_QCH 0x30b8
+#define QCH_CON_TMU_TOP_QCH 0x30bc
+#define QCH_CON_WDT_CLUSTER0_QCH 0x30c0
+#define QCH_CON_WDT_CLUSTER1_QCH 0x30c4
+#define QUEUE_CTRL_REG_BLK_MISC_CMU_MISC 0x3c00
+
+static const unsigned long misc_clk_regs[] __initconst = {
+ PLL_CON0_MUX_CLKCMU_MISC_BUS_USER,
+ PLL_CON1_MUX_CLKCMU_MISC_BUS_USER,
+ PLL_CON0_MUX_CLKCMU_MISC_SSS_USER,
+ PLL_CON1_MUX_CLKCMU_MISC_SSS_USER,
+ MISC_CMU_MISC_CONTROLLER_OPTION,
+ CLKOUT_CON_BLK_MISC_CMU_MISC_CLKOUT0,
+ CLK_CON_MUX_MUX_CLK_MISC_GIC,
+ CLK_CON_DIV_DIV_CLK_MISC_BUSP,
+ CLK_CON_DIV_DIV_CLK_MISC_GIC,
+ CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK,
+ CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK,
+ CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK,
+ CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK,
+ CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_D_SSS_IPCLKPORT_I_CLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_GIC_IPCLKPORT_I_CLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_MISC_IPCLKPORT_I_CLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AXI_D_SSS_IPCLKPORT_I_CLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_DMA_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK,
+ DMYQCH_CON_PPMU_DMA_QCH,
+ DMYQCH_CON_PUF_QCH,
+ PCH_CON_LHM_AXI_D_SSS_PCH,
+ PCH_CON_LHM_AXI_P_GIC_PCH,
+ PCH_CON_LHM_AXI_P_MISC_PCH,
+ PCH_CON_LHS_ACEL_D_MISC_PCH,
+ PCH_CON_LHS_AST_IRI_GICCPU_PCH,
+ PCH_CON_LHS_AXI_D_SSS_PCH,
+ QCH_CON_ADM_AHB_SSS_QCH,
+ QCH_CON_DIT_QCH,
+ QCH_CON_GIC_QCH,
+ QCH_CON_LHM_AST_ICC_CPUGIC_QCH,
+ QCH_CON_LHM_AXI_D_SSS_QCH,
+ QCH_CON_LHM_AXI_P_GIC_QCH,
+ QCH_CON_LHM_AXI_P_MISC_QCH,
+ QCH_CON_LHS_ACEL_D_MISC_QCH,
+ QCH_CON_LHS_AST_IRI_GICCPU_QCH,
+ QCH_CON_LHS_AXI_D_SSS_QCH,
+ QCH_CON_MCT_QCH,
+ QCH_CON_MISC_CMU_MISC_QCH,
+ QCH_CON_OTP_CON_BIRA_QCH,
+ QCH_CON_OTP_CON_BISR_QCH,
+ QCH_CON_OTP_CON_TOP_QCH,
+ QCH_CON_PDMA_QCH,
+ QCH_CON_PPMU_MISC_QCH,
+ QCH_CON_QE_DIT_QCH,
+ QCH_CON_QE_PDMA_QCH,
+ QCH_CON_QE_PPMU_DMA_QCH,
+ QCH_CON_QE_RTIC_QCH,
+ QCH_CON_QE_SPDMA_QCH,
+ QCH_CON_QE_SSS_QCH,
+ QCH_CON_RTIC_QCH,
+ QCH_CON_SPDMA_QCH,
+ QCH_CON_SSMT_DIT_QCH,
+ QCH_CON_SSMT_PDMA_QCH,
+ QCH_CON_SSMT_PPMU_DMA_QCH,
+ QCH_CON_SSMT_RTIC_QCH,
+ QCH_CON_SSMT_SPDMA_QCH,
+ QCH_CON_SSMT_SSS_QCH,
+ QCH_CON_SSS_QCH,
+ QCH_CON_SYSMMU_MISC_QCH,
+ QCH_CON_SYSMMU_SSS_QCH,
+ QCH_CON_SYSREG_MISC_QCH,
+ QCH_CON_TMU_SUB_QCH,
+ QCH_CON_TMU_TOP_QCH,
+ QCH_CON_WDT_CLUSTER0_QCH,
+ QCH_CON_WDT_CLUSTER1_QCH,
+ QUEUE_CTRL_REG_BLK_MISC_CMU_MISC,
+};
+
+/* List of parent clocks for Muxes in CMU_MISC */
+PNAME(mout_misc_bus_user_p) = { "oscclk", "dout_cmu_misc_bus" };
+PNAME(mout_misc_sss_user_p) = { "oscclk", "dout_cmu_misc_sss" };
+PNAME(mout_misc_gic_p) = { "oscclk", "dout_cmu_misc_sss" };
+
+static const struct samsung_mux_clock misc_mux_clks[] __initconst = {
+ MUX(CLK_MOUT_MISC_BUS_USER, "mout_misc_bus_user", mout_misc_bus_user_p,
+ PLL_CON0_MUX_CLKCMU_MISC_BUS_USER, 4, 1),
+ MUX(CLK_MOUT_MISC_SSS_USER, "mout_misc_sss_user", mout_misc_sss_user_p,
+ PLL_CON0_MUX_CLKCMU_MISC_SSS_USER, 4, 1),
+};
+
+static const struct samsung_div_clock misc_div_clks[] __initconst = {
+ DIV(CLK_DOUT_MISC_BUSP, "dout_misc_busp", "mout_misc_bus_user",
+ CLK_CON_DIV_DIV_CLK_MISC_BUSP, 0, 3),
+ DIV(CLK_DOUT_MISC_GIC, "dout_misc_gic", "mout_misc_bus_user",
+ CLK_CON_DIV_DIV_CLK_MISC_GIC, 0, 3),
+};
+
+static const struct samsung_gate_clock misc_gate_clks[] __initconst = {
+ GATE(CLK_GOUT_MISC_PCLK, "gout_misc_pclk", "dout_misc_busp",
+ CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_MISC_SYSREG_PCLK, "gout_misc_sysreg_pclk", "dout_misc_busp",
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_MISC_WDT_CLUSTER0, "gout_misc_wdt_cluster0", "dout_misc_busp",
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_MISC_WDT_CLUSTER1, "gout_misc_wdt_cluster1", "dout_misc_busp",
+ CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK,
+ 21, 0, 0),
+
+};
+
+static const struct samsung_cmu_info misc_cmu_info __initconst = {
+ .mux_clks = misc_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(misc_mux_clks),
+ .div_clks = misc_div_clks,
+ .nr_div_clks = ARRAY_SIZE(misc_div_clks),
+ .gate_clks = misc_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(misc_gate_clks),
+ .nr_clk_ids = MISC_NR_CLK,
+ .clk_regs = misc_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(misc_clk_regs),
+ .clk_name = "dout_misc_bus",
+};
+
/* ---- platform_driver ----------------------------------------------------- */
static int __init gs101_cmu_probe(struct platform_device *pdev)
@@ -1839,6 +2149,9 @@ static const struct of_device_id gs101_cmu_of_match[] = {
{
.compatible = "google,gs101-cmu-apm",
.data = &apm_cmu_info,
+ }, {
+ .compatible = "google,gs101-cmu-misc",
+ .data = &misc_cmu_info,
},
};
--
2.42.0.582.g8ccd20d70d-goog
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^ permalink raw reply related [flat|nested] 150+ messages in thread* Re: [PATCH 15/21] clk: google: gs101: Add support for CMU_MISC clock unit
2023-10-05 15:56 ` Peter Griffin
@ 2023-10-06 5:20 ` kernel test robot
-1 siblings, 0 replies; 150+ messages in thread
From: kernel test robot @ 2023-10-06 5:20 UTC (permalink / raw)
To: Peter Griffin, robh+dt, krzysztof.kozlowski+dt, mturquette,
conor+dt, sboyd, tomasz.figa, s.nawrocki, linus.walleij, wim,
linux, catalin.marinas, will, arnd, olof, cw00.choi
Cc: oe-kbuild-all, peter.griffin, tudor.ambarus, andre.draszik,
semen.protsenko, soc, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-clk, linux-gpio, linux-watchdog
Hi Peter,
kernel test robot noticed the following build warnings:
[auto build test WARNING on krzk/for-next]
[also build test WARNING on robh/for-next linus/master v6.6-rc4 next-20231005]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Peter-Griffin/dt-bindings-interrupt-controller-Add-gs101-interrupt-controller/20231005-235922
base: https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git for-next
patch link: https://lore.kernel.org/r/20231005155618.700312-16-peter.griffin%40linaro.org
patch subject: [PATCH 15/21] clk: google: gs101: Add support for CMU_MISC clock unit
config: nios2-allyesconfig (https://download.01.org/0day-ci/archive/20231006/202310061359.5WMm9C9Y-lkp@intel.com/config)
compiler: nios2-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20231006/202310061359.5WMm9C9Y-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202310061359.5WMm9C9Y-lkp@intel.com/
All warnings (new ones prefixed by >>):
In file included from drivers/clk/samsung/clk-gs101.c:17:
>> drivers/clk/samsung/clk-gs101.c:2087:7: warning: 'mout_misc_gic_p' defined but not used [-Wunused-const-variable=]
2087 | PNAME(mout_misc_gic_p) = { "oscclk", "dout_cmu_misc_sss" };
| ^~~~~~~~~~~~~~~
drivers/clk/samsung/clk.h:226:44: note: in definition of macro 'PNAME'
226 | #define PNAME(x) static const char * const x[] __initconst
| ^
drivers/clk/samsung/clk-gs101.c:937:7: warning: 'mout_cmu_g2d_p' defined but not used [-Wunused-const-variable=]
937 | PNAME(mout_cmu_g2d_p) = { "dout_shared0_div3", "fout_shared3_pll",
| ^~~~~~~~~~~~~~
drivers/clk/samsung/clk.h:226:44: note: in definition of macro 'PNAME'
226 | #define PNAME(x) static const char * const x[] __initconst
| ^
drivers/clk/samsung/clk-gs101.c:890:7: warning: 'mout_cmu_boost_p' defined but not used [-Wunused-const-variable=]
890 | PNAME(mout_cmu_boost_p) = { "dout_shared0_div4", "dout_shared1_div4",
| ^~~~~~~~~~~~~~~~
drivers/clk/samsung/clk.h:226:44: note: in definition of macro 'PNAME'
226 | #define PNAME(x) static const char * const x[] __initconst
| ^
drivers/clk/samsung/clk-gs101.c:811:7: warning: 'mout_cmu_pdp_vra_p' defined but not used [-Wunused-const-variable=]
811 | PNAME(mout_cmu_pdp_vra_p) = { "fout_shared2_pll", "dout_shared0_div3",
| ^~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk.h:226:44: note: in definition of macro 'PNAME'
226 | #define PNAME(x) static const char * const x[] __initconst
| ^
vim +/mout_misc_gic_p +2087 drivers/clk/samsung/clk-gs101.c
2083
2084 /* List of parent clocks for Muxes in CMU_MISC */
2085 PNAME(mout_misc_bus_user_p) = { "oscclk", "dout_cmu_misc_bus" };
2086 PNAME(mout_misc_sss_user_p) = { "oscclk", "dout_cmu_misc_sss" };
> 2087 PNAME(mout_misc_gic_p) = { "oscclk", "dout_cmu_misc_sss" };
2088
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 150+ messages in thread* Re: [PATCH 15/21] clk: google: gs101: Add support for CMU_MISC clock unit
@ 2023-10-06 5:20 ` kernel test robot
0 siblings, 0 replies; 150+ messages in thread
From: kernel test robot @ 2023-10-06 5:20 UTC (permalink / raw)
To: Peter Griffin, robh+dt, krzysztof.kozlowski+dt, mturquette,
conor+dt, sboyd, tomasz.figa, s.nawrocki, linus.walleij, wim,
linux, catalin.marinas, will, arnd, olof, cw00.choi
Cc: oe-kbuild-all, peter.griffin, tudor.ambarus, andre.draszik,
semen.protsenko, soc, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-clk, linux-gpio, linux-watchdog
Hi Peter,
kernel test robot noticed the following build warnings:
[auto build test WARNING on krzk/for-next]
[also build test WARNING on robh/for-next linus/master v6.6-rc4 next-20231005]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Peter-Griffin/dt-bindings-interrupt-controller-Add-gs101-interrupt-controller/20231005-235922
base: https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git for-next
patch link: https://lore.kernel.org/r/20231005155618.700312-16-peter.griffin%40linaro.org
patch subject: [PATCH 15/21] clk: google: gs101: Add support for CMU_MISC clock unit
config: nios2-allyesconfig (https://download.01.org/0day-ci/archive/20231006/202310061359.5WMm9C9Y-lkp@intel.com/config)
compiler: nios2-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20231006/202310061359.5WMm9C9Y-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202310061359.5WMm9C9Y-lkp@intel.com/
All warnings (new ones prefixed by >>):
In file included from drivers/clk/samsung/clk-gs101.c:17:
>> drivers/clk/samsung/clk-gs101.c:2087:7: warning: 'mout_misc_gic_p' defined but not used [-Wunused-const-variable=]
2087 | PNAME(mout_misc_gic_p) = { "oscclk", "dout_cmu_misc_sss" };
| ^~~~~~~~~~~~~~~
drivers/clk/samsung/clk.h:226:44: note: in definition of macro 'PNAME'
226 | #define PNAME(x) static const char * const x[] __initconst
| ^
drivers/clk/samsung/clk-gs101.c:937:7: warning: 'mout_cmu_g2d_p' defined but not used [-Wunused-const-variable=]
937 | PNAME(mout_cmu_g2d_p) = { "dout_shared0_div3", "fout_shared3_pll",
| ^~~~~~~~~~~~~~
drivers/clk/samsung/clk.h:226:44: note: in definition of macro 'PNAME'
226 | #define PNAME(x) static const char * const x[] __initconst
| ^
drivers/clk/samsung/clk-gs101.c:890:7: warning: 'mout_cmu_boost_p' defined but not used [-Wunused-const-variable=]
890 | PNAME(mout_cmu_boost_p) = { "dout_shared0_div4", "dout_shared1_div4",
| ^~~~~~~~~~~~~~~~
drivers/clk/samsung/clk.h:226:44: note: in definition of macro 'PNAME'
226 | #define PNAME(x) static const char * const x[] __initconst
| ^
drivers/clk/samsung/clk-gs101.c:811:7: warning: 'mout_cmu_pdp_vra_p' defined but not used [-Wunused-const-variable=]
811 | PNAME(mout_cmu_pdp_vra_p) = { "fout_shared2_pll", "dout_shared0_div3",
| ^~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk.h:226:44: note: in definition of macro 'PNAME'
226 | #define PNAME(x) static const char * const x[] __initconst
| ^
vim +/mout_misc_gic_p +2087 drivers/clk/samsung/clk-gs101.c
2083
2084 /* List of parent clocks for Muxes in CMU_MISC */
2085 PNAME(mout_misc_bus_user_p) = { "oscclk", "dout_cmu_misc_bus" };
2086 PNAME(mout_misc_sss_user_p) = { "oscclk", "dout_cmu_misc_sss" };
> 2087 PNAME(mout_misc_gic_p) = { "oscclk", "dout_cmu_misc_sss" };
2088
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 150+ messages in thread
* [PATCH 16/21] pinctrl: samsung: Add gs101 SoC pinctrl configuration
2023-10-05 15:55 ` Peter Griffin
@ 2023-10-05 15:56 ` Peter Griffin
-1 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-05 15:56 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi
Cc: peter.griffin, tudor.ambarus, andre.draszik, semen.protsenko,
soc, devicetree, linux-arm-kernel, linux-samsung-soc, linux-clk,
linux-gpio, linux-watchdog
Add support for the pin-controller found on the gs101
SoC used in Pixel 6 phones.
The alive blocks on this SoC also have a filter selection
register. Add support for this so the digital or delay filter
can be selected. If the filter selection is not available
then the default filter (digital) is applied.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
.../pinctrl/samsung/pinctrl-exynos-arm64.c | 163 ++++++++++++++++++
drivers/pinctrl/samsung/pinctrl-exynos.c | 68 +++++++-
drivers/pinctrl/samsung/pinctrl-exynos.h | 44 +++++
drivers/pinctrl/samsung/pinctrl-samsung.c | 4 +
drivers/pinctrl/samsung/pinctrl-samsung.h | 24 +++
5 files changed, 302 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
index cb965cf93705..ae681725db26 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
@@ -796,3 +796,166 @@ const struct samsung_pinctrl_of_match_data fsd_of_data __initconst = {
.ctrl = fsd_pin_ctrl,
.num_ctrl = ARRAY_SIZE(fsd_pin_ctrl),
};
+
+/*
+ * bank type for non-alive type
+ * (CON bit field: 4, DAT bit field: 1, PUD bit field: 4, DRV bit field: 4)
+ * (CONPDN bit field: 2, PUDPDN bit field: 4)
+ */
+static struct samsung_pin_bank_type bank_type_6 = {
+ .fld_width = { 4, 1, 4, 4, 2, 4, },
+ .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
+};
+
+/*
+ * bank type for alive type
+ * (CON bit field: 4, DAT bit field: 1, PUD bit field: 4, DRV bit field: 4)
+ */
+static const struct samsung_pin_bank_type bank_type_7 = {
+ .fld_width = { 4, 1, 4, 4, },
+ .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
+};
+
+/* pin banks of gs101 pin-controller (ALIVE) */
+static const struct samsung_pin_bank_data gs101_pin_alive[] = {
+ EXYNOS9_PIN_BANK_EINTW(bank_type_7, 8, 0x0, "gpa0", 0x00, 0x00, FLT_SELECTABLE),
+ EXYNOS9_PIN_BANK_EINTW(bank_type_7, 7, 0x20, "gpa1", 0x04, 0x08, FLT_SELECTABLE),
+ EXYNOS9_PIN_BANK_EINTW(bank_type_7, 5, 0x40, "gpa2", 0x08, 0x10, FLT_SELECTABLE),
+ EXYNOS9_PIN_BANK_EINTW(bank_type_7, 4, 0x60, "gpa3", 0x0c, 0x18, FLT_SELECTABLE),
+ EXYNOS9_PIN_BANK_EINTW(bank_type_7, 4, 0x80, "gpa4", 0x10, 0x1c, FLT_SELECTABLE),
+ EXYNOS9_PIN_BANK_EINTW(bank_type_7, 7, 0xa0, "gpa5", 0x14, 0x20, FLT_SELECTABLE),
+ EXYNOS9_PIN_BANK_EINTW(bank_type_7, 8, 0xc0, "gpa9", 0x18, 0x28, FLT_SELECTABLE),
+ EXYNOS9_PIN_BANK_EINTW(bank_type_7, 2, 0xe0, "gpa10", 0x1c, 0x30, FLT_SELECTABLE),
+};
+
+/* pin banks of gs101 pin-controller (FAR_ALIVE) */
+static const struct samsung_pin_bank_data gs101_pin_far_alive[] = {
+ EXYNOS9_PIN_BANK_EINTW(bank_type_7, 8, 0x0, "gpa6", 0x00, 0x00, FLT_SELECTABLE),
+ EXYNOS9_PIN_BANK_EINTW(bank_type_7, 4, 0x20, "gpa7", 0x04, 0x08, FLT_SELECTABLE),
+ EXYNOS9_PIN_BANK_EINTW(bank_type_7, 8, 0x40, "gpa8", 0x08, 0x0c, FLT_SELECTABLE),
+ EXYNOS9_PIN_BANK_EINTW(bank_type_7, 2, 0x60, "gpa11", 0x0c, 0x14, FLT_SELECTABLE),
+};
+
+/* pin banks of gs101 pin-controller (GSACORE) */
+static const struct samsung_pin_bank_data gs101_pin_gsacore[] = {
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x0, "gps0", 0x00, 0x00, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 8, 0x20, "gps1", 0x04, 0x04, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 3, 0x40, "gps2", 0x08, 0x0c, FLT_DEFAULT),
+};
+
+/* pin banks of gs101 pin-controller (GSACTRL) */
+static const struct samsung_pin_bank_data gs101_pin_gsactrl[] = {
+ EXYNOS9_PIN_BANK_EINTW(bank_type_7, 6, 0x0, "gps3", 0x00, 0x00, FLT_DEFAULT),
+};
+
+/* pin banks of gs101 pin-controller (PERIC0) */
+static const struct samsung_pin_bank_data gs101_pin_peric0[] = {
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 5, 0x0, "gpp0", 0x00, 0x00, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x20, "gpp1", 0x04, 0x08, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x40, "gpp2", 0x08, 0x0c, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x60, "gpp3", 0x0c, 0x10, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x80, "gpp4", 0x10, 0x14, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0xa0, "gpp5", 0x14, 0x18, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0xc0, "gpp6", 0x18, 0x1c, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0xe0, "gpp7", 0x1c, 0x20, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x100, "gpp8", 0x20, 0x24, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x120, "gpp9", 0x24, 0x28, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x140, "gpp10", 0x28, 0x2c, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x160, "gpp11", 0x2c, 0x30, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x180, "gpp12", 0x30, 0x34, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x1a0, "gpp13", 0x34, 0x38, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x1c0, "gpp14", 0x38, 0x3c, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x1e0, "gpp15", 0x3c, 0x40, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x200, "gpp16", 0x40, 0x44, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x220, "gpp17", 0x44, 0x48, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x240, "gpp18", 0x48, 0x4c, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x260, "gpp19", 0x4c, 0x50, FLT_DEFAULT),
+};
+
+/* pin banks of gs101 pin-controller (PERIC1) */
+static const struct samsung_pin_bank_data gs101_pin_peric1[] = {
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 8, 0x0, "gpp20", 0x00, 0x00, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x20, "gpp21", 0x04, 0x08, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x40, "gpp22", 0x08, 0x0c, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 8, 0x60, "gpp23", 0x0c, 0x10, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x80, "gpp24", 0x10, 0x18, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0xa0, "gpp25", 0x14, 0x1c, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 5, 0xc0, "gpp26", 0x18, 0x20, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0xe0, "gpp27", 0x1c, 0x28, FLT_DEFAULT),
+};
+
+/* pin banks of gs101 pin-controller (HSI1) */
+static const struct samsung_pin_bank_data gs101_pin_hsi1[] = {
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 6, 0x0, "gph0", 0x00, 0x00, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 7, 0x20, "gph1", 0x04, 0x08, FLT_DEFAULT),
+};
+
+/* pin banks of gs101 pin-controller (HSI2) */
+static const struct samsung_pin_bank_data gs101_pin_hsi2[] = {
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 6, 0x0, "gph2", 0x00, 0x00, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x20, "gph3", 0x04, 0x08, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 6, 0x40, "gph4", 0x08, 0x0c, FLT_DEFAULT),
+};
+
+static const struct samsung_pin_ctrl gs101_pin_ctrl[] __initconst = {
+ {
+ /* pin banks of gs101 pin-controller (ALIVE) */
+ .pin_banks = gs101_pin_alive,
+ .nr_banks = ARRAY_SIZE(gs101_pin_alive),
+ .eint_gpio_init = exynos_eint_gpio_init,
+ .eint_wkup_init = exynos_eint_wkup_init,
+ .suspend = exynos_pinctrl_suspend,
+ .resume = exynos_pinctrl_resume,
+ }, {
+ /* pin banks of gs101 pin-controller (FAR_ALIVE) */
+ .pin_banks = gs101_pin_far_alive,
+ .nr_banks = ARRAY_SIZE(gs101_pin_far_alive),
+ .eint_gpio_init = exynos_eint_gpio_init,
+ .eint_wkup_init = exynos_eint_wkup_init,
+ .suspend = exynos_pinctrl_suspend,
+ .resume = exynos_pinctrl_resume,
+ }, {
+ /* pin banks of gs101 pin-controller (GSACORE) */
+ .pin_banks = gs101_pin_gsacore,
+ .nr_banks = ARRAY_SIZE(gs101_pin_gsacore),
+ .eint_gpio_init = exynos_eint_gpio_init,
+ }, {
+ /* pin banks of gs101 pin-controller (GSACTRL) */
+ .pin_banks = gs101_pin_gsactrl,
+ .nr_banks = ARRAY_SIZE(gs101_pin_gsactrl),
+ .eint_gpio_init = exynos_eint_gpio_init,
+ }, {
+ /* pin banks of gs101 pin-controller (PERIC0) */
+ .pin_banks = gs101_pin_peric0,
+ .nr_banks = ARRAY_SIZE(gs101_pin_peric0),
+ .eint_gpio_init = exynos_eint_gpio_init,
+ .suspend = exynos_pinctrl_suspend,
+ .resume = exynos_pinctrl_resume,
+ }, {
+ /* pin banks of gs101 pin-controller (PERIC1) */
+ .pin_banks = gs101_pin_peric1,
+ .nr_banks = ARRAY_SIZE(gs101_pin_peric1),
+ .eint_gpio_init = exynos_eint_gpio_init,
+ .suspend = exynos_pinctrl_suspend,
+ .resume = exynos_pinctrl_resume,
+ }, {
+ /* pin banks of gs101 pin-controller (HSI1) */
+ .pin_banks = gs101_pin_hsi1,
+ .nr_banks = ARRAY_SIZE(gs101_pin_hsi1),
+ .eint_gpio_init = exynos_eint_gpio_init,
+ .suspend = exynos_pinctrl_suspend,
+ .resume = exynos_pinctrl_resume,
+ }, {
+ /* pin banks of gs101 pin-controller (HSI2) */
+ .pin_banks = gs101_pin_hsi2,
+ .nr_banks = ARRAY_SIZE(gs101_pin_hsi2),
+ .eint_gpio_init = exynos_eint_gpio_init,
+ .suspend = exynos_pinctrl_suspend,
+ .resume = exynos_pinctrl_resume,
+ },
+};
+
+const struct samsung_pinctrl_of_match_data gs101_of_data __initconst = {
+ .ctrl = gs101_pin_ctrl,
+ .num_ctrl = ARRAY_SIZE(gs101_pin_ctrl),
+};
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
index a8212fc126bf..0c6c3312abb7 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -269,6 +269,50 @@ struct exynos_eint_gpio_save {
u32 eint_mask;
};
+static void exynos_eint_flt_config(int sel, int width,
+ struct samsung_pinctrl_drv_data *d,
+ struct samsung_pin_bank *bank)
+{
+ unsigned int flt_reg, flt_con = 0;
+ unsigned int val, shift;
+ int i;
+ int loop_cnt;
+
+ flt_con |= EXYNOS_FLTCON_EN;
+
+ if (sel)
+ flt_con |= EXYNOS_FLTCON_SEL_DIGITAL;
+
+ flt_con |= EXYNOS_FLTCON_WIDTH(width);
+
+ flt_reg = EXYNOS_GPIO_EFLTCON_OFFSET + bank->fltcon_offset;
+
+ if (bank->nr_pins > EXYNOS_FLTCON_NR_PIN)
+ /*
+ * if nr_pins > 4, we should set FLTCON0 register fully.
+ * (pin0 ~ 3). So loop 4 times in case of FLTCON0.
+ */
+ loop_cnt = 4;
+ else
+ loop_cnt = bank->nr_pins;
+
+ val = readl(d->virt_base + flt_reg);
+
+ for (i = 0; i < loop_cnt; i++) {
+ shift = i * EXYNOS_FLTCON_LEN;
+ val &= ~(EXYNOS_FLTCON_MASK << shift);
+ val |= (flt_con << shift);
+ }
+
+ writel(val, d->virt_base + flt_reg);
+
+ /* if nr_pins > 4, we should also set FLTCON1 register like FLTCON0.
+ * (pin4 ~ )
+ */
+ if (bank->nr_pins > EXYNOS_FLTCON_NR_PIN)
+ writel(val, d->virt_base + flt_reg + 0x4);
+}
+
/*
* exynos_eint_gpio_init() - setup handling of external gpio interrupts.
* @d: driver data of samsung pinctrl driver.
@@ -321,6 +365,10 @@ __init int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
goto err_domains;
}
+ /* Set Delay Analog Filter */
+ if (bank->fltcon_type != FLT_DEFAULT)
+ exynos_eint_flt_config(EXYNOS_FLTCON_SEL_DELAY,
+ 0, d, bank);
}
return 0;
@@ -555,6 +603,11 @@ __init int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
if (bank->eint_type != EINT_TYPE_WKUP)
continue;
+ /* Set Digital Filter */
+ if (bank->fltcon_type != FLT_DEFAULT)
+ exynos_eint_flt_config(EXYNOS_FLTCON_SEL_DIGITAL,
+ 0, d, bank);
+
bank->irq_chip = devm_kmemdup(dev, irq_chip, sizeof(*irq_chip),
GFP_KERNEL);
if (!bank->irq_chip) {
@@ -658,6 +711,7 @@ static void exynos_pinctrl_suspend_bank(
void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata)
{
struct samsung_pin_bank *bank = drvdata->pin_banks;
+ struct samsung_pinctrl_drv_data *d = bank->drvdata;
struct exynos_irq_chip *irq_chip = NULL;
int i;
@@ -665,6 +719,10 @@ void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata)
if (bank->eint_type == EINT_TYPE_GPIO)
exynos_pinctrl_suspend_bank(drvdata, bank);
else if (bank->eint_type == EINT_TYPE_WKUP) {
+ /* Setting Delay (Analog) Filter */
+ if (bank->fltcon_type != FLT_DEFAULT)
+ exynos_eint_flt_config(EXYNOS_FLTCON_SEL_DELAY,
+ 0, d, bank);
if (!irq_chip) {
irq_chip = bank->irq_chip;
irq_chip->set_eint_wakeup_mask(drvdata,
@@ -707,11 +765,19 @@ static void exynos_pinctrl_resume_bank(
void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata)
{
struct samsung_pin_bank *bank = drvdata->pin_banks;
+ struct samsung_pinctrl_drv_data *d = bank->drvdata;
int i;
for (i = 0; i < drvdata->nr_banks; ++i, ++bank)
- if (bank->eint_type == EINT_TYPE_GPIO)
+ if (bank->eint_type == EINT_TYPE_GPIO) {
exynos_pinctrl_resume_bank(drvdata, bank);
+ } else if (bank->eint_type == EINT_TYPE_WKUP ||
+ bank->eint_type == EINT_TYPE_WKUP_MUX) {
+ /* Set Digital Filter */
+ if (bank->fltcon_type != FLT_DEFAULT)
+ exynos_eint_flt_config(EXYNOS_FLTCON_SEL_DIGITAL,
+ 0, d, bank);
+ }
}
static void exynos_retention_enable(struct samsung_pinctrl_drv_data *drvdata)
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h
index 7bd6d82c9f36..aafd8f9f52f8 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.h
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.h
@@ -16,6 +16,8 @@
#ifndef __PINCTRL_SAMSUNG_EXYNOS_H
#define __PINCTRL_SAMSUNG_EXYNOS_H
+#include <linux/bitfield.h>
+
/* Values for the pin CON register */
#define EXYNOS_PIN_CON_FUNC_EINT 0xf
@@ -50,6 +52,14 @@
#define EXYNOS_EINT_MAX_PER_BANK 8
#define EXYNOS_EINT_NR_WKUP_EINT
+/* EINT filter configuration */
+#define EXYNOS_FLTCON_EN BIT(7)
+#define EXYNOS_FLTCON_SEL_DIGITAL BIT(6)
+#define EXYNOS_FLTCON_SEL_DELAY 0
+#define EXYNOS_FLTCON_WIDTH(x) ((x) & 0x3f)
+#define EXYNOS_FLTCON_MASK 0xFF
+#define EXYNOS_FLTCON_LEN 8
+#define EXYNOS_FLTCON_NR_PIN 4
#define EXYNOS_PIN_BANK_EINTN(pins, reg, id) \
{ \
@@ -140,6 +150,40 @@
.name = id \
}
+#define EXYNOS9_PIN_BANK_EINTN(types, pins, reg, id) \
+ { \
+ .type = &types, \
+ .pctl_offset = reg, \
+ .nr_pins = pins, \
+ .eint_type = EINT_TYPE_NONE, \
+ .fltcon_type = FLT_DEFAULT \
+ .name = id \
+ }
+
+#define EXYNOS9_PIN_BANK_EINTG(types, pins, reg, id, offs, fltcon_offs, fltcontype) \
+ { \
+ .type = &types, \
+ .pctl_offset = reg, \
+ .nr_pins = pins, \
+ .eint_type = EINT_TYPE_GPIO, \
+ .eint_offset = offs, \
+ .fltcon_type = fltcontype, \
+ .fltcon_offset = fltcon_offs, \
+ .name = id \
+ }
+
+#define EXYNOS9_PIN_BANK_EINTW(types, pins, reg, id, offs, fltcon_offs, fltcontype) \
+ { \
+ .type = &types, \
+ .pctl_offset = reg, \
+ .nr_pins = pins, \
+ .eint_type = EINT_TYPE_WKUP, \
+ .eint_offset = offs, \
+ .fltcon_type = fltcontype, \
+ .fltcon_offset = fltcon_offs, \
+ .name = id \
+ }
+
/**
* struct exynos_weint_data: irq specific data for all the wakeup interrupts
* generated by the external wakeup interrupt controller.
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c
index e54847040b4a..12176f98440d 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.c
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.c
@@ -1104,6 +1104,8 @@ samsung_pinctrl_get_soc_data(struct samsung_pinctrl_drv_data *d,
bank->eint_func = bdata->eint_func;
bank->eint_type = bdata->eint_type;
bank->eint_mask = bdata->eint_mask;
+ bank->fltcon_type = bdata->fltcon_type;
+ bank->fltcon_offset = bdata->fltcon_offset;
bank->eint_offset = bdata->eint_offset;
bank->name = bdata->name;
@@ -1319,6 +1321,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
.data = &exynosautov9_of_data },
{ .compatible = "tesla,fsd-pinctrl",
.data = &fsd_of_data },
+ { .compatible = "google,gs101-pinctrl",
+ .data = &gs101_of_data },
#endif
#ifdef CONFIG_PINCTRL_S3C64XX
{ .compatible = "samsung,s3c64xx-pinctrl",
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h
index 9af93e3d8d9f..e62e909fb10d 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.h
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.h
@@ -82,6 +82,21 @@ enum eint_type {
EINT_TYPE_WKUP_MUX,
};
+/**
+ * enum fltcon_type - filter selection
+ * @FLT_DEFAULT: filter not selectable, default digital filter
+ * @FLT_SELECT: filter selectable (digital or delay)
+ *
+ * Some banks on some SoCs (gs101 and possibly others) have a selectable
+ * filter on alive banks of 'delay/analog' or 'digital'. If the filter
+ * selection is not available then the default filter is used (digital).
+ */
+
+enum fltcon_type {
+ FLT_DEFAULT,
+ FLT_SELECTABLE,
+};
+
/* maximum length of a pin in pin descriptor (example: "gpa0-0") */
#define PIN_NAME_LENGTH 10
@@ -122,6 +137,8 @@ struct samsung_pin_bank_type {
* @eint_type: type of the external interrupt supported by the bank.
* @eint_mask: bit mask of pins which support EINT function.
* @eint_offset: SoC-specific EINT register or interrupt offset of bank.
+ * @fltcon_type: whether the filter (delay/digital) is selectable
+ * @fltcon_offset: SoC-specific EINT filter control register offset of bank.
* @name: name to be prefixed for each pin in this pin bank.
*/
struct samsung_pin_bank_data {
@@ -133,6 +150,8 @@ struct samsung_pin_bank_data {
enum eint_type eint_type;
u32 eint_mask;
u32 eint_offset;
+ enum fltcon_type fltcon_type;
+ u32 fltcon_offset;
const char *name;
};
@@ -147,6 +166,8 @@ struct samsung_pin_bank_data {
* @eint_type: type of the external interrupt supported by the bank.
* @eint_mask: bit mask of pins which support EINT function.
* @eint_offset: SoC-specific EINT register or interrupt offset of bank.
+ * @fltcon_type: whether the filter (delay/digital) is selectable
+ * @fltcon_offset: SoC-specific EINT filter control register offset of bank.
* @name: name to be prefixed for each pin in this pin bank.
* @pin_base: starting pin number of the bank.
* @soc_priv: per-bank private data for SoC-specific code.
@@ -169,6 +190,8 @@ struct samsung_pin_bank {
enum eint_type eint_type;
u32 eint_mask;
u32 eint_offset;
+ enum fltcon_type fltcon_type;
+ u32 fltcon_offset;
const char *name;
u32 pin_base;
@@ -351,6 +374,7 @@ extern const struct samsung_pinctrl_of_match_data exynos7885_of_data;
extern const struct samsung_pinctrl_of_match_data exynos850_of_data;
extern const struct samsung_pinctrl_of_match_data exynosautov9_of_data;
extern const struct samsung_pinctrl_of_match_data fsd_of_data;
+extern const struct samsung_pinctrl_of_match_data gs101_of_data;
extern const struct samsung_pinctrl_of_match_data s3c64xx_of_data;
extern const struct samsung_pinctrl_of_match_data s3c2412_of_data;
extern const struct samsung_pinctrl_of_match_data s3c2416_of_data;
--
2.42.0.582.g8ccd20d70d-goog
^ permalink raw reply related [flat|nested] 150+ messages in thread* [PATCH 16/21] pinctrl: samsung: Add gs101 SoC pinctrl configuration
@ 2023-10-05 15:56 ` Peter Griffin
0 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-05 15:56 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi
Cc: peter.griffin, tudor.ambarus, andre.draszik, semen.protsenko,
soc, devicetree, linux-arm-kernel, linux-samsung-soc, linux-clk,
linux-gpio, linux-watchdog
Add support for the pin-controller found on the gs101
SoC used in Pixel 6 phones.
The alive blocks on this SoC also have a filter selection
register. Add support for this so the digital or delay filter
can be selected. If the filter selection is not available
then the default filter (digital) is applied.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
.../pinctrl/samsung/pinctrl-exynos-arm64.c | 163 ++++++++++++++++++
drivers/pinctrl/samsung/pinctrl-exynos.c | 68 +++++++-
drivers/pinctrl/samsung/pinctrl-exynos.h | 44 +++++
drivers/pinctrl/samsung/pinctrl-samsung.c | 4 +
drivers/pinctrl/samsung/pinctrl-samsung.h | 24 +++
5 files changed, 302 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
index cb965cf93705..ae681725db26 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
@@ -796,3 +796,166 @@ const struct samsung_pinctrl_of_match_data fsd_of_data __initconst = {
.ctrl = fsd_pin_ctrl,
.num_ctrl = ARRAY_SIZE(fsd_pin_ctrl),
};
+
+/*
+ * bank type for non-alive type
+ * (CON bit field: 4, DAT bit field: 1, PUD bit field: 4, DRV bit field: 4)
+ * (CONPDN bit field: 2, PUDPDN bit field: 4)
+ */
+static struct samsung_pin_bank_type bank_type_6 = {
+ .fld_width = { 4, 1, 4, 4, 2, 4, },
+ .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
+};
+
+/*
+ * bank type for alive type
+ * (CON bit field: 4, DAT bit field: 1, PUD bit field: 4, DRV bit field: 4)
+ */
+static const struct samsung_pin_bank_type bank_type_7 = {
+ .fld_width = { 4, 1, 4, 4, },
+ .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
+};
+
+/* pin banks of gs101 pin-controller (ALIVE) */
+static const struct samsung_pin_bank_data gs101_pin_alive[] = {
+ EXYNOS9_PIN_BANK_EINTW(bank_type_7, 8, 0x0, "gpa0", 0x00, 0x00, FLT_SELECTABLE),
+ EXYNOS9_PIN_BANK_EINTW(bank_type_7, 7, 0x20, "gpa1", 0x04, 0x08, FLT_SELECTABLE),
+ EXYNOS9_PIN_BANK_EINTW(bank_type_7, 5, 0x40, "gpa2", 0x08, 0x10, FLT_SELECTABLE),
+ EXYNOS9_PIN_BANK_EINTW(bank_type_7, 4, 0x60, "gpa3", 0x0c, 0x18, FLT_SELECTABLE),
+ EXYNOS9_PIN_BANK_EINTW(bank_type_7, 4, 0x80, "gpa4", 0x10, 0x1c, FLT_SELECTABLE),
+ EXYNOS9_PIN_BANK_EINTW(bank_type_7, 7, 0xa0, "gpa5", 0x14, 0x20, FLT_SELECTABLE),
+ EXYNOS9_PIN_BANK_EINTW(bank_type_7, 8, 0xc0, "gpa9", 0x18, 0x28, FLT_SELECTABLE),
+ EXYNOS9_PIN_BANK_EINTW(bank_type_7, 2, 0xe0, "gpa10", 0x1c, 0x30, FLT_SELECTABLE),
+};
+
+/* pin banks of gs101 pin-controller (FAR_ALIVE) */
+static const struct samsung_pin_bank_data gs101_pin_far_alive[] = {
+ EXYNOS9_PIN_BANK_EINTW(bank_type_7, 8, 0x0, "gpa6", 0x00, 0x00, FLT_SELECTABLE),
+ EXYNOS9_PIN_BANK_EINTW(bank_type_7, 4, 0x20, "gpa7", 0x04, 0x08, FLT_SELECTABLE),
+ EXYNOS9_PIN_BANK_EINTW(bank_type_7, 8, 0x40, "gpa8", 0x08, 0x0c, FLT_SELECTABLE),
+ EXYNOS9_PIN_BANK_EINTW(bank_type_7, 2, 0x60, "gpa11", 0x0c, 0x14, FLT_SELECTABLE),
+};
+
+/* pin banks of gs101 pin-controller (GSACORE) */
+static const struct samsung_pin_bank_data gs101_pin_gsacore[] = {
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x0, "gps0", 0x00, 0x00, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 8, 0x20, "gps1", 0x04, 0x04, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 3, 0x40, "gps2", 0x08, 0x0c, FLT_DEFAULT),
+};
+
+/* pin banks of gs101 pin-controller (GSACTRL) */
+static const struct samsung_pin_bank_data gs101_pin_gsactrl[] = {
+ EXYNOS9_PIN_BANK_EINTW(bank_type_7, 6, 0x0, "gps3", 0x00, 0x00, FLT_DEFAULT),
+};
+
+/* pin banks of gs101 pin-controller (PERIC0) */
+static const struct samsung_pin_bank_data gs101_pin_peric0[] = {
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 5, 0x0, "gpp0", 0x00, 0x00, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x20, "gpp1", 0x04, 0x08, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x40, "gpp2", 0x08, 0x0c, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x60, "gpp3", 0x0c, 0x10, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x80, "gpp4", 0x10, 0x14, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0xa0, "gpp5", 0x14, 0x18, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0xc0, "gpp6", 0x18, 0x1c, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0xe0, "gpp7", 0x1c, 0x20, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x100, "gpp8", 0x20, 0x24, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x120, "gpp9", 0x24, 0x28, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x140, "gpp10", 0x28, 0x2c, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x160, "gpp11", 0x2c, 0x30, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x180, "gpp12", 0x30, 0x34, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x1a0, "gpp13", 0x34, 0x38, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x1c0, "gpp14", 0x38, 0x3c, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x1e0, "gpp15", 0x3c, 0x40, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x200, "gpp16", 0x40, 0x44, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x220, "gpp17", 0x44, 0x48, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x240, "gpp18", 0x48, 0x4c, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x260, "gpp19", 0x4c, 0x50, FLT_DEFAULT),
+};
+
+/* pin banks of gs101 pin-controller (PERIC1) */
+static const struct samsung_pin_bank_data gs101_pin_peric1[] = {
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 8, 0x0, "gpp20", 0x00, 0x00, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x20, "gpp21", 0x04, 0x08, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x40, "gpp22", 0x08, 0x0c, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 8, 0x60, "gpp23", 0x0c, 0x10, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x80, "gpp24", 0x10, 0x18, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0xa0, "gpp25", 0x14, 0x1c, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 5, 0xc0, "gpp26", 0x18, 0x20, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0xe0, "gpp27", 0x1c, 0x28, FLT_DEFAULT),
+};
+
+/* pin banks of gs101 pin-controller (HSI1) */
+static const struct samsung_pin_bank_data gs101_pin_hsi1[] = {
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 6, 0x0, "gph0", 0x00, 0x00, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 7, 0x20, "gph1", 0x04, 0x08, FLT_DEFAULT),
+};
+
+/* pin banks of gs101 pin-controller (HSI2) */
+static const struct samsung_pin_bank_data gs101_pin_hsi2[] = {
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 6, 0x0, "gph2", 0x00, 0x00, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x20, "gph3", 0x04, 0x08, FLT_DEFAULT),
+ EXYNOS9_PIN_BANK_EINTG(bank_type_6, 6, 0x40, "gph4", 0x08, 0x0c, FLT_DEFAULT),
+};
+
+static const struct samsung_pin_ctrl gs101_pin_ctrl[] __initconst = {
+ {
+ /* pin banks of gs101 pin-controller (ALIVE) */
+ .pin_banks = gs101_pin_alive,
+ .nr_banks = ARRAY_SIZE(gs101_pin_alive),
+ .eint_gpio_init = exynos_eint_gpio_init,
+ .eint_wkup_init = exynos_eint_wkup_init,
+ .suspend = exynos_pinctrl_suspend,
+ .resume = exynos_pinctrl_resume,
+ }, {
+ /* pin banks of gs101 pin-controller (FAR_ALIVE) */
+ .pin_banks = gs101_pin_far_alive,
+ .nr_banks = ARRAY_SIZE(gs101_pin_far_alive),
+ .eint_gpio_init = exynos_eint_gpio_init,
+ .eint_wkup_init = exynos_eint_wkup_init,
+ .suspend = exynos_pinctrl_suspend,
+ .resume = exynos_pinctrl_resume,
+ }, {
+ /* pin banks of gs101 pin-controller (GSACORE) */
+ .pin_banks = gs101_pin_gsacore,
+ .nr_banks = ARRAY_SIZE(gs101_pin_gsacore),
+ .eint_gpio_init = exynos_eint_gpio_init,
+ }, {
+ /* pin banks of gs101 pin-controller (GSACTRL) */
+ .pin_banks = gs101_pin_gsactrl,
+ .nr_banks = ARRAY_SIZE(gs101_pin_gsactrl),
+ .eint_gpio_init = exynos_eint_gpio_init,
+ }, {
+ /* pin banks of gs101 pin-controller (PERIC0) */
+ .pin_banks = gs101_pin_peric0,
+ .nr_banks = ARRAY_SIZE(gs101_pin_peric0),
+ .eint_gpio_init = exynos_eint_gpio_init,
+ .suspend = exynos_pinctrl_suspend,
+ .resume = exynos_pinctrl_resume,
+ }, {
+ /* pin banks of gs101 pin-controller (PERIC1) */
+ .pin_banks = gs101_pin_peric1,
+ .nr_banks = ARRAY_SIZE(gs101_pin_peric1),
+ .eint_gpio_init = exynos_eint_gpio_init,
+ .suspend = exynos_pinctrl_suspend,
+ .resume = exynos_pinctrl_resume,
+ }, {
+ /* pin banks of gs101 pin-controller (HSI1) */
+ .pin_banks = gs101_pin_hsi1,
+ .nr_banks = ARRAY_SIZE(gs101_pin_hsi1),
+ .eint_gpio_init = exynos_eint_gpio_init,
+ .suspend = exynos_pinctrl_suspend,
+ .resume = exynos_pinctrl_resume,
+ }, {
+ /* pin banks of gs101 pin-controller (HSI2) */
+ .pin_banks = gs101_pin_hsi2,
+ .nr_banks = ARRAY_SIZE(gs101_pin_hsi2),
+ .eint_gpio_init = exynos_eint_gpio_init,
+ .suspend = exynos_pinctrl_suspend,
+ .resume = exynos_pinctrl_resume,
+ },
+};
+
+const struct samsung_pinctrl_of_match_data gs101_of_data __initconst = {
+ .ctrl = gs101_pin_ctrl,
+ .num_ctrl = ARRAY_SIZE(gs101_pin_ctrl),
+};
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
index a8212fc126bf..0c6c3312abb7 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -269,6 +269,50 @@ struct exynos_eint_gpio_save {
u32 eint_mask;
};
+static void exynos_eint_flt_config(int sel, int width,
+ struct samsung_pinctrl_drv_data *d,
+ struct samsung_pin_bank *bank)
+{
+ unsigned int flt_reg, flt_con = 0;
+ unsigned int val, shift;
+ int i;
+ int loop_cnt;
+
+ flt_con |= EXYNOS_FLTCON_EN;
+
+ if (sel)
+ flt_con |= EXYNOS_FLTCON_SEL_DIGITAL;
+
+ flt_con |= EXYNOS_FLTCON_WIDTH(width);
+
+ flt_reg = EXYNOS_GPIO_EFLTCON_OFFSET + bank->fltcon_offset;
+
+ if (bank->nr_pins > EXYNOS_FLTCON_NR_PIN)
+ /*
+ * if nr_pins > 4, we should set FLTCON0 register fully.
+ * (pin0 ~ 3). So loop 4 times in case of FLTCON0.
+ */
+ loop_cnt = 4;
+ else
+ loop_cnt = bank->nr_pins;
+
+ val = readl(d->virt_base + flt_reg);
+
+ for (i = 0; i < loop_cnt; i++) {
+ shift = i * EXYNOS_FLTCON_LEN;
+ val &= ~(EXYNOS_FLTCON_MASK << shift);
+ val |= (flt_con << shift);
+ }
+
+ writel(val, d->virt_base + flt_reg);
+
+ /* if nr_pins > 4, we should also set FLTCON1 register like FLTCON0.
+ * (pin4 ~ )
+ */
+ if (bank->nr_pins > EXYNOS_FLTCON_NR_PIN)
+ writel(val, d->virt_base + flt_reg + 0x4);
+}
+
/*
* exynos_eint_gpio_init() - setup handling of external gpio interrupts.
* @d: driver data of samsung pinctrl driver.
@@ -321,6 +365,10 @@ __init int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
goto err_domains;
}
+ /* Set Delay Analog Filter */
+ if (bank->fltcon_type != FLT_DEFAULT)
+ exynos_eint_flt_config(EXYNOS_FLTCON_SEL_DELAY,
+ 0, d, bank);
}
return 0;
@@ -555,6 +603,11 @@ __init int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
if (bank->eint_type != EINT_TYPE_WKUP)
continue;
+ /* Set Digital Filter */
+ if (bank->fltcon_type != FLT_DEFAULT)
+ exynos_eint_flt_config(EXYNOS_FLTCON_SEL_DIGITAL,
+ 0, d, bank);
+
bank->irq_chip = devm_kmemdup(dev, irq_chip, sizeof(*irq_chip),
GFP_KERNEL);
if (!bank->irq_chip) {
@@ -658,6 +711,7 @@ static void exynos_pinctrl_suspend_bank(
void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata)
{
struct samsung_pin_bank *bank = drvdata->pin_banks;
+ struct samsung_pinctrl_drv_data *d = bank->drvdata;
struct exynos_irq_chip *irq_chip = NULL;
int i;
@@ -665,6 +719,10 @@ void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata)
if (bank->eint_type == EINT_TYPE_GPIO)
exynos_pinctrl_suspend_bank(drvdata, bank);
else if (bank->eint_type == EINT_TYPE_WKUP) {
+ /* Setting Delay (Analog) Filter */
+ if (bank->fltcon_type != FLT_DEFAULT)
+ exynos_eint_flt_config(EXYNOS_FLTCON_SEL_DELAY,
+ 0, d, bank);
if (!irq_chip) {
irq_chip = bank->irq_chip;
irq_chip->set_eint_wakeup_mask(drvdata,
@@ -707,11 +765,19 @@ static void exynos_pinctrl_resume_bank(
void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata)
{
struct samsung_pin_bank *bank = drvdata->pin_banks;
+ struct samsung_pinctrl_drv_data *d = bank->drvdata;
int i;
for (i = 0; i < drvdata->nr_banks; ++i, ++bank)
- if (bank->eint_type == EINT_TYPE_GPIO)
+ if (bank->eint_type == EINT_TYPE_GPIO) {
exynos_pinctrl_resume_bank(drvdata, bank);
+ } else if (bank->eint_type == EINT_TYPE_WKUP ||
+ bank->eint_type == EINT_TYPE_WKUP_MUX) {
+ /* Set Digital Filter */
+ if (bank->fltcon_type != FLT_DEFAULT)
+ exynos_eint_flt_config(EXYNOS_FLTCON_SEL_DIGITAL,
+ 0, d, bank);
+ }
}
static void exynos_retention_enable(struct samsung_pinctrl_drv_data *drvdata)
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h
index 7bd6d82c9f36..aafd8f9f52f8 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.h
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.h
@@ -16,6 +16,8 @@
#ifndef __PINCTRL_SAMSUNG_EXYNOS_H
#define __PINCTRL_SAMSUNG_EXYNOS_H
+#include <linux/bitfield.h>
+
/* Values for the pin CON register */
#define EXYNOS_PIN_CON_FUNC_EINT 0xf
@@ -50,6 +52,14 @@
#define EXYNOS_EINT_MAX_PER_BANK 8
#define EXYNOS_EINT_NR_WKUP_EINT
+/* EINT filter configuration */
+#define EXYNOS_FLTCON_EN BIT(7)
+#define EXYNOS_FLTCON_SEL_DIGITAL BIT(6)
+#define EXYNOS_FLTCON_SEL_DELAY 0
+#define EXYNOS_FLTCON_WIDTH(x) ((x) & 0x3f)
+#define EXYNOS_FLTCON_MASK 0xFF
+#define EXYNOS_FLTCON_LEN 8
+#define EXYNOS_FLTCON_NR_PIN 4
#define EXYNOS_PIN_BANK_EINTN(pins, reg, id) \
{ \
@@ -140,6 +150,40 @@
.name = id \
}
+#define EXYNOS9_PIN_BANK_EINTN(types, pins, reg, id) \
+ { \
+ .type = &types, \
+ .pctl_offset = reg, \
+ .nr_pins = pins, \
+ .eint_type = EINT_TYPE_NONE, \
+ .fltcon_type = FLT_DEFAULT \
+ .name = id \
+ }
+
+#define EXYNOS9_PIN_BANK_EINTG(types, pins, reg, id, offs, fltcon_offs, fltcontype) \
+ { \
+ .type = &types, \
+ .pctl_offset = reg, \
+ .nr_pins = pins, \
+ .eint_type = EINT_TYPE_GPIO, \
+ .eint_offset = offs, \
+ .fltcon_type = fltcontype, \
+ .fltcon_offset = fltcon_offs, \
+ .name = id \
+ }
+
+#define EXYNOS9_PIN_BANK_EINTW(types, pins, reg, id, offs, fltcon_offs, fltcontype) \
+ { \
+ .type = &types, \
+ .pctl_offset = reg, \
+ .nr_pins = pins, \
+ .eint_type = EINT_TYPE_WKUP, \
+ .eint_offset = offs, \
+ .fltcon_type = fltcontype, \
+ .fltcon_offset = fltcon_offs, \
+ .name = id \
+ }
+
/**
* struct exynos_weint_data: irq specific data for all the wakeup interrupts
* generated by the external wakeup interrupt controller.
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c
index e54847040b4a..12176f98440d 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.c
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.c
@@ -1104,6 +1104,8 @@ samsung_pinctrl_get_soc_data(struct samsung_pinctrl_drv_data *d,
bank->eint_func = bdata->eint_func;
bank->eint_type = bdata->eint_type;
bank->eint_mask = bdata->eint_mask;
+ bank->fltcon_type = bdata->fltcon_type;
+ bank->fltcon_offset = bdata->fltcon_offset;
bank->eint_offset = bdata->eint_offset;
bank->name = bdata->name;
@@ -1319,6 +1321,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
.data = &exynosautov9_of_data },
{ .compatible = "tesla,fsd-pinctrl",
.data = &fsd_of_data },
+ { .compatible = "google,gs101-pinctrl",
+ .data = &gs101_of_data },
#endif
#ifdef CONFIG_PINCTRL_S3C64XX
{ .compatible = "samsung,s3c64xx-pinctrl",
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h
index 9af93e3d8d9f..e62e909fb10d 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.h
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.h
@@ -82,6 +82,21 @@ enum eint_type {
EINT_TYPE_WKUP_MUX,
};
+/**
+ * enum fltcon_type - filter selection
+ * @FLT_DEFAULT: filter not selectable, default digital filter
+ * @FLT_SELECT: filter selectable (digital or delay)
+ *
+ * Some banks on some SoCs (gs101 and possibly others) have a selectable
+ * filter on alive banks of 'delay/analog' or 'digital'. If the filter
+ * selection is not available then the default filter is used (digital).
+ */
+
+enum fltcon_type {
+ FLT_DEFAULT,
+ FLT_SELECTABLE,
+};
+
/* maximum length of a pin in pin descriptor (example: "gpa0-0") */
#define PIN_NAME_LENGTH 10
@@ -122,6 +137,8 @@ struct samsung_pin_bank_type {
* @eint_type: type of the external interrupt supported by the bank.
* @eint_mask: bit mask of pins which support EINT function.
* @eint_offset: SoC-specific EINT register or interrupt offset of bank.
+ * @fltcon_type: whether the filter (delay/digital) is selectable
+ * @fltcon_offset: SoC-specific EINT filter control register offset of bank.
* @name: name to be prefixed for each pin in this pin bank.
*/
struct samsung_pin_bank_data {
@@ -133,6 +150,8 @@ struct samsung_pin_bank_data {
enum eint_type eint_type;
u32 eint_mask;
u32 eint_offset;
+ enum fltcon_type fltcon_type;
+ u32 fltcon_offset;
const char *name;
};
@@ -147,6 +166,8 @@ struct samsung_pin_bank_data {
* @eint_type: type of the external interrupt supported by the bank.
* @eint_mask: bit mask of pins which support EINT function.
* @eint_offset: SoC-specific EINT register or interrupt offset of bank.
+ * @fltcon_type: whether the filter (delay/digital) is selectable
+ * @fltcon_offset: SoC-specific EINT filter control register offset of bank.
* @name: name to be prefixed for each pin in this pin bank.
* @pin_base: starting pin number of the bank.
* @soc_priv: per-bank private data for SoC-specific code.
@@ -169,6 +190,8 @@ struct samsung_pin_bank {
enum eint_type eint_type;
u32 eint_mask;
u32 eint_offset;
+ enum fltcon_type fltcon_type;
+ u32 fltcon_offset;
const char *name;
u32 pin_base;
@@ -351,6 +374,7 @@ extern const struct samsung_pinctrl_of_match_data exynos7885_of_data;
extern const struct samsung_pinctrl_of_match_data exynos850_of_data;
extern const struct samsung_pinctrl_of_match_data exynosautov9_of_data;
extern const struct samsung_pinctrl_of_match_data fsd_of_data;
+extern const struct samsung_pinctrl_of_match_data gs101_of_data;
extern const struct samsung_pinctrl_of_match_data s3c64xx_of_data;
extern const struct samsung_pinctrl_of_match_data s3c2412_of_data;
extern const struct samsung_pinctrl_of_match_data s3c2416_of_data;
--
2.42.0.582.g8ccd20d70d-goog
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^ permalink raw reply related [flat|nested] 150+ messages in thread* Re: [PATCH 16/21] pinctrl: samsung: Add gs101 SoC pinctrl configuration
2023-10-05 15:56 ` Peter Griffin
@ 2023-10-06 6:33 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 150+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-06 6:33 UTC (permalink / raw)
To: Peter Griffin, robh+dt, krzysztof.kozlowski+dt, mturquette,
conor+dt, sboyd, tomasz.figa, s.nawrocki, linus.walleij, wim,
linux, catalin.marinas, will, arnd, olof, cw00.choi
Cc: tudor.ambarus, andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog
On 05/10/2023 17:56, Peter Griffin wrote:
> Add support for the pin-controller found on the gs101
> SoC used in Pixel 6 phones.
>
> The alive blocks on this SoC also have a filter selection
> register. Add support for this so the digital or delay filter
> can be selected. If the filter selection is not available
> then the default filter (digital) is applied.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> .../pinctrl/samsung/pinctrl-exynos-arm64.c | 163 ++++++++++++++++++
> drivers/pinctrl/samsung/pinctrl-exynos.c | 68 +++++++-
> drivers/pinctrl/samsung/pinctrl-exynos.h | 44 +++++
> drivers/pinctrl/samsung/pinctrl-samsung.c | 4 +
> drivers/pinctrl/samsung/pinctrl-samsung.h | 24 +++
> 5 files changed, 302 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
> index cb965cf93705..ae681725db26 100644
> --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
> +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
> @@ -796,3 +796,166 @@ const struct samsung_pinctrl_of_match_data fsd_of_data __initconst = {
> .ctrl = fsd_pin_ctrl,
> .num_ctrl = ARRAY_SIZE(fsd_pin_ctrl),
> };
> +
> +/*
> + * bank type for non-alive type
> + * (CON bit field: 4, DAT bit field: 1, PUD bit field: 4, DRV bit field: 4)
> + * (CONPDN bit field: 2, PUDPDN bit field: 4)
> + */
> +static struct samsung_pin_bank_type bank_type_6 = {
Bank types are defined at the top. "type_6" is way too vague. Look how
the others are named.
> + .fld_width = { 4, 1, 4, 4, 2, 4, },
> + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
> +};
> +
> +/*
> + * bank type for alive type
> + * (CON bit field: 4, DAT bit field: 1, PUD bit field: 4, DRV bit field: 4)
> + */
> +static const struct samsung_pin_bank_type bank_type_7 = {
Same problem.
> + .fld_width = { 4, 1, 4, 4, },
> + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
> +};
> +
> +/* pin banks of gs101 pin-controller (ALIVE) */
> +static const struct samsung_pin_bank_data gs101_pin_alive[] = {
> + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 8, 0x0, "gpa0", 0x00, 0x00, FLT_SELECTABLE),
> + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 7, 0x20, "gpa1", 0x04, 0x08, FLT_SELECTABLE),
> + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 5, 0x40, "gpa2", 0x08, 0x10, FLT_SELECTABLE),
> + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 4, 0x60, "gpa3", 0x0c, 0x18, FLT_SELECTABLE),
> + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 4, 0x80, "gpa4", 0x10, 0x1c, FLT_SELECTABLE),
> + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 7, 0xa0, "gpa5", 0x14, 0x20, FLT_SELECTABLE),
> + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 8, 0xc0, "gpa9", 0x18, 0x28, FLT_SELECTABLE),
> + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 2, 0xe0, "gpa10", 0x1c, 0x30, FLT_SELECTABLE),
> +};
> +
> +/* pin banks of gs101 pin-controller (FAR_ALIVE) */
> +static const struct samsung_pin_bank_data gs101_pin_far_alive[] = {
> + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 8, 0x0, "gpa6", 0x00, 0x00, FLT_SELECTABLE),
> + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 4, 0x20, "gpa7", 0x04, 0x08, FLT_SELECTABLE),
> + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 8, 0x40, "gpa8", 0x08, 0x0c, FLT_SELECTABLE),
> + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 2, 0x60, "gpa11", 0x0c, 0x14, FLT_SELECTABLE),
> +};
> +
> +/* pin banks of gs101 pin-controller (GSACORE) */
> +static const struct samsung_pin_bank_data gs101_pin_gsacore[] = {
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x0, "gps0", 0x00, 0x00, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 8, 0x20, "gps1", 0x04, 0x04, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 3, 0x40, "gps2", 0x08, 0x0c, FLT_DEFAULT),
> +};
> +
> +/* pin banks of gs101 pin-controller (GSACTRL) */
> +static const struct samsung_pin_bank_data gs101_pin_gsactrl[] = {
> + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 6, 0x0, "gps3", 0x00, 0x00, FLT_DEFAULT),
> +};
> +
> +/* pin banks of gs101 pin-controller (PERIC0) */
> +static const struct samsung_pin_bank_data gs101_pin_peric0[] = {
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 5, 0x0, "gpp0", 0x00, 0x00, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x20, "gpp1", 0x04, 0x08, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x40, "gpp2", 0x08, 0x0c, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x60, "gpp3", 0x0c, 0x10, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x80, "gpp4", 0x10, 0x14, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0xa0, "gpp5", 0x14, 0x18, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0xc0, "gpp6", 0x18, 0x1c, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0xe0, "gpp7", 0x1c, 0x20, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x100, "gpp8", 0x20, 0x24, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x120, "gpp9", 0x24, 0x28, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x140, "gpp10", 0x28, 0x2c, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x160, "gpp11", 0x2c, 0x30, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x180, "gpp12", 0x30, 0x34, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x1a0, "gpp13", 0x34, 0x38, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x1c0, "gpp14", 0x38, 0x3c, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x1e0, "gpp15", 0x3c, 0x40, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x200, "gpp16", 0x40, 0x44, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x220, "gpp17", 0x44, 0x48, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x240, "gpp18", 0x48, 0x4c, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x260, "gpp19", 0x4c, 0x50, FLT_DEFAULT),
> +};
> +
> +/* pin banks of gs101 pin-controller (PERIC1) */
> +static const struct samsung_pin_bank_data gs101_pin_peric1[] = {
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 8, 0x0, "gpp20", 0x00, 0x00, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x20, "gpp21", 0x04, 0x08, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x40, "gpp22", 0x08, 0x0c, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 8, 0x60, "gpp23", 0x0c, 0x10, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x80, "gpp24", 0x10, 0x18, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0xa0, "gpp25", 0x14, 0x1c, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 5, 0xc0, "gpp26", 0x18, 0x20, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0xe0, "gpp27", 0x1c, 0x28, FLT_DEFAULT),
> +};
> +
> +/* pin banks of gs101 pin-controller (HSI1) */
> +static const struct samsung_pin_bank_data gs101_pin_hsi1[] = {
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 6, 0x0, "gph0", 0x00, 0x00, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 7, 0x20, "gph1", 0x04, 0x08, FLT_DEFAULT),
> +};
> +
> +/* pin banks of gs101 pin-controller (HSI2) */
> +static const struct samsung_pin_bank_data gs101_pin_hsi2[] = {
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 6, 0x0, "gph2", 0x00, 0x00, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x20, "gph3", 0x04, 0x08, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 6, 0x40, "gph4", 0x08, 0x0c, FLT_DEFAULT),
> +};
> +
> +static const struct samsung_pin_ctrl gs101_pin_ctrl[] __initconst = {
> + {
> + /* pin banks of gs101 pin-controller (ALIVE) */
> + .pin_banks = gs101_pin_alive,
> + .nr_banks = ARRAY_SIZE(gs101_pin_alive),
> + .eint_gpio_init = exynos_eint_gpio_init,
> + .eint_wkup_init = exynos_eint_wkup_init,
> + .suspend = exynos_pinctrl_suspend,
> + .resume = exynos_pinctrl_resume,
> + }, {
> + /* pin banks of gs101 pin-controller (FAR_ALIVE) */
> + .pin_banks = gs101_pin_far_alive,
> + .nr_banks = ARRAY_SIZE(gs101_pin_far_alive),
> + .eint_gpio_init = exynos_eint_gpio_init,
> + .eint_wkup_init = exynos_eint_wkup_init,
> + .suspend = exynos_pinctrl_suspend,
> + .resume = exynos_pinctrl_resume,
> + }, {
> + /* pin banks of gs101 pin-controller (GSACORE) */
> + .pin_banks = gs101_pin_gsacore,
> + .nr_banks = ARRAY_SIZE(gs101_pin_gsacore),
> + .eint_gpio_init = exynos_eint_gpio_init,
> + }, {
> + /* pin banks of gs101 pin-controller (GSACTRL) */
> + .pin_banks = gs101_pin_gsactrl,
> + .nr_banks = ARRAY_SIZE(gs101_pin_gsactrl),
> + .eint_gpio_init = exynos_eint_gpio_init,
> + }, {
> + /* pin banks of gs101 pin-controller (PERIC0) */
> + .pin_banks = gs101_pin_peric0,
> + .nr_banks = ARRAY_SIZE(gs101_pin_peric0),
> + .eint_gpio_init = exynos_eint_gpio_init,
> + .suspend = exynos_pinctrl_suspend,
> + .resume = exynos_pinctrl_resume,
> + }, {
> + /* pin banks of gs101 pin-controller (PERIC1) */
> + .pin_banks = gs101_pin_peric1,
> + .nr_banks = ARRAY_SIZE(gs101_pin_peric1),
> + .eint_gpio_init = exynos_eint_gpio_init,
> + .suspend = exynos_pinctrl_suspend,
> + .resume = exynos_pinctrl_resume,
> + }, {
> + /* pin banks of gs101 pin-controller (HSI1) */
> + .pin_banks = gs101_pin_hsi1,
> + .nr_banks = ARRAY_SIZE(gs101_pin_hsi1),
> + .eint_gpio_init = exynos_eint_gpio_init,
> + .suspend = exynos_pinctrl_suspend,
> + .resume = exynos_pinctrl_resume,
> + }, {
> + /* pin banks of gs101 pin-controller (HSI2) */
> + .pin_banks = gs101_pin_hsi2,
> + .nr_banks = ARRAY_SIZE(gs101_pin_hsi2),
> + .eint_gpio_init = exynos_eint_gpio_init,
> + .suspend = exynos_pinctrl_suspend,
> + .resume = exynos_pinctrl_resume,
> + },
> +};
> +
> +const struct samsung_pinctrl_of_match_data gs101_of_data __initconst = {
> + .ctrl = gs101_pin_ctrl,
> + .num_ctrl = ARRAY_SIZE(gs101_pin_ctrl),
> +};
> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
> index a8212fc126bf..0c6c3312abb7 100644
> --- a/drivers/pinctrl/samsung/pinctrl-exynos.c
> +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
> @@ -269,6 +269,50 @@ struct exynos_eint_gpio_save {
> u32 eint_mask;
> };
Please split the patch into two: one of adding new filter code and
second for new Google SoC.
>
> +static void exynos_eint_flt_config(int sel, int width,
> + struct samsung_pinctrl_drv_data *d,
> + struct samsung_pin_bank *bank)
Arguments: first drv_data, then bank, then width, then sel... and what
is sel actually?
Also, why do you need width if it is always 0? Will it be different in
next pinctrl controllers? So the filter is per entire bank?
> +{
> + unsigned int flt_reg, flt_con = 0;
> + unsigned int val, shift;
> + int i;
> + int loop_cnt;
> +
> + flt_con |= EXYNOS_FLTCON_EN;
> +
> + if (sel)
> + flt_con |= EXYNOS_FLTCON_SEL_DIGITAL;
> +
> + flt_con |= EXYNOS_FLTCON_WIDTH(width);
This is always 0, what's the point?
> +
> + flt_reg = EXYNOS_GPIO_EFLTCON_OFFSET + bank->fltcon_offset;
> +
> + if (bank->nr_pins > EXYNOS_FLTCON_NR_PIN)
> + /*
> + * if nr_pins > 4, we should set FLTCON0 register fully.
> + * (pin0 ~ 3). So loop 4 times in case of FLTCON0.
> + */
> + loop_cnt = 4;
> + else
> + loop_cnt = bank->nr_pins;
Please document the layout of the registers in exynos_eint_flt_config()
comment (not kerneldoc). Also document what do you want to achieve here
- set entire bank to one filter for the suspend/resume?
> +
> + val = readl(d->virt_base + flt_reg);
> +
> + for (i = 0; i < loop_cnt; i++) {
> + shift = i * EXYNOS_FLTCON_LEN;
> + val &= ~(EXYNOS_FLTCON_MASK << shift);
> + val |= (flt_con << shift);
> + }
> +
> + writel(val, d->virt_base + flt_reg);
> +
Missing /*
> + /* if nr_pins > 4, we should also set FLTCON1 register like FLTCON0.
> + * (pin4 ~ )
> + */
> + if (bank->nr_pins > EXYNOS_FLTCON_NR_PIN)
> + writel(val, d->virt_base + flt_reg + 0x4);
> +}
> +
> /*
> * exynos_eint_gpio_init() - setup handling of external gpio interrupts.
> * @d: driver data of samsung pinctrl driver.
> @@ -321,6 +365,10 @@ __init int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
> goto err_domains;
> }
>
> + /* Set Delay Analog Filter */
> + if (bank->fltcon_type != FLT_DEFAULT)
> + exynos_eint_flt_config(EXYNOS_FLTCON_SEL_DELAY,
> + 0, d, bank);
> }
>
> return 0;
> @@ -555,6 +603,11 @@ __init int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
> if (bank->eint_type != EINT_TYPE_WKUP)
> continue;
>
> + /* Set Digital Filter */
> + if (bank->fltcon_type != FLT_DEFAULT)
> + exynos_eint_flt_config(EXYNOS_FLTCON_SEL_DIGITAL,
> + 0, d, bank);
> +
> bank->irq_chip = devm_kmemdup(dev, irq_chip, sizeof(*irq_chip),
> GFP_KERNEL);
> if (!bank->irq_chip) {
> @@ -658,6 +711,7 @@ static void exynos_pinctrl_suspend_bank(
> void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata)
> {
> struct samsung_pin_bank *bank = drvdata->pin_banks;
> + struct samsung_pinctrl_drv_data *d = bank->drvdata;
> struct exynos_irq_chip *irq_chip = NULL;
> int i;
>
> @@ -665,6 +719,10 @@ void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata)
> if (bank->eint_type == EINT_TYPE_GPIO)
> exynos_pinctrl_suspend_bank(drvdata, bank);
> else if (bank->eint_type == EINT_TYPE_WKUP) {
> + /* Setting Delay (Analog) Filter */
> + if (bank->fltcon_type != FLT_DEFAULT)
> + exynos_eint_flt_config(EXYNOS_FLTCON_SEL_DELAY,
> + 0, d, bank);
> if (!irq_chip) {
> irq_chip = bank->irq_chip;
> irq_chip->set_eint_wakeup_mask(drvdata,
> @@ -707,11 +765,19 @@ static void exynos_pinctrl_resume_bank(
> void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata)
> {
> struct samsung_pin_bank *bank = drvdata->pin_banks;
> + struct samsung_pinctrl_drv_data *d = bank->drvdata;
> int i;
>
> for (i = 0; i < drvdata->nr_banks; ++i, ++bank)
> - if (bank->eint_type == EINT_TYPE_GPIO)
> + if (bank->eint_type == EINT_TYPE_GPIO) {
> exynos_pinctrl_resume_bank(drvdata, bank);
> + } else if (bank->eint_type == EINT_TYPE_WKUP ||
> + bank->eint_type == EINT_TYPE_WKUP_MUX) {
> + /* Set Digital Filter */
> + if (bank->fltcon_type != FLT_DEFAULT)
> + exynos_eint_flt_config(EXYNOS_FLTCON_SEL_DIGITAL,
> + 0, d, bank);
> + }
> }
>
> static void exynos_retention_enable(struct samsung_pinctrl_drv_data *drvdata)
> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h
> index 7bd6d82c9f36..aafd8f9f52f8 100644
> --- a/drivers/pinctrl/samsung/pinctrl-exynos.h
> +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h
> @@ -16,6 +16,8 @@
> #ifndef __PINCTRL_SAMSUNG_EXYNOS_H
> #define __PINCTRL_SAMSUNG_EXYNOS_H
>
> +#include <linux/bitfield.h>
> +
I don't think you use in this header anything from bitfield.
> /* Values for the pin CON register */
> #define EXYNOS_PIN_CON_FUNC_EINT 0xf
>
> @@ -50,6 +52,14 @@
>
> #define EXYNOS_EINT_MAX_PER_BANK 8
> #define EXYNOS_EINT_NR_WKUP_EINT
> +/* EINT filter configuration */
> +#define EXYNOS_FLTCON_EN BIT(7)
EXYNOS9? Earlier variants did not have it, AFAIR.
> +#define EXYNOS_FLTCON_SEL_DIGITAL BIT(6)
> +#define EXYNOS_FLTCON_SEL_DELAY 0
> +#define EXYNOS_FLTCON_WIDTH(x) ((x) & 0x3f)
> +#define EXYNOS_FLTCON_MASK 0xFF
Keep lowercase hex
> +#define EXYNOS_FLTCON_LEN 8
> +#define EXYNOS_FLTCON_NR_PIN 4
>
> #define EXYNOS_PIN_BANK_EINTN(pins, reg, id) \
> { \
> @@ -140,6 +150,40 @@
> .name = id \
> }
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 150+ messages in thread* Re: [PATCH 16/21] pinctrl: samsung: Add gs101 SoC pinctrl configuration
@ 2023-10-06 6:33 ` Krzysztof Kozlowski
0 siblings, 0 replies; 150+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-06 6:33 UTC (permalink / raw)
To: Peter Griffin, robh+dt, krzysztof.kozlowski+dt, mturquette,
conor+dt, sboyd, tomasz.figa, s.nawrocki, linus.walleij, wim,
linux, catalin.marinas, will, arnd, olof, cw00.choi
Cc: tudor.ambarus, andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog
On 05/10/2023 17:56, Peter Griffin wrote:
> Add support for the pin-controller found on the gs101
> SoC used in Pixel 6 phones.
>
> The alive blocks on this SoC also have a filter selection
> register. Add support for this so the digital or delay filter
> can be selected. If the filter selection is not available
> then the default filter (digital) is applied.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> .../pinctrl/samsung/pinctrl-exynos-arm64.c | 163 ++++++++++++++++++
> drivers/pinctrl/samsung/pinctrl-exynos.c | 68 +++++++-
> drivers/pinctrl/samsung/pinctrl-exynos.h | 44 +++++
> drivers/pinctrl/samsung/pinctrl-samsung.c | 4 +
> drivers/pinctrl/samsung/pinctrl-samsung.h | 24 +++
> 5 files changed, 302 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
> index cb965cf93705..ae681725db26 100644
> --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
> +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
> @@ -796,3 +796,166 @@ const struct samsung_pinctrl_of_match_data fsd_of_data __initconst = {
> .ctrl = fsd_pin_ctrl,
> .num_ctrl = ARRAY_SIZE(fsd_pin_ctrl),
> };
> +
> +/*
> + * bank type for non-alive type
> + * (CON bit field: 4, DAT bit field: 1, PUD bit field: 4, DRV bit field: 4)
> + * (CONPDN bit field: 2, PUDPDN bit field: 4)
> + */
> +static struct samsung_pin_bank_type bank_type_6 = {
Bank types are defined at the top. "type_6" is way too vague. Look how
the others are named.
> + .fld_width = { 4, 1, 4, 4, 2, 4, },
> + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
> +};
> +
> +/*
> + * bank type for alive type
> + * (CON bit field: 4, DAT bit field: 1, PUD bit field: 4, DRV bit field: 4)
> + */
> +static const struct samsung_pin_bank_type bank_type_7 = {
Same problem.
> + .fld_width = { 4, 1, 4, 4, },
> + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
> +};
> +
> +/* pin banks of gs101 pin-controller (ALIVE) */
> +static const struct samsung_pin_bank_data gs101_pin_alive[] = {
> + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 8, 0x0, "gpa0", 0x00, 0x00, FLT_SELECTABLE),
> + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 7, 0x20, "gpa1", 0x04, 0x08, FLT_SELECTABLE),
> + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 5, 0x40, "gpa2", 0x08, 0x10, FLT_SELECTABLE),
> + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 4, 0x60, "gpa3", 0x0c, 0x18, FLT_SELECTABLE),
> + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 4, 0x80, "gpa4", 0x10, 0x1c, FLT_SELECTABLE),
> + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 7, 0xa0, "gpa5", 0x14, 0x20, FLT_SELECTABLE),
> + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 8, 0xc0, "gpa9", 0x18, 0x28, FLT_SELECTABLE),
> + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 2, 0xe0, "gpa10", 0x1c, 0x30, FLT_SELECTABLE),
> +};
> +
> +/* pin banks of gs101 pin-controller (FAR_ALIVE) */
> +static const struct samsung_pin_bank_data gs101_pin_far_alive[] = {
> + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 8, 0x0, "gpa6", 0x00, 0x00, FLT_SELECTABLE),
> + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 4, 0x20, "gpa7", 0x04, 0x08, FLT_SELECTABLE),
> + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 8, 0x40, "gpa8", 0x08, 0x0c, FLT_SELECTABLE),
> + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 2, 0x60, "gpa11", 0x0c, 0x14, FLT_SELECTABLE),
> +};
> +
> +/* pin banks of gs101 pin-controller (GSACORE) */
> +static const struct samsung_pin_bank_data gs101_pin_gsacore[] = {
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x0, "gps0", 0x00, 0x00, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 8, 0x20, "gps1", 0x04, 0x04, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 3, 0x40, "gps2", 0x08, 0x0c, FLT_DEFAULT),
> +};
> +
> +/* pin banks of gs101 pin-controller (GSACTRL) */
> +static const struct samsung_pin_bank_data gs101_pin_gsactrl[] = {
> + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 6, 0x0, "gps3", 0x00, 0x00, FLT_DEFAULT),
> +};
> +
> +/* pin banks of gs101 pin-controller (PERIC0) */
> +static const struct samsung_pin_bank_data gs101_pin_peric0[] = {
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 5, 0x0, "gpp0", 0x00, 0x00, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x20, "gpp1", 0x04, 0x08, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x40, "gpp2", 0x08, 0x0c, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x60, "gpp3", 0x0c, 0x10, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x80, "gpp4", 0x10, 0x14, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0xa0, "gpp5", 0x14, 0x18, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0xc0, "gpp6", 0x18, 0x1c, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0xe0, "gpp7", 0x1c, 0x20, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x100, "gpp8", 0x20, 0x24, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x120, "gpp9", 0x24, 0x28, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x140, "gpp10", 0x28, 0x2c, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x160, "gpp11", 0x2c, 0x30, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x180, "gpp12", 0x30, 0x34, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x1a0, "gpp13", 0x34, 0x38, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x1c0, "gpp14", 0x38, 0x3c, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x1e0, "gpp15", 0x3c, 0x40, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x200, "gpp16", 0x40, 0x44, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x220, "gpp17", 0x44, 0x48, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x240, "gpp18", 0x48, 0x4c, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x260, "gpp19", 0x4c, 0x50, FLT_DEFAULT),
> +};
> +
> +/* pin banks of gs101 pin-controller (PERIC1) */
> +static const struct samsung_pin_bank_data gs101_pin_peric1[] = {
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 8, 0x0, "gpp20", 0x00, 0x00, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x20, "gpp21", 0x04, 0x08, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x40, "gpp22", 0x08, 0x0c, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 8, 0x60, "gpp23", 0x0c, 0x10, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x80, "gpp24", 0x10, 0x18, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0xa0, "gpp25", 0x14, 0x1c, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 5, 0xc0, "gpp26", 0x18, 0x20, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0xe0, "gpp27", 0x1c, 0x28, FLT_DEFAULT),
> +};
> +
> +/* pin banks of gs101 pin-controller (HSI1) */
> +static const struct samsung_pin_bank_data gs101_pin_hsi1[] = {
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 6, 0x0, "gph0", 0x00, 0x00, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 7, 0x20, "gph1", 0x04, 0x08, FLT_DEFAULT),
> +};
> +
> +/* pin banks of gs101 pin-controller (HSI2) */
> +static const struct samsung_pin_bank_data gs101_pin_hsi2[] = {
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 6, 0x0, "gph2", 0x00, 0x00, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x20, "gph3", 0x04, 0x08, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 6, 0x40, "gph4", 0x08, 0x0c, FLT_DEFAULT),
> +};
> +
> +static const struct samsung_pin_ctrl gs101_pin_ctrl[] __initconst = {
> + {
> + /* pin banks of gs101 pin-controller (ALIVE) */
> + .pin_banks = gs101_pin_alive,
> + .nr_banks = ARRAY_SIZE(gs101_pin_alive),
> + .eint_gpio_init = exynos_eint_gpio_init,
> + .eint_wkup_init = exynos_eint_wkup_init,
> + .suspend = exynos_pinctrl_suspend,
> + .resume = exynos_pinctrl_resume,
> + }, {
> + /* pin banks of gs101 pin-controller (FAR_ALIVE) */
> + .pin_banks = gs101_pin_far_alive,
> + .nr_banks = ARRAY_SIZE(gs101_pin_far_alive),
> + .eint_gpio_init = exynos_eint_gpio_init,
> + .eint_wkup_init = exynos_eint_wkup_init,
> + .suspend = exynos_pinctrl_suspend,
> + .resume = exynos_pinctrl_resume,
> + }, {
> + /* pin banks of gs101 pin-controller (GSACORE) */
> + .pin_banks = gs101_pin_gsacore,
> + .nr_banks = ARRAY_SIZE(gs101_pin_gsacore),
> + .eint_gpio_init = exynos_eint_gpio_init,
> + }, {
> + /* pin banks of gs101 pin-controller (GSACTRL) */
> + .pin_banks = gs101_pin_gsactrl,
> + .nr_banks = ARRAY_SIZE(gs101_pin_gsactrl),
> + .eint_gpio_init = exynos_eint_gpio_init,
> + }, {
> + /* pin banks of gs101 pin-controller (PERIC0) */
> + .pin_banks = gs101_pin_peric0,
> + .nr_banks = ARRAY_SIZE(gs101_pin_peric0),
> + .eint_gpio_init = exynos_eint_gpio_init,
> + .suspend = exynos_pinctrl_suspend,
> + .resume = exynos_pinctrl_resume,
> + }, {
> + /* pin banks of gs101 pin-controller (PERIC1) */
> + .pin_banks = gs101_pin_peric1,
> + .nr_banks = ARRAY_SIZE(gs101_pin_peric1),
> + .eint_gpio_init = exynos_eint_gpio_init,
> + .suspend = exynos_pinctrl_suspend,
> + .resume = exynos_pinctrl_resume,
> + }, {
> + /* pin banks of gs101 pin-controller (HSI1) */
> + .pin_banks = gs101_pin_hsi1,
> + .nr_banks = ARRAY_SIZE(gs101_pin_hsi1),
> + .eint_gpio_init = exynos_eint_gpio_init,
> + .suspend = exynos_pinctrl_suspend,
> + .resume = exynos_pinctrl_resume,
> + }, {
> + /* pin banks of gs101 pin-controller (HSI2) */
> + .pin_banks = gs101_pin_hsi2,
> + .nr_banks = ARRAY_SIZE(gs101_pin_hsi2),
> + .eint_gpio_init = exynos_eint_gpio_init,
> + .suspend = exynos_pinctrl_suspend,
> + .resume = exynos_pinctrl_resume,
> + },
> +};
> +
> +const struct samsung_pinctrl_of_match_data gs101_of_data __initconst = {
> + .ctrl = gs101_pin_ctrl,
> + .num_ctrl = ARRAY_SIZE(gs101_pin_ctrl),
> +};
> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
> index a8212fc126bf..0c6c3312abb7 100644
> --- a/drivers/pinctrl/samsung/pinctrl-exynos.c
> +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
> @@ -269,6 +269,50 @@ struct exynos_eint_gpio_save {
> u32 eint_mask;
> };
Please split the patch into two: one of adding new filter code and
second for new Google SoC.
>
> +static void exynos_eint_flt_config(int sel, int width,
> + struct samsung_pinctrl_drv_data *d,
> + struct samsung_pin_bank *bank)
Arguments: first drv_data, then bank, then width, then sel... and what
is sel actually?
Also, why do you need width if it is always 0? Will it be different in
next pinctrl controllers? So the filter is per entire bank?
> +{
> + unsigned int flt_reg, flt_con = 0;
> + unsigned int val, shift;
> + int i;
> + int loop_cnt;
> +
> + flt_con |= EXYNOS_FLTCON_EN;
> +
> + if (sel)
> + flt_con |= EXYNOS_FLTCON_SEL_DIGITAL;
> +
> + flt_con |= EXYNOS_FLTCON_WIDTH(width);
This is always 0, what's the point?
> +
> + flt_reg = EXYNOS_GPIO_EFLTCON_OFFSET + bank->fltcon_offset;
> +
> + if (bank->nr_pins > EXYNOS_FLTCON_NR_PIN)
> + /*
> + * if nr_pins > 4, we should set FLTCON0 register fully.
> + * (pin0 ~ 3). So loop 4 times in case of FLTCON0.
> + */
> + loop_cnt = 4;
> + else
> + loop_cnt = bank->nr_pins;
Please document the layout of the registers in exynos_eint_flt_config()
comment (not kerneldoc). Also document what do you want to achieve here
- set entire bank to one filter for the suspend/resume?
> +
> + val = readl(d->virt_base + flt_reg);
> +
> + for (i = 0; i < loop_cnt; i++) {
> + shift = i * EXYNOS_FLTCON_LEN;
> + val &= ~(EXYNOS_FLTCON_MASK << shift);
> + val |= (flt_con << shift);
> + }
> +
> + writel(val, d->virt_base + flt_reg);
> +
Missing /*
> + /* if nr_pins > 4, we should also set FLTCON1 register like FLTCON0.
> + * (pin4 ~ )
> + */
> + if (bank->nr_pins > EXYNOS_FLTCON_NR_PIN)
> + writel(val, d->virt_base + flt_reg + 0x4);
> +}
> +
> /*
> * exynos_eint_gpio_init() - setup handling of external gpio interrupts.
> * @d: driver data of samsung pinctrl driver.
> @@ -321,6 +365,10 @@ __init int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
> goto err_domains;
> }
>
> + /* Set Delay Analog Filter */
> + if (bank->fltcon_type != FLT_DEFAULT)
> + exynos_eint_flt_config(EXYNOS_FLTCON_SEL_DELAY,
> + 0, d, bank);
> }
>
> return 0;
> @@ -555,6 +603,11 @@ __init int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
> if (bank->eint_type != EINT_TYPE_WKUP)
> continue;
>
> + /* Set Digital Filter */
> + if (bank->fltcon_type != FLT_DEFAULT)
> + exynos_eint_flt_config(EXYNOS_FLTCON_SEL_DIGITAL,
> + 0, d, bank);
> +
> bank->irq_chip = devm_kmemdup(dev, irq_chip, sizeof(*irq_chip),
> GFP_KERNEL);
> if (!bank->irq_chip) {
> @@ -658,6 +711,7 @@ static void exynos_pinctrl_suspend_bank(
> void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata)
> {
> struct samsung_pin_bank *bank = drvdata->pin_banks;
> + struct samsung_pinctrl_drv_data *d = bank->drvdata;
> struct exynos_irq_chip *irq_chip = NULL;
> int i;
>
> @@ -665,6 +719,10 @@ void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata)
> if (bank->eint_type == EINT_TYPE_GPIO)
> exynos_pinctrl_suspend_bank(drvdata, bank);
> else if (bank->eint_type == EINT_TYPE_WKUP) {
> + /* Setting Delay (Analog) Filter */
> + if (bank->fltcon_type != FLT_DEFAULT)
> + exynos_eint_flt_config(EXYNOS_FLTCON_SEL_DELAY,
> + 0, d, bank);
> if (!irq_chip) {
> irq_chip = bank->irq_chip;
> irq_chip->set_eint_wakeup_mask(drvdata,
> @@ -707,11 +765,19 @@ static void exynos_pinctrl_resume_bank(
> void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata)
> {
> struct samsung_pin_bank *bank = drvdata->pin_banks;
> + struct samsung_pinctrl_drv_data *d = bank->drvdata;
> int i;
>
> for (i = 0; i < drvdata->nr_banks; ++i, ++bank)
> - if (bank->eint_type == EINT_TYPE_GPIO)
> + if (bank->eint_type == EINT_TYPE_GPIO) {
> exynos_pinctrl_resume_bank(drvdata, bank);
> + } else if (bank->eint_type == EINT_TYPE_WKUP ||
> + bank->eint_type == EINT_TYPE_WKUP_MUX) {
> + /* Set Digital Filter */
> + if (bank->fltcon_type != FLT_DEFAULT)
> + exynos_eint_flt_config(EXYNOS_FLTCON_SEL_DIGITAL,
> + 0, d, bank);
> + }
> }
>
> static void exynos_retention_enable(struct samsung_pinctrl_drv_data *drvdata)
> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h
> index 7bd6d82c9f36..aafd8f9f52f8 100644
> --- a/drivers/pinctrl/samsung/pinctrl-exynos.h
> +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h
> @@ -16,6 +16,8 @@
> #ifndef __PINCTRL_SAMSUNG_EXYNOS_H
> #define __PINCTRL_SAMSUNG_EXYNOS_H
>
> +#include <linux/bitfield.h>
> +
I don't think you use in this header anything from bitfield.
> /* Values for the pin CON register */
> #define EXYNOS_PIN_CON_FUNC_EINT 0xf
>
> @@ -50,6 +52,14 @@
>
> #define EXYNOS_EINT_MAX_PER_BANK 8
> #define EXYNOS_EINT_NR_WKUP_EINT
> +/* EINT filter configuration */
> +#define EXYNOS_FLTCON_EN BIT(7)
EXYNOS9? Earlier variants did not have it, AFAIR.
> +#define EXYNOS_FLTCON_SEL_DIGITAL BIT(6)
> +#define EXYNOS_FLTCON_SEL_DELAY 0
> +#define EXYNOS_FLTCON_WIDTH(x) ((x) & 0x3f)
> +#define EXYNOS_FLTCON_MASK 0xFF
Keep lowercase hex
> +#define EXYNOS_FLTCON_LEN 8
> +#define EXYNOS_FLTCON_NR_PIN 4
>
> #define EXYNOS_PIN_BANK_EINTN(pins, reg, id) \
> { \
> @@ -140,6 +150,40 @@
> .name = id \
> }
Best regards,
Krzysztof
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^ permalink raw reply [flat|nested] 150+ messages in thread* Re: [PATCH 16/21] pinctrl: samsung: Add gs101 SoC pinctrl configuration
2023-10-06 6:33 ` Krzysztof Kozlowski
@ 2023-10-09 7:49 ` Peter Griffin
-1 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-09 7:49 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi, tudor.ambarus,
andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog
Hi Krzysztof,
Firstly, thankyou for all your reviews. It's much appreciated.
On Fri, 6 Oct 2023 at 07:33, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 05/10/2023 17:56, Peter Griffin wrote:
> > Add support for the pin-controller found on the gs101
> > SoC used in Pixel 6 phones.
> >
> > The alive blocks on this SoC also have a filter selection
> > register. Add support for this so the digital or delay filter
> > can be selected. If the filter selection is not available
> > then the default filter (digital) is applied.
> >
> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> > ---
> > .../pinctrl/samsung/pinctrl-exynos-arm64.c | 163 ++++++++++++++++++
> > drivers/pinctrl/samsung/pinctrl-exynos.c | 68 +++++++-
> > drivers/pinctrl/samsung/pinctrl-exynos.h | 44 +++++
> > drivers/pinctrl/samsung/pinctrl-samsung.c | 4 +
> > drivers/pinctrl/samsung/pinctrl-samsung.h | 24 +++
> > 5 files changed, 302 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
> > index cb965cf93705..ae681725db26 100644
> > --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
> > +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
> > @@ -796,3 +796,166 @@ const struct samsung_pinctrl_of_match_data fsd_of_data __initconst = {
> > .ctrl = fsd_pin_ctrl,
> > .num_ctrl = ARRAY_SIZE(fsd_pin_ctrl),
> > };
> > +
> > +/*
> > + * bank type for non-alive type
> > + * (CON bit field: 4, DAT bit field: 1, PUD bit field: 4, DRV bit field: 4)
> > + * (CONPDN bit field: 2, PUDPDN bit field: 4)
> > + */
> > +static struct samsung_pin_bank_type bank_type_6 = {
>
> Bank types are defined at the top. "type_6" is way too vague. Look how
> the others are named.
Will fix
>
> > + .fld_width = { 4, 1, 4, 4, 2, 4, },
> > + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
> > +};
> > +
> > +/*
> > + * bank type for alive type
> > + * (CON bit field: 4, DAT bit field: 1, PUD bit field: 4, DRV bit field: 4)
> > + */
> > +static const struct samsung_pin_bank_type bank_type_7 = {
>
> Same problem.
Will fix
>
> > + .fld_width = { 4, 1, 4, 4, },
> > + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
> > +};
> > +
> > +/* pin banks of gs101 pin-controller (ALIVE) */
> > +static const struct samsung_pin_bank_data gs101_pin_alive[] = {
> > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 8, 0x0, "gpa0", 0x00, 0x00, FLT_SELECTABLE),
> > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 7, 0x20, "gpa1", 0x04, 0x08, FLT_SELECTABLE),
> > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 5, 0x40, "gpa2", 0x08, 0x10, FLT_SELECTABLE),
> > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 4, 0x60, "gpa3", 0x0c, 0x18, FLT_SELECTABLE),
> > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 4, 0x80, "gpa4", 0x10, 0x1c, FLT_SELECTABLE),
> > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 7, 0xa0, "gpa5", 0x14, 0x20, FLT_SELECTABLE),
> > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 8, 0xc0, "gpa9", 0x18, 0x28, FLT_SELECTABLE),
> > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 2, 0xe0, "gpa10", 0x1c, 0x30, FLT_SELECTABLE),
> > +};
> > +
> > +/* pin banks of gs101 pin-controller (FAR_ALIVE) */
> > +static const struct samsung_pin_bank_data gs101_pin_far_alive[] = {
> > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 8, 0x0, "gpa6", 0x00, 0x00, FLT_SELECTABLE),
> > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 4, 0x20, "gpa7", 0x04, 0x08, FLT_SELECTABLE),
> > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 8, 0x40, "gpa8", 0x08, 0x0c, FLT_SELECTABLE),
> > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 2, 0x60, "gpa11", 0x0c, 0x14, FLT_SELECTABLE),
> > +};
> > +
> > +/* pin banks of gs101 pin-controller (GSACORE) */
> > +static const struct samsung_pin_bank_data gs101_pin_gsacore[] = {
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x0, "gps0", 0x00, 0x00, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 8, 0x20, "gps1", 0x04, 0x04, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 3, 0x40, "gps2", 0x08, 0x0c, FLT_DEFAULT),
> > +};
> > +
> > +/* pin banks of gs101 pin-controller (GSACTRL) */
> > +static const struct samsung_pin_bank_data gs101_pin_gsactrl[] = {
> > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 6, 0x0, "gps3", 0x00, 0x00, FLT_DEFAULT),
> > +};
> > +
> > +/* pin banks of gs101 pin-controller (PERIC0) */
> > +static const struct samsung_pin_bank_data gs101_pin_peric0[] = {
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 5, 0x0, "gpp0", 0x00, 0x00, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x20, "gpp1", 0x04, 0x08, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x40, "gpp2", 0x08, 0x0c, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x60, "gpp3", 0x0c, 0x10, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x80, "gpp4", 0x10, 0x14, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0xa0, "gpp5", 0x14, 0x18, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0xc0, "gpp6", 0x18, 0x1c, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0xe0, "gpp7", 0x1c, 0x20, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x100, "gpp8", 0x20, 0x24, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x120, "gpp9", 0x24, 0x28, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x140, "gpp10", 0x28, 0x2c, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x160, "gpp11", 0x2c, 0x30, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x180, "gpp12", 0x30, 0x34, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x1a0, "gpp13", 0x34, 0x38, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x1c0, "gpp14", 0x38, 0x3c, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x1e0, "gpp15", 0x3c, 0x40, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x200, "gpp16", 0x40, 0x44, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x220, "gpp17", 0x44, 0x48, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x240, "gpp18", 0x48, 0x4c, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x260, "gpp19", 0x4c, 0x50, FLT_DEFAULT),
> > +};
> > +
> > +/* pin banks of gs101 pin-controller (PERIC1) */
> > +static const struct samsung_pin_bank_data gs101_pin_peric1[] = {
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 8, 0x0, "gpp20", 0x00, 0x00, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x20, "gpp21", 0x04, 0x08, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x40, "gpp22", 0x08, 0x0c, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 8, 0x60, "gpp23", 0x0c, 0x10, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x80, "gpp24", 0x10, 0x18, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0xa0, "gpp25", 0x14, 0x1c, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 5, 0xc0, "gpp26", 0x18, 0x20, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0xe0, "gpp27", 0x1c, 0x28, FLT_DEFAULT),
> > +};
> > +
> > +/* pin banks of gs101 pin-controller (HSI1) */
> > +static const struct samsung_pin_bank_data gs101_pin_hsi1[] = {
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 6, 0x0, "gph0", 0x00, 0x00, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 7, 0x20, "gph1", 0x04, 0x08, FLT_DEFAULT),
> > +};
> > +
> > +/* pin banks of gs101 pin-controller (HSI2) */
> > +static const struct samsung_pin_bank_data gs101_pin_hsi2[] = {
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 6, 0x0, "gph2", 0x00, 0x00, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x20, "gph3", 0x04, 0x08, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 6, 0x40, "gph4", 0x08, 0x0c, FLT_DEFAULT),
> > +};
> > +
> > +static const struct samsung_pin_ctrl gs101_pin_ctrl[] __initconst = {
> > + {
> > + /* pin banks of gs101 pin-controller (ALIVE) */
> > + .pin_banks = gs101_pin_alive,
> > + .nr_banks = ARRAY_SIZE(gs101_pin_alive),
> > + .eint_gpio_init = exynos_eint_gpio_init,
> > + .eint_wkup_init = exynos_eint_wkup_init,
> > + .suspend = exynos_pinctrl_suspend,
> > + .resume = exynos_pinctrl_resume,
> > + }, {
> > + /* pin banks of gs101 pin-controller (FAR_ALIVE) */
> > + .pin_banks = gs101_pin_far_alive,
> > + .nr_banks = ARRAY_SIZE(gs101_pin_far_alive),
> > + .eint_gpio_init = exynos_eint_gpio_init,
> > + .eint_wkup_init = exynos_eint_wkup_init,
> > + .suspend = exynos_pinctrl_suspend,
> > + .resume = exynos_pinctrl_resume,
> > + }, {
> > + /* pin banks of gs101 pin-controller (GSACORE) */
> > + .pin_banks = gs101_pin_gsacore,
> > + .nr_banks = ARRAY_SIZE(gs101_pin_gsacore),
> > + .eint_gpio_init = exynos_eint_gpio_init,
> > + }, {
> > + /* pin banks of gs101 pin-controller (GSACTRL) */
> > + .pin_banks = gs101_pin_gsactrl,
> > + .nr_banks = ARRAY_SIZE(gs101_pin_gsactrl),
> > + .eint_gpio_init = exynos_eint_gpio_init,
> > + }, {
> > + /* pin banks of gs101 pin-controller (PERIC0) */
> > + .pin_banks = gs101_pin_peric0,
> > + .nr_banks = ARRAY_SIZE(gs101_pin_peric0),
> > + .eint_gpio_init = exynos_eint_gpio_init,
> > + .suspend = exynos_pinctrl_suspend,
> > + .resume = exynos_pinctrl_resume,
> > + }, {
> > + /* pin banks of gs101 pin-controller (PERIC1) */
> > + .pin_banks = gs101_pin_peric1,
> > + .nr_banks = ARRAY_SIZE(gs101_pin_peric1),
> > + .eint_gpio_init = exynos_eint_gpio_init,
> > + .suspend = exynos_pinctrl_suspend,
> > + .resume = exynos_pinctrl_resume,
> > + }, {
> > + /* pin banks of gs101 pin-controller (HSI1) */
> > + .pin_banks = gs101_pin_hsi1,
> > + .nr_banks = ARRAY_SIZE(gs101_pin_hsi1),
> > + .eint_gpio_init = exynos_eint_gpio_init,
> > + .suspend = exynos_pinctrl_suspend,
> > + .resume = exynos_pinctrl_resume,
> > + }, {
> > + /* pin banks of gs101 pin-controller (HSI2) */
> > + .pin_banks = gs101_pin_hsi2,
> > + .nr_banks = ARRAY_SIZE(gs101_pin_hsi2),
> > + .eint_gpio_init = exynos_eint_gpio_init,
> > + .suspend = exynos_pinctrl_suspend,
> > + .resume = exynos_pinctrl_resume,
> > + },
> > +};
> > +
> > +const struct samsung_pinctrl_of_match_data gs101_of_data __initconst = {
> > + .ctrl = gs101_pin_ctrl,
> > + .num_ctrl = ARRAY_SIZE(gs101_pin_ctrl),
> > +};
> > diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
> > index a8212fc126bf..0c6c3312abb7 100644
> > --- a/drivers/pinctrl/samsung/pinctrl-exynos.c
> > +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
> > @@ -269,6 +269,50 @@ struct exynos_eint_gpio_save {
> > u32 eint_mask;
> > };
>
> Please split the patch into two: one of adding new filter code and
> second for new Google SoC.
Will do
>
> >
> > +static void exynos_eint_flt_config(int sel, int width,
> > + struct samsung_pinctrl_drv_data *d,
> > + struct samsung_pin_bank *bank)
>
> Arguments: first drv_data, then bank, then width, then sel... and what
> is sel actually?
Will fix.
Sel parameter is just setting the FLT_SEL bitfield
0 = Delay filter
1 = Digital filter
>
> Also, why do you need width if it is always 0? Will it be different in
> next pinctrl controllers?
The downstream driver never set the width bitfield so I we could remove
this width logic and add it back if it's ever required.
> So the filter is per entire bank?
The filter is selectable per pin. So each pin has a FLT_EN, FLT_SEL and
FLT_WIDTH bitfield.
>
> > +{
> > + unsigned int flt_reg, flt_con = 0;
> > + unsigned int val, shift;
> > + int i;
> > + int loop_cnt;
> > +
> > + flt_con |= EXYNOS_FLTCON_EN;
> > +
> > + if (sel)
> > + flt_con |= EXYNOS_FLTCON_SEL_DIGITAL;
> > +
> > + flt_con |= EXYNOS_FLTCON_WIDTH(width);
>
> This is always 0, what's the point?
Yeah we could remove this, and add it back if it's ever required. Let
me know if that's what you prefer?
>
> > +
> > + flt_reg = EXYNOS_GPIO_EFLTCON_OFFSET + bank->fltcon_offset;
> > +
> > + if (bank->nr_pins > EXYNOS_FLTCON_NR_PIN)
> > + /*
> > + * if nr_pins > 4, we should set FLTCON0 register fully.
> > + * (pin0 ~ 3). So loop 4 times in case of FLTCON0.
> > + */
> > + loop_cnt = 4;
> > + else
> > + loop_cnt = bank->nr_pins;
>
> Please document the layout of the registers in exynos_eint_flt_config()
> comment (not kerneldoc). Also document what do you want to achieve here
> - set entire bank to one filter for the suspend/resume?
Yes exactly it is looping through setting all the pins in the bank to
one filter on
suspend and resume. I will add a comment as you suggest.
>
> > +
> > + val = readl(d->virt_base + flt_reg);
> > +
> > + for (i = 0; i < loop_cnt; i++) {
> > + shift = i * EXYNOS_FLTCON_LEN;
> > + val &= ~(EXYNOS_FLTCON_MASK << shift);
> > + val |= (flt_con << shift);
> > + }
> > +
> > + writel(val, d->virt_base + flt_reg);
> > +
>
> Missing /*
Will fix
>
> > + /* if nr_pins > 4, we should also set FLTCON1 register like FLTCON0.
> > + * (pin4 ~ )
> > + */
> > + if (bank->nr_pins > EXYNOS_FLTCON_NR_PIN)
> > + writel(val, d->virt_base + flt_reg + 0x4);
> > +}
> > +
> > /*
> > * exynos_eint_gpio_init() - setup handling of external gpio interrupts.
> > * @d: driver data of samsung pinctrl driver.
> > @@ -321,6 +365,10 @@ __init int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
> > goto err_domains;
> > }
> >
> > + /* Set Delay Analog Filter */
> > + if (bank->fltcon_type != FLT_DEFAULT)
> > + exynos_eint_flt_config(EXYNOS_FLTCON_SEL_DELAY,
> > + 0, d, bank);
> > }
> >
> > return 0;
> > @@ -555,6 +603,11 @@ __init int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
> > if (bank->eint_type != EINT_TYPE_WKUP)
> > continue;
> >
> > + /* Set Digital Filter */
> > + if (bank->fltcon_type != FLT_DEFAULT)
> > + exynos_eint_flt_config(EXYNOS_FLTCON_SEL_DIGITAL,
> > + 0, d, bank);
> > +
> > bank->irq_chip = devm_kmemdup(dev, irq_chip, sizeof(*irq_chip),
> > GFP_KERNEL);
> > if (!bank->irq_chip) {
> > @@ -658,6 +711,7 @@ static void exynos_pinctrl_suspend_bank(
> > void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata)
> > {
> > struct samsung_pin_bank *bank = drvdata->pin_banks;
> > + struct samsung_pinctrl_drv_data *d = bank->drvdata;
> > struct exynos_irq_chip *irq_chip = NULL;
> > int i;
> >
> > @@ -665,6 +719,10 @@ void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata)
> > if (bank->eint_type == EINT_TYPE_GPIO)
> > exynos_pinctrl_suspend_bank(drvdata, bank);
> > else if (bank->eint_type == EINT_TYPE_WKUP) {
> > + /* Setting Delay (Analog) Filter */
> > + if (bank->fltcon_type != FLT_DEFAULT)
> > + exynos_eint_flt_config(EXYNOS_FLTCON_SEL_DELAY,
> > + 0, d, bank);
> > if (!irq_chip) {
> > irq_chip = bank->irq_chip;
> > irq_chip->set_eint_wakeup_mask(drvdata,
> > @@ -707,11 +765,19 @@ static void exynos_pinctrl_resume_bank(
> > void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata)
> > {
> > struct samsung_pin_bank *bank = drvdata->pin_banks;
> > + struct samsung_pinctrl_drv_data *d = bank->drvdata;
> > int i;
> >
> > for (i = 0; i < drvdata->nr_banks; ++i, ++bank)
> > - if (bank->eint_type == EINT_TYPE_GPIO)
> > + if (bank->eint_type == EINT_TYPE_GPIO) {
> > exynos_pinctrl_resume_bank(drvdata, bank);
> > + } else if (bank->eint_type == EINT_TYPE_WKUP ||
> > + bank->eint_type == EINT_TYPE_WKUP_MUX) {
> > + /* Set Digital Filter */
> > + if (bank->fltcon_type != FLT_DEFAULT)
> > + exynos_eint_flt_config(EXYNOS_FLTCON_SEL_DIGITAL,
> > + 0, d, bank);
> > + }
> > }
> >
> > static void exynos_retention_enable(struct samsung_pinctrl_drv_data *drvdata)
> > diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h
> > index 7bd6d82c9f36..aafd8f9f52f8 100644
> > --- a/drivers/pinctrl/samsung/pinctrl-exynos.h
> > +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h
> > @@ -16,6 +16,8 @@
> > #ifndef __PINCTRL_SAMSUNG_EXYNOS_H
> > #define __PINCTRL_SAMSUNG_EXYNOS_H
> >
> > +#include <linux/bitfield.h>
> > +
>
> I don't think you use in this header anything from bitfield.
>
> > /* Values for the pin CON register */
> > #define EXYNOS_PIN_CON_FUNC_EINT 0xf
> >
> > @@ -50,6 +52,14 @@
> >
> > #define EXYNOS_EINT_MAX_PER_BANK 8
> > #define EXYNOS_EINT_NR_WKUP_EINT
> > +/* EINT filter configuration */
> > +#define EXYNOS_FLTCON_EN BIT(7)
>
> EXYNOS9? Earlier variants did not have it, AFAIR.
Will fix
>
> > +#define EXYNOS_FLTCON_SEL_DIGITAL BIT(6)
> > +#define EXYNOS_FLTCON_SEL_DELAY 0
> > +#define EXYNOS_FLTCON_WIDTH(x) ((x) & 0x3f)
> > +#define EXYNOS_FLTCON_MASK 0xFF
>
> Keep lowercase hex
Will fix
Kind regards,
Peter.
^ permalink raw reply [flat|nested] 150+ messages in thread* Re: [PATCH 16/21] pinctrl: samsung: Add gs101 SoC pinctrl configuration
@ 2023-10-09 7:49 ` Peter Griffin
0 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-09 7:49 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi, tudor.ambarus,
andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog
Hi Krzysztof,
Firstly, thankyou for all your reviews. It's much appreciated.
On Fri, 6 Oct 2023 at 07:33, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 05/10/2023 17:56, Peter Griffin wrote:
> > Add support for the pin-controller found on the gs101
> > SoC used in Pixel 6 phones.
> >
> > The alive blocks on this SoC also have a filter selection
> > register. Add support for this so the digital or delay filter
> > can be selected. If the filter selection is not available
> > then the default filter (digital) is applied.
> >
> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> > ---
> > .../pinctrl/samsung/pinctrl-exynos-arm64.c | 163 ++++++++++++++++++
> > drivers/pinctrl/samsung/pinctrl-exynos.c | 68 +++++++-
> > drivers/pinctrl/samsung/pinctrl-exynos.h | 44 +++++
> > drivers/pinctrl/samsung/pinctrl-samsung.c | 4 +
> > drivers/pinctrl/samsung/pinctrl-samsung.h | 24 +++
> > 5 files changed, 302 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
> > index cb965cf93705..ae681725db26 100644
> > --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
> > +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
> > @@ -796,3 +796,166 @@ const struct samsung_pinctrl_of_match_data fsd_of_data __initconst = {
> > .ctrl = fsd_pin_ctrl,
> > .num_ctrl = ARRAY_SIZE(fsd_pin_ctrl),
> > };
> > +
> > +/*
> > + * bank type for non-alive type
> > + * (CON bit field: 4, DAT bit field: 1, PUD bit field: 4, DRV bit field: 4)
> > + * (CONPDN bit field: 2, PUDPDN bit field: 4)
> > + */
> > +static struct samsung_pin_bank_type bank_type_6 = {
>
> Bank types are defined at the top. "type_6" is way too vague. Look how
> the others are named.
Will fix
>
> > + .fld_width = { 4, 1, 4, 4, 2, 4, },
> > + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
> > +};
> > +
> > +/*
> > + * bank type for alive type
> > + * (CON bit field: 4, DAT bit field: 1, PUD bit field: 4, DRV bit field: 4)
> > + */
> > +static const struct samsung_pin_bank_type bank_type_7 = {
>
> Same problem.
Will fix
>
> > + .fld_width = { 4, 1, 4, 4, },
> > + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
> > +};
> > +
> > +/* pin banks of gs101 pin-controller (ALIVE) */
> > +static const struct samsung_pin_bank_data gs101_pin_alive[] = {
> > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 8, 0x0, "gpa0", 0x00, 0x00, FLT_SELECTABLE),
> > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 7, 0x20, "gpa1", 0x04, 0x08, FLT_SELECTABLE),
> > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 5, 0x40, "gpa2", 0x08, 0x10, FLT_SELECTABLE),
> > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 4, 0x60, "gpa3", 0x0c, 0x18, FLT_SELECTABLE),
> > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 4, 0x80, "gpa4", 0x10, 0x1c, FLT_SELECTABLE),
> > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 7, 0xa0, "gpa5", 0x14, 0x20, FLT_SELECTABLE),
> > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 8, 0xc0, "gpa9", 0x18, 0x28, FLT_SELECTABLE),
> > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 2, 0xe0, "gpa10", 0x1c, 0x30, FLT_SELECTABLE),
> > +};
> > +
> > +/* pin banks of gs101 pin-controller (FAR_ALIVE) */
> > +static const struct samsung_pin_bank_data gs101_pin_far_alive[] = {
> > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 8, 0x0, "gpa6", 0x00, 0x00, FLT_SELECTABLE),
> > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 4, 0x20, "gpa7", 0x04, 0x08, FLT_SELECTABLE),
> > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 8, 0x40, "gpa8", 0x08, 0x0c, FLT_SELECTABLE),
> > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 2, 0x60, "gpa11", 0x0c, 0x14, FLT_SELECTABLE),
> > +};
> > +
> > +/* pin banks of gs101 pin-controller (GSACORE) */
> > +static const struct samsung_pin_bank_data gs101_pin_gsacore[] = {
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x0, "gps0", 0x00, 0x00, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 8, 0x20, "gps1", 0x04, 0x04, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 3, 0x40, "gps2", 0x08, 0x0c, FLT_DEFAULT),
> > +};
> > +
> > +/* pin banks of gs101 pin-controller (GSACTRL) */
> > +static const struct samsung_pin_bank_data gs101_pin_gsactrl[] = {
> > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 6, 0x0, "gps3", 0x00, 0x00, FLT_DEFAULT),
> > +};
> > +
> > +/* pin banks of gs101 pin-controller (PERIC0) */
> > +static const struct samsung_pin_bank_data gs101_pin_peric0[] = {
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 5, 0x0, "gpp0", 0x00, 0x00, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x20, "gpp1", 0x04, 0x08, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x40, "gpp2", 0x08, 0x0c, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x60, "gpp3", 0x0c, 0x10, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x80, "gpp4", 0x10, 0x14, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0xa0, "gpp5", 0x14, 0x18, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0xc0, "gpp6", 0x18, 0x1c, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0xe0, "gpp7", 0x1c, 0x20, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x100, "gpp8", 0x20, 0x24, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x120, "gpp9", 0x24, 0x28, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x140, "gpp10", 0x28, 0x2c, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x160, "gpp11", 0x2c, 0x30, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x180, "gpp12", 0x30, 0x34, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x1a0, "gpp13", 0x34, 0x38, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x1c0, "gpp14", 0x38, 0x3c, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x1e0, "gpp15", 0x3c, 0x40, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x200, "gpp16", 0x40, 0x44, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x220, "gpp17", 0x44, 0x48, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x240, "gpp18", 0x48, 0x4c, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x260, "gpp19", 0x4c, 0x50, FLT_DEFAULT),
> > +};
> > +
> > +/* pin banks of gs101 pin-controller (PERIC1) */
> > +static const struct samsung_pin_bank_data gs101_pin_peric1[] = {
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 8, 0x0, "gpp20", 0x00, 0x00, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x20, "gpp21", 0x04, 0x08, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x40, "gpp22", 0x08, 0x0c, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 8, 0x60, "gpp23", 0x0c, 0x10, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x80, "gpp24", 0x10, 0x18, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0xa0, "gpp25", 0x14, 0x1c, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 5, 0xc0, "gpp26", 0x18, 0x20, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0xe0, "gpp27", 0x1c, 0x28, FLT_DEFAULT),
> > +};
> > +
> > +/* pin banks of gs101 pin-controller (HSI1) */
> > +static const struct samsung_pin_bank_data gs101_pin_hsi1[] = {
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 6, 0x0, "gph0", 0x00, 0x00, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 7, 0x20, "gph1", 0x04, 0x08, FLT_DEFAULT),
> > +};
> > +
> > +/* pin banks of gs101 pin-controller (HSI2) */
> > +static const struct samsung_pin_bank_data gs101_pin_hsi2[] = {
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 6, 0x0, "gph2", 0x00, 0x00, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x20, "gph3", 0x04, 0x08, FLT_DEFAULT),
> > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 6, 0x40, "gph4", 0x08, 0x0c, FLT_DEFAULT),
> > +};
> > +
> > +static const struct samsung_pin_ctrl gs101_pin_ctrl[] __initconst = {
> > + {
> > + /* pin banks of gs101 pin-controller (ALIVE) */
> > + .pin_banks = gs101_pin_alive,
> > + .nr_banks = ARRAY_SIZE(gs101_pin_alive),
> > + .eint_gpio_init = exynos_eint_gpio_init,
> > + .eint_wkup_init = exynos_eint_wkup_init,
> > + .suspend = exynos_pinctrl_suspend,
> > + .resume = exynos_pinctrl_resume,
> > + }, {
> > + /* pin banks of gs101 pin-controller (FAR_ALIVE) */
> > + .pin_banks = gs101_pin_far_alive,
> > + .nr_banks = ARRAY_SIZE(gs101_pin_far_alive),
> > + .eint_gpio_init = exynos_eint_gpio_init,
> > + .eint_wkup_init = exynos_eint_wkup_init,
> > + .suspend = exynos_pinctrl_suspend,
> > + .resume = exynos_pinctrl_resume,
> > + }, {
> > + /* pin banks of gs101 pin-controller (GSACORE) */
> > + .pin_banks = gs101_pin_gsacore,
> > + .nr_banks = ARRAY_SIZE(gs101_pin_gsacore),
> > + .eint_gpio_init = exynos_eint_gpio_init,
> > + }, {
> > + /* pin banks of gs101 pin-controller (GSACTRL) */
> > + .pin_banks = gs101_pin_gsactrl,
> > + .nr_banks = ARRAY_SIZE(gs101_pin_gsactrl),
> > + .eint_gpio_init = exynos_eint_gpio_init,
> > + }, {
> > + /* pin banks of gs101 pin-controller (PERIC0) */
> > + .pin_banks = gs101_pin_peric0,
> > + .nr_banks = ARRAY_SIZE(gs101_pin_peric0),
> > + .eint_gpio_init = exynos_eint_gpio_init,
> > + .suspend = exynos_pinctrl_suspend,
> > + .resume = exynos_pinctrl_resume,
> > + }, {
> > + /* pin banks of gs101 pin-controller (PERIC1) */
> > + .pin_banks = gs101_pin_peric1,
> > + .nr_banks = ARRAY_SIZE(gs101_pin_peric1),
> > + .eint_gpio_init = exynos_eint_gpio_init,
> > + .suspend = exynos_pinctrl_suspend,
> > + .resume = exynos_pinctrl_resume,
> > + }, {
> > + /* pin banks of gs101 pin-controller (HSI1) */
> > + .pin_banks = gs101_pin_hsi1,
> > + .nr_banks = ARRAY_SIZE(gs101_pin_hsi1),
> > + .eint_gpio_init = exynos_eint_gpio_init,
> > + .suspend = exynos_pinctrl_suspend,
> > + .resume = exynos_pinctrl_resume,
> > + }, {
> > + /* pin banks of gs101 pin-controller (HSI2) */
> > + .pin_banks = gs101_pin_hsi2,
> > + .nr_banks = ARRAY_SIZE(gs101_pin_hsi2),
> > + .eint_gpio_init = exynos_eint_gpio_init,
> > + .suspend = exynos_pinctrl_suspend,
> > + .resume = exynos_pinctrl_resume,
> > + },
> > +};
> > +
> > +const struct samsung_pinctrl_of_match_data gs101_of_data __initconst = {
> > + .ctrl = gs101_pin_ctrl,
> > + .num_ctrl = ARRAY_SIZE(gs101_pin_ctrl),
> > +};
> > diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
> > index a8212fc126bf..0c6c3312abb7 100644
> > --- a/drivers/pinctrl/samsung/pinctrl-exynos.c
> > +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
> > @@ -269,6 +269,50 @@ struct exynos_eint_gpio_save {
> > u32 eint_mask;
> > };
>
> Please split the patch into two: one of adding new filter code and
> second for new Google SoC.
Will do
>
> >
> > +static void exynos_eint_flt_config(int sel, int width,
> > + struct samsung_pinctrl_drv_data *d,
> > + struct samsung_pin_bank *bank)
>
> Arguments: first drv_data, then bank, then width, then sel... and what
> is sel actually?
Will fix.
Sel parameter is just setting the FLT_SEL bitfield
0 = Delay filter
1 = Digital filter
>
> Also, why do you need width if it is always 0? Will it be different in
> next pinctrl controllers?
The downstream driver never set the width bitfield so I we could remove
this width logic and add it back if it's ever required.
> So the filter is per entire bank?
The filter is selectable per pin. So each pin has a FLT_EN, FLT_SEL and
FLT_WIDTH bitfield.
>
> > +{
> > + unsigned int flt_reg, flt_con = 0;
> > + unsigned int val, shift;
> > + int i;
> > + int loop_cnt;
> > +
> > + flt_con |= EXYNOS_FLTCON_EN;
> > +
> > + if (sel)
> > + flt_con |= EXYNOS_FLTCON_SEL_DIGITAL;
> > +
> > + flt_con |= EXYNOS_FLTCON_WIDTH(width);
>
> This is always 0, what's the point?
Yeah we could remove this, and add it back if it's ever required. Let
me know if that's what you prefer?
>
> > +
> > + flt_reg = EXYNOS_GPIO_EFLTCON_OFFSET + bank->fltcon_offset;
> > +
> > + if (bank->nr_pins > EXYNOS_FLTCON_NR_PIN)
> > + /*
> > + * if nr_pins > 4, we should set FLTCON0 register fully.
> > + * (pin0 ~ 3). So loop 4 times in case of FLTCON0.
> > + */
> > + loop_cnt = 4;
> > + else
> > + loop_cnt = bank->nr_pins;
>
> Please document the layout of the registers in exynos_eint_flt_config()
> comment (not kerneldoc). Also document what do you want to achieve here
> - set entire bank to one filter for the suspend/resume?
Yes exactly it is looping through setting all the pins in the bank to
one filter on
suspend and resume. I will add a comment as you suggest.
>
> > +
> > + val = readl(d->virt_base + flt_reg);
> > +
> > + for (i = 0; i < loop_cnt; i++) {
> > + shift = i * EXYNOS_FLTCON_LEN;
> > + val &= ~(EXYNOS_FLTCON_MASK << shift);
> > + val |= (flt_con << shift);
> > + }
> > +
> > + writel(val, d->virt_base + flt_reg);
> > +
>
> Missing /*
Will fix
>
> > + /* if nr_pins > 4, we should also set FLTCON1 register like FLTCON0.
> > + * (pin4 ~ )
> > + */
> > + if (bank->nr_pins > EXYNOS_FLTCON_NR_PIN)
> > + writel(val, d->virt_base + flt_reg + 0x4);
> > +}
> > +
> > /*
> > * exynos_eint_gpio_init() - setup handling of external gpio interrupts.
> > * @d: driver data of samsung pinctrl driver.
> > @@ -321,6 +365,10 @@ __init int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
> > goto err_domains;
> > }
> >
> > + /* Set Delay Analog Filter */
> > + if (bank->fltcon_type != FLT_DEFAULT)
> > + exynos_eint_flt_config(EXYNOS_FLTCON_SEL_DELAY,
> > + 0, d, bank);
> > }
> >
> > return 0;
> > @@ -555,6 +603,11 @@ __init int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
> > if (bank->eint_type != EINT_TYPE_WKUP)
> > continue;
> >
> > + /* Set Digital Filter */
> > + if (bank->fltcon_type != FLT_DEFAULT)
> > + exynos_eint_flt_config(EXYNOS_FLTCON_SEL_DIGITAL,
> > + 0, d, bank);
> > +
> > bank->irq_chip = devm_kmemdup(dev, irq_chip, sizeof(*irq_chip),
> > GFP_KERNEL);
> > if (!bank->irq_chip) {
> > @@ -658,6 +711,7 @@ static void exynos_pinctrl_suspend_bank(
> > void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata)
> > {
> > struct samsung_pin_bank *bank = drvdata->pin_banks;
> > + struct samsung_pinctrl_drv_data *d = bank->drvdata;
> > struct exynos_irq_chip *irq_chip = NULL;
> > int i;
> >
> > @@ -665,6 +719,10 @@ void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata)
> > if (bank->eint_type == EINT_TYPE_GPIO)
> > exynos_pinctrl_suspend_bank(drvdata, bank);
> > else if (bank->eint_type == EINT_TYPE_WKUP) {
> > + /* Setting Delay (Analog) Filter */
> > + if (bank->fltcon_type != FLT_DEFAULT)
> > + exynos_eint_flt_config(EXYNOS_FLTCON_SEL_DELAY,
> > + 0, d, bank);
> > if (!irq_chip) {
> > irq_chip = bank->irq_chip;
> > irq_chip->set_eint_wakeup_mask(drvdata,
> > @@ -707,11 +765,19 @@ static void exynos_pinctrl_resume_bank(
> > void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata)
> > {
> > struct samsung_pin_bank *bank = drvdata->pin_banks;
> > + struct samsung_pinctrl_drv_data *d = bank->drvdata;
> > int i;
> >
> > for (i = 0; i < drvdata->nr_banks; ++i, ++bank)
> > - if (bank->eint_type == EINT_TYPE_GPIO)
> > + if (bank->eint_type == EINT_TYPE_GPIO) {
> > exynos_pinctrl_resume_bank(drvdata, bank);
> > + } else if (bank->eint_type == EINT_TYPE_WKUP ||
> > + bank->eint_type == EINT_TYPE_WKUP_MUX) {
> > + /* Set Digital Filter */
> > + if (bank->fltcon_type != FLT_DEFAULT)
> > + exynos_eint_flt_config(EXYNOS_FLTCON_SEL_DIGITAL,
> > + 0, d, bank);
> > + }
> > }
> >
> > static void exynos_retention_enable(struct samsung_pinctrl_drv_data *drvdata)
> > diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h
> > index 7bd6d82c9f36..aafd8f9f52f8 100644
> > --- a/drivers/pinctrl/samsung/pinctrl-exynos.h
> > +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h
> > @@ -16,6 +16,8 @@
> > #ifndef __PINCTRL_SAMSUNG_EXYNOS_H
> > #define __PINCTRL_SAMSUNG_EXYNOS_H
> >
> > +#include <linux/bitfield.h>
> > +
>
> I don't think you use in this header anything from bitfield.
>
> > /* Values for the pin CON register */
> > #define EXYNOS_PIN_CON_FUNC_EINT 0xf
> >
> > @@ -50,6 +52,14 @@
> >
> > #define EXYNOS_EINT_MAX_PER_BANK 8
> > #define EXYNOS_EINT_NR_WKUP_EINT
> > +/* EINT filter configuration */
> > +#define EXYNOS_FLTCON_EN BIT(7)
>
> EXYNOS9? Earlier variants did not have it, AFAIR.
Will fix
>
> > +#define EXYNOS_FLTCON_SEL_DIGITAL BIT(6)
> > +#define EXYNOS_FLTCON_SEL_DELAY 0
> > +#define EXYNOS_FLTCON_WIDTH(x) ((x) & 0x3f)
> > +#define EXYNOS_FLTCON_MASK 0xFF
>
> Keep lowercase hex
Will fix
Kind regards,
Peter.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 150+ messages in thread
* [PATCH 17/21] watchdog: s3c2410_wdt: Add support for Google tensor SoCs
2023-10-05 15:55 ` Peter Griffin
@ 2023-10-05 15:56 ` Peter Griffin
-1 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-05 15:56 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi
Cc: peter.griffin, tudor.ambarus, andre.draszik, semen.protsenko,
soc, devicetree, linux-arm-kernel, linux-samsung-soc, linux-clk,
linux-gpio, linux-watchdog
This patch adds the compatibles and drvdata for the Google
gs101 & gs201 SoCs found in Pixel 6 and Pixel 7 phones. Similar
to Exynos850 it has two watchdog instances, one for each cluster
and has some control bits in PMU registers.
The watchdog IP found in gs101 SoCs also supports a few
additional bits/features in the WTCON register which we add
support for and an additional register detailed below.
dbgack-mask - Enables masking WDT interrupt and reset request
according to asserted DBGACK input
windowed-mode - Enabled Windowed watchdog mode
Windowed watchdog mode also has an additional register WTMINCNT.
If windowed watchdog is enabled and you reload WTCNT when the
value is greater than WTMINCNT, it prompts interrupt or reset
request as if the watchdog time has expired.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
drivers/watchdog/s3c2410_wdt.c | 116 +++++++++++++++++++++++++++++----
1 file changed, 105 insertions(+), 11 deletions(-)
diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c
index 0b4bd883ff28..4c23c7e6a3f1 100644
--- a/drivers/watchdog/s3c2410_wdt.c
+++ b/drivers/watchdog/s3c2410_wdt.c
@@ -31,12 +31,14 @@
#define S3C2410_WTDAT 0x04
#define S3C2410_WTCNT 0x08
#define S3C2410_WTCLRINT 0x0c
-
+#define S3C2410_WTMINCNT 0x10
#define S3C2410_WTCNT_MAXCNT 0xffff
-#define S3C2410_WTCON_RSTEN (1 << 0)
-#define S3C2410_WTCON_INTEN (1 << 2)
-#define S3C2410_WTCON_ENABLE (1 << 5)
+#define S3C2410_WTCON_RSTEN (1 << 0)
+#define S3C2410_WTCON_INTEN (1 << 2)
+#define S3C2410_WTCON_ENABLE (1 << 5)
+#define S3C2410_WTCON_DBGACK_MASK (1 << 16)
+#define S3C2410_WTCON_WINDOWED_WD (1 << 20)
#define S3C2410_WTCON_DIV16 (0 << 3)
#define S3C2410_WTCON_DIV32 (1 << 3)
@@ -61,12 +63,16 @@
#define EXYNOS850_CLUSTER1_NONCPU_INT_EN 0x1644
#define EXYNOSAUTOV9_CLUSTER1_NONCPU_OUT 0x1520
#define EXYNOSAUTOV9_CLUSTER1_NONCPU_INT_EN 0x1544
-
#define EXYNOS850_CLUSTER0_WDTRESET_BIT 24
#define EXYNOS850_CLUSTER1_WDTRESET_BIT 23
#define EXYNOSAUTOV9_CLUSTER0_WDTRESET_BIT 25
#define EXYNOSAUTOV9_CLUSTER1_WDTRESET_BIT 24
-
+#define GS_CLUSTER0_NONCPU_OUT 0x1220
+#define GS_CLUSTER1_NONCPU_OUT 0x1420
+#define GS_CLUSTER0_NONCPU_INT_EN 0x1244
+#define GS_CLUSTER1_NONCPU_INT_EN 0x1444
+#define GS_CLUSTER2_NONCPU_INT_EN 0x1644
+#define GS_RST_STAT_REG_OFFSET 0x3B44
/**
* DOC: Quirk flags for different Samsung watchdog IP-cores
*
@@ -106,6 +112,8 @@
#define QUIRK_HAS_PMU_RST_STAT (1 << 2)
#define QUIRK_HAS_PMU_AUTO_DISABLE (1 << 3)
#define QUIRK_HAS_PMU_CNT_EN (1 << 4)
+#define QUIRK_HAS_DBGACK_BIT (1 << 5)
+#define QUIRK_HAS_WTMINCNT_REG (1 << 6)
/* These quirks require that we have a PMU register map */
#define QUIRKS_HAVE_PMUREG \
@@ -263,6 +271,54 @@ static const struct s3c2410_wdt_variant drv_data_exynosautov9_cl1 = {
QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN,
};
+static const struct s3c2410_wdt_variant drv_data_gs101_cl0 = {
+ .mask_reset_reg = GS_CLUSTER0_NONCPU_INT_EN,
+ .mask_bit = 2,
+ .mask_reset_inv = true,
+ .rst_stat_reg = GS_RST_STAT_REG_OFFSET,
+ .rst_stat_bit = 0,
+ .cnt_en_reg = GS_CLUSTER0_NONCPU_OUT,
+ .cnt_en_bit = 8,
+ .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN |
+ QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG,
+};
+
+static const struct s3c2410_wdt_variant drv_data_gs101_cl1 = {
+ .mask_reset_reg = GS_CLUSTER1_NONCPU_INT_EN,
+ .mask_bit = 2,
+ .mask_reset_inv = true,
+ .rst_stat_reg = GS_RST_STAT_REG_OFFSET,
+ .rst_stat_bit = 1,
+ .cnt_en_reg = GS_CLUSTER1_NONCPU_OUT,
+ .cnt_en_bit = 7,
+ .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN |
+ QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG,
+};
+
+static const struct s3c2410_wdt_variant drv_data_gs201_cl0 = {
+ .mask_reset_reg = GS_CLUSTER0_NONCPU_INT_EN,
+ .mask_bit = 2,
+ .mask_reset_inv = true,
+ .rst_stat_reg = GS_RST_STAT_REG_OFFSET,
+ .rst_stat_bit = 0,
+ .cnt_en_reg = GS_CLUSTER0_NONCPU_OUT,
+ .cnt_en_bit = 8,
+ .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN |
+ QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG,
+};
+
+static const struct s3c2410_wdt_variant drv_data_gs201_cl1 = {
+ .mask_reset_reg = GS_CLUSTER1_NONCPU_INT_EN,
+ .mask_bit = 2,
+ .mask_reset_inv = true,
+ .rst_stat_reg = GS_RST_STAT_REG_OFFSET,
+ .rst_stat_bit = 1,
+ .cnt_en_reg = GS_CLUSTER1_NONCPU_OUT,
+ .cnt_en_bit = 7,
+ .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN |
+ QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG,
+};
+
static const struct of_device_id s3c2410_wdt_match[] = {
{ .compatible = "samsung,s3c2410-wdt",
.data = &drv_data_s3c2410 },
@@ -278,6 +334,10 @@ static const struct of_device_id s3c2410_wdt_match[] = {
.data = &drv_data_exynos850_cl0 },
{ .compatible = "samsung,exynosautov9-wdt",
.data = &drv_data_exynosautov9_cl0 },
+ { .compatible = "google,gs101-wdt",
+ .data = &drv_data_gs101_cl0 },
+ { .compatible = "google,gs201-wdt",
+ .data = &drv_data_gs201_cl0 },
{},
};
MODULE_DEVICE_TABLE(of, s3c2410_wdt_match);
@@ -375,6 +435,21 @@ static int s3c2410wdt_enable(struct s3c2410_wdt *wdt, bool en)
return 0;
}
+static void s3c2410wdt_mask_dbgack(struct s3c2410_wdt *wdt, bool mask)
+{
+ unsigned long wtcon;
+
+ if (!(wdt->drv_data->quirks & QUIRK_HAS_DBGACK_BIT))
+ return;
+
+ wtcon = readl(wdt->reg_base + S3C2410_WTCON);
+ if (mask)
+ wtcon |= S3C2410_WTCON_DBGACK_MASK;
+ else
+ wtcon &= ~S3C2410_WTCON_DBGACK_MASK;
+ writel(wtcon, wdt->reg_base + S3C2410_WTCON);
+}
+
static int s3c2410wdt_keepalive(struct watchdog_device *wdd)
{
struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
@@ -585,9 +660,11 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt)
}
#ifdef CONFIG_OF
- /* Choose Exynos850/ExynosAutov9 driver data w.r.t. cluster index */
+ /* Choose Exynos850/ExynosAutov9/gsx01 driver data w.r.t. cluster index */
if (variant == &drv_data_exynos850_cl0 ||
- variant == &drv_data_exynosautov9_cl0) {
+ variant == &drv_data_exynosautov9_cl0 ||
+ variant == &drv_data_gs101_cl0 ||
+ variant == &drv_data_gs201_cl0) {
u32 index;
int err;
@@ -600,9 +677,14 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt)
case 0:
break;
case 1:
- variant = (variant == &drv_data_exynos850_cl0) ?
- &drv_data_exynos850_cl1 :
- &drv_data_exynosautov9_cl1;
+ if (variant == &drv_data_exynos850_cl0)
+ variant = &drv_data_exynos850_cl1;
+ else if (variant == &drv_data_exynosautov9_cl0)
+ variant = &drv_data_exynosautov9_cl1;
+ else if (variant == &drv_data_gs101_cl0)
+ variant = &drv_data_gs101_cl1;
+ else if (variant == &drv_data_gs201_cl0)
+ variant = &drv_data_gs201_cl1;
break;
default:
return dev_err_probe(dev, -EINVAL, "wrong cluster index: %u\n", index);
@@ -700,6 +782,8 @@ static int s3c2410wdt_probe(struct platform_device *pdev)
wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt);
wdt->wdt_device.parent = dev;
+ s3c2410wdt_mask_dbgack(wdt, true);
+
/*
* If "tmr_atboot" param is non-zero, start the watchdog right now. Also
* set WDOG_HW_RUNNING bit, so that watchdog core can kick the watchdog.
@@ -712,6 +796,7 @@ static int s3c2410wdt_probe(struct platform_device *pdev)
s3c2410wdt_start(&wdt->wdt_device);
set_bit(WDOG_HW_RUNNING, &wdt->wdt_device.status);
} else {
+ dev_info(dev, "stopping watchdog timer\n");
s3c2410wdt_stop(&wdt->wdt_device);
}
@@ -738,6 +823,15 @@ static int s3c2410wdt_probe(struct platform_device *pdev)
(wtcon & S3C2410_WTCON_RSTEN) ? "en" : "dis",
(wtcon & S3C2410_WTCON_INTEN) ? "en" : "dis");
+ if (wdt->drv_data->quirks & QUIRK_HAS_DBGACK_BIT)
+ dev_info(dev, "DBGACK %sabled\n",
+ (wtcon & S3C2410_WTCON_DBGACK_MASK) ? "en" : "dis");
+
+ if (wdt->drv_data->quirks & QUIRK_HAS_WTMINCNT_REG)
+ dev_info(dev, "windowed watchdog %sabled, wtmincnt=%x\n",
+ (wtcon & S3C2410_WTCON_WINDOWED_WD) ? "en" : "dis",
+ readl(wdt->reg_base + S3C2410_WTMINCNT));
+
return 0;
}
--
2.42.0.582.g8ccd20d70d-goog
^ permalink raw reply related [flat|nested] 150+ messages in thread* [PATCH 17/21] watchdog: s3c2410_wdt: Add support for Google tensor SoCs
@ 2023-10-05 15:56 ` Peter Griffin
0 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-05 15:56 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi
Cc: peter.griffin, tudor.ambarus, andre.draszik, semen.protsenko,
soc, devicetree, linux-arm-kernel, linux-samsung-soc, linux-clk,
linux-gpio, linux-watchdog
This patch adds the compatibles and drvdata for the Google
gs101 & gs201 SoCs found in Pixel 6 and Pixel 7 phones. Similar
to Exynos850 it has two watchdog instances, one for each cluster
and has some control bits in PMU registers.
The watchdog IP found in gs101 SoCs also supports a few
additional bits/features in the WTCON register which we add
support for and an additional register detailed below.
dbgack-mask - Enables masking WDT interrupt and reset request
according to asserted DBGACK input
windowed-mode - Enabled Windowed watchdog mode
Windowed watchdog mode also has an additional register WTMINCNT.
If windowed watchdog is enabled and you reload WTCNT when the
value is greater than WTMINCNT, it prompts interrupt or reset
request as if the watchdog time has expired.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
drivers/watchdog/s3c2410_wdt.c | 116 +++++++++++++++++++++++++++++----
1 file changed, 105 insertions(+), 11 deletions(-)
diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c
index 0b4bd883ff28..4c23c7e6a3f1 100644
--- a/drivers/watchdog/s3c2410_wdt.c
+++ b/drivers/watchdog/s3c2410_wdt.c
@@ -31,12 +31,14 @@
#define S3C2410_WTDAT 0x04
#define S3C2410_WTCNT 0x08
#define S3C2410_WTCLRINT 0x0c
-
+#define S3C2410_WTMINCNT 0x10
#define S3C2410_WTCNT_MAXCNT 0xffff
-#define S3C2410_WTCON_RSTEN (1 << 0)
-#define S3C2410_WTCON_INTEN (1 << 2)
-#define S3C2410_WTCON_ENABLE (1 << 5)
+#define S3C2410_WTCON_RSTEN (1 << 0)
+#define S3C2410_WTCON_INTEN (1 << 2)
+#define S3C2410_WTCON_ENABLE (1 << 5)
+#define S3C2410_WTCON_DBGACK_MASK (1 << 16)
+#define S3C2410_WTCON_WINDOWED_WD (1 << 20)
#define S3C2410_WTCON_DIV16 (0 << 3)
#define S3C2410_WTCON_DIV32 (1 << 3)
@@ -61,12 +63,16 @@
#define EXYNOS850_CLUSTER1_NONCPU_INT_EN 0x1644
#define EXYNOSAUTOV9_CLUSTER1_NONCPU_OUT 0x1520
#define EXYNOSAUTOV9_CLUSTER1_NONCPU_INT_EN 0x1544
-
#define EXYNOS850_CLUSTER0_WDTRESET_BIT 24
#define EXYNOS850_CLUSTER1_WDTRESET_BIT 23
#define EXYNOSAUTOV9_CLUSTER0_WDTRESET_BIT 25
#define EXYNOSAUTOV9_CLUSTER1_WDTRESET_BIT 24
-
+#define GS_CLUSTER0_NONCPU_OUT 0x1220
+#define GS_CLUSTER1_NONCPU_OUT 0x1420
+#define GS_CLUSTER0_NONCPU_INT_EN 0x1244
+#define GS_CLUSTER1_NONCPU_INT_EN 0x1444
+#define GS_CLUSTER2_NONCPU_INT_EN 0x1644
+#define GS_RST_STAT_REG_OFFSET 0x3B44
/**
* DOC: Quirk flags for different Samsung watchdog IP-cores
*
@@ -106,6 +112,8 @@
#define QUIRK_HAS_PMU_RST_STAT (1 << 2)
#define QUIRK_HAS_PMU_AUTO_DISABLE (1 << 3)
#define QUIRK_HAS_PMU_CNT_EN (1 << 4)
+#define QUIRK_HAS_DBGACK_BIT (1 << 5)
+#define QUIRK_HAS_WTMINCNT_REG (1 << 6)
/* These quirks require that we have a PMU register map */
#define QUIRKS_HAVE_PMUREG \
@@ -263,6 +271,54 @@ static const struct s3c2410_wdt_variant drv_data_exynosautov9_cl1 = {
QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN,
};
+static const struct s3c2410_wdt_variant drv_data_gs101_cl0 = {
+ .mask_reset_reg = GS_CLUSTER0_NONCPU_INT_EN,
+ .mask_bit = 2,
+ .mask_reset_inv = true,
+ .rst_stat_reg = GS_RST_STAT_REG_OFFSET,
+ .rst_stat_bit = 0,
+ .cnt_en_reg = GS_CLUSTER0_NONCPU_OUT,
+ .cnt_en_bit = 8,
+ .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN |
+ QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG,
+};
+
+static const struct s3c2410_wdt_variant drv_data_gs101_cl1 = {
+ .mask_reset_reg = GS_CLUSTER1_NONCPU_INT_EN,
+ .mask_bit = 2,
+ .mask_reset_inv = true,
+ .rst_stat_reg = GS_RST_STAT_REG_OFFSET,
+ .rst_stat_bit = 1,
+ .cnt_en_reg = GS_CLUSTER1_NONCPU_OUT,
+ .cnt_en_bit = 7,
+ .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN |
+ QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG,
+};
+
+static const struct s3c2410_wdt_variant drv_data_gs201_cl0 = {
+ .mask_reset_reg = GS_CLUSTER0_NONCPU_INT_EN,
+ .mask_bit = 2,
+ .mask_reset_inv = true,
+ .rst_stat_reg = GS_RST_STAT_REG_OFFSET,
+ .rst_stat_bit = 0,
+ .cnt_en_reg = GS_CLUSTER0_NONCPU_OUT,
+ .cnt_en_bit = 8,
+ .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN |
+ QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG,
+};
+
+static const struct s3c2410_wdt_variant drv_data_gs201_cl1 = {
+ .mask_reset_reg = GS_CLUSTER1_NONCPU_INT_EN,
+ .mask_bit = 2,
+ .mask_reset_inv = true,
+ .rst_stat_reg = GS_RST_STAT_REG_OFFSET,
+ .rst_stat_bit = 1,
+ .cnt_en_reg = GS_CLUSTER1_NONCPU_OUT,
+ .cnt_en_bit = 7,
+ .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN |
+ QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG,
+};
+
static const struct of_device_id s3c2410_wdt_match[] = {
{ .compatible = "samsung,s3c2410-wdt",
.data = &drv_data_s3c2410 },
@@ -278,6 +334,10 @@ static const struct of_device_id s3c2410_wdt_match[] = {
.data = &drv_data_exynos850_cl0 },
{ .compatible = "samsung,exynosautov9-wdt",
.data = &drv_data_exynosautov9_cl0 },
+ { .compatible = "google,gs101-wdt",
+ .data = &drv_data_gs101_cl0 },
+ { .compatible = "google,gs201-wdt",
+ .data = &drv_data_gs201_cl0 },
{},
};
MODULE_DEVICE_TABLE(of, s3c2410_wdt_match);
@@ -375,6 +435,21 @@ static int s3c2410wdt_enable(struct s3c2410_wdt *wdt, bool en)
return 0;
}
+static void s3c2410wdt_mask_dbgack(struct s3c2410_wdt *wdt, bool mask)
+{
+ unsigned long wtcon;
+
+ if (!(wdt->drv_data->quirks & QUIRK_HAS_DBGACK_BIT))
+ return;
+
+ wtcon = readl(wdt->reg_base + S3C2410_WTCON);
+ if (mask)
+ wtcon |= S3C2410_WTCON_DBGACK_MASK;
+ else
+ wtcon &= ~S3C2410_WTCON_DBGACK_MASK;
+ writel(wtcon, wdt->reg_base + S3C2410_WTCON);
+}
+
static int s3c2410wdt_keepalive(struct watchdog_device *wdd)
{
struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
@@ -585,9 +660,11 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt)
}
#ifdef CONFIG_OF
- /* Choose Exynos850/ExynosAutov9 driver data w.r.t. cluster index */
+ /* Choose Exynos850/ExynosAutov9/gsx01 driver data w.r.t. cluster index */
if (variant == &drv_data_exynos850_cl0 ||
- variant == &drv_data_exynosautov9_cl0) {
+ variant == &drv_data_exynosautov9_cl0 ||
+ variant == &drv_data_gs101_cl0 ||
+ variant == &drv_data_gs201_cl0) {
u32 index;
int err;
@@ -600,9 +677,14 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt)
case 0:
break;
case 1:
- variant = (variant == &drv_data_exynos850_cl0) ?
- &drv_data_exynos850_cl1 :
- &drv_data_exynosautov9_cl1;
+ if (variant == &drv_data_exynos850_cl0)
+ variant = &drv_data_exynos850_cl1;
+ else if (variant == &drv_data_exynosautov9_cl0)
+ variant = &drv_data_exynosautov9_cl1;
+ else if (variant == &drv_data_gs101_cl0)
+ variant = &drv_data_gs101_cl1;
+ else if (variant == &drv_data_gs201_cl0)
+ variant = &drv_data_gs201_cl1;
break;
default:
return dev_err_probe(dev, -EINVAL, "wrong cluster index: %u\n", index);
@@ -700,6 +782,8 @@ static int s3c2410wdt_probe(struct platform_device *pdev)
wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt);
wdt->wdt_device.parent = dev;
+ s3c2410wdt_mask_dbgack(wdt, true);
+
/*
* If "tmr_atboot" param is non-zero, start the watchdog right now. Also
* set WDOG_HW_RUNNING bit, so that watchdog core can kick the watchdog.
@@ -712,6 +796,7 @@ static int s3c2410wdt_probe(struct platform_device *pdev)
s3c2410wdt_start(&wdt->wdt_device);
set_bit(WDOG_HW_RUNNING, &wdt->wdt_device.status);
} else {
+ dev_info(dev, "stopping watchdog timer\n");
s3c2410wdt_stop(&wdt->wdt_device);
}
@@ -738,6 +823,15 @@ static int s3c2410wdt_probe(struct platform_device *pdev)
(wtcon & S3C2410_WTCON_RSTEN) ? "en" : "dis",
(wtcon & S3C2410_WTCON_INTEN) ? "en" : "dis");
+ if (wdt->drv_data->quirks & QUIRK_HAS_DBGACK_BIT)
+ dev_info(dev, "DBGACK %sabled\n",
+ (wtcon & S3C2410_WTCON_DBGACK_MASK) ? "en" : "dis");
+
+ if (wdt->drv_data->quirks & QUIRK_HAS_WTMINCNT_REG)
+ dev_info(dev, "windowed watchdog %sabled, wtmincnt=%x\n",
+ (wtcon & S3C2410_WTCON_WINDOWED_WD) ? "en" : "dis",
+ readl(wdt->reg_base + S3C2410_WTMINCNT));
+
return 0;
}
--
2.42.0.582.g8ccd20d70d-goog
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 150+ messages in thread* Re: [PATCH 17/21] watchdog: s3c2410_wdt: Add support for Google tensor SoCs
2023-10-05 15:56 ` Peter Griffin
@ 2023-10-05 18:58 ` Guenter Roeck
-1 siblings, 0 replies; 150+ messages in thread
From: Guenter Roeck @ 2023-10-05 18:58 UTC (permalink / raw)
To: Peter Griffin
Cc: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, catalin.marinas,
will, arnd, olof, cw00.choi, tudor.ambarus, andre.draszik,
semen.protsenko, soc, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-clk, linux-gpio, linux-watchdog
On Thu, Oct 05, 2023 at 04:56:14PM +0100, Peter Griffin wrote:
> This patch adds the compatibles and drvdata for the Google
> gs101 & gs201 SoCs found in Pixel 6 and Pixel 7 phones. Similar
> to Exynos850 it has two watchdog instances, one for each cluster
> and has some control bits in PMU registers.
>
> The watchdog IP found in gs101 SoCs also supports a few
> additional bits/features in the WTCON register which we add
> support for and an additional register detailed below.
>
> dbgack-mask - Enables masking WDT interrupt and reset request
> according to asserted DBGACK input
>
> windowed-mode - Enabled Windowed watchdog mode
>
> Windowed watchdog mode also has an additional register WTMINCNT.
> If windowed watchdog is enabled and you reload WTCNT when the
> value is greater than WTMINCNT, it prompts interrupt or reset
> request as if the watchdog time has expired.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> drivers/watchdog/s3c2410_wdt.c | 116 +++++++++++++++++++++++++++++----
> 1 file changed, 105 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c
> index 0b4bd883ff28..4c23c7e6a3f1 100644
> --- a/drivers/watchdog/s3c2410_wdt.c
> +++ b/drivers/watchdog/s3c2410_wdt.c
> @@ -31,12 +31,14 @@
> #define S3C2410_WTDAT 0x04
> #define S3C2410_WTCNT 0x08
> #define S3C2410_WTCLRINT 0x0c
> -
> +#define S3C2410_WTMINCNT 0x10
> #define S3C2410_WTCNT_MAXCNT 0xffff
>
> -#define S3C2410_WTCON_RSTEN (1 << 0)
> -#define S3C2410_WTCON_INTEN (1 << 2)
> -#define S3C2410_WTCON_ENABLE (1 << 5)
> +#define S3C2410_WTCON_RSTEN (1 << 0)
> +#define S3C2410_WTCON_INTEN (1 << 2)
> +#define S3C2410_WTCON_ENABLE (1 << 5)
> +#define S3C2410_WTCON_DBGACK_MASK (1 << 16)
> +#define S3C2410_WTCON_WINDOWED_WD (1 << 20)
>
> #define S3C2410_WTCON_DIV16 (0 << 3)
> #define S3C2410_WTCON_DIV32 (1 << 3)
> @@ -61,12 +63,16 @@
> #define EXYNOS850_CLUSTER1_NONCPU_INT_EN 0x1644
> #define EXYNOSAUTOV9_CLUSTER1_NONCPU_OUT 0x1520
> #define EXYNOSAUTOV9_CLUSTER1_NONCPU_INT_EN 0x1544
> -
> #define EXYNOS850_CLUSTER0_WDTRESET_BIT 24
> #define EXYNOS850_CLUSTER1_WDTRESET_BIT 23
> #define EXYNOSAUTOV9_CLUSTER0_WDTRESET_BIT 25
> #define EXYNOSAUTOV9_CLUSTER1_WDTRESET_BIT 24
> -
> +#define GS_CLUSTER0_NONCPU_OUT 0x1220
> +#define GS_CLUSTER1_NONCPU_OUT 0x1420
> +#define GS_CLUSTER0_NONCPU_INT_EN 0x1244
> +#define GS_CLUSTER1_NONCPU_INT_EN 0x1444
> +#define GS_CLUSTER2_NONCPU_INT_EN 0x1644
> +#define GS_RST_STAT_REG_OFFSET 0x3B44
> /**
> * DOC: Quirk flags for different Samsung watchdog IP-cores
> *
> @@ -106,6 +112,8 @@
> #define QUIRK_HAS_PMU_RST_STAT (1 << 2)
> #define QUIRK_HAS_PMU_AUTO_DISABLE (1 << 3)
> #define QUIRK_HAS_PMU_CNT_EN (1 << 4)
> +#define QUIRK_HAS_DBGACK_BIT (1 << 5)
> +#define QUIRK_HAS_WTMINCNT_REG (1 << 6)
>
> /* These quirks require that we have a PMU register map */
> #define QUIRKS_HAVE_PMUREG \
> @@ -263,6 +271,54 @@ static const struct s3c2410_wdt_variant drv_data_exynosautov9_cl1 = {
> QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN,
> };
>
> +static const struct s3c2410_wdt_variant drv_data_gs101_cl0 = {
> + .mask_reset_reg = GS_CLUSTER0_NONCPU_INT_EN,
> + .mask_bit = 2,
> + .mask_reset_inv = true,
> + .rst_stat_reg = GS_RST_STAT_REG_OFFSET,
> + .rst_stat_bit = 0,
> + .cnt_en_reg = GS_CLUSTER0_NONCPU_OUT,
> + .cnt_en_bit = 8,
> + .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN |
> + QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG,
> +};
> +
> +static const struct s3c2410_wdt_variant drv_data_gs101_cl1 = {
> + .mask_reset_reg = GS_CLUSTER1_NONCPU_INT_EN,
> + .mask_bit = 2,
> + .mask_reset_inv = true,
> + .rst_stat_reg = GS_RST_STAT_REG_OFFSET,
> + .rst_stat_bit = 1,
> + .cnt_en_reg = GS_CLUSTER1_NONCPU_OUT,
> + .cnt_en_bit = 7,
> + .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN |
> + QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG,
> +};
> +
> +static const struct s3c2410_wdt_variant drv_data_gs201_cl0 = {
> + .mask_reset_reg = GS_CLUSTER0_NONCPU_INT_EN,
> + .mask_bit = 2,
> + .mask_reset_inv = true,
> + .rst_stat_reg = GS_RST_STAT_REG_OFFSET,
> + .rst_stat_bit = 0,
> + .cnt_en_reg = GS_CLUSTER0_NONCPU_OUT,
> + .cnt_en_bit = 8,
> + .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN |
> + QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG,
> +};
> +
> +static const struct s3c2410_wdt_variant drv_data_gs201_cl1 = {
> + .mask_reset_reg = GS_CLUSTER1_NONCPU_INT_EN,
> + .mask_bit = 2,
> + .mask_reset_inv = true,
> + .rst_stat_reg = GS_RST_STAT_REG_OFFSET,
> + .rst_stat_bit = 1,
> + .cnt_en_reg = GS_CLUSTER1_NONCPU_OUT,
> + .cnt_en_bit = 7,
> + .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN |
> + QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG,
> +};
> +
> static const struct of_device_id s3c2410_wdt_match[] = {
> { .compatible = "samsung,s3c2410-wdt",
> .data = &drv_data_s3c2410 },
> @@ -278,6 +334,10 @@ static const struct of_device_id s3c2410_wdt_match[] = {
> .data = &drv_data_exynos850_cl0 },
> { .compatible = "samsung,exynosautov9-wdt",
> .data = &drv_data_exynosautov9_cl0 },
> + { .compatible = "google,gs101-wdt",
> + .data = &drv_data_gs101_cl0 },
> + { .compatible = "google,gs201-wdt",
> + .data = &drv_data_gs201_cl0 },
> {},
> };
> MODULE_DEVICE_TABLE(of, s3c2410_wdt_match);
> @@ -375,6 +435,21 @@ static int s3c2410wdt_enable(struct s3c2410_wdt *wdt, bool en)
> return 0;
> }
>
> +static void s3c2410wdt_mask_dbgack(struct s3c2410_wdt *wdt, bool mask)
> +{
> + unsigned long wtcon;
> +
> + if (!(wdt->drv_data->quirks & QUIRK_HAS_DBGACK_BIT))
> + return;
> +
> + wtcon = readl(wdt->reg_base + S3C2410_WTCON);
> + if (mask)
> + wtcon |= S3C2410_WTCON_DBGACK_MASK;
> + else
> + wtcon &= ~S3C2410_WTCON_DBGACK_MASK;
> + writel(wtcon, wdt->reg_base + S3C2410_WTCON);
> +}
> +
> static int s3c2410wdt_keepalive(struct watchdog_device *wdd)
> {
> struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
> @@ -585,9 +660,11 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt)
> }
>
> #ifdef CONFIG_OF
> - /* Choose Exynos850/ExynosAutov9 driver data w.r.t. cluster index */
> + /* Choose Exynos850/ExynosAutov9/gsx01 driver data w.r.t. cluster index */
> if (variant == &drv_data_exynos850_cl0 ||
> - variant == &drv_data_exynosautov9_cl0) {
> + variant == &drv_data_exynosautov9_cl0 ||
> + variant == &drv_data_gs101_cl0 ||
> + variant == &drv_data_gs201_cl0) {
> u32 index;
> int err;
>
> @@ -600,9 +677,14 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt)
> case 0:
> break;
> case 1:
> - variant = (variant == &drv_data_exynos850_cl0) ?
> - &drv_data_exynos850_cl1 :
> - &drv_data_exynosautov9_cl1;
> + if (variant == &drv_data_exynos850_cl0)
> + variant = &drv_data_exynos850_cl1;
> + else if (variant == &drv_data_exynosautov9_cl0)
> + variant = &drv_data_exynosautov9_cl1;
> + else if (variant == &drv_data_gs101_cl0)
> + variant = &drv_data_gs101_cl1;
> + else if (variant == &drv_data_gs201_cl0)
> + variant = &drv_data_gs201_cl1;
> break;
> default:
> return dev_err_probe(dev, -EINVAL, "wrong cluster index: %u\n", index);
> @@ -700,6 +782,8 @@ static int s3c2410wdt_probe(struct platform_device *pdev)
> wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt);
> wdt->wdt_device.parent = dev;
>
> + s3c2410wdt_mask_dbgack(wdt, true);
> +
> /*
> * If "tmr_atboot" param is non-zero, start the watchdog right now. Also
> * set WDOG_HW_RUNNING bit, so that watchdog core can kick the watchdog.
> @@ -712,6 +796,7 @@ static int s3c2410wdt_probe(struct platform_device *pdev)
> s3c2410wdt_start(&wdt->wdt_device);
> set_bit(WDOG_HW_RUNNING, &wdt->wdt_device.status);
> } else {
> + dev_info(dev, "stopping watchdog timer\n");
I am not inclined to accept patches adding such noise.
> s3c2410wdt_stop(&wdt->wdt_device);
> }
>
> @@ -738,6 +823,15 @@ static int s3c2410wdt_probe(struct platform_device *pdev)
> (wtcon & S3C2410_WTCON_RSTEN) ? "en" : "dis",
> (wtcon & S3C2410_WTCON_INTEN) ? "en" : "dis");
>
> + if (wdt->drv_data->quirks & QUIRK_HAS_DBGACK_BIT)
> + dev_info(dev, "DBGACK %sabled\n",
> + (wtcon & S3C2410_WTCON_DBGACK_MASK) ? "en" : "dis");
> +
> + if (wdt->drv_data->quirks & QUIRK_HAS_WTMINCNT_REG)
> + dev_info(dev, "windowed watchdog %sabled, wtmincnt=%x\n",
> + (wtcon & S3C2410_WTCON_WINDOWED_WD) ? "en" : "dis",
> + readl(wdt->reg_base + S3C2410_WTMINCNT));
... and I really don't see its value.
> +
> return 0;
> }
>
> --
> 2.42.0.582.g8ccd20d70d-goog
>
^ permalink raw reply [flat|nested] 150+ messages in thread* Re: [PATCH 17/21] watchdog: s3c2410_wdt: Add support for Google tensor SoCs
@ 2023-10-05 18:58 ` Guenter Roeck
0 siblings, 0 replies; 150+ messages in thread
From: Guenter Roeck @ 2023-10-05 18:58 UTC (permalink / raw)
To: Peter Griffin
Cc: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, catalin.marinas,
will, arnd, olof, cw00.choi, tudor.ambarus, andre.draszik,
semen.protsenko, soc, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-clk, linux-gpio, linux-watchdog
On Thu, Oct 05, 2023 at 04:56:14PM +0100, Peter Griffin wrote:
> This patch adds the compatibles and drvdata for the Google
> gs101 & gs201 SoCs found in Pixel 6 and Pixel 7 phones. Similar
> to Exynos850 it has two watchdog instances, one for each cluster
> and has some control bits in PMU registers.
>
> The watchdog IP found in gs101 SoCs also supports a few
> additional bits/features in the WTCON register which we add
> support for and an additional register detailed below.
>
> dbgack-mask - Enables masking WDT interrupt and reset request
> according to asserted DBGACK input
>
> windowed-mode - Enabled Windowed watchdog mode
>
> Windowed watchdog mode also has an additional register WTMINCNT.
> If windowed watchdog is enabled and you reload WTCNT when the
> value is greater than WTMINCNT, it prompts interrupt or reset
> request as if the watchdog time has expired.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> drivers/watchdog/s3c2410_wdt.c | 116 +++++++++++++++++++++++++++++----
> 1 file changed, 105 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c
> index 0b4bd883ff28..4c23c7e6a3f1 100644
> --- a/drivers/watchdog/s3c2410_wdt.c
> +++ b/drivers/watchdog/s3c2410_wdt.c
> @@ -31,12 +31,14 @@
> #define S3C2410_WTDAT 0x04
> #define S3C2410_WTCNT 0x08
> #define S3C2410_WTCLRINT 0x0c
> -
> +#define S3C2410_WTMINCNT 0x10
> #define S3C2410_WTCNT_MAXCNT 0xffff
>
> -#define S3C2410_WTCON_RSTEN (1 << 0)
> -#define S3C2410_WTCON_INTEN (1 << 2)
> -#define S3C2410_WTCON_ENABLE (1 << 5)
> +#define S3C2410_WTCON_RSTEN (1 << 0)
> +#define S3C2410_WTCON_INTEN (1 << 2)
> +#define S3C2410_WTCON_ENABLE (1 << 5)
> +#define S3C2410_WTCON_DBGACK_MASK (1 << 16)
> +#define S3C2410_WTCON_WINDOWED_WD (1 << 20)
>
> #define S3C2410_WTCON_DIV16 (0 << 3)
> #define S3C2410_WTCON_DIV32 (1 << 3)
> @@ -61,12 +63,16 @@
> #define EXYNOS850_CLUSTER1_NONCPU_INT_EN 0x1644
> #define EXYNOSAUTOV9_CLUSTER1_NONCPU_OUT 0x1520
> #define EXYNOSAUTOV9_CLUSTER1_NONCPU_INT_EN 0x1544
> -
> #define EXYNOS850_CLUSTER0_WDTRESET_BIT 24
> #define EXYNOS850_CLUSTER1_WDTRESET_BIT 23
> #define EXYNOSAUTOV9_CLUSTER0_WDTRESET_BIT 25
> #define EXYNOSAUTOV9_CLUSTER1_WDTRESET_BIT 24
> -
> +#define GS_CLUSTER0_NONCPU_OUT 0x1220
> +#define GS_CLUSTER1_NONCPU_OUT 0x1420
> +#define GS_CLUSTER0_NONCPU_INT_EN 0x1244
> +#define GS_CLUSTER1_NONCPU_INT_EN 0x1444
> +#define GS_CLUSTER2_NONCPU_INT_EN 0x1644
> +#define GS_RST_STAT_REG_OFFSET 0x3B44
> /**
> * DOC: Quirk flags for different Samsung watchdog IP-cores
> *
> @@ -106,6 +112,8 @@
> #define QUIRK_HAS_PMU_RST_STAT (1 << 2)
> #define QUIRK_HAS_PMU_AUTO_DISABLE (1 << 3)
> #define QUIRK_HAS_PMU_CNT_EN (1 << 4)
> +#define QUIRK_HAS_DBGACK_BIT (1 << 5)
> +#define QUIRK_HAS_WTMINCNT_REG (1 << 6)
>
> /* These quirks require that we have a PMU register map */
> #define QUIRKS_HAVE_PMUREG \
> @@ -263,6 +271,54 @@ static const struct s3c2410_wdt_variant drv_data_exynosautov9_cl1 = {
> QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN,
> };
>
> +static const struct s3c2410_wdt_variant drv_data_gs101_cl0 = {
> + .mask_reset_reg = GS_CLUSTER0_NONCPU_INT_EN,
> + .mask_bit = 2,
> + .mask_reset_inv = true,
> + .rst_stat_reg = GS_RST_STAT_REG_OFFSET,
> + .rst_stat_bit = 0,
> + .cnt_en_reg = GS_CLUSTER0_NONCPU_OUT,
> + .cnt_en_bit = 8,
> + .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN |
> + QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG,
> +};
> +
> +static const struct s3c2410_wdt_variant drv_data_gs101_cl1 = {
> + .mask_reset_reg = GS_CLUSTER1_NONCPU_INT_EN,
> + .mask_bit = 2,
> + .mask_reset_inv = true,
> + .rst_stat_reg = GS_RST_STAT_REG_OFFSET,
> + .rst_stat_bit = 1,
> + .cnt_en_reg = GS_CLUSTER1_NONCPU_OUT,
> + .cnt_en_bit = 7,
> + .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN |
> + QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG,
> +};
> +
> +static const struct s3c2410_wdt_variant drv_data_gs201_cl0 = {
> + .mask_reset_reg = GS_CLUSTER0_NONCPU_INT_EN,
> + .mask_bit = 2,
> + .mask_reset_inv = true,
> + .rst_stat_reg = GS_RST_STAT_REG_OFFSET,
> + .rst_stat_bit = 0,
> + .cnt_en_reg = GS_CLUSTER0_NONCPU_OUT,
> + .cnt_en_bit = 8,
> + .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN |
> + QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG,
> +};
> +
> +static const struct s3c2410_wdt_variant drv_data_gs201_cl1 = {
> + .mask_reset_reg = GS_CLUSTER1_NONCPU_INT_EN,
> + .mask_bit = 2,
> + .mask_reset_inv = true,
> + .rst_stat_reg = GS_RST_STAT_REG_OFFSET,
> + .rst_stat_bit = 1,
> + .cnt_en_reg = GS_CLUSTER1_NONCPU_OUT,
> + .cnt_en_bit = 7,
> + .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN |
> + QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG,
> +};
> +
> static const struct of_device_id s3c2410_wdt_match[] = {
> { .compatible = "samsung,s3c2410-wdt",
> .data = &drv_data_s3c2410 },
> @@ -278,6 +334,10 @@ static const struct of_device_id s3c2410_wdt_match[] = {
> .data = &drv_data_exynos850_cl0 },
> { .compatible = "samsung,exynosautov9-wdt",
> .data = &drv_data_exynosautov9_cl0 },
> + { .compatible = "google,gs101-wdt",
> + .data = &drv_data_gs101_cl0 },
> + { .compatible = "google,gs201-wdt",
> + .data = &drv_data_gs201_cl0 },
> {},
> };
> MODULE_DEVICE_TABLE(of, s3c2410_wdt_match);
> @@ -375,6 +435,21 @@ static int s3c2410wdt_enable(struct s3c2410_wdt *wdt, bool en)
> return 0;
> }
>
> +static void s3c2410wdt_mask_dbgack(struct s3c2410_wdt *wdt, bool mask)
> +{
> + unsigned long wtcon;
> +
> + if (!(wdt->drv_data->quirks & QUIRK_HAS_DBGACK_BIT))
> + return;
> +
> + wtcon = readl(wdt->reg_base + S3C2410_WTCON);
> + if (mask)
> + wtcon |= S3C2410_WTCON_DBGACK_MASK;
> + else
> + wtcon &= ~S3C2410_WTCON_DBGACK_MASK;
> + writel(wtcon, wdt->reg_base + S3C2410_WTCON);
> +}
> +
> static int s3c2410wdt_keepalive(struct watchdog_device *wdd)
> {
> struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
> @@ -585,9 +660,11 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt)
> }
>
> #ifdef CONFIG_OF
> - /* Choose Exynos850/ExynosAutov9 driver data w.r.t. cluster index */
> + /* Choose Exynos850/ExynosAutov9/gsx01 driver data w.r.t. cluster index */
> if (variant == &drv_data_exynos850_cl0 ||
> - variant == &drv_data_exynosautov9_cl0) {
> + variant == &drv_data_exynosautov9_cl0 ||
> + variant == &drv_data_gs101_cl0 ||
> + variant == &drv_data_gs201_cl0) {
> u32 index;
> int err;
>
> @@ -600,9 +677,14 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt)
> case 0:
> break;
> case 1:
> - variant = (variant == &drv_data_exynos850_cl0) ?
> - &drv_data_exynos850_cl1 :
> - &drv_data_exynosautov9_cl1;
> + if (variant == &drv_data_exynos850_cl0)
> + variant = &drv_data_exynos850_cl1;
> + else if (variant == &drv_data_exynosautov9_cl0)
> + variant = &drv_data_exynosautov9_cl1;
> + else if (variant == &drv_data_gs101_cl0)
> + variant = &drv_data_gs101_cl1;
> + else if (variant == &drv_data_gs201_cl0)
> + variant = &drv_data_gs201_cl1;
> break;
> default:
> return dev_err_probe(dev, -EINVAL, "wrong cluster index: %u\n", index);
> @@ -700,6 +782,8 @@ static int s3c2410wdt_probe(struct platform_device *pdev)
> wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt);
> wdt->wdt_device.parent = dev;
>
> + s3c2410wdt_mask_dbgack(wdt, true);
> +
> /*
> * If "tmr_atboot" param is non-zero, start the watchdog right now. Also
> * set WDOG_HW_RUNNING bit, so that watchdog core can kick the watchdog.
> @@ -712,6 +796,7 @@ static int s3c2410wdt_probe(struct platform_device *pdev)
> s3c2410wdt_start(&wdt->wdt_device);
> set_bit(WDOG_HW_RUNNING, &wdt->wdt_device.status);
> } else {
> + dev_info(dev, "stopping watchdog timer\n");
I am not inclined to accept patches adding such noise.
> s3c2410wdt_stop(&wdt->wdt_device);
> }
>
> @@ -738,6 +823,15 @@ static int s3c2410wdt_probe(struct platform_device *pdev)
> (wtcon & S3C2410_WTCON_RSTEN) ? "en" : "dis",
> (wtcon & S3C2410_WTCON_INTEN) ? "en" : "dis");
>
> + if (wdt->drv_data->quirks & QUIRK_HAS_DBGACK_BIT)
> + dev_info(dev, "DBGACK %sabled\n",
> + (wtcon & S3C2410_WTCON_DBGACK_MASK) ? "en" : "dis");
> +
> + if (wdt->drv_data->quirks & QUIRK_HAS_WTMINCNT_REG)
> + dev_info(dev, "windowed watchdog %sabled, wtmincnt=%x\n",
> + (wtcon & S3C2410_WTCON_WINDOWED_WD) ? "en" : "dis",
> + readl(wdt->reg_base + S3C2410_WTMINCNT));
... and I really don't see its value.
> +
> return 0;
> }
>
> --
> 2.42.0.582.g8ccd20d70d-goog
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 150+ messages in thread* Re: [PATCH 17/21] watchdog: s3c2410_wdt: Add support for Google tensor SoCs
2023-10-05 18:58 ` Guenter Roeck
@ 2023-10-09 11:56 ` Peter Griffin
-1 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-09 11:56 UTC (permalink / raw)
To: Guenter Roeck
Cc: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, catalin.marinas,
will, arnd, olof, cw00.choi, tudor.ambarus, andre.draszik,
semen.protsenko, soc, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-clk, linux-gpio, linux-watchdog
Hi Guenter,
On Thu, 5 Oct 2023 at 19:58, Guenter Roeck <linux@roeck-us.net> wrote:
>
> On Thu, Oct 05, 2023 at 04:56:14PM +0100, Peter Griffin wrote:
> > This patch adds the compatibles and drvdata for the Google
> > gs101 & gs201 SoCs found in Pixel 6 and Pixel 7 phones. Similar
> > to Exynos850 it has two watchdog instances, one for each cluster
> > and has some control bits in PMU registers.
> >
> > The watchdog IP found in gs101 SoCs also supports a few
> > additional bits/features in the WTCON register which we add
> > support for and an additional register detailed below.
> >
> > dbgack-mask - Enables masking WDT interrupt and reset request
> > according to asserted DBGACK input
> >
> > windowed-mode - Enabled Windowed watchdog mode
> >
> > Windowed watchdog mode also has an additional register WTMINCNT.
> > If windowed watchdog is enabled and you reload WTCNT when the
> > value is greater than WTMINCNT, it prompts interrupt or reset
> > request as if the watchdog time has expired.
> >
> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> > ---
> > drivers/watchdog/s3c2410_wdt.c | 116 +++++++++++++++++++++++++++++----
> > 1 file changed, 105 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c
> > index 0b4bd883ff28..4c23c7e6a3f1 100644
> > --- a/drivers/watchdog/s3c2410_wdt.c
> > +++ b/drivers/watchdog/s3c2410_wdt.c
> > @@ -31,12 +31,14 @@
> > #define S3C2410_WTDAT 0x04
> > #define S3C2410_WTCNT 0x08
> > #define S3C2410_WTCLRINT 0x0c
> > -
> > +#define S3C2410_WTMINCNT 0x10
> > #define S3C2410_WTCNT_MAXCNT 0xffff
> >
> > -#define S3C2410_WTCON_RSTEN (1 << 0)
> > -#define S3C2410_WTCON_INTEN (1 << 2)
> > -#define S3C2410_WTCON_ENABLE (1 << 5)
> > +#define S3C2410_WTCON_RSTEN (1 << 0)
> > +#define S3C2410_WTCON_INTEN (1 << 2)
> > +#define S3C2410_WTCON_ENABLE (1 << 5)
> > +#define S3C2410_WTCON_DBGACK_MASK (1 << 16)
> > +#define S3C2410_WTCON_WINDOWED_WD (1 << 20)
> >
> > #define S3C2410_WTCON_DIV16 (0 << 3)
> > #define S3C2410_WTCON_DIV32 (1 << 3)
> > @@ -61,12 +63,16 @@
> > #define EXYNOS850_CLUSTER1_NONCPU_INT_EN 0x1644
> > #define EXYNOSAUTOV9_CLUSTER1_NONCPU_OUT 0x1520
> > #define EXYNOSAUTOV9_CLUSTER1_NONCPU_INT_EN 0x1544
> > -
> > #define EXYNOS850_CLUSTER0_WDTRESET_BIT 24
> > #define EXYNOS850_CLUSTER1_WDTRESET_BIT 23
> > #define EXYNOSAUTOV9_CLUSTER0_WDTRESET_BIT 25
> > #define EXYNOSAUTOV9_CLUSTER1_WDTRESET_BIT 24
> > -
> > +#define GS_CLUSTER0_NONCPU_OUT 0x1220
> > +#define GS_CLUSTER1_NONCPU_OUT 0x1420
> > +#define GS_CLUSTER0_NONCPU_INT_EN 0x1244
> > +#define GS_CLUSTER1_NONCPU_INT_EN 0x1444
> > +#define GS_CLUSTER2_NONCPU_INT_EN 0x1644
> > +#define GS_RST_STAT_REG_OFFSET 0x3B44
> > /**
> > * DOC: Quirk flags for different Samsung watchdog IP-cores
> > *
> > @@ -106,6 +112,8 @@
> > #define QUIRK_HAS_PMU_RST_STAT (1 << 2)
> > #define QUIRK_HAS_PMU_AUTO_DISABLE (1 << 3)
> > #define QUIRK_HAS_PMU_CNT_EN (1 << 4)
> > +#define QUIRK_HAS_DBGACK_BIT (1 << 5)
> > +#define QUIRK_HAS_WTMINCNT_REG (1 << 6)
> >
> > /* These quirks require that we have a PMU register map */
> > #define QUIRKS_HAVE_PMUREG \
> > @@ -263,6 +271,54 @@ static const struct s3c2410_wdt_variant drv_data_exynosautov9_cl1 = {
> > QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN,
> > };
> >
> > +static const struct s3c2410_wdt_variant drv_data_gs101_cl0 = {
> > + .mask_reset_reg = GS_CLUSTER0_NONCPU_INT_EN,
> > + .mask_bit = 2,
> > + .mask_reset_inv = true,
> > + .rst_stat_reg = GS_RST_STAT_REG_OFFSET,
> > + .rst_stat_bit = 0,
> > + .cnt_en_reg = GS_CLUSTER0_NONCPU_OUT,
> > + .cnt_en_bit = 8,
> > + .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN |
> > + QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG,
> > +};
> > +
> > +static const struct s3c2410_wdt_variant drv_data_gs101_cl1 = {
> > + .mask_reset_reg = GS_CLUSTER1_NONCPU_INT_EN,
> > + .mask_bit = 2,
> > + .mask_reset_inv = true,
> > + .rst_stat_reg = GS_RST_STAT_REG_OFFSET,
> > + .rst_stat_bit = 1,
> > + .cnt_en_reg = GS_CLUSTER1_NONCPU_OUT,
> > + .cnt_en_bit = 7,
> > + .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN |
> > + QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG,
> > +};
> > +
> > +static const struct s3c2410_wdt_variant drv_data_gs201_cl0 = {
> > + .mask_reset_reg = GS_CLUSTER0_NONCPU_INT_EN,
> > + .mask_bit = 2,
> > + .mask_reset_inv = true,
> > + .rst_stat_reg = GS_RST_STAT_REG_OFFSET,
> > + .rst_stat_bit = 0,
> > + .cnt_en_reg = GS_CLUSTER0_NONCPU_OUT,
> > + .cnt_en_bit = 8,
> > + .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN |
> > + QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG,
> > +};
> > +
> > +static const struct s3c2410_wdt_variant drv_data_gs201_cl1 = {
> > + .mask_reset_reg = GS_CLUSTER1_NONCPU_INT_EN,
> > + .mask_bit = 2,
> > + .mask_reset_inv = true,
> > + .rst_stat_reg = GS_RST_STAT_REG_OFFSET,
> > + .rst_stat_bit = 1,
> > + .cnt_en_reg = GS_CLUSTER1_NONCPU_OUT,
> > + .cnt_en_bit = 7,
> > + .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN |
> > + QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG,
> > +};
> > +
> > static const struct of_device_id s3c2410_wdt_match[] = {
> > { .compatible = "samsung,s3c2410-wdt",
> > .data = &drv_data_s3c2410 },
> > @@ -278,6 +334,10 @@ static const struct of_device_id s3c2410_wdt_match[] = {
> > .data = &drv_data_exynos850_cl0 },
> > { .compatible = "samsung,exynosautov9-wdt",
> > .data = &drv_data_exynosautov9_cl0 },
> > + { .compatible = "google,gs101-wdt",
> > + .data = &drv_data_gs101_cl0 },
> > + { .compatible = "google,gs201-wdt",
> > + .data = &drv_data_gs201_cl0 },
> > {},
> > };
> > MODULE_DEVICE_TABLE(of, s3c2410_wdt_match);
> > @@ -375,6 +435,21 @@ static int s3c2410wdt_enable(struct s3c2410_wdt *wdt, bool en)
> > return 0;
> > }
> >
> > +static void s3c2410wdt_mask_dbgack(struct s3c2410_wdt *wdt, bool mask)
> > +{
> > + unsigned long wtcon;
> > +
> > + if (!(wdt->drv_data->quirks & QUIRK_HAS_DBGACK_BIT))
> > + return;
> > +
> > + wtcon = readl(wdt->reg_base + S3C2410_WTCON);
> > + if (mask)
> > + wtcon |= S3C2410_WTCON_DBGACK_MASK;
> > + else
> > + wtcon &= ~S3C2410_WTCON_DBGACK_MASK;
> > + writel(wtcon, wdt->reg_base + S3C2410_WTCON);
> > +}
> > +
> > static int s3c2410wdt_keepalive(struct watchdog_device *wdd)
> > {
> > struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
> > @@ -585,9 +660,11 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt)
> > }
> >
> > #ifdef CONFIG_OF
> > - /* Choose Exynos850/ExynosAutov9 driver data w.r.t. cluster index */
> > + /* Choose Exynos850/ExynosAutov9/gsx01 driver data w.r.t. cluster index */
> > if (variant == &drv_data_exynos850_cl0 ||
> > - variant == &drv_data_exynosautov9_cl0) {
> > + variant == &drv_data_exynosautov9_cl0 ||
> > + variant == &drv_data_gs101_cl0 ||
> > + variant == &drv_data_gs201_cl0) {
> > u32 index;
> > int err;
> >
> > @@ -600,9 +677,14 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt)
> > case 0:
> > break;
> > case 1:
> > - variant = (variant == &drv_data_exynos850_cl0) ?
> > - &drv_data_exynos850_cl1 :
> > - &drv_data_exynosautov9_cl1;
> > + if (variant == &drv_data_exynos850_cl0)
> > + variant = &drv_data_exynos850_cl1;
> > + else if (variant == &drv_data_exynosautov9_cl0)
> > + variant = &drv_data_exynosautov9_cl1;
> > + else if (variant == &drv_data_gs101_cl0)
> > + variant = &drv_data_gs101_cl1;
> > + else if (variant == &drv_data_gs201_cl0)
> > + variant = &drv_data_gs201_cl1;
> > break;
> > default:
> > return dev_err_probe(dev, -EINVAL, "wrong cluster index: %u\n", index);
> > @@ -700,6 +782,8 @@ static int s3c2410wdt_probe(struct platform_device *pdev)
> > wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt);
> > wdt->wdt_device.parent = dev;
> >
> > + s3c2410wdt_mask_dbgack(wdt, true);
> > +
> > /*
> > * If "tmr_atboot" param is non-zero, start the watchdog right now. Also
> > * set WDOG_HW_RUNNING bit, so that watchdog core can kick the watchdog.
> > @@ -712,6 +796,7 @@ static int s3c2410wdt_probe(struct platform_device *pdev)
> > s3c2410wdt_start(&wdt->wdt_device);
> > set_bit(WDOG_HW_RUNNING, &wdt->wdt_device.status);
> > } else {
> > + dev_info(dev, "stopping watchdog timer\n");
>
> I am not inclined to accept patches adding such noise.
>
> > s3c2410wdt_stop(&wdt->wdt_device);
> > }
> >
> > @@ -738,6 +823,15 @@ static int s3c2410wdt_probe(struct platform_device *pdev)
> > (wtcon & S3C2410_WTCON_RSTEN) ? "en" : "dis",
> > (wtcon & S3C2410_WTCON_INTEN) ? "en" : "dis");
> >
> > + if (wdt->drv_data->quirks & QUIRK_HAS_DBGACK_BIT)
> > + dev_info(dev, "DBGACK %sabled\n",
> > + (wtcon & S3C2410_WTCON_DBGACK_MASK) ? "en" : "dis");
> > +
> > + if (wdt->drv_data->quirks & QUIRK_HAS_WTMINCNT_REG)
> > + dev_info(dev, "windowed watchdog %sabled, wtmincnt=%x\n",
> > + (wtcon & S3C2410_WTCON_WINDOWED_WD) ? "en" : "dis",
> > + readl(wdt->reg_base + S3C2410_WTMINCNT));
>
> ... and I really don't see its value.
Thanks for your review feedback. I will remove these dev_info prints in v2.
regards,
Peter.
^ permalink raw reply [flat|nested] 150+ messages in thread* Re: [PATCH 17/21] watchdog: s3c2410_wdt: Add support for Google tensor SoCs
@ 2023-10-09 11:56 ` Peter Griffin
0 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-09 11:56 UTC (permalink / raw)
To: Guenter Roeck
Cc: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, catalin.marinas,
will, arnd, olof, cw00.choi, tudor.ambarus, andre.draszik,
semen.protsenko, soc, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-clk, linux-gpio, linux-watchdog
Hi Guenter,
On Thu, 5 Oct 2023 at 19:58, Guenter Roeck <linux@roeck-us.net> wrote:
>
> On Thu, Oct 05, 2023 at 04:56:14PM +0100, Peter Griffin wrote:
> > This patch adds the compatibles and drvdata for the Google
> > gs101 & gs201 SoCs found in Pixel 6 and Pixel 7 phones. Similar
> > to Exynos850 it has two watchdog instances, one for each cluster
> > and has some control bits in PMU registers.
> >
> > The watchdog IP found in gs101 SoCs also supports a few
> > additional bits/features in the WTCON register which we add
> > support for and an additional register detailed below.
> >
> > dbgack-mask - Enables masking WDT interrupt and reset request
> > according to asserted DBGACK input
> >
> > windowed-mode - Enabled Windowed watchdog mode
> >
> > Windowed watchdog mode also has an additional register WTMINCNT.
> > If windowed watchdog is enabled and you reload WTCNT when the
> > value is greater than WTMINCNT, it prompts interrupt or reset
> > request as if the watchdog time has expired.
> >
> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> > ---
> > drivers/watchdog/s3c2410_wdt.c | 116 +++++++++++++++++++++++++++++----
> > 1 file changed, 105 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c
> > index 0b4bd883ff28..4c23c7e6a3f1 100644
> > --- a/drivers/watchdog/s3c2410_wdt.c
> > +++ b/drivers/watchdog/s3c2410_wdt.c
> > @@ -31,12 +31,14 @@
> > #define S3C2410_WTDAT 0x04
> > #define S3C2410_WTCNT 0x08
> > #define S3C2410_WTCLRINT 0x0c
> > -
> > +#define S3C2410_WTMINCNT 0x10
> > #define S3C2410_WTCNT_MAXCNT 0xffff
> >
> > -#define S3C2410_WTCON_RSTEN (1 << 0)
> > -#define S3C2410_WTCON_INTEN (1 << 2)
> > -#define S3C2410_WTCON_ENABLE (1 << 5)
> > +#define S3C2410_WTCON_RSTEN (1 << 0)
> > +#define S3C2410_WTCON_INTEN (1 << 2)
> > +#define S3C2410_WTCON_ENABLE (1 << 5)
> > +#define S3C2410_WTCON_DBGACK_MASK (1 << 16)
> > +#define S3C2410_WTCON_WINDOWED_WD (1 << 20)
> >
> > #define S3C2410_WTCON_DIV16 (0 << 3)
> > #define S3C2410_WTCON_DIV32 (1 << 3)
> > @@ -61,12 +63,16 @@
> > #define EXYNOS850_CLUSTER1_NONCPU_INT_EN 0x1644
> > #define EXYNOSAUTOV9_CLUSTER1_NONCPU_OUT 0x1520
> > #define EXYNOSAUTOV9_CLUSTER1_NONCPU_INT_EN 0x1544
> > -
> > #define EXYNOS850_CLUSTER0_WDTRESET_BIT 24
> > #define EXYNOS850_CLUSTER1_WDTRESET_BIT 23
> > #define EXYNOSAUTOV9_CLUSTER0_WDTRESET_BIT 25
> > #define EXYNOSAUTOV9_CLUSTER1_WDTRESET_BIT 24
> > -
> > +#define GS_CLUSTER0_NONCPU_OUT 0x1220
> > +#define GS_CLUSTER1_NONCPU_OUT 0x1420
> > +#define GS_CLUSTER0_NONCPU_INT_EN 0x1244
> > +#define GS_CLUSTER1_NONCPU_INT_EN 0x1444
> > +#define GS_CLUSTER2_NONCPU_INT_EN 0x1644
> > +#define GS_RST_STAT_REG_OFFSET 0x3B44
> > /**
> > * DOC: Quirk flags for different Samsung watchdog IP-cores
> > *
> > @@ -106,6 +112,8 @@
> > #define QUIRK_HAS_PMU_RST_STAT (1 << 2)
> > #define QUIRK_HAS_PMU_AUTO_DISABLE (1 << 3)
> > #define QUIRK_HAS_PMU_CNT_EN (1 << 4)
> > +#define QUIRK_HAS_DBGACK_BIT (1 << 5)
> > +#define QUIRK_HAS_WTMINCNT_REG (1 << 6)
> >
> > /* These quirks require that we have a PMU register map */
> > #define QUIRKS_HAVE_PMUREG \
> > @@ -263,6 +271,54 @@ static const struct s3c2410_wdt_variant drv_data_exynosautov9_cl1 = {
> > QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN,
> > };
> >
> > +static const struct s3c2410_wdt_variant drv_data_gs101_cl0 = {
> > + .mask_reset_reg = GS_CLUSTER0_NONCPU_INT_EN,
> > + .mask_bit = 2,
> > + .mask_reset_inv = true,
> > + .rst_stat_reg = GS_RST_STAT_REG_OFFSET,
> > + .rst_stat_bit = 0,
> > + .cnt_en_reg = GS_CLUSTER0_NONCPU_OUT,
> > + .cnt_en_bit = 8,
> > + .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN |
> > + QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG,
> > +};
> > +
> > +static const struct s3c2410_wdt_variant drv_data_gs101_cl1 = {
> > + .mask_reset_reg = GS_CLUSTER1_NONCPU_INT_EN,
> > + .mask_bit = 2,
> > + .mask_reset_inv = true,
> > + .rst_stat_reg = GS_RST_STAT_REG_OFFSET,
> > + .rst_stat_bit = 1,
> > + .cnt_en_reg = GS_CLUSTER1_NONCPU_OUT,
> > + .cnt_en_bit = 7,
> > + .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN |
> > + QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG,
> > +};
> > +
> > +static const struct s3c2410_wdt_variant drv_data_gs201_cl0 = {
> > + .mask_reset_reg = GS_CLUSTER0_NONCPU_INT_EN,
> > + .mask_bit = 2,
> > + .mask_reset_inv = true,
> > + .rst_stat_reg = GS_RST_STAT_REG_OFFSET,
> > + .rst_stat_bit = 0,
> > + .cnt_en_reg = GS_CLUSTER0_NONCPU_OUT,
> > + .cnt_en_bit = 8,
> > + .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN |
> > + QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG,
> > +};
> > +
> > +static const struct s3c2410_wdt_variant drv_data_gs201_cl1 = {
> > + .mask_reset_reg = GS_CLUSTER1_NONCPU_INT_EN,
> > + .mask_bit = 2,
> > + .mask_reset_inv = true,
> > + .rst_stat_reg = GS_RST_STAT_REG_OFFSET,
> > + .rst_stat_bit = 1,
> > + .cnt_en_reg = GS_CLUSTER1_NONCPU_OUT,
> > + .cnt_en_bit = 7,
> > + .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN |
> > + QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG,
> > +};
> > +
> > static const struct of_device_id s3c2410_wdt_match[] = {
> > { .compatible = "samsung,s3c2410-wdt",
> > .data = &drv_data_s3c2410 },
> > @@ -278,6 +334,10 @@ static const struct of_device_id s3c2410_wdt_match[] = {
> > .data = &drv_data_exynos850_cl0 },
> > { .compatible = "samsung,exynosautov9-wdt",
> > .data = &drv_data_exynosautov9_cl0 },
> > + { .compatible = "google,gs101-wdt",
> > + .data = &drv_data_gs101_cl0 },
> > + { .compatible = "google,gs201-wdt",
> > + .data = &drv_data_gs201_cl0 },
> > {},
> > };
> > MODULE_DEVICE_TABLE(of, s3c2410_wdt_match);
> > @@ -375,6 +435,21 @@ static int s3c2410wdt_enable(struct s3c2410_wdt *wdt, bool en)
> > return 0;
> > }
> >
> > +static void s3c2410wdt_mask_dbgack(struct s3c2410_wdt *wdt, bool mask)
> > +{
> > + unsigned long wtcon;
> > +
> > + if (!(wdt->drv_data->quirks & QUIRK_HAS_DBGACK_BIT))
> > + return;
> > +
> > + wtcon = readl(wdt->reg_base + S3C2410_WTCON);
> > + if (mask)
> > + wtcon |= S3C2410_WTCON_DBGACK_MASK;
> > + else
> > + wtcon &= ~S3C2410_WTCON_DBGACK_MASK;
> > + writel(wtcon, wdt->reg_base + S3C2410_WTCON);
> > +}
> > +
> > static int s3c2410wdt_keepalive(struct watchdog_device *wdd)
> > {
> > struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
> > @@ -585,9 +660,11 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt)
> > }
> >
> > #ifdef CONFIG_OF
> > - /* Choose Exynos850/ExynosAutov9 driver data w.r.t. cluster index */
> > + /* Choose Exynos850/ExynosAutov9/gsx01 driver data w.r.t. cluster index */
> > if (variant == &drv_data_exynos850_cl0 ||
> > - variant == &drv_data_exynosautov9_cl0) {
> > + variant == &drv_data_exynosautov9_cl0 ||
> > + variant == &drv_data_gs101_cl0 ||
> > + variant == &drv_data_gs201_cl0) {
> > u32 index;
> > int err;
> >
> > @@ -600,9 +677,14 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt)
> > case 0:
> > break;
> > case 1:
> > - variant = (variant == &drv_data_exynos850_cl0) ?
> > - &drv_data_exynos850_cl1 :
> > - &drv_data_exynosautov9_cl1;
> > + if (variant == &drv_data_exynos850_cl0)
> > + variant = &drv_data_exynos850_cl1;
> > + else if (variant == &drv_data_exynosautov9_cl0)
> > + variant = &drv_data_exynosautov9_cl1;
> > + else if (variant == &drv_data_gs101_cl0)
> > + variant = &drv_data_gs101_cl1;
> > + else if (variant == &drv_data_gs201_cl0)
> > + variant = &drv_data_gs201_cl1;
> > break;
> > default:
> > return dev_err_probe(dev, -EINVAL, "wrong cluster index: %u\n", index);
> > @@ -700,6 +782,8 @@ static int s3c2410wdt_probe(struct platform_device *pdev)
> > wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt);
> > wdt->wdt_device.parent = dev;
> >
> > + s3c2410wdt_mask_dbgack(wdt, true);
> > +
> > /*
> > * If "tmr_atboot" param is non-zero, start the watchdog right now. Also
> > * set WDOG_HW_RUNNING bit, so that watchdog core can kick the watchdog.
> > @@ -712,6 +796,7 @@ static int s3c2410wdt_probe(struct platform_device *pdev)
> > s3c2410wdt_start(&wdt->wdt_device);
> > set_bit(WDOG_HW_RUNNING, &wdt->wdt_device.status);
> > } else {
> > + dev_info(dev, "stopping watchdog timer\n");
>
> I am not inclined to accept patches adding such noise.
>
> > s3c2410wdt_stop(&wdt->wdt_device);
> > }
> >
> > @@ -738,6 +823,15 @@ static int s3c2410wdt_probe(struct platform_device *pdev)
> > (wtcon & S3C2410_WTCON_RSTEN) ? "en" : "dis",
> > (wtcon & S3C2410_WTCON_INTEN) ? "en" : "dis");
> >
> > + if (wdt->drv_data->quirks & QUIRK_HAS_DBGACK_BIT)
> > + dev_info(dev, "DBGACK %sabled\n",
> > + (wtcon & S3C2410_WTCON_DBGACK_MASK) ? "en" : "dis");
> > +
> > + if (wdt->drv_data->quirks & QUIRK_HAS_WTMINCNT_REG)
> > + dev_info(dev, "windowed watchdog %sabled, wtmincnt=%x\n",
> > + (wtcon & S3C2410_WTCON_WINDOWED_WD) ? "en" : "dis",
> > + readl(wdt->reg_base + S3C2410_WTMINCNT));
>
> ... and I really don't see its value.
Thanks for your review feedback. I will remove these dev_info prints in v2.
regards,
Peter.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 150+ messages in thread
* [PATCH 18/21] arm64: dts: google: Add initial Google gs101 SoC support
2023-10-05 15:55 ` Peter Griffin
@ 2023-10-05 15:56 ` Peter Griffin
-1 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-05 15:56 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi
Cc: peter.griffin, tudor.ambarus, andre.draszik, semen.protsenko,
soc, devicetree, linux-arm-kernel, linux-samsung-soc, linux-clk,
linux-gpio, linux-watchdog
Google gs101 SoC is ARMv8 mobile SoC found in the Pixel 6,
(oriole) Pixel 6a (bluejay) and Pixel 6 pro (raven) mobile
phones. It features:
* 4xA55 little cluster
* 2xA76 Mid cluster
* 2xX1 Big cluster
This commit adds the basic device tree for gs101 (SoC) and oriole
(pixel 6). Further platform support will be added over time.
It has been tested with a minimal busybox initramfs and boots to
a shell.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
arch/arm64/Kconfig.platforms | 6 +
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/google/Makefile | 6 +
arch/arm64/boot/dts/google/gs101-oriole.dts | 68 +
arch/arm64/boot/dts/google/gs101-pinctrl.dtsi | 1134 +++++++++++++++++
arch/arm64/boot/dts/google/gs101-pinctrl.h | 17 +
arch/arm64/boot/dts/google/gs101.dtsi | 501 ++++++++
7 files changed, 1733 insertions(+)
create mode 100644 arch/arm64/boot/dts/google/Makefile
create mode 100644 arch/arm64/boot/dts/google/gs101-oriole.dts
create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.dtsi
create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.h
create mode 100644 arch/arm64/boot/dts/google/gs101.dtsi
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 6069120199bb..a5ed1b719488 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -107,6 +107,12 @@ config ARCH_EXYNOS
help
This enables support for ARMv8 based Samsung Exynos SoC family.
+config ARCH_GOOGLE_TENSOR
+ bool "Google Tensor SoC fmaily"
+ depends on ARCH_EXYNOS
+ help
+ Support for ARMv8 based Google Tensor platforms.
+
config ARCH_SPARX5
bool "Microchip Sparx5 SoC family"
select PINCTRL
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 30dd6347a929..a4ee7b628114 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -13,6 +13,7 @@ subdir-y += broadcom
subdir-y += cavium
subdir-y += exynos
subdir-y += freescale
+subdir-y += google
subdir-y += hisilicon
subdir-y += intel
subdir-y += lg
diff --git a/arch/arm64/boot/dts/google/Makefile b/arch/arm64/boot/dts/google/Makefile
new file mode 100644
index 000000000000..6d2026a767d4
--- /dev/null
+++ b/arch/arm64/boot/dts/google/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0
+
+dtb-$(CONFIG_ARCH_GOOGLE_TENSOR) += \
+ gs101-oriole.dtb \
+
+
diff --git a/arch/arm64/boot/dts/google/gs101-oriole.dts b/arch/arm64/boot/dts/google/gs101-oriole.dts
new file mode 100644
index 000000000000..e531a39a76a4
--- /dev/null
+++ b/arch/arm64/boot/dts/google/gs101-oriole.dts
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Oriole DVT Device Tree
+ *
+ * Copyright 2021-2023 Google,LLC
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "gs101-pinctrl.h"
+#include "gs101.dtsi"
+
+/ {
+ model = "Oriole DVT";
+ compatible = "google,gs101-oriole", "google,gs101";
+};
+
+&pinctrl_1 {
+ key_voldown: key-voldown-pins {
+ samsung,pins = "gpa7-3";
+ samsung,pin-function = <0xf>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ key_volup: key-volup-pins {
+ samsung,pins = "gpa8-1";
+ samsung,pin-function = <0xf>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+};
+
+&pinctrl_0 {
+ key_power: key-power-pins {
+ samsung,pins = "gpa10-1";
+ samsung,pin-function = <0xf>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+};
+
+&gpio_keys {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&key_voldown &key_volup &key_power>;
+ button-vol-down {
+ label = "KEY_VOLUMEDOWN";
+ linux,code = <114>;
+ gpios = <&gpa7 3 0xf>;
+ wakeup-source;
+ };
+ button-vol-up {
+ label = "KEY_VOLUMEUP";
+ linux,code = <115>;
+ gpios = <&gpa8 1 0xf>;
+ wakeup-source;
+ };
+ button-power {
+ label = "KEY_POWER";
+ linux,code = <116>;
+ gpios = <&gpa10 1 0xf>;
+ wakeup-source;
+ };
+};
diff --git a/arch/arm64/boot/dts/google/gs101-pinctrl.dtsi b/arch/arm64/boot/dts/google/gs101-pinctrl.dtsi
new file mode 100644
index 000000000000..24825205ede8
--- /dev/null
+++ b/arch/arm64/boot/dts/google/gs101-pinctrl.dtsi
@@ -0,0 +1,1134 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * GS101 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright 2019-2023 Google LLC
+ *
+ */
+
+#include <dt-bindings/interrupt-controller/gs101.h>
+#include <arm64/exynos/exynos-pinctrl.h>
+#include "gs101-pinctrl.h"
+
+/ {
+ /* GPIO_ALIVE */
+ pinctrl@174d0000 {
+ gpa0: gpa0-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI IRQ_ALIVE_EINT0 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT1 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT2 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT3 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT4 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT5 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT6 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT7 ITLH>;
+ };
+ gpa1: gpa1-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI IRQ_ALIVE_EINT8 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT9 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT10 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT11 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT12 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT13 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT14 ITLH>;
+ };
+ gpa2: gpa2-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI IRQ_ALIVE_EINT15 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT16 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT17 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT18 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT19 ITLH>;
+ };
+ gpa3: gpa3-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI IRQ_ALIVE_EINT20 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT21 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT22 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT23 ITLH>;
+ };
+ gpa4: gpa4-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI IRQ_ALIVE_EINT24 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT25 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT26 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT27 ITLH>;
+ };
+ gpa5: gpa5-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI IRQ_ALIVE_EINT28 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT29 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT30 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT31 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT32 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT33 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT34 ITLH>;
+ };
+ gpa9: gpa9-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI IRQ_ALIVE_EINT35 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT36 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT37 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT38 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT39 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT40 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT41 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT42 ITLH>;
+ };
+ gpa10: gpa10-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI IRQ_ALIVE_EINT43 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT44 ITLH>;
+ };
+
+ uart15_bus: uart15-bus-pins {
+ samsung,pins = "gpa2-3", "gpa2-4";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ };
+
+ uart16_bus: uart16-bus-pins {
+ samsung,pins = "gpa3-0", "gpa3-1", "gpa3-2", "gpa3-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ uart16_bus_rts: uart1-bus-rts-pins {
+ samsung,pins = "gpa3-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-val = <1>;
+ };
+
+ uart16_bus_tx_dat: uart1-bus-tx-dat-pins {
+ samsung,pins = "gpa3-1";
+ samsung,pin-val = <1>;
+ };
+
+ uart16_bus_tx_con: uart1-bus-tx-con-pins {
+ samsung,pins = "gpa3-1";
+ samsung,pin-function = <1>;
+ };
+
+ uart17_bus: uart17-bus-pins {
+ samsung,pins = "gpa4-0", "gpa4-1", "gpa4-2", "gpa4-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ };
+
+ spi15_bus: spi15-bus-pins {
+ samsung,pins = "gpa4-0", "gpa4-1", "gpa4-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi15_cs: spi15-cs-pins {
+ samsung,pins = "gpa4-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ };
+ /* GPIO_FAR_ALIVE */
+ pinctrl@174e0000 {
+ gpa6: gpa6-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI IRQ_ALIVE_EINT45 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT46 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT47 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT48 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT49 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT50 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT51 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT52 ITLH>;
+ };
+ gpa7: gpa7-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI IRQ_ALIVE_EINT53 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT54 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT55 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT56 ITLH>;
+ };
+ gpa8: gpa8-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI IRQ_ALIVE_EINT57 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT58 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT59 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT60 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT61 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT62 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT63 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT64 ITLH>;
+ };
+ gpa11: gpa11-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI IRQ_ALIVE_EINT65 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT66 ITLH>;
+ };
+
+ };
+ /* GPIO_GSACORE */
+ pinctrl@17a80000 {
+ gps0: gps0-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gps1: gps1-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gps2: gps2-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+ /* GPIO_GSACTRL */
+ pinctrl@17940000 {
+ gps3: gps3-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+ /* GPIO_HSI1 */
+ pinctrl@11840000 {
+ gph0: gph0-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gph1: gph1-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ pcie0_clkreq: pcie0-clkreq-pins{
+ samsung,pins = "gph0-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <GS101_PIN_DRV_10_MA>;
+ samsung,pin-con-pdn = <3>;
+ samsung,pin-pud-pdn = <3>;
+ };
+ pcie0_perst: pcie0-perst-pins {
+ samsung,pins = "gph0-0";
+ samsung,pin-function = <1>;
+ samsung,pin-drv = <GS101_PIN_DRV_10_MA>;
+ samsung,pin-con-pdn = <3>;
+ };
+ };
+ /* GPIO_HSI2 */
+ pinctrl@14440000 {
+ gph2: gph2-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gph3: gph3-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gph4: gph4-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ sd2_clk: sd2-clk-pins {
+ samsung,pins = "gph4-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>;
+ };
+
+ sd2_cmd: sd2-cmd-pins {
+ samsung,pins = "gph4-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>;
+ };
+
+ sd2_bus1: sd2-bus-width1-pins {
+ samsung,pins = "gph4-2";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>;
+ };
+
+ sd2_bus4: sd2-bus-width4-pins {
+ samsung,pins = "gph4-3", "gph4-4", "gph4-5";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>;
+ };
+
+ sd2_clk_fast_slew_rate_1x: sd2-clk-fast-slew-rate-1x-pins {
+ samsung,pins = "gph4-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ sd2_clk_fast_slew_rate_2x: sd2-clk-fast-slew-rate-2x-pins {
+ samsung,pins = "gph4-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+ };
+
+ sd2_clk_fast_slew_rate_3x: sd2-clk-fast-slew-rate-3x-pins {
+ samsung,pins = "gph4-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>;
+ };
+
+ sd2_clk_fast_slew_rate_4x: sd2-clk-fast-slew-rate-4x-pins {
+ samsung,pins = "gph4-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_10_MA>;
+ };
+ ufs_rst_n: ufs-rst-n-pins {
+ samsung,pins = "gph3-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-con-pdn = <3>;
+ samsung,pin-pud-pdn = <0>;
+ };
+
+ ufs_refclk_out: ufs-refclk-out-pins {
+ samsung,pins = "gph3-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-con-pdn = <3>;
+ samsung,pin-pud-pdn = <0>;
+ };
+ pcie1_clkreq: pcie1-clkreq-pins {
+ samsung,pins = "gph2-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <GS101_PIN_DRV_10_MA>;
+ samsung,pin-con-pdn = <3>;
+ samsung,pin-pud-pdn = <3>;
+ };
+ pcie1_perst: pcie1-perst-pins {
+ samsung,pins = "gph2-0";
+ samsung,pin-function = <1>;
+ samsung,pin-drv = <GS101_PIN_DRV_10_MA>;
+ samsung,pin-con-pdn = <3>;
+ };
+ };
+ /* GPIO_PERIC0 */
+ pinctrl@10840000 {
+ gpp0: gpp0-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp1: gpp1-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp2: gpp2-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp3: gpp3-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp4: gpp4-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp5: gpp5-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp6: gpp6-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp7: gpp7-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp8: gpp8-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp9: gpp9-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp10: gpp10-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp11: gpp11-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp12: gpp12-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp13: gpp13-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp14: gpp14-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp15: gpp15-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp16: gpp16-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp17: gpp17-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp18: gpp18-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp19: gpp19-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ /* USI_PERIC0_UART_DBG */
+ uart0_bus: uart0-bus-pins {
+ samsung,pins = "gpp1-2", "gpp1-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ };
+
+ disp_te_pri_on: disp-te-pri-on-pins {
+ samsung,pins = "gpp0-3";
+ samsung,pin-function = <0xf>;
+ };
+
+ disp_te_pri_off: disp-te-pri-off-pins {
+ samsung,pins = "gpp0-3";
+ samsung,pin-function = <0>;
+ };
+
+ disp_te_sec_on: disp-te-sec-on-pins {
+ samsung,pins = "gpp0-4";
+ samsung,pin-function = <0xf>;
+ };
+
+ disp_te_sec_off: disp-te-sec-off-pins {
+ samsung,pins = "gpp0-4";
+ samsung,pin-function = <0>;
+ };
+
+ sensor_mclk1_out: sensor-mclk1-out-pins {
+ samsung,pins = "gpp3-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+ };
+ sensor_mclk1_fn: sensor-mclk1-fn-pins {
+ samsung,pins = "gpp3-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+ };
+ sensor_mclk2_out: sensor-mclk2-out-pins {
+ samsung,pins = "gpp5-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+ };
+ sensor_mclk2_fn: sensor-mclk2-fn-pins {
+ samsung,pins = "gpp5-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+ };
+ sensor_mclk3_out: sensor-mclk3-out-pins {
+ samsung,pins = "gpp7-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+ };
+ sensor_mclk3_fn: sensor-mclk3-fn-pins {
+ samsung,pins = "gpp7-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+ };
+ sensor_mclk4_out: sensor-mclk4-out-pins {
+ samsung,pins = "gpp9-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+ };
+ sensor_mclk4_fn: sensor-mclk4-fn-pins {
+ samsung,pins = "gpp9-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+ };
+ sensor_mclk5_out: sensor-mclk5-out-pins {
+ samsung,pins = "gpp11-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+ };
+ sensor_mclk5_fn: sensor-mclk5-fn-pins {
+ samsung,pins = "gpp11-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+ };
+ sensor_mclk6_out: sensor-mclk6-out-pins {
+ samsung,pins = "gpp13-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+ };
+ sensor_mclk6_fn: sensor-mclk6-fn-pins {
+ samsung,pins = "gpp13-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+ };
+ sensor_mclk7_out: sensor-mclk7-out-pins {
+ samsung,pins = "gpp15-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+ };
+ sensor_mclk7_fn: sensor-mclk7-fn-pins {
+ samsung,pins = "gpp15-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+ };
+ sensor_mclk8_out: sensor-mclk8-out-pins {
+ samsung,pins = "gpp17-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+ };
+ sensor_mclk8_fn: sensor-mclk8-fn-pins {
+ samsung,pins = "gpp17-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+ };
+ hsi2c14_bus: hsi2c14-bus-pins {
+ samsung,pins = "gpp18-0", "gpp18-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ uart14_bus_single: uart14-bus-pins {
+ samsung,pins = "gpp18-0", "gpp18-1",
+ "gpp18-2", "gpp18-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ };
+ spi14_bus: spi14-bus-pins {
+ samsung,pins = "gpp18-0", "gpp18-1", "gpp18-2";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi14_cs: spi14-cs-pins {
+ samsung,pins = "gpp18-3";
+ samsung,pin-function = <1>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi14_cs_func: spi14-cs-func-pins {
+ samsung,pins = "gpp18-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ hsi2c8_bus: hsi2c8-bus-pins {
+ samsung,pins = "gpp16-0", "gpp16-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ samsung,pin-pud-pdn = <EXYNOS_PIN_PDN_OUT0>;
+ };
+ uart8_bus_single: uart8-bus-pins {
+ samsung,pins = "gpp16-0", "gpp16-1", "gpp16-2",
+ "gpp16-3";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ };
+ spi8_bus: spi8-bus-pins {
+ samsung,pins = "gpp16-0", "gpp16-1", "gpp16-2";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi8_cs: spi8-cs-pins {
+ samsung,pins = "gpp16-3";
+ samsung,pin-function = <1>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi8_cs_func: spi8-cs-func-pins {
+ samsung,pins = "gpp16-3";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ hsi2c7_bus: hsi2c7-bus-pins {
+ samsung,pins = "gpp14-0", "gpp14-1";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ uart7_bus_single: uart7-bus-pins {
+ samsung,pins = "gpp14-0", "gpp14-1",
+ "gpp14-2", "gpp14-3";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ };
+ spi7_bus: spi7-bus-pins {
+ samsung,pins = "gpp14-0", "gpp14-1", "gpp14-2";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi7_cs: spi7-cs-pins {
+ samsung,pins = "gpp14-3";
+ samsung,pin-function = <1>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi7_cs_func: spi7-cs-func-pins {
+ samsung,pins = "gpp14-3";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ hsi2c6_bus: hsi2c6-bus-pins {
+ samsung,pins = "gpp12-0", "gpp12-1";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ uart6_bus_single: uart6-bus-pins {
+ samsung,pins = "gpp12-0", "gpp12-1",
+ "gpp12-2", "gpp12-3";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ };
+ spi6_bus: spi6-bus-pins {
+ samsung,pins = "gpp12-0", "gpp12-1", "gpp12-2";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi6_cs: spi6-cs-pins {
+ samsung,pins = "gpp12-3";
+ samsung,pin-function = <1>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi6_cs_func: spi6-cs-func-pins {
+ samsung,pins = "gpp12-3";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ hsi2c5_bus: hsi2c5-bus-pins {
+ samsung,pins = "gpp10-0", "gpp10-1";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ uart5_bus_single: uart5-bus-pins {
+ samsung,pins = "gpp10-0", "gpp10-1",
+ "gpp10-2", "gpp10-3";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ };
+ spi5_bus: spi5-bus-pins {
+ samsung,pins = "gpp10-0", "gpp10-1", "gpp10-2";
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
+ samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>;
+ };
+ spi5_cs_func: spi5-cs-func-pins {
+ samsung,pins = "gpp10-3";
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
+ samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>;
+ };
+ hsi2c4_bus: hsi2c4-bus-pins {
+ samsung,pins = "gpp8-0", "gpp8-1";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ uart4_bus_single: uart4-bus-pins {
+ samsung,pins = "gpp8-0", "gpp8-1",
+ "gpp8-2", "gpp8-3";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ };
+ spi4_bus: spi4-bus-pins {
+ samsung,pins = "gpp8-0", "gpp8-1", "gpp8-2";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi4_cs: spi4-cs-pins {
+ samsung,pins = "gpp8-3";
+ samsung,pin-function = <1>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi4_cs_func: spi4-cs-func-pins {
+ samsung,pins = "gpp8-3";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ hsi2c3_bus: hsi2c3-bus-pins {
+ samsung,pins = "gpp6-0", "gpp6-1";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ uart3_bus_single: uart3-bus-pins {
+ samsung,pins = "gpp6-0", "gpp6-1",
+ "gpp6-2", "gpp6-3";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ };
+ spi3_bus: spi3-bus-pins {
+ samsung,pins = "gpp6-0", "gpp6-1", "gpp6-2";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi3_cs: spi3-cs-pins {
+ samsung,pins = "gpp6-3";
+ samsung,pin-function = <1>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi3_cs_func: spi3-cs-func-pins {
+ samsung,pins = "gpp6-3";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ hsi2c2_bus: hsi2c2-bus-pins {
+ samsung,pins = "gpp4-0", "gpp4-1";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ uart2_bus_single: uart2-bus-pins {
+ samsung,pins = "gpp4-0", "gpp4-1",
+ "gpp4-2", "gpp4-3";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ };
+ spi2_bus: spi2-bus-pins {
+ samsung,pins = "gpp4-0", "gpp4-1", "gpp4-2";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi2_cs: spi2-cs-pins {
+ samsung,pins = "gpp4-3";
+ samsung,pin-function = <1>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi2_cs_func: spi2-cs-func-pins {
+ samsung,pins = "gpp4-3";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ hsi2c1_bus: hsi2c1-bus-pins {
+ samsung,pins = "gpp2-0", "gpp2-1";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ uart1_bus_single: uart1-bus-pins {
+ samsung,pins = "gpp2-0", "gpp2-1",
+ "gpp2-2", "gpp2-3";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ };
+ spi1_bus: spi1-bus-pins {
+ samsung,pins = "gpp2-0", "gpp2-1", "gpp2-2";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi1_cs: spi1-cs-pins {
+ samsung,pins = "gpp2-3";
+ samsung,pin-function = <1>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi1_cs_func: spi1-cs-func-pins {
+ samsung,pins = "gpp2-3";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ };
+ /* GPIO_PERIC1 */
+ pinctrl@10c40000 {
+ gpp20: gpp20-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp21: gpp21-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp22: gpp22-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp23: gpp23-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp24: gpp24-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp25: gpp25-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp26: gpp26-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp27: gpp27-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ hsi2c13_bus: hsi2c13-bus-pins {
+ samsung,pins = "gpp25-0", "gpp25-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ uart13_bus_single: uart13-bus-pins {
+ samsung,pins = "gpp25-0", "gpp25-1",
+ "gpp25-2", "gpp25-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ };
+ spi13_bus: spi13-bus-pins {
+ samsung,pins = "gpp25-0", "gpp25-1", "gpp25-2";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi13_cs: spi13-cs-pins {
+ samsung,pins = "gpp25-3";
+ samsung,pin-function = <1>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi13_cs_func: spi13-cs-func-pins {
+ samsung,pins = "gpp25-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ hsi2c12_bus: hsi2c12-bus-pins {
+ samsung,pins = "gpp23-4", "gpp23-5";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ uart12_bus_single: uart12-bus-pins {
+ samsung,pins = "gpp23-4", "gpp23-5",
+ "gpp23-6", "gpp23-7";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ };
+ spi12_bus: spi12-bus-pins {
+ samsung,pins = "gpp23-4", "gpp23-5", "gpp23-6";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi14_cs2: spi14-cs2-pins {
+ samsung,pins = "gpp23-6";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi12_cs: spi12-cs-pins {
+ samsung,pins = "gpp23-7";
+ samsung,pin-function = <1>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi12_cs_func: spi12-cs-func-pins {
+ samsung,pins = "gpp23-7";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ hsi2c11_bus: hsi2c11-bus-pins {
+ samsung,pins = "gpp23-0", "gpp23-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ uart11_bus_single: uart11-bus-pins {
+ samsung,pins = "gpp23-0", "gpp23-1",
+ "gpp23-2", "gpp23-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ };
+ spi11_bus: spi11-bus-pins {
+ samsung,pins = "gpp23-0", "gpp23-1", "gpp23-2";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi11_cs: spi11-cs-pins {
+ samsung,pins = "gpp23-3";
+ samsung,pin-function = <1>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi11_cs_func: spi11-cs-func-pins {
+ samsung,pins = "gpp23-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ hsi2c10_bus: hsi2c10-bus-pins {
+ samsung,pins = "gpp21-0", "gpp21-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ uart10_bus_single: uart10-bus-pins {
+ samsung,pins = "gpp21-0", "gpp21-1",
+ "gpp21-2", "gpp21-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ };
+ spi10_bus: spi10-bus-pins {
+ samsung,pins = "gpp21-0", "gpp21-1", "gpp21-2";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi10_cs: spi10-cs-pins {
+ samsung,pins = "gpp21-3";
+ samsung,pin-function = <1>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi10_cs_func: spi10-cs-func-pins {
+ samsung,pins = "gpp21-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ hsi2c9_bus: hsi2c9-bus-pins {
+ samsung,pins = "gpp20-4", "gpp20-5";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ uart9_bus_single: uart9-bus-pins {
+ samsung,pins = "gpp20-4", "gpp20-5",
+ "gpp20-6", "gpp20-7";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ };
+ spi9_bus: spi9-bus-pins {
+ samsung,pins = "gpp20-4", "gpp20-5", "gpp20-6";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi9_cs: spi9-cs-pins {
+ samsung,pins = "gpp20-7";
+ samsung,pin-function = <1>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi9_cs_func: spi9-cs-func-pins {
+ samsung,pins = "gpp20-7";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ hsi2c0_bus: hsi2c0-bus-pins {
+ samsung,pins = "gpp20-0", "gpp20-1";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ uart0_bus_single: uart0-bus-pins {
+ samsung,pins = "gpp20-0", "gpp20-1",
+ "gpp20-2", "gpp20-3";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ };
+ spi0_bus: spi0-bus-pins {
+ samsung,pins = "gpp20-0", "gpp20-1", "gpp20-2";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi0_cs: spi0-cs-pins {
+ samsung,pins = "gpp20-3";
+ samsung,pin-function = <1>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi0_cs_func: spi0-cs-func-pins {
+ samsung,pins = "gpp20-3";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/google/gs101-pinctrl.h b/arch/arm64/boot/dts/google/gs101-pinctrl.h
new file mode 100644
index 000000000000..acc77c684f0d
--- /dev/null
+++ b/arch/arm64/boot/dts/google/gs101-pinctrl.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Pinctrl binding constants for GS101
+ *
+ * Copyright (c) 2020-2023 Google, LLC.
+ */
+
+#ifndef __DT_BINDINGS_PINCTRL_GS101_H__
+#define __DT_BINDINGS_PINCTRL_GS101_H__
+
+/* GS101 drive strengths */
+#define GS101_PIN_DRV_2_5_MA 0
+#define GS101_PIN_DRV_5_MA 1
+#define GS101_PIN_DRV_7_5_MA 2
+#define GS101_PIN_DRV_10_MA 3
+
+#endif /* __DT_BINDINGS_PINCTRL_GS101_H__ */
diff --git a/arch/arm64/boot/dts/google/gs101.dtsi b/arch/arm64/boot/dts/google/gs101.dtsi
new file mode 100644
index 000000000000..0bd43745f6fa
--- /dev/null
+++ b/arch/arm64/boot/dts/google/gs101.dtsi
@@ -0,0 +1,501 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * GS101 SoC
+ *
+ * Copyright 2019-2023 Google LLC
+ *
+ */
+
+#include <dt-bindings/clock/gs101.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/gs101.h>
+
+#include "gs101-pinctrl.dtsi"
+
+/ {
+ compatible = "google,gs101";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ aliases {
+ pinctrl0 = &pinctrl_0;
+ pinctrl1 = &pinctrl_1;
+ pinctrl2 = &pinctrl_2;
+ pinctrl3 = &pinctrl_3;
+ pinctrl4 = &pinctrl_4;
+ pinctrl5 = &pinctrl_5;
+ pinctrl6 = &pinctrl_6;
+ pinctrl7 = &pinctrl_7;
+
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+ cluster1 {
+ core0 {
+ cpu = <&cpu4>;
+ };
+ core1 {
+ cpu = <&cpu5>;
+ };
+ };
+ cluster2 {
+ core0 {
+ cpu = <&cpu6>;
+ };
+ core1 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x0000>;
+ enable-method = "psci";
+ cpu-idle-states = <&ANANKE_CPU_SLEEP>;
+ capacity-dmips-mhz = <250>;
+ dynamic-power-coefficient = <70>;
+ };
+ cpu1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x0100>;
+ enable-method = "psci";
+ cpu-idle-states = <&ANANKE_CPU_SLEEP>;
+ capacity-dmips-mhz = <250>;
+ dynamic-power-coefficient = <70>;
+ };
+ cpu2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x0200>;
+ enable-method = "psci";
+ cpu-idle-states = <&ANANKE_CPU_SLEEP>;
+ capacity-dmips-mhz = <250>;
+ dynamic-power-coefficient = <70>;
+ };
+ cpu3: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x0300>;
+ enable-method = "psci";
+ cpu-idle-states = <&ANANKE_CPU_SLEEP>;
+ capacity-dmips-mhz = <250>;
+ dynamic-power-coefficient = <70>;
+ };
+ cpu4: cpu@400 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x0400>;
+ enable-method = "psci";
+ cpu-idle-states = <&ENYO_CPU_SLEEP>;
+ capacity-dmips-mhz = <620>;
+ dynamic-power-coefficient = <284>;
+ };
+ cpu5: cpu@500 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x0500>;
+ enable-method = "psci";
+ cpu-idle-states = <&ENYO_CPU_SLEEP>;
+ capacity-dmips-mhz = <620>;
+ dynamic-power-coefficient = <284>;
+ };
+ cpu6: cpu@600 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x0600>;
+ enable-method = "psci";
+ cpu-idle-states = <&HERA_CPU_SLEEP>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <650>;
+ };
+ cpu7: cpu@700 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x0700>;
+ enable-method = "psci";
+ cpu-idle-states = <&HERA_CPU_SLEEP>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <650>;
+ };
+
+ idle-states {
+ entry-method = "psci";
+
+ ANANKE_CPU_SLEEP: cpu-ananke-sleep {
+ idle-state-name = "c2";
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x0010000>;
+ entry-latency-us = <70>;
+ exit-latency-us = <160>;
+ min-residency-us = <2000>;
+ status = "okay";
+ };
+
+ ENYO_CPU_SLEEP: cpu-enyo-sleep {
+ idle-state-name = "c2";
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x0010000>;
+ entry-latency-us = <150>;
+ exit-latency-us = <190>;
+ min-residency-us = <2500>;
+ status = "okay";
+ };
+
+ HERA_CPU_SLEEP: cpu-hera-sleep {
+ idle-state-name = "c2";
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x0010000>;
+ entry-latency-us = <235>;
+ exit-latency-us = <220>;
+ min-residency-us = <3500>;
+ status = "okay";
+ };
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+
+ tpu_fw_reserved: tpu_fw@93000000 {
+ reg = <0x0 0x93000000 0x1000000>;
+ no-map;
+ };
+
+ gsa_reserved_protected: gsa@90200000 {
+ reg = <0x0 0x90200000 0x400000>;
+ no-map;
+ };
+
+ aoc_reserve: aoc@94000000 {
+ reg = <0x0 0x94000000 0x03000000>;
+ no-map;
+ };
+
+ abl_reserved: abl@f8800000 {
+ reg = <0x0 0xf8800000 0x02000000>;
+ no-map;
+ };
+
+ dss_log_reserved: dss_log_reserved@fd3f0000 {
+ reg = <0 0xfd3f0000 0x0000e000>;
+ no-map;
+ };
+
+ debug_kinfo_reserved: debug_kinfo_reserved@fd3fe000 {
+ reg = <0 0xfd3fe000 0x00001000>;
+ no-map;
+ };
+
+ bldr_log_reserved: bldr_log_reserved@fd800000 {
+ reg = <0 0xfd800000 0x00100000>;
+ no-map;
+ };
+
+ bldr_log_hist_reserved: bldr_log_hist_reserved@fd900000 {
+ reg = <0 0xfd900000 0x00002000>;
+ no-map;
+ };
+ };
+
+ /* bootloader requires ect node */
+ ect {
+ parameter_address = <0x90000000>;
+ parameter_size = <0x53000>;
+ };
+
+ chosen {
+ bootargs = "earlycon=exynos4210,mmio32,0x10A00000 clk_ignore_unused";
+ };
+
+ gic: interrupt-controller@10400000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x0 0x10400000 0x10000>, /* GICD */
+ <0x0 0x10440000 0x100000>; /* GICR * 8 */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ clock-frequency = <24576000>;
+ };
+
+ ext_24_5m: ext_24_5m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24576000>;
+ clock-output-names = "oscclk";
+ };
+
+ ext_200m: ext_200m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ clock-output-names = "ext-200m";
+ };
+
+ /* GPIO_ALIVE */
+ pinctrl_0: pinctrl@174d0000 {
+ compatible = "google,gs101-pinctrl";
+ reg = <0x00000000 0x174d0000 0x00001000>;
+ interrupts = <GIC_SPI IRQ_ALIVE_EINT0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT10 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT15 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT17 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT19 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT20 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT21 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT22 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT23 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT24 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT25 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT26 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT27 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT28 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT29 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT30 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT31 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT33 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT34 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT35 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT36 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT37 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT38 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT39 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT40 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT41 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT43 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT44 IRQ_TYPE_LEVEL_HIGH>;
+
+ wakeup-interrupt-controller {
+ compatible = "google,gs101-wakeup-eint";
+ };
+ };
+
+ /* GPIO_FAR_ALIVE */
+ pinctrl_1: pinctrl@174e0000 {
+ compatible = "google,gs101-pinctrl";
+ reg = <0x00000000 0x174e0000 0x00001000>;
+ interrupts = <GIC_SPI IRQ_ALIVE_EINT45 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT46 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT47 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT48 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT49 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT50 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT51 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT52 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT53 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT54 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT55 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT56 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT57 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT58 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT59 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT60 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT61 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT62 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT63 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT64 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT65 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT66 IRQ_TYPE_LEVEL_HIGH>;
+
+ wakeup-interrupt-controller {
+ compatible = "google,gs101-wakeup-eint";
+ };
+ };
+
+ /* GPIO_GSACORE */
+ pinctrl_2: pinctrl@17a80000 {
+ compatible = "google,gs101-pinctrl";
+ reg = <0x00000000 0x17a80000 0x00001000>;
+ };
+ /* GPIO_GSACTRL */
+ pinctrl_3: pinctrl@17940000 {
+ compatible = "google,gs101-pinctrl";
+ reg = <0x00000000 0x17940000 0x00001000>;
+ };
+ /* GPIO_PERIC0 */
+ pinctrl_4: pinctrl@10840000 {
+ compatible = "google,gs101-pinctrl";
+ reg = <0x00000000 0x10840000 0x00001000>;
+ interrupts = <GIC_SPI IRQ_GPIO_PERIC0_PERIC0 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ /* GPIO_PERIC1 */
+ pinctrl_5: pinctrl@10c40000 {
+ compatible = "google,gs101-pinctrl";
+ reg = <0x00000000 0x10C40000 0x00001000>;
+ interrupts = <GIC_SPI IRQ_GPIO_PERIC1_PERIC1 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ /* GPIO_HSI1 */
+ pinctrl_6: pinctrl@11840000 {
+ compatible = "google,gs101-pinctrl";
+ reg = <0x00000000 0x11840000 0x00001000>;
+ interrupts = <GIC_SPI IRQ_GPIO_HSI1_HSI1 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ /* GPIO_HSI2 */
+ pinctrl_7: pinctrl@14440000 {
+ compatible = "google,gs101-pinctrl";
+ reg = <0x00000000 0x14440000 0x00001000>;
+ interrupts = <GIC_SPI IRQ_GPIO_HSI2_HSI2 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ arm-pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ sysreg_apm: syscon@174204e0 {
+ compatible = "google,gs101-apm-sysreg",
+ "google,gs101-sysreg", "syscon";
+ reg = <0x0 0x174204e0 0x1000>;
+ };
+
+ sysreg_peric0: syscon@10821000 {
+ compatible = "google,gs101-peric0-sysreg",
+ "google,gs101-sysreg", "syscon";
+ reg = <0x0 0x10821000 0x40000>;
+ };
+
+ sysreg_peric1: syscon@10c21000 {
+ compatible = "google,gs101-peric1-sysreg",
+ "google,gs101-sysreg", "syscon";
+ reg = <0x0 0x10C21000 0x40000>;
+ };
+
+ /* TODO replace with CCF clock */
+ dummy_clk: oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <12345>;
+ clock-output-names = "pclk";
+ };
+
+ serial_0: serial@10a00000 {
+ compatible = "samsung,exynos850-uart";
+ reg = <0x0 0x10a00000 0xc0>;
+ reg-io-width = <4>;
+ samsung,uart-fifosize = <256>;
+ interrupts = <GIC_SPI IRQ_USI0_UART_PERIC0 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&dummy_clk 0>, <&dummy_clk 0>;
+ clock-names = "uart", "clk_uart_baud0";
+ status = "okay";
+ };
+
+ pmu_system_controller: system-controller@17460000 {
+ compatible = "google,gs101-pmu", "syscon";
+ reg = <0x0 0x17460000 0x10000>;
+ };
+
+ watchdog_cl0: watchdog@10060000 {
+ compatible = "google,gs101-wdt";
+ reg = <0x0 0x10060000 0x100>;
+ interrupts = <GIC_SPI IRQ_WDT_CLUSTER0_MISC IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER0>, <&ext_24_5m>;
+ clock-names = "watchdog", "watchdog_src";
+ timeout-sec = <30>;
+ samsung,syscon-phandle = <&pmu_system_controller>;
+ samsung,cluster-index = <0>;
+ };
+
+ watchdog_cl1: watchdog@10070000 {
+ compatible = "google,gs101-wdt";
+ reg = <0x0 0x10070000 0x100>;
+ interrupts = <GIC_SPI IRQ_WDT_CLUSTER1_MISC IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER1>, <&ext_24_5m>;
+ clock-names = "watchdog", "watchdog_src";
+ timeout-sec = <30>;
+ samsung,syscon-phandle = <&pmu_system_controller>;
+ samsung,cluster-index = <1>;
+ status = "disabled";
+ };
+
+ cmu_top: clock-controller@1e080000 {
+ compatible = "google,gs101-cmu-top";
+ reg = <0x0 0x1e080000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&ext_24_5m>;
+ clock-names = "oscclk";
+ };
+
+ cmu_apm: clock-controller@17400000 {
+ compatible = "google,gs101-cmu-apm";
+ reg = <0x0 0x17400000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&ext_24_5m>;
+ clock-names = "oscclk";
+ };
+
+ cmu_misc: clock-controller@10010000 {
+ compatible = "google,gs101-cmu-misc";
+ reg = <0x0 0x10010000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&ext_24_5m>, <&cmu_top CLK_DOUT_MISC_BUS>;
+ clock-names = "oscclk", "dout_cmu_misc_bus";
+ };
+
+ dsu-pmu-0 {
+ compatible = "arm,dsu-pmu";
+ interrupts = <GIC_SPI IRQ_CPUCL0_CLUSTERPMUIRQ_CPUCL0 IRQ_TYPE_LEVEL_HIGH>;
+ cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
+ };
+
+ gpio_keys: gpio_keys {
+ compatible = "gpio-keys";
+ };
+
+};
--
2.42.0.582.g8ccd20d70d-goog
^ permalink raw reply related [flat|nested] 150+ messages in thread* [PATCH 18/21] arm64: dts: google: Add initial Google gs101 SoC support
@ 2023-10-05 15:56 ` Peter Griffin
0 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-05 15:56 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi
Cc: peter.griffin, tudor.ambarus, andre.draszik, semen.protsenko,
soc, devicetree, linux-arm-kernel, linux-samsung-soc, linux-clk,
linux-gpio, linux-watchdog
Google gs101 SoC is ARMv8 mobile SoC found in the Pixel 6,
(oriole) Pixel 6a (bluejay) and Pixel 6 pro (raven) mobile
phones. It features:
* 4xA55 little cluster
* 2xA76 Mid cluster
* 2xX1 Big cluster
This commit adds the basic device tree for gs101 (SoC) and oriole
(pixel 6). Further platform support will be added over time.
It has been tested with a minimal busybox initramfs and boots to
a shell.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
arch/arm64/Kconfig.platforms | 6 +
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/google/Makefile | 6 +
arch/arm64/boot/dts/google/gs101-oriole.dts | 68 +
arch/arm64/boot/dts/google/gs101-pinctrl.dtsi | 1134 +++++++++++++++++
arch/arm64/boot/dts/google/gs101-pinctrl.h | 17 +
arch/arm64/boot/dts/google/gs101.dtsi | 501 ++++++++
7 files changed, 1733 insertions(+)
create mode 100644 arch/arm64/boot/dts/google/Makefile
create mode 100644 arch/arm64/boot/dts/google/gs101-oriole.dts
create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.dtsi
create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.h
create mode 100644 arch/arm64/boot/dts/google/gs101.dtsi
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 6069120199bb..a5ed1b719488 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -107,6 +107,12 @@ config ARCH_EXYNOS
help
This enables support for ARMv8 based Samsung Exynos SoC family.
+config ARCH_GOOGLE_TENSOR
+ bool "Google Tensor SoC fmaily"
+ depends on ARCH_EXYNOS
+ help
+ Support for ARMv8 based Google Tensor platforms.
+
config ARCH_SPARX5
bool "Microchip Sparx5 SoC family"
select PINCTRL
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 30dd6347a929..a4ee7b628114 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -13,6 +13,7 @@ subdir-y += broadcom
subdir-y += cavium
subdir-y += exynos
subdir-y += freescale
+subdir-y += google
subdir-y += hisilicon
subdir-y += intel
subdir-y += lg
diff --git a/arch/arm64/boot/dts/google/Makefile b/arch/arm64/boot/dts/google/Makefile
new file mode 100644
index 000000000000..6d2026a767d4
--- /dev/null
+++ b/arch/arm64/boot/dts/google/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0
+
+dtb-$(CONFIG_ARCH_GOOGLE_TENSOR) += \
+ gs101-oriole.dtb \
+
+
diff --git a/arch/arm64/boot/dts/google/gs101-oriole.dts b/arch/arm64/boot/dts/google/gs101-oriole.dts
new file mode 100644
index 000000000000..e531a39a76a4
--- /dev/null
+++ b/arch/arm64/boot/dts/google/gs101-oriole.dts
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Oriole DVT Device Tree
+ *
+ * Copyright 2021-2023 Google,LLC
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "gs101-pinctrl.h"
+#include "gs101.dtsi"
+
+/ {
+ model = "Oriole DVT";
+ compatible = "google,gs101-oriole", "google,gs101";
+};
+
+&pinctrl_1 {
+ key_voldown: key-voldown-pins {
+ samsung,pins = "gpa7-3";
+ samsung,pin-function = <0xf>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ key_volup: key-volup-pins {
+ samsung,pins = "gpa8-1";
+ samsung,pin-function = <0xf>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+};
+
+&pinctrl_0 {
+ key_power: key-power-pins {
+ samsung,pins = "gpa10-1";
+ samsung,pin-function = <0xf>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+};
+
+&gpio_keys {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&key_voldown &key_volup &key_power>;
+ button-vol-down {
+ label = "KEY_VOLUMEDOWN";
+ linux,code = <114>;
+ gpios = <&gpa7 3 0xf>;
+ wakeup-source;
+ };
+ button-vol-up {
+ label = "KEY_VOLUMEUP";
+ linux,code = <115>;
+ gpios = <&gpa8 1 0xf>;
+ wakeup-source;
+ };
+ button-power {
+ label = "KEY_POWER";
+ linux,code = <116>;
+ gpios = <&gpa10 1 0xf>;
+ wakeup-source;
+ };
+};
diff --git a/arch/arm64/boot/dts/google/gs101-pinctrl.dtsi b/arch/arm64/boot/dts/google/gs101-pinctrl.dtsi
new file mode 100644
index 000000000000..24825205ede8
--- /dev/null
+++ b/arch/arm64/boot/dts/google/gs101-pinctrl.dtsi
@@ -0,0 +1,1134 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * GS101 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright 2019-2023 Google LLC
+ *
+ */
+
+#include <dt-bindings/interrupt-controller/gs101.h>
+#include <arm64/exynos/exynos-pinctrl.h>
+#include "gs101-pinctrl.h"
+
+/ {
+ /* GPIO_ALIVE */
+ pinctrl@174d0000 {
+ gpa0: gpa0-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI IRQ_ALIVE_EINT0 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT1 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT2 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT3 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT4 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT5 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT6 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT7 ITLH>;
+ };
+ gpa1: gpa1-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI IRQ_ALIVE_EINT8 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT9 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT10 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT11 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT12 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT13 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT14 ITLH>;
+ };
+ gpa2: gpa2-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI IRQ_ALIVE_EINT15 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT16 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT17 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT18 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT19 ITLH>;
+ };
+ gpa3: gpa3-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI IRQ_ALIVE_EINT20 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT21 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT22 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT23 ITLH>;
+ };
+ gpa4: gpa4-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI IRQ_ALIVE_EINT24 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT25 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT26 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT27 ITLH>;
+ };
+ gpa5: gpa5-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI IRQ_ALIVE_EINT28 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT29 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT30 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT31 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT32 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT33 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT34 ITLH>;
+ };
+ gpa9: gpa9-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI IRQ_ALIVE_EINT35 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT36 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT37 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT38 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT39 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT40 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT41 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT42 ITLH>;
+ };
+ gpa10: gpa10-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI IRQ_ALIVE_EINT43 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT44 ITLH>;
+ };
+
+ uart15_bus: uart15-bus-pins {
+ samsung,pins = "gpa2-3", "gpa2-4";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ };
+
+ uart16_bus: uart16-bus-pins {
+ samsung,pins = "gpa3-0", "gpa3-1", "gpa3-2", "gpa3-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ uart16_bus_rts: uart1-bus-rts-pins {
+ samsung,pins = "gpa3-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-val = <1>;
+ };
+
+ uart16_bus_tx_dat: uart1-bus-tx-dat-pins {
+ samsung,pins = "gpa3-1";
+ samsung,pin-val = <1>;
+ };
+
+ uart16_bus_tx_con: uart1-bus-tx-con-pins {
+ samsung,pins = "gpa3-1";
+ samsung,pin-function = <1>;
+ };
+
+ uart17_bus: uart17-bus-pins {
+ samsung,pins = "gpa4-0", "gpa4-1", "gpa4-2", "gpa4-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ };
+
+ spi15_bus: spi15-bus-pins {
+ samsung,pins = "gpa4-0", "gpa4-1", "gpa4-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi15_cs: spi15-cs-pins {
+ samsung,pins = "gpa4-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ };
+ /* GPIO_FAR_ALIVE */
+ pinctrl@174e0000 {
+ gpa6: gpa6-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI IRQ_ALIVE_EINT45 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT46 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT47 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT48 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT49 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT50 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT51 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT52 ITLH>;
+ };
+ gpa7: gpa7-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI IRQ_ALIVE_EINT53 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT54 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT55 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT56 ITLH>;
+ };
+ gpa8: gpa8-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI IRQ_ALIVE_EINT57 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT58 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT59 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT60 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT61 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT62 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT63 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT64 ITLH>;
+ };
+ gpa11: gpa11-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI IRQ_ALIVE_EINT65 ITLH>,
+ <GIC_SPI IRQ_ALIVE_EINT66 ITLH>;
+ };
+
+ };
+ /* GPIO_GSACORE */
+ pinctrl@17a80000 {
+ gps0: gps0-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gps1: gps1-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gps2: gps2-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+ /* GPIO_GSACTRL */
+ pinctrl@17940000 {
+ gps3: gps3-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+ /* GPIO_HSI1 */
+ pinctrl@11840000 {
+ gph0: gph0-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gph1: gph1-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ pcie0_clkreq: pcie0-clkreq-pins{
+ samsung,pins = "gph0-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <GS101_PIN_DRV_10_MA>;
+ samsung,pin-con-pdn = <3>;
+ samsung,pin-pud-pdn = <3>;
+ };
+ pcie0_perst: pcie0-perst-pins {
+ samsung,pins = "gph0-0";
+ samsung,pin-function = <1>;
+ samsung,pin-drv = <GS101_PIN_DRV_10_MA>;
+ samsung,pin-con-pdn = <3>;
+ };
+ };
+ /* GPIO_HSI2 */
+ pinctrl@14440000 {
+ gph2: gph2-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gph3: gph3-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gph4: gph4-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ sd2_clk: sd2-clk-pins {
+ samsung,pins = "gph4-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>;
+ };
+
+ sd2_cmd: sd2-cmd-pins {
+ samsung,pins = "gph4-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>;
+ };
+
+ sd2_bus1: sd2-bus-width1-pins {
+ samsung,pins = "gph4-2";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>;
+ };
+
+ sd2_bus4: sd2-bus-width4-pins {
+ samsung,pins = "gph4-3", "gph4-4", "gph4-5";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>;
+ };
+
+ sd2_clk_fast_slew_rate_1x: sd2-clk-fast-slew-rate-1x-pins {
+ samsung,pins = "gph4-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ sd2_clk_fast_slew_rate_2x: sd2-clk-fast-slew-rate-2x-pins {
+ samsung,pins = "gph4-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+ };
+
+ sd2_clk_fast_slew_rate_3x: sd2-clk-fast-slew-rate-3x-pins {
+ samsung,pins = "gph4-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>;
+ };
+
+ sd2_clk_fast_slew_rate_4x: sd2-clk-fast-slew-rate-4x-pins {
+ samsung,pins = "gph4-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_10_MA>;
+ };
+ ufs_rst_n: ufs-rst-n-pins {
+ samsung,pins = "gph3-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-con-pdn = <3>;
+ samsung,pin-pud-pdn = <0>;
+ };
+
+ ufs_refclk_out: ufs-refclk-out-pins {
+ samsung,pins = "gph3-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-con-pdn = <3>;
+ samsung,pin-pud-pdn = <0>;
+ };
+ pcie1_clkreq: pcie1-clkreq-pins {
+ samsung,pins = "gph2-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <GS101_PIN_DRV_10_MA>;
+ samsung,pin-con-pdn = <3>;
+ samsung,pin-pud-pdn = <3>;
+ };
+ pcie1_perst: pcie1-perst-pins {
+ samsung,pins = "gph2-0";
+ samsung,pin-function = <1>;
+ samsung,pin-drv = <GS101_PIN_DRV_10_MA>;
+ samsung,pin-con-pdn = <3>;
+ };
+ };
+ /* GPIO_PERIC0 */
+ pinctrl@10840000 {
+ gpp0: gpp0-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp1: gpp1-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp2: gpp2-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp3: gpp3-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp4: gpp4-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp5: gpp5-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp6: gpp6-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp7: gpp7-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp8: gpp8-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp9: gpp9-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp10: gpp10-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp11: gpp11-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp12: gpp12-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp13: gpp13-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp14: gpp14-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp15: gpp15-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp16: gpp16-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp17: gpp17-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp18: gpp18-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp19: gpp19-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ /* USI_PERIC0_UART_DBG */
+ uart0_bus: uart0-bus-pins {
+ samsung,pins = "gpp1-2", "gpp1-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ };
+
+ disp_te_pri_on: disp-te-pri-on-pins {
+ samsung,pins = "gpp0-3";
+ samsung,pin-function = <0xf>;
+ };
+
+ disp_te_pri_off: disp-te-pri-off-pins {
+ samsung,pins = "gpp0-3";
+ samsung,pin-function = <0>;
+ };
+
+ disp_te_sec_on: disp-te-sec-on-pins {
+ samsung,pins = "gpp0-4";
+ samsung,pin-function = <0xf>;
+ };
+
+ disp_te_sec_off: disp-te-sec-off-pins {
+ samsung,pins = "gpp0-4";
+ samsung,pin-function = <0>;
+ };
+
+ sensor_mclk1_out: sensor-mclk1-out-pins {
+ samsung,pins = "gpp3-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+ };
+ sensor_mclk1_fn: sensor-mclk1-fn-pins {
+ samsung,pins = "gpp3-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+ };
+ sensor_mclk2_out: sensor-mclk2-out-pins {
+ samsung,pins = "gpp5-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+ };
+ sensor_mclk2_fn: sensor-mclk2-fn-pins {
+ samsung,pins = "gpp5-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+ };
+ sensor_mclk3_out: sensor-mclk3-out-pins {
+ samsung,pins = "gpp7-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+ };
+ sensor_mclk3_fn: sensor-mclk3-fn-pins {
+ samsung,pins = "gpp7-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+ };
+ sensor_mclk4_out: sensor-mclk4-out-pins {
+ samsung,pins = "gpp9-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+ };
+ sensor_mclk4_fn: sensor-mclk4-fn-pins {
+ samsung,pins = "gpp9-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+ };
+ sensor_mclk5_out: sensor-mclk5-out-pins {
+ samsung,pins = "gpp11-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+ };
+ sensor_mclk5_fn: sensor-mclk5-fn-pins {
+ samsung,pins = "gpp11-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+ };
+ sensor_mclk6_out: sensor-mclk6-out-pins {
+ samsung,pins = "gpp13-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+ };
+ sensor_mclk6_fn: sensor-mclk6-fn-pins {
+ samsung,pins = "gpp13-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+ };
+ sensor_mclk7_out: sensor-mclk7-out-pins {
+ samsung,pins = "gpp15-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+ };
+ sensor_mclk7_fn: sensor-mclk7-fn-pins {
+ samsung,pins = "gpp15-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+ };
+ sensor_mclk8_out: sensor-mclk8-out-pins {
+ samsung,pins = "gpp17-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+ };
+ sensor_mclk8_fn: sensor-mclk8-fn-pins {
+ samsung,pins = "gpp17-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+ };
+ hsi2c14_bus: hsi2c14-bus-pins {
+ samsung,pins = "gpp18-0", "gpp18-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ uart14_bus_single: uart14-bus-pins {
+ samsung,pins = "gpp18-0", "gpp18-1",
+ "gpp18-2", "gpp18-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ };
+ spi14_bus: spi14-bus-pins {
+ samsung,pins = "gpp18-0", "gpp18-1", "gpp18-2";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi14_cs: spi14-cs-pins {
+ samsung,pins = "gpp18-3";
+ samsung,pin-function = <1>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi14_cs_func: spi14-cs-func-pins {
+ samsung,pins = "gpp18-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ hsi2c8_bus: hsi2c8-bus-pins {
+ samsung,pins = "gpp16-0", "gpp16-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ samsung,pin-pud-pdn = <EXYNOS_PIN_PDN_OUT0>;
+ };
+ uart8_bus_single: uart8-bus-pins {
+ samsung,pins = "gpp16-0", "gpp16-1", "gpp16-2",
+ "gpp16-3";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ };
+ spi8_bus: spi8-bus-pins {
+ samsung,pins = "gpp16-0", "gpp16-1", "gpp16-2";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi8_cs: spi8-cs-pins {
+ samsung,pins = "gpp16-3";
+ samsung,pin-function = <1>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi8_cs_func: spi8-cs-func-pins {
+ samsung,pins = "gpp16-3";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ hsi2c7_bus: hsi2c7-bus-pins {
+ samsung,pins = "gpp14-0", "gpp14-1";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ uart7_bus_single: uart7-bus-pins {
+ samsung,pins = "gpp14-0", "gpp14-1",
+ "gpp14-2", "gpp14-3";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ };
+ spi7_bus: spi7-bus-pins {
+ samsung,pins = "gpp14-0", "gpp14-1", "gpp14-2";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi7_cs: spi7-cs-pins {
+ samsung,pins = "gpp14-3";
+ samsung,pin-function = <1>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi7_cs_func: spi7-cs-func-pins {
+ samsung,pins = "gpp14-3";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ hsi2c6_bus: hsi2c6-bus-pins {
+ samsung,pins = "gpp12-0", "gpp12-1";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ uart6_bus_single: uart6-bus-pins {
+ samsung,pins = "gpp12-0", "gpp12-1",
+ "gpp12-2", "gpp12-3";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ };
+ spi6_bus: spi6-bus-pins {
+ samsung,pins = "gpp12-0", "gpp12-1", "gpp12-2";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi6_cs: spi6-cs-pins {
+ samsung,pins = "gpp12-3";
+ samsung,pin-function = <1>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi6_cs_func: spi6-cs-func-pins {
+ samsung,pins = "gpp12-3";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ hsi2c5_bus: hsi2c5-bus-pins {
+ samsung,pins = "gpp10-0", "gpp10-1";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ uart5_bus_single: uart5-bus-pins {
+ samsung,pins = "gpp10-0", "gpp10-1",
+ "gpp10-2", "gpp10-3";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ };
+ spi5_bus: spi5-bus-pins {
+ samsung,pins = "gpp10-0", "gpp10-1", "gpp10-2";
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
+ samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>;
+ };
+ spi5_cs_func: spi5-cs-func-pins {
+ samsung,pins = "gpp10-3";
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
+ samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>;
+ };
+ hsi2c4_bus: hsi2c4-bus-pins {
+ samsung,pins = "gpp8-0", "gpp8-1";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ uart4_bus_single: uart4-bus-pins {
+ samsung,pins = "gpp8-0", "gpp8-1",
+ "gpp8-2", "gpp8-3";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ };
+ spi4_bus: spi4-bus-pins {
+ samsung,pins = "gpp8-0", "gpp8-1", "gpp8-2";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi4_cs: spi4-cs-pins {
+ samsung,pins = "gpp8-3";
+ samsung,pin-function = <1>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi4_cs_func: spi4-cs-func-pins {
+ samsung,pins = "gpp8-3";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ hsi2c3_bus: hsi2c3-bus-pins {
+ samsung,pins = "gpp6-0", "gpp6-1";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ uart3_bus_single: uart3-bus-pins {
+ samsung,pins = "gpp6-0", "gpp6-1",
+ "gpp6-2", "gpp6-3";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ };
+ spi3_bus: spi3-bus-pins {
+ samsung,pins = "gpp6-0", "gpp6-1", "gpp6-2";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi3_cs: spi3-cs-pins {
+ samsung,pins = "gpp6-3";
+ samsung,pin-function = <1>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi3_cs_func: spi3-cs-func-pins {
+ samsung,pins = "gpp6-3";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ hsi2c2_bus: hsi2c2-bus-pins {
+ samsung,pins = "gpp4-0", "gpp4-1";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ uart2_bus_single: uart2-bus-pins {
+ samsung,pins = "gpp4-0", "gpp4-1",
+ "gpp4-2", "gpp4-3";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ };
+ spi2_bus: spi2-bus-pins {
+ samsung,pins = "gpp4-0", "gpp4-1", "gpp4-2";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi2_cs: spi2-cs-pins {
+ samsung,pins = "gpp4-3";
+ samsung,pin-function = <1>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi2_cs_func: spi2-cs-func-pins {
+ samsung,pins = "gpp4-3";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ hsi2c1_bus: hsi2c1-bus-pins {
+ samsung,pins = "gpp2-0", "gpp2-1";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ uart1_bus_single: uart1-bus-pins {
+ samsung,pins = "gpp2-0", "gpp2-1",
+ "gpp2-2", "gpp2-3";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ };
+ spi1_bus: spi1-bus-pins {
+ samsung,pins = "gpp2-0", "gpp2-1", "gpp2-2";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi1_cs: spi1-cs-pins {
+ samsung,pins = "gpp2-3";
+ samsung,pin-function = <1>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi1_cs_func: spi1-cs-func-pins {
+ samsung,pins = "gpp2-3";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ };
+ /* GPIO_PERIC1 */
+ pinctrl@10c40000 {
+ gpp20: gpp20-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp21: gpp21-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp22: gpp22-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp23: gpp23-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp24: gpp24-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp25: gpp25-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp26: gpp26-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp27: gpp27-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ hsi2c13_bus: hsi2c13-bus-pins {
+ samsung,pins = "gpp25-0", "gpp25-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ uart13_bus_single: uart13-bus-pins {
+ samsung,pins = "gpp25-0", "gpp25-1",
+ "gpp25-2", "gpp25-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ };
+ spi13_bus: spi13-bus-pins {
+ samsung,pins = "gpp25-0", "gpp25-1", "gpp25-2";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi13_cs: spi13-cs-pins {
+ samsung,pins = "gpp25-3";
+ samsung,pin-function = <1>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi13_cs_func: spi13-cs-func-pins {
+ samsung,pins = "gpp25-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ hsi2c12_bus: hsi2c12-bus-pins {
+ samsung,pins = "gpp23-4", "gpp23-5";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ uart12_bus_single: uart12-bus-pins {
+ samsung,pins = "gpp23-4", "gpp23-5",
+ "gpp23-6", "gpp23-7";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ };
+ spi12_bus: spi12-bus-pins {
+ samsung,pins = "gpp23-4", "gpp23-5", "gpp23-6";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi14_cs2: spi14-cs2-pins {
+ samsung,pins = "gpp23-6";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi12_cs: spi12-cs-pins {
+ samsung,pins = "gpp23-7";
+ samsung,pin-function = <1>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi12_cs_func: spi12-cs-func-pins {
+ samsung,pins = "gpp23-7";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ hsi2c11_bus: hsi2c11-bus-pins {
+ samsung,pins = "gpp23-0", "gpp23-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ uart11_bus_single: uart11-bus-pins {
+ samsung,pins = "gpp23-0", "gpp23-1",
+ "gpp23-2", "gpp23-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ };
+ spi11_bus: spi11-bus-pins {
+ samsung,pins = "gpp23-0", "gpp23-1", "gpp23-2";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi11_cs: spi11-cs-pins {
+ samsung,pins = "gpp23-3";
+ samsung,pin-function = <1>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi11_cs_func: spi11-cs-func-pins {
+ samsung,pins = "gpp23-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ hsi2c10_bus: hsi2c10-bus-pins {
+ samsung,pins = "gpp21-0", "gpp21-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ uart10_bus_single: uart10-bus-pins {
+ samsung,pins = "gpp21-0", "gpp21-1",
+ "gpp21-2", "gpp21-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ };
+ spi10_bus: spi10-bus-pins {
+ samsung,pins = "gpp21-0", "gpp21-1", "gpp21-2";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi10_cs: spi10-cs-pins {
+ samsung,pins = "gpp21-3";
+ samsung,pin-function = <1>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi10_cs_func: spi10-cs-func-pins {
+ samsung,pins = "gpp21-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ hsi2c9_bus: hsi2c9-bus-pins {
+ samsung,pins = "gpp20-4", "gpp20-5";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ uart9_bus_single: uart9-bus-pins {
+ samsung,pins = "gpp20-4", "gpp20-5",
+ "gpp20-6", "gpp20-7";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ };
+ spi9_bus: spi9-bus-pins {
+ samsung,pins = "gpp20-4", "gpp20-5", "gpp20-6";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi9_cs: spi9-cs-pins {
+ samsung,pins = "gpp20-7";
+ samsung,pin-function = <1>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi9_cs_func: spi9-cs-func-pins {
+ samsung,pins = "gpp20-7";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ hsi2c0_bus: hsi2c0-bus-pins {
+ samsung,pins = "gpp20-0", "gpp20-1";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ uart0_bus_single: uart0-bus-pins {
+ samsung,pins = "gpp20-0", "gpp20-1",
+ "gpp20-2", "gpp20-3";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ };
+ spi0_bus: spi0-bus-pins {
+ samsung,pins = "gpp20-0", "gpp20-1", "gpp20-2";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi0_cs: spi0-cs-pins {
+ samsung,pins = "gpp20-3";
+ samsung,pin-function = <1>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ spi0_cs_func: spi0-cs-func-pins {
+ samsung,pins = "gpp20-3";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/google/gs101-pinctrl.h b/arch/arm64/boot/dts/google/gs101-pinctrl.h
new file mode 100644
index 000000000000..acc77c684f0d
--- /dev/null
+++ b/arch/arm64/boot/dts/google/gs101-pinctrl.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Pinctrl binding constants for GS101
+ *
+ * Copyright (c) 2020-2023 Google, LLC.
+ */
+
+#ifndef __DT_BINDINGS_PINCTRL_GS101_H__
+#define __DT_BINDINGS_PINCTRL_GS101_H__
+
+/* GS101 drive strengths */
+#define GS101_PIN_DRV_2_5_MA 0
+#define GS101_PIN_DRV_5_MA 1
+#define GS101_PIN_DRV_7_5_MA 2
+#define GS101_PIN_DRV_10_MA 3
+
+#endif /* __DT_BINDINGS_PINCTRL_GS101_H__ */
diff --git a/arch/arm64/boot/dts/google/gs101.dtsi b/arch/arm64/boot/dts/google/gs101.dtsi
new file mode 100644
index 000000000000..0bd43745f6fa
--- /dev/null
+++ b/arch/arm64/boot/dts/google/gs101.dtsi
@@ -0,0 +1,501 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * GS101 SoC
+ *
+ * Copyright 2019-2023 Google LLC
+ *
+ */
+
+#include <dt-bindings/clock/gs101.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/gs101.h>
+
+#include "gs101-pinctrl.dtsi"
+
+/ {
+ compatible = "google,gs101";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ aliases {
+ pinctrl0 = &pinctrl_0;
+ pinctrl1 = &pinctrl_1;
+ pinctrl2 = &pinctrl_2;
+ pinctrl3 = &pinctrl_3;
+ pinctrl4 = &pinctrl_4;
+ pinctrl5 = &pinctrl_5;
+ pinctrl6 = &pinctrl_6;
+ pinctrl7 = &pinctrl_7;
+
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+ cluster1 {
+ core0 {
+ cpu = <&cpu4>;
+ };
+ core1 {
+ cpu = <&cpu5>;
+ };
+ };
+ cluster2 {
+ core0 {
+ cpu = <&cpu6>;
+ };
+ core1 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x0000>;
+ enable-method = "psci";
+ cpu-idle-states = <&ANANKE_CPU_SLEEP>;
+ capacity-dmips-mhz = <250>;
+ dynamic-power-coefficient = <70>;
+ };
+ cpu1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x0100>;
+ enable-method = "psci";
+ cpu-idle-states = <&ANANKE_CPU_SLEEP>;
+ capacity-dmips-mhz = <250>;
+ dynamic-power-coefficient = <70>;
+ };
+ cpu2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x0200>;
+ enable-method = "psci";
+ cpu-idle-states = <&ANANKE_CPU_SLEEP>;
+ capacity-dmips-mhz = <250>;
+ dynamic-power-coefficient = <70>;
+ };
+ cpu3: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x0300>;
+ enable-method = "psci";
+ cpu-idle-states = <&ANANKE_CPU_SLEEP>;
+ capacity-dmips-mhz = <250>;
+ dynamic-power-coefficient = <70>;
+ };
+ cpu4: cpu@400 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x0400>;
+ enable-method = "psci";
+ cpu-idle-states = <&ENYO_CPU_SLEEP>;
+ capacity-dmips-mhz = <620>;
+ dynamic-power-coefficient = <284>;
+ };
+ cpu5: cpu@500 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x0500>;
+ enable-method = "psci";
+ cpu-idle-states = <&ENYO_CPU_SLEEP>;
+ capacity-dmips-mhz = <620>;
+ dynamic-power-coefficient = <284>;
+ };
+ cpu6: cpu@600 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x0600>;
+ enable-method = "psci";
+ cpu-idle-states = <&HERA_CPU_SLEEP>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <650>;
+ };
+ cpu7: cpu@700 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x0700>;
+ enable-method = "psci";
+ cpu-idle-states = <&HERA_CPU_SLEEP>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <650>;
+ };
+
+ idle-states {
+ entry-method = "psci";
+
+ ANANKE_CPU_SLEEP: cpu-ananke-sleep {
+ idle-state-name = "c2";
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x0010000>;
+ entry-latency-us = <70>;
+ exit-latency-us = <160>;
+ min-residency-us = <2000>;
+ status = "okay";
+ };
+
+ ENYO_CPU_SLEEP: cpu-enyo-sleep {
+ idle-state-name = "c2";
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x0010000>;
+ entry-latency-us = <150>;
+ exit-latency-us = <190>;
+ min-residency-us = <2500>;
+ status = "okay";
+ };
+
+ HERA_CPU_SLEEP: cpu-hera-sleep {
+ idle-state-name = "c2";
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x0010000>;
+ entry-latency-us = <235>;
+ exit-latency-us = <220>;
+ min-residency-us = <3500>;
+ status = "okay";
+ };
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+
+ tpu_fw_reserved: tpu_fw@93000000 {
+ reg = <0x0 0x93000000 0x1000000>;
+ no-map;
+ };
+
+ gsa_reserved_protected: gsa@90200000 {
+ reg = <0x0 0x90200000 0x400000>;
+ no-map;
+ };
+
+ aoc_reserve: aoc@94000000 {
+ reg = <0x0 0x94000000 0x03000000>;
+ no-map;
+ };
+
+ abl_reserved: abl@f8800000 {
+ reg = <0x0 0xf8800000 0x02000000>;
+ no-map;
+ };
+
+ dss_log_reserved: dss_log_reserved@fd3f0000 {
+ reg = <0 0xfd3f0000 0x0000e000>;
+ no-map;
+ };
+
+ debug_kinfo_reserved: debug_kinfo_reserved@fd3fe000 {
+ reg = <0 0xfd3fe000 0x00001000>;
+ no-map;
+ };
+
+ bldr_log_reserved: bldr_log_reserved@fd800000 {
+ reg = <0 0xfd800000 0x00100000>;
+ no-map;
+ };
+
+ bldr_log_hist_reserved: bldr_log_hist_reserved@fd900000 {
+ reg = <0 0xfd900000 0x00002000>;
+ no-map;
+ };
+ };
+
+ /* bootloader requires ect node */
+ ect {
+ parameter_address = <0x90000000>;
+ parameter_size = <0x53000>;
+ };
+
+ chosen {
+ bootargs = "earlycon=exynos4210,mmio32,0x10A00000 clk_ignore_unused";
+ };
+
+ gic: interrupt-controller@10400000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x0 0x10400000 0x10000>, /* GICD */
+ <0x0 0x10440000 0x100000>; /* GICR * 8 */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ clock-frequency = <24576000>;
+ };
+
+ ext_24_5m: ext_24_5m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24576000>;
+ clock-output-names = "oscclk";
+ };
+
+ ext_200m: ext_200m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ clock-output-names = "ext-200m";
+ };
+
+ /* GPIO_ALIVE */
+ pinctrl_0: pinctrl@174d0000 {
+ compatible = "google,gs101-pinctrl";
+ reg = <0x00000000 0x174d0000 0x00001000>;
+ interrupts = <GIC_SPI IRQ_ALIVE_EINT0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT10 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT15 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT17 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT19 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT20 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT21 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT22 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT23 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT24 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT25 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT26 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT27 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT28 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT29 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT30 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT31 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT33 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT34 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT35 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT36 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT37 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT38 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT39 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT40 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT41 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT43 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT44 IRQ_TYPE_LEVEL_HIGH>;
+
+ wakeup-interrupt-controller {
+ compatible = "google,gs101-wakeup-eint";
+ };
+ };
+
+ /* GPIO_FAR_ALIVE */
+ pinctrl_1: pinctrl@174e0000 {
+ compatible = "google,gs101-pinctrl";
+ reg = <0x00000000 0x174e0000 0x00001000>;
+ interrupts = <GIC_SPI IRQ_ALIVE_EINT45 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT46 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT47 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT48 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT49 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT50 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT51 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT52 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT53 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT54 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT55 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT56 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT57 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT58 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT59 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT60 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT61 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT62 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT63 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT64 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT65 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI IRQ_ALIVE_EINT66 IRQ_TYPE_LEVEL_HIGH>;
+
+ wakeup-interrupt-controller {
+ compatible = "google,gs101-wakeup-eint";
+ };
+ };
+
+ /* GPIO_GSACORE */
+ pinctrl_2: pinctrl@17a80000 {
+ compatible = "google,gs101-pinctrl";
+ reg = <0x00000000 0x17a80000 0x00001000>;
+ };
+ /* GPIO_GSACTRL */
+ pinctrl_3: pinctrl@17940000 {
+ compatible = "google,gs101-pinctrl";
+ reg = <0x00000000 0x17940000 0x00001000>;
+ };
+ /* GPIO_PERIC0 */
+ pinctrl_4: pinctrl@10840000 {
+ compatible = "google,gs101-pinctrl";
+ reg = <0x00000000 0x10840000 0x00001000>;
+ interrupts = <GIC_SPI IRQ_GPIO_PERIC0_PERIC0 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ /* GPIO_PERIC1 */
+ pinctrl_5: pinctrl@10c40000 {
+ compatible = "google,gs101-pinctrl";
+ reg = <0x00000000 0x10C40000 0x00001000>;
+ interrupts = <GIC_SPI IRQ_GPIO_PERIC1_PERIC1 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ /* GPIO_HSI1 */
+ pinctrl_6: pinctrl@11840000 {
+ compatible = "google,gs101-pinctrl";
+ reg = <0x00000000 0x11840000 0x00001000>;
+ interrupts = <GIC_SPI IRQ_GPIO_HSI1_HSI1 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ /* GPIO_HSI2 */
+ pinctrl_7: pinctrl@14440000 {
+ compatible = "google,gs101-pinctrl";
+ reg = <0x00000000 0x14440000 0x00001000>;
+ interrupts = <GIC_SPI IRQ_GPIO_HSI2_HSI2 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ arm-pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ sysreg_apm: syscon@174204e0 {
+ compatible = "google,gs101-apm-sysreg",
+ "google,gs101-sysreg", "syscon";
+ reg = <0x0 0x174204e0 0x1000>;
+ };
+
+ sysreg_peric0: syscon@10821000 {
+ compatible = "google,gs101-peric0-sysreg",
+ "google,gs101-sysreg", "syscon";
+ reg = <0x0 0x10821000 0x40000>;
+ };
+
+ sysreg_peric1: syscon@10c21000 {
+ compatible = "google,gs101-peric1-sysreg",
+ "google,gs101-sysreg", "syscon";
+ reg = <0x0 0x10C21000 0x40000>;
+ };
+
+ /* TODO replace with CCF clock */
+ dummy_clk: oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <12345>;
+ clock-output-names = "pclk";
+ };
+
+ serial_0: serial@10a00000 {
+ compatible = "samsung,exynos850-uart";
+ reg = <0x0 0x10a00000 0xc0>;
+ reg-io-width = <4>;
+ samsung,uart-fifosize = <256>;
+ interrupts = <GIC_SPI IRQ_USI0_UART_PERIC0 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&dummy_clk 0>, <&dummy_clk 0>;
+ clock-names = "uart", "clk_uart_baud0";
+ status = "okay";
+ };
+
+ pmu_system_controller: system-controller@17460000 {
+ compatible = "google,gs101-pmu", "syscon";
+ reg = <0x0 0x17460000 0x10000>;
+ };
+
+ watchdog_cl0: watchdog@10060000 {
+ compatible = "google,gs101-wdt";
+ reg = <0x0 0x10060000 0x100>;
+ interrupts = <GIC_SPI IRQ_WDT_CLUSTER0_MISC IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER0>, <&ext_24_5m>;
+ clock-names = "watchdog", "watchdog_src";
+ timeout-sec = <30>;
+ samsung,syscon-phandle = <&pmu_system_controller>;
+ samsung,cluster-index = <0>;
+ };
+
+ watchdog_cl1: watchdog@10070000 {
+ compatible = "google,gs101-wdt";
+ reg = <0x0 0x10070000 0x100>;
+ interrupts = <GIC_SPI IRQ_WDT_CLUSTER1_MISC IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER1>, <&ext_24_5m>;
+ clock-names = "watchdog", "watchdog_src";
+ timeout-sec = <30>;
+ samsung,syscon-phandle = <&pmu_system_controller>;
+ samsung,cluster-index = <1>;
+ status = "disabled";
+ };
+
+ cmu_top: clock-controller@1e080000 {
+ compatible = "google,gs101-cmu-top";
+ reg = <0x0 0x1e080000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&ext_24_5m>;
+ clock-names = "oscclk";
+ };
+
+ cmu_apm: clock-controller@17400000 {
+ compatible = "google,gs101-cmu-apm";
+ reg = <0x0 0x17400000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&ext_24_5m>;
+ clock-names = "oscclk";
+ };
+
+ cmu_misc: clock-controller@10010000 {
+ compatible = "google,gs101-cmu-misc";
+ reg = <0x0 0x10010000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&ext_24_5m>, <&cmu_top CLK_DOUT_MISC_BUS>;
+ clock-names = "oscclk", "dout_cmu_misc_bus";
+ };
+
+ dsu-pmu-0 {
+ compatible = "arm,dsu-pmu";
+ interrupts = <GIC_SPI IRQ_CPUCL0_CLUSTERPMUIRQ_CPUCL0 IRQ_TYPE_LEVEL_HIGH>;
+ cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
+ };
+
+ gpio_keys: gpio_keys {
+ compatible = "gpio-keys";
+ };
+
+};
--
2.42.0.582.g8ccd20d70d-goog
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^ permalink raw reply related [flat|nested] 150+ messages in thread* Re: [PATCH 18/21] arm64: dts: google: Add initial Google gs101 SoC support
2023-10-05 15:56 ` Peter Griffin
@ 2023-10-05 16:21 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 150+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-05 16:21 UTC (permalink / raw)
To: Peter Griffin, robh+dt, krzysztof.kozlowski+dt, mturquette,
conor+dt, sboyd, tomasz.figa, s.nawrocki, linus.walleij, wim,
linux, catalin.marinas, will, arnd, olof, cw00.choi
Cc: tudor.ambarus, andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog
On 05/10/2023 17:56, Peter Griffin wrote:
> Google gs101 SoC is ARMv8 mobile SoC found in the Pixel 6,
> (oriole) Pixel 6a (bluejay) and Pixel 6 pro (raven) mobile
> phones. It features:
> * 4xA55 little cluster
> * 2xA76 Mid cluster
> * 2xX1 Big cluster
>
> This commit adds the basic device tree for gs101 (SoC) and oriole
> (pixel 6). Further platform support will be added over time.
>
> It has been tested with a minimal busybox initramfs and boots to
> a shell.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> arch/arm64/Kconfig.platforms | 6 +
> arch/arm64/boot/dts/Makefile | 1 +
> arch/arm64/boot/dts/google/Makefile | 6 +
> arch/arm64/boot/dts/google/gs101-oriole.dts | 68 +
> arch/arm64/boot/dts/google/gs101-pinctrl.dtsi | 1134 +++++++++++++++++
> arch/arm64/boot/dts/google/gs101-pinctrl.h | 17 +
> arch/arm64/boot/dts/google/gs101.dtsi | 501 ++++++++
Please split adding DTSI from adding DTS into two patches.
> 7 files changed, 1733 insertions(+)
> create mode 100644 arch/arm64/boot/dts/google/Makefile
> create mode 100644 arch/arm64/boot/dts/google/gs101-oriole.dts
> create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.dtsi
> create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.h
> create mode 100644 arch/arm64/boot/dts/google/gs101.dtsi
>
> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
> index 6069120199bb..a5ed1b719488 100644
> --- a/arch/arm64/Kconfig.platforms
> +++ b/arch/arm64/Kconfig.platforms
> @@ -107,6 +107,12 @@ config ARCH_EXYNOS
> help
> This enables support for ARMv8 based Samsung Exynos SoC family.
>
> +config ARCH_GOOGLE_TENSOR
> + bool "Google Tensor SoC fmaily"
> + depends on ARCH_EXYNOS
> + help
> + Support for ARMv8 based Google Tensor platforms.
> +
> config ARCH_SPARX5
> bool "Microchip Sparx5 SoC family"
> select PINCTRL
> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
> index 30dd6347a929..a4ee7b628114 100644
> --- a/arch/arm64/boot/dts/Makefile
> +++ b/arch/arm64/boot/dts/Makefile
> @@ -13,6 +13,7 @@ subdir-y += broadcom
> subdir-y += cavium
> subdir-y += exynos
> subdir-y += freescale
> +subdir-y += google
> subdir-y += hisilicon
> subdir-y += intel
> subdir-y += lg
> diff --git a/arch/arm64/boot/dts/google/Makefile b/arch/arm64/boot/dts/google/Makefile
> new file mode 100644
> index 000000000000..6d2026a767d4
> --- /dev/null
> +++ b/arch/arm64/boot/dts/google/Makefile
> @@ -0,0 +1,6 @@
> +# SPDX-License-Identifier: GPL-2.0
> +
> +dtb-$(CONFIG_ARCH_GOOGLE_TENSOR) += \
> + gs101-oriole.dtb \
> +
> +
Too many blank lines
> diff --git a/arch/arm64/boot/dts/google/gs101-oriole.dts b/arch/arm64/boot/dts/google/gs101-oriole.dts
> new file mode 100644
> index 000000000000..e531a39a76a4
> --- /dev/null
> +++ b/arch/arm64/boot/dts/google/gs101-oriole.dts
> @@ -0,0 +1,68 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Oriole DVT Device Tree
> + *
> + * Copyright 2021-2023 Google,LLC
> + */
> +
> +/dts-v1/;
> +/plugin/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include "gs101-pinctrl.h"
> +#include "gs101.dtsi"
> +
> +/ {
> + model = "Oriole DVT";
> + compatible = "google,gs101-oriole", "google,gs101";
> +};
> +
> +&pinctrl_1 {
> + key_voldown: key-voldown-pins {
> + samsung,pins = "gpa7-3";
> + samsung,pin-function = <0xf>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> +
> + key_volup: key-volup-pins {
> + samsung,pins = "gpa8-1";
> + samsung,pin-function = <0xf>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> +};
> +
> +&pinctrl_0 {
> + key_power: key-power-pins {
> + samsung,pins = "gpa10-1";
> + samsung,pin-function = <0xf>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> +};
> +
> +&gpio_keys {
SoC does not have gpio-keys. That's entirely a property of the board.
> + status = "okay";
Drop
> + pinctrl-names = "default";
> + pinctrl-0 = <&key_voldown &key_volup &key_power>;
Blank line
> + button-vol-down {
> + label = "KEY_VOLUMEDOWN";
> + linux,code = <114>;
> + gpios = <&gpa7 3 0xf>;
> + wakeup-source;
> + };
Blank line
> + button-vol-up {
> + label = "KEY_VOLUMEUP";
> + linux,code = <115>;
> + gpios = <&gpa8 1 0xf>;
> + wakeup-source;
> + };
Blank line
> + button-power {
> + label = "KEY_POWER";
> + linux,code = <116>;
> + gpios = <&gpa10 1 0xf>;
> + wakeup-source;
> + };
> +};
> diff --git a/arch/arm64/boot/dts/google/gs101-pinctrl.dtsi b/arch/arm64/boot/dts/google/gs101-pinctrl.dtsi
> new file mode 100644
> index 000000000000..24825205ede8
> --- /dev/null
> +++ b/arch/arm64/boot/dts/google/gs101-pinctrl.dtsi
> @@ -0,0 +1,1134 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * GS101 SoC pin-mux and pin-config device tree source
> + *
> + * Copyright 2019-2023 Google LLC
> + *
> + */
> +
> +#include <dt-bindings/interrupt-controller/gs101.h>
> +#include <arm64/exynos/exynos-pinctrl.h>
> +#include "gs101-pinctrl.h"
> +
> +/ {
> + /* GPIO_ALIVE */
> + pinctrl@174d0000 {
> + gpa0: gpa0-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI IRQ_ALIVE_EINT0 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT1 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT2 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT3 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT4 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT5 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT6 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT7 ITLH>;
> + };
Blank line
> + gpa1: gpa1-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI IRQ_ALIVE_EINT8 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT9 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT10 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT11 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT12 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT13 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT14 ITLH>;
> + };
> + gpa2: gpa2-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI IRQ_ALIVE_EINT15 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT16 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT17 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT18 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT19 ITLH>;
> + };
> + gpa3: gpa3-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI IRQ_ALIVE_EINT20 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT21 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT22 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT23 ITLH>;
> + };
> + gpa4: gpa4-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI IRQ_ALIVE_EINT24 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT25 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT26 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT27 ITLH>;
> + };
> + gpa5: gpa5-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <GIC_SPI IRQ_ALIVE_EINT28 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT29 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT30 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT31 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT32 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT33 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT34 ITLH>;
> + };
> + gpa9: gpa9-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <GIC_SPI IRQ_ALIVE_EINT35 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT36 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT37 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT38 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT39 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT40 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT41 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT42 ITLH>;
> + };
> + gpa10: gpa10-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <GIC_SPI IRQ_ALIVE_EINT43 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT44 ITLH>;
> + };
> +
> + uart15_bus: uart15-bus-pins {
> + samsung,pins = "gpa2-3", "gpa2-4";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + };
> +
> + uart16_bus: uart16-bus-pins {
> + samsung,pins = "gpa3-0", "gpa3-1", "gpa3-2", "gpa3-3";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
You should rather create macros for your SoC... unless you are 100% sure
this matches Exynos arm64 pinctrl.
...
> diff --git a/arch/arm64/boot/dts/google/gs101-pinctrl.h b/arch/arm64/boot/dts/google/gs101-pinctrl.h
> new file mode 100644
> index 000000000000..acc77c684f0d
> --- /dev/null
> +++ b/arch/arm64/boot/dts/google/gs101-pinctrl.h
> @@ -0,0 +1,17 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Pinctrl binding constants for GS101
> + *
> + * Copyright (c) 2020-2023 Google, LLC.
> + */
> +
> +#ifndef __DT_BINDINGS_PINCTRL_GS101_H__
> +#define __DT_BINDINGS_PINCTRL_GS101_H__
> +
> +/* GS101 drive strengths */
> +#define GS101_PIN_DRV_2_5_MA 0
> +#define GS101_PIN_DRV_5_MA 1
> +#define GS101_PIN_DRV_7_5_MA 2
> +#define GS101_PIN_DRV_10_MA 3
> +
> +#endif /* __DT_BINDINGS_PINCTRL_GS101_H__ */
> diff --git a/arch/arm64/boot/dts/google/gs101.dtsi b/arch/arm64/boot/dts/google/gs101.dtsi
> new file mode 100644
> index 000000000000..0bd43745f6fa
> --- /dev/null
> +++ b/arch/arm64/boot/dts/google/gs101.dtsi
> @@ -0,0 +1,501 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * GS101 SoC
> + *
> + * Copyright 2019-2023 Google LLC
> + *
> + */
> +
> +#include <dt-bindings/clock/gs101.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/interrupt-controller/gs101.h>
> +
> +#include "gs101-pinctrl.dtsi"
> +
> +/ {
> + compatible = "google,gs101";
> + interrupt-parent = <&gic>;
> + #address-cells = <2>;
> + #size-cells = <1>;
> +
> + aliases {
> + pinctrl0 = &pinctrl_0;
> + pinctrl1 = &pinctrl_1;
> + pinctrl2 = &pinctrl_2;
> + pinctrl3 = &pinctrl_3;
> + pinctrl4 = &pinctrl_4;
> + pinctrl5 = &pinctrl_5;
> + pinctrl6 = &pinctrl_6;
> + pinctrl7 = &pinctrl_7;
> +
Stray blank line
> + };
> +
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&cpu0>;
> + };
> + core1 {
> + cpu = <&cpu1>;
> + };
> + core2 {
> + cpu = <&cpu2>;
> + };
> + core3 {
> + cpu = <&cpu3>;
> + };
> + };
Blank line
> + cluster1 {
> + core0 {
> + cpu = <&cpu4>;
> + };
> + core1 {
> + cpu = <&cpu5>;
> + };
> + };
Blank line
> + cluster2 {
> + core0 {
> + cpu = <&cpu6>;
> + };
> + core1 {
> + cpu = <&cpu7>;
> + };
> + };
> + };
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0x0 0x0000>;
> + enable-method = "psci";
> + cpu-idle-states = <&ANANKE_CPU_SLEEP>;
> + capacity-dmips-mhz = <250>;
> + dynamic-power-coefficient = <70>;
> + };
Blank line
> + cpu1: cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0x0 0x0100>;
> + enable-method = "psci";
> + cpu-idle-states = <&ANANKE_CPU_SLEEP>;
> + capacity-dmips-mhz = <250>;
> + dynamic-power-coefficient = <70>;
> + };
> + cpu2: cpu@200 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0x0 0x0200>;
> + enable-method = "psci";
> + cpu-idle-states = <&ANANKE_CPU_SLEEP>;
> + capacity-dmips-mhz = <250>;
> + dynamic-power-coefficient = <70>;
> + };
> + cpu3: cpu@300 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0x0 0x0300>;
> + enable-method = "psci";
> + cpu-idle-states = <&ANANKE_CPU_SLEEP>;
> + capacity-dmips-mhz = <250>;
> + dynamic-power-coefficient = <70>;
> + };
> + cpu4: cpu@400 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0x0 0x0400>;
> + enable-method = "psci";
> + cpu-idle-states = <&ENYO_CPU_SLEEP>;
> + capacity-dmips-mhz = <620>;
> + dynamic-power-coefficient = <284>;
> + };
> + cpu5: cpu@500 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0x0 0x0500>;
> + enable-method = "psci";
> + cpu-idle-states = <&ENYO_CPU_SLEEP>;
> + capacity-dmips-mhz = <620>;
> + dynamic-power-coefficient = <284>;
> + };
> + cpu6: cpu@600 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0x0 0x0600>;
> + enable-method = "psci";
> + cpu-idle-states = <&HERA_CPU_SLEEP>;
> + capacity-dmips-mhz = <1024>;
> + dynamic-power-coefficient = <650>;
> + };
> + cpu7: cpu@700 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0x0 0x0700>;
> + enable-method = "psci";
> + cpu-idle-states = <&HERA_CPU_SLEEP>;
> + capacity-dmips-mhz = <1024>;
> + dynamic-power-coefficient = <650>;
> + };
> +
> + idle-states {
> + entry-method = "psci";
> +
> + ANANKE_CPU_SLEEP: cpu-ananke-sleep {
> + idle-state-name = "c2";
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x0010000>;
> + entry-latency-us = <70>;
> + exit-latency-us = <160>;
> + min-residency-us = <2000>;
> + status = "okay";
Drop status. Okay is by default.
> + };
> +
> + ENYO_CPU_SLEEP: cpu-enyo-sleep {
> + idle-state-name = "c2";
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x0010000>;
> + entry-latency-us = <150>;
> + exit-latency-us = <190>;
> + min-residency-us = <2500>;
> + status = "okay";
Drop status. Okay is by default.
> + };
> +
> + HERA_CPU_SLEEP: cpu-hera-sleep {
> + idle-state-name = "c2";
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x0010000>;
> + entry-latency-us = <235>;
> + exit-latency-us = <220>;
> + min-residency-us = <3500>;
> + status = "okay";
Drop status. Okay is by default.
> + };
> + };
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> +
> + reserved_memory: reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <1>;
> + ranges;
> +
> + tpu_fw_reserved: tpu_fw@93000000 {
No underscores in node names. Use hyphens.
> + reg = <0x0 0x93000000 0x1000000>;
> + no-map;
> + };
> +
> + gsa_reserved_protected: gsa@90200000 {
> + reg = <0x0 0x90200000 0x400000>;
> + no-map;
> + };
> +
> + aoc_reserve: aoc@94000000 {
> + reg = <0x0 0x94000000 0x03000000>;
> + no-map;
> + };
> +
> + abl_reserved: abl@f8800000 {
> + reg = <0x0 0xf8800000 0x02000000>;
> + no-map;
> + };
> +
> + dss_log_reserved: dss_log_reserved@fd3f0000 {
> + reg = <0 0xfd3f0000 0x0000e000>;
> + no-map;
> + };
> +
> + debug_kinfo_reserved: debug_kinfo_reserved@fd3fe000 {
> + reg = <0 0xfd3fe000 0x00001000>;
> + no-map;
> + };
> +
> + bldr_log_reserved: bldr_log_reserved@fd800000 {
> + reg = <0 0xfd800000 0x00100000>;
> + no-map;
> + };
> +
> + bldr_log_hist_reserved: bldr_log_hist_reserved@fd900000 {
> + reg = <0 0xfd900000 0x00002000>;
> + no-map;
> + };
> + };
> +
> + /* bootloader requires ect node */
> + ect {
> + parameter_address = <0x90000000>;
> + parameter_size = <0x53000>;
> + };
> +
> + chosen {
Please order the nodes by name.
> + bootargs = "earlycon=exynos4210,mmio32,0x10A00000 clk_ignore_unused";
None of these bootargs are suitable for wide, mainline use. Please drop.
> + };
> +
> + gic: interrupt-controller@10400000 {
This cannot be outside of SoC.
> + compatible = "arm,gic-v3";
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + reg = <0x0 0x10400000 0x10000>, /* GICD */
> + <0x0 0x10440000 0x100000>; /* GICR * 8 */
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
> + clock-frequency = <24576000>;
> + };
> +
> + ext_24_5m: ext_24_5m {
clock-1
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <24576000>;
> + clock-output-names = "oscclk";
> + };
> +
> + ext_200m: ext_200m {
clock-2
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <200000000>;
> + clock-output-names = "ext-200m";
> + };
> +
> + /* GPIO_ALIVE */
> + pinctrl_0: pinctrl@174d0000 {
> + compatible = "google,gs101-pinctrl";
> + reg = <0x00000000 0x174d0000 0x00001000>;
0x0
Please open Tesla FSD or Exynos850 for examples.
Also, this cannot be outside of SoC. There is no way this passes
dtbs_check W=1.
Nodes in MMIO-bus should be ordered by unit address.
> + interrupts = <GIC_SPI IRQ_ALIVE_EINT0 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT1 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT2 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT3 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT4 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT5 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT6 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT7 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT8 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT9 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT10 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT11 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT12 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT13 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT14 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT15 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT16 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT17 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT18 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT19 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT20 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT21 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT22 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT23 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT24 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT25 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT26 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT27 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT28 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT29 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT30 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT31 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT32 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT33 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT34 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT35 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT36 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT37 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT38 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT39 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT40 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT41 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT42 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT43 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT44 IRQ_TYPE_LEVEL_HIGH>;
> +
> + wakeup-interrupt-controller {
> + compatible = "google,gs101-wakeup-eint";
> + };
> + };
> +
> + /* GPIO_FAR_ALIVE */
> + pinctrl_1: pinctrl@174e0000 {
> + compatible = "google,gs101-pinctrl";
> + reg = <0x00000000 0x174e0000 0x00001000>;
> + interrupts = <GIC_SPI IRQ_ALIVE_EINT45 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT46 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT47 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT48 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT49 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT50 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT51 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT52 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT53 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT54 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT55 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT56 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT57 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT58 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT59 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT60 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT61 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT62 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT63 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT64 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT65 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT66 IRQ_TYPE_LEVEL_HIGH>;
> +
> + wakeup-interrupt-controller {
> + compatible = "google,gs101-wakeup-eint";
> + };
> + };
> +
> + /* GPIO_GSACORE */
> + pinctrl_2: pinctrl@17a80000 {
> + compatible = "google,gs101-pinctrl";
> + reg = <0x00000000 0x17a80000 0x00001000>;
> + };
> + /* GPIO_GSACTRL */
> + pinctrl_3: pinctrl@17940000 {
> + compatible = "google,gs101-pinctrl";
> + reg = <0x00000000 0x17940000 0x00001000>;
> + };
> + /* GPIO_PERIC0 */
> + pinctrl_4: pinctrl@10840000 {
> + compatible = "google,gs101-pinctrl";
> + reg = <0x00000000 0x10840000 0x00001000>;
> + interrupts = <GIC_SPI IRQ_GPIO_PERIC0_PERIC0 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + /* GPIO_PERIC1 */
> + pinctrl_5: pinctrl@10c40000 {
> + compatible = "google,gs101-pinctrl";
> + reg = <0x00000000 0x10C40000 0x00001000>;
> + interrupts = <GIC_SPI IRQ_GPIO_PERIC1_PERIC1 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + /* GPIO_HSI1 */
> + pinctrl_6: pinctrl@11840000 {
> + compatible = "google,gs101-pinctrl";
> + reg = <0x00000000 0x11840000 0x00001000>;
> + interrupts = <GIC_SPI IRQ_GPIO_HSI1_HSI1 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + /* GPIO_HSI2 */
> + pinctrl_7: pinctrl@14440000 {
> + compatible = "google,gs101-pinctrl";
> + reg = <0x00000000 0x14440000 0x00001000>;
> + interrupts = <GIC_SPI IRQ_GPIO_HSI2_HSI2 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + arm-pmu {
> + compatible = "arm,armv8-pmuv3";
> + interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
> + };
> +
> + sysreg_apm: syscon@174204e0 {
> + compatible = "google,gs101-apm-sysreg",
> + "google,gs101-sysreg", "syscon";
> + reg = <0x0 0x174204e0 0x1000>;
> + };
> +
> + sysreg_peric0: syscon@10821000 {
> + compatible = "google,gs101-peric0-sysreg",
> + "google,gs101-sysreg", "syscon";
> + reg = <0x0 0x10821000 0x40000>;
> + };
> +
> + sysreg_peric1: syscon@10c21000 {
> + compatible = "google,gs101-peric1-sysreg",
> + "google,gs101-sysreg", "syscon";
> + reg = <0x0 0x10C21000 0x40000>;
> + };
> +
> + /* TODO replace with CCF clock */
> + dummy_clk: oscillator {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <12345>;
One space before =
> + clock-output-names = "pclk";
> + };
> +
> + serial_0: serial@10a00000 {
> + compatible = "samsung,exynos850-uart";
You need also specific compatible for GS. Fallback can stay.
> + reg = <0x0 0x10a00000 0xc0>;
> + reg-io-width = <4>;
> + samsung,uart-fifosize = <256>;
> + interrupts = <GIC_SPI IRQ_USI0_UART_PERIC0 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&dummy_clk 0>, <&dummy_clk 0>;
> + clock-names = "uart", "clk_uart_baud0";
> + status = "okay";
Drop, it's default.
> + };
> +
> + pmu_system_controller: system-controller@17460000 {
> + compatible = "google,gs101-pmu", "syscon";
> + reg = <0x0 0x17460000 0x10000>;
> + };
> +
> + watchdog_cl0: watchdog@10060000 {
> + compatible = "google,gs101-wdt";
> + reg = <0x0 0x10060000 0x100>;
> + interrupts = <GIC_SPI IRQ_WDT_CLUSTER0_MISC IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER0>, <&ext_24_5m>;
> + clock-names = "watchdog", "watchdog_src";
> + timeout-sec = <30>;
This is rather property of the board.
> + samsung,syscon-phandle = <&pmu_system_controller>;
> + samsung,cluster-index = <0>;
> + };
> +
> + watchdog_cl1: watchdog@10070000 {
> + compatible = "google,gs101-wdt";
> + reg = <0x0 0x10070000 0x100>;
> + interrupts = <GIC_SPI IRQ_WDT_CLUSTER1_MISC IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER1>, <&ext_24_5m>;
> + clock-names = "watchdog", "watchdog_src";
> + timeout-sec = <30>;
> + samsung,syscon-phandle = <&pmu_system_controller>;
> + samsung,cluster-index = <1>;
> + status = "disabled";
> + };
> +
> + cmu_top: clock-controller@1e080000 {
> + compatible = "google,gs101-cmu-top";
> + reg = <0x0 0x1e080000 0x8000>;
> + #clock-cells = <1>;
> +
> + clocks = <&ext_24_5m>;
> + clock-names = "oscclk";
> + };
> +
> + cmu_apm: clock-controller@17400000 {
> + compatible = "google,gs101-cmu-apm";
> + reg = <0x0 0x17400000 0x8000>;
> + #clock-cells = <1>;
> +
> + clocks = <&ext_24_5m>;
> + clock-names = "oscclk";
> + };
> +
> + cmu_misc: clock-controller@10010000 {
> + compatible = "google,gs101-cmu-misc";
> + reg = <0x0 0x10010000 0x8000>;
> + #clock-cells = <1>;
> +
> + clocks = <&ext_24_5m>, <&cmu_top CLK_DOUT_MISC_BUS>;
> + clock-names = "oscclk", "dout_cmu_misc_bus";
> + };
> +
> + dsu-pmu-0 {
> + compatible = "arm,dsu-pmu";
> + interrupts = <GIC_SPI IRQ_CPUCL0_CLUSTERPMUIRQ_CPUCL0 IRQ_TYPE_LEVEL_HIGH>;
> + cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
> + };
> +
> + gpio_keys: gpio_keys {
> + compatible = "gpio-keys";
That's not a property of the SoC.
> + };
> +
Stray blank line.
> +};
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 150+ messages in thread* Re: [PATCH 18/21] arm64: dts: google: Add initial Google gs101 SoC support
@ 2023-10-05 16:21 ` Krzysztof Kozlowski
0 siblings, 0 replies; 150+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-05 16:21 UTC (permalink / raw)
To: Peter Griffin, robh+dt, krzysztof.kozlowski+dt, mturquette,
conor+dt, sboyd, tomasz.figa, s.nawrocki, linus.walleij, wim,
linux, catalin.marinas, will, arnd, olof, cw00.choi
Cc: tudor.ambarus, andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog
On 05/10/2023 17:56, Peter Griffin wrote:
> Google gs101 SoC is ARMv8 mobile SoC found in the Pixel 6,
> (oriole) Pixel 6a (bluejay) and Pixel 6 pro (raven) mobile
> phones. It features:
> * 4xA55 little cluster
> * 2xA76 Mid cluster
> * 2xX1 Big cluster
>
> This commit adds the basic device tree for gs101 (SoC) and oriole
> (pixel 6). Further platform support will be added over time.
>
> It has been tested with a minimal busybox initramfs and boots to
> a shell.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> arch/arm64/Kconfig.platforms | 6 +
> arch/arm64/boot/dts/Makefile | 1 +
> arch/arm64/boot/dts/google/Makefile | 6 +
> arch/arm64/boot/dts/google/gs101-oriole.dts | 68 +
> arch/arm64/boot/dts/google/gs101-pinctrl.dtsi | 1134 +++++++++++++++++
> arch/arm64/boot/dts/google/gs101-pinctrl.h | 17 +
> arch/arm64/boot/dts/google/gs101.dtsi | 501 ++++++++
Please split adding DTSI from adding DTS into two patches.
> 7 files changed, 1733 insertions(+)
> create mode 100644 arch/arm64/boot/dts/google/Makefile
> create mode 100644 arch/arm64/boot/dts/google/gs101-oriole.dts
> create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.dtsi
> create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.h
> create mode 100644 arch/arm64/boot/dts/google/gs101.dtsi
>
> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
> index 6069120199bb..a5ed1b719488 100644
> --- a/arch/arm64/Kconfig.platforms
> +++ b/arch/arm64/Kconfig.platforms
> @@ -107,6 +107,12 @@ config ARCH_EXYNOS
> help
> This enables support for ARMv8 based Samsung Exynos SoC family.
>
> +config ARCH_GOOGLE_TENSOR
> + bool "Google Tensor SoC fmaily"
> + depends on ARCH_EXYNOS
> + help
> + Support for ARMv8 based Google Tensor platforms.
> +
> config ARCH_SPARX5
> bool "Microchip Sparx5 SoC family"
> select PINCTRL
> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
> index 30dd6347a929..a4ee7b628114 100644
> --- a/arch/arm64/boot/dts/Makefile
> +++ b/arch/arm64/boot/dts/Makefile
> @@ -13,6 +13,7 @@ subdir-y += broadcom
> subdir-y += cavium
> subdir-y += exynos
> subdir-y += freescale
> +subdir-y += google
> subdir-y += hisilicon
> subdir-y += intel
> subdir-y += lg
> diff --git a/arch/arm64/boot/dts/google/Makefile b/arch/arm64/boot/dts/google/Makefile
> new file mode 100644
> index 000000000000..6d2026a767d4
> --- /dev/null
> +++ b/arch/arm64/boot/dts/google/Makefile
> @@ -0,0 +1,6 @@
> +# SPDX-License-Identifier: GPL-2.0
> +
> +dtb-$(CONFIG_ARCH_GOOGLE_TENSOR) += \
> + gs101-oriole.dtb \
> +
> +
Too many blank lines
> diff --git a/arch/arm64/boot/dts/google/gs101-oriole.dts b/arch/arm64/boot/dts/google/gs101-oriole.dts
> new file mode 100644
> index 000000000000..e531a39a76a4
> --- /dev/null
> +++ b/arch/arm64/boot/dts/google/gs101-oriole.dts
> @@ -0,0 +1,68 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Oriole DVT Device Tree
> + *
> + * Copyright 2021-2023 Google,LLC
> + */
> +
> +/dts-v1/;
> +/plugin/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include "gs101-pinctrl.h"
> +#include "gs101.dtsi"
> +
> +/ {
> + model = "Oriole DVT";
> + compatible = "google,gs101-oriole", "google,gs101";
> +};
> +
> +&pinctrl_1 {
> + key_voldown: key-voldown-pins {
> + samsung,pins = "gpa7-3";
> + samsung,pin-function = <0xf>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> +
> + key_volup: key-volup-pins {
> + samsung,pins = "gpa8-1";
> + samsung,pin-function = <0xf>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> +};
> +
> +&pinctrl_0 {
> + key_power: key-power-pins {
> + samsung,pins = "gpa10-1";
> + samsung,pin-function = <0xf>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> +};
> +
> +&gpio_keys {
SoC does not have gpio-keys. That's entirely a property of the board.
> + status = "okay";
Drop
> + pinctrl-names = "default";
> + pinctrl-0 = <&key_voldown &key_volup &key_power>;
Blank line
> + button-vol-down {
> + label = "KEY_VOLUMEDOWN";
> + linux,code = <114>;
> + gpios = <&gpa7 3 0xf>;
> + wakeup-source;
> + };
Blank line
> + button-vol-up {
> + label = "KEY_VOLUMEUP";
> + linux,code = <115>;
> + gpios = <&gpa8 1 0xf>;
> + wakeup-source;
> + };
Blank line
> + button-power {
> + label = "KEY_POWER";
> + linux,code = <116>;
> + gpios = <&gpa10 1 0xf>;
> + wakeup-source;
> + };
> +};
> diff --git a/arch/arm64/boot/dts/google/gs101-pinctrl.dtsi b/arch/arm64/boot/dts/google/gs101-pinctrl.dtsi
> new file mode 100644
> index 000000000000..24825205ede8
> --- /dev/null
> +++ b/arch/arm64/boot/dts/google/gs101-pinctrl.dtsi
> @@ -0,0 +1,1134 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * GS101 SoC pin-mux and pin-config device tree source
> + *
> + * Copyright 2019-2023 Google LLC
> + *
> + */
> +
> +#include <dt-bindings/interrupt-controller/gs101.h>
> +#include <arm64/exynos/exynos-pinctrl.h>
> +#include "gs101-pinctrl.h"
> +
> +/ {
> + /* GPIO_ALIVE */
> + pinctrl@174d0000 {
> + gpa0: gpa0-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI IRQ_ALIVE_EINT0 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT1 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT2 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT3 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT4 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT5 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT6 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT7 ITLH>;
> + };
Blank line
> + gpa1: gpa1-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI IRQ_ALIVE_EINT8 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT9 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT10 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT11 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT12 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT13 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT14 ITLH>;
> + };
> + gpa2: gpa2-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI IRQ_ALIVE_EINT15 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT16 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT17 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT18 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT19 ITLH>;
> + };
> + gpa3: gpa3-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI IRQ_ALIVE_EINT20 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT21 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT22 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT23 ITLH>;
> + };
> + gpa4: gpa4-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI IRQ_ALIVE_EINT24 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT25 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT26 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT27 ITLH>;
> + };
> + gpa5: gpa5-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <GIC_SPI IRQ_ALIVE_EINT28 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT29 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT30 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT31 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT32 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT33 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT34 ITLH>;
> + };
> + gpa9: gpa9-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <GIC_SPI IRQ_ALIVE_EINT35 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT36 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT37 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT38 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT39 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT40 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT41 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT42 ITLH>;
> + };
> + gpa10: gpa10-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <GIC_SPI IRQ_ALIVE_EINT43 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT44 ITLH>;
> + };
> +
> + uart15_bus: uart15-bus-pins {
> + samsung,pins = "gpa2-3", "gpa2-4";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + };
> +
> + uart16_bus: uart16-bus-pins {
> + samsung,pins = "gpa3-0", "gpa3-1", "gpa3-2", "gpa3-3";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
You should rather create macros for your SoC... unless you are 100% sure
this matches Exynos arm64 pinctrl.
...
> diff --git a/arch/arm64/boot/dts/google/gs101-pinctrl.h b/arch/arm64/boot/dts/google/gs101-pinctrl.h
> new file mode 100644
> index 000000000000..acc77c684f0d
> --- /dev/null
> +++ b/arch/arm64/boot/dts/google/gs101-pinctrl.h
> @@ -0,0 +1,17 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Pinctrl binding constants for GS101
> + *
> + * Copyright (c) 2020-2023 Google, LLC.
> + */
> +
> +#ifndef __DT_BINDINGS_PINCTRL_GS101_H__
> +#define __DT_BINDINGS_PINCTRL_GS101_H__
> +
> +/* GS101 drive strengths */
> +#define GS101_PIN_DRV_2_5_MA 0
> +#define GS101_PIN_DRV_5_MA 1
> +#define GS101_PIN_DRV_7_5_MA 2
> +#define GS101_PIN_DRV_10_MA 3
> +
> +#endif /* __DT_BINDINGS_PINCTRL_GS101_H__ */
> diff --git a/arch/arm64/boot/dts/google/gs101.dtsi b/arch/arm64/boot/dts/google/gs101.dtsi
> new file mode 100644
> index 000000000000..0bd43745f6fa
> --- /dev/null
> +++ b/arch/arm64/boot/dts/google/gs101.dtsi
> @@ -0,0 +1,501 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * GS101 SoC
> + *
> + * Copyright 2019-2023 Google LLC
> + *
> + */
> +
> +#include <dt-bindings/clock/gs101.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/interrupt-controller/gs101.h>
> +
> +#include "gs101-pinctrl.dtsi"
> +
> +/ {
> + compatible = "google,gs101";
> + interrupt-parent = <&gic>;
> + #address-cells = <2>;
> + #size-cells = <1>;
> +
> + aliases {
> + pinctrl0 = &pinctrl_0;
> + pinctrl1 = &pinctrl_1;
> + pinctrl2 = &pinctrl_2;
> + pinctrl3 = &pinctrl_3;
> + pinctrl4 = &pinctrl_4;
> + pinctrl5 = &pinctrl_5;
> + pinctrl6 = &pinctrl_6;
> + pinctrl7 = &pinctrl_7;
> +
Stray blank line
> + };
> +
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&cpu0>;
> + };
> + core1 {
> + cpu = <&cpu1>;
> + };
> + core2 {
> + cpu = <&cpu2>;
> + };
> + core3 {
> + cpu = <&cpu3>;
> + };
> + };
Blank line
> + cluster1 {
> + core0 {
> + cpu = <&cpu4>;
> + };
> + core1 {
> + cpu = <&cpu5>;
> + };
> + };
Blank line
> + cluster2 {
> + core0 {
> + cpu = <&cpu6>;
> + };
> + core1 {
> + cpu = <&cpu7>;
> + };
> + };
> + };
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0x0 0x0000>;
> + enable-method = "psci";
> + cpu-idle-states = <&ANANKE_CPU_SLEEP>;
> + capacity-dmips-mhz = <250>;
> + dynamic-power-coefficient = <70>;
> + };
Blank line
> + cpu1: cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0x0 0x0100>;
> + enable-method = "psci";
> + cpu-idle-states = <&ANANKE_CPU_SLEEP>;
> + capacity-dmips-mhz = <250>;
> + dynamic-power-coefficient = <70>;
> + };
> + cpu2: cpu@200 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0x0 0x0200>;
> + enable-method = "psci";
> + cpu-idle-states = <&ANANKE_CPU_SLEEP>;
> + capacity-dmips-mhz = <250>;
> + dynamic-power-coefficient = <70>;
> + };
> + cpu3: cpu@300 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0x0 0x0300>;
> + enable-method = "psci";
> + cpu-idle-states = <&ANANKE_CPU_SLEEP>;
> + capacity-dmips-mhz = <250>;
> + dynamic-power-coefficient = <70>;
> + };
> + cpu4: cpu@400 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0x0 0x0400>;
> + enable-method = "psci";
> + cpu-idle-states = <&ENYO_CPU_SLEEP>;
> + capacity-dmips-mhz = <620>;
> + dynamic-power-coefficient = <284>;
> + };
> + cpu5: cpu@500 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0x0 0x0500>;
> + enable-method = "psci";
> + cpu-idle-states = <&ENYO_CPU_SLEEP>;
> + capacity-dmips-mhz = <620>;
> + dynamic-power-coefficient = <284>;
> + };
> + cpu6: cpu@600 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0x0 0x0600>;
> + enable-method = "psci";
> + cpu-idle-states = <&HERA_CPU_SLEEP>;
> + capacity-dmips-mhz = <1024>;
> + dynamic-power-coefficient = <650>;
> + };
> + cpu7: cpu@700 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0x0 0x0700>;
> + enable-method = "psci";
> + cpu-idle-states = <&HERA_CPU_SLEEP>;
> + capacity-dmips-mhz = <1024>;
> + dynamic-power-coefficient = <650>;
> + };
> +
> + idle-states {
> + entry-method = "psci";
> +
> + ANANKE_CPU_SLEEP: cpu-ananke-sleep {
> + idle-state-name = "c2";
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x0010000>;
> + entry-latency-us = <70>;
> + exit-latency-us = <160>;
> + min-residency-us = <2000>;
> + status = "okay";
Drop status. Okay is by default.
> + };
> +
> + ENYO_CPU_SLEEP: cpu-enyo-sleep {
> + idle-state-name = "c2";
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x0010000>;
> + entry-latency-us = <150>;
> + exit-latency-us = <190>;
> + min-residency-us = <2500>;
> + status = "okay";
Drop status. Okay is by default.
> + };
> +
> + HERA_CPU_SLEEP: cpu-hera-sleep {
> + idle-state-name = "c2";
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x0010000>;
> + entry-latency-us = <235>;
> + exit-latency-us = <220>;
> + min-residency-us = <3500>;
> + status = "okay";
Drop status. Okay is by default.
> + };
> + };
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> +
> + reserved_memory: reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <1>;
> + ranges;
> +
> + tpu_fw_reserved: tpu_fw@93000000 {
No underscores in node names. Use hyphens.
> + reg = <0x0 0x93000000 0x1000000>;
> + no-map;
> + };
> +
> + gsa_reserved_protected: gsa@90200000 {
> + reg = <0x0 0x90200000 0x400000>;
> + no-map;
> + };
> +
> + aoc_reserve: aoc@94000000 {
> + reg = <0x0 0x94000000 0x03000000>;
> + no-map;
> + };
> +
> + abl_reserved: abl@f8800000 {
> + reg = <0x0 0xf8800000 0x02000000>;
> + no-map;
> + };
> +
> + dss_log_reserved: dss_log_reserved@fd3f0000 {
> + reg = <0 0xfd3f0000 0x0000e000>;
> + no-map;
> + };
> +
> + debug_kinfo_reserved: debug_kinfo_reserved@fd3fe000 {
> + reg = <0 0xfd3fe000 0x00001000>;
> + no-map;
> + };
> +
> + bldr_log_reserved: bldr_log_reserved@fd800000 {
> + reg = <0 0xfd800000 0x00100000>;
> + no-map;
> + };
> +
> + bldr_log_hist_reserved: bldr_log_hist_reserved@fd900000 {
> + reg = <0 0xfd900000 0x00002000>;
> + no-map;
> + };
> + };
> +
> + /* bootloader requires ect node */
> + ect {
> + parameter_address = <0x90000000>;
> + parameter_size = <0x53000>;
> + };
> +
> + chosen {
Please order the nodes by name.
> + bootargs = "earlycon=exynos4210,mmio32,0x10A00000 clk_ignore_unused";
None of these bootargs are suitable for wide, mainline use. Please drop.
> + };
> +
> + gic: interrupt-controller@10400000 {
This cannot be outside of SoC.
> + compatible = "arm,gic-v3";
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + reg = <0x0 0x10400000 0x10000>, /* GICD */
> + <0x0 0x10440000 0x100000>; /* GICR * 8 */
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
> + clock-frequency = <24576000>;
> + };
> +
> + ext_24_5m: ext_24_5m {
clock-1
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <24576000>;
> + clock-output-names = "oscclk";
> + };
> +
> + ext_200m: ext_200m {
clock-2
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <200000000>;
> + clock-output-names = "ext-200m";
> + };
> +
> + /* GPIO_ALIVE */
> + pinctrl_0: pinctrl@174d0000 {
> + compatible = "google,gs101-pinctrl";
> + reg = <0x00000000 0x174d0000 0x00001000>;
0x0
Please open Tesla FSD or Exynos850 for examples.
Also, this cannot be outside of SoC. There is no way this passes
dtbs_check W=1.
Nodes in MMIO-bus should be ordered by unit address.
> + interrupts = <GIC_SPI IRQ_ALIVE_EINT0 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT1 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT2 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT3 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT4 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT5 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT6 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT7 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT8 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT9 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT10 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT11 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT12 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT13 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT14 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT15 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT16 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT17 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT18 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT19 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT20 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT21 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT22 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT23 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT24 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT25 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT26 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT27 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT28 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT29 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT30 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT31 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT32 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT33 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT34 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT35 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT36 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT37 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT38 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT39 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT40 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT41 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT42 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT43 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT44 IRQ_TYPE_LEVEL_HIGH>;
> +
> + wakeup-interrupt-controller {
> + compatible = "google,gs101-wakeup-eint";
> + };
> + };
> +
> + /* GPIO_FAR_ALIVE */
> + pinctrl_1: pinctrl@174e0000 {
> + compatible = "google,gs101-pinctrl";
> + reg = <0x00000000 0x174e0000 0x00001000>;
> + interrupts = <GIC_SPI IRQ_ALIVE_EINT45 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT46 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT47 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT48 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT49 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT50 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT51 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT52 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT53 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT54 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT55 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT56 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT57 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT58 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT59 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT60 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT61 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT62 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT63 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT64 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT65 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT66 IRQ_TYPE_LEVEL_HIGH>;
> +
> + wakeup-interrupt-controller {
> + compatible = "google,gs101-wakeup-eint";
> + };
> + };
> +
> + /* GPIO_GSACORE */
> + pinctrl_2: pinctrl@17a80000 {
> + compatible = "google,gs101-pinctrl";
> + reg = <0x00000000 0x17a80000 0x00001000>;
> + };
> + /* GPIO_GSACTRL */
> + pinctrl_3: pinctrl@17940000 {
> + compatible = "google,gs101-pinctrl";
> + reg = <0x00000000 0x17940000 0x00001000>;
> + };
> + /* GPIO_PERIC0 */
> + pinctrl_4: pinctrl@10840000 {
> + compatible = "google,gs101-pinctrl";
> + reg = <0x00000000 0x10840000 0x00001000>;
> + interrupts = <GIC_SPI IRQ_GPIO_PERIC0_PERIC0 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + /* GPIO_PERIC1 */
> + pinctrl_5: pinctrl@10c40000 {
> + compatible = "google,gs101-pinctrl";
> + reg = <0x00000000 0x10C40000 0x00001000>;
> + interrupts = <GIC_SPI IRQ_GPIO_PERIC1_PERIC1 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + /* GPIO_HSI1 */
> + pinctrl_6: pinctrl@11840000 {
> + compatible = "google,gs101-pinctrl";
> + reg = <0x00000000 0x11840000 0x00001000>;
> + interrupts = <GIC_SPI IRQ_GPIO_HSI1_HSI1 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + /* GPIO_HSI2 */
> + pinctrl_7: pinctrl@14440000 {
> + compatible = "google,gs101-pinctrl";
> + reg = <0x00000000 0x14440000 0x00001000>;
> + interrupts = <GIC_SPI IRQ_GPIO_HSI2_HSI2 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + arm-pmu {
> + compatible = "arm,armv8-pmuv3";
> + interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
> + };
> +
> + sysreg_apm: syscon@174204e0 {
> + compatible = "google,gs101-apm-sysreg",
> + "google,gs101-sysreg", "syscon";
> + reg = <0x0 0x174204e0 0x1000>;
> + };
> +
> + sysreg_peric0: syscon@10821000 {
> + compatible = "google,gs101-peric0-sysreg",
> + "google,gs101-sysreg", "syscon";
> + reg = <0x0 0x10821000 0x40000>;
> + };
> +
> + sysreg_peric1: syscon@10c21000 {
> + compatible = "google,gs101-peric1-sysreg",
> + "google,gs101-sysreg", "syscon";
> + reg = <0x0 0x10C21000 0x40000>;
> + };
> +
> + /* TODO replace with CCF clock */
> + dummy_clk: oscillator {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <12345>;
One space before =
> + clock-output-names = "pclk";
> + };
> +
> + serial_0: serial@10a00000 {
> + compatible = "samsung,exynos850-uart";
You need also specific compatible for GS. Fallback can stay.
> + reg = <0x0 0x10a00000 0xc0>;
> + reg-io-width = <4>;
> + samsung,uart-fifosize = <256>;
> + interrupts = <GIC_SPI IRQ_USI0_UART_PERIC0 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&dummy_clk 0>, <&dummy_clk 0>;
> + clock-names = "uart", "clk_uart_baud0";
> + status = "okay";
Drop, it's default.
> + };
> +
> + pmu_system_controller: system-controller@17460000 {
> + compatible = "google,gs101-pmu", "syscon";
> + reg = <0x0 0x17460000 0x10000>;
> + };
> +
> + watchdog_cl0: watchdog@10060000 {
> + compatible = "google,gs101-wdt";
> + reg = <0x0 0x10060000 0x100>;
> + interrupts = <GIC_SPI IRQ_WDT_CLUSTER0_MISC IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER0>, <&ext_24_5m>;
> + clock-names = "watchdog", "watchdog_src";
> + timeout-sec = <30>;
This is rather property of the board.
> + samsung,syscon-phandle = <&pmu_system_controller>;
> + samsung,cluster-index = <0>;
> + };
> +
> + watchdog_cl1: watchdog@10070000 {
> + compatible = "google,gs101-wdt";
> + reg = <0x0 0x10070000 0x100>;
> + interrupts = <GIC_SPI IRQ_WDT_CLUSTER1_MISC IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER1>, <&ext_24_5m>;
> + clock-names = "watchdog", "watchdog_src";
> + timeout-sec = <30>;
> + samsung,syscon-phandle = <&pmu_system_controller>;
> + samsung,cluster-index = <1>;
> + status = "disabled";
> + };
> +
> + cmu_top: clock-controller@1e080000 {
> + compatible = "google,gs101-cmu-top";
> + reg = <0x0 0x1e080000 0x8000>;
> + #clock-cells = <1>;
> +
> + clocks = <&ext_24_5m>;
> + clock-names = "oscclk";
> + };
> +
> + cmu_apm: clock-controller@17400000 {
> + compatible = "google,gs101-cmu-apm";
> + reg = <0x0 0x17400000 0x8000>;
> + #clock-cells = <1>;
> +
> + clocks = <&ext_24_5m>;
> + clock-names = "oscclk";
> + };
> +
> + cmu_misc: clock-controller@10010000 {
> + compatible = "google,gs101-cmu-misc";
> + reg = <0x0 0x10010000 0x8000>;
> + #clock-cells = <1>;
> +
> + clocks = <&ext_24_5m>, <&cmu_top CLK_DOUT_MISC_BUS>;
> + clock-names = "oscclk", "dout_cmu_misc_bus";
> + };
> +
> + dsu-pmu-0 {
> + compatible = "arm,dsu-pmu";
> + interrupts = <GIC_SPI IRQ_CPUCL0_CLUSTERPMUIRQ_CPUCL0 IRQ_TYPE_LEVEL_HIGH>;
> + cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
> + };
> +
> + gpio_keys: gpio_keys {
> + compatible = "gpio-keys";
That's not a property of the SoC.
> + };
> +
Stray blank line.
> +};
Best regards,
Krzysztof
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 18/21] arm64: dts: google: Add initial Google gs101 SoC support
2023-10-05 15:56 ` Peter Griffin
@ 2023-10-05 17:59 ` William McVicker
-1 siblings, 0 replies; 150+ messages in thread
From: William McVicker @ 2023-10-05 17:59 UTC (permalink / raw)
To: Peter Griffin
Cc: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi, tudor.ambarus,
andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog, gregkh, kernel-team
On 10/05/2023, Peter Griffin wrote:
> Google gs101 SoC is ARMv8 mobile SoC found in the Pixel 6,
> (oriole) Pixel 6a (bluejay) and Pixel 6 pro (raven) mobile
> phones. It features:
> * 4xA55 little cluster
> * 2xA76 Mid cluster
> * 2xX1 Big cluster
>
> This commit adds the basic device tree for gs101 (SoC) and oriole
> (pixel 6). Further platform support will be added over time.
>
> It has been tested with a minimal busybox initramfs and boots to
> a shell.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> arch/arm64/Kconfig.platforms | 6 +
> arch/arm64/boot/dts/Makefile | 1 +
> arch/arm64/boot/dts/google/Makefile | 6 +
> arch/arm64/boot/dts/google/gs101-oriole.dts | 68 +
> arch/arm64/boot/dts/google/gs101-pinctrl.dtsi | 1134 +++++++++++++++++
> arch/arm64/boot/dts/google/gs101-pinctrl.h | 17 +
> arch/arm64/boot/dts/google/gs101.dtsi | 501 ++++++++
> 7 files changed, 1733 insertions(+)
> create mode 100644 arch/arm64/boot/dts/google/Makefile
> create mode 100644 arch/arm64/boot/dts/google/gs101-oriole.dts
> create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.dtsi
> create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.h
> create mode 100644 arch/arm64/boot/dts/google/gs101.dtsi
>
> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
> index 6069120199bb..a5ed1b719488 100644
> --- a/arch/arm64/Kconfig.platforms
> +++ b/arch/arm64/Kconfig.platforms
> @@ -107,6 +107,12 @@ config ARCH_EXYNOS
> help
> This enables support for ARMv8 based Samsung Exynos SoC family.
>
> +config ARCH_GOOGLE_TENSOR
> + bool "Google Tensor SoC fmaily"
> + depends on ARCH_EXYNOS
> + help
> + Support for ARMv8 based Google Tensor platforms.
I'd like to bring up this thread and discuss the option of not introducing
another ARCH_* config:
https://lore.kernel.org/all/20200306103652.GA3634389@kroah.com/
I especially don't like the "depends on ARCH_EXYNOS" because that forces one to
include all the other Exynos drivers that ARCH_EXYNOS selects that Google
Tensor SoCs don't need. Can we consider using SOC_GOOGLE instead and for all
drivers that actually depend on the SoC hardware, we can just add "depends on
SOC_GOOGLE"?
The idea is that drivers should be tied to hardware -- not a specific vendor.
By making drivers depend on ARCH_*, you are introducing an arbitrary vendor
dependency and not a hardware dependency.
Thanks,
Will
> +
> config ARCH_SPARX5
> bool "Microchip Sparx5 SoC family"
> select PINCTRL
> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
> index 30dd6347a929..a4ee7b628114 100644
> --- a/arch/arm64/boot/dts/Makefile
> +++ b/arch/arm64/boot/dts/Makefile
> @@ -13,6 +13,7 @@ subdir-y += broadcom
> subdir-y += cavium
> subdir-y += exynos
> subdir-y += freescale
> +subdir-y += google
> subdir-y += hisilicon
> subdir-y += intel
> subdir-y += lg
> diff --git a/arch/arm64/boot/dts/google/Makefile b/arch/arm64/boot/dts/google/Makefile
> new file mode 100644
> index 000000000000..6d2026a767d4
> --- /dev/null
> +++ b/arch/arm64/boot/dts/google/Makefile
> @@ -0,0 +1,6 @@
> +# SPDX-License-Identifier: GPL-2.0
> +
> +dtb-$(CONFIG_ARCH_GOOGLE_TENSOR) += \
> + gs101-oriole.dtb \
> +
> +
> diff --git a/arch/arm64/boot/dts/google/gs101-oriole.dts b/arch/arm64/boot/dts/google/gs101-oriole.dts
> new file mode 100644
> index 000000000000..e531a39a76a4
> --- /dev/null
> +++ b/arch/arm64/boot/dts/google/gs101-oriole.dts
> @@ -0,0 +1,68 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Oriole DVT Device Tree
> + *
> + * Copyright 2021-2023 Google,LLC
> + */
> +
> +/dts-v1/;
> +/plugin/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include "gs101-pinctrl.h"
> +#include "gs101.dtsi"
> +
> +/ {
> + model = "Oriole DVT";
> + compatible = "google,gs101-oriole", "google,gs101";
> +};
> +
> +&pinctrl_1 {
> + key_voldown: key-voldown-pins {
> + samsung,pins = "gpa7-3";
> + samsung,pin-function = <0xf>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> +
> + key_volup: key-volup-pins {
> + samsung,pins = "gpa8-1";
> + samsung,pin-function = <0xf>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> +};
> +
> +&pinctrl_0 {
> + key_power: key-power-pins {
> + samsung,pins = "gpa10-1";
> + samsung,pin-function = <0xf>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> +};
> +
> +&gpio_keys {
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&key_voldown &key_volup &key_power>;
> + button-vol-down {
> + label = "KEY_VOLUMEDOWN";
> + linux,code = <114>;
> + gpios = <&gpa7 3 0xf>;
> + wakeup-source;
> + };
> + button-vol-up {
> + label = "KEY_VOLUMEUP";
> + linux,code = <115>;
> + gpios = <&gpa8 1 0xf>;
> + wakeup-source;
> + };
> + button-power {
> + label = "KEY_POWER";
> + linux,code = <116>;
> + gpios = <&gpa10 1 0xf>;
> + wakeup-source;
> + };
> +};
> diff --git a/arch/arm64/boot/dts/google/gs101-pinctrl.dtsi b/arch/arm64/boot/dts/google/gs101-pinctrl.dtsi
> new file mode 100644
> index 000000000000..24825205ede8
> --- /dev/null
> +++ b/arch/arm64/boot/dts/google/gs101-pinctrl.dtsi
> @@ -0,0 +1,1134 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * GS101 SoC pin-mux and pin-config device tree source
> + *
> + * Copyright 2019-2023 Google LLC
> + *
> + */
> +
> +#include <dt-bindings/interrupt-controller/gs101.h>
> +#include <arm64/exynos/exynos-pinctrl.h>
> +#include "gs101-pinctrl.h"
> +
> +/ {
> + /* GPIO_ALIVE */
> + pinctrl@174d0000 {
> + gpa0: gpa0-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI IRQ_ALIVE_EINT0 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT1 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT2 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT3 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT4 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT5 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT6 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT7 ITLH>;
> + };
> + gpa1: gpa1-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI IRQ_ALIVE_EINT8 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT9 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT10 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT11 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT12 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT13 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT14 ITLH>;
> + };
> + gpa2: gpa2-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI IRQ_ALIVE_EINT15 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT16 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT17 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT18 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT19 ITLH>;
> + };
> + gpa3: gpa3-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI IRQ_ALIVE_EINT20 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT21 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT22 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT23 ITLH>;
> + };
> + gpa4: gpa4-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI IRQ_ALIVE_EINT24 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT25 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT26 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT27 ITLH>;
> + };
> + gpa5: gpa5-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <GIC_SPI IRQ_ALIVE_EINT28 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT29 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT30 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT31 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT32 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT33 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT34 ITLH>;
> + };
> + gpa9: gpa9-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <GIC_SPI IRQ_ALIVE_EINT35 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT36 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT37 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT38 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT39 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT40 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT41 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT42 ITLH>;
> + };
> + gpa10: gpa10-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <GIC_SPI IRQ_ALIVE_EINT43 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT44 ITLH>;
> + };
> +
> + uart15_bus: uart15-bus-pins {
> + samsung,pins = "gpa2-3", "gpa2-4";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + };
> +
> + uart16_bus: uart16-bus-pins {
> + samsung,pins = "gpa3-0", "gpa3-1", "gpa3-2", "gpa3-3";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + };
> +
> + uart16_bus_rts: uart1-bus-rts-pins {
> + samsung,pins = "gpa3-2";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-val = <1>;
> + };
> +
> + uart16_bus_tx_dat: uart1-bus-tx-dat-pins {
> + samsung,pins = "gpa3-1";
> + samsung,pin-val = <1>;
> + };
> +
> + uart16_bus_tx_con: uart1-bus-tx-con-pins {
> + samsung,pins = "gpa3-1";
> + samsung,pin-function = <1>;
> + };
> +
> + uart17_bus: uart17-bus-pins {
> + samsung,pins = "gpa4-0", "gpa4-1", "gpa4-2", "gpa4-3";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + };
> +
> + spi15_bus: spi15-bus-pins {
> + samsung,pins = "gpa4-0", "gpa4-1", "gpa4-2";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi15_cs: spi15-cs-pins {
> + samsung,pins = "gpa4-3";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + };
> + /* GPIO_FAR_ALIVE */
> + pinctrl@174e0000 {
> + gpa6: gpa6-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI IRQ_ALIVE_EINT45 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT46 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT47 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT48 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT49 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT50 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT51 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT52 ITLH>;
> + };
> + gpa7: gpa7-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI IRQ_ALIVE_EINT53 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT54 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT55 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT56 ITLH>;
> + };
> + gpa8: gpa8-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI IRQ_ALIVE_EINT57 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT58 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT59 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT60 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT61 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT62 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT63 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT64 ITLH>;
> + };
> + gpa11: gpa11-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI IRQ_ALIVE_EINT65 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT66 ITLH>;
> + };
> +
> + };
> + /* GPIO_GSACORE */
> + pinctrl@17a80000 {
> + gps0: gps0-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gps1: gps1-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gps2: gps2-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + };
> + /* GPIO_GSACTRL */
> + pinctrl@17940000 {
> + gps3: gps3-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + };
> + /* GPIO_HSI1 */
> + pinctrl@11840000 {
> + gph0: gph0-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gph1: gph1-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + pcie0_clkreq: pcie0-clkreq-pins{
> + samsung,pins = "gph0-1";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <GS101_PIN_DRV_10_MA>;
> + samsung,pin-con-pdn = <3>;
> + samsung,pin-pud-pdn = <3>;
> + };
> + pcie0_perst: pcie0-perst-pins {
> + samsung,pins = "gph0-0";
> + samsung,pin-function = <1>;
> + samsung,pin-drv = <GS101_PIN_DRV_10_MA>;
> + samsung,pin-con-pdn = <3>;
> + };
> + };
> + /* GPIO_HSI2 */
> + pinctrl@14440000 {
> + gph2: gph2-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gph3: gph3-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gph4: gph4-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + sd2_clk: sd2-clk-pins {
> + samsung,pins = "gph4-0";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>;
> + };
> +
> + sd2_cmd: sd2-cmd-pins {
> + samsung,pins = "gph4-1";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>;
> + };
> +
> + sd2_bus1: sd2-bus-width1-pins {
> + samsung,pins = "gph4-2";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>;
> + };
> +
> + sd2_bus4: sd2-bus-width4-pins {
> + samsung,pins = "gph4-3", "gph4-4", "gph4-5";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>;
> + };
> +
> + sd2_clk_fast_slew_rate_1x: sd2-clk-fast-slew-rate-1x-pins {
> + samsung,pins = "gph4-0";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> +
> + sd2_clk_fast_slew_rate_2x: sd2-clk-fast-slew-rate-2x-pins {
> + samsung,pins = "gph4-0";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> + };
> +
> + sd2_clk_fast_slew_rate_3x: sd2-clk-fast-slew-rate-3x-pins {
> + samsung,pins = "gph4-0";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>;
> + };
> +
> + sd2_clk_fast_slew_rate_4x: sd2-clk-fast-slew-rate-4x-pins {
> + samsung,pins = "gph4-0";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_10_MA>;
> + };
> + ufs_rst_n: ufs-rst-n-pins {
> + samsung,pins = "gph3-1";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-con-pdn = <3>;
> + samsung,pin-pud-pdn = <0>;
> + };
> +
> + ufs_refclk_out: ufs-refclk-out-pins {
> + samsung,pins = "gph3-0";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-con-pdn = <3>;
> + samsung,pin-pud-pdn = <0>;
> + };
> + pcie1_clkreq: pcie1-clkreq-pins {
> + samsung,pins = "gph2-1";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <GS101_PIN_DRV_10_MA>;
> + samsung,pin-con-pdn = <3>;
> + samsung,pin-pud-pdn = <3>;
> + };
> + pcie1_perst: pcie1-perst-pins {
> + samsung,pins = "gph2-0";
> + samsung,pin-function = <1>;
> + samsung,pin-drv = <GS101_PIN_DRV_10_MA>;
> + samsung,pin-con-pdn = <3>;
> + };
> + };
> + /* GPIO_PERIC0 */
> + pinctrl@10840000 {
> + gpp0: gpp0-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gpp1: gpp1-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gpp2: gpp2-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gpp3: gpp3-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gpp4: gpp4-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gpp5: gpp5-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gpp6: gpp6-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gpp7: gpp7-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gpp8: gpp8-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gpp9: gpp9-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gpp10: gpp10-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gpp11: gpp11-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gpp12: gpp12-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gpp13: gpp13-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gpp14: gpp14-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gpp15: gpp15-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gpp16: gpp16-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gpp17: gpp17-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gpp18: gpp18-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gpp19: gpp19-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + /* USI_PERIC0_UART_DBG */
> + uart0_bus: uart0-bus-pins {
> + samsung,pins = "gpp1-2", "gpp1-3";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + };
> +
> + disp_te_pri_on: disp-te-pri-on-pins {
> + samsung,pins = "gpp0-3";
> + samsung,pin-function = <0xf>;
> + };
> +
> + disp_te_pri_off: disp-te-pri-off-pins {
> + samsung,pins = "gpp0-3";
> + samsung,pin-function = <0>;
> + };
> +
> + disp_te_sec_on: disp-te-sec-on-pins {
> + samsung,pins = "gpp0-4";
> + samsung,pin-function = <0xf>;
> + };
> +
> + disp_te_sec_off: disp-te-sec-off-pins {
> + samsung,pins = "gpp0-4";
> + samsung,pin-function = <0>;
> + };
> +
> + sensor_mclk1_out: sensor-mclk1-out-pins {
> + samsung,pins = "gpp3-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> + samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> + };
> + sensor_mclk1_fn: sensor-mclk1-fn-pins {
> + samsung,pins = "gpp3-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> + };
> + sensor_mclk2_out: sensor-mclk2-out-pins {
> + samsung,pins = "gpp5-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> + samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> + };
> + sensor_mclk2_fn: sensor-mclk2-fn-pins {
> + samsung,pins = "gpp5-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> + };
> + sensor_mclk3_out: sensor-mclk3-out-pins {
> + samsung,pins = "gpp7-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> + samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> + };
> + sensor_mclk3_fn: sensor-mclk3-fn-pins {
> + samsung,pins = "gpp7-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> + };
> + sensor_mclk4_out: sensor-mclk4-out-pins {
> + samsung,pins = "gpp9-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> + samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> + };
> + sensor_mclk4_fn: sensor-mclk4-fn-pins {
> + samsung,pins = "gpp9-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> + };
> + sensor_mclk5_out: sensor-mclk5-out-pins {
> + samsung,pins = "gpp11-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> + samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> + };
> + sensor_mclk5_fn: sensor-mclk5-fn-pins {
> + samsung,pins = "gpp11-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> + };
> + sensor_mclk6_out: sensor-mclk6-out-pins {
> + samsung,pins = "gpp13-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> + samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> + };
> + sensor_mclk6_fn: sensor-mclk6-fn-pins {
> + samsung,pins = "gpp13-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> + };
> + sensor_mclk7_out: sensor-mclk7-out-pins {
> + samsung,pins = "gpp15-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> + samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> + };
> + sensor_mclk7_fn: sensor-mclk7-fn-pins {
> + samsung,pins = "gpp15-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> + };
> + sensor_mclk8_out: sensor-mclk8-out-pins {
> + samsung,pins = "gpp17-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> + samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> + };
> + sensor_mclk8_fn: sensor-mclk8-fn-pins {
> + samsung,pins = "gpp17-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> + };
> + hsi2c14_bus: hsi2c14-bus-pins {
> + samsung,pins = "gpp18-0", "gpp18-1";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + uart14_bus_single: uart14-bus-pins {
> + samsung,pins = "gpp18-0", "gpp18-1",
> + "gpp18-2", "gpp18-3";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + };
> + spi14_bus: spi14-bus-pins {
> + samsung,pins = "gpp18-0", "gpp18-1", "gpp18-2";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi14_cs: spi14-cs-pins {
> + samsung,pins = "gpp18-3";
> + samsung,pin-function = <1>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi14_cs_func: spi14-cs-func-pins {
> + samsung,pins = "gpp18-3";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + hsi2c8_bus: hsi2c8-bus-pins {
> + samsung,pins = "gpp16-0", "gpp16-1";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + samsung,pin-pud-pdn = <EXYNOS_PIN_PDN_OUT0>;
> + };
> + uart8_bus_single: uart8-bus-pins {
> + samsung,pins = "gpp16-0", "gpp16-1", "gpp16-2",
> + "gpp16-3";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + };
> + spi8_bus: spi8-bus-pins {
> + samsung,pins = "gpp16-0", "gpp16-1", "gpp16-2";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi8_cs: spi8-cs-pins {
> + samsung,pins = "gpp16-3";
> + samsung,pin-function = <1>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi8_cs_func: spi8-cs-func-pins {
> + samsung,pins = "gpp16-3";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + hsi2c7_bus: hsi2c7-bus-pins {
> + samsung,pins = "gpp14-0", "gpp14-1";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + uart7_bus_single: uart7-bus-pins {
> + samsung,pins = "gpp14-0", "gpp14-1",
> + "gpp14-2", "gpp14-3";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + };
> + spi7_bus: spi7-bus-pins {
> + samsung,pins = "gpp14-0", "gpp14-1", "gpp14-2";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi7_cs: spi7-cs-pins {
> + samsung,pins = "gpp14-3";
> + samsung,pin-function = <1>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi7_cs_func: spi7-cs-func-pins {
> + samsung,pins = "gpp14-3";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + hsi2c6_bus: hsi2c6-bus-pins {
> + samsung,pins = "gpp12-0", "gpp12-1";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + uart6_bus_single: uart6-bus-pins {
> + samsung,pins = "gpp12-0", "gpp12-1",
> + "gpp12-2", "gpp12-3";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + };
> + spi6_bus: spi6-bus-pins {
> + samsung,pins = "gpp12-0", "gpp12-1", "gpp12-2";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi6_cs: spi6-cs-pins {
> + samsung,pins = "gpp12-3";
> + samsung,pin-function = <1>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi6_cs_func: spi6-cs-func-pins {
> + samsung,pins = "gpp12-3";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + hsi2c5_bus: hsi2c5-bus-pins {
> + samsung,pins = "gpp10-0", "gpp10-1";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + uart5_bus_single: uart5-bus-pins {
> + samsung,pins = "gpp10-0", "gpp10-1",
> + "gpp10-2", "gpp10-3";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + };
> + spi5_bus: spi5-bus-pins {
> + samsung,pins = "gpp10-0", "gpp10-1", "gpp10-2";
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
> + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>;
> + };
> + spi5_cs_func: spi5-cs-func-pins {
> + samsung,pins = "gpp10-3";
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
> + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>;
> + };
> + hsi2c4_bus: hsi2c4-bus-pins {
> + samsung,pins = "gpp8-0", "gpp8-1";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + uart4_bus_single: uart4-bus-pins {
> + samsung,pins = "gpp8-0", "gpp8-1",
> + "gpp8-2", "gpp8-3";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + };
> + spi4_bus: spi4-bus-pins {
> + samsung,pins = "gpp8-0", "gpp8-1", "gpp8-2";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi4_cs: spi4-cs-pins {
> + samsung,pins = "gpp8-3";
> + samsung,pin-function = <1>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi4_cs_func: spi4-cs-func-pins {
> + samsung,pins = "gpp8-3";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + hsi2c3_bus: hsi2c3-bus-pins {
> + samsung,pins = "gpp6-0", "gpp6-1";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + uart3_bus_single: uart3-bus-pins {
> + samsung,pins = "gpp6-0", "gpp6-1",
> + "gpp6-2", "gpp6-3";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + };
> + spi3_bus: spi3-bus-pins {
> + samsung,pins = "gpp6-0", "gpp6-1", "gpp6-2";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi3_cs: spi3-cs-pins {
> + samsung,pins = "gpp6-3";
> + samsung,pin-function = <1>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi3_cs_func: spi3-cs-func-pins {
> + samsung,pins = "gpp6-3";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + hsi2c2_bus: hsi2c2-bus-pins {
> + samsung,pins = "gpp4-0", "gpp4-1";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + uart2_bus_single: uart2-bus-pins {
> + samsung,pins = "gpp4-0", "gpp4-1",
> + "gpp4-2", "gpp4-3";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + };
> + spi2_bus: spi2-bus-pins {
> + samsung,pins = "gpp4-0", "gpp4-1", "gpp4-2";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi2_cs: spi2-cs-pins {
> + samsung,pins = "gpp4-3";
> + samsung,pin-function = <1>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi2_cs_func: spi2-cs-func-pins {
> + samsung,pins = "gpp4-3";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + hsi2c1_bus: hsi2c1-bus-pins {
> + samsung,pins = "gpp2-0", "gpp2-1";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + uart1_bus_single: uart1-bus-pins {
> + samsung,pins = "gpp2-0", "gpp2-1",
> + "gpp2-2", "gpp2-3";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + };
> + spi1_bus: spi1-bus-pins {
> + samsung,pins = "gpp2-0", "gpp2-1", "gpp2-2";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi1_cs: spi1-cs-pins {
> + samsung,pins = "gpp2-3";
> + samsung,pin-function = <1>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi1_cs_func: spi1-cs-func-pins {
> + samsung,pins = "gpp2-3";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + };
> + /* GPIO_PERIC1 */
> + pinctrl@10c40000 {
> + gpp20: gpp20-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gpp21: gpp21-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gpp22: gpp22-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gpp23: gpp23-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gpp24: gpp24-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gpp25: gpp25-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gpp26: gpp26-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gpp27: gpp27-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + hsi2c13_bus: hsi2c13-bus-pins {
> + samsung,pins = "gpp25-0", "gpp25-1";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + uart13_bus_single: uart13-bus-pins {
> + samsung,pins = "gpp25-0", "gpp25-1",
> + "gpp25-2", "gpp25-3";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + };
> + spi13_bus: spi13-bus-pins {
> + samsung,pins = "gpp25-0", "gpp25-1", "gpp25-2";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi13_cs: spi13-cs-pins {
> + samsung,pins = "gpp25-3";
> + samsung,pin-function = <1>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi13_cs_func: spi13-cs-func-pins {
> + samsung,pins = "gpp25-3";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + hsi2c12_bus: hsi2c12-bus-pins {
> + samsung,pins = "gpp23-4", "gpp23-5";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + uart12_bus_single: uart12-bus-pins {
> + samsung,pins = "gpp23-4", "gpp23-5",
> + "gpp23-6", "gpp23-7";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + };
> + spi12_bus: spi12-bus-pins {
> + samsung,pins = "gpp23-4", "gpp23-5", "gpp23-6";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi14_cs2: spi14-cs2-pins {
> + samsung,pins = "gpp23-6";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi12_cs: spi12-cs-pins {
> + samsung,pins = "gpp23-7";
> + samsung,pin-function = <1>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi12_cs_func: spi12-cs-func-pins {
> + samsung,pins = "gpp23-7";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + hsi2c11_bus: hsi2c11-bus-pins {
> + samsung,pins = "gpp23-0", "gpp23-1";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + uart11_bus_single: uart11-bus-pins {
> + samsung,pins = "gpp23-0", "gpp23-1",
> + "gpp23-2", "gpp23-3";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + };
> + spi11_bus: spi11-bus-pins {
> + samsung,pins = "gpp23-0", "gpp23-1", "gpp23-2";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi11_cs: spi11-cs-pins {
> + samsung,pins = "gpp23-3";
> + samsung,pin-function = <1>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi11_cs_func: spi11-cs-func-pins {
> + samsung,pins = "gpp23-3";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + hsi2c10_bus: hsi2c10-bus-pins {
> + samsung,pins = "gpp21-0", "gpp21-1";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + uart10_bus_single: uart10-bus-pins {
> + samsung,pins = "gpp21-0", "gpp21-1",
> + "gpp21-2", "gpp21-3";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + };
> + spi10_bus: spi10-bus-pins {
> + samsung,pins = "gpp21-0", "gpp21-1", "gpp21-2";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi10_cs: spi10-cs-pins {
> + samsung,pins = "gpp21-3";
> + samsung,pin-function = <1>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi10_cs_func: spi10-cs-func-pins {
> + samsung,pins = "gpp21-3";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + hsi2c9_bus: hsi2c9-bus-pins {
> + samsung,pins = "gpp20-4", "gpp20-5";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + uart9_bus_single: uart9-bus-pins {
> + samsung,pins = "gpp20-4", "gpp20-5",
> + "gpp20-6", "gpp20-7";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + };
> + spi9_bus: spi9-bus-pins {
> + samsung,pins = "gpp20-4", "gpp20-5", "gpp20-6";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi9_cs: spi9-cs-pins {
> + samsung,pins = "gpp20-7";
> + samsung,pin-function = <1>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi9_cs_func: spi9-cs-func-pins {
> + samsung,pins = "gpp20-7";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + hsi2c0_bus: hsi2c0-bus-pins {
> + samsung,pins = "gpp20-0", "gpp20-1";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + uart0_bus_single: uart0-bus-pins {
> + samsung,pins = "gpp20-0", "gpp20-1",
> + "gpp20-2", "gpp20-3";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + };
> + spi0_bus: spi0-bus-pins {
> + samsung,pins = "gpp20-0", "gpp20-1", "gpp20-2";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi0_cs: spi0-cs-pins {
> + samsung,pins = "gpp20-3";
> + samsung,pin-function = <1>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi0_cs_func: spi0-cs-func-pins {
> + samsung,pins = "gpp20-3";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + };
> +};
> diff --git a/arch/arm64/boot/dts/google/gs101-pinctrl.h b/arch/arm64/boot/dts/google/gs101-pinctrl.h
> new file mode 100644
> index 000000000000..acc77c684f0d
> --- /dev/null
> +++ b/arch/arm64/boot/dts/google/gs101-pinctrl.h
> @@ -0,0 +1,17 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Pinctrl binding constants for GS101
> + *
> + * Copyright (c) 2020-2023 Google, LLC.
> + */
> +
> +#ifndef __DT_BINDINGS_PINCTRL_GS101_H__
> +#define __DT_BINDINGS_PINCTRL_GS101_H__
> +
> +/* GS101 drive strengths */
> +#define GS101_PIN_DRV_2_5_MA 0
> +#define GS101_PIN_DRV_5_MA 1
> +#define GS101_PIN_DRV_7_5_MA 2
> +#define GS101_PIN_DRV_10_MA 3
> +
> +#endif /* __DT_BINDINGS_PINCTRL_GS101_H__ */
> diff --git a/arch/arm64/boot/dts/google/gs101.dtsi b/arch/arm64/boot/dts/google/gs101.dtsi
> new file mode 100644
> index 000000000000..0bd43745f6fa
> --- /dev/null
> +++ b/arch/arm64/boot/dts/google/gs101.dtsi
> @@ -0,0 +1,501 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * GS101 SoC
> + *
> + * Copyright 2019-2023 Google LLC
> + *
> + */
> +
> +#include <dt-bindings/clock/gs101.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/interrupt-controller/gs101.h>
> +
> +#include "gs101-pinctrl.dtsi"
> +
> +/ {
> + compatible = "google,gs101";
> + interrupt-parent = <&gic>;
> + #address-cells = <2>;
> + #size-cells = <1>;
> +
> + aliases {
> + pinctrl0 = &pinctrl_0;
> + pinctrl1 = &pinctrl_1;
> + pinctrl2 = &pinctrl_2;
> + pinctrl3 = &pinctrl_3;
> + pinctrl4 = &pinctrl_4;
> + pinctrl5 = &pinctrl_5;
> + pinctrl6 = &pinctrl_6;
> + pinctrl7 = &pinctrl_7;
> +
> + };
> +
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&cpu0>;
> + };
> + core1 {
> + cpu = <&cpu1>;
> + };
> + core2 {
> + cpu = <&cpu2>;
> + };
> + core3 {
> + cpu = <&cpu3>;
> + };
> + };
> + cluster1 {
> + core0 {
> + cpu = <&cpu4>;
> + };
> + core1 {
> + cpu = <&cpu5>;
> + };
> + };
> + cluster2 {
> + core0 {
> + cpu = <&cpu6>;
> + };
> + core1 {
> + cpu = <&cpu7>;
> + };
> + };
> + };
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0x0 0x0000>;
> + enable-method = "psci";
> + cpu-idle-states = <&ANANKE_CPU_SLEEP>;
> + capacity-dmips-mhz = <250>;
> + dynamic-power-coefficient = <70>;
> + };
> + cpu1: cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0x0 0x0100>;
> + enable-method = "psci";
> + cpu-idle-states = <&ANANKE_CPU_SLEEP>;
> + capacity-dmips-mhz = <250>;
> + dynamic-power-coefficient = <70>;
> + };
> + cpu2: cpu@200 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0x0 0x0200>;
> + enable-method = "psci";
> + cpu-idle-states = <&ANANKE_CPU_SLEEP>;
> + capacity-dmips-mhz = <250>;
> + dynamic-power-coefficient = <70>;
> + };
> + cpu3: cpu@300 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0x0 0x0300>;
> + enable-method = "psci";
> + cpu-idle-states = <&ANANKE_CPU_SLEEP>;
> + capacity-dmips-mhz = <250>;
> + dynamic-power-coefficient = <70>;
> + };
> + cpu4: cpu@400 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0x0 0x0400>;
> + enable-method = "psci";
> + cpu-idle-states = <&ENYO_CPU_SLEEP>;
> + capacity-dmips-mhz = <620>;
> + dynamic-power-coefficient = <284>;
> + };
> + cpu5: cpu@500 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0x0 0x0500>;
> + enable-method = "psci";
> + cpu-idle-states = <&ENYO_CPU_SLEEP>;
> + capacity-dmips-mhz = <620>;
> + dynamic-power-coefficient = <284>;
> + };
> + cpu6: cpu@600 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0x0 0x0600>;
> + enable-method = "psci";
> + cpu-idle-states = <&HERA_CPU_SLEEP>;
> + capacity-dmips-mhz = <1024>;
> + dynamic-power-coefficient = <650>;
> + };
> + cpu7: cpu@700 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0x0 0x0700>;
> + enable-method = "psci";
> + cpu-idle-states = <&HERA_CPU_SLEEP>;
> + capacity-dmips-mhz = <1024>;
> + dynamic-power-coefficient = <650>;
> + };
> +
> + idle-states {
> + entry-method = "psci";
> +
> + ANANKE_CPU_SLEEP: cpu-ananke-sleep {
> + idle-state-name = "c2";
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x0010000>;
> + entry-latency-us = <70>;
> + exit-latency-us = <160>;
> + min-residency-us = <2000>;
> + status = "okay";
> + };
> +
> + ENYO_CPU_SLEEP: cpu-enyo-sleep {
> + idle-state-name = "c2";
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x0010000>;
> + entry-latency-us = <150>;
> + exit-latency-us = <190>;
> + min-residency-us = <2500>;
> + status = "okay";
> + };
> +
> + HERA_CPU_SLEEP: cpu-hera-sleep {
> + idle-state-name = "c2";
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x0010000>;
> + entry-latency-us = <235>;
> + exit-latency-us = <220>;
> + min-residency-us = <3500>;
> + status = "okay";
> + };
> + };
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> +
> + reserved_memory: reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <1>;
> + ranges;
> +
> + tpu_fw_reserved: tpu_fw@93000000 {
> + reg = <0x0 0x93000000 0x1000000>;
> + no-map;
> + };
> +
> + gsa_reserved_protected: gsa@90200000 {
> + reg = <0x0 0x90200000 0x400000>;
> + no-map;
> + };
> +
> + aoc_reserve: aoc@94000000 {
> + reg = <0x0 0x94000000 0x03000000>;
> + no-map;
> + };
> +
> + abl_reserved: abl@f8800000 {
> + reg = <0x0 0xf8800000 0x02000000>;
> + no-map;
> + };
> +
> + dss_log_reserved: dss_log_reserved@fd3f0000 {
> + reg = <0 0xfd3f0000 0x0000e000>;
> + no-map;
> + };
> +
> + debug_kinfo_reserved: debug_kinfo_reserved@fd3fe000 {
> + reg = <0 0xfd3fe000 0x00001000>;
> + no-map;
> + };
> +
> + bldr_log_reserved: bldr_log_reserved@fd800000 {
> + reg = <0 0xfd800000 0x00100000>;
> + no-map;
> + };
> +
> + bldr_log_hist_reserved: bldr_log_hist_reserved@fd900000 {
> + reg = <0 0xfd900000 0x00002000>;
> + no-map;
> + };
> + };
> +
> + /* bootloader requires ect node */
> + ect {
> + parameter_address = <0x90000000>;
> + parameter_size = <0x53000>;
> + };
> +
> + chosen {
> + bootargs = "earlycon=exynos4210,mmio32,0x10A00000 clk_ignore_unused";
> + };
> +
> + gic: interrupt-controller@10400000 {
> + compatible = "arm,gic-v3";
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + reg = <0x0 0x10400000 0x10000>, /* GICD */
> + <0x0 0x10440000 0x100000>; /* GICR * 8 */
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
> + clock-frequency = <24576000>;
> + };
> +
> + ext_24_5m: ext_24_5m {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <24576000>;
> + clock-output-names = "oscclk";
> + };
> +
> + ext_200m: ext_200m {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <200000000>;
> + clock-output-names = "ext-200m";
> + };
> +
> + /* GPIO_ALIVE */
> + pinctrl_0: pinctrl@174d0000 {
> + compatible = "google,gs101-pinctrl";
> + reg = <0x00000000 0x174d0000 0x00001000>;
> + interrupts = <GIC_SPI IRQ_ALIVE_EINT0 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT1 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT2 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT3 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT4 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT5 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT6 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT7 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT8 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT9 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT10 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT11 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT12 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT13 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT14 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT15 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT16 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT17 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT18 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT19 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT20 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT21 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT22 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT23 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT24 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT25 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT26 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT27 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT28 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT29 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT30 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT31 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT32 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT33 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT34 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT35 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT36 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT37 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT38 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT39 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT40 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT41 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT42 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT43 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT44 IRQ_TYPE_LEVEL_HIGH>;
> +
> + wakeup-interrupt-controller {
> + compatible = "google,gs101-wakeup-eint";
> + };
> + };
> +
> + /* GPIO_FAR_ALIVE */
> + pinctrl_1: pinctrl@174e0000 {
> + compatible = "google,gs101-pinctrl";
> + reg = <0x00000000 0x174e0000 0x00001000>;
> + interrupts = <GIC_SPI IRQ_ALIVE_EINT45 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT46 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT47 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT48 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT49 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT50 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT51 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT52 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT53 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT54 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT55 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT56 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT57 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT58 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT59 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT60 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT61 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT62 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT63 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT64 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT65 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT66 IRQ_TYPE_LEVEL_HIGH>;
> +
> + wakeup-interrupt-controller {
> + compatible = "google,gs101-wakeup-eint";
> + };
> + };
> +
> + /* GPIO_GSACORE */
> + pinctrl_2: pinctrl@17a80000 {
> + compatible = "google,gs101-pinctrl";
> + reg = <0x00000000 0x17a80000 0x00001000>;
> + };
> + /* GPIO_GSACTRL */
> + pinctrl_3: pinctrl@17940000 {
> + compatible = "google,gs101-pinctrl";
> + reg = <0x00000000 0x17940000 0x00001000>;
> + };
> + /* GPIO_PERIC0 */
> + pinctrl_4: pinctrl@10840000 {
> + compatible = "google,gs101-pinctrl";
> + reg = <0x00000000 0x10840000 0x00001000>;
> + interrupts = <GIC_SPI IRQ_GPIO_PERIC0_PERIC0 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + /* GPIO_PERIC1 */
> + pinctrl_5: pinctrl@10c40000 {
> + compatible = "google,gs101-pinctrl";
> + reg = <0x00000000 0x10C40000 0x00001000>;
> + interrupts = <GIC_SPI IRQ_GPIO_PERIC1_PERIC1 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + /* GPIO_HSI1 */
> + pinctrl_6: pinctrl@11840000 {
> + compatible = "google,gs101-pinctrl";
> + reg = <0x00000000 0x11840000 0x00001000>;
> + interrupts = <GIC_SPI IRQ_GPIO_HSI1_HSI1 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + /* GPIO_HSI2 */
> + pinctrl_7: pinctrl@14440000 {
> + compatible = "google,gs101-pinctrl";
> + reg = <0x00000000 0x14440000 0x00001000>;
> + interrupts = <GIC_SPI IRQ_GPIO_HSI2_HSI2 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + arm-pmu {
> + compatible = "arm,armv8-pmuv3";
> + interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
> + };
> +
> + sysreg_apm: syscon@174204e0 {
> + compatible = "google,gs101-apm-sysreg",
> + "google,gs101-sysreg", "syscon";
> + reg = <0x0 0x174204e0 0x1000>;
> + };
> +
> + sysreg_peric0: syscon@10821000 {
> + compatible = "google,gs101-peric0-sysreg",
> + "google,gs101-sysreg", "syscon";
> + reg = <0x0 0x10821000 0x40000>;
> + };
> +
> + sysreg_peric1: syscon@10c21000 {
> + compatible = "google,gs101-peric1-sysreg",
> + "google,gs101-sysreg", "syscon";
> + reg = <0x0 0x10C21000 0x40000>;
> + };
> +
> + /* TODO replace with CCF clock */
> + dummy_clk: oscillator {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <12345>;
> + clock-output-names = "pclk";
> + };
> +
> + serial_0: serial@10a00000 {
> + compatible = "samsung,exynos850-uart";
> + reg = <0x0 0x10a00000 0xc0>;
> + reg-io-width = <4>;
> + samsung,uart-fifosize = <256>;
> + interrupts = <GIC_SPI IRQ_USI0_UART_PERIC0 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&dummy_clk 0>, <&dummy_clk 0>;
> + clock-names = "uart", "clk_uart_baud0";
> + status = "okay";
> + };
> +
> + pmu_system_controller: system-controller@17460000 {
> + compatible = "google,gs101-pmu", "syscon";
> + reg = <0x0 0x17460000 0x10000>;
> + };
> +
> + watchdog_cl0: watchdog@10060000 {
> + compatible = "google,gs101-wdt";
> + reg = <0x0 0x10060000 0x100>;
> + interrupts = <GIC_SPI IRQ_WDT_CLUSTER0_MISC IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER0>, <&ext_24_5m>;
> + clock-names = "watchdog", "watchdog_src";
> + timeout-sec = <30>;
> + samsung,syscon-phandle = <&pmu_system_controller>;
> + samsung,cluster-index = <0>;
> + };
> +
> + watchdog_cl1: watchdog@10070000 {
> + compatible = "google,gs101-wdt";
> + reg = <0x0 0x10070000 0x100>;
> + interrupts = <GIC_SPI IRQ_WDT_CLUSTER1_MISC IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER1>, <&ext_24_5m>;
> + clock-names = "watchdog", "watchdog_src";
> + timeout-sec = <30>;
> + samsung,syscon-phandle = <&pmu_system_controller>;
> + samsung,cluster-index = <1>;
> + status = "disabled";
> + };
> +
> + cmu_top: clock-controller@1e080000 {
> + compatible = "google,gs101-cmu-top";
> + reg = <0x0 0x1e080000 0x8000>;
> + #clock-cells = <1>;
> +
> + clocks = <&ext_24_5m>;
> + clock-names = "oscclk";
> + };
> +
> + cmu_apm: clock-controller@17400000 {
> + compatible = "google,gs101-cmu-apm";
> + reg = <0x0 0x17400000 0x8000>;
> + #clock-cells = <1>;
> +
> + clocks = <&ext_24_5m>;
> + clock-names = "oscclk";
> + };
> +
> + cmu_misc: clock-controller@10010000 {
> + compatible = "google,gs101-cmu-misc";
> + reg = <0x0 0x10010000 0x8000>;
> + #clock-cells = <1>;
> +
> + clocks = <&ext_24_5m>, <&cmu_top CLK_DOUT_MISC_BUS>;
> + clock-names = "oscclk", "dout_cmu_misc_bus";
> + };
> +
> + dsu-pmu-0 {
> + compatible = "arm,dsu-pmu";
> + interrupts = <GIC_SPI IRQ_CPUCL0_CLUSTERPMUIRQ_CPUCL0 IRQ_TYPE_LEVEL_HIGH>;
> + cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
> + };
> +
> + gpio_keys: gpio_keys {
> + compatible = "gpio-keys";
> + };
> +
> +};
> --
> 2.42.0.582.g8ccd20d70d-goog
>
^ permalink raw reply [flat|nested] 150+ messages in thread* Re: [PATCH 18/21] arm64: dts: google: Add initial Google gs101 SoC support
@ 2023-10-05 17:59 ` William McVicker
0 siblings, 0 replies; 150+ messages in thread
From: William McVicker @ 2023-10-05 17:59 UTC (permalink / raw)
To: Peter Griffin
Cc: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi, tudor.ambarus,
andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog, gregkh, kernel-team
On 10/05/2023, Peter Griffin wrote:
> Google gs101 SoC is ARMv8 mobile SoC found in the Pixel 6,
> (oriole) Pixel 6a (bluejay) and Pixel 6 pro (raven) mobile
> phones. It features:
> * 4xA55 little cluster
> * 2xA76 Mid cluster
> * 2xX1 Big cluster
>
> This commit adds the basic device tree for gs101 (SoC) and oriole
> (pixel 6). Further platform support will be added over time.
>
> It has been tested with a minimal busybox initramfs and boots to
> a shell.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> arch/arm64/Kconfig.platforms | 6 +
> arch/arm64/boot/dts/Makefile | 1 +
> arch/arm64/boot/dts/google/Makefile | 6 +
> arch/arm64/boot/dts/google/gs101-oriole.dts | 68 +
> arch/arm64/boot/dts/google/gs101-pinctrl.dtsi | 1134 +++++++++++++++++
> arch/arm64/boot/dts/google/gs101-pinctrl.h | 17 +
> arch/arm64/boot/dts/google/gs101.dtsi | 501 ++++++++
> 7 files changed, 1733 insertions(+)
> create mode 100644 arch/arm64/boot/dts/google/Makefile
> create mode 100644 arch/arm64/boot/dts/google/gs101-oriole.dts
> create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.dtsi
> create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.h
> create mode 100644 arch/arm64/boot/dts/google/gs101.dtsi
>
> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
> index 6069120199bb..a5ed1b719488 100644
> --- a/arch/arm64/Kconfig.platforms
> +++ b/arch/arm64/Kconfig.platforms
> @@ -107,6 +107,12 @@ config ARCH_EXYNOS
> help
> This enables support for ARMv8 based Samsung Exynos SoC family.
>
> +config ARCH_GOOGLE_TENSOR
> + bool "Google Tensor SoC fmaily"
> + depends on ARCH_EXYNOS
> + help
> + Support for ARMv8 based Google Tensor platforms.
I'd like to bring up this thread and discuss the option of not introducing
another ARCH_* config:
https://lore.kernel.org/all/20200306103652.GA3634389@kroah.com/
I especially don't like the "depends on ARCH_EXYNOS" because that forces one to
include all the other Exynos drivers that ARCH_EXYNOS selects that Google
Tensor SoCs don't need. Can we consider using SOC_GOOGLE instead and for all
drivers that actually depend on the SoC hardware, we can just add "depends on
SOC_GOOGLE"?
The idea is that drivers should be tied to hardware -- not a specific vendor.
By making drivers depend on ARCH_*, you are introducing an arbitrary vendor
dependency and not a hardware dependency.
Thanks,
Will
> +
> config ARCH_SPARX5
> bool "Microchip Sparx5 SoC family"
> select PINCTRL
> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
> index 30dd6347a929..a4ee7b628114 100644
> --- a/arch/arm64/boot/dts/Makefile
> +++ b/arch/arm64/boot/dts/Makefile
> @@ -13,6 +13,7 @@ subdir-y += broadcom
> subdir-y += cavium
> subdir-y += exynos
> subdir-y += freescale
> +subdir-y += google
> subdir-y += hisilicon
> subdir-y += intel
> subdir-y += lg
> diff --git a/arch/arm64/boot/dts/google/Makefile b/arch/arm64/boot/dts/google/Makefile
> new file mode 100644
> index 000000000000..6d2026a767d4
> --- /dev/null
> +++ b/arch/arm64/boot/dts/google/Makefile
> @@ -0,0 +1,6 @@
> +# SPDX-License-Identifier: GPL-2.0
> +
> +dtb-$(CONFIG_ARCH_GOOGLE_TENSOR) += \
> + gs101-oriole.dtb \
> +
> +
> diff --git a/arch/arm64/boot/dts/google/gs101-oriole.dts b/arch/arm64/boot/dts/google/gs101-oriole.dts
> new file mode 100644
> index 000000000000..e531a39a76a4
> --- /dev/null
> +++ b/arch/arm64/boot/dts/google/gs101-oriole.dts
> @@ -0,0 +1,68 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Oriole DVT Device Tree
> + *
> + * Copyright 2021-2023 Google,LLC
> + */
> +
> +/dts-v1/;
> +/plugin/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include "gs101-pinctrl.h"
> +#include "gs101.dtsi"
> +
> +/ {
> + model = "Oriole DVT";
> + compatible = "google,gs101-oriole", "google,gs101";
> +};
> +
> +&pinctrl_1 {
> + key_voldown: key-voldown-pins {
> + samsung,pins = "gpa7-3";
> + samsung,pin-function = <0xf>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> +
> + key_volup: key-volup-pins {
> + samsung,pins = "gpa8-1";
> + samsung,pin-function = <0xf>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> +};
> +
> +&pinctrl_0 {
> + key_power: key-power-pins {
> + samsung,pins = "gpa10-1";
> + samsung,pin-function = <0xf>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> +};
> +
> +&gpio_keys {
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&key_voldown &key_volup &key_power>;
> + button-vol-down {
> + label = "KEY_VOLUMEDOWN";
> + linux,code = <114>;
> + gpios = <&gpa7 3 0xf>;
> + wakeup-source;
> + };
> + button-vol-up {
> + label = "KEY_VOLUMEUP";
> + linux,code = <115>;
> + gpios = <&gpa8 1 0xf>;
> + wakeup-source;
> + };
> + button-power {
> + label = "KEY_POWER";
> + linux,code = <116>;
> + gpios = <&gpa10 1 0xf>;
> + wakeup-source;
> + };
> +};
> diff --git a/arch/arm64/boot/dts/google/gs101-pinctrl.dtsi b/arch/arm64/boot/dts/google/gs101-pinctrl.dtsi
> new file mode 100644
> index 000000000000..24825205ede8
> --- /dev/null
> +++ b/arch/arm64/boot/dts/google/gs101-pinctrl.dtsi
> @@ -0,0 +1,1134 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * GS101 SoC pin-mux and pin-config device tree source
> + *
> + * Copyright 2019-2023 Google LLC
> + *
> + */
> +
> +#include <dt-bindings/interrupt-controller/gs101.h>
> +#include <arm64/exynos/exynos-pinctrl.h>
> +#include "gs101-pinctrl.h"
> +
> +/ {
> + /* GPIO_ALIVE */
> + pinctrl@174d0000 {
> + gpa0: gpa0-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI IRQ_ALIVE_EINT0 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT1 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT2 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT3 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT4 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT5 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT6 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT7 ITLH>;
> + };
> + gpa1: gpa1-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI IRQ_ALIVE_EINT8 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT9 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT10 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT11 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT12 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT13 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT14 ITLH>;
> + };
> + gpa2: gpa2-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI IRQ_ALIVE_EINT15 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT16 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT17 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT18 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT19 ITLH>;
> + };
> + gpa3: gpa3-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI IRQ_ALIVE_EINT20 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT21 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT22 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT23 ITLH>;
> + };
> + gpa4: gpa4-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI IRQ_ALIVE_EINT24 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT25 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT26 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT27 ITLH>;
> + };
> + gpa5: gpa5-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <GIC_SPI IRQ_ALIVE_EINT28 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT29 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT30 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT31 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT32 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT33 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT34 ITLH>;
> + };
> + gpa9: gpa9-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <GIC_SPI IRQ_ALIVE_EINT35 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT36 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT37 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT38 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT39 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT40 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT41 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT42 ITLH>;
> + };
> + gpa10: gpa10-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <GIC_SPI IRQ_ALIVE_EINT43 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT44 ITLH>;
> + };
> +
> + uart15_bus: uart15-bus-pins {
> + samsung,pins = "gpa2-3", "gpa2-4";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + };
> +
> + uart16_bus: uart16-bus-pins {
> + samsung,pins = "gpa3-0", "gpa3-1", "gpa3-2", "gpa3-3";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + };
> +
> + uart16_bus_rts: uart1-bus-rts-pins {
> + samsung,pins = "gpa3-2";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-val = <1>;
> + };
> +
> + uart16_bus_tx_dat: uart1-bus-tx-dat-pins {
> + samsung,pins = "gpa3-1";
> + samsung,pin-val = <1>;
> + };
> +
> + uart16_bus_tx_con: uart1-bus-tx-con-pins {
> + samsung,pins = "gpa3-1";
> + samsung,pin-function = <1>;
> + };
> +
> + uart17_bus: uart17-bus-pins {
> + samsung,pins = "gpa4-0", "gpa4-1", "gpa4-2", "gpa4-3";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + };
> +
> + spi15_bus: spi15-bus-pins {
> + samsung,pins = "gpa4-0", "gpa4-1", "gpa4-2";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi15_cs: spi15-cs-pins {
> + samsung,pins = "gpa4-3";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + };
> + /* GPIO_FAR_ALIVE */
> + pinctrl@174e0000 {
> + gpa6: gpa6-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI IRQ_ALIVE_EINT45 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT46 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT47 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT48 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT49 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT50 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT51 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT52 ITLH>;
> + };
> + gpa7: gpa7-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI IRQ_ALIVE_EINT53 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT54 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT55 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT56 ITLH>;
> + };
> + gpa8: gpa8-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI IRQ_ALIVE_EINT57 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT58 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT59 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT60 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT61 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT62 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT63 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT64 ITLH>;
> + };
> + gpa11: gpa11-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI IRQ_ALIVE_EINT65 ITLH>,
> + <GIC_SPI IRQ_ALIVE_EINT66 ITLH>;
> + };
> +
> + };
> + /* GPIO_GSACORE */
> + pinctrl@17a80000 {
> + gps0: gps0-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gps1: gps1-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gps2: gps2-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + };
> + /* GPIO_GSACTRL */
> + pinctrl@17940000 {
> + gps3: gps3-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + };
> + /* GPIO_HSI1 */
> + pinctrl@11840000 {
> + gph0: gph0-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gph1: gph1-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + pcie0_clkreq: pcie0-clkreq-pins{
> + samsung,pins = "gph0-1";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <GS101_PIN_DRV_10_MA>;
> + samsung,pin-con-pdn = <3>;
> + samsung,pin-pud-pdn = <3>;
> + };
> + pcie0_perst: pcie0-perst-pins {
> + samsung,pins = "gph0-0";
> + samsung,pin-function = <1>;
> + samsung,pin-drv = <GS101_PIN_DRV_10_MA>;
> + samsung,pin-con-pdn = <3>;
> + };
> + };
> + /* GPIO_HSI2 */
> + pinctrl@14440000 {
> + gph2: gph2-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gph3: gph3-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gph4: gph4-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + sd2_clk: sd2-clk-pins {
> + samsung,pins = "gph4-0";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>;
> + };
> +
> + sd2_cmd: sd2-cmd-pins {
> + samsung,pins = "gph4-1";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>;
> + };
> +
> + sd2_bus1: sd2-bus-width1-pins {
> + samsung,pins = "gph4-2";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>;
> + };
> +
> + sd2_bus4: sd2-bus-width4-pins {
> + samsung,pins = "gph4-3", "gph4-4", "gph4-5";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>;
> + };
> +
> + sd2_clk_fast_slew_rate_1x: sd2-clk-fast-slew-rate-1x-pins {
> + samsung,pins = "gph4-0";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> +
> + sd2_clk_fast_slew_rate_2x: sd2-clk-fast-slew-rate-2x-pins {
> + samsung,pins = "gph4-0";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> + };
> +
> + sd2_clk_fast_slew_rate_3x: sd2-clk-fast-slew-rate-3x-pins {
> + samsung,pins = "gph4-0";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>;
> + };
> +
> + sd2_clk_fast_slew_rate_4x: sd2-clk-fast-slew-rate-4x-pins {
> + samsung,pins = "gph4-0";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_10_MA>;
> + };
> + ufs_rst_n: ufs-rst-n-pins {
> + samsung,pins = "gph3-1";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-con-pdn = <3>;
> + samsung,pin-pud-pdn = <0>;
> + };
> +
> + ufs_refclk_out: ufs-refclk-out-pins {
> + samsung,pins = "gph3-0";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-con-pdn = <3>;
> + samsung,pin-pud-pdn = <0>;
> + };
> + pcie1_clkreq: pcie1-clkreq-pins {
> + samsung,pins = "gph2-1";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <GS101_PIN_DRV_10_MA>;
> + samsung,pin-con-pdn = <3>;
> + samsung,pin-pud-pdn = <3>;
> + };
> + pcie1_perst: pcie1-perst-pins {
> + samsung,pins = "gph2-0";
> + samsung,pin-function = <1>;
> + samsung,pin-drv = <GS101_PIN_DRV_10_MA>;
> + samsung,pin-con-pdn = <3>;
> + };
> + };
> + /* GPIO_PERIC0 */
> + pinctrl@10840000 {
> + gpp0: gpp0-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gpp1: gpp1-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gpp2: gpp2-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gpp3: gpp3-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gpp4: gpp4-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gpp5: gpp5-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gpp6: gpp6-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gpp7: gpp7-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gpp8: gpp8-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gpp9: gpp9-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gpp10: gpp10-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gpp11: gpp11-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gpp12: gpp12-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gpp13: gpp13-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gpp14: gpp14-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gpp15: gpp15-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gpp16: gpp16-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gpp17: gpp17-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gpp18: gpp18-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gpp19: gpp19-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + /* USI_PERIC0_UART_DBG */
> + uart0_bus: uart0-bus-pins {
> + samsung,pins = "gpp1-2", "gpp1-3";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + };
> +
> + disp_te_pri_on: disp-te-pri-on-pins {
> + samsung,pins = "gpp0-3";
> + samsung,pin-function = <0xf>;
> + };
> +
> + disp_te_pri_off: disp-te-pri-off-pins {
> + samsung,pins = "gpp0-3";
> + samsung,pin-function = <0>;
> + };
> +
> + disp_te_sec_on: disp-te-sec-on-pins {
> + samsung,pins = "gpp0-4";
> + samsung,pin-function = <0xf>;
> + };
> +
> + disp_te_sec_off: disp-te-sec-off-pins {
> + samsung,pins = "gpp0-4";
> + samsung,pin-function = <0>;
> + };
> +
> + sensor_mclk1_out: sensor-mclk1-out-pins {
> + samsung,pins = "gpp3-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> + samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> + };
> + sensor_mclk1_fn: sensor-mclk1-fn-pins {
> + samsung,pins = "gpp3-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> + };
> + sensor_mclk2_out: sensor-mclk2-out-pins {
> + samsung,pins = "gpp5-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> + samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> + };
> + sensor_mclk2_fn: sensor-mclk2-fn-pins {
> + samsung,pins = "gpp5-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> + };
> + sensor_mclk3_out: sensor-mclk3-out-pins {
> + samsung,pins = "gpp7-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> + samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> + };
> + sensor_mclk3_fn: sensor-mclk3-fn-pins {
> + samsung,pins = "gpp7-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> + };
> + sensor_mclk4_out: sensor-mclk4-out-pins {
> + samsung,pins = "gpp9-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> + samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> + };
> + sensor_mclk4_fn: sensor-mclk4-fn-pins {
> + samsung,pins = "gpp9-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> + };
> + sensor_mclk5_out: sensor-mclk5-out-pins {
> + samsung,pins = "gpp11-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> + samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> + };
> + sensor_mclk5_fn: sensor-mclk5-fn-pins {
> + samsung,pins = "gpp11-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> + };
> + sensor_mclk6_out: sensor-mclk6-out-pins {
> + samsung,pins = "gpp13-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> + samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> + };
> + sensor_mclk6_fn: sensor-mclk6-fn-pins {
> + samsung,pins = "gpp13-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> + };
> + sensor_mclk7_out: sensor-mclk7-out-pins {
> + samsung,pins = "gpp15-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> + samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> + };
> + sensor_mclk7_fn: sensor-mclk7-fn-pins {
> + samsung,pins = "gpp15-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> + };
> + sensor_mclk8_out: sensor-mclk8-out-pins {
> + samsung,pins = "gpp17-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> + samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> + };
> + sensor_mclk8_fn: sensor-mclk8-fn-pins {
> + samsung,pins = "gpp17-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> + };
> + hsi2c14_bus: hsi2c14-bus-pins {
> + samsung,pins = "gpp18-0", "gpp18-1";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + uart14_bus_single: uart14-bus-pins {
> + samsung,pins = "gpp18-0", "gpp18-1",
> + "gpp18-2", "gpp18-3";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + };
> + spi14_bus: spi14-bus-pins {
> + samsung,pins = "gpp18-0", "gpp18-1", "gpp18-2";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi14_cs: spi14-cs-pins {
> + samsung,pins = "gpp18-3";
> + samsung,pin-function = <1>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi14_cs_func: spi14-cs-func-pins {
> + samsung,pins = "gpp18-3";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + hsi2c8_bus: hsi2c8-bus-pins {
> + samsung,pins = "gpp16-0", "gpp16-1";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + samsung,pin-pud-pdn = <EXYNOS_PIN_PDN_OUT0>;
> + };
> + uart8_bus_single: uart8-bus-pins {
> + samsung,pins = "gpp16-0", "gpp16-1", "gpp16-2",
> + "gpp16-3";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + };
> + spi8_bus: spi8-bus-pins {
> + samsung,pins = "gpp16-0", "gpp16-1", "gpp16-2";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi8_cs: spi8-cs-pins {
> + samsung,pins = "gpp16-3";
> + samsung,pin-function = <1>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi8_cs_func: spi8-cs-func-pins {
> + samsung,pins = "gpp16-3";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + hsi2c7_bus: hsi2c7-bus-pins {
> + samsung,pins = "gpp14-0", "gpp14-1";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + uart7_bus_single: uart7-bus-pins {
> + samsung,pins = "gpp14-0", "gpp14-1",
> + "gpp14-2", "gpp14-3";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + };
> + spi7_bus: spi7-bus-pins {
> + samsung,pins = "gpp14-0", "gpp14-1", "gpp14-2";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi7_cs: spi7-cs-pins {
> + samsung,pins = "gpp14-3";
> + samsung,pin-function = <1>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi7_cs_func: spi7-cs-func-pins {
> + samsung,pins = "gpp14-3";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + hsi2c6_bus: hsi2c6-bus-pins {
> + samsung,pins = "gpp12-0", "gpp12-1";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + uart6_bus_single: uart6-bus-pins {
> + samsung,pins = "gpp12-0", "gpp12-1",
> + "gpp12-2", "gpp12-3";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + };
> + spi6_bus: spi6-bus-pins {
> + samsung,pins = "gpp12-0", "gpp12-1", "gpp12-2";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi6_cs: spi6-cs-pins {
> + samsung,pins = "gpp12-3";
> + samsung,pin-function = <1>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi6_cs_func: spi6-cs-func-pins {
> + samsung,pins = "gpp12-3";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + hsi2c5_bus: hsi2c5-bus-pins {
> + samsung,pins = "gpp10-0", "gpp10-1";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + uart5_bus_single: uart5-bus-pins {
> + samsung,pins = "gpp10-0", "gpp10-1",
> + "gpp10-2", "gpp10-3";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + };
> + spi5_bus: spi5-bus-pins {
> + samsung,pins = "gpp10-0", "gpp10-1", "gpp10-2";
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
> + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>;
> + };
> + spi5_cs_func: spi5-cs-func-pins {
> + samsung,pins = "gpp10-3";
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
> + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>;
> + };
> + hsi2c4_bus: hsi2c4-bus-pins {
> + samsung,pins = "gpp8-0", "gpp8-1";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + uart4_bus_single: uart4-bus-pins {
> + samsung,pins = "gpp8-0", "gpp8-1",
> + "gpp8-2", "gpp8-3";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + };
> + spi4_bus: spi4-bus-pins {
> + samsung,pins = "gpp8-0", "gpp8-1", "gpp8-2";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi4_cs: spi4-cs-pins {
> + samsung,pins = "gpp8-3";
> + samsung,pin-function = <1>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi4_cs_func: spi4-cs-func-pins {
> + samsung,pins = "gpp8-3";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + hsi2c3_bus: hsi2c3-bus-pins {
> + samsung,pins = "gpp6-0", "gpp6-1";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + uart3_bus_single: uart3-bus-pins {
> + samsung,pins = "gpp6-0", "gpp6-1",
> + "gpp6-2", "gpp6-3";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + };
> + spi3_bus: spi3-bus-pins {
> + samsung,pins = "gpp6-0", "gpp6-1", "gpp6-2";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi3_cs: spi3-cs-pins {
> + samsung,pins = "gpp6-3";
> + samsung,pin-function = <1>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi3_cs_func: spi3-cs-func-pins {
> + samsung,pins = "gpp6-3";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + hsi2c2_bus: hsi2c2-bus-pins {
> + samsung,pins = "gpp4-0", "gpp4-1";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + uart2_bus_single: uart2-bus-pins {
> + samsung,pins = "gpp4-0", "gpp4-1",
> + "gpp4-2", "gpp4-3";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + };
> + spi2_bus: spi2-bus-pins {
> + samsung,pins = "gpp4-0", "gpp4-1", "gpp4-2";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi2_cs: spi2-cs-pins {
> + samsung,pins = "gpp4-3";
> + samsung,pin-function = <1>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi2_cs_func: spi2-cs-func-pins {
> + samsung,pins = "gpp4-3";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + hsi2c1_bus: hsi2c1-bus-pins {
> + samsung,pins = "gpp2-0", "gpp2-1";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + uart1_bus_single: uart1-bus-pins {
> + samsung,pins = "gpp2-0", "gpp2-1",
> + "gpp2-2", "gpp2-3";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + };
> + spi1_bus: spi1-bus-pins {
> + samsung,pins = "gpp2-0", "gpp2-1", "gpp2-2";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi1_cs: spi1-cs-pins {
> + samsung,pins = "gpp2-3";
> + samsung,pin-function = <1>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi1_cs_func: spi1-cs-func-pins {
> + samsung,pins = "gpp2-3";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + };
> + /* GPIO_PERIC1 */
> + pinctrl@10c40000 {
> + gpp20: gpp20-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gpp21: gpp21-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gpp22: gpp22-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gpp23: gpp23-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gpp24: gpp24-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gpp25: gpp25-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gpp26: gpp26-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + gpp27: gpp27-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + hsi2c13_bus: hsi2c13-bus-pins {
> + samsung,pins = "gpp25-0", "gpp25-1";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + uart13_bus_single: uart13-bus-pins {
> + samsung,pins = "gpp25-0", "gpp25-1",
> + "gpp25-2", "gpp25-3";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + };
> + spi13_bus: spi13-bus-pins {
> + samsung,pins = "gpp25-0", "gpp25-1", "gpp25-2";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi13_cs: spi13-cs-pins {
> + samsung,pins = "gpp25-3";
> + samsung,pin-function = <1>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi13_cs_func: spi13-cs-func-pins {
> + samsung,pins = "gpp25-3";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + hsi2c12_bus: hsi2c12-bus-pins {
> + samsung,pins = "gpp23-4", "gpp23-5";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + uart12_bus_single: uart12-bus-pins {
> + samsung,pins = "gpp23-4", "gpp23-5",
> + "gpp23-6", "gpp23-7";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + };
> + spi12_bus: spi12-bus-pins {
> + samsung,pins = "gpp23-4", "gpp23-5", "gpp23-6";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi14_cs2: spi14-cs2-pins {
> + samsung,pins = "gpp23-6";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi12_cs: spi12-cs-pins {
> + samsung,pins = "gpp23-7";
> + samsung,pin-function = <1>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi12_cs_func: spi12-cs-func-pins {
> + samsung,pins = "gpp23-7";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + hsi2c11_bus: hsi2c11-bus-pins {
> + samsung,pins = "gpp23-0", "gpp23-1";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + uart11_bus_single: uart11-bus-pins {
> + samsung,pins = "gpp23-0", "gpp23-1",
> + "gpp23-2", "gpp23-3";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + };
> + spi11_bus: spi11-bus-pins {
> + samsung,pins = "gpp23-0", "gpp23-1", "gpp23-2";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi11_cs: spi11-cs-pins {
> + samsung,pins = "gpp23-3";
> + samsung,pin-function = <1>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi11_cs_func: spi11-cs-func-pins {
> + samsung,pins = "gpp23-3";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + hsi2c10_bus: hsi2c10-bus-pins {
> + samsung,pins = "gpp21-0", "gpp21-1";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + uart10_bus_single: uart10-bus-pins {
> + samsung,pins = "gpp21-0", "gpp21-1",
> + "gpp21-2", "gpp21-3";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + };
> + spi10_bus: spi10-bus-pins {
> + samsung,pins = "gpp21-0", "gpp21-1", "gpp21-2";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi10_cs: spi10-cs-pins {
> + samsung,pins = "gpp21-3";
> + samsung,pin-function = <1>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi10_cs_func: spi10-cs-func-pins {
> + samsung,pins = "gpp21-3";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + hsi2c9_bus: hsi2c9-bus-pins {
> + samsung,pins = "gpp20-4", "gpp20-5";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + uart9_bus_single: uart9-bus-pins {
> + samsung,pins = "gpp20-4", "gpp20-5",
> + "gpp20-6", "gpp20-7";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + };
> + spi9_bus: spi9-bus-pins {
> + samsung,pins = "gpp20-4", "gpp20-5", "gpp20-6";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi9_cs: spi9-cs-pins {
> + samsung,pins = "gpp20-7";
> + samsung,pin-function = <1>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi9_cs_func: spi9-cs-func-pins {
> + samsung,pins = "gpp20-7";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + hsi2c0_bus: hsi2c0-bus-pins {
> + samsung,pins = "gpp20-0", "gpp20-1";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + uart0_bus_single: uart0-bus-pins {
> + samsung,pins = "gpp20-0", "gpp20-1",
> + "gpp20-2", "gpp20-3";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + };
> + spi0_bus: spi0-bus-pins {
> + samsung,pins = "gpp20-0", "gpp20-1", "gpp20-2";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi0_cs: spi0-cs-pins {
> + samsung,pins = "gpp20-3";
> + samsung,pin-function = <1>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + spi0_cs_func: spi0-cs-func-pins {
> + samsung,pins = "gpp20-3";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> + };
> + };
> +};
> diff --git a/arch/arm64/boot/dts/google/gs101-pinctrl.h b/arch/arm64/boot/dts/google/gs101-pinctrl.h
> new file mode 100644
> index 000000000000..acc77c684f0d
> --- /dev/null
> +++ b/arch/arm64/boot/dts/google/gs101-pinctrl.h
> @@ -0,0 +1,17 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Pinctrl binding constants for GS101
> + *
> + * Copyright (c) 2020-2023 Google, LLC.
> + */
> +
> +#ifndef __DT_BINDINGS_PINCTRL_GS101_H__
> +#define __DT_BINDINGS_PINCTRL_GS101_H__
> +
> +/* GS101 drive strengths */
> +#define GS101_PIN_DRV_2_5_MA 0
> +#define GS101_PIN_DRV_5_MA 1
> +#define GS101_PIN_DRV_7_5_MA 2
> +#define GS101_PIN_DRV_10_MA 3
> +
> +#endif /* __DT_BINDINGS_PINCTRL_GS101_H__ */
> diff --git a/arch/arm64/boot/dts/google/gs101.dtsi b/arch/arm64/boot/dts/google/gs101.dtsi
> new file mode 100644
> index 000000000000..0bd43745f6fa
> --- /dev/null
> +++ b/arch/arm64/boot/dts/google/gs101.dtsi
> @@ -0,0 +1,501 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * GS101 SoC
> + *
> + * Copyright 2019-2023 Google LLC
> + *
> + */
> +
> +#include <dt-bindings/clock/gs101.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/interrupt-controller/gs101.h>
> +
> +#include "gs101-pinctrl.dtsi"
> +
> +/ {
> + compatible = "google,gs101";
> + interrupt-parent = <&gic>;
> + #address-cells = <2>;
> + #size-cells = <1>;
> +
> + aliases {
> + pinctrl0 = &pinctrl_0;
> + pinctrl1 = &pinctrl_1;
> + pinctrl2 = &pinctrl_2;
> + pinctrl3 = &pinctrl_3;
> + pinctrl4 = &pinctrl_4;
> + pinctrl5 = &pinctrl_5;
> + pinctrl6 = &pinctrl_6;
> + pinctrl7 = &pinctrl_7;
> +
> + };
> +
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&cpu0>;
> + };
> + core1 {
> + cpu = <&cpu1>;
> + };
> + core2 {
> + cpu = <&cpu2>;
> + };
> + core3 {
> + cpu = <&cpu3>;
> + };
> + };
> + cluster1 {
> + core0 {
> + cpu = <&cpu4>;
> + };
> + core1 {
> + cpu = <&cpu5>;
> + };
> + };
> + cluster2 {
> + core0 {
> + cpu = <&cpu6>;
> + };
> + core1 {
> + cpu = <&cpu7>;
> + };
> + };
> + };
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0x0 0x0000>;
> + enable-method = "psci";
> + cpu-idle-states = <&ANANKE_CPU_SLEEP>;
> + capacity-dmips-mhz = <250>;
> + dynamic-power-coefficient = <70>;
> + };
> + cpu1: cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0x0 0x0100>;
> + enable-method = "psci";
> + cpu-idle-states = <&ANANKE_CPU_SLEEP>;
> + capacity-dmips-mhz = <250>;
> + dynamic-power-coefficient = <70>;
> + };
> + cpu2: cpu@200 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0x0 0x0200>;
> + enable-method = "psci";
> + cpu-idle-states = <&ANANKE_CPU_SLEEP>;
> + capacity-dmips-mhz = <250>;
> + dynamic-power-coefficient = <70>;
> + };
> + cpu3: cpu@300 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0x0 0x0300>;
> + enable-method = "psci";
> + cpu-idle-states = <&ANANKE_CPU_SLEEP>;
> + capacity-dmips-mhz = <250>;
> + dynamic-power-coefficient = <70>;
> + };
> + cpu4: cpu@400 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0x0 0x0400>;
> + enable-method = "psci";
> + cpu-idle-states = <&ENYO_CPU_SLEEP>;
> + capacity-dmips-mhz = <620>;
> + dynamic-power-coefficient = <284>;
> + };
> + cpu5: cpu@500 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0x0 0x0500>;
> + enable-method = "psci";
> + cpu-idle-states = <&ENYO_CPU_SLEEP>;
> + capacity-dmips-mhz = <620>;
> + dynamic-power-coefficient = <284>;
> + };
> + cpu6: cpu@600 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0x0 0x0600>;
> + enable-method = "psci";
> + cpu-idle-states = <&HERA_CPU_SLEEP>;
> + capacity-dmips-mhz = <1024>;
> + dynamic-power-coefficient = <650>;
> + };
> + cpu7: cpu@700 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0x0 0x0700>;
> + enable-method = "psci";
> + cpu-idle-states = <&HERA_CPU_SLEEP>;
> + capacity-dmips-mhz = <1024>;
> + dynamic-power-coefficient = <650>;
> + };
> +
> + idle-states {
> + entry-method = "psci";
> +
> + ANANKE_CPU_SLEEP: cpu-ananke-sleep {
> + idle-state-name = "c2";
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x0010000>;
> + entry-latency-us = <70>;
> + exit-latency-us = <160>;
> + min-residency-us = <2000>;
> + status = "okay";
> + };
> +
> + ENYO_CPU_SLEEP: cpu-enyo-sleep {
> + idle-state-name = "c2";
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x0010000>;
> + entry-latency-us = <150>;
> + exit-latency-us = <190>;
> + min-residency-us = <2500>;
> + status = "okay";
> + };
> +
> + HERA_CPU_SLEEP: cpu-hera-sleep {
> + idle-state-name = "c2";
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x0010000>;
> + entry-latency-us = <235>;
> + exit-latency-us = <220>;
> + min-residency-us = <3500>;
> + status = "okay";
> + };
> + };
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> +
> + reserved_memory: reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <1>;
> + ranges;
> +
> + tpu_fw_reserved: tpu_fw@93000000 {
> + reg = <0x0 0x93000000 0x1000000>;
> + no-map;
> + };
> +
> + gsa_reserved_protected: gsa@90200000 {
> + reg = <0x0 0x90200000 0x400000>;
> + no-map;
> + };
> +
> + aoc_reserve: aoc@94000000 {
> + reg = <0x0 0x94000000 0x03000000>;
> + no-map;
> + };
> +
> + abl_reserved: abl@f8800000 {
> + reg = <0x0 0xf8800000 0x02000000>;
> + no-map;
> + };
> +
> + dss_log_reserved: dss_log_reserved@fd3f0000 {
> + reg = <0 0xfd3f0000 0x0000e000>;
> + no-map;
> + };
> +
> + debug_kinfo_reserved: debug_kinfo_reserved@fd3fe000 {
> + reg = <0 0xfd3fe000 0x00001000>;
> + no-map;
> + };
> +
> + bldr_log_reserved: bldr_log_reserved@fd800000 {
> + reg = <0 0xfd800000 0x00100000>;
> + no-map;
> + };
> +
> + bldr_log_hist_reserved: bldr_log_hist_reserved@fd900000 {
> + reg = <0 0xfd900000 0x00002000>;
> + no-map;
> + };
> + };
> +
> + /* bootloader requires ect node */
> + ect {
> + parameter_address = <0x90000000>;
> + parameter_size = <0x53000>;
> + };
> +
> + chosen {
> + bootargs = "earlycon=exynos4210,mmio32,0x10A00000 clk_ignore_unused";
> + };
> +
> + gic: interrupt-controller@10400000 {
> + compatible = "arm,gic-v3";
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + reg = <0x0 0x10400000 0x10000>, /* GICD */
> + <0x0 0x10440000 0x100000>; /* GICR * 8 */
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
> + clock-frequency = <24576000>;
> + };
> +
> + ext_24_5m: ext_24_5m {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <24576000>;
> + clock-output-names = "oscclk";
> + };
> +
> + ext_200m: ext_200m {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <200000000>;
> + clock-output-names = "ext-200m";
> + };
> +
> + /* GPIO_ALIVE */
> + pinctrl_0: pinctrl@174d0000 {
> + compatible = "google,gs101-pinctrl";
> + reg = <0x00000000 0x174d0000 0x00001000>;
> + interrupts = <GIC_SPI IRQ_ALIVE_EINT0 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT1 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT2 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT3 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT4 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT5 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT6 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT7 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT8 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT9 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT10 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT11 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT12 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT13 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT14 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT15 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT16 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT17 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT18 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT19 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT20 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT21 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT22 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT23 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT24 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT25 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT26 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT27 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT28 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT29 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT30 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT31 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT32 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT33 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT34 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT35 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT36 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT37 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT38 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT39 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT40 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT41 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT42 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT43 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT44 IRQ_TYPE_LEVEL_HIGH>;
> +
> + wakeup-interrupt-controller {
> + compatible = "google,gs101-wakeup-eint";
> + };
> + };
> +
> + /* GPIO_FAR_ALIVE */
> + pinctrl_1: pinctrl@174e0000 {
> + compatible = "google,gs101-pinctrl";
> + reg = <0x00000000 0x174e0000 0x00001000>;
> + interrupts = <GIC_SPI IRQ_ALIVE_EINT45 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT46 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT47 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT48 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT49 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT50 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT51 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT52 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT53 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT54 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT55 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT56 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT57 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT58 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT59 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT60 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT61 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT62 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT63 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT64 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT65 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI IRQ_ALIVE_EINT66 IRQ_TYPE_LEVEL_HIGH>;
> +
> + wakeup-interrupt-controller {
> + compatible = "google,gs101-wakeup-eint";
> + };
> + };
> +
> + /* GPIO_GSACORE */
> + pinctrl_2: pinctrl@17a80000 {
> + compatible = "google,gs101-pinctrl";
> + reg = <0x00000000 0x17a80000 0x00001000>;
> + };
> + /* GPIO_GSACTRL */
> + pinctrl_3: pinctrl@17940000 {
> + compatible = "google,gs101-pinctrl";
> + reg = <0x00000000 0x17940000 0x00001000>;
> + };
> + /* GPIO_PERIC0 */
> + pinctrl_4: pinctrl@10840000 {
> + compatible = "google,gs101-pinctrl";
> + reg = <0x00000000 0x10840000 0x00001000>;
> + interrupts = <GIC_SPI IRQ_GPIO_PERIC0_PERIC0 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + /* GPIO_PERIC1 */
> + pinctrl_5: pinctrl@10c40000 {
> + compatible = "google,gs101-pinctrl";
> + reg = <0x00000000 0x10C40000 0x00001000>;
> + interrupts = <GIC_SPI IRQ_GPIO_PERIC1_PERIC1 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + /* GPIO_HSI1 */
> + pinctrl_6: pinctrl@11840000 {
> + compatible = "google,gs101-pinctrl";
> + reg = <0x00000000 0x11840000 0x00001000>;
> + interrupts = <GIC_SPI IRQ_GPIO_HSI1_HSI1 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + /* GPIO_HSI2 */
> + pinctrl_7: pinctrl@14440000 {
> + compatible = "google,gs101-pinctrl";
> + reg = <0x00000000 0x14440000 0x00001000>;
> + interrupts = <GIC_SPI IRQ_GPIO_HSI2_HSI2 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + arm-pmu {
> + compatible = "arm,armv8-pmuv3";
> + interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
> + };
> +
> + sysreg_apm: syscon@174204e0 {
> + compatible = "google,gs101-apm-sysreg",
> + "google,gs101-sysreg", "syscon";
> + reg = <0x0 0x174204e0 0x1000>;
> + };
> +
> + sysreg_peric0: syscon@10821000 {
> + compatible = "google,gs101-peric0-sysreg",
> + "google,gs101-sysreg", "syscon";
> + reg = <0x0 0x10821000 0x40000>;
> + };
> +
> + sysreg_peric1: syscon@10c21000 {
> + compatible = "google,gs101-peric1-sysreg",
> + "google,gs101-sysreg", "syscon";
> + reg = <0x0 0x10C21000 0x40000>;
> + };
> +
> + /* TODO replace with CCF clock */
> + dummy_clk: oscillator {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <12345>;
> + clock-output-names = "pclk";
> + };
> +
> + serial_0: serial@10a00000 {
> + compatible = "samsung,exynos850-uart";
> + reg = <0x0 0x10a00000 0xc0>;
> + reg-io-width = <4>;
> + samsung,uart-fifosize = <256>;
> + interrupts = <GIC_SPI IRQ_USI0_UART_PERIC0 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&dummy_clk 0>, <&dummy_clk 0>;
> + clock-names = "uart", "clk_uart_baud0";
> + status = "okay";
> + };
> +
> + pmu_system_controller: system-controller@17460000 {
> + compatible = "google,gs101-pmu", "syscon";
> + reg = <0x0 0x17460000 0x10000>;
> + };
> +
> + watchdog_cl0: watchdog@10060000 {
> + compatible = "google,gs101-wdt";
> + reg = <0x0 0x10060000 0x100>;
> + interrupts = <GIC_SPI IRQ_WDT_CLUSTER0_MISC IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER0>, <&ext_24_5m>;
> + clock-names = "watchdog", "watchdog_src";
> + timeout-sec = <30>;
> + samsung,syscon-phandle = <&pmu_system_controller>;
> + samsung,cluster-index = <0>;
> + };
> +
> + watchdog_cl1: watchdog@10070000 {
> + compatible = "google,gs101-wdt";
> + reg = <0x0 0x10070000 0x100>;
> + interrupts = <GIC_SPI IRQ_WDT_CLUSTER1_MISC IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER1>, <&ext_24_5m>;
> + clock-names = "watchdog", "watchdog_src";
> + timeout-sec = <30>;
> + samsung,syscon-phandle = <&pmu_system_controller>;
> + samsung,cluster-index = <1>;
> + status = "disabled";
> + };
> +
> + cmu_top: clock-controller@1e080000 {
> + compatible = "google,gs101-cmu-top";
> + reg = <0x0 0x1e080000 0x8000>;
> + #clock-cells = <1>;
> +
> + clocks = <&ext_24_5m>;
> + clock-names = "oscclk";
> + };
> +
> + cmu_apm: clock-controller@17400000 {
> + compatible = "google,gs101-cmu-apm";
> + reg = <0x0 0x17400000 0x8000>;
> + #clock-cells = <1>;
> +
> + clocks = <&ext_24_5m>;
> + clock-names = "oscclk";
> + };
> +
> + cmu_misc: clock-controller@10010000 {
> + compatible = "google,gs101-cmu-misc";
> + reg = <0x0 0x10010000 0x8000>;
> + #clock-cells = <1>;
> +
> + clocks = <&ext_24_5m>, <&cmu_top CLK_DOUT_MISC_BUS>;
> + clock-names = "oscclk", "dout_cmu_misc_bus";
> + };
> +
> + dsu-pmu-0 {
> + compatible = "arm,dsu-pmu";
> + interrupts = <GIC_SPI IRQ_CPUCL0_CLUSTERPMUIRQ_CPUCL0 IRQ_TYPE_LEVEL_HIGH>;
> + cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
> + };
> +
> + gpio_keys: gpio_keys {
> + compatible = "gpio-keys";
> + };
> +
> +};
> --
> 2.42.0.582.g8ccd20d70d-goog
>
_______________________________________________
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^ permalink raw reply [flat|nested] 150+ messages in thread* Re: [PATCH 18/21] arm64: dts: google: Add initial Google gs101 SoC support
2023-10-05 17:59 ` William McVicker
@ 2023-10-05 18:05 ` Greg KH
-1 siblings, 0 replies; 150+ messages in thread
From: Greg KH @ 2023-10-05 18:05 UTC (permalink / raw)
To: William McVicker
Cc: Peter Griffin, robh+dt, krzysztof.kozlowski+dt, mturquette,
conor+dt, sboyd, tomasz.figa, s.nawrocki, linus.walleij, wim,
linux, catalin.marinas, will, arnd, olof, cw00.choi,
tudor.ambarus, andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog, kernel-team
On Thu, Oct 05, 2023 at 10:59:12AM -0700, William McVicker wrote:
> On 10/05/2023, Peter Griffin wrote:
> > Google gs101 SoC is ARMv8 mobile SoC found in the Pixel 6,
> > (oriole) Pixel 6a (bluejay) and Pixel 6 pro (raven) mobile
> > phones. It features:
> > * 4xA55 little cluster
> > * 2xA76 Mid cluster
> > * 2xX1 Big cluster
> >
> > This commit adds the basic device tree for gs101 (SoC) and oriole
> > (pixel 6). Further platform support will be added over time.
> >
> > It has been tested with a minimal busybox initramfs and boots to
> > a shell.
> >
> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> > ---
> > arch/arm64/Kconfig.platforms | 6 +
> > arch/arm64/boot/dts/Makefile | 1 +
> > arch/arm64/boot/dts/google/Makefile | 6 +
> > arch/arm64/boot/dts/google/gs101-oriole.dts | 68 +
> > arch/arm64/boot/dts/google/gs101-pinctrl.dtsi | 1134 +++++++++++++++++
> > arch/arm64/boot/dts/google/gs101-pinctrl.h | 17 +
> > arch/arm64/boot/dts/google/gs101.dtsi | 501 ++++++++
> > 7 files changed, 1733 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/google/Makefile
> > create mode 100644 arch/arm64/boot/dts/google/gs101-oriole.dts
> > create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.dtsi
> > create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.h
> > create mode 100644 arch/arm64/boot/dts/google/gs101.dtsi
> >
> > diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
> > index 6069120199bb..a5ed1b719488 100644
> > --- a/arch/arm64/Kconfig.platforms
> > +++ b/arch/arm64/Kconfig.platforms
> > @@ -107,6 +107,12 @@ config ARCH_EXYNOS
> > help
> > This enables support for ARMv8 based Samsung Exynos SoC family.
> >
> > +config ARCH_GOOGLE_TENSOR
> > + bool "Google Tensor SoC fmaily"
> > + depends on ARCH_EXYNOS
> > + help
> > + Support for ARMv8 based Google Tensor platforms.
>
> I'd like to bring up this thread and discuss the option of not introducing
> another ARCH_* config:
>
> https://lore.kernel.org/all/20200306103652.GA3634389@kroah.com/
I agree, PLEASE don't add platform config options as that makes it
impossible to make a unified kernel image that works for more than one
platform at the same time.
> I especially don't like the "depends on ARCH_EXYNOS" because that forces one to
> include all the other Exynos drivers that ARCH_EXYNOS selects that Google
> Tensor SoCs don't need. Can we consider using SOC_GOOGLE instead and for all
> drivers that actually depend on the SoC hardware, we can just add "depends on
> SOC_GOOGLE"?
Why do any of this at all? It should not be needed.
> The idea is that drivers should be tied to hardware -- not a specific vendor.
And drivers should be auto-loaded.
All of these drivers are not vendor-specific at all, they are based on
the same IP blocks as others, so that is how they should be unified.
> By making drivers depend on ARCH_*, you are introducing an arbitrary vendor
> dependency and not a hardware dependency.
Totally agree, thanks for bringing this up.
greg k-h
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 18/21] arm64: dts: google: Add initial Google gs101 SoC support
@ 2023-10-05 18:05 ` Greg KH
0 siblings, 0 replies; 150+ messages in thread
From: Greg KH @ 2023-10-05 18:05 UTC (permalink / raw)
To: William McVicker
Cc: Peter Griffin, robh+dt, krzysztof.kozlowski+dt, mturquette,
conor+dt, sboyd, tomasz.figa, s.nawrocki, linus.walleij, wim,
linux, catalin.marinas, will, arnd, olof, cw00.choi,
tudor.ambarus, andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog, kernel-team
On Thu, Oct 05, 2023 at 10:59:12AM -0700, William McVicker wrote:
> On 10/05/2023, Peter Griffin wrote:
> > Google gs101 SoC is ARMv8 mobile SoC found in the Pixel 6,
> > (oriole) Pixel 6a (bluejay) and Pixel 6 pro (raven) mobile
> > phones. It features:
> > * 4xA55 little cluster
> > * 2xA76 Mid cluster
> > * 2xX1 Big cluster
> >
> > This commit adds the basic device tree for gs101 (SoC) and oriole
> > (pixel 6). Further platform support will be added over time.
> >
> > It has been tested with a minimal busybox initramfs and boots to
> > a shell.
> >
> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> > ---
> > arch/arm64/Kconfig.platforms | 6 +
> > arch/arm64/boot/dts/Makefile | 1 +
> > arch/arm64/boot/dts/google/Makefile | 6 +
> > arch/arm64/boot/dts/google/gs101-oriole.dts | 68 +
> > arch/arm64/boot/dts/google/gs101-pinctrl.dtsi | 1134 +++++++++++++++++
> > arch/arm64/boot/dts/google/gs101-pinctrl.h | 17 +
> > arch/arm64/boot/dts/google/gs101.dtsi | 501 ++++++++
> > 7 files changed, 1733 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/google/Makefile
> > create mode 100644 arch/arm64/boot/dts/google/gs101-oriole.dts
> > create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.dtsi
> > create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.h
> > create mode 100644 arch/arm64/boot/dts/google/gs101.dtsi
> >
> > diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
> > index 6069120199bb..a5ed1b719488 100644
> > --- a/arch/arm64/Kconfig.platforms
> > +++ b/arch/arm64/Kconfig.platforms
> > @@ -107,6 +107,12 @@ config ARCH_EXYNOS
> > help
> > This enables support for ARMv8 based Samsung Exynos SoC family.
> >
> > +config ARCH_GOOGLE_TENSOR
> > + bool "Google Tensor SoC fmaily"
> > + depends on ARCH_EXYNOS
> > + help
> > + Support for ARMv8 based Google Tensor platforms.
>
> I'd like to bring up this thread and discuss the option of not introducing
> another ARCH_* config:
>
> https://lore.kernel.org/all/20200306103652.GA3634389@kroah.com/
I agree, PLEASE don't add platform config options as that makes it
impossible to make a unified kernel image that works for more than one
platform at the same time.
> I especially don't like the "depends on ARCH_EXYNOS" because that forces one to
> include all the other Exynos drivers that ARCH_EXYNOS selects that Google
> Tensor SoCs don't need. Can we consider using SOC_GOOGLE instead and for all
> drivers that actually depend on the SoC hardware, we can just add "depends on
> SOC_GOOGLE"?
Why do any of this at all? It should not be needed.
> The idea is that drivers should be tied to hardware -- not a specific vendor.
And drivers should be auto-loaded.
All of these drivers are not vendor-specific at all, they are based on
the same IP blocks as others, so that is how they should be unified.
> By making drivers depend on ARCH_*, you are introducing an arbitrary vendor
> dependency and not a hardware dependency.
Totally agree, thanks for bringing this up.
greg k-h
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 18/21] arm64: dts: google: Add initial Google gs101 SoC support
2023-10-05 18:05 ` Greg KH
@ 2023-10-05 19:18 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 150+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-05 19:18 UTC (permalink / raw)
To: Greg KH, William McVicker
Cc: Peter Griffin, robh+dt, krzysztof.kozlowski+dt, mturquette,
conor+dt, sboyd, tomasz.figa, s.nawrocki, linus.walleij, wim,
linux, catalin.marinas, will, arnd, olof, cw00.choi,
tudor.ambarus, andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog, kernel-team
On 05/10/2023 20:05, Greg KH wrote:
> On Thu, Oct 05, 2023 at 10:59:12AM -0700, William McVicker wrote:
>> On 10/05/2023, Peter Griffin wrote:
>>> Google gs101 SoC is ARMv8 mobile SoC found in the Pixel 6,
>>> (oriole) Pixel 6a (bluejay) and Pixel 6 pro (raven) mobile
>>> phones. It features:
>>> * 4xA55 little cluster
>>> * 2xA76 Mid cluster
>>> * 2xX1 Big cluster
>>>
>>> This commit adds the basic device tree for gs101 (SoC) and oriole
>>> (pixel 6). Further platform support will be added over time.
>>>
>>> It has been tested with a minimal busybox initramfs and boots to
>>> a shell.
>>>
>>> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
>>> ---
>>> arch/arm64/Kconfig.platforms | 6 +
>>> arch/arm64/boot/dts/Makefile | 1 +
>>> arch/arm64/boot/dts/google/Makefile | 6 +
>>> arch/arm64/boot/dts/google/gs101-oriole.dts | 68 +
>>> arch/arm64/boot/dts/google/gs101-pinctrl.dtsi | 1134 +++++++++++++++++
>>> arch/arm64/boot/dts/google/gs101-pinctrl.h | 17 +
>>> arch/arm64/boot/dts/google/gs101.dtsi | 501 ++++++++
>>> 7 files changed, 1733 insertions(+)
>>> create mode 100644 arch/arm64/boot/dts/google/Makefile
>>> create mode 100644 arch/arm64/boot/dts/google/gs101-oriole.dts
>>> create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.dtsi
>>> create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.h
>>> create mode 100644 arch/arm64/boot/dts/google/gs101.dtsi
>>>
>>> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
>>> index 6069120199bb..a5ed1b719488 100644
>>> --- a/arch/arm64/Kconfig.platforms
>>> +++ b/arch/arm64/Kconfig.platforms
>>> @@ -107,6 +107,12 @@ config ARCH_EXYNOS
>>> help
>>> This enables support for ARMv8 based Samsung Exynos SoC family.
>>>
>>> +config ARCH_GOOGLE_TENSOR
>>> + bool "Google Tensor SoC fmaily"
>>> + depends on ARCH_EXYNOS
>>> + help
>>> + Support for ARMv8 based Google Tensor platforms.
>>
>> I'd like to bring up this thread and discuss the option of not introducing
>> another ARCH_* config:
>>
>> https://lore.kernel.org/all/20200306103652.GA3634389@kroah.com/
>
> I agree, PLEASE don't add platform config options as that makes it
> impossible to make a unified kernel image that works for more than one
> platform at the same time.
There is no single problem in making unified image as we were doing
since beginning of ARM64. The ARCH_* is not a obstacle for this.
>
>> I especially don't like the "depends on ARCH_EXYNOS" because that forces one to
>> include all the other Exynos drivers that ARCH_EXYNOS selects that Google
>> Tensor SoCs don't need. Can we consider using SOC_GOOGLE instead and for all
>> drivers that actually depend on the SoC hardware, we can just add "depends on
>> SOC_GOOGLE"?
>
> Why do any of this at all? It should not be needed.
>
>> The idea is that drivers should be tied to hardware -- not a specific vendor.
>
> And drivers should be auto-loaded.
>
> All of these drivers are not vendor-specific at all, they are based on
> the same IP blocks as others, so that is how they should be unified.
They are vendor specific. All of them are specifically for Exynos
hardwre, because this is Exynos. We call it Google GS/Tensor SoC just
for fancy convenience, but this just Exynos.
>
>> By making drivers depend on ARCH_*, you are introducing an arbitrary vendor
>> dependency and not a hardware dependency.
>
> Totally agree, thanks for bringing this up.
>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 18/21] arm64: dts: google: Add initial Google gs101 SoC support
@ 2023-10-05 19:18 ` Krzysztof Kozlowski
0 siblings, 0 replies; 150+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-05 19:18 UTC (permalink / raw)
To: Greg KH, William McVicker
Cc: Peter Griffin, robh+dt, krzysztof.kozlowski+dt, mturquette,
conor+dt, sboyd, tomasz.figa, s.nawrocki, linus.walleij, wim,
linux, catalin.marinas, will, arnd, olof, cw00.choi,
tudor.ambarus, andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog, kernel-team
On 05/10/2023 20:05, Greg KH wrote:
> On Thu, Oct 05, 2023 at 10:59:12AM -0700, William McVicker wrote:
>> On 10/05/2023, Peter Griffin wrote:
>>> Google gs101 SoC is ARMv8 mobile SoC found in the Pixel 6,
>>> (oriole) Pixel 6a (bluejay) and Pixel 6 pro (raven) mobile
>>> phones. It features:
>>> * 4xA55 little cluster
>>> * 2xA76 Mid cluster
>>> * 2xX1 Big cluster
>>>
>>> This commit adds the basic device tree for gs101 (SoC) and oriole
>>> (pixel 6). Further platform support will be added over time.
>>>
>>> It has been tested with a minimal busybox initramfs and boots to
>>> a shell.
>>>
>>> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
>>> ---
>>> arch/arm64/Kconfig.platforms | 6 +
>>> arch/arm64/boot/dts/Makefile | 1 +
>>> arch/arm64/boot/dts/google/Makefile | 6 +
>>> arch/arm64/boot/dts/google/gs101-oriole.dts | 68 +
>>> arch/arm64/boot/dts/google/gs101-pinctrl.dtsi | 1134 +++++++++++++++++
>>> arch/arm64/boot/dts/google/gs101-pinctrl.h | 17 +
>>> arch/arm64/boot/dts/google/gs101.dtsi | 501 ++++++++
>>> 7 files changed, 1733 insertions(+)
>>> create mode 100644 arch/arm64/boot/dts/google/Makefile
>>> create mode 100644 arch/arm64/boot/dts/google/gs101-oriole.dts
>>> create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.dtsi
>>> create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.h
>>> create mode 100644 arch/arm64/boot/dts/google/gs101.dtsi
>>>
>>> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
>>> index 6069120199bb..a5ed1b719488 100644
>>> --- a/arch/arm64/Kconfig.platforms
>>> +++ b/arch/arm64/Kconfig.platforms
>>> @@ -107,6 +107,12 @@ config ARCH_EXYNOS
>>> help
>>> This enables support for ARMv8 based Samsung Exynos SoC family.
>>>
>>> +config ARCH_GOOGLE_TENSOR
>>> + bool "Google Tensor SoC fmaily"
>>> + depends on ARCH_EXYNOS
>>> + help
>>> + Support for ARMv8 based Google Tensor platforms.
>>
>> I'd like to bring up this thread and discuss the option of not introducing
>> another ARCH_* config:
>>
>> https://lore.kernel.org/all/20200306103652.GA3634389@kroah.com/
>
> I agree, PLEASE don't add platform config options as that makes it
> impossible to make a unified kernel image that works for more than one
> platform at the same time.
There is no single problem in making unified image as we were doing
since beginning of ARM64. The ARCH_* is not a obstacle for this.
>
>> I especially don't like the "depends on ARCH_EXYNOS" because that forces one to
>> include all the other Exynos drivers that ARCH_EXYNOS selects that Google
>> Tensor SoCs don't need. Can we consider using SOC_GOOGLE instead and for all
>> drivers that actually depend on the SoC hardware, we can just add "depends on
>> SOC_GOOGLE"?
>
> Why do any of this at all? It should not be needed.
>
>> The idea is that drivers should be tied to hardware -- not a specific vendor.
>
> And drivers should be auto-loaded.
>
> All of these drivers are not vendor-specific at all, they are based on
> the same IP blocks as others, so that is how they should be unified.
They are vendor specific. All of them are specifically for Exynos
hardwre, because this is Exynos. We call it Google GS/Tensor SoC just
for fancy convenience, but this just Exynos.
>
>> By making drivers depend on ARCH_*, you are introducing an arbitrary vendor
>> dependency and not a hardware dependency.
>
> Totally agree, thanks for bringing this up.
>
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 18/21] arm64: dts: google: Add initial Google gs101 SoC support
2023-10-05 19:18 ` Krzysztof Kozlowski
@ 2023-10-05 19:23 ` Greg KH
-1 siblings, 0 replies; 150+ messages in thread
From: Greg KH @ 2023-10-05 19:23 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: William McVicker, Peter Griffin, robh+dt, krzysztof.kozlowski+dt,
mturquette, conor+dt, sboyd, tomasz.figa, s.nawrocki,
linus.walleij, wim, linux, catalin.marinas, will, arnd, olof,
cw00.choi, tudor.ambarus, andre.draszik, semen.protsenko, soc,
devicetree, linux-arm-kernel, linux-samsung-soc, linux-clk,
linux-gpio, linux-watchdog, kernel-team
On Thu, Oct 05, 2023 at 09:18:48PM +0200, Krzysztof Kozlowski wrote:
> >> I'd like to bring up this thread and discuss the option of not introducing
> >> another ARCH_* config:
> >>
> >> https://lore.kernel.org/all/20200306103652.GA3634389@kroah.com/
> >
> > I agree, PLEASE don't add platform config options as that makes it
> > impossible to make a unified kernel image that works for more than one
> > platform at the same time.
>
> There is no single problem in making unified image as we were doing
> since beginning of ARM64. The ARCH_* is not a obstacle for this.
Then why are the ARCH_* options needed at all? What does this help out
with?
> >> I especially don't like the "depends on ARCH_EXYNOS" because that forces one to
> >> include all the other Exynos drivers that ARCH_EXYNOS selects that Google
> >> Tensor SoCs don't need. Can we consider using SOC_GOOGLE instead and for all
> >> drivers that actually depend on the SoC hardware, we can just add "depends on
> >> SOC_GOOGLE"?
> >
> > Why do any of this at all? It should not be needed.
> >
> >> The idea is that drivers should be tied to hardware -- not a specific vendor.
> >
> > And drivers should be auto-loaded.
> >
> > All of these drivers are not vendor-specific at all, they are based on
> > the same IP blocks as others, so that is how they should be unified.
>
> They are vendor specific. All of them are specifically for Exynos
> hardwre, because this is Exynos. We call it Google GS/Tensor SoC just
> for fancy convenience, but this just Exynos.
Ok, then why is this ARCH_ option needed if these IP blocks really are
from something else and are part of other drivers?
confused,
greg k-h
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 18/21] arm64: dts: google: Add initial Google gs101 SoC support
@ 2023-10-05 19:23 ` Greg KH
0 siblings, 0 replies; 150+ messages in thread
From: Greg KH @ 2023-10-05 19:23 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: William McVicker, Peter Griffin, robh+dt, krzysztof.kozlowski+dt,
mturquette, conor+dt, sboyd, tomasz.figa, s.nawrocki,
linus.walleij, wim, linux, catalin.marinas, will, arnd, olof,
cw00.choi, tudor.ambarus, andre.draszik, semen.protsenko, soc,
devicetree, linux-arm-kernel, linux-samsung-soc, linux-clk,
linux-gpio, linux-watchdog, kernel-team
On Thu, Oct 05, 2023 at 09:18:48PM +0200, Krzysztof Kozlowski wrote:
> >> I'd like to bring up this thread and discuss the option of not introducing
> >> another ARCH_* config:
> >>
> >> https://lore.kernel.org/all/20200306103652.GA3634389@kroah.com/
> >
> > I agree, PLEASE don't add platform config options as that makes it
> > impossible to make a unified kernel image that works for more than one
> > platform at the same time.
>
> There is no single problem in making unified image as we were doing
> since beginning of ARM64. The ARCH_* is not a obstacle for this.
Then why are the ARCH_* options needed at all? What does this help out
with?
> >> I especially don't like the "depends on ARCH_EXYNOS" because that forces one to
> >> include all the other Exynos drivers that ARCH_EXYNOS selects that Google
> >> Tensor SoCs don't need. Can we consider using SOC_GOOGLE instead and for all
> >> drivers that actually depend on the SoC hardware, we can just add "depends on
> >> SOC_GOOGLE"?
> >
> > Why do any of this at all? It should not be needed.
> >
> >> The idea is that drivers should be tied to hardware -- not a specific vendor.
> >
> > And drivers should be auto-loaded.
> >
> > All of these drivers are not vendor-specific at all, they are based on
> > the same IP blocks as others, so that is how they should be unified.
>
> They are vendor specific. All of them are specifically for Exynos
> hardwre, because this is Exynos. We call it Google GS/Tensor SoC just
> for fancy convenience, but this just Exynos.
Ok, then why is this ARCH_ option needed if these IP blocks really are
from something else and are part of other drivers?
confused,
greg k-h
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 18/21] arm64: dts: google: Add initial Google gs101 SoC support
2023-10-05 19:23 ` Greg KH
@ 2023-10-05 19:29 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 150+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-05 19:29 UTC (permalink / raw)
To: Greg KH
Cc: William McVicker, Peter Griffin, robh+dt, krzysztof.kozlowski+dt,
mturquette, conor+dt, sboyd, tomasz.figa, s.nawrocki,
linus.walleij, wim, linux, catalin.marinas, will, arnd, olof,
cw00.choi, tudor.ambarus, andre.draszik, semen.protsenko, soc,
devicetree, linux-arm-kernel, linux-samsung-soc, linux-clk,
linux-gpio, linux-watchdog, kernel-team
On 05/10/2023 21:23, Greg KH wrote:
> On Thu, Oct 05, 2023 at 09:18:48PM +0200, Krzysztof Kozlowski wrote:
>>>> I'd like to bring up this thread and discuss the option of not introducing
>>>> another ARCH_* config:
>>>>
>>>> https://lore.kernel.org/all/20200306103652.GA3634389@kroah.com/
>>>
>>> I agree, PLEASE don't add platform config options as that makes it
>>> impossible to make a unified kernel image that works for more than one
>>> platform at the same time.
>>
>> There is no single problem in making unified image as we were doing
>> since beginning of ARM64. The ARCH_* is not a obstacle for this.
>
> Then why are the ARCH_* options needed at all? What does this help out
> with?
It helps all the people and distros who do not want to build/package
drivers or modules for unrelated hardware or architectures.
Let's take Samsung Exynos UART driver. It will never, 100% never, work
on x86, x86_64. There is no single need to package it for kernels build
for these products. It will not work on nVidia Tegra ARM64, Qualcomm
ARM64 SoC, so if you do not want to run on Exynos, then you do no select
ARCH_EXYNOS and have significantly smaller image.
Now, there is no problem to have one kernel for nVidia Tegra + Qualcomm
+ Samsung Exynos with everything you need. The ARCH_EXYNOS or SOC_EXYNOS
or SOC_GOOGLE serves only the purpose to allow distros and people
customize build for specific hardware.
It does not limit anyone on anything.
>
>>>> I especially don't like the "depends on ARCH_EXYNOS" because that forces one to
>>>> include all the other Exynos drivers that ARCH_EXYNOS selects that Google
>>>> Tensor SoCs don't need. Can we consider using SOC_GOOGLE instead and for all
>>>> drivers that actually depend on the SoC hardware, we can just add "depends on
>>>> SOC_GOOGLE"?
>>>
>>> Why do any of this at all? It should not be needed.
>>>
>>>> The idea is that drivers should be tied to hardware -- not a specific vendor.
>>>
>>> And drivers should be auto-loaded.
>>>
>>> All of these drivers are not vendor-specific at all, they are based on
>>> the same IP blocks as others, so that is how they should be unified.
>>
>> They are vendor specific. All of them are specifically for Exynos
>> hardwre, because this is Exynos. We call it Google GS/Tensor SoC just
>> for fancy convenience, but this just Exynos.
>
> Ok, then why is this ARCH_ option needed if these IP blocks really are
> from something else and are part of other drivers?
For the same reason above, because if I want to build kernel for
Qualcomm, I want to drop easily anything not related. If I want to build
kernel without I2C, I disable I2C bus which effectively disables all
drivers which work on I2C. If I want to build kernel without Exynos, I
disable ARCH_EXYNOS which effectively disables entire Exynos hardware.
Think of SoC as a bus or interface.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 18/21] arm64: dts: google: Add initial Google gs101 SoC support
@ 2023-10-05 19:29 ` Krzysztof Kozlowski
0 siblings, 0 replies; 150+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-05 19:29 UTC (permalink / raw)
To: Greg KH
Cc: William McVicker, Peter Griffin, robh+dt, krzysztof.kozlowski+dt,
mturquette, conor+dt, sboyd, tomasz.figa, s.nawrocki,
linus.walleij, wim, linux, catalin.marinas, will, arnd, olof,
cw00.choi, tudor.ambarus, andre.draszik, semen.protsenko, soc,
devicetree, linux-arm-kernel, linux-samsung-soc, linux-clk,
linux-gpio, linux-watchdog, kernel-team
On 05/10/2023 21:23, Greg KH wrote:
> On Thu, Oct 05, 2023 at 09:18:48PM +0200, Krzysztof Kozlowski wrote:
>>>> I'd like to bring up this thread and discuss the option of not introducing
>>>> another ARCH_* config:
>>>>
>>>> https://lore.kernel.org/all/20200306103652.GA3634389@kroah.com/
>>>
>>> I agree, PLEASE don't add platform config options as that makes it
>>> impossible to make a unified kernel image that works for more than one
>>> platform at the same time.
>>
>> There is no single problem in making unified image as we were doing
>> since beginning of ARM64. The ARCH_* is not a obstacle for this.
>
> Then why are the ARCH_* options needed at all? What does this help out
> with?
It helps all the people and distros who do not want to build/package
drivers or modules for unrelated hardware or architectures.
Let's take Samsung Exynos UART driver. It will never, 100% never, work
on x86, x86_64. There is no single need to package it for kernels build
for these products. It will not work on nVidia Tegra ARM64, Qualcomm
ARM64 SoC, so if you do not want to run on Exynos, then you do no select
ARCH_EXYNOS and have significantly smaller image.
Now, there is no problem to have one kernel for nVidia Tegra + Qualcomm
+ Samsung Exynos with everything you need. The ARCH_EXYNOS or SOC_EXYNOS
or SOC_GOOGLE serves only the purpose to allow distros and people
customize build for specific hardware.
It does not limit anyone on anything.
>
>>>> I especially don't like the "depends on ARCH_EXYNOS" because that forces one to
>>>> include all the other Exynos drivers that ARCH_EXYNOS selects that Google
>>>> Tensor SoCs don't need. Can we consider using SOC_GOOGLE instead and for all
>>>> drivers that actually depend on the SoC hardware, we can just add "depends on
>>>> SOC_GOOGLE"?
>>>
>>> Why do any of this at all? It should not be needed.
>>>
>>>> The idea is that drivers should be tied to hardware -- not a specific vendor.
>>>
>>> And drivers should be auto-loaded.
>>>
>>> All of these drivers are not vendor-specific at all, they are based on
>>> the same IP blocks as others, so that is how they should be unified.
>>
>> They are vendor specific. All of them are specifically for Exynos
>> hardwre, because this is Exynos. We call it Google GS/Tensor SoC just
>> for fancy convenience, but this just Exynos.
>
> Ok, then why is this ARCH_ option needed if these IP blocks really are
> from something else and are part of other drivers?
For the same reason above, because if I want to build kernel for
Qualcomm, I want to drop easily anything not related. If I want to build
kernel without I2C, I disable I2C bus which effectively disables all
drivers which work on I2C. If I want to build kernel without Exynos, I
disable ARCH_EXYNOS which effectively disables entire Exynos hardware.
Think of SoC as a bus or interface.
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 18/21] arm64: dts: google: Add initial Google gs101 SoC support
2023-10-05 19:29 ` Krzysztof Kozlowski
@ 2023-10-05 23:19 ` William McVicker
-1 siblings, 0 replies; 150+ messages in thread
From: William McVicker @ 2023-10-05 23:19 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Greg KH, Peter Griffin, robh+dt, krzysztof.kozlowski+dt,
mturquette, conor+dt, sboyd, tomasz.figa, s.nawrocki,
linus.walleij, wim, linux, catalin.marinas, will, arnd, olof,
cw00.choi, tudor.ambarus, andre.draszik, semen.protsenko, soc,
devicetree, linux-arm-kernel, linux-samsung-soc, linux-clk,
linux-gpio, linux-watchdog, kernel-team
On 10/05/2023, Krzysztof Kozlowski wrote:
> On 05/10/2023 21:23, Greg KH wrote:
> > On Thu, Oct 05, 2023 at 09:18:48PM +0200, Krzysztof Kozlowski wrote:
> >>>> I'd like to bring up this thread and discuss the option of not introducing
> >>>> another ARCH_* config:
> >>>>
> >>>> https://lore.kernel.org/all/20200306103652.GA3634389@kroah.com/
> >>>
> >>> I agree, PLEASE don't add platform config options as that makes it
> >>> impossible to make a unified kernel image that works for more than one
> >>> platform at the same time.
> >>
> >> There is no single problem in making unified image as we were doing
> >> since beginning of ARM64. The ARCH_* is not a obstacle for this.
> >
> > Then why are the ARCH_* options needed at all? What does this help out
> > with?
>
> It helps all the people and distros who do not want to build/package
> drivers or modules for unrelated hardware or architectures.
>
> Let's take Samsung Exynos UART driver. It will never, 100% never, work
> on x86, x86_64. There is no single need to package it for kernels build
> for these products. It will not work on nVidia Tegra ARM64, Qualcomm
> ARM64 SoC, so if you do not want to run on Exynos, then you do no select
> ARCH_EXYNOS and have significantly smaller image.
>
> Now, there is no problem to have one kernel for nVidia Tegra + Qualcomm
> + Samsung Exynos with everything you need. The ARCH_EXYNOS or SOC_EXYNOS
> or SOC_GOOGLE serves only the purpose to allow distros and people
> customize build for specific hardware.
>
> It does not limit anyone on anything.
I'm glad you brought up Exynos UART because this is where one of the
limitations is introduced. For example, if you want to modularize out all the
vendor specific drivers from the core kernel to create a common arm64 kernel
binary that works on all ARM64 devices, you will not be able to build in the
early console UART drivers without enabling the respective ARCH_* configs.
Being able to include SERIAL_SAMSUNG and SERIAL_MSM without all the vendor
specific drivers that ARCH_EXYNOS and ARCH_QCOM select is very valuable for
debugging early boot issues.
I understand that ARCH_* configs are used to selectively pick which device tree
blobs are built, but forcing developers to pick all or nothing is where I have
a problem.
Regards,
Will
>
>
>
> >
> >>>> I especially don't like the "depends on ARCH_EXYNOS" because that forces one to
> >>>> include all the other Exynos drivers that ARCH_EXYNOS selects that Google
> >>>> Tensor SoCs don't need. Can we consider using SOC_GOOGLE instead and for all
> >>>> drivers that actually depend on the SoC hardware, we can just add "depends on
> >>>> SOC_GOOGLE"?
> >>>
> >>> Why do any of this at all? It should not be needed.
> >>>
> >>>> The idea is that drivers should be tied to hardware -- not a specific vendor.
> >>>
> >>> And drivers should be auto-loaded.
> >>>
> >>> All of these drivers are not vendor-specific at all, they are based on
> >>> the same IP blocks as others, so that is how they should be unified.
> >>
> >> They are vendor specific. All of them are specifically for Exynos
> >> hardwre, because this is Exynos. We call it Google GS/Tensor SoC just
> >> for fancy convenience, but this just Exynos.
> >
> > Ok, then why is this ARCH_ option needed if these IP blocks really are
> > from something else and are part of other drivers?
>
> For the same reason above, because if I want to build kernel for
> Qualcomm, I want to drop easily anything not related. If I want to build
> kernel without I2C, I disable I2C bus which effectively disables all
> drivers which work on I2C. If I want to build kernel without Exynos, I
> disable ARCH_EXYNOS which effectively disables entire Exynos hardware.
>
> Think of SoC as a bus or interface.
>
> Best regards,
> Krzysztof
>
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 18/21] arm64: dts: google: Add initial Google gs101 SoC support
@ 2023-10-05 23:19 ` William McVicker
0 siblings, 0 replies; 150+ messages in thread
From: William McVicker @ 2023-10-05 23:19 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Greg KH, Peter Griffin, robh+dt, krzysztof.kozlowski+dt,
mturquette, conor+dt, sboyd, tomasz.figa, s.nawrocki,
linus.walleij, wim, linux, catalin.marinas, will, arnd, olof,
cw00.choi, tudor.ambarus, andre.draszik, semen.protsenko, soc,
devicetree, linux-arm-kernel, linux-samsung-soc, linux-clk,
linux-gpio, linux-watchdog, kernel-team
On 10/05/2023, Krzysztof Kozlowski wrote:
> On 05/10/2023 21:23, Greg KH wrote:
> > On Thu, Oct 05, 2023 at 09:18:48PM +0200, Krzysztof Kozlowski wrote:
> >>>> I'd like to bring up this thread and discuss the option of not introducing
> >>>> another ARCH_* config:
> >>>>
> >>>> https://lore.kernel.org/all/20200306103652.GA3634389@kroah.com/
> >>>
> >>> I agree, PLEASE don't add platform config options as that makes it
> >>> impossible to make a unified kernel image that works for more than one
> >>> platform at the same time.
> >>
> >> There is no single problem in making unified image as we were doing
> >> since beginning of ARM64. The ARCH_* is not a obstacle for this.
> >
> > Then why are the ARCH_* options needed at all? What does this help out
> > with?
>
> It helps all the people and distros who do not want to build/package
> drivers or modules for unrelated hardware or architectures.
>
> Let's take Samsung Exynos UART driver. It will never, 100% never, work
> on x86, x86_64. There is no single need to package it for kernels build
> for these products. It will not work on nVidia Tegra ARM64, Qualcomm
> ARM64 SoC, so if you do not want to run on Exynos, then you do no select
> ARCH_EXYNOS and have significantly smaller image.
>
> Now, there is no problem to have one kernel for nVidia Tegra + Qualcomm
> + Samsung Exynos with everything you need. The ARCH_EXYNOS or SOC_EXYNOS
> or SOC_GOOGLE serves only the purpose to allow distros and people
> customize build for specific hardware.
>
> It does not limit anyone on anything.
I'm glad you brought up Exynos UART because this is where one of the
limitations is introduced. For example, if you want to modularize out all the
vendor specific drivers from the core kernel to create a common arm64 kernel
binary that works on all ARM64 devices, you will not be able to build in the
early console UART drivers without enabling the respective ARCH_* configs.
Being able to include SERIAL_SAMSUNG and SERIAL_MSM without all the vendor
specific drivers that ARCH_EXYNOS and ARCH_QCOM select is very valuable for
debugging early boot issues.
I understand that ARCH_* configs are used to selectively pick which device tree
blobs are built, but forcing developers to pick all or nothing is where I have
a problem.
Regards,
Will
>
>
>
> >
> >>>> I especially don't like the "depends on ARCH_EXYNOS" because that forces one to
> >>>> include all the other Exynos drivers that ARCH_EXYNOS selects that Google
> >>>> Tensor SoCs don't need. Can we consider using SOC_GOOGLE instead and for all
> >>>> drivers that actually depend on the SoC hardware, we can just add "depends on
> >>>> SOC_GOOGLE"?
> >>>
> >>> Why do any of this at all? It should not be needed.
> >>>
> >>>> The idea is that drivers should be tied to hardware -- not a specific vendor.
> >>>
> >>> And drivers should be auto-loaded.
> >>>
> >>> All of these drivers are not vendor-specific at all, they are based on
> >>> the same IP blocks as others, so that is how they should be unified.
> >>
> >> They are vendor specific. All of them are specifically for Exynos
> >> hardwre, because this is Exynos. We call it Google GS/Tensor SoC just
> >> for fancy convenience, but this just Exynos.
> >
> > Ok, then why is this ARCH_ option needed if these IP blocks really are
> > from something else and are part of other drivers?
>
> For the same reason above, because if I want to build kernel for
> Qualcomm, I want to drop easily anything not related. If I want to build
> kernel without I2C, I disable I2C bus which effectively disables all
> drivers which work on I2C. If I want to build kernel without Exynos, I
> disable ARCH_EXYNOS which effectively disables entire Exynos hardware.
>
> Think of SoC as a bus or interface.
>
> Best regards,
> Krzysztof
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 18/21] arm64: dts: google: Add initial Google gs101 SoC support
2023-10-05 23:19 ` William McVicker
@ 2023-10-06 6:06 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 150+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-06 6:06 UTC (permalink / raw)
To: William McVicker
Cc: Greg KH, Peter Griffin, robh+dt, krzysztof.kozlowski+dt,
mturquette, conor+dt, sboyd, tomasz.figa, s.nawrocki,
linus.walleij, wim, linux, catalin.marinas, will, arnd, olof,
cw00.choi, tudor.ambarus, andre.draszik, semen.protsenko, soc,
devicetree, linux-arm-kernel, linux-samsung-soc, linux-clk,
linux-gpio, linux-watchdog, kernel-team
On 06/10/2023 01:19, William McVicker wrote:
> On 10/05/2023, Krzysztof Kozlowski wrote:
>> On 05/10/2023 21:23, Greg KH wrote:
>>> On Thu, Oct 05, 2023 at 09:18:48PM +0200, Krzysztof Kozlowski wrote:
>>>>>> I'd like to bring up this thread and discuss the option of not introducing
>>>>>> another ARCH_* config:
>>>>>>
>>>>>> https://lore.kernel.org/all/20200306103652.GA3634389@kroah.com/
>>>>>
>>>>> I agree, PLEASE don't add platform config options as that makes it
>>>>> impossible to make a unified kernel image that works for more than one
>>>>> platform at the same time.
>>>>
>>>> There is no single problem in making unified image as we were doing
>>>> since beginning of ARM64. The ARCH_* is not a obstacle for this.
>>>
>>> Then why are the ARCH_* options needed at all? What does this help out
>>> with?
>>
>> It helps all the people and distros who do not want to build/package
>> drivers or modules for unrelated hardware or architectures.
>>
>> Let's take Samsung Exynos UART driver. It will never, 100% never, work
>> on x86, x86_64. There is no single need to package it for kernels build
>> for these products. It will not work on nVidia Tegra ARM64, Qualcomm
>> ARM64 SoC, so if you do not want to run on Exynos, then you do no select
>> ARCH_EXYNOS and have significantly smaller image.
>>
>> Now, there is no problem to have one kernel for nVidia Tegra + Qualcomm
>> + Samsung Exynos with everything you need. The ARCH_EXYNOS or SOC_EXYNOS
>> or SOC_GOOGLE serves only the purpose to allow distros and people
>> customize build for specific hardware.
>>
>> It does not limit anyone on anything.
>
> I'm glad you brought up Exynos UART because this is where one of the
> limitations is introduced. For example, if you want to modularize out all the
> vendor specific drivers from the core kernel to create a common arm64 kernel
> binary that works on all ARM64 devices, you will not be able to build in the
> early console UART drivers without enabling the respective ARCH_* configs.
When you build single kernel there is never need to NOT ENABLE
respective ARCH configs. Please describe me upstream case for such need
to NOT ENABLE.
> Being able to include SERIAL_SAMSUNG and SERIAL_MSM without all the vendor> specific drivers that ARCH_EXYNOS and ARCH_QCOM select is very
valuable for
> debugging early boot issues.
Really? How related? The drivers are independent. You describe some
out-of-tree development process which we never needed for upstream work.
And we did here quite a lot of upstream, specially if you look at ARCH_QCOM.
>
> I understand that ARCH_* configs are used to selectively pick which device tree
> blobs are built, but forcing developers to pick all or nothing is where I have
> a problem.
No one forces you to pick up everything or nothing. You select
ARCH_EXYNOS and still can drop all optional drivers. It's true you
cannot drop mandatory drivers, but you are upstreaming Exynos platform,
right? We do not talk about your out-of-tree Google work because it does
not matter.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 18/21] arm64: dts: google: Add initial Google gs101 SoC support
@ 2023-10-06 6:06 ` Krzysztof Kozlowski
0 siblings, 0 replies; 150+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-06 6:06 UTC (permalink / raw)
To: William McVicker
Cc: Greg KH, Peter Griffin, robh+dt, krzysztof.kozlowski+dt,
mturquette, conor+dt, sboyd, tomasz.figa, s.nawrocki,
linus.walleij, wim, linux, catalin.marinas, will, arnd, olof,
cw00.choi, tudor.ambarus, andre.draszik, semen.protsenko, soc,
devicetree, linux-arm-kernel, linux-samsung-soc, linux-clk,
linux-gpio, linux-watchdog, kernel-team
On 06/10/2023 01:19, William McVicker wrote:
> On 10/05/2023, Krzysztof Kozlowski wrote:
>> On 05/10/2023 21:23, Greg KH wrote:
>>> On Thu, Oct 05, 2023 at 09:18:48PM +0200, Krzysztof Kozlowski wrote:
>>>>>> I'd like to bring up this thread and discuss the option of not introducing
>>>>>> another ARCH_* config:
>>>>>>
>>>>>> https://lore.kernel.org/all/20200306103652.GA3634389@kroah.com/
>>>>>
>>>>> I agree, PLEASE don't add platform config options as that makes it
>>>>> impossible to make a unified kernel image that works for more than one
>>>>> platform at the same time.
>>>>
>>>> There is no single problem in making unified image as we were doing
>>>> since beginning of ARM64. The ARCH_* is not a obstacle for this.
>>>
>>> Then why are the ARCH_* options needed at all? What does this help out
>>> with?
>>
>> It helps all the people and distros who do not want to build/package
>> drivers or modules for unrelated hardware or architectures.
>>
>> Let's take Samsung Exynos UART driver. It will never, 100% never, work
>> on x86, x86_64. There is no single need to package it for kernels build
>> for these products. It will not work on nVidia Tegra ARM64, Qualcomm
>> ARM64 SoC, so if you do not want to run on Exynos, then you do no select
>> ARCH_EXYNOS and have significantly smaller image.
>>
>> Now, there is no problem to have one kernel for nVidia Tegra + Qualcomm
>> + Samsung Exynos with everything you need. The ARCH_EXYNOS or SOC_EXYNOS
>> or SOC_GOOGLE serves only the purpose to allow distros and people
>> customize build for specific hardware.
>>
>> It does not limit anyone on anything.
>
> I'm glad you brought up Exynos UART because this is where one of the
> limitations is introduced. For example, if you want to modularize out all the
> vendor specific drivers from the core kernel to create a common arm64 kernel
> binary that works on all ARM64 devices, you will not be able to build in the
> early console UART drivers without enabling the respective ARCH_* configs.
When you build single kernel there is never need to NOT ENABLE
respective ARCH configs. Please describe me upstream case for such need
to NOT ENABLE.
> Being able to include SERIAL_SAMSUNG and SERIAL_MSM without all the vendor> specific drivers that ARCH_EXYNOS and ARCH_QCOM select is very
valuable for
> debugging early boot issues.
Really? How related? The drivers are independent. You describe some
out-of-tree development process which we never needed for upstream work.
And we did here quite a lot of upstream, specially if you look at ARCH_QCOM.
>
> I understand that ARCH_* configs are used to selectively pick which device tree
> blobs are built, but forcing developers to pick all or nothing is where I have
> a problem.
No one forces you to pick up everything or nothing. You select
ARCH_EXYNOS and still can drop all optional drivers. It's true you
cannot drop mandatory drivers, but you are upstreaming Exynos platform,
right? We do not talk about your out-of-tree Google work because it does
not matter.
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 18/21] arm64: dts: google: Add initial Google gs101 SoC support
2023-10-06 6:06 ` Krzysztof Kozlowski
@ 2023-10-06 8:48 ` Arnd Bergmann
-1 siblings, 0 replies; 150+ messages in thread
From: Arnd Bergmann @ 2023-10-06 8:48 UTC (permalink / raw)
To: Krzysztof Kozlowski, William McVicker
Cc: Greg Kroah-Hartman, Peter Griffin, Rob Herring,
krzysztof.kozlowski+dt, Michael Turquette, Conor Dooley,
Stephen Boyd, Tomasz Figa, Sylwester Nawrocki, Linus Walleij,
Wim Van Sebroeck, Guenter Roeck, Catalin Marinas, Will Deacon,
Olof Johansson, Chanwoo Choi, Tudor Ambarus, andre.draszik,
semen.protsenko, soc, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-clk, open list:GPIO SUBSYSTEM,
linux-watchdog, kernel-team
On Fri, Oct 6, 2023, at 08:06, Krzysztof Kozlowski wrote:
> On 06/10/2023 01:19, William McVicker wrote:
>> On 10/05/2023, Krzysztof Kozlowski wrote:
>>> On 05/10/2023 21:23, Greg KH wrote:
>>
>> Being able to include SERIAL_SAMSUNG and SERIAL_MSM without all the vendor> specific drivers that ARCH_EXYNOS and ARCH_QCOM select is very
> valuable for
>> debugging early boot issues.
>
> Really? How related? The drivers are independent. You describe some
> out-of-tree development process which we never needed for upstream work.
> And we did here quite a lot of upstream, specially if you look at ARCH_QCOM.
Right: in general, all drivers are independent of the platform
besides the typical 'depends on ARCH_FOO || COMPILE_TEST' dependency,
but I think it's worth mentioning the known exceptions, so Greg and
Will can take that fight to the respective places rather than
discussing it in the platform submission:
- Some subsystems are considered 'special' and the maintainers
prefer the drivers to be automatically selected based on the
ARCH_* settings instead of having user-visible options. This is
traditionally true for large chunks of drivers/irqchip,
drivers/clocksource and drivers/pinctrl, though it has gotten
better over time on all of them.
- Some older 32-bit platforms are still not as modular as we'd
like them to be, especially the StrongARM (ARMv4) platforms that
require a custom kernel build, and some of ARMv4T and ARMv5
boards that are still missing DT support. These tend to require
drivers they directly link to from board code, so disabling
the drivers would cause a link failure until this gets
cleaned up.
- A couple of drivers are force-enabled based on the ARCH_*
options because booting without these drivers would risk
permanent damage to hardware, e.g. in overtemp or overcurrent
scenarios.
- ACPI based platforms require the PCI host bridge driver to
be built-in rather than a loadable module because ACPI
needs to probe PCI devices during early boot.
- Some subsystems (notably drivers/gpu/, but others as well)
have an excessive number of 'select' statements, so you
end up surprise-enabling a number of additional drivers
and subsystems by enabling certain less important platform
specific drivers.
Arnd
^ permalink raw reply [flat|nested] 150+ messages in thread* Re: [PATCH 18/21] arm64: dts: google: Add initial Google gs101 SoC support
@ 2023-10-06 8:48 ` Arnd Bergmann
0 siblings, 0 replies; 150+ messages in thread
From: Arnd Bergmann @ 2023-10-06 8:48 UTC (permalink / raw)
To: Krzysztof Kozlowski, William McVicker
Cc: Greg Kroah-Hartman, Peter Griffin, Rob Herring,
krzysztof.kozlowski+dt, Michael Turquette, Conor Dooley,
Stephen Boyd, Tomasz Figa, Sylwester Nawrocki, Linus Walleij,
Wim Van Sebroeck, Guenter Roeck, Catalin Marinas, Will Deacon,
Olof Johansson, Chanwoo Choi, Tudor Ambarus, andre.draszik,
semen.protsenko, soc, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-clk, open list:GPIO SUBSYSTEM,
linux-watchdog, kernel-team
On Fri, Oct 6, 2023, at 08:06, Krzysztof Kozlowski wrote:
> On 06/10/2023 01:19, William McVicker wrote:
>> On 10/05/2023, Krzysztof Kozlowski wrote:
>>> On 05/10/2023 21:23, Greg KH wrote:
>>
>> Being able to include SERIAL_SAMSUNG and SERIAL_MSM without all the vendor> specific drivers that ARCH_EXYNOS and ARCH_QCOM select is very
> valuable for
>> debugging early boot issues.
>
> Really? How related? The drivers are independent. You describe some
> out-of-tree development process which we never needed for upstream work.
> And we did here quite a lot of upstream, specially if you look at ARCH_QCOM.
Right: in general, all drivers are independent of the platform
besides the typical 'depends on ARCH_FOO || COMPILE_TEST' dependency,
but I think it's worth mentioning the known exceptions, so Greg and
Will can take that fight to the respective places rather than
discussing it in the platform submission:
- Some subsystems are considered 'special' and the maintainers
prefer the drivers to be automatically selected based on the
ARCH_* settings instead of having user-visible options. This is
traditionally true for large chunks of drivers/irqchip,
drivers/clocksource and drivers/pinctrl, though it has gotten
better over time on all of them.
- Some older 32-bit platforms are still not as modular as we'd
like them to be, especially the StrongARM (ARMv4) platforms that
require a custom kernel build, and some of ARMv4T and ARMv5
boards that are still missing DT support. These tend to require
drivers they directly link to from board code, so disabling
the drivers would cause a link failure until this gets
cleaned up.
- A couple of drivers are force-enabled based on the ARCH_*
options because booting without these drivers would risk
permanent damage to hardware, e.g. in overtemp or overcurrent
scenarios.
- ACPI based platforms require the PCI host bridge driver to
be built-in rather than a loadable module because ACPI
needs to probe PCI devices during early boot.
- Some subsystems (notably drivers/gpu/, but others as well)
have an excessive number of 'select' statements, so you
end up surprise-enabling a number of additional drivers
and subsystems by enabling certain less important platform
specific drivers.
Arnd
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 150+ messages in thread* Re: [PATCH 18/21] arm64: dts: google: Add initial Google gs101 SoC support
2023-10-06 8:48 ` Arnd Bergmann
@ 2023-10-06 16:33 ` William McVicker
-1 siblings, 0 replies; 150+ messages in thread
From: William McVicker @ 2023-10-06 16:33 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Krzysztof Kozlowski, Greg Kroah-Hartman, Peter Griffin,
Rob Herring, krzysztof.kozlowski+dt, Michael Turquette,
Conor Dooley, Stephen Boyd, Tomasz Figa, Sylwester Nawrocki,
Linus Walleij, Wim Van Sebroeck, Guenter Roeck, Catalin Marinas,
Will Deacon, Olof Johansson, Chanwoo Choi, Tudor Ambarus,
andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk,
open list:GPIO SUBSYSTEM, linux-watchdog, kernel-team
On 10/06/2023, Arnd Bergmann wrote:
> On Fri, Oct 6, 2023, at 08:06, Krzysztof Kozlowski wrote:
> > On 06/10/2023 01:19, William McVicker wrote:
> >> On 10/05/2023, Krzysztof Kozlowski wrote:
> >>> On 05/10/2023 21:23, Greg KH wrote:
> >>
> >> Being able to include SERIAL_SAMSUNG and SERIAL_MSM without all the vendor> specific drivers that ARCH_EXYNOS and ARCH_QCOM select is very
> > valuable for
> >> debugging early boot issues.
> >
> > Really? How related? The drivers are independent. You describe some
> > out-of-tree development process which we never needed for upstream work.
> > And we did here quite a lot of upstream, specially if you look at ARCH_QCOM.
>
> Right: in general, all drivers are independent of the platform
> besides the typical 'depends on ARCH_FOO || COMPILE_TEST' dependency,
> but I think it's worth mentioning the known exceptions, so Greg and
> Will can take that fight to the respective places rather than
> discussing it in the platform submission:
>
> - Some subsystems are considered 'special' and the maintainers
> prefer the drivers to be automatically selected based on the
> ARCH_* settings instead of having user-visible options. This is
> traditionally true for large chunks of drivers/irqchip,
> drivers/clocksource and drivers/pinctrl, though it has gotten
> better over time on all of them.
>
> - Some older 32-bit platforms are still not as modular as we'd
> like them to be, especially the StrongARM (ARMv4) platforms that
> require a custom kernel build, and some of ARMv4T and ARMv5
> boards that are still missing DT support. These tend to require
> drivers they directly link to from board code, so disabling
> the drivers would cause a link failure until this gets
> cleaned up.
>
> - A couple of drivers are force-enabled based on the ARCH_*
> options because booting without these drivers would risk
> permanent damage to hardware, e.g. in overtemp or overcurrent
> scenarios.
>
> - ACPI based platforms require the PCI host bridge driver to
> be built-in rather than a loadable module because ACPI
> needs to probe PCI devices during early boot.
>
> - Some subsystems (notably drivers/gpu/, but others as well)
> have an excessive number of 'select' statements, so you
> end up surprise-enabling a number of additional drivers
> and subsystems by enabling certain less important platform
> specific drivers.
>
> Arnd
So if the argument is that the existing upstream Exynos platforms are required
to have these drivers built-in to the kernel to boot:
COMMON_CLK_SAMSUNG
CLKSRC_EXYNOS_MCT
EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS
EXYNOS_PMU
PINCTRL
PINCTRL_EXYNOS
PM_GENERIC_DOMAINS if PM
SOC_SAMSUNG
...then that is understandable and we can work to fix that.
My last question then is -- why do we need a new ARCH_GOOGLE_TENSOR config in
the platform Kconfig? For example, I don't really like this:
diff --git a/drivers/clk/samsung/Kconfig b/drivers/clk/samsung/Kconfig
index 76a494e95027..4c8f173c4dec 100644
--- a/drivers/clk/samsung/Kconfig
+++ b/drivers/clk/samsung/Kconfig
@@ -13,6 +13,7 @@ config COMMON_CLK_SAMSUNG
select EXYNOS_5420_COMMON_CLK if ARM && SOC_EXYNOS5420
select EXYNOS_ARM64_COMMON_CLK if ARM64 && ARCH_EXYNOS
select TESLA_FSD_COMMON_CLK if ARM64 && ARCH_TESLA_FSD
+ select GOOGLE_GS101_COMMON_CLK if ARM64 && ARCH_GOOGLE_TENSOR
What happens when we have GOOGLE_GS101_COMMON_CLK, GOOGLE_GS201_COMMON_CLK, and
so on? How are we going to pick the right driver when we have a generic
ARCH_GOOGLE_TENSOR config? Ideally, we should have one Exynos clock driver that
can detect what hardware is running (using the DT) to determine what it needs
to do. If you really want to compile out the other vendor's clock drivers using
some configs, then we should do that with SOC_GS101, SOC_GS201, SOC_TESLA_FSD
configs (not ideal though). With that approach, we could drop the platform
ARCH_GOOGLE_TENSOR config and create an SOC_GS101 config that can be used for
things like the COMMON_CLK_SAMSUNG driver (for now) and building the GS101 dtb.
Let me know your thoughts.
Thanks,
Will
^ permalink raw reply related [flat|nested] 150+ messages in thread* Re: [PATCH 18/21] arm64: dts: google: Add initial Google gs101 SoC support
@ 2023-10-06 16:33 ` William McVicker
0 siblings, 0 replies; 150+ messages in thread
From: William McVicker @ 2023-10-06 16:33 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Krzysztof Kozlowski, Greg Kroah-Hartman, Peter Griffin,
Rob Herring, krzysztof.kozlowski+dt, Michael Turquette,
Conor Dooley, Stephen Boyd, Tomasz Figa, Sylwester Nawrocki,
Linus Walleij, Wim Van Sebroeck, Guenter Roeck, Catalin Marinas,
Will Deacon, Olof Johansson, Chanwoo Choi, Tudor Ambarus,
andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk,
open list:GPIO SUBSYSTEM, linux-watchdog, kernel-team
On 10/06/2023, Arnd Bergmann wrote:
> On Fri, Oct 6, 2023, at 08:06, Krzysztof Kozlowski wrote:
> > On 06/10/2023 01:19, William McVicker wrote:
> >> On 10/05/2023, Krzysztof Kozlowski wrote:
> >>> On 05/10/2023 21:23, Greg KH wrote:
> >>
> >> Being able to include SERIAL_SAMSUNG and SERIAL_MSM without all the vendor> specific drivers that ARCH_EXYNOS and ARCH_QCOM select is very
> > valuable for
> >> debugging early boot issues.
> >
> > Really? How related? The drivers are independent. You describe some
> > out-of-tree development process which we never needed for upstream work.
> > And we did here quite a lot of upstream, specially if you look at ARCH_QCOM.
>
> Right: in general, all drivers are independent of the platform
> besides the typical 'depends on ARCH_FOO || COMPILE_TEST' dependency,
> but I think it's worth mentioning the known exceptions, so Greg and
> Will can take that fight to the respective places rather than
> discussing it in the platform submission:
>
> - Some subsystems are considered 'special' and the maintainers
> prefer the drivers to be automatically selected based on the
> ARCH_* settings instead of having user-visible options. This is
> traditionally true for large chunks of drivers/irqchip,
> drivers/clocksource and drivers/pinctrl, though it has gotten
> better over time on all of them.
>
> - Some older 32-bit platforms are still not as modular as we'd
> like them to be, especially the StrongARM (ARMv4) platforms that
> require a custom kernel build, and some of ARMv4T and ARMv5
> boards that are still missing DT support. These tend to require
> drivers they directly link to from board code, so disabling
> the drivers would cause a link failure until this gets
> cleaned up.
>
> - A couple of drivers are force-enabled based on the ARCH_*
> options because booting without these drivers would risk
> permanent damage to hardware, e.g. in overtemp or overcurrent
> scenarios.
>
> - ACPI based platforms require the PCI host bridge driver to
> be built-in rather than a loadable module because ACPI
> needs to probe PCI devices during early boot.
>
> - Some subsystems (notably drivers/gpu/, but others as well)
> have an excessive number of 'select' statements, so you
> end up surprise-enabling a number of additional drivers
> and subsystems by enabling certain less important platform
> specific drivers.
>
> Arnd
So if the argument is that the existing upstream Exynos platforms are required
to have these drivers built-in to the kernel to boot:
COMMON_CLK_SAMSUNG
CLKSRC_EXYNOS_MCT
EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS
EXYNOS_PMU
PINCTRL
PINCTRL_EXYNOS
PM_GENERIC_DOMAINS if PM
SOC_SAMSUNG
...then that is understandable and we can work to fix that.
My last question then is -- why do we need a new ARCH_GOOGLE_TENSOR config in
the platform Kconfig? For example, I don't really like this:
diff --git a/drivers/clk/samsung/Kconfig b/drivers/clk/samsung/Kconfig
index 76a494e95027..4c8f173c4dec 100644
--- a/drivers/clk/samsung/Kconfig
+++ b/drivers/clk/samsung/Kconfig
@@ -13,6 +13,7 @@ config COMMON_CLK_SAMSUNG
select EXYNOS_5420_COMMON_CLK if ARM && SOC_EXYNOS5420
select EXYNOS_ARM64_COMMON_CLK if ARM64 && ARCH_EXYNOS
select TESLA_FSD_COMMON_CLK if ARM64 && ARCH_TESLA_FSD
+ select GOOGLE_GS101_COMMON_CLK if ARM64 && ARCH_GOOGLE_TENSOR
What happens when we have GOOGLE_GS101_COMMON_CLK, GOOGLE_GS201_COMMON_CLK, and
so on? How are we going to pick the right driver when we have a generic
ARCH_GOOGLE_TENSOR config? Ideally, we should have one Exynos clock driver that
can detect what hardware is running (using the DT) to determine what it needs
to do. If you really want to compile out the other vendor's clock drivers using
some configs, then we should do that with SOC_GS101, SOC_GS201, SOC_TESLA_FSD
configs (not ideal though). With that approach, we could drop the platform
ARCH_GOOGLE_TENSOR config and create an SOC_GS101 config that can be used for
things like the COMMON_CLK_SAMSUNG driver (for now) and building the GS101 dtb.
Let me know your thoughts.
Thanks,
Will
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 150+ messages in thread* Re: [PATCH 18/21] arm64: dts: google: Add initial Google gs101 SoC support
2023-10-06 16:33 ` William McVicker
@ 2023-10-07 14:34 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 150+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-07 14:34 UTC (permalink / raw)
To: William McVicker, Arnd Bergmann
Cc: Greg Kroah-Hartman, Peter Griffin, Rob Herring,
krzysztof.kozlowski+dt, Michael Turquette, Conor Dooley,
Stephen Boyd, Tomasz Figa, Sylwester Nawrocki, Linus Walleij,
Wim Van Sebroeck, Guenter Roeck, Catalin Marinas, Will Deacon,
Olof Johansson, Chanwoo Choi, Tudor Ambarus, andre.draszik,
semen.protsenko, soc, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-clk, open list:GPIO SUBSYSTEM,
linux-watchdog, kernel-team
On 06/10/2023 18:33, William McVicker wrote:
> On 10/06/2023, Arnd Bergmann wrote:
>> On Fri, Oct 6, 2023, at 08:06, Krzysztof Kozlowski wrote:
>>> On 06/10/2023 01:19, William McVicker wrote:
>>>> On 10/05/2023, Krzysztof Kozlowski wrote:
>>>>> On 05/10/2023 21:23, Greg KH wrote:
>>>>
>>>> Being able to include SERIAL_SAMSUNG and SERIAL_MSM without all the vendor> specific drivers that ARCH_EXYNOS and ARCH_QCOM select is very
>>> valuable for
>>>> debugging early boot issues.
>>>
>>> Really? How related? The drivers are independent. You describe some
>>> out-of-tree development process which we never needed for upstream work.
>>> And we did here quite a lot of upstream, specially if you look at ARCH_QCOM.
>>
>> Right: in general, all drivers are independent of the platform
>> besides the typical 'depends on ARCH_FOO || COMPILE_TEST' dependency,
>> but I think it's worth mentioning the known exceptions, so Greg and
>> Will can take that fight to the respective places rather than
>> discussing it in the platform submission:
>>
>> - Some subsystems are considered 'special' and the maintainers
>> prefer the drivers to be automatically selected based on the
>> ARCH_* settings instead of having user-visible options. This is
>> traditionally true for large chunks of drivers/irqchip,
>> drivers/clocksource and drivers/pinctrl, though it has gotten
>> better over time on all of them.
>>
>> - Some older 32-bit platforms are still not as modular as we'd
>> like them to be, especially the StrongARM (ARMv4) platforms that
>> require a custom kernel build, and some of ARMv4T and ARMv5
>> boards that are still missing DT support. These tend to require
>> drivers they directly link to from board code, so disabling
>> the drivers would cause a link failure until this gets
>> cleaned up.
>>
>> - A couple of drivers are force-enabled based on the ARCH_*
>> options because booting without these drivers would risk
>> permanent damage to hardware, e.g. in overtemp or overcurrent
>> scenarios.
>>
>> - ACPI based platforms require the PCI host bridge driver to
>> be built-in rather than a loadable module because ACPI
>> needs to probe PCI devices during early boot.
>>
>> - Some subsystems (notably drivers/gpu/, but others as well)
>> have an excessive number of 'select' statements, so you
>> end up surprise-enabling a number of additional drivers
>> and subsystems by enabling certain less important platform
>> specific drivers.
>>
>> Arnd
>
> So if the argument is that the existing upstream Exynos platforms are required
> to have these drivers built-in to the kernel to boot:
> COMMON_CLK_SAMSUNG
> CLKSRC_EXYNOS_MCT
> EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS
> EXYNOS_PMU
> PINCTRL
> PINCTRL_EXYNOS
> PM_GENERIC_DOMAINS if PM
> SOC_SAMSUNG
>
> ...then that is understandable and we can work to fix that.
>
> My last question then is -- why do we need a new ARCH_GOOGLE_TENSOR config in
> the platform Kconfig? For example, I don't really like this:
>
> diff --git a/drivers/clk/samsung/Kconfig b/drivers/clk/samsung/Kconfig
> index 76a494e95027..4c8f173c4dec 100644
> --- a/drivers/clk/samsung/Kconfig
> +++ b/drivers/clk/samsung/Kconfig
> @@ -13,6 +13,7 @@ config COMMON_CLK_SAMSUNG
> select EXYNOS_5420_COMMON_CLK if ARM && SOC_EXYNOS5420
> select EXYNOS_ARM64_COMMON_CLK if ARM64 && ARCH_EXYNOS
> select TESLA_FSD_COMMON_CLK if ARM64 && ARCH_TESLA_FSD
> + select GOOGLE_GS101_COMMON_CLK if ARM64 && ARCH_GOOGLE_TENSOR
>
> What happens when we have GOOGLE_GS101_COMMON_CLK, GOOGLE_GS201_COMMON_CLK, and
> so on?
Nothing happens... or happens anything you wish. Did you read the
motivation why this was created like this?
> How are we going to pick the right driver when e have a generic
> ARCH_GOOGLE_TENSOR config?
You do not have to pick. You select ARCH_GOOGLE_TENSOR and proper pick
is done by you. Nothing to do more.
> Ideally, we should have one Exynos clock driver that
> can detect what hardware is running (using the DT) to determine what it needs
It's already like this. We're done.
> to do. If you really want to compile out the other vendor's clock drivers using
> some configs, then we should do that with SOC_GS101, SOC_GS201, SOC_TESLA_FSD
Whether you call it SOC or ARCH it is the same. We organized it as ARCH.
> configs (not ideal though). With that approach, we could drop the platform
> ARCH_GOOGLE_TENSOR config and create an SOC_GS101 config that can be used for
> things like the COMMON_CLK_SAMSUNG driver (for now) and building the GS101 dtb.
There is no need for this. ARCH does exactly the same.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 18/21] arm64: dts: google: Add initial Google gs101 SoC support
@ 2023-10-07 14:34 ` Krzysztof Kozlowski
0 siblings, 0 replies; 150+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-07 14:34 UTC (permalink / raw)
To: William McVicker, Arnd Bergmann
Cc: Greg Kroah-Hartman, Peter Griffin, Rob Herring,
krzysztof.kozlowski+dt, Michael Turquette, Conor Dooley,
Stephen Boyd, Tomasz Figa, Sylwester Nawrocki, Linus Walleij,
Wim Van Sebroeck, Guenter Roeck, Catalin Marinas, Will Deacon,
Olof Johansson, Chanwoo Choi, Tudor Ambarus, andre.draszik,
semen.protsenko, soc, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-clk, open list:GPIO SUBSYSTEM,
linux-watchdog, kernel-team
On 06/10/2023 18:33, William McVicker wrote:
> On 10/06/2023, Arnd Bergmann wrote:
>> On Fri, Oct 6, 2023, at 08:06, Krzysztof Kozlowski wrote:
>>> On 06/10/2023 01:19, William McVicker wrote:
>>>> On 10/05/2023, Krzysztof Kozlowski wrote:
>>>>> On 05/10/2023 21:23, Greg KH wrote:
>>>>
>>>> Being able to include SERIAL_SAMSUNG and SERIAL_MSM without all the vendor> specific drivers that ARCH_EXYNOS and ARCH_QCOM select is very
>>> valuable for
>>>> debugging early boot issues.
>>>
>>> Really? How related? The drivers are independent. You describe some
>>> out-of-tree development process which we never needed for upstream work.
>>> And we did here quite a lot of upstream, specially if you look at ARCH_QCOM.
>>
>> Right: in general, all drivers are independent of the platform
>> besides the typical 'depends on ARCH_FOO || COMPILE_TEST' dependency,
>> but I think it's worth mentioning the known exceptions, so Greg and
>> Will can take that fight to the respective places rather than
>> discussing it in the platform submission:
>>
>> - Some subsystems are considered 'special' and the maintainers
>> prefer the drivers to be automatically selected based on the
>> ARCH_* settings instead of having user-visible options. This is
>> traditionally true for large chunks of drivers/irqchip,
>> drivers/clocksource and drivers/pinctrl, though it has gotten
>> better over time on all of them.
>>
>> - Some older 32-bit platforms are still not as modular as we'd
>> like them to be, especially the StrongARM (ARMv4) platforms that
>> require a custom kernel build, and some of ARMv4T and ARMv5
>> boards that are still missing DT support. These tend to require
>> drivers they directly link to from board code, so disabling
>> the drivers would cause a link failure until this gets
>> cleaned up.
>>
>> - A couple of drivers are force-enabled based on the ARCH_*
>> options because booting without these drivers would risk
>> permanent damage to hardware, e.g. in overtemp or overcurrent
>> scenarios.
>>
>> - ACPI based platforms require the PCI host bridge driver to
>> be built-in rather than a loadable module because ACPI
>> needs to probe PCI devices during early boot.
>>
>> - Some subsystems (notably drivers/gpu/, but others as well)
>> have an excessive number of 'select' statements, so you
>> end up surprise-enabling a number of additional drivers
>> and subsystems by enabling certain less important platform
>> specific drivers.
>>
>> Arnd
>
> So if the argument is that the existing upstream Exynos platforms are required
> to have these drivers built-in to the kernel to boot:
> COMMON_CLK_SAMSUNG
> CLKSRC_EXYNOS_MCT
> EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS
> EXYNOS_PMU
> PINCTRL
> PINCTRL_EXYNOS
> PM_GENERIC_DOMAINS if PM
> SOC_SAMSUNG
>
> ...then that is understandable and we can work to fix that.
>
> My last question then is -- why do we need a new ARCH_GOOGLE_TENSOR config in
> the platform Kconfig? For example, I don't really like this:
>
> diff --git a/drivers/clk/samsung/Kconfig b/drivers/clk/samsung/Kconfig
> index 76a494e95027..4c8f173c4dec 100644
> --- a/drivers/clk/samsung/Kconfig
> +++ b/drivers/clk/samsung/Kconfig
> @@ -13,6 +13,7 @@ config COMMON_CLK_SAMSUNG
> select EXYNOS_5420_COMMON_CLK if ARM && SOC_EXYNOS5420
> select EXYNOS_ARM64_COMMON_CLK if ARM64 && ARCH_EXYNOS
> select TESLA_FSD_COMMON_CLK if ARM64 && ARCH_TESLA_FSD
> + select GOOGLE_GS101_COMMON_CLK if ARM64 && ARCH_GOOGLE_TENSOR
>
> What happens when we have GOOGLE_GS101_COMMON_CLK, GOOGLE_GS201_COMMON_CLK, and
> so on?
Nothing happens... or happens anything you wish. Did you read the
motivation why this was created like this?
> How are we going to pick the right driver when e have a generic
> ARCH_GOOGLE_TENSOR config?
You do not have to pick. You select ARCH_GOOGLE_TENSOR and proper pick
is done by you. Nothing to do more.
> Ideally, we should have one Exynos clock driver that
> can detect what hardware is running (using the DT) to determine what it needs
It's already like this. We're done.
> to do. If you really want to compile out the other vendor's clock drivers using
> some configs, then we should do that with SOC_GS101, SOC_GS201, SOC_TESLA_FSD
Whether you call it SOC or ARCH it is the same. We organized it as ARCH.
> configs (not ideal though). With that approach, we could drop the platform
> ARCH_GOOGLE_TENSOR config and create an SOC_GS101 config that can be used for
> things like the COMMON_CLK_SAMSUNG driver (for now) and building the GS101 dtb.
There is no need for this. ARCH does exactly the same.
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 18/21] arm64: dts: google: Add initial Google gs101 SoC support
2023-10-07 14:34 ` Krzysztof Kozlowski
@ 2023-10-09 16:10 ` William McVicker
-1 siblings, 0 replies; 150+ messages in thread
From: William McVicker @ 2023-10-09 16:10 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Arnd Bergmann, Greg Kroah-Hartman, Peter Griffin, Rob Herring,
krzysztof.kozlowski+dt, Michael Turquette, Conor Dooley,
Stephen Boyd, Tomasz Figa, Sylwester Nawrocki, Linus Walleij,
Wim Van Sebroeck, Guenter Roeck, Catalin Marinas, Will Deacon,
Olof Johansson, Chanwoo Choi, Tudor Ambarus, andre.draszik,
semen.protsenko, soc, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-clk, open list:GPIO SUBSYSTEM,
linux-watchdog, kernel-team
On 10/07/2023, Krzysztof Kozlowski wrote:
> On 06/10/2023 18:33, William McVicker wrote:
> > On 10/06/2023, Arnd Bergmann wrote:
> >> On Fri, Oct 6, 2023, at 08:06, Krzysztof Kozlowski wrote:
> >>> On 06/10/2023 01:19, William McVicker wrote:
> >>>> On 10/05/2023, Krzysztof Kozlowski wrote:
> >>>>> On 05/10/2023 21:23, Greg KH wrote:
> >>>>
> >>>> Being able to include SERIAL_SAMSUNG and SERIAL_MSM without all the vendor> specific drivers that ARCH_EXYNOS and ARCH_QCOM select is very
> >>> valuable for
> >>>> debugging early boot issues.
> >>>
> >>> Really? How related? The drivers are independent. You describe some
> >>> out-of-tree development process which we never needed for upstream work.
> >>> And we did here quite a lot of upstream, specially if you look at ARCH_QCOM.
> >>
> >> Right: in general, all drivers are independent of the platform
> >> besides the typical 'depends on ARCH_FOO || COMPILE_TEST' dependency,
> >> but I think it's worth mentioning the known exceptions, so Greg and
> >> Will can take that fight to the respective places rather than
> >> discussing it in the platform submission:
> >>
> >> - Some subsystems are considered 'special' and the maintainers
> >> prefer the drivers to be automatically selected based on the
> >> ARCH_* settings instead of having user-visible options. This is
> >> traditionally true for large chunks of drivers/irqchip,
> >> drivers/clocksource and drivers/pinctrl, though it has gotten
> >> better over time on all of them.
> >>
> >> - Some older 32-bit platforms are still not as modular as we'd
> >> like them to be, especially the StrongARM (ARMv4) platforms that
> >> require a custom kernel build, and some of ARMv4T and ARMv5
> >> boards that are still missing DT support. These tend to require
> >> drivers they directly link to from board code, so disabling
> >> the drivers would cause a link failure until this gets
> >> cleaned up.
> >>
> >> - A couple of drivers are force-enabled based on the ARCH_*
> >> options because booting without these drivers would risk
> >> permanent damage to hardware, e.g. in overtemp or overcurrent
> >> scenarios.
> >>
> >> - ACPI based platforms require the PCI host bridge driver to
> >> be built-in rather than a loadable module because ACPI
> >> needs to probe PCI devices during early boot.
> >>
> >> - Some subsystems (notably drivers/gpu/, but others as well)
> >> have an excessive number of 'select' statements, so you
> >> end up surprise-enabling a number of additional drivers
> >> and subsystems by enabling certain less important platform
> >> specific drivers.
> >>
> >> Arnd
> >
> > So if the argument is that the existing upstream Exynos platforms are required
> > to have these drivers built-in to the kernel to boot:
> > COMMON_CLK_SAMSUNG
> > CLKSRC_EXYNOS_MCT
> > EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS
> > EXYNOS_PMU
> > PINCTRL
> > PINCTRL_EXYNOS
> > PM_GENERIC_DOMAINS if PM
> > SOC_SAMSUNG
> >
> > ...then that is understandable and we can work to fix that.
> >
> > My last question then is -- why do we need a new ARCH_GOOGLE_TENSOR config in
> > the platform Kconfig? For example, I don't really like this:
> >
> > diff --git a/drivers/clk/samsung/Kconfig b/drivers/clk/samsung/Kconfig
> > index 76a494e95027..4c8f173c4dec 100644
> > --- a/drivers/clk/samsung/Kconfig
> > +++ b/drivers/clk/samsung/Kconfig
> > @@ -13,6 +13,7 @@ config COMMON_CLK_SAMSUNG
> > select EXYNOS_5420_COMMON_CLK if ARM && SOC_EXYNOS5420
> > select EXYNOS_ARM64_COMMON_CLK if ARM64 && ARCH_EXYNOS
> > select TESLA_FSD_COMMON_CLK if ARM64 && ARCH_TESLA_FSD
> > + select GOOGLE_GS101_COMMON_CLK if ARM64 && ARCH_GOOGLE_TENSOR
> >
> > What happens when we have GOOGLE_GS101_COMMON_CLK, GOOGLE_GS201_COMMON_CLK, and
> > so on?
>
> Nothing happens... or happens anything you wish. Did you read the
> motivation why this was created like this?
>
>
> > How are we going to pick the right driver when e have a generic
> > ARCH_GOOGLE_TENSOR config?
>
Okay, we can figure that out the gs201 specifics when the time comes.
> You do not have to pick. You select ARCH_GOOGLE_TENSOR and proper pick
> is done by you. Nothing to do more.
>
> > Ideally, we should have one Exynos clock driver that
> > can detect what hardware is running (using the DT) to determine what it needs
>
> It's already like this. We're done.
>
> > to do. If you really want to compile out the other vendor's clock drivers using
> > some configs, then we should do that with SOC_GS101, SOC_GS201, SOC_TESLA_FSD
>
> Whether you call it SOC or ARCH it is the same. We organized it as ARCH.
>
> > configs (not ideal though). With that approach, we could drop the platform
> > ARCH_GOOGLE_TENSOR config and create an SOC_GS101 config that can be used for
> > things like the COMMON_CLK_SAMSUNG driver (for now) and building the GS101 dtb.
>
> There is no need for this. ARCH does exactly the same.
Okay, sounds good. Thanks for the responses.
Regards,
Will
>
> Best regards,
> Krzysztof
>
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 18/21] arm64: dts: google: Add initial Google gs101 SoC support
@ 2023-10-09 16:10 ` William McVicker
0 siblings, 0 replies; 150+ messages in thread
From: William McVicker @ 2023-10-09 16:10 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Arnd Bergmann, Greg Kroah-Hartman, Peter Griffin, Rob Herring,
krzysztof.kozlowski+dt, Michael Turquette, Conor Dooley,
Stephen Boyd, Tomasz Figa, Sylwester Nawrocki, Linus Walleij,
Wim Van Sebroeck, Guenter Roeck, Catalin Marinas, Will Deacon,
Olof Johansson, Chanwoo Choi, Tudor Ambarus, andre.draszik,
semen.protsenko, soc, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-clk, open list:GPIO SUBSYSTEM,
linux-watchdog, kernel-team
On 10/07/2023, Krzysztof Kozlowski wrote:
> On 06/10/2023 18:33, William McVicker wrote:
> > On 10/06/2023, Arnd Bergmann wrote:
> >> On Fri, Oct 6, 2023, at 08:06, Krzysztof Kozlowski wrote:
> >>> On 06/10/2023 01:19, William McVicker wrote:
> >>>> On 10/05/2023, Krzysztof Kozlowski wrote:
> >>>>> On 05/10/2023 21:23, Greg KH wrote:
> >>>>
> >>>> Being able to include SERIAL_SAMSUNG and SERIAL_MSM without all the vendor> specific drivers that ARCH_EXYNOS and ARCH_QCOM select is very
> >>> valuable for
> >>>> debugging early boot issues.
> >>>
> >>> Really? How related? The drivers are independent. You describe some
> >>> out-of-tree development process which we never needed for upstream work.
> >>> And we did here quite a lot of upstream, specially if you look at ARCH_QCOM.
> >>
> >> Right: in general, all drivers are independent of the platform
> >> besides the typical 'depends on ARCH_FOO || COMPILE_TEST' dependency,
> >> but I think it's worth mentioning the known exceptions, so Greg and
> >> Will can take that fight to the respective places rather than
> >> discussing it in the platform submission:
> >>
> >> - Some subsystems are considered 'special' and the maintainers
> >> prefer the drivers to be automatically selected based on the
> >> ARCH_* settings instead of having user-visible options. This is
> >> traditionally true for large chunks of drivers/irqchip,
> >> drivers/clocksource and drivers/pinctrl, though it has gotten
> >> better over time on all of them.
> >>
> >> - Some older 32-bit platforms are still not as modular as we'd
> >> like them to be, especially the StrongARM (ARMv4) platforms that
> >> require a custom kernel build, and some of ARMv4T and ARMv5
> >> boards that are still missing DT support. These tend to require
> >> drivers they directly link to from board code, so disabling
> >> the drivers would cause a link failure until this gets
> >> cleaned up.
> >>
> >> - A couple of drivers are force-enabled based on the ARCH_*
> >> options because booting without these drivers would risk
> >> permanent damage to hardware, e.g. in overtemp or overcurrent
> >> scenarios.
> >>
> >> - ACPI based platforms require the PCI host bridge driver to
> >> be built-in rather than a loadable module because ACPI
> >> needs to probe PCI devices during early boot.
> >>
> >> - Some subsystems (notably drivers/gpu/, but others as well)
> >> have an excessive number of 'select' statements, so you
> >> end up surprise-enabling a number of additional drivers
> >> and subsystems by enabling certain less important platform
> >> specific drivers.
> >>
> >> Arnd
> >
> > So if the argument is that the existing upstream Exynos platforms are required
> > to have these drivers built-in to the kernel to boot:
> > COMMON_CLK_SAMSUNG
> > CLKSRC_EXYNOS_MCT
> > EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS
> > EXYNOS_PMU
> > PINCTRL
> > PINCTRL_EXYNOS
> > PM_GENERIC_DOMAINS if PM
> > SOC_SAMSUNG
> >
> > ...then that is understandable and we can work to fix that.
> >
> > My last question then is -- why do we need a new ARCH_GOOGLE_TENSOR config in
> > the platform Kconfig? For example, I don't really like this:
> >
> > diff --git a/drivers/clk/samsung/Kconfig b/drivers/clk/samsung/Kconfig
> > index 76a494e95027..4c8f173c4dec 100644
> > --- a/drivers/clk/samsung/Kconfig
> > +++ b/drivers/clk/samsung/Kconfig
> > @@ -13,6 +13,7 @@ config COMMON_CLK_SAMSUNG
> > select EXYNOS_5420_COMMON_CLK if ARM && SOC_EXYNOS5420
> > select EXYNOS_ARM64_COMMON_CLK if ARM64 && ARCH_EXYNOS
> > select TESLA_FSD_COMMON_CLK if ARM64 && ARCH_TESLA_FSD
> > + select GOOGLE_GS101_COMMON_CLK if ARM64 && ARCH_GOOGLE_TENSOR
> >
> > What happens when we have GOOGLE_GS101_COMMON_CLK, GOOGLE_GS201_COMMON_CLK, and
> > so on?
>
> Nothing happens... or happens anything you wish. Did you read the
> motivation why this was created like this?
>
>
> > How are we going to pick the right driver when e have a generic
> > ARCH_GOOGLE_TENSOR config?
>
Okay, we can figure that out the gs201 specifics when the time comes.
> You do not have to pick. You select ARCH_GOOGLE_TENSOR and proper pick
> is done by you. Nothing to do more.
>
> > Ideally, we should have one Exynos clock driver that
> > can detect what hardware is running (using the DT) to determine what it needs
>
> It's already like this. We're done.
>
> > to do. If you really want to compile out the other vendor's clock drivers using
> > some configs, then we should do that with SOC_GS101, SOC_GS201, SOC_TESLA_FSD
>
> Whether you call it SOC or ARCH it is the same. We organized it as ARCH.
>
> > configs (not ideal though). With that approach, we could drop the platform
> > ARCH_GOOGLE_TENSOR config and create an SOC_GS101 config that can be used for
> > things like the COMMON_CLK_SAMSUNG driver (for now) and building the GS101 dtb.
>
> There is no need for this. ARCH does exactly the same.
Okay, sounds good. Thanks for the responses.
Regards,
Will
>
> Best regards,
> Krzysztof
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 18/21] arm64: dts: google: Add initial Google gs101 SoC support
2023-10-05 17:59 ` William McVicker
@ 2023-10-05 19:21 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 150+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-05 19:21 UTC (permalink / raw)
To: William McVicker, Peter Griffin
Cc: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi, tudor.ambarus,
andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog, gregkh, kernel-team
On 05/10/2023 19:59, William McVicker wrote:
> On 10/05/2023, Peter Griffin wrote:
>> Google gs101 SoC is ARMv8 mobile SoC found in the Pixel 6,
>> (oriole) Pixel 6a (bluejay) and Pixel 6 pro (raven) mobile
>> phones. It features:
>> * 4xA55 little cluster
>> * 2xA76 Mid cluster
>> * 2xX1 Big cluster
>>
>> This commit adds the basic device tree for gs101 (SoC) and oriole
>> (pixel 6). Further platform support will be added over time.
>>
>> It has been tested with a minimal busybox initramfs and boots to
>> a shell.
>>
>> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
>> ---
>> arch/arm64/Kconfig.platforms | 6 +
>> arch/arm64/boot/dts/Makefile | 1 +
>> arch/arm64/boot/dts/google/Makefile | 6 +
>> arch/arm64/boot/dts/google/gs101-oriole.dts | 68 +
>> arch/arm64/boot/dts/google/gs101-pinctrl.dtsi | 1134 +++++++++++++++++
>> arch/arm64/boot/dts/google/gs101-pinctrl.h | 17 +
>> arch/arm64/boot/dts/google/gs101.dtsi | 501 ++++++++
>> 7 files changed, 1733 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/google/Makefile
>> create mode 100644 arch/arm64/boot/dts/google/gs101-oriole.dts
>> create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.dtsi
>> create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.h
>> create mode 100644 arch/arm64/boot/dts/google/gs101.dtsi
>>
>> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
>> index 6069120199bb..a5ed1b719488 100644
>> --- a/arch/arm64/Kconfig.platforms
>> +++ b/arch/arm64/Kconfig.platforms
>> @@ -107,6 +107,12 @@ config ARCH_EXYNOS
>> help
>> This enables support for ARMv8 based Samsung Exynos SoC family.
>>
>> +config ARCH_GOOGLE_TENSOR
>> + bool "Google Tensor SoC fmaily"
>> + depends on ARCH_EXYNOS
>> + help
>> + Support for ARMv8 based Google Tensor platforms.
>
> I'd like to bring up this thread and discuss the option of not introducing
> another ARCH_* config:
>
> https://lore.kernel.org/all/20200306103652.GA3634389@kroah.com/
>
> I especially don't like the "depends on ARCH_EXYNOS" because that forces one to
> include all the other Exynos drivers that ARCH_EXYNOS selects that Google
Since we are creating unified kernel images, having other drivers is not
a problem.
> Tensor SoCs don't need. Can we consider using SOC_GOOGLE instead and for all
SOC_GOOGLE will work exactly the same and depend on ARCH_EXYNOS or
appear everywhere as ARCH_EXYNOS. We already had this talk with Tesla.
> drivers that actually depend on the SoC hardware, we can just add "depends on
> SOC_GOOGLE"?
>
> The idea is that drivers should be tied to hardware -- not a specific vendor.
And hardware is Exynos. Tesla FSD and Google Tensor is Exynos, even if
you do no like calling it.
> By making drivers depend on ARCH_*, you are introducing an arbitrary vendor
> dependency and not a hardware dependency.
There is no arbitrary dependency. We call it all Exynos hardware,
because this is Exynos.
I remember what you were pushing for removal of ARCH_EXYNOS and there
waas clear feedback, not only from me: this is against communities goals.
>
> Thanks,
> Will
Please trim the replies from unrelated context.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 18/21] arm64: dts: google: Add initial Google gs101 SoC support
@ 2023-10-05 19:21 ` Krzysztof Kozlowski
0 siblings, 0 replies; 150+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-05 19:21 UTC (permalink / raw)
To: William McVicker, Peter Griffin
Cc: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi, tudor.ambarus,
andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog, gregkh, kernel-team
On 05/10/2023 19:59, William McVicker wrote:
> On 10/05/2023, Peter Griffin wrote:
>> Google gs101 SoC is ARMv8 mobile SoC found in the Pixel 6,
>> (oriole) Pixel 6a (bluejay) and Pixel 6 pro (raven) mobile
>> phones. It features:
>> * 4xA55 little cluster
>> * 2xA76 Mid cluster
>> * 2xX1 Big cluster
>>
>> This commit adds the basic device tree for gs101 (SoC) and oriole
>> (pixel 6). Further platform support will be added over time.
>>
>> It has been tested with a minimal busybox initramfs and boots to
>> a shell.
>>
>> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
>> ---
>> arch/arm64/Kconfig.platforms | 6 +
>> arch/arm64/boot/dts/Makefile | 1 +
>> arch/arm64/boot/dts/google/Makefile | 6 +
>> arch/arm64/boot/dts/google/gs101-oriole.dts | 68 +
>> arch/arm64/boot/dts/google/gs101-pinctrl.dtsi | 1134 +++++++++++++++++
>> arch/arm64/boot/dts/google/gs101-pinctrl.h | 17 +
>> arch/arm64/boot/dts/google/gs101.dtsi | 501 ++++++++
>> 7 files changed, 1733 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/google/Makefile
>> create mode 100644 arch/arm64/boot/dts/google/gs101-oriole.dts
>> create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.dtsi
>> create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.h
>> create mode 100644 arch/arm64/boot/dts/google/gs101.dtsi
>>
>> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
>> index 6069120199bb..a5ed1b719488 100644
>> --- a/arch/arm64/Kconfig.platforms
>> +++ b/arch/arm64/Kconfig.platforms
>> @@ -107,6 +107,12 @@ config ARCH_EXYNOS
>> help
>> This enables support for ARMv8 based Samsung Exynos SoC family.
>>
>> +config ARCH_GOOGLE_TENSOR
>> + bool "Google Tensor SoC fmaily"
>> + depends on ARCH_EXYNOS
>> + help
>> + Support for ARMv8 based Google Tensor platforms.
>
> I'd like to bring up this thread and discuss the option of not introducing
> another ARCH_* config:
>
> https://lore.kernel.org/all/20200306103652.GA3634389@kroah.com/
>
> I especially don't like the "depends on ARCH_EXYNOS" because that forces one to
> include all the other Exynos drivers that ARCH_EXYNOS selects that Google
Since we are creating unified kernel images, having other drivers is not
a problem.
> Tensor SoCs don't need. Can we consider using SOC_GOOGLE instead and for all
SOC_GOOGLE will work exactly the same and depend on ARCH_EXYNOS or
appear everywhere as ARCH_EXYNOS. We already had this talk with Tesla.
> drivers that actually depend on the SoC hardware, we can just add "depends on
> SOC_GOOGLE"?
>
> The idea is that drivers should be tied to hardware -- not a specific vendor.
And hardware is Exynos. Tesla FSD and Google Tensor is Exynos, even if
you do no like calling it.
> By making drivers depend on ARCH_*, you are introducing an arbitrary vendor
> dependency and not a hardware dependency.
There is no arbitrary dependency. We call it all Exynos hardware,
because this is Exynos.
I remember what you were pushing for removal of ARCH_EXYNOS and there
waas clear feedback, not only from me: this is against communities goals.
>
> Thanks,
> Will
Please trim the replies from unrelated context.
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 18/21] arm64: dts: google: Add initial Google gs101 SoC support
2023-10-05 17:59 ` William McVicker
@ 2023-10-05 19:22 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 150+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-05 19:22 UTC (permalink / raw)
To: William McVicker, Peter Griffin
Cc: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi, tudor.ambarus,
andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog, gregkh, kernel-team
On 05/10/2023 19:59, William McVicker wrote:
> On 10/05/2023, Peter Griffin wrote:
>> Google gs101 SoC is ARMv8 mobile SoC found in the Pixel 6,
>> (oriole) Pixel 6a (bluejay) and Pixel 6 pro (raven) mobile
>> phones. It features:
>> * 4xA55 little cluster
>> * 2xA76 Mid cluster
>> * 2xX1 Big cluster
>>
>> This commit adds the basic device tree for gs101 (SoC) and oriole
>> (pixel 6). Further platform support will be added over time.
>>
>> It has been tested with a minimal busybox initramfs and boots to
>> a shell.
>>
William,
Please do not Cc non-existing mailboxes. You added Cc kernel-team and we
all got awesome bounces now:
"We're writing to let you know that the group you tried to contact
(kernel-team) may not exist, or you may not have permission to post
messages to the group. A few more details on why you weren't able to post:"
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 18/21] arm64: dts: google: Add initial Google gs101 SoC support
@ 2023-10-05 19:22 ` Krzysztof Kozlowski
0 siblings, 0 replies; 150+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-05 19:22 UTC (permalink / raw)
To: William McVicker, Peter Griffin
Cc: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi, tudor.ambarus,
andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog, gregkh, kernel-team
On 05/10/2023 19:59, William McVicker wrote:
> On 10/05/2023, Peter Griffin wrote:
>> Google gs101 SoC is ARMv8 mobile SoC found in the Pixel 6,
>> (oriole) Pixel 6a (bluejay) and Pixel 6 pro (raven) mobile
>> phones. It features:
>> * 4xA55 little cluster
>> * 2xA76 Mid cluster
>> * 2xX1 Big cluster
>>
>> This commit adds the basic device tree for gs101 (SoC) and oriole
>> (pixel 6). Further platform support will be added over time.
>>
>> It has been tested with a minimal busybox initramfs and boots to
>> a shell.
>>
William,
Please do not Cc non-existing mailboxes. You added Cc kernel-team and we
all got awesome bounces now:
"We're writing to let you know that the group you tried to contact
(kernel-team) may not exist, or you may not have permission to post
messages to the group. A few more details on why you weren't able to post:"
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 18/21] arm64: dts: google: Add initial Google gs101 SoC support
2023-10-05 19:22 ` Krzysztof Kozlowski
@ 2023-10-05 19:26 ` William McVicker
-1 siblings, 0 replies; 150+ messages in thread
From: William McVicker @ 2023-10-05 19:26 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Peter Griffin, robh+dt, krzysztof.kozlowski+dt, mturquette,
conor+dt, sboyd, tomasz.figa, s.nawrocki, linus.walleij, wim,
linux, catalin.marinas, will, arnd, olof, cw00.choi,
tudor.ambarus, andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog, gregkh, kernel-team
On 10/05/2023, Krzysztof Kozlowski wrote:
> On 05/10/2023 19:59, William McVicker wrote:
> > On 10/05/2023, Peter Griffin wrote:
> >> Google gs101 SoC is ARMv8 mobile SoC found in the Pixel 6,
> >> (oriole) Pixel 6a (bluejay) and Pixel 6 pro (raven) mobile
> >> phones. It features:
> >> * 4xA55 little cluster
> >> * 2xA76 Mid cluster
> >> * 2xX1 Big cluster
> >>
> >> This commit adds the basic device tree for gs101 (SoC) and oriole
> >> (pixel 6). Further platform support will be added over time.
> >>
> >> It has been tested with a minimal busybox initramfs and boots to
> >> a shell.
> >>
>
> William,
>
> Please do not Cc non-existing mailboxes. You added Cc kernel-team and we
> all got awesome bounces now:
>
> "We're writing to let you know that the group you tried to contact
> (kernel-team) may not exist, or you may not have permission to post
> messages to the group. A few more details on why you weren't able to post:"
>
> Best regards,
> Krzysztof
>
Sorry, I mistyped the email. Should have been kernel-team@android.com.
Regards,
Will
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 18/21] arm64: dts: google: Add initial Google gs101 SoC support
@ 2023-10-05 19:26 ` William McVicker
0 siblings, 0 replies; 150+ messages in thread
From: William McVicker @ 2023-10-05 19:26 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Peter Griffin, robh+dt, krzysztof.kozlowski+dt, mturquette,
conor+dt, sboyd, tomasz.figa, s.nawrocki, linus.walleij, wim,
linux, catalin.marinas, will, arnd, olof, cw00.choi,
tudor.ambarus, andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog, gregkh, kernel-team
On 10/05/2023, Krzysztof Kozlowski wrote:
> On 05/10/2023 19:59, William McVicker wrote:
> > On 10/05/2023, Peter Griffin wrote:
> >> Google gs101 SoC is ARMv8 mobile SoC found in the Pixel 6,
> >> (oriole) Pixel 6a (bluejay) and Pixel 6 pro (raven) mobile
> >> phones. It features:
> >> * 4xA55 little cluster
> >> * 2xA76 Mid cluster
> >> * 2xX1 Big cluster
> >>
> >> This commit adds the basic device tree for gs101 (SoC) and oriole
> >> (pixel 6). Further platform support will be added over time.
> >>
> >> It has been tested with a minimal busybox initramfs and boots to
> >> a shell.
> >>
>
> William,
>
> Please do not Cc non-existing mailboxes. You added Cc kernel-team and we
> all got awesome bounces now:
>
> "We're writing to let you know that the group you tried to contact
> (kernel-team) may not exist, or you may not have permission to post
> messages to the group. A few more details on why you weren't able to post:"
>
> Best regards,
> Krzysztof
>
Sorry, I mistyped the email. Should have been kernel-team@android.com.
Regards,
Will
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 18/21] arm64: dts: google: Add initial Google gs101 SoC support
2023-10-05 15:56 ` Peter Griffin
@ 2023-10-09 12:01 ` Tudor Ambarus
-1 siblings, 0 replies; 150+ messages in thread
From: Tudor Ambarus @ 2023-10-09 12:01 UTC (permalink / raw)
To: Peter Griffin, robh+dt, krzysztof.kozlowski+dt, mturquette,
conor+dt, sboyd, tomasz.figa, s.nawrocki, linus.walleij, wim,
linux, catalin.marinas, will, arnd, olof, cw00.choi
Cc: andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog
Hi, Peter,
On 10/5/23 16:56, Peter Griffin wrote:
> + serial_0: serial@10a00000 {
> + compatible = "samsung,exynos850-uart";
This deserves a SoC specific compatible so that any further quirks or
incompatibilities can be easily addressed.
Cheers,
ta
^ permalink raw reply [flat|nested] 150+ messages in thread* Re: [PATCH 18/21] arm64: dts: google: Add initial Google gs101 SoC support
@ 2023-10-09 12:01 ` Tudor Ambarus
0 siblings, 0 replies; 150+ messages in thread
From: Tudor Ambarus @ 2023-10-09 12:01 UTC (permalink / raw)
To: Peter Griffin, robh+dt, krzysztof.kozlowski+dt, mturquette,
conor+dt, sboyd, tomasz.figa, s.nawrocki, linus.walleij, wim,
linux, catalin.marinas, will, arnd, olof, cw00.choi
Cc: andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog
Hi, Peter,
On 10/5/23 16:56, Peter Griffin wrote:
> + serial_0: serial@10a00000 {
> + compatible = "samsung,exynos850-uart";
This deserves a SoC specific compatible so that any further quirks or
incompatibilities can be easily addressed.
Cheers,
ta
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 150+ messages in thread
* [PATCH 19/21] google/gs101: Add dt overlay for oriole board
2023-10-05 15:55 ` Peter Griffin
@ 2023-10-05 15:56 ` Peter Griffin
-1 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-05 15:56 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi
Cc: peter.griffin, tudor.ambarus, andre.draszik, semen.protsenko,
soc, devicetree, linux-arm-kernel, linux-samsung-soc, linux-clk,
linux-gpio, linux-watchdog
The LK bootloader on Pixel6 searches for a dt overlay in the
dtbo partition with a board_id and board_rev that matches
what is baked into the device. If this overlay is not present
then the phone will bootloop in fastboot and you can't boot
the upstream kernel.
This commit adds a dtbo for the production oriole variant.
The other pre-production board overlays are not included
at this time.
Adding the dtbo here allows for a better experience when
building/booting the upstream kernel on Pixel devices
as all the DT required to boot the device will be created
as part of the kernel build process. Rather than having to
fetch the dtbo from some other repo.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
arch/arm64/boot/dts/google/Makefile | 1 +
arch/arm64/boot/dts/google/gs101-oriole.dtso | 21 ++++++++++++++++++++
2 files changed, 22 insertions(+)
create mode 100644 arch/arm64/boot/dts/google/gs101-oriole.dtso
diff --git a/arch/arm64/boot/dts/google/Makefile b/arch/arm64/boot/dts/google/Makefile
index 6d2026a767d4..3f1761f8daa9 100644
--- a/arch/arm64/boot/dts/google/Makefile
+++ b/arch/arm64/boot/dts/google/Makefile
@@ -2,5 +2,6 @@
dtb-$(CONFIG_ARCH_GOOGLE_TENSOR) += \
gs101-oriole.dtb \
+ gs101-oriole.dtbo
diff --git a/arch/arm64/boot/dts/google/gs101-oriole.dtso b/arch/arm64/boot/dts/google/gs101-oriole.dtso
new file mode 100644
index 000000000000..50832fd94204
--- /dev/null
+++ b/arch/arm64/boot/dts/google/gs101-oriole.dtso
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Oriole DVT Device Tree
+ *
+ * Copyright 2021-2023 Google,LLC
+ */
+
+/dts-v1/;
+/plugin/;
+
+/ {
+ board_id = <0x20304>;
+ board_rev = <0x10000>;
+ fragment@boardbase {
+ target-path="/";
+ __overlay__ {
+ model = "Oriole DVT";
+ compatible = "google,gs101-oriole";
+ };
+ };
+};
--
2.42.0.582.g8ccd20d70d-goog
^ permalink raw reply related [flat|nested] 150+ messages in thread* [PATCH 19/21] google/gs101: Add dt overlay for oriole board
@ 2023-10-05 15:56 ` Peter Griffin
0 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-05 15:56 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi
Cc: peter.griffin, tudor.ambarus, andre.draszik, semen.protsenko,
soc, devicetree, linux-arm-kernel, linux-samsung-soc, linux-clk,
linux-gpio, linux-watchdog
The LK bootloader on Pixel6 searches for a dt overlay in the
dtbo partition with a board_id and board_rev that matches
what is baked into the device. If this overlay is not present
then the phone will bootloop in fastboot and you can't boot
the upstream kernel.
This commit adds a dtbo for the production oriole variant.
The other pre-production board overlays are not included
at this time.
Adding the dtbo here allows for a better experience when
building/booting the upstream kernel on Pixel devices
as all the DT required to boot the device will be created
as part of the kernel build process. Rather than having to
fetch the dtbo from some other repo.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
arch/arm64/boot/dts/google/Makefile | 1 +
arch/arm64/boot/dts/google/gs101-oriole.dtso | 21 ++++++++++++++++++++
2 files changed, 22 insertions(+)
create mode 100644 arch/arm64/boot/dts/google/gs101-oriole.dtso
diff --git a/arch/arm64/boot/dts/google/Makefile b/arch/arm64/boot/dts/google/Makefile
index 6d2026a767d4..3f1761f8daa9 100644
--- a/arch/arm64/boot/dts/google/Makefile
+++ b/arch/arm64/boot/dts/google/Makefile
@@ -2,5 +2,6 @@
dtb-$(CONFIG_ARCH_GOOGLE_TENSOR) += \
gs101-oriole.dtb \
+ gs101-oriole.dtbo
diff --git a/arch/arm64/boot/dts/google/gs101-oriole.dtso b/arch/arm64/boot/dts/google/gs101-oriole.dtso
new file mode 100644
index 000000000000..50832fd94204
--- /dev/null
+++ b/arch/arm64/boot/dts/google/gs101-oriole.dtso
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Oriole DVT Device Tree
+ *
+ * Copyright 2021-2023 Google,LLC
+ */
+
+/dts-v1/;
+/plugin/;
+
+/ {
+ board_id = <0x20304>;
+ board_rev = <0x10000>;
+ fragment@boardbase {
+ target-path="/";
+ __overlay__ {
+ model = "Oriole DVT";
+ compatible = "google,gs101-oriole";
+ };
+ };
+};
--
2.42.0.582.g8ccd20d70d-goog
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 150+ messages in thread* Re: [PATCH 19/21] google/gs101: Add dt overlay for oriole board
2023-10-05 15:56 ` Peter Griffin
@ 2023-10-05 16:33 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 150+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-05 16:33 UTC (permalink / raw)
To: Peter Griffin, robh+dt, krzysztof.kozlowski+dt, mturquette,
conor+dt, sboyd, tomasz.figa, s.nawrocki, linus.walleij, wim,
linux, catalin.marinas, will, arnd, olof, cw00.choi
Cc: tudor.ambarus, andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog
On 05/10/2023 17:56, Peter Griffin wrote:
> The LK bootloader on Pixel6 searches for a dt overlay in the
> dtbo partition with a board_id and board_rev that matches
> what is baked into the device. If this overlay is not present
> then the phone will bootloop in fastboot and you can't boot
> the upstream kernel.
>
> This commit adds a dtbo for the production oriole variant.
> The other pre-production board overlays are not included
> at this time.
>
> Adding the dtbo here allows for a better experience when
> building/booting the upstream kernel on Pixel devices
> as all the DT required to boot the device will be created
> as part of the kernel build process. Rather than having to
> fetch the dtbo from some other repo.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> arch/arm64/boot/dts/google/Makefile | 1 +
> arch/arm64/boot/dts/google/gs101-oriole.dtso | 21 ++++++++++++++++++++
> 2 files changed, 22 insertions(+)
> create mode 100644 arch/arm64/boot/dts/google/gs101-oriole.dtso
>
> diff --git a/arch/arm64/boot/dts/google/Makefile b/arch/arm64/boot/dts/google/Makefile
> index 6d2026a767d4..3f1761f8daa9 100644
> --- a/arch/arm64/boot/dts/google/Makefile
> +++ b/arch/arm64/boot/dts/google/Makefile
> @@ -2,5 +2,6 @@
>
> dtb-$(CONFIG_ARCH_GOOGLE_TENSOR) += \
> gs101-oriole.dtb \
> + gs101-oriole.dtbo
>
>
> diff --git a/arch/arm64/boot/dts/google/gs101-oriole.dtso b/arch/arm64/boot/dts/google/gs101-oriole.dtso
> new file mode 100644
> index 000000000000..50832fd94204
> --- /dev/null
> +++ b/arch/arm64/boot/dts/google/gs101-oriole.dtso
> @@ -0,0 +1,21 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Oriole DVT Device Tree
> + *
> + * Copyright 2021-2023 Google,LLC
> + */
> +
> +/dts-v1/;
> +/plugin/;
> +
> +/ {
> + board_id = <0x20304>;
> + board_rev = <0x10000>;
Undocumented properties. Please propose bindings... Also, underscores
are not allowed, so in this form it is a no-go... although I understand
the pain of not being able to change the bootloader.
For reference:
https://lore.kernel.org/all/20220605150747.GA3465286-robh@kernel.org/
https://lore.kernel.org/all/20220610163343.GA1787330-robh@kernel.org/
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 150+ messages in thread* Re: [PATCH 19/21] google/gs101: Add dt overlay for oriole board
@ 2023-10-05 16:33 ` Krzysztof Kozlowski
0 siblings, 0 replies; 150+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-05 16:33 UTC (permalink / raw)
To: Peter Griffin, robh+dt, krzysztof.kozlowski+dt, mturquette,
conor+dt, sboyd, tomasz.figa, s.nawrocki, linus.walleij, wim,
linux, catalin.marinas, will, arnd, olof, cw00.choi
Cc: tudor.ambarus, andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog
On 05/10/2023 17:56, Peter Griffin wrote:
> The LK bootloader on Pixel6 searches for a dt overlay in the
> dtbo partition with a board_id and board_rev that matches
> what is baked into the device. If this overlay is not present
> then the phone will bootloop in fastboot and you can't boot
> the upstream kernel.
>
> This commit adds a dtbo for the production oriole variant.
> The other pre-production board overlays are not included
> at this time.
>
> Adding the dtbo here allows for a better experience when
> building/booting the upstream kernel on Pixel devices
> as all the DT required to boot the device will be created
> as part of the kernel build process. Rather than having to
> fetch the dtbo from some other repo.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> arch/arm64/boot/dts/google/Makefile | 1 +
> arch/arm64/boot/dts/google/gs101-oriole.dtso | 21 ++++++++++++++++++++
> 2 files changed, 22 insertions(+)
> create mode 100644 arch/arm64/boot/dts/google/gs101-oriole.dtso
>
> diff --git a/arch/arm64/boot/dts/google/Makefile b/arch/arm64/boot/dts/google/Makefile
> index 6d2026a767d4..3f1761f8daa9 100644
> --- a/arch/arm64/boot/dts/google/Makefile
> +++ b/arch/arm64/boot/dts/google/Makefile
> @@ -2,5 +2,6 @@
>
> dtb-$(CONFIG_ARCH_GOOGLE_TENSOR) += \
> gs101-oriole.dtb \
> + gs101-oriole.dtbo
>
>
> diff --git a/arch/arm64/boot/dts/google/gs101-oriole.dtso b/arch/arm64/boot/dts/google/gs101-oriole.dtso
> new file mode 100644
> index 000000000000..50832fd94204
> --- /dev/null
> +++ b/arch/arm64/boot/dts/google/gs101-oriole.dtso
> @@ -0,0 +1,21 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Oriole DVT Device Tree
> + *
> + * Copyright 2021-2023 Google,LLC
> + */
> +
> +/dts-v1/;
> +/plugin/;
> +
> +/ {
> + board_id = <0x20304>;
> + board_rev = <0x10000>;
Undocumented properties. Please propose bindings... Also, underscores
are not allowed, so in this form it is a no-go... although I understand
the pain of not being able to change the bootloader.
For reference:
https://lore.kernel.org/all/20220605150747.GA3465286-robh@kernel.org/
https://lore.kernel.org/all/20220610163343.GA1787330-robh@kernel.org/
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 150+ messages in thread* Re: [PATCH 19/21] google/gs101: Add dt overlay for oriole board
2023-10-05 16:33 ` Krzysztof Kozlowski
@ 2023-10-09 20:03 ` William McVicker
-1 siblings, 0 replies; 150+ messages in thread
From: William McVicker @ 2023-10-09 20:03 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Peter Griffin, robh+dt, krzysztof.kozlowski+dt, mturquette,
conor+dt, sboyd, tomasz.figa, s.nawrocki, linus.walleij, wim,
linux, catalin.marinas, will, arnd, olof, cw00.choi,
tudor.ambarus, andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog, kernel-team
On 10/05/2023, Krzysztof Kozlowski wrote:
> On 05/10/2023 17:56, Peter Griffin wrote:
> > The LK bootloader on Pixel6 searches for a dt overlay in the
> > dtbo partition with a board_id and board_rev that matches
> > what is baked into the device. If this overlay is not present
> > then the phone will bootloop in fastboot and you can't boot
> > the upstream kernel.
> >
> > This commit adds a dtbo for the production oriole variant.
> > The other pre-production board overlays are not included
> > at this time.
> >
> > Adding the dtbo here allows for a better experience when
> > building/booting the upstream kernel on Pixel devices
> > as all the DT required to boot the device will be created
> > as part of the kernel build process. Rather than having to
> > fetch the dtbo from some other repo.
> >
> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> > ---
> > arch/arm64/boot/dts/google/Makefile | 1 +
> > arch/arm64/boot/dts/google/gs101-oriole.dtso | 21 ++++++++++++++++++++
> > 2 files changed, 22 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/google/gs101-oriole.dtso
> >
> > diff --git a/arch/arm64/boot/dts/google/Makefile b/arch/arm64/boot/dts/google/Makefile
> > index 6d2026a767d4..3f1761f8daa9 100644
> > --- a/arch/arm64/boot/dts/google/Makefile
> > +++ b/arch/arm64/boot/dts/google/Makefile
> > @@ -2,5 +2,6 @@
> >
> > dtb-$(CONFIG_ARCH_GOOGLE_TENSOR) += \
> > gs101-oriole.dtb \
> > + gs101-oriole.dtbo
> >
> >
> > diff --git a/arch/arm64/boot/dts/google/gs101-oriole.dtso b/arch/arm64/boot/dts/google/gs101-oriole.dtso
> > new file mode 100644
> > index 000000000000..50832fd94204
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/google/gs101-oriole.dtso
> > @@ -0,0 +1,21 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Oriole DVT Device Tree
> > + *
> > + * Copyright 2021-2023 Google,LLC
> > + */
> > +
> > +/dts-v1/;
> > +/plugin/;
> > +
> > +/ {
> > + board_id = <0x20304>;
> > + board_rev = <0x10000>;
>
> Undocumented properties. Please propose bindings... Also, underscores
> are not allowed, so in this form it is a no-go... although I understand
> the pain of not being able to change the bootloader.
>
> For reference:
> https://lore.kernel.org/all/20220605150747.GA3465286-robh@kernel.org/
> https://lore.kernel.org/all/20220610163343.GA1787330-robh@kernel.org/
These names are actually arbitrary and don't depend on the bootloader. They are
passed into the mkdtimg tool [1] using --id and --rev and used to create the
dt_table_entries. The bootloader traverses the table and picks the overlay
based on these properties. So we can use whatever property names we want
without changing the bootloader.
[1] https://android.googlesource.com/platform/system/libufdt/+/refs/heads/main/utils/
Thanks,
Will
>
>
> Best regards,
> Krzysztof
>
^ permalink raw reply [flat|nested] 150+ messages in thread* Re: [PATCH 19/21] google/gs101: Add dt overlay for oriole board
@ 2023-10-09 20:03 ` William McVicker
0 siblings, 0 replies; 150+ messages in thread
From: William McVicker @ 2023-10-09 20:03 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Peter Griffin, robh+dt, krzysztof.kozlowski+dt, mturquette,
conor+dt, sboyd, tomasz.figa, s.nawrocki, linus.walleij, wim,
linux, catalin.marinas, will, arnd, olof, cw00.choi,
tudor.ambarus, andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog, kernel-team
On 10/05/2023, Krzysztof Kozlowski wrote:
> On 05/10/2023 17:56, Peter Griffin wrote:
> > The LK bootloader on Pixel6 searches for a dt overlay in the
> > dtbo partition with a board_id and board_rev that matches
> > what is baked into the device. If this overlay is not present
> > then the phone will bootloop in fastboot and you can't boot
> > the upstream kernel.
> >
> > This commit adds a dtbo for the production oriole variant.
> > The other pre-production board overlays are not included
> > at this time.
> >
> > Adding the dtbo here allows for a better experience when
> > building/booting the upstream kernel on Pixel devices
> > as all the DT required to boot the device will be created
> > as part of the kernel build process. Rather than having to
> > fetch the dtbo from some other repo.
> >
> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> > ---
> > arch/arm64/boot/dts/google/Makefile | 1 +
> > arch/arm64/boot/dts/google/gs101-oriole.dtso | 21 ++++++++++++++++++++
> > 2 files changed, 22 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/google/gs101-oriole.dtso
> >
> > diff --git a/arch/arm64/boot/dts/google/Makefile b/arch/arm64/boot/dts/google/Makefile
> > index 6d2026a767d4..3f1761f8daa9 100644
> > --- a/arch/arm64/boot/dts/google/Makefile
> > +++ b/arch/arm64/boot/dts/google/Makefile
> > @@ -2,5 +2,6 @@
> >
> > dtb-$(CONFIG_ARCH_GOOGLE_TENSOR) += \
> > gs101-oriole.dtb \
> > + gs101-oriole.dtbo
> >
> >
> > diff --git a/arch/arm64/boot/dts/google/gs101-oriole.dtso b/arch/arm64/boot/dts/google/gs101-oriole.dtso
> > new file mode 100644
> > index 000000000000..50832fd94204
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/google/gs101-oriole.dtso
> > @@ -0,0 +1,21 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Oriole DVT Device Tree
> > + *
> > + * Copyright 2021-2023 Google,LLC
> > + */
> > +
> > +/dts-v1/;
> > +/plugin/;
> > +
> > +/ {
> > + board_id = <0x20304>;
> > + board_rev = <0x10000>;
>
> Undocumented properties. Please propose bindings... Also, underscores
> are not allowed, so in this form it is a no-go... although I understand
> the pain of not being able to change the bootloader.
>
> For reference:
> https://lore.kernel.org/all/20220605150747.GA3465286-robh@kernel.org/
> https://lore.kernel.org/all/20220610163343.GA1787330-robh@kernel.org/
These names are actually arbitrary and don't depend on the bootloader. They are
passed into the mkdtimg tool [1] using --id and --rev and used to create the
dt_table_entries. The bootloader traverses the table and picks the overlay
based on these properties. So we can use whatever property names we want
without changing the bootloader.
[1] https://android.googlesource.com/platform/system/libufdt/+/refs/heads/main/utils/
Thanks,
Will
>
>
> Best regards,
> Krzysztof
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 19/21] google/gs101: Add dt overlay for oriole board
2023-10-05 15:56 ` Peter Griffin
@ 2023-10-06 7:08 ` Geert Uytterhoeven
-1 siblings, 0 replies; 150+ messages in thread
From: Geert Uytterhoeven @ 2023-10-06 7:08 UTC (permalink / raw)
To: Peter Griffin
Cc: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi, tudor.ambarus,
andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog
Hi Peter,
On Thu, Oct 5, 2023 at 5:58 PM Peter Griffin <peter.griffin@linaro.org> wrote:
> The LK bootloader on Pixel6 searches for a dt overlay in the
> dtbo partition with a board_id and board_rev that matches
> what is baked into the device. If this overlay is not present
> then the phone will bootloop in fastboot and you can't boot
> the upstream kernel.
>
> This commit adds a dtbo for the production oriole variant.
> The other pre-production board overlays are not included
> at this time.
>
> Adding the dtbo here allows for a better experience when
> building/booting the upstream kernel on Pixel devices
> as all the DT required to boot the device will be created
> as part of the kernel build process. Rather than having to
> fetch the dtbo from some other repo.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Thanks for your patch!
> --- /dev/null
> +++ b/arch/arm64/boot/dts/google/gs101-oriole.dtso
> @@ -0,0 +1,21 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Oriole DVT Device Tree
> + *
> + * Copyright 2021-2023 Google,LLC
> + */
> +
> +/dts-v1/;
> +/plugin/;
> +
> +/ {
> + board_id = <0x20304>;
> + board_rev = <0x10000>;
> + fragment@boardbase {
> + target-path="/";
> + __overlay__ {
> + model = "Oriole DVT";
> + compatible = "google,gs101-oriole";
> + };
> + };
Please use sugar-syntax instead of manually defining
fragment/target-path/__overlay__ constructs.
You can override these properties in the root node of the base DTS
using the much simpler:
&{/} {
model = "Oriole DVT";
compatible = "google,gs101-oriole";
};
The generated DTBO should be identical (modulo naming).
> +};
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 150+ messages in thread* Re: [PATCH 19/21] google/gs101: Add dt overlay for oriole board
@ 2023-10-06 7:08 ` Geert Uytterhoeven
0 siblings, 0 replies; 150+ messages in thread
From: Geert Uytterhoeven @ 2023-10-06 7:08 UTC (permalink / raw)
To: Peter Griffin
Cc: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi, tudor.ambarus,
andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog
Hi Peter,
On Thu, Oct 5, 2023 at 5:58 PM Peter Griffin <peter.griffin@linaro.org> wrote:
> The LK bootloader on Pixel6 searches for a dt overlay in the
> dtbo partition with a board_id and board_rev that matches
> what is baked into the device. If this overlay is not present
> then the phone will bootloop in fastboot and you can't boot
> the upstream kernel.
>
> This commit adds a dtbo for the production oriole variant.
> The other pre-production board overlays are not included
> at this time.
>
> Adding the dtbo here allows for a better experience when
> building/booting the upstream kernel on Pixel devices
> as all the DT required to boot the device will be created
> as part of the kernel build process. Rather than having to
> fetch the dtbo from some other repo.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Thanks for your patch!
> --- /dev/null
> +++ b/arch/arm64/boot/dts/google/gs101-oriole.dtso
> @@ -0,0 +1,21 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Oriole DVT Device Tree
> + *
> + * Copyright 2021-2023 Google,LLC
> + */
> +
> +/dts-v1/;
> +/plugin/;
> +
> +/ {
> + board_id = <0x20304>;
> + board_rev = <0x10000>;
> + fragment@boardbase {
> + target-path="/";
> + __overlay__ {
> + model = "Oriole DVT";
> + compatible = "google,gs101-oriole";
> + };
> + };
Please use sugar-syntax instead of manually defining
fragment/target-path/__overlay__ constructs.
You can override these properties in the root node of the base DTS
using the much simpler:
&{/} {
model = "Oriole DVT";
compatible = "google,gs101-oriole";
};
The generated DTBO should be identical (modulo naming).
> +};
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 19/21] google/gs101: Add dt overlay for oriole board
2023-10-05 15:56 ` Peter Griffin
@ 2023-10-06 20:52 ` Rob Herring
-1 siblings, 0 replies; 150+ messages in thread
From: Rob Herring @ 2023-10-06 20:52 UTC (permalink / raw)
To: Peter Griffin
Cc: krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd, tomasz.figa,
s.nawrocki, linus.walleij, wim, linux, catalin.marinas, will,
arnd, olof, cw00.choi, tudor.ambarus, andre.draszik,
semen.protsenko, soc, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-clk, linux-gpio, linux-watchdog
On Thu, Oct 05, 2023 at 04:56:16PM +0100, Peter Griffin wrote:
> The LK bootloader on Pixel6 searches for a dt overlay in the
> dtbo partition with a board_id and board_rev that matches
> what is baked into the device. If this overlay is not present
> then the phone will bootloop in fastboot and you can't boot
> the upstream kernel.
>
> This commit adds a dtbo for the production oriole variant.
> The other pre-production board overlays are not included
> at this time.
>
> Adding the dtbo here allows for a better experience when
> building/booting the upstream kernel on Pixel devices
> as all the DT required to boot the device will be created
> as part of the kernel build process. Rather than having to
> fetch the dtbo from some other repo.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> arch/arm64/boot/dts/google/Makefile | 1 +
> arch/arm64/boot/dts/google/gs101-oriole.dtso | 21 ++++++++++++++++++++
> 2 files changed, 22 insertions(+)
> create mode 100644 arch/arm64/boot/dts/google/gs101-oriole.dtso
>
> diff --git a/arch/arm64/boot/dts/google/Makefile b/arch/arm64/boot/dts/google/Makefile
> index 6d2026a767d4..3f1761f8daa9 100644
> --- a/arch/arm64/boot/dts/google/Makefile
> +++ b/arch/arm64/boot/dts/google/Makefile
> @@ -2,5 +2,6 @@
>
> dtb-$(CONFIG_ARCH_GOOGLE_TENSOR) += \
> gs101-oriole.dtb \
> + gs101-oriole.dtbo
Overlays in the kernel must be able to be applied to a base DT in the
kernel. Add a rule to apply this (hint: a '-dtbs' variable does this
similar to -objs variables).
> diff --git a/arch/arm64/boot/dts/google/gs101-oriole.dtso b/arch/arm64/boot/dts/google/gs101-oriole.dtso
> new file mode 100644
> index 000000000000..50832fd94204
> --- /dev/null
> +++ b/arch/arm64/boot/dts/google/gs101-oriole.dtso
> @@ -0,0 +1,21 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Oriole DVT Device Tree
Doesn't DVT mean pre-production?
Rob
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 19/21] google/gs101: Add dt overlay for oriole board
@ 2023-10-06 20:52 ` Rob Herring
0 siblings, 0 replies; 150+ messages in thread
From: Rob Herring @ 2023-10-06 20:52 UTC (permalink / raw)
To: Peter Griffin
Cc: krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd, tomasz.figa,
s.nawrocki, linus.walleij, wim, linux, catalin.marinas, will,
arnd, olof, cw00.choi, tudor.ambarus, andre.draszik,
semen.protsenko, soc, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-clk, linux-gpio, linux-watchdog
On Thu, Oct 05, 2023 at 04:56:16PM +0100, Peter Griffin wrote:
> The LK bootloader on Pixel6 searches for a dt overlay in the
> dtbo partition with a board_id and board_rev that matches
> what is baked into the device. If this overlay is not present
> then the phone will bootloop in fastboot and you can't boot
> the upstream kernel.
>
> This commit adds a dtbo for the production oriole variant.
> The other pre-production board overlays are not included
> at this time.
>
> Adding the dtbo here allows for a better experience when
> building/booting the upstream kernel on Pixel devices
> as all the DT required to boot the device will be created
> as part of the kernel build process. Rather than having to
> fetch the dtbo from some other repo.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> arch/arm64/boot/dts/google/Makefile | 1 +
> arch/arm64/boot/dts/google/gs101-oriole.dtso | 21 ++++++++++++++++++++
> 2 files changed, 22 insertions(+)
> create mode 100644 arch/arm64/boot/dts/google/gs101-oriole.dtso
>
> diff --git a/arch/arm64/boot/dts/google/Makefile b/arch/arm64/boot/dts/google/Makefile
> index 6d2026a767d4..3f1761f8daa9 100644
> --- a/arch/arm64/boot/dts/google/Makefile
> +++ b/arch/arm64/boot/dts/google/Makefile
> @@ -2,5 +2,6 @@
>
> dtb-$(CONFIG_ARCH_GOOGLE_TENSOR) += \
> gs101-oriole.dtb \
> + gs101-oriole.dtbo
Overlays in the kernel must be able to be applied to a base DT in the
kernel. Add a rule to apply this (hint: a '-dtbs' variable does this
similar to -objs variables).
> diff --git a/arch/arm64/boot/dts/google/gs101-oriole.dtso b/arch/arm64/boot/dts/google/gs101-oriole.dtso
> new file mode 100644
> index 000000000000..50832fd94204
> --- /dev/null
> +++ b/arch/arm64/boot/dts/google/gs101-oriole.dtso
> @@ -0,0 +1,21 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Oriole DVT Device Tree
Doesn't DVT mean pre-production?
Rob
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 19/21] google/gs101: Add dt overlay for oriole board
2023-10-06 20:52 ` Rob Herring
@ 2023-10-10 12:09 ` Peter Griffin
-1 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-10 12:09 UTC (permalink / raw)
To: Rob Herring
Cc: krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd, tomasz.figa,
s.nawrocki, linus.walleij, wim, linux, catalin.marinas, will,
arnd, olof, cw00.choi, tudor.ambarus, andre.draszik,
semen.protsenko, soc, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-clk, linux-gpio, linux-watchdog
Hi Rob,
Thanks for your review!
On Fri, 6 Oct 2023 at 21:52, Rob Herring <robh@kernel.org> wrote:
>
> On Thu, Oct 05, 2023 at 04:56:16PM +0100, Peter Griffin wrote:
> > The LK bootloader on Pixel6 searches for a dt overlay in the
> > dtbo partition with a board_id and board_rev that matches
> > what is baked into the device. If this overlay is not present
> > then the phone will bootloop in fastboot and you can't boot
> > the upstream kernel.
> >
> > This commit adds a dtbo for the production oriole variant.
> > The other pre-production board overlays are not included
> > at this time.
> >
> > Adding the dtbo here allows for a better experience when
> > building/booting the upstream kernel on Pixel devices
> > as all the DT required to boot the device will be created
> > as part of the kernel build process. Rather than having to
> > fetch the dtbo from some other repo.
> >
> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> > ---
> > arch/arm64/boot/dts/google/Makefile | 1 +
> > arch/arm64/boot/dts/google/gs101-oriole.dtso | 21 ++++++++++++++++++++
> > 2 files changed, 22 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/google/gs101-oriole.dtso
> >
> > diff --git a/arch/arm64/boot/dts/google/Makefile b/arch/arm64/boot/dts/google/Makefile
> > index 6d2026a767d4..3f1761f8daa9 100644
> > --- a/arch/arm64/boot/dts/google/Makefile
> > +++ b/arch/arm64/boot/dts/google/Makefile
> > @@ -2,5 +2,6 @@
> >
> > dtb-$(CONFIG_ARCH_GOOGLE_TENSOR) += \
> > gs101-oriole.dtb \
> > + gs101-oriole.dtbo
>
> Overlays in the kernel must be able to be applied to a base DT in the
> kernel. Add a rule to apply this (hint: a '-dtbs' variable does this
> similar to -objs variables).
Ok will do, thanks for the hint
>
> > diff --git a/arch/arm64/boot/dts/google/gs101-oriole.dtso b/arch/arm64/boot/dts/google/gs101-oriole.dtso
> > new file mode 100644
> > index 000000000000..50832fd94204
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/google/gs101-oriole.dtso
> > @@ -0,0 +1,21 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Oriole DVT Device Tree
>
> Doesn't DVT mean pre-production?
Yes, DVT stands for Design Verification Testing. I can remove that
DVT suffix for v2.
I suppose that means there were no changes between DVT and production as this
is the overlay used by the production devices.
regards,
Peter
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 19/21] google/gs101: Add dt overlay for oriole board
@ 2023-10-10 12:09 ` Peter Griffin
0 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-10 12:09 UTC (permalink / raw)
To: Rob Herring
Cc: krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd, tomasz.figa,
s.nawrocki, linus.walleij, wim, linux, catalin.marinas, will,
arnd, olof, cw00.choi, tudor.ambarus, andre.draszik,
semen.protsenko, soc, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-clk, linux-gpio, linux-watchdog
Hi Rob,
Thanks for your review!
On Fri, 6 Oct 2023 at 21:52, Rob Herring <robh@kernel.org> wrote:
>
> On Thu, Oct 05, 2023 at 04:56:16PM +0100, Peter Griffin wrote:
> > The LK bootloader on Pixel6 searches for a dt overlay in the
> > dtbo partition with a board_id and board_rev that matches
> > what is baked into the device. If this overlay is not present
> > then the phone will bootloop in fastboot and you can't boot
> > the upstream kernel.
> >
> > This commit adds a dtbo for the production oriole variant.
> > The other pre-production board overlays are not included
> > at this time.
> >
> > Adding the dtbo here allows for a better experience when
> > building/booting the upstream kernel on Pixel devices
> > as all the DT required to boot the device will be created
> > as part of the kernel build process. Rather than having to
> > fetch the dtbo from some other repo.
> >
> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> > ---
> > arch/arm64/boot/dts/google/Makefile | 1 +
> > arch/arm64/boot/dts/google/gs101-oriole.dtso | 21 ++++++++++++++++++++
> > 2 files changed, 22 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/google/gs101-oriole.dtso
> >
> > diff --git a/arch/arm64/boot/dts/google/Makefile b/arch/arm64/boot/dts/google/Makefile
> > index 6d2026a767d4..3f1761f8daa9 100644
> > --- a/arch/arm64/boot/dts/google/Makefile
> > +++ b/arch/arm64/boot/dts/google/Makefile
> > @@ -2,5 +2,6 @@
> >
> > dtb-$(CONFIG_ARCH_GOOGLE_TENSOR) += \
> > gs101-oriole.dtb \
> > + gs101-oriole.dtbo
>
> Overlays in the kernel must be able to be applied to a base DT in the
> kernel. Add a rule to apply this (hint: a '-dtbs' variable does this
> similar to -objs variables).
Ok will do, thanks for the hint
>
> > diff --git a/arch/arm64/boot/dts/google/gs101-oriole.dtso b/arch/arm64/boot/dts/google/gs101-oriole.dtso
> > new file mode 100644
> > index 000000000000..50832fd94204
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/google/gs101-oriole.dtso
> > @@ -0,0 +1,21 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Oriole DVT Device Tree
>
> Doesn't DVT mean pre-production?
Yes, DVT stands for Design Verification Testing. I can remove that
DVT suffix for v2.
I suppose that means there were no changes between DVT and production as this
is the overlay used by the production devices.
regards,
Peter
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 150+ messages in thread
* [PATCH 20/21] arm64: defconfig: Enable Google Tensor SoC
2023-10-05 15:55 ` Peter Griffin
@ 2023-10-05 15:56 ` Peter Griffin
-1 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-05 15:56 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi
Cc: peter.griffin, tudor.ambarus, andre.draszik, semen.protsenko,
soc, devicetree, linux-arm-kernel, linux-samsung-soc, linux-clk,
linux-gpio, linux-watchdog
Add the Google Tensor SoC to the arm64 defconfig
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 5315789f4868..8a34603b1822 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -41,6 +41,7 @@ CONFIG_ARCH_BCMBCA=y
CONFIG_ARCH_BRCMSTB=y
CONFIG_ARCH_BERLIN=y
CONFIG_ARCH_EXYNOS=y
+CONFIG_ARCH_GOOGLE_TENSOR=y
CONFIG_ARCH_SPARX5=y
CONFIG_ARCH_K3=y
CONFIG_ARCH_LG1K=y
--
2.42.0.582.g8ccd20d70d-goog
^ permalink raw reply related [flat|nested] 150+ messages in thread
* [PATCH 20/21] arm64: defconfig: Enable Google Tensor SoC
@ 2023-10-05 15:56 ` Peter Griffin
0 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-05 15:56 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi
Cc: peter.griffin, tudor.ambarus, andre.draszik, semen.protsenko,
soc, devicetree, linux-arm-kernel, linux-samsung-soc, linux-clk,
linux-gpio, linux-watchdog
Add the Google Tensor SoC to the arm64 defconfig
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 5315789f4868..8a34603b1822 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -41,6 +41,7 @@ CONFIG_ARCH_BCMBCA=y
CONFIG_ARCH_BRCMSTB=y
CONFIG_ARCH_BERLIN=y
CONFIG_ARCH_EXYNOS=y
+CONFIG_ARCH_GOOGLE_TENSOR=y
CONFIG_ARCH_SPARX5=y
CONFIG_ARCH_K3=y
CONFIG_ARCH_LG1K=y
--
2.42.0.582.g8ccd20d70d-goog
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 150+ messages in thread
* [PATCH 21/21] MAINTAINERS: add entry for Google Tensor SoC
2023-10-05 15:55 ` Peter Griffin
@ 2023-10-05 15:56 ` Peter Griffin
-1 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-05 15:56 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi
Cc: peter.griffin, tudor.ambarus, andre.draszik, semen.protsenko,
soc, devicetree, linux-arm-kernel, linux-samsung-soc, linux-clk,
linux-gpio, linux-watchdog
Add maintainers entry for the Google tensor SoC based
platforms.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
MAINTAINERS | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 90f13281d297..23cfc0799c04 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8836,6 +8836,17 @@ S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/chrome-platform/linux.git
F: drivers/firmware/google/
+GOOGLE TENSOR SoC SUPPORT
+M: Peter Griffin <peter.griffin@linaro.org>
+L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+L: linux-samsung-soc@vger.kernel.org
+S: Maintained
+F: Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
+F: arch/arm64/boot/dts/google/
+F: drivers/clk/samsung/clk-gs101.c
+F: include/dt-bindings/clock/clk-gs101.h
+F: include/dt-bindings/interrupt-controller/gs101.h
+
GPD POCKET FAN DRIVER
M: Hans de Goede <hdegoede@redhat.com>
L: platform-driver-x86@vger.kernel.org
--
2.42.0.582.g8ccd20d70d-goog
^ permalink raw reply related [flat|nested] 150+ messages in thread
* [PATCH 21/21] MAINTAINERS: add entry for Google Tensor SoC
@ 2023-10-05 15:56 ` Peter Griffin
0 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-05 15:56 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi
Cc: peter.griffin, tudor.ambarus, andre.draszik, semen.protsenko,
soc, devicetree, linux-arm-kernel, linux-samsung-soc, linux-clk,
linux-gpio, linux-watchdog
Add maintainers entry for the Google tensor SoC based
platforms.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
MAINTAINERS | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 90f13281d297..23cfc0799c04 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8836,6 +8836,17 @@ S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/chrome-platform/linux.git
F: drivers/firmware/google/
+GOOGLE TENSOR SoC SUPPORT
+M: Peter Griffin <peter.griffin@linaro.org>
+L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+L: linux-samsung-soc@vger.kernel.org
+S: Maintained
+F: Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
+F: arch/arm64/boot/dts/google/
+F: drivers/clk/samsung/clk-gs101.c
+F: include/dt-bindings/clock/clk-gs101.h
+F: include/dt-bindings/interrupt-controller/gs101.h
+
GPD POCKET FAN DRIVER
M: Hans de Goede <hdegoede@redhat.com>
L: platform-driver-x86@vger.kernel.org
--
2.42.0.582.g8ccd20d70d-goog
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 150+ messages in thread
* Re: [PATCH 00/21] Add minimal Tensor/GS101 SoC support and Oriole/Pixel6 board
2023-10-05 15:55 ` Peter Griffin
@ 2023-10-05 16:32 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 150+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-05 16:32 UTC (permalink / raw)
To: Peter Griffin, robh+dt, krzysztof.kozlowski+dt, mturquette,
conor+dt, sboyd, tomasz.figa, s.nawrocki, linus.walleij, wim,
linux, catalin.marinas, will, arnd, olof, cw00.choi
Cc: tudor.ambarus, andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog
On 05/10/2023 17:55, Peter Griffin wrote:
> Hi folks,
>
> This series adds initial SoC support for the GS101 SoC and also initial board
> support for Pixel 6 phone (Oriole).
>
> The gs101 / Tensor SoC is also used in Pixel6a (bluejay) and Pixel 6 Pro (raven).
> Currently DT is just added for the gs101 SoC and Oriole.
Thanks for submitting the patches. Nice work!
This is basically a custom-made variant of Exynos made by Samsung for
Google. Something similar what is with Tesla FSD (and Axis Artpec-8
which was not upstreamed, AFAIR). Many, many drivers and bindings will
be re-used. I want to be sure that GS101 fits into existing Samsung
Exynos support, re-uses it as much as possible and extend when necessary
without breaking anything. Therefore, when the patches are ready, I
would like to be the one applying entire set and future submissions
through Samsung SoC tree, just like I am doing it with Tesla FSD, so I
keep entire Samsung-ecosystem in shape.
This also means that you are lucky to be selected to:
https://elixir.bootlin.com/linux/v6.6-rc4/source/Documentation/process/maintainer-soc-clean-dts.rst
joining there Tesla FSD and entire Samsung Exynos family :)
I hope that's ok.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 00/21] Add minimal Tensor/GS101 SoC support and Oriole/Pixel6 board
@ 2023-10-05 16:32 ` Krzysztof Kozlowski
0 siblings, 0 replies; 150+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-05 16:32 UTC (permalink / raw)
To: Peter Griffin, robh+dt, krzysztof.kozlowski+dt, mturquette,
conor+dt, sboyd, tomasz.figa, s.nawrocki, linus.walleij, wim,
linux, catalin.marinas, will, arnd, olof, cw00.choi
Cc: tudor.ambarus, andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog
On 05/10/2023 17:55, Peter Griffin wrote:
> Hi folks,
>
> This series adds initial SoC support for the GS101 SoC and also initial board
> support for Pixel 6 phone (Oriole).
>
> The gs101 / Tensor SoC is also used in Pixel6a (bluejay) and Pixel 6 Pro (raven).
> Currently DT is just added for the gs101 SoC and Oriole.
Thanks for submitting the patches. Nice work!
This is basically a custom-made variant of Exynos made by Samsung for
Google. Something similar what is with Tesla FSD (and Axis Artpec-8
which was not upstreamed, AFAIR). Many, many drivers and bindings will
be re-used. I want to be sure that GS101 fits into existing Samsung
Exynos support, re-uses it as much as possible and extend when necessary
without breaking anything. Therefore, when the patches are ready, I
would like to be the one applying entire set and future submissions
through Samsung SoC tree, just like I am doing it with Tesla FSD, so I
keep entire Samsung-ecosystem in shape.
This also means that you are lucky to be selected to:
https://elixir.bootlin.com/linux/v6.6-rc4/source/Documentation/process/maintainer-soc-clean-dts.rst
joining there Tesla FSD and entire Samsung Exynos family :)
I hope that's ok.
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 00/21] Add minimal Tensor/GS101 SoC support and Oriole/Pixel6 board
2023-10-05 16:32 ` Krzysztof Kozlowski
@ 2023-10-09 11:39 ` Peter Griffin
-1 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-09 11:39 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi, tudor.ambarus,
andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog
Hi Krzysztof,
On Thu, 5 Oct 2023 at 17:32, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 05/10/2023 17:55, Peter Griffin wrote:
> > Hi folks,
> >
> > This series adds initial SoC support for the GS101 SoC and also initial board
> > support for Pixel 6 phone (Oriole).
> >
> > The gs101 / Tensor SoC is also used in Pixel6a (bluejay) and Pixel 6 Pro (raven).
> > Currently DT is just added for the gs101 SoC and Oriole.
>
> Thanks for submitting the patches. Nice work!
Thanks, and thankyou for reviewing the series so promptly.
>
> This is basically a custom-made variant of Exynos made by Samsung for
> Google. Something similar what is with Tesla FSD (and Axis Artpec-8
> which was not upstreamed, AFAIR). Many, many drivers and bindings will
> be re-used. I want to be sure that GS101 fits into existing Samsung
> Exynos support, re-uses it as much as possible and extend when necessary
> without breaking anything. Therefore, when the patches are ready, I
> would like to be the one applying entire set and future submissions
> through Samsung SoC tree, just like I am doing it with Tesla FSD, so I
> keep entire Samsung-ecosystem in shape.
>
> This also means that you are lucky to be selected to:
> https://elixir.bootlin.com/linux/v6.6-rc4/source/Documentation/process/maintainer-soc-clean-dts.rst
> joining there Tesla FSD and entire Samsung Exynos family :)
>
> I hope that's ok.
That's all fine, it makes sense and it was what I was expecting. Maybe
we can try and get you some Pixel 6 hardware as well. The only other
Exynos hardware I have for testing unfortunately is the e850 board Sam
has been working on.
Coincidentally https://www.crowdsupply.com/0xda/usb-cereal just started
shipping. Which is quite nice (albeit coincidental) timing, as anyone who
has a Pixel 6 device can order one so they can run upstream kernels on
their phone and have the debug UART available (which currently is the
only way to really interact with the system until we bring up more IO).
regards,
Peter
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 00/21] Add minimal Tensor/GS101 SoC support and Oriole/Pixel6 board
@ 2023-10-09 11:39 ` Peter Griffin
0 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-09 11:39 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi, tudor.ambarus,
andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog
Hi Krzysztof,
On Thu, 5 Oct 2023 at 17:32, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 05/10/2023 17:55, Peter Griffin wrote:
> > Hi folks,
> >
> > This series adds initial SoC support for the GS101 SoC and also initial board
> > support for Pixel 6 phone (Oriole).
> >
> > The gs101 / Tensor SoC is also used in Pixel6a (bluejay) and Pixel 6 Pro (raven).
> > Currently DT is just added for the gs101 SoC and Oriole.
>
> Thanks for submitting the patches. Nice work!
Thanks, and thankyou for reviewing the series so promptly.
>
> This is basically a custom-made variant of Exynos made by Samsung for
> Google. Something similar what is with Tesla FSD (and Axis Artpec-8
> which was not upstreamed, AFAIR). Many, many drivers and bindings will
> be re-used. I want to be sure that GS101 fits into existing Samsung
> Exynos support, re-uses it as much as possible and extend when necessary
> without breaking anything. Therefore, when the patches are ready, I
> would like to be the one applying entire set and future submissions
> through Samsung SoC tree, just like I am doing it with Tesla FSD, so I
> keep entire Samsung-ecosystem in shape.
>
> This also means that you are lucky to be selected to:
> https://elixir.bootlin.com/linux/v6.6-rc4/source/Documentation/process/maintainer-soc-clean-dts.rst
> joining there Tesla FSD and entire Samsung Exynos family :)
>
> I hope that's ok.
That's all fine, it makes sense and it was what I was expecting. Maybe
we can try and get you some Pixel 6 hardware as well. The only other
Exynos hardware I have for testing unfortunately is the e850 board Sam
has been working on.
Coincidentally https://www.crowdsupply.com/0xda/usb-cereal just started
shipping. Which is quite nice (albeit coincidental) timing, as anyone who
has a Pixel 6 device can order one so they can run upstream kernels on
their phone and have the debug UART available (which currently is the
only way to really interact with the system until we bring up more IO).
regards,
Peter
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 00/21] Add minimal Tensor/GS101 SoC support and Oriole/Pixel6 board
2023-10-05 15:55 ` Peter Griffin
@ 2023-10-09 11:10 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 150+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-09 11:10 UTC (permalink / raw)
To: Peter Griffin, robh+dt, krzysztof.kozlowski+dt, mturquette,
conor+dt, sboyd, tomasz.figa, s.nawrocki, linus.walleij, wim,
linux, catalin.marinas, will, arnd, olof, cw00.choi
Cc: tudor.ambarus, andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog
On 05/10/2023 17:55, Peter Griffin wrote:
> Hi folks,
>
> This series adds initial SoC support for the GS101 SoC and also initial board
> support for Pixel 6 phone (Oriole).
>
> The gs101 / Tensor SoC is also used in Pixel6a (bluejay) and Pixel 6 Pro (raven).
> Currently DT is just added for the gs101 SoC and Oriole.
>
> The support added in this series consists of:
> * cpus
> * pinctrl
> * some CCF clock implementation
> * watchdog
> * uart
> * gpio
Hi Peter,
Heads up, in case you are not aware Arm SoC timeframes: we are at rc5,
so it means that anything targeting v6.7 should be applied this working
week, before rc6. At least as ARM SoC is concerned.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 00/21] Add minimal Tensor/GS101 SoC support and Oriole/Pixel6 board
@ 2023-10-09 11:10 ` Krzysztof Kozlowski
0 siblings, 0 replies; 150+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-09 11:10 UTC (permalink / raw)
To: Peter Griffin, robh+dt, krzysztof.kozlowski+dt, mturquette,
conor+dt, sboyd, tomasz.figa, s.nawrocki, linus.walleij, wim,
linux, catalin.marinas, will, arnd, olof, cw00.choi
Cc: tudor.ambarus, andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog
On 05/10/2023 17:55, Peter Griffin wrote:
> Hi folks,
>
> This series adds initial SoC support for the GS101 SoC and also initial board
> support for Pixel 6 phone (Oriole).
>
> The gs101 / Tensor SoC is also used in Pixel6a (bluejay) and Pixel 6 Pro (raven).
> Currently DT is just added for the gs101 SoC and Oriole.
>
> The support added in this series consists of:
> * cpus
> * pinctrl
> * some CCF clock implementation
> * watchdog
> * uart
> * gpio
Hi Peter,
Heads up, in case you are not aware Arm SoC timeframes: we are at rc5,
so it means that anything targeting v6.7 should be applied this working
week, before rc6. At least as ARM SoC is concerned.
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 00/21] Add minimal Tensor/GS101 SoC support and Oriole/Pixel6 board
2023-10-09 11:10 ` Krzysztof Kozlowski
@ 2023-10-09 11:40 ` Peter Griffin
-1 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-09 11:40 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi, tudor.ambarus,
andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog
Hi Krzysztof,
On Mon, 9 Oct 2023 at 12:10, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 05/10/2023 17:55, Peter Griffin wrote:
> > Hi folks,
> >
> > This series adds initial SoC support for the GS101 SoC and also initial board
> > support for Pixel 6 phone (Oriole).
> >
> > The gs101 / Tensor SoC is also used in Pixel6a (bluejay) and Pixel 6 Pro (raven).
> > Currently DT is just added for the gs101 SoC and Oriole.
> >
> > The support added in this series consists of:
> > * cpus
> > * pinctrl
> > * some CCF clock implementation
> > * watchdog
> > * uart
> > * gpio
>
> Hi Peter,
>
> Heads up, in case you are not aware Arm SoC timeframes: we are at rc5,
> so it means that anything targeting v6.7 should be applied this working
> week, before rc6. At least as ARM SoC is concerned.
Thanks for the heads up! I'm just working on v2 now incorporating all the
review feedback. I'm hoping to have that sent out by the end of today or early
tomorrow.
Thanks,
Peter.
^ permalink raw reply [flat|nested] 150+ messages in thread
* Re: [PATCH 00/21] Add minimal Tensor/GS101 SoC support and Oriole/Pixel6 board
@ 2023-10-09 11:40 ` Peter Griffin
0 siblings, 0 replies; 150+ messages in thread
From: Peter Griffin @ 2023-10-09 11:40 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: robh+dt, krzysztof.kozlowski+dt, mturquette, conor+dt, sboyd,
tomasz.figa, s.nawrocki, linus.walleij, wim, linux,
catalin.marinas, will, arnd, olof, cw00.choi, tudor.ambarus,
andre.draszik, semen.protsenko, soc, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-clk, linux-gpio,
linux-watchdog
Hi Krzysztof,
On Mon, 9 Oct 2023 at 12:10, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 05/10/2023 17:55, Peter Griffin wrote:
> > Hi folks,
> >
> > This series adds initial SoC support for the GS101 SoC and also initial board
> > support for Pixel 6 phone (Oriole).
> >
> > The gs101 / Tensor SoC is also used in Pixel6a (bluejay) and Pixel 6 Pro (raven).
> > Currently DT is just added for the gs101 SoC and Oriole.
> >
> > The support added in this series consists of:
> > * cpus
> > * pinctrl
> > * some CCF clock implementation
> > * watchdog
> > * uart
> > * gpio
>
> Hi Peter,
>
> Heads up, in case you are not aware Arm SoC timeframes: we are at rc5,
> so it means that anything targeting v6.7 should be applied this working
> week, before rc6. At least as ARM SoC is concerned.
Thanks for the heads up! I'm just working on v2 now incorporating all the
review feedback. I'm hoping to have that sent out by the end of today or early
tomorrow.
Thanks,
Peter.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 150+ messages in thread