* [U-Boot] [PATCH 1/9] riscv: ax25: Create a simple-bus driver for the soc node
2019-03-19 9:07 [U-Boot] [PATCH 0/9] AE350 SMP support RISC-V Andes
@ 2019-03-19 9:07 ` Andes
2019-03-20 7:22 ` Bin Meng
2019-03-19 9:07 ` [U-Boot] [PATCH 2/9] riscv: Add a SYSCON driver for Andestech's PLIC Andes
` (7 subsequent siblings)
8 siblings, 1 reply; 38+ messages in thread
From: Andes @ 2019-03-19 9:07 UTC (permalink / raw)
To: u-boot
From: Rick Chen <rick@andestech.com>
To enumerate devices on the /soc/ node, create a "simple-bus"
driver to match "andestech,riscv-ae350-soc".
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
---
arch/riscv/cpu/ax25/cpu.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/ax25/cpu.c
index 76689b2..e6e7404 100644
--- a/arch/riscv/cpu/ax25/cpu.c
+++ b/arch/riscv/cpu/ax25/cpu.c
@@ -7,6 +7,7 @@
/* CPU specific code */
#include <common.h>
#include <asm/cache.h>
+#include <dm.h>
/*
* cleanup_before_linux() is called just before we call linux
@@ -25,3 +26,18 @@ int cleanup_before_linux(void)
return 0;
}
+
+/* To enumerate devices on the /soc/ node, create a "simple-bus" driver */
+static const struct udevice_id riscv_ae350_soc_ids[] = {
+ {
+ .compatible = "andestech,riscv-ae350-soc",
+ },
+ { }
+};
+
+U_BOOT_DRIVER(riscv_ae350_soc_ids) = {
+ .name = "andestech,riscv-ae350-soc",
+ .id = UCLASS_SIMPLE_BUS,
+ .of_match = riscv_ae350_soc_ids,
+ .flags = DM_FLAG_PRE_RELOC,
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH 1/9] riscv: ax25: Create a simple-bus driver for the soc node
2019-03-19 9:07 ` [U-Boot] [PATCH 1/9] riscv: ax25: Create a simple-bus driver for the soc node Andes
@ 2019-03-20 7:22 ` Bin Meng
2019-03-21 6:49 ` Rick Chen
0 siblings, 1 reply; 38+ messages in thread
From: Bin Meng @ 2019-03-20 7:22 UTC (permalink / raw)
To: u-boot
Hi Rick,
On Tue, Mar 19, 2019 at 5:11 PM Andes <uboot@andestech.com> wrote:
>
> From: Rick Chen <rick@andestech.com>
>
> To enumerate devices on the /soc/ node, create a "simple-bus"
> driver to match "andestech,riscv-ae350-soc".
>
Could we change the /soc/ node compatible string to "simple-bus"
instead? The QEMU 'virt' created a bad example and we should stop the
contamination.
> Signed-off-by: Rick Chen <rick@andestech.com>
> Cc: Greentime Hu <greentime@andestech.com>
> ---
> arch/riscv/cpu/ax25/cpu.c | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
Regards,
Bin
^ permalink raw reply [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH 1/9] riscv: ax25: Create a simple-bus driver for the soc node
2019-03-20 7:22 ` Bin Meng
@ 2019-03-21 6:49 ` Rick Chen
2019-03-21 7:01 ` Bin Meng
0 siblings, 1 reply; 38+ messages in thread
From: Rick Chen @ 2019-03-21 6:49 UTC (permalink / raw)
To: u-boot
Hi Bin
Bin Meng <bmeng.cn@gmail.com> 於 2019年3月20日 週三 下午3:22寫道:
>
> Hi Rick,
>
> On Tue, Mar 19, 2019 at 5:11 PM Andes <uboot@andestech.com> wrote:
> >
> > From: Rick Chen <rick@andestech.com>
> >
> > To enumerate devices on the /soc/ node, create a "simple-bus"
> > driver to match "andestech,riscv-ae350-soc".
> >
>
> Could we change the /soc/ node compatible string to "simple-bus"
> instead? The QEMU 'virt' created a bad example and we should stop the
> contamination.
>
Do you mean change the
.compatible = "andestech,riscv-ae350-soc",
as "simple-bus" ???
I don't understand it.
Can you explain more clearly
Thanks
Rick
> > Signed-off-by: Rick Chen <rick@andestech.com>
> > Cc: Greentime Hu <greentime@andestech.com>
> > ---
> > arch/riscv/cpu/ax25/cpu.c | 16 ++++++++++++++++
> > 1 file changed, 16 insertions(+)
> >
>
> Regards,
> Bin
^ permalink raw reply [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH 1/9] riscv: ax25: Create a simple-bus driver for the soc node
2019-03-21 6:49 ` Rick Chen
@ 2019-03-21 7:01 ` Bin Meng
2019-03-21 8:28 ` Rick Chen
0 siblings, 1 reply; 38+ messages in thread
From: Bin Meng @ 2019-03-21 7:01 UTC (permalink / raw)
To: u-boot
Hi Rick,
On Thu, Mar 21, 2019 at 2:49 PM Rick Chen <rickchen36@gmail.com> wrote:
>
> Hi Bin
>
> Bin Meng <bmeng.cn@gmail.com> 於 2019年3月20日 週三 下午3:22寫道:
> >
> > Hi Rick,
> >
> > On Tue, Mar 19, 2019 at 5:11 PM Andes <uboot@andestech.com> wrote:
> > >
> > > From: Rick Chen <rick@andestech.com>
> > >
> > > To enumerate devices on the /soc/ node, create a "simple-bus"
> > > driver to match "andestech,riscv-ae350-soc".
> > >
> >
> > Could we change the /soc/ node compatible string to "simple-bus"
> > instead? The QEMU 'virt' created a bad example and we should stop the
> > contamination.
> >
>
> Do you mean change the
> .compatible = "andestech,riscv-ae350-soc",
> as "simple-bus" ???
Yes, I mean changing the /soc/ node compatible string in
arch/riscv/dts/ae350_{32,64}.dts to "simpble-bus".
>
> I don't understand it.
> Can you explain more clearly
>
Regards,
Bin
^ permalink raw reply [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH 1/9] riscv: ax25: Create a simple-bus driver for the soc node
2019-03-21 7:01 ` Bin Meng
@ 2019-03-21 8:28 ` Rick Chen
2019-03-21 8:49 ` Bin Meng
0 siblings, 1 reply; 38+ messages in thread
From: Rick Chen @ 2019-03-21 8:28 UTC (permalink / raw)
To: u-boot
Hi Bin
Bin Meng <bmeng.cn@gmail.com> 於 2019年3月21日 週四 下午3:01寫道:
>
> Hi Rick,
>
> On Thu, Mar 21, 2019 at 2:49 PM Rick Chen <rickchen36@gmail.com> wrote:
> >
> > Hi Bin
> >
> > Bin Meng <bmeng.cn@gmail.com> 於 2019年3月20日 週三 下午3:22寫道:
> > >
> > > Hi Rick,
> > >
> > > On Tue, Mar 19, 2019 at 5:11 PM Andes <uboot@andestech.com> wrote:
> > > >
> > > > From: Rick Chen <rick@andestech.com>
> > > >
> > > > To enumerate devices on the /soc/ node, create a "simple-bus"
> > > > driver to match "andestech,riscv-ae350-soc".
> > > >
> > >
> > > Could we change the /soc/ node compatible string to "simple-bus"
> > > instead? The QEMU 'virt' created a bad example and we should stop the
> > > contamination.
> > >
> >
> > Do you mean change the
> > .compatible = "andestech,riscv-ae350-soc",
> > as "simple-bus" ???
>
> Yes, I mean changing the /soc/ node compatible string in
> arch/riscv/dts/ae350_{32,64}.dts to "simpble-bus".
>
So you mean we shall have only riscv simple bus driver.
We shall remove
U_BOOT_DRIVER(riscv_virtio_soc) in /arch/riscv/cpu/generic/cpu.c
U_BOOT_DRIVER(riscv_ae350_soc_ids) in /arch/riscv/cpu/ax25/cpu.c
and add
static const struct udevice_id riscv_simple_bus_ids[] = {
{
.compatible = "simple-bus",
},
{ }
};
U_BOOT_DRIVER(riscv_simple_bus_ids) = {
.name = "simple-bus",
.id = UCLASS_SIMPLE_BUS,
.of_match = riscv_simple_bus_ids,
.flags = DM_FLAG_PRE_RELOC,
};
Does it right ?
Rick
> >
> > I don't understand it.
> > Can you explain more clearly
> >
>
> Regards,
> Bin
^ permalink raw reply [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH 1/9] riscv: ax25: Create a simple-bus driver for the soc node
2019-03-21 8:28 ` Rick Chen
@ 2019-03-21 8:49 ` Bin Meng
2019-03-21 9:01 ` Rick Chen
0 siblings, 1 reply; 38+ messages in thread
From: Bin Meng @ 2019-03-21 8:49 UTC (permalink / raw)
To: u-boot
Hi Rick,
On Thu, Mar 21, 2019 at 4:27 PM Rick Chen <rickchen36@gmail.com> wrote:
>
> Hi Bin
>
> Bin Meng <bmeng.cn@gmail.com> 於 2019年3月21日 週四 下午3:01寫道:
> >
> > Hi Rick,
> >
> > On Thu, Mar 21, 2019 at 2:49 PM Rick Chen <rickchen36@gmail.com> wrote:
> > >
> > > Hi Bin
> > >
> > > Bin Meng <bmeng.cn@gmail.com> 於 2019年3月20日 週三 下午3:22寫道:
> > > >
> > > > Hi Rick,
> > > >
> > > > On Tue, Mar 19, 2019 at 5:11 PM Andes <uboot@andestech.com> wrote:
> > > > >
> > > > > From: Rick Chen <rick@andestech.com>
> > > > >
> > > > > To enumerate devices on the /soc/ node, create a "simple-bus"
> > > > > driver to match "andestech,riscv-ae350-soc".
> > > > >
> > > >
> > > > Could we change the /soc/ node compatible string to "simple-bus"
> > > > instead? The QEMU 'virt' created a bad example and we should stop the
> > > > contamination.
> > > >
> > >
> > > Do you mean change the
> > > .compatible = "andestech,riscv-ae350-soc",
> > > as "simple-bus" ???
> >
> > Yes, I mean changing the /soc/ node compatible string in
> > arch/riscv/dts/ae350_{32,64}.dts to "simpble-bus".
> >
>
> So you mean we shall have only riscv simple bus driver.
> We shall remove
> U_BOOT_DRIVER(riscv_virtio_soc) in /arch/riscv/cpu/generic/cpu.c
> U_BOOT_DRIVER(riscv_ae350_soc_ids) in /arch/riscv/cpu/ax25/cpu.c
> and add
> static const struct udevice_id riscv_simple_bus_ids[] = {
> {
> .compatible = "simple-bus",
> },
> { }
> };
>
> U_BOOT_DRIVER(riscv_simple_bus_ids) = {
> .name = "simple-bus",
> .id = UCLASS_SIMPLE_BUS,
> .of_match = riscv_simple_bus_ids,
> .flags = DM_FLAG_PRE_RELOC,
> };
>
> Does it right ?
No, you don't need add anything to the RISC-V codes. U-Boot provides a
simple-bus driver and all you need do is to use "simple-bus" in your
DTS files.
Regards,
Bin
^ permalink raw reply [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH 1/9] riscv: ax25: Create a simple-bus driver for the soc node
2019-03-21 8:49 ` Bin Meng
@ 2019-03-21 9:01 ` Rick Chen
2019-03-21 9:16 ` Bin Meng
0 siblings, 1 reply; 38+ messages in thread
From: Rick Chen @ 2019-03-21 9:01 UTC (permalink / raw)
To: u-boot
Bin Meng <bmeng.cn@gmail.com> 於 2019年3月21日 週四 下午4:49寫道:
>
> Hi Rick,
>
> On Thu, Mar 21, 2019 at 4:27 PM Rick Chen <rickchen36@gmail.com> wrote:
> >
> > Hi Bin
> >
> > Bin Meng <bmeng.cn@gmail.com> 於 2019年3月21日 週四 下午3:01寫道:
> > >
> > > Hi Rick,
> > >
> > > On Thu, Mar 21, 2019 at 2:49 PM Rick Chen <rickchen36@gmail.com> wrote:
> > > >
> > > > Hi Bin
> > > >
> > > > Bin Meng <bmeng.cn@gmail.com> 於 2019年3月20日 週三 下午3:22寫道:
> > > > >
> > > > > Hi Rick,
> > > > >
> > > > > On Tue, Mar 19, 2019 at 5:11 PM Andes <uboot@andestech.com> wrote:
> > > > > >
> > > > > > From: Rick Chen <rick@andestech.com>
> > > > > >
> > > > > > To enumerate devices on the /soc/ node, create a "simple-bus"
> > > > > > driver to match "andestech,riscv-ae350-soc".
> > > > > >
> > > > >
> > > > > Could we change the /soc/ node compatible string to "simple-bus"
> > > > > instead? The QEMU 'virt' created a bad example and we should stop the
> > > > > contamination.
> > > > >
> > > >
> > > > Do you mean change the
> > > > .compatible = "andestech,riscv-ae350-soc",
> > > > as "simple-bus" ???
> > >
> > > Yes, I mean changing the /soc/ node compatible string in
> > > arch/riscv/dts/ae350_{32,64}.dts to "simpble-bus".
> > >
> >
> > So you mean we shall have only riscv simple bus driver.
> > We shall remove
> > U_BOOT_DRIVER(riscv_virtio_soc) in /arch/riscv/cpu/generic/cpu.c
> > U_BOOT_DRIVER(riscv_ae350_soc_ids) in /arch/riscv/cpu/ax25/cpu.c
> > and add
> > static const struct udevice_id riscv_simple_bus_ids[] = {
> > {
> > .compatible = "simple-bus",
> > },
> > { }
> > };
> >
> > U_BOOT_DRIVER(riscv_simple_bus_ids) = {
> > .name = "simple-bus",
> > .id = UCLASS_SIMPLE_BUS,
> > .of_match = riscv_simple_bus_ids,
> > .flags = DM_FLAG_PRE_RELOC,
> > };
> >
> > Does it right ?
>
> No, you don't need add anything to the RISC-V codes. U-Boot provides a
> simple-bus driver and all you need do is to use "simple-bus" in your
> DTS files.
>
But if I only use "simple-bus" in DTS file.
It will fail in syscon_get_first_range that can not get correct
information from reg.
> Regards,
> Bin
^ permalink raw reply [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH 1/9] riscv: ax25: Create a simple-bus driver for the soc node
2019-03-21 9:01 ` Rick Chen
@ 2019-03-21 9:16 ` Bin Meng
2019-04-10 9:05 ` Rick Chen
0 siblings, 1 reply; 38+ messages in thread
From: Bin Meng @ 2019-03-21 9:16 UTC (permalink / raw)
To: u-boot
Hi Rick,
On Thu, Mar 21, 2019 at 5:00 PM Rick Chen <rickchen36@gmail.com> wrote:
>
> Bin Meng <bmeng.cn@gmail.com> 於 2019年3月21日 週四 下午4:49寫道:
> >
> > Hi Rick,
> >
> > On Thu, Mar 21, 2019 at 4:27 PM Rick Chen <rickchen36@gmail.com> wrote:
> > >
> > > Hi Bin
> > >
> > > Bin Meng <bmeng.cn@gmail.com> 於 2019年3月21日 週四 下午3:01寫道:
> > > >
> > > > Hi Rick,
> > > >
> > > > On Thu, Mar 21, 2019 at 2:49 PM Rick Chen <rickchen36@gmail.com> wrote:
> > > > >
> > > > > Hi Bin
> > > > >
> > > > > Bin Meng <bmeng.cn@gmail.com> 於 2019年3月20日 週三 下午3:22寫道:
> > > > > >
> > > > > > Hi Rick,
> > > > > >
> > > > > > On Tue, Mar 19, 2019 at 5:11 PM Andes <uboot@andestech.com> wrote:
> > > > > > >
> > > > > > > From: Rick Chen <rick@andestech.com>
> > > > > > >
> > > > > > > To enumerate devices on the /soc/ node, create a "simple-bus"
> > > > > > > driver to match "andestech,riscv-ae350-soc".
> > > > > > >
> > > > > >
> > > > > > Could we change the /soc/ node compatible string to "simple-bus"
> > > > > > instead? The QEMU 'virt' created a bad example and we should stop the
> > > > > > contamination.
> > > > > >
> > > > >
> > > > > Do you mean change the
> > > > > .compatible = "andestech,riscv-ae350-soc",
> > > > > as "simple-bus" ???
> > > >
> > > > Yes, I mean changing the /soc/ node compatible string in
> > > > arch/riscv/dts/ae350_{32,64}.dts to "simpble-bus".
> > > >
> > >
> > > So you mean we shall have only riscv simple bus driver.
> > > We shall remove
> > > U_BOOT_DRIVER(riscv_virtio_soc) in /arch/riscv/cpu/generic/cpu.c
> > > U_BOOT_DRIVER(riscv_ae350_soc_ids) in /arch/riscv/cpu/ax25/cpu.c
> > > and add
> > > static const struct udevice_id riscv_simple_bus_ids[] = {
> > > {
> > > .compatible = "simple-bus",
> > > },
> > > { }
> > > };
> > >
> > > U_BOOT_DRIVER(riscv_simple_bus_ids) = {
> > > .name = "simple-bus",
> > > .id = UCLASS_SIMPLE_BUS,
> > > .of_match = riscv_simple_bus_ids,
> > > .flags = DM_FLAG_PRE_RELOC,
> > > };
> > >
> > > Does it right ?
> >
> > No, you don't need add anything to the RISC-V codes. U-Boot provides a
> > simple-bus driver and all you need do is to use "simple-bus" in your
> > DTS files.
> >
>
> But if I only use "simple-bus" in DTS file.
> It will fail in syscon_get_first_range that can not get correct
> information from reg.
Yes, we should fix "simple-bus" driver. See discussion in
https://patchwork.ozlabs.org/patch/1039493/
Regards,
Bin
^ permalink raw reply [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH 1/9] riscv: ax25: Create a simple-bus driver for the soc node
2019-03-21 9:16 ` Bin Meng
@ 2019-04-10 9:05 ` Rick Chen
2019-04-10 9:21 ` Auer, Lukas
0 siblings, 1 reply; 38+ messages in thread
From: Rick Chen @ 2019-04-10 9:05 UTC (permalink / raw)
To: u-boot
Hi Bin and Lukas
Bin Meng <bmeng.cn@gmail.com> 於 2019年3月21日 週四 下午5:17寫道:
>
> Hi Rick,
>
> On Thu, Mar 21, 2019 at 5:00 PM Rick Chen <rickchen36@gmail.com> wrote:
> >
> > Bin Meng <bmeng.cn@gmail.com> 於 2019年3月21日 週四 下午4:49寫道:
> > >
> > > Hi Rick,
> > >
> > > On Thu, Mar 21, 2019 at 4:27 PM Rick Chen <rickchen36@gmail.com> wrote:
> > > >
> > > > Hi Bin
> > > >
> > > > Bin Meng <bmeng.cn@gmail.com> 於 2019年3月21日 週四 下午3:01寫道:
> > > > >
> > > > > Hi Rick,
> > > > >
> > > > > On Thu, Mar 21, 2019 at 2:49 PM Rick Chen <rickchen36@gmail.com> wrote:
> > > > > >
> > > > > > Hi Bin
> > > > > >
> > > > > > Bin Meng <bmeng.cn@gmail.com> 於 2019年3月20日 週三 下午3:22寫道:
> > > > > > >
> > > > > > > Hi Rick,
> > > > > > >
> > > > > > > On Tue, Mar 19, 2019 at 5:11 PM Andes <uboot@andestech.com> wrote:
> > > > > > > >
> > > > > > > > From: Rick Chen <rick@andestech.com>
> > > > > > > >
> > > > > > > > To enumerate devices on the /soc/ node, create a "simple-bus"
> > > > > > > > driver to match "andestech,riscv-ae350-soc".
> > > > > > > >
> > > > > > >
> > > > > > > Could we change the /soc/ node compatible string to "simple-bus"
> > > > > > > instead? The QEMU 'virt' created a bad example and we should stop the
> > > > > > > contamination.
> > > > > > >
> > > > > >
> > > > > > Do you mean change the
> > > > > > .compatible = "andestech,riscv-ae350-soc",
> > > > > > as "simple-bus" ???
> > > > >
> > > > > Yes, I mean changing the /soc/ node compatible string in
> > > > > arch/riscv/dts/ae350_{32,64}.dts to "simpble-bus".
> > > > >
> > > >
> > > > So you mean we shall have only riscv simple bus driver.
> > > > We shall remove
> > > > U_BOOT_DRIVER(riscv_virtio_soc) in /arch/riscv/cpu/generic/cpu.c
> > > > U_BOOT_DRIVER(riscv_ae350_soc_ids) in /arch/riscv/cpu/ax25/cpu.c
> > > > and add
> > > > static const struct udevice_id riscv_simple_bus_ids[] = {
> > > > {
> > > > .compatible = "simple-bus",
> > > > },
> > > > { }
> > > > };
> > > >
> > > > U_BOOT_DRIVER(riscv_simple_bus_ids) = {
> > > > .name = "simple-bus",
> > > > .id = UCLASS_SIMPLE_BUS,
> > > > .of_match = riscv_simple_bus_ids,
> > > > .flags = DM_FLAG_PRE_RELOC,
> > > > };
> > > >
> > > > Does it right ?
> > >
> > > No, you don't need add anything to the RISC-V codes. U-Boot provides a
> > > simple-bus driver and all you need do is to use "simple-bus" in your
> > > DTS files.
> > >
> >
> > But if I only use "simple-bus" in DTS file.
> > It will fail in syscon_get_first_range that can not get correct
> > information from reg.
>
> Yes, we should fix "simple-bus" driver. See discussion in
> https://patchwork.ozlabs.org/patch/1039493/
The series has been pull into master by Tom.
Can you fix the "simple-bus" driver ASAP.
AE350 will encounter the problem as below with the latest u-boot-riscv
U-Boot 2019.04-rc4-07392-g48b90d9 (Apr 10 2019 - 16:27:39 +0800)
DRAM: 1 GiB
Cannot send IPI to hart 1
Relocation of secondary harts has failed, error -19
### ERROR ### Please RESET the board ###
Thanks
Rick
>
> Regards,
> Bin
^ permalink raw reply [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH 1/9] riscv: ax25: Create a simple-bus driver for the soc node
2019-04-10 9:05 ` Rick Chen
@ 2019-04-10 9:21 ` Auer, Lukas
2019-04-10 9:30 ` Rick Chen
0 siblings, 1 reply; 38+ messages in thread
From: Auer, Lukas @ 2019-04-10 9:21 UTC (permalink / raw)
To: u-boot
Hi Rick,
On Wed, 2019-04-10 at 17:05 +0800, Rick Chen wrote:
> Hi Bin and Lukas
>
> Bin Meng <bmeng.cn@gmail.com> 於 2019年3月21日 週四 下午5:17寫道:
> > Hi Rick,
> >
> > On Thu, Mar 21, 2019 at 5:00 PM Rick Chen <rickchen36@gmail.com> wrote:
> > > Bin Meng <bmeng.cn@gmail.com> 於 2019年3月21日 週四 下午4:49寫道:
> > > > Hi Rick,
> > > >
> > > > On Thu, Mar 21, 2019 at 4:27 PM Rick Chen <rickchen36@gmail.com> wrote:
> > > > > Hi Bin
> > > > >
> > > > > Bin Meng <bmeng.cn@gmail.com> 於 2019年3月21日 週四 下午3:01寫道:
> > > > > > Hi Rick,
> > > > > >
> > > > > > On Thu, Mar 21, 2019 at 2:49 PM Rick Chen <rickchen36@gmail.com> wrote:
> > > > > > > Hi Bin
> > > > > > >
> > > > > > > Bin Meng <bmeng.cn@gmail.com> 於 2019年3月20日 週三 下午3:22寫道:
> > > > > > > > Hi Rick,
> > > > > > > >
> > > > > > > > On Tue, Mar 19, 2019 at 5:11 PM Andes <uboot@andestech.com> wrote:
> > > > > > > > > From: Rick Chen <rick@andestech.com>
> > > > > > > > >
> > > > > > > > > To enumerate devices on the /soc/ node, create a "simple-bus"
> > > > > > > > > driver to match "andestech,riscv-ae350-soc".
> > > > > > > > >
> > > > > > > >
> > > > > > > > Could we change the /soc/ node compatible string to "simple-bus"
> > > > > > > > instead? The QEMU 'virt' created a bad example and we should stop the
> > > > > > > > contamination.
> > > > > > > >
> > > > > > >
> > > > > > > Do you mean change the
> > > > > > > .compatible = "andestech,riscv-ae350-soc",
> > > > > > > as "simple-bus" ???
> > > > > >
> > > > > > Yes, I mean changing the /soc/ node compatible string in
> > > > > > arch/riscv/dts/ae350_{32,64}.dts to "simpble-bus".
> > > > > >
> > > > >
> > > > > So you mean we shall have only riscv simple bus driver.
> > > > > We shall remove
> > > > > U_BOOT_DRIVER(riscv_virtio_soc) in /arch/riscv/cpu/generic/cpu.c
> > > > > U_BOOT_DRIVER(riscv_ae350_soc_ids) in /arch/riscv/cpu/ax25/cpu.c
> > > > > and add
> > > > > static const struct udevice_id riscv_simple_bus_ids[] = {
> > > > > {
> > > > > .compatible = "simple-bus",
> > > > > },
> > > > > { }
> > > > > };
> > > > >
> > > > > U_BOOT_DRIVER(riscv_simple_bus_ids) = {
> > > > > .name = "simple-bus",
> > > > > .id = UCLASS_SIMPLE_BUS,
> > > > > .of_match = riscv_simple_bus_ids,
> > > > > .flags = DM_FLAG_PRE_RELOC,
> > > > > };
> > > > >
> > > > > Does it right ?
> > > >
> > > > No, you don't need add anything to the RISC-V codes. U-Boot provides a
> > > > simple-bus driver and all you need do is to use "simple-bus" in your
> > > > DTS files.
> > > >
> > >
> > > But if I only use "simple-bus" in DTS file.
> > > It will fail in syscon_get_first_range that can not get correct
> > > information from reg.
> >
> > Yes, we should fix "simple-bus" driver. See discussion in
> > https://patchwork.ozlabs.org/patch/1039493/
>
> The series has been pull into master by Tom.
>
> Can you fix the "simple-bus" driver ASAP.
> AE350 will encounter the problem as below with the latest u-boot-riscv
>
> U-Boot 2019.04-rc4-07392-g48b90d9 (Apr 10 2019 - 16:27:39 +0800)
>
> DRAM: 1 GiB
> Cannot send IPI to hart 1
> Relocation of secondary harts has failed, error -19
> ### ERROR ### Please RESET the board ###
>
Yes, I will send the patch later today.
Thanks,
Lukas
^ permalink raw reply [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH 1/9] riscv: ax25: Create a simple-bus driver for the soc node
2019-04-10 9:21 ` Auer, Lukas
@ 2019-04-10 9:30 ` Rick Chen
0 siblings, 0 replies; 38+ messages in thread
From: Rick Chen @ 2019-04-10 9:30 UTC (permalink / raw)
To: u-boot
Hi Lukas
Auer, Lukas <lukas.auer@aisec.fraunhofer.de> 於 2019年4月10日 週三 下午5:21寫道:
>
> Hi Rick,
>
> On Wed, 2019-04-10 at 17:05 +0800, Rick Chen wrote:
> > Hi Bin and Lukas
> >
> > Bin Meng <bmeng.cn@gmail.com> 於 2019年3月21日 週四 下午5:17寫道:
> > > Hi Rick,
> > >
> > > On Thu, Mar 21, 2019 at 5:00 PM Rick Chen <rickchen36@gmail.com> wrote:
> > > > Bin Meng <bmeng.cn@gmail.com> 於 2019年3月21日 週四 下午4:49寫道:
> > > > > Hi Rick,
> > > > >
> > > > > On Thu, Mar 21, 2019 at 4:27 PM Rick Chen <rickchen36@gmail.com> wrote:
> > > > > > Hi Bin
> > > > > >
> > > > > > Bin Meng <bmeng.cn@gmail.com> 於 2019年3月21日 週四 下午3:01寫道:
> > > > > > > Hi Rick,
> > > > > > >
> > > > > > > On Thu, Mar 21, 2019 at 2:49 PM Rick Chen <rickchen36@gmail.com> wrote:
> > > > > > > > Hi Bin
> > > > > > > >
> > > > > > > > Bin Meng <bmeng.cn@gmail.com> 於 2019年3月20日 週三 下午3:22寫道:
> > > > > > > > > Hi Rick,
> > > > > > > > >
> > > > > > > > > On Tue, Mar 19, 2019 at 5:11 PM Andes <uboot@andestech.com> wrote:
> > > > > > > > > > From: Rick Chen <rick@andestech.com>
> > > > > > > > > >
> > > > > > > > > > To enumerate devices on the /soc/ node, create a "simple-bus"
> > > > > > > > > > driver to match "andestech,riscv-ae350-soc".
> > > > > > > > > >
> > > > > > > > >
> > > > > > > > > Could we change the /soc/ node compatible string to "simple-bus"
> > > > > > > > > instead? The QEMU 'virt' created a bad example and we should stop the
> > > > > > > > > contamination.
> > > > > > > > >
> > > > > > > >
> > > > > > > > Do you mean change the
> > > > > > > > .compatible = "andestech,riscv-ae350-soc",
> > > > > > > > as "simple-bus" ???
> > > > > > >
> > > > > > > Yes, I mean changing the /soc/ node compatible string in
> > > > > > > arch/riscv/dts/ae350_{32,64}.dts to "simpble-bus".
> > > > > > >
> > > > > >
> > > > > > So you mean we shall have only riscv simple bus driver.
> > > > > > We shall remove
> > > > > > U_BOOT_DRIVER(riscv_virtio_soc) in /arch/riscv/cpu/generic/cpu.c
> > > > > > U_BOOT_DRIVER(riscv_ae350_soc_ids) in /arch/riscv/cpu/ax25/cpu.c
> > > > > > and add
> > > > > > static const struct udevice_id riscv_simple_bus_ids[] = {
> > > > > > {
> > > > > > .compatible = "simple-bus",
> > > > > > },
> > > > > > { }
> > > > > > };
> > > > > >
> > > > > > U_BOOT_DRIVER(riscv_simple_bus_ids) = {
> > > > > > .name = "simple-bus",
> > > > > > .id = UCLASS_SIMPLE_BUS,
> > > > > > .of_match = riscv_simple_bus_ids,
> > > > > > .flags = DM_FLAG_PRE_RELOC,
> > > > > > };
> > > > > >
> > > > > > Does it right ?
> > > > >
> > > > > No, you don't need add anything to the RISC-V codes. U-Boot provides a
> > > > > simple-bus driver and all you need do is to use "simple-bus" in your
> > > > > DTS files.
> > > > >
> > > >
> > > > But if I only use "simple-bus" in DTS file.
> > > > It will fail in syscon_get_first_range that can not get correct
> > > > information from reg.
> > >
> > > Yes, we should fix "simple-bus" driver. See discussion in
> > > https://patchwork.ozlabs.org/patch/1039493/
> >
> > The series has been pull into master by Tom.
> >
> > Can you fix the "simple-bus" driver ASAP.
> > AE350 will encounter the problem as below with the latest u-boot-riscv
> >
> > U-Boot 2019.04-rc4-07392-g48b90d9 (Apr 10 2019 - 16:27:39 +0800)
> >
> > DRAM: 1 GiB
> > Cannot send IPI to hart 1
> > Relocation of secondary harts has failed, error -19
> > ### ERROR ### Please RESET the board ###
> >
>
> Yes, I will send the patch later today.
Thanks a lot.
Sincerely,
Rick
>
> Thanks,
> Lukas
^ permalink raw reply [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH 2/9] riscv: Add a SYSCON driver for Andestech's PLIC
2019-03-19 9:07 [U-Boot] [PATCH 0/9] AE350 SMP support RISC-V Andes
2019-03-19 9:07 ` [U-Boot] [PATCH 1/9] riscv: ax25: Create a simple-bus driver for the soc node Andes
@ 2019-03-19 9:07 ` Andes
2019-03-20 7:22 ` Bin Meng
2019-03-19 9:07 ` [U-Boot] [PATCH 3/9] riscv: Add a SYSCON driver for Andestech's PLMT Andes
` (6 subsequent siblings)
8 siblings, 1 reply; 38+ messages in thread
From: Andes @ 2019-03-19 9:07 UTC (permalink / raw)
To: u-boot
From: Rick Chen <rick@andestech.com>
The Platform-Level Interrupt Controller(PLIC)
block holds memory-mapped claim and pending registers
associated with software interrupt.It is required
for handling IPI.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
---
arch/riscv/Kconfig | 9 ++++
arch/riscv/include/asm/global_data.h | 3 ++
arch/riscv/include/asm/syscon.h | 2 +-
arch/riscv/lib/Makefile | 1 +
arch/riscv/lib/nds_plic.c | 84 ++++++++++++++++++++++++++++++++++++
5 files changed, 98 insertions(+), 1 deletion(-)
create mode 100644 arch/riscv/lib/nds_plic.c
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 3a4470d..fef11dd 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -109,6 +109,15 @@ config SIFIVE_CLINT
The SiFive CLINT block holds memory-mapped control and status registers
associated with software and timer interrupts.
+config NDS_PLIC
+ bool
+ depends on RISCV_MMODE
+ select REGMAP
+ select SYSCON
+ help
+ The Andes PLIC block holds memory-mapped claim and pending registers
+ associated with software interrupt.
+
config RISCV_RDTIME
bool
default y if RISCV_SMODE
diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h
index 80e3165..15867f5 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -18,6 +18,9 @@ struct arch_global_data {
#ifdef CONFIG_SIFIVE_CLINT
void __iomem *clint; /* clint base address */
#endif
+#ifdef CONFIG_NDS_PLIC
+ void __iomem *plic; /* plic base address */
+#endif
#ifdef CONFIG_SMP
struct ipi_data ipi[CONFIG_NR_CPUS];
#endif
diff --git a/arch/riscv/include/asm/syscon.h b/arch/riscv/include/asm/syscon.h
index d311ee6..0229989 100644
--- a/arch/riscv/include/asm/syscon.h
+++ b/arch/riscv/include/asm/syscon.h
@@ -9,11 +9,11 @@
/*
* System controllers in a RISC-V system
*
- * So far only SiFive's Core Local Interruptor (CLINT) is defined.
*/
enum {
RISCV_NONE,
RISCV_SYSCON_CLINT, /* Core Local Interruptor (CLINT) */
+ RISCV_SYSCON_PLIC, /* Platform Level Interrup Controller (PLIC) */
};
#endif /* _ASM_SYSCON_H */
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index 35dbf64..8187c2b 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_CMD_GO) += boot.o
obj-y += cache.o
obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
+obj-$(CONFIG_NDS_PLIC) += nds_plic.o
obj-y += interrupts.o
obj-y += reset.o
obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
diff --git a/arch/riscv/lib/nds_plic.c b/arch/riscv/lib/nds_plic.c
new file mode 100644
index 0000000..563da7d
--- /dev/null
+++ b/arch/riscv/lib/nds_plic.c
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019, Rick Chen <rick@andestech.com>
+ *
+ * U-Boot syscon driver for Andes's Platform Level Interrupt Controller (PLIC).
+ * The PLIC block holds memory-mapped claim and pending registers
+ * associated with software interrupt.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/syscon.h>
+
+/* pending register */
+#define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + (hart) * 8)
+/* enable register */
+#define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80)
+/* claim register */
+#define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define PLIC_BASE_GET(void) \
+ do { \
+ long *ret; \
+ \
+ if (!gd->arch.plic) { \
+ ret = syscon_get_first_range(RISCV_SYSCON_PLIC); \
+ if (IS_ERR(ret)) \
+ return PTR_ERR(ret); \
+ gd->arch.plic = ret; \
+ } \
+ } while (0)
+
+int plic_init(int harts)
+{
+ int i;
+ int en = 0x80808080;
+
+ PLIC_BASE_GET();
+ for(i=0;i<harts;i++)
+ {
+ en = en >> i;
+ writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, i));
+ }
+
+ return 0;
+}
+
+int riscv_send_ipi(int hart)
+{
+ PLIC_BASE_GET();
+
+ writel((0x80>>hart), (void __iomem *)PENDING_REG(gd->arch.plic, gd->arch.boot_hart));
+
+ return 0;
+}
+
+int riscv_clear_ipi(int hart)
+{
+ u32 source_id;
+
+ PLIC_BASE_GET();
+
+ source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart));
+ writel(source_id, (void __iomem *)CLAIM_REG(gd->arch.plic, hart));
+
+ return 0;
+}
+
+static const struct udevice_id nds_plic_ids[] = {
+ { .compatible = "riscv,plic1", .data = RISCV_SYSCON_PLIC },
+ { }
+};
+
+U_BOOT_DRIVER(nds_plic) = {
+ .name = "nds_plic",
+ .id = UCLASS_SYSCON,
+ .of_match = nds_plic_ids,
+ .flags = DM_FLAG_PRE_RELOC,
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH 2/9] riscv: Add a SYSCON driver for Andestech's PLIC
2019-03-19 9:07 ` [U-Boot] [PATCH 2/9] riscv: Add a SYSCON driver for Andestech's PLIC Andes
@ 2019-03-20 7:22 ` Bin Meng
2019-03-21 7:04 ` Rick Chen
0 siblings, 1 reply; 38+ messages in thread
From: Bin Meng @ 2019-03-20 7:22 UTC (permalink / raw)
To: u-boot
Hi Rick,
On Tue, Mar 19, 2019 at 5:12 PM Andes <uboot@andestech.com> wrote:
>
> From: Rick Chen <rick@andestech.com>
>
> The Platform-Level Interrupt Controller(PLIC)
> block holds memory-mapped claim and pending registers
> associated with software interrupt.It is required
nits: need one space after interrupt.
> for handling IPI.
>
> Signed-off-by: Rick Chen <rick@andestech.com>
> Cc: Greentime Hu <greentime@andestech.com>
> ---
> arch/riscv/Kconfig | 9 ++++
> arch/riscv/include/asm/global_data.h | 3 ++
> arch/riscv/include/asm/syscon.h | 2 +-
> arch/riscv/lib/Makefile | 1 +
> arch/riscv/lib/nds_plic.c | 84 ++++++++++++++++++++++++++++++++++++
> 5 files changed, 98 insertions(+), 1 deletion(-)
> create mode 100644 arch/riscv/lib/nds_plic.c
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 3a4470d..fef11dd 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
Probably it makes more sense to put this to arch/riscv/cpu/ax25/Kconfig?
> @@ -109,6 +109,15 @@ config SIFIVE_CLINT
> The SiFive CLINT block holds memory-mapped control and status registers
> associated with software and timer interrupts.
>
> +config NDS_PLIC
I am not sure if it is appropriate to call this "NDS_PLIC". Shouldn't
it be "ANDES_PLIC", because ANDES_ and SIFIVE_ are vendor prefixes.
> + bool
> + depends on RISCV_MMODE
> + select REGMAP
> + select SYSCON
> + help
> + The Andes PLIC block holds memory-mapped claim and pending registers
> + associated with software interrupt.
> +
> config RISCV_RDTIME
> bool
> default y if RISCV_SMODE
> diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h
> index 80e3165..15867f5 100644
> --- a/arch/riscv/include/asm/global_data.h
> +++ b/arch/riscv/include/asm/global_data.h
> @@ -18,6 +18,9 @@ struct arch_global_data {
> #ifdef CONFIG_SIFIVE_CLINT
> void __iomem *clint; /* clint base address */
> #endif
> +#ifdef CONFIG_NDS_PLIC
> + void __iomem *plic; /* plic base address */
> +#endif
> #ifdef CONFIG_SMP
> struct ipi_data ipi[CONFIG_NR_CPUS];
> #endif
> diff --git a/arch/riscv/include/asm/syscon.h b/arch/riscv/include/asm/syscon.h
> index d311ee6..0229989 100644
> --- a/arch/riscv/include/asm/syscon.h
> +++ b/arch/riscv/include/asm/syscon.h
> @@ -9,11 +9,11 @@
> /*
> * System controllers in a RISC-V system
> *
> - * So far only SiFive's Core Local Interruptor (CLINT) is defined.
> */
> enum {
> RISCV_NONE,
> RISCV_SYSCON_CLINT, /* Core Local Interruptor (CLINT) */
> + RISCV_SYSCON_PLIC, /* Platform Level Interrup Controller (PLIC) */
typo: Interrupt
> };
>
> #endif /* _ASM_SYSCON_H */
> diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
> index 35dbf64..8187c2b 100644
> --- a/arch/riscv/lib/Makefile
> +++ b/arch/riscv/lib/Makefile
> @@ -11,6 +11,7 @@ obj-$(CONFIG_CMD_GO) += boot.o
> obj-y += cache.o
> obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
> obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
> +obj-$(CONFIG_NDS_PLIC) += nds_plic.o
> obj-y += interrupts.o
> obj-y += reset.o
> obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
> diff --git a/arch/riscv/lib/nds_plic.c b/arch/riscv/lib/nds_plic.c
And move this driver to arch/riscv/cpu/ax25 since it's only available
in AX25 CPUs?
> new file mode 100644
> index 0000000..563da7d
> --- /dev/null
> +++ b/arch/riscv/lib/nds_plic.c
> @@ -0,0 +1,84 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2019, Rick Chen <rick@andestech.com>
> + *
> + * U-Boot syscon driver for Andes's Platform Level Interrupt Controller (PLIC).
> + * The PLIC block holds memory-mapped claim and pending registers
> + * associated with software interrupt.
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <regmap.h>
> +#include <syscon.h>
> +#include <asm/io.h>
> +#include <asm/syscon.h>
> +
> +/* pending register */
> +#define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + (hart) * 8)
> +/* enable register */
> +#define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80)
> +/* claim register */
> +#define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000)
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define PLIC_BASE_GET(void) \
> + do { \
> + long *ret; \
> + \
> + if (!gd->arch.plic) { \
> + ret = syscon_get_first_range(RISCV_SYSCON_PLIC); \
> + if (IS_ERR(ret)) \
> + return PTR_ERR(ret); \
> + gd->arch.plic = ret; \
> + } \
> + } while (0)
> +
> +int plic_init(int harts)
Can we make this function be automatically called in PLIC_BASE_GET()?
> +{
> + int i;
> + int en = 0x80808080;
Can we use some macros for this?
> +
> + PLIC_BASE_GET();
> + for(i=0;i<harts;i++)
nits: should have various spaces like i = 0;
> + {
> + en = en >> i;
> + writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, i));
> + }
> +
> + return 0;
> +}
> +
> +int riscv_send_ipi(int hart)
> +{
> + PLIC_BASE_GET();
> +
> + writel((0x80>>hart), (void __iomem *)PENDING_REG(gd->arch.plic, gd->arch.boot_hart));
macro for 0x80?
> +
> + return 0;
> +}
> +
> +int riscv_clear_ipi(int hart)
> +{
> + u32 source_id;
> +
> + PLIC_BASE_GET();
> +
> + source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart));
> + writel(source_id, (void __iomem *)CLAIM_REG(gd->arch.plic, hart));
> +
> + return 0;
> +}
> +
> +static const struct udevice_id nds_plic_ids[] = {
> + { .compatible = "riscv,plic1", .data = RISCV_SYSCON_PLIC },
> + { }
> +};
> +
> +U_BOOT_DRIVER(nds_plic) = {
> + .name = "nds_plic",
> + .id = UCLASS_SYSCON,
> + .of_match = nds_plic_ids,
> + .flags = DM_FLAG_PRE_RELOC,
> +};
> --
Regards,
Bin
^ permalink raw reply [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH 2/9] riscv: Add a SYSCON driver for Andestech's PLIC
2019-03-20 7:22 ` Bin Meng
@ 2019-03-21 7:04 ` Rick Chen
2019-03-21 7:32 ` Bin Meng
0 siblings, 1 reply; 38+ messages in thread
From: Rick Chen @ 2019-03-21 7:04 UTC (permalink / raw)
To: u-boot
Hi Bin
Bin Meng <bmeng.cn@gmail.com> 於 2019年3月20日 週三 下午3:22寫道:
>
> Hi Rick,
>
> On Tue, Mar 19, 2019 at 5:12 PM Andes <uboot@andestech.com> wrote:
> >
> > From: Rick Chen <rick@andestech.com>
> >
> > The Platform-Level Interrupt Controller(PLIC)
> > block holds memory-mapped claim and pending registers
> > associated with software interrupt.It is required
>
> nits: need one space after interrupt.
OK
I will add space.
>
> > for handling IPI.
> >
> > Signed-off-by: Rick Chen <rick@andestech.com>
> > Cc: Greentime Hu <greentime@andestech.com>
> > ---
> > arch/riscv/Kconfig | 9 ++++
> > arch/riscv/include/asm/global_data.h | 3 ++
> > arch/riscv/include/asm/syscon.h | 2 +-
> > arch/riscv/lib/Makefile | 1 +
> > arch/riscv/lib/nds_plic.c | 84 ++++++++++++++++++++++++++++++++++++
> > 5 files changed, 98 insertions(+), 1 deletion(-)
> > create mode 100644 arch/riscv/lib/nds_plic.c
> >
> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > index 3a4470d..fef11dd 100644
> > --- a/arch/riscv/Kconfig
> > +++ b/arch/riscv/Kconfig
>
> Probably it makes more sense to put this to arch/riscv/cpu/ax25/Kconfig?
I just refer to SIFIVE_CLINT. It also not make sense to place here, right ?
>
> > @@ -109,6 +109,15 @@ config SIFIVE_CLINT
> > The SiFive CLINT block holds memory-mapped control and status registers
> > associated with software and timer interrupts.
> >
> > +config NDS_PLIC
>
> I am not sure if it is appropriate to call this "NDS_PLIC". Shouldn't
> it be "ANDES_PLIC", because ANDES_ and SIFIVE_ are vendor prefixes.
OK
I will use ANDES_PLIC to replace NDS_PLIC.
>
> > + bool
> > + depends on RISCV_MMODE
> > + select REGMAP
> > + select SYSCON
> > + help
> > + The Andes PLIC block holds memory-mapped claim and pending registers
> > + associated with software interrupt.
> > +
> > config RISCV_RDTIME
> > bool
> > default y if RISCV_SMODE
> > diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h
> > index 80e3165..15867f5 100644
> > --- a/arch/riscv/include/asm/global_data.h
> > +++ b/arch/riscv/include/asm/global_data.h
> > @@ -18,6 +18,9 @@ struct arch_global_data {
> > #ifdef CONFIG_SIFIVE_CLINT
> > void __iomem *clint; /* clint base address */
> > #endif
> > +#ifdef CONFIG_NDS_PLIC
> > + void __iomem *plic; /* plic base address */
> > +#endif
> > #ifdef CONFIG_SMP
> > struct ipi_data ipi[CONFIG_NR_CPUS];
> > #endif
> > diff --git a/arch/riscv/include/asm/syscon.h b/arch/riscv/include/asm/syscon.h
> > index d311ee6..0229989 100644
> > --- a/arch/riscv/include/asm/syscon.h
> > +++ b/arch/riscv/include/asm/syscon.h
> > @@ -9,11 +9,11 @@
> > /*
> > * System controllers in a RISC-V system
> > *
> > - * So far only SiFive's Core Local Interruptor (CLINT) is defined.
> > */
> > enum {
> > RISCV_NONE,
> > RISCV_SYSCON_CLINT, /* Core Local Interruptor (CLINT) */
> > + RISCV_SYSCON_PLIC, /* Platform Level Interrup Controller (PLIC) */
>
> typo: Interrupt
OK
I will correct it.
>
> > };
> >
> > #endif /* _ASM_SYSCON_H */
> > diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
> > index 35dbf64..8187c2b 100644
> > --- a/arch/riscv/lib/Makefile
> > +++ b/arch/riscv/lib/Makefile
> > @@ -11,6 +11,7 @@ obj-$(CONFIG_CMD_GO) += boot.o
> > obj-y += cache.o
> > obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
> > obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
> > +obj-$(CONFIG_NDS_PLIC) += nds_plic.o
> > obj-y += interrupts.o
> > obj-y += reset.o
> > obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
> > diff --git a/arch/riscv/lib/nds_plic.c b/arch/riscv/lib/nds_plic.c
>
> And move this driver to arch/riscv/cpu/ax25 since it's only available
> in AX25 CPUs?
Same as sifive_clint.c . Shall it also move away from /lib ?
>
> > new file mode 100644
> > index 0000000..563da7d
> > --- /dev/null
> > +++ b/arch/riscv/lib/nds_plic.c
> > @@ -0,0 +1,84 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (C) 2019, Rick Chen <rick@andestech.com>
> > + *
> > + * U-Boot syscon driver for Andes's Platform Level Interrupt Controller (PLIC).
> > + * The PLIC block holds memory-mapped claim and pending registers
> > + * associated with software interrupt.
> > + */
> > +
> > +#include <common.h>
> > +#include <dm.h>
> > +#include <regmap.h>
> > +#include <syscon.h>
> > +#include <asm/io.h>
> > +#include <asm/syscon.h>
> > +
> > +/* pending register */
> > +#define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + (hart) * 8)
> > +/* enable register */
> > +#define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80)
> > +/* claim register */
> > +#define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000)
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +#define PLIC_BASE_GET(void) \
> > + do { \
> > + long *ret; \
> > + \
> > + if (!gd->arch.plic) { \
> > + ret = syscon_get_first_range(RISCV_SYSCON_PLIC); \
> > + if (IS_ERR(ret)) \
> > + return PTR_ERR(ret); \
> > + gd->arch.plic = ret; \
> > + } \
> > + } while (0)
> > +
> > +int plic_init(int harts)
>
> Can we make this function be automatically called in PLIC_BASE_GET()?
OK
I will move it in PLIC_BASE_GET()
>
> > +{
> > + int i;
> > + int en = 0x80808080;
>
> Can we use some macros for this?
OK
I will use macro to represent it.
>
> > +
> > + PLIC_BASE_GET();
> > + for(i=0;i<harts;i++)
>
> nits: should have various spaces like i = 0;
OK
>
> > + {
> > + en = en >> i;
> > + writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, i));
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +int riscv_send_ipi(int hart)
> > +{
> > + PLIC_BASE_GET();
> > +
> > + writel((0x80>>hart), (void __iomem *)PENDING_REG(gd->arch.plic, gd->arch.boot_hart));
>
> macro for 0x80?
OK
I will use macro to represent it.
Thanks for review.
Rick
>
> > +
> > + return 0;
> > +}
> > +
> > +int riscv_clear_ipi(int hart)
> > +{
> > + u32 source_id;
> > +
> > + PLIC_BASE_GET();
> > +
> > + source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart));
> > + writel(source_id, (void __iomem *)CLAIM_REG(gd->arch.plic, hart));
> > +
> > + return 0;
> > +}
> > +
> > +static const struct udevice_id nds_plic_ids[] = {
> > + { .compatible = "riscv,plic1", .data = RISCV_SYSCON_PLIC },
> > + { }
> > +};
> > +
> > +U_BOOT_DRIVER(nds_plic) = {
> > + .name = "nds_plic",
> > + .id = UCLASS_SYSCON,
> > + .of_match = nds_plic_ids,
> > + .flags = DM_FLAG_PRE_RELOC,
> > +};
> > --
>
> Regards,
> Bin
^ permalink raw reply [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH 2/9] riscv: Add a SYSCON driver for Andestech's PLIC
2019-03-21 7:04 ` Rick Chen
@ 2019-03-21 7:32 ` Bin Meng
2019-03-21 8:39 ` Rick Chen
0 siblings, 1 reply; 38+ messages in thread
From: Bin Meng @ 2019-03-21 7:32 UTC (permalink / raw)
To: u-boot
Hi Rick,
On Thu, Mar 21, 2019 at 3:04 PM Rick Chen <rickchen36@gmail.com> wrote:
>
> Hi Bin
>
> Bin Meng <bmeng.cn@gmail.com> 於 2019年3月20日 週三 下午3:22寫道:
> >
> > Hi Rick,
> >
> > On Tue, Mar 19, 2019 at 5:12 PM Andes <uboot@andestech.com> wrote:
> > >
> > > From: Rick Chen <rick@andestech.com>
> > >
> > > The Platform-Level Interrupt Controller(PLIC)
> > > block holds memory-mapped claim and pending registers
> > > associated with software interrupt.It is required
> >
> > nits: need one space after interrupt.
>
> OK
> I will add space.
>
> >
> > > for handling IPI.
> > >
> > > Signed-off-by: Rick Chen <rick@andestech.com>
> > > Cc: Greentime Hu <greentime@andestech.com>
> > > ---
> > > arch/riscv/Kconfig | 9 ++++
> > > arch/riscv/include/asm/global_data.h | 3 ++
> > > arch/riscv/include/asm/syscon.h | 2 +-
> > > arch/riscv/lib/Makefile | 1 +
> > > arch/riscv/lib/nds_plic.c | 84 ++++++++++++++++++++++++++++++++++++
> > > 5 files changed, 98 insertions(+), 1 deletion(-)
> > > create mode 100644 arch/riscv/lib/nds_plic.c
> > >
> > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > > index 3a4470d..fef11dd 100644
> > > --- a/arch/riscv/Kconfig
> > > +++ b/arch/riscv/Kconfig
> >
> > Probably it makes more sense to put this to arch/riscv/cpu/ax25/Kconfig?
>
> I just refer to SIFIVE_CLINT. It also not make sense to place here, right ?
Maybe, but since the cpu directory is renamed to 'generic', I am not
sure moving to that directory is a good idea.
>
> >
> > > @@ -109,6 +109,15 @@ config SIFIVE_CLINT
> > > The SiFive CLINT block holds memory-mapped control and status registers
> > > associated with software and timer interrupts.
> > >
> > > +config NDS_PLIC
> >
> > I am not sure if it is appropriate to call this "NDS_PLIC". Shouldn't
> > it be "ANDES_PLIC", because ANDES_ and SIFIVE_ are vendor prefixes.
>
> OK
> I will use ANDES_PLIC to replace NDS_PLIC.
>
> >
> > > + bool
> > > + depends on RISCV_MMODE
> > > + select REGMAP
> > > + select SYSCON
> > > + help
> > > + The Andes PLIC block holds memory-mapped claim and pending registers
> > > + associated with software interrupt.
> > > +
> > > config RISCV_RDTIME
> > > bool
> > > default y if RISCV_SMODE
> > > diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h
> > > index 80e3165..15867f5 100644
> > > --- a/arch/riscv/include/asm/global_data.h
> > > +++ b/arch/riscv/include/asm/global_data.h
> > > @@ -18,6 +18,9 @@ struct arch_global_data {
> > > #ifdef CONFIG_SIFIVE_CLINT
> > > void __iomem *clint; /* clint base address */
> > > #endif
> > > +#ifdef CONFIG_NDS_PLIC
> > > + void __iomem *plic; /* plic base address */
> > > +#endif
> > > #ifdef CONFIG_SMP
> > > struct ipi_data ipi[CONFIG_NR_CPUS];
> > > #endif
> > > diff --git a/arch/riscv/include/asm/syscon.h b/arch/riscv/include/asm/syscon.h
> > > index d311ee6..0229989 100644
> > > --- a/arch/riscv/include/asm/syscon.h
> > > +++ b/arch/riscv/include/asm/syscon.h
> > > @@ -9,11 +9,11 @@
> > > /*
> > > * System controllers in a RISC-V system
> > > *
> > > - * So far only SiFive's Core Local Interruptor (CLINT) is defined.
> > > */
> > > enum {
> > > RISCV_NONE,
> > > RISCV_SYSCON_CLINT, /* Core Local Interruptor (CLINT) */
> > > + RISCV_SYSCON_PLIC, /* Platform Level Interrup Controller (PLIC) */
> >
> > typo: Interrupt
>
> OK
> I will correct it.
>
> >
> > > };
> > >
> > > #endif /* _ASM_SYSCON_H */
> > > diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
> > > index 35dbf64..8187c2b 100644
> > > --- a/arch/riscv/lib/Makefile
> > > +++ b/arch/riscv/lib/Makefile
> > > @@ -11,6 +11,7 @@ obj-$(CONFIG_CMD_GO) += boot.o
> > > obj-y += cache.o
> > > obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
> > > obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
> > > +obj-$(CONFIG_NDS_PLIC) += nds_plic.o
> > > obj-y += interrupts.o
> > > obj-y += reset.o
> > > obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
> > > diff --git a/arch/riscv/lib/nds_plic.c b/arch/riscv/lib/nds_plic.c
> >
> > And move this driver to arch/riscv/cpu/ax25 since it's only available
> > in AX25 CPUs?
>
> Same as sifive_clint.c . Shall it also move away from /lib ?
>
I agree, but see comments above :)
> >
> > > new file mode 100644
> > > index 0000000..563da7d
> > > --- /dev/null
> > > +++ b/arch/riscv/lib/nds_plic.c
> > > @@ -0,0 +1,84 @@
> > > +// SPDX-License-Identifier: GPL-2.0+
> > > +/*
> > > + * Copyright (C) 2019, Rick Chen <rick@andestech.com>
> > > + *
> > > + * U-Boot syscon driver for Andes's Platform Level Interrupt Controller (PLIC).
> > > + * The PLIC block holds memory-mapped claim and pending registers
> > > + * associated with software interrupt.
> > > + */
> > > +
> > > +#include <common.h>
> > > +#include <dm.h>
> > > +#include <regmap.h>
> > > +#include <syscon.h>
> > > +#include <asm/io.h>
> > > +#include <asm/syscon.h>
> > > +
> > > +/* pending register */
> > > +#define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + (hart) * 8)
> > > +/* enable register */
> > > +#define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80)
> > > +/* claim register */
> > > +#define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000)
> > > +
> > > +DECLARE_GLOBAL_DATA_PTR;
> > > +
> > > +#define PLIC_BASE_GET(void) \
> > > + do { \
> > > + long *ret; \
> > > + \
> > > + if (!gd->arch.plic) { \
> > > + ret = syscon_get_first_range(RISCV_SYSCON_PLIC); \
> > > + if (IS_ERR(ret)) \
> > > + return PTR_ERR(ret); \
> > > + gd->arch.plic = ret; \
> > > + } \
> > > + } while (0)
> > > +
> > > +int plic_init(int harts)
> >
> > Can we make this function be automatically called in PLIC_BASE_GET()?
>
> OK
> I will move it in PLIC_BASE_GET()
>
> >
> > > +{
> > > + int i;
> > > + int en = 0x80808080;
> >
> > Can we use some macros for this?
>
> OK
> I will use macro to represent it.
>
> >
> > > +
> > > + PLIC_BASE_GET();
> > > + for(i=0;i<harts;i++)
> >
> > nits: should have various spaces like i = 0;
>
> OK
>
> >
> > > + {
> > > + en = en >> i;
> > > + writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, i));
> > > + }
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +int riscv_send_ipi(int hart)
> > > +{
> > > + PLIC_BASE_GET();
> > > +
> > > + writel((0x80>>hart), (void __iomem *)PENDING_REG(gd->arch.plic, gd->arch.boot_hart));
> >
> > macro for 0x80?
>
> OK
> I will use macro to represent it.
>
> Thanks for review.
>
Regards,
Bin
^ permalink raw reply [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH 2/9] riscv: Add a SYSCON driver for Andestech's PLIC
2019-03-21 7:32 ` Bin Meng
@ 2019-03-21 8:39 ` Rick Chen
2019-03-21 16:24 ` Troy Benjegerdes
0 siblings, 1 reply; 38+ messages in thread
From: Rick Chen @ 2019-03-21 8:39 UTC (permalink / raw)
To: u-boot
Bin Meng <bmeng.cn@gmail.com> 於 2019年3月21日 週四 下午3:32寫道:
>
> Hi Rick,
>
> On Thu, Mar 21, 2019 at 3:04 PM Rick Chen <rickchen36@gmail.com> wrote:
> >
> > Hi Bin
> >
> > Bin Meng <bmeng.cn@gmail.com> 於 2019年3月20日 週三 下午3:22寫道:
> > >
> > > Hi Rick,
> > >
> > > On Tue, Mar 19, 2019 at 5:12 PM Andes <uboot@andestech.com> wrote:
> > > >
> > > > From: Rick Chen <rick@andestech.com>
> > > >
> > > > The Platform-Level Interrupt Controller(PLIC)
> > > > block holds memory-mapped claim and pending registers
> > > > associated with software interrupt.It is required
> > >
> > > nits: need one space after interrupt.
> >
> > OK
> > I will add space.
> >
> > >
> > > > for handling IPI.
> > > >
> > > > Signed-off-by: Rick Chen <rick@andestech.com>
> > > > Cc: Greentime Hu <greentime@andestech.com>
> > > > ---
> > > > arch/riscv/Kconfig | 9 ++++
> > > > arch/riscv/include/asm/global_data.h | 3 ++
> > > > arch/riscv/include/asm/syscon.h | 2 +-
> > > > arch/riscv/lib/Makefile | 1 +
> > > > arch/riscv/lib/nds_plic.c | 84 ++++++++++++++++++++++++++++++++++++
> > > > 5 files changed, 98 insertions(+), 1 deletion(-)
> > > > create mode 100644 arch/riscv/lib/nds_plic.c
> > > >
> > > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > > > index 3a4470d..fef11dd 100644
> > > > --- a/arch/riscv/Kconfig
> > > > +++ b/arch/riscv/Kconfig
> > >
> > > Probably it makes more sense to put this to arch/riscv/cpu/ax25/Kconfig?
> >
> > I just refer to SIFIVE_CLINT. It also not make sense to place here, right ?
>
> Maybe, but since the cpu directory is renamed to 'generic', I am not
> sure moving to that directory is a good idea.
Maybe I will still put it in /arch/riscv/Kconfig.
And we can move them to the place they belong individually together if
there have better place to accommodate to SIFIVE_CLINT.
How do you think ?
Rick
>
> >
> > >
> > > > @@ -109,6 +109,15 @@ config SIFIVE_CLINT
> > > > The SiFive CLINT block holds memory-mapped control and status registers
> > > > associated with software and timer interrupts.
> > > >
> > > > +config NDS_PLIC
> > >
> > > I am not sure if it is appropriate to call this "NDS_PLIC". Shouldn't
> > > it be "ANDES_PLIC", because ANDES_ and SIFIVE_ are vendor prefixes.
> >
> > OK
> > I will use ANDES_PLIC to replace NDS_PLIC.
> >
> > >
> > > > + bool
> > > > + depends on RISCV_MMODE
> > > > + select REGMAP
> > > > + select SYSCON
> > > > + help
> > > > + The Andes PLIC block holds memory-mapped claim and pending registers
> > > > + associated with software interrupt.
> > > > +
> > > > config RISCV_RDTIME
> > > > bool
> > > > default y if RISCV_SMODE
> > > > diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h
> > > > index 80e3165..15867f5 100644
> > > > --- a/arch/riscv/include/asm/global_data.h
> > > > +++ b/arch/riscv/include/asm/global_data.h
> > > > @@ -18,6 +18,9 @@ struct arch_global_data {
> > > > #ifdef CONFIG_SIFIVE_CLINT
> > > > void __iomem *clint; /* clint base address */
> > > > #endif
> > > > +#ifdef CONFIG_NDS_PLIC
> > > > + void __iomem *plic; /* plic base address */
> > > > +#endif
> > > > #ifdef CONFIG_SMP
> > > > struct ipi_data ipi[CONFIG_NR_CPUS];
> > > > #endif
> > > > diff --git a/arch/riscv/include/asm/syscon.h b/arch/riscv/include/asm/syscon.h
> > > > index d311ee6..0229989 100644
> > > > --- a/arch/riscv/include/asm/syscon.h
> > > > +++ b/arch/riscv/include/asm/syscon.h
> > > > @@ -9,11 +9,11 @@
> > > > /*
> > > > * System controllers in a RISC-V system
> > > > *
> > > > - * So far only SiFive's Core Local Interruptor (CLINT) is defined.
> > > > */
> > > > enum {
> > > > RISCV_NONE,
> > > > RISCV_SYSCON_CLINT, /* Core Local Interruptor (CLINT) */
> > > > + RISCV_SYSCON_PLIC, /* Platform Level Interrup Controller (PLIC) */
> > >
> > > typo: Interrupt
> >
> > OK
> > I will correct it.
> >
> > >
> > > > };
> > > >
> > > > #endif /* _ASM_SYSCON_H */
> > > > diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
> > > > index 35dbf64..8187c2b 100644
> > > > --- a/arch/riscv/lib/Makefile
> > > > +++ b/arch/riscv/lib/Makefile
> > > > @@ -11,6 +11,7 @@ obj-$(CONFIG_CMD_GO) += boot.o
> > > > obj-y += cache.o
> > > > obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
> > > > obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
> > > > +obj-$(CONFIG_NDS_PLIC) += nds_plic.o
> > > > obj-y += interrupts.o
> > > > obj-y += reset.o
> > > > obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
> > > > diff --git a/arch/riscv/lib/nds_plic.c b/arch/riscv/lib/nds_plic.c
> > >
> > > And move this driver to arch/riscv/cpu/ax25 since it's only available
> > > in AX25 CPUs?
> >
> > Same as sifive_clint.c . Shall it also move away from /lib ?
> >
>
> I agree, but see comments above :)
>
> > >
> > > > new file mode 100644
> > > > index 0000000..563da7d
> > > > --- /dev/null
> > > > +++ b/arch/riscv/lib/nds_plic.c
> > > > @@ -0,0 +1,84 @@
> > > > +// SPDX-License-Identifier: GPL-2.0+
> > > > +/*
> > > > + * Copyright (C) 2019, Rick Chen <rick@andestech.com>
> > > > + *
> > > > + * U-Boot syscon driver for Andes's Platform Level Interrupt Controller (PLIC).
> > > > + * The PLIC block holds memory-mapped claim and pending registers
> > > > + * associated with software interrupt.
> > > > + */
> > > > +
> > > > +#include <common.h>
> > > > +#include <dm.h>
> > > > +#include <regmap.h>
> > > > +#include <syscon.h>
> > > > +#include <asm/io.h>
> > > > +#include <asm/syscon.h>
> > > > +
> > > > +/* pending register */
> > > > +#define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + (hart) * 8)
> > > > +/* enable register */
> > > > +#define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80)
> > > > +/* claim register */
> > > > +#define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000)
> > > > +
> > > > +DECLARE_GLOBAL_DATA_PTR;
> > > > +
> > > > +#define PLIC_BASE_GET(void) \
> > > > + do { \
> > > > + long *ret; \
> > > > + \
> > > > + if (!gd->arch.plic) { \
> > > > + ret = syscon_get_first_range(RISCV_SYSCON_PLIC); \
> > > > + if (IS_ERR(ret)) \
> > > > + return PTR_ERR(ret); \
> > > > + gd->arch.plic = ret; \
> > > > + } \
> > > > + } while (0)
> > > > +
> > > > +int plic_init(int harts)
> > >
> > > Can we make this function be automatically called in PLIC_BASE_GET()?
> >
> > OK
> > I will move it in PLIC_BASE_GET()
> >
> > >
> > > > +{
> > > > + int i;
> > > > + int en = 0x80808080;
> > >
> > > Can we use some macros for this?
> >
> > OK
> > I will use macro to represent it.
> >
> > >
> > > > +
> > > > + PLIC_BASE_GET();
> > > > + for(i=0;i<harts;i++)
> > >
> > > nits: should have various spaces like i = 0;
> >
> > OK
> >
> > >
> > > > + {
> > > > + en = en >> i;
> > > > + writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, i));
> > > > + }
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > +int riscv_send_ipi(int hart)
> > > > +{
> > > > + PLIC_BASE_GET();
> > > > +
> > > > + writel((0x80>>hart), (void __iomem *)PENDING_REG(gd->arch.plic, gd->arch.boot_hart));
> > >
> > > macro for 0x80?
> >
> > OK
> > I will use macro to represent it.
> >
> > Thanks for review.
> >
>
> Regards,
> Bin
^ permalink raw reply [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH 2/9] riscv: Add a SYSCON driver for Andestech's PLIC
2019-03-21 8:39 ` Rick Chen
@ 2019-03-21 16:24 ` Troy Benjegerdes
0 siblings, 0 replies; 38+ messages in thread
From: Troy Benjegerdes @ 2019-03-21 16:24 UTC (permalink / raw)
To: u-boot
> > > >
> > > > Probably it makes more sense to put this to arch/riscv/cpu/ax25/Kconfig?
> > >
> > > I just refer to SIFIVE_CLINT. It also not make sense to place here, right ?
> >
> > Maybe, but since the cpu directory is renamed to 'generic', I am not
> > sure moving to that directory is a good idea.
>
> Maybe I will still put it in /arch/riscv/Kconfig.
> And we can move them to the place they belong individually together if
> there have better place to accommodate to SIFIVE_CLINT.
> How do you think ?
>
> > > > > +++ b/arch/riscv/lib/Makefile
> > > > > @@ -11,6 +11,7 @@ obj-$(CONFIG_CMD_GO) += boot.o
> > > > > obj-y += cache.o
> > > > > obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
> > > > > obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
> > > > > +obj-$(CONFIG_NDS_PLIC) += nds_plic.o
> > > > > obj-y += interrupts.o
> > > > > obj-y += reset.o
> > > > > obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
> > > > > diff --git a/arch/riscv/lib/nds_plic.c b/arch/riscv/lib/nds_plic.c
> > > >
> > > > And move this driver to arch/riscv/cpu/ax25 since it's only available
> > > > in AX25 CPUs?
> > >
> > > Same as sifive_clint.c . Shall it also move away from /lib ?
> > >
> >
> > I agree, but see comments above :)
It seems to me there might be a usefull distinction between potentially
generic things like the Sifive/Berkely/Rocket-chip clint [1] and other
vendor implementations which do not have necessarily have publicly
reviewable hardware implementations.
[1] https://github.com/sifive/rocket-chip/blob/master/src/main/scala/devices/tilelink/CLINT.scala
^ permalink raw reply [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH 3/9] riscv: Add a SYSCON driver for Andestech's PLMT
2019-03-19 9:07 [U-Boot] [PATCH 0/9] AE350 SMP support RISC-V Andes
2019-03-19 9:07 ` [U-Boot] [PATCH 1/9] riscv: ax25: Create a simple-bus driver for the soc node Andes
2019-03-19 9:07 ` [U-Boot] [PATCH 2/9] riscv: Add a SYSCON driver for Andestech's PLIC Andes
@ 2019-03-19 9:07 ` Andes
2019-03-20 7:22 ` Bin Meng
2019-03-19 9:07 ` [U-Boot] [PATCH 4/9] riscv: ae350: initialize PLIC Andes
` (5 subsequent siblings)
8 siblings, 1 reply; 38+ messages in thread
From: Andes @ 2019-03-19 9:07 UTC (permalink / raw)
To: u-boot
From: Rick Chen <rick@andestech.com>
The platform-Level Machine Timer(PLMT) block
holds memory-mapped mtime register associated
with timer tick.
This driver implements the riscv_get_time()which
are required by the generic RISC-V timer driver.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
---
arch/riscv/Kconfig | 9 ++++++
arch/riscv/include/asm/global_data.h | 3 ++
arch/riscv/include/asm/syscon.h | 1 +
arch/riscv/lib/Makefile | 1 +
arch/riscv/lib/nds_plmt.c | 53 ++++++++++++++++++++++++++++++++++++
5 files changed, 67 insertions(+)
create mode 100644 arch/riscv/lib/nds_plmt.c
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index fef11dd..697892e 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -118,6 +118,15 @@ config NDS_PLIC
The Andes PLIC block holds memory-mapped claim and pending registers
associated with software interrupt.
+config NDS_PLMT
+ bool
+ depends on RISCV_MMODE
+ select REGMAP
+ select SYSCON
+ help
+ The Andes PLMT block holds memory-mapped mtime register
+ associated with timer tick.
+
config RISCV_RDTIME
bool
default y if RISCV_SMODE
diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h
index 15867f5..0695ae3 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -21,6 +21,9 @@ struct arch_global_data {
#ifdef CONFIG_NDS_PLIC
void __iomem *plic; /* plic base address */
#endif
+#ifdef CONFIG_NDS_PLMT
+ void __iomem *plmt; /* plmt base address */
+#endif
#ifdef CONFIG_SMP
struct ipi_data ipi[CONFIG_NR_CPUS];
#endif
diff --git a/arch/riscv/include/asm/syscon.h b/arch/riscv/include/asm/syscon.h
index 0229989..9fdee09 100644
--- a/arch/riscv/include/asm/syscon.h
+++ b/arch/riscv/include/asm/syscon.h
@@ -14,6 +14,7 @@ enum {
RISCV_NONE,
RISCV_SYSCON_CLINT, /* Core Local Interruptor (CLINT) */
RISCV_SYSCON_PLIC, /* Platform Level Interrup Controller (PLIC) */
+ RISCV_SYSCON_PLMT, /* Platform Level Machine Timer (PLMT) */
};
#endif /* _ASM_SYSCON_H */
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index 8187c2b..383eed3 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -12,6 +12,7 @@ obj-y += cache.o
obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
obj-$(CONFIG_NDS_PLIC) += nds_plic.o
+obj-$(CONFIG_NDS_PLMT) += nds_plmt.o
obj-y += interrupts.o
obj-y += reset.o
obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
diff --git a/arch/riscv/lib/nds_plmt.c b/arch/riscv/lib/nds_plmt.c
new file mode 100644
index 0000000..12d7e0e
--- /dev/null
+++ b/arch/riscv/lib/nds_plmt.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019, Rick Chen <rick@andestech.com>
+ *
+ * U-Boot syscon driver for Andes's Platform Level Machine Timer (PLMT).
+ * The PLMT block holds memory-mapped mtime register
+ * associated with timer tick.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/syscon.h>
+
+/* mtime register */
+#define MTIME_REG(base) ((ulong)(base))
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define PLMT_BASE_GET(void) \
+ do { \
+ long *ret; \
+ \
+ if (!gd->arch.plmt) { \
+ ret = syscon_get_first_range(RISCV_SYSCON_PLMT); \
+ if (IS_ERR(ret)) \
+ return PTR_ERR(ret); \
+ gd->arch.plmt = ret; \
+ } \
+ } while (0)
+
+int riscv_get_time(u64 *time)
+{
+ PLMT_BASE_GET();
+
+ *time = readq((void __iomem *)MTIME_REG(gd->arch.plmt));
+
+ return 0;
+}
+
+static const struct udevice_id nds_plmt_ids[] = {
+ { .compatible = "riscv,plmt0", .data = RISCV_SYSCON_PLMT },
+ { }
+};
+
+U_BOOT_DRIVER(nds_plmt) = {
+ .name = "nds_plmt",
+ .id = UCLASS_SYSCON,
+ .of_match = nds_plmt_ids,
+ .flags = DM_FLAG_PRE_RELOC,
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH 3/9] riscv: Add a SYSCON driver for Andestech's PLMT
2019-03-19 9:07 ` [U-Boot] [PATCH 3/9] riscv: Add a SYSCON driver for Andestech's PLMT Andes
@ 2019-03-20 7:22 ` Bin Meng
2019-03-21 8:41 ` Rick Chen
0 siblings, 1 reply; 38+ messages in thread
From: Bin Meng @ 2019-03-20 7:22 UTC (permalink / raw)
To: u-boot
Hi Rick,
On Tue, Mar 19, 2019 at 5:12 PM Andes <uboot@andestech.com> wrote:
>
> From: Rick Chen <rick@andestech.com>
>
> The platform-Level Machine Timer(PLMT) block
> holds memory-mapped mtime register associated
> with timer tick.
>
> This driver implements the riscv_get_time()which
nits: need one space before "which"
> are required by the generic RISC-V timer driver.
are -> is
>
> Signed-off-by: Rick Chen <rick@andestech.com>
> Cc: Greentime Hu <greentime@andestech.com>
> ---
> arch/riscv/Kconfig | 9 ++++++
> arch/riscv/include/asm/global_data.h | 3 ++
> arch/riscv/include/asm/syscon.h | 1 +
> arch/riscv/lib/Makefile | 1 +
> arch/riscv/lib/nds_plmt.c | 53 ++++++++++++++++++++++++++++++++++++
> 5 files changed, 67 insertions(+)
> create mode 100644 arch/riscv/lib/nds_plmt.c
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index fef11dd..697892e 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -118,6 +118,15 @@ config NDS_PLIC
> The Andes PLIC block holds memory-mapped claim and pending registers
> associated with software interrupt.
>
> +config NDS_PLMT
ANDES_PLMT?
> + bool
> + depends on RISCV_MMODE
> + select REGMAP
> + select SYSCON
> + help
> + The Andes PLMT block holds memory-mapped mtime register
> + associated with timer tick.
> +
> config RISCV_RDTIME
> bool
> default y if RISCV_SMODE
> diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h
> index 15867f5..0695ae3 100644
> --- a/arch/riscv/include/asm/global_data.h
> +++ b/arch/riscv/include/asm/global_data.h
> @@ -21,6 +21,9 @@ struct arch_global_data {
> #ifdef CONFIG_NDS_PLIC
> void __iomem *plic; /* plic base address */
> #endif
> +#ifdef CONFIG_NDS_PLMT
> + void __iomem *plmt; /* plmt base address */
> +#endif
> #ifdef CONFIG_SMP
> struct ipi_data ipi[CONFIG_NR_CPUS];
> #endif
> diff --git a/arch/riscv/include/asm/syscon.h b/arch/riscv/include/asm/syscon.h
> index 0229989..9fdee09 100644
> --- a/arch/riscv/include/asm/syscon.h
> +++ b/arch/riscv/include/asm/syscon.h
> @@ -14,6 +14,7 @@ enum {
> RISCV_NONE,
> RISCV_SYSCON_CLINT, /* Core Local Interruptor (CLINT) */
> RISCV_SYSCON_PLIC, /* Platform Level Interrup Controller (PLIC) */
> + RISCV_SYSCON_PLMT, /* Platform Level Machine Timer (PLMT) */
> };
>
> #endif /* _ASM_SYSCON_H */
> diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
> index 8187c2b..383eed3 100644
> --- a/arch/riscv/lib/Makefile
> +++ b/arch/riscv/lib/Makefile
> @@ -12,6 +12,7 @@ obj-y += cache.o
> obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
> obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
> obj-$(CONFIG_NDS_PLIC) += nds_plic.o
> +obj-$(CONFIG_NDS_PLMT) += nds_plmt.o
> obj-y += interrupts.o
> obj-y += reset.o
> obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
> diff --git a/arch/riscv/lib/nds_plmt.c b/arch/riscv/lib/nds_plmt.c
> new file mode 100644
> index 0000000..12d7e0e
> --- /dev/null
> +++ b/arch/riscv/lib/nds_plmt.c
> @@ -0,0 +1,53 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2019, Rick Chen <rick@andestech.com>
> + *
> + * U-Boot syscon driver for Andes's Platform Level Machine Timer (PLMT).
> + * The PLMT block holds memory-mapped mtime register
> + * associated with timer tick.
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <regmap.h>
> +#include <syscon.h>
> +#include <asm/io.h>
> +#include <asm/syscon.h>
> +
> +/* mtime register */
> +#define MTIME_REG(base) ((ulong)(base))
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define PLMT_BASE_GET(void) \
> + do { \
> + long *ret; \
> + \
> + if (!gd->arch.plmt) { \
> + ret = syscon_get_first_range(RISCV_SYSCON_PLMT); \
> + if (IS_ERR(ret)) \
> + return PTR_ERR(ret); \
> + gd->arch.plmt = ret; \
> + } \
> + } while (0)
> +
> +int riscv_get_time(u64 *time)
> +{
> + PLMT_BASE_GET();
> +
> + *time = readq((void __iomem *)MTIME_REG(gd->arch.plmt));
> +
> + return 0;
> +}
> +
> +static const struct udevice_id nds_plmt_ids[] = {
> + { .compatible = "riscv,plmt0", .data = RISCV_SYSCON_PLMT },
> + { }
> +};
> +
> +U_BOOT_DRIVER(nds_plmt) = {
> + .name = "nds_plmt",
> + .id = UCLASS_SYSCON,
> + .of_match = nds_plmt_ids,
> + .flags = DM_FLAG_PRE_RELOC,
> +};
> --
Regards,
Bin
^ permalink raw reply [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH 3/9] riscv: Add a SYSCON driver for Andestech's PLMT
2019-03-20 7:22 ` Bin Meng
@ 2019-03-21 8:41 ` Rick Chen
0 siblings, 0 replies; 38+ messages in thread
From: Rick Chen @ 2019-03-21 8:41 UTC (permalink / raw)
To: u-boot
Hi Bin
Bin Meng <bmeng.cn@gmail.com> 於 2019年3月20日 週三 下午3:22寫道:
>
> Hi Rick,
>
> On Tue, Mar 19, 2019 at 5:12 PM Andes <uboot@andestech.com> wrote:
> >
> > From: Rick Chen <rick@andestech.com>
> >
> > The platform-Level Machine Timer(PLMT) block
> > holds memory-mapped mtime register associated
> > with timer tick.
> >
> > This driver implements the riscv_get_time()which
>
> nits: need one space before "which"
OK
>
> > are required by the generic RISC-V timer driver.
>
> are -> is
OK
>
> >
> > Signed-off-by: Rick Chen <rick@andestech.com>
> > Cc: Greentime Hu <greentime@andestech.com>
> > ---
> > arch/riscv/Kconfig | 9 ++++++
> > arch/riscv/include/asm/global_data.h | 3 ++
> > arch/riscv/include/asm/syscon.h | 1 +
> > arch/riscv/lib/Makefile | 1 +
> > arch/riscv/lib/nds_plmt.c | 53 ++++++++++++++++++++++++++++++++++++
> > 5 files changed, 67 insertions(+)
> > create mode 100644 arch/riscv/lib/nds_plmt.c
> >
> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > index fef11dd..697892e 100644
> > --- a/arch/riscv/Kconfig
> > +++ b/arch/riscv/Kconfig
> > @@ -118,6 +118,15 @@ config NDS_PLIC
> > The Andes PLIC block holds memory-mapped claim and pending registers
> > associated with software interrupt.
> >
> > +config NDS_PLMT
>
> ANDES_PLMT?
OK
>
> > + bool
> > + depends on RISCV_MMODE
> > + select REGMAP
> > + select SYSCON
> > + help
> > + The Andes PLMT block holds memory-mapped mtime register
> > + associated with timer tick.
> > +
> > config RISCV_RDTIME
> > bool
> > default y if RISCV_SMODE
> > diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h
> > index 15867f5..0695ae3 100644
> > --- a/arch/riscv/include/asm/global_data.h
> > +++ b/arch/riscv/include/asm/global_data.h
> > @@ -21,6 +21,9 @@ struct arch_global_data {
> > #ifdef CONFIG_NDS_PLIC
> > void __iomem *plic; /* plic base address */
> > #endif
> > +#ifdef CONFIG_NDS_PLMT
> > + void __iomem *plmt; /* plmt base address */
> > +#endif
> > #ifdef CONFIG_SMP
> > struct ipi_data ipi[CONFIG_NR_CPUS];
> > #endif
> > diff --git a/arch/riscv/include/asm/syscon.h b/arch/riscv/include/asm/syscon.h
> > index 0229989..9fdee09 100644
> > --- a/arch/riscv/include/asm/syscon.h
> > +++ b/arch/riscv/include/asm/syscon.h
> > @@ -14,6 +14,7 @@ enum {
> > RISCV_NONE,
> > RISCV_SYSCON_CLINT, /* Core Local Interruptor (CLINT) */
> > RISCV_SYSCON_PLIC, /* Platform Level Interrup Controller (PLIC) */
> > + RISCV_SYSCON_PLMT, /* Platform Level Machine Timer (PLMT) */
> > };
> >
> > #endif /* _ASM_SYSCON_H */
> > diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
> > index 8187c2b..383eed3 100644
> > --- a/arch/riscv/lib/Makefile
> > +++ b/arch/riscv/lib/Makefile
> > @@ -12,6 +12,7 @@ obj-y += cache.o
> > obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
> > obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
> > obj-$(CONFIG_NDS_PLIC) += nds_plic.o
> > +obj-$(CONFIG_NDS_PLMT) += nds_plmt.o
> > obj-y += interrupts.o
> > obj-y += reset.o
> > obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
> > diff --git a/arch/riscv/lib/nds_plmt.c b/arch/riscv/lib/nds_plmt.c
> > new file mode 100644
> > index 0000000..12d7e0e
> > --- /dev/null
> > +++ b/arch/riscv/lib/nds_plmt.c
> > @@ -0,0 +1,53 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (C) 2019, Rick Chen <rick@andestech.com>
> > + *
> > + * U-Boot syscon driver for Andes's Platform Level Machine Timer (PLMT).
> > + * The PLMT block holds memory-mapped mtime register
> > + * associated with timer tick.
> > + */
> > +
> > +#include <common.h>
> > +#include <dm.h>
> > +#include <regmap.h>
> > +#include <syscon.h>
> > +#include <asm/io.h>
> > +#include <asm/syscon.h>
> > +
> > +/* mtime register */
> > +#define MTIME_REG(base) ((ulong)(base))
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +#define PLMT_BASE_GET(void) \
> > + do { \
> > + long *ret; \
> > + \
> > + if (!gd->arch.plmt) { \
> > + ret = syscon_get_first_range(RISCV_SYSCON_PLMT); \
> > + if (IS_ERR(ret)) \
> > + return PTR_ERR(ret); \
> > + gd->arch.plmt = ret; \
> > + } \
> > + } while (0)
> > +
> > +int riscv_get_time(u64 *time)
> > +{
> > + PLMT_BASE_GET();
> > +
> > + *time = readq((void __iomem *)MTIME_REG(gd->arch.plmt));
> > +
> > + return 0;
> > +}
> > +
> > +static const struct udevice_id nds_plmt_ids[] = {
> > + { .compatible = "riscv,plmt0", .data = RISCV_SYSCON_PLMT },
> > + { }
> > +};
> > +
> > +U_BOOT_DRIVER(nds_plmt) = {
> > + .name = "nds_plmt",
> > + .id = UCLASS_SYSCON,
> > + .of_match = nds_plmt_ids,
> > + .flags = DM_FLAG_PRE_RELOC,
> > +};
> > --
>
> Regards,
> Bin
^ permalink raw reply [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH 4/9] riscv: ae350: initialize PLIC
2019-03-19 9:07 [U-Boot] [PATCH 0/9] AE350 SMP support RISC-V Andes
` (2 preceding siblings ...)
2019-03-19 9:07 ` [U-Boot] [PATCH 3/9] riscv: Add a SYSCON driver for Andestech's PLMT Andes
@ 2019-03-19 9:07 ` Andes
2019-03-19 9:07 ` [U-Boot] [PATCH 5/9] riscv: ae350: disable ATCPIT100 timer Andes
` (4 subsequent siblings)
8 siblings, 0 replies; 38+ messages in thread
From: Andes @ 2019-03-19 9:07 UTC (permalink / raw)
To: u-boot
From: Rick Chen <rick@andestech.com>
Initialize PLIC when ae350 board startup.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
---
board/AndesTech/ax25-ae350/ax25-ae350.c | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c b/board/AndesTech/ax25-ae350/ax25-ae350.c
index d343453..ebeb4b8 100644
--- a/board/AndesTech/ax25-ae350/ax25-ae350.c
+++ b/board/AndesTech/ax25-ae350/ax25-ae350.c
@@ -11,10 +11,17 @@
#include <linux/io.h>
#include <faraday/ftsmc020.h>
#include <fdtdec.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dm/uclass-internal.h>
+#include <cpu.h>
DECLARE_GLOBAL_DATA_PTR;
extern phys_addr_t prior_stage_fdt_address;
+extern int plic_init(int harts);
+
/*
* Miscellaneous platform dependent initializations
*/
@@ -97,9 +104,32 @@ int smc_init(void)
return 0;
}
+#ifdef CONFIG_NDS_PLIC
+int init_plic(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_find_first_device(UCLASS_CPU, &dev);
+ if (ret)
+ return ret;
+
+ if (ret == 0 && dev != NULL) {
+ ret = cpu_get_count(dev);
+ plic_init(ret);
+ return 0;
+ }
+
+ return -ENODEV;
+}
+#endif
+
#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
+#ifdef CONFIG_NDS_PLIC
+ init_plic();
+#endif
smc_init();
return 0;
--
2.7.4
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH 5/9] riscv: ae350: disable ATCPIT100 timer
2019-03-19 9:07 [U-Boot] [PATCH 0/9] AE350 SMP support RISC-V Andes
` (3 preceding siblings ...)
2019-03-19 9:07 ` [U-Boot] [PATCH 4/9] riscv: ae350: initialize PLIC Andes
@ 2019-03-19 9:07 ` Andes
2019-03-20 7:22 ` Bin Meng
2019-03-19 9:07 ` [U-Boot] [PATCH 6/9] riscv: ax25: Add platform-specific Kconfig options Andes
` (3 subsequent siblings)
8 siblings, 1 reply; 38+ messages in thread
From: Andes @ 2019-03-19 9:07 UTC (permalink / raw)
To: u-boot
From: Rick Chen <rick@andestech.com>
Disable ATCPIT100 SoC timer and replace by PLMT.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
---
configs/ae350_rv32_defconfig | 1 -
configs/ae350_rv64_defconfig | 1 -
2 files changed, 2 deletions(-)
diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig
index 5837b48..e13c7de 100644
--- a/configs/ae350_rv32_defconfig
+++ b/configs/ae350_rv32_defconfig
@@ -33,4 +33,3 @@ CONFIG_BAUDRATE=38400
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_ATCSPI200_SPI=y
-CONFIG_ATCPIT100_TIMER=y
diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig
index b250d3f..a41f918 100644
--- a/configs/ae350_rv64_defconfig
+++ b/configs/ae350_rv64_defconfig
@@ -34,4 +34,3 @@ CONFIG_BAUDRATE=38400
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_ATCSPI200_SPI=y
-CONFIG_ATCPIT100_TIMER=y
--
2.7.4
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH 6/9] riscv: ax25: Add platform-specific Kconfig options
2019-03-19 9:07 [U-Boot] [PATCH 0/9] AE350 SMP support RISC-V Andes
` (4 preceding siblings ...)
2019-03-19 9:07 ` [U-Boot] [PATCH 5/9] riscv: ae350: disable ATCPIT100 timer Andes
@ 2019-03-19 9:07 ` Andes
2019-03-20 7:22 ` Bin Meng
2019-03-19 9:07 ` [U-Boot] [PATCH 7/9] riscv: ax25: Andes specific cache shall only support in M-mode Andes
` (2 subsequent siblings)
8 siblings, 1 reply; 38+ messages in thread
From: Andes @ 2019-03-19 9:07 UTC (permalink / raw)
To: u-boot
From: Rick Chen <rick@andestech.com>
Add ax25 RISC-V platform-specific Kconfig options, to include
CPU and timer drivers.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
---
arch/riscv/cpu/ax25/Kconfig | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
index e9dbca2..0901709 100644
--- a/arch/riscv/cpu/ax25/Kconfig
+++ b/arch/riscv/cpu/ax25/Kconfig
@@ -1,5 +1,11 @@
config RISCV_NDS
bool
+ select ARCH_EARLY_INIT_R
+ imply CPU
+ imply CPU_RISCV
+ imply RISCV_TIMER
+ imply NDS_PLIC if RISCV_MMODE
+ imply NDS_PLMT if RISCV_MMODE
help
Run U-Boot on AndeStar V5 platforms and use some specific features
which are provided by Andes Technology AndeStar V5 families.
--
2.7.4
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH 7/9] riscv: ax25: Andes specific cache shall only support in M-mode.
2019-03-19 9:07 [U-Boot] [PATCH 0/9] AE350 SMP support RISC-V Andes
` (5 preceding siblings ...)
2019-03-19 9:07 ` [U-Boot] [PATCH 6/9] riscv: ax25: Add platform-specific Kconfig options Andes
@ 2019-03-19 9:07 ` Andes
2019-03-20 7:22 ` Bin Meng
2019-03-19 9:07 ` [U-Boot] [PATCH 8/9] riscv: dts: ae350 support SMP Andes
2019-03-19 9:07 ` [U-Boot] [PATCH 9/9] riscv: ae350: enable SMP Andes
8 siblings, 1 reply; 38+ messages in thread
From: Andes @ 2019-03-19 9:07 UTC (permalink / raw)
To: u-boot
From: Rick Chen <rick@andestech.com>
Limit the cache configuration only can be supported in M mode.
It can not be manipulated in S mode.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
---
arch/riscv/cpu/ax25/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
index 0901709..e030df4 100644
--- a/arch/riscv/cpu/ax25/Kconfig
+++ b/arch/riscv/cpu/ax25/Kconfig
@@ -14,6 +14,7 @@ if RISCV_NDS
config RISCV_NDS_CACHE
bool "AndeStar V5 families specific cache support"
+ depends on RISCV_MMODE
help
Provide Andes Technology AndeStar V5 families specific cache support.
--
2.7.4
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH 7/9] riscv: ax25: Andes specific cache shall only support in M-mode.
2019-03-19 9:07 ` [U-Boot] [PATCH 7/9] riscv: ax25: Andes specific cache shall only support in M-mode Andes
@ 2019-03-20 7:22 ` Bin Meng
2019-03-21 8:42 ` Rick Chen
0 siblings, 1 reply; 38+ messages in thread
From: Bin Meng @ 2019-03-20 7:22 UTC (permalink / raw)
To: u-boot
Hi Rick,
On Tue, Mar 19, 2019 at 5:12 PM Andes <uboot@andestech.com> wrote:
>
> From: Rick Chen <rick@andestech.com>
>
nits: remove the ending period in the commit title
> Limit the cache configuration only can be supported in M mode.
> It can not be manipulated in S mode.
>
> Signed-off-by: Rick Chen <rick@andestech.com>
> Cc: Greentime Hu <greentime@andestech.com>
> ---
> arch/riscv/cpu/ax25/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Regards,
Bin
^ permalink raw reply [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH 7/9] riscv: ax25: Andes specific cache shall only support in M-mode.
2019-03-20 7:22 ` Bin Meng
@ 2019-03-21 8:42 ` Rick Chen
0 siblings, 0 replies; 38+ messages in thread
From: Rick Chen @ 2019-03-21 8:42 UTC (permalink / raw)
To: u-boot
Hi Bin
Bin Meng <bmeng.cn@gmail.com> 於 2019年3月20日 週三 下午3:22寫道:
>
> Hi Rick,
>
> On Tue, Mar 19, 2019 at 5:12 PM Andes <uboot@andestech.com> wrote:
> >
> > From: Rick Chen <rick@andestech.com>
> >
>
> nits: remove the ending period in the commit title
OK
I will remove it.
Thanks for review.
Rick
>
> > Limit the cache configuration only can be supported in M mode.
> > It can not be manipulated in S mode.
> >
> > Signed-off-by: Rick Chen <rick@andestech.com>
> > Cc: Greentime Hu <greentime@andestech.com>
> > ---
> > arch/riscv/cpu/ax25/Kconfig | 1 +
> > 1 file changed, 1 insertion(+)
> >
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
>
> Regards,
> Bin
^ permalink raw reply [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH 8/9] riscv: dts: ae350 support SMP.
2019-03-19 9:07 [U-Boot] [PATCH 0/9] AE350 SMP support RISC-V Andes
` (6 preceding siblings ...)
2019-03-19 9:07 ` [U-Boot] [PATCH 7/9] riscv: ax25: Andes specific cache shall only support in M-mode Andes
@ 2019-03-19 9:07 ` Andes
2019-03-20 7:22 ` Bin Meng
2019-03-19 9:07 ` [U-Boot] [PATCH 9/9] riscv: ae350: enable SMP Andes
8 siblings, 1 reply; 38+ messages in thread
From: Andes @ 2019-03-19 9:07 UTC (permalink / raw)
To: u-boot
From: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
---
arch/riscv/dts/ae350_32.dts | 81 +++++++++++++++++++++++++++++++++------------
arch/riscv/dts/ae350_64.dts | 47 +++++++++++++++++++++++---
2 files changed, 101 insertions(+), 27 deletions(-)
diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
index 0679827..0b4d966 100644
--- a/arch/riscv/dts/ae350_32.dts
+++ b/arch/riscv/dts/ae350_32.dts
@@ -25,17 +25,50 @@
reg = <0>;
status = "okay";
compatible = "riscv";
- riscv,isa = "rv32imafdc";
+ riscv,isa = "rv32i2p0m2p0a2p0f2p0d2p0c2p0xv5-0p0";
+ riscv,priv-major = <1>;
+ riscv,priv-minor = <10>;
mmu-type = "riscv,sv32";
clock-frequency = <60000000>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-line-size = <32>;
+ next-level-cache = <&L2>;
CPU0_intc: interrupt-controller {
#interrupt-cells = <1>;
interrupt-controller;
compatible = "riscv,cpu-intc";
};
};
+ CPU1: cpu at 1 {
+ device_type = "cpu";
+ reg = <1>;
+ status = "okay";
+ compatible = "riscv";
+ riscv,isa = "rv32i2p0m2p0a2p0f2p0d2p0c2p0xv5-0p0";
+ riscv,priv-major = <1>;
+ riscv,priv-minor = <10>;
+ mmu-type = "riscv,sv32";
+ clock-frequency = <60000000>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <32>;
+ next-level-cache = <&L2>;
+ CPU1_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "riscv,cpu-intc";
+ };
+ };
+
+ L2: l2-cache at e0500000 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <0x40000>;
+ reg = <0x0 0xe0500000 0x0 0x40000>;
+ };
};
memory at 0 {
@@ -49,29 +82,29 @@
compatible = "andestech,riscv-ae350-soc";
ranges;
- plic0: interrupt-controller at e4000000 {
- compatible = "riscv,plic0";
- #address-cells = <1>;
- #interrupt-cells = <1>;
- interrupt-controller;
- reg = <0xe4000000 0x2000000>;
- riscv,ndev=<71>;
- interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>;
- };
+ plic0: interrupt-controller at e4000000 {
+ compatible = "riscv,plic0";
+ #address-cells = <1>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ reg = <0xe4000000 0x2000000>;
+ riscv,ndev=<71>;
+ interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9 &CPU1_intc 11 &CPU1_intc 9>;
+ };
- plic1: interrupt-controller at e6400000 {
- compatible = "riscv,plic1";
- #address-cells = <1>;
- #interrupt-cells = <1>;
- interrupt-controller;
- reg = <0xe6400000 0x400000>;
- riscv,ndev=<1>;
- interrupts-extended = <&CPU0_intc 3>;
- };
+ plic1: interrupt-controller at e6400000 {
+ compatible = "riscv,plic1";
+ #address-cells = <1>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ reg = <0xe6400000 0x400000>;
+ riscv,ndev=<2>;
+ interrupts-extended = <&CPU0_intc 3 &CPU1_intc 3>;
+ };
- plmt0 at e6000000 {
- compatible = "riscv,plmt0";
- interrupts-extended = <&CPU0_intc 7>;
+ plmt0 at e6000000 {
+ compatible = "riscv,plmt0";
+ interrupts-extended = <&CPU0_intc 7 &CPU1_intc 7>;
reg = <0xe6000000 0x100000>;
};
};
@@ -146,6 +179,10 @@
interrupt-parent = <&plic0>;
};
+ pmu {
+ compatible = "riscv,base-pmu";
+ };
+
virtio_mmio at fe007000 {
interrupts = <0x17 0x4>;
interrupt-parent = <0x2>;
diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts
index e48c298..3c7e152 100644
--- a/arch/riscv/dts/ae350_64.dts
+++ b/arch/riscv/dts/ae350_64.dts
@@ -25,17 +25,50 @@
reg = <0>;
status = "okay";
compatible = "riscv";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64i2p0m2p0a2p0f2p0d2p0c2p0xv5-0p0";
+ riscv,priv-major = <1>;
+ riscv,priv-minor = <10>;
mmu-type = "riscv,sv39";
clock-frequency = <60000000>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-line-size = <32>;
+ next-level-cache = <&L2>;
CPU0_intc: interrupt-controller {
#interrupt-cells = <1>;
interrupt-controller;
compatible = "riscv,cpu-intc";
};
};
+ CPU1: cpu at 1 {
+ device_type = "cpu";
+ reg = <1>;
+ status = "okay";
+ compatible = "riscv";
+ riscv,isa = "rv64i2p0m2p0a2p0f2p0d2p0c2p0xv5-0p0";
+ riscv,priv-major = <1>;
+ riscv,priv-minor = <10>;
+ mmu-type = "riscv,sv39";
+ clock-frequency = <60000000>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <32>;
+ next-level-cache = <&L2>;
+ CPU1_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "riscv,cpu-intc";
+ };
+ };
+
+ L2: l2-cache at e0500000 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <0x40000>;
+ reg = <0x0 0xe0500000 0x0 0x40000>;
+ };
};
memory at 0 {
@@ -56,7 +89,7 @@
interrupt-controller;
reg = <0x0 0xe4000000 0x0 0x2000000>;
riscv,ndev=<71>;
- interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>;
+ interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9 &CPU1_intc 11 &CPU1_intc 9>;
};
plic1: interrupt-controller at e6400000 {
@@ -65,13 +98,13 @@
#interrupt-cells = <2>;
interrupt-controller;
reg = <0x0 0xe6400000 0x0 0x400000>;
- riscv,ndev=<1>;
- interrupts-extended = <&CPU0_intc 3>;
+ riscv,ndev=<2>;
+ interrupts-extended = <&CPU0_intc 3 &CPU1_intc 3>;
};
plmt0 at e6000000 {
compatible = "riscv,plmt0";
- interrupts-extended = <&CPU0_intc 7>;
+ interrupts-extended = <&CPU0_intc 7 &CPU1_intc 7>;
reg = <0x0 0xe6000000 0x0 0x100000>;
};
};
@@ -146,6 +179,10 @@
interrupt-parent = <&plic0>;
};
+ pmu {
+ compatible = "riscv,base-pmu";
+ };
+
virtio_mmio at fe007000 {
interrupts = <0x17 0x4>;
interrupt-parent = <0x2>;
--
2.7.4
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH 8/9] riscv: dts: ae350 support SMP.
2019-03-19 9:07 ` [U-Boot] [PATCH 8/9] riscv: dts: ae350 support SMP Andes
@ 2019-03-20 7:22 ` Bin Meng
2019-03-21 8:51 ` Rick Chen
0 siblings, 1 reply; 38+ messages in thread
From: Bin Meng @ 2019-03-20 7:22 UTC (permalink / raw)
To: u-boot
Hi Rick,
On Tue, Mar 19, 2019 at 5:13 PM Andes <uboot@andestech.com> wrote:
>
> From: Rick Chen <rick@andestech.com>
>
nits: remove the ending period in the commit title.
> Signed-off-by: Rick Chen <rick@andestech.com>
> Cc: Greentime Hu <greentime@andestech.com>
> ---
> arch/riscv/dts/ae350_32.dts | 81 +++++++++++++++++++++++++++++++++------------
> arch/riscv/dts/ae350_64.dts | 47 +++++++++++++++++++++++---
> 2 files changed, 101 insertions(+), 27 deletions(-)
>
> diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
> index 0679827..0b4d966 100644
> --- a/arch/riscv/dts/ae350_32.dts
> +++ b/arch/riscv/dts/ae350_32.dts
> @@ -25,17 +25,50 @@
> reg = <0>;
> status = "okay";
> compatible = "riscv";
> - riscv,isa = "rv32imafdc";
> + riscv,isa = "rv32i2p0m2p0a2p0f2p0d2p0c2p0xv5-0p0";
I am not sure what is this. Is this something approved?
> + riscv,priv-major = <1>;
> + riscv,priv-minor = <10>;
> mmu-type = "riscv,sv32";
> clock-frequency = <60000000>;
> + i-cache-size = <0x8000>;
> + i-cache-line-size = <32>;
> d-cache-size = <0x8000>;
> d-cache-line-size = <32>;
> + next-level-cache = <&L2>;
> CPU0_intc: interrupt-controller {
> #interrupt-cells = <1>;
> interrupt-controller;
> compatible = "riscv,cpu-intc";
> };
> };
> + CPU1: cpu at 1 {
> + device_type = "cpu";
> + reg = <1>;
> + status = "okay";
> + compatible = "riscv";
> + riscv,isa = "rv32i2p0m2p0a2p0f2p0d2p0c2p0xv5-0p0";
> + riscv,priv-major = <1>;
> + riscv,priv-minor = <10>;
> + mmu-type = "riscv,sv32";
> + clock-frequency = <60000000>;
> + i-cache-size = <0x8000>;
> + i-cache-line-size = <32>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <32>;
> + next-level-cache = <&L2>;
> + CPU1_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + compatible = "riscv,cpu-intc";
> + };
> + };
> +
> + L2: l2-cache at e0500000 {
> + compatible = "cache";
> + cache-level = <2>;
> + cache-size = <0x40000>;
> + reg = <0x0 0xe0500000 0x0 0x40000>;
> + };
> };
>
> memory at 0 {
> @@ -49,29 +82,29 @@
> compatible = "andestech,riscv-ae350-soc";
> ranges;
>
> - plic0: interrupt-controller at e4000000 {
> - compatible = "riscv,plic0";
> - #address-cells = <1>;
> - #interrupt-cells = <1>;
> - interrupt-controller;
> - reg = <0xe4000000 0x2000000>;
> - riscv,ndev=<71>;
> - interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>;
> - };
> + plic0: interrupt-controller at e4000000 {
> + compatible = "riscv,plic0";
> + #address-cells = <1>;
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + reg = <0xe4000000 0x2000000>;
> + riscv,ndev=<71>;
> + interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9 &CPU1_intc 11 &CPU1_intc 9>;
> + };
>
> - plic1: interrupt-controller at e6400000 {
> - compatible = "riscv,plic1";
> - #address-cells = <1>;
> - #interrupt-cells = <1>;
> - interrupt-controller;
> - reg = <0xe6400000 0x400000>;
> - riscv,ndev=<1>;
> - interrupts-extended = <&CPU0_intc 3>;
> - };
> + plic1: interrupt-controller at e6400000 {
> + compatible = "riscv,plic1";
> + #address-cells = <1>;
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + reg = <0xe6400000 0x400000>;
> + riscv,ndev=<2>;
> + interrupts-extended = <&CPU0_intc 3 &CPU1_intc 3>;
> + };
>
> - plmt0 at e6000000 {
> - compatible = "riscv,plmt0";
> - interrupts-extended = <&CPU0_intc 7>;
> + plmt0 at e6000000 {
> + compatible = "riscv,plmt0";
> + interrupts-extended = <&CPU0_intc 7 &CPU1_intc 7>;
> reg = <0xe6000000 0x100000>;
> };
> };
> @@ -146,6 +179,10 @@
> interrupt-parent = <&plic0>;
> };
>
> + pmu {
> + compatible = "riscv,base-pmu";
> + };
> +
> virtio_mmio at fe007000 {
> interrupts = <0x17 0x4>;
> interrupt-parent = <0x2>;
> diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts
> index e48c298..3c7e152 100644
> --- a/arch/riscv/dts/ae350_64.dts
> +++ b/arch/riscv/dts/ae350_64.dts
> @@ -25,17 +25,50 @@
> reg = <0>;
> status = "okay";
> compatible = "riscv";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64i2p0m2p0a2p0f2p0d2p0c2p0xv5-0p0";
> + riscv,priv-major = <1>;
> + riscv,priv-minor = <10>;
> mmu-type = "riscv,sv39";
> clock-frequency = <60000000>;
> + i-cache-size = <0x8000>;
> + i-cache-line-size = <32>;
> d-cache-size = <0x8000>;
> d-cache-line-size = <32>;
> + next-level-cache = <&L2>;
> CPU0_intc: interrupt-controller {
> #interrupt-cells = <1>;
> interrupt-controller;
> compatible = "riscv,cpu-intc";
> };
> };
> + CPU1: cpu at 1 {
> + device_type = "cpu";
> + reg = <1>;
> + status = "okay";
> + compatible = "riscv";
> + riscv,isa = "rv64i2p0m2p0a2p0f2p0d2p0c2p0xv5-0p0";
> + riscv,priv-major = <1>;
> + riscv,priv-minor = <10>;
> + mmu-type = "riscv,sv39";
> + clock-frequency = <60000000>;
> + i-cache-size = <0x8000>;
> + i-cache-line-size = <32>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <32>;
> + next-level-cache = <&L2>;
> + CPU1_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + compatible = "riscv,cpu-intc";
> + };
> + };
> +
> + L2: l2-cache at e0500000 {
> + compatible = "cache";
> + cache-level = <2>;
> + cache-size = <0x40000>;
> + reg = <0x0 0xe0500000 0x0 0x40000>;
> + };
> };
>
> memory at 0 {
> @@ -56,7 +89,7 @@
> interrupt-controller;
> reg = <0x0 0xe4000000 0x0 0x2000000>;
> riscv,ndev=<71>;
> - interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>;
> + interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9 &CPU1_intc 11 &CPU1_intc 9>;
> };
>
> plic1: interrupt-controller at e6400000 {
> @@ -65,13 +98,13 @@
> #interrupt-cells = <2>;
> interrupt-controller;
> reg = <0x0 0xe6400000 0x0 0x400000>;
> - riscv,ndev=<1>;
> - interrupts-extended = <&CPU0_intc 3>;
> + riscv,ndev=<2>;
> + interrupts-extended = <&CPU0_intc 3 &CPU1_intc 3>;
> };
>
> plmt0 at e6000000 {
> compatible = "riscv,plmt0";
> - interrupts-extended = <&CPU0_intc 7>;
> + interrupts-extended = <&CPU0_intc 7 &CPU1_intc 7>;
> reg = <0x0 0xe6000000 0x0 0x100000>;
> };
> };
> @@ -146,6 +179,10 @@
> interrupt-parent = <&plic0>;
> };
>
> + pmu {
> + compatible = "riscv,base-pmu";
> + };
> +
> virtio_mmio at fe007000 {
> interrupts = <0x17 0x4>;
> interrupt-parent = <0x2>;
> --
Regards,
Bin
^ permalink raw reply [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH 8/9] riscv: dts: ae350 support SMP.
2019-03-20 7:22 ` Bin Meng
@ 2019-03-21 8:51 ` Rick Chen
2019-03-21 9:15 ` Bin Meng
0 siblings, 1 reply; 38+ messages in thread
From: Rick Chen @ 2019-03-21 8:51 UTC (permalink / raw)
To: u-boot
Hi Bin
Bin Meng <bmeng.cn@gmail.com> 於 2019年3月20日 週三 下午3:22寫道:
>
> Hi Rick,
>
> On Tue, Mar 19, 2019 at 5:13 PM Andes <uboot@andestech.com> wrote:
> >
> > From: Rick Chen <rick@andestech.com>
> >
>
> nits: remove the ending period in the commit title.
OK.
I will remove it.
>
> > Signed-off-by: Rick Chen <rick@andestech.com>
> > Cc: Greentime Hu <greentime@andestech.com>
> > ---
> > arch/riscv/dts/ae350_32.dts | 81 +++++++++++++++++++++++++++++++++------------
> > arch/riscv/dts/ae350_64.dts | 47 +++++++++++++++++++++++---
> > 2 files changed, 101 insertions(+), 27 deletions(-)
> >
> > diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
> > index 0679827..0b4d966 100644
> > --- a/arch/riscv/dts/ae350_32.dts
> > +++ b/arch/riscv/dts/ae350_32.dts
> > @@ -25,17 +25,50 @@
> > reg = <0>;
> > status = "okay";
> > compatible = "riscv";
> > - riscv,isa = "rv32imafdc";
> > + riscv,isa = "rv32i2p0m2p0a2p0f2p0d2p0c2p0xv5-0p0";
>
> I am not sure what is this. Is this something approved?
It is about elf checking (attribute) and seem has been upstream to GCC.
https://patchwork.ozlabs.org/cover/1040998/
Thanks
Rick
>
> > + riscv,priv-major = <1>;
> > + riscv,priv-minor = <10>;
> > mmu-type = "riscv,sv32";
> > clock-frequency = <60000000>;
> > + i-cache-size = <0x8000>;
> > + i-cache-line-size = <32>;
> > d-cache-size = <0x8000>;
> > d-cache-line-size = <32>;
> > + next-level-cache = <&L2>;
> > CPU0_intc: interrupt-controller {
> > #interrupt-cells = <1>;
> > interrupt-controller;
> > compatible = "riscv,cpu-intc";
> > };
> > };
> > + CPU1: cpu at 1 {
> > + device_type = "cpu";
> > + reg = <1>;
> > + status = "okay";
> > + compatible = "riscv";
> > + riscv,isa = "rv32i2p0m2p0a2p0f2p0d2p0c2p0xv5-0p0";
> > + riscv,priv-major = <1>;
> > + riscv,priv-minor = <10>;
> > + mmu-type = "riscv,sv32";
> > + clock-frequency = <60000000>;
> > + i-cache-size = <0x8000>;
> > + i-cache-line-size = <32>;
> > + d-cache-size = <0x8000>;
> > + d-cache-line-size = <32>;
> > + next-level-cache = <&L2>;
> > + CPU1_intc: interrupt-controller {
> > + #interrupt-cells = <1>;
> > + interrupt-controller;
> > + compatible = "riscv,cpu-intc";
> > + };
> > + };
> > +
> > + L2: l2-cache at e0500000 {
> > + compatible = "cache";
> > + cache-level = <2>;
> > + cache-size = <0x40000>;
> > + reg = <0x0 0xe0500000 0x0 0x40000>;
> > + };
> > };
> >
> > memory at 0 {
> > @@ -49,29 +82,29 @@
> > compatible = "andestech,riscv-ae350-soc";
> > ranges;
> >
> > - plic0: interrupt-controller at e4000000 {
> > - compatible = "riscv,plic0";
> > - #address-cells = <1>;
> > - #interrupt-cells = <1>;
> > - interrupt-controller;
> > - reg = <0xe4000000 0x2000000>;
> > - riscv,ndev=<71>;
> > - interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>;
> > - };
> > + plic0: interrupt-controller at e4000000 {
> > + compatible = "riscv,plic0";
> > + #address-cells = <1>;
> > + #interrupt-cells = <1>;
> > + interrupt-controller;
> > + reg = <0xe4000000 0x2000000>;
> > + riscv,ndev=<71>;
> > + interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9 &CPU1_intc 11 &CPU1_intc 9>;
> > + };
> >
> > - plic1: interrupt-controller at e6400000 {
> > - compatible = "riscv,plic1";
> > - #address-cells = <1>;
> > - #interrupt-cells = <1>;
> > - interrupt-controller;
> > - reg = <0xe6400000 0x400000>;
> > - riscv,ndev=<1>;
> > - interrupts-extended = <&CPU0_intc 3>;
> > - };
> > + plic1: interrupt-controller at e6400000 {
> > + compatible = "riscv,plic1";
> > + #address-cells = <1>;
> > + #interrupt-cells = <1>;
> > + interrupt-controller;
> > + reg = <0xe6400000 0x400000>;
> > + riscv,ndev=<2>;
> > + interrupts-extended = <&CPU0_intc 3 &CPU1_intc 3>;
> > + };
> >
> > - plmt0 at e6000000 {
> > - compatible = "riscv,plmt0";
> > - interrupts-extended = <&CPU0_intc 7>;
> > + plmt0 at e6000000 {
> > + compatible = "riscv,plmt0";
> > + interrupts-extended = <&CPU0_intc 7 &CPU1_intc 7>;
> > reg = <0xe6000000 0x100000>;
> > };
> > };
> > @@ -146,6 +179,10 @@
> > interrupt-parent = <&plic0>;
> > };
> >
> > + pmu {
> > + compatible = "riscv,base-pmu";
> > + };
> > +
> > virtio_mmio at fe007000 {
> > interrupts = <0x17 0x4>;
> > interrupt-parent = <0x2>;
> > diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts
> > index e48c298..3c7e152 100644
> > --- a/arch/riscv/dts/ae350_64.dts
> > +++ b/arch/riscv/dts/ae350_64.dts
> > @@ -25,17 +25,50 @@
> > reg = <0>;
> > status = "okay";
> > compatible = "riscv";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64i2p0m2p0a2p0f2p0d2p0c2p0xv5-0p0";
> > + riscv,priv-major = <1>;
> > + riscv,priv-minor = <10>;
> > mmu-type = "riscv,sv39";
> > clock-frequency = <60000000>;
> > + i-cache-size = <0x8000>;
> > + i-cache-line-size = <32>;
> > d-cache-size = <0x8000>;
> > d-cache-line-size = <32>;
> > + next-level-cache = <&L2>;
> > CPU0_intc: interrupt-controller {
> > #interrupt-cells = <1>;
> > interrupt-controller;
> > compatible = "riscv,cpu-intc";
> > };
> > };
> > + CPU1: cpu at 1 {
> > + device_type = "cpu";
> > + reg = <1>;
> > + status = "okay";
> > + compatible = "riscv";
> > + riscv,isa = "rv64i2p0m2p0a2p0f2p0d2p0c2p0xv5-0p0";
> > + riscv,priv-major = <1>;
> > + riscv,priv-minor = <10>;
> > + mmu-type = "riscv,sv39";
> > + clock-frequency = <60000000>;
> > + i-cache-size = <0x8000>;
> > + i-cache-line-size = <32>;
> > + d-cache-size = <0x8000>;
> > + d-cache-line-size = <32>;
> > + next-level-cache = <&L2>;
> > + CPU1_intc: interrupt-controller {
> > + #interrupt-cells = <1>;
> > + interrupt-controller;
> > + compatible = "riscv,cpu-intc";
> > + };
> > + };
> > +
> > + L2: l2-cache at e0500000 {
> > + compatible = "cache";
> > + cache-level = <2>;
> > + cache-size = <0x40000>;
> > + reg = <0x0 0xe0500000 0x0 0x40000>;
> > + };
> > };
> >
> > memory at 0 {
> > @@ -56,7 +89,7 @@
> > interrupt-controller;
> > reg = <0x0 0xe4000000 0x0 0x2000000>;
> > riscv,ndev=<71>;
> > - interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>;
> > + interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9 &CPU1_intc 11 &CPU1_intc 9>;
> > };
> >
> > plic1: interrupt-controller at e6400000 {
> > @@ -65,13 +98,13 @@
> > #interrupt-cells = <2>;
> > interrupt-controller;
> > reg = <0x0 0xe6400000 0x0 0x400000>;
> > - riscv,ndev=<1>;
> > - interrupts-extended = <&CPU0_intc 3>;
> > + riscv,ndev=<2>;
> > + interrupts-extended = <&CPU0_intc 3 &CPU1_intc 3>;
> > };
> >
> > plmt0 at e6000000 {
> > compatible = "riscv,plmt0";
> > - interrupts-extended = <&CPU0_intc 7>;
> > + interrupts-extended = <&CPU0_intc 7 &CPU1_intc 7>;
> > reg = <0x0 0xe6000000 0x0 0x100000>;
> > };
> > };
> > @@ -146,6 +179,10 @@
> > interrupt-parent = <&plic0>;
> > };
> >
> > + pmu {
> > + compatible = "riscv,base-pmu";
> > + };
> > +
> > virtio_mmio at fe007000 {
> > interrupts = <0x17 0x4>;
> > interrupt-parent = <0x2>;
> > --
>
> Regards,
> Bin
^ permalink raw reply [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH 8/9] riscv: dts: ae350 support SMP.
2019-03-21 8:51 ` Rick Chen
@ 2019-03-21 9:15 ` Bin Meng
2019-03-21 9:38 ` Rick Chen
0 siblings, 1 reply; 38+ messages in thread
From: Bin Meng @ 2019-03-21 9:15 UTC (permalink / raw)
To: u-boot
Hi Rick,
On Thu, Mar 21, 2019 at 4:51 PM Rick Chen <rickchen36@gmail.com> wrote:
>
> Hi Bin
>
> Bin Meng <bmeng.cn@gmail.com> 於 2019年3月20日 週三 下午3:22寫道:
> >
> > Hi Rick,
> >
> > On Tue, Mar 19, 2019 at 5:13 PM Andes <uboot@andestech.com> wrote:
> > >
> > > From: Rick Chen <rick@andestech.com>
> > >
> >
> > nits: remove the ending period in the commit title.
>
> OK.
> I will remove it.
>
> >
> > > Signed-off-by: Rick Chen <rick@andestech.com>
> > > Cc: Greentime Hu <greentime@andestech.com>
> > > ---
> > > arch/riscv/dts/ae350_32.dts | 81 +++++++++++++++++++++++++++++++++------------
> > > arch/riscv/dts/ae350_64.dts | 47 +++++++++++++++++++++++---
> > > 2 files changed, 101 insertions(+), 27 deletions(-)
> > >
> > > diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
> > > index 0679827..0b4d966 100644
> > > --- a/arch/riscv/dts/ae350_32.dts
> > > +++ b/arch/riscv/dts/ae350_32.dts
> > > @@ -25,17 +25,50 @@
> > > reg = <0>;
> > > status = "okay";
> > > compatible = "riscv";
> > > - riscv,isa = "rv32imafdc";
> > > + riscv,isa = "rv32i2p0m2p0a2p0f2p0d2p0c2p0xv5-0p0";
> >
> > I am not sure what is this. Is this something approved?
>
> It is about elf checking (attribute) and seem has been upstream to GCC.
> https://patchwork.ozlabs.org/cover/1040998/
>
So that patch affects GCC's "-march" string? But why do we need adjust
the "riscv,isa" string in DT?
Regards,
Bin
^ permalink raw reply [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH 8/9] riscv: dts: ae350 support SMP.
2019-03-21 9:15 ` Bin Meng
@ 2019-03-21 9:38 ` Rick Chen
2019-03-21 10:12 ` Bin Meng
0 siblings, 1 reply; 38+ messages in thread
From: Rick Chen @ 2019-03-21 9:38 UTC (permalink / raw)
To: u-boot
Bin Meng <bmeng.cn@gmail.com> 於 2019年3月21日 週四 下午5:15寫道:
>
> Hi Rick,
>
> On Thu, Mar 21, 2019 at 4:51 PM Rick Chen <rickchen36@gmail.com> wrote:
> >
> > Hi Bin
> >
> > Bin Meng <bmeng.cn@gmail.com> 於 2019年3月20日 週三 下午3:22寫道:
> > >
> > > Hi Rick,
> > >
> > > On Tue, Mar 19, 2019 at 5:13 PM Andes <uboot@andestech.com> wrote:
> > > >
> > > > From: Rick Chen <rick@andestech.com>
> > > >
> > >
> > > nits: remove the ending period in the commit title.
> >
> > OK.
> > I will remove it.
> >
> > >
> > > > Signed-off-by: Rick Chen <rick@andestech.com>
> > > > Cc: Greentime Hu <greentime@andestech.com>
> > > > ---
> > > > arch/riscv/dts/ae350_32.dts | 81 +++++++++++++++++++++++++++++++++------------
> > > > arch/riscv/dts/ae350_64.dts | 47 +++++++++++++++++++++++---
> > > > 2 files changed, 101 insertions(+), 27 deletions(-)
> > > >
> > > > diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
> > > > index 0679827..0b4d966 100644
> > > > --- a/arch/riscv/dts/ae350_32.dts
> > > > +++ b/arch/riscv/dts/ae350_32.dts
> > > > @@ -25,17 +25,50 @@
> > > > reg = <0>;
> > > > status = "okay";
> > > > compatible = "riscv";
> > > > - riscv,isa = "rv32imafdc";
> > > > + riscv,isa = "rv32i2p0m2p0a2p0f2p0d2p0c2p0xv5-0p0";
> > >
> > > I am not sure what is this. Is this something approved?
> >
> > It is about elf checking (attribute) and seem has been upstream to GCC.
> > https://patchwork.ozlabs.org/cover/1040998/
> >
>
> So that patch affects GCC's "-march" string? But why do we need adjust
> the "riscv,isa" string in DT?
>
We will use this to check user program (binutils will assign this
string) when it run in kernel at run time.
> Regards,
> Bin
^ permalink raw reply [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH 8/9] riscv: dts: ae350 support SMP.
2019-03-21 9:38 ` Rick Chen
@ 2019-03-21 10:12 ` Bin Meng
2019-03-21 10:16 ` Rick Chen
0 siblings, 1 reply; 38+ messages in thread
From: Bin Meng @ 2019-03-21 10:12 UTC (permalink / raw)
To: u-boot
Hi Rick,
On Thu, Mar 21, 2019 at 5:37 PM Rick Chen <rickchen36@gmail.com> wrote:
>
> Bin Meng <bmeng.cn@gmail.com> 於 2019年3月21日 週四 下午5:15寫道:
> >
> > Hi Rick,
> >
> > On Thu, Mar 21, 2019 at 4:51 PM Rick Chen <rickchen36@gmail.com> wrote:
> > >
> > > Hi Bin
> > >
> > > Bin Meng <bmeng.cn@gmail.com> 於 2019年3月20日 週三 下午3:22寫道:
> > > >
> > > > Hi Rick,
> > > >
> > > > On Tue, Mar 19, 2019 at 5:13 PM Andes <uboot@andestech.com> wrote:
> > > > >
> > > > > From: Rick Chen <rick@andestech.com>
> > > > >
> > > >
> > > > nits: remove the ending period in the commit title.
> > >
> > > OK.
> > > I will remove it.
> > >
> > > >
> > > > > Signed-off-by: Rick Chen <rick@andestech.com>
> > > > > Cc: Greentime Hu <greentime@andestech.com>
> > > > > ---
> > > > > arch/riscv/dts/ae350_32.dts | 81 +++++++++++++++++++++++++++++++++------------
> > > > > arch/riscv/dts/ae350_64.dts | 47 +++++++++++++++++++++++---
> > > > > 2 files changed, 101 insertions(+), 27 deletions(-)
> > > > >
> > > > > diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
> > > > > index 0679827..0b4d966 100644
> > > > > --- a/arch/riscv/dts/ae350_32.dts
> > > > > +++ b/arch/riscv/dts/ae350_32.dts
> > > > > @@ -25,17 +25,50 @@
> > > > > reg = <0>;
> > > > > status = "okay";
> > > > > compatible = "riscv";
> > > > > - riscv,isa = "rv32imafdc";
> > > > > + riscv,isa = "rv32i2p0m2p0a2p0f2p0d2p0c2p0xv5-0p0";
> > > >
> > > > I am not sure what is this. Is this something approved?
> > >
> > > It is about elf checking (attribute) and seem has been upstream to GCC.
> > > https://patchwork.ozlabs.org/cover/1040998/
> > >
> >
> > So that patch affects GCC's "-march" string? But why do we need adjust
> > the "riscv,isa" string in DT?
> >
>
> We will use this to check user program (binutils will assign this
> string) when it run in kernel at run time.
Do you have details about this binutils checks? Is this new string
approved by the DT upstream? At least I see latest QEMU still
generates the old string.
Regards,
Bin
^ permalink raw reply [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH 8/9] riscv: dts: ae350 support SMP.
2019-03-21 10:12 ` Bin Meng
@ 2019-03-21 10:16 ` Rick Chen
0 siblings, 0 replies; 38+ messages in thread
From: Rick Chen @ 2019-03-21 10:16 UTC (permalink / raw)
To: u-boot
Bin Meng <bmeng.cn@gmail.com> 於 2019年3月21日 週四 下午6:12寫道:
>
> Hi Rick,
>
> On Thu, Mar 21, 2019 at 5:37 PM Rick Chen <rickchen36@gmail.com> wrote:
> >
> > Bin Meng <bmeng.cn@gmail.com> 於 2019年3月21日 週四 下午5:15寫道:
> > >
> > > Hi Rick,
> > >
> > > On Thu, Mar 21, 2019 at 4:51 PM Rick Chen <rickchen36@gmail.com> wrote:
> > > >
> > > > Hi Bin
> > > >
> > > > Bin Meng <bmeng.cn@gmail.com> 於 2019年3月20日 週三 下午3:22寫道:
> > > > >
> > > > > Hi Rick,
> > > > >
> > > > > On Tue, Mar 19, 2019 at 5:13 PM Andes <uboot@andestech.com> wrote:
> > > > > >
> > > > > > From: Rick Chen <rick@andestech.com>
> > > > > >
> > > > >
> > > > > nits: remove the ending period in the commit title.
> > > >
> > > > OK.
> > > > I will remove it.
> > > >
> > > > >
> > > > > > Signed-off-by: Rick Chen <rick@andestech.com>
> > > > > > Cc: Greentime Hu <greentime@andestech.com>
> > > > > > ---
> > > > > > arch/riscv/dts/ae350_32.dts | 81 +++++++++++++++++++++++++++++++++------------
> > > > > > arch/riscv/dts/ae350_64.dts | 47 +++++++++++++++++++++++---
> > > > > > 2 files changed, 101 insertions(+), 27 deletions(-)
> > > > > >
> > > > > > diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
> > > > > > index 0679827..0b4d966 100644
> > > > > > --- a/arch/riscv/dts/ae350_32.dts
> > > > > > +++ b/arch/riscv/dts/ae350_32.dts
> > > > > > @@ -25,17 +25,50 @@
> > > > > > reg = <0>;
> > > > > > status = "okay";
> > > > > > compatible = "riscv";
> > > > > > - riscv,isa = "rv32imafdc";
> > > > > > + riscv,isa = "rv32i2p0m2p0a2p0f2p0d2p0c2p0xv5-0p0";
> > > > >
> > > > > I am not sure what is this. Is this something approved?
> > > >
> > > > It is about elf checking (attribute) and seem has been upstream to GCC.
> > > > https://patchwork.ozlabs.org/cover/1040998/
> > > >
> > >
> > > So that patch affects GCC's "-march" string? But why do we need adjust
> > > the "riscv,isa" string in DT?
> > >
> >
> > We will use this to check user program (binutils will assign this
> > string) when it run in kernel at run time.
>
> Do you have details about this binutils checks? Is this new string
> approved by the DT upstream? At least I see latest QEMU still
> generates the old string.
The string is NOT approved by the DT upstream.
We use it internally .
>
> Regards,
> Bin
^ permalink raw reply [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH 9/9] riscv: ae350: enable SMP
2019-03-19 9:07 [U-Boot] [PATCH 0/9] AE350 SMP support RISC-V Andes
` (7 preceding siblings ...)
2019-03-19 9:07 ` [U-Boot] [PATCH 8/9] riscv: dts: ae350 support SMP Andes
@ 2019-03-19 9:07 ` Andes
2019-03-20 7:22 ` Bin Meng
8 siblings, 1 reply; 38+ messages in thread
From: Andes @ 2019-03-19 9:07 UTC (permalink / raw)
To: u-boot
From: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
---
board/AndesTech/ax25-ae350/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/board/AndesTech/ax25-ae350/Kconfig b/board/AndesTech/ax25-ae350/Kconfig
index 44cb302..5e682b6 100644
--- a/board/AndesTech/ax25-ae350/Kconfig
+++ b/board/AndesTech/ax25-ae350/Kconfig
@@ -24,5 +24,6 @@ config ENV_OFFSET
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select RISCV_NDS
+ imply SMP
endif
--
2.7.4
^ permalink raw reply related [flat|nested] 38+ messages in thread