From: Guo Ren <guoren@kernel.org> To: "Christoph Müllner" <christophm30@gmail.com> Cc: Peter Zijlstra <peterz@infradead.org>, Palmer Dabbelt <palmer@dabbelt.com>, Anup Patel <anup@brainfault.org>, linux-riscv <linux-riscv@lists.infradead.org>, Linux Kernel Mailing List <linux-kernel@vger.kernel.org>, Guo Ren <guoren@linux.alibaba.com>, Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will.deacon@arm.com>, Arnd Bergmann <arnd@arndb.de> Subject: Re: [PATCH] riscv: locks: introduce ticket-based spinlock implementation Date: Tue, 13 Apr 2021 21:19:21 +0800 [thread overview] Message-ID: <CAJF2gTSGwt-hHbYiBUdiUbo+BTkyQtv_XNkLYws-EJcwURQbLQ@mail.gmail.com> (raw) In-Reply-To: <CAHB2gtTzEuD7j-+5ztui0eV6UNiEisBTgoK+2Sr=Z0b4PPXRyA@mail.gmail.com> On Tue, Apr 13, 2021 at 6:25 PM Christoph Müllner <christophm30@gmail.com> wrote: > > On Tue, Apr 13, 2021 at 11:37 AM Peter Zijlstra <peterz@infradead.org> wrote: > > > > On Tue, Apr 13, 2021 at 11:22:40AM +0200, Christoph Müllner wrote: > > > > > > For ticket locks you really only needs atomic_fetch_add() and > > > > smp_store_release() and an architectural guarantees that the > > > > atomic_fetch_add() has fwd progress under contention and that a sub-word > > > > store (through smp_store_release()) will fail the SC. > > > > > > > > Then you can do something like: > > > > > > > > void lock(atomic_t *lock) > > > > { > > > > u32 val = atomic_fetch_add(1<<16, lock); /* SC, gives us RCsc */ > > > > u16 ticket = val >> 16; > > > > > > > > for (;;) { > > > > if (ticket == (u16)val) > > > > break; > > > > cpu_relax(); > > > > val = atomic_read_acquire(lock); > > > > } > > > > } > > > > > > > > void unlock(atomic_t *lock) > > > > { > > > > u16 *ptr = (u16 *)lock + (!!__BIG_ENDIAN__); > > > > u32 val = atomic_read(lock); > > > > > > > > smp_store_release(ptr, (u16)val + 1); > > > > } > > > > > > > > That's _almost_ as simple as a test-and-set :-) It isn't quite optimal > > > > on x86 for not being allowed to use a memop on unlock, since its being > > > > forced into a load-store because of all the volatile, but whatever. > > > > > > What about trylock()? > > > I.e. one could implement trylock() without a loop, by letting > > > trylock() fail if the SC fails. > > > That looks safe on first view, but nobody does this right now. > > > > Generic code has to use cmpxchg(), and then you get something like this: > > > > bool trylock(atomic_t *lock) > > { > > u32 old = atomic_read(lock); > > > > if ((old >> 16) != (old & 0xffff)) > > return false; > > > > return atomic_try_cmpxchg(lock, &old, old + (1<<16)); /* SC, for RCsc */ > > } > > This approach requires two loads (atomic_read() and cmpxchg()), which > is not required. > Detecting this pattern and optimizing it in a compiler is quite unlikely. > > A bit less generic solution would be to wrap the LL/SC (would be > mandatory in this case) > instructions and do something like this: > > uint32_t __smp_load_acquire_reserved(void*); > int __smp_store_release_conditional(void*, uint32_t); > > typedef union { > uint32_t v32; > struct { > uint16_t owner; > uint16_t next; > }; > } arch_spinlock_t; > > int trylock(arch_spinlock_t *lock) > { > arch_spinlock_t l; > int success; > do { > l.v32 = __smp_load_acquire_reserved(lock); > if (l.owner != l.next) > return 0; > l.next++; > success = __smp_store_release_conditional(lock, l.v32); It's a new semantics v.s cmpxchg, and cmpxchg is come from CAS instruction to solve some complex scenario. The primitive of cmpxchg has been widely used in Linux, so I don't think introducing a new semantics (reserved_conditional) is a good idea. Also, from this point: It seems CAS instruction is more suitable for software compatibility. Although riscv privilege spec chose the LR/SC and list some bad sides of CAS. > } while (!success); > return success; > } > > But here we can't tell the compiler to optimize the code between LL and SC... > > > > > That will try and do the full LL/SC loop, because it wants to complete > > the cmpxchg, but in generic code we have no other option. > > > > (Is this what C11's weak cmpxchg is for?) -- Best Regards Guo Ren ML: https://lore.kernel.org/linux-csky/
WARNING: multiple messages have this Message-ID (diff)
From: Guo Ren <guoren@kernel.org> To: "Christoph Müllner" <christophm30@gmail.com> Cc: Peter Zijlstra <peterz@infradead.org>, Palmer Dabbelt <palmer@dabbelt.com>, Anup Patel <anup@brainfault.org>, linux-riscv <linux-riscv@lists.infradead.org>, Linux Kernel Mailing List <linux-kernel@vger.kernel.org>, Guo Ren <guoren@linux.alibaba.com>, Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will.deacon@arm.com>, Arnd Bergmann <arnd@arndb.de> Subject: Re: [PATCH] riscv: locks: introduce ticket-based spinlock implementation Date: Tue, 13 Apr 2021 21:19:21 +0800 [thread overview] Message-ID: <CAJF2gTSGwt-hHbYiBUdiUbo+BTkyQtv_XNkLYws-EJcwURQbLQ@mail.gmail.com> (raw) In-Reply-To: <CAHB2gtTzEuD7j-+5ztui0eV6UNiEisBTgoK+2Sr=Z0b4PPXRyA@mail.gmail.com> On Tue, Apr 13, 2021 at 6:25 PM Christoph Müllner <christophm30@gmail.com> wrote: > > On Tue, Apr 13, 2021 at 11:37 AM Peter Zijlstra <peterz@infradead.org> wrote: > > > > On Tue, Apr 13, 2021 at 11:22:40AM +0200, Christoph Müllner wrote: > > > > > > For ticket locks you really only needs atomic_fetch_add() and > > > > smp_store_release() and an architectural guarantees that the > > > > atomic_fetch_add() has fwd progress under contention and that a sub-word > > > > store (through smp_store_release()) will fail the SC. > > > > > > > > Then you can do something like: > > > > > > > > void lock(atomic_t *lock) > > > > { > > > > u32 val = atomic_fetch_add(1<<16, lock); /* SC, gives us RCsc */ > > > > u16 ticket = val >> 16; > > > > > > > > for (;;) { > > > > if (ticket == (u16)val) > > > > break; > > > > cpu_relax(); > > > > val = atomic_read_acquire(lock); > > > > } > > > > } > > > > > > > > void unlock(atomic_t *lock) > > > > { > > > > u16 *ptr = (u16 *)lock + (!!__BIG_ENDIAN__); > > > > u32 val = atomic_read(lock); > > > > > > > > smp_store_release(ptr, (u16)val + 1); > > > > } > > > > > > > > That's _almost_ as simple as a test-and-set :-) It isn't quite optimal > > > > on x86 for not being allowed to use a memop on unlock, since its being > > > > forced into a load-store because of all the volatile, but whatever. > > > > > > What about trylock()? > > > I.e. one could implement trylock() without a loop, by letting > > > trylock() fail if the SC fails. > > > That looks safe on first view, but nobody does this right now. > > > > Generic code has to use cmpxchg(), and then you get something like this: > > > > bool trylock(atomic_t *lock) > > { > > u32 old = atomic_read(lock); > > > > if ((old >> 16) != (old & 0xffff)) > > return false; > > > > return atomic_try_cmpxchg(lock, &old, old + (1<<16)); /* SC, for RCsc */ > > } > > This approach requires two loads (atomic_read() and cmpxchg()), which > is not required. > Detecting this pattern and optimizing it in a compiler is quite unlikely. > > A bit less generic solution would be to wrap the LL/SC (would be > mandatory in this case) > instructions and do something like this: > > uint32_t __smp_load_acquire_reserved(void*); > int __smp_store_release_conditional(void*, uint32_t); > > typedef union { > uint32_t v32; > struct { > uint16_t owner; > uint16_t next; > }; > } arch_spinlock_t; > > int trylock(arch_spinlock_t *lock) > { > arch_spinlock_t l; > int success; > do { > l.v32 = __smp_load_acquire_reserved(lock); > if (l.owner != l.next) > return 0; > l.next++; > success = __smp_store_release_conditional(lock, l.v32); It's a new semantics v.s cmpxchg, and cmpxchg is come from CAS instruction to solve some complex scenario. The primitive of cmpxchg has been widely used in Linux, so I don't think introducing a new semantics (reserved_conditional) is a good idea. Also, from this point: It seems CAS instruction is more suitable for software compatibility. Although riscv privilege spec chose the LR/SC and list some bad sides of CAS. > } while (!success); > return success; > } > > But here we can't tell the compiler to optimize the code between LL and SC... > > > > > That will try and do the full LL/SC loop, because it wants to complete > > the cmpxchg, but in generic code we have no other option. > > > > (Is this what C11's weak cmpxchg is for?) -- Best Regards Guo Ren ML: https://lore.kernel.org/linux-csky/ _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2021-04-13 13:19 UTC|newest] Thread overview: 98+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-03-24 10:14 [PATCH] riscv: locks: introduce ticket-based spinlock implementation guoren 2021-03-24 10:14 ` guoren 2021-03-24 11:09 ` Peter Zijlstra 2021-03-24 11:09 ` Peter Zijlstra 2021-03-24 12:10 ` Guo Ren 2021-03-24 12:10 ` Guo Ren [not found] ` <CAM4kBBK7_s9U2vJbq68yC8WdDEfPQTaCOvn1xds3Si5B-Wpw+A@mail.gmail.com> 2021-03-24 12:23 ` Peter Zijlstra 2021-03-24 12:23 ` Peter Zijlstra 2021-03-24 12:24 ` Guo Ren 2021-03-24 12:24 ` Guo Ren 2021-03-24 12:31 ` Peter Zijlstra 2021-03-24 12:31 ` Peter Zijlstra 2021-03-24 12:28 ` Anup Patel 2021-03-24 12:28 ` Anup Patel 2021-03-24 12:37 ` Peter Zijlstra 2021-03-24 12:37 ` Peter Zijlstra 2021-03-24 12:53 ` Anup Patel 2021-03-24 12:53 ` Anup Patel 2021-04-11 21:11 ` Palmer Dabbelt 2021-04-11 21:11 ` Palmer Dabbelt 2021-04-12 13:32 ` Christoph Müllner 2021-04-12 13:32 ` Christoph Müllner 2021-04-12 14:51 ` Peter Zijlstra 2021-04-12 14:51 ` Peter Zijlstra 2021-04-12 21:21 ` Christoph Müllner 2021-04-12 21:21 ` Christoph Müllner 2021-04-12 17:33 ` Palmer Dabbelt 2021-04-12 17:33 ` Palmer Dabbelt 2021-04-12 21:54 ` Christoph Müllner 2021-04-12 21:54 ` Christoph Müllner 2021-04-13 8:03 ` Peter Zijlstra 2021-04-13 8:03 ` Peter Zijlstra 2021-04-13 8:17 ` Peter Zijlstra 2021-04-13 8:17 ` Peter Zijlstra 2021-04-14 2:26 ` Guo Ren 2021-04-14 2:26 ` Guo Ren 2021-04-14 7:08 ` Peter Zijlstra 2021-04-14 7:08 ` Peter Zijlstra 2021-04-14 9:05 ` Peter Zijlstra 2021-04-14 9:05 ` Peter Zijlstra 2021-04-14 10:16 ` [RFC][PATCH] locking: Generic ticket-lock Peter Zijlstra 2021-04-14 10:16 ` Peter Zijlstra 2021-04-14 12:39 ` Guo Ren 2021-04-14 12:39 ` Guo Ren 2021-04-14 12:55 ` Peter Zijlstra 2021-04-14 12:55 ` Peter Zijlstra 2021-04-14 13:08 ` Peter Zijlstra 2021-04-14 13:08 ` Peter Zijlstra 2021-04-14 15:59 ` David Laight 2021-04-14 15:59 ` David Laight 2021-04-14 12:45 ` Peter Zijlstra 2021-04-14 12:45 ` Peter Zijlstra 2021-04-14 21:02 ` Stafford Horne 2021-04-14 21:02 ` Stafford Horne 2021-04-14 20:47 ` Stafford Horne 2021-04-14 20:47 ` Stafford Horne 2021-04-15 8:09 ` Peter Zijlstra 2021-04-15 8:09 ` Peter Zijlstra 2021-04-15 9:02 ` Catalin Marinas 2021-04-15 9:02 ` Catalin Marinas 2021-04-15 9:22 ` Will Deacon 2021-04-15 9:22 ` Will Deacon 2021-04-15 9:24 ` Peter Zijlstra 2021-04-15 9:24 ` Peter Zijlstra 2021-04-19 17:35 ` Will Deacon 2021-04-19 17:35 ` Will Deacon 2021-04-23 6:44 ` Palmer Dabbelt 2021-04-23 6:44 ` Palmer Dabbelt 2021-04-13 9:22 ` [PATCH] riscv: locks: introduce ticket-based spinlock implementation Christoph Müllner 2021-04-13 9:22 ` Christoph Müllner 2021-04-13 9:30 ` Catalin Marinas 2021-04-13 9:30 ` Catalin Marinas 2021-04-13 9:55 ` Christoph Müllner 2021-04-13 9:55 ` Christoph Müllner 2021-04-14 0:23 ` Guo Ren 2021-04-14 0:23 ` Guo Ren 2021-04-14 9:17 ` Catalin Marinas 2021-04-14 9:17 ` Catalin Marinas 2021-04-13 9:35 ` Peter Zijlstra 2021-04-13 9:35 ` Peter Zijlstra 2021-04-13 10:25 ` Christoph Müllner 2021-04-13 10:25 ` Christoph Müllner 2021-04-13 10:45 ` Catalin Marinas 2021-04-13 10:45 ` Catalin Marinas 2021-04-13 10:54 ` David Laight 2021-04-13 10:54 ` David Laight 2021-04-14 5:54 ` Guo Ren 2021-04-14 5:54 ` Guo Ren 2021-04-13 11:04 ` Christoph Müllner 2021-04-13 11:04 ` Christoph Müllner 2021-04-13 13:19 ` Guo Ren [this message] 2021-04-13 13:19 ` Guo Ren 2021-09-19 16:53 guoren 2021-09-19 16:53 ` guoren 2021-09-25 14:47 ` Guo Ren 2021-09-25 14:47 ` Guo Ren 2021-10-21 13:13 ` Peter Zijlstra 2021-10-21 13:13 ` Peter Zijlstra
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