From: Guo Ren <guoren@kernel.org> To: David Laight <David.Laight@aculab.com> Cc: "Catalin Marinas" <catalin.marinas@arm.com>, "Christoph Müllner" <christophm30@gmail.com>, "Peter Zijlstra" <peterz@infradead.org>, "Palmer Dabbelt" <palmer@dabbelt.com>, "Anup Patel" <anup@brainfault.org>, linux-riscv <linux-riscv@lists.infradead.org>, "Linux Kernel Mailing List" <linux-kernel@vger.kernel.org>, "Guo Ren" <guoren@linux.alibaba.com>, "will.deacon@arm.com" <will.deacon@arm.com>, "Arnd Bergmann" <arnd@arndb.de> Subject: Re: [PATCH] riscv: locks: introduce ticket-based spinlock implementation Date: Wed, 14 Apr 2021 13:54:18 +0800 [thread overview] Message-ID: <CAJF2gTTE54rDfFeVGbc0BL7br3hy+6oN6KMFQDx5+aKPSSviKw@mail.gmail.com> (raw) In-Reply-To: <73cab48b63ea4ba3b1ef532f47d146f4@AcuMS.aculab.com> On Tue, Apr 13, 2021 at 6:54 PM David Laight <David.Laight@aculab.com> wrote: > > From: Catalin Marinas > > Sent: 13 April 2021 11:45 > ... > > This indeed needs some care. IIUC RISC-V has similar restrictions as arm > > here, no load/store instructions are allowed between LR and SC. You > > can't guarantee that the compiler won't spill some variable onto the > > stack. > > You can probably never guarantee the compiler won't spill to stack. > Especially if someone compiles with -O0. > > Which probably means that anything using LR/SC must be written in > asm and the C wrappers disabled. Agree, and cmpxchg has been widely used in Linux. I think it's the last requirement for complex atomic API, although cmpxchg has ABA problem: CPU0 CPU1 ======= ====== do { old32 = load32; *ptr32 = new32_tmp; *ptr32 = old32; load32 = cmpxchg(ptr32, old32, new32); //still success } while (load32 != old32); That means cmpxhg only cares about the result but not the middle situation. It's different from LR/SC or AMO instructions. > > David > > - > Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK > Registration No: 1397386 (Wales) > -- Best Regards Guo Ren ML: https://lore.kernel.org/linux-csky/
WARNING: multiple messages have this Message-ID (diff)
From: Guo Ren <guoren@kernel.org> To: David Laight <David.Laight@aculab.com> Cc: "Catalin Marinas" <catalin.marinas@arm.com>, "Christoph Müllner" <christophm30@gmail.com>, "Peter Zijlstra" <peterz@infradead.org>, "Palmer Dabbelt" <palmer@dabbelt.com>, "Anup Patel" <anup@brainfault.org>, linux-riscv <linux-riscv@lists.infradead.org>, "Linux Kernel Mailing List" <linux-kernel@vger.kernel.org>, "Guo Ren" <guoren@linux.alibaba.com>, "will.deacon@arm.com" <will.deacon@arm.com>, "Arnd Bergmann" <arnd@arndb.de> Subject: Re: [PATCH] riscv: locks: introduce ticket-based spinlock implementation Date: Wed, 14 Apr 2021 13:54:18 +0800 [thread overview] Message-ID: <CAJF2gTTE54rDfFeVGbc0BL7br3hy+6oN6KMFQDx5+aKPSSviKw@mail.gmail.com> (raw) In-Reply-To: <73cab48b63ea4ba3b1ef532f47d146f4@AcuMS.aculab.com> On Tue, Apr 13, 2021 at 6:54 PM David Laight <David.Laight@aculab.com> wrote: > > From: Catalin Marinas > > Sent: 13 April 2021 11:45 > ... > > This indeed needs some care. IIUC RISC-V has similar restrictions as arm > > here, no load/store instructions are allowed between LR and SC. You > > can't guarantee that the compiler won't spill some variable onto the > > stack. > > You can probably never guarantee the compiler won't spill to stack. > Especially if someone compiles with -O0. > > Which probably means that anything using LR/SC must be written in > asm and the C wrappers disabled. Agree, and cmpxchg has been widely used in Linux. I think it's the last requirement for complex atomic API, although cmpxchg has ABA problem: CPU0 CPU1 ======= ====== do { old32 = load32; *ptr32 = new32_tmp; *ptr32 = old32; load32 = cmpxchg(ptr32, old32, new32); //still success } while (load32 != old32); That means cmpxhg only cares about the result but not the middle situation. It's different from LR/SC or AMO instructions. > > David > > - > Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK > Registration No: 1397386 (Wales) > -- Best Regards Guo Ren ML: https://lore.kernel.org/linux-csky/ _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2021-04-14 5:54 UTC|newest] Thread overview: 98+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-03-24 10:14 [PATCH] riscv: locks: introduce ticket-based spinlock implementation guoren 2021-03-24 10:14 ` guoren 2021-03-24 11:09 ` Peter Zijlstra 2021-03-24 11:09 ` Peter Zijlstra 2021-03-24 12:10 ` Guo Ren 2021-03-24 12:10 ` Guo Ren [not found] ` <CAM4kBBK7_s9U2vJbq68yC8WdDEfPQTaCOvn1xds3Si5B-Wpw+A@mail.gmail.com> 2021-03-24 12:23 ` Peter Zijlstra 2021-03-24 12:23 ` Peter Zijlstra 2021-03-24 12:24 ` Guo Ren 2021-03-24 12:24 ` Guo Ren 2021-03-24 12:31 ` Peter Zijlstra 2021-03-24 12:31 ` Peter Zijlstra 2021-03-24 12:28 ` Anup Patel 2021-03-24 12:28 ` Anup Patel 2021-03-24 12:37 ` Peter Zijlstra 2021-03-24 12:37 ` Peter Zijlstra 2021-03-24 12:53 ` Anup Patel 2021-03-24 12:53 ` Anup Patel 2021-04-11 21:11 ` Palmer Dabbelt 2021-04-11 21:11 ` Palmer Dabbelt 2021-04-12 13:32 ` Christoph Müllner 2021-04-12 13:32 ` Christoph Müllner 2021-04-12 14:51 ` Peter Zijlstra 2021-04-12 14:51 ` Peter Zijlstra 2021-04-12 21:21 ` Christoph Müllner 2021-04-12 21:21 ` Christoph Müllner 2021-04-12 17:33 ` Palmer Dabbelt 2021-04-12 17:33 ` Palmer Dabbelt 2021-04-12 21:54 ` Christoph Müllner 2021-04-12 21:54 ` Christoph Müllner 2021-04-13 8:03 ` Peter Zijlstra 2021-04-13 8:03 ` Peter Zijlstra 2021-04-13 8:17 ` Peter Zijlstra 2021-04-13 8:17 ` Peter Zijlstra 2021-04-14 2:26 ` Guo Ren 2021-04-14 2:26 ` Guo Ren 2021-04-14 7:08 ` Peter Zijlstra 2021-04-14 7:08 ` Peter Zijlstra 2021-04-14 9:05 ` Peter Zijlstra 2021-04-14 9:05 ` Peter Zijlstra 2021-04-14 10:16 ` [RFC][PATCH] locking: Generic ticket-lock Peter Zijlstra 2021-04-14 10:16 ` Peter Zijlstra 2021-04-14 12:39 ` Guo Ren 2021-04-14 12:39 ` Guo Ren 2021-04-14 12:55 ` Peter Zijlstra 2021-04-14 12:55 ` Peter Zijlstra 2021-04-14 13:08 ` Peter Zijlstra 2021-04-14 13:08 ` Peter Zijlstra 2021-04-14 15:59 ` David Laight 2021-04-14 15:59 ` David Laight 2021-04-14 12:45 ` Peter Zijlstra 2021-04-14 12:45 ` Peter Zijlstra 2021-04-14 21:02 ` Stafford Horne 2021-04-14 21:02 ` Stafford Horne 2021-04-14 20:47 ` Stafford Horne 2021-04-14 20:47 ` Stafford Horne 2021-04-15 8:09 ` Peter Zijlstra 2021-04-15 8:09 ` Peter Zijlstra 2021-04-15 9:02 ` Catalin Marinas 2021-04-15 9:02 ` Catalin Marinas 2021-04-15 9:22 ` Will Deacon 2021-04-15 9:22 ` Will Deacon 2021-04-15 9:24 ` Peter Zijlstra 2021-04-15 9:24 ` Peter Zijlstra 2021-04-19 17:35 ` Will Deacon 2021-04-19 17:35 ` Will Deacon 2021-04-23 6:44 ` Palmer Dabbelt 2021-04-23 6:44 ` Palmer Dabbelt 2021-04-13 9:22 ` [PATCH] riscv: locks: introduce ticket-based spinlock implementation Christoph Müllner 2021-04-13 9:22 ` Christoph Müllner 2021-04-13 9:30 ` Catalin Marinas 2021-04-13 9:30 ` Catalin Marinas 2021-04-13 9:55 ` Christoph Müllner 2021-04-13 9:55 ` Christoph Müllner 2021-04-14 0:23 ` Guo Ren 2021-04-14 0:23 ` Guo Ren 2021-04-14 9:17 ` Catalin Marinas 2021-04-14 9:17 ` Catalin Marinas 2021-04-13 9:35 ` Peter Zijlstra 2021-04-13 9:35 ` Peter Zijlstra 2021-04-13 10:25 ` Christoph Müllner 2021-04-13 10:25 ` Christoph Müllner 2021-04-13 10:45 ` Catalin Marinas 2021-04-13 10:45 ` Catalin Marinas 2021-04-13 10:54 ` David Laight 2021-04-13 10:54 ` David Laight 2021-04-14 5:54 ` Guo Ren [this message] 2021-04-14 5:54 ` Guo Ren 2021-04-13 11:04 ` Christoph Müllner 2021-04-13 11:04 ` Christoph Müllner 2021-04-13 13:19 ` Guo Ren 2021-04-13 13:19 ` Guo Ren 2021-09-19 16:53 guoren 2021-09-19 16:53 ` guoren 2021-09-25 14:47 ` Guo Ren 2021-09-25 14:47 ` Guo Ren 2021-10-21 13:13 ` Peter Zijlstra 2021-10-21 13:13 ` Peter Zijlstra
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