From: Christian Eggers <ceggers@arri.de>
To: Miquel Raynal <miquel.raynal@bootlin.com>, Han Xu <han.xu@nxp.com>
Cc: Michael Nazzareno Trimarchi <michael@amarulasolutions.com>,
<linux-mtd@lists.infradead.org>, Greg Ungerer <gerg@kernel.org>,
Sascha Hauer <s.hauer@pengutronix.de>,
Stefan Riedmueller <s.riedmueller@phytec.de>,
Christian Hemp <c.hemp@phytec.de>
Subject: Re: GPMI iMX6ull timeout on DMA
Date: Fri, 8 Oct 2021 11:55:56 +0200 [thread overview]
Message-ID: <2091909.Mh6RI2rZIc@n95hx1g2> (raw)
In-Reply-To: <20211004160620.3guajv5vvtfjrl7c@umbrella>
+ set PHYTEC developers on (B)CC
On Monday, 4 October 2021, 18:06:20 CEST, Han Xu wrote:
>
> Could you please try to add clock dis/enable when setting clock rate, in case
> clock glitches.
>
> clk_disable_unprepare(r->clock[0]);
> clk_set_rate(r->clock[0], hw->clk_rate);
> clk_prepare_enable(r->clock[0]);
>
With this change, we made over 2000 successful reboots without any GPMI DMA
timeout problems!
From PHYTEC (our BSP supplier), I got some possible background for this
problem. For older revisions of IMX6DQ there was an errata (ERR007117, [1])
in the ROM bootloader which triggers a similar / the same behavior:
> For raw NAND boot, ROM switches the source of enfc_clk_root from PLL2_PFD2
> to PLL3. The root clock is required to be gated before switching the source
> clock. If the root clock is not gated, clock glitches might be passed to
> the divider that follows the clock mux, and the divider might behave
> unpredictably.
> ...
> This problem can also occur elsewhere in application code if the root clock
> is not properly gated when the clock configuration is changed.
In my case (Linux boot on i.MX6ULL), I recognized that on the 3rd call of
gpmi_nfc_apply_timings(), the rate of r->clock[0] is changed
- from: 22 MHz (CS2CDR::ENFC_CLK_PRED=6 and CS2CDR::ENFC_CLK_PODF=3)
- to: 100 MHz (CS2CDR::ENFC_CLK_PRED=4 and CS2CDR::ENFC_CLK_PODF=1)
The proposal from from Han Xu
> clk_disable_unprepare(r->clock[0]);
> clk_set_rate(r->clock[0], hw->clk_rate);
> clk_prepare_enable(r->clock[0]);
disables only CCGR4::CG14 [RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_CLK_ENABLE] during
the rate change. While this works very fine on my system, this probably doesn't
fulfill the requirements in the errata description:
> For other occurrences in application code, the following procedure should be
> followed to change the clock configuration for the enfc_clk_root:
> 1) Gate (disable) the GPMI/BCH clocks in register CCM_CCGR4.
> 2) Gate (disable) the enfc_clk_root before changing the enfc_clk_root source
> or dividers by clearing CCM_CCGR2[CG7] to 2’b00. This disables the
> iomux_ipt_clk_io_clk.
> 3) Configure CCM_CS2CDR for the new clock source configuration.
> 4) Enable enfc_clk_root by setting CCM_CCGR2[CG7] to 2’b11. This enables the
> iomux_ipt_clk_io_clk.
> 5) Enable the GPMI/BCH clocks in register CCM_CCGR4
I got another solution from PHYTEC ([2], not lengthy tested yet), which
disables all GPMI/BCH clocks on CCGR4 (verified with a JTAG debugger):
- CCGR4::CG15 [RAWNAND_U_GPMI_INPUT_APB_CLK_ENABLE]
- CCGR4::CG14 [RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_CLK_ENABLE]
- CCGR4::CG13 [RAWNAND_U_GPMI_BCH_INPUT_BCH_CLK_ENABLE]
- CCGR4::CG12 [RAWNAND_U_BCH_INPUT_APB_CLK_ENABLE]
- CCGR4::CG6 [PL301_MX6QPER1_BCHCLK_ENABLE]
CCM_CCGR2[CG7] is used for IOMUX_IPT_CLK_IO_ENABLE on i.MX6ULL, so step 2.
seems not to apply here. Actually I don't know how to gate ENFC_CLK_ROOT.
I will cyclic test the solution from PHYTEC over the weekend.
@Han Xu: Should I prefer the solution from PHYTEC?
@Stefan Riedmueller: Are you willing to commit this upstream?
regards
Christian
[1] https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf
[2] https://git.phytec.de/linux-mainline/commit/?h=v5.10.48-phy&id=866939ea8110764d9c12af960d746e2f7f5debe3
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next prev parent reply other threads:[~2021-10-08 9:57 UTC|newest]
Thread overview: 85+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-29 6:41 GPMI iMX6ull timeout on DMA Greg Ungerer
2019-07-29 8:36 ` Miquel Raynal
2019-07-29 8:42 ` Michael Nazzareno Trimarchi
2019-07-29 12:18 ` Greg Ungerer
2019-07-29 12:20 ` Michael Nazzareno Trimarchi
2019-07-29 12:33 ` Greg Ungerer
2019-07-29 12:47 ` Miquel Raynal
2019-07-29 12:49 ` Michael Nazzareno Trimarchi
2019-07-29 12:55 ` Miquel Raynal
2019-07-29 13:00 ` Michael Nazzareno Trimarchi
2019-07-29 13:22 ` Miquel Raynal
2019-07-29 20:00 ` Michael Nazzareno Trimarchi
2019-07-29 21:02 ` Miquel Raynal
2019-07-30 0:28 ` Greg Ungerer
2019-07-30 0:41 ` Greg Ungerer
2019-07-30 6:06 ` Greg Ungerer
2019-07-30 8:38 ` Miquel Raynal
2019-07-30 8:58 ` Boris Brezillon
2019-07-31 2:05 ` Greg Ungerer
2019-07-31 6:28 ` Boris Brezillon
2019-08-02 7:19 ` Greg Ungerer
2019-08-02 12:34 ` Greg Ungerer
2019-08-02 12:51 ` Boris Brezillon
2019-08-05 5:51 ` Greg Ungerer
2019-08-07 16:05 ` Miquel Raynal
2019-08-08 0:43 ` Greg Ungerer
2019-08-08 16:36 ` Boris Brezillon
2019-08-09 5:20 ` Greg Ungerer
2019-08-09 6:23 ` Boris Brezillon
2019-08-09 6:55 ` Greg Ungerer
2019-08-09 7:32 ` Boris Brezillon
2019-08-09 13:57 ` Greg Ungerer
2019-08-09 13:59 ` Boris Brezillon
2019-08-12 2:50 ` Greg Ungerer
2019-08-12 4:04 ` Greg Ungerer
2019-08-12 7:31 ` Boris Brezillon
2019-08-13 0:50 ` Greg Ungerer
2021-01-28 9:45 ` Michael Nazzareno Trimarchi
2021-01-28 10:26 ` Miquel Raynal
2021-01-28 10:35 ` Michael Nazzareno Trimarchi
2021-01-28 11:55 ` Michael Nazzareno Trimarchi
2021-01-29 12:43 ` Greg Ungerer
2021-01-30 9:41 ` Michael Nazzareno Trimarchi
2021-02-01 14:13 ` Miquel Raynal
2021-02-01 14:32 ` Michael Nazzareno Trimarchi
2021-02-01 15:08 ` Michael Nazzareno Trimarchi
2021-02-01 15:14 ` Miquel Raynal
2021-02-01 15:17 ` Michael Nazzareno Trimarchi
2021-10-15 20:05 ` Michael Trimarchi
2021-10-15 20:12 ` Michael Nazzareno Trimarchi
2021-10-18 7:19 ` Miquel Raynal
2021-10-18 7:33 ` Michael Nazzareno Trimarchi
2021-10-18 7:43 ` Miquel Raynal
2021-10-04 5:54 ` Christian Eggers
2021-10-04 6:27 ` Michael Nazzareno Trimarchi
2021-10-04 15:33 ` Miquel Raynal
2021-10-04 16:06 ` Han Xu
2021-10-05 6:02 ` Christian Eggers
2021-10-08 9:55 ` Christian Eggers [this message]
2021-10-08 12:08 ` Stefan Riedmüller
2021-10-08 12:27 ` Miquel Raynal
2021-10-08 13:11 ` Christian Eggers
2021-10-08 13:29 ` Miquel Raynal
2021-10-08 13:36 ` Miquel Raynal
2021-10-08 13:49 ` Christian Eggers
2021-10-08 16:07 ` Miquel Raynal
2021-10-09 5:53 ` Michael Nazzareno Trimarchi
2021-10-11 6:46 ` Miquel Raynal
2021-10-12 9:02 ` [RFC PATCH 1/2] mtd: rawnand: gpmi: Remove explicit default gpmi clock setting for i.MX6 Stefan Riedmueller
2021-10-12 9:02 ` [RFC PATCH 2/2] gpmi-nand: Add ERR007117 protection for nfc_apply_timings Stefan Riedmueller
2021-10-13 5:01 ` Han Xu
2021-10-22 8:45 ` Stefan Riedmüller
2021-10-22 14:35 ` han.xu
2021-10-25 9:39 ` Stefan Riedmüller
2021-10-28 9:28 ` Stefan Riedmüller
2021-11-01 4:01 ` han.xu
2021-10-13 6:10 ` Christian Eggers
2021-10-13 6:00 ` [RFC PATCH 1/2] mtd: rawnand: gpmi: Remove explicit default gpmi clock setting for i.MX6 Christian Eggers
2021-10-09 6:26 ` GPMI iMX6ull timeout on DMA Christian Eggers
2021-10-13 6:15 ` Christian Eggers
2021-10-08 13:13 ` Christian Eggers
2021-10-08 13:30 ` Miquel Raynal
2021-10-09 6:33 ` Christian Eggers
-- strict thread matches above, loose matches on Subject: below --
2018-10-02 13:22 GPMI IMX6ull timeout on dma Michael Nazzareno Trimarchi
2018-10-04 14:36 ` Michael Nazzareno Trimarchi
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