From: Greg Ungerer <gerg@kernel.org>
To: Miquel Raynal <miquel.raynal@bootlin.com>
Cc: s.hauer@pengutronix.de,
Michael Nazzareno Trimarchi <michael@amarulasolutions.com>,
linux-mtd@lists.infradead.org,
Boris Brezillon <bbrezillon@kernel.org>
Subject: Re: GPMI iMX6ull timeout on DMA
Date: Tue, 30 Jul 2019 10:41:25 +1000 [thread overview]
Message-ID: <781dd4e6-a694-c3e1-ee13-9c5c51598623@kernel.org> (raw)
In-Reply-To: <17b49e7d-ff63-315f-cf12-3474f7228c6d@kernel.org>
Hi Miquel,
On 30/7/19 10:28 am, Greg Ungerer wrote:
> On 29/7/19 10:47 pm, Miquel Raynal wrote:
>> Greg Ungerer <gerg@kernel.org> wrote on Mon, 29 Jul 2019 22:33:56 +1000:
>>> On 29/7/19 6:36 pm, Miquel Raynal wrote:
>>>> Greg Ungerer <gerg@kernel.org> wrote on Mon, 29 Jul 2019 16:41:51 +1000:
[snip]
>>>>> nand: timing mode 5 not acknowledged by the NAND chip
>>>>
>>>> What is the final timing mode used? Most of us tested in mode 5 I
>>>> guess, maybe mode 4 is broken (don't know if this is the one used here,
>>>> neither why mode 5 is refused). Can you please try by limiting the mode
>>>> to 0, 1, 2... until, hopefully, we narrow down to the failing mode.
>>>
>>> Sure, how to do that?
>>
>> This loop [1] tries to configure each mode (5, 4, ...) until one
>> succeeds (default is 0: must always work). Please try to limit mode to
>> 0, 1, etc.
>>
>> Mode 0 should work.
>>
>> [1] https://elixir.bootlin.com/linux/v5.3-rc1/source/drivers/mtd/nand/raw/nand_base.c#L933
>
> The normal behavior - which usually works - has
> chip->onfi_timing_mode_default=5 here. So in other words on the first pass
> through this loop it is checking mode 5, and setting it as the default.
>
> I am running a test/reboot loop now waiting for failure to see
> if it is still using mode 5 in that case.
With this trace in place:
--- a/linux/drivers/mtd/nand/raw/nand_base.c
+++ b/linux/drivers/mtd/nand/raw/nand_base.c
@@ -910,6 +910,7 @@ static int nand_init_data_interface(struct nand_chip *chip)
}
for (mode = fls(modes) - 1; mode >= 0; mode--) {
+ printk("%s(%d): checking mode=%d\n", __FILE__, __LINE__, mode);
ret = onfi_fill_data_interface(chip, NAND_SDR_IFACE, mode);
if (ret)
continue;
@@ -923,10 +924,12 @@ static int nand_init_data_interface(struct nand_chip *chip)
&chip->data_interface);
if (!ret) {
chip->onfi_timing_mode_default = mode;
+ printk("%s(%d): BREAKING AT mode=%d\n", __FILE__, __LINE__, mode);
break;
}
}
+ printk("%s(%d): chip->onfi_timing_mode_default=%d\n", __FILE__, __LINE__, chip->onfi_timing_mode_default);
return 0;
}
First NAND failure gives this:
nand: device found, Manufacturer ID: 0x2c, Chip ID: 0xda
nand: Micron MT29F2G08ABAEAWP
nand: 256 MiB, SLC, erase size: 128 KiB, page size: 2048, OOB size: 64
gpmi-nand 1806000.gpmi-nand: use legacy bch geometry
drivers/mtd/nand/raw/nand_base.c(913): checking mode=5
drivers/mtd/nand/raw/nand_base.c(927): BREAKING AT mode=5
drivers/mtd/nand/raw/nand_base.c(932): chip->onfi_timing_mode_default=5
gpmi-nand 1806000.gpmi-nand: DMA timeout, last DMA
gpmi-nand 1806000.gpmi-nand: Show GPMI registers :
gpmi-nand 1806000.gpmi-nand: offset 0x000 : 0x20830002
gpmi-nand 1806000.gpmi-nand: offset 0x010 : 0x00000000
gpmi-nand 1806000.gpmi-nand: offset 0x020 : 0x00000000
gpmi-nand 1806000.gpmi-nand: offset 0x030 : 0x00000000
gpmi-nand 1806000.gpmi-nand: offset 0x040 : 0x00000000
gpmi-nand 1806000.gpmi-nand: offset 0x050 : 0x00000000
gpmi-nand 1806000.gpmi-nand: offset 0x060 : 0x01c6800c
gpmi-nand 1806000.gpmi-nand: offset 0x070 : 0x00010101
gpmi-nand 1806000.gpmi-nand: offset 0x080 : 0xe0000000
gpmi-nand 1806000.gpmi-nand: offset 0x090 : 0x23023336
gpmi-nand 1806000.gpmi-nand: offset 0x0a0 : 0x000001ee
gpmi-nand 1806000.gpmi-nand: offset 0x0b0 : 0xff000001
gpmi-nand 1806000.gpmi-nand: offset 0x0c0 : 0x00000100
gpmi-nand 1806000.gpmi-nand: offset 0x0d0 : 0x05020000
gpmi-nand 1806000.gpmi-nand: Show BCH registers :
gpmi-nand 1806000.gpmi-nand: offset 0x000 : 0x00000100
gpmi-nand 1806000.gpmi-nand: offset 0x010 : 0x00000010
gpmi-nand 1806000.gpmi-nand: offset 0x020 : 0x00000000
gpmi-nand 1806000.gpmi-nand: offset 0x030 : 0x00000000
gpmi-nand 1806000.gpmi-nand: offset 0x040 : 0x00000000
gpmi-nand 1806000.gpmi-nand: offset 0x050 : 0x00000000
gpmi-nand 1806000.gpmi-nand: offset 0x060 : 0x00000000
gpmi-nand 1806000.gpmi-nand: offset 0x070 : 0x00000000
gpmi-nand 1806000.gpmi-nand: offset 0x080 : 0x030a2080
gpmi-nand 1806000.gpmi-nand: offset 0x090 : 0x083e2080
gpmi-nand 1806000.gpmi-nand: offset 0x0a0 : 0x070a4080
gpmi-nand 1806000.gpmi-nand: offset 0x0b0 : 0x10da4080
gpmi-nand 1806000.gpmi-nand: offset 0x0c0 : 0x070a4080
gpmi-nand 1806000.gpmi-nand: offset 0x0d0 : 0x10da4080
gpmi-nand 1806000.gpmi-nand: offset 0x0e0 : 0x070a4080
gpmi-nand 1806000.gpmi-nand: offset 0x0f0 : 0x10da4080
gpmi-nand 1806000.gpmi-nand: offset 0x100 : 0x00000000
gpmi-nand 1806000.gpmi-nand: offset 0x110 : 0x00000000
gpmi-nand 1806000.gpmi-nand: offset 0x120 : 0x00000000
gpmi-nand 1806000.gpmi-nand: offset 0x130 : 0x00000000
gpmi-nand 1806000.gpmi-nand: offset 0x140 : 0x00000000
gpmi-nand 1806000.gpmi-nand: offset 0x150 : 0x20484342
gpmi-nand 1806000.gpmi-nand: offset 0x160 : 0x01000000
gpmi-nand 1806000.gpmi-nand: offset 0x170 : 0x00000000
gpmi-nand 1806000.gpmi-nand: BCH Geometry :
GF length : 13
ECC Strength : 8
Page Size in Bytes : 2110
Metadata Size in Bytes : 10
ECC Chunk0 Size in Bytes: 512
ECC Chunkn Size in Bytes: 512
ECC Chunk Count : 4
Payload Size in Bytes : 2048
Auxiliary Size in Bytes: 16
Auxiliary Status Offset: 12
Block Mark Byte Offset : 1999
Block Mark Bit Offset : 0
gpmi-nand 1806000.gpmi-nand: Chip: 0, Error -110
nand: timing mode 5 not acknowledged by the NAND chip
gpmi-nand 1806000.gpmi-nand: Chip: 0, Error -22
Regards
Greg
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next prev parent reply other threads:[~2019-07-30 0:41 UTC|newest]
Thread overview: 85+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-29 6:41 GPMI iMX6ull timeout on DMA Greg Ungerer
2019-07-29 8:36 ` Miquel Raynal
2019-07-29 8:42 ` Michael Nazzareno Trimarchi
2019-07-29 12:18 ` Greg Ungerer
2019-07-29 12:20 ` Michael Nazzareno Trimarchi
2019-07-29 12:33 ` Greg Ungerer
2019-07-29 12:47 ` Miquel Raynal
2019-07-29 12:49 ` Michael Nazzareno Trimarchi
2019-07-29 12:55 ` Miquel Raynal
2019-07-29 13:00 ` Michael Nazzareno Trimarchi
2019-07-29 13:22 ` Miquel Raynal
2019-07-29 20:00 ` Michael Nazzareno Trimarchi
2019-07-29 21:02 ` Miquel Raynal
2019-07-30 0:28 ` Greg Ungerer
2019-07-30 0:41 ` Greg Ungerer [this message]
2019-07-30 6:06 ` Greg Ungerer
2019-07-30 8:38 ` Miquel Raynal
2019-07-30 8:58 ` Boris Brezillon
2019-07-31 2:05 ` Greg Ungerer
2019-07-31 6:28 ` Boris Brezillon
2019-08-02 7:19 ` Greg Ungerer
2019-08-02 12:34 ` Greg Ungerer
2019-08-02 12:51 ` Boris Brezillon
2019-08-05 5:51 ` Greg Ungerer
2019-08-07 16:05 ` Miquel Raynal
2019-08-08 0:43 ` Greg Ungerer
2019-08-08 16:36 ` Boris Brezillon
2019-08-09 5:20 ` Greg Ungerer
2019-08-09 6:23 ` Boris Brezillon
2019-08-09 6:55 ` Greg Ungerer
2019-08-09 7:32 ` Boris Brezillon
2019-08-09 13:57 ` Greg Ungerer
2019-08-09 13:59 ` Boris Brezillon
2019-08-12 2:50 ` Greg Ungerer
2019-08-12 4:04 ` Greg Ungerer
2019-08-12 7:31 ` Boris Brezillon
2019-08-13 0:50 ` Greg Ungerer
2021-01-28 9:45 ` Michael Nazzareno Trimarchi
2021-01-28 10:26 ` Miquel Raynal
2021-01-28 10:35 ` Michael Nazzareno Trimarchi
2021-01-28 11:55 ` Michael Nazzareno Trimarchi
2021-01-29 12:43 ` Greg Ungerer
2021-01-30 9:41 ` Michael Nazzareno Trimarchi
2021-02-01 14:13 ` Miquel Raynal
2021-02-01 14:32 ` Michael Nazzareno Trimarchi
2021-02-01 15:08 ` Michael Nazzareno Trimarchi
2021-02-01 15:14 ` Miquel Raynal
2021-02-01 15:17 ` Michael Nazzareno Trimarchi
2021-10-15 20:05 ` Michael Trimarchi
2021-10-15 20:12 ` Michael Nazzareno Trimarchi
2021-10-18 7:19 ` Miquel Raynal
2021-10-18 7:33 ` Michael Nazzareno Trimarchi
2021-10-18 7:43 ` Miquel Raynal
2021-10-04 5:54 ` Christian Eggers
2021-10-04 6:27 ` Michael Nazzareno Trimarchi
2021-10-04 15:33 ` Miquel Raynal
2021-10-04 16:06 ` Han Xu
2021-10-05 6:02 ` Christian Eggers
2021-10-08 9:55 ` Christian Eggers
2021-10-08 12:08 ` Stefan Riedmüller
2021-10-08 12:27 ` Miquel Raynal
2021-10-08 13:11 ` Christian Eggers
2021-10-08 13:29 ` Miquel Raynal
2021-10-08 13:36 ` Miquel Raynal
2021-10-08 13:49 ` Christian Eggers
2021-10-08 16:07 ` Miquel Raynal
2021-10-09 5:53 ` Michael Nazzareno Trimarchi
2021-10-11 6:46 ` Miquel Raynal
2021-10-12 9:02 ` [RFC PATCH 1/2] mtd: rawnand: gpmi: Remove explicit default gpmi clock setting for i.MX6 Stefan Riedmueller
2021-10-12 9:02 ` [RFC PATCH 2/2] gpmi-nand: Add ERR007117 protection for nfc_apply_timings Stefan Riedmueller
2021-10-13 5:01 ` Han Xu
2021-10-22 8:45 ` Stefan Riedmüller
2021-10-22 14:35 ` han.xu
2021-10-25 9:39 ` Stefan Riedmüller
2021-10-28 9:28 ` Stefan Riedmüller
2021-11-01 4:01 ` han.xu
2021-10-13 6:10 ` Christian Eggers
2021-10-13 6:00 ` [RFC PATCH 1/2] mtd: rawnand: gpmi: Remove explicit default gpmi clock setting for i.MX6 Christian Eggers
2021-10-09 6:26 ` GPMI iMX6ull timeout on DMA Christian Eggers
2021-10-13 6:15 ` Christian Eggers
2021-10-08 13:13 ` Christian Eggers
2021-10-08 13:30 ` Miquel Raynal
2021-10-09 6:33 ` Christian Eggers
-- strict thread matches above, loose matches on Subject: below --
2018-10-02 13:22 GPMI IMX6ull timeout on dma Michael Nazzareno Trimarchi
2018-10-04 14:36 ` Michael Nazzareno Trimarchi
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