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* [PATCHv5 00/20] PCI: mobiveil: fixes for Mobiveil PCIe Host Bridge IP driver
@ 2019-04-12  8:35 Z.q. Hou
  2019-04-12  8:35 ` [PATCHv5 01/20] PCI: mobiveil: Unify register accessors Z.q. Hou
                   ` (20 more replies)
  0 siblings, 21 replies; 67+ messages in thread
From: Z.q. Hou @ 2019-04-12  8:35 UTC (permalink / raw)
  To: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	lorenzo.pieralisi, catalin.marinas, will.deacon
  Cc: Mingkai Hu, M.h. Lian, Xiaowei Bao, Z.q. Hou

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

This patch set is to add fixes for Mobiveil PCIe Host driver.
And these patches are splited from the thread below:
http://patchwork.ozlabs.org/project/linux-pci/list/?series=96417

Hou Zhiqiang (20):
  PCI: mobiveil: Unify register accessors
  PCI: mobiveil: Format the code without functionality change
  PCI: mobiveil: Correct the returned error number
  PCI: mobiveil: Remove the flag MSI_FLAG_MULTI_PCI_MSI
  PCI: mobiveil: Correct PCI base address in MEM/IO outbound windows
  PCI: mobiveil: Replace the resource list iteration function
  PCI: mobiveil: Use WIN_NUM_0 explicitly for CFG outbound window
  PCI: mobiveil: Use the 1st inbound window for MEM inbound transactions
  PCI: mobiveil: Correct inbound/outbound window setup routines
  PCI: mobiveil: Fix the INTx process errors
  PCI: mobiveil: Correct the fixup of Class Code field
  PCI: mobiveil: Move the link up waiting out of mobiveil_host_init()
  PCI: mobiveil: Move IRQ chained handler setup out of DT parse
  PCI: mobiveil: Initialize Primary/Secondary/Subordinate bus numbers
  PCI: mobiveil: Fix the checking of valid device
  PCI: mobiveil: Add link up condition check
  PCI: mobiveil: Complete initialization of host even if no PCIe link
  PCI: mobiveil: Disable IB and OB windows set by bootloader
  PCI: mobiveil: Add 8-bit and 16-bit register accessors
  dt-bindings: PCI: mobiveil: Change gpio_slave and apb_csr to optional

 .../devicetree/bindings/pci/mobiveil-pcie.txt |   2 +
 drivers/pci/controller/pcie-mobiveil.c        | 578 +++++++++++-------
 2 files changed, 368 insertions(+), 212 deletions(-)

-- 
2.17.1


^ permalink raw reply	[flat|nested] 67+ messages in thread

* [PATCHv5 01/20] PCI: mobiveil: Unify register accessors
  2019-04-12  8:35 [PATCHv5 00/20] PCI: mobiveil: fixes for Mobiveil PCIe Host Bridge IP driver Z.q. Hou
@ 2019-04-12  8:35 ` Z.q. Hou
  2019-04-12  8:35 ` [PATCHv5 02/20] PCI: mobiveil: Format the code without functionality change Z.q. Hou
                   ` (19 subsequent siblings)
  20 siblings, 0 replies; 67+ messages in thread
From: Z.q. Hou @ 2019-04-12  8:35 UTC (permalink / raw)
  To: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	lorenzo.pieralisi, catalin.marinas, will.deacon
  Cc: Mingkai Hu, M.h. Lian, Xiaowei Bao, Z.q. Hou

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

It's confused that R/W some registers by csr_readl()/csr_writel(),
while others by read_paged_register()/write_paged_register().
Actually the lower 3KB of 4KB PCIe configure space can be accessed
directly and higher 1KB is paging area. So this patch unifies the
register accessors to csr_readl() and csr_writel() by comparing
the register offset with page access boundary 3KB in the accessor
internal.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
---
V5:
 - Corrected and retouched the subject and changelog.

 drivers/pci/controller/pcie-mobiveil.c | 179 +++++++++++++++++--------
 1 file changed, 124 insertions(+), 55 deletions(-)

diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c
index 77052a0712d0..d55c7e780c6e 100644
--- a/drivers/pci/controller/pcie-mobiveil.c
+++ b/drivers/pci/controller/pcie-mobiveil.c
@@ -47,7 +47,6 @@
 #define  PAGE_SEL_SHIFT	13
 #define  PAGE_SEL_MASK		0x3f
 #define  PAGE_LO_MASK		0x3ff
-#define  PAGE_SEL_EN		0xc00
 #define  PAGE_SEL_OFFSET_SHIFT	10
 
 #define PAB_AXI_PIO_CTRL	0x0840
@@ -117,6 +116,12 @@
 #define LINK_WAIT_MIN	90000
 #define LINK_WAIT_MAX	100000
 
+#define PAGED_ADDR_BNDRY			0xc00
+#define OFFSET_TO_PAGE_ADDR(off)		\
+	((off & PAGE_LO_MASK) | PAGED_ADDR_BNDRY)
+#define OFFSET_TO_PAGE_IDX(off)			\
+	((off >> PAGE_SEL_OFFSET_SHIFT) & PAGE_SEL_MASK)
+
 struct mobiveil_msi {			/* MSI information */
 	struct mutex lock;		/* protect bitmap variable */
 	struct irq_domain *msi_domain;
@@ -145,15 +150,119 @@ struct mobiveil_pcie {
 	struct mobiveil_msi msi;
 };
 
-static inline void csr_writel(struct mobiveil_pcie *pcie, const u32 value,
-		const u32 reg)
+/*
+ * mobiveil_pcie_sel_page - routine to access paged register
+ *
+ * Registers whose address greater than PAGED_ADDR_BNDRY (0xc00) are paged,
+ * for this scheme to work extracted higher 6 bits of the offset will be
+ * written to pg_sel field of PAB_CTRL register and rest of the lower 10
+ * bits enabled with PAGED_ADDR_BNDRY are used as offset of the register.
+ */
+static void mobiveil_pcie_sel_page(struct mobiveil_pcie *pcie, u8 pg_idx)
 {
-	writel_relaxed(value, pcie->csr_axi_slave_base + reg);
+	u32 val;
+
+	val = readl(pcie->csr_axi_slave_base + PAB_CTRL);
+	val &= ~(PAGE_SEL_MASK << PAGE_SEL_SHIFT);
+	val |= (pg_idx & PAGE_SEL_MASK) << PAGE_SEL_SHIFT;
+
+	writel(val, pcie->csr_axi_slave_base + PAB_CTRL);
 }
 
-static inline u32 csr_readl(struct mobiveil_pcie *pcie, const u32 reg)
+static void *mobiveil_pcie_comp_addr(struct mobiveil_pcie *pcie, u32 off)
 {
-	return readl_relaxed(pcie->csr_axi_slave_base + reg);
+	if (off < PAGED_ADDR_BNDRY) {
+		/* For directly accessed registers, clear the pg_sel field */
+		mobiveil_pcie_sel_page(pcie, 0);
+		return pcie->csr_axi_slave_base + off;
+	}
+
+	mobiveil_pcie_sel_page(pcie, OFFSET_TO_PAGE_IDX(off));
+	return pcie->csr_axi_slave_base + OFFSET_TO_PAGE_ADDR(off);
+}
+
+static int mobiveil_pcie_read(void __iomem *addr, int size, u32 *val)
+{
+	if ((uintptr_t)addr & (size - 1)) {
+		*val = 0;
+		return PCIBIOS_BAD_REGISTER_NUMBER;
+	}
+
+	switch (size) {
+	case 4:
+		*val = readl(addr);
+		break;
+	case 2:
+		*val = readw(addr);
+		break;
+	case 1:
+		*val = readb(addr);
+		break;
+	default:
+		*val = 0;
+		return PCIBIOS_BAD_REGISTER_NUMBER;
+	}
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static int mobiveil_pcie_write(void __iomem *addr, int size, u32 val)
+{
+	if ((uintptr_t)addr & (size - 1))
+		return PCIBIOS_BAD_REGISTER_NUMBER;
+
+	switch (size) {
+	case 4:
+		writel(val, addr);
+		break;
+	case 2:
+		writew(val, addr);
+		break;
+	case 1:
+		writeb(val, addr);
+		break;
+	default:
+		return PCIBIOS_BAD_REGISTER_NUMBER;
+	}
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static u32 csr_read(struct mobiveil_pcie *pcie, u32 off, size_t size)
+{
+	void *addr;
+	u32 val;
+	int ret;
+
+	addr = mobiveil_pcie_comp_addr(pcie, off);
+
+	ret = mobiveil_pcie_read(addr, size, &val);
+	if (ret)
+		dev_err(&pcie->pdev->dev, "read CSR address failed\n");
+
+	return val;
+}
+
+static void csr_write(struct mobiveil_pcie *pcie, u32 val, u32 off, size_t size)
+{
+	void *addr;
+	int ret;
+
+	addr = mobiveil_pcie_comp_addr(pcie, off);
+
+	ret = mobiveil_pcie_write(addr, size, val);
+	if (ret)
+		dev_err(&pcie->pdev->dev, "write CSR address failed\n");
+}
+
+static u32 csr_readl(struct mobiveil_pcie *pcie, u32 off)
+{
+	return csr_read(pcie, off, 0x4);
+}
+
+static void csr_writel(struct mobiveil_pcie *pcie, u32 val, u32 off)
+{
+	csr_write(pcie, val, off, 0x4);
 }
 
 static bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie)
@@ -342,45 +451,6 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie)
 	return 0;
 }
 
-/*
- * select_paged_register - routine to access paged register of root complex
- *
- * registers of RC are paged, for this scheme to work
- * extracted higher 6 bits of the offset will be written to pg_sel
- * field of PAB_CTRL register and rest of the lower 10 bits enabled with
- * PAGE_SEL_EN are used as offset of the register.
- */
-static void select_paged_register(struct mobiveil_pcie *pcie, u32 offset)
-{
-	int pab_ctrl_dw, pg_sel;
-
-	/* clear pg_sel field */
-	pab_ctrl_dw = csr_readl(pcie, PAB_CTRL);
-	pab_ctrl_dw = (pab_ctrl_dw & ~(PAGE_SEL_MASK << PAGE_SEL_SHIFT));
-
-	/* set pg_sel field */
-	pg_sel = (offset >> PAGE_SEL_OFFSET_SHIFT) & PAGE_SEL_MASK;
-	pab_ctrl_dw |= ((pg_sel << PAGE_SEL_SHIFT));
-	csr_writel(pcie, pab_ctrl_dw, PAB_CTRL);
-}
-
-static void write_paged_register(struct mobiveil_pcie *pcie,
-		u32 val, u32 offset)
-{
-	u32 off = (offset & PAGE_LO_MASK) | PAGE_SEL_EN;
-
-	select_paged_register(pcie, offset);
-	csr_writel(pcie, val, off);
-}
-
-static u32 read_paged_register(struct mobiveil_pcie *pcie, u32 offset)
-{
-	u32 off = (offset & PAGE_LO_MASK) | PAGE_SEL_EN;
-
-	select_paged_register(pcie, offset);
-	return csr_readl(pcie, off);
-}
-
 static void program_ib_windows(struct mobiveil_pcie *pcie, int win_num,
 		int pci_addr, u32 type, u64 size)
 {
@@ -397,19 +467,19 @@ static void program_ib_windows(struct mobiveil_pcie *pcie, int win_num,
 	pio_ctrl_val = csr_readl(pcie, PAB_PEX_PIO_CTRL);
 	csr_writel(pcie,
 		pio_ctrl_val | (1 << PIO_ENABLE_SHIFT), PAB_PEX_PIO_CTRL);
-	amap_ctrl_dw = read_paged_register(pcie, PAB_PEX_AMAP_CTRL(win_num));
+	amap_ctrl_dw = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
 	amap_ctrl_dw = (amap_ctrl_dw | (type << AMAP_CTRL_TYPE_SHIFT));
 	amap_ctrl_dw = (amap_ctrl_dw | (1 << AMAP_CTRL_EN_SHIFT));
 
-	write_paged_register(pcie, amap_ctrl_dw | lower_32_bits(size64),
-				PAB_PEX_AMAP_CTRL(win_num));
+	csr_writel(pcie, amap_ctrl_dw | lower_32_bits(size64),
+		   PAB_PEX_AMAP_CTRL(win_num));
 
-	write_paged_register(pcie, upper_32_bits(size64),
-				PAB_EXT_PEX_AMAP_SIZEN(win_num));
+	csr_writel(pcie, upper_32_bits(size64),
+		   PAB_EXT_PEX_AMAP_SIZEN(win_num));
 
-	write_paged_register(pcie, pci_addr, PAB_PEX_AMAP_AXI_WIN(win_num));
-	write_paged_register(pcie, pci_addr, PAB_PEX_AMAP_PEX_WIN_L(win_num));
-	write_paged_register(pcie, 0, PAB_PEX_AMAP_PEX_WIN_H(win_num));
+	csr_writel(pcie, pci_addr, PAB_PEX_AMAP_AXI_WIN(win_num));
+	csr_writel(pcie, pci_addr, PAB_PEX_AMAP_PEX_WIN_L(win_num));
+	csr_writel(pcie, 0, PAB_PEX_AMAP_PEX_WIN_H(win_num));
 }
 
 /*
@@ -437,8 +507,7 @@ static void program_ob_windows(struct mobiveil_pcie *pcie, int win_num,
 	csr_writel(pcie, 1 << WIN_ENABLE_SHIFT | type << WIN_TYPE_SHIFT |
 			lower_32_bits(size64), PAB_AXI_AMAP_CTRL(win_num));
 
-	write_paged_register(pcie, upper_32_bits(size64),
-				PAB_EXT_AXI_AMAP_SIZE(win_num));
+	csr_writel(pcie, upper_32_bits(size64), PAB_EXT_AXI_AMAP_SIZE(win_num));
 
 	/*
 	 * program AXI window base with appropriate value in
-- 
2.17.1


^ permalink raw reply	[flat|nested] 67+ messages in thread

* [PATCHv5 02/20] PCI: mobiveil: Format the code without functionality change
  2019-04-12  8:35 [PATCHv5 00/20] PCI: mobiveil: fixes for Mobiveil PCIe Host Bridge IP driver Z.q. Hou
  2019-04-12  8:35 ` [PATCHv5 01/20] PCI: mobiveil: Unify register accessors Z.q. Hou
@ 2019-04-12  8:35 ` Z.q. Hou
  2019-07-03 15:10   ` Lorenzo Pieralisi
  2019-07-03 15:19   ` Lorenzo Pieralisi
  2019-04-12  8:35 ` [PATCHv5 03/20] PCI: mobiveil: Correct the returned error number Z.q. Hou
                   ` (18 subsequent siblings)
  20 siblings, 2 replies; 67+ messages in thread
From: Z.q. Hou @ 2019-04-12  8:35 UTC (permalink / raw)
  To: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	lorenzo.pieralisi, catalin.marinas, will.deacon
  Cc: Mingkai Hu, M.h. Lian, Xiaowei Bao, Z.q. Hou

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Just format the code without functionality change.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
---
V5:
 - Retouched the subject.

 drivers/pci/controller/pcie-mobiveil.c | 261 +++++++++++++------------
 1 file changed, 137 insertions(+), 124 deletions(-)

diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c
index d55c7e780c6e..b87471f08a40 100644
--- a/drivers/pci/controller/pcie-mobiveil.c
+++ b/drivers/pci/controller/pcie-mobiveil.c
@@ -31,38 +31,40 @@
  * translation tables are grouped into windows, each window registers are
  * grouped into blocks of 4 or 16 registers each
  */
-#define PAB_REG_BLOCK_SIZE	16
-#define PAB_EXT_REG_BLOCK_SIZE	4
+#define PAB_REG_BLOCK_SIZE		16
+#define PAB_EXT_REG_BLOCK_SIZE		4
 
-#define PAB_REG_ADDR(offset, win) (offset + (win * PAB_REG_BLOCK_SIZE))
-#define PAB_EXT_REG_ADDR(offset, win) (offset + (win * PAB_EXT_REG_BLOCK_SIZE))
+#define PAB_REG_ADDR(offset, win)	\
+	(offset + (win * PAB_REG_BLOCK_SIZE))
+#define PAB_EXT_REG_ADDR(offset, win)	\
+	(offset + (win * PAB_EXT_REG_BLOCK_SIZE))
 
-#define LTSSM_STATUS		0x0404
-#define  LTSSM_STATUS_L0_MASK	0x3f
-#define  LTSSM_STATUS_L0	0x2d
+#define LTSSM_STATUS			0x0404
+#define  LTSSM_STATUS_L0_MASK		0x3f
+#define  LTSSM_STATUS_L0		0x2d
 
-#define PAB_CTRL		0x0808
-#define  AMBA_PIO_ENABLE_SHIFT	0
-#define  PEX_PIO_ENABLE_SHIFT	1
-#define  PAGE_SEL_SHIFT	13
-#define  PAGE_SEL_MASK		0x3f
-#define  PAGE_LO_MASK		0x3ff
-#define  PAGE_SEL_OFFSET_SHIFT	10
+#define PAB_CTRL			0x0808
+#define  AMBA_PIO_ENABLE_SHIFT		0
+#define  PEX_PIO_ENABLE_SHIFT		1
+#define  PAGE_SEL_SHIFT			13
+#define  PAGE_SEL_MASK			0x3f
+#define  PAGE_LO_MASK			0x3ff
+#define  PAGE_SEL_OFFSET_SHIFT		10
 
-#define PAB_AXI_PIO_CTRL	0x0840
-#define  APIO_EN_MASK		0xf
+#define PAB_AXI_PIO_CTRL		0x0840
+#define  APIO_EN_MASK			0xf
 
-#define PAB_PEX_PIO_CTRL	0x08c0
-#define  PIO_ENABLE_SHIFT	0
+#define PAB_PEX_PIO_CTRL		0x08c0
+#define  PIO_ENABLE_SHIFT		0
 
 #define PAB_INTP_AMBA_MISC_ENB		0x0b0c
-#define PAB_INTP_AMBA_MISC_STAT	0x0b1c
+#define PAB_INTP_AMBA_MISC_STAT		0x0b1c
 #define  PAB_INTP_INTX_MASK		0x01e0
 #define  PAB_INTP_MSI_MASK		0x8
 
-#define PAB_AXI_AMAP_CTRL(win)	PAB_REG_ADDR(0x0ba0, win)
-#define  WIN_ENABLE_SHIFT	0
-#define  WIN_TYPE_SHIFT	1
+#define PAB_AXI_AMAP_CTRL(win)		PAB_REG_ADDR(0x0ba0, win)
+#define  WIN_ENABLE_SHIFT		0
+#define  WIN_TYPE_SHIFT			1
 
 #define PAB_EXT_AXI_AMAP_SIZE(win)	PAB_EXT_REG_ADDR(0xbaf0, win)
 
@@ -70,16 +72,16 @@
 #define  AXI_WINDOW_ALIGN_MASK		3
 
 #define PAB_AXI_AMAP_PEX_WIN_L(win)	PAB_REG_ADDR(0x0ba8, win)
-#define  PAB_BUS_SHIFT		24
-#define  PAB_DEVICE_SHIFT	19
-#define  PAB_FUNCTION_SHIFT	16
+#define  PAB_BUS_SHIFT			24
+#define  PAB_DEVICE_SHIFT		19
+#define  PAB_FUNCTION_SHIFT		16
 
 #define PAB_AXI_AMAP_PEX_WIN_H(win)	PAB_REG_ADDR(0x0bac, win)
 #define PAB_INTP_AXI_PIO_CLASS		0x474
 
-#define PAB_PEX_AMAP_CTRL(win)	PAB_REG_ADDR(0x4ba0, win)
-#define  AMAP_CTRL_EN_SHIFT	0
-#define  AMAP_CTRL_TYPE_SHIFT	1
+#define PAB_PEX_AMAP_CTRL(win)		PAB_REG_ADDR(0x4ba0, win)
+#define  AMAP_CTRL_EN_SHIFT		0
+#define  AMAP_CTRL_TYPE_SHIFT		1
 
 #define PAB_EXT_PEX_AMAP_SIZEN(win)	PAB_EXT_REG_ADDR(0xbef0, win)
 #define PAB_PEX_AMAP_AXI_WIN(win)	PAB_REG_ADDR(0x4ba4, win)
@@ -87,39 +89,39 @@
 #define PAB_PEX_AMAP_PEX_WIN_H(win)	PAB_REG_ADDR(0x4bac, win)
 
 /* starting offset of INTX bits in status register */
-#define PAB_INTX_START	5
+#define PAB_INTX_START			5
 
 /* supported number of MSI interrupts */
-#define PCI_NUM_MSI	16
+#define PCI_NUM_MSI			16
 
 /* MSI registers */
-#define MSI_BASE_LO_OFFSET	0x04
-#define MSI_BASE_HI_OFFSET	0x08
-#define MSI_SIZE_OFFSET	0x0c
-#define MSI_ENABLE_OFFSET	0x14
-#define MSI_STATUS_OFFSET	0x18
-#define MSI_DATA_OFFSET	0x20
-#define MSI_ADDR_L_OFFSET	0x24
-#define MSI_ADDR_H_OFFSET	0x28
+#define MSI_BASE_LO_OFFSET		0x04
+#define MSI_BASE_HI_OFFSET		0x08
+#define MSI_SIZE_OFFSET			0x0c
+#define MSI_ENABLE_OFFSET		0x14
+#define MSI_STATUS_OFFSET		0x18
+#define MSI_DATA_OFFSET			0x20
+#define MSI_ADDR_L_OFFSET		0x24
+#define MSI_ADDR_H_OFFSET		0x28
 
 /* outbound and inbound window definitions */
-#define WIN_NUM_0		0
-#define WIN_NUM_1		1
-#define CFG_WINDOW_TYPE	0
-#define IO_WINDOW_TYPE		1
-#define MEM_WINDOW_TYPE	2
-#define IB_WIN_SIZE		((u64)256 * 1024 * 1024 * 1024)
-#define MAX_PIO_WINDOWS	8
+#define WIN_NUM_0			0
+#define WIN_NUM_1			1
+#define CFG_WINDOW_TYPE			0
+#define IO_WINDOW_TYPE			1
+#define MEM_WINDOW_TYPE			2
+#define IB_WIN_SIZE			((u64)256 * 1024 * 1024 * 1024)
+#define MAX_PIO_WINDOWS			8
 
 /* Parameters for the waiting for link up routine */
-#define LINK_WAIT_MAX_RETRIES	10
-#define LINK_WAIT_MIN	90000
-#define LINK_WAIT_MAX	100000
+#define LINK_WAIT_MAX_RETRIES		10
+#define LINK_WAIT_MIN			90000
+#define LINK_WAIT_MAX			100000
 
-#define PAGED_ADDR_BNDRY			0xc00
-#define OFFSET_TO_PAGE_ADDR(off)		\
+#define PAGED_ADDR_BNDRY		0xc00
+#define OFFSET_TO_PAGE_ADDR(off)	\
 	((off & PAGE_LO_MASK) | PAGED_ADDR_BNDRY)
-#define OFFSET_TO_PAGE_IDX(off)			\
+#define OFFSET_TO_PAGE_IDX(off)		\
 	((off >> PAGE_SEL_OFFSET_SHIFT) & PAGE_SEL_MASK)
 
 struct mobiveil_msi {			/* MSI information */
@@ -297,14 +299,14 @@ static void __iomem *mobiveil_pcie_map_bus(struct pci_bus *bus,
 					unsigned int devfn, int where)
 {
 	struct mobiveil_pcie *pcie = bus->sysdata;
+	u32 value;
 
 	if (!mobiveil_pcie_valid_device(bus, devfn))
 		return NULL;
 
-	if (bus->number == pcie->root_bus_nr) {
-		/* RC config access */
+	/* RC config access */
+	if (bus->number == pcie->root_bus_nr)
 		return pcie->csr_axi_slave_base + where;
-	}
 
 	/*
 	 * EP config access (in Config/APIO space)
@@ -312,10 +314,12 @@ static void __iomem *mobiveil_pcie_map_bus(struct pci_bus *bus,
 	 * (BDF) in PAB_AXI_AMAP_PEX_WIN_L0 Register.
 	 * Relies on pci_lock serialization
 	 */
-	csr_writel(pcie, bus->number << PAB_BUS_SHIFT |
-			PCI_SLOT(devfn) << PAB_DEVICE_SHIFT |
-			PCI_FUNC(devfn) << PAB_FUNCTION_SHIFT,
-			PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0));
+	value = bus->number << PAB_BUS_SHIFT |
+		PCI_SLOT(devfn) << PAB_DEVICE_SHIFT |
+		PCI_FUNC(devfn) << PAB_FUNCTION_SHIFT;
+
+	csr_writel(pcie, value, PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0));
+
 	return pcie->config_axi_slave_base + where;
 }
 
@@ -350,22 +354,22 @@ static void mobiveil_pcie_isr(struct irq_desc *desc)
 
 	/* Handle INTx */
 	if (intr_status & PAB_INTP_INTX_MASK) {
-		shifted_status = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT) >>
-			PAB_INTX_START;
+		shifted_status = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT);
+		shifted_status >>= PAB_INTX_START;
 		do {
 			for_each_set_bit(bit, &shifted_status, PCI_NUM_INTX) {
 				virq = irq_find_mapping(pcie->intx_domain,
-						bit + 1);
+							bit + 1);
 				if (virq)
 					generic_handle_irq(virq);
 				else
-					dev_err_ratelimited(dev,
-						"unexpected IRQ, INT%d\n", bit);
+					dev_err_ratelimited(dev, "unexpected IRQ, INT%d\n",
+							    bit);
 
 				/* clear interrupt */
 				csr_writel(pcie,
-					shifted_status << PAB_INTX_START,
-					PAB_INTP_AMBA_MISC_STAT);
+					   shifted_status << PAB_INTX_START,
+					   PAB_INTP_AMBA_MISC_STAT);
 			}
 		} while ((shifted_status >> PAB_INTX_START) != 0);
 	}
@@ -375,8 +379,7 @@ static void mobiveil_pcie_isr(struct irq_desc *desc)
 
 	/* handle MSI interrupts */
 	while (msi_status & 1) {
-		msi_data = readl_relaxed(pcie->apb_csr_base
-				+ MSI_DATA_OFFSET);
+		msi_data = readl_relaxed(pcie->apb_csr_base + MSI_DATA_OFFSET);
 
 		/*
 		 * MSI_STATUS_OFFSET register gets updated to zero
@@ -385,18 +388,18 @@ static void mobiveil_pcie_isr(struct irq_desc *desc)
 		 * two dummy reads.
 		 */
 		msi_addr_lo = readl_relaxed(pcie->apb_csr_base +
-				MSI_ADDR_L_OFFSET);
+					    MSI_ADDR_L_OFFSET);
 		msi_addr_hi = readl_relaxed(pcie->apb_csr_base +
-				MSI_ADDR_H_OFFSET);
+					    MSI_ADDR_H_OFFSET);
 		dev_dbg(dev, "MSI registers, data: %08x, addr: %08x:%08x\n",
-				msi_data, msi_addr_hi, msi_addr_lo);
+			msi_data, msi_addr_hi, msi_addr_lo);
 
 		virq = irq_find_mapping(msi->dev_domain, msi_data);
 		if (virq)
 			generic_handle_irq(virq);
 
 		msi_status = readl_relaxed(pcie->apb_csr_base +
-				MSI_STATUS_OFFSET);
+					   MSI_STATUS_OFFSET);
 	}
 
 	/* Clear the interrupt status */
@@ -413,7 +416,7 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie)
 
 	/* map config resource */
 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
-			"config_axi_slave");
+					   "config_axi_slave");
 	pcie->config_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);
 	if (IS_ERR(pcie->config_axi_slave_base))
 		return PTR_ERR(pcie->config_axi_slave_base);
@@ -421,7 +424,7 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie)
 
 	/* map csr resource */
 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
-			"csr_axi_slave");
+					   "csr_axi_slave");
 	pcie->csr_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);
 	if (IS_ERR(pcie->csr_axi_slave_base))
 		return PTR_ERR(pcie->csr_axi_slave_base);
@@ -452,7 +455,7 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie)
 }
 
 static void program_ib_windows(struct mobiveil_pcie *pcie, int win_num,
-		int pci_addr, u32 type, u64 size)
+			       int pci_addr, u32 type, u64 size)
 {
 	int pio_ctrl_val;
 	int amap_ctrl_dw;
@@ -465,19 +468,20 @@ static void program_ib_windows(struct mobiveil_pcie *pcie, int win_num,
 	}
 
 	pio_ctrl_val = csr_readl(pcie, PAB_PEX_PIO_CTRL);
-	csr_writel(pcie,
-		pio_ctrl_val | (1 << PIO_ENABLE_SHIFT), PAB_PEX_PIO_CTRL);
-	amap_ctrl_dw = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
-	amap_ctrl_dw = (amap_ctrl_dw | (type << AMAP_CTRL_TYPE_SHIFT));
-	amap_ctrl_dw = (amap_ctrl_dw | (1 << AMAP_CTRL_EN_SHIFT));
+	pio_ctrl_val |= 1 << PIO_ENABLE_SHIFT;
+	csr_writel(pcie, pio_ctrl_val, PAB_PEX_PIO_CTRL);
 
-	csr_writel(pcie, amap_ctrl_dw | lower_32_bits(size64),
-		   PAB_PEX_AMAP_CTRL(win_num));
+	amap_ctrl_dw = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
+	amap_ctrl_dw |= (type << AMAP_CTRL_TYPE_SHIFT) |
+			(1 << AMAP_CTRL_EN_SHIFT) |
+			lower_32_bits(size64);
+	csr_writel(pcie, amap_ctrl_dw, PAB_PEX_AMAP_CTRL(win_num));
 
 	csr_writel(pcie, upper_32_bits(size64),
 		   PAB_EXT_PEX_AMAP_SIZEN(win_num));
 
 	csr_writel(pcie, pci_addr, PAB_PEX_AMAP_AXI_WIN(win_num));
+
 	csr_writel(pcie, pci_addr, PAB_PEX_AMAP_PEX_WIN_L(win_num));
 	csr_writel(pcie, 0, PAB_PEX_AMAP_PEX_WIN_H(win_num));
 }
@@ -486,7 +490,8 @@ static void program_ib_windows(struct mobiveil_pcie *pcie, int win_num,
  * routine to program the outbound windows
  */
 static void program_ob_windows(struct mobiveil_pcie *pcie, int win_num,
-		u64 cpu_addr, u64 pci_addr, u32 config_io_bit, u64 size)
+			       u64 cpu_addr, u64 pci_addr,
+			       u32 config_io_bit, u64 size)
 {
 
 	u32 value, type;
@@ -505,7 +510,7 @@ static void program_ob_windows(struct mobiveil_pcie *pcie, int win_num,
 	type = config_io_bit;
 	value = csr_readl(pcie, PAB_AXI_AMAP_CTRL(win_num));
 	csr_writel(pcie, 1 << WIN_ENABLE_SHIFT | type << WIN_TYPE_SHIFT |
-			lower_32_bits(size64), PAB_AXI_AMAP_CTRL(win_num));
+		   lower_32_bits(size64), PAB_AXI_AMAP_CTRL(win_num));
 
 	csr_writel(pcie, upper_32_bits(size64), PAB_EXT_AXI_AMAP_SIZE(win_num));
 
@@ -515,14 +520,14 @@ static void program_ob_windows(struct mobiveil_pcie *pcie, int win_num,
 	 */
 	value = csr_readl(pcie, PAB_AXI_AMAP_AXI_WIN(win_num));
 	csr_writel(pcie, cpu_addr & (~AXI_WINDOW_ALIGN_MASK),
-			PAB_AXI_AMAP_AXI_WIN(win_num));
+		   PAB_AXI_AMAP_AXI_WIN(win_num));
 
 	value = csr_readl(pcie, PAB_AXI_AMAP_PEX_WIN_H(win_num));
 
 	csr_writel(pcie, lower_32_bits(pci_addr),
-			PAB_AXI_AMAP_PEX_WIN_L(win_num));
+		   PAB_AXI_AMAP_PEX_WIN_L(win_num));
 	csr_writel(pcie, upper_32_bits(pci_addr),
-			PAB_AXI_AMAP_PEX_WIN_H(win_num));
+		   PAB_AXI_AMAP_PEX_WIN_H(win_num));
 
 	pcie->ob_wins_configured++;
 }
@@ -538,7 +543,9 @@ static int mobiveil_bringup_link(struct mobiveil_pcie *pcie)
 
 		usleep_range(LINK_WAIT_MIN, LINK_WAIT_MAX);
 	}
+
 	dev_err(&pcie->pdev->dev, "link never came up\n");
+
 	return -ETIMEDOUT;
 }
 
@@ -551,16 +558,16 @@ static void mobiveil_pcie_enable_msi(struct mobiveil_pcie *pcie)
 	msi->msi_pages_phys = (phys_addr_t)msg_addr;
 
 	writel_relaxed(lower_32_bits(msg_addr),
-		pcie->apb_csr_base + MSI_BASE_LO_OFFSET);
+		       pcie->apb_csr_base + MSI_BASE_LO_OFFSET);
 	writel_relaxed(upper_32_bits(msg_addr),
-		pcie->apb_csr_base + MSI_BASE_HI_OFFSET);
+		       pcie->apb_csr_base + MSI_BASE_HI_OFFSET);
 	writel_relaxed(4096, pcie->apb_csr_base + MSI_SIZE_OFFSET);
 	writel_relaxed(1, pcie->apb_csr_base + MSI_ENABLE_OFFSET);
 }
 
 static int mobiveil_host_init(struct mobiveil_pcie *pcie)
 {
-	u32 value, pab_ctrl, type = 0;
+	u32 value, pab_ctrl, type;
 	int err;
 	struct resource_entry *win, *tmp;
 
@@ -575,26 +582,27 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
 	 * Space
 	 */
 	value = csr_readl(pcie, PCI_COMMAND);
-	csr_writel(pcie, value | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
-		PCI_COMMAND_MASTER, PCI_COMMAND);
+	value |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
+	csr_writel(pcie, value, PCI_COMMAND);
 
 	/*
 	 * program PIO Enable Bit to 1 (and PEX PIO Enable to 1) in PAB_CTRL
 	 * register
 	 */
 	pab_ctrl = csr_readl(pcie, PAB_CTRL);
-	csr_writel(pcie, pab_ctrl | (1 << AMBA_PIO_ENABLE_SHIFT) |
-		(1 << PEX_PIO_ENABLE_SHIFT), PAB_CTRL);
+	pab_ctrl |= (1 << AMBA_PIO_ENABLE_SHIFT) | (1 << PEX_PIO_ENABLE_SHIFT);
+	csr_writel(pcie, pab_ctrl, PAB_CTRL);
 
 	csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK),
-		PAB_INTP_AMBA_MISC_ENB);
+		   PAB_INTP_AMBA_MISC_ENB);
 
 	/*
 	 * program PIO Enable Bit to 1 and Config Window Enable Bit to 1 in
 	 * PAB_AXI_PIO_CTRL Register
 	 */
 	value = csr_readl(pcie, PAB_AXI_PIO_CTRL);
-	csr_writel(pcie, value | APIO_EN_MASK, PAB_AXI_PIO_CTRL);
+	value |= APIO_EN_MASK;
+	csr_writel(pcie, value, PAB_AXI_PIO_CTRL);
 
 	/*
 	 * we'll program one outbound window for config reads and
@@ -605,25 +613,25 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
 
 	/* config outbound translation window */
 	program_ob_windows(pcie, pcie->ob_wins_configured,
-			pcie->ob_io_res->start, 0, CFG_WINDOW_TYPE,
-			resource_size(pcie->ob_io_res));
+			   pcie->ob_io_res->start, 0, CFG_WINDOW_TYPE,
+			   resource_size(pcie->ob_io_res));
 
 	/* memory inbound translation window */
 	program_ib_windows(pcie, WIN_NUM_1, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE);
 
 	/* Get the I/O and memory ranges from DT */
 	resource_list_for_each_entry_safe(win, tmp, &pcie->resources) {
-		type = 0;
 		if (resource_type(win->res) == IORESOURCE_MEM)
 			type = MEM_WINDOW_TYPE;
-		if (resource_type(win->res) == IORESOURCE_IO)
+		else if (resource_type(win->res) == IORESOURCE_IO)
 			type = IO_WINDOW_TYPE;
-		if (type) {
-			/* configure outbound translation window */
-			program_ob_windows(pcie, pcie->ob_wins_configured,
-				win->res->start, 0, type,
-				resource_size(win->res));
-		}
+		else
+			continue;
+
+		/* configure outbound translation window */
+		program_ob_windows(pcie, pcie->ob_wins_configured,
+				   win->res->start, 0, type,
+				   resource_size(win->res));
 	}
 
 	/* setup MSI hardware registers */
@@ -643,7 +651,8 @@ static void mobiveil_mask_intx_irq(struct irq_data *data)
 	mask = 1 << ((data->hwirq + PAB_INTX_START) - 1);
 	raw_spin_lock_irqsave(&pcie->intx_mask_lock, flags);
 	shifted_val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
-	csr_writel(pcie, (shifted_val & (~mask)), PAB_INTP_AMBA_MISC_ENB);
+	shifted_val &= ~mask;
+	csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
 	raw_spin_unlock_irqrestore(&pcie->intx_mask_lock, flags);
 }
 
@@ -658,7 +667,8 @@ static void mobiveil_unmask_intx_irq(struct irq_data *data)
 	mask = 1 << ((data->hwirq + PAB_INTX_START) - 1);
 	raw_spin_lock_irqsave(&pcie->intx_mask_lock, flags);
 	shifted_val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
-	csr_writel(pcie, (shifted_val | mask), PAB_INTP_AMBA_MISC_ENB);
+	shifted_val |= mask;
+	csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
 	raw_spin_unlock_irqrestore(&pcie->intx_mask_lock, flags);
 }
 
@@ -672,10 +682,11 @@ static struct irq_chip intx_irq_chip = {
 
 /* routine to setup the INTx related data */
 static int mobiveil_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
-		irq_hw_number_t hwirq)
+				  irq_hw_number_t hwirq)
 {
 	irq_set_chip_and_handler(irq, &intx_irq_chip, handle_level_irq);
 	irq_set_chip_data(irq, domain->host_data);
+
 	return 0;
 }
 
@@ -692,7 +703,7 @@ static struct irq_chip mobiveil_msi_irq_chip = {
 
 static struct msi_domain_info mobiveil_msi_domain_info = {
 	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
-		MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX),
+		   MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX),
 	.chip	= &mobiveil_msi_irq_chip,
 };
 
@@ -710,7 +721,7 @@ static void mobiveil_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
 }
 
 static int mobiveil_msi_set_affinity(struct irq_data *irq_data,
-		const struct cpumask *mask, bool force)
+				     const struct cpumask *mask, bool force)
 {
 	return -EINVAL;
 }
@@ -722,7 +733,8 @@ static struct irq_chip mobiveil_msi_bottom_irq_chip = {
 };
 
 static int mobiveil_irq_msi_domain_alloc(struct irq_domain *domain,
-		unsigned int virq, unsigned int nr_irqs, void *args)
+					 unsigned int virq,
+					 unsigned int nr_irqs, void *args)
 {
 	struct mobiveil_pcie *pcie = domain->host_data;
 	struct mobiveil_msi *msi = &pcie->msi;
@@ -742,13 +754,13 @@ static int mobiveil_irq_msi_domain_alloc(struct irq_domain *domain,
 	mutex_unlock(&msi->lock);
 
 	irq_domain_set_info(domain, virq, bit, &mobiveil_msi_bottom_irq_chip,
-				domain->host_data, handle_level_irq,
-				NULL, NULL);
+			    domain->host_data, handle_level_irq, NULL, NULL);
 	return 0;
 }
 
 static void mobiveil_irq_msi_domain_free(struct irq_domain *domain,
-		unsigned int virq, unsigned int nr_irqs)
+					 unsigned int virq,
+					 unsigned int nr_irqs)
 {
 	struct irq_data *d = irq_domain_get_irq_data(domain, virq);
 	struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(d);
@@ -756,12 +768,11 @@ static void mobiveil_irq_msi_domain_free(struct irq_domain *domain,
 
 	mutex_lock(&msi->lock);
 
-	if (!test_bit(d->hwirq, msi->msi_irq_in_use)) {
+	if (!test_bit(d->hwirq, msi->msi_irq_in_use))
 		dev_err(&pcie->pdev->dev, "trying to free unused MSI#%lu\n",
 			d->hwirq);
-	} else {
+	else
 		__clear_bit(d->hwirq, msi->msi_irq_in_use);
-	}
 
 	mutex_unlock(&msi->lock);
 }
@@ -785,12 +796,14 @@ static int mobiveil_allocate_msi_domains(struct mobiveil_pcie *pcie)
 	}
 
 	msi->msi_domain = pci_msi_create_irq_domain(fwnode,
-				&mobiveil_msi_domain_info, msi->dev_domain);
+						    &mobiveil_msi_domain_info,
+						    msi->dev_domain);
 	if (!msi->msi_domain) {
 		dev_err(dev, "failed to create MSI domain\n");
 		irq_domain_remove(msi->dev_domain);
 		return -ENOMEM;
 	}
+
 	return 0;
 }
 
@@ -801,8 +814,8 @@ static int mobiveil_pcie_init_irq_domain(struct mobiveil_pcie *pcie)
 	int ret;
 
 	/* setup INTx */
-	pcie->intx_domain = irq_domain_add_linear(node,
-				PCI_NUM_INTX, &intx_domain_ops, pcie);
+	pcie->intx_domain = irq_domain_add_linear(node, PCI_NUM_INTX,
+						  &intx_domain_ops, pcie);
 
 	if (!pcie->intx_domain) {
 		dev_err(dev, "Failed to get a INTx IRQ domain\n");
@@ -917,10 +930,10 @@ MODULE_DEVICE_TABLE(of, mobiveil_pcie_of_match);
 static struct platform_driver mobiveil_pcie_driver = {
 	.probe = mobiveil_pcie_probe,
 	.driver = {
-			.name = "mobiveil-pcie",
-			.of_match_table = mobiveil_pcie_of_match,
-			.suppress_bind_attrs = true,
-		},
+		.name = "mobiveil-pcie",
+		.of_match_table = mobiveil_pcie_of_match,
+		.suppress_bind_attrs = true,
+	},
 };
 
 builtin_platform_driver(mobiveil_pcie_driver);
-- 
2.17.1


^ permalink raw reply	[flat|nested] 67+ messages in thread

* [PATCHv5 03/20] PCI: mobiveil: Correct the returned error number
  2019-04-12  8:35 [PATCHv5 00/20] PCI: mobiveil: fixes for Mobiveil PCIe Host Bridge IP driver Z.q. Hou
  2019-04-12  8:35 ` [PATCHv5 01/20] PCI: mobiveil: Unify register accessors Z.q. Hou
  2019-04-12  8:35 ` [PATCHv5 02/20] PCI: mobiveil: Format the code without functionality change Z.q. Hou
@ 2019-04-12  8:35 ` Z.q. Hou
  2019-07-03 14:17   ` Lorenzo Pieralisi
  2019-04-12  8:35 ` [PATCHv5 04/20] PCI: mobiveil: Remove the flag MSI_FLAG_MULTI_PCI_MSI Z.q. Hou
                   ` (17 subsequent siblings)
  20 siblings, 1 reply; 67+ messages in thread
From: Z.q. Hou @ 2019-04-12  8:35 UTC (permalink / raw)
  To: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	lorenzo.pieralisi, catalin.marinas, will.deacon
  Cc: Mingkai Hu, M.h. Lian, Xiaowei Bao, Z.q. Hou

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

This patch corrects the returned error number by convention,
and removes an unnecessary error check.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
---
V5:
 - Corrected and retouched the subject and changelog.

 drivers/pci/controller/pcie-mobiveil.c | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c
index b87471f08a40..563210e731d3 100644
--- a/drivers/pci/controller/pcie-mobiveil.c
+++ b/drivers/pci/controller/pcie-mobiveil.c
@@ -819,7 +819,7 @@ static int mobiveil_pcie_init_irq_domain(struct mobiveil_pcie *pcie)
 
 	if (!pcie->intx_domain) {
 		dev_err(dev, "Failed to get a INTx IRQ domain\n");
-		return -ENODEV;
+		return -ENOMEM;
 	}
 
 	raw_spin_lock_init(&pcie->intx_mask_lock);
@@ -845,11 +845,9 @@ static int mobiveil_pcie_probe(struct platform_device *pdev)
 	/* allocate the PCIe port */
 	bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
 	if (!bridge)
-		return -ENODEV;
+		return -ENOMEM;
 
 	pcie = pci_host_bridge_priv(bridge);
-	if (!pcie)
-		return -ENOMEM;
 
 	pcie->pdev = pdev;
 
@@ -866,7 +864,7 @@ static int mobiveil_pcie_probe(struct platform_device *pdev)
 						    &pcie->resources, &iobase);
 	if (ret) {
 		dev_err(dev, "Getting bridge resources failed\n");
-		return -ENOMEM;
+		return ret;
 	}
 
 	/*
-- 
2.17.1


^ permalink raw reply	[flat|nested] 67+ messages in thread

* [PATCHv5 04/20] PCI: mobiveil: Remove the flag MSI_FLAG_MULTI_PCI_MSI
  2019-04-12  8:35 [PATCHv5 00/20] PCI: mobiveil: fixes for Mobiveil PCIe Host Bridge IP driver Z.q. Hou
                   ` (2 preceding siblings ...)
  2019-04-12  8:35 ` [PATCHv5 03/20] PCI: mobiveil: Correct the returned error number Z.q. Hou
@ 2019-04-12  8:35 ` Z.q. Hou
  2019-06-11 16:59   ` Lorenzo Pieralisi
  2019-04-12  8:35 ` [PATCHv5 05/20] PCI: mobiveil: Correct PCI base address in MEM/IO outbound windows Z.q. Hou
                   ` (16 subsequent siblings)
  20 siblings, 1 reply; 67+ messages in thread
From: Z.q. Hou @ 2019-04-12  8:35 UTC (permalink / raw)
  To: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	lorenzo.pieralisi, catalin.marinas, will.deacon
  Cc: Mingkai Hu, M.h. Lian, Xiaowei Bao, Z.q. Hou

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

The current code does not support multiple MSIs, so remove
the corresponding flag from the msi_domain_info structure.

Fixes: 1e913e58335f ("PCI: mobiveil: Add MSI support")
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
---
V5:
 - Corrected the subject.

 drivers/pci/controller/pcie-mobiveil.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c
index 563210e731d3..a0dd337c6214 100644
--- a/drivers/pci/controller/pcie-mobiveil.c
+++ b/drivers/pci/controller/pcie-mobiveil.c
@@ -703,7 +703,7 @@ static struct irq_chip mobiveil_msi_irq_chip = {
 
 static struct msi_domain_info mobiveil_msi_domain_info = {
 	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
-		   MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX),
+		   MSI_FLAG_PCI_MSIX),
 	.chip	= &mobiveil_msi_irq_chip,
 };
 
-- 
2.17.1


^ permalink raw reply	[flat|nested] 67+ messages in thread

* [PATCHv5 05/20] PCI: mobiveil: Correct PCI base address in MEM/IO outbound windows
  2019-04-12  8:35 [PATCHv5 00/20] PCI: mobiveil: fixes for Mobiveil PCIe Host Bridge IP driver Z.q. Hou
                   ` (3 preceding siblings ...)
  2019-04-12  8:35 ` [PATCHv5 04/20] PCI: mobiveil: Remove the flag MSI_FLAG_MULTI_PCI_MSI Z.q. Hou
@ 2019-04-12  8:35 ` Z.q. Hou
  2019-04-12  8:35 ` [PATCHv5 06/20] PCI: mobiveil: Replace the resource list iteration function Z.q. Hou
                   ` (15 subsequent siblings)
  20 siblings, 0 replies; 67+ messages in thread
From: Z.q. Hou @ 2019-04-12  8:35 UTC (permalink / raw)
  To: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	lorenzo.pieralisi, catalin.marinas, will.deacon
  Cc: Mingkai Hu, M.h. Lian, Xiaowei Bao, Z.q. Hou

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

It should get PCI base address from the 'ranges' property of DT node
to setup MEM/IO outbound windows instead of always using zero.

Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver")
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
---
V5:
 - Corrected and retouched the subject and changelog.

 drivers/pci/controller/pcie-mobiveil.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c
index a0dd337c6214..8ff873023b5f 100644
--- a/drivers/pci/controller/pcie-mobiveil.c
+++ b/drivers/pci/controller/pcie-mobiveil.c
@@ -630,8 +630,9 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
 
 		/* configure outbound translation window */
 		program_ob_windows(pcie, pcie->ob_wins_configured,
-				   win->res->start, 0, type,
-				   resource_size(win->res));
+				   win->res->start,
+				   win->res->start - win->offset,
+				   type, resource_size(win->res));
 	}
 
 	/* setup MSI hardware registers */
-- 
2.17.1


^ permalink raw reply	[flat|nested] 67+ messages in thread

* [PATCHv5 06/20] PCI: mobiveil: Replace the resource list iteration function
  2019-04-12  8:35 [PATCHv5 00/20] PCI: mobiveil: fixes for Mobiveil PCIe Host Bridge IP driver Z.q. Hou
                   ` (4 preceding siblings ...)
  2019-04-12  8:35 ` [PATCHv5 05/20] PCI: mobiveil: Correct PCI base address in MEM/IO outbound windows Z.q. Hou
@ 2019-04-12  8:35 ` Z.q. Hou
  2019-04-12  8:35 ` [PATCHv5 07/20] PCI: mobiveil: Use WIN_NUM_0 explicitly for CFG outbound window Z.q. Hou
                   ` (14 subsequent siblings)
  20 siblings, 0 replies; 67+ messages in thread
From: Z.q. Hou @ 2019-04-12  8:35 UTC (permalink / raw)
  To: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	lorenzo.pieralisi, catalin.marinas, will.deacon
  Cc: Mingkai Hu, M.h. Lian, Xiaowei Bao, Z.q. Hou

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

As it won't delete any node during this iteration, replace
the function resource_list_for_each_entry_safe() with the
resource_list_for_each_entry().

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
---
V5:
 - Corrected and retouched the subject and changelog.

 drivers/pci/controller/pcie-mobiveil.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c
index 8ff873023b5f..b2cc9c097fc9 100644
--- a/drivers/pci/controller/pcie-mobiveil.c
+++ b/drivers/pci/controller/pcie-mobiveil.c
@@ -569,7 +569,7 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
 {
 	u32 value, pab_ctrl, type;
 	int err;
-	struct resource_entry *win, *tmp;
+	struct resource_entry *win;
 
 	err = mobiveil_bringup_link(pcie);
 	if (err) {
@@ -620,7 +620,7 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
 	program_ib_windows(pcie, WIN_NUM_1, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE);
 
 	/* Get the I/O and memory ranges from DT */
-	resource_list_for_each_entry_safe(win, tmp, &pcie->resources) {
+	resource_list_for_each_entry(win, &pcie->resources) {
 		if (resource_type(win->res) == IORESOURCE_MEM)
 			type = MEM_WINDOW_TYPE;
 		else if (resource_type(win->res) == IORESOURCE_IO)
-- 
2.17.1


^ permalink raw reply	[flat|nested] 67+ messages in thread

* [PATCHv5 07/20] PCI: mobiveil: Use WIN_NUM_0 explicitly for CFG outbound window
  2019-04-12  8:35 [PATCHv5 00/20] PCI: mobiveil: fixes for Mobiveil PCIe Host Bridge IP driver Z.q. Hou
                   ` (5 preceding siblings ...)
  2019-04-12  8:35 ` [PATCHv5 06/20] PCI: mobiveil: Replace the resource list iteration function Z.q. Hou
@ 2019-04-12  8:35 ` Z.q. Hou
  2019-06-12 15:13   ` Lorenzo Pieralisi
  2019-04-12  8:36 ` [PATCHv5 08/20] PCI: mobiveil: Use the 1st inbound window for MEM inbound transactions Z.q. Hou
                   ` (13 subsequent siblings)
  20 siblings, 1 reply; 67+ messages in thread
From: Z.q. Hou @ 2019-04-12  8:35 UTC (permalink / raw)
  To: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	lorenzo.pieralisi, catalin.marinas, will.deacon
  Cc: Mingkai Hu, M.h. Lian, Xiaowei Bao, Z.q. Hou

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

As the .map_bus() use the WIN_NUM_0 for CFG transactions,
it's better passing WIN_NUM_0 explicitly when initialize
the CFG outbound window.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
---
V5:
 - Corrected the subject.

 drivers/pci/controller/pcie-mobiveil.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c
index b2cc9c097fc9..df71c11b4810 100644
--- a/drivers/pci/controller/pcie-mobiveil.c
+++ b/drivers/pci/controller/pcie-mobiveil.c
@@ -612,9 +612,8 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
 	 */
 
 	/* config outbound translation window */
-	program_ob_windows(pcie, pcie->ob_wins_configured,
-			   pcie->ob_io_res->start, 0, CFG_WINDOW_TYPE,
-			   resource_size(pcie->ob_io_res));
+	program_ob_windows(pcie, WIN_NUM_0, pcie->ob_io_res->start, 0,
+			   CFG_WINDOW_TYPE, resource_size(pcie->ob_io_res));
 
 	/* memory inbound translation window */
 	program_ib_windows(pcie, WIN_NUM_1, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE);
-- 
2.17.1


^ permalink raw reply	[flat|nested] 67+ messages in thread

* [PATCHv5 08/20] PCI: mobiveil: Use the 1st inbound window for MEM inbound transactions
  2019-04-12  8:35 [PATCHv5 00/20] PCI: mobiveil: fixes for Mobiveil PCIe Host Bridge IP driver Z.q. Hou
                   ` (6 preceding siblings ...)
  2019-04-12  8:35 ` [PATCHv5 07/20] PCI: mobiveil: Use WIN_NUM_0 explicitly for CFG outbound window Z.q. Hou
@ 2019-04-12  8:36 ` Z.q. Hou
  2019-06-28 16:02   ` Lorenzo Pieralisi
  2019-04-12  8:36 ` [PATCHv5 09/20] PCI: mobiveil: Correct inbound/outbound window setup routines Z.q. Hou
                   ` (12 subsequent siblings)
  20 siblings, 1 reply; 67+ messages in thread
From: Z.q. Hou @ 2019-04-12  8:36 UTC (permalink / raw)
  To: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	lorenzo.pieralisi, catalin.marinas, will.deacon
  Cc: Mingkai Hu, M.h. Lian, Xiaowei Bao, Z.q. Hou

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

The inbound windows have independent register set against outbound windows.
This patch change the MEM inbound window to the first one.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
---
V5:
 - Corrected and retouched the subject and changelog.

 drivers/pci/controller/pcie-mobiveil.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c
index df71c11b4810..e88afc792a5c 100644
--- a/drivers/pci/controller/pcie-mobiveil.c
+++ b/drivers/pci/controller/pcie-mobiveil.c
@@ -616,7 +616,7 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
 			   CFG_WINDOW_TYPE, resource_size(pcie->ob_io_res));
 
 	/* memory inbound translation window */
-	program_ib_windows(pcie, WIN_NUM_1, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE);
+	program_ib_windows(pcie, WIN_NUM_0, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE);
 
 	/* Get the I/O and memory ranges from DT */
 	resource_list_for_each_entry(win, &pcie->resources) {
-- 
2.17.1


^ permalink raw reply	[flat|nested] 67+ messages in thread

* [PATCHv5 09/20] PCI: mobiveil: Correct inbound/outbound window setup routines
  2019-04-12  8:35 [PATCHv5 00/20] PCI: mobiveil: fixes for Mobiveil PCIe Host Bridge IP driver Z.q. Hou
                   ` (7 preceding siblings ...)
  2019-04-12  8:36 ` [PATCHv5 08/20] PCI: mobiveil: Use the 1st inbound window for MEM inbound transactions Z.q. Hou
@ 2019-04-12  8:36 ` Z.q. Hou
  2019-06-28 16:41   ` Lorenzo Pieralisi
  2019-04-12  8:36 ` [PATCHv5 10/20] PCI: mobiveil: Fix the INTx process errors Z.q. Hou
                   ` (11 subsequent siblings)
  20 siblings, 1 reply; 67+ messages in thread
From: Z.q. Hou @ 2019-04-12  8:36 UTC (permalink / raw)
  To: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	lorenzo.pieralisi, catalin.marinas, will.deacon
  Cc: Mingkai Hu, M.h. Lian, Xiaowei Bao, Z.q. Hou

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Outbound window routine:
 - Remove unused var definitions and register read operations.
 - Add the upper 32-bit cpu address setup of the window.
 - Instead of blindly write, only change the fields specified.
 - Mask the lower bits of window size in case override the
   control bits.
 - Check if the passing window number is available, instead of
   the total number of the initialized windows.

Inbound window routine:
 - Add parameter 'u64 cpu_addr' to specify the cpu address
   of the window instead of using 'pci_addr'.
 - Change 'int pci_addr' to 'u64 pci_addr', and add setup
   of the upper 32-bit PCI address of the window.
 - Move the PCIe PIO master enablement to mobiveil_host_init().
 - Instead of blindly write, only change the fields specified.
 - Mask the lower bits of window size in case override the
   control bits.
 - Check if the passing window number is available, instead of
   the total number of the initialized windows.
 - And add the statistic of initialized inbound windows.

Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver")
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
---
V5:
 - Corrected and retouched the subject and changelog.

 drivers/pci/controller/pcie-mobiveil.c | 70 +++++++++++++++-----------
 1 file changed, 42 insertions(+), 28 deletions(-)

diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c
index e88afc792a5c..4ba458474e42 100644
--- a/drivers/pci/controller/pcie-mobiveil.c
+++ b/drivers/pci/controller/pcie-mobiveil.c
@@ -65,9 +65,13 @@
 #define PAB_AXI_AMAP_CTRL(win)		PAB_REG_ADDR(0x0ba0, win)
 #define  WIN_ENABLE_SHIFT		0
 #define  WIN_TYPE_SHIFT			1
+#define  WIN_TYPE_MASK			0x3
+#define  WIN_SIZE_SHIFT			10
+#define  WIN_SIZE_MASK			0x3fffff
 
 #define PAB_EXT_AXI_AMAP_SIZE(win)	PAB_EXT_REG_ADDR(0xbaf0, win)
 
+#define PAB_EXT_AXI_AMAP_AXI_WIN(win)	PAB_EXT_REG_ADDR(0x80a0, win)
 #define PAB_AXI_AMAP_AXI_WIN(win)	PAB_REG_ADDR(0x0ba4, win)
 #define  AXI_WINDOW_ALIGN_MASK		3
 
@@ -82,8 +86,10 @@
 #define PAB_PEX_AMAP_CTRL(win)		PAB_REG_ADDR(0x4ba0, win)
 #define  AMAP_CTRL_EN_SHIFT		0
 #define  AMAP_CTRL_TYPE_SHIFT		1
+#define  AMAP_CTRL_TYPE_MASK		3
 
 #define PAB_EXT_PEX_AMAP_SIZEN(win)	PAB_EXT_REG_ADDR(0xbef0, win)
+#define PAB_EXT_PEX_AMAP_AXI_WIN(win)	PAB_EXT_REG_ADDR(0xb4a0, win)
 #define PAB_PEX_AMAP_AXI_WIN(win)	PAB_REG_ADDR(0x4ba4, win)
 #define PAB_PEX_AMAP_PEX_WIN_L(win)	PAB_REG_ADDR(0x4ba8, win)
 #define PAB_PEX_AMAP_PEX_WIN_H(win)	PAB_REG_ADDR(0x4bac, win)
@@ -455,49 +461,51 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie)
 }
 
 static void program_ib_windows(struct mobiveil_pcie *pcie, int win_num,
-			       int pci_addr, u32 type, u64 size)
+			       u64 cpu_addr, u64 pci_addr, u32 type, u64 size)
 {
-	int pio_ctrl_val;
-	int amap_ctrl_dw;
+	u32 value;
 	u64 size64 = ~(size - 1);
 
-	if ((pcie->ib_wins_configured + 1) > pcie->ppio_wins) {
+	if (win_num >= pcie->ppio_wins) {
 		dev_err(&pcie->pdev->dev,
 			"ERROR: max inbound windows reached !\n");
 		return;
 	}
 
-	pio_ctrl_val = csr_readl(pcie, PAB_PEX_PIO_CTRL);
-	pio_ctrl_val |= 1 << PIO_ENABLE_SHIFT;
-	csr_writel(pcie, pio_ctrl_val, PAB_PEX_PIO_CTRL);
-
-	amap_ctrl_dw = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
-	amap_ctrl_dw |= (type << AMAP_CTRL_TYPE_SHIFT) |
-			(1 << AMAP_CTRL_EN_SHIFT) |
-			lower_32_bits(size64);
-	csr_writel(pcie, amap_ctrl_dw, PAB_PEX_AMAP_CTRL(win_num));
+	value = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
+	value &= ~(AMAP_CTRL_TYPE_MASK << AMAP_CTRL_TYPE_SHIFT |
+		 WIN_SIZE_MASK << WIN_SIZE_SHIFT);
+	value |= (type << AMAP_CTRL_TYPE_SHIFT) | (1 << AMAP_CTRL_EN_SHIFT) |
+		 (lower_32_bits(size64) & WIN_SIZE_MASK << WIN_SIZE_SHIFT);
+	csr_writel(pcie, value, PAB_PEX_AMAP_CTRL(win_num));
 
 	csr_writel(pcie, upper_32_bits(size64),
 		   PAB_EXT_PEX_AMAP_SIZEN(win_num));
 
-	csr_writel(pcie, pci_addr, PAB_PEX_AMAP_AXI_WIN(win_num));
+	csr_writel(pcie, lower_32_bits(cpu_addr),
+		   PAB_PEX_AMAP_AXI_WIN(win_num));
+	csr_writel(pcie, upper_32_bits(cpu_addr),
+		   PAB_EXT_PEX_AMAP_AXI_WIN(win_num));
+
+	csr_writel(pcie, lower_32_bits(pci_addr),
+		   PAB_PEX_AMAP_PEX_WIN_L(win_num));
+	csr_writel(pcie, upper_32_bits(pci_addr),
+		   PAB_PEX_AMAP_PEX_WIN_H(win_num));
 
-	csr_writel(pcie, pci_addr, PAB_PEX_AMAP_PEX_WIN_L(win_num));
-	csr_writel(pcie, 0, PAB_PEX_AMAP_PEX_WIN_H(win_num));
+	pcie->ib_wins_configured++;
 }
 
 /*
  * routine to program the outbound windows
  */
 static void program_ob_windows(struct mobiveil_pcie *pcie, int win_num,
-			       u64 cpu_addr, u64 pci_addr,
-			       u32 config_io_bit, u64 size)
+			       u64 cpu_addr, u64 pci_addr, u32 type, u64 size)
 {
 
-	u32 value, type;
+	u32 value;
 	u64 size64 = ~(size - 1);
 
-	if ((pcie->ob_wins_configured + 1) > pcie->apio_wins) {
+	if (win_num >= pcie->apio_wins) {
 		dev_err(&pcie->pdev->dev,
 			"ERROR: max outbound windows reached !\n");
 		return;
@@ -507,10 +515,12 @@ static void program_ob_windows(struct mobiveil_pcie *pcie, int win_num,
 	 * program Enable Bit to 1, Type Bit to (00) base 2, AXI Window Size Bit
 	 * to 4 KB in PAB_AXI_AMAP_CTRL register
 	 */
-	type = config_io_bit;
 	value = csr_readl(pcie, PAB_AXI_AMAP_CTRL(win_num));
-	csr_writel(pcie, 1 << WIN_ENABLE_SHIFT | type << WIN_TYPE_SHIFT |
-		   lower_32_bits(size64), PAB_AXI_AMAP_CTRL(win_num));
+	value &= ~(WIN_TYPE_MASK << WIN_TYPE_SHIFT |
+		 WIN_SIZE_MASK << WIN_SIZE_SHIFT);
+	value |= 1 << WIN_ENABLE_SHIFT | type << WIN_TYPE_SHIFT |
+		 (lower_32_bits(size64) & WIN_SIZE_MASK << WIN_SIZE_SHIFT);
+	csr_writel(pcie, value, PAB_AXI_AMAP_CTRL(win_num));
 
 	csr_writel(pcie, upper_32_bits(size64), PAB_EXT_AXI_AMAP_SIZE(win_num));
 
@@ -518,11 +528,10 @@ static void program_ob_windows(struct mobiveil_pcie *pcie, int win_num,
 	 * program AXI window base with appropriate value in
 	 * PAB_AXI_AMAP_AXI_WIN0 register
 	 */
-	value = csr_readl(pcie, PAB_AXI_AMAP_AXI_WIN(win_num));
-	csr_writel(pcie, cpu_addr & (~AXI_WINDOW_ALIGN_MASK),
+	csr_writel(pcie, lower_32_bits(cpu_addr) & (~AXI_WINDOW_ALIGN_MASK),
 		   PAB_AXI_AMAP_AXI_WIN(win_num));
-
-	value = csr_readl(pcie, PAB_AXI_AMAP_PEX_WIN_H(win_num));
+	csr_writel(pcie, upper_32_bits(cpu_addr),
+		   PAB_EXT_AXI_AMAP_AXI_WIN(win_num));
 
 	csr_writel(pcie, lower_32_bits(pci_addr),
 		   PAB_AXI_AMAP_PEX_WIN_L(win_num));
@@ -604,6 +613,11 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
 	value |= APIO_EN_MASK;
 	csr_writel(pcie, value, PAB_AXI_PIO_CTRL);
 
+	/* Enable PCIe PIO master */
+	value = csr_readl(pcie, PAB_PEX_PIO_CTRL);
+	value |= 1 << PIO_ENABLE_SHIFT;
+	csr_writel(pcie, value, PAB_PEX_PIO_CTRL);
+
 	/*
 	 * we'll program one outbound window for config reads and
 	 * another default inbound window for all the upstream traffic
@@ -616,7 +630,7 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
 			   CFG_WINDOW_TYPE, resource_size(pcie->ob_io_res));
 
 	/* memory inbound translation window */
-	program_ib_windows(pcie, WIN_NUM_0, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE);
+	program_ib_windows(pcie, WIN_NUM_0, 0, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE);
 
 	/* Get the I/O and memory ranges from DT */
 	resource_list_for_each_entry(win, &pcie->resources) {
-- 
2.17.1


^ permalink raw reply	[flat|nested] 67+ messages in thread

* [PATCHv5 10/20] PCI: mobiveil: Fix the INTx process errors
  2019-04-12  8:35 [PATCHv5 00/20] PCI: mobiveil: fixes for Mobiveil PCIe Host Bridge IP driver Z.q. Hou
                   ` (8 preceding siblings ...)
  2019-04-12  8:36 ` [PATCHv5 09/20] PCI: mobiveil: Correct inbound/outbound window setup routines Z.q. Hou
@ 2019-04-12  8:36 ` Z.q. Hou
  2019-06-12 15:08   ` Lorenzo Pieralisi
  2019-06-28 17:05   ` Lorenzo Pieralisi
  2019-04-12  8:36 ` [PATCHv5 11/20] PCI: mobiveil: Correct the fixup of Class Code field Z.q. Hou
                   ` (10 subsequent siblings)
  20 siblings, 2 replies; 67+ messages in thread
From: Z.q. Hou @ 2019-04-12  8:36 UTC (permalink / raw)
  To: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	lorenzo.pieralisi, catalin.marinas, will.deacon
  Cc: Mingkai Hu, M.h. Lian, Xiaowei Bao, Z.q. Hou

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

In the loop block, there is not code to update the loop key,
this patch updates the loop key by re-read the INTx status
register.

This patch also add the clearing of the handled INTx status.

Note: Need MV to test this fix.

Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver")
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
---
V5:
 - Corrected and retouched the subject and changelog.

 drivers/pci/controller/pcie-mobiveil.c | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c
index 4ba458474e42..78e575e71f4d 100644
--- a/drivers/pci/controller/pcie-mobiveil.c
+++ b/drivers/pci/controller/pcie-mobiveil.c
@@ -361,6 +361,7 @@ static void mobiveil_pcie_isr(struct irq_desc *desc)
 	/* Handle INTx */
 	if (intr_status & PAB_INTP_INTX_MASK) {
 		shifted_status = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT);
+		shifted_status &= PAB_INTP_INTX_MASK;
 		shifted_status >>= PAB_INTX_START;
 		do {
 			for_each_set_bit(bit, &shifted_status, PCI_NUM_INTX) {
@@ -372,12 +373,16 @@ static void mobiveil_pcie_isr(struct irq_desc *desc)
 					dev_err_ratelimited(dev, "unexpected IRQ, INT%d\n",
 							    bit);
 
-				/* clear interrupt */
-				csr_writel(pcie,
-					   shifted_status << PAB_INTX_START,
+				/* clear interrupt handled */
+				csr_writel(pcie, 1 << (PAB_INTX_START + bit),
 					   PAB_INTP_AMBA_MISC_STAT);
 			}
-		} while ((shifted_status >> PAB_INTX_START) != 0);
+
+			shifted_status = csr_readl(pcie,
+						   PAB_INTP_AMBA_MISC_STAT);
+			shifted_status &= PAB_INTP_INTX_MASK;
+			shifted_status >>= PAB_INTX_START;
+		} while (shifted_status != 0);
 	}
 
 	/* read extra MSI status register */
-- 
2.17.1


^ permalink raw reply	[flat|nested] 67+ messages in thread

* [PATCHv5 11/20] PCI: mobiveil: Correct the fixup of Class Code field
  2019-04-12  8:35 [PATCHv5 00/20] PCI: mobiveil: fixes for Mobiveil PCIe Host Bridge IP driver Z.q. Hou
                   ` (9 preceding siblings ...)
  2019-04-12  8:36 ` [PATCHv5 10/20] PCI: mobiveil: Fix the INTx process errors Z.q. Hou
@ 2019-04-12  8:36 ` Z.q. Hou
  2019-04-12  8:36 ` [PATCHv5 12/20] PCI: mobiveil: Move the link up waiting out of mobiveil_host_init() Z.q. Hou
                   ` (9 subsequent siblings)
  20 siblings, 0 replies; 67+ messages in thread
From: Z.q. Hou @ 2019-04-12  8:36 UTC (permalink / raw)
  To: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	lorenzo.pieralisi, catalin.marinas, will.deacon
  Cc: Mingkai Hu, M.h. Lian, Xiaowei Bao, Z.q. Hou

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Only fix up the Class Code field to PCI bridge, do not change the
Revision ID. And this patch also move the Class Code fixup to
function mobiveil_host_init().

Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver")
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
---
V5:
 - Corrected and retouched the subject and changelog.

 drivers/pci/controller/pcie-mobiveil.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c
index 78e575e71f4d..8eee1ab7ee24 100644
--- a/drivers/pci/controller/pcie-mobiveil.c
+++ b/drivers/pci/controller/pcie-mobiveil.c
@@ -653,6 +653,12 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
 				   type, resource_size(win->res));
 	}
 
+	/* fixup for PCIe class register */
+	value = csr_readl(pcie, PAB_INTP_AXI_PIO_CLASS);
+	value &= 0xff;
+	value |= (PCI_CLASS_BRIDGE_PCI << 16);
+	csr_writel(pcie, value, PAB_INTP_AXI_PIO_CLASS);
+
 	/* setup MSI hardware registers */
 	mobiveil_pcie_enable_msi(pcie);
 
@@ -896,9 +902,6 @@ static int mobiveil_pcie_probe(struct platform_device *pdev)
 		goto error;
 	}
 
-	/* fixup for PCIe class register */
-	csr_writel(pcie, 0x060402ab, PAB_INTP_AXI_PIO_CLASS);
-
 	/* initialize the IRQ domains */
 	ret = mobiveil_pcie_init_irq_domain(pcie);
 	if (ret) {
-- 
2.17.1


^ permalink raw reply	[flat|nested] 67+ messages in thread

* [PATCHv5 12/20] PCI: mobiveil: Move the link up waiting out of mobiveil_host_init()
  2019-04-12  8:35 [PATCHv5 00/20] PCI: mobiveil: fixes for Mobiveil PCIe Host Bridge IP driver Z.q. Hou
                   ` (10 preceding siblings ...)
  2019-04-12  8:36 ` [PATCHv5 11/20] PCI: mobiveil: Correct the fixup of Class Code field Z.q. Hou
@ 2019-04-12  8:36 ` Z.q. Hou
  2019-04-12  8:36 ` [PATCHv5 13/20] PCI: mobiveil: Move IRQ chained handler setup out of DT parse Z.q. Hou
                   ` (8 subsequent siblings)
  20 siblings, 0 replies; 67+ messages in thread
From: Z.q. Hou @ 2019-04-12  8:36 UTC (permalink / raw)
  To: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	lorenzo.pieralisi, catalin.marinas, will.deacon
  Cc: Mingkai Hu, M.h. Lian, Xiaowei Bao, Z.q. Hou

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

The host initialize sequence does not depend on PCIe link up,
so move it to the place just before the enumeration.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
---
V5:
 - Corrected and retouched the subject and changelog.

 drivers/pci/controller/pcie-mobiveil.c | 15 +++++++--------
 1 file changed, 7 insertions(+), 8 deletions(-)

diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c
index 8eee1ab7ee24..c2848c22b466 100644
--- a/drivers/pci/controller/pcie-mobiveil.c
+++ b/drivers/pci/controller/pcie-mobiveil.c
@@ -582,15 +582,8 @@ static void mobiveil_pcie_enable_msi(struct mobiveil_pcie *pcie)
 static int mobiveil_host_init(struct mobiveil_pcie *pcie)
 {
 	u32 value, pab_ctrl, type;
-	int err;
 	struct resource_entry *win;
 
-	err = mobiveil_bringup_link(pcie);
-	if (err) {
-		dev_info(&pcie->pdev->dev, "link bring-up failed\n");
-		return err;
-	}
-
 	/*
 	 * program Bus Master Enable Bit in Command Register in PAB Config
 	 * Space
@@ -662,7 +655,7 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
 	/* setup MSI hardware registers */
 	mobiveil_pcie_enable_msi(pcie);
 
-	return err;
+	return 0;
 }
 
 static void mobiveil_mask_intx_irq(struct irq_data *data)
@@ -922,6 +915,12 @@ static int mobiveil_pcie_probe(struct platform_device *pdev)
 	bridge->map_irq = of_irq_parse_and_map_pci;
 	bridge->swizzle_irq = pci_common_swizzle;
 
+	ret = mobiveil_bringup_link(pcie);
+	if (ret) {
+		dev_info(dev, "link bring-up failed\n");
+		goto error;
+	}
+
 	/* setup the kernel resources for the newly added PCIe root bus */
 	ret = pci_scan_root_bus_bridge(bridge);
 	if (ret)
-- 
2.17.1


^ permalink raw reply	[flat|nested] 67+ messages in thread

* [PATCHv5 13/20] PCI: mobiveil: Move IRQ chained handler setup out of DT parse
  2019-04-12  8:35 [PATCHv5 00/20] PCI: mobiveil: fixes for Mobiveil PCIe Host Bridge IP driver Z.q. Hou
                   ` (11 preceding siblings ...)
  2019-04-12  8:36 ` [PATCHv5 12/20] PCI: mobiveil: Move the link up waiting out of mobiveil_host_init() Z.q. Hou
@ 2019-04-12  8:36 ` Z.q. Hou
  2019-04-12  8:36 ` [PATCHv5 14/20] PCI: mobiveil: Initialize Primary/Secondary/Subordinate bus numbers Z.q. Hou
                   ` (7 subsequent siblings)
  20 siblings, 0 replies; 67+ messages in thread
From: Z.q. Hou @ 2019-04-12  8:36 UTC (permalink / raw)
  To: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	lorenzo.pieralisi, catalin.marinas, will.deacon
  Cc: Mingkai Hu, M.h. Lian, Xiaowei Bao, Z.q. Hou

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Move irq_set_chained_handler_and_data() out of DT parse function.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
---
V5:
 - Corrected the subject.

 drivers/pci/controller/pcie-mobiveil.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c
index c2848c22b466..db7ecb021c63 100644
--- a/drivers/pci/controller/pcie-mobiveil.c
+++ b/drivers/pci/controller/pcie-mobiveil.c
@@ -460,8 +460,6 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie)
 		return -ENODEV;
 	}
 
-	irq_set_chained_handler_and_data(pcie->irq, mobiveil_pcie_isr, pcie);
-
 	return 0;
 }
 
@@ -902,6 +900,8 @@ static int mobiveil_pcie_probe(struct platform_device *pdev)
 		goto error;
 	}
 
+	irq_set_chained_handler_and_data(pcie->irq, mobiveil_pcie_isr, pcie);
+
 	ret = devm_request_pci_bus_resources(dev, &pcie->resources);
 	if (ret)
 		goto error;
-- 
2.17.1


^ permalink raw reply	[flat|nested] 67+ messages in thread

* [PATCHv5 14/20] PCI: mobiveil: Initialize Primary/Secondary/Subordinate bus numbers
  2019-04-12  8:35 [PATCHv5 00/20] PCI: mobiveil: fixes for Mobiveil PCIe Host Bridge IP driver Z.q. Hou
                   ` (12 preceding siblings ...)
  2019-04-12  8:36 ` [PATCHv5 13/20] PCI: mobiveil: Move IRQ chained handler setup out of DT parse Z.q. Hou
@ 2019-04-12  8:36 ` Z.q. Hou
  2019-04-12  8:36 ` [PATCHv5 15/20] PCI: mobiveil: Fix the checking of valid device Z.q. Hou
                   ` (6 subsequent siblings)
  20 siblings, 0 replies; 67+ messages in thread
From: Z.q. Hou @ 2019-04-12  8:36 UTC (permalink / raw)
  To: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	lorenzo.pieralisi, catalin.marinas, will.deacon
  Cc: Mingkai Hu, M.h. Lian, Xiaowei Bao, Z.q. Hou

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

The reset value of Primary, Secondary and Subordinate bus numbers is
zero, so set a workable value for these 3 bus numbers.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
---
V5:
 - Corrected and retouched the subject and changelog.

 drivers/pci/controller/pcie-mobiveil.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c
index db7ecb021c63..9210165fe8c0 100644
--- a/drivers/pci/controller/pcie-mobiveil.c
+++ b/drivers/pci/controller/pcie-mobiveil.c
@@ -582,6 +582,12 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
 	u32 value, pab_ctrl, type;
 	struct resource_entry *win;
 
+	/* setup bus numbers */
+	value = csr_readl(pcie, PCI_PRIMARY_BUS);
+	value &= 0xff000000;
+	value |= 0x00ff0100;
+	csr_writel(pcie, value, PCI_PRIMARY_BUS);
+
 	/*
 	 * program Bus Master Enable Bit in Command Register in PAB Config
 	 * Space
-- 
2.17.1


^ permalink raw reply	[flat|nested] 67+ messages in thread

* [PATCHv5 15/20] PCI: mobiveil: Fix the checking of valid device
  2019-04-12  8:35 [PATCHv5 00/20] PCI: mobiveil: fixes for Mobiveil PCIe Host Bridge IP driver Z.q. Hou
                   ` (13 preceding siblings ...)
  2019-04-12  8:36 ` [PATCHv5 14/20] PCI: mobiveil: Initialize Primary/Secondary/Subordinate bus numbers Z.q. Hou
@ 2019-04-12  8:36 ` Z.q. Hou
  2019-04-12  8:36 ` [PATCHv5 16/20] PCI: mobiveil: Add link up condition check Z.q. Hou
                   ` (5 subsequent siblings)
  20 siblings, 0 replies; 67+ messages in thread
From: Z.q. Hou @ 2019-04-12  8:36 UTC (permalink / raw)
  To: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	lorenzo.pieralisi, catalin.marinas, will.deacon
  Cc: Mingkai Hu, M.h. Lian, Xiaowei Bao, Z.q. Hou

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Allow CFG transactions to all functions of Endpoint implemented
multiple functions.

Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver")
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
---
V5:
 - Corrected and retouched the subject and changelog.

 drivers/pci/controller/pcie-mobiveil.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c
index 9210165fe8c0..621852078caf 100644
--- a/drivers/pci/controller/pcie-mobiveil.c
+++ b/drivers/pci/controller/pcie-mobiveil.c
@@ -291,7 +291,7 @@ static bool mobiveil_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
 	 * Do not read more than one device on the bus directly
 	 * attached to RC
 	 */
-	if ((bus->primary == pcie->root_bus_nr) && (devfn > 0))
+	if ((bus->primary == pcie->root_bus_nr) && (PCI_SLOT(devfn) > 0))
 		return false;
 
 	return true;
-- 
2.17.1


^ permalink raw reply	[flat|nested] 67+ messages in thread

* [PATCHv5 16/20] PCI: mobiveil: Add link up condition check
  2019-04-12  8:35 [PATCHv5 00/20] PCI: mobiveil: fixes for Mobiveil PCIe Host Bridge IP driver Z.q. Hou
                   ` (14 preceding siblings ...)
  2019-04-12  8:36 ` [PATCHv5 15/20] PCI: mobiveil: Fix the checking of valid device Z.q. Hou
@ 2019-04-12  8:36 ` Z.q. Hou
  2019-06-11 17:17   ` Lorenzo Pieralisi
  2019-04-12  8:36 ` [PATCHv5 17/20] PCI: mobiveil: Complete initialization of host even if no PCIe link Z.q. Hou
                   ` (4 subsequent siblings)
  20 siblings, 1 reply; 67+ messages in thread
From: Z.q. Hou @ 2019-04-12  8:36 UTC (permalink / raw)
  To: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	lorenzo.pieralisi, catalin.marinas, will.deacon
  Cc: Mingkai Hu, M.h. Lian, Xiaowei Bao, Z.q. Hou

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Avoid to issue CFG transactions to link partner when the PCIe
link is not up.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V5:
 - Corrected the subject.

 drivers/pci/controller/pcie-mobiveil.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c
index 621852078caf..1ee3ea2570c0 100644
--- a/drivers/pci/controller/pcie-mobiveil.c
+++ b/drivers/pci/controller/pcie-mobiveil.c
@@ -283,6 +283,10 @@ static bool mobiveil_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
 {
 	struct mobiveil_pcie *pcie = bus->sysdata;
 
+	/* If there is no link, then there is no device */
+	if (bus->number > pcie->root_bus_nr && !mobiveil_pcie_link_up(pcie))
+		return false;
+
 	/* Only one device down on each root port */
 	if ((bus->number == pcie->root_bus_nr) && (devfn > 0))
 		return false;
-- 
2.17.1


^ permalink raw reply	[flat|nested] 67+ messages in thread

* [PATCHv5 17/20] PCI: mobiveil: Complete initialization of host even if no PCIe link
  2019-04-12  8:35 [PATCHv5 00/20] PCI: mobiveil: fixes for Mobiveil PCIe Host Bridge IP driver Z.q. Hou
                   ` (15 preceding siblings ...)
  2019-04-12  8:36 ` [PATCHv5 16/20] PCI: mobiveil: Add link up condition check Z.q. Hou
@ 2019-04-12  8:36 ` Z.q. Hou
  2019-06-12 14:34   ` Lorenzo Pieralisi
  2019-04-12  8:37 ` [PATCHv5 18/20] PCI: mobiveil: Disable IB and OB windows set by bootloader Z.q. Hou
                   ` (3 subsequent siblings)
  20 siblings, 1 reply; 67+ messages in thread
From: Z.q. Hou @ 2019-04-12  8:36 UTC (permalink / raw)
  To: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	lorenzo.pieralisi, catalin.marinas, will.deacon
  Cc: Mingkai Hu, M.h. Lian, Xiaowei Bao, Z.q. Hou

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Sometimes there is not a PCIe Endpoint stalled in the slot,
so do not exit when the PCIe link is not up. And degrade the
print level of link up info.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
---
V5:
 - Corrected and retouched the subject and changelog.

 drivers/pci/controller/pcie-mobiveil.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c
index 1ee3ea2570c0..8dc87c7a600e 100644
--- a/drivers/pci/controller/pcie-mobiveil.c
+++ b/drivers/pci/controller/pcie-mobiveil.c
@@ -560,7 +560,7 @@ static int mobiveil_bringup_link(struct mobiveil_pcie *pcie)
 		usleep_range(LINK_WAIT_MIN, LINK_WAIT_MAX);
 	}
 
-	dev_err(&pcie->pdev->dev, "link never came up\n");
+	dev_info(&pcie->pdev->dev, "link never came up\n");
 
 	return -ETIMEDOUT;
 }
@@ -926,10 +926,8 @@ static int mobiveil_pcie_probe(struct platform_device *pdev)
 	bridge->swizzle_irq = pci_common_swizzle;
 
 	ret = mobiveil_bringup_link(pcie);
-	if (ret) {
+	if (ret)
 		dev_info(dev, "link bring-up failed\n");
-		goto error;
-	}
 
 	/* setup the kernel resources for the newly added PCIe root bus */
 	ret = pci_scan_root_bus_bridge(bridge);
-- 
2.17.1


^ permalink raw reply	[flat|nested] 67+ messages in thread

* [PATCHv5 18/20] PCI: mobiveil: Disable IB and OB windows set by bootloader
  2019-04-12  8:35 [PATCHv5 00/20] PCI: mobiveil: fixes for Mobiveil PCIe Host Bridge IP driver Z.q. Hou
                   ` (16 preceding siblings ...)
  2019-04-12  8:36 ` [PATCHv5 17/20] PCI: mobiveil: Complete initialization of host even if no PCIe link Z.q. Hou
@ 2019-04-12  8:37 ` Z.q. Hou
  2019-06-12 16:23   ` Lorenzo Pieralisi
  2019-04-12  8:37 ` [PATCHv5 19/20] PCI: mobiveil: Add 8-bit and 16-bit register accessors Z.q. Hou
                   ` (2 subsequent siblings)
  20 siblings, 1 reply; 67+ messages in thread
From: Z.q. Hou @ 2019-04-12  8:37 UTC (permalink / raw)
  To: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	lorenzo.pieralisi, catalin.marinas, will.deacon
  Cc: Mingkai Hu, M.h. Lian, Xiaowei Bao, Z.q. Hou

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Disable all inbound and outbound windows before set up the windows
in kernel, in case transactions match the window set by bootloader.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
---
V5:
 - No functionality change.

 drivers/pci/controller/pcie-mobiveil.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c
index 8dc87c7a600e..411e9779da12 100644
--- a/drivers/pci/controller/pcie-mobiveil.c
+++ b/drivers/pci/controller/pcie-mobiveil.c
@@ -565,6 +565,24 @@ static int mobiveil_bringup_link(struct mobiveil_pcie *pcie)
 	return -ETIMEDOUT;
 }
 
+static void mobiveil_pcie_disable_ib_win(struct mobiveil_pcie *pcie, int idx)
+{
+	u32 val;
+
+	val = csr_readl(pcie, PAB_PEX_AMAP_CTRL(idx));
+	val &= ~(1 << AMAP_CTRL_EN_SHIFT);
+	csr_writel(pcie, val, PAB_PEX_AMAP_CTRL(idx));
+}
+
+static void mobiveil_pcie_disable_ob_win(struct mobiveil_pcie *pcie, int idx)
+{
+	u32 val;
+
+	val = csr_readl(pcie, PAB_AXI_AMAP_CTRL(idx));
+	val &= ~(1 << WIN_ENABLE_SHIFT);
+	csr_writel(pcie, val, PAB_AXI_AMAP_CTRL(idx));
+}
+
 static void mobiveil_pcie_enable_msi(struct mobiveil_pcie *pcie)
 {
 	phys_addr_t msg_addr = pcie->pcie_reg_base;
@@ -585,6 +603,13 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
 {
 	u32 value, pab_ctrl, type;
 	struct resource_entry *win;
+	int i;
+
+	/* Disable all inbound/outbound windows */
+	for (i = 0; i < pcie->apio_wins; i++)
+		mobiveil_pcie_disable_ob_win(pcie, i);
+	for (i = 0; i < pcie->ppio_wins; i++)
+		mobiveil_pcie_disable_ib_win(pcie, i);
 
 	/* setup bus numbers */
 	value = csr_readl(pcie, PCI_PRIMARY_BUS);
-- 
2.17.1


^ permalink raw reply	[flat|nested] 67+ messages in thread

* [PATCHv5 19/20] PCI: mobiveil: Add 8-bit and 16-bit register accessors
  2019-04-12  8:35 [PATCHv5 00/20] PCI: mobiveil: fixes for Mobiveil PCIe Host Bridge IP driver Z.q. Hou
                   ` (17 preceding siblings ...)
  2019-04-12  8:37 ` [PATCHv5 18/20] PCI: mobiveil: Disable IB and OB windows set by bootloader Z.q. Hou
@ 2019-04-12  8:37 ` Z.q. Hou
  2019-06-12 13:54   ` Lorenzo Pieralisi
  2019-04-12  8:37 ` [PATCHv5 20/20] dt-bindings: PCI: mobiveil: Change gpio_slave and apb_csr to optional Z.q. Hou
  2019-07-03 10:33 ` [PATCHv5 00/20] PCI: mobiveil: fixes for Mobiveil PCIe Host Bridge IP driver Lorenzo Pieralisi
  20 siblings, 1 reply; 67+ messages in thread
From: Z.q. Hou @ 2019-04-12  8:37 UTC (permalink / raw)
  To: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	lorenzo.pieralisi, catalin.marinas, will.deacon
  Cc: Mingkai Hu, M.h. Lian, Xiaowei Bao, Z.q. Hou

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

There are some 8-bit and 16-bit registers in PCIe
configuration space, so add accessors for them.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
---
V5:
 - Corrected and retouched the subject and changelog.
 - No functionality change.

 drivers/pci/controller/pcie-mobiveil.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c
index 411e9779da12..456adfee393c 100644
--- a/drivers/pci/controller/pcie-mobiveil.c
+++ b/drivers/pci/controller/pcie-mobiveil.c
@@ -268,11 +268,31 @@ static u32 csr_readl(struct mobiveil_pcie *pcie, u32 off)
 	return csr_read(pcie, off, 0x4);
 }
 
+static u32 csr_readw(struct mobiveil_pcie *pcie, u32 off)
+{
+	return csr_read(pcie, off, 0x2);
+}
+
+static u32 csr_readb(struct mobiveil_pcie *pcie, u32 off)
+{
+	return csr_read(pcie, off, 0x1);
+}
+
 static void csr_writel(struct mobiveil_pcie *pcie, u32 val, u32 off)
 {
 	csr_write(pcie, val, off, 0x4);
 }
 
+static void csr_writew(struct mobiveil_pcie *pcie, u32 val, u32 off)
+{
+	csr_write(pcie, val, off, 0x2);
+}
+
+static void csr_writeb(struct mobiveil_pcie *pcie, u32 val, u32 off)
+{
+	csr_write(pcie, val, off, 0x1);
+}
+
 static bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie)
 {
 	return (csr_readl(pcie, LTSSM_STATUS) &
-- 
2.17.1


^ permalink raw reply	[flat|nested] 67+ messages in thread

* [PATCHv5 20/20] dt-bindings: PCI: mobiveil: Change gpio_slave and apb_csr to optional
  2019-04-12  8:35 [PATCHv5 00/20] PCI: mobiveil: fixes for Mobiveil PCIe Host Bridge IP driver Z.q. Hou
                   ` (18 preceding siblings ...)
  2019-04-12  8:37 ` [PATCHv5 19/20] PCI: mobiveil: Add 8-bit and 16-bit register accessors Z.q. Hou
@ 2019-04-12  8:37 ` Z.q. Hou
  2019-07-03 10:33 ` [PATCHv5 00/20] PCI: mobiveil: fixes for Mobiveil PCIe Host Bridge IP driver Lorenzo Pieralisi
  20 siblings, 0 replies; 67+ messages in thread
From: Z.q. Hou @ 2019-04-12  8:37 UTC (permalink / raw)
  To: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	lorenzo.pieralisi, catalin.marinas, will.deacon
  Cc: Mingkai Hu, M.h. Lian, Xiaowei Bao, Z.q. Hou

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Change the "gpio_slave" and "apb_csr" to optional, the "gpio_slave"
is not used in current code, and "apb_csr" is not used by some platforms.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Acked-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
---
V5:
 - Corrected and retouched the subject and changelog.

 Documentation/devicetree/bindings/pci/mobiveil-pcie.txt | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt b/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt
index a618d4787dd7..64156993e052 100644
--- a/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt
@@ -10,8 +10,10 @@ Required properties:
 	interrupt source. The value must be 1.
 - compatible: Should contain "mbvl,gpex40-pcie"
 - reg: Should contain PCIe registers location and length
+	Mandatory:
 	"config_axi_slave": PCIe controller registers
 	"csr_axi_slave"	  : Bridge config registers
+	Optional:
 	"gpio_slave"	  : GPIO registers to control slot power
 	"apb_csr"	  : MSI registers
 
-- 
2.17.1


^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCHv5 04/20] PCI: mobiveil: Remove the flag MSI_FLAG_MULTI_PCI_MSI
  2019-04-12  8:35 ` [PATCHv5 04/20] PCI: mobiveil: Remove the flag MSI_FLAG_MULTI_PCI_MSI Z.q. Hou
@ 2019-06-11 16:59   ` Lorenzo Pieralisi
  2019-06-11 17:29     ` Marc Zyngier
  2019-06-12 11:34     ` Z.q. Hou
  0 siblings, 2 replies; 67+ messages in thread
From: Lorenzo Pieralisi @ 2019-06-11 16:59 UTC (permalink / raw)
  To: Z.q. Hou
  Cc: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	catalin.marinas, will.deacon, Mingkai Hu, M.h. Lian, Xiaowei Bao

On Fri, Apr 12, 2019 at 08:35:36AM +0000, Z.q. Hou wrote:
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> 
> The current code does not support multiple MSIs, so remove
> the corresponding flag from the msi_domain_info structure.

Please explain me what's the problem before removing multi MSI
support.

Thanks,
Lorenzo

> Fixes: 1e913e58335f ("PCI: mobiveil: Add MSI support")
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> ---
> V5:
>  - Corrected the subject.
> 
>  drivers/pci/controller/pcie-mobiveil.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c
> index 563210e731d3..a0dd337c6214 100644
> --- a/drivers/pci/controller/pcie-mobiveil.c
> +++ b/drivers/pci/controller/pcie-mobiveil.c
> @@ -703,7 +703,7 @@ static struct irq_chip mobiveil_msi_irq_chip = {
>  
>  static struct msi_domain_info mobiveil_msi_domain_info = {
>  	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
> -		   MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX),
> +		   MSI_FLAG_PCI_MSIX),
>  	.chip	= &mobiveil_msi_irq_chip,
>  };
>  
> -- 
> 2.17.1
> 

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCHv5 16/20] PCI: mobiveil: Add link up condition check
  2019-04-12  8:36 ` [PATCHv5 16/20] PCI: mobiveil: Add link up condition check Z.q. Hou
@ 2019-06-11 17:17   ` Lorenzo Pieralisi
  2019-06-12 11:36     ` Z.q. Hou
  0 siblings, 1 reply; 67+ messages in thread
From: Lorenzo Pieralisi @ 2019-06-11 17:17 UTC (permalink / raw)
  To: Z.q. Hou, bhelgaas
  Cc: linux-pci, linux-arm-kernel, devicetree, linux-kernel, robh+dt,
	mark.rutland, l.subrahmanya, shawnguo, Leo Li, catalin.marinas,
	will.deacon, Mingkai Hu, M.h. Lian, Xiaowei Bao

NB: Please trim the CC list and keep it to concerned maintainers.

On Fri, Apr 12, 2019 at 08:36:48AM +0000, Z.q. Hou wrote:
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> 
> Avoid to issue CFG transactions to link partner when the PCIe
> link is not up.
> 
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
> V5:
>  - Corrected the subject.
> 
>  drivers/pci/controller/pcie-mobiveil.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c
> index 621852078caf..1ee3ea2570c0 100644
> --- a/drivers/pci/controller/pcie-mobiveil.c
> +++ b/drivers/pci/controller/pcie-mobiveil.c
> @@ -283,6 +283,10 @@ static bool mobiveil_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
>  {
>  	struct mobiveil_pcie *pcie = bus->sysdata;
>  
> +	/* If there is no link, then there is no device */
> +	if (bus->number > pcie->root_bus_nr && !mobiveil_pcie_link_up(pcie))

I think Bjorn mentioned this a million times already, eg:

https://lore.kernel.org/linux-pci/20190411201535.GS256045@google.com/

this is racy and gives a false sense of robustness. We have code in the
kernel that checks the link but adding more seems silly to me, so I am
inclined to drop this patch.

Lorenzo

> +		return false;
> +
>  	/* Only one device down on each root port */
>  	if ((bus->number == pcie->root_bus_nr) && (devfn > 0))
>  		return false;
> -- 
> 2.17.1
> 

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCHv5 04/20] PCI: mobiveil: Remove the flag MSI_FLAG_MULTI_PCI_MSI
  2019-06-11 16:59   ` Lorenzo Pieralisi
@ 2019-06-11 17:29     ` Marc Zyngier
  2019-06-12 10:54       ` Lorenzo Pieralisi
  2019-06-12 11:22       ` Marc Zyngier
  2019-06-12 11:34     ` Z.q. Hou
  1 sibling, 2 replies; 67+ messages in thread
From: Marc Zyngier @ 2019-06-11 17:29 UTC (permalink / raw)
  To: Lorenzo Pieralisi, Z.q. Hou
  Cc: mark.rutland, devicetree, Xiaowei Bao, linux-pci, l.subrahmanya,
	will.deacon, linux-kernel, Leo Li, M.h. Lian, robh+dt,
	Mingkai Hu, catalin.marinas, bhelgaas, shawnguo,
	linux-arm-kernel

On 11/06/2019 17:59, Lorenzo Pieralisi wrote:
> On Fri, Apr 12, 2019 at 08:35:36AM +0000, Z.q. Hou wrote:
>> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
>>
>> The current code does not support multiple MSIs, so remove
>> the corresponding flag from the msi_domain_info structure.
> 
> Please explain me what's the problem before removing multi MSI
> support.

The reason seems to be the following code in the allocator:

        WARN_ON(nr_irqs != 1);
        mutex_lock(&msi->lock);

        bit = find_first_zero_bit(msi->msi_irq_in_use, msi->num_of_vectors);
        if (bit >= msi->num_of_vectors) {
                mutex_unlock(&msi->lock);
                return -ENOSPC;
        }

        set_bit(bit, msi->msi_irq_in_use);

So instead of fixing the allocator, the author prefers disabling
the feature. I'm not sure whether that is an acceptable outcome...

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCHv5 04/20] PCI: mobiveil: Remove the flag MSI_FLAG_MULTI_PCI_MSI
  2019-06-11 17:29     ` Marc Zyngier
@ 2019-06-12 10:54       ` Lorenzo Pieralisi
  2019-06-12 11:22       ` Marc Zyngier
  1 sibling, 0 replies; 67+ messages in thread
From: Lorenzo Pieralisi @ 2019-06-12 10:54 UTC (permalink / raw)
  To: Marc Zyngier
  Cc: Z.q. Hou, mark.rutland, devicetree, Xiaowei Bao, linux-pci,
	l.subrahmanya, will.deacon, linux-kernel, Leo Li, M.h. Lian,
	robh+dt, Mingkai Hu, catalin.marinas, bhelgaas, shawnguo,
	linux-arm-kernel

On Tue, Jun 11, 2019 at 06:29:49PM +0100, Marc Zyngier wrote:
> On 11/06/2019 17:59, Lorenzo Pieralisi wrote:
> > On Fri, Apr 12, 2019 at 08:35:36AM +0000, Z.q. Hou wrote:
> >> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> >>
> >> The current code does not support multiple MSIs, so remove
> >> the corresponding flag from the msi_domain_info structure.
> > 
> > Please explain me what's the problem before removing multi MSI
> > support.
> 
> The reason seems to be the following code in the allocator:
> 
>         WARN_ON(nr_irqs != 1);
>         mutex_lock(&msi->lock);
> 
>         bit = find_first_zero_bit(msi->msi_irq_in_use, msi->num_of_vectors);
>         if (bit >= msi->num_of_vectors) {
>                 mutex_unlock(&msi->lock);
>                 return -ENOSPC;
>         }
> 
>         set_bit(bit, msi->msi_irq_in_use);
> 
> So instead of fixing the allocator, the author prefers disabling
> the feature. I'm not sure whether that is an acceptable outcome...

:) No it is not that's why I asked and I am waiting for an answer.

Lorenzo

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCHv5 04/20] PCI: mobiveil: Remove the flag MSI_FLAG_MULTI_PCI_MSI
  2019-06-11 17:29     ` Marc Zyngier
  2019-06-12 10:54       ` Lorenzo Pieralisi
@ 2019-06-12 11:22       ` Marc Zyngier
  1 sibling, 0 replies; 67+ messages in thread
From: Marc Zyngier @ 2019-06-12 11:22 UTC (permalink / raw)
  To: Lorenzo Pieralisi, Z.q. Hou
  Cc: mark.rutland, devicetree, Xiaowei Bao, linux-pci, l.subrahmanya,
	will.deacon, linux-kernel, Leo Li, M.h. Lian, robh+dt,
	Mingkai Hu, catalin.marinas, bhelgaas, shawnguo,
	linux-arm-kernel

On Tue, 11 Jun 2019 18:29:49 +0100,
Marc Zyngier <marc.zyngier@arm.com> wrote:
> 
> On 11/06/2019 17:59, Lorenzo Pieralisi wrote:
> > On Fri, Apr 12, 2019 at 08:35:36AM +0000, Z.q. Hou wrote:
> >> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> >>
> >> The current code does not support multiple MSIs, so remove
> >> the corresponding flag from the msi_domain_info structure.
> > 
> > Please explain me what's the problem before removing multi MSI
> > support.
> 
> The reason seems to be the following code in the allocator:
> 
>         WARN_ON(nr_irqs != 1);
>         mutex_lock(&msi->lock);
> 
>         bit = find_first_zero_bit(msi->msi_irq_in_use, msi->num_of_vectors);
>         if (bit >= msi->num_of_vectors) {
>                 mutex_unlock(&msi->lock);
>                 return -ENOSPC;
>         }
> 
>         set_bit(bit, msi->msi_irq_in_use);
> 
> So instead of fixing the allocator, the author prefers disabling
> the feature. I'm not sure whether that is an acceptable outcome...

Actually, there is a much deeper issue, and the compose_msi_msg
callback gives a clue:

  phys_addr_t addr = pcie->pcie_reg_base + (data->hwirq * sizeof(int));

This thing is using a separate target address per MSI, which is the
killer argument. Bad hardware...

Thanks,

	M.

-- 
Jazz is not dead, it just smells funny.

^ permalink raw reply	[flat|nested] 67+ messages in thread

* RE: [PATCHv5 04/20] PCI: mobiveil: Remove the flag MSI_FLAG_MULTI_PCI_MSI
  2019-06-11 16:59   ` Lorenzo Pieralisi
  2019-06-11 17:29     ` Marc Zyngier
@ 2019-06-12 11:34     ` Z.q. Hou
  2019-06-12 13:08       ` Lorenzo Pieralisi
  1 sibling, 1 reply; 67+ messages in thread
From: Z.q. Hou @ 2019-06-12 11:34 UTC (permalink / raw)
  To: Lorenzo Pieralisi
  Cc: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	catalin.marinas, will.deacon, Mingkai Hu, M.h. Lian, Xiaowei Bao

Hi Lorenzo,

Thanks a lot for your comments!

> -----Original Message-----
> From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Sent: 2019年6月12日 1:00
> To: Z.q. Hou <zhiqiang.hou@nxp.com>
> Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> bhelgaas@google.com; robh+dt@kernel.org; mark.rutland@arm.com;
> l.subrahmanya@mobiveil.co.in; shawnguo@kernel.org; Leo Li
> <leoyang.li@nxp.com>; catalin.marinas@arm.com; will.deacon@arm.com;
> Mingkai Hu <mingkai.hu@nxp.com>; M.h. Lian <minghuan.lian@nxp.com>;
> Xiaowei Bao <xiaowei.bao@nxp.com>
> Subject: Re: [PATCHv5 04/20] PCI: mobiveil: Remove the flag
> MSI_FLAG_MULTI_PCI_MSI
> 
> On Fri, Apr 12, 2019 at 08:35:36AM +0000, Z.q. Hou wrote:
> > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> >
> > The current code does not support multiple MSIs, so remove the
> > corresponding flag from the msi_domain_info structure.
> 
> Please explain me what's the problem before removing multi MSI support.

NXP LX2 PCIe use the GIC-ITS instead of Mobiveil IP internal MSI controller,
so, I didn't encounter problem.
Subbu, did you test with Endpoint supporting multi MSI?

Thanks,
Zhiqiang

> 
> Thanks,
> Lorenzo
> 
> > Fixes: 1e913e58335f ("PCI: mobiveil: Add MSI support")
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> > ---
> > V5:
> >  - Corrected the subject.
> >
> >  drivers/pci/controller/pcie-mobiveil.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/pci/controller/pcie-mobiveil.c
> > b/drivers/pci/controller/pcie-mobiveil.c
> > index 563210e731d3..a0dd337c6214 100644
> > --- a/drivers/pci/controller/pcie-mobiveil.c
> > +++ b/drivers/pci/controller/pcie-mobiveil.c
> > @@ -703,7 +703,7 @@ static struct irq_chip mobiveil_msi_irq_chip = {
> >
> >  static struct msi_domain_info mobiveil_msi_domain_info = {
> >  	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS |
> MSI_FLAG_USE_DEF_CHIP_OPS |
> > -		   MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX),
> > +		   MSI_FLAG_PCI_MSIX),
> >  	.chip	= &mobiveil_msi_irq_chip,
> >  };
> >
> > --
> > 2.17.1
> >

^ permalink raw reply	[flat|nested] 67+ messages in thread

* RE: [PATCHv5 16/20] PCI: mobiveil: Add link up condition check
  2019-06-11 17:17   ` Lorenzo Pieralisi
@ 2019-06-12 11:36     ` Z.q. Hou
  0 siblings, 0 replies; 67+ messages in thread
From: Z.q. Hou @ 2019-06-12 11:36 UTC (permalink / raw)
  To: Lorenzo Pieralisi, bhelgaas
  Cc: linux-pci, linux-arm-kernel, devicetree, linux-kernel, robh+dt,
	mark.rutland, l.subrahmanya, shawnguo, Leo Li, catalin.marinas,
	will.deacon, Mingkai Hu, M.h. Lian, Xiaowei Bao

Hi Lorenzo,

Thanks a lot for your comments!

> -----Original Message-----
> From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Sent: 2019年6月12日 1:18
> To: Z.q. Hou <zhiqiang.hou@nxp.com>; bhelgaas@google.com
> Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> robh+dt@kernel.org; mark.rutland@arm.com; l.subrahmanya@mobiveil.co.in;
> shawnguo@kernel.org; Leo Li <leoyang.li@nxp.com>;
> catalin.marinas@arm.com; will.deacon@arm.com; Mingkai Hu
> <mingkai.hu@nxp.com>; M.h. Lian <minghuan.lian@nxp.com>; Xiaowei Bao
> <xiaowei.bao@nxp.com>
> Subject: Re: [PATCHv5 16/20] PCI: mobiveil: Add link up condition check
> 
> NB: Please trim the CC list and keep it to concerned maintainers.
> 
> On Fri, Apr 12, 2019 at 08:36:48AM +0000, Z.q. Hou wrote:
> > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> >
> > Avoid to issue CFG transactions to link partner when the PCIe link is
> > not up.
> >
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > ---
> > V5:
> >  - Corrected the subject.
> >
> >  drivers/pci/controller/pcie-mobiveil.c | 4 ++++
> >  1 file changed, 4 insertions(+)
> >
> > diff --git a/drivers/pci/controller/pcie-mobiveil.c
> > b/drivers/pci/controller/pcie-mobiveil.c
> > index 621852078caf..1ee3ea2570c0 100644
> > --- a/drivers/pci/controller/pcie-mobiveil.c
> > +++ b/drivers/pci/controller/pcie-mobiveil.c
> > @@ -283,6 +283,10 @@ static bool mobiveil_pcie_valid_device(struct
> > pci_bus *bus, unsigned int devfn)  {
> >  	struct mobiveil_pcie *pcie = bus->sysdata;
> >
> > +	/* If there is no link, then there is no device */
> > +	if (bus->number > pcie->root_bus_nr && !mobiveil_pcie_link_up(pcie))
> 
> I think Bjorn mentioned this a million times already, eg:
> 
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.ke
> rnel.org%2Flinux-pci%2F20190411201535.GS256045%40google.com%2F&am
> p;data=02%7C01%7Czhiqiang.hou%40nxp.com%7Cffb4c8dcebe4493a375908
> d6ee90b471%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63695
> 8702637973543&amp;sdata=m%2FqV5zohqyBMUDT7zrVjF%2FLtYeJZO36rdY
> eMTPGGbHg%3D&amp;reserved=0
> 
> this is racy and gives a false sense of robustness. We have code in the kernel
> that checks the link but adding more seems silly to me, so I am inclined to
> drop this patch.
> 

Understand, drop it.

Thanks,
Zhiqiang

> Lorenzo
> 
> > +		return false;
> > +
> >  	/* Only one device down on each root port */
> >  	if ((bus->number == pcie->root_bus_nr) && (devfn > 0))
> >  		return false;
> > --
> > 2.17.1
> >

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCHv5 04/20] PCI: mobiveil: Remove the flag MSI_FLAG_MULTI_PCI_MSI
  2019-06-12 11:34     ` Z.q. Hou
@ 2019-06-12 13:08       ` Lorenzo Pieralisi
  2019-06-15  1:30         ` Z.q. Hou
  0 siblings, 1 reply; 67+ messages in thread
From: Lorenzo Pieralisi @ 2019-06-12 13:08 UTC (permalink / raw)
  To: Z.q. Hou
  Cc: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	catalin.marinas, will.deacon, Mingkai Hu, M.h. Lian, Xiaowei Bao

On Wed, Jun 12, 2019 at 11:34:51AM +0000, Z.q. Hou wrote:
> Hi Lorenzo,
> 
> Thanks a lot for your comments!
> 
> > -----Original Message-----
> > From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> > Sent: 2019年6月12日 1:00
> > To: Z.q. Hou <zhiqiang.hou@nxp.com>
> > Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> > devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> > bhelgaas@google.com; robh+dt@kernel.org; mark.rutland@arm.com;
> > l.subrahmanya@mobiveil.co.in; shawnguo@kernel.org; Leo Li
> > <leoyang.li@nxp.com>; catalin.marinas@arm.com; will.deacon@arm.com;
> > Mingkai Hu <mingkai.hu@nxp.com>; M.h. Lian <minghuan.lian@nxp.com>;
> > Xiaowei Bao <xiaowei.bao@nxp.com>
> > Subject: Re: [PATCHv5 04/20] PCI: mobiveil: Remove the flag
> > MSI_FLAG_MULTI_PCI_MSI
> > 
> > On Fri, Apr 12, 2019 at 08:35:36AM +0000, Z.q. Hou wrote:
> > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > >
> > > The current code does not support multiple MSIs, so remove the
> > > corresponding flag from the msi_domain_info structure.
> > 
> > Please explain me what's the problem before removing multi MSI support.
> 
> NXP LX2 PCIe use the GIC-ITS instead of Mobiveil IP internal MSI
> controller, so, I didn't encounter problem.

Well, you sent a patch to fix an issue, explain me the issue you
are fixing then, aka what have you sent this patch for ?

Lorenzo

> Subbu, did you test with Endpoint supporting multi MSI?
> 
> Thanks,
> Zhiqiang
> 
> > 
> > Thanks,
> > Lorenzo
> > 
> > > Fixes: 1e913e58335f ("PCI: mobiveil: Add MSI support")
> > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> > > ---
> > > V5:
> > >  - Corrected the subject.
> > >
> > >  drivers/pci/controller/pcie-mobiveil.c | 2 +-
> > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/pci/controller/pcie-mobiveil.c
> > > b/drivers/pci/controller/pcie-mobiveil.c
> > > index 563210e731d3..a0dd337c6214 100644
> > > --- a/drivers/pci/controller/pcie-mobiveil.c
> > > +++ b/drivers/pci/controller/pcie-mobiveil.c
> > > @@ -703,7 +703,7 @@ static struct irq_chip mobiveil_msi_irq_chip = {
> > >
> > >  static struct msi_domain_info mobiveil_msi_domain_info = {
> > >  	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS |
> > MSI_FLAG_USE_DEF_CHIP_OPS |
> > > -		   MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX),
> > > +		   MSI_FLAG_PCI_MSIX),
> > >  	.chip	= &mobiveil_msi_irq_chip,
> > >  };
> > >
> > > --
> > > 2.17.1
> > >

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCHv5 19/20] PCI: mobiveil: Add 8-bit and 16-bit register accessors
  2019-04-12  8:37 ` [PATCHv5 19/20] PCI: mobiveil: Add 8-bit and 16-bit register accessors Z.q. Hou
@ 2019-06-12 13:54   ` Lorenzo Pieralisi
  2019-06-15  1:13     ` Z.q. Hou
  0 siblings, 1 reply; 67+ messages in thread
From: Lorenzo Pieralisi @ 2019-06-12 13:54 UTC (permalink / raw)
  To: Z.q. Hou
  Cc: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	catalin.marinas, will.deacon, Mingkai Hu, M.h. Lian, Xiaowei Bao

On Fri, Apr 12, 2019 at 08:37:05AM +0000, Z.q. Hou wrote:
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> 
> There are some 8-bit and 16-bit registers in PCIe
> configuration space, so add accessors for them.
> 
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
> ---
> V5:
>  - Corrected and retouched the subject and changelog.
>  - No functionality change.
> 
>  drivers/pci/controller/pcie-mobiveil.c | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 
> diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c
> index 411e9779da12..456adfee393c 100644
> --- a/drivers/pci/controller/pcie-mobiveil.c
> +++ b/drivers/pci/controller/pcie-mobiveil.c
> @@ -268,11 +268,31 @@ static u32 csr_readl(struct mobiveil_pcie *pcie, u32 off)
>  	return csr_read(pcie, off, 0x4);
>  }
>  
> +static u32 csr_readw(struct mobiveil_pcie *pcie, u32 off)
> +{
> +	return csr_read(pcie, off, 0x2);
> +}
> +
> +static u32 csr_readb(struct mobiveil_pcie *pcie, u32 off)
> +{
> +	return csr_read(pcie, off, 0x1);
> +}
> +
>  static void csr_writel(struct mobiveil_pcie *pcie, u32 val, u32 off)
>  {
>  	csr_write(pcie, val, off, 0x4);
>  }
>  
> +static void csr_writew(struct mobiveil_pcie *pcie, u32 val, u32 off)
> +{
> +	csr_write(pcie, val, off, 0x2);
> +}
> +
> +static void csr_writeb(struct mobiveil_pcie *pcie, u32 val, u32 off)
> +{
> +	csr_write(pcie, val, off, 0x1);
> +}
> +

They are not used so you should drop this patch.

Lorenzo

>  static bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie)
>  {
>  	return (csr_readl(pcie, LTSSM_STATUS) &
> -- 
> 2.17.1
> 

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCHv5 17/20] PCI: mobiveil: Complete initialization of host even if no PCIe link
  2019-04-12  8:36 ` [PATCHv5 17/20] PCI: mobiveil: Complete initialization of host even if no PCIe link Z.q. Hou
@ 2019-06-12 14:34   ` Lorenzo Pieralisi
  2019-06-15  2:34     ` Z.q. Hou
  0 siblings, 1 reply; 67+ messages in thread
From: Lorenzo Pieralisi @ 2019-06-12 14:34 UTC (permalink / raw)
  To: Z.q. Hou
  Cc: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	catalin.marinas, will.deacon, Mingkai Hu, M.h. Lian, Xiaowei Bao

On Fri, Apr 12, 2019 at 08:36:54AM +0000, Z.q. Hou wrote:
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> 
> Sometimes there is not a PCIe Endpoint stalled in the slot,
> so do not exit when the PCIe link is not up. And degrade the
> print level of link up info.

So what's the point of probing if the link does not initialize ?

Lorenzo

> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
> ---
> V5:
>  - Corrected and retouched the subject and changelog.
> 
>  drivers/pci/controller/pcie-mobiveil.c | 6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c
> index 1ee3ea2570c0..8dc87c7a600e 100644
> --- a/drivers/pci/controller/pcie-mobiveil.c
> +++ b/drivers/pci/controller/pcie-mobiveil.c
> @@ -560,7 +560,7 @@ static int mobiveil_bringup_link(struct mobiveil_pcie *pcie)
>  		usleep_range(LINK_WAIT_MIN, LINK_WAIT_MAX);
>  	}
>  
> -	dev_err(&pcie->pdev->dev, "link never came up\n");
> +	dev_info(&pcie->pdev->dev, "link never came up\n");
>  
>  	return -ETIMEDOUT;
>  }
> @@ -926,10 +926,8 @@ static int mobiveil_pcie_probe(struct platform_device *pdev)
>  	bridge->swizzle_irq = pci_common_swizzle;
>  
>  	ret = mobiveil_bringup_link(pcie);
> -	if (ret) {
> +	if (ret)
>  		dev_info(dev, "link bring-up failed\n");
> -		goto error;
> -	}
>  
>  	/* setup the kernel resources for the newly added PCIe root bus */
>  	ret = pci_scan_root_bus_bridge(bridge);
> -- 
> 2.17.1
> 

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCHv5 10/20] PCI: mobiveil: Fix the INTx process errors
  2019-04-12  8:36 ` [PATCHv5 10/20] PCI: mobiveil: Fix the INTx process errors Z.q. Hou
@ 2019-06-12 15:08   ` Lorenzo Pieralisi
  2019-06-14  7:08     ` Karthikeyan Mitran
  2019-06-28 17:05   ` Lorenzo Pieralisi
  1 sibling, 1 reply; 67+ messages in thread
From: Lorenzo Pieralisi @ 2019-06-12 15:08 UTC (permalink / raw)
  To: Z.q. Hou, Karthikeyan Mitran
  Cc: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	catalin.marinas, will.deacon, Mingkai Hu, M.h. Lian, Xiaowei Bao

On Fri, Apr 12, 2019 at 08:36:12AM +0000, Z.q. Hou wrote:
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> 
> In the loop block, there is not code to update the loop key,
> this patch updates the loop key by re-read the INTx status
> register.
> 
> This patch also add the clearing of the handled INTx status.
> 
> Note: Need MV to test this fix.

This means INTX were never tested and current code handling them is,
AFAICS, an infinite loop which is very very bad.

This is a gross bug and must be fixed as soon as possible.

I want Karthikeyan ACK and Tested-by on this patch.

Lorenzo

> Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver")
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
> ---
> V5:
>  - Corrected and retouched the subject and changelog.
> 
>  drivers/pci/controller/pcie-mobiveil.c | 13 +++++++++----
>  1 file changed, 9 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c
> index 4ba458474e42..78e575e71f4d 100644
> --- a/drivers/pci/controller/pcie-mobiveil.c
> +++ b/drivers/pci/controller/pcie-mobiveil.c
> @@ -361,6 +361,7 @@ static void mobiveil_pcie_isr(struct irq_desc *desc)
>  	/* Handle INTx */
>  	if (intr_status & PAB_INTP_INTX_MASK) {
>  		shifted_status = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT);
> +		shifted_status &= PAB_INTP_INTX_MASK;
>  		shifted_status >>= PAB_INTX_START;
>  		do {
>  			for_each_set_bit(bit, &shifted_status, PCI_NUM_INTX) {
> @@ -372,12 +373,16 @@ static void mobiveil_pcie_isr(struct irq_desc *desc)
>  					dev_err_ratelimited(dev, "unexpected IRQ, INT%d\n",
>  							    bit);
>  
> -				/* clear interrupt */
> -				csr_writel(pcie,
> -					   shifted_status << PAB_INTX_START,
> +				/* clear interrupt handled */
> +				csr_writel(pcie, 1 << (PAB_INTX_START + bit),
>  					   PAB_INTP_AMBA_MISC_STAT);
>  			}
> -		} while ((shifted_status >> PAB_INTX_START) != 0);
> +
> +			shifted_status = csr_readl(pcie,
> +						   PAB_INTP_AMBA_MISC_STAT);
> +			shifted_status &= PAB_INTP_INTX_MASK;
> +			shifted_status >>= PAB_INTX_START;
> +		} while (shifted_status != 0);
>  	}
>  
>  	/* read extra MSI status register */
> -- 
> 2.17.1
> 

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCHv5 07/20] PCI: mobiveil: Use WIN_NUM_0 explicitly for CFG outbound window
  2019-04-12  8:35 ` [PATCHv5 07/20] PCI: mobiveil: Use WIN_NUM_0 explicitly for CFG outbound window Z.q. Hou
@ 2019-06-12 15:13   ` Lorenzo Pieralisi
  0 siblings, 0 replies; 67+ messages in thread
From: Lorenzo Pieralisi @ 2019-06-12 15:13 UTC (permalink / raw)
  To: Z.q. Hou
  Cc: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	catalin.marinas, will.deacon, Mingkai Hu, M.h. Lian, Xiaowei Bao

On Fri, Apr 12, 2019 at 08:35:54AM +0000, Z.q. Hou wrote:
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> 
> As the .map_bus() use the WIN_NUM_0 for CFG transactions,
> it's better passing WIN_NUM_0 explicitly when initialize
> the CFG outbound window.
> 
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
> ---
> V5:
>  - Corrected the subject.
> 
>  drivers/pci/controller/pcie-mobiveil.c | 5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c
> index b2cc9c097fc9..df71c11b4810 100644
> --- a/drivers/pci/controller/pcie-mobiveil.c
> +++ b/drivers/pci/controller/pcie-mobiveil.c
> @@ -612,9 +612,8 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
>  	 */
>  
>  	/* config outbound translation window */
> -	program_ob_windows(pcie, pcie->ob_wins_configured,
> -			   pcie->ob_io_res->start, 0, CFG_WINDOW_TYPE,
> -			   resource_size(pcie->ob_io_res));
> +	program_ob_windows(pcie, WIN_NUM_0, pcie->ob_io_res->start, 0,
> +			   CFG_WINDOW_TYPE, resource_size(pcie->ob_io_res));

This makes sense - current code is quite obscure and prone to
bugs.

Lorenzo

>  	/* memory inbound translation window */
>  	program_ib_windows(pcie, WIN_NUM_1, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE);
> -- 
> 2.17.1
> 

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCHv5 18/20] PCI: mobiveil: Disable IB and OB windows set by bootloader
  2019-04-12  8:37 ` [PATCHv5 18/20] PCI: mobiveil: Disable IB and OB windows set by bootloader Z.q. Hou
@ 2019-06-12 16:23   ` Lorenzo Pieralisi
  2019-06-15  5:03     ` Z.q. Hou
  0 siblings, 1 reply; 67+ messages in thread
From: Lorenzo Pieralisi @ 2019-06-12 16:23 UTC (permalink / raw)
  To: Z.q. Hou, bhelgaas
  Cc: linux-pci, linux-arm-kernel, devicetree, linux-kernel, robh+dt,
	mark.rutland, l.subrahmanya, shawnguo, Leo Li, catalin.marinas,
	will.deacon, Mingkai Hu, M.h. Lian, Xiaowei Bao

On Fri, Apr 12, 2019 at 08:37:00AM +0000, Z.q. Hou wrote:
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> 
> Disable all inbound and outbound windows before set up the windows
> in kernel, in case transactions match the window set by bootloader.

There must be no PCI transactions ongoing at bootloader<->OS handover.

The bootloader needs fixing and this patch should be dropped, the host
bridge driver assumes the host bridge state is disabled, it will
program the bridge apertures from scratch with no ongoing transactions,
anything deviating from this behaviour is a bootloader bug and a recipe
for disaster.

Lorenzo

> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
> ---
> V5:
>  - No functionality change.
> 
>  drivers/pci/controller/pcie-mobiveil.c | 25 +++++++++++++++++++++++++
>  1 file changed, 25 insertions(+)
> 
> diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c
> index 8dc87c7a600e..411e9779da12 100644
> --- a/drivers/pci/controller/pcie-mobiveil.c
> +++ b/drivers/pci/controller/pcie-mobiveil.c
> @@ -565,6 +565,24 @@ static int mobiveil_bringup_link(struct mobiveil_pcie *pcie)
>  	return -ETIMEDOUT;
>  }
>  
> +static void mobiveil_pcie_disable_ib_win(struct mobiveil_pcie *pcie, int idx)
> +{
> +	u32 val;
> +
> +	val = csr_readl(pcie, PAB_PEX_AMAP_CTRL(idx));
> +	val &= ~(1 << AMAP_CTRL_EN_SHIFT);
> +	csr_writel(pcie, val, PAB_PEX_AMAP_CTRL(idx));
> +}
> +
> +static void mobiveil_pcie_disable_ob_win(struct mobiveil_pcie *pcie, int idx)
> +{
> +	u32 val;
> +
> +	val = csr_readl(pcie, PAB_AXI_AMAP_CTRL(idx));
> +	val &= ~(1 << WIN_ENABLE_SHIFT);
> +	csr_writel(pcie, val, PAB_AXI_AMAP_CTRL(idx));
> +}
> +
>  static void mobiveil_pcie_enable_msi(struct mobiveil_pcie *pcie)
>  {
>  	phys_addr_t msg_addr = pcie->pcie_reg_base;
> @@ -585,6 +603,13 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
>  {
>  	u32 value, pab_ctrl, type;
>  	struct resource_entry *win;
> +	int i;
> +
> +	/* Disable all inbound/outbound windows */
> +	for (i = 0; i < pcie->apio_wins; i++)
> +		mobiveil_pcie_disable_ob_win(pcie, i);
> +	for (i = 0; i < pcie->ppio_wins; i++)
> +		mobiveil_pcie_disable_ib_win(pcie, i);
>  
>  	/* setup bus numbers */
>  	value = csr_readl(pcie, PCI_PRIMARY_BUS);
> -- 
> 2.17.1
> 

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCHv5 10/20] PCI: mobiveil: Fix the INTx process errors
  2019-06-12 15:08   ` Lorenzo Pieralisi
@ 2019-06-14  7:08     ` Karthikeyan Mitran
  2019-06-14 10:43       ` Lorenzo Pieralisi
  0 siblings, 1 reply; 67+ messages in thread
From: Karthikeyan Mitran @ 2019-06-14  7:08 UTC (permalink / raw)
  To: Lorenzo Pieralisi
  Cc: Z.q. Hou, linux-pci, linux-arm-kernel, devicetree, linux-kernel,
	bhelgaas, robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	catalin.marinas, will.deacon, Mingkai Hu, M.h. Lian, Xiaowei Bao

Hi Lorenzo and Hou Zhiqiang
 PAB_INTP_AMBA_MISC_STAT does have other status in the higher bits, it
should have been masked before checking for the status

Acked-by: Karthikeyan Mitran <m.karthikeyan@mobiveil.co.in>

On Wed, Jun 12, 2019 at 8:38 PM Lorenzo Pieralisi
<lorenzo.pieralisi@arm.com> wrote:
>
> On Fri, Apr 12, 2019 at 08:36:12AM +0000, Z.q. Hou wrote:
> > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> >
> > In the loop block, there is not code to update the loop key,
> > this patch updates the loop key by re-read the INTx status
> > register.
> >
> > This patch also add the clearing of the handled INTx status.
> >
> > Note: Need MV to test this fix.
>
> This means INTX were never tested and current code handling them is,
> AFAICS, an infinite loop which is very very bad.
>
> This is a gross bug and must be fixed as soon as possible.
>
> I want Karthikeyan ACK and Tested-by on this patch.
>
> Lorenzo
>
> > Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver")
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> > Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
> > ---
> > V5:
> >  - Corrected and retouched the subject and changelog.
> >
> >  drivers/pci/controller/pcie-mobiveil.c | 13 +++++++++----
> >  1 file changed, 9 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c
> > index 4ba458474e42..78e575e71f4d 100644
> > --- a/drivers/pci/controller/pcie-mobiveil.c
> > +++ b/drivers/pci/controller/pcie-mobiveil.c
> > @@ -361,6 +361,7 @@ static void mobiveil_pcie_isr(struct irq_desc *desc)
> >       /* Handle INTx */
> >       if (intr_status & PAB_INTP_INTX_MASK) {
> >               shifted_status = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT);
> > +             shifted_status &= PAB_INTP_INTX_MASK;
> >               shifted_status >>= PAB_INTX_START;
> >               do {
> >                       for_each_set_bit(bit, &shifted_status, PCI_NUM_INTX) {
> > @@ -372,12 +373,16 @@ static void mobiveil_pcie_isr(struct irq_desc *desc)
> >                                       dev_err_ratelimited(dev, "unexpected IRQ, INT%d\n",
> >                                                           bit);
> >
> > -                             /* clear interrupt */
> > -                             csr_writel(pcie,
> > -                                        shifted_status << PAB_INTX_START,
> > +                             /* clear interrupt handled */
> > +                             csr_writel(pcie, 1 << (PAB_INTX_START + bit),
> >                                          PAB_INTP_AMBA_MISC_STAT);
> >                       }
> > -             } while ((shifted_status >> PAB_INTX_START) != 0);
> > +
> > +                     shifted_status = csr_readl(pcie,
> > +                                                PAB_INTP_AMBA_MISC_STAT);
> > +                     shifted_status &= PAB_INTP_INTX_MASK;
> > +                     shifted_status >>= PAB_INTX_START;
> > +             } while (shifted_status != 0);
> >       }
> >
> >       /* read extra MSI status register */
> > --
> > 2.17.1
> >



-- 
Thanks,
Regards,
Karthikeyan Mitran

-- 
Mobiveil INC., CONFIDENTIALITY NOTICE: This e-mail message, including any 
attachments, is for the sole use of the intended recipient(s) and may 
contain proprietary confidential or privileged information or otherwise be 
protected by law. Any unauthorized review, use, disclosure or distribution 
is prohibited. If you are not the intended recipient, please notify the 
sender and destroy all copies and the original message.

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCHv5 10/20] PCI: mobiveil: Fix the INTx process errors
  2019-06-14  7:08     ` Karthikeyan Mitran
@ 2019-06-14 10:43       ` Lorenzo Pieralisi
  2019-06-19  5:28         ` Karthikeyan Mitran
  0 siblings, 1 reply; 67+ messages in thread
From: Lorenzo Pieralisi @ 2019-06-14 10:43 UTC (permalink / raw)
  To: Karthikeyan Mitran
  Cc: Z.q. Hou, linux-pci, linux-arm-kernel, devicetree, linux-kernel,
	bhelgaas, robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	catalin.marinas, will.deacon, Mingkai Hu, M.h. Lian, Xiaowei Bao

On Fri, Jun 14, 2019 at 12:38:51PM +0530, Karthikeyan Mitran wrote:
> Hi Lorenzo and Hou Zhiqiang
>  PAB_INTP_AMBA_MISC_STAT does have other status in the higher bits, it
> should have been masked before checking for the status

You are the maintainer for this driver, so if there is something to be
changed you must post a patch to that extent, I do not understand what
the above means, write the code to fix it, I won't do it.

I am getting a bit annoyed with this Mobiveil driver so either you guys
sort this out or I will have to remove it from the kernel.

> Acked-by: Karthikeyan Mitran <m.karthikeyan@mobiveil.co.in>

Ok I assume this means you tested it but according to what you
say above, are there still issues with this code path ? Should
we update the patch ?

Moreover:

https://kernelnewbies.org/PatchCulture

Please read it and never top-post.

Thanks,
Lorenzo

> On Wed, Jun 12, 2019 at 8:38 PM Lorenzo Pieralisi
> <lorenzo.pieralisi@arm.com> wrote:
> >
> > On Fri, Apr 12, 2019 at 08:36:12AM +0000, Z.q. Hou wrote:
> > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > >
> > > In the loop block, there is not code to update the loop key,
> > > this patch updates the loop key by re-read the INTx status
> > > register.
> > >
> > > This patch also add the clearing of the handled INTx status.
> > >
> > > Note: Need MV to test this fix.
> >
> > This means INTX were never tested and current code handling them is,
> > AFAICS, an infinite loop which is very very bad.
> >
> > This is a gross bug and must be fixed as soon as possible.
> >
> > I want Karthikeyan ACK and Tested-by on this patch.
> >
> > Lorenzo
> >
> > > Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver")
> > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> > > Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
> > > ---
> > > V5:
> > >  - Corrected and retouched the subject and changelog.
> > >
> > >  drivers/pci/controller/pcie-mobiveil.c | 13 +++++++++----
> > >  1 file changed, 9 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c
> > > index 4ba458474e42..78e575e71f4d 100644
> > > --- a/drivers/pci/controller/pcie-mobiveil.c
> > > +++ b/drivers/pci/controller/pcie-mobiveil.c
> > > @@ -361,6 +361,7 @@ static void mobiveil_pcie_isr(struct irq_desc *desc)
> > >       /* Handle INTx */
> > >       if (intr_status & PAB_INTP_INTX_MASK) {
> > >               shifted_status = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT);
> > > +             shifted_status &= PAB_INTP_INTX_MASK;
> > >               shifted_status >>= PAB_INTX_START;
> > >               do {
> > >                       for_each_set_bit(bit, &shifted_status, PCI_NUM_INTX) {
> > > @@ -372,12 +373,16 @@ static void mobiveil_pcie_isr(struct irq_desc *desc)
> > >                                       dev_err_ratelimited(dev, "unexpected IRQ, INT%d\n",
> > >                                                           bit);
> > >
> > > -                             /* clear interrupt */
> > > -                             csr_writel(pcie,
> > > -                                        shifted_status << PAB_INTX_START,
> > > +                             /* clear interrupt handled */
> > > +                             csr_writel(pcie, 1 << (PAB_INTX_START + bit),
> > >                                          PAB_INTP_AMBA_MISC_STAT);
> > >                       }
> > > -             } while ((shifted_status >> PAB_INTX_START) != 0);
> > > +
> > > +                     shifted_status = csr_readl(pcie,
> > > +                                                PAB_INTP_AMBA_MISC_STAT);
> > > +                     shifted_status &= PAB_INTP_INTX_MASK;
> > > +                     shifted_status >>= PAB_INTX_START;
> > > +             } while (shifted_status != 0);
> > >       }
> > >
> > >       /* read extra MSI status register */
> > > --
> > > 2.17.1
> > >
> 
> 
> 
> -- 
> Thanks,
> Regards,
> Karthikeyan Mitran
> 
> -- 
> Mobiveil INC., CONFIDENTIALITY NOTICE: This e-mail message, including any 
> attachments, is for the sole use of the intended recipient(s) and may 
> contain proprietary confidential or privileged information or otherwise be 
> protected by law. Any unauthorized review, use, disclosure or distribution 
> is prohibited. If you are not the intended recipient, please notify the 
> sender and destroy all copies and the original message.

^ permalink raw reply	[flat|nested] 67+ messages in thread

* RE: [PATCHv5 19/20] PCI: mobiveil: Add 8-bit and 16-bit register accessors
  2019-06-12 13:54   ` Lorenzo Pieralisi
@ 2019-06-15  1:13     ` Z.q. Hou
  2019-06-17  9:29       ` Lorenzo Pieralisi
  0 siblings, 1 reply; 67+ messages in thread
From: Z.q. Hou @ 2019-06-15  1:13 UTC (permalink / raw)
  To: Lorenzo Pieralisi
  Cc: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	catalin.marinas, will.deacon, Mingkai Hu, M.h. Lian, Xiaowei Bao

Hi Lorenzo,

> -----Original Message-----
> From: Lorenzo Pieralisi [mailto:lorenzo.pieralisi@arm.com]
> Sent: 2019年6月12日 21:54
> To: Z.q. Hou <zhiqiang.hou@nxp.com>
> Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> bhelgaas@google.com; robh+dt@kernel.org; mark.rutland@arm.com;
> l.subrahmanya@mobiveil.co.in; shawnguo@kernel.org; Leo Li
> <leoyang.li@nxp.com>; catalin.marinas@arm.com; will.deacon@arm.com;
> Mingkai Hu <mingkai.hu@nxp.com>; M.h. Lian <minghuan.lian@nxp.com>;
> Xiaowei Bao <xiaowei.bao@nxp.com>
> Subject: Re: [PATCHv5 19/20] PCI: mobiveil: Add 8-bit and 16-bit register
> accessors
> 
> On Fri, Apr 12, 2019 at 08:37:05AM +0000, Z.q. Hou wrote:
> > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> >
> > There are some 8-bit and 16-bit registers in PCIe configuration space,
> > so add accessors for them.
> >
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> > Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
> > ---
> > V5:
> >  - Corrected and retouched the subject and changelog.
> >  - No functionality change.
> >
> >  drivers/pci/controller/pcie-mobiveil.c | 20 ++++++++++++++++++++
> >  1 file changed, 20 insertions(+)
> >
> > diff --git a/drivers/pci/controller/pcie-mobiveil.c
> > b/drivers/pci/controller/pcie-mobiveil.c
> > index 411e9779da12..456adfee393c 100644
> > --- a/drivers/pci/controller/pcie-mobiveil.c
> > +++ b/drivers/pci/controller/pcie-mobiveil.c
> > @@ -268,11 +268,31 @@ static u32 csr_readl(struct mobiveil_pcie *pcie,
> u32 off)
> >  	return csr_read(pcie, off, 0x4);
> >  }
> >
> > +static u32 csr_readw(struct mobiveil_pcie *pcie, u32 off) {
> > +	return csr_read(pcie, off, 0x2);
> > +}
> > +
> > +static u32 csr_readb(struct mobiveil_pcie *pcie, u32 off) {
> > +	return csr_read(pcie, off, 0x1);
> > +}
> > +
> >  static void csr_writel(struct mobiveil_pcie *pcie, u32 val, u32 off)
> > {
> >  	csr_write(pcie, val, off, 0x4);
> >  }
> >
> > +static void csr_writew(struct mobiveil_pcie *pcie, u32 val, u32 off)
> > +{
> > +	csr_write(pcie, val, off, 0x2);
> > +}
> > +
> > +static void csr_writeb(struct mobiveil_pcie *pcie, u32 val, u32 off)
> > +{
> > +	csr_write(pcie, val, off, 0x1);
> > +}
> > +
> 
> They are not used so you should drop this patch.

NXP Layerscape PCIe Gen4 controller driver will use them, so don't drop it.

Thanks,
Zhiqiang

> 
> Lorenzo
> 
> >  static bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie)  {
> >  	return (csr_readl(pcie, LTSSM_STATUS) &
> > --
> > 2.17.1
> >

^ permalink raw reply	[flat|nested] 67+ messages in thread

* RE: [PATCHv5 04/20] PCI: mobiveil: Remove the flag MSI_FLAG_MULTI_PCI_MSI
  2019-06-12 13:08       ` Lorenzo Pieralisi
@ 2019-06-15  1:30         ` Z.q. Hou
  2019-06-17  9:33           ` Lorenzo Pieralisi
  0 siblings, 1 reply; 67+ messages in thread
From: Z.q. Hou @ 2019-06-15  1:30 UTC (permalink / raw)
  To: Lorenzo Pieralisi
  Cc: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	catalin.marinas, will.deacon, Mingkai Hu, M.h. Lian, Xiaowei Bao

Hi Lorenzo,

> -----Original Message-----
> From: Lorenzo Pieralisi [mailto:lorenzo.pieralisi@arm.com]
> Sent: 2019年6月12日 21:08
> To: Z.q. Hou <zhiqiang.hou@nxp.com>
> Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> bhelgaas@google.com; robh+dt@kernel.org; mark.rutland@arm.com;
> l.subrahmanya@mobiveil.co.in; shawnguo@kernel.org; Leo Li
> <leoyang.li@nxp.com>; catalin.marinas@arm.com; will.deacon@arm.com;
> Mingkai Hu <mingkai.hu@nxp.com>; M.h. Lian <minghuan.lian@nxp.com>;
> Xiaowei Bao <xiaowei.bao@nxp.com>
> Subject: Re: [PATCHv5 04/20] PCI: mobiveil: Remove the flag
> MSI_FLAG_MULTI_PCI_MSI
> 
> On Wed, Jun 12, 2019 at 11:34:51AM +0000, Z.q. Hou wrote:
> > Hi Lorenzo,
> >
> > Thanks a lot for your comments!
> >
> > > -----Original Message-----
> > > From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> > > Sent: 2019年6月12日 1:00
> > > To: Z.q. Hou <zhiqiang.hou@nxp.com>
> > > Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> > > devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> > > bhelgaas@google.com; robh+dt@kernel.org; mark.rutland@arm.com;
> > > l.subrahmanya@mobiveil.co.in; shawnguo@kernel.org; Leo Li
> > > <leoyang.li@nxp.com>; catalin.marinas@arm.com;
> will.deacon@arm.com;
> > > Mingkai Hu <mingkai.hu@nxp.com>; M.h. Lian
> <minghuan.lian@nxp.com>;
> > > Xiaowei Bao <xiaowei.bao@nxp.com>
> > > Subject: Re: [PATCHv5 04/20] PCI: mobiveil: Remove the flag
> > > MSI_FLAG_MULTI_PCI_MSI
> > >
> > > On Fri, Apr 12, 2019 at 08:35:36AM +0000, Z.q. Hou wrote:
> > > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > >
> > > > The current code does not support multiple MSIs, so remove the
> > > > corresponding flag from the msi_domain_info structure.
> > >
> > > Please explain me what's the problem before removing multi MSI support.
> >
> > NXP LX2 PCIe use the GIC-ITS instead of Mobiveil IP internal MSI
> > controller, so, I didn't encounter problem.
> 
> Well, you sent a patch to fix an issue, explain me the issue you are fixing then,
> aka what have you sent this patch for ?

I did not face issue, as I have explained NXP does not use the Mobiveil IP's MSI controller.
But obviously the MSI allocate function does not support multiple MSI, so I submitted this patch.

Thanks,
Zhiqiang

> 
> Lorenzo
> 
> > Subbu, did you test with Endpoint supporting multi MSI?
> >
> > Thanks,
> > Zhiqiang
> >
> > >
> > > Thanks,
> > > Lorenzo
> > >
> > > > Fixes: 1e913e58335f ("PCI: mobiveil: Add MSI support")
> > > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > > Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> > > > ---
> > > > V5:
> > > >  - Corrected the subject.
> > > >
> > > >  drivers/pci/controller/pcie-mobiveil.c | 2 +-
> > > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/pci/controller/pcie-mobiveil.c
> > > > b/drivers/pci/controller/pcie-mobiveil.c
> > > > index 563210e731d3..a0dd337c6214 100644
> > > > --- a/drivers/pci/controller/pcie-mobiveil.c
> > > > +++ b/drivers/pci/controller/pcie-mobiveil.c
> > > > @@ -703,7 +703,7 @@ static struct irq_chip mobiveil_msi_irq_chip =
> > > > {
> > > >
> > > >  static struct msi_domain_info mobiveil_msi_domain_info = {
> > > >  	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS |
> > > MSI_FLAG_USE_DEF_CHIP_OPS |
> > > > -		   MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX),
> > > > +		   MSI_FLAG_PCI_MSIX),
> > > >  	.chip	= &mobiveil_msi_irq_chip,
> > > >  };
> > > >
> > > > --
> > > > 2.17.1
> > > >

^ permalink raw reply	[flat|nested] 67+ messages in thread

* RE: [PATCHv5 17/20] PCI: mobiveil: Complete initialization of host even if no PCIe link
  2019-06-12 14:34   ` Lorenzo Pieralisi
@ 2019-06-15  2:34     ` Z.q. Hou
  0 siblings, 0 replies; 67+ messages in thread
From: Z.q. Hou @ 2019-06-15  2:34 UTC (permalink / raw)
  To: Lorenzo Pieralisi
  Cc: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	catalin.marinas, will.deacon, Mingkai Hu, M.h. Lian, Xiaowei Bao

Hi Lorenzo,

> -----Original Message-----
> From: Lorenzo Pieralisi [mailto:lorenzo.pieralisi@arm.com]
> Sent: 2019年6月12日 22:35
> To: Z.q. Hou <zhiqiang.hou@nxp.com>
> Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> bhelgaas@google.com; robh+dt@kernel.org; mark.rutland@arm.com;
> l.subrahmanya@mobiveil.co.in; shawnguo@kernel.org; Leo Li
> <leoyang.li@nxp.com>; catalin.marinas@arm.com; will.deacon@arm.com;
> Mingkai Hu <mingkai.hu@nxp.com>; M.h. Lian <minghuan.lian@nxp.com>;
> Xiaowei Bao <xiaowei.bao@nxp.com>
> Subject: Re: [PATCHv5 17/20] PCI: mobiveil: Complete initialization of host
> even if no PCIe link
> 
> On Fri, Apr 12, 2019 at 08:36:54AM +0000, Z.q. Hou wrote:
> > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> >
> > Sometimes there is not a PCIe Endpoint stalled in the slot, so do not
> > exit when the PCIe link is not up. And degrade the print level of link
> > up info.
> 
> So what's the point of probing if the link does not initialize ?

A simple case is plug in a PCIe device after the Linux boot up, then rescan the device.
If exit when PCIe link is not up, the PCIe controller is not initialized completely, the
rescan cannot work.

Thanks,
Zhiqiang

> Lorenzo
> 
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> > Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
> > ---
> > V5:
> >  - Corrected and retouched the subject and changelog.
> >
> >  drivers/pci/controller/pcie-mobiveil.c | 6 ++----
> >  1 file changed, 2 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/pci/controller/pcie-mobiveil.c
> > b/drivers/pci/controller/pcie-mobiveil.c
> > index 1ee3ea2570c0..8dc87c7a600e 100644
> > --- a/drivers/pci/controller/pcie-mobiveil.c
> > +++ b/drivers/pci/controller/pcie-mobiveil.c
> > @@ -560,7 +560,7 @@ static int mobiveil_bringup_link(struct
> mobiveil_pcie *pcie)
> >  		usleep_range(LINK_WAIT_MIN, LINK_WAIT_MAX);
> >  	}
> >
> > -	dev_err(&pcie->pdev->dev, "link never came up\n");
> > +	dev_info(&pcie->pdev->dev, "link never came up\n");
> >
> >  	return -ETIMEDOUT;
> >  }
> > @@ -926,10 +926,8 @@ static int mobiveil_pcie_probe(struct
> platform_device *pdev)
> >  	bridge->swizzle_irq = pci_common_swizzle;
> >
> >  	ret = mobiveil_bringup_link(pcie);
> > -	if (ret) {
> > +	if (ret)
> >  		dev_info(dev, "link bring-up failed\n");
> > -		goto error;
> > -	}
> >
> >  	/* setup the kernel resources for the newly added PCIe root bus */
> >  	ret = pci_scan_root_bus_bridge(bridge);
> > --
> > 2.17.1
> >

^ permalink raw reply	[flat|nested] 67+ messages in thread

* RE: [PATCHv5 18/20] PCI: mobiveil: Disable IB and OB windows set by bootloader
  2019-06-12 16:23   ` Lorenzo Pieralisi
@ 2019-06-15  5:03     ` Z.q. Hou
  2019-06-17  9:30       ` Lorenzo Pieralisi
  0 siblings, 1 reply; 67+ messages in thread
From: Z.q. Hou @ 2019-06-15  5:03 UTC (permalink / raw)
  To: Lorenzo Pieralisi, bhelgaas
  Cc: linux-pci, linux-arm-kernel, devicetree, linux-kernel, robh+dt,
	mark.rutland, l.subrahmanya, shawnguo, Leo Li, catalin.marinas,
	will.deacon, Mingkai Hu, M.h. Lian, Xiaowei Bao

Hi Lorenzo,

> -----Original Message-----
> From: Lorenzo Pieralisi [mailto:lorenzo.pieralisi@arm.com]
> Sent: 2019年6月13日 0:24
> To: Z.q. Hou <zhiqiang.hou@nxp.com>; bhelgaas@google.com
> Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> robh+dt@kernel.org; mark.rutland@arm.com; l.subrahmanya@mobiveil.co.in;
> shawnguo@kernel.org; Leo Li <leoyang.li@nxp.com>;
> catalin.marinas@arm.com; will.deacon@arm.com; Mingkai Hu
> <mingkai.hu@nxp.com>; M.h. Lian <minghuan.lian@nxp.com>; Xiaowei Bao
> <xiaowei.bao@nxp.com>
> Subject: Re: [PATCHv5 18/20] PCI: mobiveil: Disable IB and OB windows set
> by bootloader
> 
> On Fri, Apr 12, 2019 at 08:37:00AM +0000, Z.q. Hou wrote:
> > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> >
> > Disable all inbound and outbound windows before set up the windows in
> > kernel, in case transactions match the window set by bootloader.
> 
> There must be no PCI transactions ongoing at bootloader<->OS handover.
>

Yes, exact.
 
> The bootloader needs fixing and this patch should be dropped, the host bridge
> driver assumes the host bridge state is disabled,

The host bridge driver should not assumes the host state is disabled, actually
u-boot enable/initialize the host and without disabling it when transfer the 
control to Linux.

> it will program the bridge
> apertures from scratch with no ongoing transactions, anything deviating from
> this behaviour is a bootloader bug and a recipe for disaster.

The point of this patch is not to fix the ongoing transaction issue, it is to avoid
a potential issue which is caused by the outbound window enabled by bootloader
overlapping with Linux enabled.

Thanks,
Zhiqiang
 
> Lorenzo
> 
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> > Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
> > ---
> > V5:
> >  - No functionality change.
> >
> >  drivers/pci/controller/pcie-mobiveil.c | 25 +++++++++++++++++++++++++
> >  1 file changed, 25 insertions(+)
> >
> > diff --git a/drivers/pci/controller/pcie-mobiveil.c
> > b/drivers/pci/controller/pcie-mobiveil.c
> > index 8dc87c7a600e..411e9779da12 100644
> > --- a/drivers/pci/controller/pcie-mobiveil.c
> > +++ b/drivers/pci/controller/pcie-mobiveil.c
> > @@ -565,6 +565,24 @@ static int mobiveil_bringup_link(struct
> mobiveil_pcie *pcie)
> >  	return -ETIMEDOUT;
> >  }
> >
> > +static void mobiveil_pcie_disable_ib_win(struct mobiveil_pcie *pcie,
> > +int idx) {
> > +	u32 val;
> > +
> > +	val = csr_readl(pcie, PAB_PEX_AMAP_CTRL(idx));
> > +	val &= ~(1 << AMAP_CTRL_EN_SHIFT);
> > +	csr_writel(pcie, val, PAB_PEX_AMAP_CTRL(idx)); }
> > +
> > +static void mobiveil_pcie_disable_ob_win(struct mobiveil_pcie *pcie,
> > +int idx) {
> > +	u32 val;
> > +
> > +	val = csr_readl(pcie, PAB_AXI_AMAP_CTRL(idx));
> > +	val &= ~(1 << WIN_ENABLE_SHIFT);
> > +	csr_writel(pcie, val, PAB_AXI_AMAP_CTRL(idx)); }
> > +
> >  static void mobiveil_pcie_enable_msi(struct mobiveil_pcie *pcie)  {
> >  	phys_addr_t msg_addr = pcie->pcie_reg_base; @@ -585,6 +603,13 @@
> > static int mobiveil_host_init(struct mobiveil_pcie *pcie)  {
> >  	u32 value, pab_ctrl, type;
> >  	struct resource_entry *win;
> > +	int i;
> > +
> > +	/* Disable all inbound/outbound windows */
> > +	for (i = 0; i < pcie->apio_wins; i++)
> > +		mobiveil_pcie_disable_ob_win(pcie, i);
> > +	for (i = 0; i < pcie->ppio_wins; i++)
> > +		mobiveil_pcie_disable_ib_win(pcie, i);
> >
> >  	/* setup bus numbers */
> >  	value = csr_readl(pcie, PCI_PRIMARY_BUS);
> > --
> > 2.17.1
> >

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCHv5 19/20] PCI: mobiveil: Add 8-bit and 16-bit register accessors
  2019-06-15  1:13     ` Z.q. Hou
@ 2019-06-17  9:29       ` Lorenzo Pieralisi
  2019-06-17 10:16         ` Z.q. Hou
  0 siblings, 1 reply; 67+ messages in thread
From: Lorenzo Pieralisi @ 2019-06-17  9:29 UTC (permalink / raw)
  To: Z.q. Hou
  Cc: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	catalin.marinas, will.deacon, Mingkai Hu, M.h. Lian, Xiaowei Bao

On Sat, Jun 15, 2019 at 01:13:48AM +0000, Z.q. Hou wrote:
> Hi Lorenzo,
> 
> > -----Original Message-----
> > From: Lorenzo Pieralisi [mailto:lorenzo.pieralisi@arm.com]
> > Sent: 2019年6月12日 21:54
> > To: Z.q. Hou <zhiqiang.hou@nxp.com>
> > Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> > devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> > bhelgaas@google.com; robh+dt@kernel.org; mark.rutland@arm.com;
> > l.subrahmanya@mobiveil.co.in; shawnguo@kernel.org; Leo Li
> > <leoyang.li@nxp.com>; catalin.marinas@arm.com; will.deacon@arm.com;
> > Mingkai Hu <mingkai.hu@nxp.com>; M.h. Lian <minghuan.lian@nxp.com>;
> > Xiaowei Bao <xiaowei.bao@nxp.com>
> > Subject: Re: [PATCHv5 19/20] PCI: mobiveil: Add 8-bit and 16-bit register
> > accessors
> > 
> > On Fri, Apr 12, 2019 at 08:37:05AM +0000, Z.q. Hou wrote:
> > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > >
> > > There are some 8-bit and 16-bit registers in PCIe configuration space,
> > > so add accessors for them.
> > >
> > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> > > Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
> > > ---
> > > V5:
> > >  - Corrected and retouched the subject and changelog.
> > >  - No functionality change.
> > >
> > >  drivers/pci/controller/pcie-mobiveil.c | 20 ++++++++++++++++++++
> > >  1 file changed, 20 insertions(+)
> > >
> > > diff --git a/drivers/pci/controller/pcie-mobiveil.c
> > > b/drivers/pci/controller/pcie-mobiveil.c
> > > index 411e9779da12..456adfee393c 100644
> > > --- a/drivers/pci/controller/pcie-mobiveil.c
> > > +++ b/drivers/pci/controller/pcie-mobiveil.c
> > > @@ -268,11 +268,31 @@ static u32 csr_readl(struct mobiveil_pcie *pcie,
> > u32 off)
> > >  	return csr_read(pcie, off, 0x4);
> > >  }
> > >
> > > +static u32 csr_readw(struct mobiveil_pcie *pcie, u32 off) {
> > > +	return csr_read(pcie, off, 0x2);
> > > +}
> > > +
> > > +static u32 csr_readb(struct mobiveil_pcie *pcie, u32 off) {
> > > +	return csr_read(pcie, off, 0x1);
> > > +}
> > > +
> > >  static void csr_writel(struct mobiveil_pcie *pcie, u32 val, u32 off)
> > > {
> > >  	csr_write(pcie, val, off, 0x4);
> > >  }
> > >
> > > +static void csr_writew(struct mobiveil_pcie *pcie, u32 val, u32 off)
> > > +{
> > > +	csr_write(pcie, val, off, 0x2);
> > > +}
> > > +
> > > +static void csr_writeb(struct mobiveil_pcie *pcie, u32 val, u32 off)
> > > +{
> > > +	csr_write(pcie, val, off, 0x1);
> > > +}
> > > +
> > 
> > They are not used so you should drop this patch.
> 
> NXP Layerscape PCIe Gen4 controller driver will use them, so don't
> drop it.

You add functions when they are needed, so drop this patch and
squash it to the patch that use these functions.

Lorenzo

> Thanks,
> Zhiqiang
> 
> > 
> > Lorenzo
> > 
> > >  static bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie)  {
> > >  	return (csr_readl(pcie, LTSSM_STATUS) &
> > > --
> > > 2.17.1
> > >

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCHv5 18/20] PCI: mobiveil: Disable IB and OB windows set by bootloader
  2019-06-15  5:03     ` Z.q. Hou
@ 2019-06-17  9:30       ` Lorenzo Pieralisi
  2019-06-17 10:42         ` Z.q. Hou
  0 siblings, 1 reply; 67+ messages in thread
From: Lorenzo Pieralisi @ 2019-06-17  9:30 UTC (permalink / raw)
  To: Z.q. Hou
  Cc: bhelgaas, linux-pci, linux-arm-kernel, devicetree, linux-kernel,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	catalin.marinas, will.deacon, Mingkai Hu, M.h. Lian, Xiaowei Bao

On Sat, Jun 15, 2019 at 05:03:33AM +0000, Z.q. Hou wrote:
> Hi Lorenzo,
> 
> > -----Original Message-----
> > From: Lorenzo Pieralisi [mailto:lorenzo.pieralisi@arm.com]
> > Sent: 2019年6月13日 0:24
> > To: Z.q. Hou <zhiqiang.hou@nxp.com>; bhelgaas@google.com
> > Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> > devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> > robh+dt@kernel.org; mark.rutland@arm.com; l.subrahmanya@mobiveil.co.in;
> > shawnguo@kernel.org; Leo Li <leoyang.li@nxp.com>;
> > catalin.marinas@arm.com; will.deacon@arm.com; Mingkai Hu
> > <mingkai.hu@nxp.com>; M.h. Lian <minghuan.lian@nxp.com>; Xiaowei Bao
> > <xiaowei.bao@nxp.com>
> > Subject: Re: [PATCHv5 18/20] PCI: mobiveil: Disable IB and OB windows set
> > by bootloader
> > 
> > On Fri, Apr 12, 2019 at 08:37:00AM +0000, Z.q. Hou wrote:
> > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > >
> > > Disable all inbound and outbound windows before set up the windows in
> > > kernel, in case transactions match the window set by bootloader.
> > 
> > There must be no PCI transactions ongoing at bootloader<->OS handover.
> >
> 
> Yes, exact.
>  
> > The bootloader needs fixing and this patch should be dropped, the host bridge
> > driver assumes the host bridge state is disabled,
> 
> The host bridge driver should not assumes the host state is disabled,
> actually u-boot enable/initialize the host and without disabling it
> when transfer the control to Linux.

Fix the bootloader and drop this patch, I explain to you why.

> > it will program the bridge
> > apertures from scratch with no ongoing transactions, anything deviating from
> > this behaviour is a bootloader bug and a recipe for disaster.
> 
> The point of this patch is not to fix the ongoing transaction issue,
> it is to avoid a potential issue which is caused by the outbound
> window enabled by bootloader overlapping with Linux enabled.

See above.

Lorenzo

> Thanks,
> Zhiqiang
>  
> > Lorenzo
> > 
> > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> > > Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
> > > ---
> > > V5:
> > >  - No functionality change.
> > >
> > >  drivers/pci/controller/pcie-mobiveil.c | 25 +++++++++++++++++++++++++
> > >  1 file changed, 25 insertions(+)
> > >
> > > diff --git a/drivers/pci/controller/pcie-mobiveil.c
> > > b/drivers/pci/controller/pcie-mobiveil.c
> > > index 8dc87c7a600e..411e9779da12 100644
> > > --- a/drivers/pci/controller/pcie-mobiveil.c
> > > +++ b/drivers/pci/controller/pcie-mobiveil.c
> > > @@ -565,6 +565,24 @@ static int mobiveil_bringup_link(struct
> > mobiveil_pcie *pcie)
> > >  	return -ETIMEDOUT;
> > >  }
> > >
> > > +static void mobiveil_pcie_disable_ib_win(struct mobiveil_pcie *pcie,
> > > +int idx) {
> > > +	u32 val;
> > > +
> > > +	val = csr_readl(pcie, PAB_PEX_AMAP_CTRL(idx));
> > > +	val &= ~(1 << AMAP_CTRL_EN_SHIFT);
> > > +	csr_writel(pcie, val, PAB_PEX_AMAP_CTRL(idx)); }
> > > +
> > > +static void mobiveil_pcie_disable_ob_win(struct mobiveil_pcie *pcie,
> > > +int idx) {
> > > +	u32 val;
> > > +
> > > +	val = csr_readl(pcie, PAB_AXI_AMAP_CTRL(idx));
> > > +	val &= ~(1 << WIN_ENABLE_SHIFT);
> > > +	csr_writel(pcie, val, PAB_AXI_AMAP_CTRL(idx)); }
> > > +
> > >  static void mobiveil_pcie_enable_msi(struct mobiveil_pcie *pcie)  {
> > >  	phys_addr_t msg_addr = pcie->pcie_reg_base; @@ -585,6 +603,13 @@
> > > static int mobiveil_host_init(struct mobiveil_pcie *pcie)  {
> > >  	u32 value, pab_ctrl, type;
> > >  	struct resource_entry *win;
> > > +	int i;
> > > +
> > > +	/* Disable all inbound/outbound windows */
> > > +	for (i = 0; i < pcie->apio_wins; i++)
> > > +		mobiveil_pcie_disable_ob_win(pcie, i);
> > > +	for (i = 0; i < pcie->ppio_wins; i++)
> > > +		mobiveil_pcie_disable_ib_win(pcie, i);
> > >
> > >  	/* setup bus numbers */
> > >  	value = csr_readl(pcie, PCI_PRIMARY_BUS);
> > > --
> > > 2.17.1
> > >

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCHv5 04/20] PCI: mobiveil: Remove the flag MSI_FLAG_MULTI_PCI_MSI
  2019-06-15  1:30         ` Z.q. Hou
@ 2019-06-17  9:33           ` Lorenzo Pieralisi
  2019-06-17 10:34             ` Z.q. Hou
  0 siblings, 1 reply; 67+ messages in thread
From: Lorenzo Pieralisi @ 2019-06-17  9:33 UTC (permalink / raw)
  To: Z.q. Hou
  Cc: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	catalin.marinas, will.deacon, Mingkai Hu, M.h. Lian, Xiaowei Bao

On Sat, Jun 15, 2019 at 01:30:39AM +0000, Z.q. Hou wrote:
> Hi Lorenzo,
> 
> > -----Original Message-----
> > From: Lorenzo Pieralisi [mailto:lorenzo.pieralisi@arm.com]
> > Sent: 2019年6月12日 21:08
> > To: Z.q. Hou <zhiqiang.hou@nxp.com>
> > Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> > devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> > bhelgaas@google.com; robh+dt@kernel.org; mark.rutland@arm.com;
> > l.subrahmanya@mobiveil.co.in; shawnguo@kernel.org; Leo Li
> > <leoyang.li@nxp.com>; catalin.marinas@arm.com; will.deacon@arm.com;
> > Mingkai Hu <mingkai.hu@nxp.com>; M.h. Lian <minghuan.lian@nxp.com>;
> > Xiaowei Bao <xiaowei.bao@nxp.com>
> > Subject: Re: [PATCHv5 04/20] PCI: mobiveil: Remove the flag
> > MSI_FLAG_MULTI_PCI_MSI
> > 
> > On Wed, Jun 12, 2019 at 11:34:51AM +0000, Z.q. Hou wrote:
> > > Hi Lorenzo,
> > >
> > > Thanks a lot for your comments!
> > >
> > > > -----Original Message-----
> > > > From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> > > > Sent: 2019年6月12日 1:00
> > > > To: Z.q. Hou <zhiqiang.hou@nxp.com>
> > > > Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> > > > devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> > > > bhelgaas@google.com; robh+dt@kernel.org; mark.rutland@arm.com;
> > > > l.subrahmanya@mobiveil.co.in; shawnguo@kernel.org; Leo Li
> > > > <leoyang.li@nxp.com>; catalin.marinas@arm.com;
> > will.deacon@arm.com;
> > > > Mingkai Hu <mingkai.hu@nxp.com>; M.h. Lian
> > <minghuan.lian@nxp.com>;
> > > > Xiaowei Bao <xiaowei.bao@nxp.com>
> > > > Subject: Re: [PATCHv5 04/20] PCI: mobiveil: Remove the flag
> > > > MSI_FLAG_MULTI_PCI_MSI
> > > >
> > > > On Fri, Apr 12, 2019 at 08:35:36AM +0000, Z.q. Hou wrote:
> > > > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > > >
> > > > > The current code does not support multiple MSIs, so remove the
> > > > > corresponding flag from the msi_domain_info structure.
> > > >
> > > > Please explain me what's the problem before removing multi MSI support.
> > >
> > > NXP LX2 PCIe use the GIC-ITS instead of Mobiveil IP internal MSI
> > > controller, so, I didn't encounter problem.
> > 
> > Well, you sent a patch to fix an issue, explain me the issue you are fixing then,
> > aka what have you sent this patch for ?
> 
> I did not face issue, as I have explained NXP does not use the
> Mobiveil IP's MSI controller.  But obviously the MSI allocate function
> does not support multiple MSI, so I submitted this patch.

There is nothing obvious. Write what you are fixing in the commit log
and I will apply the patch, I won't write the commit log for you. Anyone
should be able to understand why a patch was needed by reading the
commit log, it is as important as writing the code itself.

Thanks,
Lorenzo

> Thanks,
> Zhiqiang
> 
> > 
> > Lorenzo
> > 
> > > Subbu, did you test with Endpoint supporting multi MSI?
> > >
> > > Thanks,
> > > Zhiqiang
> > >
> > > >
> > > > Thanks,
> > > > Lorenzo
> > > >
> > > > > Fixes: 1e913e58335f ("PCI: mobiveil: Add MSI support")
> > > > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > > > Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> > > > > ---
> > > > > V5:
> > > > >  - Corrected the subject.
> > > > >
> > > > >  drivers/pci/controller/pcie-mobiveil.c | 2 +-
> > > > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > > > >
> > > > > diff --git a/drivers/pci/controller/pcie-mobiveil.c
> > > > > b/drivers/pci/controller/pcie-mobiveil.c
> > > > > index 563210e731d3..a0dd337c6214 100644
> > > > > --- a/drivers/pci/controller/pcie-mobiveil.c
> > > > > +++ b/drivers/pci/controller/pcie-mobiveil.c
> > > > > @@ -703,7 +703,7 @@ static struct irq_chip mobiveil_msi_irq_chip =
> > > > > {
> > > > >
> > > > >  static struct msi_domain_info mobiveil_msi_domain_info = {
> > > > >  	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS |
> > > > MSI_FLAG_USE_DEF_CHIP_OPS |
> > > > > -		   MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX),
> > > > > +		   MSI_FLAG_PCI_MSIX),
> > > > >  	.chip	= &mobiveil_msi_irq_chip,
> > > > >  };
> > > > >
> > > > > --
> > > > > 2.17.1
> > > > >

^ permalink raw reply	[flat|nested] 67+ messages in thread

* RE: [PATCHv5 19/20] PCI: mobiveil: Add 8-bit and 16-bit register accessors
  2019-06-17  9:29       ` Lorenzo Pieralisi
@ 2019-06-17 10:16         ` Z.q. Hou
  0 siblings, 0 replies; 67+ messages in thread
From: Z.q. Hou @ 2019-06-17 10:16 UTC (permalink / raw)
  To: Lorenzo Pieralisi
  Cc: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	catalin.marinas, will.deacon, Mingkai Hu, M.h. Lian, Xiaowei Bao

Hi Lorenzo,

> -----Original Message-----
> From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Sent: 2019年6月17日 17:29
> To: Z.q. Hou <zhiqiang.hou@nxp.com>
> Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> bhelgaas@google.com; robh+dt@kernel.org; mark.rutland@arm.com;
> l.subrahmanya@mobiveil.co.in; shawnguo@kernel.org; Leo Li
> <leoyang.li@nxp.com>; catalin.marinas@arm.com; will.deacon@arm.com;
> Mingkai Hu <mingkai.hu@nxp.com>; M.h. Lian <minghuan.lian@nxp.com>;
> Xiaowei Bao <xiaowei.bao@nxp.com>
> Subject: Re: [PATCHv5 19/20] PCI: mobiveil: Add 8-bit and 16-bit register
> accessors
> 
> On Sat, Jun 15, 2019 at 01:13:48AM +0000, Z.q. Hou wrote:
> > Hi Lorenzo,
> >
> > > -----Original Message-----
> > > From: Lorenzo Pieralisi [mailto:lorenzo.pieralisi@arm.com]
> > > Sent: 2019年6月12日 21:54
> > > To: Z.q. Hou <zhiqiang.hou@nxp.com>
> > > Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> > > devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> > > bhelgaas@google.com; robh+dt@kernel.org; mark.rutland@arm.com;
> > > l.subrahmanya@mobiveil.co.in; shawnguo@kernel.org; Leo Li
> > > <leoyang.li@nxp.com>; catalin.marinas@arm.com;
> will.deacon@arm.com;
> > > Mingkai Hu <mingkai.hu@nxp.com>; M.h. Lian
> <minghuan.lian@nxp.com>;
> > > Xiaowei Bao <xiaowei.bao@nxp.com>
> > > Subject: Re: [PATCHv5 19/20] PCI: mobiveil: Add 8-bit and 16-bit
> > > register accessors
> > >
> > > On Fri, Apr 12, 2019 at 08:37:05AM +0000, Z.q. Hou wrote:
> > > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > >
> > > > There are some 8-bit and 16-bit registers in PCIe configuration
> > > > space, so add accessors for them.
> > > >
> > > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > > Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> > > > Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
> > > > ---
> > > > V5:
> > > >  - Corrected and retouched the subject and changelog.
> > > >  - No functionality change.
> > > >
> > > >  drivers/pci/controller/pcie-mobiveil.c | 20 ++++++++++++++++++++
> > > >  1 file changed, 20 insertions(+)
> > > >
> > > > diff --git a/drivers/pci/controller/pcie-mobiveil.c
> > > > b/drivers/pci/controller/pcie-mobiveil.c
> > > > index 411e9779da12..456adfee393c 100644
> > > > --- a/drivers/pci/controller/pcie-mobiveil.c
> > > > +++ b/drivers/pci/controller/pcie-mobiveil.c
> > > > @@ -268,11 +268,31 @@ static u32 csr_readl(struct mobiveil_pcie
> > > > *pcie,
> > > u32 off)
> > > >  	return csr_read(pcie, off, 0x4);  }
> > > >
> > > > +static u32 csr_readw(struct mobiveil_pcie *pcie, u32 off) {
> > > > +	return csr_read(pcie, off, 0x2); }
> > > > +
> > > > +static u32 csr_readb(struct mobiveil_pcie *pcie, u32 off) {
> > > > +	return csr_read(pcie, off, 0x1); }
> > > > +
> > > >  static void csr_writel(struct mobiveil_pcie *pcie, u32 val, u32
> > > > off) {
> > > >  	csr_write(pcie, val, off, 0x4);
> > > >  }
> > > >
> > > > +static void csr_writew(struct mobiveil_pcie *pcie, u32 val, u32
> > > > +off) {
> > > > +	csr_write(pcie, val, off, 0x2);
> > > > +}
> > > > +
> > > > +static void csr_writeb(struct mobiveil_pcie *pcie, u32 val, u32
> > > > +off) {
> > > > +	csr_write(pcie, val, off, 0x1);
> > > > +}
> > > > +
> > >
> > > They are not used so you should drop this patch.
> >
> > NXP Layerscape PCIe Gen4 controller driver will use them, so don't
> > drop it.
> 
> You add functions when they are needed, so drop this patch and squash it to
> the patch that use these functions.
>

Yes, agree, please drop it from this patch set.
 
Thanks,
Zhiqiang

> Lorenzo
> 
> > Thanks,
> > Zhiqiang
> >
> > >
> > > Lorenzo
> > >
> > > >  static bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie)  {
> > > >  	return (csr_readl(pcie, LTSSM_STATUS) &
> > > > --
> > > > 2.17.1
> > > >

^ permalink raw reply	[flat|nested] 67+ messages in thread

* RE: [PATCHv5 04/20] PCI: mobiveil: Remove the flag MSI_FLAG_MULTI_PCI_MSI
  2019-06-17  9:33           ` Lorenzo Pieralisi
@ 2019-06-17 10:34             ` Z.q. Hou
  2019-06-28 11:35               ` Lorenzo Pieralisi
  0 siblings, 1 reply; 67+ messages in thread
From: Z.q. Hou @ 2019-06-17 10:34 UTC (permalink / raw)
  To: Lorenzo Pieralisi
  Cc: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	catalin.marinas, will.deacon, Mingkai Hu, M.h. Lian, Xiaowei Bao

Hi Lorenzo,

> -----Original Message-----
> From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Sent: 2019年6月17日 17:34
> To: Z.q. Hou <zhiqiang.hou@nxp.com>
> Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> bhelgaas@google.com; robh+dt@kernel.org; mark.rutland@arm.com;
> l.subrahmanya@mobiveil.co.in; shawnguo@kernel.org; Leo Li
> <leoyang.li@nxp.com>; catalin.marinas@arm.com; will.deacon@arm.com;
> Mingkai Hu <mingkai.hu@nxp.com>; M.h. Lian <minghuan.lian@nxp.com>;
> Xiaowei Bao <xiaowei.bao@nxp.com>
> Subject: Re: [PATCHv5 04/20] PCI: mobiveil: Remove the flag
> MSI_FLAG_MULTI_PCI_MSI
> 
> On Sat, Jun 15, 2019 at 01:30:39AM +0000, Z.q. Hou wrote:
> > Hi Lorenzo,
> >
> > > -----Original Message-----
> > > From: Lorenzo Pieralisi [mailto:lorenzo.pieralisi@arm.com]
> > > Sent: 2019年6月12日 21:08
> > > To: Z.q. Hou <zhiqiang.hou@nxp.com>
> > > Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> > > devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> > > bhelgaas@google.com; robh+dt@kernel.org; mark.rutland@arm.com;
> > > l.subrahmanya@mobiveil.co.in; shawnguo@kernel.org; Leo Li
> > > <leoyang.li@nxp.com>; catalin.marinas@arm.com;
> will.deacon@arm.com;
> > > Mingkai Hu <mingkai.hu@nxp.com>; M.h. Lian
> <minghuan.lian@nxp.com>;
> > > Xiaowei Bao <xiaowei.bao@nxp.com>
> > > Subject: Re: [PATCHv5 04/20] PCI: mobiveil: Remove the flag
> > > MSI_FLAG_MULTI_PCI_MSI
> > >
> > > On Wed, Jun 12, 2019 at 11:34:51AM +0000, Z.q. Hou wrote:
> > > > Hi Lorenzo,
> > > >
> > > > Thanks a lot for your comments!
> > > >
> > > > > -----Original Message-----
> > > > > From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> > > > > Sent: 2019年6月12日 1:00
> > > > > To: Z.q. Hou <zhiqiang.hou@nxp.com>
> > > > > Cc: linux-pci@vger.kernel.org;
> > > > > linux-arm-kernel@lists.infradead.org;
> > > > > devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> > > > > bhelgaas@google.com; robh+dt@kernel.org; mark.rutland@arm.com;
> > > > > l.subrahmanya@mobiveil.co.in; shawnguo@kernel.org; Leo Li
> > > > > <leoyang.li@nxp.com>; catalin.marinas@arm.com;
> > > will.deacon@arm.com;
> > > > > Mingkai Hu <mingkai.hu@nxp.com>; M.h. Lian
> > > <minghuan.lian@nxp.com>;
> > > > > Xiaowei Bao <xiaowei.bao@nxp.com>
> > > > > Subject: Re: [PATCHv5 04/20] PCI: mobiveil: Remove the flag
> > > > > MSI_FLAG_MULTI_PCI_MSI
> > > > >
> > > > > On Fri, Apr 12, 2019 at 08:35:36AM +0000, Z.q. Hou wrote:
> > > > > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > > > >
> > > > > > The current code does not support multiple MSIs, so remove the
> > > > > > corresponding flag from the msi_domain_info structure.
> > > > >
> > > > > Please explain me what's the problem before removing multi MSI
> support.
> > > >
> > > > NXP LX2 PCIe use the GIC-ITS instead of Mobiveil IP internal MSI
> > > > controller, so, I didn't encounter problem.
> > >
> > > Well, you sent a patch to fix an issue, explain me the issue you are
> > > fixing then, aka what have you sent this patch for ?
> >
> > I did not face issue, as I have explained NXP does not use the
> > Mobiveil IP's MSI controller.  But obviously the MSI allocate function
> > does not support multiple MSI, so I submitted this patch.
> 
> There is nothing obvious. Write what you are fixing in the commit log and I will
> apply the patch, I won't write the commit log for you. Anyone should be able
> to understand why a patch was needed by reading the commit log, it is as
> important as writing the code itself.

With the flag MSI_FLAG_MULTI_PCI_MSI, when the Endpoint allocates multiple
MSI, it will trigger the "WARN_ON(nr_irqs != 1);" in mobiveil_irq_msi_domain_alloc(),
this is the issue this patch want to fix. 

Thanks,
Zhiqiang

> 
> Thanks,
> Lorenzo
> 
> > Thanks,
> > Zhiqiang
> >
> > >
> > > Lorenzo
> > >
> > > > Subbu, did you test with Endpoint supporting multi MSI?
> > > >
> > > > Thanks,
> > > > Zhiqiang
> > > >
> > > > >
> > > > > Thanks,
> > > > > Lorenzo
> > > > >
> > > > > > Fixes: 1e913e58335f ("PCI: mobiveil: Add MSI support")
> > > > > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > > > > Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> > > > > > ---
> > > > > > V5:
> > > > > >  - Corrected the subject.
> > > > > >
> > > > > >  drivers/pci/controller/pcie-mobiveil.c | 2 +-
> > > > > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > > > > >
> > > > > > diff --git a/drivers/pci/controller/pcie-mobiveil.c
> > > > > > b/drivers/pci/controller/pcie-mobiveil.c
> > > > > > index 563210e731d3..a0dd337c6214 100644
> > > > > > --- a/drivers/pci/controller/pcie-mobiveil.c
> > > > > > +++ b/drivers/pci/controller/pcie-mobiveil.c
> > > > > > @@ -703,7 +703,7 @@ static struct irq_chip
> > > > > > mobiveil_msi_irq_chip = {
> > > > > >
> > > > > >  static struct msi_domain_info mobiveil_msi_domain_info = {
> > > > > >  	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS |
> > > > > MSI_FLAG_USE_DEF_CHIP_OPS |
> > > > > > -		   MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX),
> > > > > > +		   MSI_FLAG_PCI_MSIX),
> > > > > >  	.chip	= &mobiveil_msi_irq_chip,
> > > > > >  };
> > > > > >
> > > > > > --
> > > > > > 2.17.1
> > > > > >

^ permalink raw reply	[flat|nested] 67+ messages in thread

* RE: [PATCHv5 18/20] PCI: mobiveil: Disable IB and OB windows set by bootloader
  2019-06-17  9:30       ` Lorenzo Pieralisi
@ 2019-06-17 10:42         ` Z.q. Hou
  0 siblings, 0 replies; 67+ messages in thread
From: Z.q. Hou @ 2019-06-17 10:42 UTC (permalink / raw)
  To: Lorenzo Pieralisi
  Cc: bhelgaas, linux-pci, linux-arm-kernel, devicetree, linux-kernel,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	catalin.marinas, will.deacon, Mingkai Hu, M.h. Lian, Xiaowei Bao

Hi Lorenzo,


> -----Original Message-----
> From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Sent: 2019年6月17日 17:31
> To: Z.q. Hou <zhiqiang.hou@nxp.com>
> Cc: bhelgaas@google.com; linux-pci@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; devicetree@vger.kernel.org;
> linux-kernel@vger.kernel.org; robh+dt@kernel.org; mark.rutland@arm.com;
> l.subrahmanya@mobiveil.co.in; shawnguo@kernel.org; Leo Li
> <leoyang.li@nxp.com>; catalin.marinas@arm.com; will.deacon@arm.com;
> Mingkai Hu <mingkai.hu@nxp.com>; M.h. Lian <minghuan.lian@nxp.com>;
> Xiaowei Bao <xiaowei.bao@nxp.com>
> Subject: Re: [PATCHv5 18/20] PCI: mobiveil: Disable IB and OB windows set
> by bootloader
> 
> On Sat, Jun 15, 2019 at 05:03:33AM +0000, Z.q. Hou wrote:
> > Hi Lorenzo,
> >
> > > -----Original Message-----
> > > From: Lorenzo Pieralisi [mailto:lorenzo.pieralisi@arm.com]
> > > Sent: 2019年6月13日 0:24
> > > To: Z.q. Hou <zhiqiang.hou@nxp.com>; bhelgaas@google.com
> > > Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> > > devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> > > robh+dt@kernel.org; mark.rutland@arm.com;
> > > robh+l.subrahmanya@mobiveil.co.in;
> > > shawnguo@kernel.org; Leo Li <leoyang.li@nxp.com>;
> > > catalin.marinas@arm.com; will.deacon@arm.com; Mingkai Hu
> > > <mingkai.hu@nxp.com>; M.h. Lian <minghuan.lian@nxp.com>; Xiaowei
> Bao
> > > <xiaowei.bao@nxp.com>
> > > Subject: Re: [PATCHv5 18/20] PCI: mobiveil: Disable IB and OB
> > > windows set by bootloader
> > >
> > > On Fri, Apr 12, 2019 at 08:37:00AM +0000, Z.q. Hou wrote:
> > > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > >
> > > > Disable all inbound and outbound windows before set up the windows
> > > > in kernel, in case transactions match the window set by bootloader.
> > >
> > > There must be no PCI transactions ongoing at bootloader<->OS handover.
> > >
> >
> > Yes, exact.
> >
> > > The bootloader needs fixing and this patch should be dropped, the
> > > host bridge driver assumes the host bridge state is disabled,
> >
> > The host bridge driver should not assumes the host state is disabled,
> > actually u-boot enable/initialize the host and without disabling it
> > when transfer the control to Linux.
> 
> Fix the bootloader and drop this patch, I explain to you why.

This patch is just to avoid uboot driver windows setup and Linux driver windows
setup overlap issue, please drop it if you don't think it's needed 😊.

Thanks,
Zhiqiang

> 
> > > it will program the bridge
> > > apertures from scratch with no ongoing transactions, anything
> > > deviating from this behaviour is a bootloader bug and a recipe for disaster.
> >
> > The point of this patch is not to fix the ongoing transaction issue,
> > it is to avoid a potential issue which is caused by the outbound
> > window enabled by bootloader overlapping with Linux enabled.
> 
> See above.
> 
> Lorenzo
> 
> > Thanks,
> > Zhiqiang
> >
> > > Lorenzo
> > >
> > > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > > Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> > > > Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
> > > > ---
> > > > V5:
> > > >  - No functionality change.
> > > >
> > > >  drivers/pci/controller/pcie-mobiveil.c | 25
> > > > +++++++++++++++++++++++++
> > > >  1 file changed, 25 insertions(+)
> > > >
> > > > diff --git a/drivers/pci/controller/pcie-mobiveil.c
> > > > b/drivers/pci/controller/pcie-mobiveil.c
> > > > index 8dc87c7a600e..411e9779da12 100644
> > > > --- a/drivers/pci/controller/pcie-mobiveil.c
> > > > +++ b/drivers/pci/controller/pcie-mobiveil.c
> > > > @@ -565,6 +565,24 @@ static int mobiveil_bringup_link(struct
> > > mobiveil_pcie *pcie)
> > > >  	return -ETIMEDOUT;
> > > >  }
> > > >
> > > > +static void mobiveil_pcie_disable_ib_win(struct mobiveil_pcie
> > > > +*pcie, int idx) {
> > > > +	u32 val;
> > > > +
> > > > +	val = csr_readl(pcie, PAB_PEX_AMAP_CTRL(idx));
> > > > +	val &= ~(1 << AMAP_CTRL_EN_SHIFT);
> > > > +	csr_writel(pcie, val, PAB_PEX_AMAP_CTRL(idx)); }
> > > > +
> > > > +static void mobiveil_pcie_disable_ob_win(struct mobiveil_pcie
> > > > +*pcie, int idx) {
> > > > +	u32 val;
> > > > +
> > > > +	val = csr_readl(pcie, PAB_AXI_AMAP_CTRL(idx));
> > > > +	val &= ~(1 << WIN_ENABLE_SHIFT);
> > > > +	csr_writel(pcie, val, PAB_AXI_AMAP_CTRL(idx)); }
> > > > +
> > > >  static void mobiveil_pcie_enable_msi(struct mobiveil_pcie *pcie)  {
> > > >  	phys_addr_t msg_addr = pcie->pcie_reg_base; @@ -585,6 +603,13
> @@
> > > > static int mobiveil_host_init(struct mobiveil_pcie *pcie)  {
> > > >  	u32 value, pab_ctrl, type;
> > > >  	struct resource_entry *win;
> > > > +	int i;
> > > > +
> > > > +	/* Disable all inbound/outbound windows */
> > > > +	for (i = 0; i < pcie->apio_wins; i++)
> > > > +		mobiveil_pcie_disable_ob_win(pcie, i);
> > > > +	for (i = 0; i < pcie->ppio_wins; i++)
> > > > +		mobiveil_pcie_disable_ib_win(pcie, i);
> > > >
> > > >  	/* setup bus numbers */
> > > >  	value = csr_readl(pcie, PCI_PRIMARY_BUS);
> > > > --
> > > > 2.17.1
> > > >

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCHv5 10/20] PCI: mobiveil: Fix the INTx process errors
  2019-06-14 10:43       ` Lorenzo Pieralisi
@ 2019-06-19  5:28         ` Karthikeyan Mitran
  2019-06-19  7:24           ` Z.q. Hou
  0 siblings, 1 reply; 67+ messages in thread
From: Karthikeyan Mitran @ 2019-06-19  5:28 UTC (permalink / raw)
  To: Lorenzo Pieralisi
  Cc: Z.q. Hou, linux-pci, linux-arm-kernel, devicetree, linux-kernel,
	bhelgaas, robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	catalin.marinas, will.deacon, Mingkai Hu, M.h. Lian, Xiaowei Bao

On Fri, Jun 14, 2019 at 4:14 PM Lorenzo Pieralisi
<lorenzo.pieralisi@arm.com> wrote:
>
> On Fri, Jun 14, 2019 at 12:38:51PM +0530, Karthikeyan Mitran wrote:
> > Hi Lorenzo and Hou Zhiqiang
> >  PAB_INTP_AMBA_MISC_STAT does have other status in the higher bits, it
> > should have been masked before checking for the status
>
> You are the maintainer for this driver, so if there is something to be
> changed you must post a patch to that extent, I do not understand what
> the above means, write the code to fix it, I won't do it.
>
> I am getting a bit annoyed with this Mobiveil driver so either you guys
> sort this out or I will have to remove it from the kernel.
>
> > Acked-by: Karthikeyan Mitran <m.karthikeyan@mobiveil.co.in>
>
> Ok I assume this means you tested it but according to what you
> say above, are there still issues with this code path ? Should
> we update the patch ?
Tested-by: Karthikeyan Mitran <m.karthikeyan@mobiveil.co.in>
This patch fixes the INTx status extraction and handling,
I don't see any need to update this patch.
>
> Moreover:
>
> https://kernelnewbies.org/PatchCulture
>
> Please read it and never top-post.
Thank you very much, for the information.

>
> Thanks,
> Lorenzo
>
> > On Wed, Jun 12, 2019 at 8:38 PM Lorenzo Pieralisi
> > <lorenzo.pieralisi@arm.com> wrote:
> > >
> > > On Fri, Apr 12, 2019 at 08:36:12AM +0000, Z.q. Hou wrote:
> > > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > >
> > > > In the loop block, there is not code to update the loop key,
> > > > this patch updates the loop key by re-read the INTx status
> > > > register.
> > > >
> > > > This patch also add the clearing of the handled INTx status.
> > > >
> > > > Note: Need MV to test this fix.
> > >
> > > This means INTX were never tested and current code handling them is,
> > > AFAICS, an infinite loop which is very very bad.
> > >
> > > This is a gross bug and must be fixed as soon as possible.
> > >
> > > I want Karthikeyan ACK and Tested-by on this patch.
> > >
> > > Lorenzo
> > >
> > > > Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver")
> > > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > > Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> > > > Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
> > > > ---
> > > > V5:
> > > >  - Corrected and retouched the subject and changelog.
> > > >
> > > >  drivers/pci/controller/pcie-mobiveil.c | 13 +++++++++----
> > > >  1 file changed, 9 insertions(+), 4 deletions(-)
> > > >
> > > > diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c
> > > > index 4ba458474e42..78e575e71f4d 100644
> > > > --- a/drivers/pci/controller/pcie-mobiveil.c
> > > > +++ b/drivers/pci/controller/pcie-mobiveil.c
> > > > @@ -361,6 +361,7 @@ static void mobiveil_pcie_isr(struct irq_desc *desc)
> > > >       /* Handle INTx */
> > > >       if (intr_status & PAB_INTP_INTX_MASK) {
> > > >               shifted_status = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT);
> > > > +             shifted_status &= PAB_INTP_INTX_MASK;
> > > >               shifted_status >>= PAB_INTX_START;
> > > >               do {
> > > >                       for_each_set_bit(bit, &shifted_status, PCI_NUM_INTX) {
> > > > @@ -372,12 +373,16 @@ static void mobiveil_pcie_isr(struct irq_desc *desc)
> > > >                                       dev_err_ratelimited(dev, "unexpected IRQ, INT%d\n",
> > > >                                                           bit);
> > > >
> > > > -                             /* clear interrupt */
> > > > -                             csr_writel(pcie,
> > > > -                                        shifted_status << PAB_INTX_START,
> > > > +                             /* clear interrupt handled */
> > > > +                             csr_writel(pcie, 1 << (PAB_INTX_START + bit),
> > > >                                          PAB_INTP_AMBA_MISC_STAT);
> > > >                       }
> > > > -             } while ((shifted_status >> PAB_INTX_START) != 0);
> > > > +
> > > > +                     shifted_status = csr_readl(pcie,
> > > > +                                                PAB_INTP_AMBA_MISC_STAT);
> > > > +                     shifted_status &= PAB_INTP_INTX_MASK;
> > > > +                     shifted_status >>= PAB_INTX_START;
> > > > +             } while (shifted_status != 0);
> > > >       }
> > > >
> > > >       /* read extra MSI status register */
> > > > --
> > > > 2.17.1
> > > >
> >
> >
> >
> >

-- 
Mobiveil INC., CONFIDENTIALITY NOTICE: This e-mail message, including any 
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sender and destroy all copies and the original message.

^ permalink raw reply	[flat|nested] 67+ messages in thread

* RE: [PATCHv5 10/20] PCI: mobiveil: Fix the INTx process errors
  2019-06-19  5:28         ` Karthikeyan Mitran
@ 2019-06-19  7:24           ` Z.q. Hou
  0 siblings, 0 replies; 67+ messages in thread
From: Z.q. Hou @ 2019-06-19  7:24 UTC (permalink / raw)
  To: Karthikeyan Mitran, Lorenzo Pieralisi
  Cc: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	catalin.marinas, will.deacon, Mingkai Hu, M.h. Lian, Xiaowei Bao

Hi Karthikeyan,

> -----Original Message-----
> From: Karthikeyan Mitran [mailto:m.karthikeyan@mobiveil.co.in]
> Sent: 2019年6月19日 13:29
> To: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Cc: Z.q. Hou <zhiqiang.hou@nxp.com>; linux-pci@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; devicetree@vger.kernel.org;
> linux-kernel@vger.kernel.org; bhelgaas@google.com; robh+dt@kernel.org;
> mark.rutland@arm.com; l.subrahmanya@mobiveil.co.in;
> shawnguo@kernel.org; Leo Li <leoyang.li@nxp.com>;
> catalin.marinas@arm.com; will.deacon@arm.com; Mingkai Hu
> <mingkai.hu@nxp.com>; M.h. Lian <minghuan.lian@nxp.com>; Xiaowei Bao
> <xiaowei.bao@nxp.com>
> Subject: Re: [PATCHv5 10/20] PCI: mobiveil: Fix the INTx process errors
> 
> On Fri, Jun 14, 2019 at 4:14 PM Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> wrote:
> >
> > On Fri, Jun 14, 2019 at 12:38:51PM +0530, Karthikeyan Mitran wrote:
> > > Hi Lorenzo and Hou Zhiqiang
> > >  PAB_INTP_AMBA_MISC_STAT does have other status in the higher bits,
> > > it should have been masked before checking for the status
> >
> > You are the maintainer for this driver, so if there is something to be
> > changed you must post a patch to that extent, I do not understand what
> > the above means, write the code to fix it, I won't do it.
> >
> > I am getting a bit annoyed with this Mobiveil driver so either you
> > guys sort this out or I will have to remove it from the kernel.
> >
> > > Acked-by: Karthikeyan Mitran <m.karthikeyan@mobiveil.co.in>
> >
> > Ok I assume this means you tested it but according to what you say
> > above, are there still issues with this code path ? Should we update
> > the patch ?
> Tested-by: Karthikeyan Mitran <m.karthikeyan@mobiveil.co.in> This patch
> fixes the INTx status extraction and handling, I don't see any need to update
> this patch.

Thanks a lot for your test!

Zhiqiang

> >
> > Moreover:
> >
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fkern
> >
> elnewbies.org%2FPatchCulture&amp;data=02%7C01%7Czhiqiang.hou%40nx
> p.com
> > %7C1445570163bb479cae3708d6f47709fb%7C686ea1d3bc2b4c6fa92cd99
> c5c301635
> > %7C0%7C0%7C636965189438647036&amp;sdata=xXQ5MCPuXV08Cd%2Fi
> TBnkAmOVGOsH
> > XFi7e1xcvlYIwiA%3D&amp;reserved=0
> >
> > Please read it and never top-post.
> Thank you very much, for the information.
> 
> >
> > Thanks,
> > Lorenzo
> >
> > > On Wed, Jun 12, 2019 at 8:38 PM Lorenzo Pieralisi
> > > <lorenzo.pieralisi@arm.com> wrote:
> > > >
> > > > On Fri, Apr 12, 2019 at 08:36:12AM +0000, Z.q. Hou wrote:
> > > > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > > >
> > > > > In the loop block, there is not code to update the loop key,
> > > > > this patch updates the loop key by re-read the INTx status
> > > > > register.
> > > > >
> > > > > This patch also add the clearing of the handled INTx status.
> > > > >
> > > > > Note: Need MV to test this fix.
> > > >
> > > > This means INTX were never tested and current code handling them
> > > > is, AFAICS, an infinite loop which is very very bad.
> > > >
> > > > This is a gross bug and must be fixed as soon as possible.
> > > >
> > > > I want Karthikeyan ACK and Tested-by on this patch.
> > > >
> > > > Lorenzo
> > > >
> > > > > Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host
> > > > > Bridge IP driver")
> > > > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > > > Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> > > > > Reviewed-by: Subrahmanya Lingappa
> <l.subrahmanya@mobiveil.co.in>
> > > > > ---
> > > > > V5:
> > > > >  - Corrected and retouched the subject and changelog.
> > > > >
> > > > >  drivers/pci/controller/pcie-mobiveil.c | 13 +++++++++----
> > > > >  1 file changed, 9 insertions(+), 4 deletions(-)
> > > > >
> > > > > diff --git a/drivers/pci/controller/pcie-mobiveil.c
> > > > > b/drivers/pci/controller/pcie-mobiveil.c
> > > > > index 4ba458474e42..78e575e71f4d 100644
> > > > > --- a/drivers/pci/controller/pcie-mobiveil.c
> > > > > +++ b/drivers/pci/controller/pcie-mobiveil.c
> > > > > @@ -361,6 +361,7 @@ static void mobiveil_pcie_isr(struct irq_desc
> *desc)
> > > > >       /* Handle INTx */
> > > > >       if (intr_status & PAB_INTP_INTX_MASK) {
> > > > >               shifted_status = csr_readl(pcie,
> > > > > PAB_INTP_AMBA_MISC_STAT);
> > > > > +             shifted_status &= PAB_INTP_INTX_MASK;
> > > > >               shifted_status >>= PAB_INTX_START;
> > > > >               do {
> > > > >                       for_each_set_bit(bit, &shifted_status,
> > > > > PCI_NUM_INTX) { @@ -372,12 +373,16 @@ static void
> mobiveil_pcie_isr(struct irq_desc *desc)
> > > > >
> dev_err_ratelimited(dev, "unexpected IRQ, INT%d\n",
> > > > >
> bit);
> > > > >
> > > > > -                             /* clear interrupt */
> > > > > -                             csr_writel(pcie,
> > > > > -                                        shifted_status <<
> PAB_INTX_START,
> > > > > +                             /* clear interrupt handled */
> > > > > +                             csr_writel(pcie, 1 <<
> > > > > + (PAB_INTX_START + bit),
> > > > >
> PAB_INTP_AMBA_MISC_STAT);
> > > > >                       }
> > > > > -             } while ((shifted_status >> PAB_INTX_START) != 0);
> > > > > +
> > > > > +                     shifted_status = csr_readl(pcie,
> > > > > +
> PAB_INTP_AMBA_MISC_STAT);
> > > > > +                     shifted_status &= PAB_INTP_INTX_MASK;
> > > > > +                     shifted_status >>= PAB_INTX_START;
> > > > > +             } while (shifted_status != 0);
> > > > >       }
> > > > >
> > > > >       /* read extra MSI status register */
> > > > > --
> > > > > 2.17.1
> > > > >
> > >
> > >
> > >
> > >
> 
> --
> Mobiveil INC., CONFIDENTIALITY NOTICE: This e-mail message, including any
> attachments, is for the sole use of the intended recipient(s) and may contain
> proprietary confidential or privileged information or otherwise be protected
> by law. Any unauthorized review, use, disclosure or distribution is prohibited. If
> you are not the intended recipient, please notify the sender and destroy all
> copies and the original message.

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCHv5 04/20] PCI: mobiveil: Remove the flag MSI_FLAG_MULTI_PCI_MSI
  2019-06-17 10:34             ` Z.q. Hou
@ 2019-06-28 11:35               ` Lorenzo Pieralisi
  2019-07-01 10:07                 ` Z.q. Hou
  0 siblings, 1 reply; 67+ messages in thread
From: Lorenzo Pieralisi @ 2019-06-28 11:35 UTC (permalink / raw)
  To: Z.q. Hou
  Cc: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	catalin.marinas, will.deacon, Mingkai Hu, M.h. Lian, Xiaowei Bao

On Mon, Jun 17, 2019 at 10:34:35AM +0000, Z.q. Hou wrote:

[...]

> > There is nothing obvious. Write what you are fixing in the commit log and I will
> > apply the patch, I won't write the commit log for you. Anyone should be able
> > to understand why a patch was needed by reading the commit log, it is as
> > important as writing the code itself.
> 
> With the flag MSI_FLAG_MULTI_PCI_MSI, when the Endpoint allocates
> multiple MSI, it will trigger the "WARN_ON(nr_irqs != 1);" in
> mobiveil_irq_msi_domain_alloc(), this is the issue this patch want to
> fix. 

And that's wrong. Marc explained why this controller does not support
Multi MSI and that's what should go in the commit log, triggering
a WARN_ON is the least of the problems (and the WARN_ON can even
be removed after this patch is applied), if it was used as a bandaid
to prevent allocating Multi MSI it is even more broken.

Lorenzo

> Thanks,
> Zhiqiang
> 
> > 
> > Thanks,
> > Lorenzo
> > 
> > > Thanks,
> > > Zhiqiang
> > >
> > > >
> > > > Lorenzo
> > > >
> > > > > Subbu, did you test with Endpoint supporting multi MSI?
> > > > >
> > > > > Thanks,
> > > > > Zhiqiang
> > > > >
> > > > > >
> > > > > > Thanks,
> > > > > > Lorenzo
> > > > > >
> > > > > > > Fixes: 1e913e58335f ("PCI: mobiveil: Add MSI support")
> > > > > > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > > > > > Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> > > > > > > ---
> > > > > > > V5:
> > > > > > >  - Corrected the subject.
> > > > > > >
> > > > > > >  drivers/pci/controller/pcie-mobiveil.c | 2 +-
> > > > > > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > > > > > >
> > > > > > > diff --git a/drivers/pci/controller/pcie-mobiveil.c
> > > > > > > b/drivers/pci/controller/pcie-mobiveil.c
> > > > > > > index 563210e731d3..a0dd337c6214 100644
> > > > > > > --- a/drivers/pci/controller/pcie-mobiveil.c
> > > > > > > +++ b/drivers/pci/controller/pcie-mobiveil.c
> > > > > > > @@ -703,7 +703,7 @@ static struct irq_chip
> > > > > > > mobiveil_msi_irq_chip = {
> > > > > > >
> > > > > > >  static struct msi_domain_info mobiveil_msi_domain_info = {
> > > > > > >  	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS |
> > > > > > MSI_FLAG_USE_DEF_CHIP_OPS |
> > > > > > > -		   MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX),
> > > > > > > +		   MSI_FLAG_PCI_MSIX),
> > > > > > >  	.chip	= &mobiveil_msi_irq_chip,
> > > > > > >  };
> > > > > > >
> > > > > > > --
> > > > > > > 2.17.1
> > > > > > >

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCHv5 08/20] PCI: mobiveil: Use the 1st inbound window for MEM inbound transactions
  2019-04-12  8:36 ` [PATCHv5 08/20] PCI: mobiveil: Use the 1st inbound window for MEM inbound transactions Z.q. Hou
@ 2019-06-28 16:02   ` Lorenzo Pieralisi
  2019-07-01 10:18     ` Z.q. Hou
  0 siblings, 1 reply; 67+ messages in thread
From: Lorenzo Pieralisi @ 2019-06-28 16:02 UTC (permalink / raw)
  To: Z.q. Hou
  Cc: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	catalin.marinas, will.deacon, Mingkai Hu, M.h. Lian, Xiaowei Bao

On Fri, Apr 12, 2019 at 08:36:00AM +0000, Z.q. Hou wrote:
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> 
> The inbound windows have independent register set against outbound windows.
> This patch change the MEM inbound window to the first one.

You mean that windows 0 can be used as well as window 1 for inbound
windows so it is better to opt for window 0 for consistency ?

Lorenzo

> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
> ---
> V5:
>  - Corrected and retouched the subject and changelog.
> 
>  drivers/pci/controller/pcie-mobiveil.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c
> index df71c11b4810..e88afc792a5c 100644
> --- a/drivers/pci/controller/pcie-mobiveil.c
> +++ b/drivers/pci/controller/pcie-mobiveil.c
> @@ -616,7 +616,7 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
>  			   CFG_WINDOW_TYPE, resource_size(pcie->ob_io_res));
>  
>  	/* memory inbound translation window */
> -	program_ib_windows(pcie, WIN_NUM_1, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE);
> +	program_ib_windows(pcie, WIN_NUM_0, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE);
>  
>  	/* Get the I/O and memory ranges from DT */
>  	resource_list_for_each_entry(win, &pcie->resources) {
> -- 
> 2.17.1
> 

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCHv5 09/20] PCI: mobiveil: Correct inbound/outbound window setup routines
  2019-04-12  8:36 ` [PATCHv5 09/20] PCI: mobiveil: Correct inbound/outbound window setup routines Z.q. Hou
@ 2019-06-28 16:41   ` Lorenzo Pieralisi
  2019-07-01 10:24     ` Z.q. Hou
  0 siblings, 1 reply; 67+ messages in thread
From: Lorenzo Pieralisi @ 2019-06-28 16:41 UTC (permalink / raw)
  To: Z.q. Hou
  Cc: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	catalin.marinas, will.deacon, Mingkai Hu, M.h. Lian, Xiaowei Bao

On Fri, Apr 12, 2019 at 08:36:06AM +0000, Z.q. Hou wrote:
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> 
> Outbound window routine:
>  - Remove unused var definitions and register read operations.
>  - Add the upper 32-bit cpu address setup of the window.
>  - Instead of blindly write, only change the fields specified.
>  - Mask the lower bits of window size in case override the
>    control bits.
>  - Check if the passing window number is available, instead of
>    the total number of the initialized windows.
> 
> Inbound window routine:
>  - Add parameter 'u64 cpu_addr' to specify the cpu address
>    of the window instead of using 'pci_addr'.
>  - Change 'int pci_addr' to 'u64 pci_addr', and add setup
>    of the upper 32-bit PCI address of the window.
>  - Move the PCIe PIO master enablement to mobiveil_host_init().
>  - Instead of blindly write, only change the fields specified.
>  - Mask the lower bits of window size in case override the
>    control bits.
>  - Check if the passing window number is available, instead of
>    the total number of the initialized windows.
>  - And add the statistic of initialized inbound windows.
> 
> Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver")
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
> ---
> V5:
>  - Corrected and retouched the subject and changelog.
> 
>  drivers/pci/controller/pcie-mobiveil.c | 70 +++++++++++++++-----------
>  1 file changed, 42 insertions(+), 28 deletions(-)

There are two things to be done here:

1) Separate fixes from refactoring
2) Each fix should be standalone and solve one problem only

The commit log is a list of changes, some of which I can't
parse.

You should split this patch as described above and repost it
separately but first I will try to merge what I can from this
series, do not repost as yet.

Thanks,
Lorenzo

> diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c
> index e88afc792a5c..4ba458474e42 100644
> --- a/drivers/pci/controller/pcie-mobiveil.c
> +++ b/drivers/pci/controller/pcie-mobiveil.c
> @@ -65,9 +65,13 @@
>  #define PAB_AXI_AMAP_CTRL(win)		PAB_REG_ADDR(0x0ba0, win)
>  #define  WIN_ENABLE_SHIFT		0
>  #define  WIN_TYPE_SHIFT			1
> +#define  WIN_TYPE_MASK			0x3
> +#define  WIN_SIZE_SHIFT			10
> +#define  WIN_SIZE_MASK			0x3fffff
>  
>  #define PAB_EXT_AXI_AMAP_SIZE(win)	PAB_EXT_REG_ADDR(0xbaf0, win)
>  
> +#define PAB_EXT_AXI_AMAP_AXI_WIN(win)	PAB_EXT_REG_ADDR(0x80a0, win)
>  #define PAB_AXI_AMAP_AXI_WIN(win)	PAB_REG_ADDR(0x0ba4, win)
>  #define  AXI_WINDOW_ALIGN_MASK		3
>  
> @@ -82,8 +86,10 @@
>  #define PAB_PEX_AMAP_CTRL(win)		PAB_REG_ADDR(0x4ba0, win)
>  #define  AMAP_CTRL_EN_SHIFT		0
>  #define  AMAP_CTRL_TYPE_SHIFT		1
> +#define  AMAP_CTRL_TYPE_MASK		3
>  
>  #define PAB_EXT_PEX_AMAP_SIZEN(win)	PAB_EXT_REG_ADDR(0xbef0, win)
> +#define PAB_EXT_PEX_AMAP_AXI_WIN(win)	PAB_EXT_REG_ADDR(0xb4a0, win)
>  #define PAB_PEX_AMAP_AXI_WIN(win)	PAB_REG_ADDR(0x4ba4, win)
>  #define PAB_PEX_AMAP_PEX_WIN_L(win)	PAB_REG_ADDR(0x4ba8, win)
>  #define PAB_PEX_AMAP_PEX_WIN_H(win)	PAB_REG_ADDR(0x4bac, win)
> @@ -455,49 +461,51 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie)
>  }
>  
>  static void program_ib_windows(struct mobiveil_pcie *pcie, int win_num,
> -			       int pci_addr, u32 type, u64 size)
> +			       u64 cpu_addr, u64 pci_addr, u32 type, u64 size)
>  {
> -	int pio_ctrl_val;
> -	int amap_ctrl_dw;
> +	u32 value;
>  	u64 size64 = ~(size - 1);
>  
> -	if ((pcie->ib_wins_configured + 1) > pcie->ppio_wins) {
> +	if (win_num >= pcie->ppio_wins) {
>  		dev_err(&pcie->pdev->dev,
>  			"ERROR: max inbound windows reached !\n");
>  		return;
>  	}
>  
> -	pio_ctrl_val = csr_readl(pcie, PAB_PEX_PIO_CTRL);
> -	pio_ctrl_val |= 1 << PIO_ENABLE_SHIFT;
> -	csr_writel(pcie, pio_ctrl_val, PAB_PEX_PIO_CTRL);
> -
> -	amap_ctrl_dw = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
> -	amap_ctrl_dw |= (type << AMAP_CTRL_TYPE_SHIFT) |
> -			(1 << AMAP_CTRL_EN_SHIFT) |
> -			lower_32_bits(size64);
> -	csr_writel(pcie, amap_ctrl_dw, PAB_PEX_AMAP_CTRL(win_num));
> +	value = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
> +	value &= ~(AMAP_CTRL_TYPE_MASK << AMAP_CTRL_TYPE_SHIFT |
> +		 WIN_SIZE_MASK << WIN_SIZE_SHIFT);
> +	value |= (type << AMAP_CTRL_TYPE_SHIFT) | (1 << AMAP_CTRL_EN_SHIFT) |
> +		 (lower_32_bits(size64) & WIN_SIZE_MASK << WIN_SIZE_SHIFT);
> +	csr_writel(pcie, value, PAB_PEX_AMAP_CTRL(win_num));
>  
>  	csr_writel(pcie, upper_32_bits(size64),
>  		   PAB_EXT_PEX_AMAP_SIZEN(win_num));
>  
> -	csr_writel(pcie, pci_addr, PAB_PEX_AMAP_AXI_WIN(win_num));
> +	csr_writel(pcie, lower_32_bits(cpu_addr),
> +		   PAB_PEX_AMAP_AXI_WIN(win_num));
> +	csr_writel(pcie, upper_32_bits(cpu_addr),
> +		   PAB_EXT_PEX_AMAP_AXI_WIN(win_num));
> +
> +	csr_writel(pcie, lower_32_bits(pci_addr),
> +		   PAB_PEX_AMAP_PEX_WIN_L(win_num));
> +	csr_writel(pcie, upper_32_bits(pci_addr),
> +		   PAB_PEX_AMAP_PEX_WIN_H(win_num));
>  
> -	csr_writel(pcie, pci_addr, PAB_PEX_AMAP_PEX_WIN_L(win_num));
> -	csr_writel(pcie, 0, PAB_PEX_AMAP_PEX_WIN_H(win_num));
> +	pcie->ib_wins_configured++;
>  }
>  
>  /*
>   * routine to program the outbound windows
>   */
>  static void program_ob_windows(struct mobiveil_pcie *pcie, int win_num,
> -			       u64 cpu_addr, u64 pci_addr,
> -			       u32 config_io_bit, u64 size)
> +			       u64 cpu_addr, u64 pci_addr, u32 type, u64 size)
>  {
>  
> -	u32 value, type;
> +	u32 value;
>  	u64 size64 = ~(size - 1);
>  
> -	if ((pcie->ob_wins_configured + 1) > pcie->apio_wins) {
> +	if (win_num >= pcie->apio_wins) {
>  		dev_err(&pcie->pdev->dev,
>  			"ERROR: max outbound windows reached !\n");
>  		return;
> @@ -507,10 +515,12 @@ static void program_ob_windows(struct mobiveil_pcie *pcie, int win_num,
>  	 * program Enable Bit to 1, Type Bit to (00) base 2, AXI Window Size Bit
>  	 * to 4 KB in PAB_AXI_AMAP_CTRL register
>  	 */
> -	type = config_io_bit;
>  	value = csr_readl(pcie, PAB_AXI_AMAP_CTRL(win_num));
> -	csr_writel(pcie, 1 << WIN_ENABLE_SHIFT | type << WIN_TYPE_SHIFT |
> -		   lower_32_bits(size64), PAB_AXI_AMAP_CTRL(win_num));
> +	value &= ~(WIN_TYPE_MASK << WIN_TYPE_SHIFT |
> +		 WIN_SIZE_MASK << WIN_SIZE_SHIFT);
> +	value |= 1 << WIN_ENABLE_SHIFT | type << WIN_TYPE_SHIFT |
> +		 (lower_32_bits(size64) & WIN_SIZE_MASK << WIN_SIZE_SHIFT);
> +	csr_writel(pcie, value, PAB_AXI_AMAP_CTRL(win_num));
>  
>  	csr_writel(pcie, upper_32_bits(size64), PAB_EXT_AXI_AMAP_SIZE(win_num));
>  
> @@ -518,11 +528,10 @@ static void program_ob_windows(struct mobiveil_pcie *pcie, int win_num,
>  	 * program AXI window base with appropriate value in
>  	 * PAB_AXI_AMAP_AXI_WIN0 register
>  	 */
> -	value = csr_readl(pcie, PAB_AXI_AMAP_AXI_WIN(win_num));
> -	csr_writel(pcie, cpu_addr & (~AXI_WINDOW_ALIGN_MASK),
> +	csr_writel(pcie, lower_32_bits(cpu_addr) & (~AXI_WINDOW_ALIGN_MASK),
>  		   PAB_AXI_AMAP_AXI_WIN(win_num));
> -
> -	value = csr_readl(pcie, PAB_AXI_AMAP_PEX_WIN_H(win_num));
> +	csr_writel(pcie, upper_32_bits(cpu_addr),
> +		   PAB_EXT_AXI_AMAP_AXI_WIN(win_num));
>  
>  	csr_writel(pcie, lower_32_bits(pci_addr),
>  		   PAB_AXI_AMAP_PEX_WIN_L(win_num));
> @@ -604,6 +613,11 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
>  	value |= APIO_EN_MASK;
>  	csr_writel(pcie, value, PAB_AXI_PIO_CTRL);
>  
> +	/* Enable PCIe PIO master */
> +	value = csr_readl(pcie, PAB_PEX_PIO_CTRL);
> +	value |= 1 << PIO_ENABLE_SHIFT;
> +	csr_writel(pcie, value, PAB_PEX_PIO_CTRL);
> +
>  	/*
>  	 * we'll program one outbound window for config reads and
>  	 * another default inbound window for all the upstream traffic
> @@ -616,7 +630,7 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
>  			   CFG_WINDOW_TYPE, resource_size(pcie->ob_io_res));
>  
>  	/* memory inbound translation window */
> -	program_ib_windows(pcie, WIN_NUM_0, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE);
> +	program_ib_windows(pcie, WIN_NUM_0, 0, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE);
>  
>  	/* Get the I/O and memory ranges from DT */
>  	resource_list_for_each_entry(win, &pcie->resources) {
> -- 
> 2.17.1
> 

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCHv5 10/20] PCI: mobiveil: Fix the INTx process errors
  2019-04-12  8:36 ` [PATCHv5 10/20] PCI: mobiveil: Fix the INTx process errors Z.q. Hou
  2019-06-12 15:08   ` Lorenzo Pieralisi
@ 2019-06-28 17:05   ` Lorenzo Pieralisi
  2019-07-01 10:27     ` Z.q. Hou
  1 sibling, 1 reply; 67+ messages in thread
From: Lorenzo Pieralisi @ 2019-06-28 17:05 UTC (permalink / raw)
  To: Z.q. Hou
  Cc: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	catalin.marinas, will.deacon, Mingkai Hu, M.h. Lian, Xiaowei Bao

On Fri, Apr 12, 2019 at 08:36:12AM +0000, Z.q. Hou wrote:
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> 
> In the loop block, there is not code to update the loop key,
> this patch updates the loop key by re-read the INTx status
> register.
> 
> This patch also add the clearing of the handled INTx status.

This is two bugs and that requires two patches, each of them fixing a
specific issue.

So split the patch into two and repost it.

Lorenzo

> Note: Need MV to test this fix.
> 
> Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver")
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
> ---
> V5:
>  - Corrected and retouched the subject and changelog.
> 
>  drivers/pci/controller/pcie-mobiveil.c | 13 +++++++++----
>  1 file changed, 9 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c
> index 4ba458474e42..78e575e71f4d 100644
> --- a/drivers/pci/controller/pcie-mobiveil.c
> +++ b/drivers/pci/controller/pcie-mobiveil.c
> @@ -361,6 +361,7 @@ static void mobiveil_pcie_isr(struct irq_desc *desc)
>  	/* Handle INTx */
>  	if (intr_status & PAB_INTP_INTX_MASK) {
>  		shifted_status = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT);
> +		shifted_status &= PAB_INTP_INTX_MASK;
>  		shifted_status >>= PAB_INTX_START;
>  		do {
>  			for_each_set_bit(bit, &shifted_status, PCI_NUM_INTX) {
> @@ -372,12 +373,16 @@ static void mobiveil_pcie_isr(struct irq_desc *desc)
>  					dev_err_ratelimited(dev, "unexpected IRQ, INT%d\n",
>  							    bit);
>  
> -				/* clear interrupt */
> -				csr_writel(pcie,
> -					   shifted_status << PAB_INTX_START,
> +				/* clear interrupt handled */
> +				csr_writel(pcie, 1 << (PAB_INTX_START + bit),
>  					   PAB_INTP_AMBA_MISC_STAT);
>  			}
> -		} while ((shifted_status >> PAB_INTX_START) != 0);
> +
> +			shifted_status = csr_readl(pcie,
> +						   PAB_INTP_AMBA_MISC_STAT);
> +			shifted_status &= PAB_INTP_INTX_MASK;
> +			shifted_status >>= PAB_INTX_START;
> +		} while (shifted_status != 0);
>  	}
>  
>  	/* read extra MSI status register */
> -- 
> 2.17.1
> 

^ permalink raw reply	[flat|nested] 67+ messages in thread

* RE: [PATCHv5 04/20] PCI: mobiveil: Remove the flag MSI_FLAG_MULTI_PCI_MSI
  2019-06-28 11:35               ` Lorenzo Pieralisi
@ 2019-07-01 10:07                 ` Z.q. Hou
  0 siblings, 0 replies; 67+ messages in thread
From: Z.q. Hou @ 2019-07-01 10:07 UTC (permalink / raw)
  To: Lorenzo Pieralisi
  Cc: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	catalin.marinas, will.deacon, Mingkai Hu, M.h. Lian, Xiaowei Bao

Hi Lorenzo,

Thanks a lot for your comments!

> -----Original Message-----
> From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Sent: 2019年6月28日 19:36
> To: Z.q. Hou <zhiqiang.hou@nxp.com>
> Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> bhelgaas@google.com; robh+dt@kernel.org; mark.rutland@arm.com;
> l.subrahmanya@mobiveil.co.in; shawnguo@kernel.org; Leo Li
> <leoyang.li@nxp.com>; catalin.marinas@arm.com; will.deacon@arm.com;
> Mingkai Hu <mingkai.hu@nxp.com>; M.h. Lian <minghuan.lian@nxp.com>;
> Xiaowei Bao <xiaowei.bao@nxp.com>
> Subject: Re: [PATCHv5 04/20] PCI: mobiveil: Remove the flag
> MSI_FLAG_MULTI_PCI_MSI
> 
> On Mon, Jun 17, 2019 at 10:34:35AM +0000, Z.q. Hou wrote:
> 
> [...]
> 
> > > There is nothing obvious. Write what you are fixing in the commit
> > > log and I will apply the patch, I won't write the commit log for
> > > you. Anyone should be able to understand why a patch was needed by
> > > reading the commit log, it is as important as writing the code itself.
> >
> > With the flag MSI_FLAG_MULTI_PCI_MSI, when the Endpoint allocates
> > multiple MSI, it will trigger the "WARN_ON(nr_irqs != 1);" in
> > mobiveil_irq_msi_domain_alloc(), this is the issue this patch want to
> > fix.
> 
> And that's wrong. Marc explained why this controller does not support Multi
> MSI and that's what should go in the commit log, triggering a WARN_ON is
> the least of the problems (and the WARN_ON can even be removed after
> this patch is applied), if it was used as a bandaid to prevent allocating Multi
> MSI it is even more broken.
>

Yes, I agree, the root cause is hardware limitation, is the following changelog
acceptable?

Changelog:
The Mobiveil internal MSI controller uses separate target address per MSI,
so, it is unable to support Multiple MSI feature, which requires the same
target address and incremental MSI_DATA values. This patch is to remove
the flag MSI_FLAG_MULTI_PCI_MSI.

Thanks,
Zhiqiang
 
> Lorenzo
> 
> > Thanks,
> > Zhiqiang
> >
> > >
> > > Thanks,
> > > Lorenzo
> > >
> > > > Thanks,
> > > > Zhiqiang
> > > >
> > > > >
> > > > > Lorenzo
> > > > >
> > > > > > Subbu, did you test with Endpoint supporting multi MSI?
> > > > > >
> > > > > > Thanks,
> > > > > > Zhiqiang
> > > > > >
> > > > > > >
> > > > > > > Thanks,
> > > > > > > Lorenzo
> > > > > > >
> > > > > > > > Fixes: 1e913e58335f ("PCI: mobiveil: Add MSI support")
> > > > > > > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > > > > > > Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> > > > > > > > ---
> > > > > > > > V5:
> > > > > > > >  - Corrected the subject.
> > > > > > > >
> > > > > > > >  drivers/pci/controller/pcie-mobiveil.c | 2 +-
> > > > > > > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > > > > > > >
> > > > > > > > diff --git a/drivers/pci/controller/pcie-mobiveil.c
> > > > > > > > b/drivers/pci/controller/pcie-mobiveil.c
> > > > > > > > index 563210e731d3..a0dd337c6214 100644
> > > > > > > > --- a/drivers/pci/controller/pcie-mobiveil.c
> > > > > > > > +++ b/drivers/pci/controller/pcie-mobiveil.c
> > > > > > > > @@ -703,7 +703,7 @@ static struct irq_chip
> > > > > > > > mobiveil_msi_irq_chip = {
> > > > > > > >
> > > > > > > >  static struct msi_domain_info mobiveil_msi_domain_info = {
> > > > > > > >  	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS |
> > > > > > > MSI_FLAG_USE_DEF_CHIP_OPS |
> > > > > > > > -		   MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX),
> > > > > > > > +		   MSI_FLAG_PCI_MSIX),
> > > > > > > >  	.chip	= &mobiveil_msi_irq_chip,
> > > > > > > >  };
> > > > > > > >
> > > > > > > > --
> > > > > > > > 2.17.1
> > > > > > > >

^ permalink raw reply	[flat|nested] 67+ messages in thread

* RE: [PATCHv5 08/20] PCI: mobiveil: Use the 1st inbound window for MEM inbound transactions
  2019-06-28 16:02   ` Lorenzo Pieralisi
@ 2019-07-01 10:18     ` Z.q. Hou
  0 siblings, 0 replies; 67+ messages in thread
From: Z.q. Hou @ 2019-07-01 10:18 UTC (permalink / raw)
  To: Lorenzo Pieralisi
  Cc: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	catalin.marinas, will.deacon, Mingkai Hu, M.h. Lian, Xiaowei Bao

Hi Lorenzo,

Thanks a lot for your comments!

> -----Original Message-----
> From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Sent: 2019年6月29日 0:02
> To: Z.q. Hou <zhiqiang.hou@nxp.com>
> Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> bhelgaas@google.com; robh+dt@kernel.org; mark.rutland@arm.com;
> l.subrahmanya@mobiveil.co.in; shawnguo@kernel.org; Leo Li
> <leoyang.li@nxp.com>; catalin.marinas@arm.com; will.deacon@arm.com;
> Mingkai Hu <mingkai.hu@nxp.com>; M.h. Lian <minghuan.lian@nxp.com>;
> Xiaowei Bao <xiaowei.bao@nxp.com>
> Subject: Re: [PATCHv5 08/20] PCI: mobiveil: Use the 1st inbound window for
> MEM inbound transactions
> 
> On Fri, Apr 12, 2019 at 08:36:00AM +0000, Z.q. Hou wrote:
> > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> >
> > The inbound windows have independent register set against outbound
> windows.
> > This patch change the MEM inbound window to the first one.
> 
> You mean that windows 0 can be used as well as window 1 for inbound
> windows so it is better to opt for window 0 for consistency ?

I mean the inbound windows and outbound windows are independent, they
have themselves' registers, and both serial number starts from 0:
Inbound windows: #0, #1, #2...
Outbound windows: #0, #1, #2... 

Thanks,
Zhiqiang

> Lorenzo
> 
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> > Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
> > ---
> > V5:
> >  - Corrected and retouched the subject and changelog.
> >
> >  drivers/pci/controller/pcie-mobiveil.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/pci/controller/pcie-mobiveil.c
> > b/drivers/pci/controller/pcie-mobiveil.c
> > index df71c11b4810..e88afc792a5c 100644
> > --- a/drivers/pci/controller/pcie-mobiveil.c
> > +++ b/drivers/pci/controller/pcie-mobiveil.c
> > @@ -616,7 +616,7 @@ static int mobiveil_host_init(struct mobiveil_pcie
> *pcie)
> >  			   CFG_WINDOW_TYPE, resource_size(pcie->ob_io_res));
> >
> >  	/* memory inbound translation window */
> > -	program_ib_windows(pcie, WIN_NUM_1, 0, MEM_WINDOW_TYPE,
> IB_WIN_SIZE);
> > +	program_ib_windows(pcie, WIN_NUM_0, 0, MEM_WINDOW_TYPE,
> > +IB_WIN_SIZE);
> >
> >  	/* Get the I/O and memory ranges from DT */
> >  	resource_list_for_each_entry(win, &pcie->resources) {
> > --
> > 2.17.1
> >

^ permalink raw reply	[flat|nested] 67+ messages in thread

* RE: [PATCHv5 09/20] PCI: mobiveil: Correct inbound/outbound window setup routines
  2019-06-28 16:41   ` Lorenzo Pieralisi
@ 2019-07-01 10:24     ` Z.q. Hou
  0 siblings, 0 replies; 67+ messages in thread
From: Z.q. Hou @ 2019-07-01 10:24 UTC (permalink / raw)
  To: Lorenzo Pieralisi
  Cc: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	catalin.marinas, will.deacon, Mingkai Hu, M.h. Lian, Xiaowei Bao

Hi Lorenzo,

Thanks a lot for your comments!

> -----Original Message-----
> From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Sent: 2019年6月29日 0:42
> To: Z.q. Hou <zhiqiang.hou@nxp.com>
> Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> bhelgaas@google.com; robh+dt@kernel.org; mark.rutland@arm.com;
> l.subrahmanya@mobiveil.co.in; shawnguo@kernel.org; Leo Li
> <leoyang.li@nxp.com>; catalin.marinas@arm.com; will.deacon@arm.com;
> Mingkai Hu <mingkai.hu@nxp.com>; M.h. Lian <minghuan.lian@nxp.com>;
> Xiaowei Bao <xiaowei.bao@nxp.com>
> Subject: Re: [PATCHv5 09/20] PCI: mobiveil: Correct inbound/outbound
> window setup routines
> 
> On Fri, Apr 12, 2019 at 08:36:06AM +0000, Z.q. Hou wrote:
> > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> >
> > Outbound window routine:
> >  - Remove unused var definitions and register read operations.
> >  - Add the upper 32-bit cpu address setup of the window.
> >  - Instead of blindly write, only change the fields specified.
> >  - Mask the lower bits of window size in case override the
> >    control bits.
> >  - Check if the passing window number is available, instead of
> >    the total number of the initialized windows.
> >
> > Inbound window routine:
> >  - Add parameter 'u64 cpu_addr' to specify the cpu address
> >    of the window instead of using 'pci_addr'.
> >  - Change 'int pci_addr' to 'u64 pci_addr', and add setup
> >    of the upper 32-bit PCI address of the window.
> >  - Move the PCIe PIO master enablement to mobiveil_host_init().
> >  - Instead of blindly write, only change the fields specified.
> >  - Mask the lower bits of window size in case override the
> >    control bits.
> >  - Check if the passing window number is available, instead of
> >    the total number of the initialized windows.
> >  - And add the statistic of initialized inbound windows.
> >
> > Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP
> > driver")
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> > Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
> > ---
> > V5:
> >  - Corrected and retouched the subject and changelog.
> >
> >  drivers/pci/controller/pcie-mobiveil.c | 70
> > +++++++++++++++-----------
> >  1 file changed, 42 insertions(+), 28 deletions(-)
> 
> There are two things to be done here:
> 
> 1) Separate fixes from refactoring
> 2) Each fix should be standalone and solve one problem only
> 
> The commit log is a list of changes, some of which I can't parse.
> 
> You should split this patch as described above and repost it separately but
> first I will try to merge what I can from this series, do not repost as yet.
>

Yes, will split it.

Thanks,
Zhiqiang
 
> Thanks,
> Lorenzo
> 
> > diff --git a/drivers/pci/controller/pcie-mobiveil.c
> > b/drivers/pci/controller/pcie-mobiveil.c
> > index e88afc792a5c..4ba458474e42 100644
> > --- a/drivers/pci/controller/pcie-mobiveil.c
> > +++ b/drivers/pci/controller/pcie-mobiveil.c
> > @@ -65,9 +65,13 @@
> >  #define PAB_AXI_AMAP_CTRL(win)		PAB_REG_ADDR(0x0ba0,
> win)
> >  #define  WIN_ENABLE_SHIFT		0
> >  #define  WIN_TYPE_SHIFT			1
> > +#define  WIN_TYPE_MASK			0x3
> > +#define  WIN_SIZE_SHIFT			10
> > +#define  WIN_SIZE_MASK			0x3fffff
> >
> >  #define PAB_EXT_AXI_AMAP_SIZE(win)	PAB_EXT_REG_ADDR(0xbaf0,
> win)
> >
> > +#define PAB_EXT_AXI_AMAP_AXI_WIN(win)
> 	PAB_EXT_REG_ADDR(0x80a0, win)
> >  #define PAB_AXI_AMAP_AXI_WIN(win)	PAB_REG_ADDR(0x0ba4, win)
> >  #define  AXI_WINDOW_ALIGN_MASK		3
> >
> > @@ -82,8 +86,10 @@
> >  #define PAB_PEX_AMAP_CTRL(win)		PAB_REG_ADDR(0x4ba0,
> win)
> >  #define  AMAP_CTRL_EN_SHIFT		0
> >  #define  AMAP_CTRL_TYPE_SHIFT		1
> > +#define  AMAP_CTRL_TYPE_MASK		3
> >
> >  #define PAB_EXT_PEX_AMAP_SIZEN(win)	PAB_EXT_REG_ADDR(0xbef0,
> win)
> > +#define PAB_EXT_PEX_AMAP_AXI_WIN(win)
> 	PAB_EXT_REG_ADDR(0xb4a0, win)
> >  #define PAB_PEX_AMAP_AXI_WIN(win)	PAB_REG_ADDR(0x4ba4,
> win)
> >  #define PAB_PEX_AMAP_PEX_WIN_L(win)	PAB_REG_ADDR(0x4ba8,
> win)
> >  #define PAB_PEX_AMAP_PEX_WIN_H(win)	PAB_REG_ADDR(0x4bac,
> win)
> > @@ -455,49 +461,51 @@ static int mobiveil_pcie_parse_dt(struct
> > mobiveil_pcie *pcie)  }
> >
> >  static void program_ib_windows(struct mobiveil_pcie *pcie, int
> win_num,
> > -			       int pci_addr, u32 type, u64 size)
> > +			       u64 cpu_addr, u64 pci_addr, u32 type, u64 size)
> >  {
> > -	int pio_ctrl_val;
> > -	int amap_ctrl_dw;
> > +	u32 value;
> >  	u64 size64 = ~(size - 1);
> >
> > -	if ((pcie->ib_wins_configured + 1) > pcie->ppio_wins) {
> > +	if (win_num >= pcie->ppio_wins) {
> >  		dev_err(&pcie->pdev->dev,
> >  			"ERROR: max inbound windows reached !\n");
> >  		return;
> >  	}
> >
> > -	pio_ctrl_val = csr_readl(pcie, PAB_PEX_PIO_CTRL);
> > -	pio_ctrl_val |= 1 << PIO_ENABLE_SHIFT;
> > -	csr_writel(pcie, pio_ctrl_val, PAB_PEX_PIO_CTRL);
> > -
> > -	amap_ctrl_dw = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
> > -	amap_ctrl_dw |= (type << AMAP_CTRL_TYPE_SHIFT) |
> > -			(1 << AMAP_CTRL_EN_SHIFT) |
> > -			lower_32_bits(size64);
> > -	csr_writel(pcie, amap_ctrl_dw, PAB_PEX_AMAP_CTRL(win_num));
> > +	value = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
> > +	value &= ~(AMAP_CTRL_TYPE_MASK << AMAP_CTRL_TYPE_SHIFT |
> > +		 WIN_SIZE_MASK << WIN_SIZE_SHIFT);
> > +	value |= (type << AMAP_CTRL_TYPE_SHIFT) | (1 <<
> AMAP_CTRL_EN_SHIFT) |
> > +		 (lower_32_bits(size64) & WIN_SIZE_MASK << WIN_SIZE_SHIFT);
> > +	csr_writel(pcie, value, PAB_PEX_AMAP_CTRL(win_num));
> >
> >  	csr_writel(pcie, upper_32_bits(size64),
> >  		   PAB_EXT_PEX_AMAP_SIZEN(win_num));
> >
> > -	csr_writel(pcie, pci_addr, PAB_PEX_AMAP_AXI_WIN(win_num));
> > +	csr_writel(pcie, lower_32_bits(cpu_addr),
> > +		   PAB_PEX_AMAP_AXI_WIN(win_num));
> > +	csr_writel(pcie, upper_32_bits(cpu_addr),
> > +		   PAB_EXT_PEX_AMAP_AXI_WIN(win_num));
> > +
> > +	csr_writel(pcie, lower_32_bits(pci_addr),
> > +		   PAB_PEX_AMAP_PEX_WIN_L(win_num));
> > +	csr_writel(pcie, upper_32_bits(pci_addr),
> > +		   PAB_PEX_AMAP_PEX_WIN_H(win_num));
> >
> > -	csr_writel(pcie, pci_addr, PAB_PEX_AMAP_PEX_WIN_L(win_num));
> > -	csr_writel(pcie, 0, PAB_PEX_AMAP_PEX_WIN_H(win_num));
> > +	pcie->ib_wins_configured++;
> >  }
> >
> >  /*
> >   * routine to program the outbound windows
> >   */
> >  static void program_ob_windows(struct mobiveil_pcie *pcie, int
> win_num,
> > -			       u64 cpu_addr, u64 pci_addr,
> > -			       u32 config_io_bit, u64 size)
> > +			       u64 cpu_addr, u64 pci_addr, u32 type, u64 size)
> >  {
> >
> > -	u32 value, type;
> > +	u32 value;
> >  	u64 size64 = ~(size - 1);
> >
> > -	if ((pcie->ob_wins_configured + 1) > pcie->apio_wins) {
> > +	if (win_num >= pcie->apio_wins) {
> >  		dev_err(&pcie->pdev->dev,
> >  			"ERROR: max outbound windows reached !\n");
> >  		return;
> > @@ -507,10 +515,12 @@ static void program_ob_windows(struct
> mobiveil_pcie *pcie, int win_num,
> >  	 * program Enable Bit to 1, Type Bit to (00) base 2, AXI Window Size Bit
> >  	 * to 4 KB in PAB_AXI_AMAP_CTRL register
> >  	 */
> > -	type = config_io_bit;
> >  	value = csr_readl(pcie, PAB_AXI_AMAP_CTRL(win_num));
> > -	csr_writel(pcie, 1 << WIN_ENABLE_SHIFT | type << WIN_TYPE_SHIFT |
> > -		   lower_32_bits(size64), PAB_AXI_AMAP_CTRL(win_num));
> > +	value &= ~(WIN_TYPE_MASK << WIN_TYPE_SHIFT |
> > +		 WIN_SIZE_MASK << WIN_SIZE_SHIFT);
> > +	value |= 1 << WIN_ENABLE_SHIFT | type << WIN_TYPE_SHIFT |
> > +		 (lower_32_bits(size64) & WIN_SIZE_MASK << WIN_SIZE_SHIFT);
> > +	csr_writel(pcie, value, PAB_AXI_AMAP_CTRL(win_num));
> >
> >  	csr_writel(pcie, upper_32_bits(size64),
> > PAB_EXT_AXI_AMAP_SIZE(win_num));
> >
> > @@ -518,11 +528,10 @@ static void program_ob_windows(struct
> mobiveil_pcie *pcie, int win_num,
> >  	 * program AXI window base with appropriate value in
> >  	 * PAB_AXI_AMAP_AXI_WIN0 register
> >  	 */
> > -	value = csr_readl(pcie, PAB_AXI_AMAP_AXI_WIN(win_num));
> > -	csr_writel(pcie, cpu_addr & (~AXI_WINDOW_ALIGN_MASK),
> > +	csr_writel(pcie, lower_32_bits(cpu_addr) &
> (~AXI_WINDOW_ALIGN_MASK),
> >  		   PAB_AXI_AMAP_AXI_WIN(win_num));
> > -
> > -	value = csr_readl(pcie, PAB_AXI_AMAP_PEX_WIN_H(win_num));
> > +	csr_writel(pcie, upper_32_bits(cpu_addr),
> > +		   PAB_EXT_AXI_AMAP_AXI_WIN(win_num));
> >
> >  	csr_writel(pcie, lower_32_bits(pci_addr),
> >  		   PAB_AXI_AMAP_PEX_WIN_L(win_num)); @@ -604,6 +613,11
> @@ static
> > int mobiveil_host_init(struct mobiveil_pcie *pcie)
> >  	value |= APIO_EN_MASK;
> >  	csr_writel(pcie, value, PAB_AXI_PIO_CTRL);
> >
> > +	/* Enable PCIe PIO master */
> > +	value = csr_readl(pcie, PAB_PEX_PIO_CTRL);
> > +	value |= 1 << PIO_ENABLE_SHIFT;
> > +	csr_writel(pcie, value, PAB_PEX_PIO_CTRL);
> > +
> >  	/*
> >  	 * we'll program one outbound window for config reads and
> >  	 * another default inbound window for all the upstream traffic @@
> > -616,7 +630,7 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
> >  			   CFG_WINDOW_TYPE, resource_size(pcie->ob_io_res));
> >
> >  	/* memory inbound translation window */
> > -	program_ib_windows(pcie, WIN_NUM_0, 0, MEM_WINDOW_TYPE,
> IB_WIN_SIZE);
> > +	program_ib_windows(pcie, WIN_NUM_0, 0, 0, MEM_WINDOW_TYPE,
> > +IB_WIN_SIZE);
> >
> >  	/* Get the I/O and memory ranges from DT */
> >  	resource_list_for_each_entry(win, &pcie->resources) {
> > --
> > 2.17.1
> >

^ permalink raw reply	[flat|nested] 67+ messages in thread

* RE: [PATCHv5 10/20] PCI: mobiveil: Fix the INTx process errors
  2019-06-28 17:05   ` Lorenzo Pieralisi
@ 2019-07-01 10:27     ` Z.q. Hou
  0 siblings, 0 replies; 67+ messages in thread
From: Z.q. Hou @ 2019-07-01 10:27 UTC (permalink / raw)
  To: Lorenzo Pieralisi
  Cc: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	catalin.marinas, will.deacon, Mingkai Hu, M.h. Lian, Xiaowei Bao

Hi Lorenzo,

Thanks a lot for your comments!

> -----Original Message-----
> From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Sent: 2019年6月29日 1:06
> To: Z.q. Hou <zhiqiang.hou@nxp.com>
> Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> bhelgaas@google.com; robh+dt@kernel.org; mark.rutland@arm.com;
> l.subrahmanya@mobiveil.co.in; shawnguo@kernel.org; Leo Li
> <leoyang.li@nxp.com>; catalin.marinas@arm.com; will.deacon@arm.com;
> Mingkai Hu <mingkai.hu@nxp.com>; M.h. Lian <minghuan.lian@nxp.com>;
> Xiaowei Bao <xiaowei.bao@nxp.com>
> Subject: Re: [PATCHv5 10/20] PCI: mobiveil: Fix the INTx process errors
> 
> On Fri, Apr 12, 2019 at 08:36:12AM +0000, Z.q. Hou wrote:
> > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> >
> > In the loop block, there is not code to update the loop key, this
> > patch updates the loop key by re-read the INTx status register.
> >
> > This patch also add the clearing of the handled INTx status.
> 
> This is two bugs and that requires two patches, each of them fixing a specific
> issue.
> 
> So split the patch into two and repost it.

Yes, will split it.

Thanks,
Zhiqiang
 
> Lorenzo
> 
> > Note: Need MV to test this fix.
> >
> > Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP
> > driver")
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> > Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
> > ---
> > V5:
> >  - Corrected and retouched the subject and changelog.
> >
> >  drivers/pci/controller/pcie-mobiveil.c | 13 +++++++++----
> >  1 file changed, 9 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/pci/controller/pcie-mobiveil.c
> > b/drivers/pci/controller/pcie-mobiveil.c
> > index 4ba458474e42..78e575e71f4d 100644
> > --- a/drivers/pci/controller/pcie-mobiveil.c
> > +++ b/drivers/pci/controller/pcie-mobiveil.c
> > @@ -361,6 +361,7 @@ static void mobiveil_pcie_isr(struct irq_desc *desc)
> >  	/* Handle INTx */
> >  	if (intr_status & PAB_INTP_INTX_MASK) {
> >  		shifted_status = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT);
> > +		shifted_status &= PAB_INTP_INTX_MASK;
> >  		shifted_status >>= PAB_INTX_START;
> >  		do {
> >  			for_each_set_bit(bit, &shifted_status, PCI_NUM_INTX) { @@
> -372,12
> > +373,16 @@ static void mobiveil_pcie_isr(struct irq_desc *desc)
> >  					dev_err_ratelimited(dev, "unexpected IRQ,
> INT%d\n",
> >  							    bit);
> >
> > -				/* clear interrupt */
> > -				csr_writel(pcie,
> > -					   shifted_status << PAB_INTX_START,
> > +				/* clear interrupt handled */
> > +				csr_writel(pcie, 1 << (PAB_INTX_START + bit),
> >  					   PAB_INTP_AMBA_MISC_STAT);
> >  			}
> > -		} while ((shifted_status >> PAB_INTX_START) != 0);
> > +
> > +			shifted_status = csr_readl(pcie,
> > +						   PAB_INTP_AMBA_MISC_STAT);
> > +			shifted_status &= PAB_INTP_INTX_MASK;
> > +			shifted_status >>= PAB_INTX_START;
> > +		} while (shifted_status != 0);
> >  	}
> >
> >  	/* read extra MSI status register */
> > --
> > 2.17.1
> >

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCHv5 00/20] PCI: mobiveil: fixes for Mobiveil PCIe Host Bridge IP driver
  2019-04-12  8:35 [PATCHv5 00/20] PCI: mobiveil: fixes for Mobiveil PCIe Host Bridge IP driver Z.q. Hou
                   ` (19 preceding siblings ...)
  2019-04-12  8:37 ` [PATCHv5 20/20] dt-bindings: PCI: mobiveil: Change gpio_slave and apb_csr to optional Z.q. Hou
@ 2019-07-03 10:33 ` Lorenzo Pieralisi
  2019-07-04  2:36   ` Z.q. Hou
  20 siblings, 1 reply; 67+ messages in thread
From: Lorenzo Pieralisi @ 2019-07-03 10:33 UTC (permalink / raw)
  To: Z.q. Hou
  Cc: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	catalin.marinas, will.deacon, Mingkai Hu, M.h. Lian, Xiaowei Bao

On Fri, Apr 12, 2019 at 08:35:11AM +0000, Z.q. Hou wrote:
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> 
> This patch set is to add fixes for Mobiveil PCIe Host driver.
> And these patches are splited from the thread below:
> http://patchwork.ozlabs.org/project/linux-pci/list/?series=96417
> 
> Hou Zhiqiang (20):
>   PCI: mobiveil: Unify register accessors
>   PCI: mobiveil: Format the code without functionality change
>   PCI: mobiveil: Correct the returned error number
>   PCI: mobiveil: Remove the flag MSI_FLAG_MULTI_PCI_MSI
>   PCI: mobiveil: Correct PCI base address in MEM/IO outbound windows
>   PCI: mobiveil: Replace the resource list iteration function
>   PCI: mobiveil: Use WIN_NUM_0 explicitly for CFG outbound window
>   PCI: mobiveil: Use the 1st inbound window for MEM inbound transactions
>   PCI: mobiveil: Correct inbound/outbound window setup routines
>   PCI: mobiveil: Fix the INTx process errors
>   PCI: mobiveil: Correct the fixup of Class Code field
>   PCI: mobiveil: Move the link up waiting out of mobiveil_host_init()
>   PCI: mobiveil: Move IRQ chained handler setup out of DT parse
>   PCI: mobiveil: Initialize Primary/Secondary/Subordinate bus numbers
>   PCI: mobiveil: Fix the checking of valid device
>   PCI: mobiveil: Add link up condition check
>   PCI: mobiveil: Complete initialization of host even if no PCIe link
>   PCI: mobiveil: Disable IB and OB windows set by bootloader
>   PCI: mobiveil: Add 8-bit and 16-bit register accessors
>   dt-bindings: PCI: mobiveil: Change gpio_slave and apb_csr to optional
> 
>  .../devicetree/bindings/pci/mobiveil-pcie.txt |   2 +
>  drivers/pci/controller/pcie-mobiveil.c        | 578 +++++++++++-------
>  2 files changed, 368 insertions(+), 212 deletions(-)

I am putting together a branch with the patches I would like
to queue, for the ones I requested to split please wait for
me, I will publish the branch and will ask you to rebase
on top of it.

Lorenzo

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCHv5 03/20] PCI: mobiveil: Correct the returned error number
  2019-04-12  8:35 ` [PATCHv5 03/20] PCI: mobiveil: Correct the returned error number Z.q. Hou
@ 2019-07-03 14:17   ` Lorenzo Pieralisi
  2019-07-04  2:38     ` Z.q. Hou
  0 siblings, 1 reply; 67+ messages in thread
From: Lorenzo Pieralisi @ 2019-07-03 14:17 UTC (permalink / raw)
  To: Z.q. Hou
  Cc: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	catalin.marinas, will.deacon, Mingkai Hu, M.h. Lian, Xiaowei Bao

On Fri, Apr 12, 2019 at 08:35:30AM +0000, Z.q. Hou wrote:
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> 
> This patch corrects the returned error number by convention,
> and removes an unnecessary error check.

Two distinct changes, two patches, please split and repost.

Lorenzo

> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
> ---
> V5:
>  - Corrected and retouched the subject and changelog.
> 
>  drivers/pci/controller/pcie-mobiveil.c | 8 +++-----
>  1 file changed, 3 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c
> index b87471f08a40..563210e731d3 100644
> --- a/drivers/pci/controller/pcie-mobiveil.c
> +++ b/drivers/pci/controller/pcie-mobiveil.c
> @@ -819,7 +819,7 @@ static int mobiveil_pcie_init_irq_domain(struct mobiveil_pcie *pcie)
>  
>  	if (!pcie->intx_domain) {
>  		dev_err(dev, "Failed to get a INTx IRQ domain\n");
> -		return -ENODEV;
> +		return -ENOMEM;
>  	}
>  
>  	raw_spin_lock_init(&pcie->intx_mask_lock);
> @@ -845,11 +845,9 @@ static int mobiveil_pcie_probe(struct platform_device *pdev)
>  	/* allocate the PCIe port */
>  	bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
>  	if (!bridge)
> -		return -ENODEV;
> +		return -ENOMEM;
>  
>  	pcie = pci_host_bridge_priv(bridge);
> -	if (!pcie)
> -		return -ENOMEM;
>  
>  	pcie->pdev = pdev;
>  
> @@ -866,7 +864,7 @@ static int mobiveil_pcie_probe(struct platform_device *pdev)
>  						    &pcie->resources, &iobase);
>  	if (ret) {
>  		dev_err(dev, "Getting bridge resources failed\n");
> -		return -ENOMEM;
> +		return ret;
>  	}
>  
>  	/*
> -- 
> 2.17.1
> 

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCHv5 02/20] PCI: mobiveil: Format the code without functionality change
  2019-04-12  8:35 ` [PATCHv5 02/20] PCI: mobiveil: Format the code without functionality change Z.q. Hou
@ 2019-07-03 15:10   ` Lorenzo Pieralisi
  2019-07-04  2:41     ` Z.q. Hou
  2019-07-03 15:19   ` Lorenzo Pieralisi
  1 sibling, 1 reply; 67+ messages in thread
From: Lorenzo Pieralisi @ 2019-07-03 15:10 UTC (permalink / raw)
  To: Z.q. Hou
  Cc: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	catalin.marinas, will.deacon, Mingkai Hu, M.h. Lian, Xiaowei Bao

On Fri, Apr 12, 2019 at 08:35:24AM +0000, Z.q. Hou wrote:
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> 
> Just format the code without functionality change.
> 
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> ---
> V5:
>  - Retouched the subject.
> 
>  drivers/pci/controller/pcie-mobiveil.c | 261 +++++++++++++------------
>  1 file changed, 137 insertions(+), 124 deletions(-)

Again, I will drop this patch. You tend to do multiple changes
in one single patch, I understand this patch is just
reformatting/renaming variables but at least I would separate
indentation changes from changes where eg you add local variables.

At least try to group the changes you are making instead of mixing
them all up.

Thanks,
Lorenzo

> diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c
> index d55c7e780c6e..b87471f08a40 100644
> --- a/drivers/pci/controller/pcie-mobiveil.c
> +++ b/drivers/pci/controller/pcie-mobiveil.c
> @@ -31,38 +31,40 @@
>   * translation tables are grouped into windows, each window registers are
>   * grouped into blocks of 4 or 16 registers each
>   */
> -#define PAB_REG_BLOCK_SIZE	16
> -#define PAB_EXT_REG_BLOCK_SIZE	4
> +#define PAB_REG_BLOCK_SIZE		16
> +#define PAB_EXT_REG_BLOCK_SIZE		4
>  
> -#define PAB_REG_ADDR(offset, win) (offset + (win * PAB_REG_BLOCK_SIZE))
> -#define PAB_EXT_REG_ADDR(offset, win) (offset + (win * PAB_EXT_REG_BLOCK_SIZE))
> +#define PAB_REG_ADDR(offset, win)	\
> +	(offset + (win * PAB_REG_BLOCK_SIZE))
> +#define PAB_EXT_REG_ADDR(offset, win)	\
> +	(offset + (win * PAB_EXT_REG_BLOCK_SIZE))
>  
> -#define LTSSM_STATUS		0x0404
> -#define  LTSSM_STATUS_L0_MASK	0x3f
> -#define  LTSSM_STATUS_L0	0x2d
> +#define LTSSM_STATUS			0x0404
> +#define  LTSSM_STATUS_L0_MASK		0x3f
> +#define  LTSSM_STATUS_L0		0x2d
>  
> -#define PAB_CTRL		0x0808
> -#define  AMBA_PIO_ENABLE_SHIFT	0
> -#define  PEX_PIO_ENABLE_SHIFT	1
> -#define  PAGE_SEL_SHIFT	13
> -#define  PAGE_SEL_MASK		0x3f
> -#define  PAGE_LO_MASK		0x3ff
> -#define  PAGE_SEL_OFFSET_SHIFT	10
> +#define PAB_CTRL			0x0808
> +#define  AMBA_PIO_ENABLE_SHIFT		0
> +#define  PEX_PIO_ENABLE_SHIFT		1
> +#define  PAGE_SEL_SHIFT			13
> +#define  PAGE_SEL_MASK			0x3f
> +#define  PAGE_LO_MASK			0x3ff
> +#define  PAGE_SEL_OFFSET_SHIFT		10
>  
> -#define PAB_AXI_PIO_CTRL	0x0840
> -#define  APIO_EN_MASK		0xf
> +#define PAB_AXI_PIO_CTRL		0x0840
> +#define  APIO_EN_MASK			0xf
>  
> -#define PAB_PEX_PIO_CTRL	0x08c0
> -#define  PIO_ENABLE_SHIFT	0
> +#define PAB_PEX_PIO_CTRL		0x08c0
> +#define  PIO_ENABLE_SHIFT		0
>  
>  #define PAB_INTP_AMBA_MISC_ENB		0x0b0c
> -#define PAB_INTP_AMBA_MISC_STAT	0x0b1c
> +#define PAB_INTP_AMBA_MISC_STAT		0x0b1c
>  #define  PAB_INTP_INTX_MASK		0x01e0
>  #define  PAB_INTP_MSI_MASK		0x8
>  
> -#define PAB_AXI_AMAP_CTRL(win)	PAB_REG_ADDR(0x0ba0, win)
> -#define  WIN_ENABLE_SHIFT	0
> -#define  WIN_TYPE_SHIFT	1
> +#define PAB_AXI_AMAP_CTRL(win)		PAB_REG_ADDR(0x0ba0, win)
> +#define  WIN_ENABLE_SHIFT		0
> +#define  WIN_TYPE_SHIFT			1
>  
>  #define PAB_EXT_AXI_AMAP_SIZE(win)	PAB_EXT_REG_ADDR(0xbaf0, win)
>  
> @@ -70,16 +72,16 @@
>  #define  AXI_WINDOW_ALIGN_MASK		3
>  
>  #define PAB_AXI_AMAP_PEX_WIN_L(win)	PAB_REG_ADDR(0x0ba8, win)
> -#define  PAB_BUS_SHIFT		24
> -#define  PAB_DEVICE_SHIFT	19
> -#define  PAB_FUNCTION_SHIFT	16
> +#define  PAB_BUS_SHIFT			24
> +#define  PAB_DEVICE_SHIFT		19
> +#define  PAB_FUNCTION_SHIFT		16
>  
>  #define PAB_AXI_AMAP_PEX_WIN_H(win)	PAB_REG_ADDR(0x0bac, win)
>  #define PAB_INTP_AXI_PIO_CLASS		0x474
>  
> -#define PAB_PEX_AMAP_CTRL(win)	PAB_REG_ADDR(0x4ba0, win)
> -#define  AMAP_CTRL_EN_SHIFT	0
> -#define  AMAP_CTRL_TYPE_SHIFT	1
> +#define PAB_PEX_AMAP_CTRL(win)		PAB_REG_ADDR(0x4ba0, win)
> +#define  AMAP_CTRL_EN_SHIFT		0
> +#define  AMAP_CTRL_TYPE_SHIFT		1
>  
>  #define PAB_EXT_PEX_AMAP_SIZEN(win)	PAB_EXT_REG_ADDR(0xbef0, win)
>  #define PAB_PEX_AMAP_AXI_WIN(win)	PAB_REG_ADDR(0x4ba4, win)
> @@ -87,39 +89,39 @@
>  #define PAB_PEX_AMAP_PEX_WIN_H(win)	PAB_REG_ADDR(0x4bac, win)
>  
>  /* starting offset of INTX bits in status register */
> -#define PAB_INTX_START	5
> +#define PAB_INTX_START			5
>  
>  /* supported number of MSI interrupts */
> -#define PCI_NUM_MSI	16
> +#define PCI_NUM_MSI			16
>  
>  /* MSI registers */
> -#define MSI_BASE_LO_OFFSET	0x04
> -#define MSI_BASE_HI_OFFSET	0x08
> -#define MSI_SIZE_OFFSET	0x0c
> -#define MSI_ENABLE_OFFSET	0x14
> -#define MSI_STATUS_OFFSET	0x18
> -#define MSI_DATA_OFFSET	0x20
> -#define MSI_ADDR_L_OFFSET	0x24
> -#define MSI_ADDR_H_OFFSET	0x28
> +#define MSI_BASE_LO_OFFSET		0x04
> +#define MSI_BASE_HI_OFFSET		0x08
> +#define MSI_SIZE_OFFSET			0x0c
> +#define MSI_ENABLE_OFFSET		0x14
> +#define MSI_STATUS_OFFSET		0x18
> +#define MSI_DATA_OFFSET			0x20
> +#define MSI_ADDR_L_OFFSET		0x24
> +#define MSI_ADDR_H_OFFSET		0x28
>  
>  /* outbound and inbound window definitions */
> -#define WIN_NUM_0		0
> -#define WIN_NUM_1		1
> -#define CFG_WINDOW_TYPE	0
> -#define IO_WINDOW_TYPE		1
> -#define MEM_WINDOW_TYPE	2
> -#define IB_WIN_SIZE		((u64)256 * 1024 * 1024 * 1024)
> -#define MAX_PIO_WINDOWS	8
> +#define WIN_NUM_0			0
> +#define WIN_NUM_1			1
> +#define CFG_WINDOW_TYPE			0
> +#define IO_WINDOW_TYPE			1
> +#define MEM_WINDOW_TYPE			2
> +#define IB_WIN_SIZE			((u64)256 * 1024 * 1024 * 1024)
> +#define MAX_PIO_WINDOWS			8
>  
>  /* Parameters for the waiting for link up routine */
> -#define LINK_WAIT_MAX_RETRIES	10
> -#define LINK_WAIT_MIN	90000
> -#define LINK_WAIT_MAX	100000
> +#define LINK_WAIT_MAX_RETRIES		10
> +#define LINK_WAIT_MIN			90000
> +#define LINK_WAIT_MAX			100000
>  
> -#define PAGED_ADDR_BNDRY			0xc00
> -#define OFFSET_TO_PAGE_ADDR(off)		\
> +#define PAGED_ADDR_BNDRY		0xc00
> +#define OFFSET_TO_PAGE_ADDR(off)	\
>  	((off & PAGE_LO_MASK) | PAGED_ADDR_BNDRY)
> -#define OFFSET_TO_PAGE_IDX(off)			\
> +#define OFFSET_TO_PAGE_IDX(off)		\
>  	((off >> PAGE_SEL_OFFSET_SHIFT) & PAGE_SEL_MASK)
>  
>  struct mobiveil_msi {			/* MSI information */
> @@ -297,14 +299,14 @@ static void __iomem *mobiveil_pcie_map_bus(struct pci_bus *bus,
>  					unsigned int devfn, int where)
>  {
>  	struct mobiveil_pcie *pcie = bus->sysdata;
> +	u32 value;
>  
>  	if (!mobiveil_pcie_valid_device(bus, devfn))
>  		return NULL;
>  
> -	if (bus->number == pcie->root_bus_nr) {
> -		/* RC config access */
> +	/* RC config access */
> +	if (bus->number == pcie->root_bus_nr)
>  		return pcie->csr_axi_slave_base + where;
> -	}
>  
>  	/*
>  	 * EP config access (in Config/APIO space)
> @@ -312,10 +314,12 @@ static void __iomem *mobiveil_pcie_map_bus(struct pci_bus *bus,
>  	 * (BDF) in PAB_AXI_AMAP_PEX_WIN_L0 Register.
>  	 * Relies on pci_lock serialization
>  	 */
> -	csr_writel(pcie, bus->number << PAB_BUS_SHIFT |
> -			PCI_SLOT(devfn) << PAB_DEVICE_SHIFT |
> -			PCI_FUNC(devfn) << PAB_FUNCTION_SHIFT,
> -			PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0));
> +	value = bus->number << PAB_BUS_SHIFT |
> +		PCI_SLOT(devfn) << PAB_DEVICE_SHIFT |
> +		PCI_FUNC(devfn) << PAB_FUNCTION_SHIFT;
> +
> +	csr_writel(pcie, value, PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0));
> +
>  	return pcie->config_axi_slave_base + where;
>  }
>  
> @@ -350,22 +354,22 @@ static void mobiveil_pcie_isr(struct irq_desc *desc)
>  
>  	/* Handle INTx */
>  	if (intr_status & PAB_INTP_INTX_MASK) {
> -		shifted_status = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT) >>
> -			PAB_INTX_START;
> +		shifted_status = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT);
> +		shifted_status >>= PAB_INTX_START;
>  		do {
>  			for_each_set_bit(bit, &shifted_status, PCI_NUM_INTX) {
>  				virq = irq_find_mapping(pcie->intx_domain,
> -						bit + 1);
> +							bit + 1);
>  				if (virq)
>  					generic_handle_irq(virq);
>  				else
> -					dev_err_ratelimited(dev,
> -						"unexpected IRQ, INT%d\n", bit);
> +					dev_err_ratelimited(dev, "unexpected IRQ, INT%d\n",
> +							    bit);
>  
>  				/* clear interrupt */
>  				csr_writel(pcie,
> -					shifted_status << PAB_INTX_START,
> -					PAB_INTP_AMBA_MISC_STAT);
> +					   shifted_status << PAB_INTX_START,
> +					   PAB_INTP_AMBA_MISC_STAT);
>  			}
>  		} while ((shifted_status >> PAB_INTX_START) != 0);
>  	}
> @@ -375,8 +379,7 @@ static void mobiveil_pcie_isr(struct irq_desc *desc)
>  
>  	/* handle MSI interrupts */
>  	while (msi_status & 1) {
> -		msi_data = readl_relaxed(pcie->apb_csr_base
> -				+ MSI_DATA_OFFSET);
> +		msi_data = readl_relaxed(pcie->apb_csr_base + MSI_DATA_OFFSET);
>  
>  		/*
>  		 * MSI_STATUS_OFFSET register gets updated to zero
> @@ -385,18 +388,18 @@ static void mobiveil_pcie_isr(struct irq_desc *desc)
>  		 * two dummy reads.
>  		 */
>  		msi_addr_lo = readl_relaxed(pcie->apb_csr_base +
> -				MSI_ADDR_L_OFFSET);
> +					    MSI_ADDR_L_OFFSET);
>  		msi_addr_hi = readl_relaxed(pcie->apb_csr_base +
> -				MSI_ADDR_H_OFFSET);
> +					    MSI_ADDR_H_OFFSET);
>  		dev_dbg(dev, "MSI registers, data: %08x, addr: %08x:%08x\n",
> -				msi_data, msi_addr_hi, msi_addr_lo);
> +			msi_data, msi_addr_hi, msi_addr_lo);
>  
>  		virq = irq_find_mapping(msi->dev_domain, msi_data);
>  		if (virq)
>  			generic_handle_irq(virq);
>  
>  		msi_status = readl_relaxed(pcie->apb_csr_base +
> -				MSI_STATUS_OFFSET);
> +					   MSI_STATUS_OFFSET);
>  	}
>  
>  	/* Clear the interrupt status */
> @@ -413,7 +416,7 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie)
>  
>  	/* map config resource */
>  	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> -			"config_axi_slave");
> +					   "config_axi_slave");
>  	pcie->config_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);
>  	if (IS_ERR(pcie->config_axi_slave_base))
>  		return PTR_ERR(pcie->config_axi_slave_base);
> @@ -421,7 +424,7 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie)
>  
>  	/* map csr resource */
>  	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> -			"csr_axi_slave");
> +					   "csr_axi_slave");
>  	pcie->csr_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);
>  	if (IS_ERR(pcie->csr_axi_slave_base))
>  		return PTR_ERR(pcie->csr_axi_slave_base);
> @@ -452,7 +455,7 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie)
>  }
>  
>  static void program_ib_windows(struct mobiveil_pcie *pcie, int win_num,
> -		int pci_addr, u32 type, u64 size)
> +			       int pci_addr, u32 type, u64 size)
>  {
>  	int pio_ctrl_val;
>  	int amap_ctrl_dw;
> @@ -465,19 +468,20 @@ static void program_ib_windows(struct mobiveil_pcie *pcie, int win_num,
>  	}
>  
>  	pio_ctrl_val = csr_readl(pcie, PAB_PEX_PIO_CTRL);
> -	csr_writel(pcie,
> -		pio_ctrl_val | (1 << PIO_ENABLE_SHIFT), PAB_PEX_PIO_CTRL);
> -	amap_ctrl_dw = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
> -	amap_ctrl_dw = (amap_ctrl_dw | (type << AMAP_CTRL_TYPE_SHIFT));
> -	amap_ctrl_dw = (amap_ctrl_dw | (1 << AMAP_CTRL_EN_SHIFT));
> +	pio_ctrl_val |= 1 << PIO_ENABLE_SHIFT;
> +	csr_writel(pcie, pio_ctrl_val, PAB_PEX_PIO_CTRL);
>  
> -	csr_writel(pcie, amap_ctrl_dw | lower_32_bits(size64),
> -		   PAB_PEX_AMAP_CTRL(win_num));
> +	amap_ctrl_dw = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
> +	amap_ctrl_dw |= (type << AMAP_CTRL_TYPE_SHIFT) |
> +			(1 << AMAP_CTRL_EN_SHIFT) |
> +			lower_32_bits(size64);
> +	csr_writel(pcie, amap_ctrl_dw, PAB_PEX_AMAP_CTRL(win_num));
>  
>  	csr_writel(pcie, upper_32_bits(size64),
>  		   PAB_EXT_PEX_AMAP_SIZEN(win_num));
>  
>  	csr_writel(pcie, pci_addr, PAB_PEX_AMAP_AXI_WIN(win_num));
> +
>  	csr_writel(pcie, pci_addr, PAB_PEX_AMAP_PEX_WIN_L(win_num));
>  	csr_writel(pcie, 0, PAB_PEX_AMAP_PEX_WIN_H(win_num));
>  }
> @@ -486,7 +490,8 @@ static void program_ib_windows(struct mobiveil_pcie *pcie, int win_num,
>   * routine to program the outbound windows
>   */
>  static void program_ob_windows(struct mobiveil_pcie *pcie, int win_num,
> -		u64 cpu_addr, u64 pci_addr, u32 config_io_bit, u64 size)
> +			       u64 cpu_addr, u64 pci_addr,
> +			       u32 config_io_bit, u64 size)
>  {
>  
>  	u32 value, type;
> @@ -505,7 +510,7 @@ static void program_ob_windows(struct mobiveil_pcie *pcie, int win_num,
>  	type = config_io_bit;
>  	value = csr_readl(pcie, PAB_AXI_AMAP_CTRL(win_num));
>  	csr_writel(pcie, 1 << WIN_ENABLE_SHIFT | type << WIN_TYPE_SHIFT |
> -			lower_32_bits(size64), PAB_AXI_AMAP_CTRL(win_num));
> +		   lower_32_bits(size64), PAB_AXI_AMAP_CTRL(win_num));
>  
>  	csr_writel(pcie, upper_32_bits(size64), PAB_EXT_AXI_AMAP_SIZE(win_num));
>  
> @@ -515,14 +520,14 @@ static void program_ob_windows(struct mobiveil_pcie *pcie, int win_num,
>  	 */
>  	value = csr_readl(pcie, PAB_AXI_AMAP_AXI_WIN(win_num));
>  	csr_writel(pcie, cpu_addr & (~AXI_WINDOW_ALIGN_MASK),
> -			PAB_AXI_AMAP_AXI_WIN(win_num));
> +		   PAB_AXI_AMAP_AXI_WIN(win_num));
>  
>  	value = csr_readl(pcie, PAB_AXI_AMAP_PEX_WIN_H(win_num));
>  
>  	csr_writel(pcie, lower_32_bits(pci_addr),
> -			PAB_AXI_AMAP_PEX_WIN_L(win_num));
> +		   PAB_AXI_AMAP_PEX_WIN_L(win_num));
>  	csr_writel(pcie, upper_32_bits(pci_addr),
> -			PAB_AXI_AMAP_PEX_WIN_H(win_num));
> +		   PAB_AXI_AMAP_PEX_WIN_H(win_num));
>  
>  	pcie->ob_wins_configured++;
>  }
> @@ -538,7 +543,9 @@ static int mobiveil_bringup_link(struct mobiveil_pcie *pcie)
>  
>  		usleep_range(LINK_WAIT_MIN, LINK_WAIT_MAX);
>  	}
> +
>  	dev_err(&pcie->pdev->dev, "link never came up\n");
> +
>  	return -ETIMEDOUT;
>  }
>  
> @@ -551,16 +558,16 @@ static void mobiveil_pcie_enable_msi(struct mobiveil_pcie *pcie)
>  	msi->msi_pages_phys = (phys_addr_t)msg_addr;
>  
>  	writel_relaxed(lower_32_bits(msg_addr),
> -		pcie->apb_csr_base + MSI_BASE_LO_OFFSET);
> +		       pcie->apb_csr_base + MSI_BASE_LO_OFFSET);
>  	writel_relaxed(upper_32_bits(msg_addr),
> -		pcie->apb_csr_base + MSI_BASE_HI_OFFSET);
> +		       pcie->apb_csr_base + MSI_BASE_HI_OFFSET);
>  	writel_relaxed(4096, pcie->apb_csr_base + MSI_SIZE_OFFSET);
>  	writel_relaxed(1, pcie->apb_csr_base + MSI_ENABLE_OFFSET);
>  }
>  
>  static int mobiveil_host_init(struct mobiveil_pcie *pcie)
>  {
> -	u32 value, pab_ctrl, type = 0;
> +	u32 value, pab_ctrl, type;
>  	int err;
>  	struct resource_entry *win, *tmp;
>  
> @@ -575,26 +582,27 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
>  	 * Space
>  	 */
>  	value = csr_readl(pcie, PCI_COMMAND);
> -	csr_writel(pcie, value | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
> -		PCI_COMMAND_MASTER, PCI_COMMAND);
> +	value |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
> +	csr_writel(pcie, value, PCI_COMMAND);
>  
>  	/*
>  	 * program PIO Enable Bit to 1 (and PEX PIO Enable to 1) in PAB_CTRL
>  	 * register
>  	 */
>  	pab_ctrl = csr_readl(pcie, PAB_CTRL);
> -	csr_writel(pcie, pab_ctrl | (1 << AMBA_PIO_ENABLE_SHIFT) |
> -		(1 << PEX_PIO_ENABLE_SHIFT), PAB_CTRL);
> +	pab_ctrl |= (1 << AMBA_PIO_ENABLE_SHIFT) | (1 << PEX_PIO_ENABLE_SHIFT);
> +	csr_writel(pcie, pab_ctrl, PAB_CTRL);
>  
>  	csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK),
> -		PAB_INTP_AMBA_MISC_ENB);
> +		   PAB_INTP_AMBA_MISC_ENB);
>  
>  	/*
>  	 * program PIO Enable Bit to 1 and Config Window Enable Bit to 1 in
>  	 * PAB_AXI_PIO_CTRL Register
>  	 */
>  	value = csr_readl(pcie, PAB_AXI_PIO_CTRL);
> -	csr_writel(pcie, value | APIO_EN_MASK, PAB_AXI_PIO_CTRL);
> +	value |= APIO_EN_MASK;
> +	csr_writel(pcie, value, PAB_AXI_PIO_CTRL);
>  
>  	/*
>  	 * we'll program one outbound window for config reads and
> @@ -605,25 +613,25 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
>  
>  	/* config outbound translation window */
>  	program_ob_windows(pcie, pcie->ob_wins_configured,
> -			pcie->ob_io_res->start, 0, CFG_WINDOW_TYPE,
> -			resource_size(pcie->ob_io_res));
> +			   pcie->ob_io_res->start, 0, CFG_WINDOW_TYPE,
> +			   resource_size(pcie->ob_io_res));
>  
>  	/* memory inbound translation window */
>  	program_ib_windows(pcie, WIN_NUM_1, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE);
>  
>  	/* Get the I/O and memory ranges from DT */
>  	resource_list_for_each_entry_safe(win, tmp, &pcie->resources) {
> -		type = 0;
>  		if (resource_type(win->res) == IORESOURCE_MEM)
>  			type = MEM_WINDOW_TYPE;
> -		if (resource_type(win->res) == IORESOURCE_IO)
> +		else if (resource_type(win->res) == IORESOURCE_IO)
>  			type = IO_WINDOW_TYPE;
> -		if (type) {
> -			/* configure outbound translation window */
> -			program_ob_windows(pcie, pcie->ob_wins_configured,
> -				win->res->start, 0, type,
> -				resource_size(win->res));
> -		}
> +		else
> +			continue;
> +
> +		/* configure outbound translation window */
> +		program_ob_windows(pcie, pcie->ob_wins_configured,
> +				   win->res->start, 0, type,
> +				   resource_size(win->res));
>  	}
>  
>  	/* setup MSI hardware registers */
> @@ -643,7 +651,8 @@ static void mobiveil_mask_intx_irq(struct irq_data *data)
>  	mask = 1 << ((data->hwirq + PAB_INTX_START) - 1);
>  	raw_spin_lock_irqsave(&pcie->intx_mask_lock, flags);
>  	shifted_val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
> -	csr_writel(pcie, (shifted_val & (~mask)), PAB_INTP_AMBA_MISC_ENB);
> +	shifted_val &= ~mask;
> +	csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
>  	raw_spin_unlock_irqrestore(&pcie->intx_mask_lock, flags);
>  }
>  
> @@ -658,7 +667,8 @@ static void mobiveil_unmask_intx_irq(struct irq_data *data)
>  	mask = 1 << ((data->hwirq + PAB_INTX_START) - 1);
>  	raw_spin_lock_irqsave(&pcie->intx_mask_lock, flags);
>  	shifted_val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
> -	csr_writel(pcie, (shifted_val | mask), PAB_INTP_AMBA_MISC_ENB);
> +	shifted_val |= mask;
> +	csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
>  	raw_spin_unlock_irqrestore(&pcie->intx_mask_lock, flags);
>  }
>  
> @@ -672,10 +682,11 @@ static struct irq_chip intx_irq_chip = {
>  
>  /* routine to setup the INTx related data */
>  static int mobiveil_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
> -		irq_hw_number_t hwirq)
> +				  irq_hw_number_t hwirq)
>  {
>  	irq_set_chip_and_handler(irq, &intx_irq_chip, handle_level_irq);
>  	irq_set_chip_data(irq, domain->host_data);
> +
>  	return 0;
>  }
>  
> @@ -692,7 +703,7 @@ static struct irq_chip mobiveil_msi_irq_chip = {
>  
>  static struct msi_domain_info mobiveil_msi_domain_info = {
>  	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
> -		MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX),
> +		   MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX),
>  	.chip	= &mobiveil_msi_irq_chip,
>  };
>  
> @@ -710,7 +721,7 @@ static void mobiveil_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
>  }
>  
>  static int mobiveil_msi_set_affinity(struct irq_data *irq_data,
> -		const struct cpumask *mask, bool force)
> +				     const struct cpumask *mask, bool force)
>  {
>  	return -EINVAL;
>  }
> @@ -722,7 +733,8 @@ static struct irq_chip mobiveil_msi_bottom_irq_chip = {
>  };
>  
>  static int mobiveil_irq_msi_domain_alloc(struct irq_domain *domain,
> -		unsigned int virq, unsigned int nr_irqs, void *args)
> +					 unsigned int virq,
> +					 unsigned int nr_irqs, void *args)
>  {
>  	struct mobiveil_pcie *pcie = domain->host_data;
>  	struct mobiveil_msi *msi = &pcie->msi;
> @@ -742,13 +754,13 @@ static int mobiveil_irq_msi_domain_alloc(struct irq_domain *domain,
>  	mutex_unlock(&msi->lock);
>  
>  	irq_domain_set_info(domain, virq, bit, &mobiveil_msi_bottom_irq_chip,
> -				domain->host_data, handle_level_irq,
> -				NULL, NULL);
> +			    domain->host_data, handle_level_irq, NULL, NULL);
>  	return 0;
>  }
>  
>  static void mobiveil_irq_msi_domain_free(struct irq_domain *domain,
> -		unsigned int virq, unsigned int nr_irqs)
> +					 unsigned int virq,
> +					 unsigned int nr_irqs)
>  {
>  	struct irq_data *d = irq_domain_get_irq_data(domain, virq);
>  	struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(d);
> @@ -756,12 +768,11 @@ static void mobiveil_irq_msi_domain_free(struct irq_domain *domain,
>  
>  	mutex_lock(&msi->lock);
>  
> -	if (!test_bit(d->hwirq, msi->msi_irq_in_use)) {
> +	if (!test_bit(d->hwirq, msi->msi_irq_in_use))
>  		dev_err(&pcie->pdev->dev, "trying to free unused MSI#%lu\n",
>  			d->hwirq);
> -	} else {
> +	else
>  		__clear_bit(d->hwirq, msi->msi_irq_in_use);
> -	}
>  
>  	mutex_unlock(&msi->lock);
>  }
> @@ -785,12 +796,14 @@ static int mobiveil_allocate_msi_domains(struct mobiveil_pcie *pcie)
>  	}
>  
>  	msi->msi_domain = pci_msi_create_irq_domain(fwnode,
> -				&mobiveil_msi_domain_info, msi->dev_domain);
> +						    &mobiveil_msi_domain_info,
> +						    msi->dev_domain);
>  	if (!msi->msi_domain) {
>  		dev_err(dev, "failed to create MSI domain\n");
>  		irq_domain_remove(msi->dev_domain);
>  		return -ENOMEM;
>  	}
> +
>  	return 0;
>  }
>  
> @@ -801,8 +814,8 @@ static int mobiveil_pcie_init_irq_domain(struct mobiveil_pcie *pcie)
>  	int ret;
>  
>  	/* setup INTx */
> -	pcie->intx_domain = irq_domain_add_linear(node,
> -				PCI_NUM_INTX, &intx_domain_ops, pcie);
> +	pcie->intx_domain = irq_domain_add_linear(node, PCI_NUM_INTX,
> +						  &intx_domain_ops, pcie);
>  
>  	if (!pcie->intx_domain) {
>  		dev_err(dev, "Failed to get a INTx IRQ domain\n");
> @@ -917,10 +930,10 @@ MODULE_DEVICE_TABLE(of, mobiveil_pcie_of_match);
>  static struct platform_driver mobiveil_pcie_driver = {
>  	.probe = mobiveil_pcie_probe,
>  	.driver = {
> -			.name = "mobiveil-pcie",
> -			.of_match_table = mobiveil_pcie_of_match,
> -			.suppress_bind_attrs = true,
> -		},
> +		.name = "mobiveil-pcie",
> +		.of_match_table = mobiveil_pcie_of_match,
> +		.suppress_bind_attrs = true,
> +	},
>  };
>  
>  builtin_platform_driver(mobiveil_pcie_driver);
> -- 
> 2.17.1
> 

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCHv5 02/20] PCI: mobiveil: Format the code without functionality change
  2019-04-12  8:35 ` [PATCHv5 02/20] PCI: mobiveil: Format the code without functionality change Z.q. Hou
  2019-07-03 15:10   ` Lorenzo Pieralisi
@ 2019-07-03 15:19   ` Lorenzo Pieralisi
  2019-07-03 15:24     ` Lorenzo Pieralisi
  2019-07-04  3:00     ` Z.q. Hou
  1 sibling, 2 replies; 67+ messages in thread
From: Lorenzo Pieralisi @ 2019-07-03 15:19 UTC (permalink / raw)
  To: Z.q. Hou
  Cc: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	catalin.marinas, will.deacon, Mingkai Hu, M.h. Lian, Xiaowei Bao

On Fri, Apr 12, 2019 at 08:35:24AM +0000, Z.q. Hou wrote:
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> 
> Just format the code without functionality change.
> 
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> ---
> V5:
>  - Retouched the subject.
> 
>  drivers/pci/controller/pcie-mobiveil.c | 261 +++++++++++++------------
>  1 file changed, 137 insertions(+), 124 deletions(-)

Ok, dropping this patch means that everything else should be
rebased. So what I am going to do:

- I will publish a branch (pci/mobiveil) where I added the patches
  that are ready to be merged with commit logs rewritten; this patch
  is part of it but in the final version it must be split as requested.
- You have to split this patch and the other patches I requested
  you to split but do NOT modify the patches with my commit logs
  rewritten in pci/mobiveil, it took me time to rewrite them.

If you can manage to rebase patches on pci/mobiveil on top
of v5.2-rc1, send them separately so that I can merge them
as a base for the subsequent patches to be applied.

If you have any questions please ask, do not post patches
if there is something that is not clear.

Lorenzo

> diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c
> index d55c7e780c6e..b87471f08a40 100644
> --- a/drivers/pci/controller/pcie-mobiveil.c
> +++ b/drivers/pci/controller/pcie-mobiveil.c
> @@ -31,38 +31,40 @@
>   * translation tables are grouped into windows, each window registers are
>   * grouped into blocks of 4 or 16 registers each
>   */
> -#define PAB_REG_BLOCK_SIZE	16
> -#define PAB_EXT_REG_BLOCK_SIZE	4
> +#define PAB_REG_BLOCK_SIZE		16
> +#define PAB_EXT_REG_BLOCK_SIZE		4
>  
> -#define PAB_REG_ADDR(offset, win) (offset + (win * PAB_REG_BLOCK_SIZE))
> -#define PAB_EXT_REG_ADDR(offset, win) (offset + (win * PAB_EXT_REG_BLOCK_SIZE))
> +#define PAB_REG_ADDR(offset, win)	\
> +	(offset + (win * PAB_REG_BLOCK_SIZE))
> +#define PAB_EXT_REG_ADDR(offset, win)	\
> +	(offset + (win * PAB_EXT_REG_BLOCK_SIZE))
>  
> -#define LTSSM_STATUS		0x0404
> -#define  LTSSM_STATUS_L0_MASK	0x3f
> -#define  LTSSM_STATUS_L0	0x2d
> +#define LTSSM_STATUS			0x0404
> +#define  LTSSM_STATUS_L0_MASK		0x3f
> +#define  LTSSM_STATUS_L0		0x2d
>  
> -#define PAB_CTRL		0x0808
> -#define  AMBA_PIO_ENABLE_SHIFT	0
> -#define  PEX_PIO_ENABLE_SHIFT	1
> -#define  PAGE_SEL_SHIFT	13
> -#define  PAGE_SEL_MASK		0x3f
> -#define  PAGE_LO_MASK		0x3ff
> -#define  PAGE_SEL_OFFSET_SHIFT	10
> +#define PAB_CTRL			0x0808
> +#define  AMBA_PIO_ENABLE_SHIFT		0
> +#define  PEX_PIO_ENABLE_SHIFT		1
> +#define  PAGE_SEL_SHIFT			13
> +#define  PAGE_SEL_MASK			0x3f
> +#define  PAGE_LO_MASK			0x3ff
> +#define  PAGE_SEL_OFFSET_SHIFT		10
>  
> -#define PAB_AXI_PIO_CTRL	0x0840
> -#define  APIO_EN_MASK		0xf
> +#define PAB_AXI_PIO_CTRL		0x0840
> +#define  APIO_EN_MASK			0xf
>  
> -#define PAB_PEX_PIO_CTRL	0x08c0
> -#define  PIO_ENABLE_SHIFT	0
> +#define PAB_PEX_PIO_CTRL		0x08c0
> +#define  PIO_ENABLE_SHIFT		0
>  
>  #define PAB_INTP_AMBA_MISC_ENB		0x0b0c
> -#define PAB_INTP_AMBA_MISC_STAT	0x0b1c
> +#define PAB_INTP_AMBA_MISC_STAT		0x0b1c
>  #define  PAB_INTP_INTX_MASK		0x01e0
>  #define  PAB_INTP_MSI_MASK		0x8
>  
> -#define PAB_AXI_AMAP_CTRL(win)	PAB_REG_ADDR(0x0ba0, win)
> -#define  WIN_ENABLE_SHIFT	0
> -#define  WIN_TYPE_SHIFT	1
> +#define PAB_AXI_AMAP_CTRL(win)		PAB_REG_ADDR(0x0ba0, win)
> +#define  WIN_ENABLE_SHIFT		0
> +#define  WIN_TYPE_SHIFT			1
>  
>  #define PAB_EXT_AXI_AMAP_SIZE(win)	PAB_EXT_REG_ADDR(0xbaf0, win)
>  
> @@ -70,16 +72,16 @@
>  #define  AXI_WINDOW_ALIGN_MASK		3
>  
>  #define PAB_AXI_AMAP_PEX_WIN_L(win)	PAB_REG_ADDR(0x0ba8, win)
> -#define  PAB_BUS_SHIFT		24
> -#define  PAB_DEVICE_SHIFT	19
> -#define  PAB_FUNCTION_SHIFT	16
> +#define  PAB_BUS_SHIFT			24
> +#define  PAB_DEVICE_SHIFT		19
> +#define  PAB_FUNCTION_SHIFT		16
>  
>  #define PAB_AXI_AMAP_PEX_WIN_H(win)	PAB_REG_ADDR(0x0bac, win)
>  #define PAB_INTP_AXI_PIO_CLASS		0x474
>  
> -#define PAB_PEX_AMAP_CTRL(win)	PAB_REG_ADDR(0x4ba0, win)
> -#define  AMAP_CTRL_EN_SHIFT	0
> -#define  AMAP_CTRL_TYPE_SHIFT	1
> +#define PAB_PEX_AMAP_CTRL(win)		PAB_REG_ADDR(0x4ba0, win)
> +#define  AMAP_CTRL_EN_SHIFT		0
> +#define  AMAP_CTRL_TYPE_SHIFT		1
>  
>  #define PAB_EXT_PEX_AMAP_SIZEN(win)	PAB_EXT_REG_ADDR(0xbef0, win)
>  #define PAB_PEX_AMAP_AXI_WIN(win)	PAB_REG_ADDR(0x4ba4, win)
> @@ -87,39 +89,39 @@
>  #define PAB_PEX_AMAP_PEX_WIN_H(win)	PAB_REG_ADDR(0x4bac, win)
>  
>  /* starting offset of INTX bits in status register */
> -#define PAB_INTX_START	5
> +#define PAB_INTX_START			5
>  
>  /* supported number of MSI interrupts */
> -#define PCI_NUM_MSI	16
> +#define PCI_NUM_MSI			16
>  
>  /* MSI registers */
> -#define MSI_BASE_LO_OFFSET	0x04
> -#define MSI_BASE_HI_OFFSET	0x08
> -#define MSI_SIZE_OFFSET	0x0c
> -#define MSI_ENABLE_OFFSET	0x14
> -#define MSI_STATUS_OFFSET	0x18
> -#define MSI_DATA_OFFSET	0x20
> -#define MSI_ADDR_L_OFFSET	0x24
> -#define MSI_ADDR_H_OFFSET	0x28
> +#define MSI_BASE_LO_OFFSET		0x04
> +#define MSI_BASE_HI_OFFSET		0x08
> +#define MSI_SIZE_OFFSET			0x0c
> +#define MSI_ENABLE_OFFSET		0x14
> +#define MSI_STATUS_OFFSET		0x18
> +#define MSI_DATA_OFFSET			0x20
> +#define MSI_ADDR_L_OFFSET		0x24
> +#define MSI_ADDR_H_OFFSET		0x28
>  
>  /* outbound and inbound window definitions */
> -#define WIN_NUM_0		0
> -#define WIN_NUM_1		1
> -#define CFG_WINDOW_TYPE	0
> -#define IO_WINDOW_TYPE		1
> -#define MEM_WINDOW_TYPE	2
> -#define IB_WIN_SIZE		((u64)256 * 1024 * 1024 * 1024)
> -#define MAX_PIO_WINDOWS	8
> +#define WIN_NUM_0			0
> +#define WIN_NUM_1			1
> +#define CFG_WINDOW_TYPE			0
> +#define IO_WINDOW_TYPE			1
> +#define MEM_WINDOW_TYPE			2
> +#define IB_WIN_SIZE			((u64)256 * 1024 * 1024 * 1024)
> +#define MAX_PIO_WINDOWS			8
>  
>  /* Parameters for the waiting for link up routine */
> -#define LINK_WAIT_MAX_RETRIES	10
> -#define LINK_WAIT_MIN	90000
> -#define LINK_WAIT_MAX	100000
> +#define LINK_WAIT_MAX_RETRIES		10
> +#define LINK_WAIT_MIN			90000
> +#define LINK_WAIT_MAX			100000
>  
> -#define PAGED_ADDR_BNDRY			0xc00
> -#define OFFSET_TO_PAGE_ADDR(off)		\
> +#define PAGED_ADDR_BNDRY		0xc00
> +#define OFFSET_TO_PAGE_ADDR(off)	\
>  	((off & PAGE_LO_MASK) | PAGED_ADDR_BNDRY)
> -#define OFFSET_TO_PAGE_IDX(off)			\
> +#define OFFSET_TO_PAGE_IDX(off)		\
>  	((off >> PAGE_SEL_OFFSET_SHIFT) & PAGE_SEL_MASK)
>  
>  struct mobiveil_msi {			/* MSI information */
> @@ -297,14 +299,14 @@ static void __iomem *mobiveil_pcie_map_bus(struct pci_bus *bus,
>  					unsigned int devfn, int where)
>  {
>  	struct mobiveil_pcie *pcie = bus->sysdata;
> +	u32 value;
>  
>  	if (!mobiveil_pcie_valid_device(bus, devfn))
>  		return NULL;
>  
> -	if (bus->number == pcie->root_bus_nr) {
> -		/* RC config access */
> +	/* RC config access */
> +	if (bus->number == pcie->root_bus_nr)
>  		return pcie->csr_axi_slave_base + where;
> -	}
>  
>  	/*
>  	 * EP config access (in Config/APIO space)
> @@ -312,10 +314,12 @@ static void __iomem *mobiveil_pcie_map_bus(struct pci_bus *bus,
>  	 * (BDF) in PAB_AXI_AMAP_PEX_WIN_L0 Register.
>  	 * Relies on pci_lock serialization
>  	 */
> -	csr_writel(pcie, bus->number << PAB_BUS_SHIFT |
> -			PCI_SLOT(devfn) << PAB_DEVICE_SHIFT |
> -			PCI_FUNC(devfn) << PAB_FUNCTION_SHIFT,
> -			PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0));
> +	value = bus->number << PAB_BUS_SHIFT |
> +		PCI_SLOT(devfn) << PAB_DEVICE_SHIFT |
> +		PCI_FUNC(devfn) << PAB_FUNCTION_SHIFT;
> +
> +	csr_writel(pcie, value, PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0));
> +
>  	return pcie->config_axi_slave_base + where;
>  }
>  
> @@ -350,22 +354,22 @@ static void mobiveil_pcie_isr(struct irq_desc *desc)
>  
>  	/* Handle INTx */
>  	if (intr_status & PAB_INTP_INTX_MASK) {
> -		shifted_status = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT) >>
> -			PAB_INTX_START;
> +		shifted_status = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT);
> +		shifted_status >>= PAB_INTX_START;
>  		do {
>  			for_each_set_bit(bit, &shifted_status, PCI_NUM_INTX) {
>  				virq = irq_find_mapping(pcie->intx_domain,
> -						bit + 1);
> +							bit + 1);
>  				if (virq)
>  					generic_handle_irq(virq);
>  				else
> -					dev_err_ratelimited(dev,
> -						"unexpected IRQ, INT%d\n", bit);
> +					dev_err_ratelimited(dev, "unexpected IRQ, INT%d\n",
> +							    bit);
>  
>  				/* clear interrupt */
>  				csr_writel(pcie,
> -					shifted_status << PAB_INTX_START,
> -					PAB_INTP_AMBA_MISC_STAT);
> +					   shifted_status << PAB_INTX_START,
> +					   PAB_INTP_AMBA_MISC_STAT);
>  			}
>  		} while ((shifted_status >> PAB_INTX_START) != 0);
>  	}
> @@ -375,8 +379,7 @@ static void mobiveil_pcie_isr(struct irq_desc *desc)
>  
>  	/* handle MSI interrupts */
>  	while (msi_status & 1) {
> -		msi_data = readl_relaxed(pcie->apb_csr_base
> -				+ MSI_DATA_OFFSET);
> +		msi_data = readl_relaxed(pcie->apb_csr_base + MSI_DATA_OFFSET);
>  
>  		/*
>  		 * MSI_STATUS_OFFSET register gets updated to zero
> @@ -385,18 +388,18 @@ static void mobiveil_pcie_isr(struct irq_desc *desc)
>  		 * two dummy reads.
>  		 */
>  		msi_addr_lo = readl_relaxed(pcie->apb_csr_base +
> -				MSI_ADDR_L_OFFSET);
> +					    MSI_ADDR_L_OFFSET);
>  		msi_addr_hi = readl_relaxed(pcie->apb_csr_base +
> -				MSI_ADDR_H_OFFSET);
> +					    MSI_ADDR_H_OFFSET);
>  		dev_dbg(dev, "MSI registers, data: %08x, addr: %08x:%08x\n",
> -				msi_data, msi_addr_hi, msi_addr_lo);
> +			msi_data, msi_addr_hi, msi_addr_lo);
>  
>  		virq = irq_find_mapping(msi->dev_domain, msi_data);
>  		if (virq)
>  			generic_handle_irq(virq);
>  
>  		msi_status = readl_relaxed(pcie->apb_csr_base +
> -				MSI_STATUS_OFFSET);
> +					   MSI_STATUS_OFFSET);
>  	}
>  
>  	/* Clear the interrupt status */
> @@ -413,7 +416,7 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie)
>  
>  	/* map config resource */
>  	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> -			"config_axi_slave");
> +					   "config_axi_slave");
>  	pcie->config_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);
>  	if (IS_ERR(pcie->config_axi_slave_base))
>  		return PTR_ERR(pcie->config_axi_slave_base);
> @@ -421,7 +424,7 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie)
>  
>  	/* map csr resource */
>  	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> -			"csr_axi_slave");
> +					   "csr_axi_slave");
>  	pcie->csr_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);
>  	if (IS_ERR(pcie->csr_axi_slave_base))
>  		return PTR_ERR(pcie->csr_axi_slave_base);
> @@ -452,7 +455,7 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie)
>  }
>  
>  static void program_ib_windows(struct mobiveil_pcie *pcie, int win_num,
> -		int pci_addr, u32 type, u64 size)
> +			       int pci_addr, u32 type, u64 size)
>  {
>  	int pio_ctrl_val;
>  	int amap_ctrl_dw;
> @@ -465,19 +468,20 @@ static void program_ib_windows(struct mobiveil_pcie *pcie, int win_num,
>  	}
>  
>  	pio_ctrl_val = csr_readl(pcie, PAB_PEX_PIO_CTRL);
> -	csr_writel(pcie,
> -		pio_ctrl_val | (1 << PIO_ENABLE_SHIFT), PAB_PEX_PIO_CTRL);
> -	amap_ctrl_dw = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
> -	amap_ctrl_dw = (amap_ctrl_dw | (type << AMAP_CTRL_TYPE_SHIFT));
> -	amap_ctrl_dw = (amap_ctrl_dw | (1 << AMAP_CTRL_EN_SHIFT));
> +	pio_ctrl_val |= 1 << PIO_ENABLE_SHIFT;
> +	csr_writel(pcie, pio_ctrl_val, PAB_PEX_PIO_CTRL);
>  
> -	csr_writel(pcie, amap_ctrl_dw | lower_32_bits(size64),
> -		   PAB_PEX_AMAP_CTRL(win_num));
> +	amap_ctrl_dw = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
> +	amap_ctrl_dw |= (type << AMAP_CTRL_TYPE_SHIFT) |
> +			(1 << AMAP_CTRL_EN_SHIFT) |
> +			lower_32_bits(size64);
> +	csr_writel(pcie, amap_ctrl_dw, PAB_PEX_AMAP_CTRL(win_num));
>  
>  	csr_writel(pcie, upper_32_bits(size64),
>  		   PAB_EXT_PEX_AMAP_SIZEN(win_num));
>  
>  	csr_writel(pcie, pci_addr, PAB_PEX_AMAP_AXI_WIN(win_num));
> +
>  	csr_writel(pcie, pci_addr, PAB_PEX_AMAP_PEX_WIN_L(win_num));
>  	csr_writel(pcie, 0, PAB_PEX_AMAP_PEX_WIN_H(win_num));
>  }
> @@ -486,7 +490,8 @@ static void program_ib_windows(struct mobiveil_pcie *pcie, int win_num,
>   * routine to program the outbound windows
>   */
>  static void program_ob_windows(struct mobiveil_pcie *pcie, int win_num,
> -		u64 cpu_addr, u64 pci_addr, u32 config_io_bit, u64 size)
> +			       u64 cpu_addr, u64 pci_addr,
> +			       u32 config_io_bit, u64 size)
>  {
>  
>  	u32 value, type;
> @@ -505,7 +510,7 @@ static void program_ob_windows(struct mobiveil_pcie *pcie, int win_num,
>  	type = config_io_bit;
>  	value = csr_readl(pcie, PAB_AXI_AMAP_CTRL(win_num));
>  	csr_writel(pcie, 1 << WIN_ENABLE_SHIFT | type << WIN_TYPE_SHIFT |
> -			lower_32_bits(size64), PAB_AXI_AMAP_CTRL(win_num));
> +		   lower_32_bits(size64), PAB_AXI_AMAP_CTRL(win_num));
>  
>  	csr_writel(pcie, upper_32_bits(size64), PAB_EXT_AXI_AMAP_SIZE(win_num));
>  
> @@ -515,14 +520,14 @@ static void program_ob_windows(struct mobiveil_pcie *pcie, int win_num,
>  	 */
>  	value = csr_readl(pcie, PAB_AXI_AMAP_AXI_WIN(win_num));
>  	csr_writel(pcie, cpu_addr & (~AXI_WINDOW_ALIGN_MASK),
> -			PAB_AXI_AMAP_AXI_WIN(win_num));
> +		   PAB_AXI_AMAP_AXI_WIN(win_num));
>  
>  	value = csr_readl(pcie, PAB_AXI_AMAP_PEX_WIN_H(win_num));
>  
>  	csr_writel(pcie, lower_32_bits(pci_addr),
> -			PAB_AXI_AMAP_PEX_WIN_L(win_num));
> +		   PAB_AXI_AMAP_PEX_WIN_L(win_num));
>  	csr_writel(pcie, upper_32_bits(pci_addr),
> -			PAB_AXI_AMAP_PEX_WIN_H(win_num));
> +		   PAB_AXI_AMAP_PEX_WIN_H(win_num));
>  
>  	pcie->ob_wins_configured++;
>  }
> @@ -538,7 +543,9 @@ static int mobiveil_bringup_link(struct mobiveil_pcie *pcie)
>  
>  		usleep_range(LINK_WAIT_MIN, LINK_WAIT_MAX);
>  	}
> +
>  	dev_err(&pcie->pdev->dev, "link never came up\n");
> +
>  	return -ETIMEDOUT;
>  }
>  
> @@ -551,16 +558,16 @@ static void mobiveil_pcie_enable_msi(struct mobiveil_pcie *pcie)
>  	msi->msi_pages_phys = (phys_addr_t)msg_addr;
>  
>  	writel_relaxed(lower_32_bits(msg_addr),
> -		pcie->apb_csr_base + MSI_BASE_LO_OFFSET);
> +		       pcie->apb_csr_base + MSI_BASE_LO_OFFSET);
>  	writel_relaxed(upper_32_bits(msg_addr),
> -		pcie->apb_csr_base + MSI_BASE_HI_OFFSET);
> +		       pcie->apb_csr_base + MSI_BASE_HI_OFFSET);
>  	writel_relaxed(4096, pcie->apb_csr_base + MSI_SIZE_OFFSET);
>  	writel_relaxed(1, pcie->apb_csr_base + MSI_ENABLE_OFFSET);
>  }
>  
>  static int mobiveil_host_init(struct mobiveil_pcie *pcie)
>  {
> -	u32 value, pab_ctrl, type = 0;
> +	u32 value, pab_ctrl, type;
>  	int err;
>  	struct resource_entry *win, *tmp;
>  
> @@ -575,26 +582,27 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
>  	 * Space
>  	 */
>  	value = csr_readl(pcie, PCI_COMMAND);
> -	csr_writel(pcie, value | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
> -		PCI_COMMAND_MASTER, PCI_COMMAND);
> +	value |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
> +	csr_writel(pcie, value, PCI_COMMAND);
>  
>  	/*
>  	 * program PIO Enable Bit to 1 (and PEX PIO Enable to 1) in PAB_CTRL
>  	 * register
>  	 */
>  	pab_ctrl = csr_readl(pcie, PAB_CTRL);
> -	csr_writel(pcie, pab_ctrl | (1 << AMBA_PIO_ENABLE_SHIFT) |
> -		(1 << PEX_PIO_ENABLE_SHIFT), PAB_CTRL);
> +	pab_ctrl |= (1 << AMBA_PIO_ENABLE_SHIFT) | (1 << PEX_PIO_ENABLE_SHIFT);
> +	csr_writel(pcie, pab_ctrl, PAB_CTRL);
>  
>  	csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK),
> -		PAB_INTP_AMBA_MISC_ENB);
> +		   PAB_INTP_AMBA_MISC_ENB);
>  
>  	/*
>  	 * program PIO Enable Bit to 1 and Config Window Enable Bit to 1 in
>  	 * PAB_AXI_PIO_CTRL Register
>  	 */
>  	value = csr_readl(pcie, PAB_AXI_PIO_CTRL);
> -	csr_writel(pcie, value | APIO_EN_MASK, PAB_AXI_PIO_CTRL);
> +	value |= APIO_EN_MASK;
> +	csr_writel(pcie, value, PAB_AXI_PIO_CTRL);
>  
>  	/*
>  	 * we'll program one outbound window for config reads and
> @@ -605,25 +613,25 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
>  
>  	/* config outbound translation window */
>  	program_ob_windows(pcie, pcie->ob_wins_configured,
> -			pcie->ob_io_res->start, 0, CFG_WINDOW_TYPE,
> -			resource_size(pcie->ob_io_res));
> +			   pcie->ob_io_res->start, 0, CFG_WINDOW_TYPE,
> +			   resource_size(pcie->ob_io_res));
>  
>  	/* memory inbound translation window */
>  	program_ib_windows(pcie, WIN_NUM_1, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE);
>  
>  	/* Get the I/O and memory ranges from DT */
>  	resource_list_for_each_entry_safe(win, tmp, &pcie->resources) {
> -		type = 0;
>  		if (resource_type(win->res) == IORESOURCE_MEM)
>  			type = MEM_WINDOW_TYPE;
> -		if (resource_type(win->res) == IORESOURCE_IO)
> +		else if (resource_type(win->res) == IORESOURCE_IO)
>  			type = IO_WINDOW_TYPE;
> -		if (type) {
> -			/* configure outbound translation window */
> -			program_ob_windows(pcie, pcie->ob_wins_configured,
> -				win->res->start, 0, type,
> -				resource_size(win->res));
> -		}
> +		else
> +			continue;
> +
> +		/* configure outbound translation window */
> +		program_ob_windows(pcie, pcie->ob_wins_configured,
> +				   win->res->start, 0, type,
> +				   resource_size(win->res));
>  	}
>  
>  	/* setup MSI hardware registers */
> @@ -643,7 +651,8 @@ static void mobiveil_mask_intx_irq(struct irq_data *data)
>  	mask = 1 << ((data->hwirq + PAB_INTX_START) - 1);
>  	raw_spin_lock_irqsave(&pcie->intx_mask_lock, flags);
>  	shifted_val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
> -	csr_writel(pcie, (shifted_val & (~mask)), PAB_INTP_AMBA_MISC_ENB);
> +	shifted_val &= ~mask;
> +	csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
>  	raw_spin_unlock_irqrestore(&pcie->intx_mask_lock, flags);
>  }
>  
> @@ -658,7 +667,8 @@ static void mobiveil_unmask_intx_irq(struct irq_data *data)
>  	mask = 1 << ((data->hwirq + PAB_INTX_START) - 1);
>  	raw_spin_lock_irqsave(&pcie->intx_mask_lock, flags);
>  	shifted_val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
> -	csr_writel(pcie, (shifted_val | mask), PAB_INTP_AMBA_MISC_ENB);
> +	shifted_val |= mask;
> +	csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
>  	raw_spin_unlock_irqrestore(&pcie->intx_mask_lock, flags);
>  }
>  
> @@ -672,10 +682,11 @@ static struct irq_chip intx_irq_chip = {
>  
>  /* routine to setup the INTx related data */
>  static int mobiveil_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
> -		irq_hw_number_t hwirq)
> +				  irq_hw_number_t hwirq)
>  {
>  	irq_set_chip_and_handler(irq, &intx_irq_chip, handle_level_irq);
>  	irq_set_chip_data(irq, domain->host_data);
> +
>  	return 0;
>  }
>  
> @@ -692,7 +703,7 @@ static struct irq_chip mobiveil_msi_irq_chip = {
>  
>  static struct msi_domain_info mobiveil_msi_domain_info = {
>  	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
> -		MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX),
> +		   MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX),
>  	.chip	= &mobiveil_msi_irq_chip,
>  };
>  
> @@ -710,7 +721,7 @@ static void mobiveil_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
>  }
>  
>  static int mobiveil_msi_set_affinity(struct irq_data *irq_data,
> -		const struct cpumask *mask, bool force)
> +				     const struct cpumask *mask, bool force)
>  {
>  	return -EINVAL;
>  }
> @@ -722,7 +733,8 @@ static struct irq_chip mobiveil_msi_bottom_irq_chip = {
>  };
>  
>  static int mobiveil_irq_msi_domain_alloc(struct irq_domain *domain,
> -		unsigned int virq, unsigned int nr_irqs, void *args)
> +					 unsigned int virq,
> +					 unsigned int nr_irqs, void *args)
>  {
>  	struct mobiveil_pcie *pcie = domain->host_data;
>  	struct mobiveil_msi *msi = &pcie->msi;
> @@ -742,13 +754,13 @@ static int mobiveil_irq_msi_domain_alloc(struct irq_domain *domain,
>  	mutex_unlock(&msi->lock);
>  
>  	irq_domain_set_info(domain, virq, bit, &mobiveil_msi_bottom_irq_chip,
> -				domain->host_data, handle_level_irq,
> -				NULL, NULL);
> +			    domain->host_data, handle_level_irq, NULL, NULL);
>  	return 0;
>  }
>  
>  static void mobiveil_irq_msi_domain_free(struct irq_domain *domain,
> -		unsigned int virq, unsigned int nr_irqs)
> +					 unsigned int virq,
> +					 unsigned int nr_irqs)
>  {
>  	struct irq_data *d = irq_domain_get_irq_data(domain, virq);
>  	struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(d);
> @@ -756,12 +768,11 @@ static void mobiveil_irq_msi_domain_free(struct irq_domain *domain,
>  
>  	mutex_lock(&msi->lock);
>  
> -	if (!test_bit(d->hwirq, msi->msi_irq_in_use)) {
> +	if (!test_bit(d->hwirq, msi->msi_irq_in_use))
>  		dev_err(&pcie->pdev->dev, "trying to free unused MSI#%lu\n",
>  			d->hwirq);
> -	} else {
> +	else
>  		__clear_bit(d->hwirq, msi->msi_irq_in_use);
> -	}
>  
>  	mutex_unlock(&msi->lock);
>  }
> @@ -785,12 +796,14 @@ static int mobiveil_allocate_msi_domains(struct mobiveil_pcie *pcie)
>  	}
>  
>  	msi->msi_domain = pci_msi_create_irq_domain(fwnode,
> -				&mobiveil_msi_domain_info, msi->dev_domain);
> +						    &mobiveil_msi_domain_info,
> +						    msi->dev_domain);
>  	if (!msi->msi_domain) {
>  		dev_err(dev, "failed to create MSI domain\n");
>  		irq_domain_remove(msi->dev_domain);
>  		return -ENOMEM;
>  	}
> +
>  	return 0;
>  }
>  
> @@ -801,8 +814,8 @@ static int mobiveil_pcie_init_irq_domain(struct mobiveil_pcie *pcie)
>  	int ret;
>  
>  	/* setup INTx */
> -	pcie->intx_domain = irq_domain_add_linear(node,
> -				PCI_NUM_INTX, &intx_domain_ops, pcie);
> +	pcie->intx_domain = irq_domain_add_linear(node, PCI_NUM_INTX,
> +						  &intx_domain_ops, pcie);
>  
>  	if (!pcie->intx_domain) {
>  		dev_err(dev, "Failed to get a INTx IRQ domain\n");
> @@ -917,10 +930,10 @@ MODULE_DEVICE_TABLE(of, mobiveil_pcie_of_match);
>  static struct platform_driver mobiveil_pcie_driver = {
>  	.probe = mobiveil_pcie_probe,
>  	.driver = {
> -			.name = "mobiveil-pcie",
> -			.of_match_table = mobiveil_pcie_of_match,
> -			.suppress_bind_attrs = true,
> -		},
> +		.name = "mobiveil-pcie",
> +		.of_match_table = mobiveil_pcie_of_match,
> +		.suppress_bind_attrs = true,
> +	},
>  };
>  
>  builtin_platform_driver(mobiveil_pcie_driver);
> -- 
> 2.17.1
> 

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCHv5 02/20] PCI: mobiveil: Format the code without functionality change
  2019-07-03 15:19   ` Lorenzo Pieralisi
@ 2019-07-03 15:24     ` Lorenzo Pieralisi
  2019-07-04  3:00     ` Z.q. Hou
  1 sibling, 0 replies; 67+ messages in thread
From: Lorenzo Pieralisi @ 2019-07-03 15:24 UTC (permalink / raw)
  To: Z.q. Hou
  Cc: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	catalin.marinas, will.deacon, Mingkai Hu, M.h. Lian, Xiaowei Bao

On Wed, Jul 03, 2019 at 04:19:05PM +0100, Lorenzo Pieralisi wrote:
> On Fri, Apr 12, 2019 at 08:35:24AM +0000, Z.q. Hou wrote:
> > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > 
> > Just format the code without functionality change.
> > 
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> > ---
> > V5:
> >  - Retouched the subject.
> > 
> >  drivers/pci/controller/pcie-mobiveil.c | 261 +++++++++++++------------
> >  1 file changed, 137 insertions(+), 124 deletions(-)
> 
> Ok, dropping this patch means that everything else should be
> rebased. So what I am going to do:
> 
> - I will publish a branch (pci/mobiveil) where I added the patches
>   that are ready to be merged with commit logs rewritten; this patch
>   is part of it but in the final version it must be split as requested.
> - You have to split this patch and the other patches I requested
>   you to split but do NOT modify the patches with my commit logs
>   rewritten in pci/mobiveil, it took me time to rewrite them.
> 
> If you can manage to rebase patches on pci/mobiveil on top
> of v5.2-rc1, send them separately so that I can merge them
> as a base for the subsequent patches to be applied.
> 
> If you have any questions please ask, do not post patches
> if there is something that is not clear.

This is the branch mentioned above:

https://git.kernel.org/pub/scm/linux/kernel/git/lpieralisi/pci.git/log/?h=not-to-merge/pci/mobiveil

> Lorenzo
> 
> > diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c
> > index d55c7e780c6e..b87471f08a40 100644
> > --- a/drivers/pci/controller/pcie-mobiveil.c
> > +++ b/drivers/pci/controller/pcie-mobiveil.c
> > @@ -31,38 +31,40 @@
> >   * translation tables are grouped into windows, each window registers are
> >   * grouped into blocks of 4 or 16 registers each
> >   */
> > -#define PAB_REG_BLOCK_SIZE	16
> > -#define PAB_EXT_REG_BLOCK_SIZE	4
> > +#define PAB_REG_BLOCK_SIZE		16
> > +#define PAB_EXT_REG_BLOCK_SIZE		4
> >  
> > -#define PAB_REG_ADDR(offset, win) (offset + (win * PAB_REG_BLOCK_SIZE))
> > -#define PAB_EXT_REG_ADDR(offset, win) (offset + (win * PAB_EXT_REG_BLOCK_SIZE))
> > +#define PAB_REG_ADDR(offset, win)	\
> > +	(offset + (win * PAB_REG_BLOCK_SIZE))
> > +#define PAB_EXT_REG_ADDR(offset, win)	\
> > +	(offset + (win * PAB_EXT_REG_BLOCK_SIZE))
> >  
> > -#define LTSSM_STATUS		0x0404
> > -#define  LTSSM_STATUS_L0_MASK	0x3f
> > -#define  LTSSM_STATUS_L0	0x2d
> > +#define LTSSM_STATUS			0x0404
> > +#define  LTSSM_STATUS_L0_MASK		0x3f
> > +#define  LTSSM_STATUS_L0		0x2d
> >  
> > -#define PAB_CTRL		0x0808
> > -#define  AMBA_PIO_ENABLE_SHIFT	0
> > -#define  PEX_PIO_ENABLE_SHIFT	1
> > -#define  PAGE_SEL_SHIFT	13
> > -#define  PAGE_SEL_MASK		0x3f
> > -#define  PAGE_LO_MASK		0x3ff
> > -#define  PAGE_SEL_OFFSET_SHIFT	10
> > +#define PAB_CTRL			0x0808
> > +#define  AMBA_PIO_ENABLE_SHIFT		0
> > +#define  PEX_PIO_ENABLE_SHIFT		1
> > +#define  PAGE_SEL_SHIFT			13
> > +#define  PAGE_SEL_MASK			0x3f
> > +#define  PAGE_LO_MASK			0x3ff
> > +#define  PAGE_SEL_OFFSET_SHIFT		10
> >  
> > -#define PAB_AXI_PIO_CTRL	0x0840
> > -#define  APIO_EN_MASK		0xf
> > +#define PAB_AXI_PIO_CTRL		0x0840
> > +#define  APIO_EN_MASK			0xf
> >  
> > -#define PAB_PEX_PIO_CTRL	0x08c0
> > -#define  PIO_ENABLE_SHIFT	0
> > +#define PAB_PEX_PIO_CTRL		0x08c0
> > +#define  PIO_ENABLE_SHIFT		0
> >  
> >  #define PAB_INTP_AMBA_MISC_ENB		0x0b0c
> > -#define PAB_INTP_AMBA_MISC_STAT	0x0b1c
> > +#define PAB_INTP_AMBA_MISC_STAT		0x0b1c
> >  #define  PAB_INTP_INTX_MASK		0x01e0
> >  #define  PAB_INTP_MSI_MASK		0x8
> >  
> > -#define PAB_AXI_AMAP_CTRL(win)	PAB_REG_ADDR(0x0ba0, win)
> > -#define  WIN_ENABLE_SHIFT	0
> > -#define  WIN_TYPE_SHIFT	1
> > +#define PAB_AXI_AMAP_CTRL(win)		PAB_REG_ADDR(0x0ba0, win)
> > +#define  WIN_ENABLE_SHIFT		0
> > +#define  WIN_TYPE_SHIFT			1
> >  
> >  #define PAB_EXT_AXI_AMAP_SIZE(win)	PAB_EXT_REG_ADDR(0xbaf0, win)
> >  
> > @@ -70,16 +72,16 @@
> >  #define  AXI_WINDOW_ALIGN_MASK		3
> >  
> >  #define PAB_AXI_AMAP_PEX_WIN_L(win)	PAB_REG_ADDR(0x0ba8, win)
> > -#define  PAB_BUS_SHIFT		24
> > -#define  PAB_DEVICE_SHIFT	19
> > -#define  PAB_FUNCTION_SHIFT	16
> > +#define  PAB_BUS_SHIFT			24
> > +#define  PAB_DEVICE_SHIFT		19
> > +#define  PAB_FUNCTION_SHIFT		16
> >  
> >  #define PAB_AXI_AMAP_PEX_WIN_H(win)	PAB_REG_ADDR(0x0bac, win)
> >  #define PAB_INTP_AXI_PIO_CLASS		0x474
> >  
> > -#define PAB_PEX_AMAP_CTRL(win)	PAB_REG_ADDR(0x4ba0, win)
> > -#define  AMAP_CTRL_EN_SHIFT	0
> > -#define  AMAP_CTRL_TYPE_SHIFT	1
> > +#define PAB_PEX_AMAP_CTRL(win)		PAB_REG_ADDR(0x4ba0, win)
> > +#define  AMAP_CTRL_EN_SHIFT		0
> > +#define  AMAP_CTRL_TYPE_SHIFT		1
> >  
> >  #define PAB_EXT_PEX_AMAP_SIZEN(win)	PAB_EXT_REG_ADDR(0xbef0, win)
> >  #define PAB_PEX_AMAP_AXI_WIN(win)	PAB_REG_ADDR(0x4ba4, win)
> > @@ -87,39 +89,39 @@
> >  #define PAB_PEX_AMAP_PEX_WIN_H(win)	PAB_REG_ADDR(0x4bac, win)
> >  
> >  /* starting offset of INTX bits in status register */
> > -#define PAB_INTX_START	5
> > +#define PAB_INTX_START			5
> >  
> >  /* supported number of MSI interrupts */
> > -#define PCI_NUM_MSI	16
> > +#define PCI_NUM_MSI			16
> >  
> >  /* MSI registers */
> > -#define MSI_BASE_LO_OFFSET	0x04
> > -#define MSI_BASE_HI_OFFSET	0x08
> > -#define MSI_SIZE_OFFSET	0x0c
> > -#define MSI_ENABLE_OFFSET	0x14
> > -#define MSI_STATUS_OFFSET	0x18
> > -#define MSI_DATA_OFFSET	0x20
> > -#define MSI_ADDR_L_OFFSET	0x24
> > -#define MSI_ADDR_H_OFFSET	0x28
> > +#define MSI_BASE_LO_OFFSET		0x04
> > +#define MSI_BASE_HI_OFFSET		0x08
> > +#define MSI_SIZE_OFFSET			0x0c
> > +#define MSI_ENABLE_OFFSET		0x14
> > +#define MSI_STATUS_OFFSET		0x18
> > +#define MSI_DATA_OFFSET			0x20
> > +#define MSI_ADDR_L_OFFSET		0x24
> > +#define MSI_ADDR_H_OFFSET		0x28
> >  
> >  /* outbound and inbound window definitions */
> > -#define WIN_NUM_0		0
> > -#define WIN_NUM_1		1
> > -#define CFG_WINDOW_TYPE	0
> > -#define IO_WINDOW_TYPE		1
> > -#define MEM_WINDOW_TYPE	2
> > -#define IB_WIN_SIZE		((u64)256 * 1024 * 1024 * 1024)
> > -#define MAX_PIO_WINDOWS	8
> > +#define WIN_NUM_0			0
> > +#define WIN_NUM_1			1
> > +#define CFG_WINDOW_TYPE			0
> > +#define IO_WINDOW_TYPE			1
> > +#define MEM_WINDOW_TYPE			2
> > +#define IB_WIN_SIZE			((u64)256 * 1024 * 1024 * 1024)
> > +#define MAX_PIO_WINDOWS			8
> >  
> >  /* Parameters for the waiting for link up routine */
> > -#define LINK_WAIT_MAX_RETRIES	10
> > -#define LINK_WAIT_MIN	90000
> > -#define LINK_WAIT_MAX	100000
> > +#define LINK_WAIT_MAX_RETRIES		10
> > +#define LINK_WAIT_MIN			90000
> > +#define LINK_WAIT_MAX			100000
> >  
> > -#define PAGED_ADDR_BNDRY			0xc00
> > -#define OFFSET_TO_PAGE_ADDR(off)		\
> > +#define PAGED_ADDR_BNDRY		0xc00
> > +#define OFFSET_TO_PAGE_ADDR(off)	\
> >  	((off & PAGE_LO_MASK) | PAGED_ADDR_BNDRY)
> > -#define OFFSET_TO_PAGE_IDX(off)			\
> > +#define OFFSET_TO_PAGE_IDX(off)		\
> >  	((off >> PAGE_SEL_OFFSET_SHIFT) & PAGE_SEL_MASK)
> >  
> >  struct mobiveil_msi {			/* MSI information */
> > @@ -297,14 +299,14 @@ static void __iomem *mobiveil_pcie_map_bus(struct pci_bus *bus,
> >  					unsigned int devfn, int where)
> >  {
> >  	struct mobiveil_pcie *pcie = bus->sysdata;
> > +	u32 value;
> >  
> >  	if (!mobiveil_pcie_valid_device(bus, devfn))
> >  		return NULL;
> >  
> > -	if (bus->number == pcie->root_bus_nr) {
> > -		/* RC config access */
> > +	/* RC config access */
> > +	if (bus->number == pcie->root_bus_nr)
> >  		return pcie->csr_axi_slave_base + where;
> > -	}
> >  
> >  	/*
> >  	 * EP config access (in Config/APIO space)
> > @@ -312,10 +314,12 @@ static void __iomem *mobiveil_pcie_map_bus(struct pci_bus *bus,
> >  	 * (BDF) in PAB_AXI_AMAP_PEX_WIN_L0 Register.
> >  	 * Relies on pci_lock serialization
> >  	 */
> > -	csr_writel(pcie, bus->number << PAB_BUS_SHIFT |
> > -			PCI_SLOT(devfn) << PAB_DEVICE_SHIFT |
> > -			PCI_FUNC(devfn) << PAB_FUNCTION_SHIFT,
> > -			PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0));
> > +	value = bus->number << PAB_BUS_SHIFT |
> > +		PCI_SLOT(devfn) << PAB_DEVICE_SHIFT |
> > +		PCI_FUNC(devfn) << PAB_FUNCTION_SHIFT;
> > +
> > +	csr_writel(pcie, value, PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0));
> > +
> >  	return pcie->config_axi_slave_base + where;
> >  }
> >  
> > @@ -350,22 +354,22 @@ static void mobiveil_pcie_isr(struct irq_desc *desc)
> >  
> >  	/* Handle INTx */
> >  	if (intr_status & PAB_INTP_INTX_MASK) {
> > -		shifted_status = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT) >>
> > -			PAB_INTX_START;
> > +		shifted_status = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT);
> > +		shifted_status >>= PAB_INTX_START;
> >  		do {
> >  			for_each_set_bit(bit, &shifted_status, PCI_NUM_INTX) {
> >  				virq = irq_find_mapping(pcie->intx_domain,
> > -						bit + 1);
> > +							bit + 1);
> >  				if (virq)
> >  					generic_handle_irq(virq);
> >  				else
> > -					dev_err_ratelimited(dev,
> > -						"unexpected IRQ, INT%d\n", bit);
> > +					dev_err_ratelimited(dev, "unexpected IRQ, INT%d\n",
> > +							    bit);
> >  
> >  				/* clear interrupt */
> >  				csr_writel(pcie,
> > -					shifted_status << PAB_INTX_START,
> > -					PAB_INTP_AMBA_MISC_STAT);
> > +					   shifted_status << PAB_INTX_START,
> > +					   PAB_INTP_AMBA_MISC_STAT);
> >  			}
> >  		} while ((shifted_status >> PAB_INTX_START) != 0);
> >  	}
> > @@ -375,8 +379,7 @@ static void mobiveil_pcie_isr(struct irq_desc *desc)
> >  
> >  	/* handle MSI interrupts */
> >  	while (msi_status & 1) {
> > -		msi_data = readl_relaxed(pcie->apb_csr_base
> > -				+ MSI_DATA_OFFSET);
> > +		msi_data = readl_relaxed(pcie->apb_csr_base + MSI_DATA_OFFSET);
> >  
> >  		/*
> >  		 * MSI_STATUS_OFFSET register gets updated to zero
> > @@ -385,18 +388,18 @@ static void mobiveil_pcie_isr(struct irq_desc *desc)
> >  		 * two dummy reads.
> >  		 */
> >  		msi_addr_lo = readl_relaxed(pcie->apb_csr_base +
> > -				MSI_ADDR_L_OFFSET);
> > +					    MSI_ADDR_L_OFFSET);
> >  		msi_addr_hi = readl_relaxed(pcie->apb_csr_base +
> > -				MSI_ADDR_H_OFFSET);
> > +					    MSI_ADDR_H_OFFSET);
> >  		dev_dbg(dev, "MSI registers, data: %08x, addr: %08x:%08x\n",
> > -				msi_data, msi_addr_hi, msi_addr_lo);
> > +			msi_data, msi_addr_hi, msi_addr_lo);
> >  
> >  		virq = irq_find_mapping(msi->dev_domain, msi_data);
> >  		if (virq)
> >  			generic_handle_irq(virq);
> >  
> >  		msi_status = readl_relaxed(pcie->apb_csr_base +
> > -				MSI_STATUS_OFFSET);
> > +					   MSI_STATUS_OFFSET);
> >  	}
> >  
> >  	/* Clear the interrupt status */
> > @@ -413,7 +416,7 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie)
> >  
> >  	/* map config resource */
> >  	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> > -			"config_axi_slave");
> > +					   "config_axi_slave");
> >  	pcie->config_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);
> >  	if (IS_ERR(pcie->config_axi_slave_base))
> >  		return PTR_ERR(pcie->config_axi_slave_base);
> > @@ -421,7 +424,7 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie)
> >  
> >  	/* map csr resource */
> >  	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> > -			"csr_axi_slave");
> > +					   "csr_axi_slave");
> >  	pcie->csr_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);
> >  	if (IS_ERR(pcie->csr_axi_slave_base))
> >  		return PTR_ERR(pcie->csr_axi_slave_base);
> > @@ -452,7 +455,7 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie)
> >  }
> >  
> >  static void program_ib_windows(struct mobiveil_pcie *pcie, int win_num,
> > -		int pci_addr, u32 type, u64 size)
> > +			       int pci_addr, u32 type, u64 size)
> >  {
> >  	int pio_ctrl_val;
> >  	int amap_ctrl_dw;
> > @@ -465,19 +468,20 @@ static void program_ib_windows(struct mobiveil_pcie *pcie, int win_num,
> >  	}
> >  
> >  	pio_ctrl_val = csr_readl(pcie, PAB_PEX_PIO_CTRL);
> > -	csr_writel(pcie,
> > -		pio_ctrl_val | (1 << PIO_ENABLE_SHIFT), PAB_PEX_PIO_CTRL);
> > -	amap_ctrl_dw = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
> > -	amap_ctrl_dw = (amap_ctrl_dw | (type << AMAP_CTRL_TYPE_SHIFT));
> > -	amap_ctrl_dw = (amap_ctrl_dw | (1 << AMAP_CTRL_EN_SHIFT));
> > +	pio_ctrl_val |= 1 << PIO_ENABLE_SHIFT;
> > +	csr_writel(pcie, pio_ctrl_val, PAB_PEX_PIO_CTRL);
> >  
> > -	csr_writel(pcie, amap_ctrl_dw | lower_32_bits(size64),
> > -		   PAB_PEX_AMAP_CTRL(win_num));
> > +	amap_ctrl_dw = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
> > +	amap_ctrl_dw |= (type << AMAP_CTRL_TYPE_SHIFT) |
> > +			(1 << AMAP_CTRL_EN_SHIFT) |
> > +			lower_32_bits(size64);
> > +	csr_writel(pcie, amap_ctrl_dw, PAB_PEX_AMAP_CTRL(win_num));
> >  
> >  	csr_writel(pcie, upper_32_bits(size64),
> >  		   PAB_EXT_PEX_AMAP_SIZEN(win_num));
> >  
> >  	csr_writel(pcie, pci_addr, PAB_PEX_AMAP_AXI_WIN(win_num));
> > +
> >  	csr_writel(pcie, pci_addr, PAB_PEX_AMAP_PEX_WIN_L(win_num));
> >  	csr_writel(pcie, 0, PAB_PEX_AMAP_PEX_WIN_H(win_num));
> >  }
> > @@ -486,7 +490,8 @@ static void program_ib_windows(struct mobiveil_pcie *pcie, int win_num,
> >   * routine to program the outbound windows
> >   */
> >  static void program_ob_windows(struct mobiveil_pcie *pcie, int win_num,
> > -		u64 cpu_addr, u64 pci_addr, u32 config_io_bit, u64 size)
> > +			       u64 cpu_addr, u64 pci_addr,
> > +			       u32 config_io_bit, u64 size)
> >  {
> >  
> >  	u32 value, type;
> > @@ -505,7 +510,7 @@ static void program_ob_windows(struct mobiveil_pcie *pcie, int win_num,
> >  	type = config_io_bit;
> >  	value = csr_readl(pcie, PAB_AXI_AMAP_CTRL(win_num));
> >  	csr_writel(pcie, 1 << WIN_ENABLE_SHIFT | type << WIN_TYPE_SHIFT |
> > -			lower_32_bits(size64), PAB_AXI_AMAP_CTRL(win_num));
> > +		   lower_32_bits(size64), PAB_AXI_AMAP_CTRL(win_num));
> >  
> >  	csr_writel(pcie, upper_32_bits(size64), PAB_EXT_AXI_AMAP_SIZE(win_num));
> >  
> > @@ -515,14 +520,14 @@ static void program_ob_windows(struct mobiveil_pcie *pcie, int win_num,
> >  	 */
> >  	value = csr_readl(pcie, PAB_AXI_AMAP_AXI_WIN(win_num));
> >  	csr_writel(pcie, cpu_addr & (~AXI_WINDOW_ALIGN_MASK),
> > -			PAB_AXI_AMAP_AXI_WIN(win_num));
> > +		   PAB_AXI_AMAP_AXI_WIN(win_num));
> >  
> >  	value = csr_readl(pcie, PAB_AXI_AMAP_PEX_WIN_H(win_num));
> >  
> >  	csr_writel(pcie, lower_32_bits(pci_addr),
> > -			PAB_AXI_AMAP_PEX_WIN_L(win_num));
> > +		   PAB_AXI_AMAP_PEX_WIN_L(win_num));
> >  	csr_writel(pcie, upper_32_bits(pci_addr),
> > -			PAB_AXI_AMAP_PEX_WIN_H(win_num));
> > +		   PAB_AXI_AMAP_PEX_WIN_H(win_num));
> >  
> >  	pcie->ob_wins_configured++;
> >  }
> > @@ -538,7 +543,9 @@ static int mobiveil_bringup_link(struct mobiveil_pcie *pcie)
> >  
> >  		usleep_range(LINK_WAIT_MIN, LINK_WAIT_MAX);
> >  	}
> > +
> >  	dev_err(&pcie->pdev->dev, "link never came up\n");
> > +
> >  	return -ETIMEDOUT;
> >  }
> >  
> > @@ -551,16 +558,16 @@ static void mobiveil_pcie_enable_msi(struct mobiveil_pcie *pcie)
> >  	msi->msi_pages_phys = (phys_addr_t)msg_addr;
> >  
> >  	writel_relaxed(lower_32_bits(msg_addr),
> > -		pcie->apb_csr_base + MSI_BASE_LO_OFFSET);
> > +		       pcie->apb_csr_base + MSI_BASE_LO_OFFSET);
> >  	writel_relaxed(upper_32_bits(msg_addr),
> > -		pcie->apb_csr_base + MSI_BASE_HI_OFFSET);
> > +		       pcie->apb_csr_base + MSI_BASE_HI_OFFSET);
> >  	writel_relaxed(4096, pcie->apb_csr_base + MSI_SIZE_OFFSET);
> >  	writel_relaxed(1, pcie->apb_csr_base + MSI_ENABLE_OFFSET);
> >  }
> >  
> >  static int mobiveil_host_init(struct mobiveil_pcie *pcie)
> >  {
> > -	u32 value, pab_ctrl, type = 0;
> > +	u32 value, pab_ctrl, type;
> >  	int err;
> >  	struct resource_entry *win, *tmp;
> >  
> > @@ -575,26 +582,27 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
> >  	 * Space
> >  	 */
> >  	value = csr_readl(pcie, PCI_COMMAND);
> > -	csr_writel(pcie, value | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
> > -		PCI_COMMAND_MASTER, PCI_COMMAND);
> > +	value |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
> > +	csr_writel(pcie, value, PCI_COMMAND);
> >  
> >  	/*
> >  	 * program PIO Enable Bit to 1 (and PEX PIO Enable to 1) in PAB_CTRL
> >  	 * register
> >  	 */
> >  	pab_ctrl = csr_readl(pcie, PAB_CTRL);
> > -	csr_writel(pcie, pab_ctrl | (1 << AMBA_PIO_ENABLE_SHIFT) |
> > -		(1 << PEX_PIO_ENABLE_SHIFT), PAB_CTRL);
> > +	pab_ctrl |= (1 << AMBA_PIO_ENABLE_SHIFT) | (1 << PEX_PIO_ENABLE_SHIFT);
> > +	csr_writel(pcie, pab_ctrl, PAB_CTRL);
> >  
> >  	csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK),
> > -		PAB_INTP_AMBA_MISC_ENB);
> > +		   PAB_INTP_AMBA_MISC_ENB);
> >  
> >  	/*
> >  	 * program PIO Enable Bit to 1 and Config Window Enable Bit to 1 in
> >  	 * PAB_AXI_PIO_CTRL Register
> >  	 */
> >  	value = csr_readl(pcie, PAB_AXI_PIO_CTRL);
> > -	csr_writel(pcie, value | APIO_EN_MASK, PAB_AXI_PIO_CTRL);
> > +	value |= APIO_EN_MASK;
> > +	csr_writel(pcie, value, PAB_AXI_PIO_CTRL);
> >  
> >  	/*
> >  	 * we'll program one outbound window for config reads and
> > @@ -605,25 +613,25 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
> >  
> >  	/* config outbound translation window */
> >  	program_ob_windows(pcie, pcie->ob_wins_configured,
> > -			pcie->ob_io_res->start, 0, CFG_WINDOW_TYPE,
> > -			resource_size(pcie->ob_io_res));
> > +			   pcie->ob_io_res->start, 0, CFG_WINDOW_TYPE,
> > +			   resource_size(pcie->ob_io_res));
> >  
> >  	/* memory inbound translation window */
> >  	program_ib_windows(pcie, WIN_NUM_1, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE);
> >  
> >  	/* Get the I/O and memory ranges from DT */
> >  	resource_list_for_each_entry_safe(win, tmp, &pcie->resources) {
> > -		type = 0;
> >  		if (resource_type(win->res) == IORESOURCE_MEM)
> >  			type = MEM_WINDOW_TYPE;
> > -		if (resource_type(win->res) == IORESOURCE_IO)
> > +		else if (resource_type(win->res) == IORESOURCE_IO)
> >  			type = IO_WINDOW_TYPE;
> > -		if (type) {
> > -			/* configure outbound translation window */
> > -			program_ob_windows(pcie, pcie->ob_wins_configured,
> > -				win->res->start, 0, type,
> > -				resource_size(win->res));
> > -		}
> > +		else
> > +			continue;
> > +
> > +		/* configure outbound translation window */
> > +		program_ob_windows(pcie, pcie->ob_wins_configured,
> > +				   win->res->start, 0, type,
> > +				   resource_size(win->res));
> >  	}
> >  
> >  	/* setup MSI hardware registers */
> > @@ -643,7 +651,8 @@ static void mobiveil_mask_intx_irq(struct irq_data *data)
> >  	mask = 1 << ((data->hwirq + PAB_INTX_START) - 1);
> >  	raw_spin_lock_irqsave(&pcie->intx_mask_lock, flags);
> >  	shifted_val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
> > -	csr_writel(pcie, (shifted_val & (~mask)), PAB_INTP_AMBA_MISC_ENB);
> > +	shifted_val &= ~mask;
> > +	csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
> >  	raw_spin_unlock_irqrestore(&pcie->intx_mask_lock, flags);
> >  }
> >  
> > @@ -658,7 +667,8 @@ static void mobiveil_unmask_intx_irq(struct irq_data *data)
> >  	mask = 1 << ((data->hwirq + PAB_INTX_START) - 1);
> >  	raw_spin_lock_irqsave(&pcie->intx_mask_lock, flags);
> >  	shifted_val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
> > -	csr_writel(pcie, (shifted_val | mask), PAB_INTP_AMBA_MISC_ENB);
> > +	shifted_val |= mask;
> > +	csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
> >  	raw_spin_unlock_irqrestore(&pcie->intx_mask_lock, flags);
> >  }
> >  
> > @@ -672,10 +682,11 @@ static struct irq_chip intx_irq_chip = {
> >  
> >  /* routine to setup the INTx related data */
> >  static int mobiveil_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
> > -		irq_hw_number_t hwirq)
> > +				  irq_hw_number_t hwirq)
> >  {
> >  	irq_set_chip_and_handler(irq, &intx_irq_chip, handle_level_irq);
> >  	irq_set_chip_data(irq, domain->host_data);
> > +
> >  	return 0;
> >  }
> >  
> > @@ -692,7 +703,7 @@ static struct irq_chip mobiveil_msi_irq_chip = {
> >  
> >  static struct msi_domain_info mobiveil_msi_domain_info = {
> >  	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
> > -		MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX),
> > +		   MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX),
> >  	.chip	= &mobiveil_msi_irq_chip,
> >  };
> >  
> > @@ -710,7 +721,7 @@ static void mobiveil_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
> >  }
> >  
> >  static int mobiveil_msi_set_affinity(struct irq_data *irq_data,
> > -		const struct cpumask *mask, bool force)
> > +				     const struct cpumask *mask, bool force)
> >  {
> >  	return -EINVAL;
> >  }
> > @@ -722,7 +733,8 @@ static struct irq_chip mobiveil_msi_bottom_irq_chip = {
> >  };
> >  
> >  static int mobiveil_irq_msi_domain_alloc(struct irq_domain *domain,
> > -		unsigned int virq, unsigned int nr_irqs, void *args)
> > +					 unsigned int virq,
> > +					 unsigned int nr_irqs, void *args)
> >  {
> >  	struct mobiveil_pcie *pcie = domain->host_data;
> >  	struct mobiveil_msi *msi = &pcie->msi;
> > @@ -742,13 +754,13 @@ static int mobiveil_irq_msi_domain_alloc(struct irq_domain *domain,
> >  	mutex_unlock(&msi->lock);
> >  
> >  	irq_domain_set_info(domain, virq, bit, &mobiveil_msi_bottom_irq_chip,
> > -				domain->host_data, handle_level_irq,
> > -				NULL, NULL);
> > +			    domain->host_data, handle_level_irq, NULL, NULL);
> >  	return 0;
> >  }
> >  
> >  static void mobiveil_irq_msi_domain_free(struct irq_domain *domain,
> > -		unsigned int virq, unsigned int nr_irqs)
> > +					 unsigned int virq,
> > +					 unsigned int nr_irqs)
> >  {
> >  	struct irq_data *d = irq_domain_get_irq_data(domain, virq);
> >  	struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(d);
> > @@ -756,12 +768,11 @@ static void mobiveil_irq_msi_domain_free(struct irq_domain *domain,
> >  
> >  	mutex_lock(&msi->lock);
> >  
> > -	if (!test_bit(d->hwirq, msi->msi_irq_in_use)) {
> > +	if (!test_bit(d->hwirq, msi->msi_irq_in_use))
> >  		dev_err(&pcie->pdev->dev, "trying to free unused MSI#%lu\n",
> >  			d->hwirq);
> > -	} else {
> > +	else
> >  		__clear_bit(d->hwirq, msi->msi_irq_in_use);
> > -	}
> >  
> >  	mutex_unlock(&msi->lock);
> >  }
> > @@ -785,12 +796,14 @@ static int mobiveil_allocate_msi_domains(struct mobiveil_pcie *pcie)
> >  	}
> >  
> >  	msi->msi_domain = pci_msi_create_irq_domain(fwnode,
> > -				&mobiveil_msi_domain_info, msi->dev_domain);
> > +						    &mobiveil_msi_domain_info,
> > +						    msi->dev_domain);
> >  	if (!msi->msi_domain) {
> >  		dev_err(dev, "failed to create MSI domain\n");
> >  		irq_domain_remove(msi->dev_domain);
> >  		return -ENOMEM;
> >  	}
> > +
> >  	return 0;
> >  }
> >  
> > @@ -801,8 +814,8 @@ static int mobiveil_pcie_init_irq_domain(struct mobiveil_pcie *pcie)
> >  	int ret;
> >  
> >  	/* setup INTx */
> > -	pcie->intx_domain = irq_domain_add_linear(node,
> > -				PCI_NUM_INTX, &intx_domain_ops, pcie);
> > +	pcie->intx_domain = irq_domain_add_linear(node, PCI_NUM_INTX,
> > +						  &intx_domain_ops, pcie);
> >  
> >  	if (!pcie->intx_domain) {
> >  		dev_err(dev, "Failed to get a INTx IRQ domain\n");
> > @@ -917,10 +930,10 @@ MODULE_DEVICE_TABLE(of, mobiveil_pcie_of_match);
> >  static struct platform_driver mobiveil_pcie_driver = {
> >  	.probe = mobiveil_pcie_probe,
> >  	.driver = {
> > -			.name = "mobiveil-pcie",
> > -			.of_match_table = mobiveil_pcie_of_match,
> > -			.suppress_bind_attrs = true,
> > -		},
> > +		.name = "mobiveil-pcie",
> > +		.of_match_table = mobiveil_pcie_of_match,
> > +		.suppress_bind_attrs = true,
> > +	},
> >  };
> >  
> >  builtin_platform_driver(mobiveil_pcie_driver);
> > -- 
> > 2.17.1
> > 

^ permalink raw reply	[flat|nested] 67+ messages in thread

* RE: [PATCHv5 00/20] PCI: mobiveil: fixes for Mobiveil PCIe Host Bridge IP driver
  2019-07-03 10:33 ` [PATCHv5 00/20] PCI: mobiveil: fixes for Mobiveil PCIe Host Bridge IP driver Lorenzo Pieralisi
@ 2019-07-04  2:36   ` Z.q. Hou
  0 siblings, 0 replies; 67+ messages in thread
From: Z.q. Hou @ 2019-07-04  2:36 UTC (permalink / raw)
  To: Lorenzo Pieralisi
  Cc: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	catalin.marinas, will.deacon, Mingkai Hu, M.h. Lian, Xiaowei Bao

Hi Lorenzo,

Thanks a lot for your comments!

> -----Original Message-----
> From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Sent: 2019年7月3日 18:33
> To: Z.q. Hou <zhiqiang.hou@nxp.com>
> Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> bhelgaas@google.com; robh+dt@kernel.org; mark.rutland@arm.com;
> l.subrahmanya@mobiveil.co.in; shawnguo@kernel.org; Leo Li
> <leoyang.li@nxp.com>; catalin.marinas@arm.com; will.deacon@arm.com;
> Mingkai Hu <mingkai.hu@nxp.com>; M.h. Lian <minghuan.lian@nxp.com>;
> Xiaowei Bao <xiaowei.bao@nxp.com>
> Subject: Re: [PATCHv5 00/20] PCI: mobiveil: fixes for Mobiveil PCIe Host
> Bridge IP driver
> 
> On Fri, Apr 12, 2019 at 08:35:11AM +0000, Z.q. Hou wrote:
> > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> >
> > This patch set is to add fixes for Mobiveil PCIe Host driver.
> > And these patches are splited from the thread below:
> >
> https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fpatch
> >
> work.ozlabs.org%2Fproject%2Flinux-pci%2Flist%2F%3Fseries%3D96417&am
> p;d
> >
> ata=02%7C01%7Czhiqiang.hou%40nxp.com%7C0d32165274bf4c678b4808d
> 6ffa1e42
> >
> f%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63697746817272
> 2471&amp;
> >
> sdata=RLgfyNRBIRePuLFTCQe4RQYleeXDevwtVN4I6ZFkS1s%3D&amp;reserv
> ed=0
> >
> > Hou Zhiqiang (20):
> >   PCI: mobiveil: Unify register accessors
> >   PCI: mobiveil: Format the code without functionality change
> >   PCI: mobiveil: Correct the returned error number
> >   PCI: mobiveil: Remove the flag MSI_FLAG_MULTI_PCI_MSI
> >   PCI: mobiveil: Correct PCI base address in MEM/IO outbound windows
> >   PCI: mobiveil: Replace the resource list iteration function
> >   PCI: mobiveil: Use WIN_NUM_0 explicitly for CFG outbound window
> >   PCI: mobiveil: Use the 1st inbound window for MEM inbound
> transactions
> >   PCI: mobiveil: Correct inbound/outbound window setup routines
> >   PCI: mobiveil: Fix the INTx process errors
> >   PCI: mobiveil: Correct the fixup of Class Code field
> >   PCI: mobiveil: Move the link up waiting out of mobiveil_host_init()
> >   PCI: mobiveil: Move IRQ chained handler setup out of DT parse
> >   PCI: mobiveil: Initialize Primary/Secondary/Subordinate bus numbers
> >   PCI: mobiveil: Fix the checking of valid device
> >   PCI: mobiveil: Add link up condition check
> >   PCI: mobiveil: Complete initialization of host even if no PCIe link
> >   PCI: mobiveil: Disable IB and OB windows set by bootloader
> >   PCI: mobiveil: Add 8-bit and 16-bit register accessors
> >   dt-bindings: PCI: mobiveil: Change gpio_slave and apb_csr to
> > optional
> >
> >  .../devicetree/bindings/pci/mobiveil-pcie.txt |   2 +
> >  drivers/pci/controller/pcie-mobiveil.c        | 578 +++++++++++-------
> >  2 files changed, 368 insertions(+), 212 deletions(-)
> 
> I am putting together a branch with the patches I would like to queue, for
> the ones I requested to split please wait for me, I will publish the branch and
> will ask you to rebase on top of it.
>

Ok, will split them and rebase on the new branch.

Thanks,
Zhiqiang
 
> Lorenzo

^ permalink raw reply	[flat|nested] 67+ messages in thread

* RE: [PATCHv5 03/20] PCI: mobiveil: Correct the returned error number
  2019-07-03 14:17   ` Lorenzo Pieralisi
@ 2019-07-04  2:38     ` Z.q. Hou
  0 siblings, 0 replies; 67+ messages in thread
From: Z.q. Hou @ 2019-07-04  2:38 UTC (permalink / raw)
  To: Lorenzo Pieralisi
  Cc: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	catalin.marinas, will.deacon, Mingkai Hu, M.h. Lian, Xiaowei Bao

Hi Lorenzo,

Thanks for your comments!

> -----Original Message-----
> From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Sent: 2019年7月3日 22:17
> To: Z.q. Hou <zhiqiang.hou@nxp.com>
> Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> bhelgaas@google.com; robh+dt@kernel.org; mark.rutland@arm.com;
> l.subrahmanya@mobiveil.co.in; shawnguo@kernel.org; Leo Li
> <leoyang.li@nxp.com>; catalin.marinas@arm.com; will.deacon@arm.com;
> Mingkai Hu <mingkai.hu@nxp.com>; M.h. Lian <minghuan.lian@nxp.com>;
> Xiaowei Bao <xiaowei.bao@nxp.com>
> Subject: Re: [PATCHv5 03/20] PCI: mobiveil: Correct the returned error
> number
> 
> On Fri, Apr 12, 2019 at 08:35:30AM +0000, Z.q. Hou wrote:
> > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> >
> > This patch corrects the returned error number by convention, and
> > removes an unnecessary error check.
> 
> Two distinct changes, two patches, please split and repost.

Yes, will split and rebase on the new branch.

Thanks,
Zhiqiang

> 
> Lorenzo
> 
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> > Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
> > ---
> > V5:
> >  - Corrected and retouched the subject and changelog.
> >
> >  drivers/pci/controller/pcie-mobiveil.c | 8 +++-----
> >  1 file changed, 3 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/pci/controller/pcie-mobiveil.c
> > b/drivers/pci/controller/pcie-mobiveil.c
> > index b87471f08a40..563210e731d3 100644
> > --- a/drivers/pci/controller/pcie-mobiveil.c
> > +++ b/drivers/pci/controller/pcie-mobiveil.c
> > @@ -819,7 +819,7 @@ static int mobiveil_pcie_init_irq_domain(struct
> > mobiveil_pcie *pcie)
> >
> >  	if (!pcie->intx_domain) {
> >  		dev_err(dev, "Failed to get a INTx IRQ domain\n");
> > -		return -ENODEV;
> > +		return -ENOMEM;
> >  	}
> >
> >  	raw_spin_lock_init(&pcie->intx_mask_lock);
> > @@ -845,11 +845,9 @@ static int mobiveil_pcie_probe(struct
> platform_device *pdev)
> >  	/* allocate the PCIe port */
> >  	bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
> >  	if (!bridge)
> > -		return -ENODEV;
> > +		return -ENOMEM;
> >
> >  	pcie = pci_host_bridge_priv(bridge);
> > -	if (!pcie)
> > -		return -ENOMEM;
> >
> >  	pcie->pdev = pdev;
> >
> > @@ -866,7 +864,7 @@ static int mobiveil_pcie_probe(struct
> platform_device *pdev)
> >  						    &pcie->resources, &iobase);
> >  	if (ret) {
> >  		dev_err(dev, "Getting bridge resources failed\n");
> > -		return -ENOMEM;
> > +		return ret;
> >  	}
> >
> >  	/*
> > --
> > 2.17.1
> >

^ permalink raw reply	[flat|nested] 67+ messages in thread

* RE: [PATCHv5 02/20] PCI: mobiveil: Format the code without functionality change
  2019-07-03 15:10   ` Lorenzo Pieralisi
@ 2019-07-04  2:41     ` Z.q. Hou
  0 siblings, 0 replies; 67+ messages in thread
From: Z.q. Hou @ 2019-07-04  2:41 UTC (permalink / raw)
  To: Lorenzo Pieralisi
  Cc: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	catalin.marinas, will.deacon, Mingkai Hu, M.h. Lian, Xiaowei Bao

Hi Lorenzo,

Thanks for your comments!

> -----Original Message-----
> From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Sent: 2019年7月3日 23:10
> To: Z.q. Hou <zhiqiang.hou@nxp.com>
> Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> bhelgaas@google.com; robh+dt@kernel.org; mark.rutland@arm.com;
> l.subrahmanya@mobiveil.co.in; shawnguo@kernel.org; Leo Li
> <leoyang.li@nxp.com>; catalin.marinas@arm.com; will.deacon@arm.com;
> Mingkai Hu <mingkai.hu@nxp.com>; M.h. Lian <minghuan.lian@nxp.com>;
> Xiaowei Bao <xiaowei.bao@nxp.com>
> Subject: Re: [PATCHv5 02/20] PCI: mobiveil: Format the code without
> functionality change
> 
> On Fri, Apr 12, 2019 at 08:35:24AM +0000, Z.q. Hou wrote:
> > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> >
> > Just format the code without functionality change.
> >
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> > ---
> > V5:
> >  - Retouched the subject.
> >
> >  drivers/pci/controller/pcie-mobiveil.c | 261
> > +++++++++++++------------
> >  1 file changed, 137 insertions(+), 124 deletions(-)
> 
> Again, I will drop this patch. You tend to do multiple changes in one single
> patch, I understand this patch is just reformatting/renaming variables but at
> least I would separate indentation changes from changes where eg you add
> local variables.
> 
> At least try to group the changes you are making instead of mixing them all
> up.

Yes, will spilt it.

B.R,
Zhiqiang

> 
> Thanks,
> Lorenzo
> 
> > diff --git a/drivers/pci/controller/pcie-mobiveil.c
> > b/drivers/pci/controller/pcie-mobiveil.c
> > index d55c7e780c6e..b87471f08a40 100644
> > --- a/drivers/pci/controller/pcie-mobiveil.c
> > +++ b/drivers/pci/controller/pcie-mobiveil.c
> > @@ -31,38 +31,40 @@
> >   * translation tables are grouped into windows, each window registers
> are
> >   * grouped into blocks of 4 or 16 registers each
> >   */
> > -#define PAB_REG_BLOCK_SIZE	16
> > -#define PAB_EXT_REG_BLOCK_SIZE	4
> > +#define PAB_REG_BLOCK_SIZE		16
> > +#define PAB_EXT_REG_BLOCK_SIZE		4
> >
> > -#define PAB_REG_ADDR(offset, win) (offset + (win *
> > PAB_REG_BLOCK_SIZE)) -#define PAB_EXT_REG_ADDR(offset, win) (offset
> +
> > (win * PAB_EXT_REG_BLOCK_SIZE))
> > +#define PAB_REG_ADDR(offset, win)	\
> > +	(offset + (win * PAB_REG_BLOCK_SIZE))
> > +#define PAB_EXT_REG_ADDR(offset, win)	\
> > +	(offset + (win * PAB_EXT_REG_BLOCK_SIZE))
> >
> > -#define LTSSM_STATUS		0x0404
> > -#define  LTSSM_STATUS_L0_MASK	0x3f
> > -#define  LTSSM_STATUS_L0	0x2d
> > +#define LTSSM_STATUS			0x0404
> > +#define  LTSSM_STATUS_L0_MASK		0x3f
> > +#define  LTSSM_STATUS_L0		0x2d
> >
> > -#define PAB_CTRL		0x0808
> > -#define  AMBA_PIO_ENABLE_SHIFT	0
> > -#define  PEX_PIO_ENABLE_SHIFT	1
> > -#define  PAGE_SEL_SHIFT	13
> > -#define  PAGE_SEL_MASK		0x3f
> > -#define  PAGE_LO_MASK		0x3ff
> > -#define  PAGE_SEL_OFFSET_SHIFT	10
> > +#define PAB_CTRL			0x0808
> > +#define  AMBA_PIO_ENABLE_SHIFT		0
> > +#define  PEX_PIO_ENABLE_SHIFT		1
> > +#define  PAGE_SEL_SHIFT			13
> > +#define  PAGE_SEL_MASK			0x3f
> > +#define  PAGE_LO_MASK			0x3ff
> > +#define  PAGE_SEL_OFFSET_SHIFT		10
> >
> > -#define PAB_AXI_PIO_CTRL	0x0840
> > -#define  APIO_EN_MASK		0xf
> > +#define PAB_AXI_PIO_CTRL		0x0840
> > +#define  APIO_EN_MASK			0xf
> >
> > -#define PAB_PEX_PIO_CTRL	0x08c0
> > -#define  PIO_ENABLE_SHIFT	0
> > +#define PAB_PEX_PIO_CTRL		0x08c0
> > +#define  PIO_ENABLE_SHIFT		0
> >
> >  #define PAB_INTP_AMBA_MISC_ENB		0x0b0c
> > -#define PAB_INTP_AMBA_MISC_STAT	0x0b1c
> > +#define PAB_INTP_AMBA_MISC_STAT		0x0b1c
> >  #define  PAB_INTP_INTX_MASK		0x01e0
> >  #define  PAB_INTP_MSI_MASK		0x8
> >
> > -#define PAB_AXI_AMAP_CTRL(win)	PAB_REG_ADDR(0x0ba0, win)
> > -#define  WIN_ENABLE_SHIFT	0
> > -#define  WIN_TYPE_SHIFT	1
> > +#define PAB_AXI_AMAP_CTRL(win)		PAB_REG_ADDR(0x0ba0, win)
> > +#define  WIN_ENABLE_SHIFT		0
> > +#define  WIN_TYPE_SHIFT			1
> >
> >  #define PAB_EXT_AXI_AMAP_SIZE(win)	PAB_EXT_REG_ADDR(0xbaf0,
> win)
> >
> > @@ -70,16 +72,16 @@
> >  #define  AXI_WINDOW_ALIGN_MASK		3
> >
> >  #define PAB_AXI_AMAP_PEX_WIN_L(win)	PAB_REG_ADDR(0x0ba8,
> win)
> > -#define  PAB_BUS_SHIFT		24
> > -#define  PAB_DEVICE_SHIFT	19
> > -#define  PAB_FUNCTION_SHIFT	16
> > +#define  PAB_BUS_SHIFT			24
> > +#define  PAB_DEVICE_SHIFT		19
> > +#define  PAB_FUNCTION_SHIFT		16
> >
> >  #define PAB_AXI_AMAP_PEX_WIN_H(win)	PAB_REG_ADDR(0x0bac,
> win)
> >  #define PAB_INTP_AXI_PIO_CLASS		0x474
> >
> > -#define PAB_PEX_AMAP_CTRL(win)	PAB_REG_ADDR(0x4ba0, win)
> > -#define  AMAP_CTRL_EN_SHIFT	0
> > -#define  AMAP_CTRL_TYPE_SHIFT	1
> > +#define PAB_PEX_AMAP_CTRL(win)		PAB_REG_ADDR(0x4ba0,
> win)
> > +#define  AMAP_CTRL_EN_SHIFT		0
> > +#define  AMAP_CTRL_TYPE_SHIFT		1
> >
> >  #define PAB_EXT_PEX_AMAP_SIZEN(win)	PAB_EXT_REG_ADDR(0xbef0,
> win)
> >  #define PAB_PEX_AMAP_AXI_WIN(win)	PAB_REG_ADDR(0x4ba4,
> win)
> > @@ -87,39 +89,39 @@
> >  #define PAB_PEX_AMAP_PEX_WIN_H(win)	PAB_REG_ADDR(0x4bac,
> win)
> >
> >  /* starting offset of INTX bits in status register */
> > -#define PAB_INTX_START	5
> > +#define PAB_INTX_START			5
> >
> >  /* supported number of MSI interrupts */
> > -#define PCI_NUM_MSI	16
> > +#define PCI_NUM_MSI			16
> >
> >  /* MSI registers */
> > -#define MSI_BASE_LO_OFFSET	0x04
> > -#define MSI_BASE_HI_OFFSET	0x08
> > -#define MSI_SIZE_OFFSET	0x0c
> > -#define MSI_ENABLE_OFFSET	0x14
> > -#define MSI_STATUS_OFFSET	0x18
> > -#define MSI_DATA_OFFSET	0x20
> > -#define MSI_ADDR_L_OFFSET	0x24
> > -#define MSI_ADDR_H_OFFSET	0x28
> > +#define MSI_BASE_LO_OFFSET		0x04
> > +#define MSI_BASE_HI_OFFSET		0x08
> > +#define MSI_SIZE_OFFSET			0x0c
> > +#define MSI_ENABLE_OFFSET		0x14
> > +#define MSI_STATUS_OFFSET		0x18
> > +#define MSI_DATA_OFFSET			0x20
> > +#define MSI_ADDR_L_OFFSET		0x24
> > +#define MSI_ADDR_H_OFFSET		0x28
> >
> >  /* outbound and inbound window definitions */
> > -#define WIN_NUM_0		0
> > -#define WIN_NUM_1		1
> > -#define CFG_WINDOW_TYPE	0
> > -#define IO_WINDOW_TYPE		1
> > -#define MEM_WINDOW_TYPE	2
> > -#define IB_WIN_SIZE		((u64)256 * 1024 * 1024 * 1024)
> > -#define MAX_PIO_WINDOWS	8
> > +#define WIN_NUM_0			0
> > +#define WIN_NUM_1			1
> > +#define CFG_WINDOW_TYPE			0
> > +#define IO_WINDOW_TYPE			1
> > +#define MEM_WINDOW_TYPE			2
> > +#define IB_WIN_SIZE			((u64)256 * 1024 * 1024 * 1024)
> > +#define MAX_PIO_WINDOWS			8
> >
> >  /* Parameters for the waiting for link up routine */
> > -#define LINK_WAIT_MAX_RETRIES	10
> > -#define LINK_WAIT_MIN	90000
> > -#define LINK_WAIT_MAX	100000
> > +#define LINK_WAIT_MAX_RETRIES		10
> > +#define LINK_WAIT_MIN			90000
> > +#define LINK_WAIT_MAX			100000
> >
> > -#define PAGED_ADDR_BNDRY			0xc00
> > -#define OFFSET_TO_PAGE_ADDR(off)		\
> > +#define PAGED_ADDR_BNDRY		0xc00
> > +#define OFFSET_TO_PAGE_ADDR(off)	\
> >  	((off & PAGE_LO_MASK) | PAGED_ADDR_BNDRY)
> > -#define OFFSET_TO_PAGE_IDX(off)			\
> > +#define OFFSET_TO_PAGE_IDX(off)		\
> >  	((off >> PAGE_SEL_OFFSET_SHIFT) & PAGE_SEL_MASK)
> >
> >  struct mobiveil_msi {			/* MSI information */
> > @@ -297,14 +299,14 @@ static void __iomem
> *mobiveil_pcie_map_bus(struct pci_bus *bus,
> >  					unsigned int devfn, int where)
> >  {
> >  	struct mobiveil_pcie *pcie = bus->sysdata;
> > +	u32 value;
> >
> >  	if (!mobiveil_pcie_valid_device(bus, devfn))
> >  		return NULL;
> >
> > -	if (bus->number == pcie->root_bus_nr) {
> > -		/* RC config access */
> > +	/* RC config access */
> > +	if (bus->number == pcie->root_bus_nr)
> >  		return pcie->csr_axi_slave_base + where;
> > -	}
> >
> >  	/*
> >  	 * EP config access (in Config/APIO space) @@ -312,10 +314,12 @@
> > static void __iomem *mobiveil_pcie_map_bus(struct pci_bus *bus,
> >  	 * (BDF) in PAB_AXI_AMAP_PEX_WIN_L0 Register.
> >  	 * Relies on pci_lock serialization
> >  	 */
> > -	csr_writel(pcie, bus->number << PAB_BUS_SHIFT |
> > -			PCI_SLOT(devfn) << PAB_DEVICE_SHIFT |
> > -			PCI_FUNC(devfn) << PAB_FUNCTION_SHIFT,
> > -			PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0));
> > +	value = bus->number << PAB_BUS_SHIFT |
> > +		PCI_SLOT(devfn) << PAB_DEVICE_SHIFT |
> > +		PCI_FUNC(devfn) << PAB_FUNCTION_SHIFT;
> > +
> > +	csr_writel(pcie, value, PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0));
> > +
> >  	return pcie->config_axi_slave_base + where;  }
> >
> > @@ -350,22 +354,22 @@ static void mobiveil_pcie_isr(struct irq_desc
> > *desc)
> >
> >  	/* Handle INTx */
> >  	if (intr_status & PAB_INTP_INTX_MASK) {
> > -		shifted_status = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT) >>
> > -			PAB_INTX_START;
> > +		shifted_status = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT);
> > +		shifted_status >>= PAB_INTX_START;
> >  		do {
> >  			for_each_set_bit(bit, &shifted_status, PCI_NUM_INTX) {
> >  				virq = irq_find_mapping(pcie->intx_domain,
> > -						bit + 1);
> > +							bit + 1);
> >  				if (virq)
> >  					generic_handle_irq(virq);
> >  				else
> > -					dev_err_ratelimited(dev,
> > -						"unexpected IRQ, INT%d\n", bit);
> > +					dev_err_ratelimited(dev, "unexpected IRQ,
> INT%d\n",
> > +							    bit);
> >
> >  				/* clear interrupt */
> >  				csr_writel(pcie,
> > -					shifted_status << PAB_INTX_START,
> > -					PAB_INTP_AMBA_MISC_STAT);
> > +					   shifted_status << PAB_INTX_START,
> > +					   PAB_INTP_AMBA_MISC_STAT);
> >  			}
> >  		} while ((shifted_status >> PAB_INTX_START) != 0);
> >  	}
> > @@ -375,8 +379,7 @@ static void mobiveil_pcie_isr(struct irq_desc
> > *desc)
> >
> >  	/* handle MSI interrupts */
> >  	while (msi_status & 1) {
> > -		msi_data = readl_relaxed(pcie->apb_csr_base
> > -				+ MSI_DATA_OFFSET);
> > +		msi_data = readl_relaxed(pcie->apb_csr_base +
> MSI_DATA_OFFSET);
> >
> >  		/*
> >  		 * MSI_STATUS_OFFSET register gets updated to zero @@ -385,18
> > +388,18 @@ static void mobiveil_pcie_isr(struct irq_desc *desc)
> >  		 * two dummy reads.
> >  		 */
> >  		msi_addr_lo = readl_relaxed(pcie->apb_csr_base +
> > -				MSI_ADDR_L_OFFSET);
> > +					    MSI_ADDR_L_OFFSET);
> >  		msi_addr_hi = readl_relaxed(pcie->apb_csr_base +
> > -				MSI_ADDR_H_OFFSET);
> > +					    MSI_ADDR_H_OFFSET);
> >  		dev_dbg(dev, "MSI registers, data: %08x, addr: %08x:%08x\n",
> > -				msi_data, msi_addr_hi, msi_addr_lo);
> > +			msi_data, msi_addr_hi, msi_addr_lo);
> >
> >  		virq = irq_find_mapping(msi->dev_domain, msi_data);
> >  		if (virq)
> >  			generic_handle_irq(virq);
> >
> >  		msi_status = readl_relaxed(pcie->apb_csr_base +
> > -				MSI_STATUS_OFFSET);
> > +					   MSI_STATUS_OFFSET);
> >  	}
> >
> >  	/* Clear the interrupt status */
> > @@ -413,7 +416,7 @@ static int mobiveil_pcie_parse_dt(struct
> > mobiveil_pcie *pcie)
> >
> >  	/* map config resource */
> >  	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> > -			"config_axi_slave");
> > +					   "config_axi_slave");
> >  	pcie->config_axi_slave_base = devm_pci_remap_cfg_resource(dev,
> res);
> >  	if (IS_ERR(pcie->config_axi_slave_base))
> >  		return PTR_ERR(pcie->config_axi_slave_base);
> > @@ -421,7 +424,7 @@ static int mobiveil_pcie_parse_dt(struct
> > mobiveil_pcie *pcie)
> >
> >  	/* map csr resource */
> >  	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> > -			"csr_axi_slave");
> > +					   "csr_axi_slave");
> >  	pcie->csr_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);
> >  	if (IS_ERR(pcie->csr_axi_slave_base))
> >  		return PTR_ERR(pcie->csr_axi_slave_base);
> > @@ -452,7 +455,7 @@ static int mobiveil_pcie_parse_dt(struct
> > mobiveil_pcie *pcie)  }
> >
> >  static void program_ib_windows(struct mobiveil_pcie *pcie, int
> win_num,
> > -		int pci_addr, u32 type, u64 size)
> > +			       int pci_addr, u32 type, u64 size)
> >  {
> >  	int pio_ctrl_val;
> >  	int amap_ctrl_dw;
> > @@ -465,19 +468,20 @@ static void program_ib_windows(struct
> mobiveil_pcie *pcie, int win_num,
> >  	}
> >
> >  	pio_ctrl_val = csr_readl(pcie, PAB_PEX_PIO_CTRL);
> > -	csr_writel(pcie,
> > -		pio_ctrl_val | (1 << PIO_ENABLE_SHIFT), PAB_PEX_PIO_CTRL);
> > -	amap_ctrl_dw = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
> > -	amap_ctrl_dw = (amap_ctrl_dw | (type << AMAP_CTRL_TYPE_SHIFT));
> > -	amap_ctrl_dw = (amap_ctrl_dw | (1 << AMAP_CTRL_EN_SHIFT));
> > +	pio_ctrl_val |= 1 << PIO_ENABLE_SHIFT;
> > +	csr_writel(pcie, pio_ctrl_val, PAB_PEX_PIO_CTRL);
> >
> > -	csr_writel(pcie, amap_ctrl_dw | lower_32_bits(size64),
> > -		   PAB_PEX_AMAP_CTRL(win_num));
> > +	amap_ctrl_dw = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
> > +	amap_ctrl_dw |= (type << AMAP_CTRL_TYPE_SHIFT) |
> > +			(1 << AMAP_CTRL_EN_SHIFT) |
> > +			lower_32_bits(size64);
> > +	csr_writel(pcie, amap_ctrl_dw, PAB_PEX_AMAP_CTRL(win_num));
> >
> >  	csr_writel(pcie, upper_32_bits(size64),
> >  		   PAB_EXT_PEX_AMAP_SIZEN(win_num));
> >
> >  	csr_writel(pcie, pci_addr, PAB_PEX_AMAP_AXI_WIN(win_num));
> > +
> >  	csr_writel(pcie, pci_addr, PAB_PEX_AMAP_PEX_WIN_L(win_num));
> >  	csr_writel(pcie, 0, PAB_PEX_AMAP_PEX_WIN_H(win_num));  } @@
> -486,7
> > +490,8 @@ static void program_ib_windows(struct mobiveil_pcie *pcie,
> int win_num,
> >   * routine to program the outbound windows
> >   */
> >  static void program_ob_windows(struct mobiveil_pcie *pcie, int
> win_num,
> > -		u64 cpu_addr, u64 pci_addr, u32 config_io_bit, u64 size)
> > +			       u64 cpu_addr, u64 pci_addr,
> > +			       u32 config_io_bit, u64 size)
> >  {
> >
> >  	u32 value, type;
> > @@ -505,7 +510,7 @@ static void program_ob_windows(struct
> mobiveil_pcie *pcie, int win_num,
> >  	type = config_io_bit;
> >  	value = csr_readl(pcie, PAB_AXI_AMAP_CTRL(win_num));
> >  	csr_writel(pcie, 1 << WIN_ENABLE_SHIFT | type << WIN_TYPE_SHIFT |
> > -			lower_32_bits(size64), PAB_AXI_AMAP_CTRL(win_num));
> > +		   lower_32_bits(size64), PAB_AXI_AMAP_CTRL(win_num));
> >
> >  	csr_writel(pcie, upper_32_bits(size64),
> > PAB_EXT_AXI_AMAP_SIZE(win_num));
> >
> > @@ -515,14 +520,14 @@ static void program_ob_windows(struct
> mobiveil_pcie *pcie, int win_num,
> >  	 */
> >  	value = csr_readl(pcie, PAB_AXI_AMAP_AXI_WIN(win_num));
> >  	csr_writel(pcie, cpu_addr & (~AXI_WINDOW_ALIGN_MASK),
> > -			PAB_AXI_AMAP_AXI_WIN(win_num));
> > +		   PAB_AXI_AMAP_AXI_WIN(win_num));
> >
> >  	value = csr_readl(pcie, PAB_AXI_AMAP_PEX_WIN_H(win_num));
> >
> >  	csr_writel(pcie, lower_32_bits(pci_addr),
> > -			PAB_AXI_AMAP_PEX_WIN_L(win_num));
> > +		   PAB_AXI_AMAP_PEX_WIN_L(win_num));
> >  	csr_writel(pcie, upper_32_bits(pci_addr),
> > -			PAB_AXI_AMAP_PEX_WIN_H(win_num));
> > +		   PAB_AXI_AMAP_PEX_WIN_H(win_num));
> >
> >  	pcie->ob_wins_configured++;
> >  }
> > @@ -538,7 +543,9 @@ static int mobiveil_bringup_link(struct
> > mobiveil_pcie *pcie)
> >
> >  		usleep_range(LINK_WAIT_MIN, LINK_WAIT_MAX);
> >  	}
> > +
> >  	dev_err(&pcie->pdev->dev, "link never came up\n");
> > +
> >  	return -ETIMEDOUT;
> >  }
> >
> > @@ -551,16 +558,16 @@ static void mobiveil_pcie_enable_msi(struct
> mobiveil_pcie *pcie)
> >  	msi->msi_pages_phys = (phys_addr_t)msg_addr;
> >
> >  	writel_relaxed(lower_32_bits(msg_addr),
> > -		pcie->apb_csr_base + MSI_BASE_LO_OFFSET);
> > +		       pcie->apb_csr_base + MSI_BASE_LO_OFFSET);
> >  	writel_relaxed(upper_32_bits(msg_addr),
> > -		pcie->apb_csr_base + MSI_BASE_HI_OFFSET);
> > +		       pcie->apb_csr_base + MSI_BASE_HI_OFFSET);
> >  	writel_relaxed(4096, pcie->apb_csr_base + MSI_SIZE_OFFSET);
> >  	writel_relaxed(1, pcie->apb_csr_base + MSI_ENABLE_OFFSET);  }
> >
> >  static int mobiveil_host_init(struct mobiveil_pcie *pcie)  {
> > -	u32 value, pab_ctrl, type = 0;
> > +	u32 value, pab_ctrl, type;
> >  	int err;
> >  	struct resource_entry *win, *tmp;
> >
> > @@ -575,26 +582,27 @@ static int mobiveil_host_init(struct
> mobiveil_pcie *pcie)
> >  	 * Space
> >  	 */
> >  	value = csr_readl(pcie, PCI_COMMAND);
> > -	csr_writel(pcie, value | PCI_COMMAND_IO |
> PCI_COMMAND_MEMORY |
> > -		PCI_COMMAND_MASTER, PCI_COMMAND);
> > +	value |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
> PCI_COMMAND_MASTER;
> > +	csr_writel(pcie, value, PCI_COMMAND);
> >
> >  	/*
> >  	 * program PIO Enable Bit to 1 (and PEX PIO Enable to 1) in PAB_CTRL
> >  	 * register
> >  	 */
> >  	pab_ctrl = csr_readl(pcie, PAB_CTRL);
> > -	csr_writel(pcie, pab_ctrl | (1 << AMBA_PIO_ENABLE_SHIFT) |
> > -		(1 << PEX_PIO_ENABLE_SHIFT), PAB_CTRL);
> > +	pab_ctrl |= (1 << AMBA_PIO_ENABLE_SHIFT) | (1 <<
> PEX_PIO_ENABLE_SHIFT);
> > +	csr_writel(pcie, pab_ctrl, PAB_CTRL);
> >
> >  	csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK),
> > -		PAB_INTP_AMBA_MISC_ENB);
> > +		   PAB_INTP_AMBA_MISC_ENB);
> >
> >  	/*
> >  	 * program PIO Enable Bit to 1 and Config Window Enable Bit to 1 in
> >  	 * PAB_AXI_PIO_CTRL Register
> >  	 */
> >  	value = csr_readl(pcie, PAB_AXI_PIO_CTRL);
> > -	csr_writel(pcie, value | APIO_EN_MASK, PAB_AXI_PIO_CTRL);
> > +	value |= APIO_EN_MASK;
> > +	csr_writel(pcie, value, PAB_AXI_PIO_CTRL);
> >
> >  	/*
> >  	 * we'll program one outbound window for config reads and @@
> -605,25
> > +613,25 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
> >
> >  	/* config outbound translation window */
> >  	program_ob_windows(pcie, pcie->ob_wins_configured,
> > -			pcie->ob_io_res->start, 0, CFG_WINDOW_TYPE,
> > -			resource_size(pcie->ob_io_res));
> > +			   pcie->ob_io_res->start, 0, CFG_WINDOW_TYPE,
> > +			   resource_size(pcie->ob_io_res));
> >
> >  	/* memory inbound translation window */
> >  	program_ib_windows(pcie, WIN_NUM_1, 0, MEM_WINDOW_TYPE,
> > IB_WIN_SIZE);
> >
> >  	/* Get the I/O and memory ranges from DT */
> >  	resource_list_for_each_entry_safe(win, tmp, &pcie->resources) {
> > -		type = 0;
> >  		if (resource_type(win->res) == IORESOURCE_MEM)
> >  			type = MEM_WINDOW_TYPE;
> > -		if (resource_type(win->res) == IORESOURCE_IO)
> > +		else if (resource_type(win->res) == IORESOURCE_IO)
> >  			type = IO_WINDOW_TYPE;
> > -		if (type) {
> > -			/* configure outbound translation window */
> > -			program_ob_windows(pcie, pcie->ob_wins_configured,
> > -				win->res->start, 0, type,
> > -				resource_size(win->res));
> > -		}
> > +		else
> > +			continue;
> > +
> > +		/* configure outbound translation window */
> > +		program_ob_windows(pcie, pcie->ob_wins_configured,
> > +				   win->res->start, 0, type,
> > +				   resource_size(win->res));
> >  	}
> >
> >  	/* setup MSI hardware registers */
> > @@ -643,7 +651,8 @@ static void mobiveil_mask_intx_irq(struct irq_data
> *data)
> >  	mask = 1 << ((data->hwirq + PAB_INTX_START) - 1);
> >  	raw_spin_lock_irqsave(&pcie->intx_mask_lock, flags);
> >  	shifted_val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
> > -	csr_writel(pcie, (shifted_val & (~mask)), PAB_INTP_AMBA_MISC_ENB);
> > +	shifted_val &= ~mask;
> > +	csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
> >  	raw_spin_unlock_irqrestore(&pcie->intx_mask_lock, flags);  }
> >
> > @@ -658,7 +667,8 @@ static void mobiveil_unmask_intx_irq(struct
> irq_data *data)
> >  	mask = 1 << ((data->hwirq + PAB_INTX_START) - 1);
> >  	raw_spin_lock_irqsave(&pcie->intx_mask_lock, flags);
> >  	shifted_val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
> > -	csr_writel(pcie, (shifted_val | mask), PAB_INTP_AMBA_MISC_ENB);
> > +	shifted_val |= mask;
> > +	csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
> >  	raw_spin_unlock_irqrestore(&pcie->intx_mask_lock, flags);  }
> >
> > @@ -672,10 +682,11 @@ static struct irq_chip intx_irq_chip = {
> >
> >  /* routine to setup the INTx related data */  static int
> > mobiveil_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
> > -		irq_hw_number_t hwirq)
> > +				  irq_hw_number_t hwirq)
> >  {
> >  	irq_set_chip_and_handler(irq, &intx_irq_chip, handle_level_irq);
> >  	irq_set_chip_data(irq, domain->host_data);
> > +
> >  	return 0;
> >  }
> >
> > @@ -692,7 +703,7 @@ static struct irq_chip mobiveil_msi_irq_chip = {
> >
> >  static struct msi_domain_info mobiveil_msi_domain_info = {
> >  	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS |
> MSI_FLAG_USE_DEF_CHIP_OPS |
> > -		MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX),
> > +		   MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX),
> >  	.chip	= &mobiveil_msi_irq_chip,
> >  };
> >
> > @@ -710,7 +721,7 @@ static void mobiveil_compose_msi_msg(struct
> > irq_data *data, struct msi_msg *msg)  }
> >
> >  static int mobiveil_msi_set_affinity(struct irq_data *irq_data,
> > -		const struct cpumask *mask, bool force)
> > +				     const struct cpumask *mask, bool force)
> >  {
> >  	return -EINVAL;
> >  }
> > @@ -722,7 +733,8 @@ static struct irq_chip
> > mobiveil_msi_bottom_irq_chip = {  };
> >
> >  static int mobiveil_irq_msi_domain_alloc(struct irq_domain *domain,
> > -		unsigned int virq, unsigned int nr_irqs, void *args)
> > +					 unsigned int virq,
> > +					 unsigned int nr_irqs, void *args)
> >  {
> >  	struct mobiveil_pcie *pcie = domain->host_data;
> >  	struct mobiveil_msi *msi = &pcie->msi; @@ -742,13 +754,13 @@ static
> > int mobiveil_irq_msi_domain_alloc(struct irq_domain *domain,
> >  	mutex_unlock(&msi->lock);
> >
> >  	irq_domain_set_info(domain, virq, bit,
> &mobiveil_msi_bottom_irq_chip,
> > -				domain->host_data, handle_level_irq,
> > -				NULL, NULL);
> > +			    domain->host_data, handle_level_irq, NULL, NULL);
> >  	return 0;
> >  }
> >
> >  static void mobiveil_irq_msi_domain_free(struct irq_domain *domain,
> > -		unsigned int virq, unsigned int nr_irqs)
> > +					 unsigned int virq,
> > +					 unsigned int nr_irqs)
> >  {
> >  	struct irq_data *d = irq_domain_get_irq_data(domain, virq);
> >  	struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(d); @@
> > -756,12 +768,11 @@ static void mobiveil_irq_msi_domain_free(struct
> > irq_domain *domain,
> >
> >  	mutex_lock(&msi->lock);
> >
> > -	if (!test_bit(d->hwirq, msi->msi_irq_in_use)) {
> > +	if (!test_bit(d->hwirq, msi->msi_irq_in_use))
> >  		dev_err(&pcie->pdev->dev, "trying to free unused MSI#%lu\n",
> >  			d->hwirq);
> > -	} else {
> > +	else
> >  		__clear_bit(d->hwirq, msi->msi_irq_in_use);
> > -	}
> >
> >  	mutex_unlock(&msi->lock);
> >  }
> > @@ -785,12 +796,14 @@ static int mobiveil_allocate_msi_domains(struct
> mobiveil_pcie *pcie)
> >  	}
> >
> >  	msi->msi_domain = pci_msi_create_irq_domain(fwnode,
> > -				&mobiveil_msi_domain_info, msi->dev_domain);
> > +						    &mobiveil_msi_domain_info,
> > +						    msi->dev_domain);
> >  	if (!msi->msi_domain) {
> >  		dev_err(dev, "failed to create MSI domain\n");
> >  		irq_domain_remove(msi->dev_domain);
> >  		return -ENOMEM;
> >  	}
> > +
> >  	return 0;
> >  }
> >
> > @@ -801,8 +814,8 @@ static int mobiveil_pcie_init_irq_domain(struct
> mobiveil_pcie *pcie)
> >  	int ret;
> >
> >  	/* setup INTx */
> > -	pcie->intx_domain = irq_domain_add_linear(node,
> > -				PCI_NUM_INTX, &intx_domain_ops, pcie);
> > +	pcie->intx_domain = irq_domain_add_linear(node, PCI_NUM_INTX,
> > +						  &intx_domain_ops, pcie);
> >
> >  	if (!pcie->intx_domain) {
> >  		dev_err(dev, "Failed to get a INTx IRQ domain\n"); @@ -917,10
> > +930,10 @@ MODULE_DEVICE_TABLE(of, mobiveil_pcie_of_match);
> static
> > struct platform_driver mobiveil_pcie_driver = {
> >  	.probe = mobiveil_pcie_probe,
> >  	.driver = {
> > -			.name = "mobiveil-pcie",
> > -			.of_match_table = mobiveil_pcie_of_match,
> > -			.suppress_bind_attrs = true,
> > -		},
> > +		.name = "mobiveil-pcie",
> > +		.of_match_table = mobiveil_pcie_of_match,
> > +		.suppress_bind_attrs = true,
> > +	},
> >  };
> >
> >  builtin_platform_driver(mobiveil_pcie_driver);
> > --
> > 2.17.1
> >

^ permalink raw reply	[flat|nested] 67+ messages in thread

* RE: [PATCHv5 02/20] PCI: mobiveil: Format the code without functionality change
  2019-07-03 15:19   ` Lorenzo Pieralisi
  2019-07-03 15:24     ` Lorenzo Pieralisi
@ 2019-07-04  3:00     ` Z.q. Hou
  2019-07-04 10:56       ` Lorenzo Pieralisi
  1 sibling, 1 reply; 67+ messages in thread
From: Z.q. Hou @ 2019-07-04  3:00 UTC (permalink / raw)
  To: Lorenzo Pieralisi
  Cc: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	catalin.marinas, will.deacon, Mingkai Hu, M.h. Lian, Xiaowei Bao

Hi Lorenzo,

Thanks for your comments!

> -----Original Message-----
> From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Sent: 2019年7月3日 23:19
> To: Z.q. Hou <zhiqiang.hou@nxp.com>
> Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> bhelgaas@google.com; robh+dt@kernel.org; mark.rutland@arm.com;
> l.subrahmanya@mobiveil.co.in; shawnguo@kernel.org; Leo Li
> <leoyang.li@nxp.com>; catalin.marinas@arm.com; will.deacon@arm.com;
> Mingkai Hu <mingkai.hu@nxp.com>; M.h. Lian <minghuan.lian@nxp.com>;
> Xiaowei Bao <xiaowei.bao@nxp.com>
> Subject: Re: [PATCHv5 02/20] PCI: mobiveil: Format the code without
> functionality change
> 
> On Fri, Apr 12, 2019 at 08:35:24AM +0000, Z.q. Hou wrote:
> > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> >
> > Just format the code without functionality change.
> >
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> > ---
> > V5:
> >  - Retouched the subject.
> >
> >  drivers/pci/controller/pcie-mobiveil.c | 261
> > +++++++++++++------------
> >  1 file changed, 137 insertions(+), 124 deletions(-)
> 
> Ok, dropping this patch means that everything else should be rebased. So
> what I am going to do:
> 
> - I will publish a branch (pci/mobiveil) where I added the patches
>   that are ready to be merged with commit logs rewritten; this patch
>   is part of it but in the final version it must be split as requested.
> - You have to split this patch and the other patches I requested
>   you to split but do NOT modify the patches with my commit logs
>   rewritten in pci/mobiveil, it took me time to rewrite them.

Yes, will split them and won't modify the commit logs, and thanks a lot
for your help!

> 
> If you can manage to rebase patches on pci/mobiveil on top of v5.2-rc1,
> send them separately so that I can merge them as a base for the subsequent
> patches to be applied.

You meant send the patches one by one, which you requested to split, and
other patches without any changes can be send together, right?

> 
> If you have any questions please ask, do not post patches if there is
> something that is not clear.

Yes, I'll, thanks for your guide again!

B.R,
Zhiqiang

> 
> Lorenzo
> 
> > diff --git a/drivers/pci/controller/pcie-mobiveil.c
> > b/drivers/pci/controller/pcie-mobiveil.c
> > index d55c7e780c6e..b87471f08a40 100644
> > --- a/drivers/pci/controller/pcie-mobiveil.c
> > +++ b/drivers/pci/controller/pcie-mobiveil.c
> > @@ -31,38 +31,40 @@
> >   * translation tables are grouped into windows, each window registers
> are
> >   * grouped into blocks of 4 or 16 registers each
> >   */
> > -#define PAB_REG_BLOCK_SIZE	16
> > -#define PAB_EXT_REG_BLOCK_SIZE	4
> > +#define PAB_REG_BLOCK_SIZE		16
> > +#define PAB_EXT_REG_BLOCK_SIZE		4
> >
> > -#define PAB_REG_ADDR(offset, win) (offset + (win *
> > PAB_REG_BLOCK_SIZE)) -#define PAB_EXT_REG_ADDR(offset, win) (offset
> +
> > (win * PAB_EXT_REG_BLOCK_SIZE))
> > +#define PAB_REG_ADDR(offset, win)	\
> > +	(offset + (win * PAB_REG_BLOCK_SIZE))
> > +#define PAB_EXT_REG_ADDR(offset, win)	\
> > +	(offset + (win * PAB_EXT_REG_BLOCK_SIZE))
> >
> > -#define LTSSM_STATUS		0x0404
> > -#define  LTSSM_STATUS_L0_MASK	0x3f
> > -#define  LTSSM_STATUS_L0	0x2d
> > +#define LTSSM_STATUS			0x0404
> > +#define  LTSSM_STATUS_L0_MASK		0x3f
> > +#define  LTSSM_STATUS_L0		0x2d
> >
> > -#define PAB_CTRL		0x0808
> > -#define  AMBA_PIO_ENABLE_SHIFT	0
> > -#define  PEX_PIO_ENABLE_SHIFT	1
> > -#define  PAGE_SEL_SHIFT	13
> > -#define  PAGE_SEL_MASK		0x3f
> > -#define  PAGE_LO_MASK		0x3ff
> > -#define  PAGE_SEL_OFFSET_SHIFT	10
> > +#define PAB_CTRL			0x0808
> > +#define  AMBA_PIO_ENABLE_SHIFT		0
> > +#define  PEX_PIO_ENABLE_SHIFT		1
> > +#define  PAGE_SEL_SHIFT			13
> > +#define  PAGE_SEL_MASK			0x3f
> > +#define  PAGE_LO_MASK			0x3ff
> > +#define  PAGE_SEL_OFFSET_SHIFT		10
> >
> > -#define PAB_AXI_PIO_CTRL	0x0840
> > -#define  APIO_EN_MASK		0xf
> > +#define PAB_AXI_PIO_CTRL		0x0840
> > +#define  APIO_EN_MASK			0xf
> >
> > -#define PAB_PEX_PIO_CTRL	0x08c0
> > -#define  PIO_ENABLE_SHIFT	0
> > +#define PAB_PEX_PIO_CTRL		0x08c0
> > +#define  PIO_ENABLE_SHIFT		0
> >
> >  #define PAB_INTP_AMBA_MISC_ENB		0x0b0c
> > -#define PAB_INTP_AMBA_MISC_STAT	0x0b1c
> > +#define PAB_INTP_AMBA_MISC_STAT		0x0b1c
> >  #define  PAB_INTP_INTX_MASK		0x01e0
> >  #define  PAB_INTP_MSI_MASK		0x8
> >
> > -#define PAB_AXI_AMAP_CTRL(win)	PAB_REG_ADDR(0x0ba0, win)
> > -#define  WIN_ENABLE_SHIFT	0
> > -#define  WIN_TYPE_SHIFT	1
> > +#define PAB_AXI_AMAP_CTRL(win)		PAB_REG_ADDR(0x0ba0, win)
> > +#define  WIN_ENABLE_SHIFT		0
> > +#define  WIN_TYPE_SHIFT			1
> >
> >  #define PAB_EXT_AXI_AMAP_SIZE(win)	PAB_EXT_REG_ADDR(0xbaf0,
> win)
> >
> > @@ -70,16 +72,16 @@
> >  #define  AXI_WINDOW_ALIGN_MASK		3
> >
> >  #define PAB_AXI_AMAP_PEX_WIN_L(win)	PAB_REG_ADDR(0x0ba8,
> win)
> > -#define  PAB_BUS_SHIFT		24
> > -#define  PAB_DEVICE_SHIFT	19
> > -#define  PAB_FUNCTION_SHIFT	16
> > +#define  PAB_BUS_SHIFT			24
> > +#define  PAB_DEVICE_SHIFT		19
> > +#define  PAB_FUNCTION_SHIFT		16
> >
> >  #define PAB_AXI_AMAP_PEX_WIN_H(win)	PAB_REG_ADDR(0x0bac,
> win)
> >  #define PAB_INTP_AXI_PIO_CLASS		0x474
> >
> > -#define PAB_PEX_AMAP_CTRL(win)	PAB_REG_ADDR(0x4ba0, win)
> > -#define  AMAP_CTRL_EN_SHIFT	0
> > -#define  AMAP_CTRL_TYPE_SHIFT	1
> > +#define PAB_PEX_AMAP_CTRL(win)		PAB_REG_ADDR(0x4ba0,
> win)
> > +#define  AMAP_CTRL_EN_SHIFT		0
> > +#define  AMAP_CTRL_TYPE_SHIFT		1
> >
> >  #define PAB_EXT_PEX_AMAP_SIZEN(win)	PAB_EXT_REG_ADDR(0xbef0,
> win)
> >  #define PAB_PEX_AMAP_AXI_WIN(win)	PAB_REG_ADDR(0x4ba4,
> win)
> > @@ -87,39 +89,39 @@
> >  #define PAB_PEX_AMAP_PEX_WIN_H(win)	PAB_REG_ADDR(0x4bac,
> win)
> >
> >  /* starting offset of INTX bits in status register */
> > -#define PAB_INTX_START	5
> > +#define PAB_INTX_START			5
> >
> >  /* supported number of MSI interrupts */
> > -#define PCI_NUM_MSI	16
> > +#define PCI_NUM_MSI			16
> >
> >  /* MSI registers */
> > -#define MSI_BASE_LO_OFFSET	0x04
> > -#define MSI_BASE_HI_OFFSET	0x08
> > -#define MSI_SIZE_OFFSET	0x0c
> > -#define MSI_ENABLE_OFFSET	0x14
> > -#define MSI_STATUS_OFFSET	0x18
> > -#define MSI_DATA_OFFSET	0x20
> > -#define MSI_ADDR_L_OFFSET	0x24
> > -#define MSI_ADDR_H_OFFSET	0x28
> > +#define MSI_BASE_LO_OFFSET		0x04
> > +#define MSI_BASE_HI_OFFSET		0x08
> > +#define MSI_SIZE_OFFSET			0x0c
> > +#define MSI_ENABLE_OFFSET		0x14
> > +#define MSI_STATUS_OFFSET		0x18
> > +#define MSI_DATA_OFFSET			0x20
> > +#define MSI_ADDR_L_OFFSET		0x24
> > +#define MSI_ADDR_H_OFFSET		0x28
> >
> >  /* outbound and inbound window definitions */
> > -#define WIN_NUM_0		0
> > -#define WIN_NUM_1		1
> > -#define CFG_WINDOW_TYPE	0
> > -#define IO_WINDOW_TYPE		1
> > -#define MEM_WINDOW_TYPE	2
> > -#define IB_WIN_SIZE		((u64)256 * 1024 * 1024 * 1024)
> > -#define MAX_PIO_WINDOWS	8
> > +#define WIN_NUM_0			0
> > +#define WIN_NUM_1			1
> > +#define CFG_WINDOW_TYPE			0
> > +#define IO_WINDOW_TYPE			1
> > +#define MEM_WINDOW_TYPE			2
> > +#define IB_WIN_SIZE			((u64)256 * 1024 * 1024 * 1024)
> > +#define MAX_PIO_WINDOWS			8
> >
> >  /* Parameters for the waiting for link up routine */
> > -#define LINK_WAIT_MAX_RETRIES	10
> > -#define LINK_WAIT_MIN	90000
> > -#define LINK_WAIT_MAX	100000
> > +#define LINK_WAIT_MAX_RETRIES		10
> > +#define LINK_WAIT_MIN			90000
> > +#define LINK_WAIT_MAX			100000
> >
> > -#define PAGED_ADDR_BNDRY			0xc00
> > -#define OFFSET_TO_PAGE_ADDR(off)		\
> > +#define PAGED_ADDR_BNDRY		0xc00
> > +#define OFFSET_TO_PAGE_ADDR(off)	\
> >  	((off & PAGE_LO_MASK) | PAGED_ADDR_BNDRY)
> > -#define OFFSET_TO_PAGE_IDX(off)			\
> > +#define OFFSET_TO_PAGE_IDX(off)		\
> >  	((off >> PAGE_SEL_OFFSET_SHIFT) & PAGE_SEL_MASK)
> >
> >  struct mobiveil_msi {			/* MSI information */
> > @@ -297,14 +299,14 @@ static void __iomem
> *mobiveil_pcie_map_bus(struct pci_bus *bus,
> >  					unsigned int devfn, int where)
> >  {
> >  	struct mobiveil_pcie *pcie = bus->sysdata;
> > +	u32 value;
> >
> >  	if (!mobiveil_pcie_valid_device(bus, devfn))
> >  		return NULL;
> >
> > -	if (bus->number == pcie->root_bus_nr) {
> > -		/* RC config access */
> > +	/* RC config access */
> > +	if (bus->number == pcie->root_bus_nr)
> >  		return pcie->csr_axi_slave_base + where;
> > -	}
> >
> >  	/*
> >  	 * EP config access (in Config/APIO space) @@ -312,10 +314,12 @@
> > static void __iomem *mobiveil_pcie_map_bus(struct pci_bus *bus,
> >  	 * (BDF) in PAB_AXI_AMAP_PEX_WIN_L0 Register.
> >  	 * Relies on pci_lock serialization
> >  	 */
> > -	csr_writel(pcie, bus->number << PAB_BUS_SHIFT |
> > -			PCI_SLOT(devfn) << PAB_DEVICE_SHIFT |
> > -			PCI_FUNC(devfn) << PAB_FUNCTION_SHIFT,
> > -			PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0));
> > +	value = bus->number << PAB_BUS_SHIFT |
> > +		PCI_SLOT(devfn) << PAB_DEVICE_SHIFT |
> > +		PCI_FUNC(devfn) << PAB_FUNCTION_SHIFT;
> > +
> > +	csr_writel(pcie, value, PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0));
> > +
> >  	return pcie->config_axi_slave_base + where;  }
> >
> > @@ -350,22 +354,22 @@ static void mobiveil_pcie_isr(struct irq_desc
> > *desc)
> >
> >  	/* Handle INTx */
> >  	if (intr_status & PAB_INTP_INTX_MASK) {
> > -		shifted_status = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT) >>
> > -			PAB_INTX_START;
> > +		shifted_status = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT);
> > +		shifted_status >>= PAB_INTX_START;
> >  		do {
> >  			for_each_set_bit(bit, &shifted_status, PCI_NUM_INTX) {
> >  				virq = irq_find_mapping(pcie->intx_domain,
> > -						bit + 1);
> > +							bit + 1);
> >  				if (virq)
> >  					generic_handle_irq(virq);
> >  				else
> > -					dev_err_ratelimited(dev,
> > -						"unexpected IRQ, INT%d\n", bit);
> > +					dev_err_ratelimited(dev, "unexpected IRQ,
> INT%d\n",
> > +							    bit);
> >
> >  				/* clear interrupt */
> >  				csr_writel(pcie,
> > -					shifted_status << PAB_INTX_START,
> > -					PAB_INTP_AMBA_MISC_STAT);
> > +					   shifted_status << PAB_INTX_START,
> > +					   PAB_INTP_AMBA_MISC_STAT);
> >  			}
> >  		} while ((shifted_status >> PAB_INTX_START) != 0);
> >  	}
> > @@ -375,8 +379,7 @@ static void mobiveil_pcie_isr(struct irq_desc
> > *desc)
> >
> >  	/* handle MSI interrupts */
> >  	while (msi_status & 1) {
> > -		msi_data = readl_relaxed(pcie->apb_csr_base
> > -				+ MSI_DATA_OFFSET);
> > +		msi_data = readl_relaxed(pcie->apb_csr_base +
> MSI_DATA_OFFSET);
> >
> >  		/*
> >  		 * MSI_STATUS_OFFSET register gets updated to zero @@ -385,18
> > +388,18 @@ static void mobiveil_pcie_isr(struct irq_desc *desc)
> >  		 * two dummy reads.
> >  		 */
> >  		msi_addr_lo = readl_relaxed(pcie->apb_csr_base +
> > -				MSI_ADDR_L_OFFSET);
> > +					    MSI_ADDR_L_OFFSET);
> >  		msi_addr_hi = readl_relaxed(pcie->apb_csr_base +
> > -				MSI_ADDR_H_OFFSET);
> > +					    MSI_ADDR_H_OFFSET);
> >  		dev_dbg(dev, "MSI registers, data: %08x, addr: %08x:%08x\n",
> > -				msi_data, msi_addr_hi, msi_addr_lo);
> > +			msi_data, msi_addr_hi, msi_addr_lo);
> >
> >  		virq = irq_find_mapping(msi->dev_domain, msi_data);
> >  		if (virq)
> >  			generic_handle_irq(virq);
> >
> >  		msi_status = readl_relaxed(pcie->apb_csr_base +
> > -				MSI_STATUS_OFFSET);
> > +					   MSI_STATUS_OFFSET);
> >  	}
> >
> >  	/* Clear the interrupt status */
> > @@ -413,7 +416,7 @@ static int mobiveil_pcie_parse_dt(struct
> > mobiveil_pcie *pcie)
> >
> >  	/* map config resource */
> >  	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> > -			"config_axi_slave");
> > +					   "config_axi_slave");
> >  	pcie->config_axi_slave_base = devm_pci_remap_cfg_resource(dev,
> res);
> >  	if (IS_ERR(pcie->config_axi_slave_base))
> >  		return PTR_ERR(pcie->config_axi_slave_base);
> > @@ -421,7 +424,7 @@ static int mobiveil_pcie_parse_dt(struct
> > mobiveil_pcie *pcie)
> >
> >  	/* map csr resource */
> >  	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> > -			"csr_axi_slave");
> > +					   "csr_axi_slave");
> >  	pcie->csr_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);
> >  	if (IS_ERR(pcie->csr_axi_slave_base))
> >  		return PTR_ERR(pcie->csr_axi_slave_base);
> > @@ -452,7 +455,7 @@ static int mobiveil_pcie_parse_dt(struct
> > mobiveil_pcie *pcie)  }
> >
> >  static void program_ib_windows(struct mobiveil_pcie *pcie, int
> win_num,
> > -		int pci_addr, u32 type, u64 size)
> > +			       int pci_addr, u32 type, u64 size)
> >  {
> >  	int pio_ctrl_val;
> >  	int amap_ctrl_dw;
> > @@ -465,19 +468,20 @@ static void program_ib_windows(struct
> mobiveil_pcie *pcie, int win_num,
> >  	}
> >
> >  	pio_ctrl_val = csr_readl(pcie, PAB_PEX_PIO_CTRL);
> > -	csr_writel(pcie,
> > -		pio_ctrl_val | (1 << PIO_ENABLE_SHIFT), PAB_PEX_PIO_CTRL);
> > -	amap_ctrl_dw = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
> > -	amap_ctrl_dw = (amap_ctrl_dw | (type << AMAP_CTRL_TYPE_SHIFT));
> > -	amap_ctrl_dw = (amap_ctrl_dw | (1 << AMAP_CTRL_EN_SHIFT));
> > +	pio_ctrl_val |= 1 << PIO_ENABLE_SHIFT;
> > +	csr_writel(pcie, pio_ctrl_val, PAB_PEX_PIO_CTRL);
> >
> > -	csr_writel(pcie, amap_ctrl_dw | lower_32_bits(size64),
> > -		   PAB_PEX_AMAP_CTRL(win_num));
> > +	amap_ctrl_dw = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
> > +	amap_ctrl_dw |= (type << AMAP_CTRL_TYPE_SHIFT) |
> > +			(1 << AMAP_CTRL_EN_SHIFT) |
> > +			lower_32_bits(size64);
> > +	csr_writel(pcie, amap_ctrl_dw, PAB_PEX_AMAP_CTRL(win_num));
> >
> >  	csr_writel(pcie, upper_32_bits(size64),
> >  		   PAB_EXT_PEX_AMAP_SIZEN(win_num));
> >
> >  	csr_writel(pcie, pci_addr, PAB_PEX_AMAP_AXI_WIN(win_num));
> > +
> >  	csr_writel(pcie, pci_addr, PAB_PEX_AMAP_PEX_WIN_L(win_num));
> >  	csr_writel(pcie, 0, PAB_PEX_AMAP_PEX_WIN_H(win_num));  } @@
> -486,7
> > +490,8 @@ static void program_ib_windows(struct mobiveil_pcie *pcie,
> int win_num,
> >   * routine to program the outbound windows
> >   */
> >  static void program_ob_windows(struct mobiveil_pcie *pcie, int
> win_num,
> > -		u64 cpu_addr, u64 pci_addr, u32 config_io_bit, u64 size)
> > +			       u64 cpu_addr, u64 pci_addr,
> > +			       u32 config_io_bit, u64 size)
> >  {
> >
> >  	u32 value, type;
> > @@ -505,7 +510,7 @@ static void program_ob_windows(struct
> mobiveil_pcie *pcie, int win_num,
> >  	type = config_io_bit;
> >  	value = csr_readl(pcie, PAB_AXI_AMAP_CTRL(win_num));
> >  	csr_writel(pcie, 1 << WIN_ENABLE_SHIFT | type << WIN_TYPE_SHIFT |
> > -			lower_32_bits(size64), PAB_AXI_AMAP_CTRL(win_num));
> > +		   lower_32_bits(size64), PAB_AXI_AMAP_CTRL(win_num));
> >
> >  	csr_writel(pcie, upper_32_bits(size64),
> > PAB_EXT_AXI_AMAP_SIZE(win_num));
> >
> > @@ -515,14 +520,14 @@ static void program_ob_windows(struct
> mobiveil_pcie *pcie, int win_num,
> >  	 */
> >  	value = csr_readl(pcie, PAB_AXI_AMAP_AXI_WIN(win_num));
> >  	csr_writel(pcie, cpu_addr & (~AXI_WINDOW_ALIGN_MASK),
> > -			PAB_AXI_AMAP_AXI_WIN(win_num));
> > +		   PAB_AXI_AMAP_AXI_WIN(win_num));
> >
> >  	value = csr_readl(pcie, PAB_AXI_AMAP_PEX_WIN_H(win_num));
> >
> >  	csr_writel(pcie, lower_32_bits(pci_addr),
> > -			PAB_AXI_AMAP_PEX_WIN_L(win_num));
> > +		   PAB_AXI_AMAP_PEX_WIN_L(win_num));
> >  	csr_writel(pcie, upper_32_bits(pci_addr),
> > -			PAB_AXI_AMAP_PEX_WIN_H(win_num));
> > +		   PAB_AXI_AMAP_PEX_WIN_H(win_num));
> >
> >  	pcie->ob_wins_configured++;
> >  }
> > @@ -538,7 +543,9 @@ static int mobiveil_bringup_link(struct
> > mobiveil_pcie *pcie)
> >
> >  		usleep_range(LINK_WAIT_MIN, LINK_WAIT_MAX);
> >  	}
> > +
> >  	dev_err(&pcie->pdev->dev, "link never came up\n");
> > +
> >  	return -ETIMEDOUT;
> >  }
> >
> > @@ -551,16 +558,16 @@ static void mobiveil_pcie_enable_msi(struct
> mobiveil_pcie *pcie)
> >  	msi->msi_pages_phys = (phys_addr_t)msg_addr;
> >
> >  	writel_relaxed(lower_32_bits(msg_addr),
> > -		pcie->apb_csr_base + MSI_BASE_LO_OFFSET);
> > +		       pcie->apb_csr_base + MSI_BASE_LO_OFFSET);
> >  	writel_relaxed(upper_32_bits(msg_addr),
> > -		pcie->apb_csr_base + MSI_BASE_HI_OFFSET);
> > +		       pcie->apb_csr_base + MSI_BASE_HI_OFFSET);
> >  	writel_relaxed(4096, pcie->apb_csr_base + MSI_SIZE_OFFSET);
> >  	writel_relaxed(1, pcie->apb_csr_base + MSI_ENABLE_OFFSET);  }
> >
> >  static int mobiveil_host_init(struct mobiveil_pcie *pcie)  {
> > -	u32 value, pab_ctrl, type = 0;
> > +	u32 value, pab_ctrl, type;
> >  	int err;
> >  	struct resource_entry *win, *tmp;
> >
> > @@ -575,26 +582,27 @@ static int mobiveil_host_init(struct
> mobiveil_pcie *pcie)
> >  	 * Space
> >  	 */
> >  	value = csr_readl(pcie, PCI_COMMAND);
> > -	csr_writel(pcie, value | PCI_COMMAND_IO |
> PCI_COMMAND_MEMORY |
> > -		PCI_COMMAND_MASTER, PCI_COMMAND);
> > +	value |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
> PCI_COMMAND_MASTER;
> > +	csr_writel(pcie, value, PCI_COMMAND);
> >
> >  	/*
> >  	 * program PIO Enable Bit to 1 (and PEX PIO Enable to 1) in PAB_CTRL
> >  	 * register
> >  	 */
> >  	pab_ctrl = csr_readl(pcie, PAB_CTRL);
> > -	csr_writel(pcie, pab_ctrl | (1 << AMBA_PIO_ENABLE_SHIFT) |
> > -		(1 << PEX_PIO_ENABLE_SHIFT), PAB_CTRL);
> > +	pab_ctrl |= (1 << AMBA_PIO_ENABLE_SHIFT) | (1 <<
> PEX_PIO_ENABLE_SHIFT);
> > +	csr_writel(pcie, pab_ctrl, PAB_CTRL);
> >
> >  	csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK),
> > -		PAB_INTP_AMBA_MISC_ENB);
> > +		   PAB_INTP_AMBA_MISC_ENB);
> >
> >  	/*
> >  	 * program PIO Enable Bit to 1 and Config Window Enable Bit to 1 in
> >  	 * PAB_AXI_PIO_CTRL Register
> >  	 */
> >  	value = csr_readl(pcie, PAB_AXI_PIO_CTRL);
> > -	csr_writel(pcie, value | APIO_EN_MASK, PAB_AXI_PIO_CTRL);
> > +	value |= APIO_EN_MASK;
> > +	csr_writel(pcie, value, PAB_AXI_PIO_CTRL);
> >
> >  	/*
> >  	 * we'll program one outbound window for config reads and @@
> -605,25
> > +613,25 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
> >
> >  	/* config outbound translation window */
> >  	program_ob_windows(pcie, pcie->ob_wins_configured,
> > -			pcie->ob_io_res->start, 0, CFG_WINDOW_TYPE,
> > -			resource_size(pcie->ob_io_res));
> > +			   pcie->ob_io_res->start, 0, CFG_WINDOW_TYPE,
> > +			   resource_size(pcie->ob_io_res));
> >
> >  	/* memory inbound translation window */
> >  	program_ib_windows(pcie, WIN_NUM_1, 0, MEM_WINDOW_TYPE,
> > IB_WIN_SIZE);
> >
> >  	/* Get the I/O and memory ranges from DT */
> >  	resource_list_for_each_entry_safe(win, tmp, &pcie->resources) {
> > -		type = 0;
> >  		if (resource_type(win->res) == IORESOURCE_MEM)
> >  			type = MEM_WINDOW_TYPE;
> > -		if (resource_type(win->res) == IORESOURCE_IO)
> > +		else if (resource_type(win->res) == IORESOURCE_IO)
> >  			type = IO_WINDOW_TYPE;
> > -		if (type) {
> > -			/* configure outbound translation window */
> > -			program_ob_windows(pcie, pcie->ob_wins_configured,
> > -				win->res->start, 0, type,
> > -				resource_size(win->res));
> > -		}
> > +		else
> > +			continue;
> > +
> > +		/* configure outbound translation window */
> > +		program_ob_windows(pcie, pcie->ob_wins_configured,
> > +				   win->res->start, 0, type,
> > +				   resource_size(win->res));
> >  	}
> >
> >  	/* setup MSI hardware registers */
> > @@ -643,7 +651,8 @@ static void mobiveil_mask_intx_irq(struct irq_data
> *data)
> >  	mask = 1 << ((data->hwirq + PAB_INTX_START) - 1);
> >  	raw_spin_lock_irqsave(&pcie->intx_mask_lock, flags);
> >  	shifted_val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
> > -	csr_writel(pcie, (shifted_val & (~mask)), PAB_INTP_AMBA_MISC_ENB);
> > +	shifted_val &= ~mask;
> > +	csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
> >  	raw_spin_unlock_irqrestore(&pcie->intx_mask_lock, flags);  }
> >
> > @@ -658,7 +667,8 @@ static void mobiveil_unmask_intx_irq(struct
> irq_data *data)
> >  	mask = 1 << ((data->hwirq + PAB_INTX_START) - 1);
> >  	raw_spin_lock_irqsave(&pcie->intx_mask_lock, flags);
> >  	shifted_val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
> > -	csr_writel(pcie, (shifted_val | mask), PAB_INTP_AMBA_MISC_ENB);
> > +	shifted_val |= mask;
> > +	csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
> >  	raw_spin_unlock_irqrestore(&pcie->intx_mask_lock, flags);  }
> >
> > @@ -672,10 +682,11 @@ static struct irq_chip intx_irq_chip = {
> >
> >  /* routine to setup the INTx related data */  static int
> > mobiveil_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
> > -		irq_hw_number_t hwirq)
> > +				  irq_hw_number_t hwirq)
> >  {
> >  	irq_set_chip_and_handler(irq, &intx_irq_chip, handle_level_irq);
> >  	irq_set_chip_data(irq, domain->host_data);
> > +
> >  	return 0;
> >  }
> >
> > @@ -692,7 +703,7 @@ static struct irq_chip mobiveil_msi_irq_chip = {
> >
> >  static struct msi_domain_info mobiveil_msi_domain_info = {
> >  	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS |
> MSI_FLAG_USE_DEF_CHIP_OPS |
> > -		MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX),
> > +		   MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX),
> >  	.chip	= &mobiveil_msi_irq_chip,
> >  };
> >
> > @@ -710,7 +721,7 @@ static void mobiveil_compose_msi_msg(struct
> > irq_data *data, struct msi_msg *msg)  }
> >
> >  static int mobiveil_msi_set_affinity(struct irq_data *irq_data,
> > -		const struct cpumask *mask, bool force)
> > +				     const struct cpumask *mask, bool force)
> >  {
> >  	return -EINVAL;
> >  }
> > @@ -722,7 +733,8 @@ static struct irq_chip
> > mobiveil_msi_bottom_irq_chip = {  };
> >
> >  static int mobiveil_irq_msi_domain_alloc(struct irq_domain *domain,
> > -		unsigned int virq, unsigned int nr_irqs, void *args)
> > +					 unsigned int virq,
> > +					 unsigned int nr_irqs, void *args)
> >  {
> >  	struct mobiveil_pcie *pcie = domain->host_data;
> >  	struct mobiveil_msi *msi = &pcie->msi; @@ -742,13 +754,13 @@ static
> > int mobiveil_irq_msi_domain_alloc(struct irq_domain *domain,
> >  	mutex_unlock(&msi->lock);
> >
> >  	irq_domain_set_info(domain, virq, bit,
> &mobiveil_msi_bottom_irq_chip,
> > -				domain->host_data, handle_level_irq,
> > -				NULL, NULL);
> > +			    domain->host_data, handle_level_irq, NULL, NULL);
> >  	return 0;
> >  }
> >
> >  static void mobiveil_irq_msi_domain_free(struct irq_domain *domain,
> > -		unsigned int virq, unsigned int nr_irqs)
> > +					 unsigned int virq,
> > +					 unsigned int nr_irqs)
> >  {
> >  	struct irq_data *d = irq_domain_get_irq_data(domain, virq);
> >  	struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(d); @@
> > -756,12 +768,11 @@ static void mobiveil_irq_msi_domain_free(struct
> > irq_domain *domain,
> >
> >  	mutex_lock(&msi->lock);
> >
> > -	if (!test_bit(d->hwirq, msi->msi_irq_in_use)) {
> > +	if (!test_bit(d->hwirq, msi->msi_irq_in_use))
> >  		dev_err(&pcie->pdev->dev, "trying to free unused MSI#%lu\n",
> >  			d->hwirq);
> > -	} else {
> > +	else
> >  		__clear_bit(d->hwirq, msi->msi_irq_in_use);
> > -	}
> >
> >  	mutex_unlock(&msi->lock);
> >  }
> > @@ -785,12 +796,14 @@ static int mobiveil_allocate_msi_domains(struct
> mobiveil_pcie *pcie)
> >  	}
> >
> >  	msi->msi_domain = pci_msi_create_irq_domain(fwnode,
> > -				&mobiveil_msi_domain_info, msi->dev_domain);
> > +						    &mobiveil_msi_domain_info,
> > +						    msi->dev_domain);
> >  	if (!msi->msi_domain) {
> >  		dev_err(dev, "failed to create MSI domain\n");
> >  		irq_domain_remove(msi->dev_domain);
> >  		return -ENOMEM;
> >  	}
> > +
> >  	return 0;
> >  }
> >
> > @@ -801,8 +814,8 @@ static int mobiveil_pcie_init_irq_domain(struct
> mobiveil_pcie *pcie)
> >  	int ret;
> >
> >  	/* setup INTx */
> > -	pcie->intx_domain = irq_domain_add_linear(node,
> > -				PCI_NUM_INTX, &intx_domain_ops, pcie);
> > +	pcie->intx_domain = irq_domain_add_linear(node, PCI_NUM_INTX,
> > +						  &intx_domain_ops, pcie);
> >
> >  	if (!pcie->intx_domain) {
> >  		dev_err(dev, "Failed to get a INTx IRQ domain\n"); @@ -917,10
> > +930,10 @@ MODULE_DEVICE_TABLE(of, mobiveil_pcie_of_match);
> static
> > struct platform_driver mobiveil_pcie_driver = {
> >  	.probe = mobiveil_pcie_probe,
> >  	.driver = {
> > -			.name = "mobiveil-pcie",
> > -			.of_match_table = mobiveil_pcie_of_match,
> > -			.suppress_bind_attrs = true,
> > -		},
> > +		.name = "mobiveil-pcie",
> > +		.of_match_table = mobiveil_pcie_of_match,
> > +		.suppress_bind_attrs = true,
> > +	},
> >  };
> >
> >  builtin_platform_driver(mobiveil_pcie_driver);
> > --
> > 2.17.1
> >

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCHv5 02/20] PCI: mobiveil: Format the code without functionality change
  2019-07-04  3:00     ` Z.q. Hou
@ 2019-07-04 10:56       ` Lorenzo Pieralisi
  2019-07-05  2:24         ` Z.q. Hou
  0 siblings, 1 reply; 67+ messages in thread
From: Lorenzo Pieralisi @ 2019-07-04 10:56 UTC (permalink / raw)
  To: Z.q. Hou
  Cc: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	catalin.marinas, will.deacon, Mingkai Hu, M.h. Lian, Xiaowei Bao

On Thu, Jul 04, 2019 at 03:00:37AM +0000, Z.q. Hou wrote:

[...]

> > If you can manage to rebase patches on pci/mobiveil on top of v5.2-rc1,
> > send them separately so that I can merge them as a base for the subsequent
> > patches to be applied.
> 
> You meant send the patches one by one, which you requested to split, and
> other patches without any changes can be send together, right?

First step, rebase my branch above against v5.2-rc1 *without* this
patch. Then apply all the patches I requested to split (inclusive of
this one) on top of it and send the whole patch series in one go.

Please let me know if that's still unclear.

Thanks,
Lorenzo

> > If you have any questions please ask, do not post patches if there is
> > something that is not clear.
> 
> Yes, I'll, thanks for your guide again!
> 
> B.R,
> Zhiqiang
> 
> > 
> > Lorenzo
> > 
> > > diff --git a/drivers/pci/controller/pcie-mobiveil.c
> > > b/drivers/pci/controller/pcie-mobiveil.c
> > > index d55c7e780c6e..b87471f08a40 100644
> > > --- a/drivers/pci/controller/pcie-mobiveil.c
> > > +++ b/drivers/pci/controller/pcie-mobiveil.c
> > > @@ -31,38 +31,40 @@
> > >   * translation tables are grouped into windows, each window registers
> > are
> > >   * grouped into blocks of 4 or 16 registers each
> > >   */
> > > -#define PAB_REG_BLOCK_SIZE	16
> > > -#define PAB_EXT_REG_BLOCK_SIZE	4
> > > +#define PAB_REG_BLOCK_SIZE		16
> > > +#define PAB_EXT_REG_BLOCK_SIZE		4
> > >
> > > -#define PAB_REG_ADDR(offset, win) (offset + (win *
> > > PAB_REG_BLOCK_SIZE)) -#define PAB_EXT_REG_ADDR(offset, win) (offset
> > +
> > > (win * PAB_EXT_REG_BLOCK_SIZE))
> > > +#define PAB_REG_ADDR(offset, win)	\
> > > +	(offset + (win * PAB_REG_BLOCK_SIZE))
> > > +#define PAB_EXT_REG_ADDR(offset, win)	\
> > > +	(offset + (win * PAB_EXT_REG_BLOCK_SIZE))
> > >
> > > -#define LTSSM_STATUS		0x0404
> > > -#define  LTSSM_STATUS_L0_MASK	0x3f
> > > -#define  LTSSM_STATUS_L0	0x2d
> > > +#define LTSSM_STATUS			0x0404
> > > +#define  LTSSM_STATUS_L0_MASK		0x3f
> > > +#define  LTSSM_STATUS_L0		0x2d
> > >
> > > -#define PAB_CTRL		0x0808
> > > -#define  AMBA_PIO_ENABLE_SHIFT	0
> > > -#define  PEX_PIO_ENABLE_SHIFT	1
> > > -#define  PAGE_SEL_SHIFT	13
> > > -#define  PAGE_SEL_MASK		0x3f
> > > -#define  PAGE_LO_MASK		0x3ff
> > > -#define  PAGE_SEL_OFFSET_SHIFT	10
> > > +#define PAB_CTRL			0x0808
> > > +#define  AMBA_PIO_ENABLE_SHIFT		0
> > > +#define  PEX_PIO_ENABLE_SHIFT		1
> > > +#define  PAGE_SEL_SHIFT			13
> > > +#define  PAGE_SEL_MASK			0x3f
> > > +#define  PAGE_LO_MASK			0x3ff
> > > +#define  PAGE_SEL_OFFSET_SHIFT		10
> > >
> > > -#define PAB_AXI_PIO_CTRL	0x0840
> > > -#define  APIO_EN_MASK		0xf
> > > +#define PAB_AXI_PIO_CTRL		0x0840
> > > +#define  APIO_EN_MASK			0xf
> > >
> > > -#define PAB_PEX_PIO_CTRL	0x08c0
> > > -#define  PIO_ENABLE_SHIFT	0
> > > +#define PAB_PEX_PIO_CTRL		0x08c0
> > > +#define  PIO_ENABLE_SHIFT		0
> > >
> > >  #define PAB_INTP_AMBA_MISC_ENB		0x0b0c
> > > -#define PAB_INTP_AMBA_MISC_STAT	0x0b1c
> > > +#define PAB_INTP_AMBA_MISC_STAT		0x0b1c
> > >  #define  PAB_INTP_INTX_MASK		0x01e0
> > >  #define  PAB_INTP_MSI_MASK		0x8
> > >
> > > -#define PAB_AXI_AMAP_CTRL(win)	PAB_REG_ADDR(0x0ba0, win)
> > > -#define  WIN_ENABLE_SHIFT	0
> > > -#define  WIN_TYPE_SHIFT	1
> > > +#define PAB_AXI_AMAP_CTRL(win)		PAB_REG_ADDR(0x0ba0, win)
> > > +#define  WIN_ENABLE_SHIFT		0
> > > +#define  WIN_TYPE_SHIFT			1
> > >
> > >  #define PAB_EXT_AXI_AMAP_SIZE(win)	PAB_EXT_REG_ADDR(0xbaf0,
> > win)
> > >
> > > @@ -70,16 +72,16 @@
> > >  #define  AXI_WINDOW_ALIGN_MASK		3
> > >
> > >  #define PAB_AXI_AMAP_PEX_WIN_L(win)	PAB_REG_ADDR(0x0ba8,
> > win)
> > > -#define  PAB_BUS_SHIFT		24
> > > -#define  PAB_DEVICE_SHIFT	19
> > > -#define  PAB_FUNCTION_SHIFT	16
> > > +#define  PAB_BUS_SHIFT			24
> > > +#define  PAB_DEVICE_SHIFT		19
> > > +#define  PAB_FUNCTION_SHIFT		16
> > >
> > >  #define PAB_AXI_AMAP_PEX_WIN_H(win)	PAB_REG_ADDR(0x0bac,
> > win)
> > >  #define PAB_INTP_AXI_PIO_CLASS		0x474
> > >
> > > -#define PAB_PEX_AMAP_CTRL(win)	PAB_REG_ADDR(0x4ba0, win)
> > > -#define  AMAP_CTRL_EN_SHIFT	0
> > > -#define  AMAP_CTRL_TYPE_SHIFT	1
> > > +#define PAB_PEX_AMAP_CTRL(win)		PAB_REG_ADDR(0x4ba0,
> > win)
> > > +#define  AMAP_CTRL_EN_SHIFT		0
> > > +#define  AMAP_CTRL_TYPE_SHIFT		1
> > >
> > >  #define PAB_EXT_PEX_AMAP_SIZEN(win)	PAB_EXT_REG_ADDR(0xbef0,
> > win)
> > >  #define PAB_PEX_AMAP_AXI_WIN(win)	PAB_REG_ADDR(0x4ba4,
> > win)
> > > @@ -87,39 +89,39 @@
> > >  #define PAB_PEX_AMAP_PEX_WIN_H(win)	PAB_REG_ADDR(0x4bac,
> > win)
> > >
> > >  /* starting offset of INTX bits in status register */
> > > -#define PAB_INTX_START	5
> > > +#define PAB_INTX_START			5
> > >
> > >  /* supported number of MSI interrupts */
> > > -#define PCI_NUM_MSI	16
> > > +#define PCI_NUM_MSI			16
> > >
> > >  /* MSI registers */
> > > -#define MSI_BASE_LO_OFFSET	0x04
> > > -#define MSI_BASE_HI_OFFSET	0x08
> > > -#define MSI_SIZE_OFFSET	0x0c
> > > -#define MSI_ENABLE_OFFSET	0x14
> > > -#define MSI_STATUS_OFFSET	0x18
> > > -#define MSI_DATA_OFFSET	0x20
> > > -#define MSI_ADDR_L_OFFSET	0x24
> > > -#define MSI_ADDR_H_OFFSET	0x28
> > > +#define MSI_BASE_LO_OFFSET		0x04
> > > +#define MSI_BASE_HI_OFFSET		0x08
> > > +#define MSI_SIZE_OFFSET			0x0c
> > > +#define MSI_ENABLE_OFFSET		0x14
> > > +#define MSI_STATUS_OFFSET		0x18
> > > +#define MSI_DATA_OFFSET			0x20
> > > +#define MSI_ADDR_L_OFFSET		0x24
> > > +#define MSI_ADDR_H_OFFSET		0x28
> > >
> > >  /* outbound and inbound window definitions */
> > > -#define WIN_NUM_0		0
> > > -#define WIN_NUM_1		1
> > > -#define CFG_WINDOW_TYPE	0
> > > -#define IO_WINDOW_TYPE		1
> > > -#define MEM_WINDOW_TYPE	2
> > > -#define IB_WIN_SIZE		((u64)256 * 1024 * 1024 * 1024)
> > > -#define MAX_PIO_WINDOWS	8
> > > +#define WIN_NUM_0			0
> > > +#define WIN_NUM_1			1
> > > +#define CFG_WINDOW_TYPE			0
> > > +#define IO_WINDOW_TYPE			1
> > > +#define MEM_WINDOW_TYPE			2
> > > +#define IB_WIN_SIZE			((u64)256 * 1024 * 1024 * 1024)
> > > +#define MAX_PIO_WINDOWS			8
> > >
> > >  /* Parameters for the waiting for link up routine */
> > > -#define LINK_WAIT_MAX_RETRIES	10
> > > -#define LINK_WAIT_MIN	90000
> > > -#define LINK_WAIT_MAX	100000
> > > +#define LINK_WAIT_MAX_RETRIES		10
> > > +#define LINK_WAIT_MIN			90000
> > > +#define LINK_WAIT_MAX			100000
> > >
> > > -#define PAGED_ADDR_BNDRY			0xc00
> > > -#define OFFSET_TO_PAGE_ADDR(off)		\
> > > +#define PAGED_ADDR_BNDRY		0xc00
> > > +#define OFFSET_TO_PAGE_ADDR(off)	\
> > >  	((off & PAGE_LO_MASK) | PAGED_ADDR_BNDRY)
> > > -#define OFFSET_TO_PAGE_IDX(off)			\
> > > +#define OFFSET_TO_PAGE_IDX(off)		\
> > >  	((off >> PAGE_SEL_OFFSET_SHIFT) & PAGE_SEL_MASK)
> > >
> > >  struct mobiveil_msi {			/* MSI information */
> > > @@ -297,14 +299,14 @@ static void __iomem
> > *mobiveil_pcie_map_bus(struct pci_bus *bus,
> > >  					unsigned int devfn, int where)
> > >  {
> > >  	struct mobiveil_pcie *pcie = bus->sysdata;
> > > +	u32 value;
> > >
> > >  	if (!mobiveil_pcie_valid_device(bus, devfn))
> > >  		return NULL;
> > >
> > > -	if (bus->number == pcie->root_bus_nr) {
> > > -		/* RC config access */
> > > +	/* RC config access */
> > > +	if (bus->number == pcie->root_bus_nr)
> > >  		return pcie->csr_axi_slave_base + where;
> > > -	}
> > >
> > >  	/*
> > >  	 * EP config access (in Config/APIO space) @@ -312,10 +314,12 @@
> > > static void __iomem *mobiveil_pcie_map_bus(struct pci_bus *bus,
> > >  	 * (BDF) in PAB_AXI_AMAP_PEX_WIN_L0 Register.
> > >  	 * Relies on pci_lock serialization
> > >  	 */
> > > -	csr_writel(pcie, bus->number << PAB_BUS_SHIFT |
> > > -			PCI_SLOT(devfn) << PAB_DEVICE_SHIFT |
> > > -			PCI_FUNC(devfn) << PAB_FUNCTION_SHIFT,
> > > -			PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0));
> > > +	value = bus->number << PAB_BUS_SHIFT |
> > > +		PCI_SLOT(devfn) << PAB_DEVICE_SHIFT |
> > > +		PCI_FUNC(devfn) << PAB_FUNCTION_SHIFT;
> > > +
> > > +	csr_writel(pcie, value, PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0));
> > > +
> > >  	return pcie->config_axi_slave_base + where;  }
> > >
> > > @@ -350,22 +354,22 @@ static void mobiveil_pcie_isr(struct irq_desc
> > > *desc)
> > >
> > >  	/* Handle INTx */
> > >  	if (intr_status & PAB_INTP_INTX_MASK) {
> > > -		shifted_status = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT) >>
> > > -			PAB_INTX_START;
> > > +		shifted_status = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT);
> > > +		shifted_status >>= PAB_INTX_START;
> > >  		do {
> > >  			for_each_set_bit(bit, &shifted_status, PCI_NUM_INTX) {
> > >  				virq = irq_find_mapping(pcie->intx_domain,
> > > -						bit + 1);
> > > +							bit + 1);
> > >  				if (virq)
> > >  					generic_handle_irq(virq);
> > >  				else
> > > -					dev_err_ratelimited(dev,
> > > -						"unexpected IRQ, INT%d\n", bit);
> > > +					dev_err_ratelimited(dev, "unexpected IRQ,
> > INT%d\n",
> > > +							    bit);
> > >
> > >  				/* clear interrupt */
> > >  				csr_writel(pcie,
> > > -					shifted_status << PAB_INTX_START,
> > > -					PAB_INTP_AMBA_MISC_STAT);
> > > +					   shifted_status << PAB_INTX_START,
> > > +					   PAB_INTP_AMBA_MISC_STAT);
> > >  			}
> > >  		} while ((shifted_status >> PAB_INTX_START) != 0);
> > >  	}
> > > @@ -375,8 +379,7 @@ static void mobiveil_pcie_isr(struct irq_desc
> > > *desc)
> > >
> > >  	/* handle MSI interrupts */
> > >  	while (msi_status & 1) {
> > > -		msi_data = readl_relaxed(pcie->apb_csr_base
> > > -				+ MSI_DATA_OFFSET);
> > > +		msi_data = readl_relaxed(pcie->apb_csr_base +
> > MSI_DATA_OFFSET);
> > >
> > >  		/*
> > >  		 * MSI_STATUS_OFFSET register gets updated to zero @@ -385,18
> > > +388,18 @@ static void mobiveil_pcie_isr(struct irq_desc *desc)
> > >  		 * two dummy reads.
> > >  		 */
> > >  		msi_addr_lo = readl_relaxed(pcie->apb_csr_base +
> > > -				MSI_ADDR_L_OFFSET);
> > > +					    MSI_ADDR_L_OFFSET);
> > >  		msi_addr_hi = readl_relaxed(pcie->apb_csr_base +
> > > -				MSI_ADDR_H_OFFSET);
> > > +					    MSI_ADDR_H_OFFSET);
> > >  		dev_dbg(dev, "MSI registers, data: %08x, addr: %08x:%08x\n",
> > > -				msi_data, msi_addr_hi, msi_addr_lo);
> > > +			msi_data, msi_addr_hi, msi_addr_lo);
> > >
> > >  		virq = irq_find_mapping(msi->dev_domain, msi_data);
> > >  		if (virq)
> > >  			generic_handle_irq(virq);
> > >
> > >  		msi_status = readl_relaxed(pcie->apb_csr_base +
> > > -				MSI_STATUS_OFFSET);
> > > +					   MSI_STATUS_OFFSET);
> > >  	}
> > >
> > >  	/* Clear the interrupt status */
> > > @@ -413,7 +416,7 @@ static int mobiveil_pcie_parse_dt(struct
> > > mobiveil_pcie *pcie)
> > >
> > >  	/* map config resource */
> > >  	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> > > -			"config_axi_slave");
> > > +					   "config_axi_slave");
> > >  	pcie->config_axi_slave_base = devm_pci_remap_cfg_resource(dev,
> > res);
> > >  	if (IS_ERR(pcie->config_axi_slave_base))
> > >  		return PTR_ERR(pcie->config_axi_slave_base);
> > > @@ -421,7 +424,7 @@ static int mobiveil_pcie_parse_dt(struct
> > > mobiveil_pcie *pcie)
> > >
> > >  	/* map csr resource */
> > >  	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> > > -			"csr_axi_slave");
> > > +					   "csr_axi_slave");
> > >  	pcie->csr_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);
> > >  	if (IS_ERR(pcie->csr_axi_slave_base))
> > >  		return PTR_ERR(pcie->csr_axi_slave_base);
> > > @@ -452,7 +455,7 @@ static int mobiveil_pcie_parse_dt(struct
> > > mobiveil_pcie *pcie)  }
> > >
> > >  static void program_ib_windows(struct mobiveil_pcie *pcie, int
> > win_num,
> > > -		int pci_addr, u32 type, u64 size)
> > > +			       int pci_addr, u32 type, u64 size)
> > >  {
> > >  	int pio_ctrl_val;
> > >  	int amap_ctrl_dw;
> > > @@ -465,19 +468,20 @@ static void program_ib_windows(struct
> > mobiveil_pcie *pcie, int win_num,
> > >  	}
> > >
> > >  	pio_ctrl_val = csr_readl(pcie, PAB_PEX_PIO_CTRL);
> > > -	csr_writel(pcie,
> > > -		pio_ctrl_val | (1 << PIO_ENABLE_SHIFT), PAB_PEX_PIO_CTRL);
> > > -	amap_ctrl_dw = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
> > > -	amap_ctrl_dw = (amap_ctrl_dw | (type << AMAP_CTRL_TYPE_SHIFT));
> > > -	amap_ctrl_dw = (amap_ctrl_dw | (1 << AMAP_CTRL_EN_SHIFT));
> > > +	pio_ctrl_val |= 1 << PIO_ENABLE_SHIFT;
> > > +	csr_writel(pcie, pio_ctrl_val, PAB_PEX_PIO_CTRL);
> > >
> > > -	csr_writel(pcie, amap_ctrl_dw | lower_32_bits(size64),
> > > -		   PAB_PEX_AMAP_CTRL(win_num));
> > > +	amap_ctrl_dw = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
> > > +	amap_ctrl_dw |= (type << AMAP_CTRL_TYPE_SHIFT) |
> > > +			(1 << AMAP_CTRL_EN_SHIFT) |
> > > +			lower_32_bits(size64);
> > > +	csr_writel(pcie, amap_ctrl_dw, PAB_PEX_AMAP_CTRL(win_num));
> > >
> > >  	csr_writel(pcie, upper_32_bits(size64),
> > >  		   PAB_EXT_PEX_AMAP_SIZEN(win_num));
> > >
> > >  	csr_writel(pcie, pci_addr, PAB_PEX_AMAP_AXI_WIN(win_num));
> > > +
> > >  	csr_writel(pcie, pci_addr, PAB_PEX_AMAP_PEX_WIN_L(win_num));
> > >  	csr_writel(pcie, 0, PAB_PEX_AMAP_PEX_WIN_H(win_num));  } @@
> > -486,7
> > > +490,8 @@ static void program_ib_windows(struct mobiveil_pcie *pcie,
> > int win_num,
> > >   * routine to program the outbound windows
> > >   */
> > >  static void program_ob_windows(struct mobiveil_pcie *pcie, int
> > win_num,
> > > -		u64 cpu_addr, u64 pci_addr, u32 config_io_bit, u64 size)
> > > +			       u64 cpu_addr, u64 pci_addr,
> > > +			       u32 config_io_bit, u64 size)
> > >  {
> > >
> > >  	u32 value, type;
> > > @@ -505,7 +510,7 @@ static void program_ob_windows(struct
> > mobiveil_pcie *pcie, int win_num,
> > >  	type = config_io_bit;
> > >  	value = csr_readl(pcie, PAB_AXI_AMAP_CTRL(win_num));
> > >  	csr_writel(pcie, 1 << WIN_ENABLE_SHIFT | type << WIN_TYPE_SHIFT |
> > > -			lower_32_bits(size64), PAB_AXI_AMAP_CTRL(win_num));
> > > +		   lower_32_bits(size64), PAB_AXI_AMAP_CTRL(win_num));
> > >
> > >  	csr_writel(pcie, upper_32_bits(size64),
> > > PAB_EXT_AXI_AMAP_SIZE(win_num));
> > >
> > > @@ -515,14 +520,14 @@ static void program_ob_windows(struct
> > mobiveil_pcie *pcie, int win_num,
> > >  	 */
> > >  	value = csr_readl(pcie, PAB_AXI_AMAP_AXI_WIN(win_num));
> > >  	csr_writel(pcie, cpu_addr & (~AXI_WINDOW_ALIGN_MASK),
> > > -			PAB_AXI_AMAP_AXI_WIN(win_num));
> > > +		   PAB_AXI_AMAP_AXI_WIN(win_num));
> > >
> > >  	value = csr_readl(pcie, PAB_AXI_AMAP_PEX_WIN_H(win_num));
> > >
> > >  	csr_writel(pcie, lower_32_bits(pci_addr),
> > > -			PAB_AXI_AMAP_PEX_WIN_L(win_num));
> > > +		   PAB_AXI_AMAP_PEX_WIN_L(win_num));
> > >  	csr_writel(pcie, upper_32_bits(pci_addr),
> > > -			PAB_AXI_AMAP_PEX_WIN_H(win_num));
> > > +		   PAB_AXI_AMAP_PEX_WIN_H(win_num));
> > >
> > >  	pcie->ob_wins_configured++;
> > >  }
> > > @@ -538,7 +543,9 @@ static int mobiveil_bringup_link(struct
> > > mobiveil_pcie *pcie)
> > >
> > >  		usleep_range(LINK_WAIT_MIN, LINK_WAIT_MAX);
> > >  	}
> > > +
> > >  	dev_err(&pcie->pdev->dev, "link never came up\n");
> > > +
> > >  	return -ETIMEDOUT;
> > >  }
> > >
> > > @@ -551,16 +558,16 @@ static void mobiveil_pcie_enable_msi(struct
> > mobiveil_pcie *pcie)
> > >  	msi->msi_pages_phys = (phys_addr_t)msg_addr;
> > >
> > >  	writel_relaxed(lower_32_bits(msg_addr),
> > > -		pcie->apb_csr_base + MSI_BASE_LO_OFFSET);
> > > +		       pcie->apb_csr_base + MSI_BASE_LO_OFFSET);
> > >  	writel_relaxed(upper_32_bits(msg_addr),
> > > -		pcie->apb_csr_base + MSI_BASE_HI_OFFSET);
> > > +		       pcie->apb_csr_base + MSI_BASE_HI_OFFSET);
> > >  	writel_relaxed(4096, pcie->apb_csr_base + MSI_SIZE_OFFSET);
> > >  	writel_relaxed(1, pcie->apb_csr_base + MSI_ENABLE_OFFSET);  }
> > >
> > >  static int mobiveil_host_init(struct mobiveil_pcie *pcie)  {
> > > -	u32 value, pab_ctrl, type = 0;
> > > +	u32 value, pab_ctrl, type;
> > >  	int err;
> > >  	struct resource_entry *win, *tmp;
> > >
> > > @@ -575,26 +582,27 @@ static int mobiveil_host_init(struct
> > mobiveil_pcie *pcie)
> > >  	 * Space
> > >  	 */
> > >  	value = csr_readl(pcie, PCI_COMMAND);
> > > -	csr_writel(pcie, value | PCI_COMMAND_IO |
> > PCI_COMMAND_MEMORY |
> > > -		PCI_COMMAND_MASTER, PCI_COMMAND);
> > > +	value |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
> > PCI_COMMAND_MASTER;
> > > +	csr_writel(pcie, value, PCI_COMMAND);
> > >
> > >  	/*
> > >  	 * program PIO Enable Bit to 1 (and PEX PIO Enable to 1) in PAB_CTRL
> > >  	 * register
> > >  	 */
> > >  	pab_ctrl = csr_readl(pcie, PAB_CTRL);
> > > -	csr_writel(pcie, pab_ctrl | (1 << AMBA_PIO_ENABLE_SHIFT) |
> > > -		(1 << PEX_PIO_ENABLE_SHIFT), PAB_CTRL);
> > > +	pab_ctrl |= (1 << AMBA_PIO_ENABLE_SHIFT) | (1 <<
> > PEX_PIO_ENABLE_SHIFT);
> > > +	csr_writel(pcie, pab_ctrl, PAB_CTRL);
> > >
> > >  	csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK),
> > > -		PAB_INTP_AMBA_MISC_ENB);
> > > +		   PAB_INTP_AMBA_MISC_ENB);
> > >
> > >  	/*
> > >  	 * program PIO Enable Bit to 1 and Config Window Enable Bit to 1 in
> > >  	 * PAB_AXI_PIO_CTRL Register
> > >  	 */
> > >  	value = csr_readl(pcie, PAB_AXI_PIO_CTRL);
> > > -	csr_writel(pcie, value | APIO_EN_MASK, PAB_AXI_PIO_CTRL);
> > > +	value |= APIO_EN_MASK;
> > > +	csr_writel(pcie, value, PAB_AXI_PIO_CTRL);
> > >
> > >  	/*
> > >  	 * we'll program one outbound window for config reads and @@
> > -605,25
> > > +613,25 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
> > >
> > >  	/* config outbound translation window */
> > >  	program_ob_windows(pcie, pcie->ob_wins_configured,
> > > -			pcie->ob_io_res->start, 0, CFG_WINDOW_TYPE,
> > > -			resource_size(pcie->ob_io_res));
> > > +			   pcie->ob_io_res->start, 0, CFG_WINDOW_TYPE,
> > > +			   resource_size(pcie->ob_io_res));
> > >
> > >  	/* memory inbound translation window */
> > >  	program_ib_windows(pcie, WIN_NUM_1, 0, MEM_WINDOW_TYPE,
> > > IB_WIN_SIZE);
> > >
> > >  	/* Get the I/O and memory ranges from DT */
> > >  	resource_list_for_each_entry_safe(win, tmp, &pcie->resources) {
> > > -		type = 0;
> > >  		if (resource_type(win->res) == IORESOURCE_MEM)
> > >  			type = MEM_WINDOW_TYPE;
> > > -		if (resource_type(win->res) == IORESOURCE_IO)
> > > +		else if (resource_type(win->res) == IORESOURCE_IO)
> > >  			type = IO_WINDOW_TYPE;
> > > -		if (type) {
> > > -			/* configure outbound translation window */
> > > -			program_ob_windows(pcie, pcie->ob_wins_configured,
> > > -				win->res->start, 0, type,
> > > -				resource_size(win->res));
> > > -		}
> > > +		else
> > > +			continue;
> > > +
> > > +		/* configure outbound translation window */
> > > +		program_ob_windows(pcie, pcie->ob_wins_configured,
> > > +				   win->res->start, 0, type,
> > > +				   resource_size(win->res));
> > >  	}
> > >
> > >  	/* setup MSI hardware registers */
> > > @@ -643,7 +651,8 @@ static void mobiveil_mask_intx_irq(struct irq_data
> > *data)
> > >  	mask = 1 << ((data->hwirq + PAB_INTX_START) - 1);
> > >  	raw_spin_lock_irqsave(&pcie->intx_mask_lock, flags);
> > >  	shifted_val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
> > > -	csr_writel(pcie, (shifted_val & (~mask)), PAB_INTP_AMBA_MISC_ENB);
> > > +	shifted_val &= ~mask;
> > > +	csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
> > >  	raw_spin_unlock_irqrestore(&pcie->intx_mask_lock, flags);  }
> > >
> > > @@ -658,7 +667,8 @@ static void mobiveil_unmask_intx_irq(struct
> > irq_data *data)
> > >  	mask = 1 << ((data->hwirq + PAB_INTX_START) - 1);
> > >  	raw_spin_lock_irqsave(&pcie->intx_mask_lock, flags);
> > >  	shifted_val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
> > > -	csr_writel(pcie, (shifted_val | mask), PAB_INTP_AMBA_MISC_ENB);
> > > +	shifted_val |= mask;
> > > +	csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
> > >  	raw_spin_unlock_irqrestore(&pcie->intx_mask_lock, flags);  }
> > >
> > > @@ -672,10 +682,11 @@ static struct irq_chip intx_irq_chip = {
> > >
> > >  /* routine to setup the INTx related data */  static int
> > > mobiveil_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
> > > -		irq_hw_number_t hwirq)
> > > +				  irq_hw_number_t hwirq)
> > >  {
> > >  	irq_set_chip_and_handler(irq, &intx_irq_chip, handle_level_irq);
> > >  	irq_set_chip_data(irq, domain->host_data);
> > > +
> > >  	return 0;
> > >  }
> > >
> > > @@ -692,7 +703,7 @@ static struct irq_chip mobiveil_msi_irq_chip = {
> > >
> > >  static struct msi_domain_info mobiveil_msi_domain_info = {
> > >  	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS |
> > MSI_FLAG_USE_DEF_CHIP_OPS |
> > > -		MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX),
> > > +		   MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX),
> > >  	.chip	= &mobiveil_msi_irq_chip,
> > >  };
> > >
> > > @@ -710,7 +721,7 @@ static void mobiveil_compose_msi_msg(struct
> > > irq_data *data, struct msi_msg *msg)  }
> > >
> > >  static int mobiveil_msi_set_affinity(struct irq_data *irq_data,
> > > -		const struct cpumask *mask, bool force)
> > > +				     const struct cpumask *mask, bool force)
> > >  {
> > >  	return -EINVAL;
> > >  }
> > > @@ -722,7 +733,8 @@ static struct irq_chip
> > > mobiveil_msi_bottom_irq_chip = {  };
> > >
> > >  static int mobiveil_irq_msi_domain_alloc(struct irq_domain *domain,
> > > -		unsigned int virq, unsigned int nr_irqs, void *args)
> > > +					 unsigned int virq,
> > > +					 unsigned int nr_irqs, void *args)
> > >  {
> > >  	struct mobiveil_pcie *pcie = domain->host_data;
> > >  	struct mobiveil_msi *msi = &pcie->msi; @@ -742,13 +754,13 @@ static
> > > int mobiveil_irq_msi_domain_alloc(struct irq_domain *domain,
> > >  	mutex_unlock(&msi->lock);
> > >
> > >  	irq_domain_set_info(domain, virq, bit,
> > &mobiveil_msi_bottom_irq_chip,
> > > -				domain->host_data, handle_level_irq,
> > > -				NULL, NULL);
> > > +			    domain->host_data, handle_level_irq, NULL, NULL);
> > >  	return 0;
> > >  }
> > >
> > >  static void mobiveil_irq_msi_domain_free(struct irq_domain *domain,
> > > -		unsigned int virq, unsigned int nr_irqs)
> > > +					 unsigned int virq,
> > > +					 unsigned int nr_irqs)
> > >  {
> > >  	struct irq_data *d = irq_domain_get_irq_data(domain, virq);
> > >  	struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(d); @@
> > > -756,12 +768,11 @@ static void mobiveil_irq_msi_domain_free(struct
> > > irq_domain *domain,
> > >
> > >  	mutex_lock(&msi->lock);
> > >
> > > -	if (!test_bit(d->hwirq, msi->msi_irq_in_use)) {
> > > +	if (!test_bit(d->hwirq, msi->msi_irq_in_use))
> > >  		dev_err(&pcie->pdev->dev, "trying to free unused MSI#%lu\n",
> > >  			d->hwirq);
> > > -	} else {
> > > +	else
> > >  		__clear_bit(d->hwirq, msi->msi_irq_in_use);
> > > -	}
> > >
> > >  	mutex_unlock(&msi->lock);
> > >  }
> > > @@ -785,12 +796,14 @@ static int mobiveil_allocate_msi_domains(struct
> > mobiveil_pcie *pcie)
> > >  	}
> > >
> > >  	msi->msi_domain = pci_msi_create_irq_domain(fwnode,
> > > -				&mobiveil_msi_domain_info, msi->dev_domain);
> > > +						    &mobiveil_msi_domain_info,
> > > +						    msi->dev_domain);
> > >  	if (!msi->msi_domain) {
> > >  		dev_err(dev, "failed to create MSI domain\n");
> > >  		irq_domain_remove(msi->dev_domain);
> > >  		return -ENOMEM;
> > >  	}
> > > +
> > >  	return 0;
> > >  }
> > >
> > > @@ -801,8 +814,8 @@ static int mobiveil_pcie_init_irq_domain(struct
> > mobiveil_pcie *pcie)
> > >  	int ret;
> > >
> > >  	/* setup INTx */
> > > -	pcie->intx_domain = irq_domain_add_linear(node,
> > > -				PCI_NUM_INTX, &intx_domain_ops, pcie);
> > > +	pcie->intx_domain = irq_domain_add_linear(node, PCI_NUM_INTX,
> > > +						  &intx_domain_ops, pcie);
> > >
> > >  	if (!pcie->intx_domain) {
> > >  		dev_err(dev, "Failed to get a INTx IRQ domain\n"); @@ -917,10
> > > +930,10 @@ MODULE_DEVICE_TABLE(of, mobiveil_pcie_of_match);
> > static
> > > struct platform_driver mobiveil_pcie_driver = {
> > >  	.probe = mobiveil_pcie_probe,
> > >  	.driver = {
> > > -			.name = "mobiveil-pcie",
> > > -			.of_match_table = mobiveil_pcie_of_match,
> > > -			.suppress_bind_attrs = true,
> > > -		},
> > > +		.name = "mobiveil-pcie",
> > > +		.of_match_table = mobiveil_pcie_of_match,
> > > +		.suppress_bind_attrs = true,
> > > +	},
> > >  };
> > >
> > >  builtin_platform_driver(mobiveil_pcie_driver);
> > > --
> > > 2.17.1
> > >

^ permalink raw reply	[flat|nested] 67+ messages in thread

* RE: [PATCHv5 02/20] PCI: mobiveil: Format the code without functionality change
  2019-07-04 10:56       ` Lorenzo Pieralisi
@ 2019-07-05  2:24         ` Z.q. Hou
  0 siblings, 0 replies; 67+ messages in thread
From: Z.q. Hou @ 2019-07-05  2:24 UTC (permalink / raw)
  To: Lorenzo Pieralisi
  Cc: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
	robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
	catalin.marinas, will.deacon, Mingkai Hu, M.h. Lian, Xiaowei Bao

Hi Lorenzo,

> -----Original Message-----
> From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Sent: 2019年7月4日 18:57
> To: Z.q. Hou <zhiqiang.hou@nxp.com>
> Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> bhelgaas@google.com; robh+dt@kernel.org; mark.rutland@arm.com;
> l.subrahmanya@mobiveil.co.in; shawnguo@kernel.org; Leo Li
> <leoyang.li@nxp.com>; catalin.marinas@arm.com; will.deacon@arm.com;
> Mingkai Hu <mingkai.hu@nxp.com>; M.h. Lian <minghuan.lian@nxp.com>;
> Xiaowei Bao <xiaowei.bao@nxp.com>
> Subject: Re: [PATCHv5 02/20] PCI: mobiveil: Format the code without
> functionality change
> 
> On Thu, Jul 04, 2019 at 03:00:37AM +0000, Z.q. Hou wrote:
> 
> [...]
> 
> > > If you can manage to rebase patches on pci/mobiveil on top of
> > > v5.2-rc1, send them separately so that I can merge them as a base
> > > for the subsequent patches to be applied.
> >
> > You meant send the patches one by one, which you requested to split,
> > and other patches without any changes can be send together, right?
> 
> First step, rebase my branch above against v5.2-rc1 *without* this patch.
> Then apply all the patches I requested to split (inclusive of this one) on top of
> it and send the whole patch series in one go.
> 
> Please let me know if that's still unclear.

It's clear now.

Thanks,
Zhiqiang

> Thanks,
> Lorenzo
> 
> > > If you have any questions please ask, do not post patches if there
> > > is something that is not clear.
> >
> > Yes, I'll, thanks for your guide again!
> >
> > B.R,
> > Zhiqiang
> >
> > >
> > > Lorenzo
> > >
> > > > diff --git a/drivers/pci/controller/pcie-mobiveil.c
> > > > b/drivers/pci/controller/pcie-mobiveil.c
> > > > index d55c7e780c6e..b87471f08a40 100644
> > > > --- a/drivers/pci/controller/pcie-mobiveil.c
> > > > +++ b/drivers/pci/controller/pcie-mobiveil.c
> > > > @@ -31,38 +31,40 @@
> > > >   * translation tables are grouped into windows, each window
> > > > registers
> > > are
> > > >   * grouped into blocks of 4 or 16 registers each
> > > >   */
> > > > -#define PAB_REG_BLOCK_SIZE	16
> > > > -#define PAB_EXT_REG_BLOCK_SIZE	4
> > > > +#define PAB_REG_BLOCK_SIZE		16
> > > > +#define PAB_EXT_REG_BLOCK_SIZE		4
> > > >
> > > > -#define PAB_REG_ADDR(offset, win) (offset + (win *
> > > > PAB_REG_BLOCK_SIZE)) -#define PAB_EXT_REG_ADDR(offset, win)
> > > > (offset
> > > +
> > > > (win * PAB_EXT_REG_BLOCK_SIZE))
> > > > +#define PAB_REG_ADDR(offset, win)	\
> > > > +	(offset + (win * PAB_REG_BLOCK_SIZE))
> > > > +#define PAB_EXT_REG_ADDR(offset, win)	\
> > > > +	(offset + (win * PAB_EXT_REG_BLOCK_SIZE))
> > > >
> > > > -#define LTSSM_STATUS		0x0404
> > > > -#define  LTSSM_STATUS_L0_MASK	0x3f
> > > > -#define  LTSSM_STATUS_L0	0x2d
> > > > +#define LTSSM_STATUS			0x0404
> > > > +#define  LTSSM_STATUS_L0_MASK		0x3f
> > > > +#define  LTSSM_STATUS_L0		0x2d
> > > >
> > > > -#define PAB_CTRL		0x0808
> > > > -#define  AMBA_PIO_ENABLE_SHIFT	0
> > > > -#define  PEX_PIO_ENABLE_SHIFT	1
> > > > -#define  PAGE_SEL_SHIFT	13
> > > > -#define  PAGE_SEL_MASK		0x3f
> > > > -#define  PAGE_LO_MASK		0x3ff
> > > > -#define  PAGE_SEL_OFFSET_SHIFT	10
> > > > +#define PAB_CTRL			0x0808
> > > > +#define  AMBA_PIO_ENABLE_SHIFT		0
> > > > +#define  PEX_PIO_ENABLE_SHIFT		1
> > > > +#define  PAGE_SEL_SHIFT			13
> > > > +#define  PAGE_SEL_MASK			0x3f
> > > > +#define  PAGE_LO_MASK			0x3ff
> > > > +#define  PAGE_SEL_OFFSET_SHIFT		10
> > > >
> > > > -#define PAB_AXI_PIO_CTRL	0x0840
> > > > -#define  APIO_EN_MASK		0xf
> > > > +#define PAB_AXI_PIO_CTRL		0x0840
> > > > +#define  APIO_EN_MASK			0xf
> > > >
> > > > -#define PAB_PEX_PIO_CTRL	0x08c0
> > > > -#define  PIO_ENABLE_SHIFT	0
> > > > +#define PAB_PEX_PIO_CTRL		0x08c0
> > > > +#define  PIO_ENABLE_SHIFT		0
> > > >
> > > >  #define PAB_INTP_AMBA_MISC_ENB		0x0b0c
> > > > -#define PAB_INTP_AMBA_MISC_STAT	0x0b1c
> > > > +#define PAB_INTP_AMBA_MISC_STAT		0x0b1c
> > > >  #define  PAB_INTP_INTX_MASK		0x01e0
> > > >  #define  PAB_INTP_MSI_MASK		0x8
> > > >
> > > > -#define PAB_AXI_AMAP_CTRL(win)	PAB_REG_ADDR(0x0ba0, win)
> > > > -#define  WIN_ENABLE_SHIFT	0
> > > > -#define  WIN_TYPE_SHIFT	1
> > > > +#define PAB_AXI_AMAP_CTRL(win)		PAB_REG_ADDR(0x0ba0,
> win)
> > > > +#define  WIN_ENABLE_SHIFT		0
> > > > +#define  WIN_TYPE_SHIFT			1
> > > >
> > > >  #define PAB_EXT_AXI_AMAP_SIZE(win)
> 	PAB_EXT_REG_ADDR(0xbaf0,
> > > win)
> > > >
> > > > @@ -70,16 +72,16 @@
> > > >  #define  AXI_WINDOW_ALIGN_MASK		3
> > > >
> > > >  #define PAB_AXI_AMAP_PEX_WIN_L(win)
> 	PAB_REG_ADDR(0x0ba8,
> > > win)
> > > > -#define  PAB_BUS_SHIFT		24
> > > > -#define  PAB_DEVICE_SHIFT	19
> > > > -#define  PAB_FUNCTION_SHIFT	16
> > > > +#define  PAB_BUS_SHIFT			24
> > > > +#define  PAB_DEVICE_SHIFT		19
> > > > +#define  PAB_FUNCTION_SHIFT		16
> > > >
> > > >  #define PAB_AXI_AMAP_PEX_WIN_H(win)
> 	PAB_REG_ADDR(0x0bac,
> > > win)
> > > >  #define PAB_INTP_AXI_PIO_CLASS		0x474
> > > >
> > > > -#define PAB_PEX_AMAP_CTRL(win)	PAB_REG_ADDR(0x4ba0, win)
> > > > -#define  AMAP_CTRL_EN_SHIFT	0
> > > > -#define  AMAP_CTRL_TYPE_SHIFT	1
> > > > +#define PAB_PEX_AMAP_CTRL(win)		PAB_REG_ADDR(0x4ba0,
> > > win)
> > > > +#define  AMAP_CTRL_EN_SHIFT		0
> > > > +#define  AMAP_CTRL_TYPE_SHIFT		1
> > > >
> > > >  #define PAB_EXT_PEX_AMAP_SIZEN(win)
> 	PAB_EXT_REG_ADDR(0xbef0,
> > > win)
> > > >  #define PAB_PEX_AMAP_AXI_WIN(win)	PAB_REG_ADDR(0x4ba4,
> > > win)
> > > > @@ -87,39 +89,39 @@
> > > >  #define PAB_PEX_AMAP_PEX_WIN_H(win)
> 	PAB_REG_ADDR(0x4bac,
> > > win)
> > > >
> > > >  /* starting offset of INTX bits in status register */
> > > > -#define PAB_INTX_START	5
> > > > +#define PAB_INTX_START			5
> > > >
> > > >  /* supported number of MSI interrupts */
> > > > -#define PCI_NUM_MSI	16
> > > > +#define PCI_NUM_MSI			16
> > > >
> > > >  /* MSI registers */
> > > > -#define MSI_BASE_LO_OFFSET	0x04
> > > > -#define MSI_BASE_HI_OFFSET	0x08
> > > > -#define MSI_SIZE_OFFSET	0x0c
> > > > -#define MSI_ENABLE_OFFSET	0x14
> > > > -#define MSI_STATUS_OFFSET	0x18
> > > > -#define MSI_DATA_OFFSET	0x20
> > > > -#define MSI_ADDR_L_OFFSET	0x24
> > > > -#define MSI_ADDR_H_OFFSET	0x28
> > > > +#define MSI_BASE_LO_OFFSET		0x04
> > > > +#define MSI_BASE_HI_OFFSET		0x08
> > > > +#define MSI_SIZE_OFFSET			0x0c
> > > > +#define MSI_ENABLE_OFFSET		0x14
> > > > +#define MSI_STATUS_OFFSET		0x18
> > > > +#define MSI_DATA_OFFSET			0x20
> > > > +#define MSI_ADDR_L_OFFSET		0x24
> > > > +#define MSI_ADDR_H_OFFSET		0x28
> > > >
> > > >  /* outbound and inbound window definitions */
> > > > -#define WIN_NUM_0		0
> > > > -#define WIN_NUM_1		1
> > > > -#define CFG_WINDOW_TYPE	0
> > > > -#define IO_WINDOW_TYPE		1
> > > > -#define MEM_WINDOW_TYPE	2
> > > > -#define IB_WIN_SIZE		((u64)256 * 1024 * 1024 * 1024)
> > > > -#define MAX_PIO_WINDOWS	8
> > > > +#define WIN_NUM_0			0
> > > > +#define WIN_NUM_1			1
> > > > +#define CFG_WINDOW_TYPE			0
> > > > +#define IO_WINDOW_TYPE			1
> > > > +#define MEM_WINDOW_TYPE			2
> > > > +#define IB_WIN_SIZE			((u64)256 * 1024 * 1024 * 1024)
> > > > +#define MAX_PIO_WINDOWS			8
> > > >
> > > >  /* Parameters for the waiting for link up routine */
> > > > -#define LINK_WAIT_MAX_RETRIES	10
> > > > -#define LINK_WAIT_MIN	90000
> > > > -#define LINK_WAIT_MAX	100000
> > > > +#define LINK_WAIT_MAX_RETRIES		10
> > > > +#define LINK_WAIT_MIN			90000
> > > > +#define LINK_WAIT_MAX			100000
> > > >
> > > > -#define PAGED_ADDR_BNDRY			0xc00
> > > > -#define OFFSET_TO_PAGE_ADDR(off)		\
> > > > +#define PAGED_ADDR_BNDRY		0xc00
> > > > +#define OFFSET_TO_PAGE_ADDR(off)	\
> > > >  	((off & PAGE_LO_MASK) | PAGED_ADDR_BNDRY)
> > > > -#define OFFSET_TO_PAGE_IDX(off)			\
> > > > +#define OFFSET_TO_PAGE_IDX(off)		\
> > > >  	((off >> PAGE_SEL_OFFSET_SHIFT) & PAGE_SEL_MASK)
> > > >
> > > >  struct mobiveil_msi {			/* MSI information */
> > > > @@ -297,14 +299,14 @@ static void __iomem
> > > *mobiveil_pcie_map_bus(struct pci_bus *bus,
> > > >  					unsigned int devfn, int where)  {
> > > >  	struct mobiveil_pcie *pcie = bus->sysdata;
> > > > +	u32 value;
> > > >
> > > >  	if (!mobiveil_pcie_valid_device(bus, devfn))
> > > >  		return NULL;
> > > >
> > > > -	if (bus->number == pcie->root_bus_nr) {
> > > > -		/* RC config access */
> > > > +	/* RC config access */
> > > > +	if (bus->number == pcie->root_bus_nr)
> > > >  		return pcie->csr_axi_slave_base + where;
> > > > -	}
> > > >
> > > >  	/*
> > > >  	 * EP config access (in Config/APIO space) @@ -312,10 +314,12
> @@
> > > > static void __iomem *mobiveil_pcie_map_bus(struct pci_bus *bus,
> > > >  	 * (BDF) in PAB_AXI_AMAP_PEX_WIN_L0 Register.
> > > >  	 * Relies on pci_lock serialization
> > > >  	 */
> > > > -	csr_writel(pcie, bus->number << PAB_BUS_SHIFT |
> > > > -			PCI_SLOT(devfn) << PAB_DEVICE_SHIFT |
> > > > -			PCI_FUNC(devfn) << PAB_FUNCTION_SHIFT,
> > > > -			PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0));
> > > > +	value = bus->number << PAB_BUS_SHIFT |
> > > > +		PCI_SLOT(devfn) << PAB_DEVICE_SHIFT |
> > > > +		PCI_FUNC(devfn) << PAB_FUNCTION_SHIFT;
> > > > +
> > > > +	csr_writel(pcie, value,
> PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0));
> > > > +
> > > >  	return pcie->config_axi_slave_base + where;  }
> > > >
> > > > @@ -350,22 +354,22 @@ static void mobiveil_pcie_isr(struct irq_desc
> > > > *desc)
> > > >
> > > >  	/* Handle INTx */
> > > >  	if (intr_status & PAB_INTP_INTX_MASK) {
> > > > -		shifted_status = csr_readl(pcie,
> PAB_INTP_AMBA_MISC_STAT) >>
> > > > -			PAB_INTX_START;
> > > > +		shifted_status = csr_readl(pcie,
> PAB_INTP_AMBA_MISC_STAT);
> > > > +		shifted_status >>= PAB_INTX_START;
> > > >  		do {
> > > >  			for_each_set_bit(bit, &shifted_status, PCI_NUM_INTX) {
> > > >  				virq = irq_find_mapping(pcie->intx_domain,
> > > > -						bit + 1);
> > > > +							bit + 1);
> > > >  				if (virq)
> > > >  					generic_handle_irq(virq);
> > > >  				else
> > > > -					dev_err_ratelimited(dev,
> > > > -						"unexpected IRQ, INT%d\n", bit);
> > > > +					dev_err_ratelimited(dev, "unexpected IRQ,
> > > INT%d\n",
> > > > +							    bit);
> > > >
> > > >  				/* clear interrupt */
> > > >  				csr_writel(pcie,
> > > > -					shifted_status << PAB_INTX_START,
> > > > -					PAB_INTP_AMBA_MISC_STAT);
> > > > +					   shifted_status << PAB_INTX_START,
> > > > +					   PAB_INTP_AMBA_MISC_STAT);
> > > >  			}
> > > >  		} while ((shifted_status >> PAB_INTX_START) != 0);
> > > >  	}
> > > > @@ -375,8 +379,7 @@ static void mobiveil_pcie_isr(struct irq_desc
> > > > *desc)
> > > >
> > > >  	/* handle MSI interrupts */
> > > >  	while (msi_status & 1) {
> > > > -		msi_data = readl_relaxed(pcie->apb_csr_base
> > > > -				+ MSI_DATA_OFFSET);
> > > > +		msi_data = readl_relaxed(pcie->apb_csr_base +
> > > MSI_DATA_OFFSET);
> > > >
> > > >  		/*
> > > >  		 * MSI_STATUS_OFFSET register gets updated to zero @@
> -385,18
> > > > +388,18 @@ static void mobiveil_pcie_isr(struct irq_desc *desc)
> > > >  		 * two dummy reads.
> > > >  		 */
> > > >  		msi_addr_lo = readl_relaxed(pcie->apb_csr_base +
> > > > -				MSI_ADDR_L_OFFSET);
> > > > +					    MSI_ADDR_L_OFFSET);
> > > >  		msi_addr_hi = readl_relaxed(pcie->apb_csr_base +
> > > > -				MSI_ADDR_H_OFFSET);
> > > > +					    MSI_ADDR_H_OFFSET);
> > > >  		dev_dbg(dev, "MSI registers, data: %08x, addr: %08x:%08x\n",
> > > > -				msi_data, msi_addr_hi, msi_addr_lo);
> > > > +			msi_data, msi_addr_hi, msi_addr_lo);
> > > >
> > > >  		virq = irq_find_mapping(msi->dev_domain, msi_data);
> > > >  		if (virq)
> > > >  			generic_handle_irq(virq);
> > > >
> > > >  		msi_status = readl_relaxed(pcie->apb_csr_base +
> > > > -				MSI_STATUS_OFFSET);
> > > > +					   MSI_STATUS_OFFSET);
> > > >  	}
> > > >
> > > >  	/* Clear the interrupt status */
> > > > @@ -413,7 +416,7 @@ static int mobiveil_pcie_parse_dt(struct
> > > > mobiveil_pcie *pcie)
> > > >
> > > >  	/* map config resource */
> > > >  	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> > > > -			"config_axi_slave");
> > > > +					   "config_axi_slave");
> > > >  	pcie->config_axi_slave_base =
> devm_pci_remap_cfg_resource(dev,
> > > res);
> > > >  	if (IS_ERR(pcie->config_axi_slave_base))
> > > >  		return PTR_ERR(pcie->config_axi_slave_base);
> > > > @@ -421,7 +424,7 @@ static int mobiveil_pcie_parse_dt(struct
> > > > mobiveil_pcie *pcie)
> > > >
> > > >  	/* map csr resource */
> > > >  	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> > > > -			"csr_axi_slave");
> > > > +					   "csr_axi_slave");
> > > >  	pcie->csr_axi_slave_base = devm_pci_remap_cfg_resource(dev,
> res);
> > > >  	if (IS_ERR(pcie->csr_axi_slave_base))
> > > >  		return PTR_ERR(pcie->csr_axi_slave_base);
> > > > @@ -452,7 +455,7 @@ static int mobiveil_pcie_parse_dt(struct
> > > > mobiveil_pcie *pcie)  }
> > > >
> > > >  static void program_ib_windows(struct mobiveil_pcie *pcie, int
> > > win_num,
> > > > -		int pci_addr, u32 type, u64 size)
> > > > +			       int pci_addr, u32 type, u64 size)
> > > >  {
> > > >  	int pio_ctrl_val;
> > > >  	int amap_ctrl_dw;
> > > > @@ -465,19 +468,20 @@ static void program_ib_windows(struct
> > > mobiveil_pcie *pcie, int win_num,
> > > >  	}
> > > >
> > > >  	pio_ctrl_val = csr_readl(pcie, PAB_PEX_PIO_CTRL);
> > > > -	csr_writel(pcie,
> > > > -		pio_ctrl_val | (1 << PIO_ENABLE_SHIFT), PAB_PEX_PIO_CTRL);
> > > > -	amap_ctrl_dw = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
> > > > -	amap_ctrl_dw = (amap_ctrl_dw | (type <<
> AMAP_CTRL_TYPE_SHIFT));
> > > > -	amap_ctrl_dw = (amap_ctrl_dw | (1 << AMAP_CTRL_EN_SHIFT));
> > > > +	pio_ctrl_val |= 1 << PIO_ENABLE_SHIFT;
> > > > +	csr_writel(pcie, pio_ctrl_val, PAB_PEX_PIO_CTRL);
> > > >
> > > > -	csr_writel(pcie, amap_ctrl_dw | lower_32_bits(size64),
> > > > -		   PAB_PEX_AMAP_CTRL(win_num));
> > > > +	amap_ctrl_dw = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
> > > > +	amap_ctrl_dw |= (type << AMAP_CTRL_TYPE_SHIFT) |
> > > > +			(1 << AMAP_CTRL_EN_SHIFT) |
> > > > +			lower_32_bits(size64);
> > > > +	csr_writel(pcie, amap_ctrl_dw, PAB_PEX_AMAP_CTRL(win_num));
> > > >
> > > >  	csr_writel(pcie, upper_32_bits(size64),
> > > >  		   PAB_EXT_PEX_AMAP_SIZEN(win_num));
> > > >
> > > >  	csr_writel(pcie, pci_addr, PAB_PEX_AMAP_AXI_WIN(win_num));
> > > > +
> > > >  	csr_writel(pcie, pci_addr, PAB_PEX_AMAP_PEX_WIN_L(win_num));
> > > >  	csr_writel(pcie, 0, PAB_PEX_AMAP_PEX_WIN_H(win_num));  }
> @@
> > > -486,7
> > > > +490,8 @@ static void program_ib_windows(struct mobiveil_pcie
> *pcie,
> > > int win_num,
> > > >   * routine to program the outbound windows
> > > >   */
> > > >  static void program_ob_windows(struct mobiveil_pcie *pcie, int
> > > win_num,
> > > > -		u64 cpu_addr, u64 pci_addr, u32 config_io_bit, u64 size)
> > > > +			       u64 cpu_addr, u64 pci_addr,
> > > > +			       u32 config_io_bit, u64 size)
> > > >  {
> > > >
> > > >  	u32 value, type;
> > > > @@ -505,7 +510,7 @@ static void program_ob_windows(struct
> > > mobiveil_pcie *pcie, int win_num,
> > > >  	type = config_io_bit;
> > > >  	value = csr_readl(pcie, PAB_AXI_AMAP_CTRL(win_num));
> > > >  	csr_writel(pcie, 1 << WIN_ENABLE_SHIFT | type <<
> WIN_TYPE_SHIFT |
> > > > -			lower_32_bits(size64), PAB_AXI_AMAP_CTRL(win_num));
> > > > +		   lower_32_bits(size64), PAB_AXI_AMAP_CTRL(win_num));
> > > >
> > > >  	csr_writel(pcie, upper_32_bits(size64),
> > > > PAB_EXT_AXI_AMAP_SIZE(win_num));
> > > >
> > > > @@ -515,14 +520,14 @@ static void program_ob_windows(struct
> > > mobiveil_pcie *pcie, int win_num,
> > > >  	 */
> > > >  	value = csr_readl(pcie, PAB_AXI_AMAP_AXI_WIN(win_num));
> > > >  	csr_writel(pcie, cpu_addr & (~AXI_WINDOW_ALIGN_MASK),
> > > > -			PAB_AXI_AMAP_AXI_WIN(win_num));
> > > > +		   PAB_AXI_AMAP_AXI_WIN(win_num));
> > > >
> > > >  	value = csr_readl(pcie, PAB_AXI_AMAP_PEX_WIN_H(win_num));
> > > >
> > > >  	csr_writel(pcie, lower_32_bits(pci_addr),
> > > > -			PAB_AXI_AMAP_PEX_WIN_L(win_num));
> > > > +		   PAB_AXI_AMAP_PEX_WIN_L(win_num));
> > > >  	csr_writel(pcie, upper_32_bits(pci_addr),
> > > > -			PAB_AXI_AMAP_PEX_WIN_H(win_num));
> > > > +		   PAB_AXI_AMAP_PEX_WIN_H(win_num));
> > > >
> > > >  	pcie->ob_wins_configured++;
> > > >  }
> > > > @@ -538,7 +543,9 @@ static int mobiveil_bringup_link(struct
> > > > mobiveil_pcie *pcie)
> > > >
> > > >  		usleep_range(LINK_WAIT_MIN, LINK_WAIT_MAX);
> > > >  	}
> > > > +
> > > >  	dev_err(&pcie->pdev->dev, "link never came up\n");
> > > > +
> > > >  	return -ETIMEDOUT;
> > > >  }
> > > >
> > > > @@ -551,16 +558,16 @@ static void mobiveil_pcie_enable_msi(struct
> > > mobiveil_pcie *pcie)
> > > >  	msi->msi_pages_phys = (phys_addr_t)msg_addr;
> > > >
> > > >  	writel_relaxed(lower_32_bits(msg_addr),
> > > > -		pcie->apb_csr_base + MSI_BASE_LO_OFFSET);
> > > > +		       pcie->apb_csr_base + MSI_BASE_LO_OFFSET);
> > > >  	writel_relaxed(upper_32_bits(msg_addr),
> > > > -		pcie->apb_csr_base + MSI_BASE_HI_OFFSET);
> > > > +		       pcie->apb_csr_base + MSI_BASE_HI_OFFSET);
> > > >  	writel_relaxed(4096, pcie->apb_csr_base + MSI_SIZE_OFFSET);
> > > >  	writel_relaxed(1, pcie->apb_csr_base + MSI_ENABLE_OFFSET);  }
> > > >
> > > >  static int mobiveil_host_init(struct mobiveil_pcie *pcie)  {
> > > > -	u32 value, pab_ctrl, type = 0;
> > > > +	u32 value, pab_ctrl, type;
> > > >  	int err;
> > > >  	struct resource_entry *win, *tmp;
> > > >
> > > > @@ -575,26 +582,27 @@ static int mobiveil_host_init(struct
> > > mobiveil_pcie *pcie)
> > > >  	 * Space
> > > >  	 */
> > > >  	value = csr_readl(pcie, PCI_COMMAND);
> > > > -	csr_writel(pcie, value | PCI_COMMAND_IO |
> > > PCI_COMMAND_MEMORY |
> > > > -		PCI_COMMAND_MASTER, PCI_COMMAND);
> > > > +	value |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
> > > PCI_COMMAND_MASTER;
> > > > +	csr_writel(pcie, value, PCI_COMMAND);
> > > >
> > > >  	/*
> > > >  	 * program PIO Enable Bit to 1 (and PEX PIO Enable to 1) in
> PAB_CTRL
> > > >  	 * register
> > > >  	 */
> > > >  	pab_ctrl = csr_readl(pcie, PAB_CTRL);
> > > > -	csr_writel(pcie, pab_ctrl | (1 << AMBA_PIO_ENABLE_SHIFT) |
> > > > -		(1 << PEX_PIO_ENABLE_SHIFT), PAB_CTRL);
> > > > +	pab_ctrl |= (1 << AMBA_PIO_ENABLE_SHIFT) | (1 <<
> > > PEX_PIO_ENABLE_SHIFT);
> > > > +	csr_writel(pcie, pab_ctrl, PAB_CTRL);
> > > >
> > > >  	csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK),
> > > > -		PAB_INTP_AMBA_MISC_ENB);
> > > > +		   PAB_INTP_AMBA_MISC_ENB);
> > > >
> > > >  	/*
> > > >  	 * program PIO Enable Bit to 1 and Config Window Enable Bit to 1
> in
> > > >  	 * PAB_AXI_PIO_CTRL Register
> > > >  	 */
> > > >  	value = csr_readl(pcie, PAB_AXI_PIO_CTRL);
> > > > -	csr_writel(pcie, value | APIO_EN_MASK, PAB_AXI_PIO_CTRL);
> > > > +	value |= APIO_EN_MASK;
> > > > +	csr_writel(pcie, value, PAB_AXI_PIO_CTRL);
> > > >
> > > >  	/*
> > > >  	 * we'll program one outbound window for config reads and @@
> > > -605,25
> > > > +613,25 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
> > > >
> > > >  	/* config outbound translation window */
> > > >  	program_ob_windows(pcie, pcie->ob_wins_configured,
> > > > -			pcie->ob_io_res->start, 0, CFG_WINDOW_TYPE,
> > > > -			resource_size(pcie->ob_io_res));
> > > > +			   pcie->ob_io_res->start, 0, CFG_WINDOW_TYPE,
> > > > +			   resource_size(pcie->ob_io_res));
> > > >
> > > >  	/* memory inbound translation window */
> > > >  	program_ib_windows(pcie, WIN_NUM_1, 0,
> MEM_WINDOW_TYPE,
> > > > IB_WIN_SIZE);
> > > >
> > > >  	/* Get the I/O and memory ranges from DT */
> > > >  	resource_list_for_each_entry_safe(win, tmp, &pcie->resources) {
> > > > -		type = 0;
> > > >  		if (resource_type(win->res) == IORESOURCE_MEM)
> > > >  			type = MEM_WINDOW_TYPE;
> > > > -		if (resource_type(win->res) == IORESOURCE_IO)
> > > > +		else if (resource_type(win->res) == IORESOURCE_IO)
> > > >  			type = IO_WINDOW_TYPE;
> > > > -		if (type) {
> > > > -			/* configure outbound translation window */
> > > > -			program_ob_windows(pcie, pcie->ob_wins_configured,
> > > > -				win->res->start, 0, type,
> > > > -				resource_size(win->res));
> > > > -		}
> > > > +		else
> > > > +			continue;
> > > > +
> > > > +		/* configure outbound translation window */
> > > > +		program_ob_windows(pcie, pcie->ob_wins_configured,
> > > > +				   win->res->start, 0, type,
> > > > +				   resource_size(win->res));
> > > >  	}
> > > >
> > > >  	/* setup MSI hardware registers */
> > > > @@ -643,7 +651,8 @@ static void mobiveil_mask_intx_irq(struct
> irq_data
> > > *data)
> > > >  	mask = 1 << ((data->hwirq + PAB_INTX_START) - 1);
> > > >  	raw_spin_lock_irqsave(&pcie->intx_mask_lock, flags);
> > > >  	shifted_val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
> > > > -	csr_writel(pcie, (shifted_val & (~mask)),
> PAB_INTP_AMBA_MISC_ENB);
> > > > +	shifted_val &= ~mask;
> > > > +	csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
> > > >  	raw_spin_unlock_irqrestore(&pcie->intx_mask_lock, flags);  }
> > > >
> > > > @@ -658,7 +667,8 @@ static void mobiveil_unmask_intx_irq(struct
> > > irq_data *data)
> > > >  	mask = 1 << ((data->hwirq + PAB_INTX_START) - 1);
> > > >  	raw_spin_lock_irqsave(&pcie->intx_mask_lock, flags);
> > > >  	shifted_val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
> > > > -	csr_writel(pcie, (shifted_val | mask),
> PAB_INTP_AMBA_MISC_ENB);
> > > > +	shifted_val |= mask;
> > > > +	csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
> > > >  	raw_spin_unlock_irqrestore(&pcie->intx_mask_lock, flags);  }
> > > >
> > > > @@ -672,10 +682,11 @@ static struct irq_chip intx_irq_chip = {
> > > >
> > > >  /* routine to setup the INTx related data */  static int
> > > > mobiveil_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
> > > > -		irq_hw_number_t hwirq)
> > > > +				  irq_hw_number_t hwirq)
> > > >  {
> > > >  	irq_set_chip_and_handler(irq, &intx_irq_chip, handle_level_irq);
> > > >  	irq_set_chip_data(irq, domain->host_data);
> > > > +
> > > >  	return 0;
> > > >  }
> > > >
> > > > @@ -692,7 +703,7 @@ static struct irq_chip mobiveil_msi_irq_chip = {
> > > >
> > > >  static struct msi_domain_info mobiveil_msi_domain_info = {
> > > >  	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS |
> > > MSI_FLAG_USE_DEF_CHIP_OPS |
> > > > -		MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX),
> > > > +		   MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX),
> > > >  	.chip	= &mobiveil_msi_irq_chip,
> > > >  };
> > > >
> > > > @@ -710,7 +721,7 @@ static void mobiveil_compose_msi_msg(struct
> > > > irq_data *data, struct msi_msg *msg)  }
> > > >
> > > >  static int mobiveil_msi_set_affinity(struct irq_data *irq_data,
> > > > -		const struct cpumask *mask, bool force)
> > > > +				     const struct cpumask *mask, bool force)
> > > >  {
> > > >  	return -EINVAL;
> > > >  }
> > > > @@ -722,7 +733,8 @@ static struct irq_chip
> > > > mobiveil_msi_bottom_irq_chip = {  };
> > > >
> > > >  static int mobiveil_irq_msi_domain_alloc(struct irq_domain *domain,
> > > > -		unsigned int virq, unsigned int nr_irqs, void *args)
> > > > +					 unsigned int virq,
> > > > +					 unsigned int nr_irqs, void *args)
> > > >  {
> > > >  	struct mobiveil_pcie *pcie = domain->host_data;
> > > >  	struct mobiveil_msi *msi = &pcie->msi; @@ -742,13 +754,13 @@
> static
> > > > int mobiveil_irq_msi_domain_alloc(struct irq_domain *domain,
> > > >  	mutex_unlock(&msi->lock);
> > > >
> > > >  	irq_domain_set_info(domain, virq, bit,
> > > &mobiveil_msi_bottom_irq_chip,
> > > > -				domain->host_data, handle_level_irq,
> > > > -				NULL, NULL);
> > > > +			    domain->host_data, handle_level_irq, NULL, NULL);
> > > >  	return 0;
> > > >  }
> > > >
> > > >  static void mobiveil_irq_msi_domain_free(struct irq_domain
> *domain,
> > > > -		unsigned int virq, unsigned int nr_irqs)
> > > > +					 unsigned int virq,
> > > > +					 unsigned int nr_irqs)
> > > >  {
> > > >  	struct irq_data *d = irq_domain_get_irq_data(domain, virq);
> > > >  	struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(d); @@
> > > > -756,12 +768,11 @@ static void mobiveil_irq_msi_domain_free(struct
> > > > irq_domain *domain,
> > > >
> > > >  	mutex_lock(&msi->lock);
> > > >
> > > > -	if (!test_bit(d->hwirq, msi->msi_irq_in_use)) {
> > > > +	if (!test_bit(d->hwirq, msi->msi_irq_in_use))
> > > >  		dev_err(&pcie->pdev->dev, "trying to free unused
> MSI#%lu\n",
> > > >  			d->hwirq);
> > > > -	} else {
> > > > +	else
> > > >  		__clear_bit(d->hwirq, msi->msi_irq_in_use);
> > > > -	}
> > > >
> > > >  	mutex_unlock(&msi->lock);
> > > >  }
> > > > @@ -785,12 +796,14 @@ static int
> mobiveil_allocate_msi_domains(struct
> > > mobiveil_pcie *pcie)
> > > >  	}
> > > >
> > > >  	msi->msi_domain = pci_msi_create_irq_domain(fwnode,
> > > > -				&mobiveil_msi_domain_info, msi->dev_domain);
> > > > +						    &mobiveil_msi_domain_info,
> > > > +						    msi->dev_domain);
> > > >  	if (!msi->msi_domain) {
> > > >  		dev_err(dev, "failed to create MSI domain\n");
> > > >  		irq_domain_remove(msi->dev_domain);
> > > >  		return -ENOMEM;
> > > >  	}
> > > > +
> > > >  	return 0;
> > > >  }
> > > >
> > > > @@ -801,8 +814,8 @@ static int mobiveil_pcie_init_irq_domain(struct
> > > mobiveil_pcie *pcie)
> > > >  	int ret;
> > > >
> > > >  	/* setup INTx */
> > > > -	pcie->intx_domain = irq_domain_add_linear(node,
> > > > -				PCI_NUM_INTX, &intx_domain_ops, pcie);
> > > > +	pcie->intx_domain = irq_domain_add_linear(node,
> PCI_NUM_INTX,
> > > > +						  &intx_domain_ops, pcie);
> > > >
> > > >  	if (!pcie->intx_domain) {
> > > >  		dev_err(dev, "Failed to get a INTx IRQ domain\n"); @@
> -917,10
> > > > +930,10 @@ MODULE_DEVICE_TABLE(of, mobiveil_pcie_of_match);
> > > static
> > > > struct platform_driver mobiveil_pcie_driver = {
> > > >  	.probe = mobiveil_pcie_probe,
> > > >  	.driver = {
> > > > -			.name = "mobiveil-pcie",
> > > > -			.of_match_table = mobiveil_pcie_of_match,
> > > > -			.suppress_bind_attrs = true,
> > > > -		},
> > > > +		.name = "mobiveil-pcie",
> > > > +		.of_match_table = mobiveil_pcie_of_match,
> > > > +		.suppress_bind_attrs = true,
> > > > +	},
> > > >  };
> > > >
> > > >  builtin_platform_driver(mobiveil_pcie_driver);
> > > > --
> > > > 2.17.1
> > > >

^ permalink raw reply	[flat|nested] 67+ messages in thread

end of thread, back to index

Thread overview: 67+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-04-12  8:35 [PATCHv5 00/20] PCI: mobiveil: fixes for Mobiveil PCIe Host Bridge IP driver Z.q. Hou
2019-04-12  8:35 ` [PATCHv5 01/20] PCI: mobiveil: Unify register accessors Z.q. Hou
2019-04-12  8:35 ` [PATCHv5 02/20] PCI: mobiveil: Format the code without functionality change Z.q. Hou
2019-07-03 15:10   ` Lorenzo Pieralisi
2019-07-04  2:41     ` Z.q. Hou
2019-07-03 15:19   ` Lorenzo Pieralisi
2019-07-03 15:24     ` Lorenzo Pieralisi
2019-07-04  3:00     ` Z.q. Hou
2019-07-04 10:56       ` Lorenzo Pieralisi
2019-07-05  2:24         ` Z.q. Hou
2019-04-12  8:35 ` [PATCHv5 03/20] PCI: mobiveil: Correct the returned error number Z.q. Hou
2019-07-03 14:17   ` Lorenzo Pieralisi
2019-07-04  2:38     ` Z.q. Hou
2019-04-12  8:35 ` [PATCHv5 04/20] PCI: mobiveil: Remove the flag MSI_FLAG_MULTI_PCI_MSI Z.q. Hou
2019-06-11 16:59   ` Lorenzo Pieralisi
2019-06-11 17:29     ` Marc Zyngier
2019-06-12 10:54       ` Lorenzo Pieralisi
2019-06-12 11:22       ` Marc Zyngier
2019-06-12 11:34     ` Z.q. Hou
2019-06-12 13:08       ` Lorenzo Pieralisi
2019-06-15  1:30         ` Z.q. Hou
2019-06-17  9:33           ` Lorenzo Pieralisi
2019-06-17 10:34             ` Z.q. Hou
2019-06-28 11:35               ` Lorenzo Pieralisi
2019-07-01 10:07                 ` Z.q. Hou
2019-04-12  8:35 ` [PATCHv5 05/20] PCI: mobiveil: Correct PCI base address in MEM/IO outbound windows Z.q. Hou
2019-04-12  8:35 ` [PATCHv5 06/20] PCI: mobiveil: Replace the resource list iteration function Z.q. Hou
2019-04-12  8:35 ` [PATCHv5 07/20] PCI: mobiveil: Use WIN_NUM_0 explicitly for CFG outbound window Z.q. Hou
2019-06-12 15:13   ` Lorenzo Pieralisi
2019-04-12  8:36 ` [PATCHv5 08/20] PCI: mobiveil: Use the 1st inbound window for MEM inbound transactions Z.q. Hou
2019-06-28 16:02   ` Lorenzo Pieralisi
2019-07-01 10:18     ` Z.q. Hou
2019-04-12  8:36 ` [PATCHv5 09/20] PCI: mobiveil: Correct inbound/outbound window setup routines Z.q. Hou
2019-06-28 16:41   ` Lorenzo Pieralisi
2019-07-01 10:24     ` Z.q. Hou
2019-04-12  8:36 ` [PATCHv5 10/20] PCI: mobiveil: Fix the INTx process errors Z.q. Hou
2019-06-12 15:08   ` Lorenzo Pieralisi
2019-06-14  7:08     ` Karthikeyan Mitran
2019-06-14 10:43       ` Lorenzo Pieralisi
2019-06-19  5:28         ` Karthikeyan Mitran
2019-06-19  7:24           ` Z.q. Hou
2019-06-28 17:05   ` Lorenzo Pieralisi
2019-07-01 10:27     ` Z.q. Hou
2019-04-12  8:36 ` [PATCHv5 11/20] PCI: mobiveil: Correct the fixup of Class Code field Z.q. Hou
2019-04-12  8:36 ` [PATCHv5 12/20] PCI: mobiveil: Move the link up waiting out of mobiveil_host_init() Z.q. Hou
2019-04-12  8:36 ` [PATCHv5 13/20] PCI: mobiveil: Move IRQ chained handler setup out of DT parse Z.q. Hou
2019-04-12  8:36 ` [PATCHv5 14/20] PCI: mobiveil: Initialize Primary/Secondary/Subordinate bus numbers Z.q. Hou
2019-04-12  8:36 ` [PATCHv5 15/20] PCI: mobiveil: Fix the checking of valid device Z.q. Hou
2019-04-12  8:36 ` [PATCHv5 16/20] PCI: mobiveil: Add link up condition check Z.q. Hou
2019-06-11 17:17   ` Lorenzo Pieralisi
2019-06-12 11:36     ` Z.q. Hou
2019-04-12  8:36 ` [PATCHv5 17/20] PCI: mobiveil: Complete initialization of host even if no PCIe link Z.q. Hou
2019-06-12 14:34   ` Lorenzo Pieralisi
2019-06-15  2:34     ` Z.q. Hou
2019-04-12  8:37 ` [PATCHv5 18/20] PCI: mobiveil: Disable IB and OB windows set by bootloader Z.q. Hou
2019-06-12 16:23   ` Lorenzo Pieralisi
2019-06-15  5:03     ` Z.q. Hou
2019-06-17  9:30       ` Lorenzo Pieralisi
2019-06-17 10:42         ` Z.q. Hou
2019-04-12  8:37 ` [PATCHv5 19/20] PCI: mobiveil: Add 8-bit and 16-bit register accessors Z.q. Hou
2019-06-12 13:54   ` Lorenzo Pieralisi
2019-06-15  1:13     ` Z.q. Hou
2019-06-17  9:29       ` Lorenzo Pieralisi
2019-06-17 10:16         ` Z.q. Hou
2019-04-12  8:37 ` [PATCHv5 20/20] dt-bindings: PCI: mobiveil: Change gpio_slave and apb_csr to optional Z.q. Hou
2019-07-03 10:33 ` [PATCHv5 00/20] PCI: mobiveil: fixes for Mobiveil PCIe Host Bridge IP driver Lorenzo Pieralisi
2019-07-04  2:36   ` Z.q. Hou

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