* [PATCH 01/17] dt-bindings: spi: Convert DW SPI binding to DT schema
2020-05-08 13:29 [PATCH 00/17] spi: dw: Add generic DW DMA controller support Serge Semin
@ 2020-05-08 13:29 ` Serge Semin
2020-05-08 19:39 ` Andy Shevchenko
2020-05-08 13:29 ` [PATCH 02/17] dt-bindings: spi: dw: Add DMA properties bindings Serge Semin
` (18 subsequent siblings)
19 siblings, 1 reply; 106+ messages in thread
From: Serge Semin @ 2020-05-08 13:29 UTC (permalink / raw)
To: Mark Brown, Rob Herring
Cc: Serge Semin, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Arnd Bergmann, Allison Randal, Andy Shevchenko, Gareth Williams,
linux-mips, linux-spi, devicetree, linux-kernel
Modern device tree bindings are supposed to be created as YAML-files
in accordance with dt-schema. This commit replaces two DW SPI legacy
bare text bindings with YAML file. As before the bindings file states
that the corresponding dts node is supposed to be compatible either
with generic DW APB SSI controller or with Microsemi/Amazon/Renesas
vendors-specific controllers, to have registers, interrupts and clocks
properties. Though in case of Microsemi version of the controller
there must be two registers resources specified. Properties like
clock-names, reg-io-width, cs-gpio, num-cs and SPI-specific sub-nodes
are optional.
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
Cc: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Allison Randal <allison@lohutok.net>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Gareth Williams <gareth.williams.jx@renesas.com>
Cc: linux-mips@vger.kernel.org
---
.../bindings/spi/snps,dw-apb-ssi.txt | 41 -------
.../bindings/spi/snps,dw-apb-ssi.yaml | 113 ++++++++++++++++++
.../devicetree/bindings/spi/spi-dw.txt | 24 ----
3 files changed, 113 insertions(+), 65 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
create mode 100644 Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
delete mode 100644 Documentation/devicetree/bindings/spi/spi-dw.txt
diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
deleted file mode 100644
index 3ed08ee9feba..000000000000
--- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
+++ /dev/null
@@ -1,41 +0,0 @@
-Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface.
-
-Required properties:
-- compatible : "snps,dw-apb-ssi" or "mscc,<soc>-spi", where soc is "ocelot" or
- "jaguar2", or "amazon,alpine-dw-apb-ssi"
-- reg : The register base for the controller. For "mscc,<soc>-spi", a second
- register set is required (named ICPU_CFG:SPI_MST)
-- interrupts : One interrupt, used by the controller.
-- #address-cells : <1>, as required by generic SPI binding.
-- #size-cells : <0>, also as required by generic SPI binding.
-- clocks : phandles for the clocks, see the description of clock-names below.
- The phandle for the "ssi_clk" is required. The phandle for the "pclk" clock
- is optional. If a single clock is specified but no clock-name, it is the
- "ssi_clk" clock. If both clocks are listed, the "ssi_clk" must be first.
-
-Optional properties:
-- clock-names : Contains the names of the clocks:
- "ssi_clk", for the core clock used to generate the external SPI clock.
- "pclk", the interface clock, required for register access. If a clock domain
- used to enable this clock then it should be named "pclk_clkdomain".
-- cs-gpios : Specifies the gpio pins to be used for chipselects.
-- num-cs : The number of chipselects. If omitted, this will default to 4.
-- reg-io-width : The I/O register width (in bytes) implemented by this
- device. Supported values are 2 or 4 (the default).
-
-Child nodes as per the generic SPI binding.
-
-Example:
-
- spi@fff00000 {
- compatible = "snps,dw-apb-ssi";
- reg = <0xfff00000 0x1000>;
- interrupts = <0 154 4>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&spi_m_clk>;
- num-cs = <2>;
- cs-gpios = <&gpio0 13 0>,
- <&gpio0 14 0>;
- };
-
diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
new file mode 100644
index 000000000000..e2f6d8aa6181
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
@@ -0,0 +1,113 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface
+
+maintainers:
+ - Mark Brown <broonie@kernel.org>
+
+allOf:
+ - $ref: "spi-controller.yaml#"
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - mscc,ocelot-spi
+ - mscc,jaguar2-spi
+ then:
+ properties:
+ reg:
+ minItems: 2
+
+properties:
+ compatible:
+ oneOf:
+ - description: Generic DW SPI controller
+ const: snps,dw-apb-ssi
+ - description: Microsemi Ocelot/Jaguar2 SoC SPI controller
+ items:
+ - enum:
+ - mscc,ocelot-spi
+ - mscc,jaguar2-spi
+ - const: snps,dw-apb-ssi
+ - description: Amazon Alpine SPI controller
+ const: amazon,alpine-dw-apb-ssi
+ - description: Renesas RZ/N1 SPI controlle.
+ items:
+ - const: renesas,rzn1-spi
+ - const: snps,dw-apb-ssi
+
+ reg:
+ minItems: 1
+ items:
+ - description: DW APB SSI controller memory mapped registers
+ - description: SPI MST region map
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ items:
+ - description: SPI Controller reference clock source
+ - description: APB interface clock source
+
+ clock-names:
+ minItems: 1
+ items:
+ - const: ssi_clk
+ - const: pclk
+
+ reg-io-width:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: I/O register width (in bytes) implemented by this device
+ default: 4
+ enum: [ 2, 4 ]
+
+ num-cs:
+ default: 4
+ minimum: 1
+ maximum: 4
+
+patternProperties:
+ "^.*@[0-9a-f]+$":
+ type: object
+ properties:
+ reg:
+ minimum: 0
+ maximum: 3
+
+ spi-rx-bus-width:
+ const: 1
+
+ spi-tx-bus-width:
+ const: 1
+
+unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+ - interrupts
+ - clocks
+
+examples:
+ - |
+ spi@fff00000 {
+ compatible = "snps,dw-apb-ssi";
+ reg = <0xfff00000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 154 4>;
+ clocks = <&spi_m_clk>;
+ num-cs = <2>;
+ cs-gpios = <&gpio0 13 0>,
+ <&gpio0 14 0>;
+ };
+...
diff --git a/Documentation/devicetree/bindings/spi/spi-dw.txt b/Documentation/devicetree/bindings/spi/spi-dw.txt
deleted file mode 100644
index 7b63ed601990..000000000000
--- a/Documentation/devicetree/bindings/spi/spi-dw.txt
+++ /dev/null
@@ -1,24 +0,0 @@
-Synopsys DesignWare SPI master
-
-Required properties:
-- compatible: should be "snps,designware-spi"
-- #address-cells: see spi-bus.txt
-- #size-cells: see spi-bus.txt
-- reg: address and length of the spi master registers
-- interrupts: should contain one interrupt
-- clocks: spi clock phandle
-- num-cs: see spi-bus.txt
-
-Optional properties:
-- cs-gpios: see spi-bus.txt
-
-Example:
-
-spi: spi@4020a000 {
- compatible = "snps,designware-spi";
- interrupts = <11 1>;
- reg = <0x4020a000 0x1000>;
- clocks = <&pclk>;
- num-cs = <2>;
- cs-gpios = <&banka 0 0>;
-};
--
2.25.1
^ permalink raw reply related [flat|nested] 106+ messages in thread
* Re: [PATCH 01/17] dt-bindings: spi: Convert DW SPI binding to DT schema
2020-05-08 13:29 ` [PATCH 01/17] dt-bindings: spi: Convert DW SPI binding to DT schema Serge Semin
@ 2020-05-08 19:39 ` Andy Shevchenko
2020-05-12 20:28 ` Serge Semin
0 siblings, 1 reply; 106+ messages in thread
From: Andy Shevchenko @ 2020-05-08 19:39 UTC (permalink / raw)
To: Serge Semin
Cc: Mark Brown, Rob Herring, Serge Semin, Georgy Vlasov,
Ramil Zaripov, Alexey Malahov, Thomas Bogendoerfer, Paul Burton,
Ralf Baechle, Arnd Bergmann, Allison Randal, Gareth Williams,
linux-mips, linux-spi, devicetree, linux-kernel
On Fri, May 08, 2020 at 04:29:26PM +0300, Serge Semin wrote:
> Modern device tree bindings are supposed to be created as YAML-files
> in accordance with dt-schema. This commit replaces two DW SPI legacy
> bare text bindings with YAML file. As before the bindings file states
> that the corresponding dts node is supposed to be compatible either
> with generic DW APB SSI controller or with Microsemi/Amazon/Renesas
> vendors-specific controllers, to have registers, interrupts and clocks
> properties. Though in case of Microsemi version of the controller
> there must be two registers resources specified. Properties like
> clock-names, reg-io-width, cs-gpio, num-cs and SPI-specific sub-nodes
> are optional.
Can you incorporate work done here or agree with Wan how to proceed?
https://lore.kernel.org/linux-spi/20200505191910.GA2970@bogus/T/#md626b5f6f2294b0ebd70995d5ed0e67a360e000b
>
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Cc: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
> Cc: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> Cc: Paul Burton <paulburton@kernel.org>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Allison Randal <allison@lohutok.net>
> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Cc: Gareth Williams <gareth.williams.jx@renesas.com>
> Cc: linux-mips@vger.kernel.org
> ---
> .../bindings/spi/snps,dw-apb-ssi.txt | 41 -------
> .../bindings/spi/snps,dw-apb-ssi.yaml | 113 ++++++++++++++++++
> .../devicetree/bindings/spi/spi-dw.txt | 24 ----
> 3 files changed, 113 insertions(+), 65 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
> create mode 100644 Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> delete mode 100644 Documentation/devicetree/bindings/spi/spi-dw.txt
>
> diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
> deleted file mode 100644
> index 3ed08ee9feba..000000000000
> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
> +++ /dev/null
> @@ -1,41 +0,0 @@
> -Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface.
> -
> -Required properties:
> -- compatible : "snps,dw-apb-ssi" or "mscc,<soc>-spi", where soc is "ocelot" or
> - "jaguar2", or "amazon,alpine-dw-apb-ssi"
> -- reg : The register base for the controller. For "mscc,<soc>-spi", a second
> - register set is required (named ICPU_CFG:SPI_MST)
> -- interrupts : One interrupt, used by the controller.
> -- #address-cells : <1>, as required by generic SPI binding.
> -- #size-cells : <0>, also as required by generic SPI binding.
> -- clocks : phandles for the clocks, see the description of clock-names below.
> - The phandle for the "ssi_clk" is required. The phandle for the "pclk" clock
> - is optional. If a single clock is specified but no clock-name, it is the
> - "ssi_clk" clock. If both clocks are listed, the "ssi_clk" must be first.
> -
> -Optional properties:
> -- clock-names : Contains the names of the clocks:
> - "ssi_clk", for the core clock used to generate the external SPI clock.
> - "pclk", the interface clock, required for register access. If a clock domain
> - used to enable this clock then it should be named "pclk_clkdomain".
> -- cs-gpios : Specifies the gpio pins to be used for chipselects.
> -- num-cs : The number of chipselects. If omitted, this will default to 4.
> -- reg-io-width : The I/O register width (in bytes) implemented by this
> - device. Supported values are 2 or 4 (the default).
> -
> -Child nodes as per the generic SPI binding.
> -
> -Example:
> -
> - spi@fff00000 {
> - compatible = "snps,dw-apb-ssi";
> - reg = <0xfff00000 0x1000>;
> - interrupts = <0 154 4>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - clocks = <&spi_m_clk>;
> - num-cs = <2>;
> - cs-gpios = <&gpio0 13 0>,
> - <&gpio0 14 0>;
> - };
> -
> diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> new file mode 100644
> index 000000000000..e2f6d8aa6181
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> @@ -0,0 +1,113 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface
> +
> +maintainers:
> + - Mark Brown <broonie@kernel.org>
> +
> +allOf:
> + - $ref: "spi-controller.yaml#"
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - mscc,ocelot-spi
> + - mscc,jaguar2-spi
> + then:
> + properties:
> + reg:
> + minItems: 2
> +
> +properties:
> + compatible:
> + oneOf:
> + - description: Generic DW SPI controller
> + const: snps,dw-apb-ssi
> + - description: Microsemi Ocelot/Jaguar2 SoC SPI controller
> + items:
> + - enum:
> + - mscc,ocelot-spi
> + - mscc,jaguar2-spi
> + - const: snps,dw-apb-ssi
> + - description: Amazon Alpine SPI controller
> + const: amazon,alpine-dw-apb-ssi
> + - description: Renesas RZ/N1 SPI controlle.
> + items:
> + - const: renesas,rzn1-spi
> + - const: snps,dw-apb-ssi
> +
> + reg:
> + minItems: 1
> + items:
> + - description: DW APB SSI controller memory mapped registers
> + - description: SPI MST region map
> +
> + interrupts:
> + maxItems: 1
> +
> + clocks:
> + minItems: 1
> + items:
> + - description: SPI Controller reference clock source
> + - description: APB interface clock source
> +
> + clock-names:
> + minItems: 1
> + items:
> + - const: ssi_clk
> + - const: pclk
> +
> + reg-io-width:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: I/O register width (in bytes) implemented by this device
> + default: 4
> + enum: [ 2, 4 ]
> +
> + num-cs:
> + default: 4
> + minimum: 1
> + maximum: 4
> +
> +patternProperties:
> + "^.*@[0-9a-f]+$":
> + type: object
> + properties:
> + reg:
> + minimum: 0
> + maximum: 3
> +
> + spi-rx-bus-width:
> + const: 1
> +
> + spi-tx-bus-width:
> + const: 1
> +
> +unevaluatedProperties: false
> +
> +required:
> + - compatible
> + - reg
> + - "#address-cells"
> + - "#size-cells"
> + - interrupts
> + - clocks
> +
> +examples:
> + - |
> + spi@fff00000 {
> + compatible = "snps,dw-apb-ssi";
> + reg = <0xfff00000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <0 154 4>;
> + clocks = <&spi_m_clk>;
> + num-cs = <2>;
> + cs-gpios = <&gpio0 13 0>,
> + <&gpio0 14 0>;
> + };
> +...
> diff --git a/Documentation/devicetree/bindings/spi/spi-dw.txt b/Documentation/devicetree/bindings/spi/spi-dw.txt
> deleted file mode 100644
> index 7b63ed601990..000000000000
> --- a/Documentation/devicetree/bindings/spi/spi-dw.txt
> +++ /dev/null
> @@ -1,24 +0,0 @@
> -Synopsys DesignWare SPI master
> -
> -Required properties:
> -- compatible: should be "snps,designware-spi"
> -- #address-cells: see spi-bus.txt
> -- #size-cells: see spi-bus.txt
> -- reg: address and length of the spi master registers
> -- interrupts: should contain one interrupt
> -- clocks: spi clock phandle
> -- num-cs: see spi-bus.txt
> -
> -Optional properties:
> -- cs-gpios: see spi-bus.txt
> -
> -Example:
> -
> -spi: spi@4020a000 {
> - compatible = "snps,designware-spi";
> - interrupts = <11 1>;
> - reg = <0x4020a000 0x1000>;
> - clocks = <&pclk>;
> - num-cs = <2>;
> - cs-gpios = <&banka 0 0>;
> -};
> --
> 2.25.1
>
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH 01/17] dt-bindings: spi: Convert DW SPI binding to DT schema
2020-05-08 19:39 ` Andy Shevchenko
@ 2020-05-12 20:28 ` Serge Semin
2020-05-12 20:35 ` Andy Shevchenko
0 siblings, 1 reply; 106+ messages in thread
From: Serge Semin @ 2020-05-12 20:28 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Serge Semin, Wan Ahmad Zainie, Mark Brown, Rob Herring,
Georgy Vlasov, Ramil Zaripov, Alexey Malahov,
Thomas Bogendoerfer, Paul Burton, Ralf Baechle, Arnd Bergmann,
Allison Randal, Gareth Williams, linux-mips, linux-spi,
devicetree, linux-kernel
+Cc: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
On Fri, May 08, 2020 at 10:39:34PM +0300, Andy Shevchenko wrote:
> On Fri, May 08, 2020 at 04:29:26PM +0300, Serge Semin wrote:
> > Modern device tree bindings are supposed to be created as YAML-files
> > in accordance with dt-schema. This commit replaces two DW SPI legacy
> > bare text bindings with YAML file. As before the bindings file states
> > that the corresponding dts node is supposed to be compatible either
> > with generic DW APB SSI controller or with Microsemi/Amazon/Renesas
> > vendors-specific controllers, to have registers, interrupts and clocks
> > properties. Though in case of Microsemi version of the controller
> > there must be two registers resources specified. Properties like
> > clock-names, reg-io-width, cs-gpio, num-cs and SPI-specific sub-nodes
> > are optional.
>
> Can you incorporate work done here or agree with Wan how to proceed?
>
> https://lore.kernel.org/linux-spi/20200505191910.GA2970@bogus/T/#md626b5f6f2294b0ebd70995d5ed0e67a360e000b
Don't worry. I'll make sure the updates provided by Wan including the new IP
support are preserved after rebasing this series on top of the spi/for-next.
-Sergey
>
> >
> > Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> > Cc: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
> > Cc: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
> > Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> > Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> > Cc: Paul Burton <paulburton@kernel.org>
> > Cc: Ralf Baechle <ralf@linux-mips.org>
> > Cc: Arnd Bergmann <arnd@arndb.de>
> > Cc: Allison Randal <allison@lohutok.net>
> > Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> > Cc: Gareth Williams <gareth.williams.jx@renesas.com>
> > Cc: linux-mips@vger.kernel.org
> > ---
> > .../bindings/spi/snps,dw-apb-ssi.txt | 41 -------
> > .../bindings/spi/snps,dw-apb-ssi.yaml | 113 ++++++++++++++++++
> > .../devicetree/bindings/spi/spi-dw.txt | 24 ----
> > 3 files changed, 113 insertions(+), 65 deletions(-)
> > delete mode 100644 Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
> > create mode 100644 Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> > delete mode 100644 Documentation/devicetree/bindings/spi/spi-dw.txt
> >
> > diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
> > deleted file mode 100644
> > index 3ed08ee9feba..000000000000
> > --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
> > +++ /dev/null
> > @@ -1,41 +0,0 @@
> > -Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface.
> > -
> > -Required properties:
> > -- compatible : "snps,dw-apb-ssi" or "mscc,<soc>-spi", where soc is "ocelot" or
> > - "jaguar2", or "amazon,alpine-dw-apb-ssi"
> > -- reg : The register base for the controller. For "mscc,<soc>-spi", a second
> > - register set is required (named ICPU_CFG:SPI_MST)
> > -- interrupts : One interrupt, used by the controller.
> > -- #address-cells : <1>, as required by generic SPI binding.
> > -- #size-cells : <0>, also as required by generic SPI binding.
> > -- clocks : phandles for the clocks, see the description of clock-names below.
> > - The phandle for the "ssi_clk" is required. The phandle for the "pclk" clock
> > - is optional. If a single clock is specified but no clock-name, it is the
> > - "ssi_clk" clock. If both clocks are listed, the "ssi_clk" must be first.
> > -
> > -Optional properties:
> > -- clock-names : Contains the names of the clocks:
> > - "ssi_clk", for the core clock used to generate the external SPI clock.
> > - "pclk", the interface clock, required for register access. If a clock domain
> > - used to enable this clock then it should be named "pclk_clkdomain".
> > -- cs-gpios : Specifies the gpio pins to be used for chipselects.
> > -- num-cs : The number of chipselects. If omitted, this will default to 4.
> > -- reg-io-width : The I/O register width (in bytes) implemented by this
> > - device. Supported values are 2 or 4 (the default).
> > -
> > -Child nodes as per the generic SPI binding.
> > -
> > -Example:
> > -
> > - spi@fff00000 {
> > - compatible = "snps,dw-apb-ssi";
> > - reg = <0xfff00000 0x1000>;
> > - interrupts = <0 154 4>;
> > - #address-cells = <1>;
> > - #size-cells = <0>;
> > - clocks = <&spi_m_clk>;
> > - num-cs = <2>;
> > - cs-gpios = <&gpio0 13 0>,
> > - <&gpio0 14 0>;
> > - };
> > -
> > diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> > new file mode 100644
> > index 000000000000..e2f6d8aa6181
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> > @@ -0,0 +1,113 @@
> > +# SPDX-License-Identifier: GPL-2.0-only
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface
> > +
> > +maintainers:
> > + - Mark Brown <broonie@kernel.org>
> > +
> > +allOf:
> > + - $ref: "spi-controller.yaml#"
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + enum:
> > + - mscc,ocelot-spi
> > + - mscc,jaguar2-spi
> > + then:
> > + properties:
> > + reg:
> > + minItems: 2
> > +
> > +properties:
> > + compatible:
> > + oneOf:
> > + - description: Generic DW SPI controller
> > + const: snps,dw-apb-ssi
> > + - description: Microsemi Ocelot/Jaguar2 SoC SPI controller
> > + items:
> > + - enum:
> > + - mscc,ocelot-spi
> > + - mscc,jaguar2-spi
> > + - const: snps,dw-apb-ssi
> > + - description: Amazon Alpine SPI controller
> > + const: amazon,alpine-dw-apb-ssi
> > + - description: Renesas RZ/N1 SPI controlle.
> > + items:
> > + - const: renesas,rzn1-spi
> > + - const: snps,dw-apb-ssi
> > +
> > + reg:
> > + minItems: 1
> > + items:
> > + - description: DW APB SSI controller memory mapped registers
> > + - description: SPI MST region map
> > +
> > + interrupts:
> > + maxItems: 1
> > +
> > + clocks:
> > + minItems: 1
> > + items:
> > + - description: SPI Controller reference clock source
> > + - description: APB interface clock source
> > +
> > + clock-names:
> > + minItems: 1
> > + items:
> > + - const: ssi_clk
> > + - const: pclk
> > +
> > + reg-io-width:
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + description: I/O register width (in bytes) implemented by this device
> > + default: 4
> > + enum: [ 2, 4 ]
> > +
> > + num-cs:
> > + default: 4
> > + minimum: 1
> > + maximum: 4
> > +
> > +patternProperties:
> > + "^.*@[0-9a-f]+$":
> > + type: object
> > + properties:
> > + reg:
> > + minimum: 0
> > + maximum: 3
> > +
> > + spi-rx-bus-width:
> > + const: 1
> > +
> > + spi-tx-bus-width:
> > + const: 1
> > +
> > +unevaluatedProperties: false
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - "#address-cells"
> > + - "#size-cells"
> > + - interrupts
> > + - clocks
> > +
> > +examples:
> > + - |
> > + spi@fff00000 {
> > + compatible = "snps,dw-apb-ssi";
> > + reg = <0xfff00000 0x1000>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + interrupts = <0 154 4>;
> > + clocks = <&spi_m_clk>;
> > + num-cs = <2>;
> > + cs-gpios = <&gpio0 13 0>,
> > + <&gpio0 14 0>;
> > + };
> > +...
> > diff --git a/Documentation/devicetree/bindings/spi/spi-dw.txt b/Documentation/devicetree/bindings/spi/spi-dw.txt
> > deleted file mode 100644
> > index 7b63ed601990..000000000000
> > --- a/Documentation/devicetree/bindings/spi/spi-dw.txt
> > +++ /dev/null
> > @@ -1,24 +0,0 @@
> > -Synopsys DesignWare SPI master
> > -
> > -Required properties:
> > -- compatible: should be "snps,designware-spi"
> > -- #address-cells: see spi-bus.txt
> > -- #size-cells: see spi-bus.txt
> > -- reg: address and length of the spi master registers
> > -- interrupts: should contain one interrupt
> > -- clocks: spi clock phandle
> > -- num-cs: see spi-bus.txt
> > -
> > -Optional properties:
> > -- cs-gpios: see spi-bus.txt
> > -
> > -Example:
> > -
> > -spi: spi@4020a000 {
> > - compatible = "snps,designware-spi";
> > - interrupts = <11 1>;
> > - reg = <0x4020a000 0x1000>;
> > - clocks = <&pclk>;
> > - num-cs = <2>;
> > - cs-gpios = <&banka 0 0>;
> > -};
> > --
> > 2.25.1
> >
>
> --
> With Best Regards,
> Andy Shevchenko
>
>
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH 01/17] dt-bindings: spi: Convert DW SPI binding to DT schema
2020-05-12 20:28 ` Serge Semin
@ 2020-05-12 20:35 ` Andy Shevchenko
0 siblings, 0 replies; 106+ messages in thread
From: Andy Shevchenko @ 2020-05-12 20:35 UTC (permalink / raw)
To: Serge Semin
Cc: Andy Shevchenko, Serge Semin, Wan Ahmad Zainie, Mark Brown,
Rob Herring, Georgy Vlasov, Ramil Zaripov, Alexey Malahov,
Thomas Bogendoerfer, Paul Burton, Ralf Baechle, Arnd Bergmann,
Allison Randal, Gareth Williams, linux-mips, linux-spi,
devicetree, Linux Kernel Mailing List
On Tue, May 12, 2020 at 11:29 PM Serge Semin
<Sergey.Semin@baikalelectronics.ru> wrote:
>
> +Cc: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
>
> On Fri, May 08, 2020 at 10:39:34PM +0300, Andy Shevchenko wrote:
> > On Fri, May 08, 2020 at 04:29:26PM +0300, Serge Semin wrote:
> > > Modern device tree bindings are supposed to be created as YAML-files
> > > in accordance with dt-schema. This commit replaces two DW SPI legacy
> > > bare text bindings with YAML file. As before the bindings file states
> > > that the corresponding dts node is supposed to be compatible either
> > > with generic DW APB SSI controller or with Microsemi/Amazon/Renesas
> > > vendors-specific controllers, to have registers, interrupts and clocks
> > > properties. Though in case of Microsemi version of the controller
> > > there must be two registers resources specified. Properties like
> > > clock-names, reg-io-width, cs-gpio, num-cs and SPI-specific sub-nodes
> > > are optional.
> >
> > Can you incorporate work done here or agree with Wan how to proceed?
> >
> > https://lore.kernel.org/linux-spi/20200505191910.GA2970@bogus/T/#md626b5f6f2294b0ebd70995d5ed0e67a360e000b
>
> Don't worry. I'll make sure the updates provided by Wan including the new IP
> support are preserved after rebasing this series on top of the spi/for-next.
Thanks!
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 106+ messages in thread
* [PATCH 02/17] dt-bindings: spi: dw: Add DMA properties bindings
2020-05-08 13:29 [PATCH 00/17] spi: dw: Add generic DW DMA controller support Serge Semin
2020-05-08 13:29 ` [PATCH 01/17] dt-bindings: spi: Convert DW SPI binding to DT schema Serge Semin
@ 2020-05-08 13:29 ` Serge Semin
2020-05-08 13:29 ` [PATCH 04/17] spi: dw: Cleanup generic DW DMA code namings Serge Semin
` (17 subsequent siblings)
19 siblings, 0 replies; 106+ messages in thread
From: Serge Semin @ 2020-05-08 13:29 UTC (permalink / raw)
To: Mark Brown, Rob Herring
Cc: Serge Semin, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Arnd Bergmann, Allison Randal, Andy Shevchenko, Gareth Williams,
linux-mips, linux-spi, devicetree, linux-kernel
Since DW SPI controller may use DW DMA engine to perform the CPU-less
Tx/Rx SPI transfers and the DW SPI driver now supports it, lets alter
the DW SPI bindings file to accept the Rx and Tx DMA line specifiers.
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
Cc: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Allison Randal <allison@lohutok.net>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Gareth Williams <gareth.williams.jx@renesas.com>
Cc: linux-mips@vger.kernel.org
---
.../devicetree/bindings/spi/snps,dw-apb-ssi.yaml | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
index e2f6d8aa6181..454208842084 100644
--- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
+++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
@@ -73,6 +73,16 @@ properties:
minimum: 1
maximum: 4
+ dmas:
+ items:
+ - description: TX DMA Channel
+ - description: RX DMA Channel
+
+ dma-names:
+ items:
+ - const: tx
+ - const: rx
+
patternProperties:
"^.*@[0-9a-f]+$":
type: object
--
2.25.1
^ permalink raw reply related [flat|nested] 106+ messages in thread
* [PATCH 04/17] spi: dw: Cleanup generic DW DMA code namings
2020-05-08 13:29 [PATCH 00/17] spi: dw: Add generic DW DMA controller support Serge Semin
2020-05-08 13:29 ` [PATCH 01/17] dt-bindings: spi: Convert DW SPI binding to DT schema Serge Semin
2020-05-08 13:29 ` [PATCH 02/17] dt-bindings: spi: dw: Add DMA properties bindings Serge Semin
@ 2020-05-08 13:29 ` Serge Semin
2020-05-08 19:43 ` Andy Shevchenko
2020-05-08 13:29 ` [PATCH 06/17] spi: dw: Add DW SPI DMA/PCI/MMIO dependency on DW SPI core Serge Semin
` (16 subsequent siblings)
19 siblings, 1 reply; 106+ messages in thread
From: Serge Semin @ 2020-05-08 13:29 UTC (permalink / raw)
To: Mark Brown
Cc: Serge Semin, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Arnd Bergmann, Allison Randal, Andy Shevchenko, Gareth Williams,
Rob Herring, linux-mips, devicetree, Thomas Gleixner, linux-spi,
linux-kernel
Since from now the former Intel MID platform layer will be used
as a generic DW SPI DMA module, lets alter the internal methods
naming to be DMA-related instead of having the "mid_" prefix. In
addition the DW PCI-DMA specific methods and structures should
be named with pci-suffexes, since we'll implement the DW MMIO DMA
specific functions and objects soon.
Co-developed-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
Signed-off-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
Co-developed-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
Signed-off-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Allison Randal <allison@lohutok.net>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Gareth Williams <gareth.williams.jx@renesas.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: devicetree@vger.kernel.org
---
drivers/spi/spi-dw-dma.c | 42 ++++++++++++++++++++--------------------
1 file changed, 21 insertions(+), 21 deletions(-)
diff --git a/drivers/spi/spi-dw-dma.c b/drivers/spi/spi-dw-dma.c
index 0230b4252611..523d9e39ffc1 100644
--- a/drivers/spi/spi-dw-dma.c
+++ b/drivers/spi/spi-dw-dma.c
@@ -20,10 +20,10 @@
#define RX_BUSY 0
#define TX_BUSY 1
-static struct dw_dma_slave mid_dma_tx = { .dst_id = 1 };
-static struct dw_dma_slave mid_dma_rx = { .src_id = 0 };
+static struct dw_dma_slave pci_dma_tx = { .dst_id = 1 };
+static struct dw_dma_slave pci_dma_rx = { .src_id = 0 };
-static bool mid_spi_dma_chan_filter(struct dma_chan *chan, void *param)
+static bool dw_spi_dma_chan_filter(struct dma_chan *chan, void *param)
{
struct dw_dma_slave *s = param;
@@ -34,7 +34,7 @@ static bool mid_spi_dma_chan_filter(struct dma_chan *chan, void *param)
return true;
}
-static int mid_spi_dma_init(struct dw_spi *dws)
+static int dw_spi_pci_dma_init(struct dw_spi *dws)
{
struct pci_dev *dma_dev;
struct dw_dma_slave *tx = dws->dma_tx;
@@ -54,14 +54,14 @@ static int mid_spi_dma_init(struct dw_spi *dws)
/* 1. Init rx channel */
rx->dma_dev = &dma_dev->dev;
- dws->rxchan = dma_request_channel(mask, mid_spi_dma_chan_filter, rx);
+ dws->rxchan = dma_request_channel(mask, dw_spi_dma_chan_filter, rx);
if (!dws->rxchan)
goto err_exit;
dws->master->dma_rx = dws->rxchan;
/* 2. Init tx channel */
tx->dma_dev = &dma_dev->dev;
- dws->txchan = dma_request_channel(mask, mid_spi_dma_chan_filter, tx);
+ dws->txchan = dma_request_channel(mask, dw_spi_dma_chan_filter, tx);
if (!dws->txchan)
goto free_rxchan;
dws->master->dma_tx = dws->txchan;
@@ -75,7 +75,7 @@ static int mid_spi_dma_init(struct dw_spi *dws)
return -EBUSY;
}
-static void mid_spi_dma_exit(struct dw_spi *dws)
+static void dw_spi_dma_exit(struct dw_spi *dws)
{
if (!dws->dma_inited)
return;
@@ -103,7 +103,7 @@ static irqreturn_t dma_transfer(struct dw_spi *dws)
return IRQ_HANDLED;
}
-static bool mid_spi_can_dma(struct spi_controller *master,
+static bool dw_spi_can_dma(struct spi_controller *master,
struct spi_device *spi, struct spi_transfer *xfer)
{
struct dw_spi *dws = spi_controller_get_devdata(master);
@@ -215,7 +215,7 @@ static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws,
return rxdesc;
}
-static int mid_spi_dma_setup(struct dw_spi *dws, struct spi_transfer *xfer)
+static int dw_spi_dma_setup(struct dw_spi *dws, struct spi_transfer *xfer)
{
u16 dma_ctrl = 0;
@@ -236,7 +236,7 @@ static int mid_spi_dma_setup(struct dw_spi *dws, struct spi_transfer *xfer)
return 0;
}
-static int mid_spi_dma_transfer(struct dw_spi *dws, struct spi_transfer *xfer)
+static int dw_spi_dma_transfer(struct dw_spi *dws, struct spi_transfer *xfer)
{
struct dma_async_tx_descriptor *txdesc, *rxdesc;
@@ -262,7 +262,7 @@ static int mid_spi_dma_transfer(struct dw_spi *dws, struct spi_transfer *xfer)
return 0;
}
-static void mid_spi_dma_stop(struct dw_spi *dws)
+static void dw_spi_dma_stop(struct dw_spi *dws)
{
if (test_bit(TX_BUSY, &dws->dma_chan_busy)) {
dmaengine_terminate_sync(dws->txchan);
@@ -274,19 +274,19 @@ static void mid_spi_dma_stop(struct dw_spi *dws)
}
}
-static const struct dw_spi_dma_ops mid_dma_ops = {
- .dma_init = mid_spi_dma_init,
- .dma_exit = mid_spi_dma_exit,
- .dma_setup = mid_spi_dma_setup,
- .can_dma = mid_spi_can_dma,
- .dma_transfer = mid_spi_dma_transfer,
- .dma_stop = mid_spi_dma_stop,
+static const struct dw_spi_dma_ops dw_spi_pci_dma_ops = {
+ .dma_init = dw_spi_pci_dma_init,
+ .dma_exit = dw_spi_dma_exit,
+ .dma_setup = dw_spi_dma_setup,
+ .can_dma = dw_spi_can_dma,
+ .dma_transfer = dw_spi_dma_transfer,
+ .dma_stop = dw_spi_dma_stop,
};
void dw_spi_pci_dma_setup(struct dw_spi *dws)
{
- dws->dma_tx = &mid_dma_tx;
- dws->dma_rx = &mid_dma_rx;
- dws->dma_ops = &mid_dma_ops;
+ dws->dma_tx = &pci_dma_tx;
+ dws->dma_rx = &pci_dma_rx;
+ dws->dma_ops = &dw_spi_pci_dma_ops;
}
EXPORT_SYMBOL_GPL(dw_spi_pci_dma_setup);
--
2.25.1
^ permalink raw reply related [flat|nested] 106+ messages in thread
* Re: [PATCH 04/17] spi: dw: Cleanup generic DW DMA code namings
2020-05-08 13:29 ` [PATCH 04/17] spi: dw: Cleanup generic DW DMA code namings Serge Semin
@ 2020-05-08 19:43 ` Andy Shevchenko
2020-05-12 21:26 ` Serge Semin
0 siblings, 1 reply; 106+ messages in thread
From: Andy Shevchenko @ 2020-05-08 19:43 UTC (permalink / raw)
To: Serge Semin
Cc: Mark Brown, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Arnd Bergmann, Allison Randal, Gareth Williams, Rob Herring,
linux-mips, devicetree, Thomas Gleixner, linux-spi, linux-kernel
On Fri, May 08, 2020 at 04:29:29PM +0300, Serge Semin wrote:
> Since from now the former Intel MID platform layer will be used
> as a generic DW SPI DMA module, lets alter the internal methods
> naming to be DMA-related instead of having the "mid_" prefix. In
> addition the DW PCI-DMA specific methods and structures should
> be named with pci-suffexes, since we'll implement the DW MMIO DMA
> specific functions and objects soon.
I think we rather leave Intel Medfield things alone. And I think I did this already in spi/for-next in less invasive way.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH 04/17] spi: dw: Cleanup generic DW DMA code namings
2020-05-08 19:43 ` Andy Shevchenko
@ 2020-05-12 21:26 ` Serge Semin
2020-05-12 21:37 ` Andy Shevchenko
0 siblings, 1 reply; 106+ messages in thread
From: Serge Semin @ 2020-05-12 21:26 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Serge Semin, Mark Brown, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Arnd Bergmann, Allison Randal, Gareth Williams, Rob Herring,
linux-mips, devicetree, Thomas Gleixner, linux-spi, linux-kernel
On Fri, May 08, 2020 at 10:43:24PM +0300, Andy Shevchenko wrote:
> On Fri, May 08, 2020 at 04:29:29PM +0300, Serge Semin wrote:
> > Since from now the former Intel MID platform layer will be used
> > as a generic DW SPI DMA module, lets alter the internal methods
> > naming to be DMA-related instead of having the "mid_" prefix. In
> > addition the DW PCI-DMA specific methods and structures should
> > be named with pci-suffexes, since we'll implement the DW MMIO DMA
> > specific functions and objects soon.
>
> I think we rather leave Intel Medfield things alone. And I think I did this already in spi/for-next in less invasive way.
The naming is horrible in that module. Since it's going to be a generic DMA
driver the prefixes should be correspondingly fixed. Currently they are a bit
random.
-Sergey
>
> --
> With Best Regards,
> Andy Shevchenko
>
>
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH 04/17] spi: dw: Cleanup generic DW DMA code namings
2020-05-12 21:26 ` Serge Semin
@ 2020-05-12 21:37 ` Andy Shevchenko
0 siblings, 0 replies; 106+ messages in thread
From: Andy Shevchenko @ 2020-05-12 21:37 UTC (permalink / raw)
To: Serge Semin
Cc: Andy Shevchenko, Serge Semin, Mark Brown, Georgy Vlasov,
Ramil Zaripov, Alexey Malahov, Thomas Bogendoerfer, Paul Burton,
Ralf Baechle, Arnd Bergmann, Allison Randal, Gareth Williams,
Rob Herring, linux-mips, devicetree, Thomas Gleixner, linux-spi,
Linux Kernel Mailing List
On Wed, May 13, 2020 at 12:28 AM Serge Semin
<Sergey.Semin@baikalelectronics.ru> wrote:
>
> On Fri, May 08, 2020 at 10:43:24PM +0300, Andy Shevchenko wrote:
> > On Fri, May 08, 2020 at 04:29:29PM +0300, Serge Semin wrote:
> > > Since from now the former Intel MID platform layer will be used
> > > as a generic DW SPI DMA module, lets alter the internal methods
> > > naming to be DMA-related instead of having the "mid_" prefix. In
> > > addition the DW PCI-DMA specific methods and structures should
> > > be named with pci-suffexes, since we'll implement the DW MMIO DMA
> > > specific functions and objects soon.
> >
> > I think we rather leave Intel Medfield things alone. And I think I did this already in spi/for-next in less invasive way.
>
> The naming is horrible in that module.
I agree!
> Since it's going to be a generic DMA
> driver the prefixes should be correspondingly fixed. Currently they are a bit
> random.
Unfortunately, proposed '_pci' not anyhow better. There is Medfield
stuff and non-Medfield.
Luckily Elkhart Lake uses generic approach. That's why better to have
suffix based on platform, rather than on bus.
I think what should be done here are (in a patch per item):
1) moving to new named module (w/o mid)
2) removing mid_ prefix
3) something else I forgot?
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 106+ messages in thread
* [PATCH 06/17] spi: dw: Add DW SPI DMA/PCI/MMIO dependency on DW SPI core
2020-05-08 13:29 [PATCH 00/17] spi: dw: Add generic DW DMA controller support Serge Semin
` (2 preceding siblings ...)
2020-05-08 13:29 ` [PATCH 04/17] spi: dw: Cleanup generic DW DMA code namings Serge Semin
@ 2020-05-08 13:29 ` Serge Semin
2020-05-08 13:29 ` [PATCH 08/17] spi: dw: Clear DMAC register when done or stopped Serge Semin
` (15 subsequent siblings)
19 siblings, 0 replies; 106+ messages in thread
From: Serge Semin @ 2020-05-08 13:29 UTC (permalink / raw)
To: Mark Brown
Cc: Serge Semin, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Arnd Bergmann, Allison Randal, Andy Shevchenko, Gareth Williams,
Rob Herring, linux-mips, devicetree, John Garry, Chuanhong Guo,
Krzysztof Kozlowski, Chris Packham, Masahisa Kojima,
Tomer Maimon, Florian Fainelli, linux-spi, linux-kernel
Seeing all of the DW SPI driver components like DW SPI DMA/PCI/MMIO
depend on the DW SPI core code it's better to use the if-endif
conditional kernel config statement to signify that common dependency.
Co-developed-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
Signed-off-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
Co-developed-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
Signed-off-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Allison Randal <allison@lohutok.net>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Gareth Williams <gareth.williams.jx@renesas.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: devicetree@vger.kernel.org
---
drivers/spi/Kconfig | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 9653c7f271e9..d8c67ae936e7 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -226,17 +226,21 @@ config SPI_DESIGNWARE
help
general driver for SPI controller core from DesignWare
+if SPI_DESIGNWARE
+
config SPI_DW_DMA
tristate "DMA support for DW SPI controller"
- depends on SPI_DESIGNWARE && DW_DMAC_PCI
+ depends on DW_DMAC_PCI
config SPI_DW_PCI
tristate "PCI interface driver for DW SPI core"
- depends on SPI_DESIGNWARE && PCI
+ depends on PCI
config SPI_DW_MMIO
tristate "Memory-mapped io interface driver for DW SPI core"
- depends on SPI_DESIGNWARE
+ depends on HAS_IOMEM
+
+endif
config SPI_DLN2
tristate "Diolan DLN-2 USB SPI adapter"
--
2.25.1
^ permalink raw reply related [flat|nested] 106+ messages in thread
* [PATCH 08/17] spi: dw: Clear DMAC register when done or stopped
2020-05-08 13:29 [PATCH 00/17] spi: dw: Add generic DW DMA controller support Serge Semin
` (3 preceding siblings ...)
2020-05-08 13:29 ` [PATCH 06/17] spi: dw: Add DW SPI DMA/PCI/MMIO dependency on DW SPI core Serge Semin
@ 2020-05-08 13:29 ` Serge Semin
2020-05-08 17:31 ` Mark Brown
2020-05-08 13:29 ` [PATCH 09/17] spi: dw: Enable interrupts in accordance with DMA xfer mode Serge Semin
` (14 subsequent siblings)
19 siblings, 1 reply; 106+ messages in thread
From: Serge Semin @ 2020-05-08 13:29 UTC (permalink / raw)
To: Mark Brown
Cc: Serge Semin, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Arnd Bergmann, Allison Randal, Andy Shevchenko, Gareth Williams,
Rob Herring, linux-mips, devicetree, Greg Kroah-Hartman,
Thomas Gleixner, linux-spi, linux-kernel
If DMAC register is left uncleared any further DMAless transfers
may cause the DMAC hardware handshaking interface getting activated.
So the next DMA-based Rx/Tx transaction will be started right
after the dma_async_issue_pending() method is invoked even if no
DMATDLR/DMARDLR conditions are met. This at the same time may cause
the Tx/Rx FIFO buffers underrun/overrun. In order to fix this we
must clear DMAC register after a current DMA-based transaction is
finished.
Co-developed-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
Signed-off-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Allison Randal <allison@lohutok.net>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Gareth Williams <gareth.williams.jx@renesas.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: devicetree@vger.kernel.org
---
drivers/spi/spi-dw-dma.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/spi/spi-dw-dma.c b/drivers/spi/spi-dw-dma.c
index 7f0e4d888125..7a6769386932 100644
--- a/drivers/spi/spi-dw-dma.c
+++ b/drivers/spi/spi-dw-dma.c
@@ -156,6 +156,8 @@ static void dw_spi_dma_tx_done(void *arg)
clear_bit(TX_BUSY, &dws->dma_chan_busy);
if (test_bit(RX_BUSY, &dws->dma_chan_busy))
return;
+
+ dw_writel(dws, DW_SPI_DMACR, 0);
spi_finalize_current_transfer(dws->master);
}
@@ -226,6 +228,8 @@ static void dw_spi_dma_rx_done(void *arg)
clear_bit(RX_BUSY, &dws->dma_chan_busy);
if (test_bit(TX_BUSY, &dws->dma_chan_busy))
return;
+
+ dw_writel(dws, DW_SPI_DMACR, 0);
spi_finalize_current_transfer(dws->master);
}
@@ -318,6 +322,8 @@ static void dw_spi_dma_stop(struct dw_spi *dws)
dmaengine_terminate_sync(dws->rxchan);
clear_bit(RX_BUSY, &dws->dma_chan_busy);
}
+
+ dw_writel(dws, DW_SPI_DMACR, 0);
}
static const struct dw_spi_dma_ops dw_spi_pci_dma_ops = {
--
2.25.1
^ permalink raw reply related [flat|nested] 106+ messages in thread
* Re: [PATCH 08/17] spi: dw: Clear DMAC register when done or stopped
2020-05-08 13:29 ` [PATCH 08/17] spi: dw: Clear DMAC register when done or stopped Serge Semin
@ 2020-05-08 17:31 ` Mark Brown
2020-05-13 11:56 ` Serge Semin
0 siblings, 1 reply; 106+ messages in thread
From: Mark Brown @ 2020-05-08 17:31 UTC (permalink / raw)
To: Serge Semin
Cc: Serge Semin, Georgy Vlasov, Ramil Zaripov, Alexey Malahov,
Thomas Bogendoerfer, Paul Burton, Ralf Baechle, Arnd Bergmann,
Allison Randal, Andy Shevchenko, Gareth Williams, Rob Herring,
linux-mips, devicetree, Greg Kroah-Hartman, Thomas Gleixner,
linux-spi, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 647 bytes --]
On Fri, May 08, 2020 at 04:29:33PM +0300, Serge Semin wrote:
> If DMAC register is left uncleared any further DMAless transfers
> may cause the DMAC hardware handshaking interface getting activated.
> So the next DMA-based Rx/Tx transaction will be started right
> after the dma_async_issue_pending() method is invoked even if no
> DMATDLR/DMARDLR conditions are met. This at the same time may cause
> the Tx/Rx FIFO buffers underrun/overrun. In order to fix this we
> must clear DMAC register after a current DMA-based transaction is
> finished.
This also looks like a bugfix so should be pulled forwards to the start
of the series if possible.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH 08/17] spi: dw: Clear DMAC register when done or stopped
2020-05-08 17:31 ` Mark Brown
@ 2020-05-13 11:56 ` Serge Semin
0 siblings, 0 replies; 106+ messages in thread
From: Serge Semin @ 2020-05-13 11:56 UTC (permalink / raw)
To: Mark Brown
Cc: Serge Semin, Georgy Vlasov, Ramil Zaripov, Alexey Malahov,
Thomas Bogendoerfer, Paul Burton, Ralf Baechle, Arnd Bergmann,
Allison Randal, Andy Shevchenko, Gareth Williams, Rob Herring,
linux-mips, devicetree, Greg Kroah-Hartman, Thomas Gleixner,
linux-spi, linux-kernel
On Fri, May 08, 2020 at 06:31:34PM +0100, Mark Brown wrote:
> On Fri, May 08, 2020 at 04:29:33PM +0300, Serge Semin wrote:
> > If DMAC register is left uncleared any further DMAless transfers
> > may cause the DMAC hardware handshaking interface getting activated.
> > So the next DMA-based Rx/Tx transaction will be started right
> > after the dma_async_issue_pending() method is invoked even if no
> > DMATDLR/DMARDLR conditions are met. This at the same time may cause
> > the Tx/Rx FIFO buffers underrun/overrun. In order to fix this we
> > must clear DMAC register after a current DMA-based transaction is
> > finished.
>
> This also looks like a bugfix so should be pulled forwards to the start
> of the series if possible.
Ok.
-Sergey
^ permalink raw reply [flat|nested] 106+ messages in thread
* [PATCH 09/17] spi: dw: Enable interrupts in accordance with DMA xfer mode
2020-05-08 13:29 [PATCH 00/17] spi: dw: Add generic DW DMA controller support Serge Semin
` (4 preceding siblings ...)
2020-05-08 13:29 ` [PATCH 08/17] spi: dw: Clear DMAC register when done or stopped Serge Semin
@ 2020-05-08 13:29 ` Serge Semin
2020-05-08 13:29 ` [PATCH 10/17] spi: dw: Parameterize the DMA Rx/Tx burst length Serge Semin
` (13 subsequent siblings)
19 siblings, 0 replies; 106+ messages in thread
From: Serge Semin @ 2020-05-08 13:29 UTC (permalink / raw)
To: Mark Brown
Cc: Serge Semin, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Arnd Bergmann, Allison Randal, Andy Shevchenko, Gareth Williams,
Rob Herring, linux-mips, devicetree, Thomas Gleixner, linux-spi,
linux-kernel
It's pointless to track the Tx overrun interrupts if Rx-only SPI
transfer is issued. Similarly there is no need in handling the Rx
overrun/underrun interrupts if Tx-only SPI transfer is executed.
So lets unmask the interrupts only if corresponding SPI
transactions are implied.
Co-developed-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
Signed-off-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Allison Randal <allison@lohutok.net>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Gareth Williams <gareth.williams.jx@renesas.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: devicetree@vger.kernel.org
---
drivers/spi/spi-dw-dma.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/spi/spi-dw-dma.c b/drivers/spi/spi-dw-dma.c
index 7a6769386932..201390f7d032 100644
--- a/drivers/spi/spi-dw-dma.c
+++ b/drivers/spi/spi-dw-dma.c
@@ -267,19 +267,23 @@ static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws,
static int dw_spi_dma_setup(struct dw_spi *dws, struct spi_transfer *xfer)
{
- u16 dma_ctrl = 0;
+ u16 imr = 0, dma_ctrl = 0;
dw_writel(dws, DW_SPI_DMARDLR, 0xf);
dw_writel(dws, DW_SPI_DMATDLR, 0x10);
- if (xfer->tx_buf)
+ if (xfer->tx_buf) {
dma_ctrl |= SPI_DMA_TDMAE;
- if (xfer->rx_buf)
+ imr |= SPI_INT_TXOI;
+ }
+ if (xfer->rx_buf) {
dma_ctrl |= SPI_DMA_RDMAE;
+ imr |= SPI_INT_RXUI | SPI_INT_RXOI;
+ }
dw_writel(dws, DW_SPI_DMACR, dma_ctrl);
/* Set the interrupt mask */
- spi_umask_intr(dws, SPI_INT_TXOI | SPI_INT_RXUI | SPI_INT_RXOI);
+ spi_umask_intr(dws, imr);
dws->transfer_handler = dma_transfer;
--
2.25.1
^ permalink raw reply related [flat|nested] 106+ messages in thread
* [PATCH 10/17] spi: dw: Parameterize the DMA Rx/Tx burst length
2020-05-08 13:29 [PATCH 00/17] spi: dw: Add generic DW DMA controller support Serge Semin
` (5 preceding siblings ...)
2020-05-08 13:29 ` [PATCH 09/17] spi: dw: Enable interrupts in accordance with DMA xfer mode Serge Semin
@ 2020-05-08 13:29 ` Serge Semin
2020-05-08 13:29 ` [PATCH 12/17] spi: dw: Fix dma_slave_config used partly uninitialized Serge Semin
` (12 subsequent siblings)
19 siblings, 0 replies; 106+ messages in thread
From: Serge Semin @ 2020-05-08 13:29 UTC (permalink / raw)
To: Mark Brown
Cc: Serge Semin, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Arnd Bergmann, Allison Randal, Andy Shevchenko, Gareth Williams,
Rob Herring, linux-mips, devicetree, Thomas Gleixner, linux-spi,
linux-kernel
It isn't good to have numeric literals in the code especially if there
are multiple of them and they are related. Moreover in current
implementation the Tx DMA transfer activation level isn't optimal,
since it's hardwired to be at 16-32 bytes level, while it's better
to keep the SPI FIFO buffer as full as possible until all available
data is submitted. So lets introduce the DMA burst level
parametrization macros with optimal values - issue Rx transfer if at
least 16 bytes are available in the buffer and execute Tx transaction
if at least 16 bytes room is opened in SPI Tx FIFO.
Co-developed-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
Signed-off-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
Co-developed-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
Signed-off-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Allison Randal <allison@lohutok.net>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Gareth Williams <gareth.williams.jx@renesas.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: devicetree@vger.kernel.org
---
drivers/spi/spi-dw-dma.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/spi/spi-dw-dma.c b/drivers/spi/spi-dw-dma.c
index 201390f7d032..d89a00fb705e 100644
--- a/drivers/spi/spi-dw-dma.c
+++ b/drivers/spi/spi-dw-dma.c
@@ -20,7 +20,9 @@
#define WAIT_RETRIES 5
#define RX_BUSY 0
+#define RX_BURST_LEVEL 16
#define TX_BUSY 1
+#define TX_BURST_LEVEL 16
static bool dw_spi_dma_chan_filter(struct dma_chan *chan, void *param)
{
@@ -172,7 +174,7 @@ static struct dma_async_tx_descriptor *dw_spi_dma_prepare_tx(struct dw_spi *dws,
txconf.direction = DMA_MEM_TO_DEV;
txconf.dst_addr = dws->dma_addr;
- txconf.dst_maxburst = 16;
+ txconf.dst_maxburst = TX_BURST_LEVEL;
txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
txconf.dst_addr_width = convert_dma_width(dws->dma_width);
txconf.device_fc = false;
@@ -244,7 +246,7 @@ static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws,
rxconf.direction = DMA_DEV_TO_MEM;
rxconf.src_addr = dws->dma_addr;
- rxconf.src_maxburst = 16;
+ rxconf.src_maxburst = RX_BURST_LEVEL;
rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
rxconf.src_addr_width = convert_dma_width(dws->dma_width);
rxconf.device_fc = false;
@@ -269,8 +271,8 @@ static int dw_spi_dma_setup(struct dw_spi *dws, struct spi_transfer *xfer)
{
u16 imr = 0, dma_ctrl = 0;
- dw_writel(dws, DW_SPI_DMARDLR, 0xf);
- dw_writel(dws, DW_SPI_DMATDLR, 0x10);
+ dw_writel(dws, DW_SPI_DMARDLR, RX_BURST_LEVEL - 1);
+ dw_writel(dws, DW_SPI_DMATDLR, dws->fifo_len - TX_BURST_LEVEL);
if (xfer->tx_buf) {
dma_ctrl |= SPI_DMA_TDMAE;
--
2.25.1
^ permalink raw reply related [flat|nested] 106+ messages in thread
* [PATCH 12/17] spi: dw: Fix dma_slave_config used partly uninitialized
2020-05-08 13:29 [PATCH 00/17] spi: dw: Add generic DW DMA controller support Serge Semin
` (6 preceding siblings ...)
2020-05-08 13:29 ` [PATCH 10/17] spi: dw: Parameterize the DMA Rx/Tx burst length Serge Semin
@ 2020-05-08 13:29 ` Serge Semin
2020-05-08 19:20 ` Andy Shevchenko
2020-05-08 13:29 ` [PATCH 13/17] spi: dw: Initialize paddr in DW SPI MMIO private data Serge Semin
` (11 subsequent siblings)
19 siblings, 1 reply; 106+ messages in thread
From: Serge Semin @ 2020-05-08 13:29 UTC (permalink / raw)
To: Mark Brown
Cc: Serge Semin, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Arnd Bergmann, Allison Randal, Andy Shevchenko, Gareth Williams,
Rob Herring, linux-mips, devicetree, Thomas Gleixner, linux-spi,
linux-kernel
Since the TX and RX DMA-slave config structures are declared on the
stack and only a part of their fields is initialized further in the
prepare Tx/Rx methods, the next dmaengine_slave_config() calls may
randomly perform an incorrect DMA channels setup depending on the
stack initial values. Lets fix this by zeroing the config-structures
before using them.
Co-developed-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
Signed-off-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Allison Randal <allison@lohutok.net>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Gareth Williams <gareth.williams.jx@renesas.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: devicetree@vger.kernel.org
---
drivers/spi/spi-dw-dma.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-dw-dma.c b/drivers/spi/spi-dw-dma.c
index d89a00fb705e..3802d2cafe91 100644
--- a/drivers/spi/spi-dw-dma.c
+++ b/drivers/spi/spi-dw-dma.c
@@ -166,7 +166,7 @@ static void dw_spi_dma_tx_done(void *arg)
static struct dma_async_tx_descriptor *dw_spi_dma_prepare_tx(struct dw_spi *dws,
struct spi_transfer *xfer)
{
- struct dma_slave_config txconf;
+ struct dma_slave_config txconf = {0};
struct dma_async_tx_descriptor *txdesc;
if (!xfer->tx_buf)
@@ -238,7 +238,7 @@ static void dw_spi_dma_rx_done(void *arg)
static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws,
struct spi_transfer *xfer)
{
- struct dma_slave_config rxconf;
+ struct dma_slave_config rxconf = {0};
struct dma_async_tx_descriptor *rxdesc;
if (!xfer->rx_buf)
--
2.25.1
^ permalink raw reply related [flat|nested] 106+ messages in thread
* Re: [PATCH 12/17] spi: dw: Fix dma_slave_config used partly uninitialized
2020-05-08 13:29 ` [PATCH 12/17] spi: dw: Fix dma_slave_config used partly uninitialized Serge Semin
@ 2020-05-08 19:20 ` Andy Shevchenko
0 siblings, 0 replies; 106+ messages in thread
From: Andy Shevchenko @ 2020-05-08 19:20 UTC (permalink / raw)
To: Serge Semin
Cc: Mark Brown, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Arnd Bergmann, Allison Randal, Gareth Williams, Rob Herring,
linux-mips, devicetree, Thomas Gleixner, linux-spi, linux-kernel
On Fri, May 08, 2020 at 04:29:37PM +0300, Serge Semin wrote:
> Since the TX and RX DMA-slave config structures are declared on the
> stack and only a part of their fields is initialized further in the
> prepare Tx/Rx methods, the next dmaengine_slave_config() calls may
> randomly perform an incorrect DMA channels setup depending on the
> stack initial values. Lets fix this by zeroing the config-structures
> before using them.
Already in spi/for-next.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 106+ messages in thread
* [PATCH 13/17] spi: dw: Initialize paddr in DW SPI MMIO private data
2020-05-08 13:29 [PATCH 00/17] spi: dw: Add generic DW DMA controller support Serge Semin
` (7 preceding siblings ...)
2020-05-08 13:29 ` [PATCH 12/17] spi: dw: Fix dma_slave_config used partly uninitialized Serge Semin
@ 2020-05-08 13:29 ` Serge Semin
2020-05-08 19:21 ` Andy Shevchenko
2020-05-08 13:33 ` [PATCH 00/17] spi: dw: Add generic DW DMA controller support Mark Brown
` (10 subsequent siblings)
19 siblings, 1 reply; 106+ messages in thread
From: Serge Semin @ 2020-05-08 13:29 UTC (permalink / raw)
To: Mark Brown
Cc: Serge Semin, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Arnd Bergmann, Allison Randal, Andy Shevchenko, Gareth Williams,
Rob Herring, linux-mips, devicetree, Stephen Boyd,
Thomas Gleixner, YueHaibing, Jarkko Nikula, linux-spi,
linux-kernel
This field is used only for the DW SPI DMA code initialization, that's
why there were no problems with it being uninitialized in Dw SPI MMIO
driver. Since in a further patch we are going to introduce the DW SPI DMA
support in the MMIO version of the driver, lets set the field with the
physical address of the DW SPI controller registers region.
Co-developed-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
Signed-off-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
Co-developed-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
Signed-off-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Allison Randal <allison@lohutok.net>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Gareth Williams <gareth.williams.jx@renesas.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: devicetree@vger.kernel.org
---
drivers/spi/spi-dw-mmio.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c
index 384a3ab6dc2d..2ff1b700305f 100644
--- a/drivers/spi/spi-dw-mmio.c
+++ b/drivers/spi/spi-dw-mmio.c
@@ -136,6 +136,7 @@ static int dw_spi_mmio_probe(struct platform_device *pdev)
int (*init_func)(struct platform_device *pdev,
struct dw_spi_mmio *dwsmmio);
struct dw_spi_mmio *dwsmmio;
+ struct resource *mem;
struct dw_spi *dws;
int ret;
int num_cs;
@@ -148,11 +149,13 @@ static int dw_spi_mmio_probe(struct platform_device *pdev)
dws = &dwsmmio->dws;
/* Get basic io resource and map it */
- dws->regs = devm_platform_ioremap_resource(pdev, 0);
+ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ dws->regs = devm_ioremap_resource(&pdev->dev, mem);
if (IS_ERR(dws->regs)) {
dev_err(&pdev->dev, "SPI region map failed\n");
return PTR_ERR(dws->regs);
}
+ dws->paddr = mem->start;
dws->irq = platform_get_irq(pdev, 0);
if (dws->irq < 0)
--
2.25.1
^ permalink raw reply related [flat|nested] 106+ messages in thread
* Re: [PATCH 13/17] spi: dw: Initialize paddr in DW SPI MMIO private data
2020-05-08 13:29 ` [PATCH 13/17] spi: dw: Initialize paddr in DW SPI MMIO private data Serge Semin
@ 2020-05-08 19:21 ` Andy Shevchenko
2020-05-13 12:30 ` Serge Semin
0 siblings, 1 reply; 106+ messages in thread
From: Andy Shevchenko @ 2020-05-08 19:21 UTC (permalink / raw)
To: Serge Semin
Cc: Mark Brown, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Arnd Bergmann, Allison Randal, Gareth Williams, Rob Herring,
linux-mips, devicetree, Stephen Boyd, Thomas Gleixner,
YueHaibing, Jarkko Nikula, linux-spi, linux-kernel
On Fri, May 08, 2020 at 04:29:38PM +0300, Serge Semin wrote:
> This field is used only for the DW SPI DMA code initialization, that's
> why there were no problems with it being uninitialized in Dw SPI MMIO
> driver. Since in a further patch we are going to introduce the DW SPI DMA
> support in the MMIO version of the driver, lets set the field with the
> physical address of the DW SPI controller registers region.
...
> - dws->regs = devm_platform_ioremap_resource(pdev, 0);
> + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + dws->regs = devm_ioremap_resource(&pdev->dev, mem);
There is a helper
dws->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
> if (IS_ERR(dws->regs)) {
> dev_err(&pdev->dev, "SPI region map failed\n");
> return PTR_ERR(dws->regs);
> }
> + dws->paddr = mem->start;
>
> dws->irq = platform_get_irq(pdev, 0);
> if (dws->irq < 0)
> --
> 2.25.1
>
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH 13/17] spi: dw: Initialize paddr in DW SPI MMIO private data
2020-05-08 19:21 ` Andy Shevchenko
@ 2020-05-13 12:30 ` Serge Semin
0 siblings, 0 replies; 106+ messages in thread
From: Serge Semin @ 2020-05-13 12:30 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Serge Semin, Mark Brown, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Arnd Bergmann, Allison Randal, Gareth Williams, Rob Herring,
linux-mips, devicetree, Stephen Boyd, Thomas Gleixner,
YueHaibing, Jarkko Nikula, linux-spi, linux-kernel
On Fri, May 08, 2020 at 10:21:44PM +0300, Andy Shevchenko wrote:
> On Fri, May 08, 2020 at 04:29:38PM +0300, Serge Semin wrote:
> > This field is used only for the DW SPI DMA code initialization, that's
> > why there were no problems with it being uninitialized in Dw SPI MMIO
> > driver. Since in a further patch we are going to introduce the DW SPI DMA
> > support in the MMIO version of the driver, lets set the field with the
> > physical address of the DW SPI controller registers region.
>
> ...
>
> > - dws->regs = devm_platform_ioremap_resource(pdev, 0);
> > + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > + dws->regs = devm_ioremap_resource(&pdev->dev, mem);
>
> There is a helper
> dws->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
Oh, good point. It has been just added, in kernel v5.7. v5.6 didn't provide such
a convenient helper. Thanks for the suggestion.
-Sergey
>
>
> > if (IS_ERR(dws->regs)) {
> > dev_err(&pdev->dev, "SPI region map failed\n");
> > return PTR_ERR(dws->regs);
> > }
> > + dws->paddr = mem->start;
> >
> > dws->irq = platform_get_irq(pdev, 0);
> > if (dws->irq < 0)
> > --
> > 2.25.1
> >
>
> --
> With Best Regards,
> Andy Shevchenko
>
>
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH 00/17] spi: dw: Add generic DW DMA controller support
2020-05-08 13:29 [PATCH 00/17] spi: dw: Add generic DW DMA controller support Serge Semin
` (8 preceding siblings ...)
2020-05-08 13:29 ` [PATCH 13/17] spi: dw: Initialize paddr in DW SPI MMIO private data Serge Semin
@ 2020-05-08 13:33 ` Mark Brown
2020-05-12 20:07 ` Serge Semin
[not found] ` <20200508132943.9826-8-Sergey.Semin@baikalelectronics.ru>
` (9 subsequent siblings)
19 siblings, 1 reply; 106+ messages in thread
From: Mark Brown @ 2020-05-08 13:33 UTC (permalink / raw)
To: Serge Semin
Cc: Serge Semin, Georgy Vlasov, Ramil Zaripov, Alexey Malahov,
Maxim Kaurkin, Pavel Parkhomenko, Ekaterina Skachko,
Vadim Vlasov, Alexey Kolotnikov, Thomas Bogendoerfer,
Paul Burton, Ralf Baechle, Arnd Bergmann, Allison Randal,
Andy Shevchenko, Gareth Williams, Rob Herring, linux-mips,
linux-spi, devicetree, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 432 bytes --]
On Fri, May 08, 2020 at 04:29:25PM +0300, Serge Semin wrote:
> Serge Semin (17):
> dt-bindings: spi: Convert DW SPI binding to DT schema
Please don't make new feature development dependent on conversion to the
new schema format, there's quite a backlog of reviews of schema
conversions so it can slow things down. It's good to do the conversions
but please do them after adding any new stuff to the binding rather than
before.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH 00/17] spi: dw: Add generic DW DMA controller support
2020-05-08 13:33 ` [PATCH 00/17] spi: dw: Add generic DW DMA controller support Mark Brown
@ 2020-05-12 20:07 ` Serge Semin
2020-05-13 10:23 ` Mark Brown
0 siblings, 1 reply; 106+ messages in thread
From: Serge Semin @ 2020-05-12 20:07 UTC (permalink / raw)
To: Mark Brown
Cc: Serge Semin, Georgy Vlasov, Ramil Zaripov, Alexey Malahov,
Maxim Kaurkin, Pavel Parkhomenko, Ekaterina Skachko,
Vadim Vlasov, Alexey Kolotnikov, Thomas Bogendoerfer,
Paul Burton, Ralf Baechle, Arnd Bergmann, Allison Randal,
Andy Shevchenko, Gareth Williams, Rob Herring, linux-mips,
linux-spi, devicetree, linux-kernel
On Fri, May 08, 2020 at 02:33:36PM +0100, Mark Brown wrote:
> On Fri, May 08, 2020 at 04:29:25PM +0300, Serge Semin wrote:
>
> > Serge Semin (17):
> > dt-bindings: spi: Convert DW SPI binding to DT schema
>
> Please don't make new feature development dependent on conversion to the
> new schema format, there's quite a backlog of reviews of schema
> conversions so it can slow things down. It's good to do the conversions
> but please do them after adding any new stuff to the binding rather than
> before.
So by saying this do you want me to revert an order of the first two patches
in the series, right? So the series would first add the DMA properties support
to the binding, then would convert the binding file to DT schema.
-Sergey
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH 00/17] spi: dw: Add generic DW DMA controller support
2020-05-12 20:07 ` Serge Semin
@ 2020-05-13 10:23 ` Mark Brown
2020-05-13 11:04 ` Serge Semin
0 siblings, 1 reply; 106+ messages in thread
From: Mark Brown @ 2020-05-13 10:23 UTC (permalink / raw)
To: Serge Semin
Cc: Serge Semin, Georgy Vlasov, Ramil Zaripov, Alexey Malahov,
Maxim Kaurkin, Pavel Parkhomenko, Ekaterina Skachko,
Vadim Vlasov, Alexey Kolotnikov, Thomas Bogendoerfer,
Paul Burton, Ralf Baechle, Arnd Bergmann, Allison Randal,
Andy Shevchenko, Gareth Williams, Rob Herring, linux-mips,
linux-spi, devicetree, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 856 bytes --]
On Tue, May 12, 2020 at 11:07:33PM +0300, Serge Semin wrote:
> On Fri, May 08, 2020 at 02:33:36PM +0100, Mark Brown wrote:
> > Please don't make new feature development dependent on conversion to the
> > new schema format, there's quite a backlog of reviews of schema
> > conversions so it can slow things down. It's good to do the conversions
> > but please do them after adding any new stuff to the binding rather than
> > before.
> So by saying this do you want me to revert an order of the first two patches
> in the series, right? So the series would first add the DMA properties support
> to the binding, then would convert the binding file to DT schema.
The conversion to YAML format should be the very last thing in the patch
series, and as Andy says there's another patch in flight also doing this
conversion which you should coordinate with.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH 00/17] spi: dw: Add generic DW DMA controller support
2020-05-13 10:23 ` Mark Brown
@ 2020-05-13 11:04 ` Serge Semin
2020-05-13 11:21 ` Mark Brown
0 siblings, 1 reply; 106+ messages in thread
From: Serge Semin @ 2020-05-13 11:04 UTC (permalink / raw)
To: Mark Brown
Cc: Serge Semin, Georgy Vlasov, Ramil Zaripov, Alexey Malahov,
Maxim Kaurkin, Pavel Parkhomenko, Ekaterina Skachko,
Vadim Vlasov, Alexey Kolotnikov, Thomas Bogendoerfer,
Paul Burton, Ralf Baechle, Arnd Bergmann, Allison Randal,
Andy Shevchenko, Gareth Williams, Rob Herring, linux-mips,
linux-spi, devicetree, linux-kernel
On Wed, May 13, 2020 at 11:23:24AM +0100, Mark Brown wrote:
> On Tue, May 12, 2020 at 11:07:33PM +0300, Serge Semin wrote:
> > On Fri, May 08, 2020 at 02:33:36PM +0100, Mark Brown wrote:
>
> > > Please don't make new feature development dependent on conversion to the
> > > new schema format, there's quite a backlog of reviews of schema
> > > conversions so it can slow things down. It's good to do the conversions
> > > but please do them after adding any new stuff to the binding rather than
> > > before.
>
> > So by saying this do you want me to revert an order of the first two patches
> > in the series, right? So the series would first add the DMA properties support
> > to the binding, then would convert the binding file to DT schema.
>
> The conversion to YAML format should be the very last thing in the patch
> series,
Hm, haven't heard about this requirement. Could you point me out to a doc or
some discussion concerning this for future reference? It's not a first DT
conversion patch I've submitted and non of them were addressed with such
request. I do understand that the order of DT concerning patches can be
important and agree to fix it by updating the original legacy binding first,
then perform a conversion. But placing the conversion in a tail of the series
just seems unnecessary. The patch can be dropped from any place of the series
if for some reason Rob would be late with review.
Personally I prefer placing all DT changes in the head of the series, so Rob
wouldn't need to search through the whole patchset looking for the DT-related
patches.
-Sergey
> and as Andy says there's another patch in flight also doing this
> conversion which you should coordinate with.
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH 00/17] spi: dw: Add generic DW DMA controller support
2020-05-13 11:04 ` Serge Semin
@ 2020-05-13 11:21 ` Mark Brown
2020-05-13 11:42 ` Serge Semin
0 siblings, 1 reply; 106+ messages in thread
From: Mark Brown @ 2020-05-13 11:21 UTC (permalink / raw)
To: Serge Semin
Cc: Serge Semin, Georgy Vlasov, Ramil Zaripov, Alexey Malahov,
Maxim Kaurkin, Pavel Parkhomenko, Ekaterina Skachko,
Vadim Vlasov, Alexey Kolotnikov, Thomas Bogendoerfer,
Paul Burton, Ralf Baechle, Arnd Bergmann, Allison Randal,
Andy Shevchenko, Gareth Williams, Rob Herring, linux-mips,
linux-spi, devicetree, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 1866 bytes --]
On Wed, May 13, 2020 at 02:04:07PM +0300, Serge Semin wrote:
> On Wed, May 13, 2020 at 11:23:24AM +0100, Mark Brown wrote:
> > The conversion to YAML format should be the very last thing in the patch
> > series,
> Hm, haven't heard about this requirement. Could you point me out to a doc or
> some discussion concerning this for future reference? It's not a first DT
> conversion patch I've submitted and non of them were addressed with such
> request. I do understand that the order of DT concerning patches can be
> important and agree to fix it by updating the original legacy binding first,
> then perform a conversion. But placing the conversion in a tail of the series
> just seems unnecessary. The patch can be dropped from any place of the series
> if for some reason Rob would be late with review.
This is a practical observation based on the fact that there is a huge
backlog of reviews of DT binding conversions and that those conversions
typically go through several review cycles and that not everyone who's
sending patches to the kernel is fully up to speed on processes or has
strong English. By telling people (including other people who find
instructions on the list) to put the conversion right at the end of the
series I am avoiding any ambiguity or confusion about ordering with
regard to any other patches to the DT, including any new patches that
get added to the series.
> Personally I prefer placing all DT changes in the head of the series, so Rob
> wouldn't need to search through the whole patchset looking for the DT-related
> patches.
Ideally the YAML conversions would be done entirely separately to other
development rather than as part of a bigger series, they're pretty much
orthogonal anyway. Sadly there's obvious content collisions with any
new development that adds DT stuff so that's not always the most
practical thing.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH 00/17] spi: dw: Add generic DW DMA controller support
2020-05-13 11:21 ` Mark Brown
@ 2020-05-13 11:42 ` Serge Semin
0 siblings, 0 replies; 106+ messages in thread
From: Serge Semin @ 2020-05-13 11:42 UTC (permalink / raw)
To: Mark Brown
Cc: Serge Semin, Georgy Vlasov, Ramil Zaripov, Alexey Malahov,
Maxim Kaurkin, Pavel Parkhomenko, Ekaterina Skachko,
Vadim Vlasov, Alexey Kolotnikov, Thomas Bogendoerfer,
Paul Burton, Ralf Baechle, Arnd Bergmann, Allison Randal,
Andy Shevchenko, Gareth Williams, Rob Herring, linux-mips,
linux-spi, devicetree, linux-kernel
On Wed, May 13, 2020 at 12:21:16PM +0100, Mark Brown wrote:
> On Wed, May 13, 2020 at 02:04:07PM +0300, Serge Semin wrote:
> > On Wed, May 13, 2020 at 11:23:24AM +0100, Mark Brown wrote:
>
> > > The conversion to YAML format should be the very last thing in the patch
> > > series,
>
> > Hm, haven't heard about this requirement. Could you point me out to a doc or
> > some discussion concerning this for future reference? It's not a first DT
> > conversion patch I've submitted and non of them were addressed with such
> > request. I do understand that the order of DT concerning patches can be
> > important and agree to fix it by updating the original legacy binding first,
> > then perform a conversion. But placing the conversion in a tail of the series
> > just seems unnecessary. The patch can be dropped from any place of the series
> > if for some reason Rob would be late with review.
>
> This is a practical observation based on the fact that there is a huge
> backlog of reviews of DT binding conversions and that those conversions
> typically go through several review cycles and that not everyone who's
> sending patches to the kernel is fully up to speed on processes or has
> strong English. By telling people (including other people who find
> instructions on the list) to put the conversion right at the end of the
> series I am avoiding any ambiguity or confusion about ordering with
> regard to any other patches to the DT, including any new patches that
> get added to the series.
>
> > Personally I prefer placing all DT changes in the head of the series, so Rob
> > wouldn't need to search through the whole patchset looking for the DT-related
> > patches.
>
> Ideally the YAML conversions would be done entirely separately to other
> development rather than as part of a bigger series, they're pretty much
> orthogonal anyway. Sadly there's obvious content collisions with any
> new development that adds DT stuff so that's not always the most
> practical thing.
Ok. I see your point. I'll move the conversion patch to the tail of the series
after rebasing the patchset on top of the spi/for-next branch. Thanks for
clarification.
-Sergey
^ permalink raw reply [flat|nested] 106+ messages in thread
[parent not found: <20200508132943.9826-8-Sergey.Semin@baikalelectronics.ru>]
* Re: [PATCH 07/17] spi: dw: Add Tx/Rx finish wait methods to DMA
[not found] ` <20200508132943.9826-8-Sergey.Semin@baikalelectronics.ru>
@ 2020-05-08 17:30 ` Mark Brown
[not found] ` <20200513113555.mjivjk374giopnea@mobilestation>
0 siblings, 1 reply; 106+ messages in thread
From: Mark Brown @ 2020-05-08 17:30 UTC (permalink / raw)
To: Serge Semin
Cc: Serge Semin, Georgy Vlasov, Ramil Zaripov, Alexey Malahov,
Thomas Bogendoerfer, Paul Burton, Ralf Baechle, Arnd Bergmann,
Allison Randal, Andy Shevchenko, Gareth Williams, Rob Herring,
linux-mips, devicetree, Thomas Gleixner, wuxu.wu, Linus Walleij,
linux-spi, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 1150 bytes --]
On Fri, May 08, 2020 at 04:29:32PM +0300, Serge Semin wrote:
> Since DMA transfers are performed asynchronously with actual SPI
> transaction, then even if DMA transfers are finished it doesn't mean
> all data is actually pushed to the SPI bus. Some data might still be
This looks like a bug fix so it should really have gone at the start of
the series so it can be sent to Linus as a bug fix rather than waiting
for the merge window. This makes sense to me, a couple of nits below:
> +static void dw_spi_dma_wait_tx_done(struct dw_spi *dws)
> +{
> + int retry = WAIT_RETRIES;
> + unsigned long ns;
> +
> + ns = (NSEC_PER_SEC / spi_get_clk(dws)) * dws->n_bytes * BITS_PER_BYTE;
> + ns *= dw_readl(dws, DW_SPI_TXFLR);
> +
> + while (dw_spi_dma_tx_busy(dws) && retry--)
> + ndelay(ns);
How deep can the FIFO be with this IP - could we end up ndelay()ing for
non-trivial amounts of time?
> +static inline u32 spi_get_clk(struct dw_spi *dws)
> +{
> + u32 div = dw_readl(dws, DW_SPI_BAUDR);
> +
> + return div ? dws->max_freq / div : 0;
Please write normal conditional statements rather than using the ternery
operator - it helps with legibility.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH 00/17] spi: dw: Add generic DW DMA controller support
2020-05-08 13:29 [PATCH 00/17] spi: dw: Add generic DW DMA controller support Serge Semin
` (10 preceding siblings ...)
[not found] ` <20200508132943.9826-8-Sergey.Semin@baikalelectronics.ru>
@ 2020-05-08 17:36 ` Mark Brown
2020-05-08 19:16 ` Andy Shevchenko
2020-05-12 20:30 ` Serge Semin
[not found] ` <20200508132943.9826-15-Sergey.Semin@baikalelectronics.ru>
` (7 subsequent siblings)
19 siblings, 2 replies; 106+ messages in thread
From: Mark Brown @ 2020-05-08 17:36 UTC (permalink / raw)
To: Serge Semin
Cc: Serge Semin, Georgy Vlasov, Ramil Zaripov, Alexey Malahov,
Maxim Kaurkin, Pavel Parkhomenko, Ekaterina Skachko,
Vadim Vlasov, Alexey Kolotnikov, Thomas Bogendoerfer,
Paul Burton, Ralf Baechle, Arnd Bergmann, Allison Randal,
Andy Shevchenko, Gareth Williams, Rob Herring, linux-mips,
linux-spi, devicetree, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 498 bytes --]
On Fri, May 08, 2020 at 04:29:25PM +0300, Serge Semin wrote:
> Baikal-T1 SoC provides DW DMA controller to perform low-speed peripherals
> Mem-to-Dev and Dev-to-Mem transaction. This is also applicable to the DW
> APB SSI devices embedded into the SoC. Currently this type DMA device is
This basically all looks good to me (without any hardware specific
knowledge), I had a few comments but they were mostly procedural ones -
mainly getting these bug fixes you've done merged as such. Nice work.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH 00/17] spi: dw: Add generic DW DMA controller support
2020-05-08 17:36 ` [PATCH 00/17] spi: dw: Add generic DW DMA controller support Mark Brown
@ 2020-05-08 19:16 ` Andy Shevchenko
2020-05-12 20:34 ` Serge Semin
2020-05-12 20:30 ` Serge Semin
1 sibling, 1 reply; 106+ messages in thread
From: Andy Shevchenko @ 2020-05-08 19:16 UTC (permalink / raw)
To: Mark Brown
Cc: Serge Semin, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Maxim Kaurkin, Pavel Parkhomenko,
Ekaterina Skachko, Vadim Vlasov, Alexey Kolotnikov,
Thomas Bogendoerfer, Paul Burton, Ralf Baechle, Arnd Bergmann,
Allison Randal, Gareth Williams, Rob Herring, linux-mips,
linux-spi, devicetree, linux-kernel
On Fri, May 08, 2020 at 06:36:09PM +0100, Mark Brown wrote:
> On Fri, May 08, 2020 at 04:29:25PM +0300, Serge Semin wrote:
> > Baikal-T1 SoC provides DW DMA controller to perform low-speed peripherals
> > Mem-to-Dev and Dev-to-Mem transaction. This is also applicable to the DW
> > APB SSI devices embedded into the SoC. Currently this type DMA device is
>
> This basically all looks good to me (without any hardware specific
> knowledge), I had a few comments but they were mostly procedural ones -
> mainly getting these bug fixes you've done merged as such. Nice work.
Agree that is nice work!
Though, can you please give us chance to review next version of the series and test on our hardware?
Serge, I think you should base it on spi/for-next rather than vanilla.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH 00/17] spi: dw: Add generic DW DMA controller support
2020-05-08 19:16 ` Andy Shevchenko
@ 2020-05-12 20:34 ` Serge Semin
0 siblings, 0 replies; 106+ messages in thread
From: Serge Semin @ 2020-05-12 20:34 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Serge Semin, Mark Brown, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Maxim Kaurkin, Pavel Parkhomenko,
Ekaterina Skachko, Vadim Vlasov, Alexey Kolotnikov,
Thomas Bogendoerfer, Paul Burton, Ralf Baechle, Arnd Bergmann,
Allison Randal, Gareth Williams, Rob Herring, linux-mips,
linux-spi, devicetree, linux-kernel
On Fri, May 08, 2020 at 10:16:17PM +0300, Andy Shevchenko wrote:
> On Fri, May 08, 2020 at 06:36:09PM +0100, Mark Brown wrote:
> > On Fri, May 08, 2020 at 04:29:25PM +0300, Serge Semin wrote:
> > > Baikal-T1 SoC provides DW DMA controller to perform low-speed peripherals
> > > Mem-to-Dev and Dev-to-Mem transaction. This is also applicable to the DW
> > > APB SSI devices embedded into the SoC. Currently this type DMA device is
> >
> > This basically all looks good to me (without any hardware specific
> > knowledge), I had a few comments but they were mostly procedural ones -
> > mainly getting these bug fixes you've done merged as such. Nice work.
>
> Agree that is nice work!
> Though, can you please give us chance to review next version of the series and test on our hardware?
>
> Serge, I think you should base it on spi/for-next rather than vanilla.
Yeah, seeing there are potentially merge-conflict changes in the for-next
branch I have to do the rebase. Will be done in v2.
-Sergey
>
> --
> With Best Regards,
> Andy Shevchenko
>
>
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH 00/17] spi: dw: Add generic DW DMA controller support
2020-05-08 17:36 ` [PATCH 00/17] spi: dw: Add generic DW DMA controller support Mark Brown
2020-05-08 19:16 ` Andy Shevchenko
@ 2020-05-12 20:30 ` Serge Semin
1 sibling, 0 replies; 106+ messages in thread
From: Serge Semin @ 2020-05-12 20:30 UTC (permalink / raw)
To: Mark Brown
Cc: Serge Semin, Georgy Vlasov, Ramil Zaripov, Alexey Malahov,
Maxim Kaurkin, Pavel Parkhomenko, Ekaterina Skachko,
Vadim Vlasov, Alexey Kolotnikov, Thomas Bogendoerfer,
Paul Burton, Ralf Baechle, Arnd Bergmann, Allison Randal,
Andy Shevchenko, Gareth Williams, Rob Herring, linux-mips,
linux-spi, devicetree, linux-kernel
On Fri, May 08, 2020 at 06:36:09PM +0100, Mark Brown wrote:
> On Fri, May 08, 2020 at 04:29:25PM +0300, Serge Semin wrote:
> > Baikal-T1 SoC provides DW DMA controller to perform low-speed peripherals
> > Mem-to-Dev and Dev-to-Mem transaction. This is also applicable to the DW
> > APB SSI devices embedded into the SoC. Currently this type DMA device is
>
> This basically all looks good to me (without any hardware specific
> knowledge), I had a few comments but they were mostly procedural ones -
> mainly getting these bug fixes you've done merged as such. Nice work.
Thanks. I'll address the Andy's comments and send v2 after that.
-Sergey
^ permalink raw reply [flat|nested] 106+ messages in thread
[parent not found: <20200508132943.9826-15-Sergey.Semin@baikalelectronics.ru>]
* Re: [PATCH 14/17] spi: dw: Add DMA support to the DW SPI MMIO driver
[not found] ` <20200508132943.9826-15-Sergey.Semin@baikalelectronics.ru>
@ 2020-05-08 19:23 ` Andy Shevchenko
0 siblings, 0 replies; 106+ messages in thread
From: Andy Shevchenko @ 2020-05-08 19:23 UTC (permalink / raw)
To: Serge Semin
Cc: Mark Brown, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Arnd Bergmann, Allison Randal, Gareth Williams, Rob Herring,
linux-mips, devicetree, John Garry, Chuanhong Guo,
Krzysztof Kozlowski, Geert Uytterhoeven, Chris Packham,
Tomer Maimon, Masahisa Kojima, Florian Fainelli, Thomas Gleixner,
Stephen Boyd, Jarkko Nikula, Phil Edworthy, YueHaibing,
Linus Walleij, wuxu.wu, linux-spi, linux-kernel
On Fri, May 08, 2020 at 04:29:39PM +0300, Serge Semin wrote:
> Since the common code in the spi-dw-dma.c driver is ready to be used
> by the MMIO driver, we just need to initialize the DW SPI private data
> fields with Tx/Rx DMA channel handlers and setup the DW SPI DMA
> callbacks. This commit introduces such alterations to the DW SPI
> DMA/MMIO code. A dedicated DW SPI MMIO DMA initializer performs the
> DMA channels request from the parental device (which is supposed to be
> a DW SPI platform device). Then it checks whether the retrieved DW DMA
> channels support LLP. If they don't currently we print a warning, that
> further DMA usage may be finished with DW SPI inbound FIFO overflow
> (nothing else we can do about it at the moment). Finally the DW SPI
> MMIO DMA initializer sets the DMA-inited flag.
>
> Currently the DMA will be initialized only for a generic DW SPI MMIO
> device declared with "snps,dw-apb-ssi" compatible string if SPI_DW_DMA
> kernel config is enabled.
Already in spi/for-next (see for generic suffix in spi-dw-mid.c).
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 106+ messages in thread
[parent not found: <20200508132943.9826-17-Sergey.Semin@baikalelectronics.ru>]
* Re: [PATCH 16/17] spi: dw: Fix Rx-only DMA transfers
[not found] ` <20200508132943.9826-17-Sergey.Semin@baikalelectronics.ru>
@ 2020-05-08 19:27 ` Andy Shevchenko
0 siblings, 0 replies; 106+ messages in thread
From: Andy Shevchenko @ 2020-05-08 19:27 UTC (permalink / raw)
To: Serge Semin
Cc: Mark Brown, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Arnd Bergmann, Allison Randal, Gareth Williams, Rob Herring,
linux-mips, devicetree, Linus Walleij, Greg Kroah-Hartman,
Xinwei Kong, Thor Thayer, Charles Keepax, wuxu.wu, Phil Edworthy,
Thomas Gleixner, Jarkko Nikula, linux-spi, linux-kernel
On Fri, May 08, 2020 at 04:29:41PM +0300, Serge Semin wrote:
> Tx-only DMA transfers are working perfectly fine since in this case
> the code just ignores the Rx FIFO overflow interrupts. But it turns
> out the SPI Rx-only transfers are broken since nothing pushing any
> data to the shift registers, so the Rx FIFO is left empty and the
> SPI core subsystems just returns a timeout error. Since DW DMAC
> driver doesn't support something like cyclic write operations of
> a single byte to a device register, the only way to support the
> Rx-only SPI transfers is to fake it by using a dummy Tx-buffer.
> This is what we intend to fix in this commit by setting the
> SPI_CONTROLLER_MUST_TX flag for DMA-capable platform.
Hmm... If Mark consider this a right thing to do, then it's fine.
I didn't investigate what this flag may produce as a side effect.
> --- a/drivers/spi/spi-dw.c
> +++ b/drivers/spi/spi-dw.c
> @@ -524,6 +524,7 @@ int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
> dws->dma_inited = 0;
> } else {
> master->can_dma = dws->dma_ops->can_dma;
> + master->flags |= SPI_CONTROLLER_MUST_TX;
> }
> }
>
> --
> 2.25.1
>
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 106+ messages in thread
[parent not found: <20200508132943.9826-18-Sergey.Semin@baikalelectronics.ru>]
* Re: [PATCH 17/17] spi: dw: Use regset32 DebugFS method to create a registers file
[not found] ` <20200508132943.9826-18-Sergey.Semin@baikalelectronics.ru>
@ 2020-05-08 19:30 ` Andy Shevchenko
[not found] ` <20200513124422.z6ctlmvipwer45q4@mobilestation>
0 siblings, 1 reply; 106+ messages in thread
From: Andy Shevchenko @ 2020-05-08 19:30 UTC (permalink / raw)
To: Serge Semin
Cc: Mark Brown, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Arnd Bergmann, Allison Randal, Gareth Williams, Rob Herring,
linux-mips, devicetree, fengsheng, Phil Edworthy,
Thomas Gleixner, Xinwei Kong, Aditya Pakki, wuxu.wu,
Charles Keepax, Jarkko Nikula, Linus Walleij, linux-spi,
linux-kernel
On Fri, May 08, 2020 at 04:29:42PM +0300, Serge Semin wrote:
> DebugFS kernel interface provides a dedicated method to create the
> registers dump file. Use it instead of creating a generic DebugFS
> file with manually written read callback function.
Of course ideal would be use something like regmap API which delivers this as a side effect.
But this also good clean up!
Comments below.
>
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Cc: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
> Cc: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> Cc: Paul Burton <paulburton@kernel.org>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Allison Randal <allison@lohutok.net>
> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Cc: Gareth Williams <gareth.williams.jx@renesas.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: linux-mips@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> ---
> drivers/spi/spi-dw.c | 85 +++++++++++++-------------------------------
> drivers/spi/spi-dw.h | 2 ++
> 2 files changed, 27 insertions(+), 60 deletions(-)
>
> diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c
> index 897c998af578..625a5f152e1a 100644
> --- a/drivers/spi/spi-dw.c
> +++ b/drivers/spi/spi-dw.c
> @@ -32,66 +32,28 @@ struct chip_data {
> };
>
> #ifdef CONFIG_DEBUG_FS
> -#define SPI_REGS_BUFSIZE 1024
> -static ssize_t dw_spi_show_regs(struct file *file, char __user *user_buf,
> - size_t count, loff_t *ppos)
> -{
> - struct dw_spi *dws = file->private_data;
> - char *buf;
> - u32 len = 0;
> - ssize_t ret;
> -
> - buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
> - if (!buf)
> - return 0;
> -
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "%s registers:\n", dev_name(&dws->master->dev));
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "=================================\n");
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "CTRL0: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL0));
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "CTRL1: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL1));
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR));
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "SER: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SER));
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR));
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFLTR));
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFLTR));
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR));
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "RXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_RXFLR));
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "SR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SR));
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "IMR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_IMR));
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "ISR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_ISR));
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "DMACR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_DMACR));
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "DMATDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMATDLR));
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "DMARDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMARDLR));
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "=================================\n");
> -
> - ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
> - kfree(buf);
> - return ret;
> +#define DW_SPI_DBGFS_REG(_name, _off) \
> +{ \
> + .name = _name, \
> + .offset = _off \
Leave comma here.
> }
>
> -static const struct file_operations dw_spi_regs_ops = {
> - .owner = THIS_MODULE,
> - .open = simple_open,
> - .read = dw_spi_show_regs,
> - .llseek = default_llseek,
> +static const struct debugfs_reg32 dw_spi_dbgfs_regs[] = {
> + DW_SPI_DBGFS_REG("CTRL0", DW_SPI_CTRL0),
> + DW_SPI_DBGFS_REG("CTRL1", DW_SPI_CTRL1),
> + DW_SPI_DBGFS_REG("SSIENR", DW_SPI_SSIENR),
> + DW_SPI_DBGFS_REG("SER", DW_SPI_SER),
> + DW_SPI_DBGFS_REG("BAUDR", DW_SPI_BAUDR),
> + DW_SPI_DBGFS_REG("TXFTLR", DW_SPI_TXFLTR),
> + DW_SPI_DBGFS_REG("RXFTLR", DW_SPI_RXFLTR),
> + DW_SPI_DBGFS_REG("TXFLR", DW_SPI_TXFLR),
> + DW_SPI_DBGFS_REG("RXFLR", DW_SPI_RXFLR),
> + DW_SPI_DBGFS_REG("SR", DW_SPI_SR),
> + DW_SPI_DBGFS_REG("IMR", DW_SPI_IMR),
> + DW_SPI_DBGFS_REG("ISR", DW_SPI_ISR),
> + DW_SPI_DBGFS_REG("DMACR", DW_SPI_DMACR),
> + DW_SPI_DBGFS_REG("DMATDLR", DW_SPI_DMATDLR),
> + DW_SPI_DBGFS_REG("DMARDLR", DW_SPI_DMARDLR)
> };
>
> static int dw_spi_debugfs_init(struct dw_spi *dws)
> @@ -103,8 +65,11 @@ static int dw_spi_debugfs_init(struct dw_spi *dws)
> if (!dws->debugfs)
> return -ENOMEM;
>
> - debugfs_create_file("registers", S_IFREG | S_IRUGO,
> - dws->debugfs, (void *)dws, &dw_spi_regs_ops);
> + dws->regset.regs = dw_spi_dbgfs_regs;
> + dws->regset.nregs = ARRAY_SIZE(dw_spi_dbgfs_regs);
> + dws->regset.base = dws->regs;
> + debugfs_create_regset32("registers", 0400, dws->debugfs, &dws->regset);
> +
> return 0;
> }
>
> diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
> index a6c03ea9013c..bad0eca2efe6 100644
> --- a/drivers/spi/spi-dw.h
> +++ b/drivers/spi/spi-dw.h
> @@ -4,6 +4,7 @@
>
> #include <linux/io.h>
> #include <linux/scatterlist.h>
> +#include <linux/debugfs.h>
Perhaps keep ordered?
>
> /* Register offsets */
> #define DW_SPI_CTRL0 0x00
> @@ -142,6 +143,7 @@ struct dw_spi {
> void *priv;
> #ifdef CONFIG_DEBUG_FS
> struct dentry *debugfs;
> + struct debugfs_regset32 regset;
I'm wondering why we need it here and not simple on the stack?
> #endif
> };
>
> --
> 2.25.1
>
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH 00/17] spi: dw: Add generic DW DMA controller support
2020-05-08 13:29 [PATCH 00/17] spi: dw: Add generic DW DMA controller support Serge Semin
` (14 preceding siblings ...)
[not found] ` <20200508132943.9826-18-Sergey.Semin@baikalelectronics.ru>
@ 2020-05-08 19:33 ` Andy Shevchenko
[not found] ` <20200508132943.9826-12-Sergey.Semin@baikalelectronics.ru>
` (3 subsequent siblings)
19 siblings, 0 replies; 106+ messages in thread
From: Andy Shevchenko @ 2020-05-08 19:33 UTC (permalink / raw)
To: Serge Semin
Cc: Mark Brown, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Maxim Kaurkin, Pavel Parkhomenko,
Ekaterina Skachko, Vadim Vlasov, Alexey Kolotnikov,
Thomas Bogendoerfer, Paul Burton, Ralf Baechle, Arnd Bergmann,
Allison Randal, Gareth Williams, Rob Herring, linux-mips,
linux-spi, devicetree, linux-kernel
On Fri, May 08, 2020 at 04:29:25PM +0300, Serge Semin wrote:
> Baikal-T1 SoC provides DW DMA controller to perform low-speed peripherals
> Mem-to-Dev and Dev-to-Mem transaction. This is also applicable to the DW
> APB SSI devices embedded into the SoC. Currently this type DMA device is
> supported by the DW APB SPI driver only as a middle layer code for Intel
> MID PCI devices. Seeing the same code can be used for normal platform
> DW DMAC device we introduced a set of patches to fix it within this
> patchset.
>
> First of all traditionally we replaced the legacy plain text-based dt-binding
> file with yaml-based one. Then we unpinned the Intel MID specific code from
> the generic DMA one and placed it into the spi-dw-pci.c driver, which was a
> better place for it anyway. Then we introduced a set of naming cleanups since
> the code was going to be used for generic DW DMAC device and DMAC usage
> alterations to handle the controller functionality in a generic way by the
> DW APB SSI MMIO driver as well. See the individual patches commit messages
> for details.
>
> In addition we fixed a problem in the native chip-select method, which despite
> of multiple attempts to be fixed doesn't correctly perceive the SPI_CS_HIGH
> flag and the enable-argument.
>
> Finally as a cherry on a cake we replaced the manually written DebugFS
> registers read method with a ready-to-use for the same purpose regset32
> DebugFS interface usage.
Thanks! Appreciate the series (some of the things I would like to have done
myself, but lack of time and no specific request from our hardware).
Though, I will wait for v2 rebased on top of spi/for-next and I will review the
rest of the patches (mostly those I haven't commented out).
> This patchset is rebased and tested on the mainline Linux kernel 5.7-rc4:
> 0e698dfa2822 ("Linux 5.7-rc4")
> tag: v5.7-rc4
Perhaps --base will do the trick?
>
> Co-developed-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
> Signed-off-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
> Co-developed-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
> Signed-off-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: Maxim Kaurkin <Maxim.Kaurkin@baikalelectronics.ru>
> Cc: Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>
> Cc: Ekaterina Skachko <Ekaterina.Skachko@baikalelectronics.ru>
> Cc: Vadim Vlasov <V.Vlasov@baikalelectronics.ru>
> Cc: Alexey Kolotnikov <Alexey.Kolotnikov@baikalelectronics.ru>
> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> Cc: Paul Burton <paulburton@kernel.org>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Allison Randal <allison@lohutok.net>
> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Cc: Gareth Williams <gareth.williams.jx@renesas.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: linux-mips@vger.kernel.org
> Cc: linux-spi@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
>
> Serge Semin (17):
> dt-bindings: spi: Convert DW SPI binding to DT schema
> dt-bindings: spi: dw: Add DMA properties bindings
> spi: dw: Split up the generic DMA code and Intel MID driver
> spi: dw: Cleanup generic DW DMA code namings
> spi: dw: Discard static DW DMA slave structures
> spi: dw: Add DW SPI DMA/PCI/MMIO dependency on DW SPI core
> spi: dw: Add Tx/Rx finish wait methods to DMA
> spi: dw: Clear DMAC register when done or stopped
> spi: dw: Enable interrupts in accordance with DMA xfer mode
> spi: dw: Parameterize the DMA Rx/Tx burst length
> spi: dw: Fix native CS being unset
> spi: dw: Fix dma_slave_config used partly uninitialized
> spi: dw: Initialize paddr in DW SPI MMIO private data
> spi: dw: Add DMA support to the DW SPI MMIO driver
> spi: dw: Use DMA max burst to set the request thresholds
> spi: dw: Fix Rx-only DMA transfers
> spi: dw: Use regset32 DebugFS method to create a registers file
>
> .../bindings/spi/snps,dw-apb-ssi.txt | 41 ---
> .../bindings/spi/snps,dw-apb-ssi.yaml | 123 +++++++++
> .../devicetree/bindings/spi/spi-dw.txt | 24 --
> drivers/spi/Kconfig | 16 +-
> drivers/spi/Makefile | 4 +-
> drivers/spi/{spi-dw-mid.c => spi-dw-dma.c} | 237 ++++++++++++------
> drivers/spi/spi-dw-mmio.c | 15 +-
> drivers/spi/spi-dw-pci.c | 38 ++-
> drivers/spi/spi-dw.c | 89 +++----
> drivers/spi/spi-dw.h | 27 +-
> 10 files changed, 402 insertions(+), 212 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
> create mode 100644 Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> delete mode 100644 Documentation/devicetree/bindings/spi/spi-dw.txt
> rename drivers/spi/{spi-dw-mid.c => spi-dw-dma.c} (53%)
>
> --
> 2.25.1
>
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 106+ messages in thread
[parent not found: <20200508132943.9826-12-Sergey.Semin@baikalelectronics.ru>]
* Re: [PATCH 11/17] spi: dw: Fix native CS being unset
[not found] ` <20200508132943.9826-12-Sergey.Semin@baikalelectronics.ru>
@ 2020-05-08 19:39 ` Linus Walleij
[not found] ` <20200513001347.dyt357erev7vzy3l@mobilestation>
0 siblings, 1 reply; 106+ messages in thread
From: Linus Walleij @ 2020-05-08 19:39 UTC (permalink / raw)
To: Serge Semin, Gregory Clement
Cc: Mark Brown, Charles Keepax, Serge Semin, Georgy Vlasov,
Ramil Zaripov, Alexey Malahov, Thomas Bogendoerfer, Paul Burton,
Ralf Baechle, Arnd Bergmann, Allison Randal, Andy Shevchenko,
Gareth Williams, Rob Herring, linux-mips,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Phil Edworthy, Thomas Gleixner, Alexios Zavras, Thor Thayer,
wuxu.wu, Xinwei Kong, Jarkko Nikula, linux-spi, linux-kernel
On Fri, May 8, 2020 at 3:31 PM Serge Semin
<Sergey.Semin@baikalelectronics.ru> wrote:
> Commit 6e0a32d6f376 ("spi: dw: Fix default polarity of native
> chipselect") attempted to fix the problem when GPIO active-high
> chip-select is utilized to communicate with some SPI slave. It fixed
> the problem, but broke the normal native CS support. At the same time
> the reversion commit ada9e3fcc175 ("spi: dw: Correct handling of native
> chipselect") didn't solve the problem either, since it just inverted
> the set_cs() polarity perception without taking into account that
> CS-high might be applicable. Here is what is done to finally fix the
> problem.
I'm not sure this is the whole story.
I think Charles' fix made it work, and then commit
3e5ec1db8bfee845d9f8560d1c64aeaccd586398
"spi: Fix SPI_CS_HIGH setting when using native and GPIO CS"
fixed it broken again.
This commit will make sure only set SPI_CS_HIGH on a
spi_device if it is using a GPIO as CS. Before this change,
the core would set that on everything, and expect the
.set_cs() callback to cope.
I think we fixed that and that fix should have been undone
when applying commit 3e5ec1db8bfe.
So possibly Fixes: should be set only to this commit, so
that the fix is not backported to kernels without it.
> DW SPI controller demands any native CS being set in order to proceed
> with data transfer. So in order to activate the SPI communications we
> must set any bit in the Slave Select DW SPI controller register no
> matter whether the platform requests the GPIO- or native CS.
Ah-ha! Maybe we should even add a comment explaining that.
And that is why SPI_MASTER_GPIO_SS is set.
I suppose my naive understanding was:
"bit set to 1" = CS asserted (driven low)
"bit set to 0" = CS de-asserted (driven high)
So that is not how this register works at all.
> This commit fixes the problem for all described cases. So no matter
> whether an SPI slave needs GPIO- or native-based CS with active-high
> or low signal the corresponding bit will be set in SER.
Makes sense.
> struct dw_spi *dws = spi_controller_get_devdata(spi->controller);
> struct chip_data *chip = spi_get_ctldata(spi);
> + bool cs_high = !!(spi->mode & SPI_CS_HIGH);
>
> /* Chip select logic is inverted from spi_set_cs() */
> if (chip && chip->cs_control)
> chip->cs_control(!enable);
>
> - if (!enable)
> + if (cs_high == enable)
> dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select));
This is the correct fix now but I an afraid not correct before
commit 3e5ec1db8bfe.
What I can't help but asking is: can the native chip select even
handle active high chip select if not backed by a GPIO?
Which register would set that polarity?
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 106+ messages in thread
[parent not found: <20200508132943.9826-4-Sergey.Semin@baikalelectronics.ru>]
* Re: [PATCH 03/17] spi: dw: Split up the generic DMA code and Intel MID driver
[not found] ` <20200508132943.9826-4-Sergey.Semin@baikalelectronics.ru>
@ 2020-05-08 19:41 ` Andy Shevchenko
0 siblings, 0 replies; 106+ messages in thread
From: Andy Shevchenko @ 2020-05-08 19:41 UTC (permalink / raw)
To: Serge Semin
Cc: Mark Brown, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Rob Herring, Arnd Bergmann, Allison Randal, Gareth Williams,
linux-mips, devicetree, John Garry, Chuanhong Guo,
Krzysztof Kozlowski, Gregory CLEMENT, Chris Packham,
Masahisa Kojima, Tomer Maimon, Florian Fainelli, Jassi Brar,
Eddie James, Alexios Zavras, Thomas Gleixner, Greg Kroah-Hartman,
Jarkko Nikula, Raymond Tan, Chuhong Yuan, Felipe Balbi,
Linus Walleij, wuxu.wu, linux-spi, linux-kernel
On Fri, May 08, 2020 at 04:29:28PM +0300, Serge Semin wrote:
> This is an initial preparation patch before adding the DW DMA support
> into the DW SPI MMIO driver. We need to unpin the DMA-specific code
> from the code intended to be used for Intel MID. This isn't that hard,
> since most part of the spi-dw-mid.c driver in fact implements a generic
> DW DMA interface for the DW SPI controller driver. The only Intel MID
> specifics concern getting the max frequency from the MRST Clock
> Control Unit and fetching the DMA controller channels from
> corresponding PCIe DMA controller. Since first one is related with the
> SPI interface configuration we moved it' implementation into the
> DW PCIe-SPI driver object. While seeing there is no other than Medfield
> board with DW DMA controller currently supported we left the DMA
> channels search procedure in the DW SPI DMA module. After being
> cleaned up of the Intel MID specifics former spi-dw-mid.c module
> can be just renamed to be the DW SPI DMA driver.
And I guess this already been done in spi/for-next in less invasive way.
>
> Co-developed-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
> Signed-off-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
> Co-developed-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
> Signed-off-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> Cc: Paul Burton <paulburton@kernel.org>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Allison Randal <allison@lohutok.net>
> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Cc: Gareth Williams <gareth.williams.jx@renesas.com>
> Cc: linux-mips@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> ---
> drivers/spi/Kconfig | 8 ++---
> drivers/spi/Makefile | 4 +--
> drivers/spi/{spi-dw-mid.c => spi-dw-dma.c} | 36 ++------------------
> drivers/spi/spi-dw-pci.c | 38 ++++++++++++++++++++--
> drivers/spi/spi-dw.h | 12 +++++--
> 5 files changed, 55 insertions(+), 43 deletions(-)
> rename drivers/spi/{spi-dw-mid.c => spi-dw-dma.c} (88%)
>
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index 741b9140992a..9653c7f271e9 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -226,14 +226,14 @@ config SPI_DESIGNWARE
> help
> general driver for SPI controller core from DesignWare
>
> +config SPI_DW_DMA
> + tristate "DMA support for DW SPI controller"
> + depends on SPI_DESIGNWARE && DW_DMAC_PCI
> +
> config SPI_DW_PCI
> tristate "PCI interface driver for DW SPI core"
> depends on SPI_DESIGNWARE && PCI
>
> -config SPI_DW_MID_DMA
> - bool "DMA support for DW SPI controller on Intel MID platform"
> - depends on SPI_DW_PCI && DW_DMAC_PCI
> -
> config SPI_DW_MMIO
> tristate "Memory-mapped io interface driver for DW SPI core"
> depends on SPI_DESIGNWARE
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> index 28f601327f8c..15eb760412a9 100644
> --- a/drivers/spi/Makefile
> +++ b/drivers/spi/Makefile
> @@ -36,9 +36,9 @@ obj-$(CONFIG_SPI_COLDFIRE_QSPI) += spi-coldfire-qspi.o
> obj-$(CONFIG_SPI_DAVINCI) += spi-davinci.o
> obj-$(CONFIG_SPI_DLN2) += spi-dln2.o
> obj-$(CONFIG_SPI_DESIGNWARE) += spi-dw.o
> +obj-$(CONFIG_SPI_DW_DMA) += spi-dw-dma.o
> obj-$(CONFIG_SPI_DW_MMIO) += spi-dw-mmio.o
> -obj-$(CONFIG_SPI_DW_PCI) += spi-dw-midpci.o
> -spi-dw-midpci-objs := spi-dw-pci.o spi-dw-mid.o
> +obj-$(CONFIG_SPI_DW_PCI) += spi-dw-pci.o
> obj-$(CONFIG_SPI_EFM32) += spi-efm32.o
> obj-$(CONFIG_SPI_EP93XX) += spi-ep93xx.o
> obj-$(CONFIG_SPI_FALCON) += spi-falcon.o
> diff --git a/drivers/spi/spi-dw-mid.c b/drivers/spi/spi-dw-dma.c
> similarity index 88%
> rename from drivers/spi/spi-dw-mid.c
> rename to drivers/spi/spi-dw-dma.c
> index 0d86c37e0aeb..0230b4252611 100644
> --- a/drivers/spi/spi-dw-mid.c
> +++ b/drivers/spi/spi-dw-dma.c
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0-only
> /*
> - * Special handling for DW core on Intel MID platform
> + * Special handling for DW DMA core
> *
> * Copyright (c) 2009, 2014 Intel Corporation.
> */
> @@ -14,7 +14,6 @@
>
> #include "spi-dw.h"
>
> -#ifdef CONFIG_SPI_DW_MID_DMA
> #include <linux/pci.h>
> #include <linux/platform_data/dma-dw.h>
>
> @@ -283,40 +282,11 @@ static const struct dw_spi_dma_ops mid_dma_ops = {
> .dma_transfer = mid_spi_dma_transfer,
> .dma_stop = mid_spi_dma_stop,
> };
> -#endif
>
> -/* Some specific info for SPI0 controller on Intel MID */
> -
> -/* HW info for MRST Clk Control Unit, 32b reg per controller */
> -#define MRST_SPI_CLK_BASE 100000000 /* 100m */
> -#define MRST_CLK_SPI_REG 0xff11d86c
> -#define CLK_SPI_BDIV_OFFSET 0
> -#define CLK_SPI_BDIV_MASK 0x00000007
> -#define CLK_SPI_CDIV_OFFSET 9
> -#define CLK_SPI_CDIV_MASK 0x00000e00
> -#define CLK_SPI_DISABLE_OFFSET 8
> -
> -int dw_spi_mid_init(struct dw_spi *dws)
> +void dw_spi_pci_dma_setup(struct dw_spi *dws)
> {
> - void __iomem *clk_reg;
> - u32 clk_cdiv;
> -
> - clk_reg = ioremap(MRST_CLK_SPI_REG, 16);
> - if (!clk_reg)
> - return -ENOMEM;
> -
> - /* Get SPI controller operating freq info */
> - clk_cdiv = readl(clk_reg + dws->bus_num * sizeof(u32));
> - clk_cdiv &= CLK_SPI_CDIV_MASK;
> - clk_cdiv >>= CLK_SPI_CDIV_OFFSET;
> - dws->max_freq = MRST_SPI_CLK_BASE / (clk_cdiv + 1);
> -
> - iounmap(clk_reg);
> -
> -#ifdef CONFIG_SPI_DW_MID_DMA
> dws->dma_tx = &mid_dma_tx;
> dws->dma_rx = &mid_dma_rx;
> dws->dma_ops = &mid_dma_ops;
> -#endif
> - return 0;
> }
> +EXPORT_SYMBOL_GPL(dw_spi_pci_dma_setup);
> diff --git a/drivers/spi/spi-dw-pci.c b/drivers/spi/spi-dw-pci.c
> index 12c131b5fb4e..068f6897b903 100644
> --- a/drivers/spi/spi-dw-pci.c
> +++ b/drivers/spi/spi-dw-pci.c
> @@ -16,6 +16,17 @@
>
> #define DRIVER_NAME "dw_spi_pci"
>
> +/* HW info for MRST Clk Control Unit, 32b reg per controller */
> +#define MRST_SPI_CLK_BASE 100000000 /* 100m */
> +#define MRST_CLK_SPI_REG 0xff11d86c
> +#define CLK_SPI_BDIV_OFFSET 0
> +#define CLK_SPI_BDIV_MASK 0x00000007
> +#define CLK_SPI_CDIV_OFFSET 9
> +#define CLK_SPI_CDIV_MASK 0x00000e00
> +#define CLK_SPI_DISABLE_OFFSET 8
> +
> +static int spi_mid_init(struct dw_spi *dws);
> +
> struct spi_pci_desc {
> int (*setup)(struct dw_spi *);
> u16 num_cs;
> @@ -24,13 +35,13 @@ struct spi_pci_desc {
> };
>
> static struct spi_pci_desc spi_pci_mid_desc_1 = {
> - .setup = dw_spi_mid_init,
> + .setup = spi_mid_init,
> .num_cs = 5,
> .bus_num = 0,
> };
>
> static struct spi_pci_desc spi_pci_mid_desc_2 = {
> - .setup = dw_spi_mid_init,
> + .setup = spi_mid_init,
> .num_cs = 2,
> .bus_num = 1,
> };
> @@ -41,6 +52,29 @@ static struct spi_pci_desc spi_pci_ehl_desc = {
> .max_freq = 100000000,
> };
>
> +/* Some specific info for SPI0 controller on Intel MID */
> +static int spi_mid_init(struct dw_spi *dws)
> +{
> + void __iomem *clk_reg;
> + u32 clk_cdiv;
> +
> + clk_reg = ioremap(MRST_CLK_SPI_REG, 16);
> + if (!clk_reg)
> + return -ENOMEM;
> +
> + /* Get SPI controller operating freq info */
> + clk_cdiv = readl(clk_reg + dws->bus_num * sizeof(u32));
> + clk_cdiv &= CLK_SPI_CDIV_MASK;
> + clk_cdiv >>= CLK_SPI_CDIV_OFFSET;
> + dws->max_freq = MRST_SPI_CLK_BASE / (clk_cdiv + 1);
> +
> + iounmap(clk_reg);
> +
> + dw_spi_pci_dma_setup(dws);
> +
> + return 0;
> +}
> +
> static int spi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
> {
> struct dw_spi *dws;
> diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
> index 1bf5713e047d..0a4e0890ef85 100644
> --- a/drivers/spi/spi-dw.h
> +++ b/drivers/spi/spi-dw.h
> @@ -253,6 +253,14 @@ extern void dw_spi_remove_host(struct dw_spi *dws);
> extern int dw_spi_suspend_host(struct dw_spi *dws);
> extern int dw_spi_resume_host(struct dw_spi *dws);
>
> -/* platform related setup */
> -extern int dw_spi_mid_init(struct dw_spi *dws); /* Intel MID platforms */
> +#ifdef CONFIG_SPI_DW_DMA
> +
> +extern void dw_spi_pci_dma_setup(struct dw_spi *dws);
> +
> +#else /* !CONFIG_SPI_DW_DMA */
> +
> +static inline void dw_spi_pci_dma_setup(struct dw_spi *dws) {}
> +
> +#endif /* !CONFIG_SPI_DW_DMA */
> +
> #endif /* DW_SPI_HEADER_H */
> --
> 2.25.1
>
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 106+ messages in thread
[parent not found: <20200508132943.9826-6-Sergey.Semin@baikalelectronics.ru>]
* Re: [PATCH 05/17] spi: dw: Discard static DW DMA slave structures
[not found] ` <20200508132943.9826-6-Sergey.Semin@baikalelectronics.ru>
@ 2020-05-08 19:44 ` Andy Shevchenko
0 siblings, 0 replies; 106+ messages in thread
From: Andy Shevchenko @ 2020-05-08 19:44 UTC (permalink / raw)
To: Serge Semin
Cc: Mark Brown, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Allison Randal, Gareth Williams, Arnd Bergmann, Rob Herring,
linux-mips, devicetree, Thomas Gleixner, wuxu.wu, Linus Walleij,
linux-spi, linux-kernel
On Fri, May 08, 2020 at 04:29:30PM +0300, Serge Semin wrote:
> Having them declared is redundant since each struct dw_dma_chan has
> the same structure embedded and the structure from the passed dma_chan
> private pointer will be copied there as a result of the next calls
> chain:
> dma_request_channel() -> find_candidate() -> dma_chan_get() ->
> device_alloc_chan_resources() = dwc_alloc_chan_resources() ->
> dw_dma_filter().
> So just remove the static dw_dma_chan structures and use a locally
> declared data instance with dst_id/src_id set to the same values as
> the static copies used to have.
I'm not against it, but you may leave if for the future (see spi/for-next).
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 106+ messages in thread
* [PATCH v2 00/19] spi: dw: Add generic DW DMA controller support
2020-05-08 13:29 [PATCH 00/17] spi: dw: Add generic DW DMA controller support Serge Semin
` (18 preceding siblings ...)
[not found] ` <20200508132943.9826-6-Sergey.Semin@baikalelectronics.ru>
@ 2020-05-15 10:47 ` Serge Semin
2020-05-15 10:47 ` [PATCH v2 01/19] dt-bindings: spi: dw: Add Tx/Rx DMA properties Serge Semin
` (19 more replies)
19 siblings, 20 replies; 106+ messages in thread
From: Serge Semin @ 2020-05-15 10:47 UTC (permalink / raw)
To: Mark Brown
Cc: Serge Semin, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Maxim Kaurkin, Pavel Parkhomenko,
Ekaterina Skachko, Vadim Vlasov, Alexey Kolotnikov,
Thomas Bogendoerfer, Paul Burton, Ralf Baechle, Arnd Bergmann,
Allison Randal, Andy Shevchenko, Gareth Williams, Rob Herring,
linux-mips, linux-spi, devicetree, linux-kernel
Baikal-T1 SoC provides a DW DMA controller to perform low-speed peripherals
Mem-to-Dev and Dev-to-Mem transaction. This is also applicable to the DW
APB SSI devices embedded into the SoC. Currently the DMA-based transfers
are supported by the DW APB SPI driver only as a middle layer code for
Intel MID/Elkhart PCI devices. Seeing the same code can be used for normal
platform DMAC device we introduced a set of patches to fix it within this
series.
First of all we need to add the Tx and Rx DMA channels support into the DW
APB SSI binding. Then there are several fixes and cleanups provided as a
initial preparation for the Generic DMA support integration: add Tx/Rx
finish wait methods, clear DMAC register when done or stopped, Fix native
CS being unset, enable interrupts in accordance with DMA xfer mode,
discard static DW DMA slave structures, discard unused void priv pointer
and dma_width member of the dw_spi structure, provide the DMA Tx/Rx burst
length parametrisation and make sure it's optionally set in accordance
with the DMA max-burst capability.
In order to have the DW APB SSI MMIO driver working with DMA we need to
initialize the paddr field with the physical base address of the DW APB SSI
registers space. Then we unpin the Intel MID specific code from the
generic DMA one and placed it into the spi-dw-pci.c driver, which is a
better place for it anyway. After that the naming cleanups are performed
since the code is going to be used for a generic DMAC device. Finally the
Generic DMA initialization can be added to the generic version of the
DW APB SSI IP.
Last but not least we traditionally convert the legacy plain text-based
dt-binding file with yaml-based one and as a cherry on a cake replace
the manually written DebugFS registers read method with a ready-to-use
for the same purpose regset32 DebugFS interface usage.
This patchset is rebased and tested on the spi/for-next (5.7-rc5):
base-commit: fe9fce6b2cf3 ("Merge remote-tracking branch 'spi/for-5.8' into spi-next")
Co-developed-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
Signed-off-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
Co-developed-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
Signed-off-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Maxim Kaurkin <Maxim.Kaurkin@baikalelectronics.ru>
Cc: Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>
Cc: Ekaterina Skachko <Ekaterina.Skachko@baikalelectronics.ru>
Cc: Vadim Vlasov <V.Vlasov@baikalelectronics.ru>
Cc: Alexey Kolotnikov <Alexey.Kolotnikov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Allison Randal <allison@lohutok.net>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Gareth Williams <gareth.williams.jx@renesas.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: linux-spi@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
---
Changelog v2:
- Rebase on top of the spi repository for-next branch.
- Move bindings conversion patch to the tail of the series.
- Move fixes to the head of the series.
- Apply as many changes as possible to be applied the Generic DMA
functionality support is added and the spi-dw-mid is moved to the
spi-dw-dma driver.
- Discard patch "spi: dw: Fix dma_slave_config used partly uninitialized"
since the problem has already been fixed.
- Add new patch "spi: dw: Discard unused void priv pointer".
- Add new patch "spi: dw: Discard dma_width member of the dw_spi structure".
n_bytes member of the DW SPI data can be used instead.
- Build the DMA functionality into the DW APB SSI core if required instead
of creating a separate kernel module.
- Use conditional statement instead of the ternary operator in the ref
clock getter.
Serge Semin (19):
dt-bindings: spi: dw: Add Tx/Rx DMA properties
spi: dw: Add Tx/Rx finish wait methods to the MID DMA
spi: dw: Clear DMAC register when done or stopped
spi: dw: Fix native CS being unset
spi: dw: Enable interrupts in accordance with DMA xfer mode
spi: dw: Discard static DW DMA slave structures
spi: dw: Discard unused void priv pointer
spi: dw: Discard dma_width member of the dw_spi structure
spi: dw: Parameterize the DMA Rx/Tx burst length
spi: dw: Use DMA max burst to set the request thresholds
spi: dw: Initialize paddr in DW SPI MMIO private data
spi: dw: Fix Rx-only DMA transfers
spi: dw: Move Non-DMA code to the DW PCIe-SPI driver
spi: dw: Remove DW DMA code dependency from DW_DMAC_PCI
spi: dw: Add DW SPI DMA/PCI/MMIO dependency on the DW SPI core
spi: dw: Cleanup generic DW DMA code namings
spi: dw: Add DMA support to the DW SPI MMIO driver
spi: dw: Use regset32 DebugFS method to create regdump file
dt-bindings: spi: Convert DW SPI binding to DT schema
.../bindings/spi/snps,dw-apb-ssi.txt | 42 ---
.../bindings/spi/snps,dw-apb-ssi.yaml | 127 +++++++++
.../devicetree/bindings/spi/spi-dw.txt | 24 --
drivers/spi/Kconfig | 15 +-
drivers/spi/Makefile | 7 +-
drivers/spi/{spi-dw-mid.c => spi-dw-dma.c} | 257 ++++++++++--------
drivers/spi/spi-dw-mmio.c | 9 +-
drivers/spi/spi-dw-pci.c | 50 +++-
drivers/spi/spi-dw.c | 98 +++----
drivers/spi/spi-dw.h | 33 ++-
10 files changed, 405 insertions(+), 257 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
create mode 100644 Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
delete mode 100644 Documentation/devicetree/bindings/spi/spi-dw.txt
rename drivers/spi/{spi-dw-mid.c => spi-dw-dma.c} (53%)
--
2.25.1
^ permalink raw reply [flat|nested] 106+ messages in thread
* [PATCH v2 01/19] dt-bindings: spi: dw: Add Tx/Rx DMA properties
2020-05-15 10:47 ` [PATCH v2 00/19] spi: dw: Add generic DW DMA controller support Serge Semin
@ 2020-05-15 10:47 ` Serge Semin
2020-05-15 11:51 ` Andy Shevchenko
2020-05-15 10:47 ` [PATCH v2 03/19] spi: dw: Clear DMAC register when done or stopped Serge Semin
` (18 subsequent siblings)
19 siblings, 1 reply; 106+ messages in thread
From: Serge Semin @ 2020-05-15 10:47 UTC (permalink / raw)
To: Mark Brown, Rob Herring
Cc: Serge Semin, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Arnd Bergmann, Allison Randal, Andy Shevchenko, Gareth Williams,
linux-mips, Wan Ahmad Zainie, linux-spi, devicetree,
linux-kernel
Since commit 22d48ad7bfac ("spi: dw: Add Elkhart Lake PSE DMA support")
the spi-dw-mid.c module supports a platform DMA engine handling the DW APB
SSI controller requests. Lets alter the DW SPI bindings file to accept the
Rx and Tx DMA line specifiers.
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
Cc: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Allison Randal <allison@lohutok.net>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Gareth Williams <gareth.williams.jx@renesas.com>
Cc: linux-mips@vger.kernel.org
---
Changelog v2:
- Revert the order of the DT changes: first add the DMA channels support,
then perform the binding file conversion.
---
Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
index 7a4702edf896..020e3168ee41 100644
--- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
+++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
@@ -23,6 +23,8 @@ Optional properties:
- num-cs : The number of chipselects. If omitted, this will default to 4.
- reg-io-width : The I/O register width (in bytes) implemented by this
device. Supported values are 2 or 4 (the default).
+- dmas : Phandle + identifiers of Tx and Rx DMA channels.
+- dma-names : Contains the names of the DMA channels. Must be "tx" and "rx".
Child nodes as per the generic SPI binding.
--
2.25.1
^ permalink raw reply related [flat|nested] 106+ messages in thread
* Re: [PATCH v2 01/19] dt-bindings: spi: dw: Add Tx/Rx DMA properties
2020-05-15 10:47 ` [PATCH v2 01/19] dt-bindings: spi: dw: Add Tx/Rx DMA properties Serge Semin
@ 2020-05-15 11:51 ` Andy Shevchenko
2020-05-15 12:27 ` Mark Brown
0 siblings, 1 reply; 106+ messages in thread
From: Andy Shevchenko @ 2020-05-15 11:51 UTC (permalink / raw)
To: Serge Semin
Cc: Mark Brown, Rob Herring, Serge Semin, Georgy Vlasov,
Ramil Zaripov, Alexey Malahov, Thomas Bogendoerfer, Paul Burton,
Ralf Baechle, Arnd Bergmann, Allison Randal, Gareth Williams,
linux-mips, Wan Ahmad Zainie, linux-spi, devicetree,
linux-kernel
On Fri, May 15, 2020 at 01:47:40PM +0300, Serge Semin wrote:
> Since commit 22d48ad7bfac ("spi: dw: Add Elkhart Lake PSE DMA support")
> the spi-dw-mid.c module supports a platform DMA engine handling the DW APB
> SSI controller requests. Lets alter the DW SPI bindings file to accept the
> Rx and Tx DMA line specifiers.
I'm wondering if these properties are implied by the SPI generic one?
(forgive me if I'm not understanding all DT schema relations)
Per se looks good.
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Cc: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
> Cc: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> Cc: Paul Burton <paulburton@kernel.org>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Allison Randal <allison@lohutok.net>
> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Cc: Gareth Williams <gareth.williams.jx@renesas.com>
> Cc: linux-mips@vger.kernel.org
>
> ---
>
> Changelog v2:
> - Revert the order of the DT changes: first add the DMA channels support,
> then perform the binding file conversion.
> ---
> Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
> index 7a4702edf896..020e3168ee41 100644
> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
> @@ -23,6 +23,8 @@ Optional properties:
> - num-cs : The number of chipselects. If omitted, this will default to 4.
> - reg-io-width : The I/O register width (in bytes) implemented by this
> device. Supported values are 2 or 4 (the default).
> +- dmas : Phandle + identifiers of Tx and Rx DMA channels.
> +- dma-names : Contains the names of the DMA channels. Must be "tx" and "rx".
>
> Child nodes as per the generic SPI binding.
>
> --
> 2.25.1
>
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH v2 01/19] dt-bindings: spi: dw: Add Tx/Rx DMA properties
2020-05-15 11:51 ` Andy Shevchenko
@ 2020-05-15 12:27 ` Mark Brown
2020-05-15 15:43 ` Serge Semin
0 siblings, 1 reply; 106+ messages in thread
From: Mark Brown @ 2020-05-15 12:27 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Serge Semin, Rob Herring, Serge Semin, Georgy Vlasov,
Ramil Zaripov, Alexey Malahov, Thomas Bogendoerfer, Paul Burton,
Ralf Baechle, Arnd Bergmann, Allison Randal, Gareth Williams,
linux-mips, Wan Ahmad Zainie, linux-spi, devicetree,
linux-kernel
[-- Attachment #1: Type: text/plain, Size: 635 bytes --]
On Fri, May 15, 2020 at 02:51:51PM +0300, Andy Shevchenko wrote:
> On Fri, May 15, 2020 at 01:47:40PM +0300, Serge Semin wrote:
> > Since commit 22d48ad7bfac ("spi: dw: Add Elkhart Lake PSE DMA support")
> > the spi-dw-mid.c module supports a platform DMA engine handling the DW APB
> > SSI controller requests. Lets alter the DW SPI bindings file to accept the
> > Rx and Tx DMA line specifiers.
> I'm wondering if these properties are implied by the SPI generic one?
> (forgive me if I'm not understanding all DT schema relations)
Which SPI generic DMA bindings are you thinking of here? There aren't
any in spi-controller.yaml.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH v2 01/19] dt-bindings: spi: dw: Add Tx/Rx DMA properties
2020-05-15 12:27 ` Mark Brown
@ 2020-05-15 15:43 ` Serge Semin
0 siblings, 0 replies; 106+ messages in thread
From: Serge Semin @ 2020-05-15 15:43 UTC (permalink / raw)
To: Mark Brown
Cc: Serge Semin, Andy Shevchenko, Rob Herring, Georgy Vlasov,
Ramil Zaripov, Alexey Malahov, Thomas Bogendoerfer, Paul Burton,
Ralf Baechle, Arnd Bergmann, Allison Randal, Gareth Williams,
linux-mips, Wan Ahmad Zainie, linux-spi, devicetree,
linux-kernel
On Fri, May 15, 2020 at 01:27:15PM +0100, Mark Brown wrote:
> On Fri, May 15, 2020 at 02:51:51PM +0300, Andy Shevchenko wrote:
> > On Fri, May 15, 2020 at 01:47:40PM +0300, Serge Semin wrote:
>
> > > Since commit 22d48ad7bfac ("spi: dw: Add Elkhart Lake PSE DMA support")
> > > the spi-dw-mid.c module supports a platform DMA engine handling the DW APB
> > > SSI controller requests. Lets alter the DW SPI bindings file to accept the
> > > Rx and Tx DMA line specifiers.
>
> > I'm wondering if these properties are implied by the SPI generic one?
> > (forgive me if I'm not understanding all DT schema relations)
>
> Which SPI generic DMA bindings are you thinking of here? There aren't
> any in spi-controller.yaml.
There are default schemas in the dt-core, which defines the dmas and dma-names
type, but the exact naming and number of phandler+identifiers are implementation
specific. So it's either supposed to be implemented on the generic SPI controller
basis (like in someplace of spi-controller.yaml) or in individual controllers DT
schema. As Mark said we don't have any DMA properties definition in the generic
SPI controller schema (spi-controller.yaml), so the particular SPI controllers
DT schemas have got their own DMA properties declared. Most of them BTW use the
same naming as we do here: "rx" and "tx", but some alas don't.
-Sergey
^ permalink raw reply [flat|nested] 106+ messages in thread
* [PATCH v2 03/19] spi: dw: Clear DMAC register when done or stopped
2020-05-15 10:47 ` [PATCH v2 00/19] spi: dw: Add generic DW DMA controller support Serge Semin
2020-05-15 10:47 ` [PATCH v2 01/19] dt-bindings: spi: dw: Add Tx/Rx DMA properties Serge Semin
@ 2020-05-15 10:47 ` Serge Semin
2020-05-15 12:01 ` Andy Shevchenko
2020-05-15 16:42 ` Mark Brown
2020-05-15 10:47 ` [PATCH v2 05/19] spi: dw: Enable interrupts in accordance with DMA xfer mode Serge Semin
` (17 subsequent siblings)
19 siblings, 2 replies; 106+ messages in thread
From: Serge Semin @ 2020-05-15 10:47 UTC (permalink / raw)
To: Mark Brown
Cc: Serge Semin, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Arnd Bergmann, Allison Randal, Andy Shevchenko, Gareth Williams,
Rob Herring, linux-mips, devicetree, Thomas Gleixner,
Wan Ahmad Zainie, Jarkko Nikula, linux-spi, linux-kernel
If DMAC register is left uncleared any further DMAless transfers
may cause the DMAC hardware handshaking interface getting activated.
So the next DMA-based Rx/Tx transaction will be started right
after the dma_async_issue_pending() method is invoked even if no
DMATDLR/DMARDLR conditions are met. This at the same time may cause
the Tx/Rx FIFO buffers underrun/overrun. In order to fix this we
must clear DMAC register after a current DMA-based transaction is
finished.
Co-developed-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
Signed-off-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Allison Randal <allison@lohutok.net>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Gareth Williams <gareth.williams.jx@renesas.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: devicetree@vger.kernel.org
---
Changelog v2:
- Move the patch to the head of the series so one could be picked up to
the stable kernels as a fix.
- Clear the DMACR in the DMA exit callback too.
---
drivers/spi/spi-dw-mid.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/spi/spi-dw-mid.c b/drivers/spi/spi-dw-mid.c
index 7a5ae1506365..0c597b6bb154 100644
--- a/drivers/spi/spi-dw-mid.c
+++ b/drivers/spi/spi-dw-mid.c
@@ -108,6 +108,8 @@ static void mid_spi_dma_exit(struct dw_spi *dws)
dmaengine_terminate_sync(dws->rxchan);
dma_release_channel(dws->rxchan);
}
+
+ dw_writel(dws, DW_SPI_DMACR, 0);
}
static irqreturn_t dma_transfer(struct dw_spi *dws)
@@ -178,6 +180,8 @@ static void dw_spi_dma_tx_done(void *arg)
clear_bit(TX_BUSY, &dws->dma_chan_busy);
if (test_bit(RX_BUSY, &dws->dma_chan_busy))
return;
+
+ dw_writel(dws, DW_SPI_DMACR, 0);
spi_finalize_current_transfer(dws->master);
}
@@ -249,6 +253,8 @@ static void dw_spi_dma_rx_done(void *arg)
clear_bit(RX_BUSY, &dws->dma_chan_busy);
if (test_bit(TX_BUSY, &dws->dma_chan_busy))
return;
+
+ dw_writel(dws, DW_SPI_DMACR, 0);
spi_finalize_current_transfer(dws->master);
}
@@ -342,6 +348,8 @@ static void mid_spi_dma_stop(struct dw_spi *dws)
dmaengine_terminate_sync(dws->rxchan);
clear_bit(RX_BUSY, &dws->dma_chan_busy);
}
+
+ dw_writel(dws, DW_SPI_DMACR, 0);
}
static const struct dw_spi_dma_ops mfld_dma_ops = {
--
2.25.1
^ permalink raw reply related [flat|nested] 106+ messages in thread
* Re: [PATCH v2 03/19] spi: dw: Clear DMAC register when done or stopped
2020-05-15 10:47 ` [PATCH v2 03/19] spi: dw: Clear DMAC register when done or stopped Serge Semin
@ 2020-05-15 12:01 ` Andy Shevchenko
2020-05-15 16:42 ` Mark Brown
1 sibling, 0 replies; 106+ messages in thread
From: Andy Shevchenko @ 2020-05-15 12:01 UTC (permalink / raw)
To: Serge Semin
Cc: Mark Brown, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Arnd Bergmann, Allison Randal, Gareth Williams, Rob Herring,
linux-mips, devicetree, Thomas Gleixner, Wan Ahmad Zainie,
Jarkko Nikula, linux-spi, linux-kernel
On Fri, May 15, 2020 at 01:47:42PM +0300, Serge Semin wrote:
> If DMAC register is left uncleared any further DMAless transfers
> may cause the DMAC hardware handshaking interface getting activated.
> So the next DMA-based Rx/Tx transaction will be started right
> after the dma_async_issue_pending() method is invoked even if no
> DMATDLR/DMARDLR conditions are met. This at the same time may cause
> the Tx/Rx FIFO buffers underrun/overrun. In order to fix this we
> must clear DMAC register after a current DMA-based transaction is
> finished.
After adding a Fixes tag,
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
>
> Co-developed-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
> Signed-off-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Cc: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> Cc: Paul Burton <paulburton@kernel.org>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Allison Randal <allison@lohutok.net>
> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Cc: Gareth Williams <gareth.williams.jx@renesas.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: linux-mips@vger.kernel.org
> Cc: devicetree@vger.kernel.org
>
> ---
>
> Changelog v2:
> - Move the patch to the head of the series so one could be picked up to
> the stable kernels as a fix.
> - Clear the DMACR in the DMA exit callback too.
> ---
> drivers/spi/spi-dw-mid.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/spi/spi-dw-mid.c b/drivers/spi/spi-dw-mid.c
> index 7a5ae1506365..0c597b6bb154 100644
> --- a/drivers/spi/spi-dw-mid.c
> +++ b/drivers/spi/spi-dw-mid.c
> @@ -108,6 +108,8 @@ static void mid_spi_dma_exit(struct dw_spi *dws)
> dmaengine_terminate_sync(dws->rxchan);
> dma_release_channel(dws->rxchan);
> }
> +
> + dw_writel(dws, DW_SPI_DMACR, 0);
> }
>
> static irqreturn_t dma_transfer(struct dw_spi *dws)
> @@ -178,6 +180,8 @@ static void dw_spi_dma_tx_done(void *arg)
> clear_bit(TX_BUSY, &dws->dma_chan_busy);
> if (test_bit(RX_BUSY, &dws->dma_chan_busy))
> return;
> +
> + dw_writel(dws, DW_SPI_DMACR, 0);
> spi_finalize_current_transfer(dws->master);
> }
>
> @@ -249,6 +253,8 @@ static void dw_spi_dma_rx_done(void *arg)
> clear_bit(RX_BUSY, &dws->dma_chan_busy);
> if (test_bit(TX_BUSY, &dws->dma_chan_busy))
> return;
> +
> + dw_writel(dws, DW_SPI_DMACR, 0);
> spi_finalize_current_transfer(dws->master);
> }
>
> @@ -342,6 +348,8 @@ static void mid_spi_dma_stop(struct dw_spi *dws)
> dmaengine_terminate_sync(dws->rxchan);
> clear_bit(RX_BUSY, &dws->dma_chan_busy);
> }
> +
> + dw_writel(dws, DW_SPI_DMACR, 0);
> }
>
> static const struct dw_spi_dma_ops mfld_dma_ops = {
> --
> 2.25.1
>
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH v2 03/19] spi: dw: Clear DMAC register when done or stopped
2020-05-15 10:47 ` [PATCH v2 03/19] spi: dw: Clear DMAC register when done or stopped Serge Semin
2020-05-15 12:01 ` Andy Shevchenko
@ 2020-05-15 16:42 ` Mark Brown
2020-05-15 17:21 ` Serge Semin
1 sibling, 1 reply; 106+ messages in thread
From: Mark Brown @ 2020-05-15 16:42 UTC (permalink / raw)
To: Serge Semin
Cc: Serge Semin, Georgy Vlasov, Ramil Zaripov, Alexey Malahov,
Thomas Bogendoerfer, Paul Burton, Ralf Baechle, Arnd Bergmann,
Allison Randal, Andy Shevchenko, Gareth Williams, Rob Herring,
linux-mips, devicetree, Thomas Gleixner, Wan Ahmad Zainie,
Jarkko Nikula, linux-spi, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 623 bytes --]
On Fri, May 15, 2020 at 01:47:42PM +0300, Serge Semin wrote:
> If DMAC register is left uncleared any further DMAless transfers
> may cause the DMAC hardware handshaking interface getting activated.
This and patch 4 look good as is but they don't apply against for-5.7
due to context changes in -next, unfortunately everyone seems to have
decided that now is the time to start working on this driver which makes
combinations of new work and fixes awkward. I'm going to apply these
for 5.8 but it'd be good if you could send versions based on for-5.7 as
well so I can apply there - I can sort out the conflicts with 5.8.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH v2 03/19] spi: dw: Clear DMAC register when done or stopped
2020-05-15 16:42 ` Mark Brown
@ 2020-05-15 17:21 ` Serge Semin
0 siblings, 0 replies; 106+ messages in thread
From: Serge Semin @ 2020-05-15 17:21 UTC (permalink / raw)
To: Mark Brown
Cc: Serge Semin, Georgy Vlasov, Ramil Zaripov, Alexey Malahov,
Thomas Bogendoerfer, Paul Burton, Ralf Baechle, Arnd Bergmann,
Allison Randal, Andy Shevchenko, Gareth Williams, Rob Herring,
linux-mips, devicetree, Thomas Gleixner, Wan Ahmad Zainie,
Jarkko Nikula, linux-spi, linux-kernel
On Fri, May 15, 2020 at 05:42:03PM +0100, Mark Brown wrote:
> On Fri, May 15, 2020 at 01:47:42PM +0300, Serge Semin wrote:
> > If DMAC register is left uncleared any further DMAless transfers
> > may cause the DMAC hardware handshaking interface getting activated.
>
> This and patch 4 look good as is but they don't apply against for-5.7
> due to context changes in -next, unfortunately everyone seems to have
> decided that now is the time to start working on this driver which makes
> combinations of new work and fixes awkward. I'm going to apply these
> for 5.8 but it'd be good if you could send versions based on for-5.7 as
> well so I can apply there - I can sort out the conflicts with 5.8.
>
Thanks. I'll send these two patches:
spi: dw: Clear DMAC register when done or stopped
spi: dw: Fix native CS being unset
rebased on top of the for-5.7.
-Sergey
^ permalink raw reply [flat|nested] 106+ messages in thread
* [PATCH v2 05/19] spi: dw: Enable interrupts in accordance with DMA xfer mode
2020-05-15 10:47 ` [PATCH v2 00/19] spi: dw: Add generic DW DMA controller support Serge Semin
2020-05-15 10:47 ` [PATCH v2 01/19] dt-bindings: spi: dw: Add Tx/Rx DMA properties Serge Semin
2020-05-15 10:47 ` [PATCH v2 03/19] spi: dw: Clear DMAC register when done or stopped Serge Semin
@ 2020-05-15 10:47 ` Serge Semin
2020-05-15 12:27 ` Andy Shevchenko
2020-05-15 10:47 ` [PATCH v2 09/19] spi: dw: Parameterize the DMA Rx/Tx burst length Serge Semin
` (16 subsequent siblings)
19 siblings, 1 reply; 106+ messages in thread
From: Serge Semin @ 2020-05-15 10:47 UTC (permalink / raw)
To: Mark Brown
Cc: Serge Semin, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Arnd Bergmann, Allison Randal, Andy Shevchenko, Gareth Williams,
Rob Herring, linux-mips, devicetree, Jarkko Nikula,
Thomas Gleixner, Wan Ahmad Zainie, linux-spi, linux-kernel
It's pointless to track the Tx overrun interrupts if Rx-only SPI
transfer is issued. Similarly there is no need in handling the Rx
overrun/underrun interrupts if Tx-only SPI transfer is executed.
So lets unmask the interrupts only if corresponding SPI
transactions are implied.
Co-developed-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
Signed-off-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Allison Randal <allison@lohutok.net>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Gareth Williams <gareth.williams.jx@renesas.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: devicetree@vger.kernel.org
---
drivers/spi/spi-dw-mid.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/spi/spi-dw-mid.c b/drivers/spi/spi-dw-mid.c
index 0c597b6bb154..1902336cb8d6 100644
--- a/drivers/spi/spi-dw-mid.c
+++ b/drivers/spi/spi-dw-mid.c
@@ -293,19 +293,23 @@ static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws,
static int mid_spi_dma_setup(struct dw_spi *dws, struct spi_transfer *xfer)
{
- u16 dma_ctrl = 0;
+ u16 imr = 0, dma_ctrl = 0;
dw_writel(dws, DW_SPI_DMARDLR, 0xf);
dw_writel(dws, DW_SPI_DMATDLR, 0x10);
- if (xfer->tx_buf)
+ if (xfer->tx_buf) {
dma_ctrl |= SPI_DMA_TDMAE;
- if (xfer->rx_buf)
+ imr |= SPI_INT_TXOI;
+ }
+ if (xfer->rx_buf) {
dma_ctrl |= SPI_DMA_RDMAE;
+ imr |= SPI_INT_RXUI | SPI_INT_RXOI;
+ }
dw_writel(dws, DW_SPI_DMACR, dma_ctrl);
/* Set the interrupt mask */
- spi_umask_intr(dws, SPI_INT_TXOI | SPI_INT_RXUI | SPI_INT_RXOI);
+ spi_umask_intr(dws, imr);
dws->transfer_handler = dma_transfer;
--
2.25.1
^ permalink raw reply related [flat|nested] 106+ messages in thread
* Re: [PATCH v2 05/19] spi: dw: Enable interrupts in accordance with DMA xfer mode
2020-05-15 10:47 ` [PATCH v2 05/19] spi: dw: Enable interrupts in accordance with DMA xfer mode Serge Semin
@ 2020-05-15 12:27 ` Andy Shevchenko
2020-05-16 14:06 ` Serge Semin
0 siblings, 1 reply; 106+ messages in thread
From: Andy Shevchenko @ 2020-05-15 12:27 UTC (permalink / raw)
To: Serge Semin
Cc: Mark Brown, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Arnd Bergmann, Allison Randal, Gareth Williams, Rob Herring,
linux-mips, devicetree, Jarkko Nikula, Thomas Gleixner,
Wan Ahmad Zainie, linux-spi, linux-kernel
On Fri, May 15, 2020 at 01:47:44PM +0300, Serge Semin wrote:
> It's pointless to track the Tx overrun interrupts if Rx-only SPI
> transfer is issued. Similarly there is no need in handling the Rx
> overrun/underrun interrupts if Tx-only SPI transfer is executed.
> So lets unmask the interrupts only if corresponding SPI
> transactions are implied.
My comments below.
> Co-developed-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
> Signed-off-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Cc: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> Cc: Paul Burton <paulburton@kernel.org>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Allison Randal <allison@lohutok.net>
> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Cc: Gareth Williams <gareth.williams.jx@renesas.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: linux-mips@vger.kernel.org
> Cc: devicetree@vger.kernel.org
I think you really need to revisit Cc list in all patches (DT people hardly
interested in this one, though ones where properties are being used might be
point of interest).
...
> /* Set the interrupt mask */
> - spi_umask_intr(dws, SPI_INT_TXOI | SPI_INT_RXUI | SPI_INT_RXOI);
> + spi_umask_intr(dws, imr);
Can we rather do like this
/* Set the interrupt mask */
if (xfer->tx_buf)
imr |= SPI_INT_TXOI;
if (xfer->rx_buf)
imr |= SPI_INT_RXUI | SPI_INT_RXOI;
spi_umask_intr(dws, imr);
?
(First block sets DMA, second one IRQ)
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH v2 05/19] spi: dw: Enable interrupts in accordance with DMA xfer mode
2020-05-15 12:27 ` Andy Shevchenko
@ 2020-05-16 14:06 ` Serge Semin
0 siblings, 0 replies; 106+ messages in thread
From: Serge Semin @ 2020-05-16 14:06 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Serge Semin, Mark Brown, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Arnd Bergmann, Allison Randal, Gareth Williams, Rob Herring,
linux-mips, devicetree, Jarkko Nikula, Thomas Gleixner,
Wan Ahmad Zainie, linux-spi, linux-kernel
On Fri, May 15, 2020 at 03:27:00PM +0300, Andy Shevchenko wrote:
> On Fri, May 15, 2020 at 01:47:44PM +0300, Serge Semin wrote:
> > It's pointless to track the Tx overrun interrupts if Rx-only SPI
> > transfer is issued. Similarly there is no need in handling the Rx
> > overrun/underrun interrupts if Tx-only SPI transfer is executed.
> > So lets unmask the interrupts only if corresponding SPI
> > transactions are implied.
>
> My comments below.
>
> > Co-developed-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
> > Signed-off-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
> > Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> > Cc: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
> > Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> > Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> > Cc: Paul Burton <paulburton@kernel.org>
> > Cc: Ralf Baechle <ralf@linux-mips.org>
> > Cc: Arnd Bergmann <arnd@arndb.de>
> > Cc: Allison Randal <allison@lohutok.net>
> > Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> > Cc: Gareth Williams <gareth.williams.jx@renesas.com>
> > Cc: Rob Herring <robh+dt@kernel.org>
> > Cc: linux-mips@vger.kernel.org
> > Cc: devicetree@vger.kernel.org
>
> I think you really need to revisit Cc list in all patches (DT people hardly
> interested in this one, though ones where properties are being used might be
> point of interest).
>
> ...
>
> > /* Set the interrupt mask */
> > - spi_umask_intr(dws, SPI_INT_TXOI | SPI_INT_RXUI | SPI_INT_RXOI);
> > + spi_umask_intr(dws, imr);
>
> Can we rather do like this
>
> /* Set the interrupt mask */
> if (xfer->tx_buf)
> imr |= SPI_INT_TXOI;
> if (xfer->rx_buf)
> imr |= SPI_INT_RXUI | SPI_INT_RXOI;
> spi_umask_intr(dws, imr);
>
> ?
>
> (First block sets DMA, second one IRQ)
I'd rather leave it as is.
-Sergey
>
> --
> With Best Regards,
> Andy Shevchenko
>
>
^ permalink raw reply [flat|nested] 106+ messages in thread
* [PATCH v2 09/19] spi: dw: Parameterize the DMA Rx/Tx burst length
2020-05-15 10:47 ` [PATCH v2 00/19] spi: dw: Add generic DW DMA controller support Serge Semin
` (2 preceding siblings ...)
2020-05-15 10:47 ` [PATCH v2 05/19] spi: dw: Enable interrupts in accordance with DMA xfer mode Serge Semin
@ 2020-05-15 10:47 ` Serge Semin
2020-05-15 14:01 ` Andy Shevchenko
2020-05-15 10:47 ` [PATCH v2 10/19] spi: dw: Use DMA max burst to set the request thresholds Serge Semin
` (15 subsequent siblings)
19 siblings, 1 reply; 106+ messages in thread
From: Serge Semin @ 2020-05-15 10:47 UTC (permalink / raw)
To: Mark Brown
Cc: Serge Semin, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Arnd Bergmann, Allison Randal, Andy Shevchenko, Gareth Williams,
Rob Herring, linux-mips, devicetree, Thomas Gleixner,
Wan Ahmad Zainie, Jarkko Nikula, linux-spi, linux-kernel
It isn't good to have numeric literals in the code especially if there
are multiple of them and they are related. Moreover in current
implementation the Tx DMA transfer activation level isn't optimal,
since it's hardwired to be at 16-32 bytes level, while it's better
to keep the SPI FIFO buffer as full as possible until all available
data is submitted. So lets introduce the DMA burst level
parametrization macros with optimal values - issue Rx transfer if at
least 16 bytes are available in the buffer and execute Tx transaction
if at least 16 bytes room is opened in SPI Tx FIFO.
Co-developed-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
Signed-off-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
Co-developed-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
Signed-off-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Allison Randal <allison@lohutok.net>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Gareth Williams <gareth.williams.jx@renesas.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: devicetree@vger.kernel.org
---
drivers/spi/spi-dw-mid.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/spi/spi-dw-mid.c b/drivers/spi/spi-dw-mid.c
index ca8813a693d8..e43914dbcadf 100644
--- a/drivers/spi/spi-dw-mid.c
+++ b/drivers/spi/spi-dw-mid.c
@@ -20,7 +20,9 @@
#define WAIT_RETRIES 5
#define RX_BUSY 0
+#define RX_BURST_LEVEL 16
#define TX_BUSY 1
+#define TX_BURST_LEVEL 16
static bool mid_spi_dma_chan_filter(struct dma_chan *chan, void *param)
{
@@ -193,7 +195,7 @@ static struct dma_async_tx_descriptor *dw_spi_dma_prepare_tx(struct dw_spi *dws,
memset(&txconf, 0, sizeof(txconf));
txconf.direction = DMA_MEM_TO_DEV;
txconf.dst_addr = dws->dma_addr;
- txconf.dst_maxburst = 16;
+ txconf.dst_maxburst = TX_BURST_LEVEL;
txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
txconf.dst_addr_width = convert_dma_width(dws->n_bytes);
txconf.device_fc = false;
@@ -266,7 +268,7 @@ static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws,
memset(&rxconf, 0, sizeof(rxconf));
rxconf.direction = DMA_DEV_TO_MEM;
rxconf.src_addr = dws->dma_addr;
- rxconf.src_maxburst = 16;
+ rxconf.src_maxburst = RX_BURST_LEVEL;
rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
rxconf.src_addr_width = convert_dma_width(dws->n_bytes);
rxconf.device_fc = false;
@@ -291,8 +293,8 @@ static int mid_spi_dma_setup(struct dw_spi *dws, struct spi_transfer *xfer)
{
u16 imr = 0, dma_ctrl = 0;
- dw_writel(dws, DW_SPI_DMARDLR, 0xf);
- dw_writel(dws, DW_SPI_DMATDLR, 0x10);
+ dw_writel(dws, DW_SPI_DMARDLR, RX_BURST_LEVEL - 1);
+ dw_writel(dws, DW_SPI_DMATDLR, dws->fifo_len - TX_BURST_LEVEL);
if (xfer->tx_buf) {
dma_ctrl |= SPI_DMA_TDMAE;
--
2.25.1
^ permalink raw reply related [flat|nested] 106+ messages in thread
* Re: [PATCH v2 09/19] spi: dw: Parameterize the DMA Rx/Tx burst length
2020-05-15 10:47 ` [PATCH v2 09/19] spi: dw: Parameterize the DMA Rx/Tx burst length Serge Semin
@ 2020-05-15 14:01 ` Andy Shevchenko
[not found] ` <20200516143353.hw6nny5hbwgiyxfw@mobilestation>
0 siblings, 1 reply; 106+ messages in thread
From: Andy Shevchenko @ 2020-05-15 14:01 UTC (permalink / raw)
To: Serge Semin
Cc: Mark Brown, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Arnd Bergmann, Allison Randal, Gareth Williams, Rob Herring,
linux-mips, devicetree, Thomas Gleixner, Wan Ahmad Zainie,
Jarkko Nikula, linux-spi, linux-kernel
On Fri, May 15, 2020 at 01:47:48PM +0300, Serge Semin wrote:
> It isn't good to have numeric literals in the code especially if there
> are multiple of them and they are related. Moreover in current
> implementation the Tx DMA transfer activation level isn't optimal,
> since it's hardwired to be at 16-32 bytes level, while it's better
> to keep the SPI FIFO buffer as full as possible until all available
> data is submitted. So lets introduce the DMA burst level
> parametrization macros with optimal values - issue Rx transfer if at
> least 16 bytes are available in the buffer and execute Tx transaction
> if at least 16 bytes room is opened in SPI Tx FIFO.
> - dw_writel(dws, DW_SPI_DMARDLR, 0xf);
> - dw_writel(dws, DW_SPI_DMATDLR, 0x10);
> + dw_writel(dws, DW_SPI_DMARDLR, RX_BURST_LEVEL - 1);
> + dw_writel(dws, DW_SPI_DMATDLR, dws->fifo_len - TX_BURST_LEVEL);
...and if FIFO length is less than TX_BURST_LEVEL?
For the patch that introduces definitions, i.e. keeping the last line here as
dw_writel(dws, DW_SPI_DMATDLR, TX_BURST_LEVEL);
I'm good. You may put your tag in that case. For fifo_len case we need to
discuss in separate patch, perhaps.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 106+ messages in thread
* [PATCH v2 10/19] spi: dw: Use DMA max burst to set the request thresholds
2020-05-15 10:47 ` [PATCH v2 00/19] spi: dw: Add generic DW DMA controller support Serge Semin
` (3 preceding siblings ...)
2020-05-15 10:47 ` [PATCH v2 09/19] spi: dw: Parameterize the DMA Rx/Tx burst length Serge Semin
@ 2020-05-15 10:47 ` Serge Semin
2020-05-15 14:38 ` Andy Shevchenko
2020-05-15 10:47 ` [PATCH v2 11/19] spi: dw: Initialize paddr in DW SPI MMIO private data Serge Semin
` (14 subsequent siblings)
19 siblings, 1 reply; 106+ messages in thread
From: Serge Semin @ 2020-05-15 10:47 UTC (permalink / raw)
To: Mark Brown
Cc: Serge Semin, Serge Semin, Alexey Malahov, Thomas Bogendoerfer,
Paul Burton, Ralf Baechle, Arnd Bergmann, Allison Randal,
Andy Shevchenko, Gareth Williams, Rob Herring, linux-mips,
devicetree, Georgy Vlasov, Ramil Zaripov, Jarkko Nikula,
Thomas Gleixner, Wan Ahmad Zainie, Linus Walleij, Clement Leger,
linux-spi, linux-kernel
Each channel of DMA controller may have a limited length of burst
transaction (number of IO operations performed at ones in a single
DMA client request). This parameter can be used to setup the most
optimal DMA Tx/Rx data level values. In order to avoid the Tx buffer
overrun we can set the DMA Tx level to be of FIFO depth minus the
maximum burst transactions length. To prevent the Rx buffer underflow
the DMA Rx level should be set to the maximum burst transactions length.
This commit setups the DMA channels and the DW SPI DMA Tx/Rx levels
in accordance with these rules.
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Allison Randal <allison@lohutok.net>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Gareth Williams <gareth.williams.jx@renesas.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: devicetree@vger.kernel.org
---
drivers/spi/spi-dw-mid.c | 37 +++++++++++++++++++++++++++++++++----
drivers/spi/spi-dw.h | 2 ++
2 files changed, 35 insertions(+), 4 deletions(-)
diff --git a/drivers/spi/spi-dw-mid.c b/drivers/spi/spi-dw-mid.c
index e43914dbcadf..70cb68290385 100644
--- a/drivers/spi/spi-dw-mid.c
+++ b/drivers/spi/spi-dw-mid.c
@@ -35,6 +35,31 @@ static bool mid_spi_dma_chan_filter(struct dma_chan *chan, void *param)
return true;
}
+static void mid_spi_maxburst_init(struct dw_spi *dws)
+{
+ struct dma_slave_caps caps;
+ u32 max_burst, def_burst;
+ int ret;
+
+ def_burst = dws->fifo_len / 2;
+
+ ret = dma_get_slave_caps(dws->rxchan, &caps);
+ if (!ret && caps.max_burst)
+ max_burst = caps.max_burst;
+ else
+ max_burst = RX_BURST_LEVEL;
+
+ dws->rxburst = (def_burst > max_burst) ? max_burst : def_burst;
+
+ ret = dma_get_slave_caps(dws->txchan, &caps);
+ if (!ret && caps.max_burst)
+ max_burst = caps.max_burst;
+ else
+ max_burst = TX_BURST_LEVEL;
+
+ dws->txburst = (def_burst > max_burst) ? max_burst : def_burst;
+}
+
static int mid_spi_dma_init_mfld(struct device *dev, struct dw_spi *dws)
{
struct dw_dma_slave slave = {0};
@@ -67,6 +92,8 @@ static int mid_spi_dma_init_mfld(struct device *dev, struct dw_spi *dws)
dws->master->dma_rx = dws->rxchan;
dws->master->dma_tx = dws->txchan;
+ mid_spi_maxburst_init(dws);
+
return 0;
free_rxchan:
@@ -92,6 +119,8 @@ static int mid_spi_dma_init_generic(struct device *dev, struct dw_spi *dws)
dws->master->dma_rx = dws->rxchan;
dws->master->dma_tx = dws->txchan;
+ mid_spi_maxburst_init(dws);
+
return 0;
}
@@ -195,7 +224,7 @@ static struct dma_async_tx_descriptor *dw_spi_dma_prepare_tx(struct dw_spi *dws,
memset(&txconf, 0, sizeof(txconf));
txconf.direction = DMA_MEM_TO_DEV;
txconf.dst_addr = dws->dma_addr;
- txconf.dst_maxburst = TX_BURST_LEVEL;
+ txconf.dst_maxburst = dws->txburst;
txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
txconf.dst_addr_width = convert_dma_width(dws->n_bytes);
txconf.device_fc = false;
@@ -268,7 +297,7 @@ static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws,
memset(&rxconf, 0, sizeof(rxconf));
rxconf.direction = DMA_DEV_TO_MEM;
rxconf.src_addr = dws->dma_addr;
- rxconf.src_maxburst = RX_BURST_LEVEL;
+ rxconf.src_maxburst = dws->rxburst;
rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
rxconf.src_addr_width = convert_dma_width(dws->n_bytes);
rxconf.device_fc = false;
@@ -293,8 +322,8 @@ static int mid_spi_dma_setup(struct dw_spi *dws, struct spi_transfer *xfer)
{
u16 imr = 0, dma_ctrl = 0;
- dw_writel(dws, DW_SPI_DMARDLR, RX_BURST_LEVEL - 1);
- dw_writel(dws, DW_SPI_DMATDLR, dws->fifo_len - TX_BURST_LEVEL);
+ dw_writel(dws, DW_SPI_DMARDLR, dws->rxburst - 1);
+ dw_writel(dws, DW_SPI_DMATDLR, dws->fifo_len - dws->txburst);
if (xfer->tx_buf) {
dma_ctrl |= SPI_DMA_TDMAE;
diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
index 4902f937c3d7..d0c8b7d3a5d2 100644
--- a/drivers/spi/spi-dw.h
+++ b/drivers/spi/spi-dw.h
@@ -141,7 +141,9 @@ struct dw_spi {
/* DMA info */
struct dma_chan *txchan;
+ u32 txburst;
struct dma_chan *rxchan;
+ u32 rxburst;
unsigned long dma_chan_busy;
dma_addr_t dma_addr; /* phy address of the Data register */
const struct dw_spi_dma_ops *dma_ops;
--
2.25.1
^ permalink raw reply related [flat|nested] 106+ messages in thread
* Re: [PATCH v2 10/19] spi: dw: Use DMA max burst to set the request thresholds
2020-05-15 10:47 ` [PATCH v2 10/19] spi: dw: Use DMA max burst to set the request thresholds Serge Semin
@ 2020-05-15 14:38 ` Andy Shevchenko
[not found] ` <20200516200133.wmaqnfjbr7234fzo@mobilestation>
0 siblings, 1 reply; 106+ messages in thread
From: Andy Shevchenko @ 2020-05-15 14:38 UTC (permalink / raw)
To: Serge Semin
Cc: Mark Brown, Serge Semin, Alexey Malahov, Thomas Bogendoerfer,
Paul Burton, Ralf Baechle, Arnd Bergmann, Allison Randal,
Gareth Williams, Rob Herring, linux-mips, devicetree,
Georgy Vlasov, Ramil Zaripov, Jarkko Nikula, Thomas Gleixner,
Wan Ahmad Zainie, Linus Walleij, Clement Leger, linux-spi,
linux-kernel
On Fri, May 15, 2020 at 01:47:49PM +0300, Serge Semin wrote:
> Each channel of DMA controller may have a limited length of burst
> transaction (number of IO operations performed at ones in a single
> DMA client request). This parameter can be used to setup the most
> optimal DMA Tx/Rx data level values. In order to avoid the Tx buffer
> overrun we can set the DMA Tx level to be of FIFO depth minus the
> maximum burst transactions length. To prevent the Rx buffer underflow
> the DMA Rx level should be set to the maximum burst transactions length.
> This commit setups the DMA channels and the DW SPI DMA Tx/Rx levels
> in accordance with these rules.
It's good one, but see my comments.
I think this patch should go before previous one.
(and without changes regarding FIFO length)
> +static void mid_spi_maxburst_init(struct dw_spi *dws)
> +{
> + struct dma_slave_caps caps;
> + u32 max_burst, def_burst;
> + int ret;
> +
> + def_burst = dws->fifo_len / 2;
> +
> + ret = dma_get_slave_caps(dws->rxchan, &caps);
> + if (!ret && caps.max_burst)
> + max_burst = caps.max_burst;
> + else
> + max_burst = RX_BURST_LEVEL;
> +
> + dws->rxburst = (def_burst > max_burst) ? max_burst : def_burst;
min() ?
> +
> + ret = dma_get_slave_caps(dws->txchan, &caps);
> + if (!ret && caps.max_burst)
> + max_burst = caps.max_burst;
> + else
> + max_burst = TX_BURST_LEVEL;
> +
> + dws->txburst = (def_burst > max_burst) ? max_burst : def_burst;
Ditto.
> +}
> +
> static int mid_spi_dma_init_mfld(struct device *dev, struct dw_spi *dws)
> {
> struct dw_dma_slave slave = {0};
> @@ -67,6 +92,8 @@ static int mid_spi_dma_init_mfld(struct device *dev, struct dw_spi *dws)
> dws->master->dma_rx = dws->rxchan;
> dws->master->dma_tx = dws->txchan;
>
> + mid_spi_maxburst_init(dws);
> +
> return 0;
>
> free_rxchan:
> @@ -92,6 +119,8 @@ static int mid_spi_dma_init_generic(struct device *dev, struct dw_spi *dws)
> dws->master->dma_rx = dws->rxchan;
> dws->master->dma_tx = dws->txchan;
>
> + mid_spi_maxburst_init(dws);
> +
> return 0;
> }
>
> @@ -195,7 +224,7 @@ static struct dma_async_tx_descriptor *dw_spi_dma_prepare_tx(struct dw_spi *dws,
> memset(&txconf, 0, sizeof(txconf));
> txconf.direction = DMA_MEM_TO_DEV;
> txconf.dst_addr = dws->dma_addr;
> - txconf.dst_maxburst = TX_BURST_LEVEL;
> + txconf.dst_maxburst = dws->txburst;
> txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
> txconf.dst_addr_width = convert_dma_width(dws->n_bytes);
> txconf.device_fc = false;
> @@ -268,7 +297,7 @@ static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws,
> memset(&rxconf, 0, sizeof(rxconf));
> rxconf.direction = DMA_DEV_TO_MEM;
> rxconf.src_addr = dws->dma_addr;
> - rxconf.src_maxburst = RX_BURST_LEVEL;
> + rxconf.src_maxburst = dws->rxburst;
> rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
> rxconf.src_addr_width = convert_dma_width(dws->n_bytes);
> rxconf.device_fc = false;
> @@ -293,8 +322,8 @@ static int mid_spi_dma_setup(struct dw_spi *dws, struct spi_transfer *xfer)
> {
> u16 imr = 0, dma_ctrl = 0;
>
> - dw_writel(dws, DW_SPI_DMARDLR, RX_BURST_LEVEL - 1);
> - dw_writel(dws, DW_SPI_DMATDLR, dws->fifo_len - TX_BURST_LEVEL);
> + dw_writel(dws, DW_SPI_DMARDLR, dws->rxburst - 1);
> + dw_writel(dws, DW_SPI_DMATDLR, dws->fifo_len - dws->txburst);
>
> if (xfer->tx_buf) {
> dma_ctrl |= SPI_DMA_TDMAE;
...
> /* DMA info */
> struct dma_chan *txchan;
> + u32 txburst;
> struct dma_chan *rxchan;
> + u32 rxburst;
Leave u32 together, it may be optimal on 64-bit architectures where ABIs require padding.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 106+ messages in thread
* [PATCH v2 11/19] spi: dw: Initialize paddr in DW SPI MMIO private data
2020-05-15 10:47 ` [PATCH v2 00/19] spi: dw: Add generic DW DMA controller support Serge Semin
` (4 preceding siblings ...)
2020-05-15 10:47 ` [PATCH v2 10/19] spi: dw: Use DMA max burst to set the request thresholds Serge Semin
@ 2020-05-15 10:47 ` Serge Semin
2020-05-15 14:39 ` Andy Shevchenko
2020-05-15 10:47 ` [PATCH v2 14/19] spi: dw: Remove DW DMA code dependency from DW_DMAC_PCI Serge Semin
` (13 subsequent siblings)
19 siblings, 1 reply; 106+ messages in thread
From: Serge Semin @ 2020-05-15 10:47 UTC (permalink / raw)
To: Mark Brown
Cc: Serge Semin, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Arnd Bergmann, Allison Randal, Andy Shevchenko, Gareth Williams,
Rob Herring, linux-mips, devicetree, Wan Ahmad Zainie,
Jarkko Nikula, Jay Fang, Thomas Gleixner, YueHaibing,
Stephen Boyd, linux-spi, linux-kernel
This field is used only for the DW SPI DMA code initialization, that's
why there were no problems with it being uninitialized in Dw SPI MMIO
driver. Since in a further patch we are going to introduce the DW SPI DMA
support in the MMIO version of the driver, lets set the field with the
physical address of the DW SPI controller registers region.
Co-developed-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
Signed-off-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
Co-developed-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
Signed-off-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Allison Randal <allison@lohutok.net>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Gareth Williams <gareth.williams.jx@renesas.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: devicetree@vger.kernel.org
---
drivers/spi/spi-dw-mmio.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c
index 398f7926cf92..0894b4c09496 100644
--- a/drivers/spi/spi-dw-mmio.c
+++ b/drivers/spi/spi-dw-mmio.c
@@ -184,6 +184,7 @@ static int dw_spi_mmio_probe(struct platform_device *pdev)
int (*init_func)(struct platform_device *pdev,
struct dw_spi_mmio *dwsmmio);
struct dw_spi_mmio *dwsmmio;
+ struct resource *mem;
struct dw_spi *dws;
int ret;
int num_cs;
@@ -196,10 +197,12 @@ static int dw_spi_mmio_probe(struct platform_device *pdev)
dws = &dwsmmio->dws;
/* Get basic io resource and map it */
- dws->regs = devm_platform_ioremap_resource(pdev, 0);
+ dws->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
if (IS_ERR(dws->regs))
return PTR_ERR(dws->regs);
+ dws->paddr = mem->start;
+
dws->irq = platform_get_irq(pdev, 0);
if (dws->irq < 0)
return dws->irq; /* -ENXIO */
--
2.25.1
^ permalink raw reply related [flat|nested] 106+ messages in thread
* Re: [PATCH v2 11/19] spi: dw: Initialize paddr in DW SPI MMIO private data
2020-05-15 10:47 ` [PATCH v2 11/19] spi: dw: Initialize paddr in DW SPI MMIO private data Serge Semin
@ 2020-05-15 14:39 ` Andy Shevchenko
0 siblings, 0 replies; 106+ messages in thread
From: Andy Shevchenko @ 2020-05-15 14:39 UTC (permalink / raw)
To: Serge Semin
Cc: Mark Brown, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Arnd Bergmann, Allison Randal, Gareth Williams, Rob Herring,
linux-mips, devicetree, Wan Ahmad Zainie, Jarkko Nikula,
Jay Fang, Thomas Gleixner, YueHaibing, Stephen Boyd, linux-spi,
linux-kernel
On Fri, May 15, 2020 at 01:47:50PM +0300, Serge Semin wrote:
> This field is used only for the DW SPI DMA code initialization, that's
> why there were no problems with it being uninitialized in Dw SPI MMIO
> driver. Since in a further patch we are going to introduce the DW SPI DMA
> support in the MMIO version of the driver, lets set the field with the
> physical address of the DW SPI controller registers region.
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
>
> Co-developed-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
> Signed-off-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
> Co-developed-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
> Signed-off-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> Cc: Paul Burton <paulburton@kernel.org>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Allison Randal <allison@lohutok.net>
> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Cc: Gareth Williams <gareth.williams.jx@renesas.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: linux-mips@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> ---
> drivers/spi/spi-dw-mmio.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c
> index 398f7926cf92..0894b4c09496 100644
> --- a/drivers/spi/spi-dw-mmio.c
> +++ b/drivers/spi/spi-dw-mmio.c
> @@ -184,6 +184,7 @@ static int dw_spi_mmio_probe(struct platform_device *pdev)
> int (*init_func)(struct platform_device *pdev,
> struct dw_spi_mmio *dwsmmio);
> struct dw_spi_mmio *dwsmmio;
> + struct resource *mem;
> struct dw_spi *dws;
> int ret;
> int num_cs;
> @@ -196,10 +197,12 @@ static int dw_spi_mmio_probe(struct platform_device *pdev)
> dws = &dwsmmio->dws;
>
> /* Get basic io resource and map it */
> - dws->regs = devm_platform_ioremap_resource(pdev, 0);
> + dws->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
> if (IS_ERR(dws->regs))
> return PTR_ERR(dws->regs);
>
> + dws->paddr = mem->start;
> +
> dws->irq = platform_get_irq(pdev, 0);
> if (dws->irq < 0)
> return dws->irq; /* -ENXIO */
> --
> 2.25.1
>
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 106+ messages in thread
* [PATCH v2 14/19] spi: dw: Remove DW DMA code dependency from DW_DMAC_PCI
2020-05-15 10:47 ` [PATCH v2 00/19] spi: dw: Add generic DW DMA controller support Serge Semin
` (5 preceding siblings ...)
2020-05-15 10:47 ` [PATCH v2 11/19] spi: dw: Initialize paddr in DW SPI MMIO private data Serge Semin
@ 2020-05-15 10:47 ` Serge Semin
2020-05-15 15:02 ` Andy Shevchenko
2020-05-15 10:47 ` [PATCH v2 15/19] spi: dw: Add DW SPI DMA/PCI/MMIO dependency on the DW SPI core Serge Semin
` (12 subsequent siblings)
19 siblings, 1 reply; 106+ messages in thread
From: Serge Semin @ 2020-05-15 10:47 UTC (permalink / raw)
To: Mark Brown
Cc: Serge Semin, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Rob Herring, Arnd Bergmann, Allison Randal, Andy Shevchenko,
Gareth Williams, linux-mips, devicetree, John Garry,
Chuanhong Guo, Gregory CLEMENT, Chris Packham, Masahisa Kojima,
Tomer Maimon, Krzysztof Kozlowski, linux-spi, linux-kernel
Since there is a generic method available to initialize the DW SPI DMA
interface on any DT and ACPI-based platforms, which in general can be
designed with not only DW DMAC but with any DMA engine on board, we can
freely remove the CONFIG_DW_DMAC_PCI config from dependency list of
CONFIG_SPI_DW_DMA. Especially seeing that we don't use anything DW DMAC
specific in the new driver.
Co-developed-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
Signed-off-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
Co-developed-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
Signed-off-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Allison Randal <allison@lohutok.net>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Gareth Williams <gareth.williams.jx@renesas.com>
Cc: linux-mips@vger.kernel.org
Cc: devicetree@vger.kernel.org
---
drivers/spi/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 03b061975f70..6a84f3dad35c 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -228,7 +228,7 @@ config SPI_DESIGNWARE
config SPI_DW_DMA
bool "DMA support for DW SPI controller"
- depends on SPI_DESIGNWARE && DW_DMAC_PCI
+ depends on SPI_DESIGNWARE
config SPI_DW_PCI
tristate "PCI interface driver for DW SPI core"
--
2.25.1
^ permalink raw reply related [flat|nested] 106+ messages in thread
* Re: [PATCH v2 14/19] spi: dw: Remove DW DMA code dependency from DW_DMAC_PCI
2020-05-15 10:47 ` [PATCH v2 14/19] spi: dw: Remove DW DMA code dependency from DW_DMAC_PCI Serge Semin
@ 2020-05-15 15:02 ` Andy Shevchenko
0 siblings, 0 replies; 106+ messages in thread
From: Andy Shevchenko @ 2020-05-15 15:02 UTC (permalink / raw)
To: Serge Semin
Cc: Mark Brown, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Rob Herring, Arnd Bergmann, Allison Randal, Gareth Williams,
linux-mips, devicetree, John Garry, Chuanhong Guo,
Gregory CLEMENT, Chris Packham, Masahisa Kojima, Tomer Maimon,
Krzysztof Kozlowski, linux-spi, linux-kernel
On Fri, May 15, 2020 at 01:47:53PM +0300, Serge Semin wrote:
> Since there is a generic method available to initialize the DW SPI DMA
> interface on any DT and ACPI-based platforms, which in general can be
> designed with not only DW DMAC but with any DMA engine on board, we can
> freely remove the CONFIG_DW_DMAC_PCI config from dependency list of
> CONFIG_SPI_DW_DMA. Especially seeing that we don't use anything DW DMAC
> specific in the new driver.
Right, and used data structures are always available at compile time.
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Co-developed-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
> Signed-off-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
> Co-developed-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
> Signed-off-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> Cc: Paul Burton <paulburton@kernel.org>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Allison Randal <allison@lohutok.net>
> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Cc: Gareth Williams <gareth.williams.jx@renesas.com>
> Cc: linux-mips@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> ---
> drivers/spi/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index 03b061975f70..6a84f3dad35c 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -228,7 +228,7 @@ config SPI_DESIGNWARE
>
> config SPI_DW_DMA
> bool "DMA support for DW SPI controller"
> - depends on SPI_DESIGNWARE && DW_DMAC_PCI
> + depends on SPI_DESIGNWARE
>
> config SPI_DW_PCI
> tristate "PCI interface driver for DW SPI core"
> --
> 2.25.1
>
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 106+ messages in thread
* [PATCH v2 15/19] spi: dw: Add DW SPI DMA/PCI/MMIO dependency on the DW SPI core
2020-05-15 10:47 ` [PATCH v2 00/19] spi: dw: Add generic DW DMA controller support Serge Semin
` (6 preceding siblings ...)
2020-05-15 10:47 ` [PATCH v2 14/19] spi: dw: Remove DW DMA code dependency from DW_DMAC_PCI Serge Semin
@ 2020-05-15 10:47 ` Serge Semin
2020-05-15 15:03 ` Andy Shevchenko
2020-05-15 10:47 ` [PATCH v2 17/19] spi: dw: Add DMA support to the DW SPI MMIO driver Serge Semin
` (11 subsequent siblings)
19 siblings, 1 reply; 106+ messages in thread
From: Serge Semin @ 2020-05-15 10:47 UTC (permalink / raw)
To: Mark Brown
Cc: Serge Semin, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Arnd Bergmann, Allison Randal, Andy Shevchenko, Gareth Williams,
Rob Herring, linux-mips, devicetree, John Garry, Chuanhong Guo,
Masahisa Kojima, Chris Packham, Tomer Maimon,
Krzysztof Kozlowski, linux-spi, linux-kernel
Seeing all of the DW SPI driver components like DW SPI DMA/PCI/MMIO
depend on the DW SPI core code it's better to use the if-endif
conditional kernel config statement to signify that common dependency.
Co-developed-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
Signed-off-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
Co-developed-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
Signed-off-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Allison Randal <allison@lohutok.net>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Gareth Williams <gareth.williams.jx@renesas.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: devicetree@vger.kernel.org
---
drivers/spi/Kconfig | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 6a84f3dad35c..3cdf8310d185 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -226,17 +226,20 @@ config SPI_DESIGNWARE
help
general driver for SPI controller core from DesignWare
+if SPI_DESIGNWARE
+
config SPI_DW_DMA
bool "DMA support for DW SPI controller"
- depends on SPI_DESIGNWARE
config SPI_DW_PCI
tristate "PCI interface driver for DW SPI core"
- depends on SPI_DESIGNWARE && PCI
+ depends on PCI
config SPI_DW_MMIO
tristate "Memory-mapped io interface driver for DW SPI core"
- depends on SPI_DESIGNWARE
+ depends on HAS_IOMEM
+
+endif
config SPI_DLN2
tristate "Diolan DLN-2 USB SPI adapter"
--
2.25.1
^ permalink raw reply related [flat|nested] 106+ messages in thread
* Re: [PATCH v2 15/19] spi: dw: Add DW SPI DMA/PCI/MMIO dependency on the DW SPI core
2020-05-15 10:47 ` [PATCH v2 15/19] spi: dw: Add DW SPI DMA/PCI/MMIO dependency on the DW SPI core Serge Semin
@ 2020-05-15 15:03 ` Andy Shevchenko
0 siblings, 0 replies; 106+ messages in thread
From: Andy Shevchenko @ 2020-05-15 15:03 UTC (permalink / raw)
To: Serge Semin
Cc: Mark Brown, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Arnd Bergmann, Allison Randal, Gareth Williams, Rob Herring,
linux-mips, devicetree, John Garry, Chuanhong Guo,
Masahisa Kojima, Chris Packham, Tomer Maimon,
Krzysztof Kozlowski, linux-spi, linux-kernel
On Fri, May 15, 2020 at 01:47:54PM +0300, Serge Semin wrote:
> Seeing all of the DW SPI driver components like DW SPI DMA/PCI/MMIO
> depend on the DW SPI core code it's better to use the if-endif
> conditional kernel config statement to signify that common dependency.
Makes sense!
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
>
> Co-developed-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
> Signed-off-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
> Co-developed-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
> Signed-off-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> Cc: Paul Burton <paulburton@kernel.org>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Allison Randal <allison@lohutok.net>
> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Cc: Gareth Williams <gareth.williams.jx@renesas.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: linux-mips@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> ---
> drivers/spi/Kconfig | 9 ++++++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index 6a84f3dad35c..3cdf8310d185 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -226,17 +226,20 @@ config SPI_DESIGNWARE
> help
> general driver for SPI controller core from DesignWare
>
> +if SPI_DESIGNWARE
> +
> config SPI_DW_DMA
> bool "DMA support for DW SPI controller"
> - depends on SPI_DESIGNWARE
>
> config SPI_DW_PCI
> tristate "PCI interface driver for DW SPI core"
> - depends on SPI_DESIGNWARE && PCI
> + depends on PCI
>
> config SPI_DW_MMIO
> tristate "Memory-mapped io interface driver for DW SPI core"
> - depends on SPI_DESIGNWARE
> + depends on HAS_IOMEM
> +
> +endif
>
> config SPI_DLN2
> tristate "Diolan DLN-2 USB SPI adapter"
> --
> 2.25.1
>
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 106+ messages in thread
* [PATCH v2 17/19] spi: dw: Add DMA support to the DW SPI MMIO driver
2020-05-15 10:47 ` [PATCH v2 00/19] spi: dw: Add generic DW DMA controller support Serge Semin
` (7 preceding siblings ...)
2020-05-15 10:47 ` [PATCH v2 15/19] spi: dw: Add DW SPI DMA/PCI/MMIO dependency on the DW SPI core Serge Semin
@ 2020-05-15 10:47 ` Serge Semin
2020-05-15 15:08 ` Andy Shevchenko
2020-05-15 10:47 ` [PATCH v2 19/19] dt-bindings: spi: Convert DW SPI binding to DT schema Serge Semin
` (10 subsequent siblings)
19 siblings, 1 reply; 106+ messages in thread
From: Serge Semin @ 2020-05-15 10:47 UTC (permalink / raw)
To: Mark Brown
Cc: Serge Semin, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Arnd Bergmann, Allison Randal, Andy Shevchenko, Gareth Williams,
Rob Herring, linux-mips, devicetree, Wan Ahmad Zainie,
Jarkko Nikula, Jay Fang, Thomas Gleixner, YueHaibing,
Stephen Boyd, linux-spi, linux-kernel
Since the common code in the spi-dw-dma.c driver is ready to be used
by the MMIO driver and now provides a method to generically (on any
DT or ACPI-based platforms) retrieve the Tx/Rx DMA channel handlers,
we can use it and a set of the common DW SPI DMA callbacks to enable
DMA at least for generic "snps,dw-apb-ssi" and "snps,dwc-ssi-1.01a"
devices.
Co-developed-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
Signed-off-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
Co-developed-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
Signed-off-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Allison Randal <allison@lohutok.net>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Gareth Williams <gareth.williams.jx@renesas.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: devicetree@vger.kernel.org
---
drivers/spi/spi-dw-mmio.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c
index 0894b4c09496..e23d0c53a664 100644
--- a/drivers/spi/spi-dw-mmio.c
+++ b/drivers/spi/spi-dw-mmio.c
@@ -149,6 +149,8 @@ static int dw_spi_dw_apb_init(struct platform_device *pdev,
/* Register hook to configure CTRLR0 */
dwsmmio->dws.update_cr0 = dw_spi_update_cr0;
+ dw_spi_dma_setup_generic(&dwsmmio->dws);
+
return 0;
}
@@ -158,6 +160,8 @@ static int dw_spi_dwc_ssi_init(struct platform_device *pdev,
/* Register hook to configure CTRLR0 */
dwsmmio->dws.update_cr0 = dw_spi_update_cr0_v1_01a;
+ dw_spi_dma_setup_generic(&dwsmmio->dws);
+
return 0;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 106+ messages in thread
* Re: [PATCH v2 17/19] spi: dw: Add DMA support to the DW SPI MMIO driver
2020-05-15 10:47 ` [PATCH v2 17/19] spi: dw: Add DMA support to the DW SPI MMIO driver Serge Semin
@ 2020-05-15 15:08 ` Andy Shevchenko
0 siblings, 0 replies; 106+ messages in thread
From: Andy Shevchenko @ 2020-05-15 15:08 UTC (permalink / raw)
To: Serge Semin
Cc: Mark Brown, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Arnd Bergmann, Allison Randal, Gareth Williams, Rob Herring,
linux-mips, devicetree, Wan Ahmad Zainie, Jarkko Nikula,
Jay Fang, Thomas Gleixner, YueHaibing, Stephen Boyd, linux-spi,
linux-kernel
On Fri, May 15, 2020 at 01:47:56PM +0300, Serge Semin wrote:
> Since the common code in the spi-dw-dma.c driver is ready to be used
> by the MMIO driver and now provides a method to generically (on any
> DT or ACPI-based platforms) retrieve the Tx/Rx DMA channel handlers,
> we can use it and a set of the common DW SPI DMA callbacks to enable
> DMA at least for generic "snps,dw-apb-ssi" and "snps,dwc-ssi-1.01a"
> devices.
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
>
> Co-developed-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
> Signed-off-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
> Co-developed-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
> Signed-off-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> Cc: Paul Burton <paulburton@kernel.org>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Allison Randal <allison@lohutok.net>
> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Cc: Gareth Williams <gareth.williams.jx@renesas.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: linux-mips@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> ---
> drivers/spi/spi-dw-mmio.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c
> index 0894b4c09496..e23d0c53a664 100644
> --- a/drivers/spi/spi-dw-mmio.c
> +++ b/drivers/spi/spi-dw-mmio.c
> @@ -149,6 +149,8 @@ static int dw_spi_dw_apb_init(struct platform_device *pdev,
> /* Register hook to configure CTRLR0 */
> dwsmmio->dws.update_cr0 = dw_spi_update_cr0;
>
> + dw_spi_dma_setup_generic(&dwsmmio->dws);
> +
> return 0;
> }
>
> @@ -158,6 +160,8 @@ static int dw_spi_dwc_ssi_init(struct platform_device *pdev,
> /* Register hook to configure CTRLR0 */
> dwsmmio->dws.update_cr0 = dw_spi_update_cr0_v1_01a;
>
> + dw_spi_dma_setup_generic(&dwsmmio->dws);
> +
> return 0;
> }
>
> --
> 2.25.1
>
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 106+ messages in thread
* [PATCH v2 19/19] dt-bindings: spi: Convert DW SPI binding to DT schema
2020-05-15 10:47 ` [PATCH v2 00/19] spi: dw: Add generic DW DMA controller support Serge Semin
` (8 preceding siblings ...)
2020-05-15 10:47 ` [PATCH v2 17/19] spi: dw: Add DMA support to the DW SPI MMIO driver Serge Semin
@ 2020-05-15 10:47 ` Serge Semin
2020-05-16 20:59 ` Serge Semin
2020-05-15 11:49 ` [PATCH v2 00/19] spi: dw: Add generic DW DMA controller support Andy Shevchenko
` (9 subsequent siblings)
19 siblings, 1 reply; 106+ messages in thread
From: Serge Semin @ 2020-05-15 10:47 UTC (permalink / raw)
To: Mark Brown, Rob Herring
Cc: Serge Semin, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Arnd Bergmann, Allison Randal, Andy Shevchenko, Gareth Williams,
linux-mips, Wan Ahmad Zainie, linux-spi, devicetree,
linux-kernel
Modern device tree bindings are supposed to be created as YAML-files
in accordance with dt-schema. This commit replaces two DW SPI legacy
bare text bindings with YAML file. As before the bindings file states
that the corresponding dts node is supposed to be compatible either
with generic DW APB SSI controller or with Microsemi/Amazon/Renesas/Intel
vendors-specific controllers, to have registers, interrupts and clocks
properties. Though in case of Microsemi version of the controller
there must be two registers resources specified. Properties like
clock-names, reg-io-width, cs-gpio, num-cs, DMA and slave device
sub-nodes are optional.
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
Cc: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Allison Randal <allison@lohutok.net>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Gareth Williams <gareth.williams.jx@renesas.com>
Cc: linux-mips@vger.kernel.org
---
.../bindings/spi/snps,dw-apb-ssi.txt | 44 ------
.../bindings/spi/snps,dw-apb-ssi.yaml | 127 ++++++++++++++++++
.../devicetree/bindings/spi/spi-dw.txt | 24 ----
3 files changed, 127 insertions(+), 68 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
create mode 100644 Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
delete mode 100644 Documentation/devicetree/bindings/spi/spi-dw.txt
diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
deleted file mode 100644
index 020e3168ee41..000000000000
--- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
+++ /dev/null
@@ -1,44 +0,0 @@
-Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface.
-
-Required properties:
-- compatible : "snps,dw-apb-ssi" or "mscc,<soc>-spi", where soc is "ocelot" or
- "jaguar2", or "amazon,alpine-dw-apb-ssi", or "snps,dwc-ssi-1.01a" or
- "intel,keembay-ssi"
-- reg : The register base for the controller. For "mscc,<soc>-spi", a second
- register set is required (named ICPU_CFG:SPI_MST)
-- interrupts : One interrupt, used by the controller.
-- #address-cells : <1>, as required by generic SPI binding.
-- #size-cells : <0>, also as required by generic SPI binding.
-- clocks : phandles for the clocks, see the description of clock-names below.
- The phandle for the "ssi_clk" is required. The phandle for the "pclk" clock
- is optional. If a single clock is specified but no clock-name, it is the
- "ssi_clk" clock. If both clocks are listed, the "ssi_clk" must be first.
-
-Optional properties:
-- clock-names : Contains the names of the clocks:
- "ssi_clk", for the core clock used to generate the external SPI clock.
- "pclk", the interface clock, required for register access. If a clock domain
- used to enable this clock then it should be named "pclk_clkdomain".
-- cs-gpios : Specifies the gpio pins to be used for chipselects.
-- num-cs : The number of chipselects. If omitted, this will default to 4.
-- reg-io-width : The I/O register width (in bytes) implemented by this
- device. Supported values are 2 or 4 (the default).
-- dmas : Phandle + identifiers of Tx and Rx DMA channels.
-- dma-names : Contains the names of the DMA channels. Must be "tx" and "rx".
-
-Child nodes as per the generic SPI binding.
-
-Example:
-
- spi@fff00000 {
- compatible = "snps,dw-apb-ssi";
- reg = <0xfff00000 0x1000>;
- interrupts = <0 154 4>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&spi_m_clk>;
- num-cs = <2>;
- cs-gpios = <&gpio0 13 0>,
- <&gpio0 14 0>;
- };
-
diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
new file mode 100644
index 000000000000..1fcab6415136
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
@@ -0,0 +1,127 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface
+
+maintainers:
+ - Mark Brown <broonie@kernel.org>
+
+allOf:
+ - $ref: "spi-controller.yaml#"
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - mscc,ocelot-spi
+ - mscc,jaguar2-spi
+ then:
+ properties:
+ reg:
+ minItems: 2
+
+properties:
+ compatible:
+ oneOf:
+ - description: Generic DW SPI Controller
+ enum:
+ - snps,dw-apb-ssi
+ - snps,dwc-ssi-1.01a
+ - description: Microsemi Ocelot/Jaguar2 SoC SPI Controller
+ items:
+ - enum:
+ - mscc,ocelot-spi
+ - mscc,jaguar2-spi
+ - const: snps,dw-apb-ssi
+ - description: Amazon Alpine SPI Controller
+ const: amazon,alpine-dw-apb-ssi
+ - description: Renesas RZ/N1 SPI Controller
+ items:
+ - const: renesas,rzn1-spi
+ - const: snps,dw-apb-ssi
+ - description: Intel Keem Bay SPI Controller
+ const: intel,keembay-ssi
+
+ reg:
+ minItems: 1
+ items:
+ - description: DW APB SSI controller memory mapped registers
+ - description: SPI MST region map
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ items:
+ - description: SPI Controller reference clock source
+ - description: APB interface clock source
+
+ clock-names:
+ minItems: 1
+ items:
+ - const: ssi_clk
+ - const: pclk
+
+ reg-io-width:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: I/O register width (in bytes) implemented by this device
+ default: 4
+ enum: [ 2, 4 ]
+
+ num-cs:
+ default: 4
+ minimum: 1
+ maximum: 4
+
+ dmas:
+ items:
+ - description: TX DMA Channel
+ - description: RX DMA Channel
+
+ dma-names:
+ items:
+ - const: tx
+ - const: rx
+
+patternProperties:
+ "^.*@[0-9a-f]+$":
+ type: object
+ properties:
+ reg:
+ minimum: 0
+ maximum: 3
+
+ spi-rx-bus-width:
+ const: 1
+
+ spi-tx-bus-width:
+ const: 1
+
+unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+ - interrupts
+ - clocks
+
+examples:
+ - |
+ spi@fff00000 {
+ compatible = "snps,dw-apb-ssi";
+ reg = <0xfff00000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 154 4>;
+ clocks = <&spi_m_clk>;
+ num-cs = <2>;
+ cs-gpios = <&gpio0 13 0>,
+ <&gpio0 14 0>;
+ };
+...
diff --git a/Documentation/devicetree/bindings/spi/spi-dw.txt b/Documentation/devicetree/bindings/spi/spi-dw.txt
deleted file mode 100644
index 7b63ed601990..000000000000
--- a/Documentation/devicetree/bindings/spi/spi-dw.txt
+++ /dev/null
@@ -1,24 +0,0 @@
-Synopsys DesignWare SPI master
-
-Required properties:
-- compatible: should be "snps,designware-spi"
-- #address-cells: see spi-bus.txt
-- #size-cells: see spi-bus.txt
-- reg: address and length of the spi master registers
-- interrupts: should contain one interrupt
-- clocks: spi clock phandle
-- num-cs: see spi-bus.txt
-
-Optional properties:
-- cs-gpios: see spi-bus.txt
-
-Example:
-
-spi: spi@4020a000 {
- compatible = "snps,designware-spi";
- interrupts = <11 1>;
- reg = <0x4020a000 0x1000>;
- clocks = <&pclk>;
- num-cs = <2>;
- cs-gpios = <&banka 0 0>;
-};
--
2.25.1
^ permalink raw reply related [flat|nested] 106+ messages in thread
* Re: [PATCH v2 19/19] dt-bindings: spi: Convert DW SPI binding to DT schema
2020-05-15 10:47 ` [PATCH v2 19/19] dt-bindings: spi: Convert DW SPI binding to DT schema Serge Semin
@ 2020-05-16 20:59 ` Serge Semin
0 siblings, 0 replies; 106+ messages in thread
From: Serge Semin @ 2020-05-16 20:59 UTC (permalink / raw)
To: Mark Brown, Rob Herring
Cc: Serge Semin, Georgy Vlasov, Ramil Zaripov, Alexey Malahov,
Thomas Bogendoerfer, Paul Burton, Ralf Baechle, Arnd Bergmann,
Allison Randal, Andy Shevchenko, Gareth Williams, linux-mips,
Wan Ahmad Zainie, linux-spi, devicetree, linux-kernel
Rob,
Could you take a look at this patch? We are getting closer to merging the series
into the spi/for-next branch and then to the kernel 5.8. It would be great to
have the bindings converted by the next merge window.
-Sergey
On Fri, May 15, 2020 at 01:47:58PM +0300, Serge Semin wrote:
> Modern device tree bindings are supposed to be created as YAML-files
> in accordance with dt-schema. This commit replaces two DW SPI legacy
> bare text bindings with YAML file. As before the bindings file states
> that the corresponding dts node is supposed to be compatible either
> with generic DW APB SSI controller or with Microsemi/Amazon/Renesas/Intel
> vendors-specific controllers, to have registers, interrupts and clocks
> properties. Though in case of Microsemi version of the controller
> there must be two registers resources specified. Properties like
> clock-names, reg-io-width, cs-gpio, num-cs, DMA and slave device
> sub-nodes are optional.
[nip]
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH v2 00/19] spi: dw: Add generic DW DMA controller support
2020-05-15 10:47 ` [PATCH v2 00/19] spi: dw: Add generic DW DMA controller support Serge Semin
` (9 preceding siblings ...)
2020-05-15 10:47 ` [PATCH v2 19/19] dt-bindings: spi: Convert DW SPI binding to DT schema Serge Semin
@ 2020-05-15 11:49 ` Andy Shevchenko
2020-05-15 15:30 ` Serge Semin
[not found] ` <20200515104758.6934-3-Sergey.Semin@baikalelectronics.ru>
` (8 subsequent siblings)
19 siblings, 1 reply; 106+ messages in thread
From: Andy Shevchenko @ 2020-05-15 11:49 UTC (permalink / raw)
To: Serge Semin
Cc: Mark Brown, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Maxim Kaurkin, Pavel Parkhomenko,
Ekaterina Skachko, Vadim Vlasov, Alexey Kolotnikov,
Thomas Bogendoerfer, Paul Burton, Ralf Baechle, Arnd Bergmann,
Allison Randal, Gareth Williams, Rob Herring, linux-mips,
linux-spi, devicetree, linux-kernel
On Fri, May 15, 2020 at 01:47:39PM +0300, Serge Semin wrote:
> Baikal-T1 SoC provides a DW DMA controller to perform low-speed peripherals
> Mem-to-Dev and Dev-to-Mem transaction. This is also applicable to the DW
> APB SSI devices embedded into the SoC. Currently the DMA-based transfers
> are supported by the DW APB SPI driver only as a middle layer code for
> Intel MID/Elkhart PCI devices. Seeing the same code can be used for normal
> platform DMAC device we introduced a set of patches to fix it within this
> series.
>
> First of all we need to add the Tx and Rx DMA channels support into the DW
> APB SSI binding. Then there are several fixes and cleanups provided as a
> initial preparation for the Generic DMA support integration: add Tx/Rx
> finish wait methods, clear DMAC register when done or stopped, Fix native
> CS being unset, enable interrupts in accordance with DMA xfer mode,
> discard static DW DMA slave structures, discard unused void priv pointer
> and dma_width member of the dw_spi structure, provide the DMA Tx/Rx burst
> length parametrisation and make sure it's optionally set in accordance
> with the DMA max-burst capability.
>
> In order to have the DW APB SSI MMIO driver working with DMA we need to
> initialize the paddr field with the physical base address of the DW APB SSI
> registers space. Then we unpin the Intel MID specific code from the
> generic DMA one and placed it into the spi-dw-pci.c driver, which is a
> better place for it anyway. After that the naming cleanups are performed
> since the code is going to be used for a generic DMAC device. Finally the
> Generic DMA initialization can be added to the generic version of the
> DW APB SSI IP.
>
> Last but not least we traditionally convert the legacy plain text-based
> dt-binding file with yaml-based one and as a cherry on a cake replace
> the manually written DebugFS registers read method with a ready-to-use
> for the same purpose regset32 DebugFS interface usage.
>
> This patchset is rebased and tested on the spi/for-next (5.7-rc5):
> base-commit: fe9fce6b2cf3 ("Merge remote-tracking branch 'spi/for-5.8' into spi-next")
Thanks! I'm going to review it soon.
Hint for the next time, please start always a new thread with new version.
> Co-developed-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
> Signed-off-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
> Co-developed-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
> Signed-off-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: Maxim Kaurkin <Maxim.Kaurkin@baikalelectronics.ru>
> Cc: Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>
> Cc: Ekaterina Skachko <Ekaterina.Skachko@baikalelectronics.ru>
> Cc: Vadim Vlasov <V.Vlasov@baikalelectronics.ru>
> Cc: Alexey Kolotnikov <Alexey.Kolotnikov@baikalelectronics.ru>
> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> Cc: Paul Burton <paulburton@kernel.org>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Allison Randal <allison@lohutok.net>
> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Cc: Gareth Williams <gareth.williams.jx@renesas.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: linux-mips@vger.kernel.org
> Cc: linux-spi@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
>
> ---
>
> Changelog v2:
> - Rebase on top of the spi repository for-next branch.
> - Move bindings conversion patch to the tail of the series.
> - Move fixes to the head of the series.
> - Apply as many changes as possible to be applied the Generic DMA
> functionality support is added and the spi-dw-mid is moved to the
> spi-dw-dma driver.
> - Discard patch "spi: dw: Fix dma_slave_config used partly uninitialized"
> since the problem has already been fixed.
> - Add new patch "spi: dw: Discard unused void priv pointer".
> - Add new patch "spi: dw: Discard dma_width member of the dw_spi structure".
> n_bytes member of the DW SPI data can be used instead.
> - Build the DMA functionality into the DW APB SSI core if required instead
> of creating a separate kernel module.
> - Use conditional statement instead of the ternary operator in the ref
> clock getter.
>
> Serge Semin (19):
> dt-bindings: spi: dw: Add Tx/Rx DMA properties
> spi: dw: Add Tx/Rx finish wait methods to the MID DMA
> spi: dw: Clear DMAC register when done or stopped
> spi: dw: Fix native CS being unset
> spi: dw: Enable interrupts in accordance with DMA xfer mode
> spi: dw: Discard static DW DMA slave structures
> spi: dw: Discard unused void priv pointer
> spi: dw: Discard dma_width member of the dw_spi structure
> spi: dw: Parameterize the DMA Rx/Tx burst length
> spi: dw: Use DMA max burst to set the request thresholds
> spi: dw: Initialize paddr in DW SPI MMIO private data
> spi: dw: Fix Rx-only DMA transfers
> spi: dw: Move Non-DMA code to the DW PCIe-SPI driver
> spi: dw: Remove DW DMA code dependency from DW_DMAC_PCI
> spi: dw: Add DW SPI DMA/PCI/MMIO dependency on the DW SPI core
> spi: dw: Cleanup generic DW DMA code namings
> spi: dw: Add DMA support to the DW SPI MMIO driver
> spi: dw: Use regset32 DebugFS method to create regdump file
> dt-bindings: spi: Convert DW SPI binding to DT schema
>
> .../bindings/spi/snps,dw-apb-ssi.txt | 42 ---
> .../bindings/spi/snps,dw-apb-ssi.yaml | 127 +++++++++
> .../devicetree/bindings/spi/spi-dw.txt | 24 --
> drivers/spi/Kconfig | 15 +-
> drivers/spi/Makefile | 7 +-
> drivers/spi/{spi-dw-mid.c => spi-dw-dma.c} | 257 ++++++++++--------
> drivers/spi/spi-dw-mmio.c | 9 +-
> drivers/spi/spi-dw-pci.c | 50 +++-
> drivers/spi/spi-dw.c | 98 +++----
> drivers/spi/spi-dw.h | 33 ++-
> 10 files changed, 405 insertions(+), 257 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
> create mode 100644 Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> delete mode 100644 Documentation/devicetree/bindings/spi/spi-dw.txt
> rename drivers/spi/{spi-dw-mid.c => spi-dw-dma.c} (53%)
>
> --
> 2.25.1
>
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH v2 00/19] spi: dw: Add generic DW DMA controller support
2020-05-15 11:49 ` [PATCH v2 00/19] spi: dw: Add generic DW DMA controller support Andy Shevchenko
@ 2020-05-15 15:30 ` Serge Semin
0 siblings, 0 replies; 106+ messages in thread
From: Serge Semin @ 2020-05-15 15:30 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Serge Semin, Mark Brown, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Maxim Kaurkin, Pavel Parkhomenko,
Ekaterina Skachko, Vadim Vlasov, Alexey Kolotnikov,
Thomas Bogendoerfer, Paul Burton, Ralf Baechle, Arnd Bergmann,
Allison Randal, Gareth Williams, Rob Herring, linux-mips,
linux-spi, devicetree, linux-kernel
On Fri, May 15, 2020 at 02:49:50PM +0300, Andy Shevchenko wrote:
> On Fri, May 15, 2020 at 01:47:39PM +0300, Serge Semin wrote:
> > Baikal-T1 SoC provides a DW DMA controller to perform low-speed peripherals
> > Mem-to-Dev and Dev-to-Mem transaction. This is also applicable to the DW
> > APB SSI devices embedded into the SoC. Currently the DMA-based transfers
> > are supported by the DW APB SPI driver only as a middle layer code for
> > Intel MID/Elkhart PCI devices. Seeing the same code can be used for normal
> > platform DMAC device we introduced a set of patches to fix it within this
> > series.
> >
> > First of all we need to add the Tx and Rx DMA channels support into the DW
> > APB SSI binding. Then there are several fixes and cleanups provided as a
> > initial preparation for the Generic DMA support integration: add Tx/Rx
> > finish wait methods, clear DMAC register when done or stopped, Fix native
> > CS being unset, enable interrupts in accordance with DMA xfer mode,
> > discard static DW DMA slave structures, discard unused void priv pointer
> > and dma_width member of the dw_spi structure, provide the DMA Tx/Rx burst
> > length parametrisation and make sure it's optionally set in accordance
> > with the DMA max-burst capability.
> >
> > In order to have the DW APB SSI MMIO driver working with DMA we need to
> > initialize the paddr field with the physical base address of the DW APB SSI
> > registers space. Then we unpin the Intel MID specific code from the
> > generic DMA one and placed it into the spi-dw-pci.c driver, which is a
> > better place for it anyway. After that the naming cleanups are performed
> > since the code is going to be used for a generic DMAC device. Finally the
> > Generic DMA initialization can be added to the generic version of the
> > DW APB SSI IP.
> >
> > Last but not least we traditionally convert the legacy plain text-based
> > dt-binding file with yaml-based one and as a cherry on a cake replace
> > the manually written DebugFS registers read method with a ready-to-use
> > for the same purpose regset32 DebugFS interface usage.
> >
> > This patchset is rebased and tested on the spi/for-next (5.7-rc5):
> > base-commit: fe9fce6b2cf3 ("Merge remote-tracking branch 'spi/for-5.8' into spi-next")
>
> Thanks! I'm going to review it soon.
>
> Hint for the next time, please start always a new thread with new version.
Thanks for suggestion. Indeed my knowledge of the submission procedure has
been incomplete: "However, for a multi-patch series, it is generally best
to avoid using In-Reply-To: to link to older versions of the series.
This way multiple versions of the patch don't become an unmanageable
forest of references in email clients." [1]
[1] Documentation/process/submitting-patches.rst
-Sergey
>
> > Co-developed-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
> > Signed-off-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
> > Co-developed-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
> > Signed-off-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
> > Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> > Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> > Cc: Maxim Kaurkin <Maxim.Kaurkin@baikalelectronics.ru>
> > Cc: Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>
> > Cc: Ekaterina Skachko <Ekaterina.Skachko@baikalelectronics.ru>
> > Cc: Vadim Vlasov <V.Vlasov@baikalelectronics.ru>
> > Cc: Alexey Kolotnikov <Alexey.Kolotnikov@baikalelectronics.ru>
> > Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> > Cc: Paul Burton <paulburton@kernel.org>
> > Cc: Ralf Baechle <ralf@linux-mips.org>
> > Cc: Arnd Bergmann <arnd@arndb.de>
> > Cc: Allison Randal <allison@lohutok.net>
> > Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> > Cc: Gareth Williams <gareth.williams.jx@renesas.com>
> > Cc: Rob Herring <robh+dt@kernel.org>
> > Cc: linux-mips@vger.kernel.org
> > Cc: linux-spi@vger.kernel.org
> > Cc: devicetree@vger.kernel.org
> > Cc: linux-kernel@vger.kernel.org
> >
> > ---
> >
> > Changelog v2:
> > - Rebase on top of the spi repository for-next branch.
> > - Move bindings conversion patch to the tail of the series.
> > - Move fixes to the head of the series.
> > - Apply as many changes as possible to be applied the Generic DMA
> > functionality support is added and the spi-dw-mid is moved to the
> > spi-dw-dma driver.
> > - Discard patch "spi: dw: Fix dma_slave_config used partly uninitialized"
> > since the problem has already been fixed.
> > - Add new patch "spi: dw: Discard unused void priv pointer".
> > - Add new patch "spi: dw: Discard dma_width member of the dw_spi structure".
> > n_bytes member of the DW SPI data can be used instead.
> > - Build the DMA functionality into the DW APB SSI core if required instead
> > of creating a separate kernel module.
> > - Use conditional statement instead of the ternary operator in the ref
> > clock getter.
> >
> > Serge Semin (19):
> > dt-bindings: spi: dw: Add Tx/Rx DMA properties
> > spi: dw: Add Tx/Rx finish wait methods to the MID DMA
> > spi: dw: Clear DMAC register when done or stopped
> > spi: dw: Fix native CS being unset
> > spi: dw: Enable interrupts in accordance with DMA xfer mode
> > spi: dw: Discard static DW DMA slave structures
> > spi: dw: Discard unused void priv pointer
> > spi: dw: Discard dma_width member of the dw_spi structure
> > spi: dw: Parameterize the DMA Rx/Tx burst length
> > spi: dw: Use DMA max burst to set the request thresholds
> > spi: dw: Initialize paddr in DW SPI MMIO private data
> > spi: dw: Fix Rx-only DMA transfers
> > spi: dw: Move Non-DMA code to the DW PCIe-SPI driver
> > spi: dw: Remove DW DMA code dependency from DW_DMAC_PCI
> > spi: dw: Add DW SPI DMA/PCI/MMIO dependency on the DW SPI core
> > spi: dw: Cleanup generic DW DMA code namings
> > spi: dw: Add DMA support to the DW SPI MMIO driver
> > spi: dw: Use regset32 DebugFS method to create regdump file
> > dt-bindings: spi: Convert DW SPI binding to DT schema
> >
> > .../bindings/spi/snps,dw-apb-ssi.txt | 42 ---
> > .../bindings/spi/snps,dw-apb-ssi.yaml | 127 +++++++++
> > .../devicetree/bindings/spi/spi-dw.txt | 24 --
> > drivers/spi/Kconfig | 15 +-
> > drivers/spi/Makefile | 7 +-
> > drivers/spi/{spi-dw-mid.c => spi-dw-dma.c} | 257 ++++++++++--------
> > drivers/spi/spi-dw-mmio.c | 9 +-
> > drivers/spi/spi-dw-pci.c | 50 +++-
> > drivers/spi/spi-dw.c | 98 +++----
> > drivers/spi/spi-dw.h | 33 ++-
> > 10 files changed, 405 insertions(+), 257 deletions(-)
> > delete mode 100644 Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
> > create mode 100644 Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> > delete mode 100644 Documentation/devicetree/bindings/spi/spi-dw.txt
> > rename drivers/spi/{spi-dw-mid.c => spi-dw-dma.c} (53%)
> >
> > --
> > 2.25.1
> >
>
> --
> With Best Regards,
> Andy Shevchenko
>
>
^ permalink raw reply [flat|nested] 106+ messages in thread
[parent not found: <20200515104758.6934-3-Sergey.Semin@baikalelectronics.ru>]
* Re: [PATCH v2 02/19] spi: dw: Add Tx/Rx finish wait methods to the MID DMA
[not found] ` <20200515104758.6934-3-Sergey.Semin@baikalelectronics.ru>
@ 2020-05-15 12:01 ` Andy Shevchenko
2020-05-15 12:18 ` Mark Brown
[not found] ` <20200515194058.pmpd4wa7lw2dle3g@mobilestation>
0 siblings, 2 replies; 106+ messages in thread
From: Andy Shevchenko @ 2020-05-15 12:01 UTC (permalink / raw)
To: Serge Semin
Cc: Mark Brown, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Arnd Bergmann, Allison Randal, Gareth Williams, Rob Herring,
linux-mips, devicetree, Jarkko Nikula, Wan Ahmad Zainie,
Thomas Gleixner, wuxu.wu, Clement Leger, linux-spi, linux-kernel
On Fri, May 15, 2020 at 01:47:41PM +0300, Serge Semin wrote:
> Since DMA transfers are performed asynchronously with actual SPI
> transaction, then even if DMA transfers are finished it doesn't mean
> all data is actually pushed to the SPI bus. Some data might still be
> in the controller FIFO. This is specifically true for Tx-only
> transfers. In this case if the next SPI transfer is recharged while
> a tail of the previous one is still in FIFO, we'll loose that tail
> data. In order to fix this lets add the wait procedure of the Tx/Rx
> SPI transfers completion after the corresponding DMA transactions
> are finished.
General question, doesn't spi core provides us some helpers like
spi_delay_exec()?
> Co-developed-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
> Signed-off-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Cc: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> Cc: Paul Burton <paulburton@kernel.org>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Allison Randal <allison@lohutok.net>
> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Cc: Gareth Williams <gareth.williams.jx@renesas.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: linux-mips@vger.kernel.org
> Cc: devicetree@vger.kernel.org
>
> ---
>
> Changelog v2:
> - Use conditional statement instead of the ternary operator in the ref
> clock getter.
> - Move the patch to the head of the series so one could be picked up to
> the stable kernels as a fix.
You forgot a Fixes tag.
> ---
> drivers/spi/spi-dw-mid.c | 50 ++++++++++++++++++++++++++++++++++++++++
> drivers/spi/spi-dw.h | 10 ++++++++
> 2 files changed, 60 insertions(+)
>
> diff --git a/drivers/spi/spi-dw-mid.c b/drivers/spi/spi-dw-mid.c
> index 177e1f5ec62b..7a5ae1506365 100644
> --- a/drivers/spi/spi-dw-mid.c
> +++ b/drivers/spi/spi-dw-mid.c
> @@ -16,7 +16,9 @@
> #include <linux/irqreturn.h>
> #include <linux/pci.h>
> #include <linux/platform_data/dma-dw.h>
> +#include <linux/delay.h>
Keep it in order.
>
> +#define WAIT_RETRIES 5
> #define RX_BUSY 0
> #define TX_BUSY 1
>
> @@ -141,6 +143,28 @@ static enum dma_slave_buswidth convert_dma_width(u32 dma_width) {
> return DMA_SLAVE_BUSWIDTH_UNDEFINED;
> }
>
> +static inline bool dw_spi_dma_tx_busy(struct dw_spi *dws)
> +{
> + return !(dw_readl(dws, DW_SPI_SR) & SR_TF_EMPT);
> +}
> +
> +static void dw_spi_dma_wait_tx_done(struct dw_spi *dws)
> +{
> + int retry = WAIT_RETRIES;
> + unsigned long ns;
> +
> + ns = (NSEC_PER_SEC / spi_get_clk(dws)) * dws->n_bytes * BITS_PER_BYTE;
> + ns *= dw_readl(dws, DW_SPI_TXFLR);
> +
> + while (dw_spi_dma_tx_busy(dws) && retry--)
> + ndelay(ns);
This misses power management for CPU and do you really need this to be atomic?
At the end why not to use readx_poll_timeout() ?
> + if (retry < 0) {
Usually we do
unsigned int retries = NNNN;
do {
...
} while (--retries);
if (!retries)
...
But in any case, see above.
> + dev_err(&dws->master->dev, "Tx hanged up\n");
> + dws->master->cur_msg->status = -EIO;
> + }
> +}
Same comments to Rx part.
> +
> /*
> * dws->dma_chan_busy is set before the dma transfer starts, callback for tx
> * channel will clear a corresponding bit.
> @@ -149,6 +173,8 @@ static void dw_spi_dma_tx_done(void *arg)
> {
> struct dw_spi *dws = arg;
>
> + dw_spi_dma_wait_tx_done(dws);
> +
> clear_bit(TX_BUSY, &dws->dma_chan_busy);
> if (test_bit(RX_BUSY, &dws->dma_chan_busy))
> return;
> @@ -188,6 +214,28 @@ static struct dma_async_tx_descriptor *dw_spi_dma_prepare_tx(struct dw_spi *dws,
> return txdesc;
> }
>
> +static inline bool dw_spi_dma_rx_busy(struct dw_spi *dws)
> +{
> + return !!(dw_readl(dws, DW_SPI_SR) & SR_RF_NOT_EMPT);
> +}
> +
> +static void dw_spi_dma_wait_rx_done(struct dw_spi *dws)
> +{
> + int retry = WAIT_RETRIES;
> + unsigned long ns;
> +
> + ns = (NSEC_PER_SEC / spi_get_clk(dws)) * dws->n_bytes * BITS_PER_BYTE;
> + ns *= dw_readl(dws, DW_SPI_RXFLR);
> +
> + while (dw_spi_dma_rx_busy(dws) && retry--)
> + ndelay(ns);
> +
> + if (retry < 0) {
> + dev_err(&dws->master->dev, "Rx hanged up\n");
> + dws->master->cur_msg->status = -EIO;
> + }
> +}
> +
> /*
> * dws->dma_chan_busy is set before the dma transfer starts, callback for rx
> * channel will clear a corresponding bit.
> @@ -196,6 +244,8 @@ static void dw_spi_dma_rx_done(void *arg)
> {
> struct dw_spi *dws = arg;
>
> + dw_spi_dma_wait_rx_done(dws);
> +
> clear_bit(RX_BUSY, &dws->dma_chan_busy);
> if (test_bit(TX_BUSY, &dws->dma_chan_busy))
> return;
> diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
> index e92d43b9a9e6..81364f501b7e 100644
> --- a/drivers/spi/spi-dw.h
> +++ b/drivers/spi/spi-dw.h
> @@ -210,6 +210,16 @@ static inline void spi_set_clk(struct dw_spi *dws, u16 div)
> dw_writel(dws, DW_SPI_BAUDR, div);
> }
>
> +static inline u32 spi_get_clk(struct dw_spi *dws)
> +{
> + u32 div = dw_readl(dws, DW_SPI_BAUDR);
> +
> + if (!div)
> + return 0;
> +
> + return dws->max_freq / div;
> +}
> +
> /* Disable IRQ bits */
> static inline void spi_mask_intr(struct dw_spi *dws, u32 mask)
> {
> --
> 2.25.1
>
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH v2 02/19] spi: dw: Add Tx/Rx finish wait methods to the MID DMA
2020-05-15 12:01 ` [PATCH v2 02/19] spi: dw: Add Tx/Rx finish wait methods to the MID DMA Andy Shevchenko
@ 2020-05-15 12:18 ` Mark Brown
2020-05-15 12:37 ` Andy Shevchenko
[not found] ` <20200515194058.pmpd4wa7lw2dle3g@mobilestation>
1 sibling, 1 reply; 106+ messages in thread
From: Mark Brown @ 2020-05-15 12:18 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Serge Semin, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Arnd Bergmann, Allison Randal, Gareth Williams, Rob Herring,
linux-mips, devicetree, Jarkko Nikula, Wan Ahmad Zainie,
Thomas Gleixner, wuxu.wu, Clement Leger, linux-spi, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 345 bytes --]
On Fri, May 15, 2020 at 03:01:11PM +0300, Andy Shevchenko wrote:
> General question, doesn't spi core provides us some helpers like
> spi_delay_exec()?
Well, nobody wrote one. It's also a bit tricky to handle given that
often you're checking some controller specific things while a FIFO in
the IP drains/fills, though nothing insurmountable.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH v2 02/19] spi: dw: Add Tx/Rx finish wait methods to the MID DMA
2020-05-15 12:18 ` Mark Brown
@ 2020-05-15 12:37 ` Andy Shevchenko
2020-05-15 12:41 ` Mark Brown
0 siblings, 1 reply; 106+ messages in thread
From: Andy Shevchenko @ 2020-05-15 12:37 UTC (permalink / raw)
To: Mark Brown
Cc: Serge Semin, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Arnd Bergmann, Allison Randal, Gareth Williams, Rob Herring,
linux-mips, devicetree, Jarkko Nikula, Wan Ahmad Zainie,
Thomas Gleixner, wuxu.wu, Clement Leger, linux-spi, linux-kernel
On Fri, May 15, 2020 at 01:18:15PM +0100, Mark Brown wrote:
> On Fri, May 15, 2020 at 03:01:11PM +0300, Andy Shevchenko wrote:
>
> > General question, doesn't spi core provides us some helpers like
> > spi_delay_exec()?
>
> Well, nobody wrote one.
spi_delay_exec() seems quite good to be used here.
Can we use it for delays?
> It's also a bit tricky to handle given that
> often you're checking some controller specific things while a FIFO in
> the IP drains/fills, though nothing insurmountable.
Yes, input can be gathered by reading controller specific data.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH v2 02/19] spi: dw: Add Tx/Rx finish wait methods to the MID DMA
2020-05-15 12:37 ` Andy Shevchenko
@ 2020-05-15 12:41 ` Mark Brown
[not found] ` <20200515200250.zjsv5uaftwqcnwud@mobilestation>
0 siblings, 1 reply; 106+ messages in thread
From: Mark Brown @ 2020-05-15 12:41 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Serge Semin, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Arnd Bergmann, Allison Randal, Gareth Williams, Rob Herring,
linux-mips, devicetree, Jarkko Nikula, Wan Ahmad Zainie,
Thomas Gleixner, wuxu.wu, Clement Leger, linux-spi, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 493 bytes --]
On Fri, May 15, 2020 at 03:37:02PM +0300, Andy Shevchenko wrote:
> On Fri, May 15, 2020 at 01:18:15PM +0100, Mark Brown wrote:
> > Well, nobody wrote one.
> spi_delay_exec() seems quite good to be used here.
> Can we use it for delays?
I guess we could, though it's really there because for historical
reasons we've got a bunch of different ways of specifying delays from
client drivers rather than for the executing a delay where you've
already got a good idea of the length of the delay.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 106+ messages in thread
[parent not found: <20200515194058.pmpd4wa7lw2dle3g@mobilestation>]
* Re: [PATCH v2 02/19] spi: dw: Add Tx/Rx finish wait methods to the MID DMA
[not found] ` <20200515194058.pmpd4wa7lw2dle3g@mobilestation>
@ 2020-05-18 10:55 ` Andy Shevchenko
0 siblings, 0 replies; 106+ messages in thread
From: Andy Shevchenko @ 2020-05-18 10:55 UTC (permalink / raw)
To: Serge Semin
Cc: Serge Semin, Mark Brown, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Arnd Bergmann, Allison Randal, Gareth Williams, Rob Herring,
linux-mips, devicetree, Jarkko Nikula, Wan Ahmad Zainie,
Thomas Gleixner, wuxu.wu, Clement Leger, linux-spi, linux-kernel
On Fri, May 15, 2020 at 10:40:58PM +0300, Serge Semin wrote:
> On Fri, May 15, 2020 at 03:01:11PM +0300, Andy Shevchenko wrote:
> > On Fri, May 15, 2020 at 01:47:41PM +0300, Serge Semin wrote:
> > > Since DMA transfers are performed asynchronously with actual SPI
> > > transaction, then even if DMA transfers are finished it doesn't mean
> > > all data is actually pushed to the SPI bus. Some data might still be
> > > in the controller FIFO. This is specifically true for Tx-only
> > > transfers. In this case if the next SPI transfer is recharged while
> > > a tail of the previous one is still in FIFO, we'll loose that tail
> > > data. In order to fix this lets add the wait procedure of the Tx/Rx
> > > SPI transfers completion after the corresponding DMA transactions
> > > are finished.
...
> > You forgot a Fixes tag.
>
> If you find a commit this patch fixes I'd be glad to add the tag.)
I believe you can do it, but I will help you here, what about
7063c0d942a1 ("spi/dw_spi: add DMA support")
or may be more closer to the reality
30c8eb52cc4a ("spi: dw-mid: split rx and tx callbacks when DMA")
?
...
> I will if v3 is needed.
I guess it will be due to Fixes tag.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 106+ messages in thread
[parent not found: <20200515104758.6934-5-Sergey.Semin@baikalelectronics.ru>]
* Re: [PATCH v2 04/19] spi: dw: Fix native CS being unset
[not found] ` <20200515104758.6934-5-Sergey.Semin@baikalelectronics.ru>
@ 2020-05-15 12:05 ` Andy Shevchenko
0 siblings, 0 replies; 106+ messages in thread
From: Andy Shevchenko @ 2020-05-15 12:05 UTC (permalink / raw)
To: Serge Semin
Cc: Mark Brown, Linus Walleij, Charles Keepax, Serge Semin,
Georgy Vlasov, Ramil Zaripov, Alexey Malahov,
Thomas Bogendoerfer, Paul Burton, Ralf Baechle, Arnd Bergmann,
Allison Randal, Gareth Williams, Rob Herring, linux-mips,
devicetree, Wan Ahmad Zainie, Clement Leger, Phil Edworthy,
wuxu.wu, Thomas Gleixner, linux-spi, linux-kernel
On Fri, May 15, 2020 at 01:47:43PM +0300, Serge Semin wrote:
> Commit 6e0a32d6f376 ("spi: dw: Fix default polarity of native
> chipselect") attempted to fix the problem when GPIO active-high
> chip-select is utilized to communicate with some SPI slave. It fixed
> the problem, but broke the normal native CS support. At the same time
> the reversion commit ada9e3fcc175 ("spi: dw: Correct handling of native
> chipselect") didn't solve the problem either, since it just inverted
> the set_cs() polarity perception without taking into account that
> CS-high might be applicable. Here is what is done to finally fix the
> problem.
>
> DW SPI controller demands any native CS being set in order to proceed
> with data transfer. So in order to activate the SPI communications we
> must set any bit in the Slave Select DW SPI controller register no
> matter whether the platform requests the GPIO- or native CS. Preferably
> it should be the bit corresponding to the SPI slave CS number. But
> currently the dw_spi_set_cs() method activates the chip-select
> only if the second argument is false. Since the second argument of the
> set_cs callback is expected to be a boolean with "is-high" semantics
> (actual chip-select pin state value), the bit in the DW SPI Slave
> Select register will be set only if SPI core requests the driver
> to set the CS in the low state. So this will work for active-low
> GPIO-based CS case, and won't work for active-high CS setting
> the bit when SPI core actually needs to deactivate the CS.
>
> This commit fixes the problem for all described cases. So no matter
> whether an SPI slave needs GPIO- or native-based CS with active-high
> or low signal the corresponding bit will be set in SER.
Nice catch!
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Fixes: ada9e3fcc175 ("spi: dw: Correct handling of native chipselect")
> Fixes: 6e0a32d6f376 ("spi: dw: Fix default polarity of native chipselect")
> Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com>
> Acked-by: Linus Walleij <linus.walleij@linaro.org>
> Cc: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
> Cc: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> Cc: Paul Burton <paulburton@kernel.org>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Allison Randal <allison@lohutok.net>
> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Cc: Gareth Williams <gareth.williams.jx@renesas.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: linux-mips@vger.kernel.org
> Cc: devicetree@vger.kernel.org
>
> ---
>
> Changelog v2:
> - Add a comment about SER register, that it must be set to activate the
> SPI communications.
> ---
> drivers/spi/spi-dw.c | 10 +++++++++-
> 1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c
> index 6de196df9c96..450c8218caeb 100644
> --- a/drivers/spi/spi-dw.c
> +++ b/drivers/spi/spi-dw.c
> @@ -124,8 +124,16 @@ static inline void dw_spi_debugfs_remove(struct dw_spi *dws)
> void dw_spi_set_cs(struct spi_device *spi, bool enable)
> {
> struct dw_spi *dws = spi_controller_get_devdata(spi->controller);
> + bool cs_high = !!(spi->mode & SPI_CS_HIGH);
>
> - if (!enable)
> + /*
> + * DW SPI controller demands any native CS being set in order to
> + * proceed with data transfer. So in order to activate the SPI
> + * communications we must set a corresponding bit in the Slave
> + * Enable register no matter whether the SPI core is configured to
> + * support active-high or active-low CS level.
> + */
> + if (cs_high == enable)
> dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select));
> else if (dws->cs_override)
> dw_writel(dws, DW_SPI_SER, 0);
> --
> 2.25.1
>
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 106+ messages in thread
[parent not found: <20200515104758.6934-7-Sergey.Semin@baikalelectronics.ru>]
* Re: [PATCH v2 06/19] spi: dw: Discard static DW DMA slave structures
[not found] ` <20200515104758.6934-7-Sergey.Semin@baikalelectronics.ru>
@ 2020-05-15 12:34 ` Andy Shevchenko
[not found] ` <20200516142030.kburieaxjg4n7c42@mobilestation>
0 siblings, 1 reply; 106+ messages in thread
From: Andy Shevchenko @ 2020-05-15 12:34 UTC (permalink / raw)
To: Serge Semin
Cc: Mark Brown, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Allison Randal, Gareth Williams, Arnd Bergmann, Rob Herring,
linux-mips, devicetree, Wan Ahmad Zainie, Jarkko Nikula,
Thomas Gleixner, wuxu.wu, Clement Leger, linux-spi, linux-kernel
On Fri, May 15, 2020 at 01:47:45PM +0300, Serge Semin wrote:
> Having them declared is redundant since each struct dw_dma_chan has
> the same structure embedded and the structure from the passed dma_chan
> private pointer will be copied there as a result of the next calls
> chain:
> dma_request_channel() -> find_candidate() -> dma_chan_get() ->
> device_alloc_chan_resources() = dwc_alloc_chan_resources() ->
> dw_dma_filter().
> So just remove the static dw_dma_chan structures and use a locally
> declared data instance with dst_id/src_id set to the same values as
> the static copies used to have.
...
> -static struct dw_dma_slave mid_dma_tx = { .dst_id = 1 };
> -static struct dw_dma_slave mid_dma_rx = { .src_id = 0 };
> + struct dw_dma_slave slave = {0};
I really would like to leave them separated and as in the original form, i.e.
struct dw_dma_slave tx = { .dst_id = 1 };
struct dw_dma_slave rx = { .src_id = 0 };
those src and dst IDs are put in that form on purpose...
> + /* 1. Init rx channel (.src_id = 0, .dst_id = 0) */
...this comment adds a bit of confusion.
(Needs more time to parse and understand what IDs are in use)
> + slave.dma_dev = &dma_dev->dev;
> + dws->rxchan = dma_request_channel(mask, mid_spi_dma_chan_filter, &slave);
> + /* 2. Init tx channel (.src_id = 0, .dst_id = 1) */
Ditto.
P.S. Just a recommendation for the future: in all your patches try to be less
invasive where it's possible.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 106+ messages in thread
[parent not found: <20200515104758.6934-8-Sergey.Semin@baikalelectronics.ru>]
* Re: [PATCH v2 07/19] spi: dw: Discard unused void priv pointer
[not found] ` <20200515104758.6934-8-Sergey.Semin@baikalelectronics.ru>
@ 2020-05-15 12:38 ` Andy Shevchenko
0 siblings, 0 replies; 106+ messages in thread
From: Andy Shevchenko @ 2020-05-15 12:38 UTC (permalink / raw)
To: Serge Semin
Cc: Mark Brown, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Allison Randal, Gareth Williams, Arnd Bergmann, Rob Herring,
linux-mips, devicetree, Wan Ahmad Zainie, wuxu.wu, Jarkko Nikula,
Clement Leger, linux-spi, linux-kernel
On Fri, May 15, 2020 at 01:47:46PM +0300, Serge Semin wrote:
> Seeing the "void *priv" member of the dw_spi data structure is unused
> let's remove it. The glue-layers can embed the DW APB SSI controller
> descriptor into their private data object. MMIO driver for instance
> already utilizes that design pattern.
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
>
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Cc: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
> Cc: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> Cc: Paul Burton <paulburton@kernel.org>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: Allison Randal <allison@lohutok.net>
> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Cc: Gareth Williams <gareth.williams.jx@renesas.com>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: linux-mips@vger.kernel.org
> Cc: devicetree@vger.kernel.org
>
> ---
>
> Changelog v2:
> - It's a new patch created as a result of more thorough driver study.
> ---
> drivers/spi/spi-dw.h | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
> index 60e9e430ce7b..b6ab81e0c747 100644
> --- a/drivers/spi/spi-dw.h
> +++ b/drivers/spi/spi-dw.h
> @@ -147,8 +147,6 @@ struct dw_spi {
> dma_addr_t dma_addr; /* phy address of the Data register */
> const struct dw_spi_dma_ops *dma_ops;
>
> - /* Bus interface info */
> - void *priv;
> #ifdef CONFIG_DEBUG_FS
> struct dentry *debugfs;
> #endif
> --
> 2.25.1
>
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 106+ messages in thread
[parent not found: <20200515104758.6934-9-Sergey.Semin@baikalelectronics.ru>]
* Re: [PATCH v2 08/19] spi: dw: Discard dma_width member of the dw_spi structure
[not found] ` <20200515104758.6934-9-Sergey.Semin@baikalelectronics.ru>
@ 2020-05-15 13:03 ` Andy Shevchenko
[not found] ` <20200515130559.psq2zwfhovt6rzhl@mobilestation>
0 siblings, 1 reply; 106+ messages in thread
From: Andy Shevchenko @ 2020-05-15 13:03 UTC (permalink / raw)
To: Serge Semin
Cc: Mark Brown, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Allison Randal, Gareth Williams, Arnd Bergmann, Rob Herring,
linux-mips, devicetree, Jarkko Nikula, Wan Ahmad Zainie,
Thomas Gleixner, Clement Leger, Xinwei Kong, wuxu.wu,
Phil Edworthy, Linus Walleij, linux-spi, linux-kernel
On Fri, May 15, 2020 at 01:47:47PM +0300, Serge Semin wrote:
> This member has exactly the same value as n_bytes of the DW SPI private
> data object, it's calculated at the same point of the transfer method,
> n_bytes isn't changed during the whole transfer, and they even serve for
> the same purpose - keep number of bytes per transfer word, though the
> dma_width is used only to calculate the DMA source/destination addresses
> width, which n_bytes could be also utilized for. Taking all of these
> into account let's replace the dma_width member usage with n_bytes one
> and remove the former.
I've no strong opinion about this.
So, after addressing one issue below,
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Cc: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
> Cc: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> Cc: Paul Burton <paulburton@kernel.org>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: Allison Randal <allison@lohutok.net>
> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Cc: Gareth Williams <gareth.williams.jx@renesas.com>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: linux-mips@vger.kernel.org
> Cc: devicetree@vger.kernel.org
>
> ---
>
> Changelog v2:
> - It's a new patch created as a result of more thorough driver study.
> ---
> drivers/spi/spi-dw-mid.c | 10 +++++-----
> drivers/spi/spi-dw.c | 1 -
> drivers/spi/spi-dw.h | 1 -
> 3 files changed, 5 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/spi/spi-dw-mid.c b/drivers/spi/spi-dw-mid.c
> index be886e22a1b1..ca8813a693d8 100644
> --- a/drivers/spi/spi-dw-mid.c
> +++ b/drivers/spi/spi-dw-mid.c
> @@ -132,10 +132,10 @@ static bool mid_spi_can_dma(struct spi_controller *master,
> return xfer->len > dws->fifo_len;
> }
>
> -static enum dma_slave_buswidth convert_dma_width(u32 dma_width) {
> - if (dma_width == 1)
> +static enum dma_slave_buswidth convert_dma_width(u8 n_bytes) {
It seems somebody (maybe even me) at some point messed up between enum
definition and function that returns an enum.
For what said, { should be on the separate line.
> + if (n_bytes == 1)
> return DMA_SLAVE_BUSWIDTH_1_BYTE;
> - else if (dma_width == 2)
> + else if (n_bytes == 2)
> return DMA_SLAVE_BUSWIDTH_2_BYTES;
>
> return DMA_SLAVE_BUSWIDTH_UNDEFINED;
> @@ -195,7 +195,7 @@ static struct dma_async_tx_descriptor *dw_spi_dma_prepare_tx(struct dw_spi *dws,
> txconf.dst_addr = dws->dma_addr;
> txconf.dst_maxburst = 16;
> txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
> - txconf.dst_addr_width = convert_dma_width(dws->dma_width);
> + txconf.dst_addr_width = convert_dma_width(dws->n_bytes);
> txconf.device_fc = false;
>
> dmaengine_slave_config(dws->txchan, &txconf);
> @@ -268,7 +268,7 @@ static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws,
> rxconf.src_addr = dws->dma_addr;
> rxconf.src_maxburst = 16;
> rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
> - rxconf.src_addr_width = convert_dma_width(dws->dma_width);
> + rxconf.src_addr_width = convert_dma_width(dws->n_bytes);
> rxconf.device_fc = false;
>
> dmaengine_slave_config(dws->rxchan, &rxconf);
> diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c
> index 450c8218caeb..1edb8cdd11ee 100644
> --- a/drivers/spi/spi-dw.c
> +++ b/drivers/spi/spi-dw.c
> @@ -353,7 +353,6 @@ static int dw_spi_transfer_one(struct spi_controller *master,
> }
>
> dws->n_bytes = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE);
> - dws->dma_width = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE);
>
> cr0 = dws->update_cr0(master, spi, transfer);
> dw_writel(dws, DW_SPI_CTRLR0, cr0);
> diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
> index b6ab81e0c747..4902f937c3d7 100644
> --- a/drivers/spi/spi-dw.h
> +++ b/drivers/spi/spi-dw.h
> @@ -136,7 +136,6 @@ struct dw_spi {
> void *rx_end;
> int dma_mapped;
> u8 n_bytes; /* current is a 1/2 bytes op */
> - u32 dma_width;
> irqreturn_t (*transfer_handler)(struct dw_spi *dws);
> u32 current_freq; /* frequency in hz */
>
> --
> 2.25.1
>
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 106+ messages in thread
[parent not found: <20200515104758.6934-13-Sergey.Semin@baikalelectronics.ru>]
* Re: [PATCH v2 12/19] spi: dw: Fix Rx-only DMA transfers
[not found] ` <20200515104758.6934-13-Sergey.Semin@baikalelectronics.ru>
@ 2020-05-15 14:40 ` Andy Shevchenko
2020-05-15 16:55 ` Mark Brown
0 siblings, 1 reply; 106+ messages in thread
From: Andy Shevchenko @ 2020-05-15 14:40 UTC (permalink / raw)
To: Serge Semin
Cc: Mark Brown, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Arnd Bergmann, Allison Randal, Gareth Williams, Rob Herring,
linux-mips, devicetree, Wan Ahmad Zainie, Clement Leger,
Charles Keepax, wuxu.wu, Phil Edworthy, Thomas Gleixner,
linux-spi, linux-kernel
On Fri, May 15, 2020 at 01:47:51PM +0300, Serge Semin wrote:
> Tx-only DMA transfers are working perfectly fine since in this case
> the code just ignores the Rx FIFO overflow interrupts. But it turns
> out the SPI Rx-only transfers are broken since nothing pushing any
> data to the shift registers, so the Rx FIFO is left empty and the
> SPI core subsystems just returns a timeout error. Since DW DMAC
> driver doesn't support something like cyclic write operations of
> a single byte to a device register, the only way to support the
> Rx-only SPI transfers is to fake it by using a dummy Tx-buffer.
> This is what we intend to fix in this commit by setting the
> SPI_CONTROLLER_MUST_TX flag for DMA-capable platform.
I'm fine with this if Mark considers this right thing to do.
So, conditionally
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
>
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Cc: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
> Cc: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> Cc: Paul Burton <paulburton@kernel.org>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Allison Randal <allison@lohutok.net>
> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Cc: Gareth Williams <gareth.williams.jx@renesas.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: linux-mips@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> ---
> drivers/spi/spi-dw.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c
> index 1edb8cdd11ee..31607b40147d 100644
> --- a/drivers/spi/spi-dw.c
> +++ b/drivers/spi/spi-dw.c
> @@ -517,6 +517,7 @@ int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
> dev_warn(dev, "DMA init failed\n");
> } else {
> master->can_dma = dws->dma_ops->can_dma;
> + master->flags |= SPI_CONTROLLER_MUST_TX;
> }
> }
>
> --
> 2.25.1
>
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH v2 12/19] spi: dw: Fix Rx-only DMA transfers
2020-05-15 14:40 ` [PATCH v2 12/19] spi: dw: Fix Rx-only DMA transfers Andy Shevchenko
@ 2020-05-15 16:55 ` Mark Brown
0 siblings, 0 replies; 106+ messages in thread
From: Mark Brown @ 2020-05-15 16:55 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Serge Semin, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Arnd Bergmann, Allison Randal, Gareth Williams, Rob Herring,
linux-mips, devicetree, Wan Ahmad Zainie, Clement Leger,
Charles Keepax, wuxu.wu, Phil Edworthy, Thomas Gleixner,
linux-spi, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 1101 bytes --]
On Fri, May 15, 2020 at 05:40:50PM +0300, Andy Shevchenko wrote:
> On Fri, May 15, 2020 at 01:47:51PM +0300, Serge Semin wrote:
> > Tx-only DMA transfers are working perfectly fine since in this case
> > the code just ignores the Rx FIFO overflow interrupts. But it turns
> > out the SPI Rx-only transfers are broken since nothing pushing any
> > data to the shift registers, so the Rx FIFO is left empty and the
> > SPI core subsystems just returns a timeout error. Since DW DMAC
> > driver doesn't support something like cyclic write operations of
> > a single byte to a device register, the only way to support the
> > Rx-only SPI transfers is to fake it by using a dummy Tx-buffer.
> > This is what we intend to fix in this commit by setting the
> > SPI_CONTROLLER_MUST_TX flag for DMA-capable platform.
> I'm fine with this if Mark considers this right thing to do.
> So, conditionally
> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Yes, this is good - it's quite a common issue that controllers have and
the main reason the flag exists is to provide a standard fix for it.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 106+ messages in thread
[parent not found: <20200515104758.6934-14-Sergey.Semin@baikalelectronics.ru>]
* Re: [PATCH v2 13/19] spi: dw: Move Non-DMA code to the DW PCIe-SPI driver
[not found] ` <20200515104758.6934-14-Sergey.Semin@baikalelectronics.ru>
@ 2020-05-15 14:51 ` Andy Shevchenko
[not found] ` <20200516201724.7q5uhxmzpr6xjooj@mobilestation>
0 siblings, 1 reply; 106+ messages in thread
From: Andy Shevchenko @ 2020-05-15 14:51 UTC (permalink / raw)
To: Serge Semin
Cc: Mark Brown, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Rob Herring, Arnd Bergmann, Allison Randal, Gareth Williams,
linux-mips, devicetree, John Garry, Chuanhong Guo, Joe Perches,
Gregory CLEMENT, Chris Packham, Tomer Maimon, Masahisa Kojima,
Krzysztof Kozlowski, Eddie James, Thomas Gleixner,
Wan Ahmad Zainie, Jarkko Nikula, Chuhong Yuan, Felipe Balbi,
Raymond Tan, wuxu.wu, Clement Leger, linux-spi, linux-kernel
On Fri, May 15, 2020 at 01:47:52PM +0300, Serge Semin wrote:
> This is a preparation patch before adding the DW DMA support into the
> DW SPI MMIO driver. We need to unpin the Non-DMA-specific code from the
> intended to be generic DW APB SSI DMA code. This isn't that hard,
> since the most part of the spi-dw-mid.c driver in fact implements a
> generic DMA interface for the DW SPI controller driver. The only Intel
> MID specifics concern getting the max frequency from the MRST Clock
> Control Unit and fetching the DMA controller channels from
> corresponding PCIe DMA controller. Since first one is related with the
> SPI interface configuration we moved it' implementation into the
> DW PCIe-SPI driver module. After that former spi-dw-mid.c file
> can be just renamed to be the DW SPI DMA module optionally compiled in to
> the DW APB SSI core driver.
Cc list here is huge!
I think this patch should go immediately after bunch of fixes.
...
> -obj-$(CONFIG_SPI_DESIGNWARE) += spi-dw.o
> +obj-$(CONFIG_SPI_DESIGNWARE) += spi-dw-core.o
> +spi-dw-core-y := spi-dw.o
> +spi-dw-core-$(CONFIG_SPI_DW_DMA) += spi-dw-dma.o
We may leave module name the same, right?
obj-$(CONFIG_SPI_DESIGNWARE) += spi-dw.o
spi-dw-y := spi-dw-core.o
spi-dw-$(CONFIG_SPI_DW_DMA) += spi-dw-dma.o
> obj-$(CONFIG_SPI_DW_MMIO) += spi-dw-mmio.o
> -obj-$(CONFIG_SPI_DW_PCI) += spi-dw-midpci.o
> -spi-dw-midpci-objs := spi-dw-pci.o spi-dw-mid.o
> +obj-$(CONFIG_SPI_DW_PCI) += spi-dw-pci.o
> -/* Some specific info for SPI0 controller on Intel MID */
> -
> -/* HW info for MRST Clk Control Unit, 32b reg per controller */
> -#define MRST_SPI_CLK_BASE 100000000 /* 100m */
> -#define MRST_CLK_SPI_REG 0xff11d86c
> -#define CLK_SPI_BDIV_OFFSET 0
> -#define CLK_SPI_BDIV_MASK 0x00000007
> -#define CLK_SPI_CDIV_OFFSET 9
> -#define CLK_SPI_CDIV_MASK 0x00000e00
> -#define CLK_SPI_DISABLE_OFFSET 8
> -
> -int dw_spi_mid_init_mfld(struct dw_spi *dws)
> -{
> - void __iomem *clk_reg;
> - u32 clk_cdiv;
> -
> - clk_reg = ioremap(MRST_CLK_SPI_REG, 16);
> - if (!clk_reg)
> - return -ENOMEM;
> -
> - /* Get SPI controller operating freq info */
> - clk_cdiv = readl(clk_reg + dws->bus_num * sizeof(u32));
> - clk_cdiv &= CLK_SPI_CDIV_MASK;
> - clk_cdiv >>= CLK_SPI_CDIV_OFFSET;
> - dws->max_freq = MRST_SPI_CLK_BASE / (clk_cdiv + 1);
> -
> - iounmap(clk_reg);
> -
> - /* Register hook to configure CTRLR0 */
> - dws->update_cr0 = dw_spi_update_cr0;
> -
> - dw_spi_mid_setup_dma_mfld(dws);
> - return 0;
> -}
> -
> -int dw_spi_mid_init_generic(struct dw_spi *dws)
> -{
> - /* Register hook to configure CTRLR0 */
> - dws->update_cr0 = dw_spi_update_cr0;
> -
> - dw_spi_mid_setup_dma_generic(dws);
> - return 0;
> -}
> +EXPORT_SYMBOL_GPL(dw_spi_mid_setup_dma_generic);
> diff --git a/drivers/spi/spi-dw-pci.c b/drivers/spi/spi-dw-pci.c
> index dde54a918b5d..c13707b8493e 100644
> --- a/drivers/spi/spi-dw-pci.c
> +++ b/drivers/spi/spi-dw-pci.c
> @@ -15,6 +15,15 @@
>
> #define DRIVER_NAME "dw_spi_pci"
>
> +/* HW info for MRST Clk Control Unit, 32b reg per controller */
> +#define MRST_SPI_CLK_BASE 100000000 /* 100m */
> +#define MRST_CLK_SPI_REG 0xff11d86c
> +#define CLK_SPI_BDIV_OFFSET 0
> +#define CLK_SPI_BDIV_MASK 0x00000007
> +#define CLK_SPI_CDIV_OFFSET 9
> +#define CLK_SPI_CDIV_MASK 0x00000e00
> +#define CLK_SPI_DISABLE_OFFSET 8
> +
> struct spi_pci_desc {
> int (*setup)(struct dw_spi *);
> u16 num_cs;
> @@ -22,20 +31,55 @@ struct spi_pci_desc {
> u32 max_freq;
> };
>
> +static int spi_mid_init(struct dw_spi *dws)
> +{
> + void __iomem *clk_reg;
> + u32 clk_cdiv;
> +
> + clk_reg = ioremap(MRST_CLK_SPI_REG, 16);
> + if (!clk_reg)
> + return -ENOMEM;
> +
> + /* Get SPI controller operating freq info */
> + clk_cdiv = readl(clk_reg + dws->bus_num * sizeof(u32));
> + clk_cdiv &= CLK_SPI_CDIV_MASK;
> + clk_cdiv >>= CLK_SPI_CDIV_OFFSET;
> + dws->max_freq = MRST_SPI_CLK_BASE / (clk_cdiv + 1);
> +
> + iounmap(clk_reg);
> +
> + /* Register hook to configure CTRLR0 */
> + dws->update_cr0 = dw_spi_update_cr0;
> +
> + dw_spi_mid_setup_dma_mfld(dws);
> +
> + return 0;
> +}
> +
> +static int spi_generic_init(struct dw_spi *dws)
> +{
> + /* Register hook to configure CTRLR0 */
> + dws->update_cr0 = dw_spi_update_cr0;
> +
> + dw_spi_mid_setup_dma_generic(dws);
> +
> + return 0;
> +}
> +
> static struct spi_pci_desc spi_pci_mid_desc_1 = {
> - .setup = dw_spi_mid_init_mfld,
> + .setup = spi_mid_init,
> .num_cs = 5,
> .bus_num = 0,
> };
>
> static struct spi_pci_desc spi_pci_mid_desc_2 = {
> - .setup = dw_spi_mid_init_mfld,
> + .setup = spi_mid_init,
> .num_cs = 2,
> .bus_num = 1,
> };
>
> static struct spi_pci_desc spi_pci_ehl_desc = {
> - .setup = dw_spi_mid_init_generic,
> + .setup = spi_generic_init,
> .num_cs = 2,
> .bus_num = -1,
> .max_freq = 100000000,
> diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
> index d0c8b7d3a5d2..75fdcc5e7642 100644
> --- a/drivers/spi/spi-dw.h
> +++ b/drivers/spi/spi-dw.h
> @@ -265,8 +265,16 @@ extern u32 dw_spi_update_cr0_v1_01a(struct spi_controller *master,
> struct spi_device *spi,
> struct spi_transfer *transfer);
>
> -/* platform related setup */
> -extern int dw_spi_mid_init_mfld(struct dw_spi *dws);
> -extern int dw_spi_mid_init_generic(struct dw_spi *dws);
> +#ifdef CONFIG_SPI_DW_DMA
> +
> +extern void dw_spi_mid_setup_dma_mfld(struct dw_spi *dws);
> +extern void dw_spi_mid_setup_dma_generic(struct dw_spi *dws);
> +
I would drop blank lines and extern keywords.
> +#else
> +
> +static inline void dw_spi_mid_setup_dma_mfld(struct dw_spi *dws) {}
> +static inline void dw_spi_mid_setup_dma_generic(struct dw_spi *dws) {}
> +
Ditto for blank lines.
> +#endif /* !CONFIG_SPI_DW_DMA */
>
> #endif /* DW_SPI_HEADER_H */
> --
> 2.25.1
>
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 106+ messages in thread
[parent not found: <20200515104758.6934-19-Sergey.Semin@baikalelectronics.ru>]
* Re: [PATCH v2 18/19] spi: dw: Use regset32 DebugFS method to create regdump file
[not found] ` <20200515104758.6934-19-Sergey.Semin@baikalelectronics.ru>
@ 2020-05-15 15:10 ` Andy Shevchenko
[not found] ` <20200516204634.td52orxfnh7iewg6@mobilestation>
0 siblings, 1 reply; 106+ messages in thread
From: Andy Shevchenko @ 2020-05-15 15:10 UTC (permalink / raw)
To: Serge Semin
Cc: Mark Brown, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Arnd Bergmann, Allison Randal, Gareth Williams, Rob Herring,
linux-mips, devicetree, Wan Ahmad Zainie, Charles Keepax,
Clement Leger, wuxu.wu, Phil Edworthy, Thomas Gleixner,
Jarkko Nikula, linux-spi, linux-kernel
On Fri, May 15, 2020 at 01:47:57PM +0300, Serge Semin wrote:
> DebugFS kernel interface provides a dedicated method to create the
> registers dump file. Use it instead of creating a generic DebugFS
> file with manually written read callback function.
With below nit addressed,
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Cc: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
> Cc: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> Cc: Paul Burton <paulburton@kernel.org>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Allison Randal <allison@lohutok.net>
> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Cc: Gareth Williams <gareth.williams.jx@renesas.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: linux-mips@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> ---
> drivers/spi/spi-dw.c | 86 ++++++++++++++------------------------------
> drivers/spi/spi-dw.h | 2 ++
> 2 files changed, 28 insertions(+), 60 deletions(-)
>
> diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c
> index 31607b40147d..bb470cff40d3 100644
> --- a/drivers/spi/spi-dw.c
> +++ b/drivers/spi/spi-dw.c
> @@ -29,66 +29,29 @@ struct chip_data {
> };
>
> #ifdef CONFIG_DEBUG_FS
> -#define SPI_REGS_BUFSIZE 1024
> -static ssize_t dw_spi_show_regs(struct file *file, char __user *user_buf,
> - size_t count, loff_t *ppos)
> -{
> - struct dw_spi *dws = file->private_data;
> - char *buf;
> - u32 len = 0;
> - ssize_t ret;
> -
> - buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
> - if (!buf)
> - return 0;
> -
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "%s registers:\n", dev_name(&dws->master->dev));
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "=================================\n");
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "CTRLR0: \t0x%08x\n", dw_readl(dws, DW_SPI_CTRLR0));
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "CTRLR1: \t0x%08x\n", dw_readl(dws, DW_SPI_CTRLR1));
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR));
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "SER: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SER));
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR));
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFTLR));
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFTLR));
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR));
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "RXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_RXFLR));
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "SR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SR));
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "IMR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_IMR));
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "ISR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_ISR));
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "DMACR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_DMACR));
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "DMATDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMATDLR));
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "DMARDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMARDLR));
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "=================================\n");
> -
> - ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
> - kfree(buf);
> - return ret;
> +
> +#define DW_SPI_DBGFS_REG(_name, _off) \
> +{ \
> + .name = _name, \
> + .offset = _off \
As previously discussed (did I miss your answer?) the comma at the end leaves
better pattern for maintenance prospective.
> }
>
> -static const struct file_operations dw_spi_regs_ops = {
> - .owner = THIS_MODULE,
> - .open = simple_open,
> - .read = dw_spi_show_regs,
> - .llseek = default_llseek,
> +static const struct debugfs_reg32 dw_spi_dbgfs_regs[] = {
> + DW_SPI_DBGFS_REG("CTRLR0", DW_SPI_CTRLR0),
> + DW_SPI_DBGFS_REG("CTRLR1", DW_SPI_CTRLR1),
> + DW_SPI_DBGFS_REG("SSIENR", DW_SPI_SSIENR),
> + DW_SPI_DBGFS_REG("SER", DW_SPI_SER),
> + DW_SPI_DBGFS_REG("BAUDR", DW_SPI_BAUDR),
> + DW_SPI_DBGFS_REG("TXFTLR", DW_SPI_TXFTLR),
> + DW_SPI_DBGFS_REG("RXFTLR", DW_SPI_RXFTLR),
> + DW_SPI_DBGFS_REG("TXFLR", DW_SPI_TXFLR),
> + DW_SPI_DBGFS_REG("RXFLR", DW_SPI_RXFLR),
> + DW_SPI_DBGFS_REG("SR", DW_SPI_SR),
> + DW_SPI_DBGFS_REG("IMR", DW_SPI_IMR),
> + DW_SPI_DBGFS_REG("ISR", DW_SPI_ISR),
> + DW_SPI_DBGFS_REG("DMACR", DW_SPI_DMACR),
> + DW_SPI_DBGFS_REG("DMATDLR", DW_SPI_DMATDLR),
> + DW_SPI_DBGFS_REG("DMARDLR", DW_SPI_DMARDLR)
> };
>
> static int dw_spi_debugfs_init(struct dw_spi *dws)
> @@ -100,8 +63,11 @@ static int dw_spi_debugfs_init(struct dw_spi *dws)
> if (!dws->debugfs)
> return -ENOMEM;
>
> - debugfs_create_file("registers", S_IFREG | S_IRUGO,
> - dws->debugfs, (void *)dws, &dw_spi_regs_ops);
> + dws->regset.regs = dw_spi_dbgfs_regs;
> + dws->regset.nregs = ARRAY_SIZE(dw_spi_dbgfs_regs);
> + dws->regset.base = dws->regs;
> + debugfs_create_regset32("registers", 0400, dws->debugfs, &dws->regset);
> +
> return 0;
> }
>
> diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
> index 24462b0c65cb..4adce6da6013 100644
> --- a/drivers/spi/spi-dw.h
> +++ b/drivers/spi/spi-dw.h
> @@ -2,6 +2,7 @@
> #ifndef DW_SPI_HEADER_H
> #define DW_SPI_HEADER_H
>
> +#include <linux/debugfs.h>
> #include <linux/irqreturn.h>
> #include <linux/io.h>
> #include <linux/scatterlist.h>
> @@ -150,6 +151,7 @@ struct dw_spi {
>
> #ifdef CONFIG_DEBUG_FS
> struct dentry *debugfs;
> + struct debugfs_regset32 regset;
> #endif
> };
>
> --
> 2.25.1
>
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH v2 00/19] spi: dw: Add generic DW DMA controller support
2020-05-15 10:47 ` [PATCH v2 00/19] spi: dw: Add generic DW DMA controller support Serge Semin
` (18 preceding siblings ...)
[not found] ` <20200515104758.6934-19-Sergey.Semin@baikalelectronics.ru>
@ 2020-05-15 18:21 ` Mark Brown
19 siblings, 0 replies; 106+ messages in thread
From: Mark Brown @ 2020-05-15 18:21 UTC (permalink / raw)
To: Serge Semin
Cc: Serge Semin, Georgy Vlasov, Ramil Zaripov, Alexey Malahov,
Maxim Kaurkin, Pavel Parkhomenko, Ekaterina Skachko,
Vadim Vlasov, Alexey Kolotnikov, Thomas Bogendoerfer,
Paul Burton, Ralf Baechle, Arnd Bergmann, Allison Randal,
Andy Shevchenko, Gareth Williams, Rob Herring, linux-mips,
linux-spi, devicetree, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 1075 bytes --]
On Fri, May 15, 2020 at 01:47:39PM +0300, Serge Semin wrote:
Appled:
> dt-bindings: spi: dw: Add Tx/Rx DMA properties
> spi: dw: Clear DMAC register when done or stopped
> spi: dw: Fix native CS being unset
> spi: dw: Initialize paddr in DW SPI MMIO private data
Thanks. No issues from me with the other patches.
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 106+ messages in thread