* [PATCH v9 00/10] Support Andes PMU extension
@ 2024-02-22 8:39 Yu Chien Peter Lin
2024-02-22 8:39 ` [PATCH v9 01/10] riscv: errata: Rename defines for Andes Yu Chien Peter Lin
` (10 more replies)
0 siblings, 11 replies; 23+ messages in thread
From: Yu Chien Peter Lin @ 2024-02-22 8:39 UTC (permalink / raw)
To: acme, adrian.hunter, ajones, alexander.shishkin, andre.przywara,
anup, aou, atishp, conor+dt, conor.dooley, conor, devicetree,
evan, geert+renesas, guoren, heiko, irogers, jernej.skrabec,
jolsa, jszhang, krzysztof.kozlowski+dt, linux-arm-kernel,
linux-kernel, linux-perf-users, linux-renesas-soc, linux-riscv,
linux-sunxi, locus84, magnus.damm, mark.rutland, mingo, n.shubin,
namhyung, palmer, paul.walmsley, peterlin, peterz,
prabhakar.mahadev-lad.rj, rdunlap, robh+dt, samuel, sunilvl,
tglx, tim609, uwu, wens, will, inochiama, unicorn_wang, wefu
Hi All,
This patch series introduces the Andes PMU extension, which serves the
same purpose as Sscofpmf and Smcntrpmf. Its non-standard local interrupt
is assigned to bit 18 in the custom S-mode local interrupt enable and
pending registers (slie/slip), while the interrupt cause is (256 + 18).
The series can be found on Andes Technology GitHub:
- https://github.com/andestech/linux/commits/andes-pmu-support-v9
The PMU device tree node used on AX45MP:
- https://github.com/riscv-software-src/opensbi/blob/master/docs/pmu_support.md#example-3
Locus Wei-Han Chen (1):
riscv: andes: Support specifying symbolic firmware and hardware raw
events
Yu Chien Peter Lin (9):
riscv: errata: Rename defines for Andes
irqchip/riscv-intc: Allow large non-standard interrupt number
irqchip/riscv-intc: Introduce Andes hart-level interrupt controller
dt-bindings: riscv: Add Andes interrupt controller compatible string
riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes
INTC
perf: RISC-V: Eliminate redundant interrupt enable/disable operations
perf: RISC-V: Introduce Andes PMU to support perf event sampling
dt-bindings: riscv: Add Andes PMU extension description
riscv: dts: renesas: Add Andes PMU extension for r9a07g043f
.../devicetree/bindings/riscv/cpus.yaml | 6 +-
.../devicetree/bindings/riscv/extensions.yaml | 7 +
arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 4 +-
arch/riscv/errata/andes/errata.c | 10 +-
arch/riscv/include/asm/errata_list.h | 13 +-
arch/riscv/include/asm/hwcap.h | 1 +
arch/riscv/include/asm/vendorid_list.h | 2 +-
arch/riscv/kernel/alternative.c | 2 +-
arch/riscv/kernel/cpufeature.c | 1 +
drivers/irqchip/irq-riscv-intc.c | 82 +++++++++--
drivers/perf/Kconfig | 14 ++
drivers/perf/riscv_pmu_sbi.c | 37 ++++-
include/linux/soc/andes/irq.h | 18 +++
.../arch/riscv/andes/ax45/firmware.json | 68 ++++++++++
.../arch/riscv/andes/ax45/instructions.json | 127 ++++++++++++++++++
.../arch/riscv/andes/ax45/memory.json | 57 ++++++++
.../arch/riscv/andes/ax45/microarch.json | 77 +++++++++++
tools/perf/pmu-events/arch/riscv/mapfile.csv | 1 +
18 files changed, 488 insertions(+), 39 deletions(-)
create mode 100644 include/linux/soc/andes/irq.h
create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json
create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/instructions.json
create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/memory.json
create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/microarch.json
--
2.34.1
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v9 01/10] riscv: errata: Rename defines for Andes
2024-02-22 8:39 [PATCH v9 00/10] Support Andes PMU extension Yu Chien Peter Lin
@ 2024-02-22 8:39 ` Yu Chien Peter Lin
2024-02-22 8:39 ` [PATCH v9 02/10] irqchip/riscv-intc: Allow large non-standard interrupt number Yu Chien Peter Lin
` (9 subsequent siblings)
10 siblings, 0 replies; 23+ messages in thread
From: Yu Chien Peter Lin @ 2024-02-22 8:39 UTC (permalink / raw)
To: acme, adrian.hunter, ajones, alexander.shishkin, andre.przywara,
anup, aou, atishp, conor+dt, conor.dooley, conor, devicetree,
evan, geert+renesas, guoren, heiko, irogers, jernej.skrabec,
jolsa, jszhang, krzysztof.kozlowski+dt, linux-arm-kernel,
linux-kernel, linux-perf-users, linux-renesas-soc, linux-riscv,
linux-sunxi, locus84, magnus.damm, mark.rutland, mingo, n.shubin,
namhyung, palmer, paul.walmsley, peterlin, peterz,
prabhakar.mahadev-lad.rj, rdunlap, robh+dt, samuel, sunilvl,
tglx, tim609, uwu, wens, will, inochiama, unicorn_wang, wefu
Cc: Charles Ci-Jyun Wu, Leo Yu-Chi Liang
Use "ANDES" rather than "ANDESTECH" to unify the naming
convention with directory, file names, Kconfig options
and other definitions.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Charles Ci-Jyun Wu <dminus@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Changes v1 -> v2:
- No change
Changes v2 -> v3:
- Rewrite commit message (suggested by Conor)
Changes v3 -> v4:
- Include Conor's Acked-by tag
Changes v4 -> v5:
- Include Prabhakar's RB tag
Changes v5 -> v6:
- No change
Changes v6 -> v7:
- No change
Changes v7 -> v8:
- No change
Changes v8 -> v9:
- No change
---
arch/riscv/errata/andes/errata.c | 10 +++++-----
arch/riscv/include/asm/errata_list.h | 4 ++--
arch/riscv/include/asm/vendorid_list.h | 2 +-
arch/riscv/kernel/alternative.c | 2 +-
4 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/riscv/errata/andes/errata.c b/arch/riscv/errata/andes/errata.c
index 17a904869724..f2708a9494a1 100644
--- a/arch/riscv/errata/andes/errata.c
+++ b/arch/riscv/errata/andes/errata.c
@@ -18,9 +18,9 @@
#include <asm/sbi.h>
#include <asm/vendorid_list.h>
-#define ANDESTECH_AX45MP_MARCHID 0x8000000000008a45UL
-#define ANDESTECH_AX45MP_MIMPID 0x500UL
-#define ANDESTECH_SBI_EXT_ANDES 0x0900031E
+#define ANDES_AX45MP_MARCHID 0x8000000000008a45UL
+#define ANDES_AX45MP_MIMPID 0x500UL
+#define ANDES_SBI_EXT_ANDES 0x0900031E
#define ANDES_SBI_EXT_IOCP_SW_WORKAROUND 1
@@ -32,7 +32,7 @@ static long ax45mp_iocp_sw_workaround(void)
* ANDES_SBI_EXT_IOCP_SW_WORKAROUND SBI EXT checks if the IOCP is missing and
* cache is controllable only then CMO will be applied to the platform.
*/
- ret = sbi_ecall(ANDESTECH_SBI_EXT_ANDES, ANDES_SBI_EXT_IOCP_SW_WORKAROUND,
+ ret = sbi_ecall(ANDES_SBI_EXT_ANDES, ANDES_SBI_EXT_IOCP_SW_WORKAROUND,
0, 0, 0, 0, 0, 0);
return ret.error ? 0 : ret.value;
@@ -50,7 +50,7 @@ static void errata_probe_iocp(unsigned int stage, unsigned long arch_id, unsigne
done = true;
- if (arch_id != ANDESTECH_AX45MP_MARCHID || impid != ANDESTECH_AX45MP_MIMPID)
+ if (arch_id != ANDES_AX45MP_MARCHID || impid != ANDES_AX45MP_MIMPID)
return;
if (!ax45mp_iocp_sw_workaround())
diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
index ea33288f8a25..96025eec5631 100644
--- a/arch/riscv/include/asm/errata_list.h
+++ b/arch/riscv/include/asm/errata_list.h
@@ -12,8 +12,8 @@
#include <asm/vendorid_list.h>
#ifdef CONFIG_ERRATA_ANDES
-#define ERRATA_ANDESTECH_NO_IOCP 0
-#define ERRATA_ANDESTECH_NUMBER 1
+#define ERRATA_ANDES_NO_IOCP 0
+#define ERRATA_ANDES_NUMBER 1
#endif
#ifdef CONFIG_ERRATA_SIFIVE
diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/asm/vendorid_list.h
index e55407ace0c3..2f2bb0c84f9a 100644
--- a/arch/riscv/include/asm/vendorid_list.h
+++ b/arch/riscv/include/asm/vendorid_list.h
@@ -5,7 +5,7 @@
#ifndef ASM_VENDOR_LIST_H
#define ASM_VENDOR_LIST_H
-#define ANDESTECH_VENDOR_ID 0x31e
+#define ANDES_VENDOR_ID 0x31e
#define SIFIVE_VENDOR_ID 0x489
#define THEAD_VENDOR_ID 0x5b7
diff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternative.c
index 319a1da0358b..0128b161bfda 100644
--- a/arch/riscv/kernel/alternative.c
+++ b/arch/riscv/kernel/alternative.c
@@ -43,7 +43,7 @@ static void riscv_fill_cpu_mfr_info(struct cpu_manufacturer_info_t *cpu_mfr_info
switch (cpu_mfr_info->vendor_id) {
#ifdef CONFIG_ERRATA_ANDES
- case ANDESTECH_VENDOR_ID:
+ case ANDES_VENDOR_ID:
cpu_mfr_info->patch_func = andes_errata_patch_func;
break;
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v9 02/10] irqchip/riscv-intc: Allow large non-standard interrupt number
2024-02-22 8:39 [PATCH v9 00/10] Support Andes PMU extension Yu Chien Peter Lin
2024-02-22 8:39 ` [PATCH v9 01/10] riscv: errata: Rename defines for Andes Yu Chien Peter Lin
@ 2024-02-22 8:39 ` Yu Chien Peter Lin
2024-02-22 21:33 ` Thomas Gleixner
2024-02-23 9:44 ` [tip: irq/msi] " tip-bot2 for Yu Chien Peter Lin
2024-02-22 8:39 ` [PATCH v9 03/10] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller Yu Chien Peter Lin
` (8 subsequent siblings)
10 siblings, 2 replies; 23+ messages in thread
From: Yu Chien Peter Lin @ 2024-02-22 8:39 UTC (permalink / raw)
To: acme, adrian.hunter, ajones, alexander.shishkin, andre.przywara,
anup, aou, atishp, conor+dt, conor.dooley, conor, devicetree,
evan, geert+renesas, guoren, heiko, irogers, jernej.skrabec,
jolsa, jszhang, krzysztof.kozlowski+dt, linux-arm-kernel,
linux-kernel, linux-perf-users, linux-renesas-soc, linux-riscv,
linux-sunxi, locus84, magnus.damm, mark.rutland, mingo, n.shubin,
namhyung, palmer, paul.walmsley, peterlin, peterz,
prabhakar.mahadev-lad.rj, rdunlap, robh+dt, samuel, sunilvl,
tglx, tim609, uwu, wens, will, inochiama, unicorn_wang, wefu
Cc: Randolph, Atish Patra
Currently, the implementation of the RISC-V INTC driver uses the
interrupt cause as the hardware interrupt number, with a maximum of
64 interrupts. However, the platform can expand the interrupt number
further for custom local interrupts.
To fully utilize the available local interrupt sources, switch
to using irq_domain_create_tree() that creates the radix tree
map, add global variables (riscv_intc_nr_irqs, riscv_intc_custom_base
and riscv_intc_custom_nr_irqs) to determine the valid range of local
interrupt number (hwirq).
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Randolph <randolph@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
---
Changes v1 -> v2:
- Fixed irq mapping failure checking (suggested by Clément and Anup)
Changes v2 -> v3:
- No change
Changes v3 -> v4: (Suggested by Thomas [1])
- Use pr_warn_ratelimited instead
- Fix coding style and commit message
Changes v4 -> v5: (Suggested by Thomas)
- Fix commit message
Changes v5 -> v6: (Suggested by Anup [2])
- Add riscv_intc_* global variables for checking the range of valid
interrupt number in riscv_intc_domain_alloc()
- Advertise the number of interrupts allowed
Changes v6 -> v7:
- No functional change
Changes v7 -> v8:
- Include Reviewed-by tags from Anup and Atish
Changes v8 -> v9 (Suggested by Thomas [3]):
- Fix coding style
- Update hwirq range checks
- Update riscv_intc_* global variables initialization
[1] https://patchwork.kernel.org/project/linux-riscv/patch/20231023004100.2663486-3-peterlin@andestech.com/#25573085
[2] https://patchwork.kernel.org/project/linux-riscv/patch/20231213070301.1684751-3-peterlin@andestech.com/#25636589
[3] https://patchwork.kernel.org/project/linux-riscv/patch/20240129092553.2058043-3-peterlin@andestech.com/#25710584
---
drivers/irqchip/irq-riscv-intc.c | 26 +++++++++++++++++++-------
1 file changed, 19 insertions(+), 7 deletions(-)
diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
index e8d01b14ccdd..684875c39728 100644
--- a/drivers/irqchip/irq-riscv-intc.c
+++ b/drivers/irqchip/irq-riscv-intc.c
@@ -19,15 +19,16 @@
#include <linux/smp.h>
static struct irq_domain *intc_domain;
+static unsigned int riscv_intc_nr_irqs __ro_after_init = BITS_PER_LONG;
+static unsigned int riscv_intc_custom_base __ro_after_init = BITS_PER_LONG;
+static unsigned int riscv_intc_custom_nr_irqs __ro_after_init;
static asmlinkage void riscv_intc_irq(struct pt_regs *regs)
{
unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG;
- if (unlikely(cause >= BITS_PER_LONG))
- panic("unexpected interrupt cause");
-
- generic_handle_domain_irq(intc_domain, cause);
+ if (generic_handle_domain_irq(intc_domain, cause))
+ pr_warn_ratelimited("Failed to handle interrupt (cause: %ld)\n", cause);
}
/*
@@ -93,6 +94,14 @@ static int riscv_intc_domain_alloc(struct irq_domain *domain,
if (ret)
return ret;
+ /*
+ * Only allow hwirq for which we have corresponding standard or
+ * custom interrupt enable register.
+ */
+ if ((hwirq >= riscv_intc_nr_irqs && hwirq < riscv_intc_custom_base) ||
+ (hwirq >= riscv_intc_custom_base + riscv_intc_custom_nr_irqs))
+ return -EINVAL;
+
for (i = 0; i < nr_irqs; i++) {
ret = riscv_intc_domain_map(domain, virq + i, hwirq + i);
if (ret)
@@ -117,8 +126,7 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn)
{
int rc;
- intc_domain = irq_domain_create_linear(fn, BITS_PER_LONG,
- &riscv_intc_domain_ops, NULL);
+ intc_domain = irq_domain_create_tree(fn, &riscv_intc_domain_ops, NULL);
if (!intc_domain) {
pr_err("unable to add IRQ domain\n");
return -ENXIO;
@@ -132,7 +140,11 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn)
riscv_set_intc_hwnode_fn(riscv_intc_hwnode);
- pr_info("%d local interrupts mapped\n", BITS_PER_LONG);
+ pr_info("%d local interrupts mapped\n", riscv_intc_nr_irqs);
+ if (riscv_intc_custom_nr_irqs) {
+ pr_info("%d custom local interrupts mapped\n",
+ riscv_intc_custom_nr_irqs);
+ }
return 0;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v9 03/10] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller
2024-02-22 8:39 [PATCH v9 00/10] Support Andes PMU extension Yu Chien Peter Lin
2024-02-22 8:39 ` [PATCH v9 01/10] riscv: errata: Rename defines for Andes Yu Chien Peter Lin
2024-02-22 8:39 ` [PATCH v9 02/10] irqchip/riscv-intc: Allow large non-standard interrupt number Yu Chien Peter Lin
@ 2024-02-22 8:39 ` Yu Chien Peter Lin
2024-02-22 21:36 ` Thomas Gleixner
2024-02-23 9:43 ` [tip: irq/msi] " tip-bot2 for Yu Chien Peter Lin
2024-02-22 8:39 ` [PATCH v9 04/10] dt-bindings: riscv: Add Andes interrupt controller compatible string Yu Chien Peter Lin
` (7 subsequent siblings)
10 siblings, 2 replies; 23+ messages in thread
From: Yu Chien Peter Lin @ 2024-02-22 8:39 UTC (permalink / raw)
To: acme, adrian.hunter, ajones, alexander.shishkin, andre.przywara,
anup, aou, atishp, conor+dt, conor.dooley, conor, devicetree,
evan, geert+renesas, guoren, heiko, irogers, jernej.skrabec,
jolsa, jszhang, krzysztof.kozlowski+dt, linux-arm-kernel,
linux-kernel, linux-perf-users, linux-renesas-soc, linux-riscv,
linux-sunxi, locus84, magnus.damm, mark.rutland, mingo, n.shubin,
namhyung, palmer, paul.walmsley, peterlin, peterz,
prabhakar.mahadev-lad.rj, rdunlap, robh+dt, samuel, sunilvl,
tglx, tim609, uwu, wens, will, inochiama, unicorn_wang, wefu
Cc: Randolph
Add support for the Andes hart-level interrupt controller. This
controller provides interrupt mask/unmask functions to access the
custom register (SLIE) where the non-standard S-mode local interrupt
enable bits are located. The base of custom interrupt number is set
to 256.
To share the riscv_intc_domain_map() with the generic RISC-V INTC and
ACPI, add a chip parameter to riscv_intc_init_common(), so it can be
passed to the irq_domain_set_info() as a private data.
Andes hart-level interrupt controller requires the "andestech,cpu-intc"
compatible string to be present in interrupt-controller of cpu node to
enable the use of custom local interrupt source.
e.g.,
cpu0: cpu@0 {
compatible = "andestech,ax45mp", "riscv";
...
cpu0-intc: interrupt-controller {
#interrupt-cells = <0x01>;
compatible = "andestech,cpu-intc", "riscv,cpu-intc";
interrupt-controller;
};
};
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Randolph <randolph@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
---
Changes v1 -> v2:
- New patch
Changes v2 -> v3:
- Return -ENXIO if no valid compatible INTC found
- Allow falling back to generic RISC-V INTC
Changes v3 -> v4: (Suggested by Thomas [1])
- Add comment to andes irq chip function
- Refine code flow to share with generic RISC-V INTC and ACPI
- Move Andes specific definitions to include/linux/soc/andes/irq.h
Changes v4 -> v5: (Suggested by Thomas)
- Fix commit message
- Subtract ANDES_SLI_CAUSE_BASE from d->hwirq to calculate the value of mask
- Do not set chip_data to the chip itself with irq_domain_set_info()
- Follow reverse fir tree order variable declarations
Changes v5 -> v6:
- To follow the naming on datasheet, rename ANDES_RV_IRQ_PMU to ANDES_RV_IRQ_PMOVI
- Initialize the riscv_intc_* global variables for Andes INTC (Suggested by Anup)
- Use BITS_PER_LONG to compute the bit mask of SIE/SLIE as they are 64-bit registers (32-bit for RV32)
Changes v6 -> v7:
- No change
Changes v7 -> v8:
- Include Reviewed-by tags from Anup
Changes v8 -> v9:
- No functional change
[1] https://patchwork.kernel.org/project/linux-riscv/patch/20231019135723.3657156-1-peterlin@andestech.com/
---
drivers/irqchip/irq-riscv-intc.c | 58 ++++++++++++++++++++++++++++----
include/linux/soc/andes/irq.h | 18 ++++++++++
2 files changed, 69 insertions(+), 7 deletions(-)
create mode 100644 include/linux/soc/andes/irq.h
diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
index 684875c39728..0cd6b48a5dbf 100644
--- a/drivers/irqchip/irq-riscv-intc.c
+++ b/drivers/irqchip/irq-riscv-intc.c
@@ -17,6 +17,7 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/smp.h>
+#include <linux/soc/andes/irq.h>
static struct irq_domain *intc_domain;
static unsigned int riscv_intc_nr_irqs __ro_after_init = BITS_PER_LONG;
@@ -48,6 +49,31 @@ static void riscv_intc_irq_unmask(struct irq_data *d)
csr_set(CSR_IE, BIT(d->hwirq));
}
+static void andes_intc_irq_mask(struct irq_data *d)
+{
+ /*
+ * Andes specific S-mode local interrupt causes (hwirq)
+ * are defined as (256 + n) and controlled by n-th bit
+ * of SLIE.
+ */
+ unsigned int mask = BIT(d->hwirq % BITS_PER_LONG);
+
+ if (d->hwirq < ANDES_SLI_CAUSE_BASE)
+ csr_clear(CSR_IE, mask);
+ else
+ csr_clear(ANDES_CSR_SLIE, mask);
+}
+
+static void andes_intc_irq_unmask(struct irq_data *d)
+{
+ unsigned int mask = BIT(d->hwirq % BITS_PER_LONG);
+
+ if (d->hwirq < ANDES_SLI_CAUSE_BASE)
+ csr_set(CSR_IE, mask);
+ else
+ csr_set(ANDES_CSR_SLIE, mask);
+}
+
static void riscv_intc_irq_eoi(struct irq_data *d)
{
/*
@@ -71,12 +97,21 @@ static struct irq_chip riscv_intc_chip = {
.irq_eoi = riscv_intc_irq_eoi,
};
+static struct irq_chip andes_intc_chip = {
+ .name = "RISC-V INTC",
+ .irq_mask = andes_intc_irq_mask,
+ .irq_unmask = andes_intc_irq_unmask,
+ .irq_eoi = riscv_intc_irq_eoi,
+};
+
static int riscv_intc_domain_map(struct irq_domain *d, unsigned int irq,
irq_hw_number_t hwirq)
{
+ struct irq_chip *chip = d->host_data;
+
irq_set_percpu_devid(irq);
- irq_domain_set_info(d, irq, hwirq, &riscv_intc_chip, d->host_data,
- handle_percpu_devid_irq, NULL, NULL);
+ irq_domain_set_info(d, irq, hwirq, chip, NULL, handle_percpu_devid_irq,
+ NULL, NULL);
return 0;
}
@@ -122,11 +157,12 @@ static struct fwnode_handle *riscv_intc_hwnode(void)
return intc_domain->fwnode;
}
-static int __init riscv_intc_init_common(struct fwnode_handle *fn)
+static int __init riscv_intc_init_common(struct fwnode_handle *fn,
+ struct irq_chip *chip)
{
int rc;
- intc_domain = irq_domain_create_tree(fn, &riscv_intc_domain_ops, NULL);
+ intc_domain = irq_domain_create_tree(fn, &riscv_intc_domain_ops, chip);
if (!intc_domain) {
pr_err("unable to add IRQ domain\n");
return -ENXIO;
@@ -152,8 +188,9 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn)
static int __init riscv_intc_init(struct device_node *node,
struct device_node *parent)
{
- int rc;
+ struct irq_chip *chip = &riscv_intc_chip;
unsigned long hartid;
+ int rc;
rc = riscv_of_parent_hartid(node, &hartid);
if (rc < 0) {
@@ -178,10 +215,17 @@ static int __init riscv_intc_init(struct device_node *node,
return 0;
}
- return riscv_intc_init_common(of_node_to_fwnode(node));
+ if (of_device_is_compatible(node, "andestech,cpu-intc")) {
+ riscv_intc_custom_base = ANDES_SLI_CAUSE_BASE;
+ riscv_intc_custom_nr_irqs = ANDES_RV_IRQ_LAST;
+ chip = &andes_intc_chip;
+ }
+
+ return riscv_intc_init_common(of_node_to_fwnode(node), chip);
}
IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init);
+IRQCHIP_DECLARE(andes, "andestech,cpu-intc", riscv_intc_init);
#ifdef CONFIG_ACPI
@@ -208,7 +252,7 @@ static int __init riscv_intc_acpi_init(union acpi_subtable_headers *header,
return -ENOMEM;
}
- return riscv_intc_init_common(fn);
+ return riscv_intc_init_common(fn, &riscv_intc_chip);
}
IRQCHIP_ACPI_DECLARE(riscv_intc, ACPI_MADT_TYPE_RINTC, NULL,
diff --git a/include/linux/soc/andes/irq.h b/include/linux/soc/andes/irq.h
new file mode 100644
index 000000000000..edc3182d6e66
--- /dev/null
+++ b/include/linux/soc/andes/irq.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2023 Andes Technology Corporation
+ */
+#ifndef __ANDES_IRQ_H
+#define __ANDES_IRQ_H
+
+/* Andes PMU irq number */
+#define ANDES_RV_IRQ_PMOVI 18
+#define ANDES_RV_IRQ_LAST ANDES_RV_IRQ_PMOVI
+#define ANDES_SLI_CAUSE_BASE 256
+
+/* Andes PMU related registers */
+#define ANDES_CSR_SLIE 0x9c4
+#define ANDES_CSR_SLIP 0x9c5
+#define ANDES_CSR_SCOUNTEROF 0x9d4
+
+#endif /* __ANDES_IRQ_H */
--
2.34.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v9 04/10] dt-bindings: riscv: Add Andes interrupt controller compatible string
2024-02-22 8:39 [PATCH v9 00/10] Support Andes PMU extension Yu Chien Peter Lin
` (2 preceding siblings ...)
2024-02-22 8:39 ` [PATCH v9 03/10] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller Yu Chien Peter Lin
@ 2024-02-22 8:39 ` Yu Chien Peter Lin
2024-02-22 8:39 ` [PATCH v9 05/10] riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC Yu Chien Peter Lin
` (6 subsequent siblings)
10 siblings, 0 replies; 23+ messages in thread
From: Yu Chien Peter Lin @ 2024-02-22 8:39 UTC (permalink / raw)
To: acme, adrian.hunter, ajones, alexander.shishkin, andre.przywara,
anup, aou, atishp, conor+dt, conor.dooley, conor, devicetree,
evan, geert+renesas, guoren, heiko, irogers, jernej.skrabec,
jolsa, jszhang, krzysztof.kozlowski+dt, linux-arm-kernel,
linux-kernel, linux-perf-users, linux-renesas-soc, linux-riscv,
linux-sunxi, locus84, magnus.damm, mark.rutland, mingo, n.shubin,
namhyung, palmer, paul.walmsley, peterlin, peterz,
prabhakar.mahadev-lad.rj, rdunlap, robh+dt, samuel, sunilvl,
tglx, tim609, uwu, wens, will, inochiama, unicorn_wang, wefu
Add "andestech,cpu-intc" compatible string to indicate that
Andes specific local interrupt is supported on the core,
e.g. AX45MP cores have 3 types of non-standard local interrupt
which can be handled in supervisor mode:
- Slave port ECC error interrupt
- Bus write transaction error interrupt
- Performance monitor overflow interrupt
These interrupts are enabled/disabled via a custom register
SLIE instead of the standard interrupt enable register SIE.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Changes v1 -> v2:
- New patch
Changes v2 -> v3:
- Updated commit message
- Fixed possible compatibles for Andes INTC
Changes v3 -> v4:
- Add const entry instead of enum (Suggested by Conor)
Changes v4 -> v5:
- Include Conor's Acked-by
- Include Prabhakar's Reviewed-by
Changes v5 -> v6:
- No change
Changes v6 -> v7:
- No change
Changes v7 -> v8:
- No change
Changes v8 -> v9:
- No change
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 9d8670c00e3b..6ccd75cbbc59 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -106,7 +106,11 @@ properties:
const: 1
compatible:
- const: riscv,cpu-intc
+ oneOf:
+ - items:
+ - const: andestech,cpu-intc
+ - const: riscv,cpu-intc
+ - const: riscv,cpu-intc
interrupt-controller: true
--
2.34.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v9 05/10] riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC
2024-02-22 8:39 [PATCH v9 00/10] Support Andes PMU extension Yu Chien Peter Lin
` (3 preceding siblings ...)
2024-02-22 8:39 ` [PATCH v9 04/10] dt-bindings: riscv: Add Andes interrupt controller compatible string Yu Chien Peter Lin
@ 2024-02-22 8:39 ` Yu Chien Peter Lin
2024-02-26 12:27 ` Geert Uytterhoeven
2024-02-22 8:39 ` [PATCH v9 06/10] perf: RISC-V: Eliminate redundant interrupt enable/disable operations Yu Chien Peter Lin
` (5 subsequent siblings)
10 siblings, 1 reply; 23+ messages in thread
From: Yu Chien Peter Lin @ 2024-02-22 8:39 UTC (permalink / raw)
To: acme, adrian.hunter, ajones, alexander.shishkin, andre.przywara,
anup, aou, atishp, conor+dt, conor.dooley, conor, devicetree,
evan, geert+renesas, guoren, heiko, irogers, jernej.skrabec,
jolsa, jszhang, krzysztof.kozlowski+dt, linux-arm-kernel,
linux-kernel, linux-perf-users, linux-renesas-soc, linux-riscv,
linux-sunxi, locus84, magnus.damm, mark.rutland, mingo, n.shubin,
namhyung, palmer, paul.walmsley, peterlin, peterz,
prabhakar.mahadev-lad.rj, rdunlap, robh+dt, samuel, sunilvl,
tglx, tim609, uwu, wens, will, inochiama, unicorn_wang, wefu
The Andes hart-level interrupt controller (Andes INTC) allows AX45MP
cores to handle custom local interrupts, such as the performance
counter overflow interrupt.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Changes v1 -> v2:
- New patch
Changes v2 -> v3:
- Fixed possible compatibles for Andes INTC
Changes v3 -> v4:
- No change
Changes v4 -> v5:
- Include Geert's Reviewed-by
- Include Prabhakar's Reviewed/Tested-by
Changes v5 -> v6:
- No change
Changes v6 -> v7:
- No change
Changes v7 -> v8:
- No change
Changes v8 -> v9:
- No change
---
arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
index a92cfcfc021b..099f3df75b42 100644
--- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
+++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
@@ -39,7 +39,7 @@ cpu0: cpu@0 {
cpu0_intc: interrupt-controller {
#interrupt-cells = <1>;
- compatible = "riscv,cpu-intc";
+ compatible = "andestech,cpu-intc", "riscv,cpu-intc";
interrupt-controller;
};
};
--
2.34.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v9 06/10] perf: RISC-V: Eliminate redundant interrupt enable/disable operations
2024-02-22 8:39 [PATCH v9 00/10] Support Andes PMU extension Yu Chien Peter Lin
` (4 preceding siblings ...)
2024-02-22 8:39 ` [PATCH v9 05/10] riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC Yu Chien Peter Lin
@ 2024-02-22 8:39 ` Yu Chien Peter Lin
2024-02-22 8:39 ` [PATCH v9 07/10] perf: RISC-V: Introduce Andes PMU to support perf event sampling Yu Chien Peter Lin
` (4 subsequent siblings)
10 siblings, 0 replies; 23+ messages in thread
From: Yu Chien Peter Lin @ 2024-02-22 8:39 UTC (permalink / raw)
To: acme, adrian.hunter, ajones, alexander.shishkin, andre.przywara,
anup, aou, atishp, conor+dt, conor.dooley, conor, devicetree,
evan, geert+renesas, guoren, heiko, irogers, jernej.skrabec,
jolsa, jszhang, krzysztof.kozlowski+dt, linux-arm-kernel,
linux-kernel, linux-perf-users, linux-renesas-soc, linux-riscv,
linux-sunxi, locus84, magnus.damm, mark.rutland, mingo, n.shubin,
namhyung, palmer, paul.walmsley, peterlin, peterz,
prabhakar.mahadev-lad.rj, rdunlap, robh+dt, samuel, sunilvl,
tglx, tim609, uwu, wens, will, inochiama, unicorn_wang, wefu
Cc: Atish Patra
The interrupt enable/disable operations are already performed by the
IRQ chip functions riscv_intc_irq_unmask()/riscv_intc_irq_mask() during
enable_percpu_irq()/disable_percpu_irq(). It can be done only once.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
---
This patch allows us to drop unnecessary ALT_SBI_PMU_OVF_{DISABLE,ENABLE}
in the initial PATCH3 [1].
[1] https://patchwork.kernel.org/project/linux-riscv/patch/20230907021635.1002738-4-peterlin@andestech.com/
Changes v1 -> v2:
- New patch
Changes v2 -> v3:
- No change
Changes v3 -> v4:
- No change
Changes v4 -> v5:
- No change
Changes v5 -> v6:
- No change
Changes v6 -> v7:
- No change
Changes v7 -> v8:
- Include Reviewed-by tags from Atish
Changes v8 -> v9:
- No change
---
drivers/perf/riscv_pmu_sbi.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
index 16acd4dcdb96..2edbc37abadf 100644
--- a/drivers/perf/riscv_pmu_sbi.c
+++ b/drivers/perf/riscv_pmu_sbi.c
@@ -781,7 +781,6 @@ static int pmu_sbi_starting_cpu(unsigned int cpu, struct hlist_node *node)
if (riscv_pmu_use_irq) {
cpu_hw_evt->irq = riscv_pmu_irq;
csr_clear(CSR_IP, BIT(riscv_pmu_irq_num));
- csr_set(CSR_IE, BIT(riscv_pmu_irq_num));
enable_percpu_irq(riscv_pmu_irq, IRQ_TYPE_NONE);
}
@@ -792,7 +791,6 @@ static int pmu_sbi_dying_cpu(unsigned int cpu, struct hlist_node *node)
{
if (riscv_pmu_use_irq) {
disable_percpu_irq(riscv_pmu_irq);
- csr_clear(CSR_IE, BIT(riscv_pmu_irq_num));
}
/* Disable all counters access for user mode now */
--
2.34.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v9 07/10] perf: RISC-V: Introduce Andes PMU to support perf event sampling
2024-02-22 8:39 [PATCH v9 00/10] Support Andes PMU extension Yu Chien Peter Lin
` (5 preceding siblings ...)
2024-02-22 8:39 ` [PATCH v9 06/10] perf: RISC-V: Eliminate redundant interrupt enable/disable operations Yu Chien Peter Lin
@ 2024-02-22 8:39 ` Yu Chien Peter Lin
2024-02-22 8:39 ` [PATCH v9 08/10] dt-bindings: riscv: Add Andes PMU extension description Yu Chien Peter Lin
` (3 subsequent siblings)
10 siblings, 0 replies; 23+ messages in thread
From: Yu Chien Peter Lin @ 2024-02-22 8:39 UTC (permalink / raw)
To: acme, adrian.hunter, ajones, alexander.shishkin, andre.przywara,
anup, aou, atishp, conor+dt, conor.dooley, conor, devicetree,
evan, geert+renesas, guoren, heiko, irogers, jernej.skrabec,
jolsa, jszhang, krzysztof.kozlowski+dt, linux-arm-kernel,
linux-kernel, linux-perf-users, linux-renesas-soc, linux-riscv,
linux-sunxi, locus84, magnus.damm, mark.rutland, mingo, n.shubin,
namhyung, palmer, paul.walmsley, peterlin, peterz,
prabhakar.mahadev-lad.rj, rdunlap, robh+dt, samuel, sunilvl,
tglx, tim609, uwu, wens, will, inochiama, unicorn_wang, wefu
Cc: Charles Ci-Jyun Wu, Leo Yu-Chi Liang
Assign riscv_pmu_irq_num the value of (256 + 18) for the custome PMU
and add SSCOUNTOVF and SIP alternatives to ALT_SBI_PMU_OVERFLOW()
and ALT_SBI_PMU_OVF_CLEAR_PENDING() macros, respectively.
To make use of Andes PMU extension, "xandespmu" needs to be appended
to the riscv,isa-extensions for each cpu node in device-tree, and
make sure CONFIG_ANDES_CUSTOM_PMU is enabled.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Charles Ci-Jyun Wu <dminus@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Co-developed-by: Locus Wei-Han Chen <locus84@andestech.com>
Signed-off-by: Locus Wei-Han Chen <locus84@andestech.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Changes v1 -> v2:
- New patch
Changes v2 -> v3:
- Reordered list in riscv_isa_ext[]
- Removed mvendorid check in pmu_sbi_setup_irqs()
Changes v3 -> v4:
- No change
Changes v4 -> v5:
- Let ANDES_CUSTOM_PMU depend on ARCH_RENESAS
- Include Prabhakar's Reviewed/Tested-by
Changes v5 -> v6:
- No change
Changes v6 -> v7:
- No change
Changes v7 -> v8:
- No change
Changes v8 -> v9:
- No change
---
arch/riscv/include/asm/errata_list.h | 9 -------
arch/riscv/include/asm/hwcap.h | 1 +
arch/riscv/kernel/cpufeature.c | 1 +
drivers/perf/Kconfig | 14 +++++++++++
drivers/perf/riscv_pmu_sbi.c | 35 +++++++++++++++++++++++++---
5 files changed, 48 insertions(+), 12 deletions(-)
diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
index 96025eec5631..1f2dbfb8a8bf 100644
--- a/arch/riscv/include/asm/errata_list.h
+++ b/arch/riscv/include/asm/errata_list.h
@@ -112,15 +112,6 @@ asm volatile(ALTERNATIVE( \
#define THEAD_C9XX_RV_IRQ_PMU 17
#define THEAD_C9XX_CSR_SCOUNTEROF 0x5c5
-#define ALT_SBI_PMU_OVERFLOW(__ovl) \
-asm volatile(ALTERNATIVE( \
- "csrr %0, " __stringify(CSR_SSCOUNTOVF), \
- "csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF), \
- THEAD_VENDOR_ID, ERRATA_THEAD_PMU, \
- CONFIG_ERRATA_THEAD_PMU) \
- : "=r" (__ovl) : \
- : "memory")
-
#endif /* __ASSEMBLY__ */
#endif
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 5340f818746b..bae7eac76c18 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -80,6 +80,7 @@
#define RISCV_ISA_EXT_ZFA 71
#define RISCV_ISA_EXT_ZTSO 72
#define RISCV_ISA_EXT_ZACAS 73
+#define RISCV_ISA_EXT_XANDESPMU 74
#define RISCV_ISA_EXT_MAX 128
#define RISCV_ISA_EXT_INVALID U32_MAX
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 89920f84d0a3..0c7688fa8376 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -307,6 +307,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
__RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
__RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
__RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
+ __RISCV_ISA_EXT_DATA(xandespmu, RISCV_ISA_EXT_XANDESPMU),
};
const size_t riscv_isa_ext_count = ARRAY_SIZE(riscv_isa_ext);
diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig
index ec6e0d9194a1..564e813d8c69 100644
--- a/drivers/perf/Kconfig
+++ b/drivers/perf/Kconfig
@@ -86,6 +86,20 @@ config RISCV_PMU_SBI
full perf feature support i.e. counter overflow, privilege mode
filtering, counter configuration.
+config ANDES_CUSTOM_PMU
+ bool "Andes custom PMU support"
+ depends on ARCH_RENESAS && RISCV_ALTERNATIVE && RISCV_PMU_SBI
+ default y
+ help
+ The Andes cores implement the PMU overflow extension very
+ similar to the standard Sscofpmf and Smcntrpmf extension.
+
+ This will patch the overflow and pending CSRs and handle the
+ non-standard behaviour via the regular SBI PMU driver and
+ interface.
+
+ If you don't know what to do here, say "Y".
+
config ARM_PMU_ACPI
depends on ARM_PMU && ACPI
def_bool y
diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
index 2edbc37abadf..bbd6fe021b3a 100644
--- a/drivers/perf/riscv_pmu_sbi.c
+++ b/drivers/perf/riscv_pmu_sbi.c
@@ -19,11 +19,33 @@
#include <linux/of.h>
#include <linux/cpu_pm.h>
#include <linux/sched/clock.h>
+#include <linux/soc/andes/irq.h>
#include <asm/errata_list.h>
#include <asm/sbi.h>
#include <asm/cpufeature.h>
+#define ALT_SBI_PMU_OVERFLOW(__ovl) \
+asm volatile(ALTERNATIVE_2( \
+ "csrr %0, " __stringify(CSR_SSCOUNTOVF), \
+ "csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF), \
+ THEAD_VENDOR_ID, ERRATA_THEAD_PMU, \
+ CONFIG_ERRATA_THEAD_PMU, \
+ "csrr %0, " __stringify(ANDES_CSR_SCOUNTEROF), \
+ 0, RISCV_ISA_EXT_XANDESPMU, \
+ CONFIG_ANDES_CUSTOM_PMU) \
+ : "=r" (__ovl) : \
+ : "memory")
+
+#define ALT_SBI_PMU_OVF_CLEAR_PENDING(__irq_mask) \
+asm volatile(ALTERNATIVE( \
+ "csrc " __stringify(CSR_IP) ", %0\n\t", \
+ "csrc " __stringify(ANDES_CSR_SLIP) ", %0\n\t", \
+ 0, RISCV_ISA_EXT_XANDESPMU, \
+ CONFIG_ANDES_CUSTOM_PMU) \
+ : : "r"(__irq_mask) \
+ : "memory")
+
#define SYSCTL_NO_USER_ACCESS 0
#define SYSCTL_USER_ACCESS 1
#define SYSCTL_LEGACY 2
@@ -61,6 +83,7 @@ static int sysctl_perf_user_access __read_mostly = SYSCTL_USER_ACCESS;
static union sbi_pmu_ctr_info *pmu_ctr_list;
static bool riscv_pmu_use_irq;
static unsigned int riscv_pmu_irq_num;
+static unsigned int riscv_pmu_irq_mask;
static unsigned int riscv_pmu_irq;
/* Cache the available counters in a bitmask */
@@ -694,7 +717,7 @@ static irqreturn_t pmu_sbi_ovf_handler(int irq, void *dev)
event = cpu_hw_evt->events[fidx];
if (!event) {
- csr_clear(CSR_SIP, BIT(riscv_pmu_irq_num));
+ ALT_SBI_PMU_OVF_CLEAR_PENDING(riscv_pmu_irq_mask);
return IRQ_NONE;
}
@@ -708,7 +731,7 @@ static irqreturn_t pmu_sbi_ovf_handler(int irq, void *dev)
* Overflow interrupt pending bit should only be cleared after stopping
* all the counters to avoid any race condition.
*/
- csr_clear(CSR_SIP, BIT(riscv_pmu_irq_num));
+ ALT_SBI_PMU_OVF_CLEAR_PENDING(riscv_pmu_irq_mask);
/* No overflow bit is set */
if (!overflow)
@@ -780,7 +803,7 @@ static int pmu_sbi_starting_cpu(unsigned int cpu, struct hlist_node *node)
if (riscv_pmu_use_irq) {
cpu_hw_evt->irq = riscv_pmu_irq;
- csr_clear(CSR_IP, BIT(riscv_pmu_irq_num));
+ ALT_SBI_PMU_OVF_CLEAR_PENDING(riscv_pmu_irq_mask);
enable_percpu_irq(riscv_pmu_irq, IRQ_TYPE_NONE);
}
@@ -814,8 +837,14 @@ static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu, struct platform_device *pde
riscv_cached_mimpid(0) == 0) {
riscv_pmu_irq_num = THEAD_C9XX_RV_IRQ_PMU;
riscv_pmu_use_irq = true;
+ } else if (riscv_isa_extension_available(NULL, XANDESPMU) &&
+ IS_ENABLED(CONFIG_ANDES_CUSTOM_PMU)) {
+ riscv_pmu_irq_num = ANDES_SLI_CAUSE_BASE + ANDES_RV_IRQ_PMOVI;
+ riscv_pmu_use_irq = true;
}
+ riscv_pmu_irq_mask = BIT(riscv_pmu_irq_num % BITS_PER_LONG);
+
if (!riscv_pmu_use_irq)
return -EOPNOTSUPP;
--
2.34.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v9 08/10] dt-bindings: riscv: Add Andes PMU extension description
2024-02-22 8:39 [PATCH v9 00/10] Support Andes PMU extension Yu Chien Peter Lin
` (6 preceding siblings ...)
2024-02-22 8:39 ` [PATCH v9 07/10] perf: RISC-V: Introduce Andes PMU to support perf event sampling Yu Chien Peter Lin
@ 2024-02-22 8:39 ` Yu Chien Peter Lin
2024-02-22 8:39 ` [PATCH v9 09/10] riscv: dts: renesas: Add Andes PMU extension for r9a07g043f Yu Chien Peter Lin
` (2 subsequent siblings)
10 siblings, 0 replies; 23+ messages in thread
From: Yu Chien Peter Lin @ 2024-02-22 8:39 UTC (permalink / raw)
To: acme, adrian.hunter, ajones, alexander.shishkin, andre.przywara,
anup, aou, atishp, conor+dt, conor.dooley, conor, devicetree,
evan, geert+renesas, guoren, heiko, irogers, jernej.skrabec,
jolsa, jszhang, krzysztof.kozlowski+dt, linux-arm-kernel,
linux-kernel, linux-perf-users, linux-renesas-soc, linux-riscv,
linux-sunxi, locus84, magnus.damm, mark.rutland, mingo, n.shubin,
namhyung, palmer, paul.walmsley, peterlin, peterz,
prabhakar.mahadev-lad.rj, rdunlap, robh+dt, samuel, sunilvl,
tglx, tim609, uwu, wens, will, inochiama, unicorn_wang, wefu
Document the ISA string for Andes Technology performance monitor
extension which provides counter overflow interrupt and mode
filtering mechanisms.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Changes v2 -> v3:
- New patch
Changes v3 -> v4:
- Include Conor's Acked-by
Changes v4 -> v5:
- Include Prabhakar's Reviewed-by
Changes v5 -> v6:
- No change
Changes v6 -> v7:
- No change
Changes v7 -> v8:
- No change
Changes v8 -> v9:
- No change
---
Documentation/devicetree/bindings/riscv/extensions.yaml | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index 63d81dc895e5..468c646247aa 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -477,5 +477,12 @@ properties:
latency, as ratified in commit 56ed795 ("Update
riscv-crypto-spec-vector.adoc") of riscv-crypto.
+ - const: xandespmu
+ description:
+ The Andes Technology performance monitor extension for counter overflow
+ and privilege mode filtering. For more details, see Counter Related
+ Registers in the AX45MP datasheet.
+ https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
+
additionalProperties: true
...
--
2.34.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v9 09/10] riscv: dts: renesas: Add Andes PMU extension for r9a07g043f
2024-02-22 8:39 [PATCH v9 00/10] Support Andes PMU extension Yu Chien Peter Lin
` (7 preceding siblings ...)
2024-02-22 8:39 ` [PATCH v9 08/10] dt-bindings: riscv: Add Andes PMU extension description Yu Chien Peter Lin
@ 2024-02-22 8:39 ` Yu Chien Peter Lin
2024-02-26 12:28 ` Geert Uytterhoeven
2024-02-22 8:39 ` [PATCH v9 10/10] riscv: andes: Support specifying symbolic firmware and hardware raw events Yu Chien Peter Lin
2024-03-14 12:30 ` [PATCH v9 00/10] Support Andes PMU extension patchwork-bot+linux-riscv
10 siblings, 1 reply; 23+ messages in thread
From: Yu Chien Peter Lin @ 2024-02-22 8:39 UTC (permalink / raw)
To: acme, adrian.hunter, ajones, alexander.shishkin, andre.przywara,
anup, aou, atishp, conor+dt, conor.dooley, conor, devicetree,
evan, geert+renesas, guoren, heiko, irogers, jernej.skrabec,
jolsa, jszhang, krzysztof.kozlowski+dt, linux-arm-kernel,
linux-kernel, linux-perf-users, linux-renesas-soc, linux-riscv,
linux-sunxi, locus84, magnus.damm, mark.rutland, mingo, n.shubin,
namhyung, palmer, paul.walmsley, peterlin, peterz,
prabhakar.mahadev-lad.rj, rdunlap, robh+dt, samuel, sunilvl,
tglx, tim609, uwu, wens, will, inochiama, unicorn_wang, wefu
xandespmu stands for Andes Performance Monitor Unit extension.
Based on the added Andes PMU ISA string, the SBI PMU driver
will make use of the non-standard irq source.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
Changes v1 -> v2:
- New patch
Changes v2 -> v3:
- No change
Changes v3 -> v4:
- No change
Changes v4 -> v5:
- Include Geert's Reviewed-by
- Include Prabhakar's Reviewed/Tested-by
Changes v5 -> v6:
- Include Conor's Acked-by
Changes v6 -> v7:
- No change
Changes v7 -> v8:
- No change
Changes v8 -> v9:
- No change
---
arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
index 099f3df75b42..d7a66043f13b 100644
--- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
+++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
@@ -27,7 +27,7 @@ cpu0: cpu@0 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xandespmu";
mmu-type = "riscv,sv39";
i-cache-size = <0x8000>;
i-cache-line-size = <0x40>;
--
2.34.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v9 10/10] riscv: andes: Support specifying symbolic firmware and hardware raw events
2024-02-22 8:39 [PATCH v9 00/10] Support Andes PMU extension Yu Chien Peter Lin
` (8 preceding siblings ...)
2024-02-22 8:39 ` [PATCH v9 09/10] riscv: dts: renesas: Add Andes PMU extension for r9a07g043f Yu Chien Peter Lin
@ 2024-02-22 8:39 ` Yu Chien Peter Lin
2024-03-14 12:30 ` [PATCH v9 00/10] Support Andes PMU extension patchwork-bot+linux-riscv
10 siblings, 0 replies; 23+ messages in thread
From: Yu Chien Peter Lin @ 2024-02-22 8:39 UTC (permalink / raw)
To: acme, adrian.hunter, ajones, alexander.shishkin, andre.przywara,
anup, aou, atishp, conor+dt, conor.dooley, conor, devicetree,
evan, geert+renesas, guoren, heiko, irogers, jernej.skrabec,
jolsa, jszhang, krzysztof.kozlowski+dt, linux-arm-kernel,
linux-kernel, linux-perf-users, linux-renesas-soc, linux-riscv,
linux-sunxi, locus84, magnus.damm, mark.rutland, mingo, n.shubin,
namhyung, palmer, paul.walmsley, peterlin, peterz,
prabhakar.mahadev-lad.rj, rdunlap, robh+dt, samuel, sunilvl,
tglx, tim609, uwu, wens, will, inochiama, unicorn_wang, wefu
Cc: Charles Ci-Jyun Wu, Leo Yu-Chi Liang, Atish Patra
From: Locus Wei-Han Chen <locus84@andestech.com>
Add the Andes AX45 JSON files that allows specifying symbolic event
names for the raw PMU events.
Signed-off-by: Locus Wei-Han Chen <locus84@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Charles Ci-Jyun Wu <dminus@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Atish Patra <atishp@rivosinc.com>
Acked-by: Ian Rogers <irogers@google.com>
---
Changes v1 -> v2:
- No change
Changes v2 -> v3:
- No change
Changes v3 -> v4:
- No change
Changes v4 -> v5:
- Include Prabhakar's Tested-by
Changes v5 -> v6:
- No change
Changes v6 -> v7:
- No change
Changes v7 -> v8:
- Include Atish's Acked-by
Changes v8 -> v9:
- Include Ian's Acked-by
---
.../arch/riscv/andes/ax45/firmware.json | 68 ++++++++++
.../arch/riscv/andes/ax45/instructions.json | 127 ++++++++++++++++++
.../arch/riscv/andes/ax45/memory.json | 57 ++++++++
.../arch/riscv/andes/ax45/microarch.json | 77 +++++++++++
tools/perf/pmu-events/arch/riscv/mapfile.csv | 1 +
5 files changed, 330 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json
create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/instructions.json
create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/memory.json
create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/microarch.json
diff --git a/tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json b/tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json
new file mode 100644
index 000000000000..9b4a032186a7
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json
@@ -0,0 +1,68 @@
+[
+ {
+ "ArchStdEvent": "FW_MISALIGNED_LOAD"
+ },
+ {
+ "ArchStdEvent": "FW_MISALIGNED_STORE"
+ },
+ {
+ "ArchStdEvent": "FW_ACCESS_LOAD"
+ },
+ {
+ "ArchStdEvent": "FW_ACCESS_STORE"
+ },
+ {
+ "ArchStdEvent": "FW_ILLEGAL_INSN"
+ },
+ {
+ "ArchStdEvent": "FW_SET_TIMER"
+ },
+ {
+ "ArchStdEvent": "FW_IPI_SENT"
+ },
+ {
+ "ArchStdEvent": "FW_IPI_RECEIVED"
+ },
+ {
+ "ArchStdEvent": "FW_FENCE_I_SENT"
+ },
+ {
+ "ArchStdEvent": "FW_FENCE_I_RECEIVED"
+ },
+ {
+ "ArchStdEvent": "FW_SFENCE_VMA_SENT"
+ },
+ {
+ "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED"
+ },
+ {
+ "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED"
+ },
+ {
+ "ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED"
+ },
+ {
+ "ArchStdEvent": "FW_HFENCE_GVMA_SENT"
+ },
+ {
+ "ArchStdEvent": "FW_HFENCE_GVMA_RECEIVED"
+ },
+ {
+ "ArchStdEvent": "FW_HFENCE_GVMA_VMID_SENT"
+ },
+ {
+ "ArchStdEvent": "FW_HFENCE_GVMA_VMID_RECEIVED"
+ },
+ {
+ "ArchStdEvent": "FW_HFENCE_VVMA_SENT"
+ },
+ {
+ "ArchStdEvent": "FW_HFENCE_VVMA_RECEIVED"
+ },
+ {
+ "ArchStdEvent": "FW_HFENCE_VVMA_ASID_SENT"
+ },
+ {
+ "ArchStdEvent": "FW_HFENCE_VVMA_ASID_RECEIVED"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/riscv/andes/ax45/instructions.json b/tools/perf/pmu-events/arch/riscv/andes/ax45/instructions.json
new file mode 100644
index 000000000000..713a08c1a40f
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/andes/ax45/instructions.json
@@ -0,0 +1,127 @@
+[
+ {
+ "EventCode": "0x10",
+ "EventName": "cycle_count",
+ "BriefDescription": "Cycle count"
+ },
+ {
+ "EventCode": "0x20",
+ "EventName": "inst_count",
+ "BriefDescription": "Retired instruction count"
+ },
+ {
+ "EventCode": "0x30",
+ "EventName": "int_load_inst",
+ "BriefDescription": "Integer load instruction count"
+ },
+ {
+ "EventCode": "0x40",
+ "EventName": "int_store_inst",
+ "BriefDescription": "Integer store instruction count"
+ },
+ {
+ "EventCode": "0x50",
+ "EventName": "atomic_inst",
+ "BriefDescription": "Atomic instruction count"
+ },
+ {
+ "EventCode": "0x60",
+ "EventName": "sys_inst",
+ "BriefDescription": "System instruction count"
+ },
+ {
+ "EventCode": "0x70",
+ "EventName": "int_compute_inst",
+ "BriefDescription": "Integer computational instruction count"
+ },
+ {
+ "EventCode": "0x80",
+ "EventName": "condition_br",
+ "BriefDescription": "Conditional branch instruction count"
+ },
+ {
+ "EventCode": "0x90",
+ "EventName": "taken_condition_br",
+ "BriefDescription": "Taken conditional branch instruction count"
+ },
+ {
+ "EventCode": "0xA0",
+ "EventName": "jal_inst",
+ "BriefDescription": "JAL instruction count"
+ },
+ {
+ "EventCode": "0xB0",
+ "EventName": "jalr_inst",
+ "BriefDescription": "JALR instruction count"
+ },
+ {
+ "EventCode": "0xC0",
+ "EventName": "ret_inst",
+ "BriefDescription": "Return instruction count"
+ },
+ {
+ "EventCode": "0xD0",
+ "EventName": "control_trans_inst",
+ "BriefDescription": "Control transfer instruction count"
+ },
+ {
+ "EventCode": "0xE0",
+ "EventName": "ex9_inst",
+ "BriefDescription": "EXEC.IT instruction count"
+ },
+ {
+ "EventCode": "0xF0",
+ "EventName": "int_mul_inst",
+ "BriefDescription": "Integer multiplication instruction count"
+ },
+ {
+ "EventCode": "0x100",
+ "EventName": "int_div_rem_inst",
+ "BriefDescription": "Integer division/remainder instruction count"
+ },
+ {
+ "EventCode": "0x110",
+ "EventName": "float_load_inst",
+ "BriefDescription": "Floating-point load instruction count"
+ },
+ {
+ "EventCode": "0x120",
+ "EventName": "float_store_inst",
+ "BriefDescription": "Floating-point store instruction count"
+ },
+ {
+ "EventCode": "0x130",
+ "EventName": "float_add_sub_inst",
+ "BriefDescription": "Floating-point addition/subtraction instruction count"
+ },
+ {
+ "EventCode": "0x140",
+ "EventName": "float_mul_inst",
+ "BriefDescription": "Floating-point multiplication instruction count"
+ },
+ {
+ "EventCode": "0x150",
+ "EventName": "float_fused_muladd_inst",
+ "BriefDescription": "Floating-point fused multiply-add instruction count"
+ },
+ {
+ "EventCode": "0x160",
+ "EventName": "float_div_sqrt_inst",
+ "BriefDescription": "Floating-point division or square-root instruction count"
+ },
+ {
+ "EventCode": "0x170",
+ "EventName": "other_float_inst",
+ "BriefDescription": "Other floating-point instruction count"
+ },
+ {
+ "EventCode": "0x180",
+ "EventName": "int_mul_add_sub_inst",
+ "BriefDescription": "Integer multiplication and add/sub instruction count"
+ },
+ {
+ "EventCode": "0x190",
+ "EventName": "retired_ops",
+ "BriefDescription": "Retired operation count"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/riscv/andes/ax45/memory.json b/tools/perf/pmu-events/arch/riscv/andes/ax45/memory.json
new file mode 100644
index 000000000000..c7401b526c77
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/andes/ax45/memory.json
@@ -0,0 +1,57 @@
+[
+ {
+ "EventCode": "0x01",
+ "EventName": "ilm_access",
+ "BriefDescription": "ILM access"
+ },
+ {
+ "EventCode": "0x11",
+ "EventName": "dlm_access",
+ "BriefDescription": "DLM access"
+ },
+ {
+ "EventCode": "0x21",
+ "EventName": "icache_access",
+ "BriefDescription": "ICACHE access"
+ },
+ {
+ "EventCode": "0x31",
+ "EventName": "icache_miss",
+ "BriefDescription": "ICACHE miss"
+ },
+ {
+ "EventCode": "0x41",
+ "EventName": "dcache_access",
+ "BriefDescription": "DCACHE access"
+ },
+ {
+ "EventCode": "0x51",
+ "EventName": "dcache_miss",
+ "BriefDescription": "DCACHE miss"
+ },
+ {
+ "EventCode": "0x61",
+ "EventName": "dcache_load_access",
+ "BriefDescription": "DCACHE load access"
+ },
+ {
+ "EventCode": "0x71",
+ "EventName": "dcache_load_miss",
+ "BriefDescription": "DCACHE load miss"
+ },
+ {
+ "EventCode": "0x81",
+ "EventName": "dcache_store_access",
+ "BriefDescription": "DCACHE store access"
+ },
+ {
+ "EventCode": "0x91",
+ "EventName": "dcache_store_miss",
+ "BriefDescription": "DCACHE store miss"
+ },
+ {
+ "EventCode": "0xA1",
+ "EventName": "dcache_wb",
+ "BriefDescription": "DCACHE writeback"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/riscv/andes/ax45/microarch.json b/tools/perf/pmu-events/arch/riscv/andes/ax45/microarch.json
new file mode 100644
index 000000000000..a6d378cbaa74
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/andes/ax45/microarch.json
@@ -0,0 +1,77 @@
+[
+ {
+ "EventCode": "0xB1",
+ "EventName": "cycle_wait_icache_fill",
+ "BriefDescription": "Cycles waiting for ICACHE fill data"
+ },
+ {
+ "EventCode": "0xC1",
+ "EventName": "cycle_wait_dcache_fill",
+ "BriefDescription": "Cycles waiting for DCACHE fill data"
+ },
+ {
+ "EventCode": "0xD1",
+ "EventName": "uncached_ifetch_from_bus",
+ "BriefDescription": "Uncached ifetch data access from bus"
+ },
+ {
+ "EventCode": "0xE1",
+ "EventName": "uncached_load_from_bus",
+ "BriefDescription": "Uncached load data access from bus"
+ },
+ {
+ "EventCode": "0xF1",
+ "EventName": "cycle_wait_uncached_ifetch",
+ "BriefDescription": "Cycles waiting for uncached ifetch data from bus"
+ },
+ {
+ "EventCode": "0x101",
+ "EventName": "cycle_wait_uncached_load",
+ "BriefDescription": "Cycles waiting for uncached load data from bus"
+ },
+ {
+ "EventCode": "0x111",
+ "EventName": "main_itlb_access",
+ "BriefDescription": "Main ITLB access"
+ },
+ {
+ "EventCode": "0x121",
+ "EventName": "main_itlb_miss",
+ "BriefDescription": "Main ITLB miss"
+ },
+ {
+ "EventCode": "0x131",
+ "EventName": "main_dtlb_access",
+ "BriefDescription": "Main DTLB access"
+ },
+ {
+ "EventCode": "0x141",
+ "EventName": "main_dtlb_miss",
+ "BriefDescription": "Main DTLB miss"
+ },
+ {
+ "EventCode": "0x151",
+ "EventName": "cycle_wait_itlb_fill",
+ "BriefDescription": "Cycles waiting for Main ITLB fill data"
+ },
+ {
+ "EventCode": "0x161",
+ "EventName": "pipe_stall_cycle_dtlb_miss",
+ "BriefDescription": "Pipeline stall cycles caused by Main DTLB miss"
+ },
+ {
+ "EventCode": "0x02",
+ "EventName": "mispredict_condition_br",
+ "BriefDescription": "Misprediction of conditional branches"
+ },
+ {
+ "EventCode": "0x12",
+ "EventName": "mispredict_take_condition_br",
+ "BriefDescription": "Misprediction of taken conditional branches"
+ },
+ {
+ "EventCode": "0x22",
+ "EventName": "mispredict_target_ret_inst",
+ "BriefDescription": "Misprediction of targets of Return instructions"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/riscv/mapfile.csv b/tools/perf/pmu-events/arch/riscv/mapfile.csv
index cfc449b19810..3d3a809a5446 100644
--- a/tools/perf/pmu-events/arch/riscv/mapfile.csv
+++ b/tools/perf/pmu-events/arch/riscv/mapfile.csv
@@ -17,3 +17,4 @@
0x489-0x8000000000000007-0x[[:xdigit:]]+,v1,sifive/u74,core
0x5b7-0x0-0x0,v1,thead/c900-legacy,core
0x67e-0x80000000db0000[89]0-0x[[:xdigit:]]+,v1,starfive/dubhe-80,core
+0x31e-0x8000000000008a45-0x[[:xdigit:]]+,v1,andes/ax45,core
--
2.34.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH v9 02/10] irqchip/riscv-intc: Allow large non-standard interrupt number
2024-02-22 8:39 ` [PATCH v9 02/10] irqchip/riscv-intc: Allow large non-standard interrupt number Yu Chien Peter Lin
@ 2024-02-22 21:33 ` Thomas Gleixner
2024-02-23 9:44 ` [tip: irq/msi] " tip-bot2 for Yu Chien Peter Lin
1 sibling, 0 replies; 23+ messages in thread
From: Thomas Gleixner @ 2024-02-22 21:33 UTC (permalink / raw)
To: Yu Chien Peter Lin, acme, adrian.hunter, ajones,
alexander.shishkin, andre.przywara, anup, aou, atishp, conor+dt,
conor.dooley, conor, devicetree, evan, geert+renesas, guoren,
heiko, irogers, jernej.skrabec, jolsa, jszhang,
krzysztof.kozlowski+dt, linux-arm-kernel, linux-kernel,
linux-perf-users, linux-renesas-soc, linux-riscv, linux-sunxi,
locus84, magnus.damm, mark.rutland, mingo, n.shubin, namhyung,
palmer, paul.walmsley, peterlin, peterz,
prabhakar.mahadev-lad.rj, rdunlap, robh+dt, samuel, sunilvl,
tim609, uwu, wens, will, inochiama, unicorn_wang, wefu
Cc: Randolph, Atish Patra
On Thu, Feb 22 2024 at 16:39, Yu Chien Peter Lin wrote:
> Currently, the implementation of the RISC-V INTC driver uses the
> interrupt cause as the hardware interrupt number, with a maximum of
> 64 interrupts. However, the platform can expand the interrupt number
> further for custom local interrupts.
>
> To fully utilize the available local interrupt sources, switch
> to using irq_domain_create_tree() that creates the radix tree
> map, add global variables (riscv_intc_nr_irqs, riscv_intc_custom_base
> and riscv_intc_custom_nr_irqs) to determine the valid range of local
> interrupt number (hwirq).
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> Reviewed-by: Randolph <randolph@andestech.com>
> Reviewed-by: Anup Patel <anup@brainfault.org>
> Reviewed-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v9 03/10] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller
2024-02-22 8:39 ` [PATCH v9 03/10] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller Yu Chien Peter Lin
@ 2024-02-22 21:36 ` Thomas Gleixner
2024-02-23 8:49 ` Thomas Gleixner
2024-02-23 9:43 ` [tip: irq/msi] " tip-bot2 for Yu Chien Peter Lin
1 sibling, 1 reply; 23+ messages in thread
From: Thomas Gleixner @ 2024-02-22 21:36 UTC (permalink / raw)
To: Yu Chien Peter Lin, acme, adrian.hunter, ajones,
alexander.shishkin, andre.przywara, anup, aou, atishp, conor+dt,
conor.dooley, conor, devicetree, evan, geert+renesas, guoren,
heiko, irogers, jernej.skrabec, jolsa, jszhang,
krzysztof.kozlowski+dt, linux-arm-kernel, linux-kernel,
linux-perf-users, linux-renesas-soc, linux-riscv, linux-sunxi,
locus84, magnus.damm, mark.rutland, mingo, n.shubin, namhyung,
palmer, paul.walmsley, peterlin, peterz,
prabhakar.mahadev-lad.rj, rdunlap, robh+dt, samuel, sunilvl,
tim609, uwu, wens, will, inochiama, unicorn_wang, wefu
Cc: Randolph
On Thu, Feb 22 2024 at 16:39, Yu Chien Peter Lin wrote:
> Add support for the Andes hart-level interrupt controller. This
> controller provides interrupt mask/unmask functions to access the
> custom register (SLIE) where the non-standard S-mode local interrupt
> enable bits are located. The base of custom interrupt number is set
> to 256.
>
> To share the riscv_intc_domain_map() with the generic RISC-V INTC and
> ACPI, add a chip parameter to riscv_intc_init_common(), so it can be
> passed to the irq_domain_set_info() as a private data.
>
> Andes hart-level interrupt controller requires the "andestech,cpu-intc"
> compatible string to be present in interrupt-controller of cpu node to
> enable the use of custom local interrupt source.
> e.g.,
>
> cpu0: cpu@0 {
> compatible = "andestech,ax45mp", "riscv";
> ...
> cpu0-intc: interrupt-controller {
> #interrupt-cells = <0x01>;
> compatible = "andestech,cpu-intc", "riscv,cpu-intc";
> interrupt-controller;
> };
> };
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> Reviewed-by: Randolph <randolph@andestech.com>
> Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Palmer, feel free to take this through the riscv tree. I have no other
changes pending against that driver.
Thanks,
tglx
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v9 03/10] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller
2024-02-22 21:36 ` Thomas Gleixner
@ 2024-02-23 8:49 ` Thomas Gleixner
2024-02-23 8:54 ` Thomas Gleixner
0 siblings, 1 reply; 23+ messages in thread
From: Thomas Gleixner @ 2024-02-23 8:49 UTC (permalink / raw)
To: Yu Chien Peter Lin, acme, adrian.hunter, ajones,
alexander.shishkin, andre.przywara, anup, aou, atishp, conor+dt,
conor.dooley, conor, devicetree, evan, geert+renesas, guoren,
heiko, irogers, jernej.skrabec, jolsa, jszhang,
krzysztof.kozlowski+dt, linux-arm-kernel, linux-kernel,
linux-perf-users, linux-renesas-soc, linux-riscv, linux-sunxi,
locus84, magnus.damm, mark.rutland, mingo, n.shubin, namhyung,
palmer, paul.walmsley, peterlin, peterz,
prabhakar.mahadev-lad.rj, rdunlap, robh+dt, samuel, sunilvl,
tim609, uwu, wens, will, inochiama, unicorn_wang, wefu
Cc: Randolph
On Thu, Feb 22 2024 at 22:36, Thomas Gleixner wrote:
> Palmer, feel free to take this through the riscv tree. I have no other
> changes pending against that driver.
Aargh. Spoken too early. This conflicts with Anups AIA series.
https://lore.kernel.org/all/20240222094006.1030709-1-apatel@ventanamicro.com
So I rather take the pile through my tree and deal with the conflicts
localy than inflicting it on next.
Palmer?
Thanks,
tglx
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v9 03/10] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller
2024-02-23 8:49 ` Thomas Gleixner
@ 2024-02-23 8:54 ` Thomas Gleixner
2024-02-23 9:06 ` Thomas Gleixner
0 siblings, 1 reply; 23+ messages in thread
From: Thomas Gleixner @ 2024-02-23 8:54 UTC (permalink / raw)
To: Yu Chien Peter Lin, acme, adrian.hunter, ajones,
alexander.shishkin, andre.przywara, anup, aou, atishp, conor+dt,
conor.dooley, conor, devicetree, evan, geert+renesas, guoren,
heiko, irogers, jernej.skrabec, jolsa, jszhang,
krzysztof.kozlowski+dt, linux-arm-kernel, linux-kernel,
linux-perf-users, linux-renesas-soc, linux-riscv, linux-sunxi,
locus84, magnus.damm, mark.rutland, mingo, n.shubin, namhyung,
palmer, paul.walmsley, peterlin, peterz,
prabhakar.mahadev-lad.rj, rdunlap, robh+dt, samuel, sunilvl,
tim609, uwu, wens, will, inochiama, unicorn_wang, wefu
Cc: Randolph
On Fri, Feb 23 2024 at 09:49, Thomas Gleixner wrote:
> On Thu, Feb 22 2024 at 22:36, Thomas Gleixner wrote:
>> Palmer, feel free to take this through the riscv tree. I have no other
>> changes pending against that driver.
>
> Aargh. Spoken too early. This conflicts with Anups AIA series.
>
> https://lore.kernel.org/all/20240222094006.1030709-1-apatel@ventanamicro.com
>
> So I rather take the pile through my tree and deal with the conflicts
> localy than inflicting it on next.
> Palmer?
Nah. I just apply the two intc patches localy and give you a tag to pull
from so we carry both the same commits. Then I can deal with the
conflicts on my side trivially.
Thanks,
tglx
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v9 03/10] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller
2024-02-23 8:54 ` Thomas Gleixner
@ 2024-02-23 9:06 ` Thomas Gleixner
2024-03-12 14:23 ` Palmer Dabbelt
0 siblings, 1 reply; 23+ messages in thread
From: Thomas Gleixner @ 2024-02-23 9:06 UTC (permalink / raw)
To: Yu Chien Peter Lin, acme, adrian.hunter, ajones,
alexander.shishkin, andre.przywara, anup, aou, atishp, conor+dt,
conor.dooley, conor, devicetree, evan, geert+renesas, guoren,
heiko, irogers, jernej.skrabec, jolsa, jszhang,
krzysztof.kozlowski+dt, linux-arm-kernel, linux-kernel,
linux-perf-users, linux-renesas-soc, linux-riscv, linux-sunxi,
locus84, magnus.damm, mark.rutland, mingo, n.shubin, namhyung,
palmer, paul.walmsley, peterlin, peterz,
prabhakar.mahadev-lad.rj, rdunlap, robh+dt, samuel, sunilvl,
tim609, uwu, wens, will, inochiama, unicorn_wang, wefu
Cc: Randolph
On Fri, Feb 23 2024 at 09:54, Thomas Gleixner wrote:
> On Fri, Feb 23 2024 at 09:49, Thomas Gleixner wrote:
>> On Thu, Feb 22 2024 at 22:36, Thomas Gleixner wrote:
>>> Palmer, feel free to take this through the riscv tree. I have no other
>>> changes pending against that driver.
>>
>> Aargh. Spoken too early. This conflicts with Anups AIA series.
>>
>> https://lore.kernel.org/all/20240222094006.1030709-1-apatel@ventanamicro.com
>>
>> So I rather take the pile through my tree and deal with the conflicts
>> localy than inflicting it on next.
>
>> Palmer?
>
> Nah. I just apply the two intc patches localy and give you a tag to pull
> from so we carry both the same commits. Then I can deal with the
> conflicts on my side trivially.
Here you go:
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git irq-for-riscv-02-23-24
Contains:
f4cc33e78ba8 ("irqchip/riscv-intc: Introduce Andes hart-level interrupt controller")
96303bcb401c ("irqchip/riscv-intc: Allow large non-standard interrupt number")
on top of v6.8-rc1
Thanks,
tglx
^ permalink raw reply [flat|nested] 23+ messages in thread
* [tip: irq/msi] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller
2024-02-22 8:39 ` [PATCH v9 03/10] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller Yu Chien Peter Lin
2024-02-22 21:36 ` Thomas Gleixner
@ 2024-02-23 9:43 ` tip-bot2 for Yu Chien Peter Lin
1 sibling, 0 replies; 23+ messages in thread
From: tip-bot2 for Yu Chien Peter Lin @ 2024-02-23 9:43 UTC (permalink / raw)
To: linux-tip-commits
Cc: Yu Chien Peter Lin, Thomas Gleixner, Randolph, Anup Patel, x86,
linux-kernel
The following commit has been merged into the irq/msi branch of tip:
Commit-ID: f4cc33e78ba8624a79ba8dea98ce5c85aa9ca33c
Gitweb: https://git.kernel.org/tip/f4cc33e78ba8624a79ba8dea98ce5c85aa9ca33c
Author: Yu Chien Peter Lin <peterlin@andestech.com>
AuthorDate: Thu, 22 Feb 2024 16:39:39 +08:00
Committer: Thomas Gleixner <tglx@linutronix.de>
CommitterDate: Fri, 23 Feb 2024 09:57:42 +01:00
irqchip/riscv-intc: Introduce Andes hart-level interrupt controller
Add support for the Andes hart-level interrupt controller. This
controller provides interrupt mask/unmask functions to access the
custom register (SLIE) where the non-standard S-mode local interrupt
enable bits are located. The base of custom interrupt number is set
to 256.
To share the riscv_intc_domain_map() with the generic RISC-V INTC and
ACPI, add a chip parameter to riscv_intc_init_common(), so it can be
passed to the irq_domain_set_info() as a private data.
Andes hart-level interrupt controller requires the "andestech,cpu-intc"
compatible string to be present in interrupt-controller of cpu node to
enable the use of custom local interrupt source.
e.g.,
cpu0: cpu@0 {
compatible = "andestech,ax45mp", "riscv";
...
cpu0-intc: interrupt-controller {
#interrupt-cells = <0x01>;
compatible = "andestech,cpu-intc", "riscv,cpu-intc";
interrupt-controller;
};
};
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Randolph <randolph@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20240222083946.3977135-4-peterlin@andestech.com
---
drivers/irqchip/irq-riscv-intc.c | 58 +++++++++++++++++++++++++++----
include/linux/soc/andes/irq.h | 18 ++++++++++-
2 files changed, 69 insertions(+), 7 deletions(-)
create mode 100644 include/linux/soc/andes/irq.h
diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
index 684875c..0cd6b48 100644
--- a/drivers/irqchip/irq-riscv-intc.c
+++ b/drivers/irqchip/irq-riscv-intc.c
@@ -17,6 +17,7 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/smp.h>
+#include <linux/soc/andes/irq.h>
static struct irq_domain *intc_domain;
static unsigned int riscv_intc_nr_irqs __ro_after_init = BITS_PER_LONG;
@@ -48,6 +49,31 @@ static void riscv_intc_irq_unmask(struct irq_data *d)
csr_set(CSR_IE, BIT(d->hwirq));
}
+static void andes_intc_irq_mask(struct irq_data *d)
+{
+ /*
+ * Andes specific S-mode local interrupt causes (hwirq)
+ * are defined as (256 + n) and controlled by n-th bit
+ * of SLIE.
+ */
+ unsigned int mask = BIT(d->hwirq % BITS_PER_LONG);
+
+ if (d->hwirq < ANDES_SLI_CAUSE_BASE)
+ csr_clear(CSR_IE, mask);
+ else
+ csr_clear(ANDES_CSR_SLIE, mask);
+}
+
+static void andes_intc_irq_unmask(struct irq_data *d)
+{
+ unsigned int mask = BIT(d->hwirq % BITS_PER_LONG);
+
+ if (d->hwirq < ANDES_SLI_CAUSE_BASE)
+ csr_set(CSR_IE, mask);
+ else
+ csr_set(ANDES_CSR_SLIE, mask);
+}
+
static void riscv_intc_irq_eoi(struct irq_data *d)
{
/*
@@ -71,12 +97,21 @@ static struct irq_chip riscv_intc_chip = {
.irq_eoi = riscv_intc_irq_eoi,
};
+static struct irq_chip andes_intc_chip = {
+ .name = "RISC-V INTC",
+ .irq_mask = andes_intc_irq_mask,
+ .irq_unmask = andes_intc_irq_unmask,
+ .irq_eoi = riscv_intc_irq_eoi,
+};
+
static int riscv_intc_domain_map(struct irq_domain *d, unsigned int irq,
irq_hw_number_t hwirq)
{
+ struct irq_chip *chip = d->host_data;
+
irq_set_percpu_devid(irq);
- irq_domain_set_info(d, irq, hwirq, &riscv_intc_chip, d->host_data,
- handle_percpu_devid_irq, NULL, NULL);
+ irq_domain_set_info(d, irq, hwirq, chip, NULL, handle_percpu_devid_irq,
+ NULL, NULL);
return 0;
}
@@ -122,11 +157,12 @@ static struct fwnode_handle *riscv_intc_hwnode(void)
return intc_domain->fwnode;
}
-static int __init riscv_intc_init_common(struct fwnode_handle *fn)
+static int __init riscv_intc_init_common(struct fwnode_handle *fn,
+ struct irq_chip *chip)
{
int rc;
- intc_domain = irq_domain_create_tree(fn, &riscv_intc_domain_ops, NULL);
+ intc_domain = irq_domain_create_tree(fn, &riscv_intc_domain_ops, chip);
if (!intc_domain) {
pr_err("unable to add IRQ domain\n");
return -ENXIO;
@@ -152,8 +188,9 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn)
static int __init riscv_intc_init(struct device_node *node,
struct device_node *parent)
{
- int rc;
+ struct irq_chip *chip = &riscv_intc_chip;
unsigned long hartid;
+ int rc;
rc = riscv_of_parent_hartid(node, &hartid);
if (rc < 0) {
@@ -178,10 +215,17 @@ static int __init riscv_intc_init(struct device_node *node,
return 0;
}
- return riscv_intc_init_common(of_node_to_fwnode(node));
+ if (of_device_is_compatible(node, "andestech,cpu-intc")) {
+ riscv_intc_custom_base = ANDES_SLI_CAUSE_BASE;
+ riscv_intc_custom_nr_irqs = ANDES_RV_IRQ_LAST;
+ chip = &andes_intc_chip;
+ }
+
+ return riscv_intc_init_common(of_node_to_fwnode(node), chip);
}
IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init);
+IRQCHIP_DECLARE(andes, "andestech,cpu-intc", riscv_intc_init);
#ifdef CONFIG_ACPI
@@ -208,7 +252,7 @@ static int __init riscv_intc_acpi_init(union acpi_subtable_headers *header,
return -ENOMEM;
}
- return riscv_intc_init_common(fn);
+ return riscv_intc_init_common(fn, &riscv_intc_chip);
}
IRQCHIP_ACPI_DECLARE(riscv_intc, ACPI_MADT_TYPE_RINTC, NULL,
diff --git a/include/linux/soc/andes/irq.h b/include/linux/soc/andes/irq.h
new file mode 100644
index 0000000..edc3182
--- /dev/null
+++ b/include/linux/soc/andes/irq.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2023 Andes Technology Corporation
+ */
+#ifndef __ANDES_IRQ_H
+#define __ANDES_IRQ_H
+
+/* Andes PMU irq number */
+#define ANDES_RV_IRQ_PMOVI 18
+#define ANDES_RV_IRQ_LAST ANDES_RV_IRQ_PMOVI
+#define ANDES_SLI_CAUSE_BASE 256
+
+/* Andes PMU related registers */
+#define ANDES_CSR_SLIE 0x9c4
+#define ANDES_CSR_SLIP 0x9c5
+#define ANDES_CSR_SCOUNTEROF 0x9d4
+
+#endif /* __ANDES_IRQ_H */
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [tip: irq/msi] irqchip/riscv-intc: Allow large non-standard interrupt number
2024-02-22 8:39 ` [PATCH v9 02/10] irqchip/riscv-intc: Allow large non-standard interrupt number Yu Chien Peter Lin
2024-02-22 21:33 ` Thomas Gleixner
@ 2024-02-23 9:44 ` tip-bot2 for Yu Chien Peter Lin
1 sibling, 0 replies; 23+ messages in thread
From: tip-bot2 for Yu Chien Peter Lin @ 2024-02-23 9:44 UTC (permalink / raw)
To: linux-tip-commits
Cc: Yu Chien Peter Lin, Thomas Gleixner, Randolph, Anup Patel,
Atish Patra, x86, linux-kernel
The following commit has been merged into the irq/msi branch of tip:
Commit-ID: 96303bcb401c21dc1426d8d9bb1fc74aae5c02a9
Gitweb: https://git.kernel.org/tip/96303bcb401c21dc1426d8d9bb1fc74aae5c02a9
Author: Yu Chien Peter Lin <peterlin@andestech.com>
AuthorDate: Thu, 22 Feb 2024 16:39:38 +08:00
Committer: Thomas Gleixner <tglx@linutronix.de>
CommitterDate: Fri, 23 Feb 2024 09:57:42 +01:00
irqchip/riscv-intc: Allow large non-standard interrupt number
Currently, the implementation of the RISC-V INTC driver uses the
interrupt cause as the hardware interrupt number, with a maximum of
64 interrupts. However, the platform can expand the interrupt number
further for custom local interrupts.
To fully utilize the available local interrupt sources, switch
to using irq_domain_create_tree() that creates the radix tree
map, add global variables (riscv_intc_nr_irqs, riscv_intc_custom_base
and riscv_intc_custom_nr_irqs) to determine the valid range of local
interrupt number (hwirq).
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Randolph <randolph@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20240222083946.3977135-3-peterlin@andestech.com
---
drivers/irqchip/irq-riscv-intc.c | 26 +++++++++++++++++++-------
1 file changed, 19 insertions(+), 7 deletions(-)
diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
index e8d01b1..684875c 100644
--- a/drivers/irqchip/irq-riscv-intc.c
+++ b/drivers/irqchip/irq-riscv-intc.c
@@ -19,15 +19,16 @@
#include <linux/smp.h>
static struct irq_domain *intc_domain;
+static unsigned int riscv_intc_nr_irqs __ro_after_init = BITS_PER_LONG;
+static unsigned int riscv_intc_custom_base __ro_after_init = BITS_PER_LONG;
+static unsigned int riscv_intc_custom_nr_irqs __ro_after_init;
static asmlinkage void riscv_intc_irq(struct pt_regs *regs)
{
unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG;
- if (unlikely(cause >= BITS_PER_LONG))
- panic("unexpected interrupt cause");
-
- generic_handle_domain_irq(intc_domain, cause);
+ if (generic_handle_domain_irq(intc_domain, cause))
+ pr_warn_ratelimited("Failed to handle interrupt (cause: %ld)\n", cause);
}
/*
@@ -93,6 +94,14 @@ static int riscv_intc_domain_alloc(struct irq_domain *domain,
if (ret)
return ret;
+ /*
+ * Only allow hwirq for which we have corresponding standard or
+ * custom interrupt enable register.
+ */
+ if ((hwirq >= riscv_intc_nr_irqs && hwirq < riscv_intc_custom_base) ||
+ (hwirq >= riscv_intc_custom_base + riscv_intc_custom_nr_irqs))
+ return -EINVAL;
+
for (i = 0; i < nr_irqs; i++) {
ret = riscv_intc_domain_map(domain, virq + i, hwirq + i);
if (ret)
@@ -117,8 +126,7 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn)
{
int rc;
- intc_domain = irq_domain_create_linear(fn, BITS_PER_LONG,
- &riscv_intc_domain_ops, NULL);
+ intc_domain = irq_domain_create_tree(fn, &riscv_intc_domain_ops, NULL);
if (!intc_domain) {
pr_err("unable to add IRQ domain\n");
return -ENXIO;
@@ -132,7 +140,11 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn)
riscv_set_intc_hwnode_fn(riscv_intc_hwnode);
- pr_info("%d local interrupts mapped\n", BITS_PER_LONG);
+ pr_info("%d local interrupts mapped\n", riscv_intc_nr_irqs);
+ if (riscv_intc_custom_nr_irqs) {
+ pr_info("%d custom local interrupts mapped\n",
+ riscv_intc_custom_nr_irqs);
+ }
return 0;
}
^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH v9 05/10] riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC
2024-02-22 8:39 ` [PATCH v9 05/10] riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC Yu Chien Peter Lin
@ 2024-02-26 12:27 ` Geert Uytterhoeven
0 siblings, 0 replies; 23+ messages in thread
From: Geert Uytterhoeven @ 2024-02-26 12:27 UTC (permalink / raw)
To: Yu Chien Peter Lin
Cc: acme, adrian.hunter, ajones, alexander.shishkin, andre.przywara,
anup, aou, atishp, conor+dt, conor.dooley, conor, devicetree,
evan, geert+renesas, guoren, heiko, irogers, jernej.skrabec,
jolsa, jszhang, krzysztof.kozlowski+dt, linux-arm-kernel,
linux-kernel, linux-perf-users, linux-renesas-soc, linux-riscv,
linux-sunxi, locus84, magnus.damm, mark.rutland, mingo, n.shubin,
namhyung, palmer, paul.walmsley, peterz,
prabhakar.mahadev-lad.rj, rdunlap, robh+dt, samuel, sunilvl,
tglx, tim609, uwu, wens, will, inochiama, unicorn_wang, wefu
On Thu, Feb 22, 2024 at 9:40 AM Yu Chien Peter Lin
<peterlin@andestech.com> wrote:
> The Andes hart-level interrupt controller (Andes INTC) allows AX45MP
> cores to handle custom local interrupts, such as the performance
> counter overflow interrupt.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> Changes v1 -> v2:
> - New patch
> Changes v2 -> v3:
> - Fixed possible compatibles for Andes INTC
> Changes v3 -> v4:
> - No change
> Changes v4 -> v5:
> - Include Geert's Reviewed-by
> - Include Prabhakar's Reviewed/Tested-by
> Changes v5 -> v6:
> - No change
> Changes v6 -> v7:
> - No change
> Changes v7 -> v8:
> - No change
> Changes v8 -> v9:
> - No change
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
so Palmer can pick it up with the rest of the series
(the Renesas tree imerge window for v6.9 has closed)
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v9 09/10] riscv: dts: renesas: Add Andes PMU extension for r9a07g043f
2024-02-22 8:39 ` [PATCH v9 09/10] riscv: dts: renesas: Add Andes PMU extension for r9a07g043f Yu Chien Peter Lin
@ 2024-02-26 12:28 ` Geert Uytterhoeven
0 siblings, 0 replies; 23+ messages in thread
From: Geert Uytterhoeven @ 2024-02-26 12:28 UTC (permalink / raw)
To: Yu Chien Peter Lin
Cc: acme, adrian.hunter, ajones, alexander.shishkin, andre.przywara,
anup, aou, atishp, conor+dt, conor.dooley, conor, devicetree,
evan, geert+renesas, guoren, heiko, irogers, jernej.skrabec,
jolsa, jszhang, krzysztof.kozlowski+dt, linux-arm-kernel,
linux-kernel, linux-perf-users, linux-renesas-soc, linux-riscv,
linux-sunxi, locus84, magnus.damm, mark.rutland, mingo, n.shubin,
namhyung, palmer, paul.walmsley, peterz,
prabhakar.mahadev-lad.rj, rdunlap, robh+dt, samuel, sunilvl,
tglx, tim609, uwu, wens, will, inochiama, unicorn_wang, wefu
On Thu, Feb 22, 2024 at 9:41 AM Yu Chien Peter Lin
<peterlin@andestech.com> wrote:
> xandespmu stands for Andes Performance Monitor Unit extension.
> Based on the added Andes PMU ISA string, the SBI PMU driver
> will make use of the non-standard irq source.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> Changes v1 -> v2:
> - New patch
> Changes v2 -> v3:
> - No change
> Changes v3 -> v4:
> - No change
> Changes v4 -> v5:
> - Include Geert's Reviewed-by
> - Include Prabhakar's Reviewed/Tested-by
> Changes v5 -> v6:
> - Include Conor's Acked-by
> Changes v6 -> v7:
> - No change
> Changes v7 -> v8:
> - No change
> Changes v8 -> v9:
> - No change
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
so Palmer can pick it up with the rest of the series
(the Renesas tree merge window for v6.9 has closed)
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v9 03/10] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller
2024-02-23 9:06 ` Thomas Gleixner
@ 2024-03-12 14:23 ` Palmer Dabbelt
2024-03-12 14:28 ` Thomas Gleixner
0 siblings, 1 reply; 23+ messages in thread
From: Palmer Dabbelt @ 2024-03-12 14:23 UTC (permalink / raw)
To: tglx
Cc: peterlin, acme, adrian.hunter, ajones, alexander.shishkin,
andre.przywara, anup, aou, atishp, conor+dt, Conor Dooley,
Conor Dooley, devicetree, Evan Green, geert+renesas, guoren,
Heiko Stuebner, irogers, jernej.skrabec, jolsa, jszhang,
krzysztof.kozlowski+dt, linux-arm-kernel, linux-kernel,
linux-perf-users, linux-renesas-soc, linux-riscv, linux-sunxi,
locus84, magnus.damm, Mark Rutland, mingo, n.shubin, namhyung,
Paul Walmsley, peterlin, peterz, prabhakar.mahadev-lad.rj,
rdunlap, robh+dt, samuel, Sunil V L, tim609, uwu, wens,
Will Deacon, inochiama, unicorn_wang, wefu, randolph
On Fri, 23 Feb 2024 01:06:44 PST (-0800), tglx@linutronix.de wrote:
> On Fri, Feb 23 2024 at 09:54, Thomas Gleixner wrote:
>> On Fri, Feb 23 2024 at 09:49, Thomas Gleixner wrote:
>>> On Thu, Feb 22 2024 at 22:36, Thomas Gleixner wrote:
>>>> Palmer, feel free to take this through the riscv tree. I have no other
>>>> changes pending against that driver.
>>>
>>> Aargh. Spoken too early. This conflicts with Anups AIA series.
>>>
>>> https://lore.kernel.org/all/20240222094006.1030709-1-apatel@ventanamicro.com
>>>
>>> So I rather take the pile through my tree and deal with the conflicts
>>> localy than inflicting it on next.
>>
>>> Palmer?
>>
>> Nah. I just apply the two intc patches localy and give you a tag to pull
>> from so we carry both the same commits. Then I can deal with the
>> conflicts on my side trivially.
>
> Here you go:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git irq-for-riscv-02-23-24
>
> Contains:
>
> f4cc33e78ba8 ("irqchip/riscv-intc: Introduce Andes hart-level interrupt controller")
> 96303bcb401c ("irqchip/riscv-intc: Allow large non-standard interrupt number")
>
> on top of v6.8-rc1
Sorry I missed this. I just merged this into my testing tree, it might
take a bit to show up because I've managed to break my VPN so I can't
poke the tester box right now...
>
> Thanks,
>
> tglx
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v9 03/10] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller
2024-03-12 14:23 ` Palmer Dabbelt
@ 2024-03-12 14:28 ` Thomas Gleixner
0 siblings, 0 replies; 23+ messages in thread
From: Thomas Gleixner @ 2024-03-12 14:28 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: peterlin, acme, adrian.hunter, ajones, alexander.shishkin,
andre.przywara, anup, aou, atishp, conor+dt, Conor Dooley,
Conor Dooley, devicetree, Evan Green, geert+renesas, guoren,
Heiko Stuebner, irogers, jernej.skrabec, jolsa, jszhang,
krzysztof.kozlowski+dt, linux-arm-kernel, linux-kernel,
linux-perf-users, linux-renesas-soc, linux-riscv, linux-sunxi,
locus84, magnus.damm, Mark Rutland, mingo, n.shubin, namhyung,
Paul Walmsley, peterlin, peterz, prabhakar.mahadev-lad.rj,
rdunlap, robh+dt, samuel, Sunil V L, tim609, uwu, wens,
Will Deacon, inochiama, unicorn_wang, wefu, randolph
On Tue, Mar 12 2024 at 07:23, Palmer Dabbelt wrote:
> On Fri, 23 Feb 2024 01:06:44 PST (-0800), tglx@linutronix.de wrote:
>> Contains:
>>
>> f4cc33e78ba8 ("irqchip/riscv-intc: Introduce Andes hart-level interrupt controller")
>> 96303bcb401c ("irqchip/riscv-intc: Allow large non-standard interrupt number")
>>
>> on top of v6.8-rc1
>
> Sorry I missed this. I just merged this into my testing tree, it might
> take a bit to show up because I've managed to break my VPN so I can't
> poke the tester box right now...
Alternatively you can just rebase on Linus tree. The interrupt changes
are already merged.
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v9 00/10] Support Andes PMU extension
2024-02-22 8:39 [PATCH v9 00/10] Support Andes PMU extension Yu Chien Peter Lin
` (9 preceding siblings ...)
2024-02-22 8:39 ` [PATCH v9 10/10] riscv: andes: Support specifying symbolic firmware and hardware raw events Yu Chien Peter Lin
@ 2024-03-14 12:30 ` patchwork-bot+linux-riscv
10 siblings, 0 replies; 23+ messages in thread
From: patchwork-bot+linux-riscv @ 2024-03-14 12:30 UTC (permalink / raw)
To: Yu Chien Peter Lin
Cc: linux-riscv, acme, adrian.hunter, ajones, alexander.shishkin,
andre.przywara, anup, aou, atishp, conor+dt, conor.dooley, conor,
devicetree, evan, geert+renesas, guoren, heiko, irogers,
jernej.skrabec, jolsa, jszhang, krzysztof.kozlowski+dt,
linux-arm-kernel, linux-kernel, linux-perf-users,
linux-renesas-soc, linux-sunxi, locus84, magnus.damm,
mark.rutland, mingo, n.shubin, namhyung, palmer, paul.walmsley,
peterz, prabhakar.mahadev-lad.rj, rdunlap, robh+dt, samuel,
sunilvl, tglx, tim609, uwu, wens, will, inochiama, unicorn_wang,
wefu
Hello:
This series was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <palmer@rivosinc.com>:
On Thu, 22 Feb 2024 16:39:36 +0800 you wrote:
> Hi All,
>
> This patch series introduces the Andes PMU extension, which serves the
> same purpose as Sscofpmf and Smcntrpmf. Its non-standard local interrupt
> is assigned to bit 18 in the custom S-mode local interrupt enable and
> pending registers (slie/slip), while the interrupt cause is (256 + 18).
>
> [...]
Here is the summary with links:
- [v9,01/10] riscv: errata: Rename defines for Andes
https://git.kernel.org/riscv/c/be5e8872b3fb
- [v9,02/10] irqchip/riscv-intc: Allow large non-standard interrupt number
https://git.kernel.org/riscv/c/96303bcb401c
- [v9,03/10] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller
https://git.kernel.org/riscv/c/f4cc33e78ba8
- [v9,04/10] dt-bindings: riscv: Add Andes interrupt controller compatible string
https://git.kernel.org/riscv/c/b88727d554f0
- [v9,05/10] riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC
https://git.kernel.org/riscv/c/95113bb70515
- [v9,06/10] perf: RISC-V: Eliminate redundant interrupt enable/disable operations
https://git.kernel.org/riscv/c/ea0e0178e101
- [v9,07/10] perf: RISC-V: Introduce Andes PMU to support perf event sampling
https://git.kernel.org/riscv/c/bc969d6cc96a
- [v9,08/10] dt-bindings: riscv: Add Andes PMU extension description
https://git.kernel.org/riscv/c/61609bf2b29d
- [v9,09/10] riscv: dts: renesas: Add Andes PMU extension for r9a07g043f
https://git.kernel.org/riscv/c/270fc77e7b0e
- [v9,10/10] riscv: andes: Support specifying symbolic firmware and hardware raw events
https://git.kernel.org/riscv/c/f5102e31c209
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
^ permalink raw reply [flat|nested] 23+ messages in thread
end of thread, other threads:[~2024-03-14 12:30 UTC | newest]
Thread overview: 23+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-02-22 8:39 [PATCH v9 00/10] Support Andes PMU extension Yu Chien Peter Lin
2024-02-22 8:39 ` [PATCH v9 01/10] riscv: errata: Rename defines for Andes Yu Chien Peter Lin
2024-02-22 8:39 ` [PATCH v9 02/10] irqchip/riscv-intc: Allow large non-standard interrupt number Yu Chien Peter Lin
2024-02-22 21:33 ` Thomas Gleixner
2024-02-23 9:44 ` [tip: irq/msi] " tip-bot2 for Yu Chien Peter Lin
2024-02-22 8:39 ` [PATCH v9 03/10] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller Yu Chien Peter Lin
2024-02-22 21:36 ` Thomas Gleixner
2024-02-23 8:49 ` Thomas Gleixner
2024-02-23 8:54 ` Thomas Gleixner
2024-02-23 9:06 ` Thomas Gleixner
2024-03-12 14:23 ` Palmer Dabbelt
2024-03-12 14:28 ` Thomas Gleixner
2024-02-23 9:43 ` [tip: irq/msi] " tip-bot2 for Yu Chien Peter Lin
2024-02-22 8:39 ` [PATCH v9 04/10] dt-bindings: riscv: Add Andes interrupt controller compatible string Yu Chien Peter Lin
2024-02-22 8:39 ` [PATCH v9 05/10] riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC Yu Chien Peter Lin
2024-02-26 12:27 ` Geert Uytterhoeven
2024-02-22 8:39 ` [PATCH v9 06/10] perf: RISC-V: Eliminate redundant interrupt enable/disable operations Yu Chien Peter Lin
2024-02-22 8:39 ` [PATCH v9 07/10] perf: RISC-V: Introduce Andes PMU to support perf event sampling Yu Chien Peter Lin
2024-02-22 8:39 ` [PATCH v9 08/10] dt-bindings: riscv: Add Andes PMU extension description Yu Chien Peter Lin
2024-02-22 8:39 ` [PATCH v9 09/10] riscv: dts: renesas: Add Andes PMU extension for r9a07g043f Yu Chien Peter Lin
2024-02-26 12:28 ` Geert Uytterhoeven
2024-02-22 8:39 ` [PATCH v9 10/10] riscv: andes: Support specifying symbolic firmware and hardware raw events Yu Chien Peter Lin
2024-03-14 12:30 ` [PATCH v9 00/10] Support Andes PMU extension patchwork-bot+linux-riscv
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).