From: Huang Shijie <b32955-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
To: dwmw2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org
Cc: computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
marex-ynQEQJNshbs@public.gmane.org,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-spi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Huang Shijie <b32955-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
Subject: [PATCH v2 08/10] mtd: spi-nor: add more read transfer flags for n25q256a
Date: Mon, 28 Apr 2014 11:53:45 +0800 [thread overview]
Message-ID: <1398657227-20721-9-git-send-email-b32955@freescale.com> (raw)
In-Reply-To: <1398657227-20721-1-git-send-email-b32955-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
The NOR flash can supports dual/quad/ddr-quad read.
Add more flags for these read transfers.
>From the datasheet, the chip support the 64K sector erase operation.
So remove the SECT_4K for the chip which makes the flash_erase faster.
Signed-off-by: Huang Shijie <b32955-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
---
drivers/mtd/spi-nor/spi-nor.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index e0bc11a..07d249c 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -500,7 +500,7 @@ const struct spi_device_id spi_nor_ids[] = {
{ "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, 0) },
{ "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, 0) },
{ "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, 0) },
- { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K) },
+ { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_DDR_QUAD_READ) },
{ "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K) },
/* PMC */
--
1.7.2.rc3
--
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WARNING: multiple messages have this Message-ID (diff)
From: Huang Shijie <b32955-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
To: <dwmw2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org>
Cc: <computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
<marex-ynQEQJNshbs@public.gmane.org>,
<linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>,
<linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
<linux-spi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
<linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>,
<devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
Huang Shijie <b32955-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
Subject: [PATCH v2 08/10] mtd: spi-nor: add more read transfer flags for n25q256a
Date: Mon, 28 Apr 2014 11:53:45 +0800 [thread overview]
Message-ID: <1398657227-20721-9-git-send-email-b32955@freescale.com> (raw)
In-Reply-To: <1398657227-20721-1-git-send-email-b32955-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
The NOR flash can supports dual/quad/ddr-quad read.
Add more flags for these read transfers.
>From the datasheet, the chip support the 64K sector erase operation.
So remove the SECT_4K for the chip which makes the flash_erase faster.
Signed-off-by: Huang Shijie <b32955-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
---
drivers/mtd/spi-nor/spi-nor.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index e0bc11a..07d249c 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -500,7 +500,7 @@ const struct spi_device_id spi_nor_ids[] = {
{ "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, 0) },
{ "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, 0) },
{ "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, 0) },
- { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K) },
+ { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_DDR_QUAD_READ) },
{ "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K) },
/* PMC */
--
1.7.2.rc3
--
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WARNING: multiple messages have this Message-ID (diff)
From: Huang Shijie <b32955@freescale.com>
To: <dwmw2@infradead.org>
Cc: marex@denx.de, devicetree@vger.kernel.org,
linux-doc@vger.kernel.org, linux-spi@vger.kernel.org,
Huang Shijie <b32955@freescale.com>,
linux-mtd@lists.infradead.org, computersforpeace@gmail.com,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 08/10] mtd: spi-nor: add more read transfer flags for n25q256a
Date: Mon, 28 Apr 2014 11:53:45 +0800 [thread overview]
Message-ID: <1398657227-20721-9-git-send-email-b32955@freescale.com> (raw)
In-Reply-To: <1398657227-20721-1-git-send-email-b32955@freescale.com>
The NOR flash can supports dual/quad/ddr-quad read.
Add more flags for these read transfers.
>From the datasheet, the chip support the 64K sector erase operation.
So remove the SECT_4K for the chip which makes the flash_erase faster.
Signed-off-by: Huang Shijie <b32955@freescale.com>
---
drivers/mtd/spi-nor/spi-nor.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index e0bc11a..07d249c 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -500,7 +500,7 @@ const struct spi_device_id spi_nor_ids[] = {
{ "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, 0) },
{ "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, 0) },
{ "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, 0) },
- { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K) },
+ { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_DDR_QUAD_READ) },
{ "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K) },
/* PMC */
--
1.7.2.rc3
WARNING: multiple messages have this Message-ID (diff)
From: b32955@freescale.com (Huang Shijie)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 08/10] mtd: spi-nor: add more read transfer flags for n25q256a
Date: Mon, 28 Apr 2014 11:53:45 +0800 [thread overview]
Message-ID: <1398657227-20721-9-git-send-email-b32955@freescale.com> (raw)
In-Reply-To: <1398657227-20721-1-git-send-email-b32955@freescale.com>
The NOR flash can supports dual/quad/ddr-quad read.
Add more flags for these read transfers.
>From the datasheet, the chip support the 64K sector erase operation.
So remove the SECT_4K for the chip which makes the flash_erase faster.
Signed-off-by: Huang Shijie <b32955@freescale.com>
---
drivers/mtd/spi-nor/spi-nor.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index e0bc11a..07d249c 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -500,7 +500,7 @@ const struct spi_device_id spi_nor_ids[] = {
{ "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, 0) },
{ "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, 0) },
{ "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, 0) },
- { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K) },
+ { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_DDR_QUAD_READ) },
{ "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K) },
/* PMC */
--
1.7.2.rc3
next prev parent reply other threads:[~2014-04-28 3:53 UTC|newest]
Thread overview: 95+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-04-28 3:53 [PATCH v2 00/10] mtd: spi-nor: Add the DDR quad read support Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` [PATCH v2 03/10] mtd: spi-nor: add " Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 20:23 ` Marek Vasut
2014-04-28 20:23 ` Marek Vasut
2014-04-28 20:23 ` Marek Vasut
2014-07-30 5:08 ` Brian Norris
2014-07-30 5:08 ` Brian Norris
2014-07-30 5:08 ` Brian Norris
2014-07-30 6:44 ` Huang Shijie
2014-07-30 6:44 ` Huang Shijie
2014-07-30 6:44 ` Huang Shijie
2014-07-30 7:45 ` Brian Norris
2014-07-30 7:45 ` Brian Norris
2014-07-30 7:45 ` Brian Norris
2014-07-30 10:46 ` Mark Brown
2014-07-30 10:46 ` Mark Brown
2014-07-30 10:46 ` Mark Brown
2014-08-02 2:06 ` Brian Norris
2014-08-02 2:06 ` Brian Norris
2014-08-02 2:06 ` Brian Norris
2014-08-02 9:09 ` Geert Uytterhoeven
2014-08-02 9:09 ` Geert Uytterhoeven
2014-08-02 9:09 ` Geert Uytterhoeven
[not found] ` <CAMuHMdWxzKG1TTUVgYqfRP0Prp85HPwVxH7NQp7S-pNeLfFqjA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2014-08-04 14:25 ` Mark Brown
2014-08-04 14:25 ` Mark Brown
2014-08-04 14:25 ` Mark Brown
2015-07-22 18:15 ` Zhi Li
2015-07-22 18:15 ` Zhi Li
2015-07-22 18:18 ` Zhi Li
2015-07-22 18:18 ` Zhi Li
2014-07-30 15:23 ` Huang Shijie
2014-07-30 15:23 ` Huang Shijie
2014-07-30 15:23 ` Huang Shijie
[not found] ` <1398657227-20721-1-git-send-email-b32955-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
2014-04-28 3:53 ` [PATCH v2 01/10] mtd: spi-nor: fix the wrong dummy value Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
[not found] ` <1398657227-20721-2-git-send-email-b32955-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
2014-04-28 20:22 ` Marek Vasut
2014-04-28 20:22 ` Marek Vasut
2014-04-28 20:22 ` Marek Vasut
2014-11-05 8:27 ` Brian Norris
2014-11-05 8:27 ` Brian Norris
2014-11-05 8:27 ` Brian Norris
2014-04-28 3:53 ` [PATCH v2 02/10] mtd: spi-nor: add a new field for spi_nor{} Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
[not found] ` <1398657227-20721-3-git-send-email-b32955-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
2014-04-28 20:23 ` Marek Vasut
2014-04-28 20:23 ` Marek Vasut
2014-04-28 20:23 ` Marek Vasut
[not found] ` <201404282223.26174.marex-ynQEQJNshbs@public.gmane.org>
2014-04-29 5:18 ` Huang Shijie
2014-04-29 5:18 ` Huang Shijie
2014-04-29 5:18 ` Huang Shijie
2014-04-29 5:18 ` Huang Shijie
2014-04-29 6:54 ` Marek Vasut
2014-04-29 6:54 ` Marek Vasut
2014-04-29 6:54 ` Marek Vasut
2014-04-29 6:05 ` Huang Shijie
2014-04-29 6:05 ` Huang Shijie
2014-04-29 6:05 ` Huang Shijie
2014-04-29 6:05 ` Huang Shijie
2014-04-28 3:53 ` [PATCH v2 04/10] Documentation: mtd: add a new document for SPI NOR flash Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` [PATCH v2 05/10] Documentation: fsl-quadspi: update the document Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` [PATCH v2 06/10] mtd: fsl-quadspi: use the information stored in spi-nor{} Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` [PATCH v2 07/10] mtd: fsl-quadspi: add the DDR quad read support for Spansion NOR Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie [this message]
2014-04-28 3:53 ` [PATCH v2 08/10] mtd: spi-nor: add more read transfer flags for n25q256a Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` [PATCH v2 09/10] mtd: spi-nor: add DDR quad read support for Micron Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` [PATCH v2 10/10] mtd: fsl-quadspi: " Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
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