From: Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
To: Geert Uytterhoeven <geert-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org>
Cc: "Brian Norris"
<computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
"Huang Shijie"
<shijie.huang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>,
"Huang Shijie" <b32955-KZfg59tc24xl57MIdRCFDg@public.gmane.org>,
"Marek Vašut" <marex-ynQEQJNshbs@public.gmane.org>,
"devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
<devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
"linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
<linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
linux-spi <linux-spi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
"MTD Maling List"
<linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>,
"David Woodhouse" <dwmw2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org>,
"linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org"
<linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>
Subject: Re: [PATCH v2 03/10] mtd: spi-nor: add DDR quad read support
Date: Mon, 4 Aug 2014 15:25:07 +0100 [thread overview]
Message-ID: <20140804142507.GP30458@sirena.org.uk> (raw)
In-Reply-To: <CAMuHMdWxzKG1TTUVgYqfRP0Prp85HPwVxH7NQp7S-pNeLfFqjA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
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On Sat, Aug 02, 2014 at 11:09:09AM +0200, Geert Uytterhoeven wrote:
> On Sat, Aug 2, 2014 at 4:06 AM, Brian Norris
> > On Wed, Jul 30, 2014 at 11:46:07AM +0100, Mark Brown wrote:
> >> I don't know what DDR is in this context, sorry.
> > I think it's just the ability to latch data on both the rising and
> > falling edges of the SPI clock. For SPI flash, it seems to be used for
> > the data portion of the opcode/address/data sequence.
> > Yeah, I suppose it could be wedged in later if drivers/spi/ ever adopts
> > a solution.
> I think this can just be another SPI_* spi_device.mode flag.
Sounds like it yes - I was wondering if this might be one of the modes
with extra clock cycles that I've heard mentioned before which might be
a little more fun.
> Do we need bindings for this in
> Documentation/devicetree/bindings/spi/spi-bus.txt?
> Unlike Quad SPI transfer support, this doesn't need special wiring, so DDR
> capability is an intrinsic property of the SPI slave, and the mode bit can just
> be set in the SPI slave driver, without any DT magic?
Right, unless we run into things like board design issues causing
constraints this is something that can be enabled by the two drivers
without needing DT configuration.
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WARNING: multiple messages have this Message-ID (diff)
From: Mark Brown <broonie@kernel.org>
To: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: "Marek Vašut" <marex@denx.de>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-doc@vger.kernel.org" <linux-doc@vger.kernel.org>,
linux-spi <linux-spi@vger.kernel.org>,
"Huang Shijie" <b32955@freescale.com>,
"MTD Maling List" <linux-mtd@lists.infradead.org>,
"Huang Shijie" <shijie.huang@intel.com>,
"Brian Norris" <computersforpeace@gmail.com>,
"David Woodhouse" <dwmw2@infradead.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v2 03/10] mtd: spi-nor: add DDR quad read support
Date: Mon, 4 Aug 2014 15:25:07 +0100 [thread overview]
Message-ID: <20140804142507.GP30458@sirena.org.uk> (raw)
In-Reply-To: <CAMuHMdWxzKG1TTUVgYqfRP0Prp85HPwVxH7NQp7S-pNeLfFqjA@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 1232 bytes --]
On Sat, Aug 02, 2014 at 11:09:09AM +0200, Geert Uytterhoeven wrote:
> On Sat, Aug 2, 2014 at 4:06 AM, Brian Norris
> > On Wed, Jul 30, 2014 at 11:46:07AM +0100, Mark Brown wrote:
> >> I don't know what DDR is in this context, sorry.
> > I think it's just the ability to latch data on both the rising and
> > falling edges of the SPI clock. For SPI flash, it seems to be used for
> > the data portion of the opcode/address/data sequence.
> > Yeah, I suppose it could be wedged in later if drivers/spi/ ever adopts
> > a solution.
> I think this can just be another SPI_* spi_device.mode flag.
Sounds like it yes - I was wondering if this might be one of the modes
with extra clock cycles that I've heard mentioned before which might be
a little more fun.
> Do we need bindings for this in
> Documentation/devicetree/bindings/spi/spi-bus.txt?
> Unlike Quad SPI transfer support, this doesn't need special wiring, so DDR
> capability is an intrinsic property of the SPI slave, and the mode bit can just
> be set in the SPI slave driver, without any DT magic?
Right, unless we run into things like board design issues causing
constraints this is something that can be enabled by the two drivers
without needing DT configuration.
[-- Attachment #2: Digital signature --]
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WARNING: multiple messages have this Message-ID (diff)
From: broonie@kernel.org (Mark Brown)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 03/10] mtd: spi-nor: add DDR quad read support
Date: Mon, 4 Aug 2014 15:25:07 +0100 [thread overview]
Message-ID: <20140804142507.GP30458@sirena.org.uk> (raw)
In-Reply-To: <CAMuHMdWxzKG1TTUVgYqfRP0Prp85HPwVxH7NQp7S-pNeLfFqjA@mail.gmail.com>
On Sat, Aug 02, 2014 at 11:09:09AM +0200, Geert Uytterhoeven wrote:
> On Sat, Aug 2, 2014 at 4:06 AM, Brian Norris
> > On Wed, Jul 30, 2014 at 11:46:07AM +0100, Mark Brown wrote:
> >> I don't know what DDR is in this context, sorry.
> > I think it's just the ability to latch data on both the rising and
> > falling edges of the SPI clock. For SPI flash, it seems to be used for
> > the data portion of the opcode/address/data sequence.
> > Yeah, I suppose it could be wedged in later if drivers/spi/ ever adopts
> > a solution.
> I think this can just be another SPI_* spi_device.mode flag.
Sounds like it yes - I was wondering if this might be one of the modes
with extra clock cycles that I've heard mentioned before which might be
a little more fun.
> Do we need bindings for this in
> Documentation/devicetree/bindings/spi/spi-bus.txt?
> Unlike Quad SPI transfer support, this doesn't need special wiring, so DDR
> capability is an intrinsic property of the SPI slave, and the mode bit can just
> be set in the SPI slave driver, without any DT magic?
Right, unless we run into things like board design issues causing
constraints this is something that can be enabled by the two drivers
without needing DT configuration.
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next prev parent reply other threads:[~2014-08-04 14:25 UTC|newest]
Thread overview: 95+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-04-28 3:53 [PATCH v2 00/10] mtd: spi-nor: Add the DDR quad read support Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` [PATCH v2 03/10] mtd: spi-nor: add " Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 20:23 ` Marek Vasut
2014-04-28 20:23 ` Marek Vasut
2014-04-28 20:23 ` Marek Vasut
2014-07-30 5:08 ` Brian Norris
2014-07-30 5:08 ` Brian Norris
2014-07-30 5:08 ` Brian Norris
2014-07-30 6:44 ` Huang Shijie
2014-07-30 6:44 ` Huang Shijie
2014-07-30 6:44 ` Huang Shijie
2014-07-30 7:45 ` Brian Norris
2014-07-30 7:45 ` Brian Norris
2014-07-30 7:45 ` Brian Norris
2014-07-30 10:46 ` Mark Brown
2014-07-30 10:46 ` Mark Brown
2014-07-30 10:46 ` Mark Brown
2014-08-02 2:06 ` Brian Norris
2014-08-02 2:06 ` Brian Norris
2014-08-02 2:06 ` Brian Norris
2014-08-02 9:09 ` Geert Uytterhoeven
2014-08-02 9:09 ` Geert Uytterhoeven
2014-08-02 9:09 ` Geert Uytterhoeven
[not found] ` <CAMuHMdWxzKG1TTUVgYqfRP0Prp85HPwVxH7NQp7S-pNeLfFqjA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2014-08-04 14:25 ` Mark Brown [this message]
2014-08-04 14:25 ` Mark Brown
2014-08-04 14:25 ` Mark Brown
2015-07-22 18:15 ` Zhi Li
2015-07-22 18:15 ` Zhi Li
2015-07-22 18:18 ` Zhi Li
2015-07-22 18:18 ` Zhi Li
2014-07-30 15:23 ` Huang Shijie
2014-07-30 15:23 ` Huang Shijie
2014-07-30 15:23 ` Huang Shijie
[not found] ` <1398657227-20721-1-git-send-email-b32955-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
2014-04-28 3:53 ` [PATCH v2 01/10] mtd: spi-nor: fix the wrong dummy value Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
[not found] ` <1398657227-20721-2-git-send-email-b32955-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
2014-04-28 20:22 ` Marek Vasut
2014-04-28 20:22 ` Marek Vasut
2014-04-28 20:22 ` Marek Vasut
2014-11-05 8:27 ` Brian Norris
2014-11-05 8:27 ` Brian Norris
2014-11-05 8:27 ` Brian Norris
2014-04-28 3:53 ` [PATCH v2 02/10] mtd: spi-nor: add a new field for spi_nor{} Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
[not found] ` <1398657227-20721-3-git-send-email-b32955-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
2014-04-28 20:23 ` Marek Vasut
2014-04-28 20:23 ` Marek Vasut
2014-04-28 20:23 ` Marek Vasut
[not found] ` <201404282223.26174.marex-ynQEQJNshbs@public.gmane.org>
2014-04-29 5:18 ` Huang Shijie
2014-04-29 5:18 ` Huang Shijie
2014-04-29 5:18 ` Huang Shijie
2014-04-29 5:18 ` Huang Shijie
2014-04-29 6:54 ` Marek Vasut
2014-04-29 6:54 ` Marek Vasut
2014-04-29 6:54 ` Marek Vasut
2014-04-29 6:05 ` Huang Shijie
2014-04-29 6:05 ` Huang Shijie
2014-04-29 6:05 ` Huang Shijie
2014-04-29 6:05 ` Huang Shijie
2014-04-28 3:53 ` [PATCH v2 04/10] Documentation: mtd: add a new document for SPI NOR flash Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` [PATCH v2 05/10] Documentation: fsl-quadspi: update the document Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` [PATCH v2 06/10] mtd: fsl-quadspi: use the information stored in spi-nor{} Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` [PATCH v2 07/10] mtd: fsl-quadspi: add the DDR quad read support for Spansion NOR Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` [PATCH v2 08/10] mtd: spi-nor: add more read transfer flags for n25q256a Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` [PATCH v2 09/10] mtd: spi-nor: add DDR quad read support for Micron Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` [PATCH v2 10/10] mtd: fsl-quadspi: " Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
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