From: Brian Norris <computersforpeace@gmail.com>
To: Mark Brown <broonie@kernel.org>
Cc: Huang Shijie <shijie.huang@intel.com>,
Huang Shijie <b32955@freescale.com>,
marex@denx.de, devicetree@vger.kernel.org,
linux-doc@vger.kernel.org, linux-spi@vger.kernel.org,
linux-mtd@lists.infradead.org, dwmw2@infradead.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 03/10] mtd: spi-nor: add DDR quad read support
Date: Fri, 1 Aug 2014 19:06:17 -0700 [thread overview]
Message-ID: <20140802020617.GS3711@ld-irv-0074> (raw)
In-Reply-To: <20140730104607.GQ17528@sirena.org.uk>
On Wed, Jul 30, 2014 at 11:46:07AM +0100, Mark Brown wrote:
> On Wed, Jul 30, 2014 at 12:45:00AM -0700, Brian Norris wrote:
> > On Wed, Jul 30, 2014 at 02:44:13PM +0800, Huang Shijie wrote:
> > > IMHO, the DDR modes can _NOT_ be handled by the driver/spi/*.
>
> > I agree to some extent, but I wanted to confirm with the SPI guys that
> > DDR is truly unique to SPI NOR. (I know it doesn't currently support
> > it.)
>
> I don't know what DDR is in this context, sorry.
I think it's just the ability to latch data on both the rising and
falling edges of the SPI clock. For SPI flash, it seems to be used for
the data portion of the opcode/address/data sequence.
> I'm guessing you're
> right since it sounds like something to do with extra clocks and this is
> probably not something used by generic SPI devices at present (if it
> ends up being widely implemented by sufficiently generic controllers
> that might change but the trend seems to be to flash specific
> controllers).
OK, thanks for chiming in.
Yeah, I suppose it could be wedged in later if drivers/spi/ ever adopts
a solution.
Brian
WARNING: multiple messages have this Message-ID (diff)
From: Brian Norris <computersforpeace@gmail.com>
To: Mark Brown <broonie@kernel.org>
Cc: marex@denx.de, devicetree@vger.kernel.org,
linux-doc@vger.kernel.org, linux-spi@vger.kernel.org,
Huang Shijie <b32955@freescale.com>,
linux-mtd@lists.infradead.org,
Huang Shijie <shijie.huang@intel.com>,
dwmw2@infradead.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 03/10] mtd: spi-nor: add DDR quad read support
Date: Fri, 1 Aug 2014 19:06:17 -0700 [thread overview]
Message-ID: <20140802020617.GS3711@ld-irv-0074> (raw)
In-Reply-To: <20140730104607.GQ17528@sirena.org.uk>
On Wed, Jul 30, 2014 at 11:46:07AM +0100, Mark Brown wrote:
> On Wed, Jul 30, 2014 at 12:45:00AM -0700, Brian Norris wrote:
> > On Wed, Jul 30, 2014 at 02:44:13PM +0800, Huang Shijie wrote:
> > > IMHO, the DDR modes can _NOT_ be handled by the driver/spi/*.
>
> > I agree to some extent, but I wanted to confirm with the SPI guys that
> > DDR is truly unique to SPI NOR. (I know it doesn't currently support
> > it.)
>
> I don't know what DDR is in this context, sorry.
I think it's just the ability to latch data on both the rising and
falling edges of the SPI clock. For SPI flash, it seems to be used for
the data portion of the opcode/address/data sequence.
> I'm guessing you're
> right since it sounds like something to do with extra clocks and this is
> probably not something used by generic SPI devices at present (if it
> ends up being widely implemented by sufficiently generic controllers
> that might change but the trend seems to be to flash specific
> controllers).
OK, thanks for chiming in.
Yeah, I suppose it could be wedged in later if drivers/spi/ ever adopts
a solution.
Brian
WARNING: multiple messages have this Message-ID (diff)
From: computersforpeace@gmail.com (Brian Norris)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 03/10] mtd: spi-nor: add DDR quad read support
Date: Fri, 1 Aug 2014 19:06:17 -0700 [thread overview]
Message-ID: <20140802020617.GS3711@ld-irv-0074> (raw)
In-Reply-To: <20140730104607.GQ17528@sirena.org.uk>
On Wed, Jul 30, 2014 at 11:46:07AM +0100, Mark Brown wrote:
> On Wed, Jul 30, 2014 at 12:45:00AM -0700, Brian Norris wrote:
> > On Wed, Jul 30, 2014 at 02:44:13PM +0800, Huang Shijie wrote:
> > > IMHO, the DDR modes can _NOT_ be handled by the driver/spi/*.
>
> > I agree to some extent, but I wanted to confirm with the SPI guys that
> > DDR is truly unique to SPI NOR. (I know it doesn't currently support
> > it.)
>
> I don't know what DDR is in this context, sorry.
I think it's just the ability to latch data on both the rising and
falling edges of the SPI clock. For SPI flash, it seems to be used for
the data portion of the opcode/address/data sequence.
> I'm guessing you're
> right since it sounds like something to do with extra clocks and this is
> probably not something used by generic SPI devices at present (if it
> ends up being widely implemented by sufficiently generic controllers
> that might change but the trend seems to be to flash specific
> controllers).
OK, thanks for chiming in.
Yeah, I suppose it could be wedged in later if drivers/spi/ ever adopts
a solution.
Brian
next prev parent reply other threads:[~2014-08-02 2:06 UTC|newest]
Thread overview: 95+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-04-28 3:53 [PATCH v2 00/10] mtd: spi-nor: Add the DDR quad read support Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` [PATCH v2 03/10] mtd: spi-nor: add " Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 20:23 ` Marek Vasut
2014-04-28 20:23 ` Marek Vasut
2014-04-28 20:23 ` Marek Vasut
2014-07-30 5:08 ` Brian Norris
2014-07-30 5:08 ` Brian Norris
2014-07-30 5:08 ` Brian Norris
2014-07-30 6:44 ` Huang Shijie
2014-07-30 6:44 ` Huang Shijie
2014-07-30 6:44 ` Huang Shijie
2014-07-30 7:45 ` Brian Norris
2014-07-30 7:45 ` Brian Norris
2014-07-30 7:45 ` Brian Norris
2014-07-30 10:46 ` Mark Brown
2014-07-30 10:46 ` Mark Brown
2014-07-30 10:46 ` Mark Brown
2014-08-02 2:06 ` Brian Norris [this message]
2014-08-02 2:06 ` Brian Norris
2014-08-02 2:06 ` Brian Norris
2014-08-02 9:09 ` Geert Uytterhoeven
2014-08-02 9:09 ` Geert Uytterhoeven
2014-08-02 9:09 ` Geert Uytterhoeven
[not found] ` <CAMuHMdWxzKG1TTUVgYqfRP0Prp85HPwVxH7NQp7S-pNeLfFqjA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2014-08-04 14:25 ` Mark Brown
2014-08-04 14:25 ` Mark Brown
2014-08-04 14:25 ` Mark Brown
2015-07-22 18:15 ` Zhi Li
2015-07-22 18:15 ` Zhi Li
2015-07-22 18:18 ` Zhi Li
2015-07-22 18:18 ` Zhi Li
2014-07-30 15:23 ` Huang Shijie
2014-07-30 15:23 ` Huang Shijie
2014-07-30 15:23 ` Huang Shijie
[not found] ` <1398657227-20721-1-git-send-email-b32955-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
2014-04-28 3:53 ` [PATCH v2 01/10] mtd: spi-nor: fix the wrong dummy value Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
[not found] ` <1398657227-20721-2-git-send-email-b32955-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
2014-04-28 20:22 ` Marek Vasut
2014-04-28 20:22 ` Marek Vasut
2014-04-28 20:22 ` Marek Vasut
2014-11-05 8:27 ` Brian Norris
2014-11-05 8:27 ` Brian Norris
2014-11-05 8:27 ` Brian Norris
2014-04-28 3:53 ` [PATCH v2 02/10] mtd: spi-nor: add a new field for spi_nor{} Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
[not found] ` <1398657227-20721-3-git-send-email-b32955-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
2014-04-28 20:23 ` Marek Vasut
2014-04-28 20:23 ` Marek Vasut
2014-04-28 20:23 ` Marek Vasut
[not found] ` <201404282223.26174.marex-ynQEQJNshbs@public.gmane.org>
2014-04-29 5:18 ` Huang Shijie
2014-04-29 5:18 ` Huang Shijie
2014-04-29 5:18 ` Huang Shijie
2014-04-29 5:18 ` Huang Shijie
2014-04-29 6:54 ` Marek Vasut
2014-04-29 6:54 ` Marek Vasut
2014-04-29 6:54 ` Marek Vasut
2014-04-29 6:05 ` Huang Shijie
2014-04-29 6:05 ` Huang Shijie
2014-04-29 6:05 ` Huang Shijie
2014-04-29 6:05 ` Huang Shijie
2014-04-28 3:53 ` [PATCH v2 04/10] Documentation: mtd: add a new document for SPI NOR flash Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` [PATCH v2 05/10] Documentation: fsl-quadspi: update the document Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` [PATCH v2 06/10] mtd: fsl-quadspi: use the information stored in spi-nor{} Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` [PATCH v2 07/10] mtd: fsl-quadspi: add the DDR quad read support for Spansion NOR Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` [PATCH v2 08/10] mtd: spi-nor: add more read transfer flags for n25q256a Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` [PATCH v2 09/10] mtd: spi-nor: add DDR quad read support for Micron Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` [PATCH v2 10/10] mtd: fsl-quadspi: " Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
2014-04-28 3:53 ` Huang Shijie
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