* [U-Boot] [PATCH 01/26] mpc8xx: remove FPS{850, 860}L, NSCU, SM850, TK885D, virtlab2 support
2014-12-15 14:26 [U-Boot] [PATCH 0/26] Start removing non-generic boards Masahiro Yamada
@ 2014-12-15 14:26 ` Masahiro Yamada
2015-01-05 18:21 ` Tom Rini
2014-12-15 14:26 ` [U-Boot] [PATCH 02/26] powerpc: manroland: remove uc100, uc101, mucmc52, hmi1001 support Masahiro Yamada
` (26 subsequent siblings)
27 siblings, 1 reply; 55+ messages in thread
From: Masahiro Yamada @ 2014-12-15 14:26 UTC (permalink / raw)
To: u-boot
These boards are still non-generic boards.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
---
arch/powerpc/cpu/mpc8xx/Kconfig | 18 --
board/tqc/tqm8xx/Kconfig | 78 -------
board/tqc/tqm8xx/MAINTAINERS | 16 --
board/tqc/tqm8xx/tqm8xx.c | 58 +----
configs/FPS850L_defconfig | 3 -
configs/FPS860L_defconfig | 3 -
configs/NSCU_defconfig | 3 -
configs/SM850_defconfig | 3 -
configs/TK885D_defconfig | 3 -
configs/virtlab2_defconfig | 3 -
doc/README.scrapyard | 8 +-
drivers/pcmcia/mpc8xx_pcmcia.c | 2 +-
drivers/pcmcia/tqm8xx_pcmcia.c | 51 +----
include/commproc.h | 55 +----
include/configs/FPS850L.h | 413 ---------------------------------
include/configs/FPS860L.h | 415 ----------------------------------
include/configs/NSCU.h | 463 -------------------------------------
include/configs/SM850.h | 351 ----------------------------
include/configs/TK885D.h | 490 ----------------------------------------
include/configs/virtlab2.h | 469 --------------------------------------
20 files changed, 11 insertions(+), 2894 deletions(-)
delete mode 100644 configs/FPS850L_defconfig
delete mode 100644 configs/FPS860L_defconfig
delete mode 100644 configs/NSCU_defconfig
delete mode 100644 configs/SM850_defconfig
delete mode 100644 configs/TK885D_defconfig
delete mode 100644 configs/virtlab2_defconfig
delete mode 100644 include/configs/FPS850L.h
delete mode 100644 include/configs/FPS860L.h
delete mode 100644 include/configs/NSCU.h
delete mode 100644 include/configs/SM850.h
delete mode 100644 include/configs/TK885D.h
delete mode 100644 include/configs/virtlab2.h
diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig
index 99420ab..33fff0c 100644
--- a/arch/powerpc/cpu/mpc8xx/Kconfig
+++ b/arch/powerpc/cpu/mpc8xx/Kconfig
@@ -49,21 +49,6 @@ config TARGET_ELPT860
config TARGET_UC100
bool "Support uc100"
-config TARGET_FPS850L
- bool "Support FPS850L"
-
-config TARGET_FPS860L
- bool "Support FPS860L"
-
-config TARGET_NSCU
- bool "Support NSCU"
-
-config TARGET_SM850
- bool "Support SM850"
-
-config TARGET_TK885D
- bool "Support TK885D"
-
config TARGET_TQM823L
bool "Support TQM823L"
@@ -100,9 +85,6 @@ config TARGET_TQM866M
config TARGET_TQM885D
bool "Support TQM885D"
-config TARGET_VIRTLAB2
- bool "Support virtlab2"
-
endchoice
source "board/LEOX/elpt860/Kconfig"
diff --git a/board/tqc/tqm8xx/Kconfig b/board/tqc/tqm8xx/Kconfig
index 926a37a..857fedb 100644
--- a/board/tqc/tqm8xx/Kconfig
+++ b/board/tqc/tqm8xx/Kconfig
@@ -1,68 +1,3 @@
-if TARGET_FPS850L
-
-config SYS_BOARD
- default "tqm8xx"
-
-config SYS_VENDOR
- default "tqc"
-
-config SYS_CONFIG_NAME
- default "FPS850L"
-
-endif
-
-if TARGET_FPS860L
-
-config SYS_BOARD
- default "tqm8xx"
-
-config SYS_VENDOR
- default "tqc"
-
-config SYS_CONFIG_NAME
- default "FPS860L"
-
-endif
-
-if TARGET_NSCU
-
-config SYS_BOARD
- default "tqm8xx"
-
-config SYS_VENDOR
- default "tqc"
-
-config SYS_CONFIG_NAME
- default "NSCU"
-
-endif
-
-if TARGET_SM850
-
-config SYS_BOARD
- default "tqm8xx"
-
-config SYS_VENDOR
- default "tqc"
-
-config SYS_CONFIG_NAME
- default "SM850"
-
-endif
-
-if TARGET_TK885D
-
-config SYS_BOARD
- default "tqm8xx"
-
-config SYS_VENDOR
- default "tqc"
-
-config SYS_CONFIG_NAME
- default "TK885D"
-
-endif
-
if TARGET_TQM823L
config SYS_BOARD
@@ -218,16 +153,3 @@ config SYS_CONFIG_NAME
default "TQM885D"
endif
-
-if TARGET_VIRTLAB2
-
-config SYS_BOARD
- default "tqm8xx"
-
-config SYS_VENDOR
- default "tqc"
-
-config SYS_CONFIG_NAME
- default "virtlab2"
-
-endif
diff --git a/board/tqc/tqm8xx/MAINTAINERS b/board/tqc/tqm8xx/MAINTAINERS
index fe4a212..f3ddc6a 100644
--- a/board/tqc/tqm8xx/MAINTAINERS
+++ b/board/tqc/tqm8xx/MAINTAINERS
@@ -2,12 +2,6 @@ TQM8XX BOARD
M: Wolfgang Denk <wd@denx.de>
S: Maintained
F: board/tqc/tqm8xx/
-F: include/configs/FPS850L.h
-F: configs/FPS850L_defconfig
-F: include/configs/FPS860L.h
-F: configs/FPS860L_defconfig
-F: include/configs/SM850.h
-F: configs/SM850_defconfig
F: include/configs/TQM823L.h
F: configs/TQM823L_defconfig
F: configs/TQM823L_LCD_defconfig
@@ -34,14 +28,4 @@ F: configs/TQM866M_defconfig
F: include/configs/TQM885D.h
F: configs/TQM885D_defconfig
F: configs/TTTech_defconfig
-F: include/configs/virtlab2.h
-F: configs/virtlab2_defconfig
F: configs/wtk_defconfig
-
-NSCU BOARD
-#M: -
-S: Maintained
-F: include/configs/NSCU.h
-F: configs/NSCU_defconfig
-F: include/configs/TK885D.h
-F: configs/TK885D_defconfig
diff --git a/board/tqc/tqm8xx/tqm8xx.c b/board/tqc/tqm8xx/tqm8xx.c
index 3b5230a..6d17830 100644
--- a/board/tqc/tqm8xx/tqm8xx.c
+++ b/board/tqc/tqm8xx/tqm8xx.c
@@ -118,9 +118,7 @@ int checkboard (void)
break;
putc (buf[i]);
}
-#ifdef CONFIG_VIRTLAB2
- puts (" (Virtlab2)");
-#endif
+
putc ('\n');
return (0);
@@ -512,14 +510,6 @@ int misc_init_r (void)
immap->im_ioport.iop_padat &= ~0x0001; /* turn it off */
# endif
-#ifdef CONFIG_NSCU
- /* wake up ethernet module */
- immap->im_ioport.iop_pcpar &= ~0x0004; /* GPIO pin */
- immap->im_ioport.iop_pcdir |= 0x0004; /* output */
- immap->im_ioport.iop_pcso &= ~0x0004; /* for clarity */
- immap->im_ioport.iop_pcdat |= 0x0004; /* enable */
-#endif /* CONFIG_NSCU */
-
return (0);
}
#endif /* CONFIG_MISC_INIT_R */
@@ -682,49 +672,3 @@ int ft_board_setup(void *blob, bd_t *bd)
return 0;
}
#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
-
-/* ---------------------------------------------------------------------------- */
-/* TK885D specific initializaion */
-/* ---------------------------------------------------------------------------- */
-#ifdef CONFIG_TK885D
-#include <miiphy.h>
-int last_stage_init(void)
-{
- const unsigned char phy[] = {CONFIG_FEC1_PHY, CONFIG_FEC2_PHY};
- unsigned short reg;
- int ret, i = 100;
- char *s;
-
- mii_init();
- /* Without this delay 0xff is read from the UART buffer later in
- * abortboot() and autoboot is aborted */
- udelay(10000);
- while (tstc() && i--)
- (void)getc();
-
- /* Check if auto-negotiation is prohibited */
- s = getenv("phy_auto_nego");
-
- if (!s || !strcmp(s, "on"))
- /* Nothing to do - autonegotiation by default */
- return 0;
-
- for (i = 0; i < 2; i++) {
- ret = miiphy_read("FEC", phy[i], MII_BMCR, ®);
- if (ret) {
- printf("Cannot read BMCR on PHY %d\n", phy[i]);
- return 0;
- }
- /* Auto-negotiation off, hard set full duplex, 100Mbps */
- ret = miiphy_write("FEC", phy[i],
- MII_BMCR, (reg | BMCR_SPEED100 |
- BMCR_FULLDPLX) & ~BMCR_ANENABLE);
- if (ret) {
- printf("Cannot write BMCR on PHY %d\n", phy[i]);
- return 0;
- }
- }
-
- return 0;
-}
-#endif
diff --git a/configs/FPS850L_defconfig b/configs/FPS850L_defconfig
deleted file mode 100644
index e72ccdd..0000000
--- a/configs/FPS850L_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_8xx=y
-CONFIG_TARGET_FPS850L=y
diff --git a/configs/FPS860L_defconfig b/configs/FPS860L_defconfig
deleted file mode 100644
index 643da6a..0000000
--- a/configs/FPS860L_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_8xx=y
-CONFIG_TARGET_FPS860L=y
diff --git a/configs/NSCU_defconfig b/configs/NSCU_defconfig
deleted file mode 100644
index be96cbd..0000000
--- a/configs/NSCU_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_8xx=y
-CONFIG_TARGET_NSCU=y
diff --git a/configs/SM850_defconfig b/configs/SM850_defconfig
deleted file mode 100644
index 6a50316..0000000
--- a/configs/SM850_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_8xx=y
-CONFIG_TARGET_SM850=y
diff --git a/configs/TK885D_defconfig b/configs/TK885D_defconfig
deleted file mode 100644
index 01bc6dc..0000000
--- a/configs/TK885D_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_8xx=y
-CONFIG_TARGET_TK885D=y
diff --git a/configs/virtlab2_defconfig b/configs/virtlab2_defconfig
deleted file mode 100644
index 3eb3993..0000000
--- a/configs/virtlab2_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_8xx=y
-CONFIG_TARGET_VIRTLAB2=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index deb4af4..3cf32e7 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,7 +12,13 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
-hermes powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
+FPS850L powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
+FPS860L powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
+NSCU powerpc mpc8xx - -
+SM850 powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
+TK885D powerpc mpc8xx - -
+virtlab2 powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
+hermes powerpc mpc8xx 36da51e 2014-12-08 Wolfgang Denk <wd@denx.de>
PRS200 powerpc mpc5200 ecfdcee 2014-11-12
MCC200 powerpc mpc5200 ecfdcee 2014-11-12
TOP5200 powerpc mpc5200 d58a945 2014-10-28 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
diff --git a/drivers/pcmcia/mpc8xx_pcmcia.c b/drivers/pcmcia/mpc8xx_pcmcia.c
index af77426..ea88494 100644
--- a/drivers/pcmcia/mpc8xx_pcmcia.c
+++ b/drivers/pcmcia/mpc8xx_pcmcia.c
@@ -58,7 +58,7 @@ static const u_int m8xx_size_to_gray[M8XX_SIZES_NO] =
/* -------------------------------------------------------------------- */
-#if defined(CONFIG_LWMON) || defined(CONFIG_NSCU)
+#if defined(CONFIG_LWMON)
#define CONFIG_SYS_PCMCIA_TIMING ( PCMCIA_SHT(9) \
| PCMCIA_SST(3) \
| PCMCIA_SL(12))
diff --git a/drivers/pcmcia/tqm8xx_pcmcia.c b/drivers/pcmcia/tqm8xx_pcmcia.c
index 8b74478..45dcb54 100644
--- a/drivers/pcmcia/tqm8xx_pcmcia.c
+++ b/drivers/pcmcia/tqm8xx_pcmcia.c
@@ -22,51 +22,10 @@
#if defined(CONFIG_PCMCIA) \
&& defined(CONFIG_TQM8xxL)
-#if defined(CONFIG_VIRTLAB2)
-#define PCMCIA_BOARD_MSG "Virtlab2"
-#elif defined(CONFIG_TQM8xxL)
+#if defined(CONFIG_TQM8xxL)
#define PCMCIA_BOARD_MSG "TQM8xxL"
#endif
-#if defined(CONFIG_NSCU)
-
-static inline void power_config(int slot) {}
-static inline void power_off(int slot) {}
-static inline void power_on_5_0(int slot) {}
-static inline void power_on_3_3(int slot) {}
-
-#elif defined(CONFIG_VIRTLAB2)
-
-static inline void power_config(int slot) {}
-
-static inline void power_off(int slot)
-{
- volatile unsigned __iomem *addr;
- addr = (volatile unsigned __iomem *)PCMCIA_CTRL;
-
- out_be32(addr, 0);
-}
-
-static inline void power_on_5_0(int slot)
-{
- volatile unsigned __iomem *addr;
- addr = (volatile unsigned __iomem *)PCMCIA_CTRL;
-
- /* Enable 5V Vccout */
- out_be32(addr, 2);
-}
-
-static inline void power_on_3_3(int slot)
-{
- volatile unsigned __iomem *addr;
- addr = (volatile unsigned __iomem *)PCMCIA_CTRL;
-
- /* Enable 3.3V Vccout */
- out_be32(addr, 1);
-}
-
-#else
-
static inline void power_config(int slot)
{
immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
@@ -98,8 +57,6 @@ static inline void power_on_3_3(int slot)
setbits_be16(&immap->im_ioport.iop_pcdir, 0x0002 | 0x0004);
}
-#endif
-
/*
* Function to retrieve the PIPR register, used for debuging purposes.
*/
@@ -121,11 +78,7 @@ static inline int check_card_is_absent(int slot)
return pipr & (0x18000000 >> (slot << 4));
}
-#ifdef NSCU_OE_INV
-#define NSCU_GCRX_CXOE 0
-#else
#define NSCU_GCRX_CXOE __MY_PCMCIA_GCRX_CXOE
-#endif
int pcmcia_hardware_enable(int slot)
{
@@ -243,7 +196,6 @@ int pcmcia_hardware_disable(int slot)
int pcmcia_voltage_set(int slot, int vcc, int vpp)
{
-#ifndef CONFIG_NSCU
u_long reg;
uint32_t pipr = 0;
@@ -296,7 +248,6 @@ done:
udelay(500);
debug("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", slot+'A');
-#endif /* CONFIG_NSCU */
return 0;
}
diff --git a/include/commproc.h b/include/commproc.h
index 6875c4c..3e19603 100644
--- a/include/commproc.h
+++ b/include/commproc.h
@@ -510,31 +510,6 @@ typedef struct scc_enet {
#endif
-/*** FPS850L, FPS860L ************************************************/
-
-#if defined(CONFIG_FPS850L) || defined(CONFIG_FPS860L)
-/* Bits in parallel I/O port registers that have to be set/cleared
- * to configure the pins for SCC2 use.
- */
-#define PROFF_ENET PROFF_SCC2
-#define CPM_CR_ENET CPM_CR_CH_SCC2
-#define SCC_ENET 1
-#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
-#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
-#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
-#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
-
-#define PC_ENET_TENA ((ushort)0x0002) /* PC 14 */
-#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
-#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
-
-/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
- * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
- */
-#define SICR_ENET_MASK ((uint)0x0000ff00)
-#define SICR_ENET_CLKRT ((uint)0x00002600)
-#endif /* CONFIG_FPS850L, CONFIG_FPS860L */
-
/*** IP860 **********************************************************/
#if defined(CONFIG_IP860)
@@ -708,32 +683,6 @@ typedef struct scc_enet {
#endif /* CONFIG_NETVIA */
-/*** SM850 *********************************************************/
-
-/* The SM850 Service Module uses SCC2 for IrDA and SCC3 for Ethernet */
-
-#ifdef CONFIG_SM850
-#define PROFF_ENET PROFF_SCC3 /* Ethernet on SCC3 */
-#define CPM_CR_ENET CPM_CR_CH_SCC3
-#define SCC_ENET 2
-#define PB_ENET_RXD ((uint)0x00000004) /* PB 29 */
-#define PB_ENET_TXD ((uint)0x00000002) /* PB 30 */
-#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
-#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
-
-#define PC_ENET_LBK ((ushort)0x0008) /* PC 12 */
-#define PC_ENET_TENA ((ushort)0x0004) /* PC 13 */
-
-#define PC_ENET_RENA ((ushort)0x0800) /* PC 4 */
-#define PC_ENET_CLSN ((ushort)0x0400) /* PC 5 */
-
-/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
- * SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero.
- */
-#define SICR_ENET_MASK ((uint)0x00FF0000)
-#define SICR_ENET_CLKRT ((uint)0x00260000)
-#endif /* CONFIG_SM850 */
-
/*** SPD823TS ******************************************************/
#ifdef CONFIG_SPD823TS
@@ -770,16 +719,14 @@ typedef struct scc_enet {
defined(CONFIG_RRVISION)|| defined(CONFIG_TQM823L) || \
defined(CONFIG_TQM823M) || defined(CONFIG_TQM850L) || \
defined(CONFIG_TQM850M) || defined(CONFIG_TQM885D) || \
- defined(CONFIG_RRVISION)|| defined(CONFIG_VIRTLAB2)
+ defined(CONFIG_RRVISION)
/* Bits in parallel I/O port registers that have to be set/cleared
* to configure the pins for SCC2 use.
*/
#define PROFF_ENET PROFF_SCC2
#define CPM_CR_ENET CPM_CR_CH_SCC2
-#if (!defined(CONFIG_TK885D)) /* TK885D does not use SCC Ethernet */
#define SCC_ENET 1
-#endif
#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
diff --git a/include/configs/FPS850L.h b/include/configs/FPS850L.h
deleted file mode 100644
index 4ea24a6..0000000
--- a/include/configs/FPS850L.h
+++ /dev/null
@@ -1,413 +0,0 @@
-/*
- * (C) Copyright 2000-2008
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
-#define CONFIG_FPS850L 1 /* ...on a FingerPrint Sensor */
-
-#define CONFIG_SYS_TEXT_BASE 0x40000000
-
-#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
-#define CONFIG_SYS_SMC_RXBUFLEN 128
-#define CONFIG_SYS_MAXIDLE 10
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_BOOTCOUNT_LIMIT
-
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#define CONFIG_BOARD_TYPES 1 /* support board types */
-
-#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "flash_nfs=run nfsargs addip;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
- "rootpath=/opt/eldk/ppc_8xx\0" \
- "hostname=FPS850L\0" \
- "bootfile=FPS850L/uImage\0" \
- "fdt_addr=40040000\0" \
- "kernel_addr=40060000\0" \
- "ramdisk_addr=40200000\0" \
- "u-boot=FPS850L/u-image.bin\0" \
- "load=tftp 200000 ${u-boot}\0" \
- "update=prot off 40000000 +${filesize};" \
- "era 40000000 +${filesize};" \
- "cp.b 200000 40000000 ${filesize};" \
- "sete filesize;save\0" \
- ""
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_NISDOMAIN
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_BOOTP_NTPSERVER
-#define CONFIG_BOOTP_TIMEOFFSET
-
-#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_SNTP
-
-
-#define CONFIG_NETCONSOLE
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xFFF00000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0x40000000
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-
-/* use CFI flash driver */
-#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-
-#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
-
-#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
-
-/*-----------------------------------------------------------------------
- * Dynamic MTD partition support
- */
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
-#define CONFIG_FLASH_CFI_MTD
-#define MTDIDS_DEFAULT "nor0=TQM8xxL-0"
-
-#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \
- "128k(dtb)," \
- "1664k(kernel)," \
- "2m(rootfs)," \
- "4m(data)"
-
-/*-----------------------------------------------------------------------
- * Hardware Information Block
- */
-#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
-#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
-#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register 11-27
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit - leave PLL multiplication factor unchanged !
- */
-#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK SCCR_EBDF11
-#define CONFIG_SYS_SCCR (SCCR_TBS | \
- SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
- SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
- SCCR_DFALCD00)
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_DER 0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
-
-/*
- * FLASH timing:
- */
-#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
- OR_SCY_3_CLK | OR_EHTR | OR_BI)
-
-#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
-
-#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
-#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
-
-/*
- * BR2/3 and OR2/3 (SDRAM)
- *
- */
-#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
-#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
-#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
-#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
-
-#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
-#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
-#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-/*
- * Memory Periodic Timer Prescaler
- *
- * The Divider for PTA (refresh timer) configuration is based on an
- * example SDRAM configuration (64 MBit, one bank). The adjustment to
- * the number of chip selects (NCS) and the actually needed refresh
- * rate is done by setting MPTPR.
- *
- * PTA is calculated from
- * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
- *
- * gclk CPU clock (not bus clock!)
- * Trefresh Refresh cycle * 4 (four word bursts used)
- *
- * 4096 Rows from SDRAM example configuration
- * 1000 factor s -> ms
- * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
- * 4 Number of refresh cycles per period
- * 64 Refresh cycle in ms per number of rows
- * --------------------------------------------
- * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
- *
- * 50 MHz => 50.000.000 / Divider = 98
- * 66 Mhz => 66.000.000 / Divider = 129
- * 80 Mhz => 80.000.000 / Divider = 156
- */
-
-#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
-#define CONFIG_SYS_MAMR_PTA 98
-
-/*
- * For 16 MBit, refresh rates could be 31.3 us
- * (= 64 ms / 2K = 125 / quad bursts).
- * For a simpler initialization, 15.6 us is used instead.
- *
- * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
- * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
- */
-#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
-#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-/* 9 column SDRAM */
-#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-#define CONFIG_HWCONFIG 1
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/FPS860L.h b/include/configs/FPS860L.h
deleted file mode 100644
index c368861..0000000
--- a/include/configs/FPS860L.h
+++ /dev/null
@@ -1,415 +0,0 @@
-/*
- * (C) Copyright 2000-2008
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
-#define CONFIG_FPS860L 1 /* ...on a FingerPrint Sensor */
-
-#define CONFIG_SYS_TEXT_BASE 0x40000000
-
-#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
-#define CONFIG_SYS_SMC_RXBUFLEN 128
-#define CONFIG_SYS_MAXIDLE 10
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_BOOTCOUNT_LIMIT
-
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#define CONFIG_BOARD_TYPES 1 /* support board types */
-
-#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "flash_nfs=run nfsargs addip;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
- "rootpath=/opt/eldk/ppc_8xx\0" \
- "hostname=FPS860L\0" \
- "bootfile=FPS860L/uImage\0" \
- "fdt_addr=40040000\0" \
- "kernel_addr=40060000\0" \
- "ramdisk_addr=40200000\0" \
- "u-boot=FPS860L/u-image.bin\0" \
- "load=tftp 200000 ${u-boot}\0" \
- "update=prot off 40000000 +${filesize};" \
- "era 40000000 +${filesize};" \
- "cp.b 200000 40000000 ${filesize};" \
- "sete filesize;save\0" \
- ""
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_NISDOMAIN
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_BOOTP_NTPSERVER
-#define CONFIG_BOOTP_TIMEOFFSET
-
-#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_SNTP
-
-
-#define CONFIG_NETCONSOLE
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xFFF00000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0x40000000
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-
-/* use CFI flash driver */
-#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-
-#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
-
-#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
-
-/*-----------------------------------------------------------------------
- * Dynamic MTD partition support
- */
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
-#define CONFIG_FLASH_CFI_MTD
-#define MTDIDS_DEFAULT "nor0=TQM8xxL-0"
-
-#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \
- "128k(dtb)," \
- "1664k(kernel)," \
- "2m(rootfs)," \
- "4m(data)"
-
-/*-----------------------------------------------------------------------
- * Hardware Information Block
- */
-#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
-#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
-#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register 11-27
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit - leave PLL multiplication factor unchanged !
- */
-#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK SCCR_EBDF11
-#define CONFIG_SYS_SCCR (SCCR_TBS | \
- SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
- SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
- SCCR_DFALCD00)
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_DER 0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
-
-/*
- * FLASH timing:
- */
-#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
- OR_SCY_3_CLK | OR_EHTR | OR_BI)
-
-#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
-
-#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
-#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
-
-/*
- * BR2/3 and OR2/3 (SDRAM)
- *
- */
-#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
-#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
-#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
-#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
-
-#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
-#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
-#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-/*
- * Memory Periodic Timer Prescaler
- *
- * The Divider for PTA (refresh timer) configuration is based on an
- * example SDRAM configuration (64 MBit, one bank). The adjustment to
- * the number of chip selects (NCS) and the actually needed refresh
- * rate is done by setting MPTPR.
- *
- * PTA is calculated from
- * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
- *
- * gclk CPU clock (not bus clock!)
- * Trefresh Refresh cycle * 4 (four word bursts used)
- *
- * 4096 Rows from SDRAM example configuration
- * 1000 factor s -> ms
- * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
- * 4 Number of refresh cycles per period
- * 64 Refresh cycle in ms per number of rows
- * --------------------------------------------
- * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
- *
- * 50 MHz => 50.000.000 / Divider = 98
- * 66 Mhz => 66.000.000 / Divider = 129
- * 80 Mhz => 80.000.000 / Divider = 156
- */
-
-#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
-#define CONFIG_SYS_MAMR_PTA 98
-
-/*
- * For 16 MBit, refresh rates could be 31.3 us
- * (= 64 ms / 2K = 125 / quad bursts).
- * For a simpler initialization, 15.6 us is used instead.
- *
- * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
- * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
- */
-#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
-#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-/* 9 column SDRAM */
-#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-#define CONFIG_SCC1_ENET
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-#define CONFIG_HWCONFIG 1
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/NSCU.h b/include/configs/NSCU.h
deleted file mode 100644
index a9c649a..0000000
--- a/include/configs/NSCU.h
+++ /dev/null
@@ -1,463 +0,0 @@
-/*
- * (C) Copyright 2000-2008
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC855 1 /* This is a MPC855 CPU */
-#define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */
-#define CONFIG_NSCU 1
-
-#define CONFIG_SYS_TEXT_BASE 0x40000000
-
-#define CONFIG_8xx_CONS_SCC1 1 /* Console is on SMC1 */
-#define CONFIG_SYS_SMC_RXBUFLEN 128
-#define CONFIG_SYS_MAXIDLE 10
-
-#define CONFIG_66MHz 1 /* running@66 MHz, 1:1 clock */
-
-#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
-
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#define CONFIG_BOARD_TYPES 1 /* support board types */
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "flash_nfs=run nfsargs addip;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
- "rootpath=/opt/eldk/ppc_8xx\0" \
- "hostname=NSCU\0" \
- "bootfile=${hostname}/uImage\0" \
- "kernel_addr=40080000\0" \
- "ramdisk_addr=40180000\0" \
- "u-boot=${hostname}/u-image.bin\0" \
- "load=tftp 200000 ${u-boot}\0" \
- "update=prot off 40000000 +${filesize};" \
- "era 40000000 +${filesize};" \
- "cp.b 200000 40000000 ${filesize};" \
- "sete filesize;save\0" \
- ""
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-#define CONFIG_MISC_INIT_R 1
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_STATUS_LED 1 /* Status LED enabled */
-
-#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-
-#define CONFIG_ISP1362_USB /* ISP1362 USB OTG controller */
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_SNTP
-
-
-#define CONFIG_NETCONSOLE
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history
-*/
-#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xFFF00000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0x40000000
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-
-/* use CFI flash driver */
-#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-
-#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
-
-/*-----------------------------------------------------------------------
- * Hardware Information Block
- */
-#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
-#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
-#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#ifndef CONFIG_CAN_DRIVER
-#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-#else /* we must activate GPL5 in the SIUMCR for CAN */
-#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-#endif /* CONFIG_CAN_DRIVER */
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register 11-27
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit
- */
-#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK SCCR_EBDF11
-#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
- SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
- SCCR_DFALCD00)
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-/* NSCU use both slots, SLOT_A as "primary". */
-#define CONFIG_PCMCIA_SLOT_A 1
-
-#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
-#define PCMCIA_MEM_WIN_NO 8 /* override default 4 in pcmcia.h */
-#define PCMCIA_SOCKETS_NO 2 /* we have two sockets */
-#undef NSCU_OE_INV /* PCMCIA_GCRX_CXOE was inverted on early boards */
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
- *-----------------------------------------------------------------------
- */
-
-#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
-#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
-
-#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
-#undef CONFIG_IDE_LED /* LED for ide not supported */
-#undef CONFIG_IDE_RESET /* reset for ide not supported */
-
-#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE buses */
-#define CONFIG_SYS_IDE_MAXDEVICE 4 /* max. 2 drives per IDE bus */
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-#define CONFIG_SYS_ATA_IDE1_OFFSET (4 * CONFIG_SYS_PCMCIA_MEM_SIZE) /* starts @ 4th window */
-
-#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_DER 0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
-
-/*
- * FLASH timing:
- */
-#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
- OR_SCY_3_CLK | OR_EHTR | OR_BI)
-
-#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
-
-#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
-#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
-
-/*
- * BR2/3 and OR2/3 (SDRAM)
- *
- */
-#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
-#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
-#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
-#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
-
-#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
-#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-#ifndef CONFIG_CAN_DRIVER
-#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
-#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
-#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
-#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
-#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
-#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
- BR_PS_8 | BR_MS_UPMB | BR_V )
-#endif /* CONFIG_CAN_DRIVER */
-
-#ifdef CONFIG_ISP1362_USB
-#define CONFIG_SYS_ISP1362_BASE 0xD0000000 /* ISP1362 mapped@0xD0000000 */
-#define CONFIG_SYS_ISP1362_OR_AM 0xFFFF8000 /* 32 kB address mask */
-#define CONFIG_SYS_OR5_ISP1362 (CONFIG_SYS_ISP1362_OR_AM | OR_CSNT_SAM | \
- OR_ACS_DIV2 | OR_BI | OR_SCY_5_CLK)
-#define CONFIG_SYS_BR5_ISP1362 ((CONFIG_SYS_ISP1362_BASE & BR_BA_MSK) | \
- BR_PS_16 | BR_MS_GPCM | BR_V )
-#endif /* CONFIG_ISP1362_USB */
-
-/*
- * Memory Periodic Timer Prescaler
- *
- * The Divider for PTA (refresh timer) configuration is based on an
- * example SDRAM configuration (64 MBit, one bank). The adjustment to
- * the number of chip selects (NCS) and the actually needed refresh
- * rate is done by setting MPTPR.
- *
- * PTA is calculated from
- * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
- *
- * gclk CPU clock (not bus clock!)
- * Trefresh Refresh cycle * 4 (four word bursts used)
- *
- * 4096 Rows from SDRAM example configuration
- * 1000 factor s -> ms
- * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
- * 4 Number of refresh cycles per period
- * 64 Refresh cycle in ms per number of rows
- * --------------------------------------------
- * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
- *
- * 50 MHz => 50.000.000 / Divider = 98
- * 66 Mhz => 66.000.000 / Divider = 129
- * 80 Mhz => 80.000.000 / Divider = 156
- */
-
-#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
-#define CONFIG_SYS_MAMR_PTA 98
-
-/*
- * For 16 MBit, refresh rates could be 31.3 us
- * (= 64 ms / 2K = 125 / quad bursts).
- * For a simpler initialization, 15.6 us is used instead.
- *
- * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
- * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
- */
-#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
-#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-/* 9 column SDRAM */
-#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-#undef CONFIG_SCC1_ENET
-#define CONFIG_FEC_ENET
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-#define CONFIG_HWCONFIG 1
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/SM850.h b/include/configs/SM850.h
deleted file mode 100644
index a7e4464..0000000
--- a/include/configs/SM850.h
+++ /dev/null
@@ -1,351 +0,0 @@
-/*
- * (C) Copyright 2000-2008
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#undef TQM8xxL_80MHz /* 1 / * define for 80 MHz CPU only */
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
-#define CONFIG_SM850 1 /*...on a MPC850 Service Module */
-
-#define CONFIG_SYS_TEXT_BASE 0x40000000
-
-#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
-#define CONFIG_SYS_SMC_RXBUFLEN 128
-#define CONFIG_SYS_MAXIDLE 10
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
-
-#define CONFIG_BOARD_TYPES 1 /* support board types */
-
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND \
- "bootp; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
- "bootm"
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#undef CONFIG_STATUS_LED /* Status LED not enabled */
-
-#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DATE
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB) && defined(KGDB_DEBUG)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xFFF00000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0x40000000
-#if defined(DEBUG)
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#else
-#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
-#endif
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-/* use CFI flash driver */
-#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
-
-#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
-
-/*-----------------------------------------------------------------------
- * Hardware Information Block
- */
-#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
-#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
-#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#ifndef CONFIG_CAN_DRIVER
-#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-#else /* we must activate GPL5 in the SIUMCR for CAN */
-#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-#endif /* CONFIG_CAN_DRIVER */
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register 11-27
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit
- *
- * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
- */
-#ifdef TQM8xxL_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
-#define CONFIG_SYS_PLPRCR \
- ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
-#else
-#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-#endif /* TQM8xxL_80MHz */
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK SCCR_EBDF11
-#ifdef TQM8xxL_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
-#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ \
- SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
- SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
- SCCR_DFALCD00)
-#else /* up to 50 MHz we use a 1:1 clock */
-#define CONFIG_SYS_SCCR (SCCR_TBS | \
- SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
- SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
- SCCR_DFALCD00)
-#endif /* TQM8xxL_80MHz */
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_DER 0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
-
-/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
-#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
- OR_SCY_5_CLK | OR_EHTR)
-
-#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
-
-#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
-#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
-
-/*
- * BR2/3 and OR2/3 (SDRAM)
- *
- */
-#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
-#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
-#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
-#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
-
-#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
-#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-#ifndef CONFIG_CAN_DRIVER
-#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
-#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
-#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
-#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
-#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
-#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
- BR_PS_8 | BR_MS_UPMB | BR_V )
-#endif /* CONFIG_CAN_DRIVER */
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */
-
-/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
-#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
-#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-/* 9 column SDRAM */
-#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-#define CONFIG_HWCONFIG 1
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/TK885D.h b/include/configs/TK885D.h
deleted file mode 100644
index 5e1c52d..0000000
--- a/include/configs/TK885D.h
+++ /dev/null
@@ -1,490 +0,0 @@
-/*
- * (C) Copyright 2000-2005
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * (C) Copyright 2006
- * Martin Krause, TQ-Systems GmBH, martin.krause@tqs.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC885 1 /* This is a MPC885 CPU */
-#define CONFIG_TQM885D 1 /* ...on a TQM88D module */
-#define CONFIG_TK885D 1 /* ...in a TK885D base board */
-
-#define CONFIG_SYS_TEXT_BASE 0x40000000
-
-#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */
-#define CONFIG_SYS_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */
-#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */
-#define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 66 MHz - CPU default clock */
- /* (it will be used if there is no */
- /* 'cpuclk' variable with valid value) */
-
-#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#define CONFIG_SYS_SMC_RXBUFLEN 128
-#define CONFIG_SYS_MAXIDLE 10
-#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
-
-#define CONFIG_BOOTCOUNT_LIMIT
-
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#define CONFIG_BOARD_TYPES 1 /* support board types */
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "ethprime=FEC\0" \
- "ethact=FEC\0" \
- "netdev=eth0\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "flash_nfs=run nfsargs addip;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
- "rootpath=/opt/eldk/ppc_8xx\0" \
- "bootfile=/tftpboot/tk885d/uImage\0" \
- "u-boot=/tftpboot/tk885d/u-boot.bin\0" \
- "kernel_addr=40080000\0" \
- "ramdisk_addr=40180000\0" \
- "load=tftp 200000 ${u-boot}\0" \
- "update=protect off 40000000 +${filesize};" \
- "erase 40000000 +${filesize};" \
- "cp.b 200000 40000000 ${filesize};" \
- "protect on 40000000 +${filesize}\0" \
- ""
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_STATUS_LED 1 /* Status LED enabled */
-
-#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-
-/* enable I2C and select the hardware/software driver */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define PB_SCL 0x00000020 /* PB 26 */
-#define PB_SDA 0x00000010 /* PB 27 */
-
-#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
-#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
-#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
-#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
-#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
- else immr->im_cpm.cp_pbdat &= ~PB_SDA
-#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
- else immr->im_cpm.cp_pbdat &= ~PB_SCL
-#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C?? */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-
-# define CONFIG_RTC_DS1337 1
-# define CONFIG_SYS_I2C_RTC_ADDR 0x68
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#undef CONFIG_RTC_MPC8xx /* MPC885 does not support RTC */
-
-#define CONFIG_TIMESTAMP /* but print image timestmps */
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PING
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0300000 /* 1 ... 3 MB in DRAM */
-#define CONFIG_SYS_ALT_MEMTEST /* alternate, more extensive
- memory test.*/
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-/*
- * Enable loopw command.
- */
-#define CONFIG_LOOPW
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xFFF00000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0x40000000
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-
-/* use CFI flash driver */
-#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */
-#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-
-/*-----------------------------------------------------------------------
- * Hardware Information Block
- */
-#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
-#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
-#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#ifndef CONFIG_CAN_DRIVER
-#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-#else /* we must activate GPL5 in the SIUMCR for CAN */
-#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-#endif /* CONFIG_CAN_DRIVER */
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK SCCR_EBDF11
-#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
- SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
- SCCR_DFALCD00)
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
- *-----------------------------------------------------------------------
- */
-
-#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
-#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
-
-#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
-#undef CONFIG_IDE_LED /* LED for ide not supported */
-#undef CONFIG_IDE_RESET /* reset for ide not supported */
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_DER 0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
-
-/*
- * FLASH timing: Default value of OR0 after reset
- */
-#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
- OR_SCY_6_CLK | OR_TRLX)
-
-#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
-
-#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
-#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
-
-/*
- * BR2/3 and OR2/3 (SDRAM)
- *
- */
-#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
-#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
-#define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
-#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
-
-#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
-#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-#ifndef CONFIG_CAN_DRIVER
-#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
-#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
-#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped@0xC0000000 */
-#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
-#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
-#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
- BR_PS_8 | BR_MS_UPMB | BR_V )
-#endif /* CONFIG_CAN_DRIVER */
-
-/*
- * 4096 Rows from SDRAM example configuration
- * 1000 factor s -> ms
- * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
- * 4 Number of refresh cycles per period
- * 64 Refresh cycle in ms per number of rows
- */
-#define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
-
-/*
- * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad)
- *
- * CPUclock(MHz) * 31.2
- * CONFIG_SYS_MAMR_PTA = ----------------------------------- with DFBRG = 0
- * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16
- *
- * CPU clock = 15 MHz: CONFIG_SYS_MAMR_PTA = 29 -> 4 * 7.73 us
- * CPU clock = 50 MHz: CONFIG_SYS_MAMR_PTA = 97 -> 4 * 7.76 us
- * CPU clock = 66 MHz: CONFIG_SYS_MAMR_PTA = 128 -> 4 * 7.75 us
- * CPU clock = 133 MHz: CONFIG_SYS_MAMR_PTA = 255 -> 4 * 7.67 us
- *
- * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will
- * be met also in the default configuration, i.e. if environment variable
- * 'cpuclk' is not set.
- */
-#define CONFIG_SYS_MAMR_PTA 128
-
-/*
- * Memory Periodic Timer Prescaler Register (MPTPR) values.
- */
-/* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */
-#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16
-/* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */
-#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-/* 9 column SDRAM */
-#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-/* 10 column SDRAM */
-#define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-/*
- * Network configuration
- */
-#define CONFIG_FEC_ENET /* enable ethernet on FEC */
-#define CONFIG_ETHER_ON_FEC1 /* ... for FEC1 */
-#define CONFIG_ETHER_ON_FEC2 /* ... for FEC2 */
-
-#define CONFIG_LAST_STAGE_INIT 1 /* Have to configure PHYs for Linux */
-
-/* CONFIG_SYS_DISCOVER_PHY only works with FEC if only one interface is enabled */
-#if (!defined(CONFIG_ETHER_ON_FEC1) || !defined(CONFIG_ETHER_ON_FEC2))
-#define CONFIG_SYS_DISCOVER_PHY
-#endif
-
-#ifndef CONFIG_SYS_DISCOVER_PHY
-/* PHY addresses - hard wired in hardware */
-#define CONFIG_FEC1_PHY 1
-#define CONFIG_FEC2_PHY 2
-#endif
-
-#define CONFIG_MII_INIT 1
-
-#define CONFIG_NET_RETRY_COUNT 3
-#define CONFIG_ETHPRIME "FEC"
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-#define CONFIG_HWCONFIG 1
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/virtlab2.h b/include/configs/virtlab2.h
deleted file mode 100644
index 0457cdf..0000000
--- a/include/configs/virtlab2.h
+++ /dev/null
@@ -1,469 +0,0 @@
-/*
- * (C) Copyright 2006-2008
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
-#define CONFIG_VIRTLAB2 1 /* ...on a virtlab2 module */
-#define CONFIG_TQM8xxL 1
-
-#define CONFIG_SYS_TEXT_BASE 0x40000000
-
-#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#define CONFIG_SYS_SMC_RXBUFLEN 128
-#define CONFIG_SYS_MAXIDLE 10
-#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
-
-#define CONFIG_BOOTCOUNT_LIMIT
-
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#define CONFIG_BOARD_TYPES 1 /* support board types */
-
-#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "flash_nfs=run nfsargs addip;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
- "rootpath=/opt/eldk/ppc_8xx\0" \
- "hostname=virtlab2\0" \
- "bootfile=virtlab2/uImage\0" \
- "fdt_addr=40040000\0" \
- "kernel_addr=40060000\0" \
- "ramdisk_addr=40200000\0" \
- "u-boot=virtlab2/u-image.bin\0" \
- "load=tftp 200000 ${u-boot}\0" \
- "update=prot off 40000000 +${filesize};" \
- "era 40000000 +${filesize};" \
- "cp.b 200000 40000000 ${filesize};" \
- "sete filesize;save\0" \
- ""
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#if defined(CONFIG_LCD)
-# undef CONFIG_STATUS_LED /* disturbs display */
-#else
-# define CONFIG_STATUS_LED 1 /* Status LED enabled */
-#endif /* CONFIG_LCD */
-
-#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_SNTP
-
-#if defined(CONFIG_SPLASH_SCREEN)
- #define CONFIG_CMD_BMP
-#endif
-
-
-#define CONFIG_NETCONSOLE
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xFFF00000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0x40000000
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-
-/* use CFI flash driver */
-#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-
-#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
-
-#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
-
-/*-----------------------------------------------------------------------
- * Dynamic MTD partition support
- */
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
-#define CONFIG_FLASH_CFI_MTD
-#define MTDIDS_DEFAULT "nor0=TQM8xxL-0"
-
-#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \
- "128k(dtb)," \
- "1664k(kernel)," \
- "2m(rootfs)," \
- "4m(data)"
-
-/*-----------------------------------------------------------------------
- * Hardware Information Block
- */
-#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
-#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
-#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#ifndef CONFIG_CAN_DRIVER
-#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-#else /* we must activate GPL5 in the SIUMCR for CAN */
-#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-#endif /* CONFIG_CAN_DRIVER */
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register 11-27
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit
- */
-#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK SCCR_EBDF11
-#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
- SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
- SCCR_DFALCD00)
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
- *-----------------------------------------------------------------------
- */
-
-#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
-#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
-
-#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
-#undef CONFIG_IDE_LED /* LED for ide not supported */
-#undef CONFIG_IDE_RESET /* reset for ide not supported */
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_DER 0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
-
-/*
- * FLASH timing:
- */
-#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
- OR_SCY_3_CLK | OR_EHTR | OR_BI)
-
-#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
-
-#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
-#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
-
-/*
- * BR2/3 and OR2/3 (SDRAM)
- *
- */
-#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
-#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
-#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
-#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
-
-#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
-#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-#ifndef CONFIG_CAN_DRIVER
-#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
-#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
-#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped@0xC0000000 */
-#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
-#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
-#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
- BR_PS_8 | BR_MS_UPMB | BR_V )
-#endif /* CONFIG_CAN_DRIVER */
-
-/*
- * Memory Periodic Timer Prescaler
- *
- * The Divider for PTA (refresh timer) configuration is based on an
- * example SDRAM configuration (64 MBit, one bank). The adjustment to
- * the number of chip selects (NCS) and the actually needed refresh
- * rate is done by setting MPTPR.
- *
- * PTA is calculated from
- * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
- *
- * gclk CPU clock (not bus clock!)
- * Trefresh Refresh cycle * 4 (four word bursts used)
- *
- * 4096 Rows from SDRAM example configuration
- * 1000 factor s -> ms
- * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
- * 4 Number of refresh cycles per period
- * 64 Refresh cycle in ms per number of rows
- * --------------------------------------------
- * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
- *
- * 50 MHz => 50.000.000 / Divider = 98
- * 66 Mhz => 66.000.000 / Divider = 129
- * 80 Mhz => 80.000.000 / Divider = 156
- */
-
-#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
-#define CONFIG_SYS_MAMR_PTA 98
-
-/*
- * For 16 MBit, refresh rates could be 31.3 us
- * (= 64 ms / 2K = 125 / quad bursts).
- * For a simpler initialization, 15.6 us is used instead.
- *
- * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
- * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
- */
-#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
-#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-/* 9 column SDRAM */
-#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-/* Map peripheral control registers on CS4 */
-#define CONFIG_SYS_PERIPHERAL_BASE 0xA0000000
-#define CONFIG_SYS_PERIPHERAL_OR_AM 0xFFFF8000 /* 32 kB address mask */
-#define CONFIG_SYS_OR4_PRELIM (CONFIG_SYS_PERIPHERAL_OR_AM | OR_TRLX | OR_CSNT_SAM | \
- OR_SCY_2_CLK)
-#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_PERIPHERAL_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
-#define PCMCIA_CTRL (CONFIG_SYS_PERIPHERAL_BASE + 0xB00)
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-#define CONFIG_HWCONFIG 1
-
-#endif /* __CONFIG_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [U-Boot] [PATCH 01/26] mpc8xx: remove FPS{850, 860}L, NSCU, SM850, TK885D, virtlab2 support
2014-12-15 14:26 ` [U-Boot] [PATCH 01/26] mpc8xx: remove FPS{850, 860}L, NSCU, SM850, TK885D, virtlab2 support Masahiro Yamada
@ 2015-01-05 18:21 ` Tom Rini
0 siblings, 0 replies; 55+ messages in thread
From: Tom Rini @ 2015-01-05 18:21 UTC (permalink / raw)
To: u-boot
On Mon, Dec 15, 2014 at 11:26:06PM +0900, Masahiro Yamada wrote:
> These boards are still non-generic boards.
>
> Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
> Cc: Wolfgang Denk <wd@denx.de>
Applied to u-boot/master, thanks!
--
Tom
-------------- next part --------------
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^ permalink raw reply [flat|nested] 55+ messages in thread
* [U-Boot] [PATCH 02/26] powerpc: manroland: remove uc100, uc101, mucmc52, hmi1001 support
2014-12-15 14:26 [U-Boot] [PATCH 0/26] Start removing non-generic boards Masahiro Yamada
2014-12-15 14:26 ` [U-Boot] [PATCH 01/26] mpc8xx: remove FPS{850, 860}L, NSCU, SM850, TK885D, virtlab2 support Masahiro Yamada
@ 2014-12-15 14:26 ` Masahiro Yamada
2015-01-05 18:20 ` Tom Rini
2014-12-15 14:26 ` [U-Boot] [PATCH 03/26] mpc8xx: remove ELPT860 board support Masahiro Yamada
` (25 subsequent siblings)
27 siblings, 1 reply; 55+ messages in thread
From: Masahiro Yamada @ 2014-12-15 14:26 UTC (permalink / raw)
To: u-boot
These boards are still non-generic boards.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Stefan Roese <sr@denx.de>
---
arch/powerpc/cpu/mpc5xxx/Kconfig | 12 -
arch/powerpc/cpu/mpc5xxx/ide.c | 8 -
arch/powerpc/cpu/mpc8xx/Kconfig | 4 -
board/manroland/hmi1001/Kconfig | 12 -
board/manroland/hmi1001/MAINTAINERS | 6 -
board/manroland/hmi1001/Makefile | 8 -
board/manroland/hmi1001/hmi1001.c | 301 ----------------------
board/manroland/mucmc52/Kconfig | 12 -
board/manroland/mucmc52/MAINTAINERS | 6 -
board/manroland/mucmc52/Makefile | 11 -
board/manroland/mucmc52/mucmc52.c | 394 -----------------------------
board/manroland/uc100/Kconfig | 12 -
board/manroland/uc100/MAINTAINERS | 6 -
board/manroland/uc100/Makefile | 8 -
board/manroland/uc100/pcmcia.c | 192 --------------
board/manroland/uc100/uc100.c | 254 -------------------
board/manroland/uc101/Kconfig | 12 -
board/manroland/uc101/MAINTAINERS | 6 -
board/manroland/uc101/Makefile | 8 -
board/manroland/uc101/uc101.c | 367 ---------------------------
configs/hmi1001_defconfig | 3 -
configs/mucmc52_defconfig | 3 -
configs/uc100_defconfig | 3 -
configs/uc101_defconfig | 3 -
doc/README.scrapyard | 4 +
drivers/net/mpc5xxx_fec.c | 5 -
drivers/video/smiLynxEM.c | 3 -
include/configs/hmi1001.h | 339 -------------------------
include/configs/mucmc52.h | 126 ----------
include/configs/uc100.h | 482 ------------------------------------
include/configs/uc101.h | 103 --------
include/pcmcia.h | 2 -
32 files changed, 4 insertions(+), 2711 deletions(-)
delete mode 100644 board/manroland/hmi1001/Kconfig
delete mode 100644 board/manroland/hmi1001/MAINTAINERS
delete mode 100644 board/manroland/hmi1001/Makefile
delete mode 100644 board/manroland/hmi1001/hmi1001.c
delete mode 100644 board/manroland/mucmc52/Kconfig
delete mode 100644 board/manroland/mucmc52/MAINTAINERS
delete mode 100644 board/manroland/mucmc52/Makefile
delete mode 100644 board/manroland/mucmc52/mucmc52.c
delete mode 100644 board/manroland/uc100/Kconfig
delete mode 100644 board/manroland/uc100/MAINTAINERS
delete mode 100644 board/manroland/uc100/Makefile
delete mode 100644 board/manroland/uc100/pcmcia.c
delete mode 100644 board/manroland/uc100/uc100.c
delete mode 100644 board/manroland/uc101/Kconfig
delete mode 100644 board/manroland/uc101/MAINTAINERS
delete mode 100644 board/manroland/uc101/Makefile
delete mode 100644 board/manroland/uc101/uc101.c
delete mode 100644 configs/hmi1001_defconfig
delete mode 100644 configs/mucmc52_defconfig
delete mode 100644 configs/uc100_defconfig
delete mode 100644 configs/uc101_defconfig
delete mode 100644 include/configs/hmi1001.h
delete mode 100644 include/configs/mucmc52.h
delete mode 100644 include/configs/uc100.h
delete mode 100644 include/configs/uc101.h
diff --git a/arch/powerpc/cpu/mpc5xxx/Kconfig b/arch/powerpc/cpu/mpc5xxx/Kconfig
index bd64ea6..e2e9cb7 100644
--- a/arch/powerpc/cpu/mpc5xxx/Kconfig
+++ b/arch/powerpc/cpu/mpc5xxx/Kconfig
@@ -83,15 +83,6 @@ config TARGET_O3DNT
config TARGET_DIGSY_MTC
bool "Support digsy_mtc"
-config TARGET_HMI1001
- bool "Support hmi1001"
-
-config TARGET_MUCMC52
- bool "Support mucmc52"
-
-config TARGET_UC101
- bool "Support uc101"
-
config TARGET_PCM030
bool "Support pcm030"
@@ -124,9 +115,6 @@ source "board/inka4x0/Kconfig"
source "board/intercontrol/digsy_mtc/Kconfig"
source "board/ipek01/Kconfig"
source "board/jupiter/Kconfig"
-source "board/manroland/hmi1001/Kconfig"
-source "board/manroland/mucmc52/Kconfig"
-source "board/manroland/uc101/Kconfig"
source "board/motionpro/Kconfig"
source "board/munices/Kconfig"
source "board/phytec/pcm030/Kconfig"
diff --git a/arch/powerpc/cpu/mpc5xxx/ide.c b/arch/powerpc/cpu/mpc5xxx/ide.c
index 03cd7fd..9003b77 100644
--- a/arch/powerpc/cpu/mpc5xxx/ide.c
+++ b/arch/powerpc/cpu/mpc5xxx/ide.c
@@ -41,19 +41,11 @@ int ide_preinit (void)
/* All sample codes do that... */
*(vu_long *) MPC5XXX_ATA_SHARE_COUNT = 0;
-#if defined(CONFIG_UC101)
- /* Configure and reset host */
- *(vu_long *) MPC5XXX_ATA_HOST_CONFIG =
- MPC5xxx_ATA_HOSTCONF_SMR | MPC5xxx_ATA_HOSTCONF_FR;
- udelay (10);
- *(vu_long *) MPC5XXX_ATA_HOST_CONFIG = 0;
-#else
/* Configure and reset host */
*(vu_long *) MPC5XXX_ATA_HOST_CONFIG = MPC5xxx_ATA_HOSTCONF_IORDY |
MPC5xxx_ATA_HOSTCONF_SMR | MPC5xxx_ATA_HOSTCONF_FR;
udelay (10);
*(vu_long *) MPC5XXX_ATA_HOST_CONFIG = MPC5xxx_ATA_HOSTCONF_IORDY;
-#endif
/* Disable prefetch on Commbus */
psdma->PtdCntrl |= 1;
diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig
index 33fff0c..9eb7e17 100644
--- a/arch/powerpc/cpu/mpc8xx/Kconfig
+++ b/arch/powerpc/cpu/mpc8xx/Kconfig
@@ -46,9 +46,6 @@ config TARGET_KUP4X
config TARGET_ELPT860
bool "Support ELPT860"
-config TARGET_UC100
- bool "Support uc100"
-
config TARGET_TQM823L
bool "Support TQM823L"
@@ -96,7 +93,6 @@ source "board/ivm/Kconfig"
source "board/kup/kup4k/Kconfig"
source "board/kup/kup4x/Kconfig"
source "board/lwmon/Kconfig"
-source "board/manroland/uc100/Kconfig"
source "board/netvia/Kconfig"
source "board/r360mpi/Kconfig"
source "board/spd8xx/Kconfig"
diff --git a/board/manroland/hmi1001/Kconfig b/board/manroland/hmi1001/Kconfig
deleted file mode 100644
index 996a87f..0000000
--- a/board/manroland/hmi1001/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_HMI1001
-
-config SYS_BOARD
- default "hmi1001"
-
-config SYS_VENDOR
- default "manroland"
-
-config SYS_CONFIG_NAME
- default "hmi1001"
-
-endif
diff --git a/board/manroland/hmi1001/MAINTAINERS b/board/manroland/hmi1001/MAINTAINERS
deleted file mode 100644
index a66a981..0000000
--- a/board/manroland/hmi1001/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-HMI1001 BOARD
-#M: -
-S: Maintained
-F: board/manroland/hmi1001/
-F: include/configs/hmi1001.h
-F: configs/hmi1001_defconfig
diff --git a/board/manroland/hmi1001/Makefile b/board/manroland/hmi1001/Makefile
deleted file mode 100644
index c29a665..0000000
--- a/board/manroland/hmi1001/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := hmi1001.o
diff --git a/board/manroland/hmi1001/hmi1001.c b/board/manroland/hmi1001/hmi1001.c
deleted file mode 100644
index 64bdd8f..0000000
--- a/board/manroland/hmi1001/hmi1001.c
+++ /dev/null
@@ -1,301 +0,0 @@
-/*
- * (C) Copyright 2003-2008
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas at motorola.com.
- *
- * (C) Copyright 2004
- * Martin Krause, TQ-Systems GmbH, martin.krause at tqs.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <malloc.h>
-
-#ifndef CONFIG_SYS_RAMBOOT
-static void sdram_start (int hi_addr)
-{
- long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
- /* unlock mode register */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* precharge all banks */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
- __asm__ volatile ("sync");
-
-#if SDRAM_DDR
- /* set mode register: extended mode */
- *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
- __asm__ volatile ("sync");
-
- /* set mode register: reset DLL */
- *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
- __asm__ volatile ("sync");
-#endif
-
- /* precharge all banks */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* auto refresh */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* set mode register */
- *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
- __asm__ volatile ("sync");
-
- /* normal operation */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
- __asm__ volatile ("sync");
-}
-#endif
-
-/*
- * ATTENTION: Although partially referenced initdram does NOT make real use
- * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
- * is something else than 0x00000000.
- */
-
-phys_size_t initdram (int board_type)
-{
- ulong dramsize = 0;
-#ifndef CONFIG_SYS_RAMBOOT
- ulong test1, test2;
- uint svr, pvr;
-
- /* setup SDRAM chip selects */
- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
- __asm__ volatile ("sync");
-
- /* setup config registers */
- *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
- *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
- __asm__ volatile ("sync");
-
-#if SDRAM_DDR
- /* set tap delay */
- *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
- __asm__ volatile ("sync");
-#endif
-
- /* find RAM size using SDRAM CS0 only */
- sdram_start(0);
- test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
- sdram_start(1);
- test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
- if (test1 > test2) {
- sdram_start(0);
- dramsize = test1;
- } else {
- dramsize = test2;
- }
-
- /* memory smaller than 1MB is impossible */
- if (dramsize < (1 << 20)) {
- dramsize = 0;
- }
-
- /* set SDRAM CS0 size according to the amount of RAM found */
- if (dramsize > 0) {
- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
- __builtin_ffs(dramsize >> 20) - 1;
- } else {
- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
- }
-
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
-#else /* CONFIG_SYS_RAMBOOT */
-
- /* retrieve size of memory connected to SDRAM CS0 */
- dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
- if (dramsize >= 0x13) {
- dramsize = (1 << (dramsize - 0x13)) << 20;
- } else {
- dramsize = 0;
- }
-
- /* retrieve size of memory connected to SDRAM CS1 */
- dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
- if (dramsize2 >= 0x13) {
- dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
- } else {
- dramsize2 = 0;
- }
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
- /*
- * On MPC5200B we need to set the special configuration delay in the
- * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
- * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
- *
- * "The SDelay should be written to a value of 0x00000004. It is
- * required to account for changes caused by normal wafer processing
- * parameters."
- */
- svr = get_svr();
- pvr = get_pvr();
- if ((SVR_MJREV(svr) >= 2) &&
- (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
-
- *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
- __asm__ volatile ("sync");
- }
-
-/* return dramsize + dramsize2; */
- return dramsize;
-}
-
-int checkboard (void)
-{
- puts ("Board: HMI1001\n");
- return 0;
-}
-
-#ifdef CONFIG_PREBOOT
-
-static uchar kbd_magic_prefix[] = "key_magic";
-static uchar kbd_command_prefix[] = "key_cmd";
-
-#define S1_ROT 0xf0
-#define S2_Q 0x40
-#define S2_M 0x20
-
-struct kbd_data_t {
- char s1;
- char s2;
-};
-
-struct kbd_data_t* get_keys (struct kbd_data_t *kbd_data)
-{
- kbd_data->s1 = *((volatile uchar*)(CONFIG_SYS_STATUS1_BASE));
- kbd_data->s2 = *((volatile uchar*)(CONFIG_SYS_STATUS2_BASE));
-
- return kbd_data;
-}
-
-static int compare_magic (const struct kbd_data_t *kbd_data, char *str)
-{
- char s1 = str[0];
- char s2;
-
- if (s1 >= '0' && s1 <= '9')
- s1 -= '0';
- else if (s1 >= 'a' && s1 <= 'f')
- s1 = s1 - 'a' + 10;
- else if (s1 >= 'A' && s1 <= 'F')
- s1 = s1 - 'A' + 10;
- else
- return -1;
-
- if (((S1_ROT & kbd_data->s1) >> 4) != s1)
- return -1;
-
- s2 = (S2_Q | S2_M) & kbd_data->s2;
-
- switch (str[1]) {
- case 'q':
- case 'Q':
- if (s2 == S2_Q)
- return -1;
- break;
- case 'm':
- case 'M':
- if (s2 == S2_M)
- return -1;
- break;
- case '\0':
- if (s2 == (S2_Q | S2_M))
- return 0;
- default:
- return -1;
- }
-
- if (str[2])
- return -1;
-
- return 0;
-}
-
-static char *key_match (const struct kbd_data_t *kbd_data)
-{
- char magic[sizeof (kbd_magic_prefix) + 1];
- char *suffix;
- char *kbd_magic_keys;
-
- /*
- * The following string defines the characters that can be appended
- * to "key_magic" to form the names of environment variables that
- * hold "magic" key codes, i. e. such key codes that can cause
- * pre-boot actions. If the string is empty (""), then only
- * "key_magic" is checked (old behaviour); the string "125" causes
- * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
- */
- if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
- kbd_magic_keys = "";
-
- /* loop over all magic keys;
- * use '\0' suffix in case of empty string
- */
- for (suffix = kbd_magic_keys; *suffix ||
- suffix == kbd_magic_keys; ++suffix) {
- sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
-
- if (compare_magic(kbd_data, getenv(magic)) == 0) {
- char cmd_name[sizeof (kbd_command_prefix) + 1];
- char *cmd;
-
- sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
- cmd = getenv (cmd_name);
-
- return (cmd);
- }
- }
-
- return (NULL);
-}
-
-#endif /* CONFIG_PREBOOT */
-
-int misc_init_r (void)
-{
-#ifdef CONFIG_PREBOOT
- struct kbd_data_t kbd_data;
- /* Decode keys */
- char *str = strdup (key_match (get_keys (&kbd_data)));
- /* Set or delete definition */
- setenv ("preboot", str);
- free (str);
-#endif /* CONFIG_PREBOOT */
-
- return 0;
-}
-
-int board_early_init_r (void)
-{
- *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
- *(vu_long *)MPC5XXX_BOOTCS_START =
- *(vu_long *)MPC5XXX_CS0_START = START_REG(CONFIG_SYS_FLASH_BASE);
- *(vu_long *)MPC5XXX_BOOTCS_STOP =
- *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE);
- return 0;
-}
-#ifdef CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
- pci_mpc5xxx_init(&hose);
-}
-#endif
diff --git a/board/manroland/mucmc52/Kconfig b/board/manroland/mucmc52/Kconfig
deleted file mode 100644
index a033610..0000000
--- a/board/manroland/mucmc52/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MUCMC52
-
-config SYS_BOARD
- default "mucmc52"
-
-config SYS_VENDOR
- default "manroland"
-
-config SYS_CONFIG_NAME
- default "mucmc52"
-
-endif
diff --git a/board/manroland/mucmc52/MAINTAINERS b/board/manroland/mucmc52/MAINTAINERS
deleted file mode 100644
index 45a2764..0000000
--- a/board/manroland/mucmc52/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MUCMC52 BOARD
-M: Heiko Schocher <hs@denx.de>
-S: Maintained
-F: board/manroland/mucmc52/
-F: include/configs/mucmc52.h
-F: configs/mucmc52_defconfig
diff --git a/board/manroland/mucmc52/Makefile b/board/manroland/mucmc52/Makefile
deleted file mode 100644
index 927fc32..0000000
--- a/board/manroland/mucmc52/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2008
-# Heiko Schocher, DENX Software Engineering, hs at denx.de.
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := mucmc52.o
diff --git a/board/manroland/mucmc52/mucmc52.c b/board/manroland/mucmc52/mucmc52.c
deleted file mode 100644
index c8ed5b7..0000000
--- a/board/manroland/mucmc52/mucmc52.c
+++ /dev/null
@@ -1,394 +0,0 @@
-/*
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas at motorola.com.
- *
- * (C) Copyright 2004
- * Martin Krause, TQ-Systems GmbH, martin.krause at tqs.de
- *
- * (C) Copyright 2008
- * Heiko Schocher, DENX Software Engineering, hs at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <fdt_support.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-#include <malloc.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-
-#ifndef CONFIG_SYS_RAMBOOT
-static void sdram_start (int hi_addr)
-{
- long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
- /* unlock mode register */
- out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CTRL,
- (SDRAM_CONTROL | 0x80000000 | hi_addr_bit));
- __asm__ volatile ("sync");
-
- /* precharge all banks */
- out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CTRL,
- (SDRAM_CONTROL | 0x80000002 | hi_addr_bit));
- __asm__ volatile ("sync");
-
-#if SDRAM_DDR
- /* set mode register: extended mode */
- out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_MODE, (SDRAM_EMODE));
- __asm__ volatile ("sync");
-
- /* set mode register: reset DLL */
- out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_MODE,
- (SDRAM_MODE | 0x04000000));
- __asm__ volatile ("sync");
-#endif
-
- /* precharge all banks */
- out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CTRL,
- (SDRAM_CONTROL | 0x80000002 | hi_addr_bit));
- __asm__ volatile ("sync");
-
- /* auto refresh */
- out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CTRL,
- (SDRAM_CONTROL | 0x80000004 | hi_addr_bit));
- __asm__ volatile ("sync");
-
- /* set mode register */
- out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_MODE, (SDRAM_MODE));
- __asm__ volatile ("sync");
-
- /* normal operation */
- out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CTRL,
- (SDRAM_CONTROL | hi_addr_bit));
- __asm__ volatile ("sync");
-}
-#endif
-
-/*
- * ATTENTION: Although partially referenced initdram does NOT make real use
- * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
- * is something else than 0x00000000.
- */
-
-phys_size_t initdram (int board_type)
-{
- ulong dramsize = 0;
- ulong dramsize2 = 0;
- uint svr, pvr;
-
-#ifndef CONFIG_SYS_RAMBOOT
- ulong test1, test2;
-
- /* setup SDRAM chip selects */
- out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS0CFG, 0x0000001c); /* 512MB at 0x0 */
- out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS1CFG, 0x80000000);/* disabled */
- __asm__ volatile ("sync");
-
- /* setup config registers */
- out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
- out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
- __asm__ volatile ("sync");
-
-#if SDRAM_DDR
- /* set tap delay */
- out_be32 ((unsigned __iomem *)MPC5XXX_CDM_PORCFG, SDRAM_TAPDELAY);
- __asm__ volatile ("sync");
-#endif
-
- /* find RAM size using SDRAM CS0 only */
- sdram_start (0);
- test1 = get_ram_size ((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
- sdram_start(1);
- test2 = get_ram_size ((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
- if (test1 > test2) {
- sdram_start (0);
- dramsize = test1;
- } else {
- dramsize = test2;
- }
-
- /* memory smaller than 1MB is impossible */
- if (dramsize < (1 << 20)) {
- dramsize = 0;
- }
-
- /* set SDRAM CS0 size according to the amount of RAM found */
- if (dramsize > 0) {
- out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS0CFG,
- (0x13 + __builtin_ffs(dramsize >> 20) - 1));
- } else {
- out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */
- }
-
- /* let SDRAM CS1 start right after CS0 */
- out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS1CFG, (dramsize + 0x0000001c));/*512MB*/
-
- /* find RAM size using SDRAM CS1 only */
- if (!dramsize)
- sdram_start (0);
- test2 = test1 = get_ram_size ((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
- if (!dramsize) {
- sdram_start (1);
- test2 = get_ram_size ((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
- }
- if (test1 > test2) {
- sdram_start (0);
- dramsize2 = test1;
- } else {
- dramsize2 = test2;
- }
-
- /* memory smaller than 1MB is impossible */
- if (dramsize2 < (1 << 20)) {
- dramsize2 = 0;
- }
-
- /* set SDRAM CS1 size according to the amount of RAM found */
- if (dramsize2 > 0) {
- out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS1CFG,
- (dramsize | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1)));
- } else {
- out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS1CFG, dramsize); /* disabled */
- }
-
-#else /* CONFIG_SYS_RAMBOOT */
-
- /* retrieve size of memory connected to SDRAM CS0 */
- dramsize = in_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
- if (dramsize >= 0x13) {
- dramsize = (1 << (dramsize - 0x13)) << 20;
- } else {
- dramsize = 0;
- }
-
- /* retrieve size of memory connected to SDRAM CS1 */
- dramsize2 = in_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS1CFG) & 0xFF;
- if (dramsize2 >= 0x13) {
- dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
- } else {
- dramsize2 = 0;
- }
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
- /*
- * On MPC5200B we need to set the special configuration delay in the
- * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
- * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
- *
- * "The SDelay should be written to a value of 0x00000004. It is
- * required to account for changes caused by normal wafer processing
- * parameters."
- */
- svr = get_svr();
- pvr = get_pvr();
- if ((SVR_MJREV(svr) >= 2) &&
- (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
-
- out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_SDELAY, 0x04);
- __asm__ volatile ("sync");
- }
-
- return dramsize + dramsize2;
-}
-
-int checkboard (void)
-{
- puts ("Board: MUC.MC-52 HW WDT ");
-#if defined(CONFIG_HW_WATCHDOG)
- puts ("enabled\n");
-#else
- puts ("disabled\n");
-#endif
- return 0;
-}
-
-#ifdef CONFIG_PREBOOT
-
-static uchar kbd_magic_prefix[] = "key_magic";
-static uchar kbd_command_prefix[] = "key_cmd";
-
-#define S1_ROT 0xf0
-#define S2_Q 0x40
-#define S2_M 0x20
-
-struct kbd_data_t {
- char s1;
- char s2;
-};
-
-struct kbd_data_t* get_keys (struct kbd_data_t *kbd_data)
-{
- kbd_data->s1 = in_8 ((volatile uchar*)CONFIG_SYS_STATUS1_BASE);
- kbd_data->s2 = in_8 ((volatile uchar*)CONFIG_SYS_STATUS2_BASE);
-
- return kbd_data;
-}
-
-static int compare_magic (const struct kbd_data_t *kbd_data, char *str)
-{
- char s1 = str[0];
- char s2;
-
- if (s1 >= '0' && s1 <= '9')
- s1 -= '0';
- else if (s1 >= 'a' && s1 <= 'f')
- s1 = s1 - 'a' + 10;
- else if (s1 >= 'A' && s1 <= 'F')
- s1 = s1 - 'A' + 10;
- else
- return -1;
-
- if (((S1_ROT & kbd_data->s1) >> 4) != s1)
- return -1;
-
- s2 = (S2_Q | S2_M) & kbd_data->s2;
-
- switch (str[1]) {
- case 'q':
- case 'Q':
- if (s2 == S2_Q)
- return -1;
- break;
- case 'm':
- case 'M':
- if (s2 == S2_M)
- return -1;
- break;
- case '\0':
- if (s2 == (S2_Q | S2_M))
- return 0;
- default:
- return -1;
- }
-
- if (str[2])
- return -1;
-
- return 0;
-}
-
-static char *key_match (const struct kbd_data_t *kbd_data)
-{
- char magic[sizeof (kbd_magic_prefix) + 1];
- char *suffix;
- char *kbd_magic_keys;
-
- /*
- * The following string defines the characters that can be appended
- * to "key_magic" to form the names of environment variables that
- * hold "magic" key codes, i. e. such key codes that can cause
- * pre-boot actions. If the string is empty (""), then only
- * "key_magic" is checked (old behaviour); the string "125" causes
- * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
- */
- if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
- kbd_magic_keys = "";
-
- /* loop over all magic keys;
- * use '\0' suffix in case of empty string
- */
- for (suffix = kbd_magic_keys; *suffix ||
- suffix == kbd_magic_keys; ++suffix) {
- sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
-
- if (compare_magic(kbd_data, getenv(magic)) == 0) {
- char cmd_name[sizeof (kbd_command_prefix) + 1];
- char *cmd;
-
- sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
- cmd = getenv (cmd_name);
-
- return (cmd);
- }
- }
-
- return (NULL);
-}
-
-#endif /* CONFIG_PREBOOT */
-
-int misc_init_r (void)
-{
-#ifdef CONFIG_PREBOOT
- struct kbd_data_t kbd_data;
- /* Decode keys */
- char *str = strdup (key_match (get_keys (&kbd_data)));
- /* Set or delete definition */
- setenv ("preboot", str);
- free (str);
-#endif /* CONFIG_PREBOOT */
-
- out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x38), ' ');
- out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x39), ' ');
- out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3A), ' ');
- out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3B), ' ');
- out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3C), ' ');
- out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3D), ' ');
- out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3E), ' ');
- out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3F), ' ');
-
- return 0;
-}
-
-int board_early_init_r (void)
-{
- out_be32 ((unsigned __iomem *)MPC5XXX_BOOTCS_CFG, in_be32 ((unsigned __iomem *)MPC5XXX_BOOTCS_CFG) & ~0x1);
- out_be32 ((unsigned __iomem *)MPC5XXX_BOOTCS_START, START_REG(CONFIG_SYS_FLASH_BASE));
- out_be32 ((unsigned __iomem *)MPC5XXX_CS0_START, START_REG(CONFIG_SYS_FLASH_BASE));
- out_be32 ((unsigned __iomem *)MPC5XXX_BOOTCS_STOP,
- STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE));
- out_be32 ((unsigned __iomem *)MPC5XXX_CS0_STOP,
- STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE));
- return 0;
-}
-
-int last_stage_init (void)
-{
- out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x38), 'M');
- out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x39), 'U');
- out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3A), 'C');
- out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3B), '.');
- out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3C), 'M');
- out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3D), 'C');
- out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3E), '5');
- out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3F), '2');
-
- return 0;
-}
-
-#if defined(CONFIG_HW_WATCHDOG)
-#define GPT_OUT_0 0x00000027
-#define GPT_OUT_1 0x00000037
-void hw_watchdog_reset (void)
-{
- /* Trigger HW Watchdog with TIMER_0 */
- out_be32 ((unsigned __iomem *)MPC5XXX_GPT0_ENABLE, GPT_OUT_1);
- out_be32 ((unsigned __iomem *)MPC5XXX_GPT0_ENABLE, GPT_OUT_0);
-}
-#endif
-
-#ifdef CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init (struct pci_controller *);
-
-void pci_init_board (void)
-{
- pci_mpc5xxx_init (&hose);
-}
-#endif
-
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
-
- return 0;
-}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/manroland/uc100/Kconfig b/board/manroland/uc100/Kconfig
deleted file mode 100644
index 08f681b..0000000
--- a/board/manroland/uc100/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_UC100
-
-config SYS_BOARD
- default "uc100"
-
-config SYS_VENDOR
- default "manroland"
-
-config SYS_CONFIG_NAME
- default "uc100"
-
-endif
diff --git a/board/manroland/uc100/MAINTAINERS b/board/manroland/uc100/MAINTAINERS
deleted file mode 100644
index 260471c..0000000
--- a/board/manroland/uc100/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-UC100 BOARD
-M: Stefan Roese <sr@denx.de>
-S: Maintained
-F: board/manroland/uc100/
-F: include/configs/uc100.h
-F: configs/uc100_defconfig
diff --git a/board/manroland/uc100/Makefile b/board/manroland/uc100/Makefile
deleted file mode 100644
index 8e69c52..0000000
--- a/board/manroland/uc100/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = uc100.o pcmcia.o
diff --git a/board/manroland/uc100/pcmcia.c b/board/manroland/uc100/pcmcia.c
deleted file mode 100644
index db3821a..0000000
--- a/board/manroland/uc100/pcmcia.c
+++ /dev/null
@@ -1,192 +0,0 @@
-#include <common.h>
-#include <mpc8xx.h>
-#include <pcmcia.h>
-
-#undef CONFIG_PCMCIA
-
-#if defined(CONFIG_CMD_PCMCIA)
-#define CONFIG_PCMCIA
-#endif
-
-#if (defined(CONFIG_CMD_IDE)) && defined(CONFIG_IDE_8xx_PCCARD)
-#define CONFIG_PCMCIA
-#endif
-
-#ifdef CONFIG_PCMCIA
-
-#define PCMCIA_BOARD_MSG "UC100"
-
-/*
- * Remark: don't turn off OE "__MY_PCMCIA_GCRX_CXOE" on UC100 board.
- * This leads to board-hangup! (sr, 8 Dez. 2004)
- */
-static void cfg_ports (void)
-{
- volatile immap_t *immap;
-
- immap = (immap_t *)CONFIG_SYS_IMMR;
-
- /*
- * Configure Port A for MAX1602 PC-Card Power-Interface Switch
- */
- immap->im_ioport.iop_padat &= ~0x8000; /* set port x output to low */
- immap->im_ioport.iop_padir |= 0x8000; /* enable port x as output */
-
- debug ("Set Port A: PAR: %08x DIR: %08x DAT: %08x\n",
- immap->im_ioport.iop_papar, immap->im_ioport.iop_padir,
- immap->im_ioport.iop_padat);
-}
-
-int pcmcia_hardware_enable(int slot)
-{
- volatile immap_t *immap;
- volatile pcmconf8xx_t *pcmp;
- volatile sysconf8xx_t *sysp;
- uint reg, mask;
-
- debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
-
- udelay(10000);
-
- immap = (immap_t *)CONFIG_SYS_IMMR;
- sysp = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf));
- pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
-
- /* Configure Ports for TPS2211A PC-Card Power-Interface Switch */
- cfg_ports ();
-
- /*
- * Configure SIUMCR to enable PCMCIA port B
- * (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
- */
- sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */
-
- /* clear interrupt state, and disable interrupts */
- pcmp->pcmc_pscr = PCMCIA_MASK(_slot_);
- pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
-
- /*
- * Disable interrupts, DMA, and PCMCIA buffers
- * (isolate the interface) and assert RESET signal
- */
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = 0;
- reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
- PCMCIA_PGCRX(_slot_) = reg;
- udelay(500);
-
- /*
- * Make sure there is a card in the slot, then configure the interface.
- */
- udelay(10000);
- debug ("[%d] %s: PIPR(%p)=0x%x\n",
- __LINE__,__FUNCTION__,
- &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
- if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
- printf (" No Card found\n");
- return (1);
- }
-
- /*
- * Power On.
- */
- mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
- reg = pcmp->pcmc_pipr;
- debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
- reg,
- (reg&PCMCIA_VS1(slot))?"n":"ff",
- (reg&PCMCIA_VS2(slot))?"n":"ff");
-
- if ((reg & mask) == mask)
- puts (" 5.0V card found: ");
- else
- puts (" 3.3V card found: ");
-
- /* switch VCC on */
- immap->im_ioport.iop_padat |= 0x8000; /* power enable 3.3V */
-
- udelay(10000);
-
- debug ("Enable PCMCIA buffers and stop RESET\n");
- reg = PCMCIA_PGCRX(_slot_);
- reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
-
- udelay(250000); /* some cards need >150 ms to come up :-( */
-
- debug ("# hardware_enable done\n");
-
- return (0);
-}
-
-
-#if defined(CONFIG_CMD_PCMCIA)
-int pcmcia_hardware_disable(int slot)
-{
- volatile immap_t *immap;
- volatile cpm8xx_t *cp;
- volatile pcmconf8xx_t *pcmp;
- u_long reg;
-
- debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
-
- immap = (immap_t *)CONFIG_SYS_IMMR;
- pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
-
- /* switch VCC off */
- immap->im_ioport.iop_padat &= ~0x8000; /* power disable 3.3V */
-
- /* Configure PCMCIA General Control Register */
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = 0;
- reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
- PCMCIA_PGCRX(_slot_) = reg;
-
- udelay(10000);
-
- return (0);
-}
-#endif
-
-
-int pcmcia_voltage_set(int slot, int vcc, int vpp)
-{
- u_long reg;
-
- debug ("voltage_set: "
- PCMCIA_BOARD_MSG
- " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
- 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
-
- /*
- * Disable PCMCIA buffers (isolate the interface)
- * and assert RESET signal
- */
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = PCMCIA_PGCRX(_slot_);
- reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
- PCMCIA_PGCRX(_slot_) = reg;
- udelay(500);
-
- /*
- * Configure Port C pins for
- * 5 Volts Enable and 3 Volts enable,
- * Turn all power pins to Hi-Z
- */
- debug ("PCMCIA power OFF\n");
- cfg_ports (); /* Enables switch, but all in Hi-Z */
-
- debug ("Enable PCMCIA buffers and stop RESET\n");
- reg = PCMCIA_PGCRX(_slot_);
- reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
- udelay(500);
-
- debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
- slot+'A');
- return (0);
-}
-
-#endif /* CONFIG_PCMCIA */
diff --git a/board/manroland/uc100/uc100.c b/board/manroland/uc100/uc100.c
deleted file mode 100644
index 31f08dd..0000000
--- a/board/manroland/uc100/uc100.c
+++ /dev/null
@@ -1,254 +0,0 @@
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#if 0
-#define DEBUG
-#endif
-
-#include <common.h>
-#include <mpc8xx.h>
-#include <i2c.h>
-#include <miiphy.h>
-
-int fec8xx_miiphy_write(char *devname, unsigned char addr,
- unsigned char reg, unsigned short value);
-
-/*********************************************************************/
-/* UPMA Pre Initilization Table by WV (Miron MT48LC16M16A2-7E B) */
-/*********************************************************************/
-const uint sdram_init_upm_table[] = {
- /* SDRAM Initialisation Sequence (offset 0 in UPMA RAM) WV */
- /* NOP - Precharge - AutoRefr - NOP - NOP */
- /* NOP - AutoRefr - NOP */
- /* NOP - NOP - LoadModeR - NOP - Active */
- /* Position of Single Read */
- 0x0ffffc04, 0x0ff77c04, 0x0ff5fc04, 0x0ffffc04, 0x0ffffc04,
- 0x0ffffc04, 0x0ff5fc04, 0x0ffffc04,
-
- /* Burst Read. (offset 8 in UPMA RAM) */
- /* Cycle lent for Initialisation WV */
- 0x0ffffc04, 0x0ffffc34, 0x0f057c34, 0x0ffffc30, 0x1ff7fc05,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-
- /* Single Write. (offset 18 in UPMA RAM) */
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-
- /* Burst Write. (offset 20 in UPMA RAM) */
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-
- /* Refresh (offset 30 in UPMA RAM) */
- 0x0FF77C04, 0x0FFFFC04, 0x0FF5FC84, 0x0FFFFC04, 0x0FFFFC04,
- 0x0FFFFC84, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF,
-
- /* Exception. (offset 3c in UPMA RAM) */
- 0x7FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-};
-
-/*********************************************************************/
-/* UPMA initilization table. */
-/*********************************************************************/
-const uint sdram_upm_table[] = {
- /* single read. (offset 0 in UPMA RAM) */
- 0x0F07FC04, 0x0FFFFC04, 0x00BDFC04, 0x0FF77C00, 0x1FFFFC05,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, /* 0x05-0x07 new WV */
-
- /* Burst Read. (offset 8 in UPMA RAM) */
- 0x0F07FC04, 0x0FFFFC04, 0x00BDFC04, 0x00FFFC00, 0x00FFFC00,
- 0x00FFFC00, 0x0FF77C00, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-
- /* Single Write. (offset 18 in UPMA RAM) */
- 0x0F07FC04, 0x0FFFFC00, 0x00BD7C04, 0x0FFFFC04, 0x0FF77C04,
- 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF,
-
- /* Burst Write. (offset 20 in UPMA RAM) */
- 0x0F07FC04, 0x0FFFFC00, 0x00BD7C00, 0x00FFFC00, 0x00FFFC00,
- 0x00FFFC04, 0x0FFFFC04, 0x0FF77C04, 0x1FFFFC05, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-
- /* Refresh (offset 30 in UPMA RAM) */
- 0x0FF77C04, 0x0FFFFC04, 0x0FF5FC84, 0x0FFFFC04, 0x0FFFFC04,
- 0x0FFFFC84, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF,
-
- /* Exception. (offset 3c in UPMA RAM) */
- 0x7FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, /* 0x3C new WV */
-};
-
-/*********************************************************************/
-/* UPMB initilization table. */
-/*********************************************************************/
-const uint mpm_upm_table[] = {
- /* single read. (offset 0 in upm RAM) */
- 0x8FF00004, 0x0FF00004, 0x0FF81004, 0x1FF00001,
- 0x1FF00001, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-
- /* burst read. (Offset 8 in upm RAM) */
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-
- /* single write. (Offset 0x18 in upm RAM) */
- 0x8FF00004, 0x0FF00004, 0x0FF81004, 0x0FF00004,
- 0x0FF00004, 0x1FF00001, 0xFFFFFFFF, 0xFFFFFFFF,
-
- /* burst write. (Offset 0x20 in upm RAM) */
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-
- /* Refresh cycle, offset 0x30 */
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-
- /* Exception, 0ffset 0x3C */
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-};
-
-
-int board_switch(void)
-{
- volatile pcmconf8xx_t *pcmp;
-
- pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
-
- return ((pcmp->pcmc_pipr >> 24) & 0xf);
-}
-
-
-/*
- * Check Board Identity:
- */
-int checkboard (void)
-{
- char str[64];
- int i = getenv_f("serial#", str, sizeof(str));
-
- puts ("Board: ");
-
- if (i == -1) {
- puts ("### No HW ID - assuming UC100");
- } else {
- puts(str);
- }
-
- printf (" (SWITCH=%1X)\n", board_switch());
-
- return 0;
-}
-
-
-/*
- * Initialize SDRAM
- */
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
- /*---------------------------------------------------------------------*/
- /* Initialize the UPMA/UPMB registers with the appropriate table. */
- /*---------------------------------------------------------------------*/
- upmconfig (UPMA, (uint *) sdram_init_upm_table,
- sizeof (sdram_init_upm_table) / sizeof (uint));
- upmconfig (UPMB, (uint *) mpm_upm_table,
- sizeof (mpm_upm_table) / sizeof (uint));
-
- /*---------------------------------------------------------------------*/
- /* Memory Periodic Timer Prescaler: divide by 16 */
- /*---------------------------------------------------------------------*/
- memctl->memc_mptpr = 0x0200; /* Divide by 32 WV */
-
- memctl->memc_mamr = CONFIG_SYS_MAMR_VAL & 0xFF7FFFFF; /* Bit 8 := "0" Kein Refresh WV */
- memctl->memc_mbmr = CONFIG_SYS_MBMR_VAL;
-
- /*---------------------------------------------------------------------*/
- /* Initialize the Memory Controller registers, MPTPR, Chip Select 1 */
- /* for SDRAM */
- /* */
- /* NOTE: The refresh rate in MAMR reg is set according to the lowest */
- /* clock rate (16.67MHz) to allow proper operation for all ADS */
- /* clock frequencies. */
- /*---------------------------------------------------------------------*/
- memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
- memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
-
- /*-------------------------------------------------------------------*/
- /* Wait at least 200 usec for DRAM to stabilize, this magic number */
- /* obtained from the init code. */
- /*-------------------------------------------------------------------*/
- udelay(200);
-
- memctl->memc_mamr = (memctl->memc_mamr | 0x04) & ~0x08;
-
- memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
- memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
-
- /*---------------------------------------------------------------------*/
- /* run MRS command in location 5-8 of UPMB. */
- /*---------------------------------------------------------------------*/
- memctl->memc_mar = 0x88;
- /* RUN UPMA on CS1 1-time from UPMA addr 0x05 */
-
- memctl->memc_mcr = 0x80002100;
- /* RUN UPMA on CS1 1-time from UPMA addr 0x00 WV */
-
- udelay(200);
-
- /*---------------------------------------------------------------------*/
- /* Initialisation for normal access WV */
- /*---------------------------------------------------------------------*/
-
- /*---------------------------------------------------------------------*/
- /* Initialize the UPMA register with the appropriate table. */
- /*---------------------------------------------------------------------*/
- upmconfig (UPMA, (uint *) sdram_upm_table,
- sizeof (sdram_upm_table) / sizeof (uint));
-
- /*---------------------------------------------------------------------*/
- /* rerstore MBMR value (4-beat refresh burst.) */
- /*---------------------------------------------------------------------*/
- memctl->memc_mamr = CONFIG_SYS_MAMR_VAL | 0x00800000; /* Bit 8 := "1" Refresh Enable WV */
-
- udelay(200);
-
- return (64 * 1024 * 1024); /* fixed setup for 64MBytes! */
-}
-
-
-int misc_init_r (void)
-{
- uchar val;
-
- /*
- * Make sure that RTC has clock output enabled (triggers watchdog!)
- */
- val = i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, 0x0D);
- val |= 0x80;
- i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, 0x0D, val);
-
- /*
- * Configure PHY to setup LED's correctly and use 100MBit, FD
- */
- mii_init();
-
- /* disable auto-negotiation, 100mbit, full-duplex */
- fec8xx_miiphy_write(NULL, 0, MII_BMCR, 0x2100);
-
- /* set LED's to Link, Transmit, Receive */
- fec8xx_miiphy_write(NULL, 0, MII_NWAYTEST, 0x4122);
-
- return 0;
-}
diff --git a/board/manroland/uc101/Kconfig b/board/manroland/uc101/Kconfig
deleted file mode 100644
index c285b22..0000000
--- a/board/manroland/uc101/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_UC101
-
-config SYS_BOARD
- default "uc101"
-
-config SYS_VENDOR
- default "manroland"
-
-config SYS_CONFIG_NAME
- default "uc101"
-
-endif
diff --git a/board/manroland/uc101/MAINTAINERS b/board/manroland/uc101/MAINTAINERS
deleted file mode 100644
index 0fc7b85..0000000
--- a/board/manroland/uc101/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-UC101 BOARD
-M: Heiko Schocher <hs@denx.de>
-S: Maintained
-F: board/manroland/uc101/
-F: include/configs/uc101.h
-F: configs/uc101_defconfig
diff --git a/board/manroland/uc101/Makefile b/board/manroland/uc101/Makefile
deleted file mode 100644
index 9289d91..0000000
--- a/board/manroland/uc101/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := uc101.o
diff --git a/board/manroland/uc101/uc101.c b/board/manroland/uc101/uc101.c
deleted file mode 100644
index e794c46..0000000
--- a/board/manroland/uc101/uc101.c
+++ /dev/null
@@ -1,367 +0,0 @@
-/*
- * (C) Copyright 2006
- * Heiko Schocher, DENX Software Engineering, hs at denx.de.
- *
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas at motorola.com.
- *
- * (C) Copyright 2004
- * Martin Krause, TQ-Systems GmbH, martin.krause at tqs.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <fdt_support.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-#include <malloc.h>
-
-/* some SIMPLE GPIO Pins */
-#define GPIO_USB_8 (31-12)
-#define GPIO_USB_7 (31-13)
-#define GPIO_USB_6 (31-14)
-#define GPIO_USB_0 (31-15)
-#define GPIO_PSC3_7 (31-18)
-#define GPIO_PSC3_6 (31-19)
-#define GPIO_PSC3_1 (31-22)
-#define GPIO_PSC3_0 (31-23)
-
-/* some simple Interrupt GPIO Pins */
-#define GPIO_PSC3_8 2
-#define GPIO_USB1_9 3
-
-#define GPT_OUT_0 0x00000027
-#define GPT_OUT_1 0x00000037
-#define GPT_DISABLE 0x00000000 /* GPT pin disabled */
-
-#define GP_SIMP_ENABLE_O(n, v) {pgpio->simple_dvo |= (v << n); \
- pgpio->simple_ddr |= (1 << n); \
- pgpio->simple_gpioe |= (1 << n); \
- }
-
-#define GP_SIMP_ENABLE_I(n) { pgpio->simple_ddr |= ~(1 << n); \
- pgpio->simple_gpioe |= (1 << n); \
- }
-
-#define GP_SIMP_SET_O(n, v) (pgpio->simple_dvo = v ? \
- (pgpio->simple_dvo | (1 << n)) : \
- (pgpio->simple_dvo & ~(1 << n)) )
-
-#define GP_SIMP_GET_O(n) ((pgpio->simple_dvo >> n) & 1)
-#define GP_SIMP_GET_I(n) ((pgpio->simple_ival >> n) & 1)
-
-#define GP_SINT_SET_O(n, v) (pgpio->sint_dvo = v ? \
- (pgpio->sint_dvo | (1 << n)) : \
- (pgpio->sint_dvo & ~(1 << n)) )
-
-#define GP_SINT_ENABLE_O(n, v) {pgpio->sint_ode &= ~(1 << n); \
- pgpio->sint_ddr |= (1 << n); \
- GP_SINT_SET_O(n, v); \
- pgpio->sint_gpioe |= (1 << n); \
- }
-
-#define GP_SINT_ENABLE_I(n) { pgpio->sint_ddr |= ~(1 << n); \
- pgpio->sint_gpioe |= (1 << n); \
- }
-
-#define GP_SINT_GET_O(n) ((pgpio->sint_ival >> n) & 1)
-#define GP_SINT_GET_I(n) ((pgpio-ntt_ival >> n) & 1)
-
-#define GP_TIMER_ENABLE_O(n, v) ( \
- ((volatile struct mpc5xxx_gpt *)(MPC5XXX_GPT + n))->emsr = v ? \
- GPT_OUT_1 : \
- GPT_OUT_0 )
-
-#define GP_TIMER_SET_O(n, v) GP_TIMER_ENABLE_O(n, v)
-
-#define GP_TIMER_GET_O(n, v) ( \
- (((volatile struct mpc5xxx_gpt *)(MPC5XXX_GPT + n))->emsr & 0x10) >> 4)
-
-#define GP_TIMER_GET_I(n, v) ( \
- (((volatile struct mpc5xxx_gpt *)(MPC5XXX_GPT + n))->sr & 0x100) >> 8)
-
-#ifndef CONFIG_SYS_RAMBOOT
-static void sdram_start (int hi_addr)
-{
- long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
- /* unlock mode register */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* precharge all banks */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
- __asm__ volatile ("sync");
-
-#if SDRAM_DDR
- /* set mode register: extended mode */
- *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
- __asm__ volatile ("sync");
-
- /* set mode register: reset DLL */
- *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
- __asm__ volatile ("sync");
-#endif
-
- /* precharge all banks */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* auto refresh */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* set mode register */
- *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
- __asm__ volatile ("sync");
-
- /* normal operation */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
- __asm__ volatile ("sync");
-}
-#endif
-
-/*
- * ATTENTION: Although partially referenced initdram does NOT make real use
- * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
- * is something else than 0x00000000.
- */
-
-phys_size_t initdram (int board_type)
-{
- ulong dramsize = 0;
-#ifndef CONFIG_SYS_RAMBOOT
- ulong test1, test2;
-
- /* setup SDRAM chip selects */
- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
- __asm__ volatile ("sync");
-
- /* setup config registers */
- *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
- *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
- __asm__ volatile ("sync");
-
-#if SDRAM_DDR
- /* set tap delay */
- *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
- __asm__ volatile ("sync");
-#endif
-
- /* find RAM size using SDRAM CS0 only */
- sdram_start(0);
- test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
- sdram_start(1);
- test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
- if (test1 > test2) {
- sdram_start(0);
- dramsize = test1;
- } else {
- dramsize = test2;
- }
-
- /* memory smaller than 1MB is impossible */
- if (dramsize < (1 << 20)) {
- dramsize = 0;
- }
-
- /* set SDRAM CS0 size according to the amount of RAM found */
- if (dramsize > 0) {
- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
- __builtin_ffs(dramsize >> 20) - 1;
- } else {
- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
- }
-
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
-#else /* CONFIG_SYS_RAMBOOT */
-
- /* retrieve size of memory connected to SDRAM CS0 */
- dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
- if (dramsize >= 0x13) {
- dramsize = (1 << (dramsize - 0x13)) << 20;
- } else {
- dramsize = 0;
- }
-
- /* retrieve size of memory connected to SDRAM CS1 */
- dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
- if (dramsize2 >= 0x13) {
- dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
- } else {
- dramsize2 = 0;
- }
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-/* return dramsize + dramsize2; */
- return dramsize;
-}
-
-int checkboard (void)
-{
- puts ("Board: MAN UC101\n");
- /* clear the Display */
- *(char *)(CONFIG_SYS_DISP_CWORD) = 0x80;
- return 0;
-}
-
-static void init_ports (void)
-{
- volatile struct mpc5xxx_gpio *pgpio =
- (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
-
- GP_SIMP_ENABLE_I(GPIO_USB_8); /* HEX Bit 3 */
- GP_SIMP_ENABLE_I(GPIO_USB_7); /* HEX Bit 2 */
- GP_SIMP_ENABLE_I(GPIO_USB_6); /* HEX Bit 1 */
- GP_SIMP_ENABLE_I(GPIO_USB_0); /* HEX Bit 0 */
- GP_SIMP_ENABLE_I(GPIO_PSC3_0); /* Switch Menue A */
- GP_SIMP_ENABLE_I(GPIO_PSC3_1); /* Switch Menue B */
- GP_SIMP_ENABLE_I(GPIO_PSC3_6); /* Switch Cold_Warm */
- GP_SIMP_ENABLE_I(GPIO_PSC3_7); /* Switch Restart */
- GP_SINT_ENABLE_O(GPIO_PSC3_8, 0); /* LED H2 */
- GP_SINT_ENABLE_O(GPIO_USB1_9, 0); /* LED H3 */
- GP_TIMER_ENABLE_O(4, 0); /* LED H4 */
- GP_TIMER_ENABLE_O(5, 0); /* LED H5 */
- GP_TIMER_ENABLE_O(3, 0); /* LED HB */
- GP_TIMER_ENABLE_O(1, 0); /* RES_COLDSTART */
-}
-
-#ifdef CONFIG_PREBOOT
-
-static uchar kbd_magic_prefix[] = "key_magic";
-static uchar kbd_command_prefix[] = "key_cmd";
-
-struct kbd_data_t {
- char s1;
-};
-
-struct kbd_data_t* get_keys (struct kbd_data_t *kbd_data)
-{
- volatile struct mpc5xxx_gpio *pgpio =
- (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
-
- kbd_data->s1 = GP_SIMP_GET_I(GPIO_USB_8) << 3 | \
- GP_SIMP_GET_I(GPIO_USB_7) << 2 | \
- GP_SIMP_GET_I(GPIO_USB_6) << 1 | \
- GP_SIMP_GET_I(GPIO_USB_0) << 0;
- return kbd_data;
-}
-
-static int compare_magic (const struct kbd_data_t *kbd_data, char *str)
-{
- char s1 = str[0];
-
- if (s1 >= '0' && s1 <= '9')
- s1 -= '0';
- else if (s1 >= 'a' && s1 <= 'f')
- s1 = s1 - 'a' + 10;
- else if (s1 >= 'A' && s1 <= 'F')
- s1 = s1 - 'A' + 10;
- else
- return -1;
-
- if (s1 != kbd_data->s1) return -1;
- return 0;
-}
-
-static char *key_match (const struct kbd_data_t *kbd_data)
-{
- char magic[sizeof (kbd_magic_prefix) + 1];
- char *suffix;
- char *kbd_magic_keys;
-
- /*
- * The following string defines the characters that can be appended
- * to "key_magic" to form the names of environment variables that
- * hold "magic" key codes, i. e. such key codes that can cause
- * pre-boot actions. If the string is empty (""), then only
- * "key_magic" is checked (old behaviour); the string "125" causes
- * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
- */
- if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
- kbd_magic_keys = "";
-
- /* loop over all magic keys;
- * use '\0' suffix in case of empty string
- */
- for (suffix = kbd_magic_keys; *suffix ||
- suffix == kbd_magic_keys; ++suffix) {
- sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
-
- if (compare_magic(kbd_data, getenv(magic)) == 0) {
- char cmd_name[sizeof (kbd_command_prefix) + 1];
- char *cmd;
-
- sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
- cmd = getenv (cmd_name);
-
- return (cmd);
- }
- }
-
- return (NULL);
-}
-
-#endif /* CONFIG_PREBOOT */
-
-int misc_init_r (void)
-{
- /* Init the I/O ports */
- init_ports ();
-
-#ifdef CONFIG_PREBOOT
- struct kbd_data_t kbd_data;
- /* Decode keys */
- char *str = strdup (key_match (get_keys (&kbd_data)));
- /* Set or delete definition */
- setenv ("preboot", str);
- free (str);
-#endif /* CONFIG_PREBOOT */
- return 0;
-}
-
-int board_early_init_r (void)
-{
- *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
- *(vu_long *)MPC5XXX_BOOTCS_START =
- *(vu_long *)MPC5XXX_CS0_START = START_REG(CONFIG_SYS_FLASH_BASE);
- *(vu_long *)MPC5XXX_BOOTCS_STOP =
- *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE);
- /* Interbus enable it here ?? */
- *(vu_long *)MPC5XXX_GPT6_ENABLE = GPT_OUT_1;
- return 0;
-}
-#ifdef CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
- pci_mpc5xxx_init(&hose);
-}
-#endif
-
-#if defined(CONFIG_HW_WATCHDOG)
-void hw_watchdog_reset(void)
-{
- /* Trigger HW Watchdog with TIMER_0 */
- *(vu_long *)MPC5XXX_GPT0_ENABLE = GPT_OUT_1;
- *(vu_long *)MPC5XXX_GPT0_ENABLE = GPT_OUT_0;
-}
-#endif
-
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
-
- return 0;
-}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/configs/hmi1001_defconfig b/configs/hmi1001_defconfig
deleted file mode 100644
index a351dbe..0000000
--- a/configs/hmi1001_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_HMI1001=y
diff --git a/configs/mucmc52_defconfig b/configs/mucmc52_defconfig
deleted file mode 100644
index 1e49695..0000000
--- a/configs/mucmc52_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_MUCMC52=y
diff --git a/configs/uc100_defconfig b/configs/uc100_defconfig
deleted file mode 100644
index 76eeb11..0000000
--- a/configs/uc100_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_8xx=y
-CONFIG_TARGET_UC100=y
diff --git a/configs/uc101_defconfig b/configs/uc101_defconfig
deleted file mode 100644
index b365bff..0000000
--- a/configs/uc101_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_UC101=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 3cf32e7..8bd7056 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,10 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+hmi1001 powerpc mpc5xxx - -
+mucmc52 powerpc mpc5xxx - - Heiko Schocher <hs@denx.de>
+uc101 powerpc mpc5xxx - - Heiko Schocher <hs@denx.de>
+uc100 powerpc mpc8xx - - Stefan Roese <sr@denx.de>
FPS850L powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
FPS860L powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
NSCU powerpc mpc8xx - -
diff --git a/drivers/net/mpc5xxx_fec.c b/drivers/net/mpc5xxx_fec.c
index 1093ba5..d9d6f4f 100644
--- a/drivers/net/mpc5xxx_fec.c
+++ b/drivers/net/mpc5xxx_fec.c
@@ -476,11 +476,6 @@ static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis)
miiphy_write(dev->name, phyAddr, 0x0, 0x8000);
udelay(1000);
-#if defined(CONFIG_UC101) || defined(CONFIG_MUCMC52)
- /* Set the LED configuration Register for the UC101
- and MUCMC52 Board */
- miiphy_write(dev->name, phyAddr, 0x14, 0x4122);
-#endif
if (fec->xcv_type == MII10) {
/*
* Force 10Base-T, FDX operation
diff --git a/drivers/video/smiLynxEM.c b/drivers/video/smiLynxEM.c
index 614bcb3..1880ccc 100644
--- a/drivers/video/smiLynxEM.c
+++ b/drivers/video/smiLynxEM.c
@@ -131,9 +131,6 @@ static char SMI_PCR [] = {
};
static char SMI_MCR[] = {
0x60, 0x01, 0x61, 0x00,
-#ifdef CONFIG_HMI1001
- 0x62, 0x74, /* Memory type is not configured by pins on HMI1001 */
-#endif
};
static char SMI_HCR[] = {
diff --git a/include/configs/hmi1001.h b/include/configs/hmi1001.h
deleted file mode 100644
index a1a88b5..0000000
--- a/include/configs/hmi1001.h
+++ /dev/null
@@ -1,339 +0,0 @@
-/*
- * (C) Copyright 2003-2005
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
-#define CONFIG_HMI1001 1 /* HMI1001 board */
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xFFF00000
-#endif
-
-#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
-
-#define CONFIG_BOARD_EARLY_INIT_R
-
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
-#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/* Partitions */
-#define CONFIG_DOS_PARTITION
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DISPLAY
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_SNTP
-
-
-#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
-
-#if (CONFIG_SYS_TEXT_BASE == 0xFFF00000) /* Boot low */
-# define CONFIG_SYS_LOWBOOT 1
-#endif
-
-/*
- * Autobooting
- */
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "flash_nfs=run nfsargs addip;" \
- "bootm ${kernel_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
- "rootpath=/opt/eldk/ppc_82xx\0" \
- ""
-
-#define CONFIG_BOOTCOMMAND "run net_nfs"
-
-#define CONFIG_MISC_INIT_R 1
-
-/*
- * IPB Bus clocking configuration.
- */
-#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
-
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
-
-#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-/*
- * EEPROM configuration
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-/*
- * RTC configuration
- */
-#define CONFIG_RTC_PCF8563
-#define CONFIG_SYS_I2C_RTC_ADDR 0x51
-
-/*
- * Flash configuration
- */
-#define CONFIG_SYS_FLASH_BASE 0xFF800000
-
-#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */
-#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max num of sects on one chip */
-
-#define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE+0x40000) /* second sector */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
- (= chip selects) */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
-
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_CFI_AMD_RESET
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SIZE 0x4000
-#define CONFIG_ENV_SECT_SIZE 0x20000
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR 0xF0000000
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
-#define CONFIG_SYS_DISPLAY_BASE 0x80600000
-#define CONFIG_SYS_STATUS1_BASE 0x80600200
-#define CONFIG_SYS_STATUS2_BASE 0x80600300
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_DDR 1
-#define SDRAM_MODE 0x018D0000
-#define SDRAM_EMODE 0x40090000
-#define SDRAM_CONTROL 0x714f0f00
-#define SDRAM_CONFIG1 0x73722930
-#define SDRAM_CONFIG2 0x47770000
-#define SDRAM_TAPDELAY 0x10000000
-
-/* Use ON-Chip SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
-
-/* preserve space for the post_word at end of on-chip SRAM */
-#define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)
-
-#ifdef CONFIG_POST
-#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
-#else
-#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
-#endif
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-# define CONFIG_SYS_RAMBOOT 1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 128 kB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC 1
-#define CONFIG_MPC5xxx_FEC_MII100
-#define CONFIG_PHY_ADDR 0x00
-#define CONFIG_MII 1 /* MII PHY management */
-
-/*
- * GPIO configuration
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG 0x01051004
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/* Enable an alternate, more extensive memory test */
-#define CONFIG_SYS_ALT_MEMTEST
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-/*
- * Enable loopw command.
- */
-#define CONFIG_LOOPW
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL HID0_ICE
-
-#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_BOOTCS_CFG 0x0004FB00
-#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
-
-/* 8Mbit SRAM @0x80100000 */
-#define CONFIG_SYS_CS1_START 0x80100000
-#define CONFIG_SYS_CS1_SIZE 0x00100000
-#define CONFIG_SYS_CS1_CFG 0x19B00
-
-/* FRAM 32Kbyte @0x80700000 */
-#define CONFIG_SYS_CS2_START 0x80700000
-#define CONFIG_SYS_CS2_SIZE 0x00008000
-#define CONFIG_SYS_CS2_CFG 0x19800
-
-/* Display H1, Status Inputs, EPLD @0x80600000 */
-#define CONFIG_SYS_CS3_START 0x80600000
-#define CONFIG_SYS_CS3_SIZE 0x00100000
-#define CONFIG_SYS_CS3_CFG 0x00019800
-
-#define CONFIG_SYS_CS_BURST 0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff Supports IDE harddisk
- *-----------------------------------------------------------------------
- */
-
-#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
-
-#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
-#undef CONFIG_IDE_LED /* LED for ide not supported */
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
-
-#define CONFIG_IDE_PREINIT 1
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
-
-/* Interval between registers */
-#define CONFIG_SYS_ATA_STRIDE 4
-
-#define CONFIG_ATAPI 1
-
-#define CONFIG_VIDEO_SMI_LYNXEM
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_VIDEO_LOGO
-
-/*
- * PCI Mapping:
- * 0x40000000 - 0x4fffffff - PCI Memory
- * 0x50000000 - 0x50ffffff - PCI IO Space
- */
-#define CONFIG_PCI 1
-#define CONFIG_PCI_PNP 1
-#define CONFIG_PCI_SCAN_SHOW 1
-#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
-
-#define CONFIG_PCI_MEM_BUS 0x40000000
-#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE 0x10000000
-
-#define CONFIG_PCI_IO_BUS 0x50000000
-#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE 0x01000000
-
-#define CONFIG_SYS_ISA_IO CONFIG_PCI_IO_BUS
-
-/*---------------------------------------------------------------------*/
-/* Display addresses */
-/*---------------------------------------------------------------------*/
-
-#define CONFIG_PDSP188x
-#define CONFIG_SYS_DISP_CHR_RAM (CONFIG_SYS_DISPLAY_BASE + 0x38)
-#define CONFIG_SYS_DISP_CWORD (CONFIG_SYS_DISPLAY_BASE + 0x30)
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/mucmc52.h b/include/configs/mucmc52.h
deleted file mode 100644
index ff75ead..0000000
--- a/include/configs/mucmc52.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * (C) Copyright 2008-2009
- * Heiko Schocher, DENX Software Engineering, hs at denx.de.
- *
- * (C) Copyright 2003-2005
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MUCMC52 1 /* MUCMC52 board */
-#define CONFIG_HOSTNAME mucmc52
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xFFF00000
-#endif
-
-#include "manroland/common.h"
-#include "manroland/mpc5200-common.h"
-
-#define CONFIG_LAST_STAGE_INIT
-/*
- * Serial console configuration
- */
-#define CONFIG_BAUDRATE 38400 /* ... at 38400 bps */
-
-#define CONFIG_CMD_PCI
-
-/*
- * Flash configuration
- */
-#define CONFIG_SYS_MAX_FLASH_SECT 67
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_SECT_SIZE 0x20000
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_STATUS1_BASE 0x80600200
-#define CONFIG_SYS_STATUS2_BASE 0x80600300
-#define CONFIG_SYS_PMI_UNI_BASE 0x80800000
-#define CONFIG_SYS_PMI_BROAD_BASE 0x80810000
-
-/*
- * GPIO configuration
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG 0x8D550644
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000
-#define CONFIG_SYS_MEMTEST_END 0x00f00000
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000
-
-#define CONFIG_SYS_BOOTCS_CFG 0x0004FB00
-
-/* 8Mbit SRAM @0x80100000 */
-#define CONFIG_SYS_CS1_SIZE 0x00100000
-#define CONFIG_SYS_CS1_CFG 0x00019B00
-
-#define CONFIG_SYS_SRAM_SIZE CONFIG_SYS_CS1_SIZE
-
-/* FRAM 32Kbyte @0x80700000 */
-#define CONFIG_SYS_CS2_START 0x80700000
-#define CONFIG_SYS_CS2_SIZE 0x00008000
-#define CONFIG_SYS_CS2_CFG 0x00019800
-
-/* Display H1, Status Inputs, EPLD @0x80600000 */
-#define CONFIG_SYS_CS3_START 0x80600000
-#define CONFIG_SYS_CS3_SIZE 0x00100000
-#define CONFIG_SYS_CS3_CFG 0x00019800
-
-/* PMI Unicast 32Kbyte @0x80800000 */
-#define CONFIG_SYS_CS6_START CONFIG_SYS_PMI_UNI_BASE
-#define CONFIG_SYS_CS6_SIZE 0x00008000
-#define CONFIG_SYS_CS6_CFG 0xFFFFF930
-
-/* PMI Broadcast 32Kbyte @0x80810000 */
-#define CONFIG_SYS_CS7_START CONFIG_SYS_PMI_BROAD_BASE
-#define CONFIG_SYS_CS7_SIZE 0x00008000
-#define CONFIG_SYS_CS7_CFG 0xFF00F930
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff Supports IDE harddisk
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus */
-
-/*
- * PCI Mapping:
- * 0x40000000 - 0x4fffffff - PCI Memory
- * 0x50000000 - 0x50ffffff - PCI IO Space
- */
-#define CONFIG_PCI 1
-#define CONFIG_PCI_PNP 1
-#define CONFIG_PCI_SCAN_SHOW 1
-#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
-
-#define CONFIG_PCI_MEM_BUS 0x40000000
-#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE 0x10000000
-
-#define CONFIG_PCI_IO_BUS 0x50000000
-#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE 0x01000000
-
-#define CONFIG_SYS_ISA_IO CONFIG_PCI_IO_BUS
-
-/*---------------------------------------------------------------------*/
-/* Display addresses */
-/*---------------------------------------------------------------------*/
-
-#define CONFIG_SYS_DISP_CHR_RAM (CONFIG_SYS_DISPLAY_BASE + 0x38)
-#define CONFIG_SYS_DISP_CWORD (CONFIG_SYS_DISPLAY_BASE + 0x30)
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/uc100.h b/include/configs/uc100.h
deleted file mode 100644
index cad897f..0000000
--- a/include/configs/uc100.h
+++ /dev/null
@@ -1,482 +0,0 @@
-/*
- * (C) Copyright 2000-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC860 1
-#define CONFIG_MPC860T 1
-#define CONFIG_MPC862 1 /* enable 862 since the */
-#define CONFIG_MPC857 1 /* 857 is a variant of the 862 */
-
-#define CONFIG_UC100 1 /* ...on a UC100 module */
-
-#define CONFIG_SYS_TEXT_BASE 0x40700000
-
-#define MPC8XX_FACT 4 /* Multiply by 4 */
-#define MPC8XX_XIN 25000000 /* 25.0 MHz in */
-#define CONFIG_8xx_GCLK_FREQ (MPC8XX_FACT * MPC8XX_XIN)
- /* define if cant' use get_gclk_freq */
-
-#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-
-#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
-
-#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
-
-#define CONFIG_BOOTCOUNT_LIMIT
-
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#define CONFIG_BOARD_TYPES 1 /* support board types */
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
- "flash_nfs=run nfsargs addip addtty;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip addtty;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
- "bootm\0" \
- "rootpath=/opt/eldk/ppc_8xx\0" \
- "bootfile=/tftpboot/uc100/uImage\0" \
- "kernel_addr=40000000\0" \
- "ramdisk_addr=40100000\0" \
- "load=tftp 100000 /tftpboot/uc100/u-boot.bin\0" \
- "update=protect off 40700000 4073ffff;era 40700000 4073ffff;" \
- "cp.b 100000 40700000 ${filesize};" \
- "setenv filesize;saveenv\0" \
- ""
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#undef CONFIG_STATUS_LED /* no status-led */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#undef CONFIG_RTC_MPC8xx
-#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */
-#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
-
-/*
- * Power On Self Test support
- */
-#define CONFIG_POST ( CONFIG_SYS_POST_CACHE | \
- CONFIG_SYS_POST_MEMORY | \
- CONFIG_SYS_POST_CPU | \
- CONFIG_SYS_POST_UART | \
- CONFIG_SYS_POST_SPR )
-#undef CONFIG_POST
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SNTP
-
-#ifdef CONFIG_POST
-#define CONFIG_CMD_DIAG
-#endif
-
-
-#define CONFIG_NETCONSOLE
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#if 0
-#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
-#endif
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xF0000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0x40000000
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE+0x00700000) /* resetvec fff00100*/
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*-----------------------------------------------------------------------
- * Address accessed to reset the board - must not be mapped/assigned
- */
-#define CONFIG_SYS_RESET_ADDRESS 0x90000000
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
-#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
-#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CONFIG_SYS_SIUMCR (SIUMCR_FRC | SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register 11-27
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit
- */
-#define CONFIG_SYS_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
- PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK 0x00000000
-#define CONFIG_SYS_SCCR (SCCR_EBDF11)
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
- *-----------------------------------------------------------------------
- */
-
-#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
-#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
-
-#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
-#undef CONFIG_IDE_LED /* LED for ide not supported */
-#undef CONFIG_IDE_RESET /* reset for ide not supported */
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_DER 0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
-
-/*
- * FLASH timing:
- */
-#define CONFIG_SYS_OR_TIMING_FLASH (0x00000d24)
-
-#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
-
-#define CONFIG_SYS_BR1_PRELIM 0x00000081 /* Chip select for SDRAM (32 Bit, UPMA) */
-#define CONFIG_SYS_OR1_PRELIM 0xfc000a00
-#define CONFIG_SYS_BR2_PRELIM 0x80000001 /* Chip select for SRAM (32 Bit, GPCM) */
-#define CONFIG_SYS_OR2_PRELIM 0xfff00d24
-#define CONFIG_SYS_BR3_PRELIM 0x80600401 /* Chip select for Display (8 Bit, GPCM) */
-#define CONFIG_SYS_OR3_PRELIM 0xffff8f44
-#define CONFIG_SYS_BR4_PRELIM 0xc05108c1 /* Chip select for Interbus MPM (16 Bit, UPMB) */
-#define CONFIG_SYS_OR4_PRELIM 0xffff0300
-#define CONFIG_SYS_BR5_PRELIM 0xc0500401 /* Chip select for Interbus Status (8 Bit, GPCM) */
-#define CONFIG_SYS_OR5_PRELIM 0xffff8db0
-
-/*
- * Memory Periodic Timer Prescaler
- *
- * The Divider for PTA (refresh timer) configuration is based on an
- * example SDRAM configuration (64 MBit, one bank). The adjustment to
- * the number of chip selects (NCS) and the actually needed refresh
- * rate is done by setting MPTPR.
- *
- * PTA is calculated from
- * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
- *
- * gclk CPU clock (not bus clock!)
- * Trefresh Refresh cycle * 4 (four word bursts used)
- *
- * 4096 Rows from SDRAM example configuration
- * 1000 factor s -> ms
- * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
- * 4 Number of refresh cycles per period
- * 64 Refresh cycle in ms per number of rows
- * --------------------------------------------
- * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
- *
- * 50 MHz => 50.000.000 / Divider = 98
- * 66 Mhz => 66.000.000 / Divider = 129
- * 80 Mhz => 80.000.000 / Divider = 156
- * 100 Mhz => 100.000.000 / Divider = 195
- */
-
-#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
-#define CONFIG_SYS_MAMR_PTA 98
-
-/*
- * For 16 MBit, refresh rates could be 31.3 us
- * (= 64 ms / 2K = 125 / quad bursts).
- * For a simpler initialization, 15.6 us is used instead.
- *
- * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
- * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
- */
-#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
-#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-/* 9 column SDRAM */
-#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-#define CONFIG_SYS_MAMR_VAL 0x30904114 /* for SDRAM */
-#define CONFIG_SYS_MBMR_VAL 0xff001111 /* for Interbus-MPM */
-
-/*-----------------------------------------------------------------------
- * I2C stuff
- */
-
-/* enable I2C and select the hardware/software driver */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define PB_SCL 0x00000020 /* PB 26 */
-#define PB_SDA 0x00000010 /* PB 27 */
-
-#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
-#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
-#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
-#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
-#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
- else immr->im_cpm.cp_pbdat &= ~PB_SDA
-#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
- else immr->im_cpm.cp_pbdat &= ~PB_SCL
-#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (24C164)
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 /* EEPROM AT24C164 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
-
-#define CONFIG_FEC_ENET 1 /* use FEC ethernet */
-#define FEC_ENET
-#define CONFIG_MII
-#define CONFIG_MII_INIT 1
-#define CONFIG_SYS_DISCOVER_PHY 1
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/uc101.h b/include/configs/uc101.h
deleted file mode 100644
index f93dea7..0000000
--- a/include/configs/uc101.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * (C) Copyright 2003-2009
- * Heiko Schocher, DENX Software Engineering, hs at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_UC101 1 /* UC101 board */
-#define CONFIG_HOSTNAME uc101
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xFFF00000
-#endif
-#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds"
-
-#include "manroland/common.h"
-#include "manroland/mpc5200-common.h"
-
-/*
- * Serial console configuration
- */
-#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Flash configuration
- */
-#define CONFIG_SYS_MAX_FLASH_SECT 140
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_SECT_SIZE 0x10000
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_IB_MASTER 0xc0510000 /* CS 6 */
-#define CONFIG_SYS_IB_EPLD 0xc0500000 /* CS 7 */
-
-/* SRAM */
-#define CONFIG_SYS_SRAM_SIZE 0x200000
-
-/*
- * GPIO configuration
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG 0x4d558044
-
-#define CONFIG_SYS_MEMTEST_START 0x00300000
-#define CONFIG_SYS_MEMTEST_END 0x00f00000
-
-#define CONFIG_SYS_LOAD_ADDR 0x300000
-
-#define CONFIG_SYS_BOOTCS_CFG 0x00045D00
-
-/* 8Mbit SRAM @0x80100000 */
-#define CONFIG_SYS_CS1_SIZE 0x00200000
-#define CONFIG_SYS_CS1_CFG 0x21D00
-
-/* Display H1, Status Inputs, EPLD @0x80600000 8 Bit */
-#define CONFIG_SYS_CS3_START CONFIG_SYS_DISPLAY_BASE
-#define CONFIG_SYS_CS3_SIZE 0x00000100
-#define CONFIG_SYS_CS3_CFG 0x00081802
-
-/* Interbus Master 16 Bit */
-#define CONFIG_SYS_CS6_START CONFIG_SYS_IB_MASTER
-#define CONFIG_SYS_CS6_SIZE 0x00010000
-#define CONFIG_SYS_CS6_CFG 0x00FF3500
-
-/* Interbus EPLD 8 Bit */
-#define CONFIG_SYS_CS7_START CONFIG_SYS_IB_EPLD
-#define CONFIG_SYS_CS7_SIZE 0x00010000
-#define CONFIG_SYS_CS7_CFG 0x00081800
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff Supports IDE harddisk
- *-----------------------------------------------------------------------
- */
-
-#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus*/
-
-/*---------------------------------------------------------------------*/
-/* Display addresses */
-/*---------------------------------------------------------------------*/
-#define CONFIG_SYS_DISP_CHR_RAM (CONFIG_SYS_DISPLAY_BASE + 0x38)
-#define CONFIG_SYS_DISP_CWORD (CONFIG_SYS_DISPLAY_BASE + 0x30)
-
-#endif /* __CONFIG_H */
diff --git a/include/pcmcia.h b/include/pcmcia.h
index 00065b2..2ff399b 100644
--- a/include/pcmcia.h
+++ b/include/pcmcia.h
@@ -33,8 +33,6 @@
# define CONFIG_PCMCIA_SLOT_B
#elif defined(CONFIG_ATC) /* The ATC use SLOT_A */
# define CONFIG_PCMCIA_SLOT_A
-#elif defined(CONFIG_UC100) /* The UC100 use SLOT_B */
-# define CONFIG_PCMCIA_SLOT_B
#else
# error "PCMCIA Slot not configured"
#endif
--
1.9.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [U-Boot] [PATCH 02/26] powerpc: manroland: remove uc100, uc101, mucmc52, hmi1001 support
2014-12-15 14:26 ` [U-Boot] [PATCH 02/26] powerpc: manroland: remove uc100, uc101, mucmc52, hmi1001 support Masahiro Yamada
@ 2015-01-05 18:20 ` Tom Rini
0 siblings, 0 replies; 55+ messages in thread
From: Tom Rini @ 2015-01-05 18:20 UTC (permalink / raw)
To: u-boot
On Mon, Dec 15, 2014 at 11:26:07PM +0900, Masahiro Yamada wrote:
> These boards are still non-generic boards.
>
> Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
> Cc: Heiko Schocher <hs@denx.de>
> Cc: Stefan Roese <sr@denx.de>
Applied to u-boot/master, thanks!
--
Tom
-------------- next part --------------
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^ permalink raw reply [flat|nested] 55+ messages in thread
* [U-Boot] [PATCH 03/26] mpc8xx: remove ELPT860 board support
2014-12-15 14:26 [U-Boot] [PATCH 0/26] Start removing non-generic boards Masahiro Yamada
2014-12-15 14:26 ` [U-Boot] [PATCH 01/26] mpc8xx: remove FPS{850, 860}L, NSCU, SM850, TK885D, virtlab2 support Masahiro Yamada
2014-12-15 14:26 ` [U-Boot] [PATCH 02/26] powerpc: manroland: remove uc100, uc101, mucmc52, hmi1001 support Masahiro Yamada
@ 2014-12-15 14:26 ` Masahiro Yamada
2015-01-05 18:20 ` Tom Rini
2014-12-15 14:26 ` [U-Boot] [PATCH 04/26] mpc8xx: remove KUP4X, KUP4K " Masahiro Yamada
` (24 subsequent siblings)
27 siblings, 1 reply; 55+ messages in thread
From: Masahiro Yamada @ 2014-12-15 14:26 UTC (permalink / raw)
To: u-boot
This board is still a non-generic board.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: The LEOX team <team@leox.org>
---
arch/powerpc/cpu/mpc8xx/Kconfig | 4 -
board/LEOX/elpt860/Kconfig | 12 -
board/LEOX/elpt860/MAINTAINERS | 6 -
board/LEOX/elpt860/Makefile | 21 --
board/LEOX/elpt860/README.LEOX | 423 -------------------------
board/LEOX/elpt860/elpt860.c | 336 --------------------
board/LEOX/elpt860/flash.c | 602 ------------------------------------
board/LEOX/elpt860/u-boot.lds | 103 ------
board/LEOX/elpt860/u-boot.lds.debug | 126 --------
configs/ELPT860_defconfig | 3 -
doc/README.scrapyard | 1 +
include/commproc.h | 26 --
include/configs/ELPT860.h | 374 ----------------------
13 files changed, 1 insertion(+), 2036 deletions(-)
delete mode 100644 board/LEOX/elpt860/Kconfig
delete mode 100644 board/LEOX/elpt860/MAINTAINERS
delete mode 100644 board/LEOX/elpt860/Makefile
delete mode 100644 board/LEOX/elpt860/README.LEOX
delete mode 100644 board/LEOX/elpt860/elpt860.c
delete mode 100644 board/LEOX/elpt860/flash.c
delete mode 100644 board/LEOX/elpt860/u-boot.lds
delete mode 100644 board/LEOX/elpt860/u-boot.lds.debug
delete mode 100644 configs/ELPT860_defconfig
delete mode 100644 include/configs/ELPT860.h
diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig
index 9eb7e17..30f8533 100644
--- a/arch/powerpc/cpu/mpc8xx/Kconfig
+++ b/arch/powerpc/cpu/mpc8xx/Kconfig
@@ -43,9 +43,6 @@ config TARGET_KUP4K
config TARGET_KUP4X
bool "Support KUP4X"
-config TARGET_ELPT860
- bool "Support ELPT860"
-
config TARGET_TQM823L
bool "Support TQM823L"
@@ -84,7 +81,6 @@ config TARGET_TQM885D
endchoice
-source "board/LEOX/elpt860/Kconfig"
source "board/RRvision/Kconfig"
source "board/cogent/Kconfig"
source "board/esteem192e/Kconfig"
diff --git a/board/LEOX/elpt860/Kconfig b/board/LEOX/elpt860/Kconfig
deleted file mode 100644
index ed74956..0000000
--- a/board/LEOX/elpt860/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_ELPT860
-
-config SYS_BOARD
- default "elpt860"
-
-config SYS_VENDOR
- default "LEOX"
-
-config SYS_CONFIG_NAME
- default "ELPT860"
-
-endif
diff --git a/board/LEOX/elpt860/MAINTAINERS b/board/LEOX/elpt860/MAINTAINERS
deleted file mode 100644
index 8f8a199..0000000
--- a/board/LEOX/elpt860/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-ELPT860 BOARD
-M: The LEOX team <team@leox.org>
-S: Maintained
-F: board/LEOX/elpt860/
-F: include/configs/ELPT860.h
-F: configs/ELPT860_defconfig
diff --git a/board/LEOX/elpt860/Makefile b/board/LEOX/elpt860/Makefile
deleted file mode 100644
index b811adb..0000000
--- a/board/LEOX/elpt860/Makefile
+++ /dev/null
@@ -1,21 +0,0 @@
-#######################################################################
-#
-# Copyright (C) 2000, 2001, 2002, 2003
-# The LEOX team <team@leox.org>, http://www.leox.org
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# LEOX.org is about the development of free hardware and software resources
-# for system on chip.
-#
-# Description: U-Boot port on the LEOX's ELPT860 CPU board
-# ~~~~~~~~~~~
-#
-#######################################################################
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-#######################################################################
-
-obj-y = elpt860.o flash.o
diff --git a/board/LEOX/elpt860/README.LEOX b/board/LEOX/elpt860/README.LEOX
deleted file mode 100644
index aa41ff8..0000000
--- a/board/LEOX/elpt860/README.LEOX
+++ /dev/null
@@ -1,423 +0,0 @@
-=============================================================================
-
- U-Boot port on the LEOX's ELPT860 CPU board
- -------------------------------------------
-
-LEOX.org is about the development of free hardware and software resources
- for system on chip.
-
-For more information, contact The LEOX team <team@leox.org>
-
-References:
-~~~~~~~~~~
- 1) Get the last stable release from denx.de:
- o ftp://ftp.denx.de/pub/u-boot/u-boot-0.2.0.tar.bz2
- 2) Get the current CVS snapshot:
- o cvs -d:pserver:anonymous at cvs.u-boot.sourceforge.net:/cvsroot/u-boot login
- o cvs -z6 -d:pserver:anonymous at cvs.u-boot.sourceforge.net:/cvsroot/u-boot co -P u-boot
-
-=============================================================================
-
-The ELPT860 CPU board has the following features:
-
-Processor: - MPC860T @ 50MHz
- - PowerPC Core
- - 65 MIPS
- - Caches: D->4KB, I->4KB
- - CPM: 4 SCCs, 2 SMCs
- - Ethernet 10/100
- - SPI, I2C, PCMCIA, Parallel
-
-CPU board: - DRAM: 16 MB
- - FLASH: 512 KB + (2 * 4 MB)
- - NVRAM: 128 KB
- - 1 Serial link
- - 2 Ethernet 10 BaseT Channels
-
-On power-up the processor jumps to the address of 0x02000100
-
-Thus, U-Boot is configured to reside in flash starting at the address of
-0x02001000. The environment space is located in NVRAM separately from
-U-Boot, at the address of 0x03000000.
-
-=============================================================================
-
- U-Boot test results
-
-=============================================================================
-
-##################################################
-# Operation on the serial console (SMC1)
-##############################
-
-U-Boot 0.2.2 (Jan 19 2003 - 11:08:39)
-
-CPU: XPC860xxZPnnB at 50 MHz: 4 kB I-Cache 4 kB D-Cache FEC present
- *** Warning: CPU Core has Silicon Bugs -- Check the Errata ***
-Board: ### No HW ID - assuming ELPT860
-DRAM: 16 MB
-FLASH: 512 kB
-In: serial
-Out: serial
-Err: serial
-Net: SCC ETHERNET
-
-Type "run nfsboot" to mount root filesystem over NFS
-
-Hit any key to stop autoboot: 0
-LEOX_elpt860: help
-askenv - get environment variables from stdin
-base - print or set address offset
-bdinfo - print Board Info structure
-bootm - boot application image from memory
-bootp - boot image via network using BootP/TFTP protocol
-bootd - boot default, i.e., run 'bootcmd'
-cmp - memory compare
-coninfo - print console devices and informations
-cp - memory copy
-crc32 - checksum calculation
-echo - echo args to console
-erase - erase FLASH memory
-flinfo - print FLASH memory information
-go - start application at address 'addr'
-help - print online help
-iminfo - print header information for application image
-loadb - load binary file over serial line (kermit mode)
-loads - load S-Record file over serial line
-loop - infinite loop on address range
-md - memory display
-mm - memory modify (auto-incrementing)
-mtest - simple RAM test
-mw - memory write (fill)
-nm - memory modify (constant address)
-printenv- print environment variables
-protect - enable or disable FLASH write protection
-rarpboot- boot image via network using RARP/TFTP protocol
-reset - Perform RESET of the CPU
-run - run commands in an environment variable
-saveenv - save environment variables to persistent storage
-setenv - set environment variables
-sleep - delay execution for some time
-source - run script from memory
-tftpboot- boot image via network using TFTP protocol
- and env variables ipaddr and serverip
-version - print monitor version
-? - alias for 'help'
-
-##################################################
-# Environment Variables (CONFIG_ENV_IS_IN_NVRAM)
-##############################
-
-LEOX_elpt860: printenv
-bootdelay=5
-loads_echo=1
-baudrate=9600
-stdin=serial
-stdout=serial
-stderr=serial
-ethaddr=00:03:ca:00:64:df
-ipaddr=192.168.0.30
-netmask=255.255.255.0
-serverip=192.168.0.1
-nfsserverip=192.168.0.1
-preboot=echo;echo Type "run nfsboot" to mount root filesystem over NFS;echo
-gatewayip=192.168.0.1
-ramargs=setenv bootargs root=/dev/ram rw
-rootargs=setenv rootpath /tftp/${ipaddr}
-nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${nfsserverip}:${rootpath}
-addip=setenv bootargs ${bootargs} ip=${ipaddr}:${nfsserverip}:${gatewayip}:${netmask}:${hostname}:eth0:
-ramboot=tftp 400000 /home/leox/pMulti;run ramargs;bootm
-nfsboot=tftp 400000 /home/leox/uImage;run rootargs;run nfsargs;run addip;bootm
-bootcmd=run ramboot
-clocks_in_mhz=1
-
-Environment size: 730/16380 bytes
-
-##################################################
-# Flash Memory Information
-##############################
-
-LEOX_elpt860: flinfo
-
-Bank # 1: AMD AM29F040 (4 Mbits)
- Size: 512 KB in 8 Sectors
- Sector Start Addresses:
- 02000000 (RO) 02010000 (RO) 02020000 (RO) 02030000 (RO) 02040000
- 02050000 02060000 02070000
-
-##################################################
-# Board Information Structure
-##############################
-
-LEOX_elpt860: bdinfo
-memstart = 0x00000000
-memsize = 0x01000000
-flashstart = 0x02000000
-flashsize = 0x00080000
-flashoffset = 0x00030000
-sramstart = 0x00000000
-sramsize = 0x00000000
-immr_base = 0xFF000000
-bootflags = 0x00000001
-intfreq = 50 MHz
-busfreq = 50 MHz
-ethaddr = 00:03:ca:00:64:df
-IP addr = 192.168.0.30
-baudrate = 9600 bps
-
-##################################################
-# Image Download and run over serial port
-# hello_world (S-Record image)
-# ===> 1) Enter "loads" command into U-Boot monitor
-# ===> 2) From TeraTerm's bar menu, Select 'File/Send file...'
-# Then select 'hello_world.srec' with the file browser
-##############################
-
-U-Boot 0.2.2 (Jan 19 2003 - 11:08:39)
-
-CPU: XPC860xxZPnnB at 50 MHz: 4 kB I-Cache 4 kB D-Cache FEC present
- *** Warning: CPU Core has Silicon Bugs -- Check the Errata ***
-Board: ### No HW ID - assuming ELPT860
-DRAM: 16 MB
-FLASH: 512 kB
-In: serial
-Out: serial
-Err: serial
-Net: SCC ETHERNET
-
-Type "run nfsboot" to mount root filesystem over NFS
-
-Hit any key to stop autoboot: 0
-LEOX_elpt860: loads
-## Ready for S-Record download ...
-S804040004F3050154000501709905014C000501388D
-## First Load Addr = 0x00040000
-## Last Load Addr = 0x0005018B
-## Total Size = 0x0001018C = 65932 Bytes
-## Start Addr = 0x00040004
-LEOX_elpt860: go 40004 This is a test !!!
-## Starting application at 0x00040004 ...
-Hello World
-argc = 6
-argv[0] = "40004"
-argv[1] = "This"
-argv[2] = "is"
-argv[3] = "a"
-argv[4] = "test"
-argv[5] = "!!!"
-argv[6] = "<NULL>"
-Hit any key to exit ...
-
-## Application terminated, rc = 0x0
-
-##################################################
-# Image download and run over ethernet interface
-# Linux-2.4.4 (uImage) + Root filesystem mounted over NFS
-##############################
-
-U-Boot 0.2.2 (Jan 19 2003 - 11:08:39)
-
-CPU: XPC860xxZPnnB at 50 MHz: 4 kB I-Cache 4 kB D-Cache FEC present
- *** Warning: CPU Core has Silicon Bugs -- Check the Errata ***
-Board: ### No HW ID - assuming ELPT860
-DRAM: 16 MB
-FLASH: 512 kB
-In: serial
-Out: serial
-Err: serial
-Net: SCC ETHERNET
-
-Type "run nfsboot" to mount root filesystem over NFS
-
-Hit any key to stop autoboot: 0
-LEOX_elpt860: run nfsboot
-ARP broadcast 1
-TFTP from server 192.168.0.1; our IP address is 192.168.0.30
-Filename '/home/leox/uImage'.
-Load address: 0x400000
-Loading: #################################################################
- #############################
-done
-Bytes transferred = 477294 (7486e hex)
-## Booting image at 00400000 ...
- Image Name: Linux-2.4.4
- Image Type: PowerPC Linux Kernel Image (gzip compressed)
- Data Size: 477230 Bytes = 466 kB = 0 MB
- Load Address: 00000000
- Entry Point: 00000000
- Verifying Checksum ... OK
- Uncompressing Kernel Image ... OK
-Linux version 2.4.4-rthal5 (leox at p5ak6650) (gcc version 2.95.3 20010315 (release/MontaVista)) #1 Wed Jul 3 10:23:53 CEST 2002
-On node 0 totalpages: 4096
-zone(0): 4096 pages.
-zone(1): 0 pages.
-zone(2): 0 pages.
-Kernel command line: root=/dev/nfs rw nfsroot=192.168.0.1:/tftp/192.168.0.30 ip=192.168.0.30:192.168.0.1:192.168.0.1:255.255.255.0::eth0:
-rtsched version <20010618.1050.24>
-Decrementer Frequency: 3125000
-Warning: real time clock seems stuck!
-Calibrating delay loop... 49.76 BogoMIPS
-Memory: 14720k available (928k kernel code, 384k data, 44k init, 0k highmem)
-Dentry-cache hash table entries: 2048 (order: 2, 16384 bytes)
-Buffer-cache hash table entries: 1024 (order: 0, 4096 bytes)
-Page-cache hash table entries: 4096 (order: 2, 16384 bytes)
-Inode-cache hash table entries: 1024 (order: 1, 8192 bytes)
-POSIX conformance testing by UNIFIX
-Linux NET4.0 for Linux 2.4
-Based upon Swansea University Computer Society NET3.039
-Starting kswapd v1.8
-CPM UART driver version 0.03
-ttyS0 on SMC1 at 0x0280, BRG1
-block: queued sectors max/low 9701kB/3233kB, 64 slots per queue
-RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
-eth0: CPM ENET Version 0.2 on SCC1, 00:03:ca:00:64:df
-NET4: Linux TCP/IP 1.0 for NET4.0
-IP Protocols: ICMP, UDP, TCP
-IP: routing cache hash table of 512 buckets, 4Kbytes
-TCP: Hash tables configured (established 1024 bind 1024)
-NET4: Unix domain sockets 1.0/SMP for Linux NET4.0.
-Looking up port of RPC 100003/2 on 192.168.0.1
-Looking up port of RPC 100005/2 on 192.168.0.1
-VFS: Mounted root (nfs filesystem).
-Freeing unused kernel memory: 44k init
-INIT: version 2.78 booting
- Welcome to DENX Embedded Linux Environment
- Press 'I' to enter interactive startup.
-Mounting proc filesystem: [ OK ]
-Configuring kernel parameters: [ OK ]
-Cannot access the Hardware Clock via any known method.
-Use the --debug option to see the details of our search for an access method.
-Setting clock : Wed Dec 31 19:00:11 EST 1969 [ OK ]
-Activating swap partitions: [ OK ]
-Setting hostname 192.168.0.30: [ OK ]
-Finding module dependencies:
-[ OK ]
-Checking filesystems
-Checking all file systems.
-[ OK ]
-Mounting local filesystems: [ OK ]
-Enabling swap space: [ OK ]
-INIT: Entering runlevel: 3
-Entering non-interactive startup
-Starting system logger: [ OK ]
-Starting kernel logger: [ OK ]
-Starting xinetd: [ OK ]
-
-192 login: root
-Last login: Wed Dec 31 19:00:41 on ttyS0
-bash-2.04#
-
-##################################################
-# Image download and run over ethernet interface
-# Linux-2.4.4 + Root filesystem mounted from RAM (pMulti)
-##############################
-
-U-Boot 0.2.2 (Jan 19 2003 - 11:08:39)
-
-CPU: XPC860xxZPnnB at 50 MHz: 4 kB I-Cache 4 kB D-Cache FEC present
- *** Warning: CPU Core has Silicon Bugs -- Check the Errata ***
-Board: ### No HW ID - assuming ELPT860
-DRAM: 16 MB
-FLASH: 512 kB
-In: serial
-Out: serial
-Err: serial
-Net: SCC ETHERNET
-
-Type "run nfsboot" to mount root filesystem over NFS
-
-Hit any key to stop autoboot: 0
-LEOX_elpt860: run ramboot
-ARP broadcast 1
-TFTP from server 192.168.0.1; our IP address is 192.168.0.30
-Filename '/home/leox/pMulti'.
-Load address: 0x400000
-Loading: #################################################################
- #################################################################
- #################################################################
- #################################################################
- #################################################################
- ########################################################
-done
-Bytes transferred = 1947816 (1db8a8 hex)
-## Booting image at 00400000 ...
- Image Name: linux-2.4.4-2002-03-21 Multiboot
- Image Type: PowerPC Linux Multi-File Image (gzip compressed)
- Data Size: 1947752 Bytes = 1902 kB = 1 MB
- Load Address: 00000000
- Entry Point: 00000000
- Contents:
- Image 0: 477230 Bytes = 466 kB = 0 MB
- Image 1: 1470508 Bytes = 1436 kB = 1 MB
- Verifying Checksum ... OK
- Uncompressing Multi-File Image ... OK
- Loading Ramdisk to 00e44000, end 00fab02c ... OK
-Linux version 2.4.4-rthal5 (leox at p5ak6650) (gcc version 2.95.3 20010315 (release/MontaVista)) #1 Wed Jul 3 10:23:53 CEST 2002
-On node 0 totalpages: 4096
-zone(0): 4096 pages.
-zone(1): 0 pages.
-zone(2): 0 pages.
-Kernel command line: root=/dev/ram rw
-rtsched version <20010618.1050.24>
-Decrementer Frequency: 3125000
-Warning: real time clock seems stuck!
-Calibrating delay loop... 49.76 BogoMIPS
-Memory: 13280k available (928k kernel code, 384k data, 44k init, 0k highmem)
-Dentry-cache hash table entries: 2048 (order: 2, 16384 bytes)
-Buffer-cache hash table entries: 1024 (order: 0, 4096 bytes)
-Page-cache hash table entries: 4096 (order: 2, 16384 bytes)
-Inode-cache hash table entries: 1024 (order: 1, 8192 bytes)
-POSIX conformance testing by UNIFIX
-Linux NET4.0 for Linux 2.4
-Based upon Swansea University Computer Society NET3.039
-Starting kswapd v1.8
-CPM UART driver version 0.03
-ttyS0 on SMC1 at 0x0280, BRG1
-block: queued sectors max/low 8741kB/2913kB, 64 slots per queue
-RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
-eth0: CPM ENET Version 0.2 on SCC1, 00:03:ca:00:64:df
-RAMDISK: Compressed image found at block 0
-Freeing initrd memory: 1436k freed
-NET4: Linux TCP/IP 1.0 for NET4.0
-IP Protocols: ICMP, UDP, TCP
-IP: routing cache hash table of 512 buckets, 4Kbytes
-TCP: Hash tables configured (established 1024 bind 1024)
-IP-Config: Incomplete network configuration information.
-NET4: Unix domain sockets 1.0/SMP for Linux NET4.0.
-VFS: Mounted root (ext2 filesystem).
-Freeing unused kernel memory: 44k init
-init started: BusyBox v0.60.2 (2002.07.01-12:06+0000) multi-call Configuring hostname
-Configuring lo...
-Configuring eth0...
-Configuring Gateway...
-
-Please press Enter to activate this console.
-
-ELPT860 login: root
-Password:
-Welcome to Linux-2.4.4 for ELPT CPU board (MPC860T @ 50MHz)
-
- a8888b.
- d888888b.
- 8P"YP"Y88
- _ _ 8|o||o|88
- | | |_| 8' .88
- | | _ ____ _ _ _ _ 8`._.' Y8.
- | | | | _ \| | | |\ \/ / d/ `8b.
- | |___ | | | | | |_| |/ \ .dP . Y8b.
- |_____||_|_| |_|\____|\_/\_/ d8:' " `::88b.
- d8" `Y88b
- :8P ' :888
- 8a. : _a88P
- ._/"Yaa_ : .| 88P|
- \ YP" `| 8P `.
- / \._____.d| .'
- `--..__)888888P`._.'
-login[21]: root login on `ttyS0'
-
-
-
-BusyBox v0.60.3 (2002.07.20-10:39+0000) Built-in shell (ash)
-Enter 'help' for a list of built-in commands.
-
-root at ELPT860:~ #
diff --git a/board/LEOX/elpt860/elpt860.c b/board/LEOX/elpt860/elpt860.c
deleted file mode 100644
index 81820cb..0000000
--- a/board/LEOX/elpt860/elpt860.c
+++ /dev/null
@@ -1,336 +0,0 @@
-/*
-**=====================================================================
-**
-** Copyright (C) 2000, 2001, 2002, 2003
-** The LEOX team <team@leox.org>, http://www.leox.org
-**
-** LEOX.org is about the development of free hardware and software resources
-** for system on chip.
-**
-** Description: U-Boot port on the LEOX's ELPT860 CPU board
-** ~~~~~~~~~~~
-**
-**=====================================================================
-**
- * SPDX-License-Identifier: GPL-2.0+
-**
-**=====================================================================
-*/
-
-/*
-** Note 1: In this file, you have to provide the following functions:
-** ------
-** int board_early_init_f(void)
-** int checkboard(void)
-** phys_size_t initdram(int board_type)
-** called from 'board_init_f()' into 'common/board.c'
-**
-** void reset_phy(void)
-** called from 'board_init_r()' into 'common/board.c'
-*/
-
-#include <common.h>
-#include <mpc8xx.h>
-
-/* ------------------------------------------------------------------------- */
-
-static long int dram_size (long int, long int *, long int);
-
-/* ------------------------------------------------------------------------- */
-
-#define _NOT_USED_ 0xFFFFFFFF
-
-const uint init_sdram_table[] = {
- /*
- * Single Read. (Offset 0 in UPMA RAM)
- */
- 0x0FFCCC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04,
- 0xFFFFFC04, /* last */
- /*
- * SDRAM Initialization (offset 5 in UPMA RAM)
- *
- * This is no UPM entry point. The following definition uses
- * the remaining space to establish an initialization
- * sequence, which is executed by a RUN command.
- *
- */
- 0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04, /* last */
- /*
- * Burst Read. (Offset 8 in UPMA RAM)
- */
- 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
- 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
- 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04,
- 0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, /* last */
- /*
- * Single Write. (Offset 18 in UPMA RAM)
- */
- 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04,
- 0xFFFFFC04, 0xFFFFFC04, 0x0FFFFC04, 0xFFFFFC04, /* last */
- /*
- * Burst Write. (Offset 20 in UPMA RAM)
- */
- 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
- 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04,
- 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC34, 0x0FAC0C34,
- 0xFFFFFC05, 0xFFFFFC04, 0x0FFCFC04, 0xFFFFFC05, /* last */
-};
-
-const uint sdram_table[] = {
- /*
- * Single Read. (Offset 0 in UPMA RAM)
- */
- 0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04,
- 0xFF0FFC00, /* last */
- /*
- * SDRAM Initialization (offset 5 in UPMA RAM)
- *
- * This is no UPM entry point. The following definition uses
- * the remaining space to establish an initialization
- * sequence, which is executed by a RUN command.
- *
- */
- 0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC05, /* last */
- /*
- * Burst Read. (Offset 8 in UPMA RAM)
- */
- 0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04,
- 0xF00FFC00, 0xF00FFC00, 0xF00FFC00, 0xFF0FFC00,
- 0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04,
- 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */
- /*
- * Single Write. (Offset 18 in UPMA RAM)
- */
- 0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF0C00,
- 0xFF0FFC04, 0x0FFCCC04, 0xFFAFFC05, /* last */
- _NOT_USED_,
- /*
- * Burst Write. (Offset 20 in UPMA RAM)
- */
- 0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC00, 0x00AF0C00,
- 0xF00FFC00, 0xF00FFC00, 0xF00FFC04, 0x0FFCCC04,
- 0xFFAFFC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04,
- 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */
- /*
- * Refresh (Offset 30 in UPMA RAM)
- */
- 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
- 0xFFFFFC05, 0xFFFFFC04, 0xFFFFFC05, _NOT_USED_,
- 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */
- /*
- * Exception. (Offset 3c in UPMA RAM)
- */
- 0x0FFFFC34, 0x0FAC0C34, 0xFFFFFC05, 0xFFAFFC04, /* last */
-};
-
-/* ------------------------------------------------------------------------- */
-
-#define CONFIG_SYS_PC4 0x0800
-
-#define CONFIG_SYS_DS1 CONFIG_SYS_PC4
-
-/*
- * Very early board init code (fpga boot, etc.)
- */
-int board_early_init_f (void)
-{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
-
- /*
- * Light up the red led on ELPT860 pcb (DS1) (PCDAT)
- */
- immr->im_ioport.iop_pcdat &= ~CONFIG_SYS_DS1; /* PCDAT (DS1 = 0) */
- immr->im_ioport.iop_pcpar &= ~CONFIG_SYS_DS1; /* PCPAR (0=general purpose I/O) */
- immr->im_ioport.iop_pcdir |= CONFIG_SYS_DS1; /* PCDIR (I/O: 0=input, 1=output) */
-
- return (0); /* success */
-}
-
-/*
- * Check Board Identity:
- *
- * Test ELPT860 ID string
- *
- * Return 1 if no second DRAM bank, otherwise returns 0
- */
-
-int checkboard (void)
-{
- char buf[64];
- int i = getenv_f("serial#", buf, sizeof(buf));
-
- if ((i < 0) || strncmp(buf, "ELPT860", 7))
- printf ("### No HW ID - assuming ELPT860\n");
-
- return (0); /* success */
-}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- long int size8, size9;
- long int size_b0 = 0;
-
- /*
- * This sequence initializes SDRAM chips on ELPT860 board
- */
- upmconfig (UPMA, (uint *) init_sdram_table,
- sizeof (init_sdram_table) / sizeof (uint));
-
- memctl->memc_mptpr = 0x0200;
- memctl->memc_mamr = 0x18002111;
-
- memctl->memc_mar = 0x00000088;
- memctl->memc_mcr = 0x80002000; /* CS1: SDRAM bank 0 */
-
- upmconfig (UPMA, (uint *) sdram_table,
- sizeof (sdram_table) / sizeof (uint));
-
- /*
- * Preliminary prescaler for refresh (depends on number of
- * banks): This value is selected for four cycles every 62.4 us
- * with two SDRAM banks or four cycles every 31.2 us with one
- * bank. It will be adjusted after memory sizing.
- */
- memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
-
- /*
- * The following value is used as an address (i.e. opcode) for
- * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
- * the port size is 32bit the SDRAM does NOT "see" the lower two
- * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
- * MICRON SDRAMs:
- * -> 0 00 010 0 010
- * | | | | +- Burst Length = 4
- * | | | +----- Burst Type = Sequential
- * | | +------- CAS Latency = 2
- * | +----------- Operating Mode = Standard
- * +-------------- Write Burst Mode = Programmed Burst Length
- */
- memctl->memc_mar = 0x00000088;
-
- /*
- * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
- * preliminary addresses - these have to be modified after the
- * SDRAM size has been determined.
- */
- memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
- memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
-
- memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
-
- udelay (200);
-
- /* perform SDRAM initializsation sequence */
-
- memctl->memc_mcr = 0x80002105; /* CS1: SDRAM bank 0 */
- udelay (1);
- memctl->memc_mcr = 0x80002230; /* CS1: SDRAM bank 0 - execute twice */
- udelay (1);
-
- memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
-
- udelay (1000);
-
- /*
- * Check Bank 0 Memory Size for re-configuration
- *
- * try 8 column mode
- */
- size8 = dram_size (CONFIG_SYS_MAMR_8COL,
- SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
-
- udelay (1000);
-
- /*
- * try 9 column mode
- */
- size9 = dram_size (CONFIG_SYS_MAMR_9COL,
- SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
-
- if (size8 < size9) { /* leave configuration@9 columns */
- size_b0 = size9;
- /* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
- } else { /* back to 8 columns */
-
- size_b0 = size8;
- memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
- udelay (500);
- /* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
- }
-
- udelay (1000);
-
- /*
- * Adjust refresh rate depending on SDRAM type, both banks
- * For types > 128 MBit leave it at the current (fast) rate
- */
- if (size_b0 < 0x02000000) {
- /* reduce to 15.6 us (62.4 us / quad) */
- memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
- udelay (1000);
- }
-
- /*
- * Final mapping: map bigger bank first
- */
- memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
- memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
-
- {
- unsigned long reg;
-
- /* adjust refresh rate depending on SDRAM type, one bank */
- reg = memctl->memc_mptpr;
- reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
- memctl->memc_mptpr = reg;
- }
-
- udelay (10000);
-
- return (size_b0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-
-static long int
-dram_size (long int mamr_value, long int *base, long int maxsize)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
- memctl->memc_mamr = mamr_value;
-
- return (get_ram_size (base, maxsize));
-}
-
-/* ------------------------------------------------------------------------- */
-
-#define CONFIG_SYS_PA1 0x4000
-#define CONFIG_SYS_PA2 0x2000
-
-#define CONFIG_SYS_LBKs (CONFIG_SYS_PA2 | CONFIG_SYS_PA1)
-
-void reset_phy (void)
-{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
-
- /*
- * Ensure LBK LXT901 ethernet 1 & 2 = 0 ... for normal loopback in effect
- * and no AUI loopback
- */
- immr->im_ioport.iop_padat &= ~CONFIG_SYS_LBKs; /* PADAT (LBK eth 1&2 = 0) */
- immr->im_ioport.iop_papar &= ~CONFIG_SYS_LBKs; /* PAPAR (0=general purpose I/O) */
- immr->im_ioport.iop_padir |= CONFIG_SYS_LBKs; /* PADIR (I/O: 0=input, 1=output) */
-}
diff --git a/board/LEOX/elpt860/flash.c b/board/LEOX/elpt860/flash.c
deleted file mode 100644
index 0377c89..0000000
--- a/board/LEOX/elpt860/flash.c
+++ /dev/null
@@ -1,602 +0,0 @@
-/*
-**=====================================================================
-**
-** Copyright (C) 2000, 2001, 2002, 2003
-** The LEOX team <team@leox.org>, http://www.leox.org
-**
-** LEOX.org is about the development of free hardware and software resources
-** for system on chip.
-**
-** Description: U-Boot port on the LEOX's ELPT860 CPU board
-** ~~~~~~~~~~~
-**
-**=====================================================================
-**
- * SPDX-License-Identifier: GPL-2.0+
-**
-**=====================================================================
-*/
-
-/*
-** Note 1: In this file, you have to provide the following variable:
-** ------
-** flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]
-** 'flash_info_t' structure is defined into 'include/flash.h'
-** and defined as extern into 'common/cmd_flash.c'
-**
-** Note 2: In this file, you have to provide the following functions:
-** ------
-** unsigned long flash_init(void)
-** called from 'board_init_r()' into 'common/board.c'
-**
-** void flash_print_info(flash_info_t *info)
-** called from 'do_flinfo()' into 'common/cmd_flash.c'
-**
-** int flash_erase(flash_info_t *info,
-** int s_first,
-** int s_last)
-** called from 'do_flerase()' & 'flash_sect_erase()' into 'common/cmd_flash.c'
-**
-** int write_buff (flash_info_t *info,
-** uchar *src,
-** ulong addr,
-** ulong cnt)
-** called from 'flash_write()' into 'common/cmd_flash.c'
-*/
-
-#include <common.h>
-#include <mpc8xx.h>
-
-
-#ifndef CONFIG_ENV_ADDR
-# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-#endif
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Internal Functions
- */
-static void flash_get_offsets (ulong base, flash_info_t *info);
-static ulong flash_get_size (volatile unsigned char *addr, flash_info_t *info);
-
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static int write_byte (flash_info_t *info, ulong dest, uchar data);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long
-flash_init (void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- unsigned long size_b0;
- int i;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i)
- {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size_b0 = flash_get_size ((volatile unsigned char *)FLASH_BASE0_PRELIM,
- &flash_info[0]);
-
- if ( flash_info[0].flash_id == FLASH_UNKNOWN )
- {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0<<20);
- }
-
- /* Remap FLASH according to real size */
- memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
- memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_PS_8 | BR_V;
-
- /* Re-do sizing to get full correct info */
- size_b0 = flash_get_size ((volatile unsigned char *)CONFIG_SYS_FLASH_BASE,
- &flash_info[0]);
-
- flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + monitor_flash_len-1,
- &flash_info[0]);
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE-1,
- &flash_info[0]);
-#endif
-
- flash_info[0].size = size_b0;
-
- return (size_b0);
-}
-
-/*-----------------------------------------------------------------------
- */
-static void
-flash_get_offsets (ulong base,
- flash_info_t *info)
-{
- int i;
-
-#define SECTOR_64KB 0x00010000
-
- /* set up sector start adress table */
- for (i = 0; i < info->sector_count; i++)
- {
- info->start[i] = base + (i * SECTOR_64KB);
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-void
-flash_print_info (flash_info_t *info)
-{
- int i;
-
- if ( info->flash_id == FLASH_UNKNOWN )
- {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch ( info->flash_id & FLASH_VENDMASK )
- {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
- case FLASH_MAN_STM: printf ("STM (Thomson) "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch ( info->flash_id & FLASH_TYPEMASK )
- {
- case FLASH_AM040: printf ("AM29F040 (4 Mbits)\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld KB in %d Sectors\n",
- info->size >> 10, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i)
- {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
-
- return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong
-flash_get_size (volatile unsigned char *addr,
- flash_info_t *info)
-{
- short i;
- uchar value;
- ulong base = (ulong)addr;
-
- /* Write auto select command: read Manufacturer ID */
- addr[0x0555] = 0xAA;
- addr[0x02AA] = 0x55;
- addr[0x0555] = 0x90;
-
- value = addr[0];
-
- switch ( value )
- {
- /* case AMD_MANUFACT: */
- case 0x01:
- info->flash_id = FLASH_MAN_AMD;
- break;
- /* case FUJ_MANUFACT: */
- case 0x04:
- info->flash_id = FLASH_MAN_FUJ;
- break;
- /* case STM_MANUFACT: */
- case 0x20:
- info->flash_id = FLASH_MAN_STM;
- break;
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
- value = addr[1]; /* device ID */
-
- switch ( value )
- {
- case STM_ID_F040B:
- case AMD_ID_F040B:
- info->flash_id += FLASH_AM040; /* 4 Mbits = 512k * 8 */
- info->sector_count = 8;
- info->size = 0x00080000;
- break;
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
- }
-
- /* set up sector start adress table */
- for (i = 0; i < info->sector_count; i++)
- {
- info->start[i] = base + (i * 0x00010000);
- }
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++)
- {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- addr = (volatile unsigned char *)(info->start[i]);
- info->protect[i] = addr[2] & 1;
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if ( info->flash_id != FLASH_UNKNOWN )
- {
- addr = (volatile unsigned char *)info->start[0];
-
- *addr = 0xF0; /* reset bank */
- }
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int
-flash_erase (flash_info_t *info,
- int s_first,
- int s_last)
-{
- volatile unsigned char *addr = (volatile unsigned char *)(info->start[0]);
- int flag, prot, sect, l_sect;
- ulong start, now, last;
-
- if ( (s_first < 0) || (s_first > s_last) )
- {
- if ( info->flash_id == FLASH_UNKNOWN )
- {
- printf ("- missing\n");
- }
- else
- {
- printf ("- no sectors to erase\n");
- }
- return ( 1 );
- }
-
- if ( (info->flash_id == FLASH_UNKNOWN) ||
- (info->flash_id > FLASH_AMD_COMP) )
- {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return ( 1 );
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect)
- {
- if ( info->protect[sect] )
- {
- prot++;
- }
- }
-
- if ( prot )
- {
- printf ("- Warning: %d protected sectors will not be erased!\n", prot);
- }
- else
- {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x0555] = 0xAA;
- addr[0x02AA] = 0x55;
- addr[0x0555] = 0x80;
- addr[0x0555] = 0xAA;
- addr[0x02AA] = 0x55;
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++)
- {
- if (info->protect[sect] == 0) /* not protected */
- {
- addr = (volatile unsigned char *)(info->start[sect]);
- addr[0] = 0x30;
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if ( flag )
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if ( l_sect < 0 )
- goto DONE;
-
- start = get_timer (0);
- last = start;
- addr = (volatile unsigned char *)(info->start[l_sect]);
- while ( (addr[0] & 0x80) != 0x80 )
- {
- if ( (now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT )
- {
- printf ("Timeout\n");
- return ( 1 );
- }
- /* show that we're waiting */
- if ( (now - last) > 1000 ) /* every second */
- {
- putc ('.');
- last = now;
- }
- }
-
-DONE:
- /* reset to read mode */
- addr = (volatile unsigned char *)info->start[0];
- addr[0] = 0xF0; /* reset bank */
-
- printf (" done\n");
-
- return ( 0 );
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int
-write_buff (flash_info_t *info,
- uchar *src,
- ulong addr,
- ulong cnt)
-{
- ulong cp, wp, data;
- uchar bdata;
- int i, l, rc;
-
- if ( (info->flash_id & FLASH_TYPEMASK) == FLASH_AM040 )
- {
- /* Width of the data bus: 8 bits */
-
- wp = addr;
-
- while ( cnt )
- {
- bdata = *src++;
-
- if ( (rc = write_byte(info, wp, bdata)) != 0 )
- {
- return (rc);
- }
-
- ++wp;
- --cnt;
- }
-
- return ( 0 );
- }
- else
- {
- /* Width of the data bus: 32 bits */
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ( (l = addr - wp) != 0 )
- {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp)
- {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i)
- {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp)
- {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ( (rc = write_word(info, wp, data)) != 0 )
- {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while ( cnt >= 4 )
- {
- data = 0;
- for (i=0; i<4; ++i)
- {
- data = (data << 8) | *src++;
- }
- if ( (rc = write_word(info, wp, data)) != 0 )
- {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if ( cnt == 0 )
- {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp)
- {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<4; ++i, ++cp)
- {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_word(info, wp, data));
- }
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int
-write_word (flash_info_t *info,
- ulong dest,
- ulong data)
-{
- vu_long *addr = (vu_long*)(info->start[0]);
- ulong start;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ( (*((vu_long *)dest) & data) != data )
- {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
- addr[0x0555] = 0x00A000A0;
-
- *((vu_long *)dest) = data;
-
- /* re-enable interrupts if necessary */
- if ( flag )
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ( (*((vu_long *)dest) & 0x00800080) != (data & 0x00800080) )
- {
- if ( get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT )
- {
- return (1);
- }
- }
-
- return (0);
-}
-
-/*-----------------------------------------------------------------------
- * Write a byte to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int
-write_byte (flash_info_t *info,
- ulong dest,
- uchar data)
-{
- volatile unsigned char *addr = (volatile unsigned char *)(info->start[0]);
- ulong start;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ( (*((volatile unsigned char *)dest) & data) != data )
- {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x0555] = 0xAA;
- addr[0x02AA] = 0x55;
- addr[0x0555] = 0xA0;
-
- *((volatile unsigned char *)dest) = data;
-
- /* re-enable interrupts if necessary */
- if ( flag )
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ( (*((volatile unsigned char *)dest) & 0x80) != (data & 0x80) )
- {
- if ( get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT )
- {
- return (1);
- }
- }
-
- return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
diff --git a/board/LEOX/elpt860/u-boot.lds b/board/LEOX/elpt860/u-boot.lds
deleted file mode 100644
index c5e57ec..0000000
--- a/board/LEOX/elpt860/u-boot.lds
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
-**=====================================================================
-**
-** Copyright (C) 2000, 2001, 2002, 2003
-** The LEOX team <team@leox.org>, http://www.leox.org
-**
-** LEOX.org is about the development of free hardware and software resources
-** for system on chip.
-**
-** Description: U-Boot port on the LEOX's ELPT860 CPU board
-** ~~~~~~~~~~~
-**
-**=====================================================================
-**
- * SPDX-License-Identifier: GPL-2.0+
-**
-**=====================================================================
-*/
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text*)
- arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- common/built-in.o (.text*)
- arch/powerpc/cpu/mpc8xx/built-in.o (.text*)
- board/LEOX/elpt860/built-in.o (.text*)
- arch/powerpc/lib/built-in.o (.text*)
-
- . = env_offset;
- common/env_embedded.o (.text*)
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
diff --git a/board/LEOX/elpt860/u-boot.lds.debug b/board/LEOX/elpt860/u-boot.lds.debug
deleted file mode 100644
index ce81046..0000000
--- a/board/LEOX/elpt860/u-boot.lds.debug
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
-**=====================================================================
-**
-** Copyright (C) 2000, 2001, 2002, 2003
-** The LEOX team <team@leox.org>, http://www.leox.org
-**
-** LEOX.org is about the development of free hardware and software resources
-** for system on chip.
-**
-** Description: U-Boot port on the LEOX's ELPT860 CPU board
-** ~~~~~~~~~~~
-**
-**=====================================================================
-**
- * SPDX-License-Identifier: GPL-2.0+
-**
-**=====================================================================
-*/
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
-
- . = env_offset;
- common/env_embedded.o (.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
diff --git a/configs/ELPT860_defconfig b/configs/ELPT860_defconfig
deleted file mode 100644
index d02b313..0000000
--- a/configs/ELPT860_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_8xx=y
-CONFIG_TARGET_ELPT860=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 8bd7056..426cadc 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+ELPT860 powerpc mpc8xx - - The LEOX team <team@leox.org>
hmi1001 powerpc mpc5xxx - -
mucmc52 powerpc mpc5xxx - - Heiko Schocher <hs@denx.de>
uc101 powerpc mpc5xxx - - Heiko Schocher <hs@denx.de>
diff --git a/include/commproc.h b/include/commproc.h
index 3e19603..af67878 100644
--- a/include/commproc.h
+++ b/include/commproc.h
@@ -456,32 +456,6 @@ typedef struct scc_enet {
#define SICR_ENET_CLKRT ((uint)0x00002c00)
#endif /* CONFIG_BSEIP */
-/*** ELPT860 *********************************************************/
-
-#ifdef CONFIG_ELPT860
-/* Bits in parallel I/O port registers that have to be set/cleared
- * to configure the pins for SCC1 use.
- */
-# define PROFF_ENET PROFF_SCC1
-# define CPM_CR_ENET CPM_CR_CH_SCC1
-# define SCC_ENET 0
-
-# define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */
-# define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */
-# define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
-# define PA_ENET_TCLK ((ushort)0x0200) /* PA 6 */
-
-# define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */
-# define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */
-# define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */
-
-/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK1) to
- * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
- */
-# define SICR_ENET_MASK ((uint)0x000000FF)
-# define SICR_ENET_CLKRT ((uint)0x00000025)
-#endif /* CONFIG_ELPT860 */
-
/*** ESTEEM 192E **************************************************/
#ifdef CONFIG_ESTEEM192E
/* ESTEEM192E
diff --git a/include/configs/ELPT860.h b/include/configs/ELPT860.h
deleted file mode 100644
index a9d62c8..0000000
--- a/include/configs/ELPT860.h
+++ /dev/null
@@ -1,374 +0,0 @@
-/*
-**=====================================================================
-**
-** Copyright (C) 2000, 2001, 2002, 2003
-** The LEOX team <team@leox.org>, http://www.leox.org
-**
-** LEOX.org is about the development of free hardware and software resources
-** for system on chip.
-**
-** Description: U-Boot port on the LEOX's ELPT860 CPU board
-** ~~~~~~~~~~~
-**
-**=====================================================================
-**
- * SPDX-License-Identifier: GPL-2.0+
-**
-**=====================================================================
-*/
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC860 1 /* It's a MPC860, in fact a 860T CPU */
-#define CONFIG_MPC860T 1
-#define CONFIG_ELPT860 1 /* ...on a LEOX's ELPT860 CPU board */
-
-#define CONFIG_SYS_TEXT_BASE 0x02000000
-
-#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-
-#define CONFIG_CLOCKS_IN_MHZ 1 /* Clock passed to Linux (<2.4.5) in MHz */
-#define CONFIG_8xx_GCLK_FREQ 50000000 /* MPC860T runs@50MHz */
-
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
-
-/* BOOT arguments */
-#define CONFIG_PREBOOT \
- "echo;" \
- "echo Type \"run nfsboot\" to mount root filesystem over NFS;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "rootargs=setenv rootpath /tftp/${ipaddr}\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:eth0:off panic=1\0" \
- "ramboot=tftp 400000 /home/paugaml/pMulti;" \
- "run ramargs;bootm\0" \
- "nfsboot=tftp 400000 /home/paugaml/uImage;" \
- "run rootargs;run nfsargs;run addip;bootm\0" \
- ""
-#define CONFIG_BOOTCOMMAND "run ramboot"
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-#undef CONFIG_RTC_MPC8xx /* internal RTC MPC8xx unused */
-#define CONFIG_RTC_DS164x 1 /* RTC is a Dallas DS1646 */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DATE
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "LEOX_elpt860: " /* Monitor Command Prompt */
-
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
-
-/*
- * Environment Variables and Storages
- */
-#define CONFIG_ENV_OVERWRITE 1 /* Allow Overwrite of serial# & ethaddr */
-
-#undef CONFIG_ENV_IS_IN_NVRAM /* Environment is in NVRAM */
-#undef CONFIG_ENV_IS_IN_EEPROM /* Environment is in I2C EEPROM */
-#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment is in FLASH */
-
-#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600 bps */
-
-#define CONFIG_ETHADDR 00:01:77:00:60:40
-#define CONFIG_IPADDR 192.168.0.30
-#define CONFIG_NETMASK 255.255.255.0
-
-#define CONFIG_SERVERIP 192.168.0.1
-#define CONFIG_GATEWAYIP 192.168.0.1
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xFF000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0x02000000
-#define CONFIG_SYS_NVRAM_BASE 0x03000000
-
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-# if defined(DEBUG)
-# define CONFIG_SYS_MONITOR_LEN (320 << 10) /* Reserve 320 kB for Monitor */
-# else
-# define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-# endif
-#else
-# if defined(DEBUG)
-# define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-# else
-# define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
-# endif
-#endif
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-# define CONFIG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */
-# define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
-#endif
-
-/*-----------------------------------------------------------------------
- * NVRAM organization
- */
-#define CONFIG_SYS_NVRAM_BASE_ADDR CONFIG_SYS_NVRAM_BASE /* Base address of NVRAM area */
-#define CONFIG_SYS_NVRAM_SIZE ((128*1024)-8) /* clock regs resident in the */
- /* 8 top NVRAM locations */
-
-#if defined(CONFIG_ENV_IS_IN_NVRAM)
-# define CONFIG_ENV_ADDR CONFIG_SYS_NVRAM_BASE /* Base address of NVRAM area */
-# define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
-#endif
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-# define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP)
-#else
-# define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register 11-27
- *-----------------------------------------------------------------------
- * Once-per-Second Interrupt, Alarm Interrupt, RTC freezing enabled, RTC
- * enabled
- */
-#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit - leave PLL multiplication factor unchanged !
- */
-#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK SCCR_EBDF11
-#define CONFIG_SYS_SCCR (SCCR_TBS | \
- SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
- SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
- SCCR_DFALCD00)
-
-/*-----------------------------------------------------------------------
- * Chip Selects + SDRAM timings + Memory Periodic Timer Prescaler
- *-----------------------------------------------------------------------
- *
- */
-#ifdef DEBUG
-# define CONFIG_SYS_DER 0xFFE7400F /* Debug Enable Register */
-#else
-# define CONFIG_SYS_DER 0
-#endif
-
-/*
- * Init Memory Controller:
- * ~~~~~~~~~~~~~~~~~~~~~~
- *
- * BR0 and OR0 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CONFIG_SYS_PRELIM_OR_AM 0xFF000000 /* 16 MB between each CSx */
-
-/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 0, SCY = 8, EHTR = 0 */
-#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV2 | OR_BI | OR_SCY_8_CLK)
-
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
-
-/*
- * BR1 and OR1 (SDRAM)
- *
- */
-#define SDRAM_BASE1_PRELIM CONFIG_SYS_SDRAM_BASE /* SDRAM bank #0 */
-#define SDRAM_MAX_SIZE 0x02000000 /* 32 MB MAX for CS1 */
-
-/* SDRAM timing: */
-#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000000
-
-#define CONFIG_SYS_OR1_PRELIM ((2 * CONFIG_SYS_PRELIM_OR_AM) | CONFIG_SYS_OR_TIMING_SDRAM )
-#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-/*
- * BR2 and OR2 (NVRAM)
- *
- */
-#define NVRAM_BASE1_PRELIM CONFIG_SYS_NVRAM_BASE /* NVRAM bank #0 */
-#define NVRAM_MAX_SIZE 0x00020000 /* 128 KB MAX for CS2 */
-
-#define CONFIG_SYS_OR2_PRELIM 0xFFF80160
-#define CONFIG_SYS_BR2_PRELIM ((NVRAM_BASE1_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */
-
-/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
-#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
-#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-/* 9 column SDRAM */
-#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-#endif /* __CONFIG_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [U-Boot] [PATCH 04/26] mpc8xx: remove KUP4X, KUP4K board support
2014-12-15 14:26 [U-Boot] [PATCH 0/26] Start removing non-generic boards Masahiro Yamada
` (2 preceding siblings ...)
2014-12-15 14:26 ` [U-Boot] [PATCH 03/26] mpc8xx: remove ELPT860 board support Masahiro Yamada
@ 2014-12-15 14:26 ` Masahiro Yamada
2015-01-05 18:20 ` Tom Rini
2014-12-15 14:26 ` [U-Boot] [PATCH 05/26] mpc8xx: remove SPD823TS " Masahiro Yamada
` (23 subsequent siblings)
27 siblings, 1 reply; 55+ messages in thread
From: Masahiro Yamada @ 2014-12-15 14:26 UTC (permalink / raw)
To: u-boot
These boards are still non-generic boards.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Klaus Heydeck <heydeck@kieback-peter.de>
---
arch/powerpc/cpu/mpc8xx/Kconfig | 8 -
arch/powerpc/cpu/mpc8xx/cpu.c | 11 -
board/kup/common/flash.c | 499 ---------------------------------
board/kup/common/kup.c | 68 -----
board/kup/common/kup.h | 40 ---
board/kup/common/load_sernum_ethaddr.c | 78 ------
board/kup/common/pcmcia.c | 221 ---------------
board/kup/kup4k/Kconfig | 12 -
board/kup/kup4k/MAINTAINERS | 6 -
board/kup/kup4k/Makefile | 8 -
board/kup/kup4k/kup4k.c | 289 -------------------
board/kup/kup4k/u-boot.lds.debug | 121 --------
board/kup/kup4x/Kconfig | 12 -
board/kup/kup4x/MAINTAINERS | 6 -
board/kup/kup4x/Makefile | 8 -
board/kup/kup4x/kup4x.c | 185 ------------
board/kup/kup4x/u-boot.lds | 82 ------
board/kup/kup4x/u-boot.lds.debug | 121 --------
configs/KUP4K_defconfig | 3 -
configs/KUP4X_defconfig | 3 -
doc/README.scrapyard | 2 +
include/commproc.h | 30 --
include/configs/KUP4K.h | 488 --------------------------------
include/configs/KUP4X.h | 440 -----------------------------
include/status_led.h | 16 --
25 files changed, 2 insertions(+), 2755 deletions(-)
delete mode 100644 board/kup/common/flash.c
delete mode 100644 board/kup/common/kup.c
delete mode 100644 board/kup/common/kup.h
delete mode 100644 board/kup/common/load_sernum_ethaddr.c
delete mode 100644 board/kup/common/pcmcia.c
delete mode 100644 board/kup/kup4k/Kconfig
delete mode 100644 board/kup/kup4k/MAINTAINERS
delete mode 100644 board/kup/kup4k/Makefile
delete mode 100644 board/kup/kup4k/kup4k.c
delete mode 100644 board/kup/kup4k/u-boot.lds.debug
delete mode 100644 board/kup/kup4x/Kconfig
delete mode 100644 board/kup/kup4x/MAINTAINERS
delete mode 100644 board/kup/kup4x/Makefile
delete mode 100644 board/kup/kup4x/kup4x.c
delete mode 100644 board/kup/kup4x/u-boot.lds
delete mode 100644 board/kup/kup4x/u-boot.lds.debug
delete mode 100644 configs/KUP4K_defconfig
delete mode 100644 configs/KUP4X_defconfig
delete mode 100644 include/configs/KUP4K.h
delete mode 100644 include/configs/KUP4X.h
diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig
index 30f8533..7fa5b0b 100644
--- a/arch/powerpc/cpu/mpc8xx/Kconfig
+++ b/arch/powerpc/cpu/mpc8xx/Kconfig
@@ -37,12 +37,6 @@ config TARGET_RRVISION
config TARGET_SPD823TS
bool "Support SPD823TS"
-config TARGET_KUP4K
- bool "Support KUP4K"
-
-config TARGET_KUP4X
- bool "Support KUP4X"
-
config TARGET_TQM823L
bool "Support TQM823L"
@@ -86,8 +80,6 @@ source "board/cogent/Kconfig"
source "board/esteem192e/Kconfig"
source "board/ip860/Kconfig"
source "board/ivm/Kconfig"
-source "board/kup/kup4k/Kconfig"
-source "board/kup/kup4x/Kconfig"
source "board/lwmon/Kconfig"
source "board/netvia/Kconfig"
source "board/r360mpi/Kconfig"
diff --git a/arch/powerpc/cpu/mpc8xx/cpu.c b/arch/powerpc/cpu/mpc8xx/cpu.c
index eb4432f..9967664 100644
--- a/arch/powerpc/cpu/mpc8xx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xx/cpu.c
@@ -598,17 +598,6 @@ void reset_8xx_watchdog (volatile immap_t * immr)
immr->im_ioport.iop_paodr &= ~(WATCHDOG_BIT); /* active output */
immr->im_ioport.iop_padat ^= WATCHDOG_BIT; /* Toggle WDI */
-# elif defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X)
- /*
- * The KUP4 boards uses a TPS3705 Watchdog
- * with the trigger pin connected to port PA.5
- */
-# define WATCHDOG_BIT 0x0400
- immr->im_ioport.iop_papar &= ~(WATCHDOG_BIT); /* GPIO */
- immr->im_ioport.iop_padir |= WATCHDOG_BIT; /* Output */
- immr->im_ioport.iop_paodr &= ~(WATCHDOG_BIT); /* active output */
-
- immr->im_ioport.iop_padat ^= WATCHDOG_BIT; /* Toggle WDI */
# else
/*
* All other boards use the MPC8xx Internal Watchdog
diff --git a/board/kup/common/flash.c b/board/kup/common/flash.c
deleted file mode 100644
index 77c7b6c..0000000
--- a/board/kup/common/flash.c
+++ /dev/null
@@ -1,499 +0,0 @@
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-#ifndef CONFIG_ENV_ADDR
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-#endif
-
-#define CONFIG_FLASH_16BIT
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- unsigned long size_b0;
- int i;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0<<20);
- }
-
-
- /* Remap FLASH according to real size */
- memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
- memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V | BR_PS_16;
-
- /* Re-do sizing to get full correct info */
- size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[0]);
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
- &flash_info[0]);
-#endif
-
- flash_info[0].size = size_b0;
-
- return (size_b0);
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
- break;
- case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
- break;
- case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
- break;
- case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
- return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
- short i;
- ulong value;
- ulong base = (ulong)addr;
-
- /* Write auto select command: read Manufacturer ID */
- vu_short *s_addr=(vu_short*)addr;
- s_addr[0x5555] = 0x00AA;
- s_addr[0x2AAA] = 0x0055;
- s_addr[0x5555] = 0x0090;
-
- value = s_addr[0];
- value = value|(value<<16);
-
- switch (value) {
- case AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
- case FUJ_MANUFACT:
- info->flash_id = FLASH_MAN_FUJ;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
- value = s_addr[1];
- value = value|(value<<16);
-
- switch (value) {
- case FUJI_ID_29F800BA:
- info->flash_id += FLASH_AM400T;
- info->sector_count = 19;
- info->size = 0x00100000;
- break; /* => 1 MB */
- case AMD_ID_LV800T:
- info->flash_id += FLASH_AM800T;
- info->sector_count = 19;
- info->size = 0x00100000;
- break; /* => 1 MB */
- case AMD_ID_LV800B:
- info->flash_id += FLASH_AM800B;
- info->sector_count = 19;
- info->size = 0x00100000;
- break; /* => 1 MB */
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
- }
-
- /* set up sector start address table */
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000) - 0x00030000;
- }
-
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- s_addr = (volatile unsigned short *)(info->start[i]);
- info->protect[i] = s_addr[2] & 1;
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- s_addr = (volatile unsigned short *)info->start[0];
- *s_addr = 0x00F0; /* reset bank */
- }
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- vu_long *addr = (vu_long*)(info->start[0]);
- int flag, prot, sect;
- ulong start, now, last;
-#ifdef CONFIG_FLASH_16BIT
- vu_short *s_addr = (vu_short*)addr;
-#endif
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-/*#ifndef CONFIG_FLASH_16BIT
- ulong type;
- type = (info->flash_id & FLASH_VENDMASK);
- if ((type != FLASH_MAN_SST) && (type != FLASH_MAN_STM)) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return;
- }
-#endif*/
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- start = get_timer (0);
- last = start;
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
-#ifdef CONFIG_FLASH_16BIT
- vu_short *s_sect_addr = (vu_short*)(info->start[sect]);
-#else
- vu_long *sect_addr = (vu_long*)(info->start[sect]);
-#endif
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
-#ifdef CONFIG_FLASH_16BIT
-
- /*printf("\ns_sect_addr=%x",s_sect_addr);*/
- s_addr[0x5555] = 0x00AA;
- s_addr[0x2AAA] = 0x0055;
- s_addr[0x5555] = 0x0080;
- s_addr[0x5555] = 0x00AA;
- s_addr[0x2AAA] = 0x0055;
- s_sect_addr[0] = 0x0030;
-#else
- addr[0x5555] = 0x00AA00AA;
- addr[0x2AAA] = 0x00550055;
- addr[0x5555] = 0x00800080;
- addr[0x5555] = 0x00AA00AA;
- addr[0x2AAA] = 0x00550055;
- sect_addr[0] = 0x00300030;
-#endif
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
-#ifdef CONFIG_FLASH_16BIT
- while ((s_sect_addr[0] & 0x0080) != 0x0080) {
-#else
- while ((sect_addr[0] & 0x00800080) != 0x00800080) {
-#endif
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
- }
- }
-
- /* reset to read mode */
- addr = (volatile unsigned long *)info->start[0];
-#ifdef CONFIG_FLASH_16BIT
- s_addr[0] = 0x00F0; /* reset bank */
-#else
- addr[0] = 0x00F000F0; /* reset bank */
-#endif
-
- printf (" done\n");
- return 0;
-}
-
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i=0; i<4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_word(info, wp, data));
-}
-
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
- vu_long *addr = (vu_long*)(info->start[0]);
-
-#ifdef CONFIG_FLASH_16BIT
- vu_short high_data;
- vu_short low_data;
- vu_short *s_addr = (vu_short*)addr;
-#endif
- ulong start;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((vu_long *)dest) & data) != data) {
- return (2);
- }
-
-#ifdef CONFIG_FLASH_16BIT
- /* Write the 16 higher-bits */
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- high_data = ((data>>16) & 0x0000ffff);
-
- s_addr[0x5555] = 0x00AA;
- s_addr[0x2AAA] = 0x0055;
- s_addr[0x5555] = 0x00A0;
-
- *((vu_short *)dest) = high_data;
-
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((*((vu_short *)dest) & 0x0080) != (high_data & 0x0080)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
-
-
- /* Write the 16 lower-bits */
-#endif
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-#ifdef CONFIG_FLASH_16BIT
- dest += 0x2;
- low_data = (data & 0x0000ffff);
-
- s_addr[0x5555] = 0x00AA;
- s_addr[0x2AAA] = 0x0055;
- s_addr[0x5555] = 0x00A0;
- *((vu_short *)dest) = low_data;
-
-#else
- addr[0x5555] = 0x00AA00AA;
- addr[0x2AAA] = 0x00550055;
- addr[0x5555] = 0x00A000A0;
- *((vu_long *)dest) = data;
-#endif
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
-
-#ifdef CONFIG_FLASH_16BIT
- while ((*((vu_short *)dest) & 0x0080) != (low_data & 0x0080)) {
-#else
- while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
-#endif
-
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- return (0);
-}
diff --git a/board/kup/common/kup.c b/board/kup/common/kup.c
deleted file mode 100644
index 03ab018..0000000
--- a/board/kup/common/kup.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * (C) Copyright 2004
- * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck at kieback-peter.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-#include "kup.h"
-#include <asm/io.h>
-
-
-int misc_init_f(void)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile sysconf8xx_t *siu = &immap->im_siu_conf;
-
- while (in_be32(&siu->sc_sipend) & 0x20000000) {
- debug("waiting for 5V VCC\n");
- }
-
- /* RS232 / RS485 default is RS232 */
- clrbits_be16(&immap->im_ioport.iop_padat, PA_RS485);
- clrbits_be16(&immap->im_ioport.iop_papar, PA_RS485);
- clrbits_be16(&immap->im_ioport.iop_paodr, PA_RS485);
- setbits_be16(&immap->im_ioport.iop_padir, PA_RS485);
-
- /* IO Reset min 1 msec */
- setbits_be16(&immap->im_ioport.iop_padat,
- (PA_RESET_IO_01 | PA_RESET_IO_02));
- clrbits_be16(&immap->im_ioport.iop_papar,
- (PA_RESET_IO_01 | PA_RESET_IO_02));
- clrbits_be16(&immap->im_ioport.iop_paodr,
- (PA_RESET_IO_01 | PA_RESET_IO_02));
- setbits_be16(&immap->im_ioport.iop_padir,
- (PA_RESET_IO_01 | PA_RESET_IO_02));
- udelay(1000);
- clrbits_be16(&immap->im_ioport.iop_padat,
- (PA_RESET_IO_01 | PA_RESET_IO_02));
- return (0);
-}
-
-#ifdef CONFIG_IDE_LED
-void ide_led(uchar led, uchar status)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-
- /* We have one led for both pcmcia slots */
- if (status)
- clrbits_be16(&immap->im_ioport.iop_padat, PA_LED_YELLOW);
- else
- setbits_be16(&immap->im_ioport.iop_padat, PA_LED_YELLOW);
-}
-#endif
-
-void poweron_key(void)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-
- clrbits_be16(&immap->im_ioport.iop_pcpar, PC_SWITCH1);
- clrbits_be16(&immap->im_ioport.iop_pcdir, PC_SWITCH1);
-
- if (in_be16(&immap->im_ioport.iop_pcdat) & (PC_SWITCH1))
- setenv("key1", "off");
- else
- setenv("key1", "on");
-}
diff --git a/board/kup/common/kup.h b/board/kup/common/kup.h
deleted file mode 100644
index a1369ae..0000000
--- a/board/kup/common/kup.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * (C) Copyright 2004
- * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck at kieback-peter.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __KUP_H
-#define __KUP_H
-
-#define PA_8 0x0080
-#define PA_9 0x0040
-#define PA_10 0x0020
-#define PA_11 0x0010
-#define PA_12 0x0008
-
-#define PB_14 0x00020000
-#define PB_15 0x00010000
-#define PB_16 0x00008000
-#define PB_17 0x00004000
-
-#define PC_4 0x0800
-#define PC_5 0x0400
-#define PC_9 0x0040
-
-#define PA_RS485 PA_11 /* SCC1: 0=RS232 1=RS485 */
-#define PA_LED_YELLOW PA_8
-#define PA_RESET_IO_01 PA_9 /* Reset left IO */
-#define PA_RESET_IO_02 PA_10 /* Reset right IO */
-#define PB_PROG_IO_01 PB_15 /* Program left IO */
-#define PB_PROG_IO_02 PB_16 /* Program right IO */
-#define BP_USB_VCC PB_14 /* VCC for USB devices 0=vcc on, 1=vcc off */
-#define PB_LCD_PWM PB_17 /* PB 17 */
-#define PC_SWITCH1 PC_9 /* Reboot switch */
-
-
-extern void poweron_key(void);
-extern void load_sernum_ethaddr(void);
-
-#endif /* __KUP_H */
diff --git a/board/kup/common/load_sernum_ethaddr.c b/board/kup/common/load_sernum_ethaddr.c
deleted file mode 100644
index 20fe799..0000000
--- a/board/kup/common/load_sernum_ethaddr.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-/*-----------------------------------------------------------------------
- * Process Hardware Information Block:
- *
- * If we boot on a system fresh from factory, check if the Hardware
- * Information Block exists and save the information it contains.
- *
- * The KUP Hardware Information Block is defined as
- * follows:
- * - located in first flash bank
- * - starts at offset CONFIG_SYS_HWINFO_OFFSET
- * - size CONFIG_SYS_HWINFO_SIZE
- *
- * Internal structure:
- * - sequence of ASCII character lines
- * - fields separated by <CR><LF>
- * - last field terminated by NUL character (0x00)
- *
- * Fields in Hardware Information Block:
- * 1) Module Type
- * 2) MAC Address
- * 3) ....
- */
-
-
-#define ETHADDR_TOKEN "ethaddr="
-#define LCD_TOKEN "lcd="
-
-void load_sernum_ethaddr (void)
-{
- unsigned char *hwi;
- char *var;
- unsigned char hwi_stack[CONFIG_SYS_HWINFO_SIZE];
- char *p;
-
- hwi = (unsigned char *) (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_HWINFO_OFFSET);
- if (*((unsigned long *) hwi) != (unsigned long) CONFIG_SYS_HWINFO_MAGIC) {
- printf ("HardwareInfo not found!\n");
- return;
- }
- memcpy (hwi_stack, hwi, CONFIG_SYS_HWINFO_SIZE);
-
- /*
- ** ethaddr
- */
- var = strstr ((char *)hwi_stack, ETHADDR_TOKEN);
- if (var) {
- var += sizeof (ETHADDR_TOKEN) - 1;
- p = strchr (var, '\r');
- if ((unsigned char *)p < hwi + CONFIG_SYS_HWINFO_SIZE) {
- *p = '\0';
- setenv ("ethaddr", var);
- *p = '\r';
- }
- }
- /*
- ** lcd
- */
- var = strstr ((char *)hwi_stack, LCD_TOKEN);
- if (var) {
- var += sizeof (LCD_TOKEN) - 1;
- p = strchr (var, '\r');
- if ((unsigned char *)p < hwi + CONFIG_SYS_HWINFO_SIZE) {
- *p = '\0';
- setenv ("lcd", var);
- *p = '\r';
- }
- }
-}
diff --git a/board/kup/common/pcmcia.c b/board/kup/common/pcmcia.c
deleted file mode 100644
index 61ba586..0000000
--- a/board/kup/common/pcmcia.c
+++ /dev/null
@@ -1,221 +0,0 @@
-#include <common.h>
-#include <mpc8xx.h>
-#include <pcmcia.h>
-
-#undef CONFIG_PCMCIA
-
-#if defined(CONFIG_CMD_PCMCIA)
-#define CONFIG_PCMCIA
-#endif
-
-#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
-#define CONFIG_PCMCIA
-#endif
-
-#ifdef CONFIG_PCMCIA
-
-#define PCMCIA_BOARD_MSG "KUP"
-
-#define KUP4K_PCMCIA_B_3V3 (0x00020000)
-
-int pcmcia_hardware_enable(int slot)
-{
- volatile cpm8xx_t *cp;
- volatile pcmconf8xx_t *pcmp;
- volatile sysconf8xx_t *sysp;
- uint reg, mask;
-
- debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
-
- udelay(10000);
-
- sysp = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf));
- pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
- cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
-
- /*
- * Configure SIUMCR to enable PCMCIA port B
- * (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
- */
- sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */
-
- /* clear interrupt state, and disable interrupts */
- pcmp->pcmc_pscr = PCMCIA_MASK(slot);
- pcmp->pcmc_per &= ~PCMCIA_MASK(slot);
-
- /*
- * Disable interrupts, DMA, and PCMCIA buffers
- * (isolate the interface) and assert RESET signal
- */
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = 0;
- reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(slot) = reg;
- udelay(2500);
-
- /*
- * Configure Port B pins for
- * 3 Volts enable
- */
- if (slot) { /* Slot A is built-in */
- cp->cp_pbdir |= KUP4K_PCMCIA_B_3V3;
- cp->cp_pbpar &= ~KUP4K_PCMCIA_B_3V3;
- /* remove all power */
- cp->cp_pbdat |= KUP4K_PCMCIA_B_3V3; /* active low */
- }
- /*
- * Make sure there is a card in the slot, then configure the interface.
- */
- udelay(10000);
- debug ("[%d] %s: PIPR(%p)=0x%x\n",
- __LINE__,__FUNCTION__,
- &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
- if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
- printf (" No Card found\n");
- return (1);
- }
-
- /*
- * Power On.
- */
- printf("%s Slot %c:", slot ? "" : "\n", 'A' + slot);
- mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
- reg = pcmp->pcmc_pipr;
- debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
- reg,
- (reg&PCMCIA_VS1(slot))?"n":"ff",
- (reg&PCMCIA_VS2(slot))?"n":"ff");
- if ((reg & mask) == mask) {
- puts (" 5.0V card found: NOT SUPPORTED !!!\n");
- } else {
- if(slot)
- cp->cp_pbdat &= ~KUP4K_PCMCIA_B_3V3;
- puts (" 3.3V card found: ");
- }
-#if 0
- /* VCC switch error flag, PCMCIA slot INPACK_ pin */
- cp->cp_pbdir &= ~(0x0020 | 0x0010);
- cp->cp_pbpar &= ~(0x0020 | 0x0010);
- udelay(500000);
-#endif
- debug ("Enable PCMCIA buffers and stop RESET\n");
- reg = PCMCIA_PGCRX(slot);
- reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(slot) = reg;
-
- udelay(250000); /* some cards need >150 ms to come up :-( */
-
- debug ("# hardware_enable done\n");
-
- return (0);
-}
-
-
-#if defined(CONFIG_CMD_PCMCIA)
-int pcmcia_hardware_disable(int slot)
-{
- volatile immap_t *immap;
- volatile cpm8xx_t *cp;
- volatile pcmconf8xx_t *pcmp;
- u_long reg;
-
- debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
-
- immap = (immap_t *)CONFIG_SYS_IMMR;
- pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
- cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
-
- /* remove all power */
- if (slot)
- cp->cp_pbdat |= KUP4K_PCMCIA_B_3V3;
-
- /* Configure PCMCIA General Control Register */
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = 0;
- reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(slot) = reg;
-
- udelay(10000);
-
- return (0);
-}
-#endif
-
-
-int pcmcia_voltage_set(int slot, int vcc, int vpp)
-{
- volatile cpm8xx_t *cp;
- volatile pcmconf8xx_t *pcmp;
- u_long reg;
-
- debug ("voltage_set: " \
- PCMCIA_BOARD_MSG \
- " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
- 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
-
- if (!slot) /* Slot A is not configurable */
- return 0;
-
- pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
- cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
-
- /*
- * Disable PCMCIA buffers (isolate the interface)
- * and assert RESET signal
- */
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = PCMCIA_PGCRX(slot);
- reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(slot) = reg;
- udelay(500);
-
- debug ("PCMCIA power OFF\n");
- /*
- * Configure Port B pins for
- * 3 Volts enable
- */
- cp->cp_pbdir |= KUP4K_PCMCIA_B_3V3;
- cp->cp_pbpar &= ~KUP4K_PCMCIA_B_3V3;
- /* remove all power */
- cp->cp_pbdat |= KUP4K_PCMCIA_B_3V3; /* active low */
-
- switch(vcc) {
- case 0: break;
- case 33:
- cp->cp_pbdat &= ~KUP4K_PCMCIA_B_3V3;
- debug ("PCMCIA powered at 3.3V\n");
- break;
- case 50:
- debug ("PCMCIA: 5Volt vcc not supported\n");
- break;
- default:
- puts("PCMCIA: vcc not supported");
- break;
- }
- udelay(10000);
- /* Checking supported voltages */
-
- debug ("PIPR: 0x%x --> %s\n",
- pcmp->pcmc_pipr,
- (pcmp->pcmc_pipr & (0x80000000 >> (slot << 4)))
- ? "only 5 V --> NOT SUPPORTED"
- : "can do 3.3V");
-
-
- debug ("Enable PCMCIA buffers and stop RESET\n");
- reg = PCMCIA_PGCRX(slot);
- reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(slot) = reg;
- udelay(500);
-
- debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
- slot+'A');
- return (0);
-}
-
-#endif /* CONFIG_PCMCIA */
diff --git a/board/kup/kup4k/Kconfig b/board/kup/kup4k/Kconfig
deleted file mode 100644
index 903c341..0000000
--- a/board/kup/kup4k/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_KUP4K
-
-config SYS_BOARD
- default "kup4k"
-
-config SYS_VENDOR
- default "kup"
-
-config SYS_CONFIG_NAME
- default "KUP4K"
-
-endif
diff --git a/board/kup/kup4k/MAINTAINERS b/board/kup/kup4k/MAINTAINERS
deleted file mode 100644
index 25d90cf..0000000
--- a/board/kup/kup4k/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-KUP4K BOARD
-M: Klaus Heydeck <heydeck@kieback-peter.de>
-S: Maintained
-F: board/kup/kup4k/
-F: include/configs/KUP4K.h
-F: configs/KUP4K_defconfig
diff --git a/board/kup/kup4k/Makefile b/board/kup/kup4k/Makefile
deleted file mode 100644
index c896fcd..0000000
--- a/board/kup/kup4k/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = kup4k.o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o ../common/pcmcia.o
diff --git a/board/kup/kup4k/kup4k.c b/board/kup/kup4k/kup4k.c
deleted file mode 100644
index 71c6a79..0000000
--- a/board/kup/kup4k/kup4k.c
+++ /dev/null
@@ -1,289 +0,0 @@
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck at kieback-peter.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <libfdt.h>
-#include <mpc8xx.h>
-#include <hwconfig.h>
-#include <i2c.h>
-#include "../common/kup.h"
-#include <asm/io.h>
-
-static unsigned char swapbyte(unsigned char c);
-static int read_diag(void);
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* ----------------------------------------------------------------------- */
-
-#define _NOT_USED_ 0xFFFFFFFF
-
-const uint sdram_table[] = {
- /*
- * Single Read. (Offset 0 in UPMA RAM)
- */
- 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
- 0x1FF77C47, /* last */
-
- /*
- * SDRAM Initialization (offset 5 in UPMA RAM)
- *
- * This is no UPM entry point. The following definition uses
- * the remaining space to establish an initialization
- * sequence, which is executed by a RUN command.
- *
- */
- 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */
-
- /*
- * Burst Read. (Offset 8 in UPMA RAM)
- */
- 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
- 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /*
- * Single Write. (Offset 18 in UPMA RAM)
- */
- 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /*
- * Burst Write. (Offset 20 in UPMA RAM)
- */
- 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
- 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
- _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /*
- * Refresh (Offset 30 in UPMA RAM)
- */
- 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
- 0xFFFFFC84, 0xFFFFFC07, /* last */
- _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /*
- * Exception. (Offset 3c in UPMA RAM)
- */
- 0x7FFFFC07, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
-};
-
-/* ----------------------------------------------------------------------- */
-
-/*
- * Check Board Identity:
- */
-
-int checkboard(void)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- uchar rev,mod,tmp,pcf,ak_rev,ak_mod;
-
- /*
- * Init ChipSelect #4 (CAN + HW-Latch)
- */
- out_be32(&immap->im_memctl.memc_or4, CONFIG_SYS_OR4);
- out_be32(&immap->im_memctl.memc_br4, CONFIG_SYS_BR4);
-
- /*
- * Init ChipSelect #5 (S1D13768)
- */
- out_be32(&immap->im_memctl.memc_or5, CONFIG_SYS_OR5);
- out_be32(&immap->im_memctl.memc_br5, CONFIG_SYS_BR5);
-
- tmp = swapbyte(in_8((unsigned char*) LATCH_ADDR));
- rev = (tmp & 0xF8) >> 3;
- mod = (tmp & 0x07);
-
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-
- if (read_diag())
- gd->flags &= ~GD_FLG_SILENT;
-
- printf("Board: KUP4K Rev %d.%d AK:",rev,mod);
- /*
- * TI Application report: Before using the IO as an input,
- * a high must be written to the IO first
- */
- pcf = 0xFF;
- i2c_write(0x21, 0, 0 , &pcf, 1);
- if (i2c_read(0x21, 0, 0, &pcf, 1)) {
- puts("n/a\n");
- } else {
- ak_rev = (pcf & 0xF8) >> 3;
- ak_mod = (pcf & 0x07);
- printf("%d.%d\n", ak_rev, ak_mod);
- }
- return 0;
-}
-
-/* ----------------------------------------------------------------------- */
-
-
-phys_size_t initdram(int board_type)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- long int size = 0;
- uchar *latch, rev, tmp;
-
- /*
- * Init ChipSelect #4 (CAN + HW-Latch) to determine Hardware Revision
- * Rev 1..6 -> 48 MB RAM; Rev >= 7 -> 96 MB
- */
- out_be32(&immap->im_memctl.memc_or4, CONFIG_SYS_OR4);
- out_be32(&immap->im_memctl.memc_br4, CONFIG_SYS_BR4);
-
- latch = (uchar *)0x90000200;
- tmp = swapbyte(*latch);
- rev = (tmp & 0xF8) >> 3;
-
- upmconfig(UPMA, (uint *) sdram_table,
- sizeof (sdram_table) / sizeof (uint));
-
- out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR);
-
- out_be32(&memctl->memc_mar, 0x00000088);
- /* no refresh yet */
- if(rev >= 7) {
- out_be32(&memctl->memc_mamr,
- CONFIG_SYS_MAMR_9COL & (~(MAMR_PTAE)));
- } else {
- out_be32(&memctl->memc_mamr,
- CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)));
- }
-
- udelay(200);
-
- /* perform SDRAM initializsation sequence */
-
- /* SDRAM bank 0 */
- out_be32(&memctl->memc_mcr, 0x80002105);
- udelay(1);
- out_be32(&memctl->memc_mcr, 0x80002830); /* execute twice */
- udelay(1);
- out_be32(&memctl->memc_mcr, 0x80002106); /* RUN MRS Pattern from loc 6 */
- udelay(1);
-
- /* SDRAM bank 1 */
- out_be32(&memctl->memc_mcr, 0x80004105);
- udelay(1);
- out_be32(&memctl->memc_mcr, 0x80004830); /* execute twice */
- udelay(1);
- out_be32(&memctl->memc_mcr, 0x80004106); /* RUN MRS Pattern from loc 6 */
- udelay(1);
-
- /* SDRAM bank 2 */
- out_be32(&memctl->memc_mcr, 0x80006105);
- udelay(1);
- out_be32(&memctl->memc_mcr, 0x80006830); /* execute twice */
- udelay(1);
- out_be32(&memctl->memc_mcr, 0x80006106); /* RUN MRS Pattern from loc 6 */
- udelay(1);
-
- setbits_be32(&memctl->memc_mamr, MAMR_PTAE); /* enable refresh */
- udelay(1000);
-
- out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR);
- udelay(1000);
- if(rev >= 7) {
- size = 32 * 3 * 1024 * 1024;
- out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_9COL);
- out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_9COL);
- out_be32(&memctl->memc_or2, CONFIG_SYS_OR2_9COL);
- out_be32(&memctl->memc_br2, CONFIG_SYS_BR2_9COL);
- out_be32(&memctl->memc_or3, CONFIG_SYS_OR3_9COL);
- out_be32(&memctl->memc_br3, CONFIG_SYS_BR3_9COL);
- } else {
- size = 16 * 3 * 1024 * 1024;
- out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_8COL);
- out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_8COL);
- out_be32(&memctl->memc_or2, CONFIG_SYS_OR2_8COL);
- out_be32(&memctl->memc_br2, CONFIG_SYS_BR2_8COL);
- out_be32(&memctl->memc_or3, CONFIG_SYS_OR3_8COL);
- out_be32(&memctl->memc_br3, CONFIG_SYS_BR3_8COL);
- }
- return (size);
-}
-
-/* ----------------------------------------------------------------------- */
-
-
-int misc_init_r(void)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-
-#ifdef CONFIG_IDE_LED
- /* Configure PA8 as output port */
- setbits_be16(&immap->im_ioport.iop_padir, PA_8);
- setbits_be16(&immap->im_ioport.iop_paodr, PA_8);
- clrbits_be16(&immap->im_ioport.iop_papar, PA_8);
- setbits_be16(&immap->im_ioport.iop_padat, PA_8); /* turn it off */
-#endif
- load_sernum_ethaddr();
- setenv("hw","4k");
- poweron_key();
- return (0);
-}
-
-
-static int read_diag(void)
-{
- int diag;
- immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-
- clrbits_be16(&immr->im_ioport.iop_pcdir, PC_4); /* input */
- clrbits_be16(&immr->im_ioport.iop_pcpar, PC_4); /* gpio */
- setbits_be16(&immr->im_ioport.iop_pcdir, PC_5); /* output */
- clrbits_be16(&immr->im_ioport.iop_pcpar, PC_4); /* gpio */
- setbits_be16(&immr->im_ioport.iop_pcdat, PC_5); /* 1 */
- udelay(500);
- if (in_be16(&immr->im_ioport.iop_pcdat) & PC_4) {
- clrbits_be16(&immr->im_ioport.iop_pcdat, PC_5);/* 0 */
- udelay(500);
- if(in_be16(&immr->im_ioport.iop_pcdat) & PC_4)
- diag = 0;
- else
- diag = 1;
- } else {
- diag = 0;
- }
- clrbits_be16(&immr->im_ioport.iop_pcdir, PC_5); /* input */
- return (diag);
-}
-
-static unsigned char swapbyte(unsigned char c)
-{
- unsigned char result = 0;
- int i = 0;
-
- for(i = 0; i < 8; ++i) {
- result = result << 1;
- result |= (c & 1);
- c = c >> 1;
- }
- return result;
-}
-
-/*
- * Device Tree Support
- */
-#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
-int ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
-
- return 0;
-}
-#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
diff --git a/board/kup/kup4k/u-boot.lds.debug b/board/kup/kup4k/u-boot.lds.debug
deleted file mode 100644
index 0ea27e8..0000000
--- a/board/kup/kup4k/u-boot.lds.debug
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
-
- . = env_offset;
- common/env_embedded.o(.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
diff --git a/board/kup/kup4x/Kconfig b/board/kup/kup4x/Kconfig
deleted file mode 100644
index eeb5d83..0000000
--- a/board/kup/kup4x/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_KUP4X
-
-config SYS_BOARD
- default "kup4x"
-
-config SYS_VENDOR
- default "kup"
-
-config SYS_CONFIG_NAME
- default "KUP4X"
-
-endif
diff --git a/board/kup/kup4x/MAINTAINERS b/board/kup/kup4x/MAINTAINERS
deleted file mode 100644
index 85159e4..0000000
--- a/board/kup/kup4x/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-KUP4X BOARD
-M: Klaus Heydeck <heydeck@kieback-peter.de>
-S: Maintained
-F: board/kup/kup4x/
-F: include/configs/KUP4X.h
-F: configs/KUP4X_defconfig
diff --git a/board/kup/kup4x/Makefile b/board/kup/kup4x/Makefile
deleted file mode 100644
index 6945943..0000000
--- a/board/kup/kup4x/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = kup4x.o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o ../common/pcmcia.o
diff --git a/board/kup/kup4x/kup4x.c b/board/kup/kup4x/kup4x.c
deleted file mode 100644
index 0e51bd1..0000000
--- a/board/kup/kup4x/kup4x.c
+++ /dev/null
@@ -1,185 +0,0 @@
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck at kieback-peter.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-#include <post.h>
-#include "../common/kup.h"
-#include <asm/io.h>
-
-
-#define _NOT_USED_ 0xFFFFFFFF
-
-const uint sdram_table[] = {
- /*
- * Single Read. (Offset 0 in UPMA RAM)
- */
- 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
- 0x1FF77C47, /* last */
-
- /*
- * SDRAM Initialization (offset 5 in UPMA RAM)
- *
- * This is no UPM entry point. The following definition uses
- * the remaining space to establish an initialization
- * sequence, which is executed by a RUN command.
- *
- */
- 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */
-
- /*
- * Burst Read. (Offset 8 in UPMA RAM)
- */
- 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
- 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /*
- * Single Write. (Offset 18 in UPMA RAM)
- */
- 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /*
- * Burst Write. (Offset 20 in UPMA RAM)
- */
- 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
- 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
- _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /*
- * Refresh (Offset 30 in UPMA RAM)
- */
- 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
- 0xFFFFFC84, 0xFFFFFC07, /* last */
- _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /*
- * Exception. (Offset 3c in UPMA RAM)
- */
- 0x7FFFFC07, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
-};
-
-
-/*
- * Check Board Identity:
- */
-
-int checkboard(void)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- uchar latch, rev, mod;
-
- /*
- * Init ChipSelect #4 (CAN + HW-Latch)
- */
- out_be32(&memctl->memc_or4, 0xFFFF8926);
- out_be32(&memctl->memc_br4, 0x90000401);
-
- latch = in_8( (unsigned char *) LATCH_ADDR);
- rev = (latch & 0xF8) >> 3;
- mod = (latch & 0x03);
-
- printf("Board: KUP4X Rev %d.%d\n", rev, mod);
-
- return 0;
-}
-
-
-phys_size_t initdram(int board_type)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
- upmconfig(UPMA, (uint *) sdram_table,
- sizeof (sdram_table) / sizeof (uint));
-
- out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR);
-
- out_be32(&memctl->memc_mar, 0x00000088);
-
- out_be32(&memctl->memc_mamr,
- CONFIG_SYS_MAMR & (~(MAMR_PTAE))); /* no refresh yet */
-
- udelay(200);
-
- /* perform SDRAM initializsation sequence */
-
- /* SDRAM bank 0 */
- out_be32(&memctl->memc_mcr, 0x80002105);
- udelay(1);
- out_be32(&memctl->memc_mcr, 0x80002830); /* execute twice */
- udelay(1);
- out_be32(&memctl->memc_mcr, 0x80002106); /* RUN MRS Pattern from loc 6 */
- udelay(1);
-
- /* SDRAM bank 1 */
- out_be32(&memctl->memc_mcr, 0x80004105);
- udelay(1);
- out_be32(&memctl->memc_mcr, 0x80004830); /* execute twice */
- udelay(1);
- out_be32(&memctl->memc_mcr, 0x80004106); /* RUN MRS Pattern from loc 6 */
- udelay(1);
-
- /* SDRAM bank 2 */
- out_be32(&memctl->memc_mcr, 0x80006105);
- udelay(1);
- out_be32(&memctl->memc_mcr, 0x80006830); /* execute twice */
- udelay(1);
- out_be32(&memctl->memc_mcr, 0x80006106); /* RUN MRS Pattern from loc 6 */
- udelay(1);
-
- /* SDRAM bank 3 */
- out_be32(&memctl->memc_mcr, 0x8000C105);
- udelay(1);
- out_be32(&memctl->memc_mcr, 0x8000C830); /* execute twice */
- udelay(1);
- out_be32(&memctl->memc_mcr, 0x8000C106); /* RUN MRS Pattern from loc 6 */
- udelay(1);
-
- setbits_be32(&memctl->memc_mamr, MAMR_PTAE); /* enable refresh */
-
- udelay(1000);
- /* 4 x 16 MB */
- out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR);
- udelay(1000);
- out_be32(&memctl->memc_or1, 0xFF000A00);
- out_be32(&memctl->memc_br1, 0x00000081);
- out_be32(&memctl->memc_or2, 0xFE000A00);
- out_be32(&memctl->memc_br2, 0x01000081);
- out_be32(&memctl->memc_or3, 0xFD000A00);
- out_be32(&memctl->memc_br3, 0x02000081);
- out_be32(&memctl->memc_or6, 0xFC000A00);
- out_be32(&memctl->memc_br6, 0x03000081);
- udelay(10000);
-
- return (4 * 16 * 1024 * 1024);
-}
-
-int misc_init_r(void)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-
-#ifdef CONFIG_IDE_LED
- /* Configure PA8 as output port */
- setbits_be16(&immap->im_ioport.iop_padir, PA_8);
- setbits_be16(&immap->im_ioport.iop_paodr, PA_8);
- clrbits_be16(&immap->im_ioport.iop_papar, PA_8);
- setbits_be16(&immap->im_ioport.iop_padat, PA_8); /* turn it off */
-#endif
- load_sernum_ethaddr();
- setenv("hw", "4x");
- poweron_key();
- return 0;
-}
diff --git a/board/kup/kup4x/u-boot.lds b/board/kup/kup4x/u-boot.lds
deleted file mode 100644
index 0eb2fba..0000000
--- a/board/kup/kup4x/u-boot.lds
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- arch/powerpc/cpu/mpc8xx/start.o (.text*)
- arch/powerpc/cpu/mpc8xx/traps.o (.text*)
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
diff --git a/board/kup/kup4x/u-boot.lds.debug b/board/kup/kup4x/u-boot.lds.debug
deleted file mode 100644
index 0ea27e8..0000000
--- a/board/kup/kup4x/u-boot.lds.debug
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
-
- . = env_offset;
- common/env_embedded.o(.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
diff --git a/configs/KUP4K_defconfig b/configs/KUP4K_defconfig
deleted file mode 100644
index 8e9e26d..0000000
--- a/configs/KUP4K_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_8xx=y
-CONFIG_TARGET_KUP4K=y
diff --git a/configs/KUP4X_defconfig b/configs/KUP4X_defconfig
deleted file mode 100644
index 29520c9..0000000
--- a/configs/KUP4X_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_8xx=y
-CONFIG_TARGET_KUP4X=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 426cadc..3a27d4c 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,8 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+KUP4K powerpc mpc8xx - - Klaus Heydeck <heydeck@kieback-peter.de>
+KUP4X powerpc mpc8xx - - Klaus Heydeck <heydeck@kieback-peter.de>
ELPT860 powerpc mpc8xx - - The LEOX team <team@leox.org>
hmi1001 powerpc mpc5xxx - -
mucmc52 powerpc mpc5xxx - - Heiko Schocher <hs@denx.de>
diff --git a/include/commproc.h b/include/commproc.h
index af67878..311745e 100644
--- a/include/commproc.h
+++ b/include/commproc.h
@@ -543,36 +543,6 @@ typedef struct scc_enet {
#endif /* CONFIG_IVMS8, CONFIG_IVML24 */
-/*** KUP4K, KUP4X ****************************************************/
-/* The KUP4 boards uses the FEC on a MPC8xx for Ethernet */
-
-#if defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X)
-
-#define FEC_ENET /* use FEC for EThernet */
-#undef SCC_ENET
-
-#define PB_ENET_POWER ((uint)0x00010000) /* PB 15 */
-
-#define PC_ENET_RESET ((ushort)0x0010) /* PC 11 */
-
-#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
-#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
-#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
-#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
-#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
-#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
-#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
-#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
-#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
-#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
-#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
-#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
-#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
-
-#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
-
-#endif /* CONFIG_KUP4K */
-
/*** LWMON **********************************************************/
#if defined(CONFIG_LWMON)
diff --git a/include/configs/KUP4K.h b/include/configs/KUP4K.h
deleted file mode 100644
index 7cf09d0..0000000
--- a/include/configs/KUP4K.h
+++ /dev/null
@@ -1,488 +0,0 @@
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck at kieback-peter.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- * Derived from ../tqm8xx/tqm8xx.c
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC855 1 /* This is a MPC855 CPU */
-#define CONFIG_KUP4K 1 /* ...on a KUP4K module */
-
-#define CONFIG_SYS_TEXT_BASE 0x40000000
-
-#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE 115200 /* console baudrate */
-#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
-
-#define CONFIG_BOARD_TYPES 1 /* support board types */
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-"slot_a_boot=setenv bootargs root=/dev/sda2 ip=off;" \
- "run addhw; mw.b 400000 00 80; diskboot 400000 0:1; bootm 400000\0" \
-"slot_b_boot=setenv bootargs root=/dev/sda2 ip=off;" \
- "run addhw; mw.b 400000 00 80; diskboot 400000 2:1; bootm 400000\0" \
-"nfs_boot=mw.b 400000 00 80; dhcp; run nfsargs addip addhw; bootm 400000\0" \
-"fat_boot=mw.b 400000 00 80; fatload ide 2:1 400000 st.bin; run addhw; \
- bootm 400000 \0" \
-"panic_boot=echo No Bootdevice !!! reset\0" \
-"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${rootpath}\0" \
-"ramargs=setenv bootargs root=/dev/ram rw\0" \
-"addip=setenv bootargs ${bootargs} ip=${ipaddr}::${gatewayip}" \
- ":${netmask}:${hostname}:${netdev}:off\0" \
-"addhw=setenv bootargs ${bootargs} ${mtdparts} console=${console} ${debug} \
- hw=${hw} key1=${key1} panic=1 mem=${mem}\0" \
-"console=ttyCPM0,115200\0" \
-"netdev=eth0\0" \
-"contrast=20\0" \
-"silent=1\0" \
-"mtdparts=" MTDPARTS_DEFAULT "\0" \
-"load=tftp 200000 bootloader-4k.bitmap;tftp 100000 bootloader-4k.bin\0" \
-"update=protect off 1:0-9;era 1:0-9;cp.b 100000 40000000 ${filesize};" \
- "cp.b 200000 40050000 14000\0"
-
-#define CONFIG_BOOTCOMMAND \
- "run fat_boot;run slot_b_boot;run slot_a_boot;run nfs_boot;run panic_boot"
-
-#define CONFIG_PREBOOT "setenv preboot; saveenv"
-
-#define CONFIG_MISC_INIT_R 1
-#define CONFIG_MISC_INIT_F 1
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-#define CONFIG_WATCHDOG 1 /* watchdog enabled */
-
-#define CONFIG_STATUS_LED 1 /* Status LED enabled */
-
-#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-/*
- * enable I2C and select the hardware/software driver
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
-
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define PB_SCL 0x00000020 /* PB 26 */
-#define PB_SDA 0x00000010 /* PB 27 */
-
-#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
-#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
-#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
-#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
-#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
- else immr->im_cpm.cp_pbdat &= ~PB_SDA
-#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
- else immr->im_cpm.cp_pbdat &= ~PB_SCL
-#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
-
-/*-----------------------------------------------------------------------
- * I2C Configuration
- */
-
-#define CONFIG_SYS_I2C_PICIO_ADDR 0x21 /* PCF8574 IO Expander */
-#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */
-
-/* List of I2C addresses to be verified by POST */
-
-#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_PICIO_ADDR, \
- CONFIG_SYS_I2C_RTC_ADDR, \
- }
-
-#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
-
-#define CONFIG_SYS_DISCOVER_PHY
-#define CONFIG_MII
-
-/* Define to allow the user to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_SNTP
-
-#ifdef CONFIG_POST
- #define CONFIG_CMD_DIAG
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
-#endif
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x000400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x005C00000 /* 4 ... 92 MB in DRAM */
-#define CONFIG_SYS_ALT_MEMTEST 1
-#define CONFIG_SYS_MEMTEST_SCRATCH 0x90000200 /* using latch as scratch register */
-
-#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
-
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 115200 }
-
-#define CONFIG_SYS_CONSOLE_INFO_QUIET 1
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xFFF00000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0x40000000
-#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 19 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
-#define CONFIG_ENV_SECT_SIZE 0x10000
-
-/*-----------------------------------------------------------------------
- * Dynamic MTD partition support
- */
-#define MTDPARTS_DEFAULT "mtdparts=40000000.flash:256k(u-boot)," \
- "64k(env)," \
- "128k(splash)," \
- "512k(etc)," \
- "64k(hw-info)"
-
-/*-----------------------------------------------------------------------
- * Hardware Information Block
- */
-#define CONFIG_SYS_HWINFO_OFFSET 0x000F0000 /* offset of HW Info block */
-#define CONFIG_SYS_HWINFO_SIZE 0x00000100 /* size of HW Info block */
-#define CONFIG_SYS_HWINFO_MAGIC 0x4B26500D /* 'K&P<CR>' */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register 11-27
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit
- *
- * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
- */
-#define CONFIG_SYS_PLPRCR ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK SCCR_EBDF00
-#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_EBDF01 | \
- SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
- SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
- SCCR_DFALCD00)
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-
-/* KUP4K use both slots, SLOT_A as "primary". */
-#define CONFIG_PCMCIA_SLOT_A 1
-
-#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
-
-#define PCMCIA_SOCKETS_NO 2
-#define PCMCIA_MEM_WIN_NO 8
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
- *-----------------------------------------------------------------------
- */
-
-#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
-#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
-
-#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
-#define CONFIG_IDE_LED 1 /* LED for ide supported */
-#undef CONFIG_IDE_RESET /* reset for ide not supported */
-
-#define CONFIG_SYS_IDE_MAXBUS 2
-#define CONFIG_SYS_IDE_MAXDEVICE 4
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_IDE1_OFFSET (4 * CONFIG_SYS_PCMCIA_MEM_SIZE)
-
-#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_DER 0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
-
-/*
- * FLASH timing:
- */
-#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV2 | OR_CSNT_SAM | \
- OR_SCY_5_CLK | OR_EHTR | OR_BI)
-
-#define CONFIG_SYS_OR0_REMAP \
- (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM \
- (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR0_PRELIM \
- ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
-
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
-#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
-
-/*
- * Memory Periodic Timer Prescaler
- *
- * The Divider for PTA (refresh timer) configuration is based on an
- * example SDRAM configuration (64 MBit, one bank). The adjustment to
- * the number of chip selects (NCS) and the actually needed refresh
- * rate is done by setting MPTPR.
- *
- * PTA is calculated from
- * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
- *
- * gclk CPU clock (not bus clock!)
- * Trefresh Refresh cycle * 4 (four word bursts used)
- *
- * 4096 Rows from SDRAM example configuration
- * 1000 factor s -> ms
- * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
- * 4 Number of refresh cycles per period
- * 64 Refresh cycle in ms per number of rows
- * --------------------------------------------
- * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
- *
- * 50 MHz => 50.000.000 / Divider = 98
- * 66 Mhz => 66.000.000 / Divider = 129
- * 80 Mhz => 80.000.000 / Divider = 156
- */
-#if defined(CONFIG_80MHz)
-#define CONFIG_SYS_MAMR_PTA 156
-#elif defined(CONFIG_66MHz)
-#define CONFIG_SYS_MAMR_PTA 129
-#else /* 50 MHz */
-#define CONFIG_SYS_MAMR_PTA 98
-#endif /*CONFIG_??MHz */
-
-/*
- * For 16 MBit, refresh rates could be 31.3 us
- * (= 64 ms / 2K = 125 / quad bursts).
- * For a simpler initialization, 15.6 us is used instead.
- *
- * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
- * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
- */
-#define CONFIG_SYS_MPTPR 0x400
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CONFIG_SYS_MAMR_8COL 0x68802114
-/* 9 column SDRAM */
-#define CONFIG_SYS_MAMR_9COL 0x68904114
-
-/*
- * Chip Selects
- */
-#define CONFIG_SYS_OR0
-#define CONFIG_SYS_BR0
-
-#define CONFIG_SYS_OR1_8COL 0xFF000A00
-#define CONFIG_SYS_BR1_8COL 0x00000081
-#define CONFIG_SYS_OR2_8COL 0xFE000A00
-#define CONFIG_SYS_BR2_8COL 0x01000081
-#define CONFIG_SYS_OR3_8COL 0xFC000A00
-#define CONFIG_SYS_BR3_8COL 0x02000081
-
-#define CONFIG_SYS_OR1_9COL 0xFE000A00
-#define CONFIG_SYS_BR1_9COL 0x00000081
-#define CONFIG_SYS_OR2_9COL 0xFE000A00
-#define CONFIG_SYS_BR2_9COL 0x02000081
-#define CONFIG_SYS_OR3_9COL 0xFE000A00
-#define CONFIG_SYS_BR3_9COL 0x04000081
-
-#define CONFIG_SYS_OR4 0xFFFF8926
-#define CONFIG_SYS_BR4 0x90000401
-
-#define CONFIG_SYS_OR5 0xFFC007F0 /* EPSON: 4 MB 17 WS or externel TA */
-#define CONFIG_SYS_BR5 0x80080801 /* Start at 0x80080000 */
-
-#define LATCH_ADDR 0x90000200
-
-#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
-#define CONFIG_AUTOBOOT_STOP_STR "."
-#define CONFIG_SILENT_CONSOLE 1
-#define CONFIG_SYS_DEVICE_NULLDEV 1 /* enble null device */
-#define CONFIG_VERSION_VARIABLE 1
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/KUP4X.h b/include/configs/KUP4X.h
deleted file mode 100644
index 47d1623..0000000
--- a/include/configs/KUP4X.h
+++ /dev/null
@@ -1,440 +0,0 @@
-/*
- * (C) Copyright 2000-2005
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck at kieback-peter.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- * Derived from ../tqm8xx/tqm8xx.c
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC859T 1 /* This is a MPC859T CPU */
-#define CONFIG_KUP4X 1 /* ...on a KUP4X module */
-
-#define CONFIG_SYS_TEXT_BASE 0x40000000
-
-#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE 115200 /* console baudrate */
-
-#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
-
-#define CONFIG_BOARD_TYPES 1 /* support board types */
-
-#define CONFIG_SYS_8XX_FACT 8 /* Multiply by 8 */
-#define CONFIG_SYS_8XX_XIN 16000000 /* 16 MHz in */
-
-
-#define MPC8XX_HZ ((CONFIG_SYS_8XX_XIN) * (CONFIG_SYS_8XX_FACT))
-
-/* should ALWAYS define this, measure_gclk in speed.c is unreliable */
-/* in general, we always know this for FADS+new ADS anyway */
-#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ
-
-
-#undef CONFIG_BOOTARGS
-
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-"slot_a_boot=setenv bootargs root=/dev/hda2 ip=off;" \
- "run addhw;diskboot 200000 0:1;bootm 200000\0" \
-"usb_boot=setenv bootargs root=/dev/sda2 ip=off; \
- run addhw; sleep 2; usb reset; usb scan; usbboot 200000 0:1; \
- usb stop; bootm 200000\0" \
-"nfs_boot=dhcp;run nfsargs addip addhw;bootm 200000\0" \
-"panic_boot=echo No Bootdevice !!! reset\0" \
-"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
-"ramargs=setenv bootargs root=/dev/ram rw\0" \
-"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}" \
- ":${netmask}:${hostname}:${netdev}:off\0" \
-"addhw=setenv bootargs ${bootargs} hw=${hw} key1=${key1} panic=1\0" \
-"netdev=eth0\0" \
-"silent=1\0" \
-"load=tftp 200000 bootloader-4x.bitmap;tftp 100000 bootloader-4x.bin\0" \
-"update=protect off 1:0-5;era 1:0-5;cp.b 100000 40000000 ${filesize};" \
- "cp.b 200000 40040000 14000\0"
-
-#define CONFIG_BOOTCOMMAND \
- "run usb_boot;run slot_a_boot;run nfs_boot;run panic_boot"
-
-
-#define CONFIG_MISC_INIT_R 1
-#define CONFIG_MISC_INIT_F 1
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-#define CONFIG_WATCHDOG 1 /* watchdog enabled */
-
-#define CONFIG_STATUS_LED 1 /* Status LED enabled */
-
-#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-/*
- * enable I2C and select the hardware/software driver
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-
-#ifdef CONFIG_SYS_I2C_SOFT
-#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
-
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define PB_SCL 0x00000020 /* PB 26 */
-#define PB_SDA 0x00000010 /* PB 27 */
-
-#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
-#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
-#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
-#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
-#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
- else immr->im_cpm.cp_pbdat &= ~PB_SDA
-#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
- else immr->im_cpm.cp_pbdat &= ~PB_SCL
-#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
-#endif /* CONFIG_SYS_I2C_SOFT */
-
-
-/*-----------------------------------------------------------------------
- * I2C Configuration
- */
-
-#define CONFIG_SYS_I2C_PICIO_ADDR 0x21 /* PCF8574 IO Expander */
-#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */
-
-
-/* List of I2C addresses to be verified by POST */
-
-#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_PICIO_ADDR, \
- CONFIG_SYS_I2C_RTC_ADDR, \
- }
-
-
-#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
-
-#define CONFIG_SYS_DISCOVER_PHY
-#define CONFIG_MII
-
-#undef CONFIG_KUP4K_LOGO
-
-/* Define to allow the user to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-
-/* POST support */
-#define CONFIG_POST (CONFIG_SYS_POST_CPU | \
- CONFIG_SYS_POST_RTC | \
- CONFIG_SYS_POST_I2C)
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_SNTP
-#define CONFIG_CMD_USB
-
-#ifdef CONFIG_POST
- #define CONFIG_CMD_DIAG
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x000400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x003C00000 /* 4 ... 60 MB in DRAM */
-#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */
-
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 115200 }
-
-#define CONFIG_SYS_CONSOLE_INFO_QUIET 1
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xFFF00000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0x40000000
-#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 19 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
-#define CONFIG_ENV_SECT_SIZE 0x10000
-
-/* Address and size of Redundant Environment Sector */
-#if 0
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-#endif
-/*-----------------------------------------------------------------------
- * Hardware Information Block
- */
-#if 1
-#define CONFIG_SYS_HWINFO_OFFSET 0x000F0000 /* offset of HW Info block */
-#define CONFIG_SYS_HWINFO_SIZE 0x00000100 /* size of HW Info block */
-#define CONFIG_SYS_HWINFO_MAGIC 0x4B26500D /* 'K&P<CR>' */
-#endif
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if 0 && defined(CONFIG_WATCHDOG) /* KUP uses external TPS3705 WD */
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- * set the PLL, the low-power modes and the reset control (15-29)
- */
-#define CONFIG_SYS_PLPRCR ((CONFIG_SYS_8XX_FACT << PLPRCR_MFI_SHIFT) | \
- PLPRCR_SPLSS | PLPRCR_TEXPS)
-
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK SCCR_EBDF00
-#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_EBDF01 | \
- SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
- SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
- SCCR_DFALCD00)
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-
-/* KUP4K use both slots, SLOT_A as "primary". */
-#define CONFIG_PCMCIA_SLOT_A 1
-
-#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
-
-#define PCMCIA_SOCKETS_NO 1
-#define PCMCIA_MEM_WIN_NO 8
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
- *-----------------------------------------------------------------------
- */
-
-#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
-#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
-
-#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
-#define CONFIG_IDE_LED 1 /* LED for ide supported */
-#undef CONFIG_IDE_RESET /* reset for ide not supported */
-
-#define CONFIG_SYS_IDE_MAXBUS 1
-#define CONFIG_SYS_IDE_MAXDEVICE 2
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_IDE1_OFFSET (4 * CONFIG_SYS_PCMCIA_MEM_SIZE)
-
-#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
-
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_DER 0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
-
-/*
- * FLASH timing:
- */
-#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
- OR_SCY_2_CLK | OR_EHTR | OR_BI)
-
-#define CONFIG_SYS_OR0_REMAP \
- (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM \
- (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR0_PRELIM \
- ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
-
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
-#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
-
-
-#define CONFIG_SYS_MPTPR 0x400
-
-/*
- * MAMR settings for SDRAM
- */
-#define CONFIG_SYS_MAMR 0x80802114
-
-
-/*
- * Chip Selects
- */
-
-#define CONFIG_SYS_OR4 0xFFFF8926
-#define CONFIG_SYS_BR4 0x90000401
-
-#define LATCH_ADDR 0x90000200
-
-#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
-
-#define CONFIG_AUTOBOOT_STOP_STR "." /* easy to stop for now */
-#define CONFIG_SILENT_CONSOLE 1
-
-#define CONFIG_USB_STORAGE 1
-#define CONFIG_USB_SL811HS 1
-
-#endif /* __CONFIG_H */
diff --git a/include/status_led.h b/include/status_led.h
index c5de894..1feeff5 100644
--- a/include/status_led.h
+++ b/include/status_led.h
@@ -158,22 +158,6 @@ void status_led_set (int led, int state);
# define STATUS_LED_ACTIVE 1 /* LED on for bit == 0 */
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
-/***** KUP4K, KUP4X ****************************************************/
-#elif defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X)
-
-# define STATUS_LED_PAR im_ioport.iop_papar
-# define STATUS_LED_DIR im_ioport.iop_padir
-# define STATUS_LED_ODR im_ioport.iop_paodr
-# define STATUS_LED_DAT im_ioport.iop_padat
-
-# define STATUS_LED_BIT 0x00000300 /* green + red PA[8]=yellow, PA[7]=red, PA[6]=green */
-# define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
-# define STATUS_LED_STATE STATUS_LED_BLINKING
-
-# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
-
-# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
-
#elif defined(CONFIG_V38B)
# define STATUS_LED_BIT 0x0010 /* Timer7 GPIO */
--
1.9.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [U-Boot] [PATCH 05/26] mpc8xx: remove SPD823TS board support
2014-12-15 14:26 [U-Boot] [PATCH 0/26] Start removing non-generic boards Masahiro Yamada
` (3 preceding siblings ...)
2014-12-15 14:26 ` [U-Boot] [PATCH 04/26] mpc8xx: remove KUP4X, KUP4K " Masahiro Yamada
@ 2014-12-15 14:26 ` Masahiro Yamada
2015-01-05 18:20 ` Tom Rini
2014-12-15 14:26 ` [U-Boot] [PATCH 06/26] mpc8xx: remove RRvision " Masahiro Yamada
` (22 subsequent siblings)
27 siblings, 1 reply; 55+ messages in thread
From: Masahiro Yamada @ 2014-12-15 14:26 UTC (permalink / raw)
To: u-boot
This board is still a non-generic board.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
---
arch/powerpc/cpu/mpc8xx/Kconfig | 4 -
arch/powerpc/cpu/mpc8xx/cpu_init.c | 3 +-
board/spd8xx/Kconfig | 9 -
board/spd8xx/MAINTAINERS | 6 -
board/spd8xx/Makefile | 8 -
board/spd8xx/flash.c | 41 ----
board/spd8xx/spd8xx.c | 278 -------------------------
board/spd8xx/u-boot.lds | 91 ---------
board/spd8xx/u-boot.lds.debug | 122 -----------
common/flash.c | 6 -
configs/SPD823TS_defconfig | 3 -
doc/README.scrapyard | 1 +
include/commproc.h | 29 ---
include/configs/SPD823TS.h | 402 -------------------------------------
include/pcmcia.h | 2 -
15 files changed, 2 insertions(+), 1003 deletions(-)
delete mode 100644 board/spd8xx/Kconfig
delete mode 100644 board/spd8xx/MAINTAINERS
delete mode 100644 board/spd8xx/Makefile
delete mode 100644 board/spd8xx/flash.c
delete mode 100644 board/spd8xx/spd8xx.c
delete mode 100644 board/spd8xx/u-boot.lds
delete mode 100644 board/spd8xx/u-boot.lds.debug
delete mode 100644 configs/SPD823TS_defconfig
delete mode 100644 include/configs/SPD823TS.h
diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig
index 7fa5b0b..8bda42e 100644
--- a/arch/powerpc/cpu/mpc8xx/Kconfig
+++ b/arch/powerpc/cpu/mpc8xx/Kconfig
@@ -34,9 +34,6 @@ config TARGET_R360MPI
config TARGET_RRVISION
bool "Support RRvision"
-config TARGET_SPD823TS
- bool "Support SPD823TS"
-
config TARGET_TQM823L
bool "Support TQM823L"
@@ -83,7 +80,6 @@ source "board/ivm/Kconfig"
source "board/lwmon/Kconfig"
source "board/netvia/Kconfig"
source "board/r360mpi/Kconfig"
-source "board/spd8xx/Kconfig"
source "board/tqc/tqm8xx/Kconfig"
endmenu
diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c
index 6a1cd46..f772787 100644
--- a/arch/powerpc/cpu/mpc8xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c
@@ -130,8 +130,7 @@ void cpu_init_f (volatile immap_t * immr)
defined(CONFIG_IVMS8) || \
defined(CONFIG_LWMON) || \
defined(CONFIG_R360MPI) || \
- defined(CONFIG_RMU) || \
- defined(CONFIG_SPD823TS)
+ defined(CONFIG_RMU)
memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM;
#endif
diff --git a/board/spd8xx/Kconfig b/board/spd8xx/Kconfig
deleted file mode 100644
index 2430616..0000000
--- a/board/spd8xx/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_SPD823TS
-
-config SYS_BOARD
- default "spd8xx"
-
-config SYS_CONFIG_NAME
- default "SPD823TS"
-
-endif
diff --git a/board/spd8xx/MAINTAINERS b/board/spd8xx/MAINTAINERS
deleted file mode 100644
index 7ed9423..0000000
--- a/board/spd8xx/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-SPD8XX BOARD
-M: Wolfgang Denk <wd@denx.de>
-S: Maintained
-F: board/spd8xx/
-F: include/configs/SPD823TS.h
-F: configs/SPD823TS_defconfig
diff --git a/board/spd8xx/Makefile b/board/spd8xx/Makefile
deleted file mode 100644
index c393f06..0000000
--- a/board/spd8xx/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = spd8xx.o flash.o
diff --git a/board/spd8xx/flash.c b/board/spd8xx/flash.c
deleted file mode 100644
index 4a332e0..0000000
--- a/board/spd8xx/flash.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- /* All Speech Design board memory (DRAM and EPROM) initialisation is
- done in dram_init().
- The caller of ths function here expects the total size and will hang,
- if we give here back 0. So we return the EPROM size. */
-
- return (1024 * 1024); /* 1 MB */
-}
-
-/*-----------------------------------------------------------------------
- */
-
-void flash_print_info (flash_info_t *info)
-{
- printf("no FLASH memory in MPC823TS board\n");
- return;
-}
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- return 1;
-}
-
-/*-----------------------------------------------------------------------
- */
diff --git a/board/spd8xx/spd8xx.c b/board/spd8xx/spd8xx.c
deleted file mode 100644
index d3320bb..0000000
--- a/board/spd8xx/spd8xx.c
+++ /dev/null
@@ -1,278 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- * Ulrich Lutz, Speech Design GmbH, ulutz at datalab.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-#include <commproc.h>
-
-/* ------------------------------------------------------------------------- */
-
-static long int dram_size (long int, long int *, long int);
-
-/* ------------------------------------------------------------------------- */
-
-#define _NOT_USED_ 0xFFFFFFFF
-
-const uint sharc_table[] = {
- /*
- * Single Read. (Offset 0 in UPM RAM)
- */
- 0x0FF3FC04, 0x0FF3EC00, 0x7FFFEC04, 0xFFFFEC04,
- 0xFFFFEC05, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Burst Read. (Offset 8 in UPM RAM)
- */
- /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Single Write. (Offset 18 in UPM RAM)
- */
- 0x0FAFFC04, 0x0FAFEC00, 0x7FFFEC04, 0xFFFFEC04,
- 0xFFFFEC05, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Burst Write. (Offset 20 in UPM RAM)
- */
- /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Refresh (Offset 30 in UPM RAM)
- */
- /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Exception. (Offset 3c in UPM RAM)
- */
- 0x7FFFFC07, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
-};
-
-
-const uint sdram_table[] = {
- /*
- * Single Read. (Offset 0 in UPM RAM)
- */
- 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
- 0x1FF77C47, /* last */
- /*
- * SDRAM Initialization (offset 5 in UPM RAM)
- *
- * This is no UPM entry point. The following definition uses
- * the remaining space to establish an initialization
- * sequence, which is executed by a RUN command.
- *
- */
- 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */
- /*
- * Burst Read. (Offset 8 in UPM RAM)
- */
- 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
- 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Single Write. (Offset 18 in UPM RAM)
- */
- 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Burst Write. (Offset 20 in UPM RAM)
- */
- 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
- 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
- _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Refresh (Offset 30 in UPM RAM)
- */
- 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
- 0xFFFFFC84, 0xFFFFFC07, /* last */
- _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Exception. (Offset 3c in UPM RAM)
- */
- 0x7FFFFC07, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
-};
-
-/* ------------------------------------------------------------------------- */
-
-
-/*
- * Check Board Identity:
- *
- */
-
-int checkboard (void)
-{
- puts ("Board: SPD823TS\n");
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- long int size_b0;
-
-#if 0
- /*
- * Map controller bank 2 to the SRAM bank at preliminary address.
- */
- memctl->memc_or2 = CONFIG_SYS_OR2;
- memctl->memc_br2 = CONFIG_SYS_BR2;
-#endif
-
- /*
- * Map controller bank 4 to the PER8 bank.
- */
- memctl->memc_or4 = CONFIG_SYS_OR4;
- memctl->memc_br4 = CONFIG_SYS_BR4;
-
-#if 0
- /* Configure SHARC at UMA */
- upmconfig (UPMA, (uint *) sharc_table,
- sizeof (sharc_table) / sizeof (uint));
- /* Map controller bank 5 to the SHARC */
- memctl->memc_or5 = CONFIG_SYS_OR5;
- memctl->memc_br5 = CONFIG_SYS_BR5;
-#endif
-
- memctl->memc_mamr = 0x00001000;
-
- /* Configure SDRAM at UMB */
- upmconfig (UPMB, (uint *) sdram_table,
- sizeof (sdram_table) / sizeof (uint));
-
- memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_8K;
-
- memctl->memc_mar = 0x00000088;
-
- /*
- * Map controller bank 3 to the SDRAM bank at preliminary address.
- */
- memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
- memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
-
- memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL; /* refresh not enabled yet */
-
- udelay (200);
- memctl->memc_mcr = 0x80806105;
- udelay (1);
- memctl->memc_mcr = 0x80806130;
- udelay (1);
- memctl->memc_mcr = 0x80806130;
- udelay (1);
- memctl->memc_mcr = 0x80806106;
-
- memctl->memc_mbmr |= MBMR_PTBE; /* refresh enabled */
-
- /*
- * Check Bank 0 Memory Size for re-configuration
- */
- size_b0 =
- dram_size (CONFIG_SYS_MBMR_8COL, SDRAM_BASE3_PRELIM,
- SDRAM_MAX_SIZE);
-
- memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL | MBMR_PTBE;
-
- return (size_b0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-
-static long int dram_size (long int mamr_value, long int *base,
- long int maxsize)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
- memctl->memc_mbmr = mamr_value;
-
- return (get_ram_size (base, maxsize));
-}
-
-/* ------------------------------------------------------------------------- */
-
-void reset_phy (void)
-{
- immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- ushort sreg;
-
- /* Configure extra port pins for NS DP83843 PHY */
- immr->im_ioport.iop_papar &= ~(PA_ENET_MDC | PA_ENET_MDIO);
-
- sreg = immr->im_ioport.iop_padir;
- sreg |= PA_ENET_MDC; /* Mgmt. Data Clock is Output */
- sreg &= ~(PA_ENET_MDIO); /* Mgmt. Data I/O is bidirect. => Input */
- immr->im_ioport.iop_padir = sreg;
-
- immr->im_ioport.iop_padat &= ~(PA_ENET_MDC); /* set MDC = 0 */
-
- /*
- * RESET in implemented by a positive pulse of at least 1 us
- * at the reset pin.
- *
- * Configure RESET pins for NS DP83843 PHY, and RESET chip.
- *
- * Note: The RESET pin is high active, but there is an
- * inverter on the SPD823TS board...
- */
- immr->im_ioport.iop_pcpar &= ~(PC_ENET_RESET);
- immr->im_ioport.iop_pcdir |= PC_ENET_RESET;
- /* assert RESET signal of PHY */
- immr->im_ioport.iop_pcdat &= ~(PC_ENET_RESET);
- udelay (10);
- /* de-assert RESET signal of PHY */
- immr->im_ioport.iop_pcdat |= PC_ENET_RESET;
- udelay (10);
-}
-
-/* ------------------------------------------------------------------------- */
-
-void ide_set_reset (int on)
-{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
-
- /*
- * Configure PC for IDE Reset Pin
- */
- if (on) { /* assert RESET */
- immr->im_ioport.iop_pcdat &= ~(CONFIG_SYS_PC_IDE_RESET);
- } else { /* release RESET */
- immr->im_ioport.iop_pcdat |= CONFIG_SYS_PC_IDE_RESET;
- }
-
- /* program port pin as GPIO output */
- immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_IDE_RESET);
- immr->im_ioport.iop_pcso &= ~(CONFIG_SYS_PC_IDE_RESET);
- immr->im_ioport.iop_pcdir |= CONFIG_SYS_PC_IDE_RESET;
-}
-
-/* ------------------------------------------------------------------------- */
diff --git a/board/spd8xx/u-boot.lds b/board/spd8xx/u-boot.lds
deleted file mode 100644
index 463af7e..0000000
--- a/board/spd8xx/u-boot.lds
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text*)
- arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- net/built-in.o (.text*)
- arch/powerpc/cpu/mpc8xx/built-in.o (.text*)
- *(.text.v*printf)
-
- . = DEFINED(env_offset) ? env_offset : .;
- common/env_embedded.o (.ppcenv*)
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
diff --git a/board/spd8xx/u-boot.lds.debug b/board/spd8xx/u-boot.lds.debug
deleted file mode 100644
index 7cfed1f..0000000
--- a/board/spd8xx/u-boot.lds.debug
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
- arch/powerpc/lib/extable.o (.text)
-
- . = env_offset;
- common/env_embedded.o(.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
diff --git a/common/flash.c b/common/flash.c
index f1440c2..fa33f03 100644
--- a/common/flash.c
+++ b/common/flash.c
@@ -88,7 +88,6 @@ flash_protect (int flag, ulong from, ulong to, flash_info_t *info)
flash_info_t *
addr2info (ulong addr)
{
-#ifndef CONFIG_SPD823TS
flash_info_t *info;
int i;
@@ -104,7 +103,6 @@ addr2info (ulong addr)
return (info);
}
}
-#endif /* CONFIG_SPD823TS */
return (NULL);
}
@@ -125,9 +123,6 @@ addr2info (ulong addr)
int
flash_write (char *src, ulong addr, ulong cnt)
{
-#ifdef CONFIG_SPD823TS
- return (ERR_TIMOUT); /* any other error codes are possible as well */
-#else
int i;
ulong end = addr + cnt - 1;
flash_info_t *info_first = addr2info (addr);
@@ -181,7 +176,6 @@ flash_write (char *src, ulong addr, ulong cnt)
#endif /* CONFIG_SYS_FLASH_VERIFY_AFTER_WRITE */
return (ERR_OK);
-#endif /* CONFIG_SPD823TS */
}
/*-----------------------------------------------------------------------
diff --git a/configs/SPD823TS_defconfig b/configs/SPD823TS_defconfig
deleted file mode 100644
index 1b218c6..0000000
--- a/configs/SPD823TS_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_8xx=y
-CONFIG_TARGET_SPD823TS=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 3a27d4c..623a30e 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+SPD823TS powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
KUP4K powerpc mpc8xx - - Klaus Heydeck <heydeck@kieback-peter.de>
KUP4X powerpc mpc8xx - - Klaus Heydeck <heydeck@kieback-peter.de>
ELPT860 powerpc mpc8xx - - The LEOX team <team@leox.org>
diff --git a/include/commproc.h b/include/commproc.h
index 311745e..4c39934 100644
--- a/include/commproc.h
+++ b/include/commproc.h
@@ -627,35 +627,6 @@ typedef struct scc_enet {
#endif /* CONFIG_NETVIA */
-/*** SPD823TS ******************************************************/
-
-#ifdef CONFIG_SPD823TS
-/* Bits in parallel I/O port registers that have to be set/cleared
- * to configure the pins for SCC2 use.
- */
-#define PROFF_ENET PROFF_SCC2 /* Ethernet on SCC2 */
-#define CPM_CR_ENET CPM_CR_CH_SCC2
-#define SCC_ENET 1
-#define PA_ENET_MDC ((ushort)0x0001) /* PA 15 !!! */
-#define PA_ENET_MDIO ((ushort)0x0002) /* PA 14 !!! */
-#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
-#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
-#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
-#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
-
-#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
-
-#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
-#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
-#define PC_ENET_RESET ((ushort)0x0100) /* PC 7 !!! */
-
-/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to
- * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
- */
-#define SICR_ENET_MASK ((uint)0x0000ff00)
-#define SICR_ENET_CLKRT ((uint)0x00002E00)
-#endif /* CONFIG_SPD823TS */
-
/*** MVS1, TQM823L/M, TQM850L/M, TQM885D, R360MPI **********/
#if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \
diff --git a/include/configs/SPD823TS.h b/include/configs/SPD823TS.h
deleted file mode 100644
index a8b4fbb..0000000
--- a/include/configs/SPD823TS.h
+++ /dev/null
@@ -1,402 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
-#define CONFIG_SPD823TS 1 /* ...on a SPD823TS board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFF000000
-
-#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
-
-#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE 115200
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-
-#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
-
-#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
-
-#define CONFIG_BOOTARGS "root=/dev/nfs rw " \
- "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \
- "nfsaddrs=10.0.0.99:10.0.0.2"
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_IDE
-
-#undef CONFIG_CMD_SAVEENV
-#undef CONFIG_CMD_FLASH
-
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*----------------------------------------------------------------------*/
-#define CONFIG_ETHADDR 00:D0:93:00:01:CB
-#define CONFIG_IPADDR 10.0.0.98
-#define CONFIG_SERVERIP 10.0.0.1
-#undef CONFIG_BOOTCOMMAND
-#define CONFIG_BOOTCOMMAND "tftp 200000 uImage;bootm 200000"
-/*----------------------------------------------------------------------*/
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
-
-#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
-
-#define CONFIG_SYS_PC_IDE_RESET ((ushort)0x0008) /* PC 12 */
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xFFF00000 /* was: 0xFF000000 */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFF000000
-#ifdef DEBUG
-#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
-#else
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#endif
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 0 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 0 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 0 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 0 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE 0x0800 /* Total Size of Environment Sector */
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-/* 0x00000040 */
-#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00 | SIUMCR_GB5E)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit, set PLL multiplication factor !
- */
-/* 0x00b0c0c0 */
-#define CONFIG_SYS_PLPRCR \
- ( (11 << PLPRCR_MF_SHIFT) | \
- PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/ \
- /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
- PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \
- )
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK SCCR_EBDF11
-/* 0x01800014 */
-#define CONFIG_SYS_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \
- SCCR_RTDIV | SCCR_RTSEL | \
- /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
- SCCR_EBDF00 | SCCR_DFSYNC00 | \
- SCCR_DFBRG00 | SCCR_DFNL000 | \
- SCCR_DFNH000 | SCCR_DFLCD101 | \
- SCCR_DFALCD00)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register
- *-----------------------------------------------------------------------
- */
-/* 0x00C3 */
-#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration Register
- *-----------------------------------------------------------------------
- */
-/* TIMEP=2 */
-#define CONFIG_SYS_RCCR 0x0200
-
-/*-----------------------------------------------------------------------
- * RMDS - RISC Microcode Development Support Control Register
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RMDS 0
-
-/*-----------------------------------------------------------------------
- * SDSR - SDMA Status Register
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_SDSR ((u_char)0x83)
-
-/*-----------------------------------------------------------------------
- * SDMR - SDMA Mask Register
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_SDMR ((u_char)0x00)
-
-/*-----------------------------------------------------------------------
- *
- * Interrupt Levels
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_CPM_INTERRUPT 13 /* SIU_LEVEL6 */
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
-#define CONFIG_IDE_INIT_POSTRESET 1 /* Use postreset IDE hook */
-#define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */
-#define CONFIG_IDE_LED 1 /* LED for ide supported */
-#define CONFIG_IDE_RESET 1 /* reset for ide supported */
-
-#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */
-#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
-
-#define CONFIG_SYS_ATA_BASE_ADDR 0xFE100000
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0C00
-
-#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
-#define CONFIG_SYS_ATA_REG_OFFSET 0x0080 /* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 /* Offset for alternate registers */
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_DER 0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0xFF080000 /* FLASH bank #1 */
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-/* EPROMs are 512kb */
-#define CONFIG_SYS_REMAP_OR_AM 0xFFF80000 /* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */
-
-/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
-#define CONFIG_SYS_OR_TIMING_FLASH (/* OR_CSNT_SAM | */ OR_ACS_DIV4 | OR_BI | \
- OR_SCY_5_CLK | OR_EHTR)
-
-#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-/* 16 bit, bank valid */
-#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
-
-#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
-/* 16 bit, bank valid */
-#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
-
-/*
- * BR2-5 and OR2-5 (SRAM/SDRAM/PER8/SHARC)
- *
- */
-#define SRAM_BASE 0xFE200000 /* SRAM bank */
-#define SRAM_OR_AM 0xFFE00000 /* SRAM is 2 MB */
-
-#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */
-#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */
-#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */
-
-#define PER8_BASE 0xFE000000 /* PER8 bank */
-#define PER8_OR_AM 0xFFF00000 /* PER8 is 1 MB */
-
-#define SHARC_BASE 0xFE400000 /* SHARC bank */
-#define SHARC_OR_AM 0xFFC00000 /* SHARC is 4 MB */
-
-/* SRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
-
-#define CONFIG_SYS_OR_TIMING_SRAM 0x00000D42 /* SRAM-Timing */
-#define CONFIG_SYS_OR2 (SRAM_OR_AM | CONFIG_SYS_OR_TIMING_SRAM )
-#define CONFIG_SYS_BR2 ((SRAM_BASE & BR_BA_MSK) | BR_PS_16 | BR_V )
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
-
-#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 /* SDRAM-Timing */
-#define CONFIG_SYS_OR3_PRELIM (SDRAM_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
-#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V )
-
-#define CONFIG_SYS_OR_TIMING_PER8 0x00000F32 /* PER8-Timing */
-#define CONFIG_SYS_OR4 (PER8_OR_AM | CONFIG_SYS_OR_TIMING_PER8 )
-#define CONFIG_SYS_BR4 ((PER8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
-
-#define CONFIG_SYS_OR_TIMING_SHARC 0x00000700 /* SHARC-Timing */
-#define CONFIG_SYS_OR5 (SHARC_OR_AM | CONFIG_SYS_OR_TIMING_SHARC )
-#define CONFIG_SYS_BR5 ((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V )
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CONFIG_SYS_MBMR_PTB 204
-
-/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
-#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
-#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
-
-/*
- * MBMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \
- MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \
- MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X)
-
-#endif /* __CONFIG_H */
diff --git a/include/pcmcia.h b/include/pcmcia.h
index 2ff399b..371c9a4 100644
--- a/include/pcmcia.h
+++ b/include/pcmcia.h
@@ -23,8 +23,6 @@
#if defined(CONFIG_TQM8xxL)
# define CONFIG_PCMCIA_SLOT_B /* The TQM8xxL use SLOT_B */
-#elif defined(CONFIG_SPD823TS) /* The SPD8xx use SLOT_B */
-# define CONFIG_PCMCIA_SLOT_B
#elif defined(CONFIG_IVMS8) || defined(CONFIG_IVML24) /* The IVM* use SLOT_A */
# define CONFIG_PCMCIA_SLOT_A
#elif defined(CONFIG_LWMON) /* The LWMON use SLOT_B */
--
1.9.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [U-Boot] [PATCH 06/26] mpc8xx: remove RRvision board support
2014-12-15 14:26 [U-Boot] [PATCH 0/26] Start removing non-generic boards Masahiro Yamada
` (4 preceding siblings ...)
2014-12-15 14:26 ` [U-Boot] [PATCH 05/26] mpc8xx: remove SPD823TS " Masahiro Yamada
@ 2014-12-15 14:26 ` Masahiro Yamada
2015-01-05 18:20 ` Tom Rini
2014-12-15 14:26 ` [U-Boot] [PATCH 07/26] mpc8xx: remove R360MPI " Masahiro Yamada
` (21 subsequent siblings)
27 siblings, 1 reply; 55+ messages in thread
From: Masahiro Yamada @ 2014-12-15 14:26 UTC (permalink / raw)
To: u-boot
This board is still a non-generic board.
Unused code in arch/powerpc/cpu/mpc8xx/video.c should be also deleted
because CONFIG_VIDEO_ENCODER_AD7176, CONFIG_VIDEO_ENCODER_AD7177,
CONFIG_VIDEO_ENCODER_AD7179 are not defined any more.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
---
arch/powerpc/cpu/mpc8xx/Kconfig | 4 -
arch/powerpc/cpu/mpc8xx/video.c | 148 ------------
board/RRvision/Kconfig | 9 -
board/RRvision/MAINTAINERS | 7 -
board/RRvision/Makefile | 8 -
board/RRvision/RRvision.c | 222 ------------------
board/RRvision/flash.c | 506 ----------------------------------------
board/RRvision/u-boot.lds | 87 -------
board/RRvision/video_ad7179.h | 52 -----
configs/RRvision_LCD_defconfig | 4 -
configs/RRvision_defconfig | 3 -
doc/README.scrapyard | 1 +
drivers/video/mpc8xx_lcd.c | 17 --
include/commproc.h | 5 +-
include/configs/RRvision.h | 450 -----------------------------------
include/video_ad7176.h | 89 -------
include/video_ad7177.h | 133 -----------
include/video_ad7179.h | 20 --
18 files changed, 3 insertions(+), 1762 deletions(-)
delete mode 100644 board/RRvision/Kconfig
delete mode 100644 board/RRvision/MAINTAINERS
delete mode 100644 board/RRvision/Makefile
delete mode 100644 board/RRvision/RRvision.c
delete mode 100644 board/RRvision/flash.c
delete mode 100644 board/RRvision/u-boot.lds
delete mode 100644 board/RRvision/video_ad7179.h
delete mode 100644 configs/RRvision_LCD_defconfig
delete mode 100644 configs/RRvision_defconfig
delete mode 100644 include/configs/RRvision.h
delete mode 100644 include/video_ad7176.h
delete mode 100644 include/video_ad7177.h
delete mode 100644 include/video_ad7179.h
diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig
index 8bda42e..37ee5f6 100644
--- a/arch/powerpc/cpu/mpc8xx/Kconfig
+++ b/arch/powerpc/cpu/mpc8xx/Kconfig
@@ -31,9 +31,6 @@ config TARGET_NETVIA
config TARGET_R360MPI
bool "Support R360MPI"
-config TARGET_RRVISION
- bool "Support RRvision"
-
config TARGET_TQM823L
bool "Support TQM823L"
@@ -72,7 +69,6 @@ config TARGET_TQM885D
endchoice
-source "board/RRvision/Kconfig"
source "board/cogent/Kconfig"
source "board/esteem192e/Kconfig"
source "board/ip860/Kconfig"
diff --git a/arch/powerpc/cpu/mpc8xx/video.c b/arch/powerpc/cpu/mpc8xx/video.c
index 9590bfd..659e688 100644
--- a/arch/powerpc/cpu/mpc8xx/video.c
+++ b/arch/powerpc/cpu/mpc8xx/video.c
@@ -53,34 +53,6 @@ DECLARE_GLOBAL_DATA_PTR;
#define VIDEO_INFO_Y 16
/************************************************************************/
-/* ** VIDEO ENCODER CONSTANTS */
-/************************************************************************/
-
-#ifdef CONFIG_VIDEO_ENCODER_AD7176
-
-#include <video_ad7176.h> /* Sets encoder data, mode, and visible and active area */
-
-#define VIDEO_I2C 1
-#define VIDEO_I2C_ADDR CONFIG_VIDEO_ENCODER_AD7176_ADDR
-#endif
-
-#ifdef CONFIG_VIDEO_ENCODER_AD7177
-
-#include <video_ad7177.h> /* Sets encoder data, mode, and visible and active area */
-
-#define VIDEO_I2C 1
-#define VIDEO_I2C_ADDR CONFIG_VIDEO_ENCODER_AD7177_ADDR
-#endif
-
-#ifdef CONFIG_VIDEO_ENCODER_AD7179
-
-#include <video_ad7179.h> /* Sets encoder data, mode, and visible and active area */
-
-#define VIDEO_I2C 1
-#define VIDEO_I2C_ADDR CONFIG_VIDEO_ENCODER_AD7179_ADDR
-#endif
-
-/************************************************************************/
/* ** VIDEO MODE CONSTANTS */
/************************************************************************/
@@ -467,7 +439,6 @@ static inline void video_putstring (int xx, int yy, unsigned char *s)
/* ** VIDEO CONTROLLER LOW-LEVEL FUNCTIONS */
/************************************************************************/
-#if !defined(CONFIG_RRVISION)
static void video_mode_dupefield (VRAM * source, VRAM * dest, int entries)
{
int i;
@@ -480,7 +451,6 @@ static void video_mode_dupefield (VRAM * source, VRAM * dest, int entries)
dest[0].lcyc++; /* Add a cycle to the first entry */
dest[entries - 1].lst = 1; /* Set end of ram entries */
}
-#endif
static void inline video_mode_addentry (VRAM * vr,
int Hx, int Vx, int Fx, int Bx,
@@ -641,72 +611,6 @@ static int video_mode_generate (void)
#ifdef VIDEO_MODE_PAL
-#if defined(CONFIG_RRVISION)
-
-#define HPW 160 /* horizontal pulse width (was 139) */
-#define VPW 2 /* vertical pulse width */
-#define HBP 104 /* horizontal back porch (was 112) */
-#define VBP 19 /* vertical back porch (was 19) */
-#define VID_R 240 /* number of rows */
-
- debug ("[VIDEO CTRL] Starting to add controller entries...");
-/*
- * Even field
- */
- ADDENTRY (0, 3, 0, 3, 1, 0, 2, 0, 0);
- ADDENTRY (0, 0, 0, 3, 1, 0, HPW, 0, 0);
- ADDENTRY (3, 0, 0, 3, 1, 0, HBP + (VIDEO_COLS * 2) + 72, 0, 0);
-
- ADDENTRY (0, 0, 0, 3, 1, 0, VPW, 1, 0);
- ADDENTRY (0, 0, 0, 3, 1, 0, HPW-1, 0, 0);
- ADDENTRY (3, 0, 0, 3, 1, 0, HBP + (VIDEO_COLS * 2) + 72, 1, 0);
-
- ADDENTRY (0, 3, 0, 3, 1, 0, VBP, 1, 0);
- ADDENTRY (0, 3, 0, 3, 1, 0, HPW-1, 0, 0);
- ADDENTRY (3, 3, 0, 3, 1, 0, HBP + (VIDEO_COLS * 2) + 72, 1, 0);
-/*
- * Active area
- */
- ADDENTRY (0, 3, 0, 3, 1, 0, VID_R , 1, 0);
- ADDENTRY (0, 3, 0, 3, 1, 0, HPW-1, 0, 0);
- ADDENTRY (3, 3, 0, 3, 1, 0, HBP, 0, 0);
- ADDENTRY (3, 3, 0, 3, 0, 0, VIDEO_COLS*2, 0, 0);
- ADDENTRY (3, 3, 0, 3, 1, 0, 72, 1, 1);
-
- ADDENTRY (0, 3, 0, 3, 1, 0, 51, 1, 0);
- ADDENTRY (0, 3, 0, 3, 1, 0, HPW-1, 0, 0);
- ADDENTRY (3, 3, 0, 3, 1, 0, HBP +(VIDEO_COLS * 2) + 72 , 1, 0);
-/*
- * Odd field
- */
- ADDENTRY (0, 3, 0, 3, 1, 0, 2, 0, 0);
- ADDENTRY (0, 0, 0, 3, 1, 0, HPW, 0, 0);
- ADDENTRY (3, 0, 0, 3, 1, 0, HBP + (VIDEO_COLS * 2) + 72, 0, 0);
-
- ADDENTRY (0, 0, 0, 3, 1, 0, VPW+1, 1, 0);
- ADDENTRY (0, 0, 0, 3, 1, 0, HPW-1, 0, 0);
- ADDENTRY (3, 0, 0, 3, 1, 0, HBP + (VIDEO_COLS * 2) + 72, 1, 0);
-
- ADDENTRY (0, 3, 0, 3, 1, 0, VBP, 1, 0);
- ADDENTRY (0, 3, 0, 3, 1, 0, HPW-1, 0, 0);
- ADDENTRY (3, 3, 0, 3, 1, 0, HBP + (VIDEO_COLS * 2) + 72, 1, 0);
-/*
- * Active area
- */
- ADDENTRY (0, 3, 0, 3, 1, 0, VID_R , 1, 0);
- ADDENTRY (0, 3, 0, 3, 1, 0, HPW-1, 0, 0);
- ADDENTRY (3, 3, 0, 3, 1, 0, HBP, 0, 0);
- ADDENTRY (3, 3, 0, 3, 0, 0, VIDEO_COLS*2, 0, 0);
- ADDENTRY (3, 3, 0, 3, 1, 0, 72, 1, 1);
-
- ADDENTRY (0, 3, 0, 3, 1, 0, 51, 1, 0);
- ADDENTRY (0, 3, 0, 3, 1, 0, HPW-1, 0, 0);
- ADDENTRY (3, 3, 0, 3, 1, 0, HBP +(VIDEO_COLS * 2) + 72 , 1, 0);
-
- debug ("done\n");
-
-#else /* !CONFIG_RRVISION */
-
/*
* Hx Vx Fx Bx VDS INT LCYC LP LST
*
@@ -758,7 +662,6 @@ static int video_mode_generate (void)
* one more cycle loop and a last identifier)
*/
video_mode_dupefield (vr, &vr[entry], entry);
-#endif /* CONFIG_RRVISION */
#endif /* VIDEO_MODE_PAL */
@@ -787,42 +690,6 @@ static int video_mode_generate (void)
static void video_encoder_init (void)
{
-#ifdef VIDEO_I2C
- int rc;
-
- /* Initialize the I2C */
- debug ("[VIDEO ENCODER] Initializing I2C bus...\n");
-#ifdef CONFIG_SYS_I2C
- i2c_init_all();
-#else
- i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-#endif
-
- /* Send configuration */
-#ifdef DEBUG
- {
- int i;
-
- puts ("[VIDEO ENCODER] Configuring the encoder...\n");
-
- printf ("Sending %zu bytes (@ %08lX) to I2C 0x%lX:\n ",
- sizeof(video_encoder_data),
- (ulong)video_encoder_data,
- (ulong)VIDEO_I2C_ADDR);
- for (i=0; i<sizeof(video_encoder_data); ++i) {
- printf(" %02X", video_encoder_data[i]);
- }
- putc ('\n');
- }
-#endif /* DEBUG */
-
- if ((rc = i2c_write (VIDEO_I2C_ADDR, 0, 1,
- video_encoder_data,
- sizeof(video_encoder_data))) != 0) {
- printf ("i2c_send error: rc=%d\n", rc);
- return;
- }
-#endif /* VIDEO_I2C */
return;
}
@@ -866,21 +733,6 @@ static void video_ctrl_init (void *memptr)
immap->im_ioport.iop_pdpar = 0x1fff;
immap->im_ioport.iop_pddir = 0x0000;
-#ifdef CONFIG_RRVISION
- debug ("PC5->Output(1): enable PAL clock");
- immap->im_ioport.iop_pcpar &= ~(0x0400);
- immap->im_ioport.iop_pcdir |= 0x0400 ;
- immap->im_ioport.iop_pcdat |= 0x0400 ;
- debug ("PDPAR=0x%04X PDDIR=0x%04X PDDAT=0x%04X\n",
- immap->im_ioport.iop_pdpar,
- immap->im_ioport.iop_pddir,
- immap->im_ioport.iop_pddat);
- debug ("PCPAR=0x%04X PCDIR=0x%04X PCDAT=0x%04X\n",
- immap->im_ioport.iop_pcpar,
- immap->im_ioport.iop_pcdir,
- immap->im_ioport.iop_pcdat);
-#endif /* CONFIG_RRVISION */
-
/* Blanking the screen. */
debug ("[VIDEO CTRL] Blanking the screen...\n");
video_fill (VIDEO_BG_COL);
diff --git a/board/RRvision/Kconfig b/board/RRvision/Kconfig
deleted file mode 100644
index 7c8a6f6..0000000
--- a/board/RRvision/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_RRVISION
-
-config SYS_BOARD
- default "RRvision"
-
-config SYS_CONFIG_NAME
- default "RRvision"
-
-endif
diff --git a/board/RRvision/MAINTAINERS b/board/RRvision/MAINTAINERS
deleted file mode 100644
index 59b5c5f..0000000
--- a/board/RRvision/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-RRVISION BOARD
-M: Wolfgang Denk <wd@denx.de>
-S: Maintained
-F: board/RRvision/
-F: include/configs/RRvision.h
-F: configs/RRvision_defconfig
-F: configs/RRvision_LCD_defconfig
diff --git a/board/RRvision/Makefile b/board/RRvision/Makefile
deleted file mode 100644
index 908e8f8..0000000
--- a/board/RRvision/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = RRvision.o flash.o
diff --git a/board/RRvision/RRvision.c b/board/RRvision/RRvision.c
deleted file mode 100644
index d94e238..0000000
--- a/board/RRvision/RRvision.c
+++ /dev/null
@@ -1,222 +0,0 @@
-/*
- * (C) Copyright 2001-2002
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-/* ------------------------------------------------------------------------- */
-
-static long int dram_size (long int, long int *, long int);
-
-/* ------------------------------------------------------------------------- */
-
-#define _NOT_USED_ 0xFFFFFFFF
-
-const uint sdram_table[] =
-{
- /*
- * Single Read. (Offset 0 in UPMA RAM)
- */
- 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
- 0x1FF77C47, /* last */
- /*
- * SDRAM Initialization (offset 5 in UPMA RAM)
- *
- * This is no UPM entry point. The following definition uses
- * the remaining space to establish an initialization
- * sequence, which is executed by a RUN command.
- *
- */
- 0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */
- /*
- * Burst Read. (Offset 8 in UPMA RAM)
- */
- 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
- 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Single Write. (Offset 18 in UPMA RAM)
- */
- 0x1F07FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Burst Write. (Offset 20 in UPMA RAM)
- */
- 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
- 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
- _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Refresh (Offset 30 in UPMA RAM)
- */
- 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
- 0xFFFFFC84, 0xFFFFFC07, /* last */
- _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Exception. (Offset 3c in UPMA RAM)
- */
- 0x7FFFFC07, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
-};
-
-/* ------------------------------------------------------------------------- */
-
-
-/*
- * Check Board Identity:
- *
- * Always return 1 (no second DRAM bank).
- */
-
-int checkboard (void)
-{
- char buf[64];
- int i;
- int l = getenv_f("serial#", buf, sizeof(buf));
-
- puts ("Board: RRvision ");
-
- for (i=0; i < l; ++i) {
- if (buf[i] == ' ')
- break;
- putc (buf[i]);
- }
-
- putc ('\n');
-
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- unsigned long reg;
- long int size8, size9;
- long int size = 0;
-
- upmconfig (UPMA, (uint *)sdram_table, sizeof(sdram_table) / sizeof(uint));
-
- /*
- * Preliminary prescaler for refresh (depends on number of
- * banks): This value is selected for four cycles every 62.4 us
- * with two SDRAM banks or four cycles every 31.2 us with one
- * bank. It will be adjusted after memory sizing.
- */
- memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
-
- memctl->memc_mar = 0x00000088;
-
- /*
- * Map controller bank 1 the SDRAM bank 2 at physical address 0.
- */
- memctl->memc_or1 = CONFIG_SYS_OR2_PRELIM;
- memctl->memc_br1 = CONFIG_SYS_BR2_PRELIM;
-
- memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
-
- udelay (200);
-
- /* perform SDRAM initializsation sequence */
-
- memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */
- udelay (1);
- memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - execute twice */
- udelay (1);
-
- memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
-
- udelay (1000);
-
- /*
- * Check Bank 0 Memory Size
- *
- * try 8 column mode
- */
- size8 = dram_size (CONFIG_SYS_MAMR_8COL,
- SDRAM_BASE2_PRELIM,
- SDRAM_MAX_SIZE);
-
- udelay (1000);
-
- /*
- * try 9 column mode
- */
- size9 = dram_size (CONFIG_SYS_MAMR_9COL,
- SDRAM_BASE2_PRELIM,
- SDRAM_MAX_SIZE);
-
- if (size8 < size9) { /* leave configuration@9 columns */
- size = size9;
-/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
- } else { /* back to 8 columns */
- size = size8;
- memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
- udelay (500);
-/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
- }
-
- udelay (1000);
-
- /*
- * Adjust refresh rate depending on SDRAM type
- * For types > 128 MBit leave it at the current (fast) rate
- */
- if (size < 0x02000000) {
- /* reduce to 15.6 us (62.4 us / quad) */
- memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
- udelay (1000);
- }
-
- /*
- * Final mapping
- */
- memctl->memc_or1 = ((-size) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
- memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
-
- /*
- * No bank 1
- *
- * invalidate bank
- */
- memctl->memc_br3 = 0;
-
- /* adjust refresh rate depending on SDRAM type, one bank */
- reg = memctl->memc_mptpr;
- reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
- memctl->memc_mptpr = reg;
-
- udelay (10000);
-
- return (size);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-
-static long int dram_size (long int mamr_value, long int *base,
- long int maxsize)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
- memctl->memc_mamr = mamr_value;
-
- return (get_ram_size(base, maxsize));
-}
diff --git a/board/RRvision/flash.c b/board/RRvision/flash.c
deleted file mode 100644
index 146a923..0000000
--- a/board/RRvision/flash.c
+++ /dev/null
@@ -1,506 +0,0 @@
-/*
- * (C) Copyright 2000-2002
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#define DEBUG
-
-#include <common.h>
-#include <mpc8xx.h>
-
-#ifndef CONFIG_ENV_ADDR
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-#endif
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- unsigned long size;
- int i;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size, size<<20);
- }
-
- /* Remap FLASH according to real size */
- memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & OR_AM_MSK);
- memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
-
- /* Re-do sizing to get full correct info */
- size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[0]);
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
- &flash_info[0]);
-#endif
-
- flash_info[0].size = size;
-
- return (size);
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- puts ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: puts ("AMD "); break;
- case FLASH_MAN_FUJ: puts ("FUJITSU "); break;
- default: puts ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM400B: puts ("AM29LV400B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400T: puts ("AM29LV400T (4 Mbit, top boot sector)\n");
- break;
- case FLASH_AM800B: puts ("AM29LV800B (8 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM800T: puts ("AM29LV800T (8 Mbit, top boot sector)\n");
- break;
- case FLASH_AM160B: puts ("AM29LV160B (16 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM160T: puts ("AM29LV160T (16 Mbit, top boot sector)\n");
- break;
- case FLASH_AM320B: puts ("AM29LV320B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM320T: puts ("AM29LV320T (32 Mbit, top boot sector)\n");
- break;
- default: puts ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- puts (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- puts ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- puts ("\n");
- return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
- short i;
- ulong value;
- ulong base = (ulong)addr;
-
- /* Write auto select command: read Manufacturer ID */
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
- addr[0x0555] = 0x00900090;
-
- value = addr[0];
-
- switch (value) {
- case AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
- case FUJ_MANUFACT:
- info->flash_id = FLASH_MAN_FUJ;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
- value = addr[1]; /* device ID */
-
- switch (value) {
- case AMD_ID_LV400T:
- info->flash_id += FLASH_AM400T;
- info->sector_count = 11;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case AMD_ID_LV400B:
- info->flash_id += FLASH_AM400B;
- info->sector_count = 11;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case AMD_ID_LV800T:
- info->flash_id += FLASH_AM800T;
- info->sector_count = 19;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case AMD_ID_LV800B:
- info->flash_id += FLASH_AM800B;
- info->sector_count = 19;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case AMD_ID_LV160T:
- info->flash_id += FLASH_AM160T;
- info->sector_count = 35;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case AMD_ID_LV160B:
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00400000;
- break; /* => 4 MB */
- case AMD_ID_LV320T:
- info->flash_id += FLASH_AM320T;
- info->sector_count = 71;
- info->size = 0x00800000;
- break; /* => 8 MB */
-
- case AMD_ID_LV320B:
- info->flash_id += FLASH_AM320B;
- info->sector_count = 71;
- info->size = 0x00800000;
- break; /* => 8 MB */
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
- }
-
- /* set up sector start address table */
- switch (value) {
- case AMD_ID_LV400B:
- case AMD_ID_LV800B:
- case AMD_ID_LV160B:
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00008000;
- info->start[2] = base + 0x0000C000;
- info->start[3] = base + 0x00010000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00020000) - 0x00060000;
- }
- break;
- case AMD_ID_LV400T:
- case AMD_ID_LV800T:
- case AMD_ID_LV160T:
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00008000;
- info->start[i--] = base + info->size - 0x0000C000;
- info->start[i--] = base + info->size - 0x00010000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00020000;
- }
- break;
- case AMD_ID_LV320B:
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base;
- /*
- * The first 8 sectors are 8 kB,
- * all the other ones are 64 kB
- */
- base += (i < 8)
- ? 2 * ( 8 << 10)
- : 2 * (64 << 10);
- }
- break;
- case AMD_ID_LV320T:
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base;
- /*
- * The last 8 sectors are 8 kB,
- * all the other ones are 64 kB
- */
- base += (i < (info->sector_count - 8))
- ? 2 * (64 << 10)
- : 2 * ( 8 << 10);
- }
- break;
- default:
- return (0);
- break;
- }
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- addr = (volatile unsigned long *)(info->start[i]);
- info->protect[i] = addr[2] & 1;
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- addr = (volatile unsigned long *)info->start[0];
-
- *addr = 0x00F000F0; /* reset bank */
- }
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- vu_long *addr = (vu_long*)(info->start[0]);
- int flag, prot, sect, l_sect;
- ulong start, now, last;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- puts ("- missing\n");
- } else {
- puts ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id == FLASH_UNKNOWN) ||
- (info->flash_id > FLASH_AMD_COMP)) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- puts ("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
- addr[0x0555] = 0x00800080;
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = (vu_long*)(info->start[sect]);
- addr[0] = 0x00300030;
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer (0);
- last = start;
- addr = (vu_long*)(info->start[l_sect]);
- while ((addr[0] & 0x00800080) != 0x00800080) {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- puts ("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
-DONE:
- /* reset to read mode */
- addr = (volatile unsigned long *)info->start[0];
- addr[0] = 0x00F000F0; /* reset bank */
-
- puts (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i=0; i<4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
- vu_long *addr = (vu_long*)(info->start[0]);
- ulong start;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((vu_long *)dest) & data) != data) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
- addr[0x0555] = 0x00A000A0;
-
- *((vu_long *)dest) = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
diff --git a/board/RRvision/u-boot.lds b/board/RRvision/u-boot.lds
deleted file mode 100644
index 9470a24..0000000
--- a/board/RRvision/u-boot.lds
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
- arch/powerpc/cpu/mpc8xx/start.o (.text*)
- arch/powerpc/cpu/mpc8xx/traps.o (.text*)
-
- . = env_offset;
- common/env_embedded.o (.ppcenv)
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
diff --git a/board/RRvision/video_ad7179.h b/board/RRvision/video_ad7179.h
deleted file mode 100644
index 1fc1ef4..0000000
--- a/board/RRvision/video_ad7179.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * (C) Copyright 2003 Wolfgang Grandegger <wg@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#define VIDEO_ENCODER_NAME "Analog Devices AD7179"
-
-#define VIDEO_ENCODER_I2C_RATE 100000 /* Max rate is 100Khz */
-#define VIDEO_ENCODER_CB_Y_CR_Y /* Use CB Y CR Y format... */
-
-#define VIDEO_MODE_YUYV /* The only mode supported by this encoder */
-#undef VIDEO_MODE_RGB
-#define VIDEO_MODE_BPP 16
-
-#ifdef VIDEO_MODE_PAL
-#define VIDEO_ACTIVE_COLS 720
-#define VIDEO_ACTIVE_ROWS 576
-#define VIDEO_VISIBLE_COLS 640
-#define VIDEO_VISIBLE_ROWS 480
-#else
-#error "NTSC mode is not supported"
-#endif
-
-static unsigned char video_encoder_data[] = {
- 0x05, /* Mode Register 0 */
- 0x11, /* Mode Register 1 */
- 0x20, /* Mode Register 2 */
- 0x0C, /* Mode Register 3 */
- 0x01, /* Mode Register 4 */
- 0x00, /* Reserved */
- 0x00, /* Reserved */
- 0x04, /* Timing Register 0 */
- 0x00, /* Timing Register 1 */
- 0xCB, /* Subcarrier Frequency Register 0 */
- 0x0A, /* Subcarrier Frequency Register 1 */
- 0x09, /* Subcarrier Frequency Register 2 */
- 0x2A, /* Subcarrier Frequency Register 3 */
- 0x00, /* Subcarrier Phase */
- 0x00, /* Closed Captioning Ext Reg 0 */
- 0x00, /* Closed Captioning Ext Reg 1 */
- 0x00, /* Closed Captioning Reg 0 */
- 0x00, /* Closed Captioning Reg 1 */
- 0x00, /* Pedestal Control Reg 0 */
- 0x00, /* Pedestal Control Reg 1 */
- 0x00, /* Pedestal Control Reg 2 */
- 0x00, /* Pedestal Control Reg 3 */
- 0x00, /* CGMS_WSS Reg 0 */
- 0x00, /* CGMS_WSS Reg 0 */
- 0x00, /* CGMS_WSS Reg 0 */
- 0x00 /* Teletext Req. Control Reg */
-} ;
diff --git a/configs/RRvision_LCD_defconfig b/configs/RRvision_LCD_defconfig
deleted file mode 100644
index 4d61187..0000000
--- a/configs/RRvision_LCD_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="LCD,SHARP_LQ104V7DS01"
-CONFIG_PPC=y
-CONFIG_8xx=y
-CONFIG_TARGET_RRVISION=y
diff --git a/configs/RRvision_defconfig b/configs/RRvision_defconfig
deleted file mode 100644
index bdb4d7a..0000000
--- a/configs/RRvision_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_8xx=y
-CONFIG_TARGET_RRVISION=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 623a30e..00a5447 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+RRvision powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
SPD823TS powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
KUP4K powerpc mpc8xx - - Klaus Heydeck <heydeck@kieback-peter.de>
KUP4X powerpc mpc8xx - - Klaus Heydeck <heydeck@kieback-peter.de>
diff --git a/drivers/video/mpc8xx_lcd.c b/drivers/video/mpc8xx_lcd.c
index 2bc3ceb..a5c1e19 100644
--- a/drivers/video/mpc8xx_lcd.c
+++ b/drivers/video/mpc8xx_lcd.c
@@ -448,23 +448,6 @@ void lcd_enable (void)
r360_i2c_lcd_write(0x40 | ((ctr>>8) & 0xF), ctr & 0xFF);
}
#endif /* CONFIG_R360MPI */
-#ifdef CONFIG_RRVISION
- debug ("PC4->Output(1): enable LVDS\n");
- debug ("PC5->Output(0): disable PAL clock\n");
- immr->im_ioport.iop_pddir |= 0x1000;
- immr->im_ioport.iop_pcpar &= ~(0x0C00);
- immr->im_ioport.iop_pcdir |= 0x0C00 ;
- immr->im_ioport.iop_pcdat |= 0x0800 ;
- immr->im_ioport.iop_pcdat &= ~(0x0400);
- debug ("PDPAR=0x%04X PDDIR=0x%04X PDDAT=0x%04X\n",
- immr->im_ioport.iop_pdpar,
- immr->im_ioport.iop_pddir,
- immr->im_ioport.iop_pddat);
- debug ("PCPAR=0x%04X PCDIR=0x%04X PCDAT=0x%04X\n",
- immr->im_ioport.iop_pcpar,
- immr->im_ioport.iop_pcdir,
- immr->im_ioport.iop_pcdat);
-#endif
}
/************************************************************************/
diff --git a/include/commproc.h b/include/commproc.h
index 4c39934..7d62861 100644
--- a/include/commproc.h
+++ b/include/commproc.h
@@ -631,10 +631,9 @@ typedef struct scc_enet {
#if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \
defined(CONFIG_R360MPI) || \
- defined(CONFIG_RRVISION)|| defined(CONFIG_TQM823L) || \
+ defined(CONFIG_TQM823L) || \
defined(CONFIG_TQM823M) || defined(CONFIG_TQM850L) || \
- defined(CONFIG_TQM850M) || defined(CONFIG_TQM885D) || \
- defined(CONFIG_RRVISION)
+ defined(CONFIG_TQM850M) || defined(CONFIG_TQM885D)
/* Bits in parallel I/O port registers that have to be set/cleared
* to configure the pins for SCC2 use.
diff --git a/include/configs/RRvision.h b/include/configs/RRvision.h
deleted file mode 100644
index 97f7798..0000000
--- a/include/configs/RRvision.h
+++ /dev/null
@@ -1,450 +0,0 @@
-/*
- * (C) Copyright 2000, 2001, 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
-#define CONFIG_RRVISION 1 /* ...on a RRvision board */
-
-#define CONFIG_SYS_TEXT_BASE 0x40000000
-
-#define CONFIG_8xx_GCLK_FREQ 64000000
-
-#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
-#endif
-
-#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
-
-#define CONFIG_PREBOOT "setenv stdout serial"
-
-#undef CONFIG_BOOTARGS
-#define CONFIG_ETHADDR 00:50:C2:00:E0:70
-#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
-#define CONFIG_IPADDR 10.0.0.5
-#define CONFIG_SERVERIP 10.0.0.2
-#define CONFIG_NETMASK 255.0.0.0
-#define CONFIG_ROOTPATH "/opt/eldk/ppc_8xx"
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}" \
- ":${gatewayip}:${netmask}:${hostname}:${netdev}:off\0" \
- "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
- "load=tftp 100000 /tftpboot/u-boot.bin\0" \
- "update=protect off 1:0-8;era 1:0-8;" \
- "cp.b 100000 40000000 ${filesize};" \
- "setenv filesize;saveenv\0" \
- "kernel_addr=40040000\0" \
- "ramdisk_addr=40100000\0" \
- "kernel_img=/tftpboot/uImage\0" \
- "kernel_load=tftp 200000 ${kernel_img}\0" \
- "net_nfs=run kernel_load nfsargs addip addtty;bootm\0" \
- "flash_nfs=run nfsargs addip addtty;bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip addtty;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0"
-
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#undef CONFIG_STATUS_LED /* disturbs display */
-
-#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-
-
-#ifdef CONFIG_LCD
-#define CONFIG_MPC8XX_LCD
-#else
-#define CONFIG_VIDEO 1 /* To enable the video initialization */
-
-/* Video related */
-#define CONFIG_VIDEO_LOGO 1 /* Show the logo */
-#define CONFIG_VIDEO_ENCODER_AD7179 1 /* Enable this encoder */
-#define CONFIG_VIDEO_ENCODER_AD7179_ADDR 0x2A /* ALSB to ground */
-#endif
-
-/* enable I2C and select the hardware/software driver */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED 50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define PB_SCL 0x00000020 /* PB 26 */
-#define PB_SDA 0x00000010 /* PB 27 */
-
-#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
-#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
-#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
-#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
-#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
- else immr->im_cpm.cp_pbdat &= ~PB_SDA
-#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
- else immr->im_cpm.cp_pbdat &= ~PB_SCL
-#define I2C_DELAY udelay(1) /* 1/4 I2C clock duration */
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_DATE
-
-#undef CONFIG_CMD_PCMCIA
-#undef CONFIG_CMD_IDE
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xFFF00000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0x40000000
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
-
-/* timeout values are in ticks = ms */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (120*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT (1 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-
-#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#ifndef CONFIG_CAN_DRIVER
-#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-#else /* we must activate GPL5 in the SIUMCR for CAN */
-#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-#endif /* CONFIG_CAN_DRIVER */
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register 11-27
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit
- */
-
-/* for 64 MHz, we use a 16 MHz clock * 4 */
-#define CONFIG_SYS_PLPRCR ( (4-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK SCCR_EBDF11
-#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_RTSEL | SCCR_RTDIV | \
- SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
- SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
- SCCR_DFALCD00)
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
- *-----------------------------------------------------------------------
- */
-
-#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
-#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
-
-#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
-#undef CONFIG_IDE_LED /* LED for ide not supported */
-#undef CONFIG_IDE_RESET /* reset for ide not supported */
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-/*#define CONFIG_SYS_DER 0x2002000F*/
-#define CONFIG_SYS_DER 0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
-
-/*
- * FLASH timing:
- */
-/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
-#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
- OR_SCY_3_CLK | OR_EHTR | OR_BI)
-
-#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
-
-/*
- * BR2/3 and OR2/3 (SDRAM)
- *
- */
-#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
-#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
-#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
-#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
-
-#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
-#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-#ifndef CONFIG_CAN_DRIVER
-#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
-#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
-#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped@0xC0000000 */
-#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
-#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
-#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
- BR_PS_8 | BR_MS_UPMB | BR_V )
-#endif /* CONFIG_CAN_DRIVER */
-
-/*
- * Memory Periodic Timer Prescaler
- *
- * The Divider for PTA (refresh timer) configuration is based on an
- * example SDRAM configuration (64 MBit, one bank). The adjustment to
- * the number of chip selects (NCS) and the actually needed refresh
- * rate is done by setting MPTPR.
- *
- * PTA is calculated from
- * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
- *
- * gclk CPU clock (not bus clock!)
- * Trefresh Refresh cycle * 4 (four word bursts used)
- *
- * 4096 Rows from SDRAM example configuration
- * 1000 factor s -> ms
- * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
- * 4 Number of refresh cycles per period
- * 64 Refresh cycle in ms per number of rows
- * --------------------------------------------
- * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
- *
- * 50 MHz => 50.000.000 / Divider = 98
- * 66 Mhz => 66.000.000 / Divider = 129
- * 80 Mhz => 80.000.000 / Divider = 156
- */
-#define CONFIG_SYS_MAMR_PTA 129
-
-/*
- * For 16 MBit, refresh rates could be 31.3 us
- * (= 64 ms / 2K = 125 / quad bursts).
- * For a simpler initialization, 15.6 us is used instead.
- *
- * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
- * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
- */
-#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
-#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-/* 9 column SDRAM */
-#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-
-#endif /* __CONFIG_H */
diff --git a/include/video_ad7176.h b/include/video_ad7176.h
deleted file mode 100644
index 6a0230e..0000000
--- a/include/video_ad7176.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * (C) Copyright 2000
- * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio at tin.it
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _VIDEO_AD7176_H_
-#define _VIDEO_AD7176_H_
-
-#define VIDEO_ENCODER_NAME "Analog Devices AD7176"
-
-#define VIDEO_ENCODER_I2C_RATE 100000 /* Max rate is 100 kHz */
-#define VIDEO_ENCODER_CB_Y_CR_Y /* Use CB Y CR Y format... */
-
-#define VIDEO_MODE_YUYV /* The only mode supported by this encoder */
-#undef VIDEO_MODE_RGB
-#define VIDEO_MODE_BPP 16
-
-#ifdef VIDEO_MODE_PAL
-#define VIDEO_ACTIVE_COLS 720
-#define VIDEO_ACTIVE_ROWS 576
-#define VIDEO_VISIBLE_COLS 640
-#define VIDEO_VISIBLE_ROWS 480
-#endif
-
-#ifdef VIDEO_MODE_NTSC
-#define VIDEO_ACTIVE_COLS 720
-#define VIDEO_ACTIVE_ROWS 525
-#define VIDEO_VISIBLE_COLS 640
-#define VIDEO_VISIBLE_ROWS 400
-#endif
-
-static unsigned char video_encoder_data[] = {
-#ifdef VIDEO_MODE_NTSC
- 0x04, /* Mode Register 0 */
-#ifdef VIDEO_DEBUG_COLORBARS
- 0x82,
-#else
- 0x02, /* Mode Register 1 */
-#endif /* VIDEO_DEBUG_COLORBARS */
- 0x16, /* Subcarrier Freq 0 */
- 0x7c, /* Subcarrier Freq 1 */
- 0xf0, /* Subcarrier Freq 2 */
- 0x21, /* Subcarrier Freq 3 */
- 0x00, /* Subcarrier phase */
- 0x02, /* Timing Register 0 */
- 0x00, /* Extended Captioning 0 */
- 0x00, /* Extended Captioning 1 */
- 0x00, /* Closed Captioning 0 */
- 0x00, /* Closed Captioning 1 */
- 0x00, /* Timing Register 1 */
- 0x08, /* Mode Register 2 */
- 0x00, /* Pedestal Register 0 */
- 0x00, /* Pedestal Register 1 */
- 0x00, /* Pedestal Register 2 */
- 0x00, /* Pedestal Register 3 */
- 0x00 /* Mode Register 3 */
-
-#endif /* VIDEO_MODE_NTSC */
-
-#ifdef VIDEO_MODE_PAL
- 0x05, /* Mode Register 0 */
-#ifdef VIDEO_DEBUG_COLORBARS
- 0x82,
-#else
- 0x02, /* Mode Register 1 (2) */
-#endif /* VIDEO_DEBUG_COLORBARS */
- 0xcb, /* Subcarrier Freq 0 */
- 0x8a, /* Subcarrier Freq 1 */
- 0x09, /* Subcarrier Freq 2 */
- 0x2a, /* Subcarrier Freq 3 */
- 0x00, /* Subcarrier phase */
- 0x0a, /* Timing Register 0 (a) */
- 0x00, /* Extended Captioning 0 */
- 0x00, /* Extended Captioning 1 */
- 0x00, /* Closed Captioning 0 */
- 0x00, /* Closed Captioning 1 */
- 0x00, /* Timing Register 1 */
- 0x08, /* Mode Register 2 (8) */
- 0x00, /* Pedestal Register 0 */
- 0x00, /* Pedestal Register 1 */
- 0x00, /* Pedestal Register 2 */
- 0x00, /* Pedestal Register 3 */
- 0x00 /* Mode Register 3 */
-#endif /* VIDEO_MODE_PAL */
-} ;
-
-#endif /* _VIDEO_AD7176_H_ */
diff --git a/include/video_ad7177.h b/include/video_ad7177.h
deleted file mode 100644
index 38436d6..0000000
--- a/include/video_ad7177.h
+++ /dev/null
@@ -1,133 +0,0 @@
-/*
- * (C) Copyright 2000
- * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio at tin.it
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _VIDEO_AD7177_H_
-#define _VIDEO_AD7177_H_
-
-/* #define VIDEO_DEBUG_DISABLE_COLORS 0 */
-
-#define VIDEO_ENCODER_NAME "Analog Devices AD7177"
-
-#define VIDEO_ENCODER_I2C_RATE 100000 /* Max rate is 100 kHz */
-#define VIDEO_ENCODER_CB_Y_CR_Y /* Use CB Y CR Y format... */
-
-#define VIDEO_MODE_YUYV /* The only mode supported by this encoder */
-#undef VIDEO_MODE_RGB
-#define VIDEO_MODE_BPP 16
-
-#ifdef VIDEO_MODE_PAL
-#define VIDEO_ACTIVE_COLS 720
-#define VIDEO_ACTIVE_ROWS 576
-#define VIDEO_VISIBLE_COLS 640
-#define VIDEO_VISIBLE_ROWS 480
-#endif
-
-#ifdef VIDEO_MODE_NTSC
-#define VIDEO_ACTIVE_COLS 720
-#define VIDEO_ACTIVE_ROWS 525
-#define VIDEO_VISIBLE_COLS 640
-#define VIDEO_VISIBLE_ROWS 400
-#endif
-
-static unsigned char
- video_encoder_data[] = {
-#ifdef VIDEO_MODE_NTSC
- 0x04, /* Mode Register 0 */
-#ifdef VIDEO_DEBUG_COLORBARS
- 0xc2,
-#else
- 0x42, /* Mode Register 1 */
-#endif /* VIDEO_DEBUG_COLORBARS */
- 0x16, /* Subcarrier Freq 0 */
- 0x7c, /* Subcarrier Freq 1 */
- 0xf0, /* Subcarrier Freq 2 */
- 0x21, /* Subcarrier Freq 3 */
- 0x00, /* Subcarrier phase */
- 0x02, /* Timing Register 0 */
- 0x00, /* Extended Captioning 0 */
- 0x00, /* Extended Captioning 1 */
- 0x00, /* Closed Captioning 0 */
- 0x00, /* Closed Captioning 1 */
- 0x00, /* Timing Register 1 */
- 0x08, /* Mode Register 2 */
- 0x00, /* Pedestal Register 0 */
- 0x00, /* Pedestal Register 1 */
- 0x00, /* Pedestal Register 2 */
- 0x00, /* Pedestal Register 3 */
- 0x08, /* Mode Register 3 */
-
-#endif /* VIDEO_MODE_NTSC */
-
-#ifdef VIDEO_MODE_PAL
-#ifdef VIDEO_MODE_RGB_OUT
-
- 0x69, /* Mode Register 0 */
-#ifdef VIDEO_DEBUG_COLORBARS
- 0xc0, /* Mode Register 1 (c0) */
-#else
- 0x40, /* Mode Register 1 (c0) */
-#endif /* VIDEO_DEBUG_COLORBARS */
- 0xcb, /* Subcarrier Freq 0 */
- 0x8a, /* Subcarrier Freq 1 */
- 0x09, /* Subcarrier Freq 2 */
- 0x2a, /* Subcarrier Freq 3 */
- 0x00, /* Subcarrier phase */
- 0x02, /* Timing Register 0 */
- 0x00, /* Extended Captioning 0 */
- 0x00, /* Extended Captioning 1 */
- 0x00, /* Closed Captioning 0 */
- 0x00, /* Closed Captioning 1 */
- 0x00, /* Timing Register 1 */
- 0x28, /* Mode Register 2 */
- 0x00, /* Pedestal Register 0 */
- 0x00, /* Pedestal Register 1 */
- 0x00, /* Pedestal Register 2 */
- 0x00, /* Pedestal Register 3 */
- 0x08, /* Mode Register 3 */
-
-#else /* ! VIDEO_MODE_RGB_OUT */
-
- 0x09, /* Mode Register 0 (was 01) */
-#ifdef VIDEO_DEBUG_COLORBARS
- 0xd8, /* */
-#else
- 0x59, /* Mode Register 1 (was 58) */
-#endif /* VIDEO_DEBUG_COLORBARS */
- 0xcb, /* Subcarrier Freq 0 */
- 0x8a, /* Subcarrier Freq 1 */
- 0x09, /* Subcarrier Freq 2 */
- 0x2a, /* Subcarrier Freq 3 */
- 0x00, /* Subcarrier phase */
- 0x02, /* Timing Register 0 (was a) */
- 0x00, /* Extended Captioning 0 */
- 0x00, /* Extended Captioning 1 */
- 0x00, /* Closed Captioning 0 */
- 0x00, /* Closed Captioning 1 */
- 0x00, /* Timing Register 1 */
-#ifdef VIDEO_DEBUG_LOWPOWER
-#ifdef VIDEO_DEBUG_DISABLE_COLORS
- 0x98, /* Mode Register 2 */
-#else
- 0x88, /* Mode Register 2 */
-#endif /* VIDEO_DEBUG_DISABLE_COLORS */
-#else /* ! VIDEO_DEBUG_LOWPOWER */
-#ifdef VIDEO_DEBUG_DISABLE_COLORS
- 0x18, /* Mode Register 2 */
-#else
- 0x08, /* Mode Register 2 */
-#endif /* VIDEO_DEBUG_DISABLE_COLORS */
-#endif /* VIDEO_DEBUG_LOWPOWER */
- 0x00, /* Pedestal Register 0 */
- 0x00, /* Pedestal Register 1 */
- 0x00, /* Pedestal Register 2 */
- 0x00, /* Pedestal Register 3 */
- 0x08 /* Mode Register 3 */
-#endif /* VIDEO_MODE_RGB_OUT */
-#endif /* VIDEO_MODE_PAL */
- } ;
-
-#endif /* _VIDEO_AD7177_H_ */
diff --git a/include/video_ad7179.h b/include/video_ad7179.h
deleted file mode 100644
index 67c1ec0..0000000
--- a/include/video_ad7179.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * (C) Copyright 2003 Wolfgang Grandegger <wg@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _VIDEO_AD7179_H_
-#define _VIDEO_AD7179_H_
-
-/*
- * The video encoder data are board specific now!
- */
-
-#if defined(CONFIG_RRVISION)
-#include "../board/RRvision/video_ad7179.h"
-#else
-#error "Please provide a board-specific video_ad7179.h"
-#endif
-
-#endif /* _VIDEO_AD7179_H_ */
--
1.9.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [U-Boot] [PATCH 07/26] mpc8xx: remove R360MPI board support
2014-12-15 14:26 [U-Boot] [PATCH 0/26] Start removing non-generic boards Masahiro Yamada
` (5 preceding siblings ...)
2014-12-15 14:26 ` [U-Boot] [PATCH 06/26] mpc8xx: remove RRvision " Masahiro Yamada
@ 2014-12-15 14:26 ` Masahiro Yamada
2015-01-05 18:20 ` Tom Rini
2014-12-15 14:26 ` [U-Boot] [PATCH 08/26] mpc8xx: remove NETVIA " Masahiro Yamada
` (20 subsequent siblings)
27 siblings, 1 reply; 55+ messages in thread
From: Masahiro Yamada @ 2014-12-15 14:26 UTC (permalink / raw)
To: u-boot
This board is still a non-generic board.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
---
arch/powerpc/cpu/mpc8xx/Kconfig | 4 -
arch/powerpc/cpu/mpc8xx/cpu_init.c | 1 -
board/r360mpi/Kconfig | 9 -
board/r360mpi/MAINTAINERS | 6 -
board/r360mpi/Makefile | 8 -
board/r360mpi/flash.c | 468 -------------------------------------
board/r360mpi/pcmcia.c | 232 ------------------
board/r360mpi/r360mpi.c | 403 --------------------------------
board/r360mpi/u-boot.lds | 89 -------
configs/R360MPI_defconfig | 3 -
doc/README.scrapyard | 1 +
drivers/video/mpc8xx_lcd.c | 25 --
include/commproc.h | 4 -
include/configs/R360MPI.h | 464 ------------------------------------
include/pcmcia.h | 2 -
15 files changed, 1 insertion(+), 1718 deletions(-)
delete mode 100644 board/r360mpi/Kconfig
delete mode 100644 board/r360mpi/MAINTAINERS
delete mode 100644 board/r360mpi/Makefile
delete mode 100644 board/r360mpi/flash.c
delete mode 100644 board/r360mpi/pcmcia.c
delete mode 100644 board/r360mpi/r360mpi.c
delete mode 100644 board/r360mpi/u-boot.lds
delete mode 100644 configs/R360MPI_defconfig
delete mode 100644 include/configs/R360MPI.h
diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig
index 37ee5f6..4e67ff2 100644
--- a/arch/powerpc/cpu/mpc8xx/Kconfig
+++ b/arch/powerpc/cpu/mpc8xx/Kconfig
@@ -28,9 +28,6 @@ config TARGET_LWMON
config TARGET_NETVIA
bool "Support NETVIA"
-config TARGET_R360MPI
- bool "Support R360MPI"
-
config TARGET_TQM823L
bool "Support TQM823L"
@@ -75,7 +72,6 @@ source "board/ip860/Kconfig"
source "board/ivm/Kconfig"
source "board/lwmon/Kconfig"
source "board/netvia/Kconfig"
-source "board/r360mpi/Kconfig"
source "board/tqc/tqm8xx/Kconfig"
endmenu
diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c
index f772787..9350fdd 100644
--- a/arch/powerpc/cpu/mpc8xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c
@@ -129,7 +129,6 @@ void cpu_init_f (volatile immap_t * immr)
defined(CONFIG_IVML24) || \
defined(CONFIG_IVMS8) || \
defined(CONFIG_LWMON) || \
- defined(CONFIG_R360MPI) || \
defined(CONFIG_RMU)
memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM;
diff --git a/board/r360mpi/Kconfig b/board/r360mpi/Kconfig
deleted file mode 100644
index fe8484f..0000000
--- a/board/r360mpi/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_R360MPI
-
-config SYS_BOARD
- default "r360mpi"
-
-config SYS_CONFIG_NAME
- default "R360MPI"
-
-endif
diff --git a/board/r360mpi/MAINTAINERS b/board/r360mpi/MAINTAINERS
deleted file mode 100644
index a67ab0c..0000000
--- a/board/r360mpi/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-R360MPI BOARD
-M: Wolfgang Denk <wd@denx.de>
-S: Maintained
-F: board/r360mpi/
-F: include/configs/R360MPI.h
-F: configs/R360MPI_defconfig
diff --git a/board/r360mpi/Makefile b/board/r360mpi/Makefile
deleted file mode 100644
index f8f7fe7..0000000
--- a/board/r360mpi/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = r360mpi.o flash.o pcmcia.o
diff --git a/board/r360mpi/flash.c b/board/r360mpi/flash.c
deleted file mode 100644
index 996a22e..0000000
--- a/board/r360mpi/flash.c
+++ /dev/null
@@ -1,468 +0,0 @@
-/*
- * (C) Copyright 2001
- * Kyle Harris, Nexus Technologies, Inc. kharris at nexus-tech.net
- *
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* #define DEBUG */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-# ifndef CONFIG_ENV_ADDR
-# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-# endif
-# ifndef CONFIG_ENV_SIZE
-# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-# endif
-# ifndef CONFIG_ENV_SECT_SIZE
-# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
-# endif
-#endif
-
-/*-----------------------------------------------------------------------
- * Protection Flags:
- */
-#define FLAG_PROTECT_SET 0x01
-#define FLAG_PROTECT_CLEAR 0x02
-
-/* Board support for 1 or 2 flash devices */
-#undef FLASH_PORT_WIDTH32
-#define FLASH_PORT_WIDTH16
-
-#ifdef FLASH_PORT_WIDTH16
-#define FLASH_PORT_WIDTH ushort
-#define FLASH_PORT_WIDTHV vu_short
-#else
-#define FLASH_PORT_WIDTH ulong
-#define FLASH_PORT_WIDTHV vu_long
-#endif
-
-#define FPW FLASH_PORT_WIDTH
-#define FPWV FLASH_PORT_WIDTHV
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (FPW * addr, flash_info_t * info);
-static int write_data (flash_info_t * info, ulong dest, FPW data);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- unsigned long size_b0;
- int i;
-
- /* Init: no FLASHes known */
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
- size_b0 = flash_get_size ((FPW *) FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0 << 20);
- }
-
- /* Remap FLASH according to real size */
- memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
- memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V;
-
- /* Re-do sizing to get full correct info */
- size_b0 = flash_get_size ((FPW *) CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
- flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- (void) flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_FLASH_BASE,
- CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
- &flash_info[0]);
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
- &flash_info[0]);
-#endif
-
- flash_info[0].size = size_b0;
-
- return (size_b0);
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t * info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- return;
- }
-
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00020000);
- }
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_INTEL:
- printf ("INTEL ");
- break;
- default:
- printf ("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F320J3A:
- printf ("28F320J3A\n");
- break;
- case FLASH_28F640J3A:
- printf ("28F640J3A\n");
- break;
- case FLASH_28F128J3A:
- printf ("28F128J3A\n");
- break;
- default:
- printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " ");
- }
- printf ("\n");
- return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size (FPW * addr, flash_info_t * info)
-{
- FPW value;
-
- /* Make sure Block Lock Bits get cleared */
- addr[0] = (FPW) 0x00FF00FF;
- addr[0] = (FPW) 0x00600060;
- addr[0] = (FPW) 0x00D000D0;
- addr[0] = (FPW) 0x00FF00FF;
-
- /* Write auto select command: read Manufacturer ID */
- addr[0x5555] = (FPW) 0x00AA00AA;
- addr[0x2AAA] = (FPW) 0x00550055;
- addr[0x5555] = (FPW) 0x00900090;
-
- value = addr[0];
-
- debug("Manuf. ID @ 0x%08lx: 0x%08x\n", (ulong)addr, value);
-
- switch (value) {
- case (FPW) INTEL_MANUFACT:
- info->flash_id = FLASH_MAN_INTEL;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
- return (0); /* no or unknown flash */
- }
-
- value = addr[1]; /* device ID */
-
- debug("Device ID @ 0x%08lx: 0x%08x\n", (ulong)(&addr[1]), value);
-
- switch (value) {
- case (FPW) INTEL_ID_28F320J3A:
- info->flash_id += FLASH_28F320J3A;
- info->sector_count = 32;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case (FPW) INTEL_ID_28F640J3A:
- info->flash_id += FLASH_28F640J3A;
- info->sector_count = 64;
- info->size = 0x00800000;
- break; /* => 8 MB */
-
- case (FPW) INTEL_ID_28F128J3A:
- info->flash_id += FLASH_28F128J3A;
- info->sector_count = 128;
- info->size = 0x01000000;
- break; /* => 16 MB */
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- break;
- }
-
- if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
- printf ("** ERROR: sector count %d > max (%d) **\n",
- info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
- info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- }
-
- addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
- int flag, prot, sect;
- ulong type, start, now, last;
- int rcode = 0;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- type = (info->flash_id & FLASH_VENDMASK);
- if ((type != FLASH_MAN_INTEL)) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- start = get_timer (0);
- last = start;
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- FPWV *addr = (FPWV *) (info->start[sect]);
- FPW status;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- *addr = (FPW) 0x00500050; /* clear status register */
- *addr = (FPW) 0x00200020; /* erase setup */
- *addr = (FPW) 0x00D000D0; /* erase confirm */
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- *addr = (FPW) 0x00B000B0; /* suspend erase */
- *addr = (FPW) 0x00FF00FF; /* reset to read mode */
- rcode = 1;
- break;
- }
-
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
- *addr = (FPW) 0x00FF00FF; /* reset to read mode */
- }
- }
- printf (" done\n");
- return rcode;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 4 - Flash not identified
- */
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- ulong cp, wp;
- FPW data;
-
- int i, l, rc, port_width;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- return 4;
- }
-/* get lower word aligned address */
-#ifdef FLASH_PORT_WIDTH16
- wp = (addr & ~1);
- port_width = 2;
-#else
- wp = (addr & ~3);
- port_width = 4;
-#endif
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i = 0, cp = wp; i < l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
- for (; i < port_width && cnt > 0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt == 0 && i < port_width; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- if ((rc = write_data (info, wp, data)) != 0) {
- return (rc);
- }
- wp += port_width;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= port_width) {
- data = 0;
- for (i = 0; i < port_width; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_data (info, wp, data)) != 0) {
- return (rc);
- }
- wp += port_width;
- cnt -= port_width;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i < port_width; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- return (write_data (info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word or halfword to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_data (flash_info_t * info, ulong dest, FPW data)
-{
- FPWV *addr = (FPWV *) dest;
- ulong status;
- ulong start;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*addr & data) != data) {
- printf ("not erased@%08lx (%x)\n", (ulong) addr, *addr);
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- *addr = (FPW) 0x00400040; /* write setup */
- *addr = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- start = get_timer (0);
-
- while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- *addr = (FPW) 0x00FF00FF; /* restore read mode */
- return (1);
- }
- }
-
- *addr = (FPW) 0x00FF00FF; /* restore read mode */
-
- return (0);
-}
diff --git a/board/r360mpi/pcmcia.c b/board/r360mpi/pcmcia.c
deleted file mode 100644
index a939b31..0000000
--- a/board/r360mpi/pcmcia.c
+++ /dev/null
@@ -1,232 +0,0 @@
-#include <common.h>
-#include <mpc8xx.h>
-#include <pcmcia.h>
-
-#undef CONFIG_PCMCIA
-
-#if defined(CONFIG_CMD_PCMCIA)
-#define CONFIG_PCMCIA
-#endif
-
-#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
-#define CONFIG_PCMCIA
-#endif
-
-#ifdef CONFIG_PCMCIA
-
-#define PCMCIA_BOARD_MSG "R360MPI"
-
-int pcmcia_hardware_enable(int slot)
-{
- volatile immap_t *immap;
- volatile pcmconf8xx_t *pcmp;
- volatile sysconf8xx_t *sysp;
- uint reg, mask;
-
- debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
-
- udelay(10000);
-
- immap = (immap_t *)CONFIG_SYS_IMMR;
- sysp = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf));
- pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
-
- /*
- * Configure SIUMCR to enable PCMCIA port B
- * (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
- */
- sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */
-
- /* clear interrupt state, and disable interrupts */
- pcmp->pcmc_pscr = PCMCIA_MASK(_slot_);
- pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
-
- /*
- * Disable interrupts, DMA, and PCMCIA buffers
- * (isolate the interface) and assert RESET signal
- */
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = 0;
- reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
- udelay(500);
-
- /*
- * Configure Ports A, B & C pins for
- * 5 Volts Enable and 3 Volts enable
- */
- immap->im_ioport.iop_pcpar &= ~(0x0400);
- immap->im_ioport.iop_pcso &= ~(0x0400);/*
- immap->im_ioport.iop_pcdir |= 0x0400;*/
-
- immap->im_ioport.iop_papar &= ~(0x0200);/*
- immap->im_ioport.iop_padir |= 0x0200;*/
-#if 0
- immap->im_ioport.iop_pbpar &= ~(0xC000);
- immap->im_ioport.iop_pbdir &= ~(0xC000);
-#endif
- /* remove all power */
-
- immap->im_ioport.iop_pcdat |= 0x0400;
- immap->im_ioport.iop_padat |= 0x0200;
-
- /*
- * Make sure there is a card in the slot, then configure the interface.
- */
- udelay(10000);
- debug ("[%d] %s: PIPR(%p)=0x%x\n",
- __LINE__,__FUNCTION__,
- &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
- if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
- printf (" No Card found\n");
- return (1);
- }
-
- /*
- * Power On.
- */
- mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
- reg = pcmp->pcmc_pipr;
- debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
- reg,
- (reg&PCMCIA_VS1(slot))?"n":"ff",
- (reg&PCMCIA_VS2(slot))?"n":"ff");
- if ((reg & mask) == mask) {
- immap->im_ioport.iop_pcdat &= ~(0x4000);
- puts (" 5.0V card found: ");
- } else {
- immap->im_ioport.iop_padat &= ~(0x0002);
- puts (" 3.3V card found: ");
- }
- immap->im_ioport.iop_pcdir |= 0x0400;
- immap->im_ioport.iop_padir |= 0x0200;
-#if 0
- /* VCC switch error flag, PCMCIA slot INPACK_ pin */
- cp->cp_pbdir &= ~(0x0020 | 0x0010);
- cp->cp_pbpar &= ~(0x0020 | 0x0010);
- udelay(500000);
-#endif
- debug ("Enable PCMCIA buffers and stop RESET\n");
- reg = PCMCIA_PGCRX(_slot_);
- reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
-
- udelay(250000); /* some cards need >150 ms to come up :-( */
-
- debug ("# hardware_enable done\n");
-
- return (0);
-}
-
-
-#if defined(CONFIG_CMD_PCMCIA)
-int pcmcia_hardware_disable(int slot)
-{
- volatile immap_t *immap;
- u_long reg;
-
- debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
-
- immap = (immap_t *)CONFIG_SYS_IMMR;
-
- /* remove all power */
- immap->im_ioport.iop_pcdat |= 0x0400;
- immap->im_ioport.iop_padat |= 0x0200;
-
- /* Configure PCMCIA General Control Register */
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = 0;
- reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
-
- udelay(10000);
-
- return (0);
-}
-#endif
-
-
-int pcmcia_voltage_set(int slot, int vcc, int vpp)
-{
- volatile immap_t *immap;
- volatile pcmconf8xx_t *pcmp;
- u_long reg;
-
- debug ("voltage_set: "
- PCMCIA_BOARD_MSG
- " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
- 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
-
- immap = (immap_t *)CONFIG_SYS_IMMR;
- pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
- /*
- * Disable PCMCIA buffers (isolate the interface)
- * and assert RESET signal
- */
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = PCMCIA_PGCRX(_slot_);
- reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
- udelay(500);
-
- /*
- * Configure Ports A & C pins for
- * 5 Volts Enable and 3 Volts enable,
- * Turn off all power
- */
- debug ("PCMCIA power OFF\n");
- immap->im_ioport.iop_pcpar &= ~(0x0400);
- immap->im_ioport.iop_pcso &= ~(0x0400);/*
- immap->im_ioport.iop_pcdir |= 0x0400;*/
-
- immap->im_ioport.iop_papar &= ~(0x0200);/*
- immap->im_ioport.iop_padir |= 0x0200;*/
-
- immap->im_ioport.iop_pcdat |= 0x0400;
- immap->im_ioport.iop_padat |= 0x0200;
-
- reg = 0;
- switch(vcc) {
- case 0: break;
- case 33: reg |= 0x0200; break;
- case 50: reg |= 0x0400; break;
- default: goto done;
- }
-
- /* Checking supported voltages */
-
- debug ("PIPR: 0x%x --> %s\n",
- pcmp->pcmc_pipr,
- (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V");
-
- if (reg & 0x0200)
- immap->im_ioport.iop_pcdat &= !reg;
- if (reg & 0x0400)
- immap->im_ioport.iop_padat &= !reg;
- immap->im_ioport.iop_pcdir |= 0x0200;
- immap->im_ioport.iop_padir |= 0x0400;
- if (reg) {
- debug ("PCMCIA powered at %sV\n",
- (reg&0x0400) ? "5.0" : "3.3");
- } else {
- debug ("PCMCIA powered down\n");
- }
-
-done:
- debug ("Enable PCMCIA buffers and stop RESET\n");
- reg = PCMCIA_PGCRX(_slot_);
- reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
- udelay(500);
-
- debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
- slot+'A');
- return (0);
-}
-
-#endif /* CCONFIG_PCMCIA */
diff --git a/board/r360mpi/r360mpi.c b/board/r360mpi/r360mpi.c
deleted file mode 100644
index d06aea7..0000000
--- a/board/r360mpi/r360mpi.c
+++ /dev/null
@@ -1,403 +0,0 @@
-/*
- * (C) Copyright 2001-2003
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-#include <mpc8xx.h>
-#include <i2c.h>
-
-#include <commproc.h>
-#include <command.h>
-#include <malloc.h>
-
-#include <linux/types.h>
-#include <linux/string.h> /* for strdup */
-
-
-/*
- * Memory Controller Using
- *
- * CS0 - Flash memory (0x40000000)
- * CS1 - FLASH memory (0x????????)
- * CS2 - SDRAM (0x00000000)
- * CS3 -
- * CS4 -
- * CS5 -
- * CS6 - PCMCIA device
- * CS7 - PCMCIA device
- */
-
-/* ------------------------------------------------------------------------- */
-
-#define _not_used_ 0xffffffff
-
-const uint sdram_table[]=
-{
- /* single read. (offset 0 in upm RAM) */
- 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
- 0x1ff77c47,
-
- /* MRS initialization (offset 5) */
-
- 0x1ff77c34, 0xefeabc34, 0x1fb57c35,
-
- /* burst read. (offset 8 in upm RAM) */
- 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
- 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
- _not_used_, _not_used_, _not_used_, _not_used_,
- _not_used_, _not_used_, _not_used_, _not_used_,
-
- /* single write. (offset 18 in upm RAM) */
- 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
- _not_used_, _not_used_, _not_used_, _not_used_,
-
- /* burst write. (offset 20 in upm RAM) */
- 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
- 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_,
- _not_used_, _not_used_, _not_used_, _not_used_,
- _not_used_, _not_used_, _not_used_, _not_used_,
-
- /* refresh. (offset 30 in upm RAM) */
- 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
- 0xfffffc84, 0xfffffc07, _not_used_, _not_used_,
- _not_used_, _not_used_, _not_used_, _not_used_,
-
- /* exception. (offset 3c in upm RAM) */
- 0x7ffffc07, _not_used_, _not_used_, _not_used_ };
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check Board Identity:
- */
-
-int checkboard (void)
-{
- puts ("Board: R360 MPI Board\n");
- return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-static long int dram_size (long int, long int *, long int);
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- long int size8, size9;
- long int size_b0 = 0;
- unsigned long reg;
-
- upmconfig (UPMA, (uint *) sdram_table,
- sizeof (sdram_table) / sizeof (uint));
-
- /*
- * Preliminary prescaler for refresh (depends on number of
- * banks): This value is selected for four cycles every 62.4 us
- * with two SDRAM banks or four cycles every 31.2 us with one
- * bank. It will be adjusted after memory sizing.
- */
- memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
-
- memctl->memc_mar = 0x00000088;
-
- /*
- * Map controller bank 2 to the SDRAM bank at
- * preliminary address - these have to be modified after the
- * SDRAM size has been determined.
- */
- memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
- memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
-
- memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
-
- udelay (200);
-
- /* perform SDRAM initializsation sequence */
-
- memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
- udelay (200);
- memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */
- udelay (200);
-
- memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
-
- udelay (1000);
-
- /*
- * Check Bank 2 Memory Size for re-configuration
- *
- * try 8 column mode
- */
- size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE2_PRELIM,
- SDRAM_MAX_SIZE);
-
- udelay (1000);
-
- /*
- * try 9 column mode
- */
- size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE2_PRELIM,
- SDRAM_MAX_SIZE);
-
- if (size8 < size9) { /* leave configuration@9 columns */
- size_b0 = size9;
-/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
- } else { /* back to 8 columns */
- size_b0 = size8;
- memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
- udelay (500);
-/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
- }
-
- udelay (1000);
-
- /*
- * Adjust refresh rate depending on SDRAM type, both banks
- * For types > 128 MBit leave it at the current (fast) rate
- */
- if ((size_b0 < 0x02000000)) {
- /* reduce to 15.6 us (62.4 us / quad) */
- memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
- udelay (1000);
- }
-
- /*
- * Final mapping
- */
-
- memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
- memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
-
- /* adjust refresh rate depending on SDRAM type, one bank */
- reg = memctl->memc_mptpr;
- reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
- memctl->memc_mptpr = reg;
-
- udelay (10000);
-
-#ifdef CONFIG_CAN_DRIVER
- /* Initialize OR3 / BR3 */
- memctl->memc_or3 = CONFIG_SYS_OR3_CAN; /* switch GPLB_5 to GPLA_5 */
- memctl->memc_br3 = CONFIG_SYS_BR3_CAN;
-
- /* Initialize MBMR */
- memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 works as UPWAITB */
-
- /* Initialize UPMB for CAN: single read */
- memctl->memc_mdr = 0xFFFFC004;
- memctl->memc_mcr = 0x0100 | UPMB;
-
- memctl->memc_mdr = 0x0FFFD004;
- memctl->memc_mcr = 0x0101 | UPMB;
-
- memctl->memc_mdr = 0x0FFFC000;
- memctl->memc_mcr = 0x0102 | UPMB;
-
- memctl->memc_mdr = 0x3FFFC004;
- memctl->memc_mcr = 0x0103 | UPMB;
-
- memctl->memc_mdr = 0xFFFFDC05;
- memctl->memc_mcr = 0x0104 | UPMB;
-
- /* Initialize UPMB for CAN: single write */
- memctl->memc_mdr = 0xFFFCC004;
- memctl->memc_mcr = 0x0118 | UPMB;
-
- memctl->memc_mdr = 0xCFFCD004;
- memctl->memc_mcr = 0x0119 | UPMB;
-
- memctl->memc_mdr = 0x0FFCC000;
- memctl->memc_mcr = 0x011A | UPMB;
-
- memctl->memc_mdr = 0x7FFCC004;
- memctl->memc_mcr = 0x011B | UPMB;
-
- memctl->memc_mdr = 0xFFFDCC05;
- memctl->memc_mcr = 0x011C | UPMB;
-#endif
-
- return (size_b0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-
-static long int dram_size (long int mamr_value,
- long int *base, long int maxsize)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
- memctl->memc_mamr = mamr_value;
-
- return (get_ram_size(base, maxsize));
-}
-
-/* ------------------------------------------------------------------------- */
-
-void r360_i2c_lcd_write (uchar data0, uchar data1)
-{
- if (i2c_write (CONFIG_SYS_I2C_LCD_ADDR, data0, 1, &data1, 1)) {
- printf("Can't write lcd data 0x%02X 0x%02X.\n", data0, data1);
- }
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*-----------------------------------------------------------------------
- * Keyboard Controller
- */
-
-/* Number of bytes returned from Keyboard Controller */
-#define KEYBD_KEY_MAX 16 /* maximum key number */
-#define KEYBD_DATALEN ((KEYBD_KEY_MAX + 7) / 8) /* normal key scan data */
-
-static uchar *key_match (uchar *);
-
-int misc_init_r (void)
-{
- char kbd_data[KEYBD_DATALEN];
- char keybd_env[2 * KEYBD_DATALEN + 1];
- char *str;
- int i;
-
- i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-
- i2c_read (CONFIG_SYS_I2C_KEY_ADDR, 0, 0, (uchar *)kbd_data, KEYBD_DATALEN);
-
- for (i = 0; i < KEYBD_DATALEN; ++i) {
- sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
- }
- setenv ("keybd", keybd_env);
-
- str = strdup ((char *)key_match ((uchar *)keybd_env)); /* decode keys */
-
-#ifdef CONFIG_PREBOOT /* automatically configure "preboot" command on key match */
- setenv ("preboot", str); /* set or delete definition */
-#endif /* CONFIG_PREBOOT */
- if (str != NULL) {
- free (str);
- }
-
- return (0);
-}
-
-/*-----------------------------------------------------------------------
- * Check if pressed key(s) match magic sequence,
- * and return the command string associated with that key(s).
- *
- * If no key press was decoded, NULL is returned.
- *
- * Note: the first character of the argument will be overwritten with
- * the "magic charcter code" of the decoded key(s), or '\0'.
- *
- *
- * Note: the string points to static environment data and must be
- * saved before you call any function that modifies the environment.
- */
-#ifdef CONFIG_PREBOOT
-
-static uchar kbd_magic_prefix[] = "key_magic";
-static uchar kbd_command_prefix[] = "key_cmd";
-
-static uchar *key_match (uchar * kbd_str)
-{
- uchar magic[sizeof (kbd_magic_prefix) + 1];
- uchar cmd_name[sizeof (kbd_command_prefix) + 1];
- uchar *str, *suffix;
- uchar *kbd_magic_keys;
- char *cmd;
-
- /*
- * The following string defines the characters that can pe appended
- * to "key_magic" to form the names of environment variables that
- * hold "magic" key codes, i. e. such key codes that can cause
- * pre-boot actions. If the string is empty (""), then only
- * "key_magic" is checked (old behaviour); the string "125" causes
- * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
- */
- if ((kbd_magic_keys = (uchar *)getenv ("magic_keys")) != NULL) {
- /* loop over all magic keys;
- * use '\0' suffix in case of empty string
- */
- for (suffix = kbd_magic_keys;
- *suffix || suffix == kbd_magic_keys;
- ++suffix) {
- sprintf ((char *)magic, "%s%c", kbd_magic_prefix, *suffix);
-
-#if 0
- printf ("### Check magic \"%s\"\n", magic);
-#endif
-
- if ((str = (uchar *)getenv ((char *)magic)) != 0) {
-
-#if 0
- printf ("### Compare \"%s\" \"%s\"\n",
- kbd_str, str);
-#endif
- if (strcmp ((char *)kbd_str, (char *)str) == 0) {
- sprintf ((char *)cmd_name, "%s%c",
- kbd_command_prefix,
- *suffix);
-
- if ((cmd = getenv ((char *)cmd_name)) != 0) {
-#if 0
- printf ("### Set PREBOOT to $(%s): \"%s\"\n",
- cmd_name, cmd);
-#endif
- return ((uchar *)cmd);
- }
- }
- }
- }
- }
-#if 0
- printf ("### Delete PREBOOT\n");
-#endif
- *kbd_str = '\0';
- return (NULL);
-}
-#endif /* CONFIG_PREBOOT */
-
-/* Read Keyboard status */
-int do_kbd (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- uchar kbd_data[KEYBD_DATALEN];
- uchar keybd_env[2 * KEYBD_DATALEN + 1];
- int i;
-
- i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-
- /* Read keys */
- i2c_read (CONFIG_SYS_I2C_KEY_ADDR, 0, 0, kbd_data, KEYBD_DATALEN);
-
- puts ("Keys:");
- for (i = 0; i < KEYBD_DATALEN; ++i) {
- sprintf ((char *)(keybd_env + i + i), "%02X", kbd_data[i]);
- printf (" %02x", kbd_data[i]);
- }
- putc ('\n');
- setenv ("keybd", (char *)keybd_env);
- return 0;
-}
-
-U_BOOT_CMD(
- kbd, 1, 1, do_kbd,
- "read keyboard status",
- ""
-);
diff --git a/board/r360mpi/u-boot.lds b/board/r360mpi/u-boot.lds
deleted file mode 100644
index 5f69bc4..0000000
--- a/board/r360mpi/u-boot.lds
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
- arch/powerpc/cpu/mpc8xx/start.o (.text*)
- arch/powerpc/cpu/mpc8xx/traps.o (.text*)
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end = . ;
- PROVIDE (end = .);
- . = ALIGN(128 * 1024);
- .ppcenv :
- {
- common/env_embedded.o (.ppcenv)
- }
-}
diff --git a/configs/R360MPI_defconfig b/configs/R360MPI_defconfig
deleted file mode 100644
index 290f694..0000000
--- a/configs/R360MPI_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_8xx=y
-CONFIG_TARGET_R360MPI=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 00a5447..1e475af 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+R360MPI powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
RRvision powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
SPD823TS powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
KUP4K powerpc mpc8xx - - Klaus Heydeck <heydeck@kieback-peter.de>
diff --git a/drivers/video/mpc8xx_lcd.c b/drivers/video/mpc8xx_lcd.c
index a5c1e19..336788f 100644
--- a/drivers/video/mpc8xx_lcd.c
+++ b/drivers/video/mpc8xx_lcd.c
@@ -423,31 +423,6 @@ void lcd_enable (void)
pic_write (0x60, c);
}
#endif /* CONFIG_LWMON */
-
-#if defined(CONFIG_R360MPI)
- {
- extern void r360_i2c_lcd_write (uchar data0, uchar data1);
- unsigned long bgi, ctr;
- char *p;
-
- if ((p = getenv("lcdbgi")) != NULL) {
- bgi = simple_strtoul (p, 0, 10) & 0xFFF;
- } else {
- bgi = 0xFFF;
- }
-
- if ((p = getenv("lcdctr")) != NULL) {
- ctr = simple_strtoul (p, 0, 10) & 0xFFF;
- } else {
- ctr=0x7FF;
- }
-
- r360_i2c_lcd_write(0x10, 0x01);
- r360_i2c_lcd_write(0x20, 0x01);
- r360_i2c_lcd_write(0x30 | ((bgi>>8) & 0xF), bgi & 0xFF);
- r360_i2c_lcd_write(0x40 | ((ctr>>8) & 0xF), ctr & 0xFF);
- }
-#endif /* CONFIG_R360MPI */
}
/************************************************************************/
diff --git a/include/commproc.h b/include/commproc.h
index 7d62861..38e4e7d 100644
--- a/include/commproc.h
+++ b/include/commproc.h
@@ -630,7 +630,6 @@ typedef struct scc_enet {
/*** MVS1, TQM823L/M, TQM850L/M, TQM885D, R360MPI **********/
#if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \
- defined(CONFIG_R360MPI) || \
defined(CONFIG_TQM823L) || \
defined(CONFIG_TQM823M) || defined(CONFIG_TQM850L) || \
defined(CONFIG_TQM850M) || defined(CONFIG_TQM885D)
@@ -650,9 +649,6 @@ typedef struct scc_enet {
#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
-#if defined(CONFIG_R360MPI)
-#define PC_ENET_LBK ((ushort)0x0008) /* PC 12 */
-#endif /* CONFIG_R360MPI */
/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
* SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
diff --git a/include/configs/R360MPI.h b/include/configs/R360MPI.h
deleted file mode 100644
index 009d1cf..0000000
--- a/include/configs/R360MPI.h
+++ /dev/null
@@ -1,464 +0,0 @@
-/*
- * (C) Copyright 2000-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
-#define CONFIG_R360MPI 1
-
-#define CONFIG_SYS_TEXT_BASE 0x40000000
-
-#define CONFIG_LCD
-#define CONFIG_MPC8XX_LCD
-#undef CONFIG_EDT32F10
-#define CONFIG_SHARP_LQ057Q3DC02
-
-#define CONFIG_SPLASH_SCREEN
-
-#define MPC8XX_FACT 1 /* Multiply by 1 */
-#define MPC8XX_XIN 50000000 /* 50 MHz in */
-#define CONFIG_8xx_GCLK_FREQ 50000000 /* define if can't use get_gclk_freq */
-
-#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE 115200 /* console baudrate in bps */
-#if 0
-#define CONFIG_BOOTDELAY 0 /* immediate boot */
-#else
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-
-#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
-
-#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
-
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND \
- "bootp; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
- "bootm"
-
-#undef CONFIG_SCC1_ENET
-#define CONFIG_SCC2_ENET
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-#define CONFIG_MISC_INIT_R /* have misc_init_r() function */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_CAN_DRIVER /* CAN Driver support enabled */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-
-#define CONFIG_HARD_I2C 1 /* To I2C with hardware support */
-#undef CONFIG_SYS_I2C_SOFT /* To I2C with software support */
-#define CONFIG_SYS_I2C_SPEED 4700 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-#if defined(CONFIG_SYS_I2C_SOFT)
-#define CONFIG_SYS_SYS_I2C_SOFT_SPEED 4700 /* I2C speed and slave address */
-#define CONFIG_SYS_SYS_I2C_SOFT_SLAVE 0x7F
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define PB_SCL 0x00000020 /* PB 26 */
-#define PB_SDA 0x00000010 /* PB 27 */
-
-#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
-#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
-#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
-#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
-#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
- else immr->im_cpm.cp_pbdat &= ~PB_SDA
-#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
- else immr->im_cpm.cp_pbdat &= ~PB_SCL
-#define I2C_DELAY udelay(50)
-#endif /* #define(CONFIG_SYS_I2C_SOFT) */
-
-#define CONFIG_SYS_I2C_LCD_ADDR 0x8 /* LCD Control */
-#define CONFIG_SYS_I2C_KEY_ADDR 0x9 /* Keyboard coprocessor */
-#define CONFIG_SYS_I2C_TEM_ADDR 0x49 /* Temperature Sensors */
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BMP
-#define CONFIG_CMD_BSP
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PCMCIA
-#define CONFIG_CMD_SNTP
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_DEVICE_NULLDEV 1 /* we need the null device */
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 /* must set console from env */
-
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-/*
- * JFFS2 partitions
- */
-/* No command line, one static partition
- * use all the space starting at offset 3MB*/
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV "nor0"
-#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET 0x00300000
-
-/* mtdparts command line support */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT "nor0=r360-0"
-#define MTDPARTS_DEFAULT "mtdparts=r360-0:- at 3m(user)"
-*/
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xFF000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0x40000000
-#if defined(DEBUG)
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#else
-#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
-#endif
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment */
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment sector */
-#define CONFIG_ENV_SIZE 0x4000 /* Used Size of Environment sector */
-#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register 11-27
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit
- *
- * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
- */
-#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
-#define CONFIG_SYS_PLPRCR \
- ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
-#else /* up to 50 MHz we use a 1:1 clock */
-#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-#endif /* CONFIG_80MHz */
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK SCCR_EBDF11
-#define CONFIG_SYS_SCCR (SCCR_TBS | \
- SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
- SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
- SCCR_DFALCD00)
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
- *-----------------------------------------------------------------------
- */
-
-#if 1
-#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
-#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
-
-#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
-#undef CONFIG_IDE_LED /* LED for ide not supported */
-#undef CONFIG_IDE_RESET /* reset for ide not supported */
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
-#endif
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_DER 0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM 0xFF000000 /* OR addr mask */
-
-/*
- * FLASH timing:
- */
-#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_SCY_7_CLK | OR_BI)
-
-#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
-
-
-/*
- * BR2 and OR2 (SDRAM)
- *
- */
-#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
-#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
-
-#define CONFIG_SYS_PRELIM_OR2_AM 0xF8000000 /* OR addr mask */
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
-#define CONFIG_SYS_OR_TIMING_SDRAM (OR_ACS_DIV1 | OR_CSNT_SAM | \
- OR_SCY_0_CLK | OR_G5LS)
-
-#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR2_AM | CONFIG_SYS_OR_TIMING_SDRAM )
-#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-/*
- * BR3 and OR3 (CAN Controller)
- */
-#ifdef CONFIG_CAN_DRIVER
-#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN base address */
-#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
-#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA |OR_BI)
-#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
- BR_PS_8 | BR_MS_UPMB | BR_V)
-#endif /* CONFIG_CAN_DRIVER */
-
-
-/*
- * Memory Periodic Timer Prescaler
- *
- * The Divider for PTA (refresh timer) configuration is based on an
- * example SDRAM configuration (64 MBit, one bank). The adjustment to
- * the number of chip selects (NCS) and the actually needed refresh
- * rate is done by setting MPTPR.
- *
- * PTA is calculated from
- * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
- *
- * gclk CPU clock (not bus clock!)
- * Trefresh Refresh cycle * 4 (four word bursts used)
- *
- * 4096 Rows from SDRAM example configuration
- * 1000 factor s -> ms
- * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
- * 4 Number of refresh cycles per period
- * 64 Refresh cycle in ms per number of rows
- * --------------------------------------------
- * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
- *
- * 50 MHz => 50.000.000 / Divider = 98
- * 66 Mhz => 66.000.000 / Divider = 129
- * 80 Mhz => 80.000.000 / Divider = 156
- */
-#if defined(CONFIG_80MHz)
-#define CONFIG_SYS_MAMR_PTA 156
-#elif defined(CONFIG_66MHz)
-#define CONFIG_SYS_MAMR_PTA 129
-#else /* 50 MHz */
-#define CONFIG_SYS_MAMR_PTA 98
-#endif /*CONFIG_??MHz */
-
-/*
- * For 16 MBit, refresh rates could be 31.3 us
- * (= 64 ms / 2K = 125 / quad bursts).
- * For a simpler initialization, 15.6 us is used instead.
- *
- * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
- * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
- */
-#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
-#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-/* 9 column SDRAM */
-#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-#endif /* __CONFIG_H */
diff --git a/include/pcmcia.h b/include/pcmcia.h
index 371c9a4..7e495bc 100644
--- a/include/pcmcia.h
+++ b/include/pcmcia.h
@@ -27,8 +27,6 @@
# define CONFIG_PCMCIA_SLOT_A
#elif defined(CONFIG_LWMON) /* The LWMON use SLOT_B */
# define CONFIG_PCMCIA_SLOT_B
-#elif defined(CONFIG_R360MPI) /* The R360MPI use SLOT_B */
-# define CONFIG_PCMCIA_SLOT_B
#elif defined(CONFIG_ATC) /* The ATC use SLOT_A */
# define CONFIG_PCMCIA_SLOT_A
#else
--
1.9.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [U-Boot] [PATCH 08/26] mpc8xx: remove NETVIA board support
2014-12-15 14:26 [U-Boot] [PATCH 0/26] Start removing non-generic boards Masahiro Yamada
` (6 preceding siblings ...)
2014-12-15 14:26 ` [U-Boot] [PATCH 07/26] mpc8xx: remove R360MPI " Masahiro Yamada
@ 2014-12-15 14:26 ` Masahiro Yamada
2015-01-05 18:20 ` Tom Rini
2014-12-15 14:26 ` [U-Boot] [PATCH 09/26] mpc8xx: remove lwmon " Masahiro Yamada
` (19 subsequent siblings)
27 siblings, 1 reply; 55+ messages in thread
From: Masahiro Yamada @ 2014-12-15 14:26 UTC (permalink / raw)
To: u-boot
This board is still a non-generic board.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Pantelis Antoniou <panto@intracom.gr>
---
arch/powerpc/cpu/mpc8xx/Kconfig | 4 -
arch/powerpc/cpu/mpc8xx/scc.c | 20 --
board/netvia/Kconfig | 9 -
board/netvia/MAINTAINERS | 7 -
board/netvia/Makefile | 8 -
board/netvia/flash.c | 495 ----------------------------------------
board/netvia/netvia.c | 401 --------------------------------
board/netvia/u-boot.lds.debug | 121 ----------
configs/NETVIA_V2_defconfig | 4 -
configs/NETVIA_defconfig | 4 -
doc/README.scrapyard | 1 +
include/commproc.h | 33 ---
include/configs/NETVIA.h | 435 -----------------------------------
include/status_led.h | 23 --
14 files changed, 1 insertion(+), 1564 deletions(-)
delete mode 100644 board/netvia/Kconfig
delete mode 100644 board/netvia/MAINTAINERS
delete mode 100644 board/netvia/Makefile
delete mode 100644 board/netvia/flash.c
delete mode 100644 board/netvia/netvia.c
delete mode 100644 board/netvia/u-boot.lds.debug
delete mode 100644 configs/NETVIA_V2_defconfig
delete mode 100644 configs/NETVIA_defconfig
delete mode 100644 include/configs/NETVIA.h
diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig
index 4e67ff2..b510e1f 100644
--- a/arch/powerpc/cpu/mpc8xx/Kconfig
+++ b/arch/powerpc/cpu/mpc8xx/Kconfig
@@ -25,9 +25,6 @@ config TARGET_IVMS8
config TARGET_LWMON
bool "Support lwmon"
-config TARGET_NETVIA
- bool "Support NETVIA"
-
config TARGET_TQM823L
bool "Support TQM823L"
@@ -71,7 +68,6 @@ source "board/esteem192e/Kconfig"
source "board/ip860/Kconfig"
source "board/ivm/Kconfig"
source "board/lwmon/Kconfig"
-source "board/netvia/Kconfig"
source "board/tqc/tqm8xx/Kconfig"
endmenu
diff --git a/arch/powerpc/cpu/mpc8xx/scc.c b/arch/powerpc/cpu/mpc8xx/scc.c
index 01029ff..610fd78 100644
--- a/arch/powerpc/cpu/mpc8xx/scc.c
+++ b/arch/powerpc/cpu/mpc8xx/scc.c
@@ -448,26 +448,6 @@ static int scc_init (struct eth_device *dev, bd_t * bis)
#error Configuration Error: exactly ONE of PB_ENET_TENA, PC_ENET_TENA must be defined
#endif
-#if defined(CONFIG_NETVIA)
-#if defined(PA_ENET_PDN)
- immr->im_ioport.iop_papar &= ~PA_ENET_PDN;
- immr->im_ioport.iop_padir |= PA_ENET_PDN;
- immr->im_ioport.iop_padat |= PA_ENET_PDN;
-#elif defined(PB_ENET_PDN)
- immr->im_cpm.cp_pbpar &= ~PB_ENET_PDN;
- immr->im_cpm.cp_pbdir |= PB_ENET_PDN;
- immr->im_cpm.cp_pbdat |= PB_ENET_PDN;
-#elif defined(PC_ENET_PDN)
- immr->im_ioport.iop_pcpar &= ~PC_ENET_PDN;
- immr->im_ioport.iop_pcdir |= PC_ENET_PDN;
- immr->im_ioport.iop_pcdat |= PC_ENET_PDN;
-#elif defined(PD_ENET_PDN)
- immr->im_ioport.iop_pdpar &= ~PD_ENET_PDN;
- immr->im_ioport.iop_pddir |= PD_ENET_PDN;
- immr->im_ioport.iop_pddat |= PD_ENET_PDN;
-#endif
-#endif
-
/*
* Set the ENT/ENR bits in the GSMR Low -- Enable Transmit/Receive
*/
diff --git a/board/netvia/Kconfig b/board/netvia/Kconfig
deleted file mode 100644
index 3e740e5..0000000
--- a/board/netvia/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_NETVIA
-
-config SYS_BOARD
- default "netvia"
-
-config SYS_CONFIG_NAME
- default "NETVIA"
-
-endif
diff --git a/board/netvia/MAINTAINERS b/board/netvia/MAINTAINERS
deleted file mode 100644
index 0313058..0000000
--- a/board/netvia/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-NETVIA BOARD
-M: Pantelis Antoniou <panto@intracom.gr>
-S: Maintained
-F: board/netvia/
-F: include/configs/NETVIA.h
-F: configs/NETVIA_defconfig
-F: configs/NETVIA_V2_defconfig
diff --git a/board/netvia/Makefile b/board/netvia/Makefile
deleted file mode 100644
index b667bc9..0000000
--- a/board/netvia/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = netvia.o flash.o
diff --git a/board/netvia/flash.c b/board/netvia/flash.c
deleted file mode 100644
index 14888f8..0000000
--- a/board/netvia/flash.c
+++ /dev/null
@@ -1,495 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size(vu_long * addr, flash_info_t * info);
-static int write_byte(flash_info_t * info, ulong dest, uchar data);
-static void flash_get_offsets(ulong base, flash_info_t * info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init(void)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- unsigned long size;
- int i;
-
- /* Init: no FLASHes known */
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i)
- flash_info[i].flash_id = FLASH_UNKNOWN;
-
- size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", size, size << 20);
- }
-
- /* Remap FLASH according to real size */
- memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000);
- memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK));
-
- /* Re-do sizing to get full correct info */
- size = flash_get_size((vu_long *) CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
- flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
- &flash_info[0]);
-
- flash_protect ( FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
- &flash_info[0]);
-
-#ifdef CONFIG_ENV_ADDR_REDUND
- flash_protect ( FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR_REDUND,
- CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
- &flash_info[0]);
-#endif
-
-
- flash_info[0].size = size;
-
- return (size);
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets(ulong base, flash_info_t * info)
-{
- int i;
-
- /* set up sector start address table */
- if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000);
- }
- } else if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000) - 0x00030000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- }
-
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info(flash_info_t * info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD:
- printf("AMD ");
- break;
- case FLASH_MAN_FUJ:
- printf("FUJITSU ");
- break;
- case FLASH_MAN_MX:
- printf("MXIC ");
- break;
- default:
- printf("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM040:
- printf("AM29LV040B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400B:
- printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400T:
- printf("AM29LV400T (4 Mbit, top boot sector)\n");
- break;
- case FLASH_AM800B:
- printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM800T:
- printf("AM29LV800T (8 Mbit, top boot sector)\n");
- break;
- case FLASH_AM160B:
- printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM160T:
- printf("AM29LV160T (16 Mbit, top boot sector)\n");
- break;
- case FLASH_AM320B:
- printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM320T:
- printf("AM29LV320T (32 Mbit, top boot sector)\n");
- break;
- default:
- printf("Unknown Chip Type\n");
- break;
- }
-
- printf(" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count);
-
- printf(" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf("\n ");
- printf(" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : " ");
- }
- printf("\n");
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size(vu_long * addr, flash_info_t * info)
-{
- short i;
- uchar mid;
- uchar pid;
- vu_char *caddr = (vu_char *) addr;
- ulong base = (ulong) addr;
-
-
- /* Write auto select command: read Manufacturer ID */
- caddr[0x0555] = 0xAA;
- caddr[0x02AA] = 0x55;
- caddr[0x0555] = 0x90;
-
- mid = caddr[0];
- switch (mid) {
- case (AMD_MANUFACT & 0xFF):
- info->flash_id = FLASH_MAN_AMD;
- break;
- case (FUJ_MANUFACT & 0xFF):
- info->flash_id = FLASH_MAN_FUJ;
- break;
- case (MX_MANUFACT & 0xFF):
- info->flash_id = FLASH_MAN_MX;
- break;
- case (STM_MANUFACT & 0xFF):
- info->flash_id = FLASH_MAN_STM;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
- pid = caddr[1]; /* device ID */
- switch (pid) {
- case (AMD_ID_LV400T & 0xFF):
- info->flash_id += FLASH_AM400T;
- info->sector_count = 11;
- info->size = 0x00080000;
- break; /* => 512 kB */
-
- case (AMD_ID_LV400B & 0xFF):
- info->flash_id += FLASH_AM400B;
- info->sector_count = 11;
- info->size = 0x00080000;
- break; /* => 512 kB */
-
- case (AMD_ID_LV800T & 0xFF):
- info->flash_id += FLASH_AM800T;
- info->sector_count = 19;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (AMD_ID_LV800B & 0xFF):
- info->flash_id += FLASH_AM800B;
- info->sector_count = 19;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (AMD_ID_LV160T & 0xFF):
- info->flash_id += FLASH_AM160T;
- info->sector_count = 35;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (AMD_ID_LV160B & 0xFF):
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (AMD_ID_LV040B & 0xFF):
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x00080000;
- break;
-
- case (STM_ID_M29W040B & 0xFF):
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x00080000;
- break;
-
-#if 0 /* enable when device IDs are available */
- case (AMD_ID_LV320T & 0xFF):
- info->flash_id += FLASH_AM320T;
- info->sector_count = 67;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case (AMD_ID_LV320B & 0xFF):
- info->flash_id += FLASH_AM320B;
- info->sector_count = 67;
- info->size = 0x00400000;
- break; /* => 4 MB */
-#endif
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
-
- }
-
- printf(" ");
- /* set up sector start address table */
- if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000);
- }
- } else if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000) - 0x00030000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- }
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection: D0 = 1 if protected */
- caddr = (volatile unsigned char *)(info->start[i]);
- info->protect[i] = caddr[2] & 1;
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- caddr = (vu_char *) info->start[0];
-
- caddr[0x0555] = 0xAA;
- caddr[0x02AA] = 0x55;
- caddr[0x0555] = 0xF0;
-
- udelay(20000);
- }
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase(flash_info_t * info, int s_first, int s_last)
-{
- vu_char *addr = (vu_char *) (info->start[0]);
- int flag, prot, sect, l_sect;
- ulong start, now, last;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf("- missing\n");
- } else {
- printf("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id == FLASH_UNKNOWN) ||
- (info->flash_id > FLASH_AMD_COMP)) {
- printf("Can't erase unknown flash type %08lx - aborted\n", info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf("- Warning: %d protected sectors will not be erased!\n", prot);
- } else {
- printf("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x0555] = 0xAA;
- addr[0x02AA] = 0x55;
- addr[0x0555] = 0x80;
- addr[0x0555] = 0xAA;
- addr[0x02AA] = 0x55;
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = (vu_char *) (info->start[sect]);
- addr[0] = 0x30;
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay(1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer(0);
- last = start;
- addr = (vu_char *) (info->start[l_sect]);
- while ((addr[0] & 0x80) != 0x80) {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc('.');
- last = now;
- }
- }
-
- DONE:
- /* reset to read mode */
- addr = (vu_char *) info->start[0];
- addr[0] = 0xF0; /* reset bank */
-
- printf(" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- int rc;
-
- while (cnt > 0) {
- if ((rc = write_byte(info, addr++, *src++)) != 0) {
- return (rc);
- }
- --cnt;
- }
-
- return (0);
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_byte(flash_info_t * info, ulong dest, uchar data)
-{
- vu_char *addr = (vu_char *) (info->start[0]);
- ulong start;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((vu_char *) dest) & data) != data) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x0555] = 0xAA;
- addr[0x02AA] = 0x55;
- addr[0x0555] = 0xA0;
-
- *((vu_char *) dest) = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer(0);
- while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
diff --git a/board/netvia/netvia.c b/board/netvia/netvia.c
deleted file mode 100644
index b3bbf47..0000000
--- a/board/netvia/netvia.c
+++ /dev/null
@@ -1,401 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Pantelis Antoniou, Intracom S.A., panto at intracom.gr
- * U-Boot port on NetVia board
- */
-
-#include <common.h>
-#include "mpc8xx.h"
-
-/****************************************************************/
-
-#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
-/* last value written to the external register; we cannot read back */
-unsigned int last_er_val;
-#endif
-
-/****************************************************************/
-
-/****************************************************************/
-
-/* some sane bit macros */
-#define _BD(_b) (1U << (31-(_b)))
-#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
-
-#define _BW(_b) (1U << (15-(_b)))
-#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
-
-#define _BB(_b) (1U << (7-(_b)))
-#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
-
-#define _B(_b) _BD(_b)
-#define _BR(_l, _h) _BDR(_l, _h)
-
-/****************************************************************/
-
-#define _NOT_USED_ 0xFFFFFFFF
-
-/****************************************************************/
-
-#define CS_0000 0x00000000
-#define CS_0001 0x10000000
-#define CS_0010 0x20000000
-#define CS_0011 0x30000000
-#define CS_0100 0x40000000
-#define CS_0101 0x50000000
-#define CS_0110 0x60000000
-#define CS_0111 0x70000000
-#define CS_1000 0x80000000
-#define CS_1001 0x90000000
-#define CS_1010 0xA0000000
-#define CS_1011 0xB0000000
-#define CS_1100 0xC0000000
-#define CS_1101 0xD0000000
-#define CS_1110 0xE0000000
-#define CS_1111 0xF0000000
-
-#define BS_0000 0x00000000
-#define BS_0001 0x01000000
-#define BS_0010 0x02000000
-#define BS_0011 0x03000000
-#define BS_0100 0x04000000
-#define BS_0101 0x05000000
-#define BS_0110 0x06000000
-#define BS_0111 0x07000000
-#define BS_1000 0x08000000
-#define BS_1001 0x09000000
-#define BS_1010 0x0A000000
-#define BS_1011 0x0B000000
-#define BS_1100 0x0C000000
-#define BS_1101 0x0D000000
-#define BS_1110 0x0E000000
-#define BS_1111 0x0F000000
-
-#define A10_AAAA 0x00000000
-#define A10_AAA0 0x00200000
-#define A10_AAA1 0x00300000
-#define A10_000A 0x00800000
-#define A10_0000 0x00A00000
-#define A10_0001 0x00B00000
-#define A10_111A 0x00C00000
-#define A10_1110 0x00E00000
-#define A10_1111 0x00F00000
-
-#define RAS_0000 0x00000000
-#define RAS_0001 0x00040000
-#define RAS_1110 0x00080000
-#define RAS_1111 0x000C0000
-
-#define CAS_0000 0x00000000
-#define CAS_0001 0x00010000
-#define CAS_1110 0x00020000
-#define CAS_1111 0x00030000
-
-#define WE_0000 0x00000000
-#define WE_0001 0x00004000
-#define WE_1110 0x00008000
-#define WE_1111 0x0000C000
-
-#define GPL4_0000 0x00000000
-#define GPL4_0001 0x00001000
-#define GPL4_1110 0x00002000
-#define GPL4_1111 0x00003000
-
-#define GPL5_0000 0x00000000
-#define GPL5_0001 0x00000400
-#define GPL5_1110 0x00000800
-#define GPL5_1111 0x00000C00
-#define LOOP 0x00000080
-
-#define EXEN 0x00000040
-
-#define AMX_COL 0x00000000
-#define AMX_ROW 0x00000020
-#define AMX_MAR 0x00000030
-
-#define NA 0x00000008
-
-#define UTA 0x00000004
-
-#define TODT 0x00000002
-
-#define LAST 0x00000001
-
-const uint sdram_table[0x40] = {
- /* RSS */
- CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
- CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
- CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
- CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
- _NOT_USED_, _NOT_USED_,
-
- /* RBS */
- CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
- CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
- CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
- CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
- CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /* WSS */
- CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,
- CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,
- CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA,
- CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /* WBS */
- CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
- CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */
- CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
- CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /* UPT */
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | LOOP,
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | LOOP,
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | LAST,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_,
-
- /* EXC */
- CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL,
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST,
-
- /* REG */
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1110 | AMX_MAR,
- CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | TODT | LAST,
-};
-
-/* ------------------------------------------------------------------------- */
-
-
-/*
- * Check Board Identity:
- *
- * Test ETX ID string (ETX_xxx...)
- *
- * Return 1 always.
- */
-
-int checkboard(void)
-{
-#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
- printf ("NETVIA v1\n");
-#else
- printf ("NETVIA v2+\n");
-#endif
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */
-#define MAR_SDRAM_INIT 0x000000C8LU
-
-#define MCR_OP(x) ((unsigned long)((x) & 3) << (31-1))
-#define MCR_OP_MASK MCR_OP(3)
-
-#define MCR_UM(x) ((unsigned long)((x) & 1) << (31 - 8))
-#define MCR_UM_MASK MCR_UM(1)
-#define MCR_UM_UPMA MCR_UM(0)
-#define MCR_UM_UPMB MCR_UM(1)
-
-#define MCR_MB(x) ((unsigned long)((x) & 7) << (31 - 18))
-#define MCR_MB_MASK MCR_MB(7)
-#define MCR_MB_CS(x) MCR_MB(x)
-
-#define MCR_MCLF(x) ((unsigned long)((x) & 15) << (31 - 23))
-#define MCR_MCLF_MASK MCR_MCLF(15)
-
-phys_size_t initdram(int board_type)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- long int size;
-
- upmconfig(UPMA, (uint *) sdram_table, sizeof(sdram_table) / sizeof(uint));
-
- /*
- * Preliminary prescaler for refresh
- */
- memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_8K;
-
- memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */
-
- /*
- * Map controller bank 3 to the SDRAM bank at preliminary address.
- */
- memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
- memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
-
- memctl->memc_mamr = CONFIG_SYS_MAMR_9COL & ~MAMR_PTAE; /* no refresh yet */
-
- udelay(200);
-
- /* perform SDRAM initialisation sequence */
- memctl->memc_mcr = MCR_OP_RUN | MCR_UM_UPMA | MCR_MB_CS3 | MCR_MCLF(1) | MCR_MAD(0x3C); /* precharge all */
- udelay(1);
- memctl->memc_mcr = MCR_OP_RUN | MCR_UM_UPMA | MCR_MB_CS3 | MCR_MCLF(0) | MCR_MAD(0x30); /* refresh 16 times(0) */
- udelay(1);
- memctl->memc_mcr = MCR_OP_RUN | MCR_UM_UPMA | MCR_MB_CS3 | MCR_MCLF(1) | MCR_MAD(0x3E); /* exception program (write mar) */
- udelay(1);
-
- memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
-
- udelay(1000);
-
- memctl->memc_mamr = CONFIG_SYS_MAMR_9COL;
-
- size = SDRAM_MAX_SIZE;
-
- udelay(10000);
-
- return (size);
-}
-
-/* ------------------------------------------------------------------------- */
-
-int misc_init_r(void)
-{
-#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
- last_er_val = 0xffffffff;
-#endif
- return(0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/* GP = general purpose, SP = special purpose (on chip peripheral) */
-
-/* bits that can have a special purpose or can be configured as inputs/outputs */
-#define PA_GP_INMASK 0
-#define PA_GP_OUTMASK (_BW(5) | _BWR(14, 15))
-#define PA_SP_MASK (_BW(4) | _BWR(6, 13))
-#define PA_ODR_VAL 0
-#define PA_GP_OUTVAL _BW(5)
-#define PA_SP_DIRVAL 0
-
-#define PB_GP_INMASK _B(28)
-#define PB_GP_OUTMASK (_BR(16, 19) | _BR(26, 27) | _BR(29, 31))
-#define PB_SP_MASK _BR(22, 25)
-#define PB_ODR_VAL 0
-#define PB_GP_OUTVAL (_BR(16, 19) | _BR(26, 27) | _BR(29, 31))
-#define PB_SP_DIRVAL 0
-
-#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
-
-#define PC_GP_INMASK (_BWR(5, 7) | _BWR(9, 10) | _BW(13))
-#define PC_GP_OUTMASK _BW(12)
-#define PC_SP_MASK (_BW(4) | _BW(8))
-#define PC_SOVAL 0
-#define PC_INTVAL 0
-#define PC_GP_OUTVAL 0
-#define PC_SP_DIRVAL 0
-
-#define PD_GP_INMASK 0
-#define PD_GP_OUTMASK _BWR(3, 15)
-#define PD_SP_MASK 0
-#define PD_GP_OUTVAL (_BW(3) | _BW(5) | _BW(7) | _BWR(8, 15))
-#define PD_SP_DIRVAL 0
-
-#elif CONFIG_NETVIA_VERSION >= 2
-
-#define PC_GP_INMASK (_BW(5) | _BW(7) | _BWR(9, 11) | _BWR(13, 15))
-#define PC_GP_OUTMASK (_BW(6) | _BW(12))
-#define PC_SP_MASK (_BW(4) | _BW(8))
-#define PC_SOVAL 0
-#define PC_INTVAL _BW(7)
-#define PC_GP_OUTVAL (_BW(6) | _BW(12))
-#define PC_SP_DIRVAL 0
-
-#define PD_GP_INMASK 0
-#define PD_GP_OUTMASK _BWR(3, 15)
-#define PD_SP_MASK 0
-#define PD_GP_OUTVAL (_BW(3) | _BW(5) | _BW(9) | _BW(11))
-#define PD_SP_DIRVAL 0
-
-#else
-#error Unknown NETVIA board version.
-#endif
-
-int board_early_init_f(void)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile iop8xx_t *ioport = &immap->im_ioport;
- volatile cpm8xx_t *cpm = &immap->im_cpm;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
- /* DSP0 chip select */
- memctl->memc_or4 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX);
- memctl->memc_br4 = ((DSP0_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
-
- /* DSP1 chip select */
- memctl->memc_or5 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX);
- memctl->memc_br5 = ((DSP1_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
-
- /* FPGA chip select */
- memctl->memc_or6 = ((0xFFFFFFFFLU & ~(FPGA_SIZE - 1)) | OR_BI | OR_SCY_1_CLK);
- memctl->memc_br6 = ((FPGA_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
-
-#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
- /* NAND chip select */
- memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK | OR_EHTR | OR_TRLX);
- memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
-
- /* kill this chip select */
- memctl->memc_br2 &= ~BR_V; /* invalid */
-
- /* external reg chip select */
- memctl->memc_or7 = ((0xFFFFFFFFLU & ~(ER_SIZE - 1)) | OR_BI | OR_SCY_4_CLK);
- memctl->memc_br7 = ((ER_BASE & BR_BA_MSK) | BR_PS_32 | BR_V);
-#endif
-
- ioport->iop_padat = PA_GP_OUTVAL;
- ioport->iop_paodr = PA_ODR_VAL;
- ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL;
- ioport->iop_papar = PA_SP_MASK;
-
- cpm->cp_pbdat = PB_GP_OUTVAL;
- cpm->cp_pbodr = PB_ODR_VAL;
- cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL;
- cpm->cp_pbpar = PB_SP_MASK;
-
- ioport->iop_pcdat = PC_GP_OUTVAL;
- ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL;
- ioport->iop_pcso = PC_SOVAL;
- ioport->iop_pcint = PC_INTVAL;
- ioport->iop_pcpar = PC_SP_MASK;
-
- ioport->iop_pddat = PD_GP_OUTVAL;
- ioport->iop_pddir = PD_GP_OUTMASK | PD_SP_DIRVAL;
- ioport->iop_pdpar = PD_SP_MASK;
-
-#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
- /* external register init */
- *(volatile uint *)ER_BASE = 0xFFFFFFFF;
-#endif
-
- return 0;
-}
diff --git a/board/netvia/u-boot.lds.debug b/board/netvia/u-boot.lds.debug
deleted file mode 100644
index 5bbf1c5..0000000
--- a/board/netvia/u-boot.lds.debug
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
-
- . = env_offset;
- common/env_embedded.o(.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
diff --git a/configs/NETVIA_V2_defconfig b/configs/NETVIA_V2_defconfig
deleted file mode 100644
index 2715910..0000000
--- a/configs/NETVIA_V2_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="NETVIA_VERSION=2"
-CONFIG_PPC=y
-CONFIG_8xx=y
-CONFIG_TARGET_NETVIA=y
diff --git a/configs/NETVIA_defconfig b/configs/NETVIA_defconfig
deleted file mode 100644
index 27c8f2b..0000000
--- a/configs/NETVIA_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="NETVIA_VERSION=1"
-CONFIG_PPC=y
-CONFIG_8xx=y
-CONFIG_TARGET_NETVIA=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 1e475af..6b391df 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+NETVIA powerpc mpc8xx - - Pantelis Antoniou <panto@intracom.gr>
R360MPI powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
RRvision powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
SPD823TS powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
diff --git a/include/commproc.h b/include/commproc.h
index 38e4e7d..8de0d15 100644
--- a/include/commproc.h
+++ b/include/commproc.h
@@ -594,39 +594,6 @@ typedef struct scc_enet {
#define SICR_ENET_CLKRT ((uint)0x00250000)
#endif /* CONFIG_KM8XX */
-/*** NETVIA *******************************************************/
-
-#if defined(CONFIG_NETVIA)
-/* Bits in parallel I/O port registers that have to be set/cleared
- * to configure the pins for SCC2 use.
- */
-#define PROFF_ENET PROFF_SCC2
-#define CPM_CR_ENET CPM_CR_CH_SCC2
-#define SCC_ENET 1
-#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
-#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
-#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
-#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */
-
-#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
-# define PB_ENET_PDN ((ushort)0x4000) /* PB 17 */
-#elif CONFIG_NETVIA_VERSION >= 2
-# define PC_ENET_PDN ((ushort)0x0008) /* PC 12 */
-#endif
-
-#define PB_ENET_TENA ((ushort)0x2000) /* PB 18 */
-
-#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
-#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
-
-/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
- * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
- */
-#define SICR_ENET_MASK ((uint)0x0000ff00)
-#define SICR_ENET_CLKRT ((uint)0x00002f00)
-
-#endif /* CONFIG_NETVIA */
-
/*** MVS1, TQM823L/M, TQM850L/M, TQM885D, R360MPI **********/
#if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \
diff --git a/include/configs/NETVIA.h b/include/configs/NETVIA.h
deleted file mode 100644
index 4a0fa9e..0000000
--- a/include/configs/NETVIA.h
+++ /dev/null
@@ -1,435 +0,0 @@
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
- * U-Boot port on NetVia board
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
-#define CONFIG_NETVIA 1 /* ...on a NetVia board */
-
-#define CONFIG_SYS_TEXT_BASE 0x40000000
-
-#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
-#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-#else
-#define CONFIG_8xx_CONS_NONE
-#define CONFIG_MAX3100_SERIAL
-#endif
-
-#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
-
-#define CONFIG_XIN 10000000
-#define CONFIG_8xx_GCLK_FREQ 80000000
-
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-
-#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */
-
-#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
-
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND \
- "tftpboot; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
- "bootm"
-
-#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_STATUS_LED 1 /* Status LED enabled */
-
-#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
-#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
-#endif
-
-#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_NISDOMAIN
-
-
-#undef CONFIG_MAC_PARTITION
-#undef CONFIG_DOS_PARTITION
-
-#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
-
-#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
-/* #define CONFIG_CMD_NAND */ /* disabled */
-#endif
-
-
-#define CONFIG_BOARD_EARLY_INIT_F 1
-#define CONFIG_MISC_INIT_R
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xFF000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0x40000000
-#if defined(DEBUG)
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#else
-#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
-#endif
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SECT_SIZE 0x10000
-
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x60000)
-#define CONFIG_ENV_SIZE 0x4000
-
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x70000)
-#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#ifndef CONFIG_CAN_DRIVER
-#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
-#else /* we must activate GPL5 in the SIUMCR for CAN */
-#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
-#endif /* CONFIG_CAN_DRIVER */
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register 11-27
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit
- *
- *
- *-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-
-#define SCCR_MASK SCCR_EBDF11
-
-#if CONFIG_8xx_GCLK_FREQ == 50000000
-
-#define CONFIG_SYS_PLPRCR ( ((5 - 1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-#define CONFIG_SYS_SCCR (SCCR_TBS | \
- SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
- SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
- SCCR_DFALCD00)
-
-#elif CONFIG_8xx_GCLK_FREQ == 80000000
-
-#define CONFIG_SYS_PLPRCR ( ((8 - 1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-#define CONFIG_SYS_SCCR (SCCR_TBS | \
- SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
- SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
- SCCR_DFALCD00 | SCCR_EBDF01)
-
-#endif
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-/*#define CONFIG_SYS_DER 0x2002000F*/
-#define CONFIG_SYS_DER 0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
-
-/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
-#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX)
-
-#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
-
-/*
- * BR3 and OR3 (SDRAM)
- *
- */
-#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */
-#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
-#define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS)
-
-#define CONFIG_SYS_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM)
-#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V)
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CONFIG_SYS_MAMR_PTA 208
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
-#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 9 column SDRAM */
-#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-/* Ethernet@SCC2 */
-#define CONFIG_SCC2_ENET
-
-/****************************************************************/
-
-#define DSP_SIZE 0x00010000 /* 64K */
-#define FPGA_SIZE 0x00010000 /* 64K */
-
-#define DSP0_BASE 0xF1000000
-#define DSP1_BASE (DSP0_BASE + DSP_SIZE)
-#define FPGA_BASE (DSP1_BASE + DSP_SIZE)
-
-#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
-
-#define ER_SIZE 0x00010000 /* 64K */
-#define ER_BASE (FPGA_BASE + FPGA_SIZE)
-
-#define NAND_SIZE 0x00010000 /* 64K */
-#define NAND_BASE (ER_BASE + ER_SIZE)
-
-#endif
-
-/****************************************************************/
-
-#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
-
-#define STATUS_LED_BIT 0x00000001 /* bit 31 */
-#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
-#define STATUS_LED_STATE STATUS_LED_BLINKING
-
-#define STATUS_LED_BIT1 0x00000002 /* bit 30 */
-#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
-#define STATUS_LED_STATE1 STATUS_LED_OFF
-
-#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
-#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
-
-#endif
-
-
-/*****************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
-
-/* LEDs */
-
-/* last value written to the external register; we cannot read back */
-extern unsigned int last_er_val;
-
-/* led_id_t is unsigned long mask */
-typedef unsigned int led_id_t;
-
-static inline void __led_init(led_id_t mask, int state)
-{
- unsigned int new_er_val;
-
- if (state)
- new_er_val = last_er_val & ~mask;
- else
- new_er_val = last_er_val | mask;
-
- *(volatile unsigned int *)ER_BASE = new_er_val;
- last_er_val = new_er_val;
-}
-
-static inline void __led_toggle(led_id_t mask)
-{
- unsigned int new_er_val;
-
- new_er_val = last_er_val ^ mask;
- *(volatile unsigned int *)ER_BASE = new_er_val;
- last_er_val = new_er_val;
-}
-
-static inline void __led_set(led_id_t mask, int state)
-{
- unsigned int new_er_val;
-
- if (state)
- new_er_val = last_er_val & ~mask;
- else
- new_er_val = last_er_val | mask;
-
- *(volatile unsigned int *)ER_BASE = new_er_val;
- last_er_val = new_er_val;
-}
-
-/* MAX3100 console */
-#define MAX3100_SPI_RXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
-#define MAX3100_SPI_RXD_BIT 0x00000008
-
-#define MAX3100_SPI_TXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
-#define MAX3100_SPI_TXD_BIT 0x00000004
-
-#define MAX3100_SPI_CLK_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
-#define MAX3100_SPI_CLK_BIT 0x00000002
-
-#define MAX3100_CS_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat)
-#define MAX3100_CS_BIT 0x0010
-
-#endif
-
-#endif
-
-/*************************************************************************************************/
-
-#endif /* __CONFIG_H */
diff --git a/include/status_led.h b/include/status_led.h
index 1feeff5..919e3ae 100644
--- a/include/status_led.h
+++ b/include/status_led.h
@@ -122,29 +122,6 @@ void status_led_set (int led, int state);
* filling this file up with lots of custom board stuff.
*/
-/***** NetVia ********************************************************/
-#elif defined(CONFIG_NETVIA)
-
-#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
-
-#define STATUS_LED_PAR im_ioport.iop_pdpar
-#define STATUS_LED_DIR im_ioport.iop_pddir
-#undef STATUS_LED_ODR
-#define STATUS_LED_DAT im_ioport.iop_pddat
-
-# define STATUS_LED_BIT 0x0080 /* PD.8 */
-# define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
-# define STATUS_LED_STATE STATUS_LED_BLINKING
-
-# define STATUS_LED_BIT1 0x0040 /* PD.9 */
-# define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
-# define STATUS_LED_STATE1 STATUS_LED_OFF
-
-# define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
-# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
-
-#endif
-
/***** CMI ********************************************************/
#elif defined(CONFIG_CMI)
# define STATUS_LED_DIR im_mios.mios_mpiosm32ddr
--
1.9.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [U-Boot] [PATCH 09/26] mpc8xx: remove lwmon board support
2014-12-15 14:26 [U-Boot] [PATCH 0/26] Start removing non-generic boards Masahiro Yamada
` (7 preceding siblings ...)
2014-12-15 14:26 ` [U-Boot] [PATCH 08/26] mpc8xx: remove NETVIA " Masahiro Yamada
@ 2014-12-15 14:26 ` Masahiro Yamada
2015-01-05 18:20 ` Tom Rini
2014-12-15 14:26 ` [U-Boot] [PATCH 10/26] mpc8xx: remove IVMS8, IVML24 " Masahiro Yamada
` (18 subsequent siblings)
27 siblings, 1 reply; 55+ messages in thread
From: Masahiro Yamada @ 2014-12-15 14:26 UTC (permalink / raw)
To: u-boot
This board is still a non-generic board.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
---
arch/powerpc/cpu/mpc8xx/Kconfig | 4 -
arch/powerpc/cpu/mpc8xx/cpu.c | 46 +-
arch/powerpc/cpu/mpc8xx/cpu_init.c | 1 -
arch/powerpc/cpu/mpc8xx/i2c.c | 7 -
arch/powerpc/cpu/mpc8xx/scc.c | 4 -
arch/powerpc/cpu/mpc8xx/serial.c | 16 -
arch/powerpc/include/asm/global_data.h | 2 +-
board/lwmon/Kconfig | 9 -
board/lwmon/MAINTAINERS | 6 -
board/lwmon/Makefile | 8 -
board/lwmon/README.keybd | 126 ----
board/lwmon/flash.c | 632 -------------------
board/lwmon/lwmon.c | 1071 --------------------------------
board/lwmon/pcmcia.c | 234 -------
board/lwmon/u-boot.lds.debug | 122 ----
configs/lwmon_defconfig | 3 -
doc/README.scrapyard | 1 +
drivers/pcmcia/mpc8xx_pcmcia.c | 6 -
drivers/video/mpc8xx_lcd.c | 11 -
examples/standalone/test_burst.c | 19 -
include/common.h | 4 -
include/commproc.h | 26 -
include/configs/lwmon.h | 587 -----------------
include/pcmcia.h | 2 -
24 files changed, 3 insertions(+), 2944 deletions(-)
delete mode 100644 board/lwmon/Kconfig
delete mode 100644 board/lwmon/MAINTAINERS
delete mode 100644 board/lwmon/Makefile
delete mode 100644 board/lwmon/README.keybd
delete mode 100644 board/lwmon/flash.c
delete mode 100644 board/lwmon/lwmon.c
delete mode 100644 board/lwmon/pcmcia.c
delete mode 100644 board/lwmon/u-boot.lds.debug
delete mode 100644 configs/lwmon_defconfig
delete mode 100644 include/configs/lwmon.h
diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig
index b510e1f..4d47d05 100644
--- a/arch/powerpc/cpu/mpc8xx/Kconfig
+++ b/arch/powerpc/cpu/mpc8xx/Kconfig
@@ -22,9 +22,6 @@ config TARGET_IVML24
config TARGET_IVMS8
bool "Support IVMS8"
-config TARGET_LWMON
- bool "Support lwmon"
-
config TARGET_TQM823L
bool "Support TQM823L"
@@ -67,7 +64,6 @@ source "board/cogent/Kconfig"
source "board/esteem192e/Kconfig"
source "board/ip860/Kconfig"
source "board/ivm/Kconfig"
-source "board/lwmon/Kconfig"
source "board/tqc/tqm8xx/Kconfig"
endmenu
diff --git a/arch/powerpc/cpu/mpc8xx/cpu.c b/arch/powerpc/cpu/mpc8xx/cpu.c
index 9967664..105be9c 100644
--- a/arch/powerpc/cpu/mpc8xx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xx/cpu.c
@@ -457,8 +457,6 @@ void upmconfig (uint upm, uint * table, uint size)
/* ------------------------------------------------------------------------- */
-#ifndef CONFIG_LWMON
-
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
ulong msr, addr;
@@ -493,32 +491,6 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
return 1;
}
-#else /* CONFIG_LWMON */
-
-/*
- * On the LWMON board, the MCLR reset input of the PIC's on the board
- * uses a 47K/1n RC combination which has a 47us time constant. The
- * low signal on the HRESET pin of the CPU is only 512 clocks = 8 us
- * and thus too short to reset the external hardware. So we use the
- * watchdog to reset the board.
- */
-int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- /* prevent triggering the watchdog */
- disable_interrupts ();
-
- /* make sure the watchdog is running */
- reset_8xx_watchdog ((immap_t *) CONFIG_SYS_IMMR);
-
- /* wait for watchdog reset */
- while (1) {};
-
- /* NOTREACHED */
- return 1;
-}
-
-#endif /* CONFIG_LWMON */
-
/* ------------------------------------------------------------------------- */
/*
@@ -580,31 +552,15 @@ void watchdog_reset (void)
}
#endif /* CONFIG_WATCHDOG */
-#if defined(CONFIG_WATCHDOG) || defined(CONFIG_LWMON)
+#if defined(CONFIG_WATCHDOG)
void reset_8xx_watchdog (volatile immap_t * immr)
{
-# if defined(CONFIG_LWMON)
- /*
- * The LWMON board uses a MAX6301 Watchdog
- * with the trigger pin connected to port PA.7
- *
- * (The old board version used a MAX706TESA Watchdog, which
- * had to be handled exactly the same.)
- */
-# define WATCHDOG_BIT 0x0100
- immr->im_ioport.iop_papar &= ~(WATCHDOG_BIT); /* GPIO */
- immr->im_ioport.iop_padir |= WATCHDOG_BIT; /* Output */
- immr->im_ioport.iop_paodr &= ~(WATCHDOG_BIT); /* active output */
-
- immr->im_ioport.iop_padat ^= WATCHDOG_BIT; /* Toggle WDI */
-# else
/*
* All other boards use the MPC8xx Internal Watchdog
*/
immr->im_siu_conf.sc_swsr = 0x556c; /* write magic1 */
immr->im_siu_conf.sc_swsr = 0xaa39; /* write magic2 */
-# endif /* CONFIG_LWMON */
}
#endif /* CONFIG_WATCHDOG */
diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c
index 9350fdd..d41fa88 100644
--- a/arch/powerpc/cpu/mpc8xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c
@@ -128,7 +128,6 @@ void cpu_init_f (volatile immap_t * immr)
#if defined(CONFIG_IP860) || \
defined(CONFIG_IVML24) || \
defined(CONFIG_IVMS8) || \
- defined(CONFIG_LWMON) || \
defined(CONFIG_RMU)
memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM;
diff --git a/arch/powerpc/cpu/mpc8xx/i2c.c b/arch/powerpc/cpu/mpc8xx/i2c.c
index 2f8b139..6146de3 100644
--- a/arch/powerpc/cpu/mpc8xx/i2c.c
+++ b/arch/powerpc/cpu/mpc8xx/i2c.c
@@ -17,9 +17,6 @@
#include <commproc.h>
#include <i2c.h>
-#ifdef CONFIG_LWMON
-#include <watchdog.h>
-#endif
DECLARE_GLOBAL_DATA_PTR;
@@ -591,10 +588,6 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
uchar xaddr[4];
int rc;
-#ifdef CONFIG_LWMON
- WATCHDOG_RESET();
-#endif
-
xaddr[0] = (addr >> 24) & 0xFF;
xaddr[1] = (addr >> 16) & 0xFF;
xaddr[2] = (addr >> 8) & 0xFF;
diff --git a/arch/powerpc/cpu/mpc8xx/scc.c b/arch/powerpc/cpu/mpc8xx/scc.c
index 610fd78..251966b 100644
--- a/arch/powerpc/cpu/mpc8xx/scc.c
+++ b/arch/powerpc/cpu/mpc8xx/scc.c
@@ -193,10 +193,6 @@ static int scc_init (struct eth_device *dev, bd_t * bis)
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
-#if defined(CONFIG_LWMON)
- reset_phy();
-#endif
-
pram_ptr = (scc_enet_t *) & (immr->im_cpm.cp_dparam[PROFF_ENET]);
rxIdx = 0;
diff --git a/arch/powerpc/cpu/mpc8xx/serial.c b/arch/powerpc/cpu/mpc8xx/serial.c
index b1625fb..bb16b17 100644
--- a/arch/powerpc/cpu/mpc8xx/serial.c
+++ b/arch/powerpc/cpu/mpc8xx/serial.c
@@ -405,22 +405,6 @@ static int scc_init (void)
sp = (scc_t *) &(cp->cp_scc[SCC_INDEX]);
up = (scc_uart_t *) &cp->cp_dparam[PROFF_SCC];
-#if defined(CONFIG_LWMON) && defined(CONFIG_8xx_CONS_SCC2)
- { /* Disable Ethernet, enable Serial */
- uchar c;
-
- c = pic_read (0x61);
- c &= ~0x40; /* enable COM3 */
- c |= 0x80; /* disable Ethernet */
- pic_write (0x61, c);
-
- /* enable RTS2 */
- cp->cp_pbpar |= 0x2000;
- cp->cp_pbdat |= 0x2000;
- cp->cp_pbdir |= 0x2000;
- }
-#endif /* CONFIG_LWMON */
-
/* Disable transmitter/receiver. */
sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index 8e59e8b..4430477 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -109,7 +109,7 @@ struct arch_global_data {
#if defined(CONFIG_WD_MAX_RATE)
unsigned long long wdt_last; /* trace watch-dog triggering rate */
#endif
-#if defined(CONFIG_LWMON) || defined(CONFIG_LWMON5)
+#if defined(CONFIG_LWMON5)
unsigned long kbd_status;
#endif
};
diff --git a/board/lwmon/Kconfig b/board/lwmon/Kconfig
deleted file mode 100644
index e98c794..0000000
--- a/board/lwmon/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_LWMON
-
-config SYS_BOARD
- default "lwmon"
-
-config SYS_CONFIG_NAME
- default "lwmon"
-
-endif
diff --git a/board/lwmon/MAINTAINERS b/board/lwmon/MAINTAINERS
deleted file mode 100644
index 763ce22..0000000
--- a/board/lwmon/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-LWMON BOARD
-M: Wolfgang Denk <wd@denx.de>
-S: Maintained
-F: board/lwmon/
-F: include/configs/lwmon.h
-F: configs/lwmon_defconfig
diff --git a/board/lwmon/Makefile b/board/lwmon/Makefile
deleted file mode 100644
index 599a613..0000000
--- a/board/lwmon/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = lwmon.o flash.o pcmcia.o
diff --git a/board/lwmon/README.keybd b/board/lwmon/README.keybd
deleted file mode 100644
index 5e5144e..0000000
--- a/board/lwmon/README.keybd
+++ /dev/null
@@ -1,126 +0,0 @@
-
-Tastaturabfrage:
-
-Die Implementierung / Decodierung beruht auf den Angaben aus dem Do-
-kument "PIC LWE-Tastatur" in der Fassung vom 9. 3. 2001, insbesonde-
-re Tabelle 3 im Kapitel 4.3 Tastencodes. In U-Boot werden die vom
-Keyboard-Controller gelesenen Daten hexadezimal codiert in der auto-
-matisch angelegten Environment-Variablen "keybd" ?bergeben. Ist kei-
-ne Taste gedr?ckt worden, steht dort:
-
- keybd=000000000000000000
-
-Der decodierte Tastencode ("keybd") kann mit den "bootargs" an den
-Linux-Kernel ?bergeben und dort z. B. in einem Device-Treiber oder
-einer Applikation ausgewertet werden.
-
-
-Sonderfunktionen beim Booten:
-
-Es lassen sich eine oder mehrere (beliebig viele) Tasten oder Tasten-
-kombinationen definieren, die Sonderfunktionen ausl?sen, wenn diese
-Tasten beim Booten (Reset) gedr?ckt sind.
-
-Wird eine eingestellte Taste bzw. Tastenkombination erkannt, so wird
-in U-Boot noch vor dem Start des "Countdown" und somit vor jedem an-
-deren Kommando der Inhalt einer dieser Taste bzw. Tastenkombination
-zugeordneten Environment-Variablen ausf?hren.
-
-
-Die Environment-Variable "magic_keys" wird als Liste von Zeichen ver-
-standen, die als Suffix an den Namen "key_magic" angef?gt werden und
-so die Namen der Environment-Variablen definieren, mit denen die
-Tasten (-kombinationen) festgelegt werden:
-
-Ist "magic_keys" NICHT definiert, so wird nur die in der Environment-
-Variablen "key_magic" codierte Tasten (-kombination) gepr?ft, und
-ggf. der Inhalt der Environment-Variablen "key_cmd" ausgef?hrt (ge-
-nauer: der Inhalt von "key_cmd" wird der Variablen "preboot" zugewie-
-sen, die ausgef?hrt wird, unmittelbar bevor die interaktive Kommando-
-interpretation beginnt).
-
-Enth?lt "magic_keys" z. B. die Zeichenkette "0123CB*", so werden
-nacheinander folgende Aktionen ausgef?hrt:
-
- pr?fe Tastencode ggf. f?hre aus Kommando
- in Variable in Variable
- -----------------------------------
- key_magic0 ==> key_cmd0
- key_magic1 ==> key_cmd1
- key_magic2 ==> key_cmd2
- key_magic3 ==> key_cmd3
- key_magicC ==> key_cmdC
- key_magicB ==> key_cmdB
- key_magicA ==> key_cmdA
- key_magic* ==> key_cmd*
-
-Hinweis: sobald ein aktivierter Tastencode erkannt wurde, wird die
-Bearbeitung abgebrochen; es wird daher h?chstens eines der definier-
-ten Kommandos ausgef?hrt, wobei die Priorit?t durch die Suchreihen-
-folge festgelegt wird, also durch die Reihenfolge der Zeichen in der
-Varuiablen "magic_keys".
-
-
-Die Codierung der Tasten, die beim Booten gedr?ckt werden m?ssen, um
-eine Funktion auszul?sen, erfolgt nach der Tastaturtabelle.
-
-Die Definitionen
-
- => setenv key_magic0 3a+3b
- => setenv key_cmd0 setenv bootdelay 30
-
-bedeuten dementsprechend, da? die Tasten mit den Codes 0x3A (Taste
-"F1") und 0x3B (Taste "F2") gleichzeitig gedr?ckt werden m?ssen. Sie
-k?nnen dort eine beliebige Tastenkombination eintragen (jeweils 2
-Zeichen f?r die Hex-Codes der Tasten, und '+' als Trennzeichen).
-
-Wird die eingestellte Tastenkombination erkannt, so wird in U-Boot
-noch vor dem Start des "Countdown" und somit vor jedem anderen Kom-
-mando das angebene Kommando ausgef?hrt und somit ein langes Boot-
-Delay eingetragen.
-
-Praktisch k?nnten Sie also in U-Boot "bootdelay" auf 0 setzen und
-somit stets ohne jede User-Interaktion automatisch booten, au?er,
-wenn die beiden Tasten "F1" und "F2" beim Booten gedr?ckt werden:
-dann w?rde ein Boot-Delay von 30 Sekunden eingef?gt.
-
-
-Hinweis: dem Zeichen '#' kommt innerhalb von "magic_keys" eine beson-
-dere Bedeutung zu: die dadurch definierte Key-Sequenz schaltet den
-Monitor in den "Debug-Modus" - das bedeutet zun?chst, da? alle weite-
-ren Meldungen von U-Boot ?ber das LCD-Display ausgegeben werden;
-au?erdem kann man durch das mit dieser Tastenkombination verkn?pfte
-Kommando z. B. die Linux-Bootmeldungen ebenfalls auf das LCD-Display
-legen, so da? der Boot-Vorgang direkt und ohne weitere Hilfsmittel
-analysiert werden kann.
-
-Beispiel:
-
-In U-Boot werden folgende Environment-Variablen gesetzt und abgespei-
-chert:
-
-(1) => setenv magic_keys 01234#X
-(2) => setenv key_cmd# setenv addfb setenv bootargs \\${bootargs} console=tty0 console=ttyS1,\\${baudrate}
-(3) => setenv nfsargs setenv bootargs root=/dev/nfs rw nfsroot=\${serverip}:\${rootpath}
-(4) => setenv addip setenv bootargs \${bootargs} ip=\${ipaddr}:\${serverip}:\${gatewayip}:\${netmask}:\${hostname}::off panic=1
-(5) => setenv addfb setenv bootargs \${bootargs} console=ttyS1,\${baudrate}
-(6) => setenv bootcmd bootp\;run nfsargs\;run addip\;run addfb\;bootm
-
-Hierbei wird die Linux Commandline (in der Variablen "bootargs") im
-Boot-Kommando "bootcmd" (6) schrittweise zusammengesetzt: zun?chst
-werden die f?r Root-Filesystem ?ber NFS erforderlichen Optionen ge-
-setzt ("run nfsargs", vgl. (3)), dann die Netzwerkkonfiguration an-
-gef?gt ("run addip", vgl. (4)), und schlie?lich die Systemconsole
-definiert ("run addfb").
-
-Dabei wird im Normalfall die Definition (5) verwendt; wurde aller-
-dings beim Reset die entsprechende Taste gedr?ckt gehalten, so wird
-diese Definition bei der Ausf?hrung des in (2) definierten Kommandos
-?berschrieben, so da? Linux die Bootmeldungen auch ?ber das Frame-
-buffer-Device (=LCD-Display) ausgibt.
-
-Beachten Sie die Verdoppelung der '\'-Escapes in der Definition von
-"key_cmd#" - diese ist erforderlich, weil der String _zweimal_ inter-
-pretiert wird: das erste Mal bei der Eingabe von "key_cmd#", das
-zweite Mal, wenn der String (als Inhalt von "preboot") ausgef?hrt
-wird.
diff --git a/board/lwmon/flash.c b/board/lwmon/flash.c
deleted file mode 100644
index cb60c41..0000000
--- a/board/lwmon/flash.c
+++ /dev/null
@@ -1,632 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* #define DEBUG */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-# ifndef CONFIG_ENV_ADDR
-# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-# endif
-# ifndef CONFIG_ENV_SIZE
-# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-# endif
-# ifndef CONFIG_ENV_SECT_SIZE
-# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
-# endif
-#endif
-
-/*---------------------------------------------------------------------*/
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_data (flash_info_t *info, ulong dest, ulong data);
-#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-static int write_data_buf (flash_info_t * info, ulong dest, uchar * cp, int len);
-#endif
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- unsigned long size_b0, size_b1;
- int i;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- debug ("\n## Get flash bank 1 size @ 0x%08x\n",FLASH_BASE0_PRELIM);
-
- size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0: "
- "ID 0x%lx, Size = 0x%08lx = %ld MB\n",
- flash_info[0].flash_id,
- size_b0, size_b0<<20);
- }
-
- debug ("## Get flash bank 2 size @ 0x%08x\n",FLASH_BASE1_PRELIM);
-
- size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
-
- debug ("## Prelim. Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
-
- if (size_b1 > size_b0) {
- printf ("## ERROR: "
- "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
- size_b1, size_b1<<20,
- size_b0, size_b0<<20
- );
- flash_info[0].flash_id = FLASH_UNKNOWN;
- flash_info[1].flash_id = FLASH_UNKNOWN;
- flash_info[0].sector_count = -1;
- flash_info[1].sector_count = -1;
- flash_info[0].size = 0;
- flash_info[1].size = 0;
- return (0);
- }
-
- debug ("## Before remap: "
- "BR0: 0x%08x OR0: 0x%08x "
- "BR1: 0x%08x OR1: 0x%08x\n",
- memctl->memc_br0, memctl->memc_or0,
- memctl->memc_br1, memctl->memc_or1);
-
- /* Remap FLASH according to real size */
- memctl->memc_or0 = (-size_b0 & 0xFFFF8000) | CONFIG_SYS_OR_TIMING_FLASH |
- OR_CSNT_SAM | OR_ACS_DIV1;
- memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_PS_32 | BR_V;
-
- debug ("## BR0: 0x%08x OR0: 0x%08x\n",
- memctl->memc_br0, memctl->memc_or0);
-
- /* Re-do sizing to get full correct info */
- size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
- flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
- flash_info[0].size = size_b0;
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[0]);
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
- &flash_info[0]);
-#endif
-
- if (size_b1) {
- memctl->memc_or1 = (-size_b1 & 0xFFFF8000) | CONFIG_SYS_OR_TIMING_FLASH |
- OR_CSNT_SAM | OR_ACS_DIV1;
- memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) |
- BR_PS_32 | BR_V;
-
- debug ("## BR1: 0x%08x OR1: 0x%08x\n",
- memctl->memc_br1, memctl->memc_or1);
-
- /* Re-do sizing to get full correct info */
- size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0),
- &flash_info[1]);
-
- flash_info[1].size = size_b1;
-
- flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]);
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[1]);
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
- &flash_info[1]);
-#endif
- } else {
- memctl->memc_br1 = 0; /* invalidate bank */
- memctl->memc_or1 = 0; /* invalidate bank */
-
- debug ("## DISABLE BR1: 0x%08x OR1: 0x%08x\n",
- memctl->memc_br1, memctl->memc_or1);
-
- flash_info[1].flash_id = FLASH_UNKNOWN;
- flash_info[1].sector_count = -1;
- flash_info[1].size = 0;
- }
-
- debug ("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
-
- return (size_b0 + size_b1);
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_INTEL:
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base;
- base += 0x00020000 * 2; /* 128k * 2 chips per bank */
- }
- return;
-
- default:
- printf ("Don't know sector ofsets for flash type 0x%lx\n",
- info->flash_id);
- return;
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_FUJ: printf ("Fujitsu "); break;
- case FLASH_MAN_SST: printf ("SST "); break;
- case FLASH_MAN_STM: printf ("STM "); break;
- case FLASH_MAN_INTEL: printf ("Intel "); break;
- case FLASH_MAN_MT: printf ("MT "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F320J3A: printf ("28F320J3A (32Mbit = 128K x 32)\n");
- break;
- case FLASH_28F640J3A: printf ("28F640J3A (64Mbit = 128K x 64)\n");
- break;
- case FLASH_28F128J3A: printf ("28F128J3A (128Mbit = 128K x 128)\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- if (info->size >= (1 << 20)) {
- i = 20;
- } else {
- i = 10;
- }
- printf (" Size: %ld %cB in %d Sectors\n",
- info->size >> i,
- (i == 20) ? 'M' : 'k',
- info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
- return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
- ulong value;
-
- /* Read Manufacturer ID */
- addr[0] = 0x00900090;
- value = addr[0];
-
- debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value);
-
- switch (value) {
- case AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
- case FUJ_MANUFACT:
- info->flash_id = FLASH_MAN_FUJ;
- break;
- case SST_MANUFACT:
- info->flash_id = FLASH_MAN_SST;
- break;
- case STM_MANUFACT:
- info->flash_id = FLASH_MAN_STM;
- break;
- case INTEL_MANUFACT:
- info->flash_id = FLASH_MAN_INTEL;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- addr[0] = 0x00FF00FF; /* restore read mode */
- return (0); /* no or unknown flash */
- }
-
- value = addr[1]; /* device ID */
-
- debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value);
-
- switch (value) {
- case INTEL_ID_28F320J3A:
- info->flash_id += FLASH_28F320J3A;
- info->sector_count = 32;
- info->size = 0x00400000 * 2;
- break; /* => 8 MB */
-
- case INTEL_ID_28F640J3A:
- info->flash_id += FLASH_28F640J3A;
- info->sector_count = 64;
- info->size = 0x00800000 * 2;
- break; /* => 16 MB */
-
- case INTEL_ID_28F128J3A:
- info->flash_id += FLASH_28F128J3A;
- info->sector_count = 128;
- info->size = 0x01000000 * 2;
- break; /* => 32 MB */
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- addr[0] = 0x00FF00FF; /* restore read mode */
- return (0); /* => no or unknown flash */
-
- }
-
- if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
- printf ("** ERROR: sector count %d > max (%d) **\n",
- info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
- info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- }
-
- addr[0] = 0x00FF00FF; /* restore read mode */
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- int flag, prot, sect;
- ulong start, now, last;
-
- debug ("flash_erase: first: %d last: %d\n", s_first, s_last);
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) {
- printf ("Can erase only Intel flash types - aborted\n");
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- start = get_timer (0);
- last = start;
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- vu_long *addr = (vu_long *)(info->start[sect]);
- unsigned long status;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- *addr = 0x00600060; /* clear lock bit setup */
- *addr = 0x00D000D0; /* clear lock bit confirm */
-
- udelay (1000);
- /* This takes awfully long - up to 50 ms and more */
- while (((status = *addr) & 0x00800080) != 0x00800080) {
- if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- *addr = 0x00FF00FF; /* reset to read mode */
- return 1;
- }
-
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- udelay (1000); /* to trigger the watchdog */
- }
-
- *addr = 0x00500050; /* clear status register */
- *addr = 0x00200020; /* erase setup */
- *addr = 0x00D000D0; /* erase confirm */
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- while (((status = *addr) & 0x00800080) != 0x00800080) {
- if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- *addr = 0x00B000B0; /* suspend erase */
- *addr = 0x00FF00FF; /* reset to read mode */
- return 1;
- }
-
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- udelay (1000); /* to trigger the watchdog */
- }
-
- *addr = 0x00FF00FF; /* reset to read mode */
- }
- }
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 4 - Flash not identified
- */
-
-#define FLASH_WIDTH 4 /* flash bus width in bytes */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- return 4;
- }
-
- wp = (addr & ~(FLASH_WIDTH-1)); /* get lower FLASH_WIDTH aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<FLASH_WIDTH && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<FLASH_WIDTH; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_data(info, wp, data)) != 0) {
- return (rc);
- }
- wp += FLASH_WIDTH;
- }
-
- /*
- * handle FLASH_WIDTH aligned part
- */
-#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
- while(cnt >= FLASH_WIDTH) {
- i = CONFIG_SYS_FLASH_BUFFER_SIZE > cnt ?
- (cnt & ~(FLASH_WIDTH - 1)) : CONFIG_SYS_FLASH_BUFFER_SIZE;
- if((rc = write_data_buf(info, wp, src,i)) != 0)
- return rc;
- wp += i;
- src += i;
- cnt -=i;
- }
-#else
- while (cnt >= FLASH_WIDTH) {
- data = 0;
- for (i=0; i<FLASH_WIDTH; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_data(info, wp, data)) != 0) {
- return (rc);
- }
- wp += FLASH_WIDTH;
- cnt -= FLASH_WIDTH;
- }
-#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<FLASH_WIDTH && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<FLASH_WIDTH; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_data(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Check flash status, returns:
- * 0 - OK
- * 1 - timeout
- */
-static int flash_status_check(vu_long *addr, ulong tout, char * prompt)
-{
- ulong status;
- ulong start;
-
- /* Wait for command completion */
- start = get_timer (0);
- while(((status = *addr) & 0x00800080) != 0x00800080) {
- if (get_timer(start) > tout) {
- printf("Flash %s timeout at address %p\n", prompt, addr);
- *addr = 0x00FF00FF; /* restore read mode */
- return (1);
- }
- }
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_data (flash_info_t *info, ulong dest, ulong data)
-{
- vu_long *addr = (vu_long *)dest;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*addr & data) != data) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- *addr = 0x00400040; /* write setup */
- *addr = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- if (flash_status_check(addr, CONFIG_SYS_FLASH_WRITE_TOUT, "write") != 0) {
- return (1);
- }
-
- *addr = 0x00FF00FF; /* restore read mode */
-
- return (0);
-}
-
-#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-/*-----------------------------------------------------------------------
- * Write a buffer to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- */
-static int write_data_buf(flash_info_t * info, ulong dest, uchar * cp, int len)
-{
- vu_long *addr = (vu_long *)dest;
- int sector;
- int cnt;
- int retcode;
- vu_long * src = (vu_long *)cp;
- vu_long * dst = (vu_long *)dest;
-
- /* find sector */
- for(sector = info->sector_count - 1; sector >= 0; sector--) {
- if(dest >= info->start[sector])
- break;
- }
-
- *addr = 0x00500050; /* clear status */
- *addr = 0x00e800e8; /* write buffer */
-
- if((retcode = flash_status_check(addr, CONFIG_SYS_FLASH_BUFFER_WRITE_TOUT,
- "write to buffer")) == 0) {
- cnt = len / FLASH_WIDTH;
- *addr = (cnt-1) | ((cnt-1) << 16);
- while(cnt-- > 0) {
- *dst++ = *src++;
- }
- *addr = 0x00d000d0; /* write buffer confirm */
- retcode = flash_status_check(addr, CONFIG_SYS_FLASH_BUFFER_WRITE_TOUT,
- "buffer write");
- }
- *addr = 0x00FF00FF; /* restore read mode */
- *addr = 0x00500050; /* clear status */
- return retcode;
-}
-#endif /* CONFIG_SYS_USE_FLASH_BUFFER_WRITE */
-
-/*-----------------------------------------------------------------------
- */
diff --git a/board/lwmon/lwmon.c b/board/lwmon/lwmon.c
deleted file mode 100644
index 225b1ef..0000000
--- a/board/lwmon/lwmon.c
+++ /dev/null
@@ -1,1071 +0,0 @@
-/***********************************************************************
- *
-M* Modul: lwmon.c
-M*
-M* Content: LWMON specific U-Boot commands.
- *
- * (C) Copyright 2001, 2002
- * DENX Software Engineering
- * Wolfgang Denk, wd at denx.de
- *
-D* Design: wd at denx.de
-C* Coding: wd at denx.de
-V* Verification: dzu at denx.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- ***********************************************************************/
-
-/*---------------------------- Headerfiles ----------------------------*/
-#include <common.h>
-#include <mpc8xx.h>
-#include <commproc.h>
-#include <i2c.h>
-#include <command.h>
-#include <malloc.h>
-#include <post.h>
-#include <serial.h>
-
-#include <linux/types.h>
-#include <linux/string.h> /* for strdup */
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*------------------------ Local prototypes ---------------------------*/
-static long int dram_size (long int, long int *, long int);
-static void kbd_init (void);
-static int compare_magic (uchar *kbd_data, uchar *str);
-
-
-/*--------------------- Local macros and constants --------------------*/
-#define _NOT_USED_ 0xFFFFFFFF
-
-#ifdef CONFIG_MODEM_SUPPORT
-static int key_pressed(void);
-extern void disable_putc(void);
-#endif /* CONFIG_MODEM_SUPPORT */
-
-/*
- * 66 MHz SDRAM access using UPM A
- */
-const uint sdram_table[] =
-{
-#if defined(CONFIG_SYS_MEMORY_75) || defined(CONFIG_SYS_MEMORY_8E)
- /*
- * Single Read. (Offset 0 in UPM RAM)
- */
- 0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00,
- 0x1FF5FC47, /* last */
- /*
- * SDRAM Initialization (offset 5 in UPM RAM)
- *
- * This is no UPM entry point. The following definition uses
- * the remaining space to establish an initialization
- * sequence, which is executed by a RUN command.
- *
- */
- 0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
- /*
- * Burst Read. (Offset 8 in UPM RAM)
- */
- 0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
- 0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Single Write. (Offset 18 in UPM RAM)
- */
- 0x1F2DFC04, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Burst Write. (Offset 20 in UPM RAM)
- */
- 0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
- 0xF0AFFC00, 0xE1BAFC04, 0x01FF5FC47, /* last */
- _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Refresh (Offset 30 in UPM RAM)
- */
- 0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
- 0xFFFFFC84, 0xFFFFFC07, /* last */
- _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Exception. (Offset 3c in UPM RAM)
- */
- 0x7FFFFC07, /* last */
- 0xFFFFFCFF, 0xFFFFFCFF, 0xFFFFFCFF,
-#endif
-#ifdef CONFIG_SYS_MEMORY_7E
- /*
- * Single Read. (Offset 0 in UPM RAM)
- */
- 0x0E2DBC04, 0x11AF7C04, 0xEFBAFC00, 0x1FF5FC47, /* last */
- _NOT_USED_,
- /*
- * SDRAM Initialization (offset 5 in UPM RAM)
- *
- * This is no UPM entry point. The following definition uses
- * the remaining space to establish an initialization
- * sequence, which is executed by a RUN command.
- *
- */
- 0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
- /*
- * Burst Read. (Offset 8 in UPM RAM)
- */
- 0x0E2DBC04, 0x10AF7C04, 0xF0AFFC00, 0xF0AFFC00,
- 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
- _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Single Write. (Offset 18 in UPM RAM)
- */
- 0x0E29BC04, 0x01B27C04, 0x1FF5FC47, /* last */
- _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Burst Write. (Offset 20 in UPM RAM)
- */
- 0x0E29BC04, 0x10A77C00, 0xF0AFFC00, 0xF0AFFC00,
- 0xE1BAFC04, 0x1FF5FC47, /* last */
- _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Refresh (Offset 30 in UPM RAM)
- */
- 0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
- 0xFFFFFC84, 0xFFFFFC07, /* last */
- _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Exception. (Offset 3c in UPM RAM)
- */
- 0x7FFFFC07, /* last */
- 0xFFFFFCFF, 0xFFFFFCFF, 0xFFFFFCFF,
-#endif
-};
-
-/*
- * Check Board Identity:
- *
- */
-
-/***********************************************************************
-F* Function: int checkboard (void) P*A*Z*
- *
-P* Parameters: none
-P*
-P* Returnvalue: int - 0 is always returned
- *
-Z* Intention: This function is the checkboard() method implementation
-Z* for the lwmon board. Only a standard message is printed.
- *
-D* Design: wd at denx.de
-C* Coding: wd at denx.de
-V* Verification: dzu at denx.de
- ***********************************************************************/
-int checkboard (void)
-{
- puts ("Board: LICCON Konsole LCD3\n");
- return (0);
-}
-
-/***********************************************************************
-F* Function: phys_size_t initdram (int board_type) P*A*Z*
- *
-P* Parameters: int board_type
-P* - Usually type of the board - ignored here.
-P*
-P* Returnvalue: long int
-P* - Size of initialized memory
- *
-Z* Intention: This function is the initdram() method implementation
-Z* for the lwmon board.
-Z* The memory controller is initialized to access the
-Z* DRAM.
- *
-D* Design: wd at denx.de
-C* Coding: wd at denx.de
-V* Verification: dzu at denx.de
- ***********************************************************************/
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immr->im_memctl;
- long int size_b0;
- long int size8, size9;
- int i;
-
- /*
- * Configure UPMA for SDRAM
- */
- upmconfig (UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
-
- memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-
- /* burst length=4, burst type=sequential, CAS latency=2 */
- memctl->memc_mar = CONFIG_SYS_MAR;
-
- /*
- * Map controller bank 3 to the SDRAM bank at preliminary address.
- */
- memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
- memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
-
- /* initialize memory address register */
- memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; /* refresh not enabled yet */
-
- /* mode initialization (offset 5) */
- udelay (200); /* 0x80006105 */
- memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x05);
-
- /* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
- udelay (1); /* 0x80006130 */
- memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30);
- udelay (1); /* 0x80006130 */
- memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30);
-
- udelay (1); /* 0x80006106 */
- memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x06);
-
- memctl->memc_mamr |= MAMR_PTAE; /* refresh enabled */
-
- udelay (200);
-
- /* Need at least 10 DRAM accesses to stabilize */
- for (i = 0; i < 10; ++i) {
- volatile unsigned long *addr =
- (volatile unsigned long *) SDRAM_BASE3_PRELIM;
- unsigned long val;
-
- val = *(addr + i);
- *(addr + i) = val;
- }
-
- /*
- * Check Bank 0 Memory Size for re-configuration
- *
- * try 8 column mode
- */
- size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
-
- udelay (1000);
-
- /*
- * try 9 column mode
- */
- size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
-
- if (size8 < size9) { /* leave configuration@9 columns */
- size_b0 = size9;
- memctl->memc_mamr = CONFIG_SYS_MAMR_9COL | MAMR_PTAE;
- udelay (500);
- } else { /* back to 8 columns */
- size_b0 = size8;
- memctl->memc_mamr = CONFIG_SYS_MAMR_8COL | MAMR_PTAE;
- udelay (500);
- }
-
- /*
- * Final mapping:
- */
-
- memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) |
- OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING;
- memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
- udelay (1000);
-
- return (size_b0);
-}
-
-/***********************************************************************
-F* Function: static long int dram_size (long int mamr_value,
-F* long int *base,
-F* long int maxsize) P*A*Z*
- *
-P* Parameters: long int mamr_value
-P* - Value for MAMR for the test
-P* long int *base
-P* - Base address for the test
-P* long int maxsize
-P* - Maximum size to test for
-P*
-P* Returnvalue: long int
-P* - Size of probed memory
- *
-Z* Intention: Check memory range for valid RAM. A simple memory test
-Z* determines the actually available RAM size between
-Z* addresses `base' and `base + maxsize'. Some (not all)
-Z* hardware errors are detected:
-Z* - short between address lines
-Z* - short between data lines
- *
-D* Design: wd at denx.de
-C* Coding: wd at denx.de
-V* Verification: dzu at denx.de
- ***********************************************************************/
-static long int dram_size (long int mamr_value, long int *base, long int maxsize)
-{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immr->im_memctl;
-
- memctl->memc_mamr = mamr_value;
-
- return (get_ram_size(base, maxsize));
-}
-
-/* ------------------------------------------------------------------------- */
-
-#ifndef PB_ENET_TENA
-# define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
-#endif
-
-/***********************************************************************
-F* Function: int board_early_init_f (void) P*A*Z*
- *
-P* Parameters: none
-P*
-P* Returnvalue: int
-P* - 0 is always returned.
- *
-Z* Intention: This function is the board_early_init_f() method implementation
-Z* for the lwmon board.
-Z* Disable Ethernet TENA on Port B.
- *
-D* Design: wd at denx.de
-C* Coding: wd at denx.de
-V* Verification: dzu at denx.de
- ***********************************************************************/
-int board_early_init_f (void)
-{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
-
- /* Disable Ethernet TENA on Port B
- * Necessary because of pull up in COM3 port.
- *
- * This is just a preliminary fix, intended to turn off TENA
- * as soon as possible to avoid noise on the network. Once
- * I2C is running we will make sure the interface is
- * correctly initialized.
- */
- immr->im_cpm.cp_pbpar &= ~PB_ENET_TENA;
- immr->im_cpm.cp_pbodr &= ~PB_ENET_TENA;
- immr->im_cpm.cp_pbdat &= ~PB_ENET_TENA; /* set to 0 = disabled */
- immr->im_cpm.cp_pbdir |= PB_ENET_TENA;
-
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/***********************************************************************
-F* Function: void reset_phy (void) P*A*Z*
- *
-P* Parameters: none
-P*
-P* Returnvalue: none
- *
-Z* Intention: Reset the PHY. In the lwmon case we do this by the
-Z* signaling the PIC I/O expander.
- *
-D* Design: wd at denx.de
-C* Coding: wd at denx.de
-V* Verification: dzu at denx.de
- ***********************************************************************/
-void reset_phy (void)
-{
- uchar c;
-
-#ifdef DEBUG
- printf ("### Switch on Ethernet for SCC2 ###\n");
-#endif
- c = pic_read (0x61);
-#ifdef DEBUG
- printf ("Old PIC read: reg_61 = 0x%02x\n", c);
-#endif
- c |= 0x40; /* disable COM3 */
- c &= ~0x80; /* enable Ethernet */
- pic_write (0x61, c);
-#ifdef DEBUG
- c = pic_read (0x61);
- printf ("New PIC read: reg_61 = 0x%02x\n", c);
-#endif
- udelay (1000);
-}
-
-
-/*------------------------- Keyboard controller -----------------------*/
-/* command codes */
-#define KEYBD_CMD_READ_KEYS 0x01
-#define KEYBD_CMD_READ_VERSION 0x02
-#define KEYBD_CMD_READ_STATUS 0x03
-#define KEYBD_CMD_RESET_ERRORS 0x10
-
-/* status codes */
-#define KEYBD_STATUS_MASK 0x3F
-#define KEYBD_STATUS_H_RESET 0x20
-#define KEYBD_STATUS_BROWNOUT 0x10
-#define KEYBD_STATUS_WD_RESET 0x08
-#define KEYBD_STATUS_OVERLOAD 0x04
-#define KEYBD_STATUS_ILLEGAL_WR 0x02
-#define KEYBD_STATUS_ILLEGAL_RD 0x01
-
-/* Number of bytes returned from Keyboard Controller */
-#define KEYBD_VERSIONLEN 2 /* version information */
-#define KEYBD_DATALEN 9 /* normal key scan data */
-
-/* maximum number of "magic" key codes that can be assigned */
-
-static uchar kbd_addr = CONFIG_SYS_I2C_KEYBD_ADDR;
-
-static uchar *key_match (uchar *);
-
-#define KEYBD_SET_DEBUGMODE '#' /* Magic key to enable debug output */
-
-/***********************************************************************
-F* Function: int board_postclk_init (void) P*A*Z*
- *
-P* Parameters: none
-P*
-P* Returnvalue: int
-P* - 0 is always returned.
- *
-Z* Intention: This function is the board_postclk_init() method implementation
-Z* for the lwmon board.
- *
- ***********************************************************************/
-int board_postclk_init (void)
-{
- kbd_init();
-
-#ifdef CONFIG_MODEM_SUPPORT
- if (key_pressed()) {
- disable_putc(); /* modem doesn't understand banner etc */
- gd->do_mdm_init = 1;
- }
-#endif
-
- return (0);
-}
-
-struct serial_device * default_serial_console (void)
-{
- return gd->do_mdm_init ? &serial_scc_device : &serial_smc_device;
-}
-
-static void kbd_init (void)
-{
- uchar kbd_data[KEYBD_DATALEN];
- uchar tmp_data[KEYBD_DATALEN];
- uchar val, errcd;
- int i;
-
- i2c_set_bus_num(0);
-
- gd->arch.kbd_status = 0;
-
- /* Forced by PIC. Delays <= 175us loose */
- udelay(1000);
-
- /* Read initial keyboard error code */
- val = KEYBD_CMD_READ_STATUS;
- i2c_write (kbd_addr, 0, 0, &val, 1);
- i2c_read (kbd_addr, 0, 0, &errcd, 1);
- /* clear unused bits */
- errcd &= KEYBD_STATUS_MASK;
- /* clear "irrelevant" bits. Recommended by Martin Rajek, LWN */
- errcd &= ~(KEYBD_STATUS_H_RESET|KEYBD_STATUS_BROWNOUT);
- if (errcd) {
- gd->arch.kbd_status |= errcd << 8;
- }
- /* Reset error code and verify */
- val = KEYBD_CMD_RESET_ERRORS;
- i2c_write (kbd_addr, 0, 0, &val, 1);
- udelay(1000); /* delay NEEDED by keyboard PIC !!! */
-
- val = KEYBD_CMD_READ_STATUS;
- i2c_write (kbd_addr, 0, 0, &val, 1);
- i2c_read (kbd_addr, 0, 0, &val, 1);
-
- val &= KEYBD_STATUS_MASK; /* clear unused bits */
- if (val) { /* permanent error, report it */
- gd->arch.kbd_status |= val;
- return;
- }
-
- /*
- * Read current keyboard state.
- *
- * After the error reset it may take some time before the
- * keyboard PIC picks up a valid keyboard scan - the total
- * scan time is approx. 1.6 ms (information by Martin Rajek,
- * 28 Sep 2002). We read a couple of times for the keyboard
- * to stabilize, using a big enough delay.
- * 10 times should be enough. If the data is still changing,
- * we use what we get :-(
- */
-
- memset (tmp_data, 0xFF, KEYBD_DATALEN); /* impossible value */
- for (i=0; i<10; ++i) {
- val = KEYBD_CMD_READ_KEYS;
- i2c_write (kbd_addr, 0, 0, &val, 1);
- i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
-
- if (memcmp(kbd_data, tmp_data, KEYBD_DATALEN) == 0) {
- /* consistent state, done */
- break;
- }
- /* remeber last state, delay, and retry */
- memcpy (tmp_data, kbd_data, KEYBD_DATALEN);
- udelay (5000);
- }
-}
-
-/***********************************************************************
-F* Function: int misc_init_r (void) P*A*Z*
- *
-P* Parameters: none
-P*
-P* Returnvalue: int
-P* - 0 is always returned, even in the case of a keyboard
-P* error.
- *
-Z* Intention: This function is the misc_init_r() method implementation
-Z* for the lwmon board.
-Z* The keyboard controller is initialized and the result
-Z* of a read copied to the environment variable "keybd".
-Z* If KEYBD_SET_DEBUGMODE is defined, a check is made for
-Z* this key, and if found display to the LCD will be enabled.
-Z* The keys in "keybd" are checked against the magic
-Z* keycommands defined in the environment.
-Z* See also key_match().
- *
-D* Design: wd at denx.de
-C* Coding: wd at denx.de
-V* Verification: dzu@denx.de
- ***********************************************************************/
-int misc_init_r (void)
-{
- uchar kbd_data[KEYBD_DATALEN];
- char keybd_env[2 * KEYBD_DATALEN + 1];
- uchar kbd_init_status = gd->arch.kbd_status >> 8;
- uchar kbd_status = gd->arch.kbd_status;
- uchar val;
- char *str;
- int i;
-
- if (kbd_init_status) {
- printf ("KEYBD: Error %02X\n", kbd_init_status);
- }
- if (kbd_status) { /* permanent error, report it */
- printf ("*** Keyboard error code %02X ***\n", kbd_status);
- sprintf (keybd_env, "%02X", kbd_status);
- setenv ("keybd", keybd_env);
- return 0;
- }
-
- /*
- * Now we know that we have a working keyboard, so disable
- * all output to the LCD except when a key press is detected.
- */
-
- if ((console_assign (stdout, "serial") < 0) ||
- (console_assign (stderr, "serial") < 0)) {
- printf ("Can't assign serial port as output device\n");
- }
-
- /* Read Version */
- val = KEYBD_CMD_READ_VERSION;
- i2c_write (kbd_addr, 0, 0, &val, 1);
- i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_VERSIONLEN);
- printf ("KEYBD: Version %d.%d\n", kbd_data[0], kbd_data[1]);
-
- /* Read current keyboard state */
- val = KEYBD_CMD_READ_KEYS;
- i2c_write (kbd_addr, 0, 0, &val, 1);
- i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
-
- for (i = 0; i < KEYBD_DATALEN; ++i) {
- sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
- }
- setenv ("keybd", keybd_env);
-
- str = strdup ((char *)key_match (kbd_data)); /* decode keys */
-#ifdef KEYBD_SET_DEBUGMODE
- if (kbd_data[0] == KEYBD_SET_DEBUGMODE) { /* set debug mode */
- if ((console_assign (stdout, "lcd") < 0) ||
- (console_assign (stderr, "lcd") < 0)) {
- printf ("Can't assign LCD display as output device\n");
- }
- }
-#endif /* KEYBD_SET_DEBUGMODE */
-#ifdef CONFIG_PREBOOT /* automatically configure "preboot" command on key match */
- setenv ("preboot", str); /* set or delete definition */
-#endif /* CONFIG_PREBOOT */
- if (str != NULL) {
- free (str);
- }
- return (0);
-}
-
-#ifdef CONFIG_PREBOOT
-
-static uchar kbd_magic_prefix[] = "key_magic";
-static uchar kbd_command_prefix[] = "key_cmd";
-
-static int compare_magic (uchar *kbd_data, uchar *str)
-{
- uchar compare[KEYBD_DATALEN-1];
- char *nxt;
- int i;
-
- /* Don't include modifier byte */
- memcpy (compare, kbd_data+1, KEYBD_DATALEN-1);
-
- for (; str != NULL; str = (*nxt) ? (uchar *)(nxt+1) : (uchar *)nxt) {
- uchar c;
- int k;
-
- c = (uchar) simple_strtoul ((char *)str, (char **) (&nxt), 16);
-
- if (str == (uchar *)nxt) { /* invalid character */
- break;
- }
-
- /*
- * Check if this key matches the input.
- * Set matches to zero, so they match only once
- * and we can find duplicates or extra keys
- */
- for (k = 0; k < sizeof(compare); ++k) {
- if (compare[k] == '\0') /* only non-zero entries */
- continue;
- if (c == compare[k]) { /* found matching key */
- compare[k] = '\0';
- break;
- }
- }
- if (k == sizeof(compare)) {
- return -1; /* unmatched key */
- }
- }
-
- /*
- * A full match leaves no keys in the `compare' array,
- */
- for (i = 0; i < sizeof(compare); ++i) {
- if (compare[i])
- {
- return -1;
- }
- }
-
- return 0;
-}
-
-/***********************************************************************
-F* Function: static uchar *key_match (uchar *kbd_data) P*A*Z*
- *
-P* Parameters: uchar *kbd_data
-P* - The keys to match against our magic definitions
-P*
-P* Returnvalue: uchar *
-P* - != NULL: Pointer to the corresponding command(s)
-P* NULL: No magic is about to happen
- *
-Z* Intention: Check if pressed key(s) match magic sequence,
-Z* and return the command string associated with that key(s).
-Z*
-Z* If no key press was decoded, NULL is returned.
-Z*
-Z* Note: the first character of the argument will be
-Z* overwritten with the "magic charcter code" of the
-Z* decoded key(s), or '\0'.
-Z*
-Z* Note: the string points to static environment data
-Z* and must be saved before you call any function that
-Z* modifies the environment.
- *
-D* Design: wd at denx.de
-C* Coding: wd at denx.de
-V* Verification: dzu@denx.de
- ***********************************************************************/
-static uchar *key_match (uchar *kbd_data)
-{
- char magic[sizeof (kbd_magic_prefix) + 1];
- uchar *suffix;
- char *kbd_magic_keys;
-
- /*
- * The following string defines the characters that can pe appended
- * to "key_magic" to form the names of environment variables that
- * hold "magic" key codes, i. e. such key codes that can cause
- * pre-boot actions. If the string is empty (""), then only
- * "key_magic" is checked (old behaviour); the string "125" causes
- * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
- */
- if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
- kbd_magic_keys = "";
-
- /* loop over all magic keys;
- * use '\0' suffix in case of empty string
- */
- for (suffix=(uchar *)kbd_magic_keys; *suffix || suffix==(uchar *)kbd_magic_keys; ++suffix) {
- sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
-#if 0
- printf ("### Check magic \"%s\"\n", magic);
-#endif
- if (compare_magic(kbd_data, (uchar *)getenv(magic)) == 0) {
- char cmd_name[sizeof (kbd_command_prefix) + 1];
- char *cmd;
-
- sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
-
- cmd = getenv (cmd_name);
-#if 0
- printf ("### Set PREBOOT to $(%s): \"%s\"\n",
- cmd_name, cmd ? cmd : "<<NULL>>");
-#endif
- *kbd_data = *suffix;
- return ((uchar *)cmd);
- }
- }
-#if 0
- printf ("### Delete PREBOOT\n");
-#endif
- *kbd_data = '\0';
- return (NULL);
-}
-#endif /* CONFIG_PREBOOT */
-
-#ifdef CONFIG_LCD_INFO
-#include <lcd.h>
-#include <version.h>
-#include <timestamp.h>
-
-void lcd_show_board_info(void)
-{
- char temp[32];
-
- lcd_printf ("%s (%s - %s)\n", U_BOOT_VERSION, U_BOOT_DATE, U_BOOT_TIME);
- lcd_printf ("(C) 2008 DENX Software Engineering GmbH\n");
- lcd_printf (" Wolfgang DENK, wd at denx.de\n");
-#ifdef CONFIG_LCD_INFO_BELOW_LOGO
- lcd_printf ("MPC823 CPU at %s MHz\n",
- strmhz(temp, gd->cpu_clk));
- lcd_printf (" %ld MB RAM, %ld MB Flash\n",
- gd->ram_size >> 20,
- gd->bd->bi_flashsize >> 20 );
-#else
- /* leave one blank line */
- lcd_printf ("\nMPC823 CPU at %s MHz, %ld MB RAM, %ld MB Flash\n",
- strmhz(temp, gd->cpu_clk),
- gd->ram_size >> 20,
- gd->bd->bi_flashsize >> 20 );
-#endif /* CONFIG_LCD_INFO_BELOW_LOGO */
-}
-#endif /* CONFIG_LCD_INFO */
-
-/*---------------Board Special Commands: PIC read/write ---------------*/
-
-#if defined(CONFIG_CMD_BSP)
-/***********************************************************************
-F* Function: int do_pic (cmd_tbl_t *cmdtp, int flag,
-F* int argc, char * const argv[]) P*A*Z*
- *
-P* Parameters: cmd_tbl_t *cmdtp
-P* - Pointer to our command table entry
-P* int flag
-P* - If the CMD_FLAG_REPEAT bit is set, then this call is
-P* a repetition
-P* int argc
-P* - Argument count
-P* char * const argv[]
-P* - Array of the actual arguments
-P*
-P* Returnvalue: int
-P* - 0 The command was handled successfully
-P* 1 An error occurred
- *
-Z* Intention: Implement the "pic [read|write]" commands.
-Z* The read subcommand takes one argument, the register,
-Z* whereas the write command takes two, the register and
-Z* the new value.
- *
-D* Design: wd at denx.de
-C* Coding: wd at denx.de
-V* Verification: dzu at denx.de
- ***********************************************************************/
-int do_pic (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- uchar reg, val;
-
- switch (argc) {
- case 3: /* PIC read reg */
- if (strcmp (argv[1], "read") != 0)
- break;
-
- reg = simple_strtoul (argv[2], NULL, 16);
-
- printf ("PIC read: reg %02x: %02x\n\n", reg, pic_read (reg));
-
- return 0;
- case 4: /* PIC write reg val */
- if (strcmp (argv[1], "write") != 0)
- break;
-
- reg = simple_strtoul (argv[2], NULL, 16);
- val = simple_strtoul (argv[3], NULL, 16);
-
- printf ("PIC write: reg %02x val 0x%02x: %02x => ",
- reg, val, pic_read (reg));
- pic_write (reg, val);
- printf ("%02x\n\n", pic_read (reg));
- return 0;
- default:
- break;
- }
- return cmd_usage(cmdtp);
-}
-U_BOOT_CMD(
- pic, 4, 1, do_pic,
- "read and write PIC registers",
- "read reg - read PIC register `reg'\n"
- "pic write reg val - write value `val' to PIC register `reg'"
-);
-
-/***********************************************************************
-F* Function: int do_kbd (cmd_tbl_t *cmdtp, int flag,
-F* int argc, char * const argv[]) P*A*Z*
- *
-P* Parameters: cmd_tbl_t *cmdtp
-P* - Pointer to our command table entry
-P* int flag
-P* - If the CMD_FLAG_REPEAT bit is set, then this call is
-P* a repetition
-P* int argc
-P* - Argument count
-P* char * const argv[]
-P* - Array of the actual arguments
-P*
-P* Returnvalue: int
-P* - 0 is always returned.
- *
-Z* Intention: Implement the "kbd" command.
-Z* The keyboard status is read. The result is printed on
-Z* the console and written into the "keybd" environment
-Z* variable.
- *
-D* Design: wd at denx.de
-C* Coding: wd at denx.de
-V* Verification: dzu at denx.de
- ***********************************************************************/
-int do_kbd (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- uchar kbd_data[KEYBD_DATALEN];
- char keybd_env[2 * KEYBD_DATALEN + 1];
- uchar val;
- int i;
-
-#if 0 /* Done in kbd_init */
- i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-#endif
-
- /* Read keys */
- val = KEYBD_CMD_READ_KEYS;
- i2c_write (kbd_addr, 0, 0, &val, 1);
- i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
-
- puts ("Keys:");
- for (i = 0; i < KEYBD_DATALEN; ++i) {
- sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
- printf (" %02x", kbd_data[i]);
- }
- putc ('\n');
- setenv ("keybd", keybd_env);
- return 0;
-}
-
-U_BOOT_CMD(
- kbd, 1, 1, do_kbd,
- "read keyboard status",
- ""
-);
-
-/* Read and set LSB switch */
-#define CONFIG_SYS_PC_TXD1_ENA 0x0008 /* PC.12 */
-
-/***********************************************************************
-F* Function: int do_lsb (cmd_tbl_t *cmdtp, int flag,
-F* int argc, char * const argv[]) P*A*Z*
- *
-P* Parameters: cmd_tbl_t *cmdtp
-P* - Pointer to our command table entry
-P* int flag
-P* - If the CMD_FLAG_REPEAT bit is set, then this call is
-P* a repetition
-P* int argc
-P* - Argument count
-P* char * const argv[]
-P* - Array of the actual arguments
-P*
-P* Returnvalue: int
-P* - 0 The command was handled successfully
-P* 1 An error occurred
- *
-Z* Intention: Implement the "lsb [on|off]" commands.
-Z* The lsb is switched according to the first parameter by
-Z* by signaling the PIC I/O expander.
-Z* Called with no arguments, the current setting is
-Z* printed.
- *
-D* Design: wd at denx.de
-C* Coding: wd at denx.de
-V* Verification: dzu@denx.de
- ***********************************************************************/
-int do_lsb (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- uchar val;
- immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
-
- switch (argc) {
- case 1: /* lsb - print setting */
- val = pic_read (0x60);
- printf ("LSB is o%s\n", (val & 0x20) ? "n" : "ff");
- return 0;
- case 2: /* lsb on or lsb off - set switch */
- val = pic_read (0x60);
-
- if (strcmp (argv[1], "on") == 0) {
- val |= 0x20;
- immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_TXD1_ENA);
- immr->im_ioport.iop_pcdat |= CONFIG_SYS_PC_TXD1_ENA;
- immr->im_ioport.iop_pcdir |= CONFIG_SYS_PC_TXD1_ENA;
- } else if (strcmp (argv[1], "off") == 0) {
- val &= ~0x20;
- immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_TXD1_ENA);
- immr->im_ioport.iop_pcdat &= ~(CONFIG_SYS_PC_TXD1_ENA);
- immr->im_ioport.iop_pcdir |= CONFIG_SYS_PC_TXD1_ENA;
- } else {
- break;
- }
- pic_write (0x60, val);
- return 0;
- default:
- break;
- }
- return cmd_usage(cmdtp);
-}
-
-U_BOOT_CMD(
- lsb, 2, 1, do_lsb,
- "check and set LSB switch",
- "on - switch LSB on\n"
- "lsb off - switch LSB off\n"
- "lsb - print current setting"
-);
-
-#endif
-
-/*----------------------------- Utilities -----------------------------*/
-/***********************************************************************
-F* Function: uchar pic_read (uchar reg) P*A*Z*
- *
-P* Parameters: uchar reg
-P* - Register to read
-P*
-P* Returnvalue: uchar
-P* - Value read from register
- *
-Z* Intention: Read a register from the PIC I/O expander.
- *
-D* Design: wd at denx.de
-C* Coding: wd at denx.de
-V* Verification: dzu at denx.de
- ***********************************************************************/
-uchar pic_read (uchar reg)
-{
- return (i2c_reg_read (CONFIG_SYS_I2C_PICIO_ADDR, reg));
-}
-
-/***********************************************************************
-F* Function: void pic_write (uchar reg, uchar val) P*A*Z*
- *
-P* Parameters: uchar reg
-P* - Register to read
-P* uchar val
-P* - Value to write
-P*
-P* Returnvalue: none
- *
-Z* Intention: Write to a register on the PIC I/O expander.
- *
-D* Design: wd at denx.de
-C* Coding: wd at denx.de
-V* Verification: dzu at denx.de
- ***********************************************************************/
-void pic_write (uchar reg, uchar val)
-{
- i2c_reg_write (CONFIG_SYS_I2C_PICIO_ADDR, reg, val);
-}
-
-/*---------------------- Board Control Functions ----------------------*/
-/***********************************************************************
-F* Function: void board_poweroff (void) P*A*Z*
- *
-P* Parameters: none
-P*
-P* Returnvalue: none
- *
-Z* Intention: Turn off the battery power and loop endless, so this
-Z* should better be the last function you call...
- *
-D* Design: wd at denx.de
-C* Coding: wd at denx.de
-V* Verification: dzu at denx.de
- ***********************************************************************/
-void board_poweroff (void)
-{
- /* Turn battery off */
- ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat &= ~(1 << (31 - 13));
-
- while (1);
-}
-
-#ifdef CONFIG_MODEM_SUPPORT
-static int key_pressed(void)
-{
- uchar kbd_data[KEYBD_DATALEN];
- uchar val;
-
- /* Read keys */
- val = KEYBD_CMD_READ_KEYS;
- i2c_write (kbd_addr, 0, 0, &val, 1);
- i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
-
- return (compare_magic(kbd_data, (uchar *)CONFIG_MODEM_KEY_MAGIC) == 0);
-}
-#endif /* CONFIG_MODEM_SUPPORT */
-
-#ifdef CONFIG_POST
-/*
- * Returns 1 if keys pressed to start the power-on long-running tests
- * Called from board_init_f().
- */
-int post_hotkeys_pressed(void)
-{
- uchar kbd_data[KEYBD_DATALEN];
- uchar val;
-
- /* Read keys */
- val = KEYBD_CMD_READ_KEYS;
- i2c_write (kbd_addr, 0, 0, &val, 1);
- i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
-
- return (compare_magic(kbd_data, (uchar *)CONFIG_POST_KEY_MAGIC) == 0);
-}
-#endif
diff --git a/board/lwmon/pcmcia.c b/board/lwmon/pcmcia.c
deleted file mode 100644
index b9894cf..0000000
--- a/board/lwmon/pcmcia.c
+++ /dev/null
@@ -1,234 +0,0 @@
-#include <common.h>
-#include <mpc8xx.h>
-#include <pcmcia.h>
-#include <i2c.h>
-
-#undef CONFIG_PCMCIA
-
-#if defined(CONFIG_CMD_PCMCIA)
-#define CONFIG_PCMCIA
-#endif
-
-#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
-#define CONFIG_PCMCIA
-#endif
-
-#ifdef CONFIG_PCMCIA
-
-#define PCMCIA_BOARD_MSG "LWMON"
-
-/* #define's for MAX1604 Power Switch */
-#define MAX1604_OP_SUS 0x80
-#define MAX1604_VCCBON 0x40
-#define MAX1604_VCC_35 0x20
-#define MAX1604_VCCBHIZ 0x10
-#define MAX1604_VPPBON 0x08
-#define MAX1604_VPPBPBPGM 0x04
-#define MAX1604_VPPBHIZ 0x02
-/* reserved 0x01 */
-
-int pcmcia_hardware_enable(int slot)
-{
- volatile pcmconf8xx_t *pcmp;
- volatile sysconf8xx_t *sysp;
- uint reg, mask;
- uchar val;
-
-
- debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
-
- /* Switch on PCMCIA port in PIC register 0x60 */
- reg = pic_read (0x60);
- debug ("[%d] PIC read: reg_60 = 0x%02x\n", __LINE__, reg);
- reg &= ~0x10;
- /* reg |= 0x08; Vpp not needed */
- pic_write (0x60, reg);
-#ifdef DEBUG
- reg = pic_read (0x60);
- printf ("[%d] PIC read: reg_60 = 0x%02x\n", __LINE__, reg);
-#endif
- udelay(10000);
-
- sysp = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf));
- pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
-
- /*
- * Configure SIUMCR to enable PCMCIA port B
- * (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
- */
- sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */
-
- /* clear interrupt state, and disable interrupts */
- pcmp->pcmc_pscr = PCMCIA_MASK(_slot_);
- pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
-
- /*
- * Disable interrupts, DMA, and PCMCIA buffers
- * (isolate the interface) and assert RESET signal
- */
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = 0;
- reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
- udelay(500);
-
- /*
- * Make sure there is a card in the slot, then configure the interface.
- */
- udelay(10000);
- debug ("[%d] %s: PIPR(%p)=0x%x\n",
- __LINE__,__FUNCTION__,
- &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
- if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
- printf (" No Card found\n");
- return (1);
- }
-
- /*
- * Power On.
- */
- mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
- reg = pcmp->pcmc_pipr;
- debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
- reg,
- (reg&PCMCIA_VS1(slot))?"n":"ff",
- (reg&PCMCIA_VS2(slot))?"n":"ff");
- if ((reg & mask) == mask) {
- val = 0; /* VCCB3/5 = 0 ==> use Vx = 5.0 V */
- puts (" 5.0V card found: ");
- } else {
- val = MAX1604_VCC_35; /* VCCB3/5 = 1 ==> use Vy = 3.3 V */
- puts (" 3.3V card found: ");
- }
-
- /* switch VCC on */
- val |= MAX1604_OP_SUS | MAX1604_VCCBON;
- i2c_set_bus_num(0);
- i2c_write (CONFIG_SYS_I2C_POWER_A_ADDR, 0, 0, &val, 1);
-
- udelay(500000);
-
- debug ("Enable PCMCIA buffers and stop RESET\n");
- reg = PCMCIA_PGCRX(_slot_);
- reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
-
- udelay(250000); /* some cards need >150 ms to come up :-( */
-
- debug ("# hardware_enable done\n");
-
- return (0);
-}
-
-
-#if defined(CONFIG_CMD_PCMCIA)
-int pcmcia_hardware_disable(int slot)
-{
- volatile immap_t *immap;
- volatile pcmconf8xx_t *pcmp;
- u_long reg;
- uchar val;
-
- debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
-
- immap = (immap_t *)CONFIG_SYS_IMMR;
- pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
-
- /* remove all power, put output in high impedance state */
- val = MAX1604_VCCBHIZ | MAX1604_VPPBHIZ;
- i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
- i2c_write (CONFIG_SYS_I2C_POWER_A_ADDR, 0, 0, &val, 1);
-
- /* Configure PCMCIA General Control Register */
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = 0;
- reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
-
- /* Switch off PCMCIA port in PIC register 0x60 */
- reg = pic_read (0x60);
- debug ("[%d] PIC read: reg_60 = 0x%02x\n", __LINE__, reg);
- reg |= 0x10;
- reg &= ~0x08;
- pic_write (0x60, reg);
-#ifdef DEBUG
- reg = pic_read (0x60);
- printf ("[%d] PIC read: reg_60 = 0x%02x\n", __LINE__, reg);
-#endif
- udelay(10000);
-
- return (0);
-}
-#endif
-
-
-int pcmcia_voltage_set(int slot, int vcc, int vpp)
-{
- volatile pcmconf8xx_t *pcmp;
- u_long reg;
- uchar val;
-
- debug ("voltage_set: "
- PCMCIA_BOARD_MSG
- " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
- 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
-
- pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
- /*
- * Disable PCMCIA buffers (isolate the interface)
- * and assert RESET signal
- */
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = PCMCIA_PGCRX(_slot_);
- reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
- udelay(500);
-
- /*
- * Turn off all power (switch to high impedance)
- */
- debug ("PCMCIA power OFF\n");
- val = MAX1604_VCCBHIZ | MAX1604_VPPBHIZ;
- i2c_set_bus_num(0);
- i2c_write (CONFIG_SYS_I2C_POWER_A_ADDR, 0, 0, &val, 1);
-
- val = 0;
- switch(vcc) {
- case 0: break;
- case 33: val = MAX1604_VCC_35; break;
- case 50: break;
- default: goto done;
- }
-
- /* Checking supported voltages */
-
- debug ("PIPR: 0x%x --> %s\n",
- pcmp->pcmc_pipr,
- (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V");
-
- i2c_write (CONFIG_SYS_I2C_POWER_A_ADDR, 0, 0, &val, 1);
- if (val) {
- debug ("PCMCIA powered at %sV\n",
- (val & MAX1604_VCC_35) ? "3.3" : "5.0");
- } else {
- debug ("PCMCIA powered down\n");
- }
-
-done:
- debug ("Enable PCMCIA buffers and stop RESET\n");
- reg = PCMCIA_PGCRX(_slot_);
- reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
- udelay(500);
-
- debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
- slot+'A');
- return (0);
-}
-
-#endif /* CONFIG_PCMCIA */
diff --git a/board/lwmon/u-boot.lds.debug b/board/lwmon/u-boot.lds.debug
deleted file mode 100644
index 75a1337..0000000
--- a/board/lwmon/u-boot.lds.debug
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
- arch/powerpc/lib/extable.o (.text)
-
- . = env_offset;
- common/env_embedded.o(.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
diff --git a/configs/lwmon_defconfig b/configs/lwmon_defconfig
deleted file mode 100644
index 128ff5f..0000000
--- a/configs/lwmon_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_8xx=y
-CONFIG_TARGET_LWMON=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 6b391df..1f5ff8f 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+lwmon powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
NETVIA powerpc mpc8xx - - Pantelis Antoniou <panto@intracom.gr>
R360MPI powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
RRvision powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
diff --git a/drivers/pcmcia/mpc8xx_pcmcia.c b/drivers/pcmcia/mpc8xx_pcmcia.c
index ea88494..1b41e39 100644
--- a/drivers/pcmcia/mpc8xx_pcmcia.c
+++ b/drivers/pcmcia/mpc8xx_pcmcia.c
@@ -58,15 +58,9 @@ static const u_int m8xx_size_to_gray[M8XX_SIZES_NO] =
/* -------------------------------------------------------------------- */
-#if defined(CONFIG_LWMON)
-#define CONFIG_SYS_PCMCIA_TIMING ( PCMCIA_SHT(9) \
- | PCMCIA_SST(3) \
- | PCMCIA_SL(12))
-#else
#define CONFIG_SYS_PCMCIA_TIMING ( PCMCIA_SHT(2) \
| PCMCIA_SST(4) \
| PCMCIA_SL(9))
-#endif
/* -------------------------------------------------------------------- */
diff --git a/drivers/video/mpc8xx_lcd.c b/drivers/video/mpc8xx_lcd.c
index 336788f..50eed89 100644
--- a/drivers/video/mpc8xx_lcd.c
+++ b/drivers/video/mpc8xx_lcd.c
@@ -412,17 +412,6 @@ void lcd_enable (void)
/* Enable the LCD panel */
immr->im_siu_conf.sc_sdcr |= (1 << (31 - 25)); /* LAM = 1 */
lcdp->lcd_lccr |= LCCR_PON;
-
-#if defined(CONFIG_LWMON)
- { uchar c = pic_read (0x60);
-#if defined(CONFIG_LCD) && defined(CONFIG_LWMON) && (CONFIG_POST & CONFIG_SYS_POST_SYSMON)
- /* Enable LCD later in sysmon test, only if temperature is OK */
-#else
- c |= 0x07; /* Power on CCFL, Enable CCFL, Chip Enable LCD */
-#endif
- pic_write (0x60, c);
- }
-#endif /* CONFIG_LWMON */
}
/************************************************************************/
diff --git a/examples/standalone/test_burst.c b/examples/standalone/test_burst.c
index 4a16ffb..f2fdbf1 100644
--- a/examples/standalone/test_burst.c
+++ b/examples/standalone/test_burst.c
@@ -31,25 +31,6 @@
*/
#define TEST_FLASH_ADDR 0x40100000
-/* Define GPIO ports to signal start of burst transfers and errors */
-#ifdef CONFIG_LWMON
-/* Use PD.8 to signal start of burst transfers */
-#define GPIO1_DAT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat)
-#define GPIO1_BIT 0x0080
-/* Configure PD.8 as general purpose output */
-#define GPIO1_INIT \
- ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar &= ~GPIO1_BIT; \
- ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir |= GPIO1_BIT;
-/* Use PD.9 to signal error */
-#define GPIO2_DAT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat)
-#define GPIO2_BIT 0x0040
-/* Configure PD.9 as general purpose output */
-#define GPIO2_INIT \
- ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar &= ~GPIO2_BIT; \
- ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir |= GPIO2_BIT;
-#endif /* CONFIG_LWMON */
-
-
static void test_prepare (void);
static int test_burst_start (unsigned long size, unsigned long pattern);
static void test_map_8M (unsigned long paddr, unsigned long vaddr, int cached);
diff --git a/include/common.h b/include/common.h
index 46f07fe..bab77e6 100644
--- a/include/common.h
+++ b/include/common.h
@@ -421,10 +421,6 @@ int eeprom_probe (unsigned dev_addr, unsigned offset);
#endif
int eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt);
int eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt);
-#ifdef CONFIG_LWMON
-extern uchar pic_read (uchar reg);
-extern void pic_write (uchar reg, uchar val);
-#endif
/*
* Set this up regardless of board
diff --git a/include/commproc.h b/include/commproc.h
index 8de0d15..509d6e4 100644
--- a/include/commproc.h
+++ b/include/commproc.h
@@ -543,32 +543,6 @@ typedef struct scc_enet {
#endif /* CONFIG_IVMS8, CONFIG_IVML24 */
-/*** LWMON **********************************************************/
-
-#if defined(CONFIG_LWMON)
-/* Bits in parallel I/O port registers that have to be set/cleared
- * to configure the pins for SCC2 use.
- */
-#define PROFF_ENET PROFF_SCC2
-#define CPM_CR_ENET CPM_CR_CH_SCC2
-#define SCC_ENET 1
-#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
-#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
-#define PA_ENET_RCLK ((ushort)0x0800) /* PA 4 */
-#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
-
-#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
-
-#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
-#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
-
-/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK4) to
- * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
- */
-#define SICR_ENET_MASK ((uint)0x0000ff00)
-#define SICR_ENET_CLKRT ((uint)0x00003E00)
-#endif /* CONFIG_LWMON */
-
/*** KM8XX *********************************************************/
/* The KM8XX Service Module uses SCC3 for Ethernet */
diff --git a/include/configs/lwmon.h b/include/configs/lwmon.h
deleted file mode 100644
index f204587..0000000
--- a/include/configs/lwmon.h
+++ /dev/null
@@ -1,587 +0,0 @@
-/*
- * (C) Copyright 2001-2005
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* External logbuffer support */
-#define CONFIG_LOGBUFFER
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC823 1 /* This is a MPC823E CPU */
-#define CONFIG_LWMON 1 /* ...on a LWMON board */
-
-#define CONFIG_SYS_TEXT_BASE 0x40000000
-
-/* Default Ethernet MAC address */
-#define CONFIG_ETHADDR 00:11:B0:00:00:00
-
-/* The default Ethernet MAC address can be overwritten just once */
-#ifdef CONFIG_ETHADDR
-#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
-#endif
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */
-#define CONFIG_BOARD_POSTCLK_INIT 1 /* Call board_postclk_init() */
-#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */
-
-#define CONFIG_LCD 1 /* use LCD controller ... */
-#define CONFIG_MPC8XX_LCD
-#define CONFIG_HLD1045 1 /* ... with a HLD1045 display */
-
-#define CONFIG_LCD_LOGO 1 /* print our logo on the LCD */
-#define CONFIG_LCD_INFO 1 /* ... and some board info */
-#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/
-
-#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
-#define CONFIG_8xx_CONS_SCC2 1 /* Console is on SCC2 */
-
-#define CONFIG_BAUDRATE 115200 /* with watchdog >= 38400 needed */
-
-#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
-
-#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
-
-/* pre-boot commands */
-#define CONFIG_PREBOOT "setenv bootdelay 15"
-
-#undef CONFIG_BOOTARGS
-
-/* POST support */
-#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
- CONFIG_SYS_POST_WATCHDOG | \
- CONFIG_SYS_POST_RTC | \
- CONFIG_SYS_POST_MEMORY | \
- CONFIG_SYS_POST_CPU | \
- CONFIG_SYS_POST_UART | \
- CONFIG_SYS_POST_ETHER | \
- CONFIG_SYS_POST_I2C | \
- CONFIG_SYS_POST_SPI | \
- CONFIG_SYS_POST_USB | \
- CONFIG_SYS_POST_SPR | \
- CONFIG_SYS_POST_SYSMON)
-
-/*
- * Keyboard commands:
- * # = 0x28 = ENTER : enable bootmessages on LCD
- * 2 = 0x3A+0x3C = F1 + F3 : enable update mode
- * 3 = 0x3C+0x3F = F3 + F6 : enable test mode
- */
-
-#define CONFIG_BOOTCOMMAND "source 40040000;saveenv"
-
-/* "gatewayip=10.8.211.250\0" \ */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "kernel_addr=40080000\0" \
- "ramdisk_addr=40280000\0" \
- "netmask=255.255.192.0\0" \
- "serverip=10.8.2.101\0" \
- "ipaddr=10.8.57.0\0" \
- "magic_keys=#23\0" \
- "key_magic#=28\0" \
- "key_cmd#=setenv addfb setenv 'bootargs $bootargs console=tty0'\0" \
- "key_magic2=3A+3C\0" \
- "key_cmd2=echo *** Entering Update Mode ***;" \
- "if fatload ide 0:3 10000 update.scr;" \
- "then source 10000;" \
- "else echo *** UPDATE FAILED ***;" \
- "fi\0" \
- "key_magic3=3C+3F\0" \
- "key_cmd3=echo *** Entering Test Mode ***;" \
- "setenv add_misc 'setenv bootargs $bootargs testmode'\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addfb=setenv bootargs $bootargs console=ttyS1,$baudrate\0" \
- "addip=setenv bootargs $bootargs " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \
- "panic=1\0" \
- "add_wdt=setenv bootargs $bootargs $wdt_args\0" \
- "add_misc=setenv bootargs $bootargs runmode\0" \
- "flash_nfs=run nfsargs addip add_wdt addfb add_misc;" \
- "bootm $kernel_addr\0" \
- "flash_self=run ramargs addip add_wdt addfb add_misc;" \
- "bootm $kernel_addr $ramdisk_addr\0" \
- "net_nfs=tftp 100000 /tftpboot/uImage.lwmon;" \
- "run nfsargs addip add_wdt addfb;bootm\0" \
- "rootpath=/opt/eldk/ppc_8xx\0" \
- "load=tftp 100000 /tftpboot/u-boot.bin\0" \
- "update=protect off 1:0;era 1:0;cp.b 100000 40000000 $filesize\0" \
- "wdt_args=wdt_8xx=off\0" \
- "verify=no"
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-#define CONFIG_WATCHDOG 1 /* watchdog enabled */
-#define CONFIG_SYS_WATCHDOG_FREQ (CONFIG_SYS_HZ / 20)
-
-#undef CONFIG_STATUS_LED /* Status LED disabled */
-
-/* enable I2C and select the hardware/software driver */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define PB_SCL 0x00000020 /* PB 26 */
-#define PB_SDA 0x00000010 /* PB 27 */
-
-#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
-#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
-#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
-#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
-#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
- else immr->im_cpm.cp_pbdat &= ~PB_SDA
-#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
- else immr->im_cpm.cp_pbdat &= ~PB_SCL
-#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
-
-
-#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_BMP
-#define CONFIG_CMD_BSP
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_SNTP
-
-#ifdef CONFIG_POST
-#define CONFIG_CMD_DIAG
-#endif
-
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
-
-#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
-
-/*
- * When the watchdog is enabled, output must be fast enough in Linux.
- */
-#ifdef CONFIG_WATCHDOG
-#define CONFIG_SYS_BAUDRATE_TABLE { 38400, 57600, 115200 }
-#endif
-
-/*----------------------------------------------------------------------*/
-#define CONFIG_MODEM_SUPPORT 1 /* enable modem initialization stuff */
-#undef CONFIG_MODEM_SUPPORT_DEBUG
-
-#define CONFIG_MODEM_KEY_MAGIC "3C+3D" /* press F3 + F4 keys to enable modem */
-#define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */
-#if 0
-#define CONFIG_AUTOBOOT_KEYED /* Enable "password" protection */
-#define CONFIG_AUTOBOOT_PROMPT \
- "\nEnter password - autoboot in %d sec...\n", bootdelay
-#define CONFIG_AUTOBOOT_DELAY_STR " " /* "password" */
-#endif
-/*----------------------------------------------------------------------*/
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xFFF00000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0x40000000
-#if defined(DEBUG) || defined(CONFIG_CMD_IDE)
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#else
-#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
-#endif
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#define CONFIG_SYS_FLASH_BUFFER_WRITE_TOUT 2048 /* Timeout for Flash Buffer Write (in ms) */
-/* Buffer size.
- We have two flash devices connected in parallel.
- Each device incorporates a Write Buffer of 32 bytes.
- */
-#define CONFIG_SYS_FLASH_BUFFER_SIZE (2*32)
-
-/* Put environment in flash which is much faster to boot than using the EEPROM */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR 0x40040000 /* Address of Environment Sector */
-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment */
-#define CONFIG_ENV_SECT_SIZE 0x40000 /* we have BIG sectors only :-( */
-
-/*-----------------------------------------------------------------------
- * I2C/EEPROM Configuration
- */
-
-#define CONFIG_SYS_I2C_AUDIO_ADDR 0x28 /* Audio volume control */
-#define CONFIG_SYS_I2C_SYSMON_ADDR 0x2E /* LM87 System Monitor */
-#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */
-#define CONFIG_SYS_I2C_POWER_A_ADDR 0x52 /* PCMCIA/USB power switch, channel A */
-#define CONFIG_SYS_I2C_POWER_B_ADDR 0x53 /* PCMCIA/USB power switch, channel B */
-#define CONFIG_SYS_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */
-#define CONFIG_SYS_I2C_PICIO_ADDR 0x57 /* PIC IO Expander */
-
-#undef CONFIG_USE_FRAM /* Use FRAM instead of EEPROM */
-
-#ifdef CONFIG_USE_FRAM /* use FRAM */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x55 /* FRAM FM24CL64 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#else /* use EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 /* EEPROM AT24C164 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */
-#endif /* CONFIG_USE_FRAM */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
-
-/* List of I2C addresses to be verified by POST */
-#ifdef CONFIG_USE_FRAM
-#define CONFIG_SYS_POST_I2C_ADDRS {/* CONFIG_SYS_I2C_AUDIO_ADDR, */ \
- CONFIG_SYS_I2C_SYSMON_ADDR, \
- CONFIG_SYS_I2C_RTC_ADDR, \
- CONFIG_SYS_I2C_POWER_A_ADDR, \
- CONFIG_SYS_I2C_POWER_B_ADDR, \
- CONFIG_SYS_I2C_KEYBD_ADDR, \
- CONFIG_SYS_I2C_PICIO_ADDR, \
- CONFIG_SYS_I2C_EEPROM_ADDR, \
- }
-#else /* Use EEPROM - which show up on 8 consequtive addresses */
-#define CONFIG_SYS_POST_I2C_ADDRS {/* CONFIG_SYS_I2C_AUDIO_ADDR, */ \
- CONFIG_SYS_I2C_SYSMON_ADDR, \
- CONFIG_SYS_I2C_RTC_ADDR, \
- CONFIG_SYS_I2C_POWER_A_ADDR, \
- CONFIG_SYS_I2C_POWER_B_ADDR, \
- CONFIG_SYS_I2C_KEYBD_ADDR, \
- CONFIG_SYS_I2C_PICIO_ADDR, \
- CONFIG_SYS_I2C_EEPROM_ADDR+0, \
- CONFIG_SYS_I2C_EEPROM_ADDR+1, \
- CONFIG_SYS_I2C_EEPROM_ADDR+2, \
- CONFIG_SYS_I2C_EEPROM_ADDR+3, \
- CONFIG_SYS_I2C_EEPROM_ADDR+4, \
- CONFIG_SYS_I2C_EEPROM_ADDR+5, \
- CONFIG_SYS_I2C_EEPROM_ADDR+6, \
- CONFIG_SYS_I2C_EEPROM_ADDR+7, \
- }
-#endif /* CONFIG_USE_FRAM */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if 0 && defined(CONFIG_WATCHDOG) /* LWMON uses external MAX706TESA WD */
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-/* EARB, DBGC and DBPC are initialised by the HCW */
-/* => 0x000000C0 */
-#define CONFIG_SYS_SIUMCR (SIUMCR_GB5E)
-/*#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) */
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit, set PLL multiplication factor !
- */
-/* 0x00405000 */
-#define CONFIG_SYS_PLPRCR_MF 4 /* (4+1) * 13.2 = 66 MHz Clock */
-#define CONFIG_SYS_PLPRCR \
- ( (CONFIG_SYS_PLPRCR_MF << PLPRCR_MF_SHIFT) | \
- PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \
- /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
- PLPRCR_CSR /*| PLPRCR_LOLRE|PLPRCR_FIOPD*/ \
- )
-
-#define CONFIG_8xx_GCLK_FREQ ((CONFIG_SYS_PLPRCR_MF+1)*13200000)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK SCCR_EBDF11
-/* 0x01800000 */
-#define CONFIG_SYS_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \
- SCCR_RTDIV | SCCR_RTSEL | \
- /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
- SCCR_EBDF00 | SCCR_DFSYNC00 | \
- SCCR_DFBRG00 | SCCR_DFNL000 | \
- SCCR_DFNH000 | SCCR_DFLCD100 | \
- SCCR_DFALCD01)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register 11-27
- *-----------------------------------------------------------------------
- */
-/* 0x00C3 => 0x0003 */
-#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration Register 19-4
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RCCR 0x0000
-
-/*-----------------------------------------------------------------------
- * RMDS - RISC Microcode Development Support Control Register
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RMDS 0
-
-/*-----------------------------------------------------------------------
- *
- * Interrupt Levels
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_CPM_INTERRUPT 13 /* SIU_LEVEL6 */
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_PCMCIA_MEM_ADDR (0x50000000)
-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_DMA_ADDR (0x54000000)
-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0x58000000)
-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_IO_ADDR (0x5C000000)
-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
- *-----------------------------------------------------------------------
- */
-
-#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
-#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
-
-#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
-#undef CONFIG_IDE_LED /* LED for ide not supported */
-#undef CONFIG_IDE_RESET /* reset for ide not supported */
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
-
-#define CONFIG_SUPPORT_VFAT /* enable VFAT support */
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_DER 0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH) - second Flash bank optional
- */
-
-#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0x41000000 /* FLASH bank #1 */
-
-/* used to re-map FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CONFIG_SYS_REMAP_OR_AM 0xFF000000 /* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM 0xFF000000 /* OR addr mask */
-
-/* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 8, EHTR = 0 */
-#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_8_CLK)
-
-#define CONFIG_SYS_OR0_REMAP ( CONFIG_SYS_REMAP_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
- CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \
- CONFIG_SYS_OR_TIMING_FLASH)
-/* 16 bit, bank valid */
-#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
-
-#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
-#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
-
-/*
- * BR3/OR3: SDRAM
- *
- * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
- */
-#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */
-#define SDRAM_PRELIM_OR_AM 0xF0000000 /* map 256 MB (>SDRAM_MAX_SIZE!) */
-#define SDRAM_TIMING OR_SCY_0_CLK /* SDRAM-Timing */
-
-#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB SDRAM */
-
-#define CONFIG_SYS_OR3_PRELIM (SDRAM_PRELIM_OR_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING )
-#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-/*
- * BR5/OR5: Touch Panel
- *
- * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0
- */
-#define TOUCHPNL_BASE 0x20000000
-#define TOUCHPNL_OR_AM 0xFFFF8000
-#define TOUCHPNL_TIMING OR_SCY_0_CLK
-
-#define CONFIG_SYS_OR5_PRELIM (TOUCHPNL_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
- TOUCHPNL_TIMING )
-#define CONFIG_SYS_BR5_PRELIM ((TOUCHPNL_BASE & BR_BA_MSK) | BR_PS_32 | BR_V )
-
-#define CONFIG_SYS_MEMORY_75
-#undef CONFIG_SYS_MEMORY_7E
-#undef CONFIG_SYS_MEMORY_8E
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CONFIG_SYS_MPTPR 0x200
-
-/*
- * MAMR settings for SDRAM
- */
-
-#define CONFIG_SYS_MAMR_8COL 0x80802114
-#define CONFIG_SYS_MAMR_9COL 0x80904114
-
-/*
- * MAR setting for SDRAM
- */
-#define CONFIG_SYS_MAR 0x00000088
-
-#endif /* __CONFIG_H */
diff --git a/include/pcmcia.h b/include/pcmcia.h
index 7e495bc..54ab2ac 100644
--- a/include/pcmcia.h
+++ b/include/pcmcia.h
@@ -25,8 +25,6 @@
# define CONFIG_PCMCIA_SLOT_B /* The TQM8xxL use SLOT_B */
#elif defined(CONFIG_IVMS8) || defined(CONFIG_IVML24) /* The IVM* use SLOT_A */
# define CONFIG_PCMCIA_SLOT_A
-#elif defined(CONFIG_LWMON) /* The LWMON use SLOT_B */
-# define CONFIG_PCMCIA_SLOT_B
#elif defined(CONFIG_ATC) /* The ATC use SLOT_A */
# define CONFIG_PCMCIA_SLOT_A
#else
--
1.9.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [U-Boot] [PATCH 10/26] mpc8xx: remove IVMS8, IVML24 board support
2014-12-15 14:26 [U-Boot] [PATCH 0/26] Start removing non-generic boards Masahiro Yamada
` (8 preceding siblings ...)
2014-12-15 14:26 ` [U-Boot] [PATCH 09/26] mpc8xx: remove lwmon " Masahiro Yamada
@ 2014-12-15 14:26 ` Masahiro Yamada
2015-01-05 18:20 ` Tom Rini
2014-12-15 14:26 ` [U-Boot] [PATCH 11/26] mpc8xx: remove IP860 " Masahiro Yamada
` (17 subsequent siblings)
27 siblings, 1 reply; 55+ messages in thread
From: Masahiro Yamada @ 2014-12-15 14:26 UTC (permalink / raw)
To: u-boot
This board is still a non-generic board.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
---
arch/powerpc/cpu/mpc8xx/Kconfig | 7 -
arch/powerpc/cpu/mpc8xx/cpu_init.c | 2 -
board/ivm/Kconfig | 19 --
board/ivm/MAINTAINERS | 12 -
board/ivm/Makefile | 8 -
board/ivm/flash.c | 582 -------------------------------------
board/ivm/ivm.c | 382 ------------------------
board/ivm/u-boot.lds.debug | 122 --------
configs/IVML24_128_defconfig | 4 -
configs/IVML24_256_defconfig | 4 -
configs/IVML24_defconfig | 4 -
configs/IVMS8_128_defconfig | 4 -
configs/IVMS8_256_defconfig | 4 -
configs/IVMS8_defconfig | 4 -
doc/README.scrapyard | 2 +
include/commproc.h | 31 --
include/configs/IVML24.h | 458 -----------------------------
include/configs/IVMS8.h | 441 ----------------------------
include/pcmcia.h | 2 -
include/status_led.h | 58 ----
20 files changed, 2 insertions(+), 2148 deletions(-)
delete mode 100644 board/ivm/Kconfig
delete mode 100644 board/ivm/MAINTAINERS
delete mode 100644 board/ivm/Makefile
delete mode 100644 board/ivm/flash.c
delete mode 100644 board/ivm/ivm.c
delete mode 100644 board/ivm/u-boot.lds.debug
delete mode 100644 configs/IVML24_128_defconfig
delete mode 100644 configs/IVML24_256_defconfig
delete mode 100644 configs/IVML24_defconfig
delete mode 100644 configs/IVMS8_128_defconfig
delete mode 100644 configs/IVMS8_256_defconfig
delete mode 100644 configs/IVMS8_defconfig
delete mode 100644 include/configs/IVML24.h
delete mode 100644 include/configs/IVMS8.h
diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig
index 4d47d05..ef5c511 100644
--- a/arch/powerpc/cpu/mpc8xx/Kconfig
+++ b/arch/powerpc/cpu/mpc8xx/Kconfig
@@ -16,12 +16,6 @@ config TARGET_ESTEEM192E
config TARGET_IP860
bool "Support IP860"
-config TARGET_IVML24
- bool "Support IVML24"
-
-config TARGET_IVMS8
- bool "Support IVMS8"
-
config TARGET_TQM823L
bool "Support TQM823L"
@@ -63,7 +57,6 @@ endchoice
source "board/cogent/Kconfig"
source "board/esteem192e/Kconfig"
source "board/ip860/Kconfig"
-source "board/ivm/Kconfig"
source "board/tqc/tqm8xx/Kconfig"
endmenu
diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c
index d41fa88..753d25d 100644
--- a/arch/powerpc/cpu/mpc8xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c
@@ -126,8 +126,6 @@ void cpu_init_f (volatile immap_t * immr)
*/
#if defined(CONFIG_IP860) || \
- defined(CONFIG_IVML24) || \
- defined(CONFIG_IVMS8) || \
defined(CONFIG_RMU)
memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM;
diff --git a/board/ivm/Kconfig b/board/ivm/Kconfig
deleted file mode 100644
index 6ff3025..0000000
--- a/board/ivm/Kconfig
+++ /dev/null
@@ -1,19 +0,0 @@
-if TARGET_IVML24
-
-config SYS_BOARD
- default "ivm"
-
-config SYS_CONFIG_NAME
- default "IVML24"
-
-endif
-
-if TARGET_IVMS8
-
-config SYS_BOARD
- default "ivm"
-
-config SYS_CONFIG_NAME
- default "IVMS8"
-
-endif
diff --git a/board/ivm/MAINTAINERS b/board/ivm/MAINTAINERS
deleted file mode 100644
index 6a9082c..0000000
--- a/board/ivm/MAINTAINERS
+++ /dev/null
@@ -1,12 +0,0 @@
-IVM BOARD
-M: Wolfgang Denk <wd@denx.de>
-S: Maintained
-F: board/ivm/
-F: include/configs/IVML24.h
-F: configs/IVML24_defconfig
-F: configs/IVML24_128_defconfig
-F: configs/IVML24_256_defconfig
-F: include/configs/IVMS8.h
-F: configs/IVMS8_defconfig
-F: configs/IVMS8_128_defconfig
-F: configs/IVMS8_256_defconfig
diff --git a/board/ivm/Makefile b/board/ivm/Makefile
deleted file mode 100644
index e53a276..0000000
--- a/board/ivm/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = ivm.o flash.o
diff --git a/board/ivm/flash.c b/board/ivm/flash.c
deleted file mode 100644
index 14d3aee..0000000
--- a/board/ivm/flash.c
+++ /dev/null
@@ -1,582 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-# ifndef CONFIG_ENV_ADDR
-# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-# endif
-# ifndef CONFIG_ENV_SIZE
-# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-# endif
-# ifndef CONFIG_ENV_SECT_SIZE
-# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
-# endif
-#endif
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_data (flash_info_t *info, ulong dest, ulong data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- unsigned long size_b0;
- int i;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0: "
- "ID 0x%lx, Size = 0x%08lx = %ld MB\n",
- flash_info[0].flash_id,
- size_b0, size_b0<<20);
- }
-
- /* Remap FLASH according to real size */
- memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
- memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | \
- BR_MS_GPCM | BR_PS_16 | BR_V;
-
- /* Re-do sizing to get full correct info */
- size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
- flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
- flash_info[0].size = size_b0;
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[0]);
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
- &flash_info[0]);
-#endif
-
- return (size_b0);
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_MT:
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + ((i-3) * 0x00020000);
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00020000;
- }
- }
- return;
-
- case FLASH_MAN_SST:
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00002000);
- }
- return;
-
- case FLASH_MAN_AMD:
- case FLASH_MAN_FUJ:
-
- /* set up sector start address table */
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00008000;
- info->start[2] = base + 0x0000C000;
- info->start[3] = base + 0x00010000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00020000) - 0x00060000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00008000;
- info->start[i--] = base + info->size - 0x0000C000;
- info->start[i--] = base + info->size - 0x00010000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00020000;
- }
- }
- return;
- default:
- printf ("Don't know sector ofsets for flash type 0x%lx\n",
- info->flash_id);
- return;
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_FUJ: printf ("Fujitsu "); break;
- case FLASH_MAN_SST: printf ("SST "); break;
- case FLASH_MAN_STM: printf ("STM "); break;
- case FLASH_MAN_MT: printf ("MT "); break;
- case FLASH_MAN_INTEL: printf ("Intel "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
- break;
- case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
- break;
- case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
- break;
- case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
- break;
- case FLASH_SST200A: printf ("39xF200A (2M = 128K x 16)\n");
- break;
- case FLASH_SST400A: printf ("39xF400A (4M = 256K x 16)\n");
- break;
- case FLASH_SST800A: printf ("39xF800A (8M = 512K x 16)\n");
- break;
- case FLASH_STM800AB: printf ("M29W800AB (8M = 512K x 16)\n");
- break;
- case FLASH_28F008S5: printf ("28F008S5 (1M = 64K x 16)\n");
- break;
- case FLASH_28F400_T: printf ("28F400B3 (4Mbit, top boot sector)\n");
- break;
- case FLASH_28F400_B: printf ("28F400B3 (4Mbit, bottom boot sector)\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- if (info->size >= (1 << 20)) {
- i = 20;
- } else {
- i = 10;
- }
- printf (" Size: %ld %cB in %d Sectors\n",
- info->size >> i,
- (i == 20) ? 'M' : 'k',
- info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
- return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
- ushort value;
- vu_short *saddr = (vu_short *)addr;
-
- /* Read Manufacturer ID */
- saddr[0] = 0x0090;
- value = saddr[0];
-
- switch (value) {
- case (AMD_MANUFACT & 0xFFFF):
- info->flash_id = FLASH_MAN_AMD;
- break;
- case (FUJ_MANUFACT & 0xFFFF):
- info->flash_id = FLASH_MAN_FUJ;
- break;
- case (SST_MANUFACT & 0xFFFF):
- info->flash_id = FLASH_MAN_SST;
- break;
- case (STM_MANUFACT & 0xFFFF):
- info->flash_id = FLASH_MAN_STM;
- break;
- case (MT_MANUFACT & 0xFFFF):
- info->flash_id = FLASH_MAN_MT;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- saddr[0] = 0x00FF; /* restore read mode */
- return (0); /* no or unknown flash */
- }
-
- value = saddr[1]; /* device ID */
-
- switch (value) {
- case (AMD_ID_LV400T & 0xFFFF):
- info->flash_id += FLASH_AM400T;
- info->sector_count = 11;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (AMD_ID_LV400B & 0xFFFF):
- info->flash_id += FLASH_AM400B;
- info->sector_count = 11;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (AMD_ID_LV800T & 0xFFFF):
- info->flash_id += FLASH_AM800T;
- info->sector_count = 19;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (AMD_ID_LV800B & 0xFFFF):
- info->flash_id += FLASH_AM800B;
- info->sector_count = 19;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (AMD_ID_LV160T & 0xFFFF):
- info->flash_id += FLASH_AM160T;
- info->sector_count = 35;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case (AMD_ID_LV160B & 0xFFFF):
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00400000;
- break; /* => 4 MB */
-#if 0 /* enable when device IDs are available */
- case (AMD_ID_LV320T & 0xFFFF):
- info->flash_id += FLASH_AM320T;
- info->sector_count = 67;
- info->size = 0x00800000;
- break; /* => 8 MB */
-
- case (AMD_ID_LV320B & 0xFFFF):
- info->flash_id += FLASH_AM320B;
- info->sector_count = 67;
- info->size = 0x00800000;
- break; /* => 8 MB */
-#endif
- case (SST_ID_xF200A & 0xFFFF):
- info->flash_id += FLASH_SST200A;
- info->sector_count = 64; /* 39xF200A ID ( 2M = 128K x 16 ) */
- info->size = 0x00080000;
- break;
- case (SST_ID_xF400A & 0xFFFF):
- info->flash_id += FLASH_SST400A;
- info->sector_count = 128; /* 39xF400A ID ( 4M = 256K x 16 ) */
- info->size = 0x00100000;
- break;
- case (SST_ID_xF800A & 0xFFFF):
- info->flash_id += FLASH_SST800A;
- info->sector_count = 256; /* 39xF800A ID ( 8M = 512K x 16 ) */
- info->size = 0x00200000;
- break; /* => 2 MB */
- case (STM_ID_x800AB & 0xFFFF):
- info->flash_id += FLASH_STM800AB;
- info->sector_count = 19;
- info->size = 0x00200000;
- break; /* => 2 MB */
- case (MT_ID_28F400_T & 0xFFFF):
- info->flash_id += FLASH_28F400_T;
- info->sector_count = 7;
- info->size = 0x00080000;
- break; /* => 512 kB */
- case (MT_ID_28F400_B & 0xFFFF):
- info->flash_id += FLASH_28F400_B;
- info->sector_count = 7;
- info->size = 0x00080000;
- break; /* => 512 kB */
- default:
- info->flash_id = FLASH_UNKNOWN;
- saddr[0] = 0x00FF; /* restore read mode */
- return (0); /* => no or unknown flash */
-
- }
-
- if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
- printf ("** ERROR: sector count %d > max (%d) **\n",
- info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
- info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- }
-
- saddr[0] = 0x00FF; /* restore read mode */
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- int flag, prot, sect;
- ulong start, now, last;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_MT) {
- printf ("Can erase only MT flash types - aborted\n");
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- start = get_timer (0);
- last = start;
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- vu_short *addr = (vu_short *)(info->start[sect]);
- unsigned short status;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- *addr = 0x0050; /* clear status register */
- *addr = 0x0020; /* erase setup */
- *addr = 0x00D0; /* erase confirm */
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- while (((status = *addr) & 0x0080) != 0x0080) {
- if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- *addr = 0x00FF; /* reset to read mode */
- return 1;
- }
-
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
- *addr = 0x00FF; /* reset to read mode */
- }
- }
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 4 - Flash not identified
- */
-
-#define FLASH_WIDTH 2 /* flash bus width in bytes */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- return 4;
- }
-
- wp = (addr & ~(FLASH_WIDTH-1)); /* get lower FLASH_WIDTH aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<FLASH_WIDTH && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<FLASH_WIDTH; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_data(info, wp, data)) != 0) {
- return (rc);
- }
- wp += FLASH_WIDTH;
- }
-
- /*
- * handle FLASH_WIDTH aligned part
- */
- while (cnt >= FLASH_WIDTH) {
- data = 0;
- for (i=0; i<FLASH_WIDTH; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_data(info, wp, data)) != 0) {
- return (rc);
- }
- wp += FLASH_WIDTH;
- cnt -= FLASH_WIDTH;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<FLASH_WIDTH && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<FLASH_WIDTH; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_data(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_data (flash_info_t *info, ulong dest, ulong data)
-{
- vu_short *addr = (vu_short *)dest;
- ushort sdata = (ushort)data;
- ushort status;
- ulong start;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*addr & sdata) != sdata) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- *addr = 0x0040; /* write setup */
- *addr = sdata;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- start = get_timer (0);
-
- while (((status = *addr) & 0x0080) != 0x0080) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- *addr = 0x00FF; /* restore read mode */
- return (1);
- }
- }
-
- *addr = 0x00FF; /* restore read mode */
-
- return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
diff --git a/board/ivm/ivm.c b/board/ivm/ivm.c
deleted file mode 100644
index 3bdbdd1..0000000
--- a/board/ivm/ivm.c
+++ /dev/null
@@ -1,382 +0,0 @@
-/*
- * (C) Copyright 2000, 2001
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- * Ulrich Lutz, Speech Design GmbH, ulutz at datalab.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-#include <commproc.h>
-
-#ifdef CONFIG_STATUS_LED
-# include <status_led.h>
-#endif
-
-/* ------------------------------------------------------------------------- */
-
-static long int dram_size (long int, long int *, long int);
-
-/* ------------------------------------------------------------------------- */
-
-#define _NOT_USED_ 0xFFFFFFFF
-
-/*
- * 50 MHz SHARC access using UPM A
- */
-const uint sharc_table[] = {
- /*
- * Single Read. (Offset 0 in UPM RAM)
- */
- 0x0FF3FC04, 0x0FF3EC00, 0x7FFFEC04, 0xFFFFEC04,
- 0xFFFFEC05, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Burst Read. (Offset 8 in UPM RAM)
- */
- /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Single Write. (Offset 18 in UPM RAM)
- */
- 0x0FAFFC04, 0x0FAFEC00, 0x7FFFEC04, 0xFFFFEC04,
- 0xFFFFEC05, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Burst Write. (Offset 20 in UPM RAM)
- */
- /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Refresh (Offset 30 in UPM RAM)
- */
- /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Exception. (Offset 3c in UPM RAM)
- */
- 0x7FFFFC07, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
-};
-
-
-/*
- * 50 MHz SDRAM access using UPM B
- */
-const uint sdram_table[] = {
- /*
- * Single Read. (Offset 0 in UPM RAM)
- */
- 0x0E26FC04, 0x11ADFC04, 0xEFBBBC00, 0x1FF77C45, /* last */
- _NOT_USED_,
- /*
- * SDRAM Initialization (offset 5 in UPM RAM)
- *
- * This is no UPM entry point. The following definition uses
- * the remaining space to establish an initialization
- * sequence, which is executed by a RUN command.
- *
- */
- 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */
- /*
- * Burst Read. (Offset 8 in UPM RAM)
- */
- 0x0E26FC04, 0x10ADFC04, 0xF0AFFC00, 0xF0AFFC00,
- 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C45, /* last */
- _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Single Write. (Offset 18 in UPM RAM)
- */
- 0x1F27FC04, 0xEEAEBC04, 0x01B93C00, 0x1FF77C45, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Burst Write. (Offset 20 in UPM RAM)
- */
- 0x0E26BC00, 0x10AD7C00, 0xF0AFFC00, 0xF0AFFC00,
- 0xE1BBBC04, 0x1FF77C45, /* last */
- _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Refresh (Offset 30 in UPM RAM)
- */
- 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC84,
- 0xFFFFFC05, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Exception. (Offset 3c in UPM RAM)
- */
- 0x7FFFFC07, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
-};
-
-/* ------------------------------------------------------------------------- */
-
-
-/*
- * Check Board Identity:
- *
- */
-
-int checkboard (void)
-{
-#ifdef CONFIG_IVMS8
- puts ("Board: IVMS8\n");
-#endif
-#ifdef CONFIG_IVML24
- puts ("Board: IVM-L8/24\n");
-#endif
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immr->im_memctl;
- long int size_b0;
-
- /* enable SDRAM clock ("switch on" SDRAM) */
- immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_SDRAM_CLKE); /* GPIO */
- immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_SDRAM_CLKE); /* active output */
- immr->im_cpm.cp_pbdir |= CONFIG_SYS_PB_SDRAM_CLKE; /* output */
- immr->im_cpm.cp_pbdat |= CONFIG_SYS_PB_SDRAM_CLKE; /* assert SDRAM CLKE */
- udelay (1);
-
- /*
- * Map controller bank 1 for ELIC SACCO
- */
- memctl->memc_or1 = CONFIG_SYS_OR1;
- memctl->memc_br1 = CONFIG_SYS_BR1;
-
- /*
- * Map controller bank 2 for ELIC EPIC
- */
- memctl->memc_or2 = CONFIG_SYS_OR2;
- memctl->memc_br2 = CONFIG_SYS_BR2;
-
- /*
- * Configure UPMA for SHARC
- */
- upmconfig (UPMA, (uint *) sharc_table,
- sizeof (sharc_table) / sizeof (uint));
-
-#if defined(CONFIG_IVML24)
- /*
- * Map controller bank 4 for HDLC Address space
- */
- memctl->memc_or4 = CONFIG_SYS_OR4;
- memctl->memc_br4 = CONFIG_SYS_BR4;
-#endif
-
- /*
- * Map controller bank 5 for SHARC
- */
- memctl->memc_or5 = CONFIG_SYS_OR5;
- memctl->memc_br5 = CONFIG_SYS_BR5;
-
- memctl->memc_mamr = 0x00001000;
-
- /*
- * Configure UPMB for SDRAM
- */
- upmconfig (UPMB, (uint *) sdram_table,
- sizeof (sdram_table) / sizeof (uint));
-
- memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_8K;
-
- memctl->memc_mar = 0x00000088;
-
- /*
- * Map controller bank 3 to the SDRAM bank at preliminary address.
- */
- memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
- memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
-
- memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL; /* refresh not enabled yet */
-
- udelay (200);
- memctl->memc_mcr = 0x80806105; /* precharge */
- udelay (1);
- memctl->memc_mcr = 0x80806106; /* load mode register */
- udelay (1);
- memctl->memc_mcr = 0x80806130; /* autorefresh */
- udelay (1);
- memctl->memc_mcr = 0x80806130; /* autorefresh */
- udelay (1);
- memctl->memc_mcr = 0x80806130; /* autorefresh */
- udelay (1);
- memctl->memc_mcr = 0x80806130; /* autorefresh */
- udelay (1);
- memctl->memc_mcr = 0x80806130; /* autorefresh */
- udelay (1);
- memctl->memc_mcr = 0x80806130; /* autorefresh */
- udelay (1);
- memctl->memc_mcr = 0x80806130; /* autorefresh */
- udelay (1);
- memctl->memc_mcr = 0x80806130; /* autorefresh */
-
- memctl->memc_mbmr |= MBMR_PTBE; /* refresh enabled */
-
- /*
- * Check Bank 0 Memory Size for re-configuration
- */
- size_b0 =
- dram_size (CONFIG_SYS_MBMR_8COL, (long *) SDRAM_BASE3_PRELIM,
- SDRAM_MAX_SIZE);
-
- memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL | MBMR_PTBE;
-
- return (size_b0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-
-static long int dram_size (long int mamr_value, long int *base,
- long int maxsize)
-{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immr->im_memctl;
-
- memctl->memc_mbmr = mamr_value;
-
- return (get_ram_size (base, maxsize));
-}
-
-/* ------------------------------------------------------------------------- */
-
-void reset_phy (void)
-{
- immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
-
- /* De-assert Ethernet Powerdown */
- immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_ETH_POWERDOWN); /* GPIO */
- immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_ETH_POWERDOWN); /* active output */
- immr->im_cpm.cp_pbdir |= CONFIG_SYS_PB_ETH_POWERDOWN; /* output */
- immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_ETH_POWERDOWN); /* Enable PHY power */
- udelay (1000);
-
- /*
- * RESET is implemented by a positive pulse of at least 1 us
- * at the reset pin.
- *
- * Configure RESET pins for NS DP83843 PHY, and RESET chip.
- *
- * Note: The RESET pin is high active, but there is an
- * inverter on the SPD823TS board...
- */
- immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_ETH_RESET);
- immr->im_ioport.iop_pcdir |= CONFIG_SYS_PC_ETH_RESET;
- /* assert RESET signal of PHY */
- immr->im_ioport.iop_pcdat &= ~(CONFIG_SYS_PC_ETH_RESET);
- udelay (10);
- /* de-assert RESET signal of PHY */
- immr->im_ioport.iop_pcdat |= CONFIG_SYS_PC_ETH_RESET;
- udelay (10);
-}
-
-/* ------------------------------------------------------------------------- */
-
-void show_boot_progress (int status)
-{
-#if defined(CONFIG_STATUS_LED)
-# if defined(STATUS_LED_YELLOW)
- status_led_set (STATUS_LED_YELLOW,
- (status < 0) ? STATUS_LED_ON : STATUS_LED_OFF);
-# endif /* STATUS_LED_YELLOW */
-# if defined(STATUS_LED_BOOT)
- if (status == BOOTSTAGE_ID_DECOMP_IMAGE)
- status_led_set (STATUS_LED_BOOT, STATUS_LED_OFF);
-# endif /* STATUS_LED_BOOT */
-#endif /* CONFIG_STATUS_LED */
-}
-
-/* ------------------------------------------------------------------------- */
-
-void ide_set_reset (int on)
-{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- int i;
-
- /*
- * Configure PC for IDE Reset Pin
- */
- if (on) { /* assert RESET */
- immr->im_ioport.iop_pcdat &= ~(CONFIG_SYS_PC_IDE_RESET);
-
-#ifdef CONFIG_SYS_PB_12V_ENABLE
- /* 12V Enable output OFF */
- immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_12V_ENABLE);
-
- immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_12V_ENABLE);
- immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_12V_ENABLE);
- immr->im_cpm.cp_pbdir |= CONFIG_SYS_PB_12V_ENABLE;
-
- /* wait 500 ms for the voltage to stabilize */
- for (i = 0; i < 500; ++i)
- udelay(1000);
-#endif /* CONFIG_SYS_PB_12V_ENABLE */
- } else { /* release RESET */
-#ifdef CONFIG_SYS_PB_12V_ENABLE
- /* 12V Enable output ON */
- immr->im_cpm.cp_pbdat |= CONFIG_SYS_PB_12V_ENABLE;
-#endif /* CONFIG_SYS_PB_12V_ENABLE */
-
-#ifdef CONFIG_SYS_PB_IDE_MOTOR
- /* configure IDE Motor voltage monitor pin as input */
- immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_IDE_MOTOR);
- immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_IDE_MOTOR);
- immr->im_cpm.cp_pbdir &= ~(CONFIG_SYS_PB_IDE_MOTOR);
-
-/* wait up to 1 s for the motor voltage to stabilize */
- for (i = 0; i < 1000; ++i) {
- if ((immr->im_cpm.cp_pbdat
- & CONFIG_SYS_PB_IDE_MOTOR) != 0)
- break;
- udelay(1000);
- }
-
- if (i == 1000) { /* Timeout */
- printf("\nWarning: 5V for IDE Motor missing\n");
-#ifdef CONFIG_STATUS_LED
-#ifdef STATUS_LED_YELLOW
- status_led_set(STATUS_LED_YELLOW, STATUS_LED_ON);
-#endif
-#ifdef STATUS_LED_GREEN
- status_led_set(STATUS_LED_GREEN, STATUS_LED_OFF);
-#endif
-#endif /* CONFIG_STATUS_LED */
- }
-#endif /* CONFIG_SYS_PB_IDE_MOTOR */
-
- immr->im_ioport.iop_pcdat |= CONFIG_SYS_PC_IDE_RESET;
- }
-
- /* program port pin as GPIO output */
- immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_IDE_RESET);
- immr->im_ioport.iop_pcso &= ~(CONFIG_SYS_PC_IDE_RESET);
- immr->im_ioport.iop_pcdir |= CONFIG_SYS_PC_IDE_RESET;
-}
-
-/* ------------------------------------------------------------------------- */
diff --git a/board/ivm/u-boot.lds.debug b/board/ivm/u-boot.lds.debug
deleted file mode 100644
index 1dd207b..0000000
--- a/board/ivm/u-boot.lds.debug
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
- arch/powerpc/lib/extable.o (.text)
-
- . = env_offset;
- common/env_embedded.o(.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
diff --git a/configs/IVML24_128_defconfig b/configs/IVML24_128_defconfig
deleted file mode 100644
index f0850f6..0000000
--- a/configs/IVML24_128_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="IVML24_32M"
-CONFIG_PPC=y
-CONFIG_8xx=y
-CONFIG_TARGET_IVML24=y
diff --git a/configs/IVML24_256_defconfig b/configs/IVML24_256_defconfig
deleted file mode 100644
index 9c241c2..0000000
--- a/configs/IVML24_256_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="IVML24_64M"
-CONFIG_PPC=y
-CONFIG_8xx=y
-CONFIG_TARGET_IVML24=y
diff --git a/configs/IVML24_defconfig b/configs/IVML24_defconfig
deleted file mode 100644
index 0f85d43..0000000
--- a/configs/IVML24_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="IVML24_16M"
-CONFIG_PPC=y
-CONFIG_8xx=y
-CONFIG_TARGET_IVML24=y
diff --git a/configs/IVMS8_128_defconfig b/configs/IVMS8_128_defconfig
deleted file mode 100644
index 685d76f..0000000
--- a/configs/IVMS8_128_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="IVMS8_32M"
-CONFIG_PPC=y
-CONFIG_8xx=y
-CONFIG_TARGET_IVMS8=y
diff --git a/configs/IVMS8_256_defconfig b/configs/IVMS8_256_defconfig
deleted file mode 100644
index 63435d2..0000000
--- a/configs/IVMS8_256_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="IVMS8_64M"
-CONFIG_PPC=y
-CONFIG_8xx=y
-CONFIG_TARGET_IVMS8=y
diff --git a/configs/IVMS8_defconfig b/configs/IVMS8_defconfig
deleted file mode 100644
index 3f4087b..0000000
--- a/configs/IVMS8_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="IVMS8_16M"
-CONFIG_PPC=y
-CONFIG_8xx=y
-CONFIG_TARGET_IVMS8=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 1f5ff8f..252b607 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,8 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+IVML24 powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
+IVMS8 powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
lwmon powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
NETVIA powerpc mpc8xx - - Pantelis Antoniou <panto@intracom.gr>
R360MPI powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
diff --git a/include/commproc.h b/include/commproc.h
index 509d6e4..6e0a233 100644
--- a/include/commproc.h
+++ b/include/commproc.h
@@ -512,37 +512,6 @@ typedef struct scc_enet {
#define SICR_ENET_CLKRT ((uint)0x0000002C)
#endif /* CONFIG_IP860 */
-/*** IVMS8 **********************************************************/
-
-/* The IVMS8 uses the FEC on a MPC860T for Ethernet */
-
-#if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24)
-
-#define FEC_ENET /* use FEC for EThernet */
-#undef SCC_ENET
-
-#define PB_ENET_POWER ((uint)0x00010000) /* PB 15 */
-
-#define PC_ENET_RESET ((ushort)0x0010) /* PC 11 */
-
-#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
-#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
-#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
-#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
-#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
-#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
-#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
-#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
-#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
-#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
-#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
-#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
-#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
-
-#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
-
-#endif /* CONFIG_IVMS8, CONFIG_IVML24 */
-
/*** KM8XX *********************************************************/
/* The KM8XX Service Module uses SCC3 for Ethernet */
diff --git a/include/configs/IVML24.h b/include/configs/IVML24.h
deleted file mode 100644
index 8aa4ac2..0000000
--- a/include/configs/IVML24.h
+++ /dev/null
@@ -1,458 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
-#define CONFIG_IVML24 1 /* ...on a IVML24 board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFF000000
-
-#if defined (CONFIG_IVML24_16M)
-# define CONFIG_IDENT_STRING " IVML24"
-#elif defined (CONFIG_IVML24_32M)
-# define CONFIG_IDENT_STRING " IVML24_128"
-#elif defined (CONFIG_IVML24_64M)
-# define CONFIG_IDENT_STRING " IVML24_256"
-#endif
-
-#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
-#define CONFIG_8xx_GCLK_FREQ 50331648
-
-#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
-
-#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */
-
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
-
-#define CONFIG_BOOTARGS "root=/dev/nfs rw " \
- "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \
- "nfsaddrs=10.0.0.99:10.0.0.2"
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_STATUS_LED 1 /* Status LED enabled */
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_IDE
-
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
-
-#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
-
-#define CONFIG_SYS_PB_12V_ENABLE 0x00002000 /* PB 18 */
-#define CONFIG_SYS_PB_ILOCK_SWITCH 0x00004000 /* PB 17 */
-#define CONFIG_SYS_PB_SDRAM_CLKE 0x00008000 /* PB 16 */
-#define CONFIG_SYS_PB_ETH_POWERDOWN 0x00010000 /* PB 15 */
-#define CONFIG_SYS_PB_IDE_MOTOR 0x00020000 /* PB 14 */
-
-#define CONFIG_SYS_PC_ETH_RESET ((ushort)0x0010) /* PC 11 */
-#define CONFIG_SYS_PC_IDE_RESET ((ushort)0x0020) /* PC 10 */
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xFFF00000 /* was: 0xFF000000 */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-
-#if defined (CONFIG_IVML24_16M)
-# define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
-#elif defined (CONFIG_IVML24_32M)
-# define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */
-#elif defined (CONFIG_IVML24_64M)
-# define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */
-#endif
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFF000000
-#ifdef DEBUG
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#else
-#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
-#endif
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x7A000 /* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-
-# if defined (CONFIG_IVML24_16M)
-# define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-# elif defined (CONFIG_IVML24_32M)
-# define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWP)
-# elif defined (CONFIG_IVML24_64M)
-# define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWP)
-# endif
-
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-/* EARB, DBGC and DBPC are initialised by the HCW */
-/* => 0x000000C0 */
-#define CONFIG_SYS_SIUMCR (SIUMCR_BSC | SIUMCR_GB5E)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit, set PLL multiplication factor !
- */
-/* 0x00B0C0C0 */
-#define CONFIG_SYS_PLPRCR \
- ( (11 << PLPRCR_MF_SHIFT) | \
- PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/ \
- /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
- PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \
- )
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK SCCR_EBDF11
-/* 0x01800014 */
-#define CONFIG_SYS_SCCR (SCCR_COM01 | /*SCCR_TBS|*/ \
- SCCR_RTDIV | SCCR_RTSEL | \
- /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
- SCCR_EBDF00 | SCCR_DFSYNC00 | \
- SCCR_DFBRG00 | SCCR_DFNL000 | \
- SCCR_DFNH000 | SCCR_DFLCD101 | \
- SCCR_DFALCD00)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register 11-27
- *-----------------------------------------------------------------------
- */
-/* 0x00C3 */
-#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration Register 19-4
- *-----------------------------------------------------------------------
- */
-/* TIMEP=2 */
-#define CONFIG_SYS_RCCR 0x0200
-
-/*-----------------------------------------------------------------------
- * RMDS - RISC Microcode Development Support Control Register
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RMDS 0
-
-/*-----------------------------------------------------------------------
- *
- * Interrupt Levels
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_CPM_INTERRUPT 13 /* SIU_LEVEL6 */
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
-#define CONFIG_IDE_INIT_POSTRESET 1 /* Use postreset IDE hook */
-#define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */
-#define CONFIG_IDE_RESET 1 /* reset for ide supported */
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* The IVML24 has only 1 IDE bus*/
-#define CONFIG_SYS_IDE_MAXDEVICE 1 /* ... and only 1 IDE device */
-
-#define CONFIG_SYS_ATA_BASE_ADDR 0xFE100000
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-#undef CONFIG_SYS_ATA_IDE1_OFFSET /* only one IDE bus available */
-
-#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
-#define CONFIG_SYS_ATA_REG_OFFSET 0x0080 /* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 /* Offset for alternate registers */
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_DER 0
-
-/*
- * Init Memory Controller:
- *
- * BR0 and OR0 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank #0 */
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-/* EPROMs are 512kb */
-#define CONFIG_SYS_REMAP_OR_AM 0xFFF80000 /* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */
-
-/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
-#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_5_CLK | OR_EHTR)
-
-#define CONFIG_SYS_OR0_REMAP ( CONFIG_SYS_REMAP_OR_AM | OR_ACS_DIV4 | OR_BI | \
- CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | OR_ACS_DIV4 | OR_BI | \
- CONFIG_SYS_OR_TIMING_FLASH)
-/* 16 bit, bank valid */
-#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
-
-/*
- * BR1/OR1 - ELIC SACCO bank @ 0xFE000000
- *
- * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1
- */
-#define ELIC_SACCO_BASE 0xFE000000
-#define ELIC_SACCO_OR_AM 0xFFFF8000
-#define ELIC_SACCO_TIMING (OR_SCY_2_CLK | OR_TRLX | OR_EHTR)
-
-#define CONFIG_SYS_OR1 (ELIC_SACCO_OR_AM | OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
- ELIC_SACCO_TIMING)
-#define CONFIG_SYS_BR1 ((ELIC_SACCO_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
-
-/*
- * BR2/OR2 - ELIC EPIC bank @ 0xFE008000
- *
- * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1
- */
-#define ELIC_EPIC_BASE 0xFE008000
-#define ELIC_EPIC_OR_AM 0xFFFF8000
-#define ELIC_EPIC_TIMING (OR_SCY_2_CLK | OR_TRLX | OR_EHTR)
-
-#define CONFIG_SYS_OR2 (ELIC_EPIC_OR_AM | OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
- ELIC_EPIC_TIMING)
-#define CONFIG_SYS_BR2 ((ELIC_EPIC_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
-
-/*
- * BR3/OR3: SDRAM
- *
- * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
- */
-#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */
-#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */
-#define SDRAM_TIMING OR_SCY_0_CLK /* SDRAM-Timing */
-
-#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */
-
-#define CONFIG_SYS_OR3_PRELIM (SDRAM_PRELIM_OR_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING )
-#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V )
-
-/*
- * BR4/OR4 - HDLC Address
- *
- * AM=0xFFFF8 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=0 BIH=1 SCY=1 SETA=0 TRLX=0 EHTR=0
- */
-#define HDLC_ADDR_BASE 0xFE108000 /* HDLC Address area */
-#define HDLC_ADDR_OR_AM 0xFFFF8000
-#define HDLC_ADDR_TIMING OR_SCY_1_CLK
-
-#define CONFIG_SYS_OR4 (HDLC_ADDR_OR_AM | OR_BI | HDLC_ADDR_TIMING)
-#define CONFIG_SYS_BR4 ((HDLC_ADDR_BASE & BR_BA_MSK) | BR_PS_8 | BR_WP | BR_V )
-
-/*
- * BR5/OR5: SHARC ADSP-2165L
- *
- * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0
- */
-#define SHARC_BASE 0xFE400000
-#define SHARC_OR_AM 0xFFC00000
-#define SHARC_TIMING OR_SCY_0_CLK
-
-#define CONFIG_SYS_OR5 (SHARC_OR_AM | OR_ACS_DIV2 | OR_BI | SHARC_TIMING )
-#define CONFIG_SYS_BR5 ((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V )
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CONFIG_SYS_MBMR_PTB 204
-
-/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
-#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
-#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
-
-#if defined (CONFIG_IVML24_16M)
-# define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
-#elif defined (CONFIG_IVML24_32M)
-# define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
-#elif defined (CONFIG_IVML24_64M)
-# define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV8 /* setting for 1 bank */
-#endif
-
-
-/*
- * MBMR settings for SDRAM
- */
-
-#if defined (CONFIG_IVML24_16M)
- /* 8 column SDRAM */
-# define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \
- MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \
- MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X)
-#elif defined (CONFIG_IVML24_32M)
-/* 128 MBit SDRAM */
-# define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \
- MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 | \
- MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X)
-#elif defined (CONFIG_IVML24_64M)
-/* 128 MBit SDRAM */
-# define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \
- MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 | \
- MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X)
-#endif
-#endif /* __CONFIG_H */
diff --git a/include/configs/IVMS8.h b/include/configs/IVMS8.h
deleted file mode 100644
index 0b54af5..0000000
--- a/include/configs/IVMS8.h
+++ /dev/null
@@ -1,441 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
-#define CONFIG_IVMS8 1 /* ...on a IVMS8 board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFF000000
-
-#if defined (CONFIG_IVMS8_16M)
-# define CONFIG_IDENT_STRING " IVMS8"
-#elif defined (CONFIG_IVMS8_32M)
-# define CONFIG_IDENT_STRING " IVMS8_128"
-#elif defined (CONFIG_IVMS8_64M)
-# define CONFIG_IDENT_STRING " IVMS8_256"
-#endif
-
-#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
-
-#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
-#define CONFIG_8xx_GCLK_FREQ 50331648
-
-#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */
-
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
-
-#define CONFIG_BOOTARGS "root=/dev/nfs rw " \
- "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \
- "nfsaddrs=10.0.0.99:10.0.0.2"
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_STATUS_LED 1 /* Status LED enabled */
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_IDE
-
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
-
-#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
-
-#define CONFIG_SYS_PB_SDRAM_CLKE 0x00008000 /* PB 16 */
-#define CONFIG_SYS_PB_ETH_POWERDOWN 0x00010000 /* PB 15 */
-#define CONFIG_SYS_PB_IDE_MOTOR 0x00020000 /* PB 14 */
-
-#define CONFIG_SYS_PC_ETH_RESET ((ushort)0x0010) /* PC 11 */
-#define CONFIG_SYS_PC_IDE_RESET ((ushort)0x0020) /* PC 10 */
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xFFF00000 /* was: 0xFF000000 */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#if defined (CONFIG_IVMS8_16M)
-# define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
-#elif defined (CONFIG_IVMS8_32M)
-# define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */
-#elif defined (CONFIG_IVMS8_64M)
-# define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */
-#endif
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFF000000
-#ifdef DEBUG
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#else
-#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
-#endif
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x7A000 /* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-# if defined (CONFIG_IVMS8_16M)
-# define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-# elif defined (CONFIG_IVMS8_32M)
-# define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWP)
-# elif defined (CONFIG_IVMS8_64M)
-# define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWP)
-# endif
-#else
-# define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-/* EARB, DBGC and DBPC are initialised by the HCW */
-/* => 0x000000C0 */
-#define CONFIG_SYS_SIUMCR (SIUMCR_BSC | SIUMCR_GB5E)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit, set PLL multiplication factor !
- */
-/* 0x00B0C0C0 */
-#define CONFIG_SYS_PLPRCR \
- ( (11 << PLPRCR_MF_SHIFT) | \
- PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/ \
- /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
- PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \
- )
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK SCCR_EBDF11
-/* 0x01800014 */
-#define CONFIG_SYS_SCCR (SCCR_COM01 | /*SCCR_TBS|*/ \
- SCCR_RTDIV | SCCR_RTSEL | \
- /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
- SCCR_EBDF00 | SCCR_DFSYNC00 | \
- SCCR_DFBRG00 | SCCR_DFNL000 | \
- SCCR_DFNH000 | SCCR_DFLCD101 | \
- SCCR_DFALCD00)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register 11-27
- *-----------------------------------------------------------------------
- */
-/* 0x00C3 */
-#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration Register 19-4
- *-----------------------------------------------------------------------
- */
-/* TIMEP=2 */
-#define CONFIG_SYS_RCCR 0x0200
-
-/*-----------------------------------------------------------------------
- * RMDS - RISC Microcode Development Support Control Register
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RMDS 0
-
-/*-----------------------------------------------------------------------
- *
- * Interrupt Levels
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_CPM_INTERRUPT 13 /* SIU_LEVEL6 */
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
-#define CONFIG_IDE_INIT_POSTRESET 1 /* Use postreset IDE hook */
-#define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */
-#define CONFIG_IDE_RESET 1 /* reset for ide supported */
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* The IVMS8 has only 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 1 /* ... and only 1 IDE device */
-
-#define CONFIG_SYS_ATA_BASE_ADDR 0xFE100000
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-#undef CONFIG_SYS_ATA_IDE1_OFFSET /* only one IDE bus available */
-
-#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
-#define CONFIG_SYS_ATA_REG_OFFSET 0x0080 /* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 /* Offset for alternate registers */
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_DER 0
-
-/*
- * Init Memory Controller:
- *
- * BR0 and OR0 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank #0 */
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-/* EPROMs are 512kb */
-#define CONFIG_SYS_REMAP_OR_AM 0xFFF80000 /* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */
-
-/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
-#define CONFIG_SYS_OR_TIMING_FLASH (/* OR_CSNT_SAM | */ OR_ACS_DIV4 | OR_BI | \
- OR_SCY_5_CLK | OR_EHTR)
-
-#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-/* 16 bit, bank valid */
-#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
-
-/*
- * BR1/OR1 - ELIC SACCO bank @ 0xFE000000
- *
- * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1
- */
-#define ELIC_SACCO_BASE 0xFE000000
-#define ELIC_SACCO_OR_AM 0xFFFF8000
-#define ELIC_SACCO_TIMING 0x00000F26
-
-#define CONFIG_SYS_OR1 (ELIC_SACCO_OR_AM | ELIC_SACCO_TIMING)
-#define CONFIG_SYS_BR1 ((ELIC_SACCO_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
-
-/*
- * BR2/OR2 - ELIC EPIC bank @ 0xFE008000
- *
- * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1
- */
-#define ELIC_EPIC_BASE 0xFE008000
-#define ELIC_EPIC_OR_AM 0xFFFF8000
-#define ELIC_EPIC_TIMING 0x00000F26
-
-#define CONFIG_SYS_OR2 (ELIC_EPIC_OR_AM | ELIC_EPIC_TIMING)
-#define CONFIG_SYS_BR2 ((ELIC_EPIC_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
-
-/*
- * BR3/OR3: SDRAM
- *
- * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
- */
-#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */
-#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */
-#define SDRAM_TIMING 0x00000A00 /* SDRAM-Timing */
-
-#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */
-
-#define CONFIG_SYS_OR3_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
-#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V )
-
-/*
- * BR4/OR4: not used
- */
-
-/*
- * BR5/OR5: SHARC ADSP-2165L
- *
- * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0
- */
-#define SHARC_BASE 0xFE400000
-#define SHARC_OR_AM 0xFFC00000
-#define SHARC_TIMING 0x00000700
-
-#define CONFIG_SYS_OR5 (SHARC_OR_AM | SHARC_TIMING )
-#define CONFIG_SYS_BR5 ((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V )
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CONFIG_SYS_MBMR_PTB 204
-
-/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
-#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
-#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
-#if defined (CONFIG_IVMS8_16M)
- #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
-#elif defined (CONFIG_IVMS8_32M)
-#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
-#elif defined (CONFIG_IVMS8_64M)
-#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV8 /* setting for 1 bank */
-#endif
-
-
-/*
- * MBMR settings for SDRAM
- */
-
-#if defined (CONFIG_IVMS8_16M)
- /* 8 column SDRAM */
-# define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \
- MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \
- MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X)
-#elif defined (CONFIG_IVMS8_32M)
-/* 128 MBit SDRAM */
-#define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \
- MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 | \
- MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X)
-#elif defined (CONFIG_IVMS8_64M)
-/* 128 MBit SDRAM */
-#define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \
- MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 | \
- MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X)
-
-#endif
-#endif /* __CONFIG_H */
diff --git a/include/pcmcia.h b/include/pcmcia.h
index 54ab2ac..8e8831f 100644
--- a/include/pcmcia.h
+++ b/include/pcmcia.h
@@ -23,8 +23,6 @@
#if defined(CONFIG_TQM8xxL)
# define CONFIG_PCMCIA_SLOT_B /* The TQM8xxL use SLOT_B */
-#elif defined(CONFIG_IVMS8) || defined(CONFIG_IVML24) /* The IVM* use SLOT_A */
-# define CONFIG_PCMCIA_SLOT_A
#elif defined(CONFIG_ATC) /* The ATC use SLOT_A */
# define CONFIG_PCMCIA_SLOT_A
#else
diff --git a/include/status_led.h b/include/status_led.h
index 919e3ae..27f4bdf 100644
--- a/include/status_led.h
+++ b/include/status_led.h
@@ -56,64 +56,6 @@ void status_led_set (int led, int state);
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
-/***** IVMS8 **********************************************************/
-#elif defined(CONFIG_IVMS8)
-
-# define STATUS_LED_PAR im_cpm.cp_pbpar
-# define STATUS_LED_DIR im_cpm.cp_pbdir
-# define STATUS_LED_ODR im_cpm.cp_pbodr
-# define STATUS_LED_DAT im_cpm.cp_pbdat
-
-# define STATUS_LED_BIT 0x00000010 /* LED 0 is on PB.27 */
-# define STATUS_LED_PERIOD (1 * CONFIG_SYS_HZ)
-# define STATUS_LED_STATE STATUS_LED_OFF
-# define STATUS_LED_BIT1 0x00000020 /* LED 1 is on PB.26 */
-# define STATUS_LED_PERIOD1 (1 * CONFIG_SYS_HZ)
-# define STATUS_LED_STATE1 STATUS_LED_OFF
-/* IDE LED usable for other purposes, too */
-# define STATUS_LED_BIT2 0x00000008 /* LED 2 is on PB.28 */
-# define STATUS_LED_PERIOD2 (1 * CONFIG_SYS_HZ)
-# define STATUS_LED_STATE2 STATUS_LED_OFF
-
-# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
-
-# define STATUS_ILOCK_SWITCH 0x00800000 /* ILOCK switch in IRQ4 */
-
-# define STATUS_ILOCK_PERIOD (CONFIG_SYS_HZ / 10) /* about every 100 ms */
-
-# define STATUS_LED_YELLOW 0
-# define STATUS_LED_GREEN 1
-# define STATUS_LED_BOOT 2 /* IDE LED used for boot status */
-
-/***** IVML24 *********************************************************/
-#elif defined(CONFIG_IVML24)
-
-# define STATUS_LED_PAR im_cpm.cp_pbpar
-# define STATUS_LED_DIR im_cpm.cp_pbdir
-# define STATUS_LED_ODR im_cpm.cp_pbodr
-# define STATUS_LED_DAT im_cpm.cp_pbdat
-
-# define STATUS_LED_BIT 0x00000010 /* LED 0 is on PB.27 */
-# define STATUS_LED_PERIOD (1 * CONFIG_SYS_HZ)
-# define STATUS_LED_STATE STATUS_LED_OFF
-# define STATUS_LED_BIT1 0x00000020 /* LED 1 is on PB.26 */
-# define STATUS_LED_PERIOD1 (1 * CONFIG_SYS_HZ)
-# define STATUS_LED_STATE1 STATUS_LED_OFF
-/* IDE LED usable for other purposes, too */
-# define STATUS_LED_BIT2 0x00000008 /* LED 2 is on PB.28 */
-# define STATUS_LED_PERIOD2 (1 * CONFIG_SYS_HZ)
-# define STATUS_LED_STATE2 STATUS_LED_OFF
-
-# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
-
-# define STATUS_ILOCK_SWITCH 0x00004000 /* ILOCK is on PB.17 */
-
-# define STATUS_ILOCK_PERIOD (CONFIG_SYS_HZ / 10) /* about every 100 ms */
-
-# define STATUS_LED_YELLOW 0
-# define STATUS_LED_GREEN 1
-# define STATUS_LED_BOOT 2 /* IDE LED used for boot status */
-
/***** Someone else defines these *************************************/
#elif defined(STATUS_LED_PAR)
--
1.9.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [U-Boot] [PATCH 11/26] mpc8xx: remove IP860 board support
2014-12-15 14:26 [U-Boot] [PATCH 0/26] Start removing non-generic boards Masahiro Yamada
` (9 preceding siblings ...)
2014-12-15 14:26 ` [U-Boot] [PATCH 10/26] mpc8xx: remove IVMS8, IVML24 " Masahiro Yamada
@ 2014-12-15 14:26 ` Masahiro Yamada
2015-01-05 18:20 ` Tom Rini
2014-12-15 14:26 ` [U-Boot] [PATCH 12/26] mpc8xx: remove ESTEEM192E " Masahiro Yamada
` (16 subsequent siblings)
27 siblings, 1 reply; 55+ messages in thread
From: Masahiro Yamada @ 2014-12-15 14:26 UTC (permalink / raw)
To: u-boot
This board is still a non-generic board.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
---
arch/powerpc/cpu/mpc8xx/Kconfig | 4 -
arch/powerpc/cpu/mpc8xx/cpu_init.c | 10 -
arch/powerpc/cpu/mpc8xx/serial.c | 7 +-
board/ip860/Kconfig | 9 -
board/ip860/MAINTAINERS | 6 -
board/ip860/Makefile | 8 -
board/ip860/flash.c | 440 -------------------------------------
board/ip860/ip860.c | 340 ----------------------------
board/ip860/u-boot.lds.debug | 122 ----------
configs/IP860_defconfig | 3 -
doc/README.scrapyard | 1 +
include/commproc.h | 28 ---
include/configs/IP860.h | 438 ------------------------------------
13 files changed, 2 insertions(+), 1414 deletions(-)
delete mode 100644 board/ip860/Kconfig
delete mode 100644 board/ip860/MAINTAINERS
delete mode 100644 board/ip860/Makefile
delete mode 100644 board/ip860/flash.c
delete mode 100644 board/ip860/ip860.c
delete mode 100644 board/ip860/u-boot.lds.debug
delete mode 100644 configs/IP860_defconfig
delete mode 100644 include/configs/IP860.h
diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig
index ef5c511..45e7d7e 100644
--- a/arch/powerpc/cpu/mpc8xx/Kconfig
+++ b/arch/powerpc/cpu/mpc8xx/Kconfig
@@ -13,9 +13,6 @@ config TARGET_COGENT_MPC8XX
config TARGET_ESTEEM192E
bool "Support ESTEEM192E"
-config TARGET_IP860
- bool "Support IP860"
-
config TARGET_TQM823L
bool "Support TQM823L"
@@ -56,7 +53,6 @@ endchoice
source "board/cogent/Kconfig"
source "board/esteem192e/Kconfig"
-source "board/ip860/Kconfig"
source "board/tqc/tqm8xx/Kconfig"
endmenu
diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c
index 753d25d..f621d62 100644
--- a/arch/powerpc/cpu/mpc8xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c
@@ -125,12 +125,6 @@ void cpu_init_f (volatile immap_t * immr)
* I owe him a free beer. - wd]
*/
-#if defined(CONFIG_IP860) || \
- defined(CONFIG_RMU)
-
- memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM;
-#endif
-
#if defined(CONFIG_SYS_OR0_REMAP)
memctl->memc_or0 = CONFIG_SYS_OR0_REMAP;
#endif
@@ -150,10 +144,6 @@ void cpu_init_f (volatile immap_t * immr)
memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
#endif
-#if defined(CONFIG_IP860) /* disable CS0 now that Flash is mapped on CS1 */
- memctl->memc_br0 = 0;
-#endif
-
#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
diff --git a/arch/powerpc/cpu/mpc8xx/serial.c b/arch/powerpc/cpu/mpc8xx/serial.c
index bb16b17..af65c96 100644
--- a/arch/powerpc/cpu/mpc8xx/serial.c
+++ b/arch/powerpc/cpu/mpc8xx/serial.c
@@ -416,18 +416,13 @@ static int scc_init (void)
cp->cp_pbdir &= ~0x06;
cp->cp_pbodr &= ~0x06;
-#elif (SCC_INDEX < 2) || !defined(CONFIG_IP860)
+#elif (SCC_INDEX < 2)
/*
* Standard configuration for SCC's is on Part A
*/
ip->iop_papar |= ((3 << (2 * SCC_INDEX)));
ip->iop_padir &= ~((3 << (2 * SCC_INDEX)));
ip->iop_paodr &= ~((3 << (2 * SCC_INDEX)));
-#else
- /*
- * The IP860 has SCC3 and SCC4 on Port D
- */
- ip->iop_pdpar |= ((3 << (2 * SCC_INDEX)));
#endif
/* Allocate space for two buffer descriptors in the DP ram. */
diff --git a/board/ip860/Kconfig b/board/ip860/Kconfig
deleted file mode 100644
index 955c9db..0000000
--- a/board/ip860/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_IP860
-
-config SYS_BOARD
- default "ip860"
-
-config SYS_CONFIG_NAME
- default "IP860"
-
-endif
diff --git a/board/ip860/MAINTAINERS b/board/ip860/MAINTAINERS
deleted file mode 100644
index 36d5690..0000000
--- a/board/ip860/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-IP860 BOARD
-M: Wolfgang Denk <wd@denx.de>
-S: Maintained
-F: board/ip860/
-F: include/configs/IP860.h
-F: configs/IP860_defconfig
diff --git a/board/ip860/Makefile b/board/ip860/Makefile
deleted file mode 100644
index 3c60006..0000000
--- a/board/ip860/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = ip860.o flash.o
diff --git a/board/ip860/flash.c b/board/ip860/flash.c
deleted file mode 100644
index 542b0c8..0000000
--- a/board/ip860/flash.c
+++ /dev/null
@@ -1,440 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-# ifndef CONFIG_ENV_ADDR
-# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-# endif
-# ifndef CONFIG_ENV_SIZE
-# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-# endif
-# ifndef CONFIG_ENV_SECT_SIZE
-# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
-# endif
-#endif
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- volatile ip860_bcsr_t *bcsr = (ip860_bcsr_t *)BCSR_BASE;
- unsigned long size;
- int i;
-
- /* Init: enable write,
- * or we cannot even write flash commands
- */
- bcsr->bd_ctrl |= BD_CTRL_FLWE;
-
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size = flash_get_size((vu_long *)FLASH_BASE, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size, size<<20);
- }
-
- /* Remap FLASH according to real size */
- memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000);
- memctl->memc_br1 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) |
- (memctl->memc_br1 & ~(BR_BA_MSK));
-
- /* Re-do sizing to get full correct info */
- size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
- flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
- flash_info[0].size = size;
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[0]);
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
- &flash_info[0]);
-#endif
- return (size);
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
- int i;
-
- /* all possible flash types
- * (28F016SV, 28F160S3, 28F320S3)
- * have the same erase block size: 64 kB per chip,
- * of 128 kB per bank
- */
-
- /* set up sector start address table */
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base;
- base += 0x00020000;
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_INTEL: printf ("Intel "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n");
- break;
- case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n");
- break;
- case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
- return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
- short i;
- ulong value;
- ulong base = (ulong)addr;
-
- /* Write "Intelligent Identifier" command: read Manufacturer ID */
- *addr = 0x90909090;
-
- value = addr[0];
- switch (value) {
- case (MT_MANUFACT & 0x00FF00FF): /* MT or => Intel */
- case (INTEL_ALT_MANU & 0x00FF00FF):
- info->flash_id = FLASH_MAN_INTEL;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
- value = addr[1]; /* device ID */
-
- switch (value) {
- case (INTEL_ID_28F016S):
- info->flash_id += FLASH_28F016SV;
- info->sector_count = 32;
- info->size = 0x00400000;
- break; /* => 2x2 MB */
-
- case (INTEL_ID_28F160S3):
- info->flash_id += FLASH_28F160S3;
- info->sector_count = 32;
- info->size = 0x00400000;
- break; /* => 2x2 MB */
-
- case (INTEL_ID_28F320S3):
- info->flash_id += FLASH_28F320S3;
- info->sector_count = 64;
- info->size = 0x00800000;
- break; /* => 2x4 MB */
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
-
- }
-
- /* set up sector start address table */
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00020000);
- /* don't know how to check sector protection */
- info->protect[i] = 0;
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- addr = (vu_long *)info->start[0];
-
- *addr = 0xFFFFFF; /* reset bank to read array mode */
- }
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- int flag, prot, sect;
- ulong start, now, last;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- start = get_timer (0);
- last = start;
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- vu_long *addr = (vu_long *)(info->start[sect]);
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- /* Single Block Erase Command */
- *addr = 0x20202020;
- /* Confirm */
- *addr = 0xD0D0D0D0;
- /* Resume Command, as per errata update */
- *addr = 0xD0D0D0D0;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- while ((*addr & 0x00800080) != 0x00800080) {
- if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- *addr = 0xFFFFFFFF; /* reset bank */
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
- /* reset to read mode */
- *addr = 0xFFFFFFFF;
- }
- }
-
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i=0; i<4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
- vu_long *addr = (vu_long *)dest;
- ulong start, csr;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*addr & data) != data) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- /* Write Command */
- *addr = 0x10101010;
-
- /* Write Data */
- *addr = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
- flag = 0;
- while (((csr = *addr) & 0x00800080) != 0x00800080) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- flag = 1;
- break;
- }
- }
- if (csr & 0x00400040) {
-printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr);
- flag = 1;
- }
-
- /* Clear Status Registers Command */
- *addr = 0x50505050;
- /* Reset to read array mode */
- *addr = 0xFFFFFFFF;
-
- return (flag);
-}
-
-/*-----------------------------------------------------------------------
- */
diff --git a/board/ip860/ip860.c b/board/ip860/ip860.c
deleted file mode 100644
index 4e3b1b5..0000000
--- a/board/ip860/ip860.c
+++ /dev/null
@@ -1,340 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <commproc.h>
-#include <mpc8xx.h>
-
-/* ------------------------------------------------------------------------- */
-
-static long int dram_size (long int, long int *, long int);
-unsigned long ip860_get_dram_size(void);
-unsigned long ip860_get_clk_freq (void);
-/* ------------------------------------------------------------------------- */
-
-#define _NOT_USED_ 0xFFFFFFFF
-
-const uint sdram_table[] = {
- /*
- * Single Read. (Offset 0 in UPMA RAM)
- */
- 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
- 0x1ff77c47, /* last */
- /*
- * SDRAM Initialization (offset 5 in UPMA RAM)
- *
- * This is no UPM entry point. The following definition uses
- * the remaining space to establish an initialization
- * sequence, which is executed by a RUN command.
- *
- */
- 0x1ff77c34, 0xefeabc34, 0x1fb57c35, /* last */
- /*
- * Burst Read. (Offset 8 in UPMA RAM)
- */
- 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
- 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Single Write. (Offset 18 in UPMA RAM)
- */
- 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Burst Write. (Offset 20 in UPMA RAM)
- */
- 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
- 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, /* last */
- _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Refresh (Offset 30 in UPMA RAM)
- */
- 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
- 0xfffffc84, 0xfffffc07, /* last */
- _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Exception. (Offset 3c in UPMA RAM)
- */
- 0x7ffffc07, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
-};
-
-
-/* ------------------------------------------------------------------------- */
-int board_early_init_f(void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
-/* init BCSR chipselect line for ip860_get_clk_freq() and ip860_get_dram_size() */
- memctl->memc_or4 = CONFIG_SYS_OR4;
- memctl->memc_br4 = CONFIG_SYS_BR4;
-
- return 0;
-}
-
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check Board Identity:
- *
- * Test ID string (IP860...)
- */
-
-int checkboard (void)
-{
- unsigned char *s, *e;
- unsigned char buf[64];
- int i;
-
- puts ("Board: ");
-
- i = getenv_f("serial#", (char *)buf, sizeof (buf));
- s = (i > 0) ? buf : NULL;
-
- if (!s || strncmp ((char *)s, "IP860", 5)) {
- puts ("### No HW ID - assuming IP860");
- } else {
- for (e = s; *e; ++e) {
- if (*e == ' ')
- break;
- }
-
- for (; s < e; ++s) {
- putc (*s);
- }
- }
-
- putc ('\n');
-
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- long int size;
- ulong refresh_val;
-
- upmconfig (UPMA, (uint *) sdram_table,
- sizeof (sdram_table) / sizeof (uint));
-
- /*
- * Preliminary prescaler for refresh
- */
- if (ip860_get_clk_freq() == 50000000)
- {
- memctl->memc_mptpr = 0x0400;
- refresh_val = 0xC3000000;
- }
- else
- {
- memctl->memc_mptpr = 0x0200;
- refresh_val = 0x9C000000;
- }
-
-
- memctl->memc_mar = 0x00000088;
-
- /*
- * Map controller banks 2 to the SDRAM address
- */
- memctl->memc_or2 = CONFIG_SYS_OR2;
- memctl->memc_br2 = CONFIG_SYS_BR2;
-
- /* IP860 boards have only one bank SDRAM */
-
-
- udelay (200);
-
- /* perform SDRAM initializsation sequence */
-
- memctl->memc_mamr = 0x00804114 | refresh_val;
- memctl->memc_mcr = 0x80004105; /* run precharge pattern from loc 5 */
- udelay(1);
- memctl->memc_mamr = 0x00804118 | refresh_val;
- memctl->memc_mcr = 0x80004130; /* run refresh pattern 8 times */
-
-
- udelay (1000);
-
- /*
- * Check SDRAM Memory Size
- */
- if (ip860_get_dram_size() == 16)
- size = dram_size (refresh_val | 0x00804114, SDRAM_BASE, SDRAM_MAX_SIZE);
- else
- size = dram_size (refresh_val | 0x00906114, SDRAM_BASE, SDRAM_MAX_SIZE);
-
- udelay (1000);
-
- memctl->memc_or2 = ((-size) & 0xFFFF0000) | SDRAM_TIMING;
- memctl->memc_br2 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
-
- udelay (10000);
-
- /*
- * Also, map other memory to correct position
- */
-
-#if (defined(CONFIG_SYS_OR1) && defined(CONFIG_SYS_BR1_PRELIM))
- memctl->memc_or1 = CONFIG_SYS_OR1;
- memctl->memc_br1 = CONFIG_SYS_BR1;
-#endif
-
-#if defined(CONFIG_SYS_OR3) && defined(CONFIG_SYS_BR3)
- memctl->memc_or3 = CONFIG_SYS_OR3;
- memctl->memc_br3 = CONFIG_SYS_BR3;
-#endif
-
-#if defined(CONFIG_SYS_OR4) && defined(CONFIG_SYS_BR4)
- memctl->memc_or4 = CONFIG_SYS_OR4;
- memctl->memc_br4 = CONFIG_SYS_BR4;
-#endif
-
-#if defined(CONFIG_SYS_OR5) && defined(CONFIG_SYS_BR5)
- memctl->memc_or5 = CONFIG_SYS_OR5;
- memctl->memc_br5 = CONFIG_SYS_BR5;
-#endif
-
-#if defined(CONFIG_SYS_OR6) && defined(CONFIG_SYS_BR6)
- memctl->memc_or6 = CONFIG_SYS_OR6;
- memctl->memc_br6 = CONFIG_SYS_BR6;
-#endif
-
-#if defined(CONFIG_SYS_OR7) && defined(CONFIG_SYS_BR7)
- memctl->memc_or7 = CONFIG_SYS_OR7;
- memctl->memc_br7 = CONFIG_SYS_BR7;
-#endif
-
- return (size);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-
-static long int dram_size (long int mamr_value, long int *base,
- long int maxsize)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
- memctl->memc_mamr = mamr_value;
-
- return (get_ram_size(base, maxsize));
-}
-
-/* ------------------------------------------------------------------------- */
-
-void reset_phy (void)
-{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- ulong mask = PB_ENET_RESET | PB_ENET_JABD;
- ulong reg;
-
- /* Make sure PHY is not in low-power mode */
- immr->im_cpm.cp_pbpar &= ~(mask); /* GPIO */
- immr->im_cpm.cp_pbodr &= ~(mask); /* active output */
-
- /* Set JABD low (no JABber Disable),
- * and RESET high (Reset PHY)
- */
- reg = immr->im_cpm.cp_pbdat;
- reg = (reg & ~PB_ENET_JABD) | PB_ENET_RESET;
- immr->im_cpm.cp_pbdat = reg;
-
- /* now drive outputs */
- immr->im_cpm.cp_pbdir |= mask; /* output */
- udelay (1000);
- /*
- * Release RESET signal
- */
- immr->im_cpm.cp_pbdat &= ~(PB_ENET_RESET);
- udelay (1000);
-}
-
-/* ------------------------------------------------------------------------- */
-
-unsigned long ip860_get_clk_freq(void)
-{
- volatile ip860_bcsr_t *bcsr = (ip860_bcsr_t *)BCSR_BASE;
- ulong temp;
- uchar sysclk;
-
- if ((bcsr->bd_status & 0x80) == 0x80) /* bd_rev valid ? */
- sysclk = (bcsr->bd_rev & 0x18) >> 3;
- else
- sysclk = 0x00;
-
- switch (sysclk)
- {
- case 0x00:
- temp = 50000000;
- break;
-
- case 0x01:
- temp = 80000000;
- break;
-
- default:
- temp = 50000000;
- break;
- }
-
- return (temp);
-
-}
-
-
-/* ------------------------------------------------------------------------- */
-
-unsigned long ip860_get_dram_size(void)
-{
- volatile ip860_bcsr_t *bcsr = (ip860_bcsr_t *)BCSR_BASE;
- ulong temp;
- uchar dram_size;
-
- if ((bcsr->bd_status & 0x80) == 0x80) /* bd_rev valid ? */
- dram_size = (bcsr->bd_rev & 0xE0) >> 5;
- else
- dram_size = 0x00; /* default is 16 MB */
-
- switch (dram_size)
- {
- case 0x00:
- temp = 16;
- break;
-
- case 0x01:
- temp = 32;
- break;
-
- default:
- temp = 16;
- break;
- }
-
- return (temp);
-
-}
-
-/* ------------------------------------------------------------------------- */
diff --git a/board/ip860/u-boot.lds.debug b/board/ip860/u-boot.lds.debug
deleted file mode 100644
index e561bb4..0000000
--- a/board/ip860/u-boot.lds.debug
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- arch/powerpc/lib/ppcstring.o (.text)
- arch/powerpc/cpu/mpc8xx/interrupts.o (.text)
- arch/powerpc/lib/time.o (.text)
- arch/powerpc/lib/ticks.o (.text)
-/**
- . = env_offset;
- common/env_embedded.o(.text)
-**/
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
diff --git a/configs/IP860_defconfig b/configs/IP860_defconfig
deleted file mode 100644
index feb243d..0000000
--- a/configs/IP860_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_8xx=y
-CONFIG_TARGET_IP860=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 252b607..0e39857 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+IP860 powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
IVML24 powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
IVMS8 powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
lwmon powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
diff --git a/include/commproc.h b/include/commproc.h
index 6e0a233..c53482c 100644
--- a/include/commproc.h
+++ b/include/commproc.h
@@ -484,34 +484,6 @@ typedef struct scc_enet {
#endif
-/*** IP860 **********************************************************/
-
-#if defined(CONFIG_IP860)
-/* Bits in parallel I/O port registers that have to be set/cleared
- * to configure the pins for SCC1 use.
- */
-#define PROFF_ENET PROFF_SCC1
-#define CPM_CR_ENET CPM_CR_CH_SCC1
-#define SCC_ENET 0
-#define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */
-#define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */
-#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
-#define PA_ENET_TCLK ((ushort)0x0100) /* PA 7 */
-
-#define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */
-#define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */
-#define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */
-
-#define PB_ENET_RESET (uint)0x00000008 /* PB 28 */
-#define PB_ENET_JABD (uint)0x00000004 /* PB 29 */
-
-/* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to
- * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
- */
-#define SICR_ENET_MASK ((uint)0x000000ff)
-#define SICR_ENET_CLKRT ((uint)0x0000002C)
-#endif /* CONFIG_IP860 */
-
/*** KM8XX *********************************************************/
/* The KM8XX Service Module uses SCC3 for Ethernet */
diff --git a/include/configs/IP860.h b/include/configs/IP860.h
deleted file mode 100644
index 97eda58..0000000
--- a/include/configs/IP860.h
+++ /dev/null
@@ -1,438 +0,0 @@
-/*
- * (C) Copyright 2000-2005
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
-#define CONFIG_IP860 1 /* ...on a IP860 board */
-
-#define CONFIG_SYS_TEXT_BASE 0x10000000
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
-
-#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#define CONFIG_BAUDRATE 9600
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" \
-"\0load=tftp \"/tftpboot/u-boot.bin\"\0update=protect off 1:0;era 1:0;cp.b 100000 10000000 ${filesize}\0"
-
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND \
- "bootp; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
- "bootm"
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-
-/* enable I2C and select the hardware/software driver */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED 50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define PB_SCL 0x00000020 /* PB 26 */
-#define PB_SDA 0x00000010 /* PB 27 */
-
-#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
-#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
-#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
-#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
-#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
- else immr->im_cpm.cp_pbdat &= ~PB_SDA
-#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
- else immr->im_cpm.cp_pbdat &= ~PB_SCL
-#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
-
-# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C16 */
-# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */
-
-#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BEDBUG
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_SNTP
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
-
-#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xF1000000 /* Non-standard value!! */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0x10000000
-#ifdef DEBUG
-#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
-#else
-#if 0 /* need more space for I2C tests */
-#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
-#else
-#define CONFIG_SYS_MONITOR_LEN (256 << 10)
-#endif
-#endif
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 124 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#undef CONFIG_ENV_IS_IN_FLASH
-#undef CONFIG_ENV_IS_IN_NVRAM
-#undef CONFIG_ENV_IS_IN_NVRAM
-#undef DEBUG_I2C
-#define CONFIG_ENV_IS_IN_EEPROM
-
-#ifdef CONFIG_ENV_IS_IN_NVRAM
-#define CONFIG_ENV_ADDR 0x20000000 /* use SRAM */
-#define CONFIG_ENV_SIZE (16<<10) /* use 16 kB */
-#endif /* CONFIG_ENV_IS_IN_NVRAM */
-
-#ifdef CONFIG_ENV_IS_IN_EEPROM
-#define CONFIG_ENV_OFFSET 512 /* Leave 512 bytes free for other data */
-#define CONFIG_ENV_SIZE 1536 /* Use remaining space */
-#endif /* CONFIG_ENV_IS_IN_EEPROM */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-#define CONFIG_SYS_DELAYED_ICACHE 1 /* enable ICache not before
- * running in RAM.
- */
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- * +0x0004
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- * +0x0000 => 0x80600800
- */
-#define CONFIG_SYS_SIUMCR (SIUMCR_EARB | SIUMCR_EARP0 | \
- SIUMCR_DBGC11 | SIUMCR_MLRC10)
-
-/*-----------------------------------------------------------------------
- * Clock Setting - get clock frequency from Board Revision Register
- *-----------------------------------------------------------------------
- */
-#ifndef __ASSEMBLY__
-extern unsigned long ip860_get_clk_freq (void);
-#endif
-#define CONFIG_8xx_GCLK_FREQ ip860_get_clk_freq()
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- * +0x0200 => 0x00C2
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- * +0x0240 => 0x0082
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit, set PLL multiplication factor !
- */
-/* +0x0286 => was: 0x0000D000 */
-#define CONFIG_SYS_PLPRCR \
- ( PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \
- /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
- PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \
- )
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK SCCR_EBDF11
-#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_TBS | \
- SCCR_RTDIV | SCCR_RTSEL | \
- /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
- SCCR_EBDF00 | SCCR_DFSYNC00 | \
- SCCR_DFBRG00 | SCCR_DFNL000 | \
- SCCR_DFNH000)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register 11-27
- *-----------------------------------------------------------------------
- */
-/* +0x0220 => 0x00C3 */
-#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration Register 19-4
- *-----------------------------------------------------------------------
- */
-/* +0x09C4 => TIMEP=1 */
-#define CONFIG_SYS_RCCR 0x0100
-
-/*-----------------------------------------------------------------------
- * RMDS - RISC Microcode Development Support Control Register
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RMDS 0
-
-/*-----------------------------------------------------------------------
- * DER - Debug Event Register
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_DER 0
-
-/*
- * Init Memory Controller:
- */
-
-/*
- * MAMR settings for SDRAM - 16-14
- * => 0xC3804114
- */
-
-/* periodic timer for refresh */
-#define CONFIG_SYS_MAMR_PTA 0xC3
-
-#define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-/*
- * BR1 and OR1 (FLASH)
- */
-#define FLASH_BASE 0x10000000 /* FLASH bank #0 */
-
-/* used to re-map FLASH
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-/* allow for max 8 MB of Flash */
-#define CONFIG_SYS_REMAP_OR_AM 0xFF800000 /* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
-
-#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_6_CLK)
-
-#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-/* 16 bit, bank valid */
-#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE & BR_BA_MSK) | BR_PS_32 | BR_V )
-
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
-#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_BR0_PRELIM
-
-/*
- * BR2/OR2 - SDRAM
- */
-#define SDRAM_BASE 0x00000000 /* SDRAM bank */
-#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */
-#define SDRAM_TIMING 0x00000A00 /* SDRAM-Timing */
-
-#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */
-
-#define CONFIG_SYS_OR2 (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
-#define CONFIG_SYS_BR2 ((SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-/*
- * BR3/OR3 - SRAM (16 bit)
- */
-#define SRAM_BASE 0x20000000
-#define CONFIG_SYS_OR3 0xFFF00130 /* BI/SCY = 5/TRLX (internal) */
-#define CONFIG_SYS_BR3 ((SRAM_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
-#define SRAM_SIZE (1 + (~(CONFIG_SYS_OR3 & BR_BA_MSK)))
-#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR3 /* Make sure to map early */
-#define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_BR3 /* in case it's used for ENV */
-#define CONFIG_SYS_SRAM_BASE SRAM_BASE
-#define CONFIG_SYS_SRAM_SIZE SRAM_SIZE
-
-/*
- * BR4/OR4 - Board Control & Status (8 bit)
- */
-#define BCSR_BASE 0xFC000000
-#define CONFIG_SYS_OR4 0xFFFF0120 /* BI (internal) */
-#define CONFIG_SYS_BR4 ((BCSR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
-
-/*
- * BR5/OR5 - IP Slot A/B (16 bit)
- */
-#define IP_SLOT_BASE 0x40000000
-#define CONFIG_SYS_OR5 0xFE00010C /* SETA/TRLX/BI/ SCY=0 (external) */
-#define CONFIG_SYS_BR5 ((IP_SLOT_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
-
-/*
- * BR6/OR6 - VME STD (16 bit)
- */
-#define VME_STD_BASE 0xFE000000
-#define CONFIG_SYS_OR6 0xFF00010C /* SETA/TRLX/BI/SCY=0 (external) */
-#define CONFIG_SYS_BR6 ((VME_STD_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
-
-/*
- * BR7/OR7 - SHORT I/O + RTC + IACK (16 bit)
- */
-#define VME_SHORT_BASE 0xFF000000
-#define CONFIG_SYS_OR7 0xFF00010C /* SETA/TRLX/BI/ SCY=0 (external) */
-#define CONFIG_SYS_BR7 ((VME_SHORT_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
-
-/*-----------------------------------------------------------------------
- * Board Control and Status Region:
- *-----------------------------------------------------------------------
- */
-#ifndef __ASSEMBLY__
-typedef struct ip860_bcsr_s {
- unsigned char shmem_addr; /* +00 shared memory address register */
- unsigned char reserved0;
- unsigned char mbox_addr; /* +02 mailbox address register */
- unsigned char reserved1;
- unsigned char vme_int_mask; /* +04 VME Bus interrupt mask register */
- unsigned char reserved2;
- unsigned char vme_int_pend; /* +06 VME interrupt pending register */
- unsigned char reserved3;
- unsigned char bd_int_mask; /* +08 board interrupt mask register */
- unsigned char reserved4;
- unsigned char bd_int_pend; /* +0A board interrupt pending register */
- unsigned char reserved5;
- unsigned char bd_ctrl; /* +0C board control register */
- unsigned char reserved6;
- unsigned char bd_status; /* +0E board status register */
- unsigned char reserved7;
- unsigned char vme_irq; /* +10 VME interrupt request register */
- unsigned char reserved8;
- unsigned char vme_ivec; /* +12 VME interrupt vector register */
- unsigned char reserved9;
- unsigned char cli_mbox; /* +14 clear mailbox irq */
- unsigned char reservedA;
- unsigned char rtc; /* +16 RTC control register */
- unsigned char reservedB;
- unsigned char mbox_data; /* +18 mailbox read/write register */
- unsigned char reservedC;
- unsigned char wd_trigger; /* +1A Watchdog trigger register */
- unsigned char reservedD;
- unsigned char rmw_req; /* +1C RMW request register */
- unsigned char reservedE;
- unsigned char bd_rev; /* +1E Board Revision register */
-} ip860_bcsr_t;
-#endif /* __ASSEMBLY__ */
-
-/*-----------------------------------------------------------------------
- * Board Control Register: bd_ctrl (Offset 0x0C)
- *-----------------------------------------------------------------------
- */
-#define BD_CTRL_IPLSE 0x80 /* IP Slot Long Select Enable */
-#define BD_CTRL_WDOGE 0x40 /* Watchdog Enable */
-#define BD_CTRL_FLWE 0x20 /* Flash Write Enable */
-#define BD_CTRL_RWDN 0x10 /* VMEBus Requester Release When Done Enable */
-
-#endif /* __CONFIG_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [U-Boot] [PATCH 12/26] mpc8xx: remove ESTEEM192E board support
2014-12-15 14:26 [U-Boot] [PATCH 0/26] Start removing non-generic boards Masahiro Yamada
` (10 preceding siblings ...)
2014-12-15 14:26 ` [U-Boot] [PATCH 11/26] mpc8xx: remove IP860 " Masahiro Yamada
@ 2014-12-15 14:26 ` Masahiro Yamada
2015-01-05 18:20 ` Tom Rini
2014-12-15 14:26 ` [U-Boot] [PATCH 13/26] powerpc: remove cogent_8xx, cogent_mpc8260 " Masahiro Yamada
` (15 subsequent siblings)
27 siblings, 1 reply; 55+ messages in thread
From: Masahiro Yamada @ 2014-12-15 14:26 UTC (permalink / raw)
To: u-boot
This board is still a non-generic board.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Conn Clark <clark@esteem.com>
---
arch/powerpc/cpu/mpc8xx/Kconfig | 4 -
board/esteem192e/Kconfig | 9 -
board/esteem192e/MAINTAINERS | 6 -
board/esteem192e/Makefile | 8 -
board/esteem192e/esteem192e.c | 225 --------
board/esteem192e/flash.c | 1119 ---------------------------------------
board/esteem192e/u-boot.lds | 90 ----
configs/ESTEEM192E_defconfig | 3 -
doc/README.scrapyard | 1 +
include/commproc.h | 28 -
include/configs/ESTEEM192E.h | 292 ----------
11 files changed, 1 insertion(+), 1784 deletions(-)
delete mode 100644 board/esteem192e/Kconfig
delete mode 100644 board/esteem192e/MAINTAINERS
delete mode 100644 board/esteem192e/Makefile
delete mode 100644 board/esteem192e/esteem192e.c
delete mode 100644 board/esteem192e/flash.c
delete mode 100644 board/esteem192e/u-boot.lds
delete mode 100644 configs/ESTEEM192E_defconfig
delete mode 100644 include/configs/ESTEEM192E.h
diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig
index 45e7d7e..428a129 100644
--- a/arch/powerpc/cpu/mpc8xx/Kconfig
+++ b/arch/powerpc/cpu/mpc8xx/Kconfig
@@ -10,9 +10,6 @@ choice
config TARGET_COGENT_MPC8XX
bool "Support cogent_mpc8xx"
-config TARGET_ESTEEM192E
- bool "Support ESTEEM192E"
-
config TARGET_TQM823L
bool "Support TQM823L"
@@ -52,7 +49,6 @@ config TARGET_TQM885D
endchoice
source "board/cogent/Kconfig"
-source "board/esteem192e/Kconfig"
source "board/tqc/tqm8xx/Kconfig"
endmenu
diff --git a/board/esteem192e/Kconfig b/board/esteem192e/Kconfig
deleted file mode 100644
index f895bc4..0000000
--- a/board/esteem192e/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_ESTEEM192E
-
-config SYS_BOARD
- default "esteem192e"
-
-config SYS_CONFIG_NAME
- default "ESTEEM192E"
-
-endif
diff --git a/board/esteem192e/MAINTAINERS b/board/esteem192e/MAINTAINERS
deleted file mode 100644
index 8d6634c..0000000
--- a/board/esteem192e/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-ESTEEM192E BOARD
-M: Conn Clark <clark@esteem.com>
-S: Maintained
-F: board/esteem192e/
-F: include/configs/ESTEEM192E.h
-F: configs/ESTEEM192E_defconfig
diff --git a/board/esteem192e/Makefile b/board/esteem192e/Makefile
deleted file mode 100644
index 55d80b6..0000000
--- a/board/esteem192e/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = esteem192e.o flash.o
diff --git a/board/esteem192e/esteem192e.c b/board/esteem192e/esteem192e.c
deleted file mode 100644
index b54c614..0000000
--- a/board/esteem192e/esteem192e.c
+++ /dev/null
@@ -1,225 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Modified By Conn Clark to work with Esteem 192E 7/31/00
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-/* ------------------------------------------------------------------------- */
-
-#define _NOT_USED_ 0xFFFFFFFF
-
-const uint sdram_table[] = {
- /*
- * Single Read. (Offset 0 in UPMA RAM)
- *
- * active, NOP, read, precharge, NOP */
- 0x0F27CC04, 0x0EAECC04, 0x00B98C04, 0x00F74C00,
- 0x11FFCC05, /* last */
- /*
- * SDRAM Initialization (offset 5 in UPMA RAM)
- *
- * This is no UPM entry point. The following definition uses
- * the remaining space to establish an initialization
- * sequence, which is executed by a RUN command.
- * NOP, Program
- */
- 0x0F0A8C34, 0x1F354C37, /* last */
-
- _NOT_USED_, /* Not used */
-
- /*
- * Burst Read. (Offset 8 in UPMA RAM)
- * active, NOP, read, NOP, NOP, NOP, NOP, NOP */
- 0x0F37CC04, 0x0EFECC04, 0x00FDCC04, 0x00FFCC00,
- 0x00FFCC00, 0x01FFCC00, 0x0FFFCC00, 0x1FFFCC05, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Single Write. (Offset 18 in UPMA RAM)
- * active, NOP, write, NOP, precharge, NOP */
- 0x0F27CC04, 0x0EAE8C00, 0x01BD4C04, 0x0FFB8C04,
- 0x0FF74C04, 0x1FFFCC05, /* last */
- _NOT_USED_, _NOT_USED_,
- /*
- * Burst Write. (Offset 20 in UPMA RAM)
- * active, NOP, write, NOP, NOP, NOP, NOP, NOP */
- 0x0F37CC04, 0x0EFE8C00, 0x00FD4C00, 0x00FFCC00,
- 0x00FFCC00, 0x01FFCC04, 0x0FFFCC04, 0x1FFFCC05, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Refresh (Offset 30 in UPMA RAM)
- * precharge, NOP, auto_ref, NOP, NOP, NOP */
- 0x0FF74C34, 0x0FFACCB4, 0x0FF5CC34, 0x0FFFCC34,
- 0x0FFFCCB4, 0x1FFFCC35, /* last */
- _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Exception. (Offset 3c in UPMA RAM)
- */
- 0x0FFB8C00, 0x1FF74C03, /* last */
- _NOT_USED_, _NOT_USED_
-};
-
-/* ------------------------------------------------------------------------- */
-
-
-/*
- * Check Board Identity:
- */
-
-int checkboard (void)
-{
- puts ("Board: Esteem 192E\n");
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- long int size_b0, size_b1;
-
- /*
- * Explain frequency of refresh here
- */
-
- memctl->memc_mptpr = 0x0200; /* divide by 32 */
-
- memctl->memc_mamr = 0x18003112; /*CONFIG_SYS_MAMR_8COL; */ /* 0x18005112 TODO: explain here */
-
- upmconfig (UPMA, (uint *) sdram_table,
- sizeof (sdram_table) / sizeof (uint));
-
- /*
- * Map cs 2 and 3 to the SDRAM banks 0 and 1 at
- * preliminary addresses - these have to be modified after the
- * SDRAM size has been determined.
- */
-
- memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; /* not defined yet */
- memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
-
- memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
- memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
-
-
- /* perform SDRAM initializsation sequence */
- memctl->memc_mar = 0x00000088;
- memctl->memc_mcr = 0x80004830; /* SDRAM bank 0 execute 8 refresh */
- memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
-
- memctl->memc_mcr = 0x80006830; /* SDRAM bank 1 execute 8 refresh */
- memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */
-
- memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; /* 0x18803112 start refresh timer TODO: explain here */
-
-/* printf ("banks 0 and 1 are programed\n"); */
-
- /*
- * Check Bank 0 Memory Size for re-configuration
- *
- */
- size_b0 = get_ram_size ( (long *)SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
- size_b1 = get_ram_size ( (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
-
- printf ("\nbank 0 size %lu\nbank 1 size %lu\n", size_b0, size_b1);
-
-/* printf ("bank 1 size %u\n",size_b1); */
-
- if (size_b1 == 0) {
- /*
- * Adjust refresh rate if bank 0 isn't stuffed
- */
- memctl->memc_mptpr = 0x0400; /* divide by 64 */
- memctl->memc_br3 &= 0x0FFFFFFFE;
-
- /*
- * Adjust OR2 for size of bank 0
- */
- memctl->memc_or2 |= 7 * size_b0;
- } else {
- if (size_b0 < size_b1) {
- memctl->memc_br2 &= 0x00007FFE;
- memctl->memc_br3 &= 0x00007FFF;
-
- /*
- * Adjust OR3 for size of bank 1
- */
- memctl->memc_or3 |= 15 * size_b1;
-
- /*
- * Adjust OR2 for size of bank 0
- */
- memctl->memc_or2 |= 15 * size_b0;
- memctl->memc_br2 += (size_b1 + 1);
- } else {
- memctl->memc_br3 &= 0x00007FFE;
-
- /*
- * Adjust OR2 for size of bank 0
- */
- memctl->memc_or2 |= 15 * size_b0;
-
- /*
- * Adjust OR3 for size of bank 1
- */
- memctl->memc_or3 |= 15 * size_b1;
- memctl->memc_br3 += (size_b0 + 1);
- }
- }
-
- /* before leaving set all unused i/o pins to outputs */
-
- /*
- * --*Unused Pin List*--
- *
- * group/port bit number
- * IP_B 0,1,3,4,5 Taken care of in pcmcia-cs-x.x.xx
- * PA 5,7,8,9,14,15
- * PB 22,23,31
- * PC 4,5,6,7,10,11,12,13,14,15
- * PD 5,6,7
- *
- */
-
- /*
- * --*Pin Used for I/O List*--
- *
- * port input bit number output bit number either
- * PB 18,26,27
- * PD 3,4 8,9,10,11,12,13,14,15
- *
- */
-
- immap->im_ioport.iop_papar &= ~0x05C3; /* set pins as io */
- immap->im_ioport.iop_padir |= 0x05C3; /* set pins as output */
- immap->im_ioport.iop_paodr &= 0x0008; /* config pins 9 & 14 as normal outputs */
- immap->im_ioport.iop_padat |= 0x05C3; /* set unused pins as high */
-
- immap->im_cpm.cp_pbpar &= ~0x00001331; /* set unused port b pins as io */
- immap->im_cpm.cp_pbdir |= 0x00001331; /* set unused port b pins as output */
- immap->im_cpm.cp_pbodr &= ~0x00001331; /* config bits 18,22,23,26,27 & 31 as normal outputs */
- immap->im_cpm.cp_pbdat |= 0x00001331; /* set T/E LED, /NV_CS, & /POWER_ADJ_CS and the rest to a high */
-
- immap->im_ioport.iop_pcpar &= ~0x0F3F; /* set unused port c pins as io */
- immap->im_ioport.iop_pcdir |= 0x0F3F; /* set unused port c pins as output */
- immap->im_ioport.iop_pcso &= ~0x0F3F; /* clear special purpose bit for unused port c pins for clarity */
- immap->im_ioport.iop_pcdat |= 0x0F3F; /* set unused port c pins high */
-
- immap->im_ioport.iop_pdpar &= 0xE000; /* set pins as io */
- immap->im_ioport.iop_pddir &= 0xE000; /* set bit 3 & 4 as inputs */
- immap->im_ioport.iop_pddir |= 0x07FF; /* set bits 5 - 15 as outputs */
- immap->im_ioport.iop_pddat = 0x0055; /* set alternating pattern on test port */
-
- return (size_b0 + size_b1);
-}
diff --git a/board/esteem192e/flash.c b/board/esteem192e/flash.c
deleted file mode 100644
index a121104..0000000
--- a/board/esteem192e/flash.c
+++ /dev/null
@@ -1,1119 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-#ifdef CONFIG_FLASH_16BIT
-#define FLASH_WORD_SIZE unsigned short
-#define FLASH_ID_MASK 0xFFFF
-#else
-#define FLASH_WORD_SIZE unsigned long
-#define FLASH_ID_MASK 0xFFFFFFFF
-#endif
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-
-ulong flash_get_size (volatile FLASH_WORD_SIZE * addr, flash_info_t * info);
-
-#ifndef CONFIG_FLASH_16BIT
-static int write_word (flash_info_t * info, ulong dest, ulong data);
-#else
-static int write_short (flash_info_t * info, ulong dest, ushort data);
-#endif
-/*int flash_write (uchar *, ulong, ulong); */
-/*flash_info_t *addr2info (ulong); */
-
-static void flash_get_offsets (ulong base, flash_info_t * info);
-
-/*-----------------------------------------------------------------------
- */
-unsigned long flash_init (void)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- unsigned long size_b0, size_b1;
- int i;
-
- /* Init: no FLASHes known */
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size_b0 =
- flash_get_size ((volatile FLASH_WORD_SIZE *)
- FLASH_BASE0_PRELIM, &flash_info[0]);
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", size_b0, size_b0 << 20);
- }
-
- size_b1 =
- flash_get_size ((volatile FLASH_WORD_SIZE *)
- FLASH_BASE1_PRELIM, &flash_info[1]);
-
- if (size_b1 > size_b0) {
- printf ("## ERROR: "
- "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
- size_b1, size_b1 << 20, size_b0, size_b0 << 20);
- flash_info[0].flash_id = FLASH_UNKNOWN;
- flash_info[1].flash_id = FLASH_UNKNOWN;
- flash_info[0].sector_count = -1;
- flash_info[1].sector_count = -1;
- flash_info[0].size = 0;
- flash_info[1].size = 0;
- return (0);
- }
-
- /* Remap FLASH according to real size */
- memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
- memctl->memc_br0 = CONFIG_SYS_FLASH_BASE | 0x00000801; /* (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; */
-
- /* Re-do sizing to get full correct info */
-
- size_b0 = flash_get_size ((volatile FLASH_WORD_SIZE *) CONFIG_SYS_FLASH_BASE,
- &flash_info[0]);
- flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- (void) flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
- &flash_info[0]);
-#endif
-
- if (size_b1) {
- memctl->memc_or1 =
- CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
- memctl->memc_br1 =
- (CONFIG_SYS_FLASH_BASE | 0x00000801) + (size_b0 & BR_BA_MSK);
- /*((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) |
- BR_MS_GPCM | BR_V; */
-
- /* Re-do sizing to get full correct info */
- size_b1 =
- flash_get_size ((volatile FLASH_WORD_SIZE
- *) (CONFIG_SYS_FLASH_BASE + size_b0),
- &flash_info[1]);
-
- flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]);
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- (void) flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + monitor_flash_len -
- 1, &flash_info[1]);
-#endif
- } else {
- memctl->memc_br1 = 0; /* invalidate bank */
-
- flash_info[1].flash_id = FLASH_UNKNOWN;
- flash_info[1].sector_count = -1;
- }
-
- flash_info[0].size = size_b0;
- flash_info[1].size = size_b1;
-
- return (size_b0 + size_b1);
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t * info)
-{
- int i;
-
- /* set up sector start adress table */
- if (info->flash_id & FLASH_BTYPE) {
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
-
-#ifndef CONFIG_FLASH_16BIT
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00008000;
- info->start[3] = base + 0x0000C000;
- info->start[4] = base + 0x00010000;
- info->start[5] = base + 0x00014000;
- info->start[6] = base + 0x00018000;
- info->start[7] = base + 0x0001C000;
- for (i = 8; i < info->sector_count; i++) {
- info->start[i] =
- base + (i * 0x00020000) - 0x000E0000;
- }
- } else {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00008000;
- info->start[2] = base + 0x0000C000;
- info->start[3] = base + 0x00010000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] =
- base + (i * 0x00020000) - 0x00060000;
- }
- }
-#else
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00002000;
- info->start[2] = base + 0x00004000;
- info->start[3] = base + 0x00006000;
- info->start[4] = base + 0x00008000;
- info->start[5] = base + 0x0000A000;
- info->start[6] = base + 0x0000C000;
- info->start[7] = base + 0x0000E000;
- for (i = 8; i < info->sector_count; i++) {
- info->start[i] =
- base + (i * 0x00010000) - 0x00070000;
- }
- } else {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] =
- base + (i * 0x00010000) - 0x00030000;
- }
- }
-#endif
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
-
-#ifndef CONFIG_FLASH_16BIT
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00008000;
- info->start[i--] = base + info->size - 0x0000C000;
- info->start[i--] = base + info->size - 0x00010000;
- info->start[i--] = base + info->size - 0x00014000;
- info->start[i--] = base + info->size - 0x00018000;
- info->start[i--] = base + info->size - 0x0001C000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00020000;
- }
-
- } else {
-
- info->start[i--] = base + info->size - 0x00008000;
- info->start[i--] = base + info->size - 0x0000C000;
- info->start[i--] = base + info->size - 0x00010000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00020000;
- }
- }
-#else
- info->start[i--] = base + info->size - 0x00002000;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- info->start[i--] = base + info->size - 0x0000A000;
- info->start[i--] = base + info->size - 0x0000C000;
- info->start[i--] = base + info->size - 0x0000E000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
-
- } else {
-
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- }
-#endif
- }
-
-
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
- int i;
- uchar *boottype;
- uchar botboot[] = ", bottom boot sect)\n";
- uchar topboot[] = ", top boot sector)\n";
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD:
- printf ("AMD ");
- break;
- case FLASH_MAN_FUJ:
- printf ("FUJITSU ");
- break;
- case FLASH_MAN_SST:
- printf ("SST ");
- break;
- case FLASH_MAN_STM:
- printf ("STM ");
- break;
- case FLASH_MAN_INTEL:
- printf ("INTEL ");
- break;
- default:
- printf ("Unknown Vendor ");
- break;
- }
-
- if (info->flash_id & 0x0001) {
- boottype = botboot;
- } else {
- boottype = topboot;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM400B:
- printf ("AM29LV400B (4 Mbit%s", boottype);
- break;
- case FLASH_AM400T:
- printf ("AM29LV400T (4 Mbit%s", boottype);
- break;
- case FLASH_AM800B:
- printf ("AM29LV800B (8 Mbit%s", boottype);
- break;
- case FLASH_AM800T:
- printf ("AM29LV800T (8 Mbit%s", boottype);
- break;
- case FLASH_AM160B:
- printf ("AM29LV160B (16 Mbit%s", boottype);
- break;
- case FLASH_AM160T:
- printf ("AM29LV160T (16 Mbit%s", boottype);
- break;
- case FLASH_AM320B:
- printf ("AM29LV320B (32 Mbit%s", boottype);
- break;
- case FLASH_AM320T:
- printf ("AM29LV320T (32 Mbit%s", boottype);
- break;
- case FLASH_INTEL800B:
- printf ("INTEL28F800B (8 Mbit%s", boottype);
- break;
- case FLASH_INTEL800T:
- printf ("INTEL28F800T (8 Mbit%s", boottype);
- break;
- case FLASH_INTEL160B:
- printf ("INTEL28F160B (16 Mbit%s", boottype);
- break;
- case FLASH_INTEL160T:
- printf ("INTEL28F160T (16 Mbit%s", boottype);
- break;
- case FLASH_INTEL320B:
- printf ("INTEL28F320B (32 Mbit%s", boottype);
- break;
- case FLASH_INTEL320T:
- printf ("INTEL28F320T (32 Mbit%s", boottype);
- break;
-
-#if 0 /* enable when devices are available */
-
- case FLASH_INTEL640B:
- printf ("INTEL28F640B (64 Mbit%s", boottype);
- break;
- case FLASH_INTEL640T:
- printf ("INTEL28F640T (64 Mbit%s", boottype);
- break;
-#endif
-
- default:
- printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i], info->protect[i] ? " (RO)" : " ");
- }
- printf ("\n");
- return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-ulong flash_get_size (volatile FLASH_WORD_SIZE * addr, flash_info_t * info)
-{
- short i;
- ulong base = (ulong) addr;
- FLASH_WORD_SIZE value;
-
- /* Write auto select command: read Manufacturer ID */
-
-
-#ifndef CONFIG_FLASH_16BIT
-
- /*
- * Note: if it is an AMD flash and the word at addr[0000]
- * is 0x00890089 this routine will think it is an Intel
- * flash device and may(most likely) cause trouble.
- */
-
- addr[0x0000] = 0x00900090;
- if (addr[0x0000] != 0x00890089) {
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
- addr[0x0555] = 0x00900090;
-#else
-
- /*
- * Note: if it is an AMD flash and the word at addr[0000]
- * is 0x0089 this routine will think it is an Intel
- * flash device and may(most likely) cause trouble.
- */
-
- addr[0x0000] = 0x0090;
-
- if (addr[0x0000] != 0x0089) {
- addr[0x0555] = 0x00AA;
- addr[0x02AA] = 0x0055;
- addr[0x0555] = 0x0090;
-#endif
- }
- value = addr[0];
-
- switch (value) {
- case (AMD_MANUFACT & FLASH_ID_MASK):
- info->flash_id = FLASH_MAN_AMD;
- break;
- case (FUJ_MANUFACT & FLASH_ID_MASK):
- info->flash_id = FLASH_MAN_FUJ;
- break;
- case (STM_MANUFACT & FLASH_ID_MASK):
- info->flash_id = FLASH_MAN_STM;
- break;
- case (SST_MANUFACT & FLASH_ID_MASK):
- info->flash_id = FLASH_MAN_SST;
- break;
- case (INTEL_MANUFACT & FLASH_ID_MASK):
- info->flash_id = FLASH_MAN_INTEL;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
-
- }
-
- value = addr[1]; /* device ID */
-
- switch (value) {
-
- case (AMD_ID_LV400T & FLASH_ID_MASK):
- info->flash_id += FLASH_AM400T;
- info->sector_count = 11;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (AMD_ID_LV400B & FLASH_ID_MASK):
- info->flash_id += FLASH_AM400B;
- info->sector_count = 11;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (AMD_ID_LV800T & FLASH_ID_MASK):
- info->flash_id += FLASH_AM800T;
- info->sector_count = 19;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (AMD_ID_LV800B & FLASH_ID_MASK):
- info->flash_id += FLASH_AM800B;
- info->sector_count = 19;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (AMD_ID_LV160T & FLASH_ID_MASK):
- info->flash_id += FLASH_AM160T;
- info->sector_count = 35;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case (AMD_ID_LV160B & FLASH_ID_MASK):
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00400000;
- break; /* => 4 MB */
-#if 0 /* enable when device IDs are available */
- case (AMD_ID_LV320T & FLASH_ID_MASK):
- info->flash_id += FLASH_AM320T;
- info->sector_count = 67;
- info->size = 0x00800000;
- break; /* => 8 MB */
-
- case (AMD_ID_LV320B & FLASH_ID_MASK):
- info->flash_id += FLASH_AM320B;
- info->sector_count = 67;
- info->size = 0x00800000;
- break; /* => 8 MB */
-#endif
-
- case (INTEL_ID_28F800B3T & FLASH_ID_MASK):
- info->flash_id += FLASH_INTEL800T;
- info->sector_count = 23;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (INTEL_ID_28F800B3B & FLASH_ID_MASK):
- info->flash_id += FLASH_INTEL800B;
- info->sector_count = 23;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (INTEL_ID_28F160B3T & FLASH_ID_MASK):
- info->flash_id += FLASH_INTEL160T;
- info->sector_count = 39;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case (INTEL_ID_28F160B3B & FLASH_ID_MASK):
- info->flash_id += FLASH_INTEL160B;
- info->sector_count = 39;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case (INTEL_ID_28F320B3T & FLASH_ID_MASK):
- info->flash_id += FLASH_INTEL320T;
- info->sector_count = 71;
- info->size = 0x00800000;
- break; /* => 8 MB */
-
- case (INTEL_ID_28F320B3B & FLASH_ID_MASK):
- info->flash_id += FLASH_AM320B;
- info->sector_count = 71;
- info->size = 0x00800000;
- break; /* => 8 MB */
-
-#if 0 /* enable when devices are available */
- case (INTEL_ID_28F320B3T & FLASH_ID_MASK):
- info->flash_id += FLASH_INTEL320T;
- info->sector_count = 135;
- info->size = 0x01000000;
- break; /* => 16 MB */
-
- case (INTEL_ID_28F320B3B & FLASH_ID_MASK):
- info->flash_id += FLASH_AM320B;
- info->sector_count = 135;
- info->size = 0x01000000;
- break; /* => 16 MB */
-#endif
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
-
- }
-
- /* set up sector start adress table */
- if (info->flash_id & FLASH_BTYPE) {
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
-
-#ifndef CONFIG_FLASH_16BIT
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00008000;
- info->start[3] = base + 0x0000C000;
- info->start[4] = base + 0x00010000;
- info->start[5] = base + 0x00014000;
- info->start[6] = base + 0x00018000;
- info->start[7] = base + 0x0001C000;
- for (i = 8; i < info->sector_count; i++) {
- info->start[i] =
- base + (i * 0x00020000) - 0x000E0000;
- }
- } else {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00008000;
- info->start[2] = base + 0x0000C000;
- info->start[3] = base + 0x00010000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] =
- base + (i * 0x00020000) - 0x00060000;
- }
- }
-#else
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00002000;
- info->start[2] = base + 0x00004000;
- info->start[3] = base + 0x00006000;
- info->start[4] = base + 0x00008000;
- info->start[5] = base + 0x0000A000;
- info->start[6] = base + 0x0000C000;
- info->start[7] = base + 0x0000E000;
- for (i = 8; i < info->sector_count; i++) {
- info->start[i] =
- base + (i * 0x00010000) - 0x00070000;
- }
- } else {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] =
- base + (i * 0x00010000) - 0x00030000;
- }
- }
-#endif
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
-
-#ifndef CONFIG_FLASH_16BIT
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00008000;
- info->start[i--] = base + info->size - 0x0000C000;
- info->start[i--] = base + info->size - 0x00010000;
- info->start[i--] = base + info->size - 0x00014000;
- info->start[i--] = base + info->size - 0x00018000;
- info->start[i--] = base + info->size - 0x0001C000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00020000;
- }
-
- } else {
-
- info->start[i--] = base + info->size - 0x00008000;
- info->start[i--] = base + info->size - 0x0000C000;
- info->start[i--] = base + info->size - 0x00010000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00020000;
- }
- }
-#else
- info->start[i--] = base + info->size - 0x00002000;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- info->start[i--] = base + info->size - 0x0000A000;
- info->start[i--] = base + info->size - 0x0000C000;
- info->start[i--] = base + info->size - 0x0000E000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
-
- } else {
-
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- }
-#endif
- }
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- addr = (volatile FLASH_WORD_SIZE *) (info->start[i]);
- info->protect[i] = addr[2] & 1;
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- addr = (volatile FLASH_WORD_SIZE *) info->start[0];
- if ((info->flash_id & 0xFF00) == FLASH_MAN_INTEL) {
- *addr = (0x00F000F0 & FLASH_ID_MASK); /* reset bank */
- } else {
- *addr = (0x00FF00FF & FLASH_ID_MASK); /* reset bank */
- }
- }
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
-
- volatile FLASH_WORD_SIZE *addr =
- (volatile FLASH_WORD_SIZE *) (info->start[0]);
- int flag, prot, sect, l_sect, barf;
- ulong start, now, last;
- int rcode = 0;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id == FLASH_UNKNOWN) ||
- ((info->flash_id > FLASH_AMD_COMP) &&
- ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL))) {
- printf ("Can't erase unknown flash type - aborted\n");
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n", prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
- if (info->flash_id < FLASH_AMD_COMP) {
-#ifndef CONFIG_FLASH_16BIT
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
- addr[0x0555] = 0x00800080;
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
-#else
- addr[0x0555] = 0x00AA;
- addr[0x02AA] = 0x0055;
- addr[0x0555] = 0x0080;
- addr[0x0555] = 0x00AA;
- addr[0x02AA] = 0x0055;
-#endif
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = (volatile FLASH_WORD_SIZE *) (info->start[sect]);
- addr[0] = (0x00300030 & FLASH_ID_MASK);
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer (0);
- last = start;
- addr = (volatile FLASH_WORD_SIZE *) (info->start[l_sect]);
- while ((addr[0] & (0x00800080 & FLASH_ID_MASK)) !=
- (0x00800080 & FLASH_ID_MASK)) {
- if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- serial_putc ('.');
- last = now;
- }
- }
-
- DONE:
- /* reset to read mode */
- addr = (volatile FLASH_WORD_SIZE *) info->start[0];
- addr[0] = (0x00F000F0 & FLASH_ID_MASK); /* reset bank */
- } else {
-
-
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- barf = 0;
-#ifndef CONFIG_FLASH_16BIT
- addr = (vu_long *) (info->start[sect]);
- addr[0] = 0x00200020;
- addr[0] = 0x00D000D0;
- while (!(addr[0] & 0x00800080)); /* wait for error or finish */
- if (addr[0] & 0x003A003A) { /* check for error */
- barf = addr[0] & 0x003A0000;
- if (barf) {
- barf >>= 16;
- } else {
- barf = addr[0] & 0x0000003A;
- }
- }
-#else
- addr = (vu_short *) (info->start[sect]);
- addr[0] = 0x0020;
- addr[0] = 0x00D0;
- while (!(addr[0] & 0x0080)); /* wait for error or finish */
- if (addr[0] & 0x003A) /* check for error */
- barf = addr[0] & 0x003A;
-#endif
- if (barf) {
- printf ("\nFlash error in sector at %lx\n", (unsigned long) addr);
- if (barf & 0x0002)
- printf ("Block locked, not erased.\n");
- if ((barf & 0x0030) == 0x0030)
- printf ("Command Sequence error.\n");
- if ((barf & 0x0030) == 0x0020)
- printf ("Block Erase error.\n");
- if (barf & 0x0008)
- printf ("Vpp Low error.\n");
- rcode = 1;
- } else
- printf (".");
- l_sect = sect;
- }
- addr = (volatile FLASH_WORD_SIZE *) info->start[0];
- addr[0] = (0x00FF00FF & FLASH_ID_MASK); /* reset bank */
-
- }
-
- }
- printf (" done\n");
- return rcode;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
-#ifndef CONFIG_FLASH_16BIT
- ulong cp, wp, data;
- int l;
-#else
- ulong cp, wp;
- ushort data;
-#endif
- int i, rc;
-
-#ifndef CONFIG_FLASH_16BIT
-
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i = 0, cp = wp; i < l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
- for (; i < 4 && cnt > 0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt == 0 && i < 4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- if ((rc = write_word (info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i = 0; i < 4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word (info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i < 4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- return (write_word (info, wp, data));
-
-#else
- wp = (addr & ~1); /* get lower word aligned address */
-
- /*
- * handle unaligned start byte
- */
- if (addr - wp) {
- data = 0;
- data = (data << 8) | *src++;
- --cnt;
- if ((rc = write_short (info, wp, data)) != 0) {
- return (rc);
- }
- wp += 2;
- }
-
- /*
- * handle word aligned part
- */
-/* l = 0; used for debuging */
- while (cnt >= 2) {
- data = 0;
- for (i = 0; i < 2; ++i) {
- data = (data << 8) | *src++;
- }
-
-/* if(!l){
- printf("%x",data);
- l = 1;
- } used for debuging */
-
- if ((rc = write_short (info, wp, data)) != 0) {
- return (rc);
- }
- wp += 2;
- cnt -= 2;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i < 2; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- return (write_short (info, wp, data));
-
-
-#endif
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-#ifndef CONFIG_FLASH_16BIT
-static int write_word (flash_info_t * info, ulong dest, ulong data)
-{
- vu_long *addr = (vu_long *) (info->start[0]);
- ulong start, barf;
- int flag;
-
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((vu_long *) dest) & data) != data) {
- return (2);
- }
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- if (info->flash_id > FLASH_AMD_COMP) {
- /* AMD stuff */
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
- addr[0x0555] = 0x00A000A0;
- } else {
- /* intel stuff */
- *addr = 0x00400040;
- }
- *((vu_long *) dest) = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- /* data polling for D7 */
- start = get_timer (0);
-
- if (info->flash_id > FLASH_AMD_COMP) {
-
- while ((*((vu_long *) dest) & 0x00800080) !=
- (data & 0x00800080)) {
- if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
-
- } else {
-
- while (!(addr[0] & 0x00800080)) { /* wait for error or finish */
- if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
-
- if (addr[0] & 0x003A003A) { /* check for error */
- barf = addr[0] & 0x003A0000;
- if (barf) {
- barf >>= 16;
- } else {
- barf = addr[0] & 0x0000003A;
- }
- printf ("\nFlash write error at address %lx\n", (unsigned long) dest);
- if (barf & 0x0002)
- printf ("Block locked, not erased.\n");
- if (barf & 0x0010)
- printf ("Programming error.\n");
- if (barf & 0x0008)
- printf ("Vpp Low error.\n");
- return (2);
- }
-
-
- }
-
- return (0);
-
- }
-
-#else
-
-static int write_short (flash_info_t * info, ulong dest, ushort data)
-{
- vu_short *addr = (vu_short *) (info->start[0]);
- ulong start, barf;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((vu_short *) dest) & data) != data) {
- return (2);
- }
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- if (info->flash_id < FLASH_AMD_COMP) {
- /* AMD stuff */
- addr[0x0555] = 0x00AA;
- addr[0x02AA] = 0x0055;
- addr[0x0555] = 0x00A0;
- } else {
- /* intel stuff */
- *addr = 0x00D0;
- *addr = 0x0040;
- }
- *((vu_short *) dest) = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- /* data polling for D7 */
- start = get_timer (0);
-
- if (info->flash_id < FLASH_AMD_COMP) {
- /* AMD stuff */
- while ((*((vu_short *) dest) & 0x0080) != (data & 0x0080)) {
- if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
-
- } else {
- /* intel stuff */
- while (!(addr[0] & 0x0080)) { /* wait for error or finish */
- if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT)
- return (1);
- }
-
- if (addr[0] & 0x003A) { /* check for error */
- barf = addr[0] & 0x003A;
- printf ("\nFlash write error at address %lx\n",
- (unsigned long) dest);
- if (barf & 0x0002)
- printf ("Block locked, not erased.\n");
- if (barf & 0x0010)
- printf ("Programming error.\n");
- if (barf & 0x0008)
- printf ("Vpp Low error.\n");
- return (2);
- }
- *addr = 0x00B0;
- *addr = 0x0070;
- while (!(addr[0] & 0x0080)) { /* wait for error or finish */
- if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT)
- return (1);
- }
- *addr = 0x00FF;
- }
- return (0);
-}
-
-#endif
-/*-----------------------------------------------------------------------*/
diff --git a/board/esteem192e/u-boot.lds b/board/esteem192e/u-boot.lds
deleted file mode 100644
index 59a86bf..0000000
--- a/board/esteem192e/u-boot.lds
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text*)
- arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- net/built-in.o (.text*)
- board/esteem192e/built-in.o (.text*)
-
- . = env_offset;
- common/env_embedded.o (.text*)
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
diff --git a/configs/ESTEEM192E_defconfig b/configs/ESTEEM192E_defconfig
deleted file mode 100644
index e6279b8..0000000
--- a/configs/ESTEEM192E_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_8xx=y
-CONFIG_TARGET_ESTEEM192E=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 0e39857..9d6a6b6 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+ESTEEM192E powerpc mpc8xx - - Conn Clark <clark@esteem.com>
IP860 powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
IVML24 powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
IVMS8 powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
diff --git a/include/commproc.h b/include/commproc.h
index c53482c..9582746 100644
--- a/include/commproc.h
+++ b/include/commproc.h
@@ -456,34 +456,6 @@ typedef struct scc_enet {
#define SICR_ENET_CLKRT ((uint)0x00002c00)
#endif /* CONFIG_BSEIP */
-/*** ESTEEM 192E **************************************************/
-#ifdef CONFIG_ESTEEM192E
-/* ESTEEM192E
- * This ENET stuff is for the MPC850 with ethernet on SCC2. This
- * is very similar to the RPX-Lite configuration.
- * Note TENA , LOOPBACK , FDPLEX_DIS on Port B.
- */
-
-#define PROFF_ENET PROFF_SCC2
-#define CPM_CR_ENET CPM_CR_CH_SCC2
-#define SCC_ENET 1
-
-#define PA_ENET_RXD ((ushort)0x0004)
-#define PA_ENET_TXD ((ushort)0x0008)
-#define PA_ENET_TCLK ((ushort)0x0200)
-#define PA_ENET_RCLK ((ushort)0x0800)
-#define PB_ENET_TENA ((uint)0x00002000)
-#define PC_ENET_CLSN ((ushort)0x0040)
-#define PC_ENET_RENA ((ushort)0x0080)
-
-#define SICR_ENET_MASK ((uint)0x0000ff00)
-#define SICR_ENET_CLKRT ((uint)0x00003d00)
-
-#define PB_ENET_LOOPBACK ((uint)0x00004000)
-#define PB_ENET_FDPLEX_DIS ((uint)0x00008000)
-
-#endif
-
/*** KM8XX *********************************************************/
/* The KM8XX Service Module uses SCC3 for Ethernet */
diff --git a/include/configs/ESTEEM192E.h b/include/configs/ESTEEM192E.h
deleted file mode 100644
index 347f8b6..0000000
--- a/include/configs/ESTEEM192E.h
+++ /dev/null
@@ -1,292 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
-#define CONFIG_ESTEEM192E 1 /* ...on a EST ESTEEM192E */
-
-#define CONFIG_SYS_TEXT_BASE 0x40000000
-
-#define CONFIG_FLASH_16BIT 1 /* Rom 16 bit data bus */
-
-#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-
-#define MPC8XX_FACT 10 /* Multiply by 10 */
-#define MPC8XX_XIN 4915200 /* 4.915200 MHz in - ??? - XXX */
-#define CONFIG_SYS_PLPRCR_MF ((MPC8XX_FACT-1) << 20)
-#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) /* 49,152,000 Hz */
-
-#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ /* Force it - dont measure it */
-
-#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
-
-#define CONFIG_BAUDRATE 9600
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-#define CONFIG_BOOTCOMMAND "bootm 40030000" /* autoboot command */
-
-#define CONFIG_BOOTARGS "root=/dev/ram rw ramdisk=8192 " \
- "ip=100.100.100.21:100.100.100.14:100.100.100.1:255.0.0.0 "
-/*
- * Miscellaneous configurable options
- */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "BOOT: " /* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 8 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xFF000000
-
- /*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0x40000000
-#ifdef DEBUG
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#else
-#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
-#endif
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-
-/*-----------------------------------------------------------------------
- * SUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) /* DBGC00 */
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
-
-/* (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) */
-
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit - leave PLL multiplication factor unchanged !
- */
-#define CONFIG_SYS_PLPRCR (CONFIG_SYS_PLPRCR_MF | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK SCCR_EBDF11
-#define CONFIG_SYS_SCCR (SCCR_TBS | \
- SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
- SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
- SCCR_DFALCD00)
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
-
-#define CONFIG_SYS_PCMCIA_INTERRUPT SIU_LEVEL6
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-/*#define CONFIG_SYS_DER 0x2002000F*/
-#define CONFIG_SYS_DER 0
-/*#define CONFIG_SYS_DER 0x02002000 */
-
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
-
-/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
-#define CONFIG_SYS_OR_TIMING_FLASH 0x00000160
- /*(OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
- OR_SCY_5_CLK | OR_EHTR) */
-
-#define CONFIG_SYS_OR0_REMAP 0x80000160 /*(CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)*/
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR0_PRELIM ( FLASH_BASE0_PRELIM | 0x00000801 )
-
-#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
-#define CONFIG_SYS_BR1_PRELIM ( FLASH_BASE1_PRELIM | 0x00000801 )
-
-/*
- * BR2/3 and OR2/3 (SDRAM)
- *
- */
-#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
-#define SDRAM_BASE3_PRELIM 0x04000000 /* SDRAM bank #1 */
-#define SDRAM_MAX_SIZE 0x02000000 /* max 32 MB per bank */
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
-#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
-
-#define CONFIG_SYS_OR2_PRELIM 0xFC000E00
-#define CONFIG_SYS_BR2_PRELIM (SDRAM_BASE2_PRELIM | 0x00000081)
-
-#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
-#define CONFIG_SYS_BR3_PRELIM (SDRAM_BASE3_PRELIM | 0x00000081)
-
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */
-
-/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
-#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
-#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CONFIG_SYS_MAMR_8COL 0x18803112
-#define CONFIG_SYS_MAMR_9COL 0x18803112 /* same as 8 column because its just easier to port with*/
-
-#endif /* __CONFIG_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [U-Boot] [PATCH 13/26] powerpc: remove cogent_8xx, cogent_mpc8260 board support
2014-12-15 14:26 [U-Boot] [PATCH 0/26] Start removing non-generic boards Masahiro Yamada
` (11 preceding siblings ...)
2014-12-15 14:26 ` [U-Boot] [PATCH 12/26] mpc8xx: remove ESTEEM192E " Masahiro Yamada
@ 2014-12-15 14:26 ` Masahiro Yamada
2015-01-05 18:21 ` Tom Rini
2014-12-15 14:26 ` [U-Boot] [PATCH 14/26] mpc8260: remove sacsng " Masahiro Yamada
` (14 subsequent siblings)
27 siblings, 1 reply; 55+ messages in thread
From: Masahiro Yamada @ 2014-12-15 14:26 UTC (permalink / raw)
To: u-boot
These boards are still non-generic boards.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Murray Jensen <Murray.Jensen@csiro.au>
---
arch/powerpc/cpu/mpc8260/Kconfig | 4 -
arch/powerpc/cpu/mpc8260/cpu_init.c | 4 -
arch/powerpc/cpu/mpc8260/start.S | 61 ----
arch/powerpc/cpu/mpc8xx/Kconfig | 4 -
board/cogent/Kconfig | 19 --
board/cogent/MAINTAINERS | 8 -
board/cogent/Makefile | 8 -
board/cogent/README | 118 -------
board/cogent/README.cma286 | 69 ----
board/cogent/dipsw.c | 50 ---
board/cogent/dipsw.h | 3 -
board/cogent/flash.c | 633 ------------------------------------
board/cogent/flash.h | 305 -----------------
board/cogent/kbm.c | 3 -
board/cogent/lcd.c | 245 --------------
board/cogent/lcd.h | 84 -----
board/cogent/mb.c | 280 ----------------
board/cogent/mb.h | 513 -----------------------------
board/cogent/par.c | 3 -
board/cogent/par.h | 3 -
board/cogent/pci.c | 3 -
board/cogent/pci.h | 3 -
board/cogent/rtc.c | 3 -
board/cogent/rtc.h | 3 -
board/cogent/serial.c | 189 -----------
board/cogent/serial.h | 15 -
board/cogent/u-boot.lds | 86 -----
board/cogent/u-boot.lds.debug | 121 -------
configs/cogent_mpc8260_defconfig | 3 -
configs/cogent_mpc8xx_defconfig | 3 -
doc/README.scrapyard | 2 +
include/configs/cogent_common.h | 192 -----------
include/configs/cogent_mpc8260.h | 392 ----------------------
include/configs/cogent_mpc8xx.h | 349 --------------------
34 files changed, 2 insertions(+), 3779 deletions(-)
delete mode 100644 board/cogent/Kconfig
delete mode 100644 board/cogent/MAINTAINERS
delete mode 100644 board/cogent/Makefile
delete mode 100644 board/cogent/README
delete mode 100644 board/cogent/README.cma286
delete mode 100644 board/cogent/dipsw.c
delete mode 100644 board/cogent/dipsw.h
delete mode 100644 board/cogent/flash.c
delete mode 100644 board/cogent/flash.h
delete mode 100644 board/cogent/kbm.c
delete mode 100644 board/cogent/lcd.c
delete mode 100644 board/cogent/lcd.h
delete mode 100644 board/cogent/mb.c
delete mode 100644 board/cogent/mb.h
delete mode 100644 board/cogent/par.c
delete mode 100644 board/cogent/par.h
delete mode 100644 board/cogent/pci.c
delete mode 100644 board/cogent/pci.h
delete mode 100644 board/cogent/rtc.c
delete mode 100644 board/cogent/rtc.h
delete mode 100644 board/cogent/serial.c
delete mode 100644 board/cogent/serial.h
delete mode 100644 board/cogent/u-boot.lds
delete mode 100644 board/cogent/u-boot.lds.debug
delete mode 100644 configs/cogent_mpc8260_defconfig
delete mode 100644 configs/cogent_mpc8xx_defconfig
delete mode 100644 include/configs/cogent_common.h
delete mode 100644 include/configs/cogent_mpc8260.h
delete mode 100644 include/configs/cogent_mpc8xx.h
diff --git a/arch/powerpc/cpu/mpc8260/Kconfig b/arch/powerpc/cpu/mpc8260/Kconfig
index 2541400..17e303d 100644
--- a/arch/powerpc/cpu/mpc8260/Kconfig
+++ b/arch/powerpc/cpu/mpc8260/Kconfig
@@ -10,9 +10,6 @@ choice
config TARGET_ATC
bool "Support atc"
-config TARGET_COGENT_MPC8260
- bool "Support cogent_mpc8260"
-
config TARGET_CPU86
bool "Support CPU86"
@@ -58,7 +55,6 @@ config TARGET_KM82XX
endchoice
source "board/atc/Kconfig"
-source "board/cogent/Kconfig"
source "board/cpu86/Kconfig"
source "board/cpu87/Kconfig"
source "board/ep8260/Kconfig"
diff --git a/arch/powerpc/cpu/mpc8260/cpu_init.c b/arch/powerpc/cpu/mpc8260/cpu_init.c
index f46a9c0..a9bb5ad 100644
--- a/arch/powerpc/cpu/mpc8260/cpu_init.c
+++ b/arch/powerpc/cpu/mpc8260/cpu_init.c
@@ -88,9 +88,7 @@ static void config_8260_ioports (volatile immap_t * immr)
*/
void cpu_init_f (volatile immap_t * immr)
{
-#if !defined(CONFIG_COGENT) /* done in start.S for the cogent */
uint sccr;
-#endif
#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
unsigned long cpu_clk;
#endif
@@ -141,13 +139,11 @@ void cpu_init_f (volatile immap_t * immr)
/* initialize the PIT (4-42) */
immr->im_sit.sit_piscr = CONFIG_SYS_PISCR;
-#if !defined(CONFIG_COGENT) /* done in start.S for the cogent */
/* System clock control register (9-8) */
sccr = immr->im_clkrst.car_sccr &
(SCCR_PCI_MODE | SCCR_PCI_MODCK | SCCR_PCIDF_MSK);
immr->im_clkrst.car_sccr = sccr |
(CONFIG_SYS_SCCR & ~(SCCR_PCI_MODE | SCCR_PCI_MODCK | SCCR_PCIDF_MSK) );
-#endif /* !CONFIG_COGENT */
/*
* Memory Controller:
diff --git a/arch/powerpc/cpu/mpc8260/start.S b/arch/powerpc/cpu/mpc8260/start.S
index 5f1e174..d255bde 100644
--- a/arch/powerpc/cpu/mpc8260/start.S
+++ b/arch/powerpc/cpu/mpc8260/start.S
@@ -136,14 +136,6 @@ _hrcw_table:
_start:
mfmsr r5 /* save msr contents */
-#if defined(CONFIG_COGENT)
- /* this is what the cogent EPROM does */
- li r0, 0
- mtmsr r0
- isync
- bl cogent_init_8260
-#endif /* CONFIG_COGENT */
-
#if defined(CONFIG_SYS_DEFAULT_IMMR)
lis r3, CONFIG_SYS_IMMR at h
ori r3, r3, CONFIG_SYS_IMMR at l
@@ -379,57 +371,6 @@ int_return:
SYNC
rfi
-#if defined(CONFIG_COGENT)
-
-/*
- * This code initialises the MPC8260 processor core
- * (conforms to PowerPC 603e spec)
- */
-
- .globl cogent_init_8260
-cogent_init_8260:
-
- /* Taken from page 14 of CMA282 manual */
- /*--------------------------------------------------------------*/
-
- lis r4, (CONFIG_SYS_IMMR+IM_REGBASE)@h
- lis r3, CONFIG_SYS_IMMR at h
- stw r3, IM_IMMR at l(r4)
- lwz r3, IM_IMMR at l(r4)
- stw r3, 0(r0)
- lis r3, CONFIG_SYS_SYPCR at h
- ori r3, r3, CONFIG_SYS_SYPCR at l
- stw r3, IM_SYPCR at l(r4)
- lwz r3, IM_SYPCR at l(r4)
- stw r3, 4(r0)
- lis r3, CONFIG_SYS_SCCR at h
- ori r3, r3, CONFIG_SYS_SCCR at l
- stw r3, IM_SCCR at l(r4)
- lwz r3, IM_SCCR at l(r4)
- stw r3, 8(r0)
-
- /* the rest of this was disassembled from the */
- /* EPROM code that came with my CMA282 CPU module */
- /*--------------------------------------------------------------*/
-
- lis r1, 0x1234
- ori r1, r1, 0x5678
- stw r1, 0x20(r0)
- lwz r1, 0x20(r0)
- stw r1, 0x24(r0)
- lwz r1, 0x24(r0)
- lis r3, 0x0e80
- ori r3, r3, 0
- stw r1, 4(r3)
- lwz r1, 4(r3)
-
- /* Done! */
- /*--------------------------------------------------------------*/
-
- blr
-
-#endif /* CONFIG_COGENT */
-
/*
* This code initialises the MPC8260 processor core
* (conforms to PowerPC 603e spec)
@@ -456,11 +397,9 @@ init_8260_core:
/*--------------------------------------------------------------*/
lis r3, (CONFIG_SYS_IMMR+IM_REGBASE)@h
-#if !defined(CONFIG_COGENT)
lis r4, CONFIG_SYS_SYPCR at h
ori r4, r4, CONFIG_SYS_SYPCR at l
stw r4, IM_SYPCR at l(r3)
-#endif /* !CONFIG_COGENT */
#if defined(CONFIG_WATCHDOG)
li r4, 21868 /* = 0x556c */
sth r4, IM_SWSR at l(r3)
diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig
index 428a129..e8bcbe9 100644
--- a/arch/powerpc/cpu/mpc8xx/Kconfig
+++ b/arch/powerpc/cpu/mpc8xx/Kconfig
@@ -7,9 +7,6 @@ config SYS_CPU
choice
prompt "Target select"
-config TARGET_COGENT_MPC8XX
- bool "Support cogent_mpc8xx"
-
config TARGET_TQM823L
bool "Support TQM823L"
@@ -48,7 +45,6 @@ config TARGET_TQM885D
endchoice
-source "board/cogent/Kconfig"
source "board/tqc/tqm8xx/Kconfig"
endmenu
diff --git a/board/cogent/Kconfig b/board/cogent/Kconfig
deleted file mode 100644
index 7f34a14..0000000
--- a/board/cogent/Kconfig
+++ /dev/null
@@ -1,19 +0,0 @@
-if TARGET_COGENT_MPC8260
-
-config SYS_BOARD
- default "cogent"
-
-config SYS_CONFIG_NAME
- default "cogent_mpc8260"
-
-endif
-
-if TARGET_COGENT_MPC8XX
-
-config SYS_BOARD
- default "cogent"
-
-config SYS_CONFIG_NAME
- default "cogent_mpc8xx"
-
-endif
diff --git a/board/cogent/MAINTAINERS b/board/cogent/MAINTAINERS
deleted file mode 100644
index 7126015..0000000
--- a/board/cogent/MAINTAINERS
+++ /dev/null
@@ -1,8 +0,0 @@
-COGENT BOARD
-M: Murray Jensen <Murray.Jensen@csiro.au>
-S: Maintained
-F: board/cogent/
-F: include/configs/cogent_mpc8260.h
-F: configs/cogent_mpc8260_defconfig
-F: include/configs/cogent_mpc8xx.h
-F: configs/cogent_mpc8xx_defconfig
diff --git a/board/cogent/Makefile b/board/cogent/Makefile
deleted file mode 100644
index 30fe98d..0000000
--- a/board/cogent/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := mb.o flash.o dipsw.o lcd.o serial.o # pci.o rtc.o par.o kbm.o
diff --git a/board/cogent/README b/board/cogent/README
deleted file mode 100644
index 4343f73..0000000
--- a/board/cogent/README
+++ /dev/null
@@ -1,118 +0,0 @@
-Cogent Modular Architecture configuration
------------------------------------------
-
-As the name suggests, the Cogent platform is a modular system where
-you have a motherboard into which plugs a cpu module and one or more
-i/o modules. This provides very nice flexibility, but makes the
-configuration task somewhat harder.
-
-The possible Cogent motherboards are:
-
-Code Config Variable Description
----- --------------- -----------
-
-CMA101 CONFIG_CMA101 32MB ram, 2 ser, 1 par, rtc, dipsw,
- 2x16 lcd, eth(?)
-CMA102 CONFIG_CMA102 32MB ram, 2 ser, 1 par, rtc, dipsw,
- 2x16 lcd
-CMA111 CONFIG_CMA111 32MB ram, 1MB flash, 4 ser, 1 par,
- rtc, ps/2 kbd/mse, 2x16 lcd, 2xPCI,
- 10/100TP eth
-CMA120 CONFIG_CMA120 32MB ram, 1MB flash, 4 ser, 1 par,
- rtc, ps/2 kbd/mse, 2x16 lcd, 2xPCI,
- 10/100TP eth, 2xPCMCIA, video/lcd-panel
-CMA150 CONFIG_CMA150 8MB ram, 1MB flash, 2 ser, 1 par, rtc,
- ps/2 kbd/mse, 2x16 lcd
-
-The possible Cogent PowerPC CPU modules are:
-
-Code Config Variable Description
----- --------------- -----------
-
-CMA278-603EV CONFIG_CMA278_603EV PPC603ev CPU, 66MHz clock, 512K EPROM,
- JTAG/COP
-CMA278-603ER CONFIG_CMA278_603ER PPC603er CPU, 66MHz clock, 512K EPROM,
- JTAG/COP
-CMA278-740 CONFIG_CMA278_740 PPC740 CPU, 66MHz clock, 512K EPROM,
- JTAG/COP
-CMA280-509 CONFIG_CMA280_509 MPC505/509 CPU, 50MHz clock,
- 512K EPROM, BDM
-CMA282 CONFIG_CMA282 MPC8260 CPU, 66MHz clock, 512K EPROM,
- JTAG, 16M RAM, 1 x ser (SMC2),
- 1 x 10baseT PHY (SCC4), 1 x 10/100 TP
- PHY (FCC1), 2 x 48pin DIN (FCC2 + TDM1)
-CMA285 CONFIG_CMA285 MPC801 CPU, 33MHz clock, 512K EPROM,
- BDM
-CMA286-21 CONFIG_CMA286_21 MPC821 CPU, 66MHz clock, 512K EPROM,
- BDM, 16M RAM, 2 x ser (SMC1 + SMC2),
- 1 x 10baseT PHY (SCC2)
-CMA286-60-OLD CONFIG_CMA286_60_OLD MPC860 CPU, 33MHz clock, 128K EPROM,
- BDM
-CMA286-60 CONFIG_CMA286_60 MPC860 CPU, 66MHz clock, 512K EPROM,
- BDM, 16M RAM, 2 x ser (SMC1 + SMC2),
- 1 x 10baseT PHY (SCC2)
-CMA286-60P CONFIG_CMA286_60P MPC860P CPU, 66MHz clock, 512K EPROM,
- BDM, 16M RAM, 2 x ser (SMC1 + SMC2),
- 1 x 10baseT PHY (SCC2)
-CMA287-23 CONFIG_CMA287_23 MPC823 CPU, 33MHz clock, 512K EPROM,
- BDM
-CMA287-50 CONFIG_CMA287_50 MPC850 CPU, 33MHz clock, 512K EPROM,
- BDM
-
-(there are a lot of other cpu modules with ARM, MIPS and M-CORE CPUs,
-but we'll worry about those later).
-
-The possible Cogent CMA I/O Modules are:
-
-Code Config Variable Description
----- --------------- -----------
-
-CMA302 CONFIG_CMA302 up to 16M flash, ps/2 keyboard/mouse
-CMA352 CONFIG_CMA352 CMAbus <=> PCI
-
-Currently supported:
-
- Motherboards: CMA102
- CPU Modules: CMA286-60-OLD
- I/O Modules: CMA302 I/O module
-
-To configure, perform the usual U-Boot configuration task of editing
-"include/config_cogent_mpc8xx.h" and reviewing all the options and
-settings in there. In particular, check the chip select values
-installed into the memory controller's various option and base
-registers - these are set by the defines CONFIG_SYS_CMA_CSn_{BASE,SIZE} and
-CONFIG_SYS_{B,O}Rn_PRELIM. Also be careful of the clock settings installed
-into the SCCR - via the define CONFIG_SYS_SCCR. Finally, decide whether you
-want the serial console on motherboard serial port A or on one of the
-8xx SMC ports, and set CONFIG_8xx_CONS_{SMC1,SMC2,NONE} accordingly
-(NONE means use Cogent motherboard serial port A).
-
-Then edit the file "cogent/config.mk". Firstly, set CONFIG_SYS_TEXT_BASE to be
-the base address of the EPROM for the CPU module. This should be the
-same as the value selected for CONFIG_SYS_MONITOR_BASE in
-"include/config_cogent_*.h" (in fact, I have made this automatic via
-the -CONFIG_SYS_TEXT_BASE=... option in CPPFLAGS).
-
-Finally, set the values of the make variables $(CMA_MB) and $(CMA_IOMS).
-
-$(CMA_MB) is the name of the directory that contains support for your
-motherboard. At this stage, only "cma10x" exists, which supports the
-CMA101 and CMA102 motherboards - but only selected devices, namely
-serial, lcd and dipsw.
-
-$(CMA_IOMS) is a list of zero or more directories that contain
-support for the i/o modules you have installed. At this stage, only
-"cma302" exists, which supports the CMA302 flash i/o module - but
-only the flash part, not the ps/2 keyboard and mouse interfaces.
-
-There should be a make variable for each of the above directories,
-which is the directory name with "_O" appended. This make variable is
-a list of object files to compile from that directory and include in
-the library.
-
- e.g. cma10x_O = serial.o ...
-
-That's it. Good Luck.
-
-Murray.Jensen at cmst.csiro.au
-August 31, 2000.
diff --git a/board/cogent/README.cma286 b/board/cogent/README.cma286
deleted file mode 100644
index 0345fea..0000000
--- a/board/cogent/README.cma286
+++ /dev/null
@@ -1,69 +0,0 @@
-CPU module revisions
---------------------
-
-My cpu module has the model number "CMA286-60-990526-01". My motherboard
-has the model number "CMA102-32M-990526-01". These are both fairly old,
-and may not reflect current design. In particular, I can see from the
-Cogent web site that the CMA286 has been significantly redesigned - it
-now has on board RAM (4M), ethernet 10baseT PHY (on SCC2), 2 serial ports
-(SMC1 and SMC2), and 48pin DIN for the FEC (if present i.e. MPC860T), and
-also the EPROM is 512K.
-
-My CMA286-60 has none of this, and only 128K EPROM. In addition, the CPU
-clock is listed as 66MHz, whereas mine is 33.333MHz.
-
-Clocks
-------
-
-Quote from my "CMA286 MPC860/821 User's Manual":
-
-"When setting up the Periodic Interrupt Timer (PIT), be aware that the
-CMA286 places the MPC860/821 in PLL X1 Mode. This means that we feed
-a 25MHz clock directly into the MPC860/821. This mode sets the divisor
-for the PIT to be 512. In addition, the Time Base Register (TMB)
-divisor is set to 16."
-
-I interpreted this information to mean that EXTCLK is 25MHz and that at
-power on reset, MODCK1=1 and MODCK2=0, which selects EXTCLK as the
-source for OSCCLK and PITRTCLK, sets RTDIV to 512 and sets MF (the
-multiplication factor) to 1 (I assume this is what they mean by X1
-mode above). MF=1 means the cpus internal clock runs at the same
-rate as EXTCLK i.e. 25MHz.
-
-Furthermore, since SCCR[TBS] (the Time Base Source selector bit in the
-System Clock and Reset Control register) is set in the cpu initialisation
-code, the TMBCLK source is forced to be GCLK2 and the TMBCLK prescale is
-forced to be 16. This results in TMBCLK=1562500.
-
-One problem - since PITRTCLK source is EXTCLK (25Mhz) and RTDIV is 512,
-PITRTCLK will be 48828.125 (huh?). Another quote from the MPC860 Users
-Manual:
-
-"When used by the real-time clock (RTC), the PITRTCLK source is first
-divided as determined by RTDIV, and then divided in the RTC circuits by
-either 8192 or 9600. Therefore, in order for the RTC to count in
-seconds, the clock source must satisfy:
-
- (EXTCLK or OSCM) / [(4 or 512) x (8192 or 9600)] = 1
-
-The RTC will operate with other frequencies, but it will not count in
-units of seconds."
-
-Therefore, the internal RTC of the MPC860 is not going to count in
-seconds, so we must use the motherboard RTC (if we need a RTC).
-
-I presume this means that they do not provide a fixed oscillator for
-OSCM. The code in get_gclk_freq() assumes PITRTCLK source is OSCM,
-RTDIV is 4, and that OSCM/4 is 8192 (i.e. a ~32KHz oscillator). Since
-the CMA286-60 doesn't have this (at least mine doesn't) we can't use
-the code in get_gclk_freq().
-
-Finally, it appears that the internal clock in my CMA286-60 is actually
-33.333MHz. Which makes TMBCLK=2083312.5 (another huh?) and
-PITRTCLK=65103.515625 (bloody hell!).
-
-If anyone finds anything wrong with the stuff above, I would appreciate
-an email about it.
-
-Murray Jensen <Murray.Jensen@csiro.au>
-21-Aug-00
diff --git a/board/cogent/dipsw.c b/board/cogent/dipsw.c
deleted file mode 100644
index ecfbc25..0000000
--- a/board/cogent/dipsw.c
+++ /dev/null
@@ -1,50 +0,0 @@
-#include <common.h>
-#include "dipsw.h"
-
-unsigned char
-dipsw_raw(void)
-{
- return cma_mb_reg_read(&((cma_mb_dipsw *)CMA_MB_DIPSW_BASE)->dip_val);
-}
-
-unsigned char
-dipsw_cooked(void)
-{
- unsigned char val1, val2, mask1, mask2;
-
- val1 = dipsw_raw();
-
- /*
- * we want to mirror the bits because the low bit is switch 1 and high
- * bit is switch 8 and also invert them because 1=off and 0=on, according
- * to manual.
- *
- * this makes the value more intuitive i.e.
- * - left most, or high, or top, bit is left most switch (1);
- * - right most, or low, or bottom, bit is right most switch (8)
- * - a set bit means "on" and a clear bit means "off"
- */
-
- val2 = 0;
- for (mask1 = 1 << 7, mask2 = 1; mask1 > 0; mask1 >>= 1, mask2 <<= 1)
- if ((val1 & mask1) == 0)
- val2 |= mask2;
-
- return (val2);
-}
-
-void
-dipsw_init(void)
-{
- unsigned char val, mask;
-
- val = dipsw_cooked();
-
- printf("|");
- for (mask = 1 << 7; mask > 0; mask >>= 1)
- if (val & mask)
- printf("on |");
- else
- printf("off|");
- printf("\n");
-}
diff --git a/board/cogent/dipsw.h b/board/cogent/dipsw.h
deleted file mode 100644
index 4f52fd4..0000000
--- a/board/cogent/dipsw.h
+++ /dev/null
@@ -1,3 +0,0 @@
-extern unsigned char dipsw_raw(void);
-extern unsigned char dipsw_cooked(void);
-extern void dipsw_init(void);
diff --git a/board/cogent/flash.c b/board/cogent/flash.c
deleted file mode 100644
index 1da8f10..0000000
--- a/board/cogent/flash.c
+++ /dev/null
@@ -1,633 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include "flash.h"
-#include <linux/compiler.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-# ifndef CONFIG_ENV_ADDR
-# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-# endif
-# ifndef CONFIG_ENV_SIZE
-# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-# endif
-# ifndef CONFIG_ENV_SECT_SIZE
-# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
-# endif
-#endif
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-
-/*-----------------------------------------------------------------------
- */
-
-
-#if defined(CONFIG_CMA302)
-
-/*
- * probe for the existence of flash at address "addr"
- * 0 = yes, 1 = bad Manufacturer's Id, 2 = bad Device Id
- */
-static int
-c302f_probe_word(c302f_addr_t addr)
-{
- /* reset the flash */
- *addr = C302F_BNK_CMD_RST;
-
- /* check the manufacturer id */
- *addr = C302F_BNK_CMD_RD_ID;
- if (*C302F_BNK_ADDR_MAN(addr) != C302F_BNK_RD_ID_MAN)
- return 1;
-
- /* check the device id */
- *addr = C302F_BNK_CMD_RD_ID;
- if (*C302F_BNK_ADDR_DEV(addr) != C302F_BNK_RD_ID_DEV)
- return 2;
-
-#ifdef FLASH_DEBUG
- {
- int i;
-
- printf("\nMaster Lock Config = 0x%08lx\n",
- *C302F_BNK_ADDR_CFGM(addr));
- for (i = 0; i < C302F_BNK_NBLOCKS; i++)
- printf("Block %2d Lock Config = 0x%08lx\n",
- i, *C302F_BNK_ADDR_CFG(i, addr));
- }
-#endif
-
- /* reset the flash again */
- *addr = C302F_BNK_CMD_RST;
-
- return 0;
-}
-
-/*
- * probe for Cogent CMA302 flash module at address "base" and store
- * info for any found into flash_info entry "fip". Must find@least
- * one bank.
- */
-static void
-c302f_probe(flash_info_t *fip, c302f_addr_t base)
-{
- c302f_addr_t addr, eaddr;
- int nbanks;
-
- fip->size = 0L;
- fip->sector_count = 0;
-
- addr = base;
- eaddr = C302F_BNK_ADDR_BASE(addr, C302F_MAX_BANKS);
- nbanks = 0;
-
- while (addr < eaddr) {
- c302f_addr_t addrw, eaddrw, addrb;
- int i, osc, nsc;
-
- addrw = addr;
- eaddrw = C302F_BNK_ADDR_NEXT_WORD(addrw);
-
- while (addrw < eaddrw)
- if (c302f_probe_word(addrw++) != 0)
- goto out;
-
- /* bank exists - append info for this bank to *fip */
- fip->flash_id = FLASH_MAN_INTEL|FLASH_28F008S5;
- fip->size += C302F_BNK_SIZE;
- osc = fip->sector_count;
- fip->sector_count += C302F_BNK_NBLOCKS;
- if ((nsc = fip->sector_count) >= CONFIG_SYS_MAX_FLASH_SECT)
- panic("Too many sectors in flash at address 0x%08lx\n",
- (unsigned long)base);
-
- addrb = addr;
- for (i = osc; i < nsc; i++) {
- fip->start[i] = (ulong)addrb;
- fip->protect[i] = 0;
- addrb = C302F_BNK_ADDR_NEXT_BLK(addrb);
- }
-
- addr = C302F_BNK_ADDR_NEXT_BNK(addr);
- nbanks++;
- }
-
-out:
- if (nbanks == 0)
- panic("ERROR: no flash found at address 0x%08lx\n",
- (unsigned long)base);
-}
-
-static void
-c302f_reset(flash_info_t *info, int sect)
-{
- c302f_addr_t addrw, eaddrw;
-
- addrw = (c302f_addr_t)info->start[sect];
- eaddrw = C302F_BNK_ADDR_NEXT_WORD(addrw);
-
- while (addrw < eaddrw) {
-#ifdef FLASH_DEBUG
- printf(" writing reset cmd to addr 0x%08lx\n",
- (unsigned long)addrw);
-#endif
- *addrw = C302F_BNK_CMD_RST;
- addrw++;
- }
-}
-
-static void
-c302f_erase_init(flash_info_t *info, int sect)
-{
- c302f_addr_t addrw, saddrw, eaddrw;
- int flag;
-
-#ifdef FLASH_DEBUG
- printf("0x%08lx C302F_BNK_CMD_PROG\n", C302F_BNK_CMD_PROG);
- printf("0x%08lx C302F_BNK_CMD_ERASE1\n", C302F_BNK_CMD_ERASE1);
- printf("0x%08lx C302F_BNK_CMD_ERASE2\n", C302F_BNK_CMD_ERASE2);
- printf("0x%08lx C302F_BNK_CMD_CLR_STAT\n", C302F_BNK_CMD_CLR_STAT);
- printf("0x%08lx C302F_BNK_CMD_RST\n", C302F_BNK_CMD_RST);
- printf("0x%08lx C302F_BNK_STAT_RDY\n", C302F_BNK_STAT_RDY);
- printf("0x%08lx C302F_BNK_STAT_ERR\n", C302F_BNK_STAT_ERR);
-#endif
-
- saddrw = (c302f_addr_t)info->start[sect];
- eaddrw = C302F_BNK_ADDR_NEXT_WORD(saddrw);
-
-#ifdef FLASH_DEBUG
- printf("erasing sector %d, start addr = 0x%08lx "
- "(bank next word addr = 0x%08lx)\n", sect,
- (unsigned long)saddrw, (unsigned long)eaddrw);
-#endif
-
- /* Disable intrs which might cause a timeout here */
- flag = disable_interrupts();
-
- for (addrw = saddrw; addrw < eaddrw; addrw++) {
-#ifdef FLASH_DEBUG
- printf(" writing erase cmd to addr 0x%08lx\n",
- (unsigned long)addrw);
-#endif
- *addrw = C302F_BNK_CMD_ERASE1;
- *addrw = C302F_BNK_CMD_ERASE2;
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-}
-
-static int
-c302f_erase_poll(flash_info_t *info, int sect)
-{
- c302f_addr_t addrw, saddrw, eaddrw;
- int sectdone, haderr;
-
- saddrw = (c302f_addr_t)info->start[sect];
- eaddrw = C302F_BNK_ADDR_NEXT_WORD(saddrw);
-
- sectdone = 1;
- haderr = 0;
-
- for (addrw = saddrw; addrw < eaddrw; addrw++) {
- c302f_word_t stat = *addrw;
-
-#ifdef FLASH_DEBUG
- printf(" checking status at addr "
- "0x%08lx [0x%08lx]\n",
- (unsigned long)addrw, stat);
-#endif
- if ((stat & C302F_BNK_STAT_RDY) != C302F_BNK_STAT_RDY)
- sectdone = 0;
- else if ((stat & C302F_BNK_STAT_ERR) != 0) {
- printf(" failed on sector %d "
- "(stat = 0x%08lx)@"
- "address 0x%08lx\n",
- sect, stat,
- (unsigned long)addrw);
- *addrw = C302F_BNK_CMD_CLR_STAT;
- haderr = 1;
- }
- }
-
- if (haderr)
- return (-1);
- else
- return (sectdone);
-}
-
-static int
-c302f_write_word(c302f_addr_t addr, c302f_word_t value)
-{
- c302f_word_t stat;
- ulong start;
- int flag, retval;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- *addr = C302F_BNK_CMD_PROG;
-
- *addr = value;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- retval = 0;
-
- /* data polling for D7 */
- start = get_timer (0);
- do {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- retval = 1;
- goto done;
- }
- stat = *addr;
- } while ((stat & C302F_BNK_STAT_RDY) != C302F_BNK_STAT_RDY);
-
- if ((stat & C302F_BNK_STAT_ERR) != 0) {
- printf("flash program failed (stat = 0x%08lx) "
- "at address 0x%08lx\n", (ulong)stat, (ulong)addr);
- *addr = C302F_BNK_CMD_CLR_STAT;
- retval = 3;
- }
-
-done:
- /* reset to read mode */
- *addr = C302F_BNK_CMD_RST;
-
- return (retval);
-}
-
-#endif /* CONFIG_CMA302 */
-
-unsigned long
-flash_init(void)
-{
- unsigned long total;
- int i;
- __maybe_unused flash_info_t *fip;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- fip = &flash_info[0];
- total = 0L;
-
-#if defined(CONFIG_CMA302)
- c302f_probe(fip, (c302f_addr_t)CONFIG_SYS_FLASH_BASE);
- total += fip->size;
- fip++;
-#endif
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
- /* not yet ...
- cmbf_probe(fip, (cmbf_addr_t)CMA_MB_FLASH_BASE);
- total += fip->size;
- fip++;
- */
-#endif
-
- /*
- * protect monitor and environment sectors
- */
-
-#if CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[0]);
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
- &flash_info[0]);
-#endif
- return total;
-}
-
-/*-----------------------------------------------------------------------
- */
-void
-flash_print_info(flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_INTEL: printf ("INTEL "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F008S5: printf ("28F008S5\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 4) == 0)
- printf ("\n ");
- printf (" %2d - %08lX%s", i,
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
- return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-int
-flash_erase(flash_info_t *info, int s_first, int s_last)
-{
- int prot, sect, haderr;
- ulong start, now, last;
- void (*erase_init)(flash_info_t *, int);
- int (*erase_poll)(flash_info_t *, int);
- void (*reset)(flash_info_t *, int);
- int rcode = 0;
-
-#ifdef FLASH_DEBUG
- printf("\nflash_erase: erase %d sectors (%d to %d incl.) from\n"
- " Bank # %d: ", s_last - s_first + 1, s_first, s_last,
- (info - flash_info) + 1);
- flash_print_info(info);
-#endif
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- switch (info->flash_id) {
-
-#if defined(CONFIG_CMA302)
- case FLASH_MAN_INTEL|FLASH_28F008S5:
- erase_init = c302f_erase_init;
- erase_poll = c302f_erase_poll;
- reset = c302f_reset;
- break;
-#endif
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
- case FLASH_MAN_INTEL|FLASH_28F800_B:
- case FLASH_MAN_AMD|FLASH_AM29F800B:
- /* not yet ...
- erase_init = cmbf_erase_init;
- erase_poll = cmbf_erase_poll;
- reset = cmbf_reset;
- break;
- */
-#endif
-
- default:
- printf ("Flash type %08lx not supported - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf("- Warning: %d protected sector%s will not be erased!\n",
- prot, (prot > 1 ? "s" : ""));
- }
-
- start = get_timer (0);
- last = 0;
- haderr = 0;
-
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- ulong estart;
- int sectdone;
-
- (*erase_init)(info, sect);
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- estart = get_timer(start);
-
- do {
- now = get_timer(start);
-
- if (now - estart > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout (sect %d)\n", sect);
- haderr = 1;
- break;
- }
-
-#ifndef FLASH_DEBUG
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
-#endif
-
- sectdone = (*erase_poll)(info, sect);
-
- if (sectdone < 0) {
- haderr = 1;
- break;
- }
-
- } while (!sectdone);
-
- if (haderr)
- break;
- }
- }
-
- if (haderr > 0) {
- printf (" failed\n");
- rcode = 1;
- }
- else
- printf (" done\n");
-
- /* reset to read mode */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- (*reset)(info, sect);
- }
- }
- return rcode;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 3 - write error
- */
-
-int
-write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
- ulong start, now, last;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- start = get_timer (0);
- last = 0;
- while (cnt >= 4) {
- data = 0;
- for (i=0; i<4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
-
- /* show that we're waiting */
- now = get_timer(start);
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 3 - write error
- */
-static int
-write_word(flash_info_t *info, ulong dest, ulong data)
-{
- int retval;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*(ulong *)dest & data) != data) {
- return (2);
- }
-
- switch (info->flash_id) {
-
-#if defined(CONFIG_CMA302)
- case FLASH_MAN_INTEL|FLASH_28F008S5:
- retval = c302f_write_word((c302f_addr_t)dest, (c302f_word_t)data);
- break;
-#endif
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
- case FLASH_MAN_INTEL|FLASH_28F800_B:
- case FLASH_MAN_AMD|FLASH_AM29F800B:
- /* not yet ...
- retval = cmbf_write_word((cmbf_addr_t)dest, (cmbf_word_t)data);
- */
- retval = 3;
- break;
-#endif
-
- default:
- printf ("Flash type %08lx not supported - aborted\n",
- info->flash_id);
- retval = 3;
- break;
- }
-
- return (retval);
-}
-
-/*-----------------------------------------------------------------------
- */
diff --git a/board/cogent/flash.h b/board/cogent/flash.h
deleted file mode 100644
index 0b8d6aa..0000000
--- a/board/cogent/flash.h
+++ /dev/null
@@ -1,305 +0,0 @@
-/**************** DEFINES for Intel 28F008S5 FLASH chip **********************/
-
-/* register addresses, valid only following a I8S5_CMD_RD_ID command */
-#define I8S5_ADDR_MAN 0x00000 /* manufacturer's id */
-#define I8S5_ADDR_DEV 0x00001 /* device id */
-#define I8S5_ADDR_CFGM 0x00003 /* master lock configuration */
-#define I8S5_ADDR_CFG(b) (((b)<<16)|2) /* block lock configuration */
-
-/* Commands */
-#define I8S5_CMD_RST 0xFF /* reset flash */
-#define I8S5_CMD_RD_ID 0x90 /* read the id and lock bits */
-#define I8S5_CMD_RD_STAT 0x70 /* read the status register */
-#define I8S5_CMD_CLR_STAT 0x50 /* clear the staus register */
-#define I8S5_CMD_ERASE1 0x20 /* first word for block erase */
-#define I8S5_CMD_ERASE2 0xD0 /* second word for block erase */
-#define I8S5_CMD_PROG 0x40 /* program word command */
-#define I8S5_CMD_LOCK 0x60 /* first word for all lock commands */
-#define I8S5_CMD_SET_LOCK_BLK 0x01 /* 2nd word for set block lock bit */
-#define I8S5_CMD_SET_LOCK_MSTR 0xF1 /* 2nd word for set master lock bit */
-#define I8S5_CMD_CLR_LOCK_BLK 0xD0 /* 2nd word for clear block lock bit */
-
-/* status register bits */
-#define I8S5_STAT_DPS 0x02 /* Device Protect Status */
-#define I8S5_STAT_PSS 0x04 /* Program Suspend Status */
-#define I8S5_STAT_VPPS 0x08 /* VPP Status */
-#define I8S5_STAT_PSLBS 0x10 /* Program and Set Lock Bit Status */
-#define I8S5_STAT_ECLBS 0x20 /* Erase and Clear Lock Bit Status */
-#define I8S5_STAT_ESS 0x40 /* Erase Suspend Status */
-#define I8S5_STAT_RDY 0x80 /* Write State Machine Status, 1=rdy */
-
-#define I8S5_STAT_ERR (I8S5_STAT_VPPS | I8S5_STAT_DPS | \
- I8S5_STAT_ECLBS | I8S5_STAT_PSLBS)
-
-/* ID and Lock Configuration */
-#define I8S5_RD_ID_LOCK 0x01 /* Bit 0 of each byte */
-#define I8S5_RD_ID_MAN 0x89 /* Manufacturer code = 0x89 */
-#define I8S5_RD_ID_DEV 0xA6 /* Device code = 0xA6, 28F008S5 */
-
-/* dimensions */
-#define I8S5_NBLOCKS 16 /* a 28F008S5 consists of 16 blocks */
-#define I8S5_BLKSZ (64*1024) /* of 64Kbyte each */
-#define I8S5_SIZE (I8S5_BLKSZ * I8S5_NBLOCKS)
-
-/**************** DEFINES for Intel 28F800B5 FLASH chip **********************/
-
-/* register addresses, valid only following a I8S5_CMD_RD_ID command */
-#define I8B5_ADDR_MAN 0x00000 /* manufacturer's id */
-#define I8B5_ADDR_DEV 0x00001 /* device id */
-
-/* Commands */
-#define I8B5_CMD_RST 0xFF /* reset flash */
-#define I8B5_CMD_RD_ID 0x90 /* read the id and lock bits */
-#define I8B5_CMD_RD_STAT 0x70 /* read the status register */
-#define I8B5_CMD_CLR_STAT 0x50 /* clear the staus register */
-#define I8B5_CMD_ERASE1 0x20 /* first word for block erase */
-#define I8B5_CMD_ERASE2 0xD0 /* second word for block erase */
-#define I8B5_CMD_PROG 0x40 /* program word command */
-
-/* status register bits */
-#define I8B5_STAT_VPPS 0x08 /* VPP Status */
-#define I8B5_STAT_DWS 0x10 /* Program and Set Lock Bit Status */
-#define I8B5_STAT_ES 0x20 /* Erase and Clear Lock Bit Status */
-#define I8B5_STAT_ESS 0x40 /* Erase Suspend Status */
-#define I8B5_STAT_RDY 0x80 /* Write State Machine Status, 1=rdy */
-
-#define I8B5_STAT_ERR (I8B5_STAT_VPPS | I8B5_STAT_DWS | I8B5_STAT_ES)
-
-/* ID Configuration */
-#define I8B5_RD_ID_MAN 0x89 /* Manufacturer code = 0x89 */
-#define I8B5_RD_ID_DEV1 0x889D /* Device code = 0x889D, 28F800B5 */
-
-/* dimensions */
-#define I8B5_NBLOCKS 8 /* a 28F008S5 consists of 16 blocks */
-#define I8B5_BLKSZ (128*1024) /* of 64Kbyte each */
-#define I8B5_SIZE (I8B5_BLKSZ * I8B5_NBLOCKS)
-
-/****************** DEFINES for Cogent CMA302 Flash **************************/
-
-/*
- * Quoted from the CMA302 manual:
- *
- * Although the CMA302 supports 64-bit reads, all writes must be done with
- * word size only. When programming the CMA302, the FLASH devices appear as 2
- * banks of interleaved, 32-bit wide FLASH. Each 32-bit word consists of four
- * 28F008S5 devices. The first bank is accessed when the word address is even,
- * while the second bank is accessed when the word address is odd. This must
- * be taken into account when programming the desired word. Also, when locking
- * blocks, software must lock both banks. The CMA302 does not directly support
- * byte writing. Programming and/or erasing individual bytes is done with
- * selective use of the Write Command. By not placing the Write Command value
- * on a particular byte lane, that byte will not be written with the following
- * Write Data. Also, remember that within a byte lane (i.e. D0-7), there are
- * two 28F008S5 devices, one for each bank or every other word.
- *
- * End quote.
- *
- * Each 28F008S5 is 8Mbit, with 8 bit wide data. i.e. each is 1Mbyte. The
- * chips are arranged on the CMA302 in multiples of two banks, each bank having
- * 4 chips. Each bank must be accessed as a single 32 bit wide device (i.e.
- * aligned on a 32 bit boundary), with each byte lane within the 32 bits (0-3)
- * going to each of the 4 chips and the word address selecting the bank, even
- * being the low bank and odd the high bank. For 64bit reads, both banks are
- * read simultaneously with the second bank on byte lanes 4-7. Each 28F008S5
- * consists of 16 64Kbyte "block"s. Before programming a byte, the block that
- * the byte resides within must be erased. So if you want to program contiguous
- * memory locations, you must erase all 8 chips at the same time. i.e. the
- * flash on the CMA302 can be viewed as a number of 512Kbyte blocks.
- *
- * Note: I am going to treat banks as 8 Mbytes (1Meg of 64bit words), whereas
- * the example code treats them as a pair of interleaved 1 Mbyte x 32bit banks.
- */
-
-typedef unsigned long c302f_word_t; /* 32 or 64 bit unsigned integer */
-typedef volatile c302f_word_t *c302f_addr_t;
-typedef unsigned long c302f_size_t; /* want this big - at least 32 bit */
-
-/* layout of banks on cma302 board */
-#define C302F_BNK_WIDTH 8 /* each bank is 8 chips wide */
-#define C302F_BNK_WSHIFT 3 /* log base 2 of C302F_BNK_WIDTH */
-#define C302F_BNK_NBLOCKS I8S5_NBLOCKS
-#define C302F_BNK_BLKSZ (I8S5_BLKSZ * C302F_BNK_WIDTH)
-#define C302F_BNK_SIZE (I8S5_SIZE * C302F_BNK_WIDTH)
-
-#define C302F_MAX_BANKS 2 /* up to 2 banks (8M each) on CMA302 */
-
-/* align addresses and sizes to bank boundaries */
-#define C302F_BNK_ADDR_ALIGN(a) ((c302f_addr_t)((c302f_size_t)(a) \
- & ~(C302F_BNK_WIDTH - 1)))
-#define C302F_BNK_SIZE_ALIGN(s) ((c302f_size_t)C302F_BNK_ADDR_ALIGN( \
- (c302f_size_t)(s) + (C302F_BNK_WIDTH - 1)))
-
-/* align addresses and sizes to block boundaries */
-#define C302F_BLK_ADDR_ALIGN(a) ((c302f_addr_t)((c302f_size_t)(a) \
- & ~(C302F_BNK_BLKSZ - 1)))
-#define C302F_BLK_SIZE_ALIGN(s) ((c302f_size_t)C302F_BLK_ADDR_ALIGN( \
- (c302f_size_t)(s) + (C302F_BNK_BLKSZ - 1)))
-
-/* add a byte offset to a flash address */
-#define C302F_ADDR_ADD_BYTEOFF(a,o) \
- (c302f_addr_t)((c302f_size_t)(a) + (o))
-
-/* get base address of bank b, given flash base address a */
-#define C302F_BNK_ADDR_BASE(a,b) \
- C302F_ADDR_ADD_BYTEOFF((a), \
- (c302f_size_t)(b) * C302F_BNK_SIZE)
-
-/* adjust an address a (within a bank) to next word, block or bank */
-#define C302F_BNK_ADDR_NEXT_WORD(a) \
- C302F_ADDR_ADD_BYTEOFF((a), C302F_BNK_WIDTH)
-#define C302F_BNK_ADDR_NEXT_BLK(a) \
- C302F_ADDR_ADD_BYTEOFF((a), C302F_BNK_BLKSZ)
-#define C302F_BNK_ADDR_NEXT_BNK(a) \
- C302F_ADDR_ADD_BYTEOFF((a), C302F_BNK_SIZE)
-
-/* get bank address of chip register r given a bank base address a */
-#define C302F_BNK_ADDR_I8S5REG(a,r) \
- C302F_ADDR_ADD_BYTEOFF((a), \
- (r) << C302F_BNK_WSHIFT)
-
-/* make a bank representation for each chip address */
-
-#define C302F_BNK_ADDR_MAN(a) C302F_BNK_ADDR_I8S5REG((a), I8S5_ADDR_MAN)
-#define C302F_BNK_ADDR_DEV(a) C302F_BNK_ADDR_I8S5REG((a), I8S5_ADDR_DEV)
-#define C302F_BNK_ADDR_CFGM(a) C302F_BNK_ADDR_I8S5REG((a), I8S5_ADDR_CFGM)
-#define C302F_BNK_ADDR_CFG(b,a) C302F_BNK_ADDR_I8S5REG((a), I8S5_ADDR_CFG(b))
-
-/*
- * replicate a chip cmd/stat/rd value into each byte position within a word
- * so that multiple chips are accessed in a single word i/o operation
- *
- * this must be as wide as the c302f_word_t type
- */
-#define C302F_FILL_WORD(o) (((unsigned long)(o) << 24) | \
- ((unsigned long)(o) << 16) | \
- ((unsigned long)(o) << 8) | \
- (unsigned long)(o))
-
-/* make a bank representation for each chip cmd/stat/rd value */
-
-/* Commands */
-#define C302F_BNK_CMD_RST C302F_FILL_WORD(I8S5_CMD_RST)
-#define C302F_BNK_CMD_RD_ID C302F_FILL_WORD(I8S5_CMD_RD_ID)
-#define C302F_BNK_CMD_RD_STAT C302F_FILL_WORD(I8S5_CMD_RD_STAT)
-#define C302F_BNK_CMD_CLR_STAT C302F_FILL_WORD(I8S5_CMD_CLR_STAT)
-#define C302F_BNK_CMD_ERASE1 C302F_FILL_WORD(I8S5_CMD_ERASE1)
-#define C302F_BNK_CMD_ERASE2 C302F_FILL_WORD(I8S5_CMD_ERASE2)
-#define C302F_BNK_CMD_PROG C302F_FILL_WORD(I8S5_CMD_PROG)
-#define C302F_BNK_CMD_LOCK C302F_FILL_WORD(I8S5_CMD_LOCK)
-#define C302F_BNK_CMD_SET_LOCK_BLK C302F_FILL_WORD(I8S5_CMD_SET_LOCK_BLK)
-#define C302F_BNK_CMD_SET_LOCK_MSTR C302F_FILL_WORD(I8S5_CMD_SET_LOCK_MSTR)
-#define C302F_BNK_CMD_CLR_LOCK_BLK C302F_FILL_WORD(I8S5_CMD_CLR_LOCK_BLK)
-
-/* status register bits */
-#define C302F_BNK_STAT_DPS C302F_FILL_WORD(I8S5_STAT_DPS)
-#define C302F_BNK_STAT_PSS C302F_FILL_WORD(I8S5_STAT_PSS)
-#define C302F_BNK_STAT_VPPS C302F_FILL_WORD(I8S5_STAT_VPPS)
-#define C302F_BNK_STAT_PSLBS C302F_FILL_WORD(I8S5_STAT_PSLBS)
-#define C302F_BNK_STAT_ECLBS C302F_FILL_WORD(I8S5_STAT_ECLBS)
-#define C302F_BNK_STAT_ESS C302F_FILL_WORD(I8S5_STAT_ESS)
-#define C302F_BNK_STAT_RDY C302F_FILL_WORD(I8S5_STAT_RDY)
-
-#define C302F_BNK_STAT_ERR C302F_FILL_WORD(I8S5_STAT_ERR)
-
-/* ID and Lock Configuration */
-#define C302F_BNK_RD_ID_LOCK C302F_FILL_WORD(I8S5_RD_ID_LOCK)
-#define C302F_BNK_RD_ID_MAN C302F_FILL_WORD(I8S5_RD_ID_MAN)
-#define C302F_BNK_RD_ID_DEV C302F_FILL_WORD(I8S5_RD_ID_DEV)
-
-/*************** DEFINES for Cogent Motherboard Flash ************************/
-
-typedef unsigned short cmbf_word_t; /* 16 bit unsigned integer */
-typedef volatile cmbf_word_t *cmbf_addr_t;
-typedef unsigned long cmbf_size_t; /* want this big - at least 32 bit */
-
-/* layout of banks on cogent motherboard - only 1 bank, 16 bit wide */
-#define CMBF_BNK_WIDTH 1 /* each bank is one chip wide */
-#define CMBF_BNK_WSHIFT 0 /* log base 2 of CMBF_BNK_WIDTH */
-#define CMBF_BNK_NBLOCKS I8B5_NBLOCKS
-#define CMBF_BNK_BLKSZ (I8B5_BLKSZ * CMBF_BNK_WIDTH)
-#define CMBF_BNK_SIZE (I8B5_SIZE * CMBF_BNK_WIDTH)
-
-#define CMBF_MAX_BANKS 1 /* only 1 x 1Mbyte bank on cogent m/b */
-
-/* align addresses and sizes to bank boundaries */
-#define CMBF_BNK_ADDR_ALIGN(a) ((c302f_addr_t)((c302f_size_t)(a) \
- & ~(CMBF_BNK_WIDTH - 1)))
-#define CMBF_BNK_SIZE_ALIGN(s) ((c302f_size_t)CMBF_BNK_ADDR_ALIGN( \
- (c302f_size_t)(s) + (CMBF_BNK_WIDTH - 1)))
-
-/* align addresses and sizes to block boundaries */
-#define CMBF_BLK_ADDR_ALIGN(a) ((c302f_addr_t)((c302f_size_t)(a) \
- & ~(CMBF_BNK_BLKSZ - 1)))
-#define CMBF_BLK_SIZE_ALIGN(s) ((c302f_size_t)CMBF_BLK_ADDR_ALIGN( \
- (c302f_size_t)(s) + (CMBF_BNK_BLKSZ - 1)))
-
-/* add a byte offset to a flash address */
-#define CMBF_ADDR_ADD_BYTEOFF(a,o) \
- (c302f_addr_t)((c302f_size_t)(a) + (o))
-
-/* get base address of bank b, given flash base address a */
-#define CMBF_BNK_ADDR_BASE(a,b) \
- CMBF_ADDR_ADD_BYTEOFF((a), \
- (c302f_size_t)(b) * CMBF_BNK_SIZE)
-
-/* adjust an address a (within a bank) to next word, block or bank */
-#define CMBF_BNK_ADDR_NEXT_WORD(a) \
- CMBF_ADDR_ADD_BYTEOFF((a), CMBF_BNK_WIDTH)
-#define CMBF_BNK_ADDR_NEXT_BLK(a) \
- CMBF_ADDR_ADD_BYTEOFF((a), CMBF_BNK_BLKSZ)
-#define CMBF_BNK_ADDR_NEXT_BNK(a) \
- CMBF_ADDR_ADD_BYTEOFF((a), CMBF_BNK_SIZE)
-
-/* get bank address of chip register r given a bank base address a */
-#define CMBF_BNK_ADDR_I8B5REG(a,r) \
- CMBF_ADDR_ADD_BYTEOFF((a), \
- (r) << CMBF_BNK_WSHIFT)
-
-/* make a bank representation for each chip address */
-
-#define CMBF_BNK_ADDR_MAN(a) CMBF_BNK_ADDR_I8B5REG((a), I8B5_ADDR_MAN)
-#define CMBF_BNK_ADDR_DEV(a) CMBF_BNK_ADDR_I8B5REG((a), I8B5_ADDR_DEV)
-#define CMBF_BNK_ADDR_CFGM(a) CMBF_BNK_ADDR_I8B5REG((a), I8B5_ADDR_CFGM)
-#define CMBF_BNK_ADDR_CFG(b,a) CMBF_BNK_ADDR_I8B5REG((a), I8B5_ADDR_CFG(b))
-
-/*
- * replicate a chip cmd/stat/rd value into each byte position within a word
- * so that multiple chips are accessed in a single word i/o operation
- *
- * this must be as wide as the c302f_word_t type
- */
-#define CMBF_FILL_WORD(o) (((unsigned long)(o) << 24) | \
- ((unsigned long)(o) << 16) | \
- ((unsigned long)(o) << 8) | \
- (unsigned long)(o))
-
-/* make a bank representation for each chip cmd/stat/rd value */
-
-/* Commands */
-#define CMBF_BNK_CMD_RST CMBF_FILL_WORD(I8B5_CMD_RST)
-#define CMBF_BNK_CMD_RD_ID CMBF_FILL_WORD(I8B5_CMD_RD_ID)
-#define CMBF_BNK_CMD_RD_STAT CMBF_FILL_WORD(I8B5_CMD_RD_STAT)
-#define CMBF_BNK_CMD_CLR_STAT CMBF_FILL_WORD(I8B5_CMD_CLR_STAT)
-#define CMBF_BNK_CMD_ERASE1 CMBF_FILL_WORD(I8B5_CMD_ERASE1)
-#define CMBF_BNK_CMD_ERASE2 CMBF_FILL_WORD(I8B5_CMD_ERASE2)
-#define CMBF_BNK_CMD_PROG CMBF_FILL_WORD(I8B5_CMD_PROG)
-#define CMBF_BNK_CMD_LOCK CMBF_FILL_WORD(I8B5_CMD_LOCK)
-#define CMBF_BNK_CMD_SET_LOCK_BLK CMBF_FILL_WORD(I8B5_CMD_SET_LOCK_BLK)
-#define CMBF_BNK_CMD_SET_LOCK_MSTR CMBF_FILL_WORD(I8B5_CMD_SET_LOCK_MSTR)
-#define CMBF_BNK_CMD_CLR_LOCK_BLK CMBF_FILL_WORD(I8B5_CMD_CLR_LOCK_BLK)
-
-/* status register bits */
-#define CMBF_BNK_STAT_DPS CMBF_FILL_WORD(I8B5_STAT_DPS)
-#define CMBF_BNK_STAT_PSS CMBF_FILL_WORD(I8B5_STAT_PSS)
-#define CMBF_BNK_STAT_VPPS CMBF_FILL_WORD(I8B5_STAT_VPPS)
-#define CMBF_BNK_STAT_PSLBS CMBF_FILL_WORD(I8B5_STAT_PSLBS)
-#define CMBF_BNK_STAT_ECLBS CMBF_FILL_WORD(I8B5_STAT_ECLBS)
-#define CMBF_BNK_STAT_ESS CMBF_FILL_WORD(I8B5_STAT_ESS)
-#define CMBF_BNK_STAT_RDY CMBF_FILL_WORD(I8B5_STAT_RDY)
-
-#define CMBF_BNK_STAT_ERR CMBF_FILL_WORD(I8B5_STAT_ERR)
-
-/* ID and Lock Configuration */
-#define CMBF_BNK_RD_ID_LOCK CMBF_FILL_WORD(I8B5_RD_ID_LOCK)
-#define CMBF_BNK_RD_ID_MAN CMBF_FILL_WORD(I8B5_RD_ID_MAN)
-#define CMBF_BNK_RD_ID_DEV CMBF_FILL_WORD(I8B5_RD_ID_DEV)
diff --git a/board/cogent/kbm.c b/board/cogent/kbm.c
deleted file mode 100644
index 8496402..0000000
--- a/board/cogent/kbm.c
+++ /dev/null
@@ -1,3 +0,0 @@
-/* keyboard/mouse not implemented yet */
-
-int cma_kbm_not_implemented = 1;
diff --git a/board/cogent/lcd.c b/board/cogent/lcd.c
deleted file mode 100644
index 05ffc4d..0000000
--- a/board/cogent/lcd.c
+++ /dev/null
@@ -1,245 +0,0 @@
-/* most of this is taken from the file */
-/* hal/powerpc/cogent/current/src/hal_diag.c in the */
-/* Cygnus eCos source. Here is the copyright notice: */
-/* */
-/*============================================================================= */
-/* */
-/* hal_diag.c */
-/* */
-/* HAL diagnostic output code */
-/* */
-/*============================================================================= */
-/*####COPYRIGHTBEGIN#### */
-/* */
-/* ------------------------------------------- */
-/* The contents of this file are subject to the Cygnus eCos Public License */
-/* Version 1.0 (the "License"); you may not use this file except in */
-/* compliance with the License. You may obtain a copy of the License@*/
-/* http://sourceware.cygnus.com/ecos */
-/* */
-/* Software distributed under the License is distributed on an "AS IS" */
-/* basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the */
-/* License for the specific language governing rights and limitations under */
-/* the License. */
-/* */
-/* The Original Code is eCos - Embedded Cygnus Operating System, released */
-/* September 30, 1998. */
-/* */
-/* The Initial Developer of the Original Code is Cygnus. Portions created */
-/* by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. */
-/* ------------------------------------------- */
-/* */
-/*####COPYRIGHTEND#### */
-/*============================================================================= */
-/*#####DESCRIPTIONBEGIN#### */
-/* */
-/* Author(s): nickg, jskov */
-/* Contributors: nickg, jskov */
-/* Date: 1999-03-23 */
-/* Purpose: HAL diagnostic output */
-/* Description: Implementations of HAL diagnostic output support. */
-/* */
-/*####DESCRIPTIONEND#### */
-/* */
-/*============================================================================= */
-
-/*----------------------------------------------------------------------------- */
-/* Cogent board specific LCD code */
-
-#include <common.h>
-#include <stdarg.h>
-#include "lcd.h"
-
-static char lines[2][LCD_LINE_LENGTH+1];
-static int curline;
-static int linepos;
-static int heartbeat_active;
-/* make the next two strings exactly LCD_LINE_LENGTH (16) chars long */
-/* pad to the right with spaces if necessary */
-static char init_line0[LCD_LINE_LENGTH+1] = "U-Boot Cogent ";
-static char init_line1[LCD_LINE_LENGTH+1] = "mjj, 11 Aug 2000";
-
-static inline unsigned char
-lcd_read_status(cma_mb_lcd *clp)
-{
- /* read the Busy Status Register */
- return (cma_mb_reg_read(&clp->lcd_bsr));
-}
-
-static inline void
-lcd_wait_not_busy(cma_mb_lcd *clp)
-{
- /*
- * wait for not busy
- * Note: It seems that the LCD isn't quite ready to process commands
- * when it clears the BUSY flag. Reading the status address an extra
- * time seems to give it enough breathing room.
- */
-
- while (lcd_read_status(clp) & LCD_STAT_BUSY)
- ;
-
- (void)lcd_read_status(clp);
-}
-
-static inline void
-lcd_write_command(cma_mb_lcd *clp, unsigned char cmd)
-{
- lcd_wait_not_busy(clp);
-
- /* write the Command Register */
- cma_mb_reg_write(&clp->lcd_cmd, cmd);
-}
-
-static inline void
-lcd_write_data(cma_mb_lcd *clp, unsigned char data)
-{
- lcd_wait_not_busy(clp);
-
- /* write the Current Character Register */
- cma_mb_reg_write(&clp->lcd_ccr, data);
-}
-
-static inline void
-lcd_dis(int addr, char *string)
-{
- cma_mb_lcd *clp = (cma_mb_lcd *)CMA_MB_LCD_BASE;
- int pos, linelen;
-
- linelen = LCD_LINE_LENGTH;
- if (heartbeat_active && addr == LCD_LINE0)
- linelen--;
-
- lcd_write_command(clp, LCD_CMD_ADD + addr);
- for (pos = 0; *string != '\0' && pos < linelen; pos++)
- lcd_write_data(clp, *string++);
-}
-
-void
-lcd_init(void)
-{
- cma_mb_lcd *clp = (cma_mb_lcd *)CMA_MB_LCD_BASE;
- int i;
-
- /* configure the lcd for 8 bits/char, 2 lines and 5x7 dot matrix */
- lcd_write_command(clp, LCD_CMD_MODE);
-
- /* turn the LCD display on */
- lcd_write_command(clp, LCD_CMD_DON);
-
- curline = 0;
- linepos = 0;
-
- for (i = 0; i < LCD_LINE_LENGTH; i++) {
- lines[0][i] = init_line0[i];
- lines[1][i] = init_line1[i];
- }
-
- lines[0][LCD_LINE_LENGTH] = lines[1][LCD_LINE_LENGTH] = 0;
-
- lcd_dis(LCD_LINE0, lines[0]);
- lcd_dis(LCD_LINE1, lines[1]);
-
- printf("HD44780 2 line x %d char display\n", LCD_LINE_LENGTH);
-}
-
-void
-lcd_write_char(const char c)
-{
- int i, linelen;
-
- /* ignore CR */
- if (c == '\r')
- return;
-
- linelen = LCD_LINE_LENGTH;
- if (heartbeat_active && curline == 0)
- linelen--;
-
- if (c == '\n') {
- lcd_dis(LCD_LINE0, &lines[curline^1][0]);
- lcd_dis(LCD_LINE1, &lines[curline][0]);
-
- /* Do a line feed */
- curline ^= 1;
- linelen = LCD_LINE_LENGTH;
- if (heartbeat_active && curline == 0)
- linelen--;
- linepos = 0;
-
- for (i = 0; i < linelen; i++)
- lines[curline][i] = ' ';
-
- return;
- }
-
- /* Only allow to be output if there is room on the LCD line */
- if (linepos < linelen)
- lines[curline][linepos++] = c;
-}
-
-void
-lcd_flush(void)
-{
- lcd_dis(LCD_LINE1, &lines[curline][0]);
-}
-
-void
-lcd_write_string(const char *s)
-{
- char *p;
-
- for (p = (char *)s; *p != '\0'; p++)
- lcd_write_char(*p);
-}
-
-void
-lcd_printf(const char *fmt, ...)
-{
- va_list args;
- char buf[CONFIG_SYS_PBSIZE];
-
- va_start(args, fmt);
- (void)vsprintf(buf, fmt, args);
- va_end(args);
-
- lcd_write_string(buf);
-}
-
-void
-lcd_heartbeat(void)
-{
- cma_mb_lcd *clp = (cma_mb_lcd *)CMA_MB_LCD_BASE;
-#if 0
- static char rotchars[] = { '|', '/', '-', '\\' };
-#else
- /* HD44780 Rom Code A00 has no backslash */
- static char rotchars[] = { '|', '/', '-', '\315' };
-#endif
- static int rotator_index = 0;
-
- heartbeat_active = 1;
-
- /* write the address */
- lcd_write_command(clp, LCD_CMD_ADD + LCD_LINE0 + (LCD_LINE_LENGTH - 1));
-
- /* write the next char in the sequence */
- lcd_write_data(clp, rotchars[rotator_index]);
-
- if (++rotator_index >= (sizeof rotchars / sizeof rotchars[0]))
- rotator_index = 0;
-}
-
-#ifdef CONFIG_SHOW_ACTIVITY
-void board_show_activity (ulong timestamp)
-{
-#ifdef CONFIG_STATUS_LED
- if ((timestamp % (CONFIG_SYS_HZ / 2)) == 0)
- lcd_heartbeat ();
-#endif
-}
-
-void show_activity(int arg)
-{
-}
-#endif
diff --git a/board/cogent/lcd.h b/board/cogent/lcd.h
deleted file mode 100644
index 9e6157e..0000000
--- a/board/cogent/lcd.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/* most of this is taken from the file */
-/* hal/powerpc/cogent/current/src/hal_diag.c in the */
-/* Cygnus eCos source. Here is the copyright notice: */
-/* */
-/*============================================================================= */
-/* */
-/* hal_diag.c */
-/* */
-/* HAL diagnostic output code */
-/* */
-/*============================================================================= */
-/*####COPYRIGHTBEGIN#### */
-/* */
-/* ------------------------------------------- */
-/* The contents of this file are subject to the Cygnus eCos Public License */
-/* Version 1.0 (the "License"); you may not use this file except in */
-/* compliance with the License. You may obtain a copy of the License at */
-/* http://sourceware.cygnus.com/ecos */
-/* */
-/* Software distributed under the License is distributed on an "AS IS" */
-/* basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the */
-/* License for the specific language governing rights and limitations under */
-/* the License. */
-/* */
-/* The Original Code is eCos - Embedded Cygnus Operating System, released */
-/* September 30, 1998. */
-/* */
-/* The Initial Developer of the Original Code is Cygnus. Portions created */
-/* by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. */
-/* ------------------------------------------- */
-/* */
-/*####COPYRIGHTEND#### */
-/*============================================================================= */
-/*#####DESCRIPTIONBEGIN#### */
-/* */
-/* Author(s): nickg, jskov */
-/* Contributors: nickg, jskov */
-/* Date: 1999-03-23 */
-/* Purpose: HAL diagnostic output */
-/* Description: Implementations of HAL diagnostic output support. */
-/* */
-/*####DESCRIPTIONEND#### */
-/* */
-/*============================================================================= */
-
-/* FEMA 162B 16 character x 2 line LCD */
-
-/* status register bit definitions */
-#define LCD_STAT_BUSY 0x80 /* 1 = display busy */
-#define LCD_STAT_ADD 0x7F /* bits 0-6 return current display address */
-
-/* command register definitions */
-#define LCD_CMD_RST 0x01 /* clear entire display and reset display addr */
-#define LCD_CMD_HOME 0x02 /* reset display address and reset any shifting */
-#define LCD_CMD_ECL 0x04 /* move cursor left one pos on next data write */
-#define LCD_CMD_ESL 0x05 /* shift display left one pos on next data write */
-#define LCD_CMD_ECR 0x06 /* move cursor right one pos on next data write */
-#define LCD_CMD_ESR 0x07 /* shift disp right one pos on next data write */
-#define LCD_CMD_DOFF 0x08 /* display off, cursor off, blinking off */
-#define LCD_CMD_BL 0x09 /* blink character at current cursor position */
-#define LCD_CMD_CUR 0x0A /* enable cursor on */
-#define LCD_CMD_DON 0x0C /* turn display on */
-#define LCD_CMD_CL 0x10 /* move cursor left one position */
-#define LCD_CMD_SL 0x14 /* shift display left one position */
-#define LCD_CMD_CR 0x18 /* move cursor right one position */
-#define LCD_CMD_SR 0x1C /* shift display right one position */
-#define LCD_CMD_MODE 0x38 /* sets 8 bits, 2 lines, 5x7 characters */
-#define LCD_CMD_ACG 0x40 /* bits 0-5 sets character generator address */
-#define LCD_CMD_ADD 0x80 /* bits 0-6 sets display data addr to line 1 + */
-
-/* LCD status values */
-#define LCD_OK 0x00
-#define LCD_ERR 0x01
-
-#define LCD_LINE0 0x00
-#define LCD_LINE1 0x40
-
-#define LCD_LINE_LENGTH 16
-
-extern void lcd_init(void);
-extern void lcd_write_char(const char);
-extern void lcd_flush(void);
-extern void lcd_write_string(const char *);
-extern void lcd_printf(const char *, ...);
diff --git a/board/cogent/mb.c b/board/cogent/mb.c
deleted file mode 100644
index c025643..0000000
--- a/board/cogent/mb.c
+++ /dev/null
@@ -1,280 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include "dipsw.h"
-#include "lcd.h"
-#include "rtc.h"
-#include "par.h"
-#include "pci.h"
-
-/* ------------------------------------------------------------------------- */
-
-#if defined(CONFIG_MPC8260)
-
-#include <ioports.h>
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
- /* Port A configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PA31 */ {0, 0, 0, 0, 0, 0},
- /* PA30 */ {0, 0, 0, 0, 0, 0},
- /* PA29 */ {0, 0, 0, 0, 0, 0},
- /* PA28 */ {0, 0, 0, 0, 0, 0},
- /* PA27 */ {0, 0, 0, 0, 0, 0},
- /* PA26 */ {0, 0, 0, 0, 0, 0},
- /* PA25 */ {0, 0, 0, 0, 0, 0},
- /* PA24 */ {0, 0, 0, 0, 0, 0},
- /* PA23 */ {0, 0, 0, 0, 0, 0},
- /* PA22 */ {0, 0, 0, 0, 0, 0},
- /* PA21 */ {0, 0, 0, 0, 0, 0},
- /* PA20 */ {0, 0, 0, 0, 0, 0},
- /* PA19 */ {0, 0, 0, 0, 0, 0},
- /* PA18 */ {0, 0, 0, 0, 0, 0},
- /* PA17 */ {0, 0, 0, 0, 0, 0},
- /* PA16 */ {0, 0, 0, 0, 0, 0},
- /* PA15 */ {0, 0, 0, 0, 0, 0},
- /* PA14 */ {0, 0, 0, 0, 0, 0},
- /* PA13 */ {0, 0, 0, 0, 0, 0},
- /* PA12 */ {0, 0, 0, 0, 0, 0},
- /* PA11 */ {0, 0, 0, 0, 0, 0},
- /* PA10 */ {0, 0, 0, 0, 0, 0},
- /* PA9 */ {1, 1, 0, 1, 0, 0},
- /* SMC2 TXD */
- /* PA8 */ {1, 1, 0, 0, 0, 0},
- /* SMC2 RXD */
- /* PA7 */ {0, 0, 0, 0, 0, 0},
- /* PA6 */ {0, 0, 0, 0, 0, 0},
- /* PA5 */ {0, 0, 0, 0, 0, 0},
- /* PA4 */ {0, 0, 0, 0, 0, 0},
- /* PA3 */ {0, 0, 0, 0, 0, 0},
- /* PA2 */ {0, 0, 0, 0, 0, 0},
- /* PA1 */ {0, 0, 0, 0, 0, 0},
- /* PA0 */ {0, 0, 0, 0, 0, 0}
- },
-
-
- { /* conf ppar psor pdir podr pdat */
- /* PB31 */ {0, 0, 0, 0, 0, 0},
- /* PB30 */ {0, 0, 0, 0, 0, 0},
- /* PB29 */ {0, 0, 0, 0, 0, 0},
- /* PB28 */ {0, 0, 0, 0, 0, 0},
- /* PB27 */ {0, 0, 0, 0, 0, 0},
- /* PB26 */ {0, 0, 0, 0, 0, 0},
- /* PB25 */ {0, 0, 0, 0, 0, 0},
- /* PB24 */ {0, 0, 0, 0, 0, 0},
- /* PB23 */ {0, 0, 0, 0, 0, 0},
- /* PB22 */ {0, 0, 0, 0, 0, 0},
- /* PB21 */ {0, 0, 0, 0, 0, 0},
- /* PB20 */ {0, 0, 0, 0, 0, 0},
- /* PB19 */ {0, 0, 0, 0, 0, 0},
- /* PB18 */ {0, 0, 0, 0, 0, 0},
- /* PB17 */ {0, 0, 0, 0, 0, 0},
- /* PB16 */ {0, 0, 0, 0, 0, 0},
- /* PB15 */ {0, 0, 0, 0, 0, 0},
- /* PB14 */ {0, 0, 0, 0, 0, 0},
- /* PB13 */ {0, 0, 0, 0, 0, 0},
- /* PB12 */ {0, 0, 0, 0, 0, 0},
- /* PB11 */ {0, 0, 0, 0, 0, 0},
- /* PB10 */ {0, 0, 0, 0, 0, 0},
- /* PB9 */ {0, 0, 0, 0, 0, 0},
- /* PB8 */ {0, 0, 0, 0, 0, 0},
- /* PB7 */ {0, 0, 0, 0, 0, 0},
- /* PB6 */ {0, 0, 0, 0, 0, 0},
- /* PB5 */ {0, 0, 0, 0, 0, 0},
- /* PB4 */ {0, 0, 0, 0, 0, 0},
- /* PB3 */ {0, 0, 0, 0, 0, 0},
- /* pin doesn't exist */
- /* PB2 */ {0, 0, 0, 0, 0, 0},
- /* pin doesn't exist */
- /* PB1 */ {0, 0, 0, 0, 0, 0},
- /* pin doesn't exist */
- /* PB0 */ {0, 0, 0, 0, 0, 0}
- /* pin doesn't exist */
- },
-
-
- { /* conf ppar psor pdir podr pdat */
- /* PC31 */ {0, 0, 0, 0, 0, 0},
- /* PC30 */ {0, 0, 0, 0, 0, 0},
- /* PC29 */ {0, 0, 0, 0, 0, 0},
- /* PC28 */ {0, 0, 0, 0, 0, 0},
- /* PC27 */ {0, 0, 0, 0, 0, 0},
- /* PC26 */ {0, 0, 0, 0, 0, 0},
- /* PC25 */ {0, 0, 0, 0, 0, 0},
- /* PC24 */ {0, 0, 0, 0, 0, 0},
- /* PC23 */ {0, 0, 0, 0, 0, 0},
- /* PC22 */ {0, 0, 0, 0, 0, 0},
- /* PC21 */ {0, 0, 0, 0, 0, 0},
- /* PC20 */ {0, 0, 0, 0, 0, 0},
- /* PC19 */ {0, 0, 0, 0, 0, 0},
- /* PC18 */ {0, 0, 0, 0, 0, 0},
- /* PC17 */ {0, 0, 0, 0, 0, 0},
- /* PC16 */ {0, 0, 0, 0, 0, 0},
- /* PC15 */ {0, 0, 0, 0, 0, 0},
- /* PC14 */ {0, 0, 0, 0, 0, 0},
- /* PC13 */ {0, 0, 0, 0, 0, 0},
- /* PC12 */ {0, 0, 0, 0, 0, 0},
- /* PC11 */ {0, 0, 0, 0, 0, 0},
- /* PC10 */ {0, 0, 0, 0, 0, 0},
- /* PC9 */ {0, 0, 0, 0, 0, 0},
- /* PC8 */ {0, 0, 0, 0, 0, 0},
- /* PC7 */ {0, 0, 0, 0, 0, 0},
- /* PC6 */ {0, 0, 0, 0, 0, 0},
- /* PC5 */ {0, 0, 0, 0, 0, 0},
- /* PC4 */ {0, 0, 0, 0, 0, 0},
- /* PC3 */ {0, 0, 0, 0, 0, 0},
- /* PC2 */ {0, 0, 0, 0, 0, 0},
- /* PC1 */ {0, 0, 0, 0, 0, 0},
- /* PC0 */ {0, 0, 0, 0, 0, 0}
- },
-
-
- { /* conf ppar psor pdir podr pdat */
- /* PD31 */ {0, 0, 0, 0, 0, 0},
- /* PD30 */ {0, 0, 0, 0, 0, 0},
- /* PD29 */ {0, 0, 0, 0, 0, 0},
- /* PD28 */ {0, 0, 0, 0, 0, 0},
- /* PD27 */ {0, 0, 0, 0, 0, 0},
- /* PD26 */ {0, 0, 0, 0, 0, 0},
- /* PD25 */ {0, 0, 0, 0, 0, 0},
- /* PD24 */ {0, 0, 0, 0, 0, 0},
- /* PD23 */ {0, 0, 0, 0, 0, 0},
- /* PD22 */ {0, 0, 0, 0, 0, 0},
- /* PD21 */ {0, 0, 0, 0, 0, 0},
- /* PD20 */ {0, 0, 0, 0, 0, 0},
- /* PD19 */ {0, 0, 0, 0, 0, 0},
- /* PD18 */ {0, 0, 0, 0, 0, 0},
- /* PD17 */ {0, 0, 0, 0, 0, 0},
- /* PD16 */ {0, 0, 0, 0, 0, 0},
- /* PD15 */ {1, 1, 1, 0, 0, 0},
- /* I2C SDA */
- /* PD14 */ {1, 1, 1, 0, 0, 0},
- /* I2C SCL */
- /* PD13 */ {0, 0, 0, 0, 0, 0},
- /* PD12 */ {0, 0, 0, 0, 0, 0},
- /* PD11 */ {0, 0, 0, 0, 0, 0},
- /* PD10 */ {0, 0, 0, 0, 0, 0},
- /* PD9 */ {1, 1, 0, 1, 0, 0},
- /* SMC1 TXD */
- /* PD8 */ {1, 1, 0, 0, 0, 0},
- /* SMC1 RXD */
- /* PD7 */ {0, 0, 0, 0, 0, 0},
- /* PD6 */ {0, 0, 0, 0, 0, 0},
- /* PD5 */ {0, 0, 0, 0, 0, 0},
- /* PD4 */ {0, 0, 0, 0, 0, 0},
- /* PD3 */ {0, 0, 0, 0, 0, 0},
- /* pin doesn't exist */
- /* PD2 */ {0, 0, 0, 0, 0, 0},
- /* pin doesn't exist */
- /* PD1 */ {0, 0, 0, 0, 0, 0},
- /* pin doesn't exist */
- /* PD0 */ {0, 0, 0, 0, 0, 0}
- /* pin doesn't exist */
- }
-};
-
-#endif /* CONFIG_MPC8260 */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check Board Identity:
- */
-
-int checkboard (void)
-{
- puts ("Board: Cogent " COGENT_MOTHERBOARD " motherboard with a "
- COGENT_CPU_MODULE " CPU Module\n");
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Miscelaneous platform dependent initialisations while still
- * running in flash
- */
-
-int misc_init_f (void)
-{
- printf ("DIPSW: ");
- dipsw_init ();
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
-#ifdef CONFIG_CMA111
- return (32L * 1024L * 1024L);
-#else
- unsigned char dipsw_val;
- int dual, size0, size1;
- long int memsize;
-
- dipsw_val = dipsw_cooked ();
-
- dual = dipsw_val & 0x01;
- size0 = (dipsw_val & 0x08) >> 3;
- size1 = (dipsw_val & 0x04) >> 2;
-
- if (size0)
- if (size1)
- memsize = 16L * 1024L * 1024L;
- else
- memsize = 1L * 1024L * 1024L;
- else if (size1)
- memsize = 4L * 1024L * 1024L;
- else {
- printf ("[Illegal dip switch settings - assuming 16Mbyte SIMMs] ");
- memsize = 16L * 1024L * 1024L; /* shouldn't happen - guess 16M */
- }
-
- if (dual)
- memsize *= 2L;
-
- return (memsize);
-#endif
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Miscelaneous platform dependent initialisations after monitor
- * has been relocated into ram
- */
-
-int misc_init_r (void)
-{
- printf ("LCD: ");
- lcd_init ();
-
-#if 0
- printf ("RTC: ");
- rtc_init ();
-
- printf ("PAR: ");
- par_init ();
-
- printf ("KBM: ");
- kbm_init ();
-
- printf ("PCI: ");
- pci_init ();
-#endif
- return (0);
-}
diff --git a/board/cogent/mb.h b/board/cogent/mb.h
deleted file mode 100644
index 1db516f..0000000
--- a/board/cogent/mb.h
+++ /dev/null
@@ -1,513 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * defines for Cogent Motherboards
- */
-
-#ifndef _COGENT_MB_H
-#define _COGENT_MB_H
-
-/*
- * Cogent Motherboard Address Map
- *
- * The size of a Cogent motherboard address space is 256 Mbytes (i.e. 28 bits).
- *
- * The first 32 Mbyte (0x0000000-0x1FFFFFF) is usually RAM. The following
- * 3 x 32 Mbyte areas (0x2000000-0x3FFFFFF, 0x4000000-0x5FFFFFF and
- * 0x6000000-0x7FFFFFF) are general I/O "slots" (slots 1, 2 and 3).
- * Most other motherboard devices have registers mapped into the area
- * 0xE000000-0xFFFFFFF (Motherboard I/O slot?). The area 0x8000000-0xDFFFFFF
- * is free for whatever.
- *
- * The location of the motherboard address space in the physical address space
- * of the cpu is given by CMA_MB_BASE. This value is determined by the cpu
- * module plugged into the motherboard and is configured above.
- *
- * Motherboard I/O devices mapped into the area (0xE000000-0xFFFFFFF)
- * generally only use byte lane 0 (D0-7) for their transfers, i.e. only
- * 8 bit, or 1 byte, transfers can take place, so all the registers are
- * only 8 bits wide. The exceptions are the motherboard flash, which uses
- * byte lanes 0 and 1 (i.e. 16 bits), and the mapped PCI address space.
- *
- * I/O registers within the mapped motherboard devices are 64 bit aligned
- * i.e. they are 8 bytes apart. For big endian addressing, the 8 bit register
- * will be at byte 7 (the address + 7). For little endian addressing, the
- * register will be at byte 0 (the address + 0). To learn the endianess
- * we must include <endian.h>
- *
- * Take the CMA102 and CMA111 motherboards as examples...
- *
- * The CMA102 has three CMABus I/O Expansion slots and no PCI bridge. The 3
- * CMABus slots are each mapped directly onto the three general I/O slots.
- *
- * The CMA111 has only one CMABus I/O Expansion slot, but has a V360EPC PCI
- * bridge. The CMABus slot is mapped onto general I/O slot 1. The standard
- * PCI Bus space is mapped onto general I/O slot 2, with a small area at the
- * top reserved for access to the V360EPC registers (0x5FF0000-0x5FFFFFF).
- * I/O slot 3 is unused. The extended PCI Bus space is mapped onto the area
- * 0xA000000-0xDFFFFFF.
- */
-
-#define CMA_MB_RAM_BASE (CONFIG_SYS_CMA_MB_BASE+0x0000000)
-#define CMA_MB_RAM_SIZE 0x2000000 /* dip sws set actual size */
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT1)
-#define CMA_MB_SLOT1_BASE (CONFIG_SYS_CMA_MB_BASE+0x2000000)
-#define CMA_MB_SLOT1_SIZE 0x2000000
-#endif
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT2)
-#define CMA_MB_SLOT2_BASE (CONFIG_SYS_CMA_MB_BASE+0x4000000)
-#define CMA_MB_SLOT2_SIZE 0x2000000
-#endif
-#if (CMA_MB_CAPS & CMA_MB_CAP_PCI)
-#define CMA_MB_STDPCI_BASE (CONFIG_SYS_CMA_MB_BASE+0x4000000)
-#define CMA_MB_STDPCI_SIZE 0x1ff0000
-#define CMA_MB_V360EPC_BASE (CONFIG_SYS_CMA_MB_BASE+0x5ff0000)
-#define CMA_MB_V360EPC_SIZE 0x10000
-#endif
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT3)
-#define CMA_MB_SLOT3_BASE (CONFIG_SYS_CMA_MB_BASE+0x6000000)
-#define CMA_MB_SLOT3_SIZE 0x2000000
-#endif
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_PCI_EXT)
-#define CMA_MB_EXTPCI_BASE (CONFIG_SYS_CMA_MB_BASE+0xa000000)
-#define CMA_MB_EXTPCI_SIZE 0x4000000
-#endif
-
-#define CMA_MB_ROMLOW_BASE (CONFIG_SYS_CMA_MB_BASE+0xe000000)
-#define CMA_MB_ROMLOW_SIZE 0x800000
-#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
-#define CMA_MB_FLLOW_EXEC_BASE (CONFIG_SYS_CMA_MB_BASE+0xe000000)
-#define CMA_MB_FLLOW_EXEC_SIZE 0x100000
-#define CMA_MB_FLLOW_RDWR_BASE (CONFIG_SYS_CMA_MB_BASE+0xe400000)
-#define CMA_MB_FLLOW_RDWR_SIZE 0x400000
-#endif
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_RTC)
-#define CMA_MB_RTC_BASE (CONFIG_SYS_CMA_MB_BASE+0xe800000)
-#define CMA_MB_RTC_SIZE 0x4000
-#endif
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_SERPAR)
-#define CMA_MB_SERPAR_BASE (CONFIG_SYS_CMA_MB_BASE+0xe900000)
-#define CMA_MB_SERIALB_BASE (CMA_MB_SERPAR_BASE+0x00)
-#define CMA_MB_SERIALA_BASE (CMA_MB_SERPAR_BASE+0x40)
-#define CMA_MB_PARALLEL_BASE (CMA_MB_SERPAR_BASE+0x80)
-#define CMA_MB_SERPAR_SIZE 0xa0
-#endif
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_KBM)
-#define CMA_MB_PKBM_BASE (CONFIG_SYS_CMA_MB_BASE+0xe900100)
-#define CMA_MB_PKBM_SIZE 0x10
-#endif
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_LCD)
-#define CMA_MB_LCD_BASE (CONFIG_SYS_CMA_MB_BASE+0xeb00000)
-#define CMA_MB_LCD_SIZE 0x10
-#endif
-
-#define CMA_MB_DIPSW_BASE (CONFIG_SYS_CMA_MB_BASE+0xec00000)
-#define CMA_MB_DIPSW_SIZE 0x10
-
-#if (CMA_MB_CAPS & (CMA_MB_CAP_SLOT1|CMA_MB_CAP_SER2|CMA_MB_CAP_KBM))
-#define CMA_MB_SLOT1CFG_BASE (CONFIG_SYS_CMA_MB_BASE+0xf100000)
-#if (CMA_MB_CAPS & CMA_MB_CAP_SER2)
-#define CMA_MB_SER2_BASE (CMA_MB_SLOT1CFG_BASE+0x80)
-#define CMA_MB_SER2B_BASE (CMA_MB_SER2_BASE+0x00)
-#define CMA_MB_SER2A_BASE (CMA_MB_SER2_BASE+0x40)
-#endif
-#if defined(CONFIG_CMA302) && defined(CONFIG_CMA302_SLOT1)
-#define CMA_MB_S1KBM_BASE (CMA_MB_SLOT1CFG_BASE+0x200)
-#endif
-#if (CMA_MB_CAPS & CMA_MB_CAP_KBM) && !defined(COGENT_CMA150)
-#define CMA_MB_IREQ1STAT_BASE (CMA_MB_SLOT1CFG_BASE+0x100)
-#define CMA_MB_AKBM_BASE (CMA_MB_SLOT1CFG_BASE+0x200)
-#define CMA_MB_IREQ1MASK_BASE (CMA_MB_SLOT1CFG_BASE+0x300)
-#endif
-#define CMA_MB_SLOT1CFG_SIZE 0x400
-#endif
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT2)
-#define CMA_MB_SLOT2CFG_BASE (CONFIG_SYS_CMA_MB_BASE+0xf200000)
-#if defined(CONFIG_CMA302) && defined(CONFIG_CMA302_SLOT2)
-#define CMA_MB_S2KBM_BASE (CMA_MB_SLOT2CFG_BASE+0x200)
-#endif
-#define CMA_MB_SLOT2CFG_SIZE 0x400
-#endif
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_PCI)
-#define CMA_MB_PCICTL_BASE (CONFIG_SYS_CMA_MB_BASE+0xf200000)
-#define CMA_MB_PCI_V3CTL_BASE (CMA_MB_PCICTL_BASE+0x100)
-#define CMA_MB_PCI_IDSEL_BASE (CMA_MB_PCICTL_BASE+0x200)
-#define CMA_MB_PCI_IMASK_BASE (CMA_MB_PCICTL_BASE+0x300)
-#define CMA_MB_PCI_ISTAT_BASE (CMA_MB_PCICTL_BASE+0x400)
-#define CMA_MB_PCI_MBID_BASE (CMA_MB_PCICTL_BASE+0x500)
-#define CMA_MB_PCI_MBREV_BASE (CMA_MB_PCICTL_BASE+0x600)
-#define CMA_MB_PCICTL_SIZE 0x700
-#endif
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT3)
-#define CMA_MB_SLOT3CFG_BASE (CONFIG_SYS_CMA_MB_BASE+0xf300000)
-#if defined(CONFIG_CMA302) && defined(CONFIG_CMA302_SLOT3)
-#define CMA_MB_S3KBM_BASE (CMA_MB_SLOT3CFG_BASE+0x200)
-#endif
-#define CMA_MB_SLOT3CFG_SIZE 0x400
-#endif
-
-#define CMA_MB_ROMHIGH_BASE (CONFIG_SYS_CMA_MB_BASE+0xf800000)
-#define CMA_MB_ROMHIGH_SIZE 0x800000
-#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
-#define CMA_MB_FLHIGH_EXEC_BASE (CONFIG_SYS_CMA_MB_BASE+0xf800000)
-#define CMA_MB_FLHIGH_EXEC_SIZE 0x100000
-#define CMA_MB_FLHIGH_RDWR_BASE (CONFIG_SYS_CMA_MB_BASE+0xfc00000)
-#define CMA_MB_FLHIGH_RDWR_SIZE 0x400000
-#endif
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_PCI)
-
-/* PCI Control Register bits */
-
-/* V360EPC Control register bits */
-#define CMA_MB_PCI_V3CTL_RESET 0x01
-#define CMA_MB_PCI_V3CTL_EXTADD 0x08
-
-/* PCI ID Select register bits */
-#define CMA_MB_PCI_IDSEL_SLOTA 0x01
-#define CMA_MB_PCI_IDSEL_SLOTB 0x02
-#define CMA_MB_PCI_IDSEL_GD82559 0x04
-#define CMA_MB_PCI_IDSEL_B69000 0x08
-#define CMA_MB_PCI_IDSEL_PD6832 0x10
-
-/* PCI Interrupt Mask/Status register bits */
-#define CMA_MB_PCI_IMS_INTA 0x01
-#define CMA_MB_PCI_IMS_INTB 0x02
-#define CMA_MB_PCI_IMS_INTC 0x04
-#define CMA_MB_PCI_IMS_INTD 0x08
-#define CMA_MB_PCI_IMS_CBINT 0x10
-#define CMA_MB_PCI_IMS_V3LINT 0x80
-
-#endif
-
-#if (CMA_MB_CAPS & (CMA_MB_CAP_KBM|CMA_MB_CAP_SER2)) && !defined(COGENT_CMA150)
-
-/*
- * IREQ1 Interrupt Mask/Status register bits
- * (Note: not available on CMA150 - must poll HT6542B interrupt register)
- */
-
-#define IREQ1_MINT 0x01
-#define IREQ1_KINT 0x02
-#if (CMA_MB_CAPS & CMA_MB_CAP_SER2)
-#define IREQ1_SINT2 0x04
-#define IREQ1_SINT3 0x08
-#endif
-
-#endif
-
-#ifndef __ASSEMBLY__
-
-#ifdef USE_HOSTCC
-#include <endian.h> /* avoid using private kernel header files */
-#else
-#include <asm/byteorder.h> /* use U-Boot provided headers */
-#endif
-
-/* a single CMA10x motherboard i/o register */
-typedef
- struct {
-#if __BYTE_ORDER == __LITTLE_ENDIAN
- unsigned char value;
-#endif
- unsigned char filler[7];
-#if __BYTE_ORDER == __BIG_ENDIAN
- unsigned char value;
-#endif
- }
-cma_mb_reg;
-
-extern __inline__ unsigned char
-cma_mb_reg_read(volatile cma_mb_reg *reg)
-{
- unsigned char data = reg->value;
- __asm__ __volatile__ ("eieio" : : : "memory");
- return data;
-}
-
-extern __inline__ void
-cma_mb_reg_write(volatile cma_mb_reg *reg, unsigned char data)
-{
- reg->value = data;
- __asm__ __volatile__ ("eieio" : : : "memory");
-}
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_RTC)
-
-/* MK48T02 RTC registers */
-typedef
- struct {
- cma_mb_reg sram[2040];/* Battery-Backed SRAM */
- cma_mb_reg clk_ctl; /* Clock Control Register */
- cma_mb_reg clk_sec; /* Clock Seconds Register */
- cma_mb_reg clk_min; /* Clock Minutes Register */
- cma_mb_reg clk_hour; /* Clock Hour Register */
- cma_mb_reg clk_day; /* Clock Day Register */
- cma_mb_reg clk_date; /* Clock Date Register */
- cma_mb_reg clk_month; /* Clock Month Register */
- cma_mb_reg clk_year; /* Clock Year Register */
- }
-cma_mb_rtc;
-
-#endif
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_SERPAR)
-
-/* ST16C522 Serial I/O */
-typedef
- struct {
- cma_mb_reg ser_rhr; /* Receive Holding Register (R, DLAB=0) */
- cma_mb_reg ser_ier; /* Interrupt Enable Register (R/W, DLAB=0) */
- cma_mb_reg ser_isr; /* Interrupt Status Register (R) */
- cma_mb_reg ser_lcr; /* Line Control Register (R/W) */
- cma_mb_reg ser_mcr; /* Modem Control Register (R/W) */
- cma_mb_reg ser_lsr; /* Line Status Register (R) */
- cma_mb_reg ser_msr; /* Modem Status Register (R/W) */
- cma_mb_reg ser_spr; /* Scratch Pad Register (R/W) */
- }
-cma_mb_serial;
-
-#define ser_thr ser_rhr /* Transmit Holding Register (W, DLAB=0) */
-#define ser_brl ser_rhr /* Baud Rate Divisor Low Byte (R/W, DLAB=1) */
-#define ser_brh ser_ier /* Baud Rate Divisor High Byte (R/W, DLAB=1) */
-#define ser_fcr ser_isr /* FIFO Control Register (W) */
-#define ser_nop ser_lsr /* No Operation (W) */
-
-/* ST16C522 Parallel I/O */
-typedef
- struct {
- cma_mb_reg par_rdr; /* Port Read Data Register (R) */
- cma_mb_reg par_sr; /* Status Register (R) */
- cma_mb_reg par_cmd; /* Command Register (R) */
- }
-cma_mb_parallel;
-
-#define par_wdr par_rdr /* Port Write Data Register (W) */
-#define par_ios par_sr /* I/O Select Register (W) */
-#define par_ctl par_cmd /* Control Register (W) */
-
-#endif
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_KBM) || defined(CONFIG_CMA302)
-
-/* HT6542B PS/2 Keyboard/Mouse Controller */
-typedef
- struct {
- cma_mb_reg kbm_rdr; /* Read Data Register (R) */
- cma_mb_reg kbm_sr; /* Status Register (R) */
- }
-cma_mb_kbm;
-
-#define kbm_wdr kbm_rdr /* Write Data Register (W) */
-#define kbm_cmd kbm_sr /* Command Register (W) */
-
-#endif
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_LCD)
-
-/* HD44780 LCD Display */
-typedef
- struct {
- cma_mb_reg lcd_ccr; /* Current Character Register (R/W) */
- cma_mb_reg lcd_bsr; /* Busy Status Register (R) */
- }
-cma_mb_lcd;
-
-#define lcd_cmd lcd_bsr /* Command Register (W) */
-
-#endif
-
-/* 8-Position Configuration Switch */
-typedef
- struct {
- cma_mb_reg dip_val; /* Dip Switch value (R) */
- }
-cma_mb_dipsw;
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_PCI)
-
-/* V360EPC PCI Bridge */
-typedef
- struct {
-#if __BYTE_ORDER == __LITTLE_ENDIAN
- unsigned short v3_pci_vendor; /* 0x00 */
- unsigned short v3_pci_device;
- unsigned short v3_pci_cmd; /* 0x04 */
- unsigned short v3_pci_stat;
- unsigned long v3_pci_cc_rev; /* 0x08 */
- unsigned long v3_pci_hdr_cfg; /* 0x0c */
- unsigned long v3_pci_io_base; /* 0x10 */
- unsigned long v3_pci_base0; /* 0x14 */
- unsigned long v3_pci_base1; /* 0x18 */
- unsigned long reserved1[4]; /* 0x1c */
- unsigned short v3_pci_sub_vendor; /* 0x2c */
- unsigned short v3_pci_sub_id;
- unsigned long v3_pci_rom; /* 0x30 */
- unsigned long reserved2[2]; /* 0x34 */
- unsigned long v3_pci_bparam; /* 0x3c */
- unsigned long v3_pci_map0; /* 0x40 */
- unsigned long v3_pci_map1; /* 0x44 */
- unsigned long v3_pci_int_stat; /* 0x48 */
- unsigned long v3_pci_int_cfg; /* 0x4c */
- unsigned long reserved3[1]; /* 0x50 */
- unsigned long v3_lb_base0; /* 0x54 */
- unsigned long v3_lb_base1; /* 0x58 */
- unsigned short reserved4; /* 0x5c */
- unsigned short v3_lb_map0;
- unsigned short reserved5; /* 0x60 */
- unsigned short v3_lb_map1;
- unsigned short v3_lb_base2; /* 0x64 */
- unsigned short v3_lb_map2;
- unsigned long v3_lb_size; /* 0x68 */
- unsigned short reserved6; /* 0x6c */
- unsigned short v3_lb_io_base;
- unsigned short v3_fifo_cfg; /* 0x70 */
- unsigned short v3_fifo_priority;
- unsigned short v3_fifo_stat; /* 0x74 */
- unsigned char v3_lb_istat;
- unsigned char v3_lb_imask;
- unsigned short v3_system; /* 0x78 */
- unsigned short v3_lb_cfg;
- unsigned short v3_pci_cfg; /* 0x7c */
- unsigned short reserved7;
- unsigned long v3_dma_pci_addr0; /* 0x80 */
- unsigned long v3_dma_local_addr0; /* 0x84 */
- unsigned long v3_dma_length0:24; /* 0x88 */
- unsigned long v3_dma_csr0:8;
- unsigned long v3_dma_ctlb_adr0; /* 0x8c */
- unsigned long v3_dma_pci_addr1; /* 0x90 */
- unsigned long v3_dma_local_addr1; /* 0x94 */
- unsigned long v3_dma_length1:24; /* 0x98 */
- unsigned long v3_dma_csr1:8;
- unsigned long v3_dma_ctlb_adr1; /* 0x9c */
- unsigned long v3_i20_mups[8]; /* 0xa0 */
- unsigned char v3_mail_data0; /* 0xc0 */
- unsigned char v3_mail_data1;
- unsigned char v3_mail_data2;
- unsigned char v3_mail_data3;
- unsigned char v3_mail_data4; /* 0xc4 */
- unsigned char v3_mail_data5;
- unsigned char v3_mail_data6;
- unsigned char v3_mail_data7;
- unsigned char v3_mail_data8; /* 0xc8 */
- unsigned char v3_mail_data9;
- unsigned char v3_mail_data10;
- unsigned char v3_mail_data11;
- unsigned char v3_mail_data12; /* 0xcc */
- unsigned char v3_mail_data13;
- unsigned char v3_mail_data14;
- unsigned char v3_mail_data15;
- unsigned short v3_pci_mail_iewr; /* 0xd0 */
- unsigned short v3_pci_mail_ierd;
- unsigned short v3_lb_mail_iewr; /* 0xd4 */
- unsigned short v3_lb_mail_ierd;
- unsigned short v3_mail_wr_stat; /* 0xd8 */
- unsigned short v3_mail_rd_stat;
- unsigned long v3_qba_map; /* 0xdc */
- unsigned long v3_dma_delay:8; /* 0xe0 */
- unsigned long reserved8:24;
- unsigned long reserved9[7]; /* 0xe4 */
-#endif
-#if __BYTE_ORDER == __BIG_ENDIAN
- unsigned short v3_pci_device; /* 0x00 */
- unsigned short v3_pci_vendor;
- unsigned short v3_pci_stat; /* 0x04 */
- unsigned short v3_pci_cmd;
- unsigned long v3_pci_cc_rev; /* 0x08 */
- unsigned long v3_pci_hdr_cfg; /* 0x0c */
- unsigned long v3_pci_io_base; /* 0x10 */
- unsigned long v3_pci_base0; /* 0x14 */
- unsigned long v3_pci_base1; /* 0x18 */
- unsigned long reserved1[4]; /* 0x1c */
- unsigned short v3_pci_sub_id; /* 0x2c */
- unsigned short v3_pci_sub_vendor;
- unsigned long v3_pci_rom; /* 0x30 */
- unsigned long reserved2[2]; /* 0x34 */
- unsigned long v3_pci_bparam; /* 0x3c */
- unsigned long v3_pci_map0; /* 0x40 */
- unsigned long v3_pci_map1; /* 0x44 */
- unsigned long v3_pci_int_stat; /* 0x48 */
- unsigned long v3_pci_int_cfg; /* 0x4c */
- unsigned long reserved3; /* 0x50 */
- unsigned long v3_lb_base0; /* 0x54 */
- unsigned long v3_lb_base1; /* 0x58 */
- unsigned short v3_lb_map0; /* 0x5c */
- unsigned short reserved4;
- unsigned short v3_lb_map1; /* 0x60 */
- unsigned short reserved5;
- unsigned short v3_lb_map2; /* 0x64 */
- unsigned short v3_lb_base2;
- unsigned long v3_lb_size; /* 0x68 */
- unsigned short v3_lb_io_base; /* 0x6c */
- unsigned short reserved6;
- unsigned short v3_fifo_priority; /* 0x70 */
- unsigned short v3_fifo_cfg;
- unsigned char v3_lb_imask; /* 0x74 */
- unsigned char v3_lb_istat;
- unsigned short v3_fifo_stat;
- unsigned short v3_lb_cfg; /* 0x78 */
- unsigned short v3_system;
- unsigned short reserved7; /* 0x7c */
- unsigned short v3_pci_cfg;
- unsigned long v3_dma_pci_addr0; /* 0x80 */
- unsigned long v3_dma_local_addr0; /* 0x84 */
- unsigned long v3_dma_csr0:8; /* 0x88 */
- unsigned long v3_dma_length0:24;
- unsigned long v3_dma_ctlb_adr0; /* 0x8c */
- unsigned long v3_dma_pci_addr1; /* 0x90 */
- unsigned long v3_dma_local_addr1; /* 0x94 */
- unsigned long v3_dma_csr1:8; /* 0x98 */
- unsigned long v3_dma_length1:24;
- unsigned long v3_dma_ctlb_adr1; /* 0x9c */
- unsigned long v3_i20_mups[8]; /* 0xa0 */
- unsigned char v3_mail_data3; /* 0xc0 */
- unsigned char v3_mail_data2;
- unsigned char v3_mail_data1;
- unsigned char v3_mail_data0;
- unsigned char v3_mail_data7; /* 0xc4 */
- unsigned char v3_mail_data6;
- unsigned char v3_mail_data5;
- unsigned char v3_mail_data4;
- unsigned char v3_mail_data11; /* 0xc8 */
- unsigned char v3_mail_data10;
- unsigned char v3_mail_data9;
- unsigned char v3_mail_data8;
- unsigned char v3_mail_data15; /* 0xcc */
- unsigned char v3_mail_data14;
- unsigned char v3_mail_data13;
- unsigned char v3_mail_data12;
- unsigned short v3_pci_mail_ierd; /* 0xd0 */
- unsigned short v3_pci_mail_iewr;
- unsigned short v3_lb_mail_ierd; /* 0xd4 */
- unsigned short v3_lb_mail_iewr;
- unsigned short v3_mail_rd_stat; /* 0xd8 */
- unsigned short v3_mail_wr_stat;
- unsigned long v3_qba_map; /* 0xdc */
- unsigned long reserved8:24; /* 0xe0 */
- unsigned long v3_dma_delay:8;
- unsigned long reserved9[7]; /* 0xe4 */
-#endif
- } /* 0x100 */
-cma_mb_v360epc;
-
-#endif
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* _COGENT_MB_H */
diff --git a/board/cogent/par.c b/board/cogent/par.c
deleted file mode 100644
index a03c0f1..0000000
--- a/board/cogent/par.c
+++ /dev/null
@@ -1,3 +0,0 @@
-/* parallel not implemented yet */
-
-int cma_parallel_not_implemented = 1;
diff --git a/board/cogent/par.h b/board/cogent/par.h
deleted file mode 100644
index 664ae4a..0000000
--- a/board/cogent/par.h
+++ /dev/null
@@ -1,3 +0,0 @@
-/* parallel not implemented yet */
-
-extern int cma_parallel_not_implemented;
diff --git a/board/cogent/pci.c b/board/cogent/pci.c
deleted file mode 100644
index 0a57c0c..0000000
--- a/board/cogent/pci.c
+++ /dev/null
@@ -1,3 +0,0 @@
-/* pci not implemented yet */
-
-int cma_pci_not_implemented = 1;
diff --git a/board/cogent/pci.h b/board/cogent/pci.h
deleted file mode 100644
index 35aa354..0000000
--- a/board/cogent/pci.h
+++ /dev/null
@@ -1,3 +0,0 @@
-/* pci not implemented yet */
-
-extern int cma_pci_not_implemented;
diff --git a/board/cogent/rtc.c b/board/cogent/rtc.c
deleted file mode 100644
index ace9193..0000000
--- a/board/cogent/rtc.c
+++ /dev/null
@@ -1,3 +0,0 @@
-/* rtc not implemented yet */
-
-int cma_rtc_not_implemented = 1;
diff --git a/board/cogent/rtc.h b/board/cogent/rtc.h
deleted file mode 100644
index 4b55bd2..0000000
--- a/board/cogent/rtc.h
+++ /dev/null
@@ -1,3 +0,0 @@
-/* rtc not implemented yet */
-
-extern int cma_rtc_not_implemented;
diff --git a/board/cogent/serial.c b/board/cogent/serial.c
deleted file mode 100644
index 95c8120..0000000
--- a/board/cogent/serial.c
+++ /dev/null
@@ -1,189 +0,0 @@
-/*
- * Simple serial driver for Cogent motherboard serial ports
- * for use during boot
- */
-
-#include <common.h>
-#include "serial.h"
-#include <serial.h>
-#include <linux/compiler.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_SERPAR)
-
-#if (defined(CONFIG_8xx) && defined(CONFIG_8xx_CONS_NONE)) || \
- (defined(CONFIG_MPC8260) && defined(CONFIG_CONS_NONE))
-
-#if CONFIG_CONS_INDEX == 1
-#define CMA_MB_SERIAL_BASE CMA_MB_SERIALA_BASE
-#elif CONFIG_CONS_INDEX == 2
-#define CMA_MB_SERIAL_BASE CMA_MB_SERIALB_BASE
-#elif CONFIG_CONS_INDEX == 3 && (CMA_MB_CAPS & CMA_MB_CAP_SER2)
-#define CMA_MB_SERIAL_BASE CMA_MB_SER2A_BASE
-#elif CONFIG_CONS_INDEX == 4 && (CMA_MB_CAPS & CMA_MB_CAP_SER2)
-#define CMA_MB_SERIAL_BASE CMA_MB_SER2B_BASE
-#else
-#error CONFIG_CONS_INDEX must be configured for Cogent motherboard serial
-#endif
-
-static int cogent_serial_init(void)
-{
- cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE;
-
- cma_mb_reg_write (&mbsp->ser_ier, 0x00); /* turn off interrupts */
- serial_setbrg ();
- cma_mb_reg_write (&mbsp->ser_lcr, 0x03); /* 8 data, 1 stop, no parity */
- cma_mb_reg_write (&mbsp->ser_mcr, 0x03); /* RTS/DTR */
- cma_mb_reg_write (&mbsp->ser_fcr, 0x07); /* Clear & enable FIFOs */
-
- return (0);
-}
-
-static void cogent_serial_setbrg(void)
-{
- cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE;
- unsigned int divisor;
- unsigned char lcr;
-
- if ((divisor = br_to_div (gd->baudrate)) == 0)
- divisor = DEFDIV;
-
- lcr = cma_mb_reg_read (&mbsp->ser_lcr);
- cma_mb_reg_write (&mbsp->ser_lcr, lcr | 0x80); /* Access baud rate(set DLAB) */
- cma_mb_reg_write (&mbsp->ser_brl, divisor & 0xff);
- cma_mb_reg_write (&mbsp->ser_brh, (divisor >> 8) & 0xff);
- cma_mb_reg_write (&mbsp->ser_lcr, lcr); /* unset DLAB */
-}
-
-static void cogent_serial_putc(const char c)
-{
- cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE;
-
- if (c == '\n')
- serial_putc ('\r');
-
- while ((cma_mb_reg_read (&mbsp->ser_lsr) & LSR_THRE) == 0);
-
- cma_mb_reg_write (&mbsp->ser_thr, c);
-}
-
-static int cogent_serial_getc(void)
-{
- cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE;
-
- while ((cma_mb_reg_read (&mbsp->ser_lsr) & LSR_DR) == 0);
-
- return ((int) cma_mb_reg_read (&mbsp->ser_rhr) & 0x7f);
-}
-
-static int cogent_serial_tstc(void)
-{
- cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE;
-
- return ((cma_mb_reg_read (&mbsp->ser_lsr) & LSR_DR) != 0);
-}
-
-static struct serial_device cogent_serial_drv = {
- .name = "cogent_serial",
- .start = cogent_serial_init,
- .stop = NULL,
- .setbrg = cogent_serial_setbrg,
- .putc = cogent_serial_putc,
- .puts = default_serial_puts,
- .getc = cogent_serial_getc,
- .tstc = cogent_serial_tstc,
-};
-
-void cogent_serial_initialize(void)
-{
- serial_register(&cogent_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
- return &cogent_serial_drv;
-}
-#endif /* CONS_NONE */
-
-#if defined(CONFIG_CMD_KGDB) && \
- defined(CONFIG_KGDB_NONE)
-
-#if CONFIG_KGDB_INDEX == CONFIG_CONS_INDEX
-#error Console and kgdb are on the same serial port - this is not supported
-#endif
-
-#if CONFIG_KGDB_INDEX == 1
-#define CMA_MB_KGDB_SER_BASE CMA_MB_SERIALA_BASE
-#elif CONFIG_KGDB_INDEX == 2
-#define CMA_MB_KGDB_SER_BASE CMA_MB_SERIALB_BASE
-#elif CONFIG_KGDB_INDEX == 3 && (CMA_MB_CAPS & CMA_MB_CAP_SER2)
-#define CMA_MB_KGDB_SER_BASE CMA_MB_SER2A_BASE
-#elif CONFIG_KGDB_INDEX == 4 && (CMA_MB_CAPS & CMA_MB_CAP_SER2)
-#define CMA_MB_KGDB_SER_BASE CMA_MB_SER2B_BASE
-#else
-#error CONFIG_KGDB_INDEX must be configured for Cogent motherboard serial
-#endif
-
-void kgdb_serial_init (void)
-{
- cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_KGDB_SER_BASE;
- unsigned int divisor;
-
- if ((divisor = br_to_div (CONFIG_KGDB_BAUDRATE)) == 0)
- divisor = DEFDIV;
-
- cma_mb_reg_write (&mbsp->ser_ier, 0x00); /* turn off interrupts */
- cma_mb_reg_write (&mbsp->ser_lcr, 0x80); /* Access baud rate(set DLAB) */
- cma_mb_reg_write (&mbsp->ser_brl, divisor & 0xff);
- cma_mb_reg_write (&mbsp->ser_brh, (divisor >> 8) & 0xff);
- cma_mb_reg_write (&mbsp->ser_lcr, 0x03); /* 8 data, 1 stop, no parity */
- cma_mb_reg_write (&mbsp->ser_mcr, 0x03); /* RTS/DTR */
- cma_mb_reg_write (&mbsp->ser_fcr, 0x07); /* Clear & enable FIFOs */
-
- printf ("[on cma10x serial port B] ");
-}
-
-void putDebugChar (int c)
-{
- cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_KGDB_SER_BASE;
-
- while ((cma_mb_reg_read (&mbsp->ser_lsr) & LSR_THRE) == 0);
-
- cma_mb_reg_write (&mbsp->ser_thr, c & 0xff);
-}
-
-void putDebugStr (const char *str)
-{
- while (*str != '\0') {
- if (*str == '\n')
- putDebugChar ('\r');
- putDebugChar (*str++);
- }
-}
-
-int getDebugChar (void)
-{
- cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_KGDB_SER_BASE;
-
- while ((cma_mb_reg_read (&mbsp->ser_lsr) & LSR_DR) == 0);
-
- return ((int) cma_mb_reg_read (&mbsp->ser_rhr) & 0x7f);
-}
-
-void kgdb_interruptible (int yes)
-{
- cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_KGDB_SER_BASE;
-
- if (yes == 1) {
- printf ("kgdb: turning serial ints on\n");
- cma_mb_reg_write (&mbsp->ser_ier, 0xf);
- } else {
- printf ("kgdb: turning serial ints off\n");
- cma_mb_reg_write (&mbsp->ser_ier, 0x0);
- }
-}
-
-#endif /* KGDB && KGDB_NONE */
-
-#endif /* CAPS & SERPAR */
diff --git a/board/cogent/serial.h b/board/cogent/serial.h
deleted file mode 100644
index 89962d8..0000000
--- a/board/cogent/serial.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* Line Status Register bits */
-#define LSR_DR 0x01 /* Data ready */
-#define LSR_OE 0x02 /* Overrun */
-#define LSR_PE 0x04 /* Parity error */
-#define LSR_FE 0x08 /* Framing error */
-#define LSR_BI 0x10 /* Break */
-#define LSR_THRE 0x20 /* Xmit holding register empty */
-#define LSR_TEMT 0x40 /* Xmitter empty */
-#define LSR_ERR 0x80 /* Error */
-
-#define CLKRATE 3686400 /* cogent motherboard serial clk = 3.6864MHz */
-#define DEFDIV 1 /* default to 230400 bps */
-
-#define br_to_div(br) (CLKRATE / (16 * (br)))
-#define div_to_br(div) (CLKRATE / (16 * (div)))
diff --git a/board/cogent/u-boot.lds b/board/cogent/u-boot.lds
deleted file mode 100644
index 4c63ff2..0000000
--- a/board/cogent/u-boot.lds
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
-#ifdef CONFIG_MPC8260
- arch/powerpc/cpu/mpc8260/start.o (.text*)
-#else
- arch/powerpc/cpu/mpc8xx/start.o (.text*)
- arch/powerpc/cpu/mpc8xx/traps.o (.text*)
-#endif
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
diff --git a/board/cogent/u-boot.lds.debug b/board/cogent/u-boot.lds.debug
deleted file mode 100644
index b9c84c7..0000000
--- a/board/cogent/u-boot.lds.debug
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
-
- . = env_offset;
- common/env_embedded.o(.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
diff --git a/configs/cogent_mpc8260_defconfig b/configs/cogent_mpc8260_defconfig
deleted file mode 100644
index dc297f1..0000000
--- a/configs/cogent_mpc8260_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_COGENT_MPC8260=y
diff --git a/configs/cogent_mpc8xx_defconfig b/configs/cogent_mpc8xx_defconfig
deleted file mode 100644
index 2fe7a5a..0000000
--- a/configs/cogent_mpc8xx_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_8xx=y
-CONFIG_TARGET_COGENT_MPC8XX=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 9d6a6b6..c9b4b17 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,8 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+cogent_mpc8260 powerpc mpc8260 - - Murray Jensen <Murray.Jensen@csiro.au>
+cogent_8xx powerpc mpc8xx - - Murray Jensen <Murray.Jensen@csiro.au>
ESTEEM192E powerpc mpc8xx - - Conn Clark <clark@esteem.com>
IP860 powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
IVML24 powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
diff --git a/include/configs/cogent_common.h b/include/configs/cogent_common.h
deleted file mode 100644
index 1b5d6a5..0000000
--- a/include/configs/cogent_common.h
+++ /dev/null
@@ -1,192 +0,0 @@
-/*
- * (C) Copyright 2000
- * Murray Jensen, CSIRO-MST
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _CONFIG_COGENT_COMMON_H
-#define _CONFIG_COGENT_COMMON_H
-
-/*
- * Cogent Motherboard Capabilities
- */
-#define CMA_MB_CAP_SERPAR 0x0001 /* has dual serial+parallel (16C552) */
-#define CMA_MB_CAP_LCD 0x0002 /* has LCD display (HD44780) */
-#define CMA_MB_CAP_FLASH 0x0004 /* has flash (E28F800B or AM29F800BB) */
-#define CMA_MB_CAP_RTC 0x0008 /* has RTC+NVRAM (MK48T02) */
-#define CMA_MB_CAP_ETHER 0x0010 /* has Ethernet (MB86964) */
-#define CMA_MB_CAP_SLOT1 0x0020 /* has CMABus slot 1 */
-#define CMA_MB_CAP_SLOT2 0x0040 /* has CMABus slot 2 */
-#define CMA_MB_CAP_SLOT3 0x0080 /* has CMABus slot 3 */
-#define CMA_MB_CAP_KBM 0x0100 /* has PS/2 keyboard+mouse (HT6542B) */
-#define CMA_MB_CAP_SER2 0x0200 /* has 2nd dual serial (16C2552) */
-#define CMA_MB_CAP_PCI 0x0400 /* has pci bridge (V360EPC) */
-#define CMA_MB_CAP_PCI_EXT 0x0800 /* can access extended pci space */
-#define CMA_MB_CAP_PCI_ETHER 0x1000 /* has 10/100 ether on PCI (GD82559) */
-#define CMA_MB_CAP_PCI_VIDEO 0x2000 /* has video int'face on PCI (B69000) */
-#define CMA_MB_CAP_PCI_CARDBUS 0x4000 /* has Cardbus Ctlr on PCI (PD6832) */
-
-/*
- * Cogent option sanity checking
- */
-
-#if defined(CONFIG_MPC821) || defined(CONFIG_MPC823) || \
- defined(CONFIG_MPC850) || defined(CONFIG_MPC860)
-
-/*
- * check a PowerPC 8xx cpu module has been selected
- */
-
-# if defined(CONFIG_CMA286_21)
-
-# define COGENT_CPU_MODULE "CMA286-21"
-
-# elif defined(CONFIG_CMA286_60_OLD)
-
-# define COGENT_CPU_MODULE "CMA286-60 (old)"
-
-# elif defined(CONFIG_CMA286_60)
-
-# define COGENT_CPU_MODULE "CMA286-60"
-
-# elif defined(CONFIG_CMA286_60P)
-
-# define COGENT_CPU_MODULE "CMA286-60P"
-
-# elif defined(CONFIG_CMA287_21)
-
-# define COGENT_CPU_MODULE "CMA287-21"
-
-# elif defined(CONFIG_CMA287_50)
-
-# define COGENT_CPU_MODULE "CMA287-50"
-
-# else
-
-# error Cogent CPU Module must be a PowerPC MPC8xx module
-
-# endif
-
-#elif defined(CONFIG_MPC8260)
-
-/*
- * check a PowerPC 8260 cpu module has been selected
- */
-
-# if defined(CONFIG_CMA282)
-
-# define COGENT_CPU_MODULE "CMA282"
-
-# else
-
-# error Cogent CPU Module must be a PowerPC MPC8260 module
-
-# endif
-
-#else
-
-# error CPU type must be PowerPC 8xx or 8260
-
-#endif
-
-/*
- * check a motherboard has been selected
- * define the motherboard capabilities while we're at it
- */
-
-#if defined(CONFIG_CMA101)
-
-# define COGENT_MOTHERBOARD "CMA101"
-# define CMA_MB_CAPS (CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \
- CMA_MB_CAP_RTC | CMA_MB_CAP_ETHER | \
- CMA_MB_CAP_SLOT1 | CMA_MB_CAP_SLOT2 | \
- CMA_MB_CAP_SLOT3)
-# define CMA_MB_NSLOTS 3
-
-#elif defined(CONFIG_CMA102)
-
-# define COGENT_MOTHERBOARD "CMA102"
-# define CMA_MB_CAPS (CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \
- CMA_MB_CAP_RTC | CMA_MB_CAP_SLOT1 | \
- CMA_MB_CAP_SLOT2 | CMA_MB_CAP_SLOT3)
-# define CMA_MB_NSLOTS 3
-
-#elif defined(CONFIG_CMA110)
-
-# define COGENT_MOTHERBOARD "CMA110"
-# define CMA_MB_CAPS (CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \
- CMA_MB_CAP_FLASH | CMA_MB_CAP_RTC | \
- CMA_MB_CAP_KBM | CMA_MB_CAP_PCI)
-# define CMA_MB_NSLOTS 0
-
-#elif defined(CONFIG_CMA111)
-
-# define COGENT_MOTHERBOARD "CMA111"
-# define CMA_MB_CAPS (CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \
- CMA_MB_CAP_FLASH | CMA_MB_CAP_RTC | \
- CMA_MB_CAP_SLOT1 | CMA_MB_CAP_KBM | \
- CMA_MB_CAP_PCI | CMA_MB_CAP_PCI_EXT | \
- CMA_MB_CAP_PCI_ETHER)
-# define CMA_MB_NSLOTS 1
-
-#elif defined(CONFIG_CMA120)
-
-# define COGENT_MOTHERBOARD "CMA120"
-# define CMA_MB_CAPS (CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \
- CMA_MB_CAP_FLASH | CMA_MB_CAP_RTC | \
- CMA_MB_CAP_SLOT1 | CMA_MB_CAP_KBM | \
- CMA_MB_CAP_SER2 | CMA_MB_CAP_PCI | \
- CMA_MB_CAP_PCI_EXT | CMA_MB_CAP_PCI_ETHER | \
- CMA_MB_CAP_PCI_VIDEO | CMA_MB_CAP_PCI_CARDBUS)
-# define CMA_MB_NSLOTS 1
-
-#elif defined(CONFIG_CMA150)
-
-# define COGENT_MOTHERBOARD "CMA150"
-# define CMA_MB_CAPS (CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \
- CMA_MB_CAP_FLASH | CMA_MB_CAP_RTC | \
- CMA_MB_CAP_KBM)
-# define CMA_MB_NSLOTS 0
-
-#else
-
-# error Cogent Motherboard either unsupported or undefined
-
-#endif
-
-/*
- * check a flash i/o module has been selected if no flash on m/b
- */
-
-#if defined(CONFIG_CMA302)
-
-# define COGENT_FLASH_MODULE "CMA302"
-
-#elif (CMA_MB_CAPS & CMA_MB_CAP_FLASH) == 0
-
-# error Cogent Flash I/O module (e.g. CMA302) is required with this Motherboard
-
-#endif
-
-/*
- * some further sanity checks
- */
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_PCI) && (CMA_MB_CAPS & CMA_MB_CAP_SLOT2)
-#error Cogent Sanity Check: Both Slot2 and PCI are defined
-#endif
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_PCI_EXT) && !(CMA_MB_CAPS & CMA_MB_CAP_PCI)
-#error Extended PCI capability defined without PCI capability
-#endif
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_PCI_ETHER) && !(CMA_MB_CAPS & CMA_MB_CAP_PCI)
-#error Motherboard ethernet capability defined without PCI capability
-#endif
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_SER2) && !(CMA_MB_CAPS & CMA_MB_CAP_SERPAR)
-#error 2nd dual serial capability defined without serial/parallel capability
-#endif
-#include "../board/cogent/mb.h"
-#endif /* _CONFIG_COGENT_COMMON_H */
diff --git a/include/configs/cogent_mpc8260.h b/include/configs/cogent_mpc8260.h
deleted file mode 100644
index 02b25c6..0000000
--- a/include/configs/cogent_mpc8260.h
+++ /dev/null
@@ -1,392 +0,0 @@
-/*
- * (C) Copyright 2000
- * Murray Jensen <Murray.Jensen@cmst.csiro.au>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Config header file for Cogent platform using an MPC8xx CPU module
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
-#define CONFIG_COGENT 1 /* using Cogent Modular Architecture */
-#define CONFIG_CPM2 1 /* Has a CPM2 */
-
-#define CONFIG_SYS_TEXT_BASE 0xfff00000
-
-#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
-#define CONFIG_MISC_INIT_R /* Use misc_init_r() */
-
-/* Cogent Modular Architecture options */
-#define CONFIG_CMA282 1 /* ...on a CMA282 CPU module */
-#define CONFIG_CMA111 1 /* ...on a CMA111 motherboard */
-
-/*
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * if CONFIG_CONS_NONE is defined, then the serial console routines must
- * defined elsewhere (for example, on the cogent platform, there are serial
- * ports on the motherboard which are used for the serial console - see
- * cogent/cma101/serial.[ch]).
- */
-#define CONFIG_CONS_ON_SMC /* define if console on SMC */
-#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
-#undef CONFIG_CONS_NONE /* define if console on something else*/
-#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
-#undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
-#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */
-#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
-
-/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
- */
-#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
-#undef CONFIG_ETHER_ON_FCC /* define if ether on FCC */
-#define CONFIG_ETHER_NONE /* define if ether on something else */
-#define CONFIG_ETHER_INDEX 1 /* which channel for ether */
-
-/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
-#define CONFIG_8260_CLKIN 66666666 /* in Hz */
-
-#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
-#define CONFIG_BAUDRATE 230400
-#else
-#define CONFIG_BAUDRATE 9600
-#endif
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_KGDB
-
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
-
-#ifdef DEBUG
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-#define CONFIG_BOOTCOMMAND "bootm 04080000 04200000" /* autoboot command*/
-
-#define CONFIG_BOOTARGS "root=/dev/ram rw"
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
-#undef CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
-#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
-#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
-#define CONFIG_KGDB_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
-#define CONFIG_KGDB_EXTC_RATE 3686400 /* serial ext clk rate in Hz */
-#define CONFIG_KGDB_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
-# if defined(CONFIG_KGDB_NONE) || defined(CONFIG_KGDB_USE_EXTC)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port at */
-# else
-#define CONFIG_KGDB_BAUDRATE 9600 /* speed to run kgdb serial port at */
-# endif
-#endif
-
-#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x01c00000 /* 4 ... 28 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*-----------------------------------------------------------------------
- * Low Level Cogent settings
- * if CONFIG_SYS_CMA_CONS_SERIAL is defined, make sure the 8260 CPM serial is not.
- * also, make sure CONFIG_CONS_INDEX is still defined - the index will be
- * 1 for serialA, 2 for serialB, 3 for ser2A, 4 for ser2B
- * (second 2 for CMA120 only)
- */
-#define CONFIG_SYS_CMA_MB_BASE 0x00000000 /* base of m/b address space */
-
-#include <configs/cogent_common.h>
-
-#ifdef CONFIG_CONS_NONE
-#define CONFIG_SYS_CMA_CONS_SERIAL /* use Cogent motherboard serial for console */
-#endif
-#define CONFIG_SYS_CMA_LCD_HEARTBEAT /* define for sec rotator in lcd corner */
-#define CONFIG_SHOW_ACTIVITY
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
-/*
- * flash exists on the motherboard
- * set these four according to TOP dipsw:
- * TOP on => ..._FLLOW_... (boot EPROM space is high so FLASH is low )
- * TOP off => ..._FLHIGH_... (boot EPROM space is low so FLASH is high)
- */
-#define CMA_MB_FLASH_EXEC_BASE CMA_MB_FLLOW_EXEC_BASE
-#define CMA_MB_FLASH_EXEC_SIZE CMA_MB_FLLOW_EXEC_SIZE
-#define CMA_MB_FLASH_RDWR_BASE CMA_MB_FLLOW_RDWR_BASE
-#define CMA_MB_FLASH_RDWR_SIZE CMA_MB_FLLOW_RDWR_SIZE
-#endif
-#define CMA_MB_FLASH_BASE CMA_MB_FLASH_EXEC_BASE
-#define CMA_MB_FLASH_SIZE CMA_MB_FLASH_EXEC_SIZE
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
- *
- * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
- * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
- */
-#define CONFIG_SYS_HRCW_MASTER (HRCW_EBM|HRCW_BPS10|HRCW_L2CPC10|HRCW_DPPC11|\
- HRCW_ISB100|HRCW_MMR11|HRCW_MODCK_H0101)
-/* no slaves so just duplicate the master hrcw */
-#define CONFIG_SYS_HRCW_SLAVE1 CONFIG_SYS_HRCW_MASTER
-#define CONFIG_SYS_HRCW_SLAVE2 CONFIG_SYS_HRCW_MASTER
-#define CONFIG_SYS_HRCW_SLAVE3 CONFIG_SYS_HRCW_MASTER
-#define CONFIG_SYS_HRCW_SLAVE4 CONFIG_SYS_HRCW_MASTER
-#define CONFIG_SYS_HRCW_SLAVE5 CONFIG_SYS_HRCW_MASTER
-#define CONFIG_SYS_HRCW_SLAVE6 CONFIG_SYS_HRCW_MASTER
-#define CONFIG_SYS_HRCW_SLAVE7 CONFIG_SYS_HRCW_MASTER
-
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xF0000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE CMA_MB_RAM_BASE
-#ifdef CONFIG_CMA302
-#define CONFIG_SYS_FLASH_BASE CMA_MB_SLOT2_BASE /* cma302 in slot 2 */
-#else
-#define CONFIG_SYS_FLASH_BASE CMA_MB_FLASH_BASE /* flash on m/b */
-#endif
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max num of sects on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE /* Addr of Environment Sector */
-#ifdef CONFIG_CMA302
-#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
-#define CONFIG_ENV_SECT_SIZE (512*1024) /* see README - env sect real size */
-#else
-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
-#endif
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value*/
-#endif
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers 2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
- HID0_IFEM|HID0_ABE)
-#define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE)
-#define CONFIG_SYS_HID2 0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register 5-5
- *-----------------------------------------------------------------------
- * turn on Checkstop Reset Enable
- */
-#define CONFIG_SYS_RMR RMR_CSRE
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration 4-25
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_BCR BCR_EBM
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 4-31
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC11|SIUMCR_L2CPC10|SIUMCR_MMR11)
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 4-35
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
- SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
- SYPCR_SWRI|SYPCR_SWP)
-#endif /* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control 4-40
- *-----------------------------------------------------------------------
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- */
-#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control 9-8
- *-----------------------------------------------------------------------
- * Ensure DFBRG is Divide by 16
- */
-#define CONFIG_SYS_SCCR (SCCR_DFBRG01)
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration 13-7
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RCCR 0
-
-#if defined(CONFIG_CMA282)
-
-/*
- * Init Memory Controller:
- *
- * According to the Cogent manual, only CS0 and CS2 are used - CS0 for EPROM
- * and CS2 for (optional) local bus RAM on the CPU module.
- *
- * Note the motherboard address space (256 Mbyte in size) is connected
- * to the 60x Bus and is located starting at address 0. The Hard Reset
- * Configuration Word should put the 60x Bus into External Bus Mode, since
- * we dont set up any memory controller maps for it (see BCR[EBM], 4-26).
- *
- * (the *_SIZE vars must be a power of 2)
- */
-
-#define CONFIG_SYS_CMA_CS0_BASE CONFIG_SYS_TEXT_BASE /* EPROM */
-#define CONFIG_SYS_CMA_CS0_SIZE (1 << 20)
-#if 0
-#define CONFIG_SYS_CMA_CS2_BASE 0x10000000 /* Local Bus SDRAM */
-#define CONFIG_SYS_CMA_CS2_SIZE (16 << 20)
-#endif
-
-/*
- * CS0 maps the EPROM on the cpu module
- * Set it for 10 wait states, address CONFIG_SYS_MONITOR_BASE and size 1M
- *
- * Note: We must have already transferred control to the final location
- * of the EPROM before these are used, because when BR0/OR0 are set, the
- * mirror of the eprom at any other addresses will disappear.
- */
-
-/* base address = CONFIG_SYS_CMA_CS0_BASE, 16-bit, no parity, r/o, gpcm (60x bus) */
-#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_CMA_CS0_BASE&BRx_BA_MSK)|BRx_PS_16|BRx_WP|BRx_V)
-/* mask size CONFIG_SYS_CMA_CS0_SIZE, csneg 1/4 early, adr-to-cs 1/2, 10-wait states */
-#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_CMA_CS0_SIZE)|\
- ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK)
-
-/*
- * CS2 enables the Local Bus SDRAM on the CPU Module
- *
- * Will leave this unset for the moment, because a) my CPU module has no
- * SDRAM installed (it is optional); and b) it will require programming
- * one of the UPMs in SDRAM mode - not a trivial job, and hard to get right
- * if you can't test it.
- */
-
-#if 0
-/* base address = CONFIG_SYS_CMA_CS2_BASE, 32-bit, no parity, ??? */
-#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_CMA_CS2_BASE&BRx_BA_MSK)|BRx_PS_32|/*???*/|BRx_V)
-/* mask size CONFIG_SYS_CMA_CS2_SIZE, CS time normal, ??? */
-#define CONFIG_SYS_OR2_PRELIM ((~(CONFIG_SYS_CMA_CS2_SIZE-1)&ORx_AM_MSK)|/*???*/)
-#endif
-
-#endif
-#endif /* __CONFIG_H */
diff --git a/include/configs/cogent_mpc8xx.h b/include/configs/cogent_mpc8xx.h
deleted file mode 100644
index c98b687..0000000
--- a/include/configs/cogent_mpc8xx.h
+++ /dev/null
@@ -1,349 +0,0 @@
-/*
- * (C) Copyright 2000-2010
- * Murray Jensen <Murray.Jensen@cmst.csiro.au>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Config header file for Cogent platform using an MPC8xx CPU module
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC860 1 /* This is an MPC860 CPU */
-#define CONFIG_COGENT 1 /* using Cogent Modular Architecture */
-
-#define CONFIG_SYS_TEXT_BASE 0xfff00000
-
-#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
-#define CONFIG_MISC_INIT_R /* Use misc_init_r() */
-
-/* Cogent Modular Architecture options */
-#define CONFIG_CMA286_60_OLD 1 /* ...on an old CMA286-60 CPU module */
-#define CONFIG_CMA102 1 /* ...on a CMA102 motherboard */
-#define CONFIG_CMA302 1 /* ...with a CMA302 flash I/O module */
-
-/* serial console configuration */
-#undef CONFIG_8xx_CONS_SMC1
-#undef CONFIG_8xx_CONS_SMC2
-#define CONFIG_8xx_CONS_NONE /* not on 8xx serial ports (eg on cogent m/b) */
-
-#if defined(CONFIG_CMA286_60_OLD)
-#define CONFIG_8xx_GCLK_FREQ 33333000 /* define if cant use get_gclk_freq */
-#endif
-
-#define CONFIG_BAUDRATE 230400
-
-#define CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_KGDB
-#define CONFIG_CMD_I2C
-
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
-
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-#define CONFIG_BOOTCOMMAND "bootm 04080000 04200000" /* autoboot command*/
-
-#define CONFIG_BOOTARGS "root=/dev/ram rw"
-
-#if defined(CONFIG_CMD_KGDB)
-#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
-#undef CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
-#define CONFIG_KGDB_NONE /* define if kgdb on something else */
-#define CONFIG_KGDB_INDEX 2 /* which SMC/SCC channel for kgdb */
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-#define CONFIG_WATCHDOG /* turn on platform specific watchdog */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x01c00000 /* 4 ... 28 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#define CONFIG_SYS_ALLOC_DPRAM
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*-----------------------------------------------------------------------
- * Low Level Cogent settings
- * if CONFIG_SYS_CMA_CONS_SERIAL is defined, make sure the 8xx CPM serial is not.
- * also, make sure CONFIG_CONS_INDEX is still defined - the index will be
- * 1 for serialA, 2 for serialB, 3 for ser2A, 4 for ser2B
- * (second 2 for CMA120 only)
- */
-#define CONFIG_SYS_CMA_MB_BASE 0x00000000 /* base of m/b address space */
-
-#include <configs/cogent_common.h>
-
-#define CONFIG_SYS_CMA_CONS_SERIAL /* use Cogent motherboard serial for console */
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_CMA_LCD_HEARTBEAT /* define for sec rotator in lcd corner */
-#define CONFIG_SHOW_ACTIVITY
-#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
-/*
- * flash exists on the motherboard
- * set these four according to TOP dipsw:
- * TOP on => ..._FLLOW_... (boot EPROM space is high so FLASH is low )
- * TOP off => ..._FLHIGH_... (boot EPROM space is low so FLASH is high)
- */
-#define CMA_MB_FLASH_EXEC_BASE CMA_MB_FLLOW_EXEC_BASE
-#define CMA_MB_FLASH_EXEC_SIZE CMA_MB_FLLOW_EXEC_SIZE
-#define CMA_MB_FLASH_RDWR_BASE CMA_MB_FLLOW_RDWR_BASE
-#define CMA_MB_FLASH_RDWR_SIZE CMA_MB_FLLOW_RDWR_SIZE
-#endif
-#define CMA_MB_FLASH_BASE CMA_MB_FLASH_EXEC_BASE
-#define CMA_MB_FLASH_SIZE CMA_MB_FLASH_EXEC_SIZE
-
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xFF000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE CMA_MB_RAM_BASE
-#ifdef CONFIG_CMA302
-#define CONFIG_SYS_FLASH_BASE CMA_MB_SLOT2_BASE /* cma302 in slot 2 */
-#else
-#define CONFIG_SYS_FLASH_BASE CMA_MB_FLASH_BASE /* flash on m/b */
-#endif
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE /* Addr of Environment Sector */
-#ifdef CONFIG_CMA302
-#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
-#define CONFIG_ENV_SECT_SIZE (512*1024) /* see README - env sect real size */
-#else
-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
-#endif
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif /* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit - leave PLL multiplication factor unchanged !
- */
-#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK SCCR_EBDF11
-#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_RTDIV | SCCR_RTSEL | \
- SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
- SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
- SCCR_DFALCD00)
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-/*#define CONFIG_SYS_DER 0x2002000F*/
-#define CONFIG_SYS_DER 0
-
-#if defined(CONFIG_CMA286_60_OLD)
-
-/*
- * Init Memory Controller:
- *
- * NOTE: although the names (CONFIG_SYS_xRn_PRELIM) suggest preliminary settings,
- * they are actually the final settings for this cpu/board, because the
- * flash and RAM are on the motherboard, accessed via the CMAbus, and the
- * mappings are pretty much fixed.
- *
- * (the *_SIZE vars must be a power of 2)
- */
-
-#define CONFIG_SYS_CMA_CS0_BASE CONFIG_SYS_TEXT_BASE /* EPROM */
-#define CONFIG_SYS_CMA_CS0_SIZE (1 << 20)
-#define CONFIG_SYS_CMA_CS1_BASE CMA_MB_RAM_BASE /* RAM + I/O SLOT 1 */
-#define CONFIG_SYS_CMA_CS1_SIZE (64 << 20)
-#define CONFIG_SYS_CMA_CS2_BASE CMA_MB_SLOT2_BASE /* I/O SLOTS 2 + 3 */
-#define CONFIG_SYS_CMA_CS2_SIZE (64 << 20)
-#define CONFIG_SYS_CMA_CS3_BASE CMA_MB_ROMLOW_BASE /* M/B I/O */
-#define CONFIG_SYS_CMA_CS3_SIZE (32 << 20)
-
-/*
- * CS0 maps the EPROM on the cpu module
- * Set it for 4 wait states, address CONFIG_SYS_MONITOR_BASE and size 1M
- *
- * Note: We must have already transferred control to the final location
- * of the EPROM before these are used, because when BR0/OR0 are set, the
- * mirror of the eprom@any other addresses will disappear.
- */
-
-/* base address = CONFIG_SYS_CMA_CS0_BASE, 16-bit, no parity, r/o, gpcm */
-#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_CMA_CS0_BASE&BR_BA_MSK)|BR_PS_16|BR_WP|BR_V)
-/* mask size CONFIG_SYS_CMA_CS0_SIZE, CS time normal, burst inhibit, 4-wait states */
-#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_CMA_CS0_SIZE-1)&OR_AM_MSK)|OR_BI|OR_SCY_4_CLK)
-
-/*
- * CS1 maps motherboard DRAM and motherboard I/O slot 1
- * (each 32Mbyte in size)
- */
-
-/* base address = CONFIG_SYS_CMA_CS1_BASE, 32-bit, no parity, r/w, gpcm */
-#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_CMA_CS1_BASE&BR_BA_MSK)|BR_V)
-/* mask size CONFIG_SYS_CMA_CS1_SIZE, CS time normal, burst ok, ext xfer ack */
-#define CONFIG_SYS_OR1_PRELIM ((~(CONFIG_SYS_CMA_CS1_SIZE-1)&OR_AM_MSK)|OR_SETA)
-
-/*
- * CS2 maps motherboard I/O slots 2 and 3
- * (each 32Mbyte in size)
- */
-
-/* base address = CONFIG_SYS_CMA_CS2_BASE, 32-bit, no parity, r/w, gpcm */
-#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_CMA_CS2_BASE&BR_BA_MSK)|BR_V)
-/* mask size CONFIG_SYS_CMA_CS2_SIZE, CS time normal, burst ok, ext xfer ack */
-#define CONFIG_SYS_OR2_PRELIM ((~(CONFIG_SYS_CMA_CS2_SIZE-1)&OR_AM_MSK)|OR_SETA)
-
-/*
- * CS3 maps motherboard I/O
- * (32Mbyte in size)
- */
-
-/* base address = CONFIG_SYS_CMA_CS3_BASE, 32-bit, no parity, r/w, gpcm */
-#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_CMA_CS3_BASE&BR_BA_MSK)|BR_V)
-/* mask size CONFIG_SYS_CMA_CS3_SIZE, CS time normal, burst inhibit, ext xfer ack */
-#define CONFIG_SYS_OR3_PRELIM ((~(CONFIG_SYS_CMA_CS3_SIZE-1)&OR_AM_MSK)|OR_BI|OR_SETA)
-
-#endif
-#endif /* __CONFIG_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [U-Boot] [PATCH 14/26] mpc8260: remove sacsng board support
2014-12-15 14:26 [U-Boot] [PATCH 0/26] Start removing non-generic boards Masahiro Yamada
` (12 preceding siblings ...)
2014-12-15 14:26 ` [U-Boot] [PATCH 13/26] powerpc: remove cogent_8xx, cogent_mpc8260 " Masahiro Yamada
@ 2014-12-15 14:26 ` Masahiro Yamada
2015-01-05 18:21 ` Tom Rini
2014-12-15 14:26 ` [U-Boot] [PATCH 15/26] mpc8260: remove ppmc8260 " Masahiro Yamada
` (13 subsequent siblings)
27 siblings, 1 reply; 55+ messages in thread
From: Masahiro Yamada @ 2014-12-15 14:26 UTC (permalink / raw)
To: u-boot
This board is still a non-generic board.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
---
arch/powerpc/cpu/mpc8260/Kconfig | 4 -
board/sacsng/Kconfig | 9 -
board/sacsng/MAINTAINERS | 6 -
board/sacsng/Makefile | 8 -
board/sacsng/clkinit.c | 1009 ------------------------------------
board/sacsng/clkinit.h | 103 ----
board/sacsng/flash.c | 507 -------------------
board/sacsng/ioconfig.h | 217 --------
board/sacsng/sacsng.c | 848 -------------------------------
configs/sacsng_defconfig | 3 -
doc/README.scrapyard | 1 +
include/configs/sacsng.h | 1038 --------------------------------------
12 files changed, 1 insertion(+), 3752 deletions(-)
delete mode 100644 board/sacsng/Kconfig
delete mode 100644 board/sacsng/MAINTAINERS
delete mode 100644 board/sacsng/Makefile
delete mode 100644 board/sacsng/clkinit.c
delete mode 100644 board/sacsng/clkinit.h
delete mode 100644 board/sacsng/flash.c
delete mode 100644 board/sacsng/ioconfig.h
delete mode 100644 board/sacsng/sacsng.c
delete mode 100644 configs/sacsng_defconfig
delete mode 100644 include/configs/sacsng.h
diff --git a/arch/powerpc/cpu/mpc8260/Kconfig b/arch/powerpc/cpu/mpc8260/Kconfig
index 17e303d..bdaf126 100644
--- a/arch/powerpc/cpu/mpc8260/Kconfig
+++ b/arch/powerpc/cpu/mpc8260/Kconfig
@@ -40,9 +40,6 @@ config TARGET_PM828
config TARGET_PPMC8260
bool "Support ppmc8260"
-config TARGET_SACSNG
- bool "Support sacsng"
-
config TARGET_MPC8266ADS
bool "Support MPC8266ADS"
@@ -68,6 +65,5 @@ source "board/muas3001/Kconfig"
source "board/pm826/Kconfig"
source "board/pm828/Kconfig"
source "board/ppmc8260/Kconfig"
-source "board/sacsng/Kconfig"
endmenu
diff --git a/board/sacsng/Kconfig b/board/sacsng/Kconfig
deleted file mode 100644
index 1646425..0000000
--- a/board/sacsng/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_SACSNG
-
-config SYS_BOARD
- default "sacsng"
-
-config SYS_CONFIG_NAME
- default "sacsng"
-
-endif
diff --git a/board/sacsng/MAINTAINERS b/board/sacsng/MAINTAINERS
deleted file mode 100644
index b76e462..0000000
--- a/board/sacsng/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-SACSNG BOARD
-#M: Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
-S: Orphan (since 2014-06)
-F: board/sacsng/
-F: include/configs/sacsng.h
-F: configs/sacsng_defconfig
diff --git a/board/sacsng/Makefile b/board/sacsng/Makefile
deleted file mode 100644
index 95e6b8d..0000000
--- a/board/sacsng/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := sacsng.o flash.o clkinit.o
diff --git a/board/sacsng/clkinit.c b/board/sacsng/clkinit.c
deleted file mode 100644
index 2a28037..0000000
--- a/board/sacsng/clkinit.c
+++ /dev/null
@@ -1,1009 +0,0 @@
-/*
- * (C) Copyright 2002
- * Custom IDEAS, Inc. <www.cideas.com>
- * Jon Diekema <diekema@cideas.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc8260.h>
-#include <asm/cpm_8260.h>
-#include <configs/sacsng.h>
-
-#include "clkinit.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int Daq64xSampling = 0;
-
-
-void Daq_BRG_Reset(uint brg)
-{
- volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
- volatile uint *brg_ptr;
-
- brg_ptr = (uint *)&immr->im_brgc1;
-
- if (brg >= 5) {
- brg_ptr = (uint *)&immr->im_brgc5;
- brg -= 4;
- }
- brg_ptr += brg;
- *brg_ptr |= CPM_BRG_RST;
- *brg_ptr &= ~CPM_BRG_RST;
-}
-
-void Daq_BRG_Disable(uint brg)
-{
- volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
- volatile uint *brg_ptr;
-
- brg_ptr = (uint *)&immr->im_brgc1;
-
- if (brg >= 5) {
- brg_ptr = (uint *)&immr->im_brgc5;
- brg -= 4;
- }
- brg_ptr += brg;
- *brg_ptr &= ~CPM_BRG_EN;
-}
-
-void Daq_BRG_Enable(uint brg)
-{
- volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
- volatile uint *brg_ptr;
-
- brg_ptr = (uint *)&immr->im_brgc1;
- if (brg >= 5) {
- brg_ptr = (uint *)&immr->im_brgc5;
- brg -= 4;
- }
- brg_ptr += brg;
- *brg_ptr |= CPM_BRG_EN;
-}
-
-uint Daq_BRG_Get_Div16(uint brg)
-{
- volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
- uint *brg_ptr;
-
- brg_ptr = (uint *)&immr->im_brgc1;
- if (brg >= 5) {
- brg_ptr = (uint *)&immr->im_brgc5;
- brg -= 4;
- }
- brg_ptr += brg;
-
- if (*brg_ptr & CPM_BRG_DIV16) {
- /* DIV16 active */
- return true;
- }
- else {
- /* DIV16 inactive */
- return false;
- }
-}
-
-void Daq_BRG_Set_Div16(uint brg, uint div16)
-{
- volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
- uint *brg_ptr;
-
- brg_ptr = (uint *)&immr->im_brgc1;
- if (brg >= 5) {
- brg_ptr = (uint *)&immr->im_brgc5;
- brg -= 4;
- }
- brg_ptr += brg;
-
- if (div16) {
- /* DIV16 active */
- *brg_ptr |= CPM_BRG_DIV16;
- }
- else {
- /* DIV16 inactive */
- *brg_ptr &= ~CPM_BRG_DIV16;
- }
-}
-
-uint Daq_BRG_Get_Count(uint brg)
-{
- volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
- uint *brg_ptr;
- uint brg_cnt;
-
- brg_ptr = (uint *)&immr->im_brgc1;
- if (brg >= 5) {
- brg_ptr = (uint *)&immr->im_brgc5;
- brg -= 4;
- }
- brg_ptr += brg;
-
- /* Get the clock divider
- *
- * Note: A clock divider of 0 means divide by 1,
- * therefore we need to add 1 to the count.
- */
- brg_cnt = (*brg_ptr & CPM_BRG_CD_MASK) >> CPM_BRG_DIV16_SHIFT;
- brg_cnt++;
- if (*brg_ptr & CPM_BRG_DIV16) {
- brg_cnt *= 16;
- }
-
- return (brg_cnt);
-}
-
-void Daq_BRG_Set_Count(uint brg, uint brg_cnt)
-{
- volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
- uint *brg_ptr;
-
- brg_ptr = (uint *)&immr->im_brgc1;
- if (brg >= 5) {
- brg_ptr = (uint *)&immr->im_brgc5;
- brg -= 4;
- }
- brg_ptr += brg;
-
- /*
- * Note: A clock divider of 0 means divide by 1,
- * therefore we need to subtract 1 from the count.
- */
- if (brg_cnt > 4096) {
- /* Prescale = Divide by 16 */
- *brg_ptr = (*brg_ptr & ~CPM_BRG_CD_MASK) |
- (((brg_cnt / 16) - 1) << CPM_BRG_DIV16_SHIFT);
- *brg_ptr |= CPM_BRG_DIV16;
- }
- else {
- /* Prescale = Divide by 1 */
- *brg_ptr = (*brg_ptr & ~CPM_BRG_CD_MASK) |
- ((brg_cnt - 1) << CPM_BRG_DIV16_SHIFT);
- *brg_ptr &= ~CPM_BRG_DIV16;
- }
-}
-
-uint Daq_BRG_Get_ExtClk(uint brg)
-{
- volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
- uint *brg_ptr;
-
- brg_ptr = (uint *)&immr->im_brgc1;
- if (brg >= 5) {
- brg_ptr = (uint *)&immr->im_brgc5;
- brg -= 4;
- }
- brg_ptr += brg;
-
- return ((*brg_ptr & CPM_BRG_EXTC_MASK) >> CPM_BRG_EXTC_SHIFT);
-}
-
-char* Daq_BRG_Get_ExtClk_Description(uint brg)
-{
- uint extc;
-
- extc = Daq_BRG_Get_ExtClk(brg);
-
- switch (brg + 1) {
- case 1:
- case 2:
- case 5:
- case 6: {
- switch (extc) {
- case 0: {
- return ("BRG_INT");
- }
- case 1: {
- return ("CLK3");
- }
- case 2: {
- return ("CLK5");
- }
- }
- return ("??1245??");
- }
- case 3:
- case 4:
- case 7:
- case 8: {
- switch (extc) {
- case 0: {
- return ("BRG_INT");
- }
- case 1: {
- return ("CLK9");
- }
- case 2: {
- return ("CLK15");
- }
- }
- return ("??3478??");
- }
- }
- return ("??9876??");
-}
-
-void Daq_BRG_Set_ExtClk(uint brg, uint extc)
-{
- volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
- uint *brg_ptr;
-
- brg_ptr = (uint *)&immr->im_brgc1;
- if (brg >= 5) {
- brg_ptr = (uint *)&immr->im_brgc5;
- brg -= 4;
- }
- brg_ptr += brg;
-
- *brg_ptr = (*brg_ptr & ~CPM_BRG_EXTC_MASK) |
- ((extc << CPM_BRG_EXTC_SHIFT) & CPM_BRG_EXTC_MASK);
-}
-
-uint Daq_BRG_Rate(uint brg)
-{
- volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
- uint *brg_ptr;
- uint brg_cnt;
- uint brg_freq = 0;
-
- brg_ptr = (uint *)&immr->im_brgc1;
- brg_ptr += brg;
- if (brg >= 5) {
- brg_ptr = (uint *)&immr->im_brgc5;
- brg_ptr += (brg - 4);
- }
-
- brg_cnt = Daq_BRG_Get_Count(brg);
-
- switch (Daq_BRG_Get_ExtClk(brg)) {
- case CPM_BRG_EXTC_CLK3:
- case CPM_BRG_EXTC_CLK5: {
- brg_freq = brg_cnt;
- break;
- }
- default: {
- brg_freq = (uint)BRG_INT_CLK / brg_cnt;
- }
- }
- return (brg_freq);
-}
-
-uint Daq_Get_SampleRate(void)
-{
- /*
- * Read the BRG's to return the actual sample rate.
- */
- return (Daq_BRG_Rate(MCLK_BRG) / (MCLK_DIVISOR * SCLK_DIVISOR));
-}
-
-void Daq_Init_Clocks(int sample_rate, int sample_64x)
-{
- volatile ioport_t *iopa = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0 /* port A */);
- uint mclk_divisor; /* MCLK divisor */
- int flag; /* Interrupt state */
-
- /* Save off the clocking data */
- Daq64xSampling = sample_64x;
-
- /*
- * Limit the sample rate to some sensible values.
- */
- if (sample_rate > MAX_64x_SAMPLE_RATE) {
- sample_rate = MAX_64x_SAMPLE_RATE;
- }
- if (sample_rate < MIN_SAMPLE_RATE) {
- sample_rate = MIN_SAMPLE_RATE;
- }
-
- /*
- * Initialize the MCLK/SCLK/LRCLK baud rate generators.
- */
-
- /* Setup MCLK */
- Daq_BRG_Set_ExtClk(MCLK_BRG, CPM_BRG_EXTC_BRGCLK);
-
- /* Setup SCLK */
-# ifdef RUN_SCLK_ON_BRG_INT
- Daq_BRG_Set_ExtClk(SCLK_BRG, CPM_BRG_EXTC_BRGCLK);
-# else
- Daq_BRG_Set_ExtClk(SCLK_BRG, CPM_BRG_EXTC_CLK9);
-# endif
-
- /* Setup LRCLK */
-# ifdef RUN_LRCLK_ON_BRG_INT
- Daq_BRG_Set_ExtClk(LRCLK_BRG, CPM_BRG_EXTC_BRGCLK);
-# else
- Daq_BRG_Set_ExtClk(LRCLK_BRG, CPM_BRG_EXTC_CLK5);
-# endif
-
- /*
- * Dynamically adjust MCLK based on the new sample rate.
- */
-
- /* Compute the divisors */
- mclk_divisor = BRG_INT_CLK / (sample_rate * MCLK_DIVISOR * SCLK_DIVISOR);
-
- /*
- * Disable interrupt and save the current state
- */
- flag = disable_interrupts();
-
- /* Setup MCLK */
- Daq_BRG_Set_Count(MCLK_BRG, mclk_divisor);
-
- /* Setup SCLK */
-# ifdef RUN_SCLK_ON_BRG_INT
- Daq_BRG_Set_Count(SCLK_BRG, mclk_divisor * MCLK_DIVISOR);
-# else
- Daq_BRG_Set_Count(SCLK_BRG, MCLK_DIVISOR);
-# endif
-
-# ifdef RUN_LRCLK_ON_BRG_INT
- Daq_BRG_Set_Count(LRCLK_BRG,
- mclk_divisor * MCLK_DIVISOR * SCLK_DIVISOR);
-# else
- Daq_BRG_Set_Count(LRCLK_BRG, SCLK_DIVISOR);
-# endif
-
- /*
- * Restore the Interrupt state
- */
- if (flag) {
- enable_interrupts();
- }
-
- /* Enable the clock drivers */
- iopa->pdat &= ~SLRCLK_EN_MASK;
-}
-
-void Daq_Stop_Clocks(void)
-
-{
-#ifdef TIGHTEN_UP_BRG_TIMING
- volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
- register uint mclk_brg; /* MCLK BRG value */
- register uint sclk_brg; /* SCLK BRG value */
- register uint lrclk_brg; /* LRCLK BRG value */
- unsigned long flag; /* Interrupt flags */
-#endif
-
-# ifdef TIGHTEN_UP_BRG_TIMING
- /*
- * Obtain MCLK BRG reset/disabled value
- */
-# if (MCLK_BRG == 0)
- mclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN;
-# endif
-# if (MCLK_BRG == 1)
- mclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN;
-# endif
-# if (MCLK_BRG == 2)
- mclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN;
-# endif
-# if (MCLK_BRG == 3)
- mclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN;
-# endif
-# if (MCLK_BRG == 4)
- mclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN;
-# endif
-# if (MCLK_BRG == 5)
- mclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN;
-# endif
-# if (MCLK_BRG == 6)
- mclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN;
-# endif
-# if (MCLK_BRG == 7)
- mclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN;
-# endif
-
- /*
- * Obtain SCLK BRG reset/disabled value
- */
-# if (SCLK_BRG == 0)
- sclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN;
-# endif
-# if (SCLK_BRG == 1)
- sclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN;
-# endif
-# if (SCLK_BRG == 2)
- sclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN;
-# endif
-# if (SCLK_BRG == 3)
- sclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN;
-# endif
-# if (SCLK_BRG == 4)
- sclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN;
-# endif
-# if (SCLK_BRG == 5)
- sclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN;
-# endif
-# if (SCLK_BRG == 6)
- sclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN;
-# endif
-# if (SCLK_BRG == 7)
- sclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN;
-# endif
-
- /*
- * Obtain LRCLK BRG reset/disabled value
- */
-# if (LRCLK_BRG == 0)
- lrclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN;
-# endif
-# if (LRCLK_BRG == 1)
- lrclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN;
-# endif
-# if (LRCLK_BRG == 2)
- lrclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN;
-# endif
-# if (LRCLK_BRG == 3)
- lrclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN;
-# endif
-# if (LRCLK_BRG == 4)
- lrclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN;
-# endif
-# if (LRCLK_BRG == 5)
- lrclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN;
-# endif
-# if (LRCLK_BRG == 6)
- lrclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN;
-# endif
-# if (LRCLK_BRG == 7)
- lrclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN;
-# endif
-
- /*
- * Disable interrupt and save the current state
- */
- flag = disable_interrupts();
-
- /*
- * Set reset on MCLK BRG
- */
-# if (MCLK_BRG == 0)
- *IM_BRGC1 = mclk_brg;
-# endif
-# if (MCLK_BRG == 1)
- *IM_BRGC2 = mclk_brg;
-# endif
-# if (MCLK_BRG == 2)
- *IM_BRGC3 = mclk_brg;
-# endif
-# if (MCLK_BRG == 3)
- *IM_BRGC4 = mclk_brg;
-# endif
-# if (MCLK_BRG == 4)
- *IM_BRGC5 = mclk_brg;
-# endif
-# if (MCLK_BRG == 5)
- *IM_BRGC6 = mclk_brg;
-# endif
-# if (MCLK_BRG == 6)
- *IM_BRGC7 = mclk_brg;
-# endif
-# if (MCLK_BRG == 7)
- *IM_BRGC8 = mclk_brg;
-# endif
-
- /*
- * Set reset on SCLK BRG
- */
-# if (SCLK_BRG == 0)
- *IM_BRGC1 = sclk_brg;
-# endif
-# if (SCLK_BRG == 1)
- *IM_BRGC2 = sclk_brg;
-# endif
-# if (SCLK_BRG == 2)
- *IM_BRGC3 = sclk_brg;
-# endif
-# if (SCLK_BRG == 3)
- *IM_BRGC4 = sclk_brg;
-# endif
-# if (SCLK_BRG == 4)
- *IM_BRGC5 = sclk_brg;
-# endif
-# if (SCLK_BRG == 5)
- *IM_BRGC6 = sclk_brg;
-# endif
-# if (SCLK_BRG == 6)
- *IM_BRGC7 = sclk_brg;
-# endif
-# if (SCLK_BRG == 7)
- *IM_BRGC8 = sclk_brg;
-# endif
-
- /*
- * Set reset on LRCLK BRG
- */
-# if (LRCLK_BRG == 0)
- *IM_BRGC1 = lrclk_brg;
-# endif
-# if (LRCLK_BRG == 1)
- *IM_BRGC2 = lrclk_brg;
-# endif
-# if (LRCLK_BRG == 2)
- *IM_BRGC3 = lrclk_brg;
-# endif
-# if (LRCLK_BRG == 3)
- *IM_BRGC4 = lrclk_brg;
-# endif
-# if (LRCLK_BRG == 4)
- *IM_BRGC5 = lrclk_brg;
-# endif
-# if (LRCLK_BRG == 5)
- *IM_BRGC6 = lrclk_brg;
-# endif
-# if (LRCLK_BRG == 6)
- *IM_BRGC7 = lrclk_brg;
-# endif
-# if (LRCLK_BRG == 7)
- *IM_BRGC8 = lrclk_brg;
-# endif
-
- /*
- * Clear reset on MCLK BRG
- */
-# if (MCLK_BRG == 0)
- *IM_BRGC1 = mclk_brg & ~CPM_BRG_RST;
-# endif
-# if (MCLK_BRG == 1)
- *IM_BRGC2 = mclk_brg & ~CPM_BRG_RST;
-# endif
-# if (MCLK_BRG == 2)
- *IM_BRGC3 = mclk_brg & ~CPM_BRG_RST;
-# endif
-# if (MCLK_BRG == 3)
- *IM_BRGC4 = mclk_brg & ~CPM_BRG_RST;
-# endif
-# if (MCLK_BRG == 4)
- *IM_BRGC5 = mclk_brg & ~CPM_BRG_RST;
-# endif
-# if (MCLK_BRG == 5)
- *IM_BRGC6 = mclk_brg & ~CPM_BRG_RST;
-# endif
-# if (MCLK_BRG == 6)
- *IM_BRGC7 = mclk_brg & ~CPM_BRG_RST;
-# endif
-# if (MCLK_BRG == 7)
- *IM_BRGC8 = mclk_brg & ~CPM_BRG_RST;
-# endif
-
- /*
- * Clear reset on SCLK BRG
- */
-# if (SCLK_BRG == 0)
- *IM_BRGC1 = sclk_brg & ~CPM_BRG_RST;
-# endif
-# if (SCLK_BRG == 1)
- *IM_BRGC2 = sclk_brg & ~CPM_BRG_RST;
-# endif
-# if (SCLK_BRG == 2)
- *IM_BRGC3 = sclk_brg & ~CPM_BRG_RST;
-# endif
-# if (SCLK_BRG == 3)
- *IM_BRGC4 = sclk_brg & ~CPM_BRG_RST;
-# endif
-# if (SCLK_BRG == 4)
- *IM_BRGC5 = sclk_brg & ~CPM_BRG_RST;
-# endif
-# if (SCLK_BRG == 5)
- *IM_BRGC6 = sclk_brg & ~CPM_BRG_RST;
-# endif
-# if (SCLK_BRG == 6)
- *IM_BRGC7 = sclk_brg & ~CPM_BRG_RST;
-# endif
-# if (SCLK_BRG == 7)
- *IM_BRGC8 = sclk_brg & ~CPM_BRG_RST;
-# endif
-
- /*
- * Clear reset on LRCLK BRG
- */
-# if (LRCLK_BRG == 0)
- *IM_BRGC1 = lrclk_brg & ~CPM_BRG_RST;
-# endif
-# if (LRCLK_BRG == 1)
- *IM_BRGC2 = lrclk_brg & ~CPM_BRG_RST;
-# endif
-# if (LRCLK_BRG == 2)
- *IM_BRGC3 = lrclk_brg & ~CPM_BRG_RST;
-# endif
-# if (LRCLK_BRG == 3)
- *IM_BRGC4 = lrclk_brg & ~CPM_BRG_RST;
-# endif
-# if (LRCLK_BRG == 4)
- *IM_BRGC5 = lrclk_brg & ~CPM_BRG_RST;
-# endif
-# if (LRCLK_BRG == 5)
- *IM_BRGC6 = lrclk_brg & ~CPM_BRG_RST;
-# endif
-# if (LRCLK_BRG == 6)
- *IM_BRGC7 = lrclk_brg & ~CPM_BRG_RST;
-# endif
-# if (LRCLK_BRG == 7)
- *IM_BRGC8 = lrclk_brg & ~CPM_BRG_RST;
-# endif
-
- /*
- * Restore the Interrupt state
- */
- if (flag) {
- enable_interrupts();
- }
-# else
- /*
- * Reset the clocks
- */
- Daq_BRG_Reset(MCLK_BRG);
- Daq_BRG_Reset(SCLK_BRG);
- Daq_BRG_Reset(LRCLK_BRG);
-# endif
-}
-
-void Daq_Start_Clocks(int sample_rate)
-
-{
-#ifdef TIGHTEN_UP_BRG_TIMING
- volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-
- register uint mclk_brg; /* MCLK BRG value */
- register uint sclk_brg; /* SCLK BRG value */
- register uint temp_lrclk_brg; /* Temporary LRCLK BRG value */
- register uint real_lrclk_brg; /* Permanent LRCLK BRG value */
- uint lrclk_brg; /* LRCLK BRG value */
- unsigned long flags; /* Interrupt flags */
- uint sclk_cnt; /* SCLK count */
- uint delay_cnt; /* Delay count */
-#endif
-
-# ifdef TIGHTEN_UP_BRG_TIMING
- /*
- * Obtain the enabled MCLK BRG value
- */
-# if (MCLK_BRG == 0)
- mclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN;
-# endif
-# if (MCLK_BRG == 1)
- mclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN;
-# endif
-# if (MCLK_BRG == 2)
- mclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN;
-# endif
-# if (MCLK_BRG == 3)
- mclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN;
-# endif
-# if (MCLK_BRG == 4)
- mclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN;
-# endif
-# if (MCLK_BRG == 5)
- mclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN;
-# endif
-# if (MCLK_BRG == 6)
- mclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN;
-# endif
-# if (MCLK_BRG == 7)
- mclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN;
-# endif
-
- /*
- * Obtain the enabled SCLK BRG value
- */
-# if (SCLK_BRG == 0)
- sclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN;
-# endif
-# if (SCLK_BRG == 1)
- sclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN;
-# endif
-# if (SCLK_BRG == 2)
- sclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN;
-# endif
-# if (SCLK_BRG == 3)
- sclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN;
-# endif
-# if (SCLK_BRG == 4)
- sclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN;
-# endif
-# if (SCLK_BRG == 5)
- sclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN;
-# endif
-# if (SCLK_BRG == 6)
- sclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN;
-# endif
-# if (SCLK_BRG == 7)
- sclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN;
-# endif
-
- /*
- * Obtain the enabled LRCLK BRG value
- */
-# if (LRCLK_BRG == 0)
- lrclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN;
-# endif
-# if (LRCLK_BRG == 1)
- lrclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN;
-# endif
-# if (LRCLK_BRG == 2)
- lrclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN;
-# endif
-# if (LRCLK_BRG == 3)
- lrclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN;
-# endif
-# if (LRCLK_BRG == 4)
- lrclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN;
-# endif
-# if (LRCLK_BRG == 5)
- lrclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN;
-# endif
-# if (LRCLK_BRG == 6)
- lrclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN;
-# endif
-# if (LRCLK_BRG == 7)
- lrclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN;
-# endif
-
- /* Save off the real LRCLK value */
- real_lrclk_brg = lrclk_brg;
-
- /* Obtain the current SCLK count */
- sclk_cnt = ((sclk_brg & 0x00001FFE) >> 1) + 1;
-
- /* Compute the delay as a function of SCLK count */
- delay_cnt = ((sclk_cnt / 4) - 2) * 10 + 6;
- if (DaqSampleRate == 43402) {
- delay_cnt++;
- }
-
- /* Clear out the count */
- temp_lrclk_brg = sclk_brg & ~0x00001FFE;
-
- /* Insert the count */
- temp_lrclk_brg |= ((delay_cnt + (sclk_cnt / 2) - 1) << 1) & 0x00001FFE;
-
- /*
- * Disable interrupt and save the current state
- */
- flag = disable_interrupts();
-
- /*
- * Enable MCLK BRG
- */
-# if (MCLK_BRG == 0)
- *IM_BRGC1 = mclk_brg;
-# endif
-# if (MCLK_BRG == 1)
- *IM_BRGC2 = mclk_brg;
-# endif
-# if (MCLK_BRG == 2)
- *IM_BRGC3 = mclk_brg;
-# endif
-# if (MCLK_BRG == 3)
- *IM_BRGC4 = mclk_brg;
-# endif
-# if (MCLK_BRG == 4)
- *IM_BRGC5 = mclk_brg;
-# endif
-# if (MCLK_BRG == 5)
- *IM_BRGC6 = mclk_brg;
-# endif
-# if (MCLK_BRG == 6)
- *IM_BRGC7 = mclk_brg;
-# endif
-# if (MCLK_BRG == 7)
- *IM_BRGC8 = mclk_brg;
-# endif
-
- /*
- * Enable SCLK BRG
- */
-# if (SCLK_BRG == 0)
- *IM_BRGC1 = sclk_brg;
-# endif
-# if (SCLK_BRG == 1)
- *IM_BRGC2 = sclk_brg;
-# endif
-# if (SCLK_BRG == 2)
- *IM_BRGC3 = sclk_brg;
-# endif
-# if (SCLK_BRG == 3)
- *IM_BRGC4 = sclk_brg;
-# endif
-# if (SCLK_BRG == 4)
- *IM_BRGC5 = sclk_brg;
-# endif
-# if (SCLK_BRG == 5)
- *IM_BRGC6 = sclk_brg;
-# endif
-# if (SCLK_BRG == 6)
- *IM_BRGC7 = sclk_brg;
-# endif
-# if (SCLK_BRG == 7)
- *IM_BRGC8 = sclk_brg;
-# endif
-
- /*
- * Enable LRCLK BRG (1st time - temporary)
- */
-# if (LRCLK_BRG == 0)
- *IM_BRGC1 = temp_lrclk_brg;
-# endif
-# if (LRCLK_BRG == 1)
- *IM_BRGC2 = temp_lrclk_brg;
-# endif
-# if (LRCLK_BRG == 2)
- *IM_BRGC3 = temp_lrclk_brg;
-# endif
-# if (LRCLK_BRG == 3)
- *IM_BRGC4 = temp_lrclk_brg;
-# endif
-# if (LRCLK_BRG == 4)
- *IM_BRGC5 = temp_lrclk_brg;
-# endif
-# if (LRCLK_BRG == 5)
- *IM_BRGC6 = temp_lrclk_brg;
-# endif
-# if (LRCLK_BRG == 6)
- *IM_BRGC7 = temp_lrclk_brg;
-# endif
-# if (LRCLK_BRG == 7)
- *IM_BRGC8 = temp_lrclk_brg;
-# endif
-
- /*
- * Enable LRCLK BRG (2nd time - permanent)
- */
-# if (LRCLK_BRG == 0)
- *IM_BRGC1 = real_lrclk_brg;
-# endif
-# if (LRCLK_BRG == 1)
- *IM_BRGC2 = real_lrclk_brg;
-# endif
-# if (LRCLK_BRG == 2)
- *IM_BRGC3 = real_lrclk_brg;
-# endif
-# if (LRCLK_BRG == 3)
- *IM_BRGC4 = real_lrclk_brg;
-# endif
-# if (LRCLK_BRG == 4)
- *IM_BRGC5 = real_lrclk_brg;
-# endif
-# if (LRCLK_BRG == 5)
- *IM_BRGC6 = real_lrclk_brg;
-# endif
-# if (LRCLK_BRG == 6)
- *IM_BRGC7 = real_lrclk_brg;
-# endif
-# if (LRCLK_BRG == 7)
- *IM_BRGC8 = real_lrclk_brg;
-# endif
-
- /*
- * Restore the Interrupt state
- */
- if (flag) {
- enable_interrupts();
- }
-# else
- /*
- * Enable the clocks
- */
- Daq_BRG_Enable(LRCLK_BRG);
- Daq_BRG_Enable(SCLK_BRG);
- Daq_BRG_Enable(MCLK_BRG);
-# endif
-}
-
-void Daq_Display_Clocks(void)
-
-{
- volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
- uint mclk_divisor; /* Detected MCLK divisor */
- uint sclk_divisor; /* Detected SCLK divisor */
-
- printf("\nBRG:\n");
- if (immr->im_brgc4 != 0) {
- printf("\tbrgc4\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, MCLK\n",
- immr->im_brgc4,
- (uint)&(immr->im_brgc4),
- Daq_BRG_Get_Count(3),
- Daq_BRG_Get_ExtClk(3),
- Daq_BRG_Get_ExtClk_Description(3));
- }
- if (immr->im_brgc8 != 0) {
- printf("\tbrgc8\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SCLK\n",
- immr->im_brgc8,
- (uint)&(immr->im_brgc8),
- Daq_BRG_Get_Count(7),
- Daq_BRG_Get_ExtClk(7),
- Daq_BRG_Get_ExtClk_Description(7));
- }
- if (immr->im_brgc6 != 0) {
- printf("\tbrgc6\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, LRCLK\n",
- immr->im_brgc6,
- (uint)&(immr->im_brgc6),
- Daq_BRG_Get_Count(5),
- Daq_BRG_Get_ExtClk(5),
- Daq_BRG_Get_ExtClk_Description(5));
- }
- if (immr->im_brgc1 != 0) {
- printf("\tbrgc1\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SMC1\n",
- immr->im_brgc1,
- (uint)&(immr->im_brgc1),
- Daq_BRG_Get_Count(0),
- Daq_BRG_Get_ExtClk(0),
- Daq_BRG_Get_ExtClk_Description(0));
- }
- if (immr->im_brgc2 != 0) {
- printf("\tbrgc2\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SMC2\n",
- immr->im_brgc2,
- (uint)&(immr->im_brgc2),
- Daq_BRG_Get_Count(1),
- Daq_BRG_Get_ExtClk(1),
- Daq_BRG_Get_ExtClk_Description(1));
- }
- if (immr->im_brgc3 != 0) {
- printf("\tbrgc3\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SCC1\n",
- immr->im_brgc3,
- (uint)&(immr->im_brgc3),
- Daq_BRG_Get_Count(2),
- Daq_BRG_Get_ExtClk(2),
- Daq_BRG_Get_ExtClk_Description(2));
- }
- if (immr->im_brgc5 != 0) {
- printf("\tbrgc5\t0x%08x @ 0x%08x, %5d count, %d extc, %8s\n",
- immr->im_brgc5,
- (uint)&(immr->im_brgc5),
- Daq_BRG_Get_Count(4),
- Daq_BRG_Get_ExtClk(4),
- Daq_BRG_Get_ExtClk_Description(4));
- }
- if (immr->im_brgc7 != 0) {
- printf("\tbrgc7\t0x%08x @ 0x%08x, %5d count, %d extc, %8s\n",
- immr->im_brgc7,
- (uint)&(immr->im_brgc7),
- Daq_BRG_Get_Count(6),
- Daq_BRG_Get_ExtClk(6),
- Daq_BRG_Get_ExtClk_Description(6));
- }
-
-# ifdef RUN_SCLK_ON_BRG_INT
- mclk_divisor = Daq_BRG_Rate(MCLK_BRG) / Daq_BRG_Rate(SCLK_BRG);
-# else
- mclk_divisor = Daq_BRG_Get_Count(SCLK_BRG);
-# endif
-# ifdef RUN_LRCLK_ON_BRG_INT
- sclk_divisor = Daq_BRG_Rate(SCLK_BRG) / Daq_BRG_Rate(LRCLK_BRG);
-# else
- sclk_divisor = Daq_BRG_Get_Count(LRCLK_BRG);
-# endif
-
- printf("\nADC/DAC Clocking (%d/%d):\n", sclk_divisor, mclk_divisor);
- printf("\tMCLK %8d Hz, or %3dx SCLK, or %3dx LRCLK\n",
- Daq_BRG_Rate(MCLK_BRG),
- mclk_divisor,
- mclk_divisor * sclk_divisor);
-# ifdef RUN_SCLK_ON_BRG_INT
- printf("\tSCLK %8d Hz, or %3dx LRCLK\n",
- Daq_BRG_Rate(SCLK_BRG),
- sclk_divisor);
-# else
- printf("\tSCLK %8d Hz, or %3dx LRCLK\n",
- Daq_BRG_Rate(MCLK_BRG) / mclk_divisor,
- sclk_divisor);
-# endif
-# ifdef RUN_LRCLK_ON_BRG_INT
- printf("\tLRCLK %8d Hz\n",
- Daq_BRG_Rate(LRCLK_BRG));
-# else
-# ifdef RUN_SCLK_ON_BRG_INT
- printf("\tLRCLK %8d Hz\n",
- Daq_BRG_Rate(SCLK_BRG) / sclk_divisor);
-# else
- printf("\tLRCLK %8d Hz\n",
- Daq_BRG_Rate(MCLK_BRG) / (mclk_divisor * sclk_divisor));
-# endif
-# endif
- printf("\n");
-}
diff --git a/board/sacsng/clkinit.h b/board/sacsng/clkinit.h
deleted file mode 100644
index 3f759dd..0000000
--- a/board/sacsng/clkinit.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * (C) Copyright 2002
- * Custom IDEAS, Inc. <www.cideas.com>
- * Jon Diekema <diekema@cideas.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#define SLRCLK_EN_MASK 0x00040000 /* PA13 - SLRCLK_EN* */
-
-#define MIN_SAMPLE_RATE 4000 /* Minimum sample rate */
-#define MAX_128x_SAMPLE_RATE 43402 /* Maximum 128x sample rate */
-#define MAX_64x_SAMPLE_RATE 86805 /* Maximum 64x sample rate */
-
-#define KHZ ((uint)1000)
-#define MHZ ((uint)(1000 * KHZ))
-
-#define MCLK_BRG 3 /* MCLK, Master CLocK for the A/D & D/A */
-#define SCLK_BRG 7 /* SCLK, Sample CLocK for the A/D & D/A */
-#define LRCLK_BRG 5 /* LRCLK, L/R CLocK for the A/D & D/A */
- /* 0 == BRG1 (used for SMC1) */
- /* 1 == BRG2 (used for SMC2) */
- /* 2 == BRG3 (used for SCC1) */
- /* 3 == BRG4 (MCLK) */
- /* 4 == BRG5 */
- /* 5 == BRG6 (LRCLK) */
- /* 6 == BRG7 */
- /* 7 == BRG8 (SCLK) */
-
-#define MCLK_DIVISOR 4 /* SCLK = MCLK / MCLK_DIVISOR */
-#define SCLK_DIVISOR (Daq64xSampling ? 64 : 128)
- /* LRCLK = SCLK / SCLK_DIVISOR */
-
-#define TIGHTEN_UP_BRG_EN_TIMING /* Tighten up the BRG enable timing */
-#define RUN_SCLK_ON_BRG_INT /* Run SCLK on BRG_INT instead of MCLK */
- /* The 8260 (Mask B.3) seems to have */
- /* problems generating SCLK from MCLK */
- /* via CLK9. */
-#define RUN_LRCLK_ON_BRG_INT /* Run LRCLK on BRG_INT instead of SCLK */
- /* The 8260 (Mask B.3) seems to have */
- /* problems generating LRCLK from SCLK */
-
-#define NUM_LRCLKS_TO_STABILIZE 1 /* Number of LRCLK period (sample) */
- /* to wait for the clock to stabilize */
-
-#define CPM_CLK (gd->bd->bi_cpmfreq)
-#define DFBRG 4
-#define BRG_INT_CLK (CPM_CLK * 2 / DFBRG)
- /* BRG = CPM * 2 / DFBRG (Sect 9.8) */
- /* BRG = CPM * 2 / 4 */
- /* BRG = CPM / 2 */
-
-#define CPM_BRG_EXTC_MASK ((uint)0x0000C000)
-#define CPM_BRG_EXTC_SHIFT 14
-
-#define CPM_BRG_DIV16_MASK ((uint)0x00000001)
-#define CPM_BRG_DIV16_SHIFT 1
-
-#define CPM_BRG_EXTC_BRGCLK 0
-#define CPM_BRG_EXTC_CLK3 1
-#define CPM_BRG_EXTC_CLK9 CPM_BRG_EXTC_CLK3
-#define CPM_BRG_EXTC_CLK5 2
-#define CPM_BRG_EXTC_CLK15 CPM_BRG_EXTC_CLK5
-
-#define IM_BRGC1 ((uint *)0xf00119f0)
-#define IM_BRGC2 ((uint *)0xf00119f4)
-#define IM_BRGC3 ((uint *)0xf00119f8)
-#define IM_BRGC4 ((uint *)0xf00119fc)
-#define IM_BRGC5 ((uint *)0xf00115f0)
-#define IM_BRGC6 ((uint *)0xf00115f4)
-#define IM_BRGC7 ((uint *)0xf00115f8)
-#define IM_BRGC8 ((uint *)0xf00115fc)
-
-/*
- * External declarations
- */
-
-extern int Daq64xSampling;
-
-extern void Daq_BRG_Reset(uint brg);
-extern void Daq_BRG_Run(uint brg);
-
-extern void Daq_BRG_Disable(uint brg);
-extern void Daq_BRG_Enable(uint brg);
-
-extern uint Daq_BRG_Get_Div16(uint brg);
-extern void Daq_BRG_Set_Div16(uint brg, uint div16);
-
-extern uint Daq_BRG_Get_Count(uint brg);
-extern void Daq_BRG_Set_Count(uint brg, uint brg_cnt);
-
-extern uint Daq_BRG_Get_ExtClk(uint brg);
-extern char* Daq_BRG_Get_ExtClk_Description(uint brg);
-extern void Daq_BRG_Set_ExtClk(uint brg, uint extc);
-
-extern uint Daq_BRG_Rate(uint brg);
-
-extern uint Daq_Get_SampleRate(void);
-
-extern void Daq_Init_Clocks(int sample_rate, int sample_64x);
-extern void Daq_Stop_Clocks(void);
-extern void Daq_Start_Clocks(int sample_rate);
-extern void Daq_Display_Clocks(void);
diff --git a/board/sacsng/flash.c b/board/sacsng/flash.c
deleted file mode 100644
index 686fb22..0000000
--- a/board/sacsng/flash.c
+++ /dev/null
@@ -1,507 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <configs/sacsng.h>
-
-
-#undef DEBUG
-
-#ifndef CONFIG_ENV_ADDR
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-#endif
-#ifndef CONFIG_ENV_SIZE
-#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-#endif
-
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_short *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- unsigned long size_b0, size_b1;
- int i;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- size_b0 = flash_get_size((vu_short *)CONFIG_SYS_FLASH0_BASE, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0<<20);
- }
-
- size_b1 = flash_get_size((vu_short *)CONFIG_SYS_FLASH1_BASE, &flash_info[1]);
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[0]);
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
- &flash_info[0]);
-#endif
-
- if (size_b1) {
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[1]);
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
- &flash_info[1]);
-#endif
- } else {
- flash_info[1].flash_id = FLASH_UNKNOWN;
- flash_info[1].sector_count = -1;
- }
-
- flash_info[0].size = size_b0;
- flash_info[1].size = size_b1;
-
- /*
- * We only report the primary flash for U-Boot's use.
- */
- return (size_b0);
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
- break;
- case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
- break;
- case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
- break;
- case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
- return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size (vu_short *addr, flash_info_t *info)
-{
- short i;
- ushort value;
- ulong base = (ulong)addr;
-
- /* Write auto select command: read Manufacturer ID */
- addr[0x0555] = 0xAAAA;
- addr[0x02AA] = 0x5555;
- addr[0x0555] = 0x9090;
- __asm__ __volatile__(" sync\n ");
-
- value = addr[0];
-#ifdef DEBUG
- printf("Flash manufacturer 0x%04X\n", value);
-#endif
-
- if(value == (ushort)AMD_MANUFACT) {
- info->flash_id = FLASH_MAN_AMD;
- } else if (value == (ushort)FUJ_MANUFACT) {
- info->flash_id = FLASH_MAN_FUJ;
- } else {
-#ifdef DEBUG
- printf("Unknown flash manufacturer 0x%04X\n", value);
-#endif
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
- value = addr[1]; /* device ID */
-#ifdef DEBUG
- printf("Flash type 0x%04X\n", value);
-#endif
-
- if(value == (ushort)AMD_ID_LV400T) {
- info->flash_id += FLASH_AM400T;
- info->sector_count = 11;
- info->size = 0x00080000; /* => 0.5 MB */
- } else if(value == (ushort)AMD_ID_LV400B) {
- info->flash_id += FLASH_AM400B;
- info->sector_count = 11;
- info->size = 0x00080000; /* => 0.5 MB */
- } else if(value == (ushort)AMD_ID_LV800T) {
- info->flash_id += FLASH_AM800T;
- info->sector_count = 19;
- info->size = 0x00100000; /* => 1 MB */
- } else if(value == (ushort)AMD_ID_LV800B) {
- info->flash_id += FLASH_AM800B;
- info->sector_count = 19;
- info->size = 0x00100000; /* => 1 MB */
- } else if(value == (ushort)AMD_ID_LV160T) {
- info->flash_id += FLASH_AM160T;
- info->sector_count = 35;
- info->size = 0x00200000; /* => 2 MB */
- } else if(value == (ushort)AMD_ID_LV160B) {
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00200000; /* => 2 MB */
- } else if(value == (ushort)AMD_ID_LV320T) {
- info->flash_id += FLASH_AM320T;
- info->sector_count = 67;
- info->size = 0x00400000; /* => 4 MB */
- } else if(value == (ushort)AMD_ID_LV320B) {
- info->flash_id += FLASH_AM320B;
- info->sector_count = 67;
- info->size = 0x00400000; /* => 4 MB */
- } else {
-#ifdef DEBUG
- printf("Unknown flash type 0x%04X\n", value);
- info->size = CONFIG_SYS_FLASH_SIZE;
-#else
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
-#endif
- }
-
- /* set up sector start address table */
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + ((i - 3) * 0x00010000);
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + (i * 0x00010000);
- }
- }
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- addr = (volatile unsigned short *)(info->start[i]);
- info->protect[i] = addr[2] & 1;
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- addr = (volatile unsigned short *)info->start[0];
-
- }
-
- addr[0] = 0xF0F0; /* reset bank */
- __asm__ __volatile__(" sync\n ");
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- vu_short *addr = (vu_short*)(info->start[0]);
- int flag, prot, sect, l_sect;
- ulong start, now, last;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id == FLASH_UNKNOWN) ||
- (info->flash_id > FLASH_AMD_COMP)) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x0555] = 0xAAAA;
- addr[0x02AA] = 0x5555;
- addr[0x0555] = 0x8080;
- addr[0x0555] = 0xAAAA;
- addr[0x02AA] = 0x5555;
- __asm__ __volatile__(" sync\n ");
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = (vu_short*)(info->start[sect]);
- addr[0] = 0x3030;
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer (0);
- last = start;
- addr = (vu_short*)(info->start[l_sect]);
- while ((addr[0] & 0x0080) != 0x0080) {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- addr[0] = 0xF0F0; /* reset bank */
- __asm__ __volatile__(" sync\n ");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
-DONE:
- /* reset to read mode */
- addr = (vu_short*)info->start[0];
- addr[0] = 0xF0F0; /* reset bank */
- __asm__ __volatile__(" sync\n ");
-
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i=0; i<4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
- vu_short *addr = (vu_short*)(info->start[0]);
- ulong start;
- int flag;
- int j;
-
- /* Check if Flash is (sufficiently) erased */
- if (((*(vu_long *)dest) & data) != data) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- /* The original routine was designed to write 32 bit words to
- * 32 bit wide memory. We have 16 bit wide memory so we do
- * two writes. We write the LSB first at dest+2 and then the
- * MSB at dest (lousy big endian).
- */
- dest += 2;
- for(j = 0; j < 2; j++) {
- addr[0x0555] = 0xAAAA;
- addr[0x02AA] = 0x5555;
- addr[0x0555] = 0xA0A0;
- __asm__ __volatile__(" sync\n ");
-
- *((vu_short *)dest) = (ushort)data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
- while (*(vu_short *)dest != (ushort)data) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- dest -= 2;
- data >>= 16;
- }
- return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
diff --git a/board/sacsng/ioconfig.h b/board/sacsng/ioconfig.h
deleted file mode 100644
index ac8f152..0000000
--- a/board/sacsng/ioconfig.h
+++ /dev/null
@@ -1,217 +0,0 @@
-/*
- * I/O Port configuration table
- *
- * If conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-#ifdef SKIP
-#undef SKIP
-#endif
-
-#ifdef CONF
-#undef CONF
-#endif
-
-#ifdef DIN
-#undef DIN
-#endif
-
-#ifdef DOUT
-#undef DOUT
-#endif
-
-#ifdef GPIO
-#undef GPIO
-#endif
-
-#ifdef SPEC
-#undef SPEC
-#endif
-
-#ifdef ACTV
-#undef ACTV
-#endif
-
-#ifdef OPEN
-#undef OPEN
-#endif
-
-#define SKIP 0 /* SKIP over this port */
-#define CONF 1 /* CONFiguration the port */
-
-#define DIN 0 /* PDIRx 0: Direction IN */
-#define DOUT 1 /* PDIRx 1: Direction OUT */
-
-#define GPIO 0 /* PPARx 0: General Purpose I/O */
-#define SPEC 1 /* PPARx 1: dedicated to a peripheral function, */
- /* i.e. the port has a SPECial use. */
-
-#define ACTV 0 /* PODRx 0: ACTiVely driven as an output */
-#define OPEN 1 /* PODRx 1: OPEN-drain driver */
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
- /* Port A configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PA31 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS8* */
- /* PA30 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS7* */
- /* PA29 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS6* */
- /* PA28 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS5* */
- /* PA27 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS4* */
- /* PA26 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS3* */
- /* PA25 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS2* */
- /* PA24 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS1* */
- /* PA23 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* ODIS_EN* */
- /* PA22 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* STLED2_EN* */
- /* PA21 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* STLED1_EN* */
- /* PA20 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* PLED3_EN* */
- /* PA19 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* PLED2_EN* */
- /* PA18 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* PLED1_EN* */
- /* PA17 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
- /* PA16 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* DAC_RST* */
- /* PA15 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* CH34SDATA_PU */
- /* PA14 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* CH12SDATA_PU */
- /* PA13 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* SLRCLK_EN* */
- /* PA12 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_4ACDC* */
- /* PA11 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_4TEDS* */
- /* PA10 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_4XTDS* */
- /* PA9 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_3ACDC* */
- /* PA8 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_3TEDS* */
- /* PA7 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_3XTDS* */
- /* PA6 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_2ACDC* */
- /* PA5 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_2TEDS* */
- /* PA4 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_2XTDS* */
- /* PA3 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
- /* PA2 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_1ACDC* */
- /* PA1 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_1TEDS* */
- /* PA0 */ { CONF, GPIO, 0, DOUT, ACTV, 1 } /* MTRX_1XTDS* */
- },
-
- /* Port B configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PB31 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* FCC2 MII_TX_ER */
- /* PB30 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_RX_DV */
- /* PB29 */ { CONF, SPEC, 1, DOUT, ACTV, 0 }, /* FCC2 MII_TX_EN */
- /* PB28 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_RX_ER */
- /* PB27 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_COL */
- /* PB26 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_CRS */
- /* PB25 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* FCC2 MII_TXD3 */
- /* PB24 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* FCC2 MII_TXD2 */
- /* PB23 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* FCC2 MII_TXD1 */
- /* PB22 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* FCC2 MII_TXD0 */
- /* PB21 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_RXD0 */
- /* PB20 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_RXD1 */
- /* PB19 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_RXD2 */
- /* PB18 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_RXD3 */
- /* PB17 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
- /* PB16 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
- /* PB15 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
- /* PB14 */ { CONF, SPEC, 1, DIN, ACTV, 0 }, /* L1RXDC1, BSDATA_ADC12 */
- /* PB13 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
- /* PB12 */ { CONF, SPEC, 1, DIN, ACTV, 0 }, /* L1RSYNCC1, LRCLK */
- /* PB11 */ { CONF, SPEC, 1, DIN, ACTV, 0 }, /* L1TXDD1, RSDATA_DAC12 */
- /* PB10 */ { CONF, SPEC, 1, DIN, ACTV, 0 }, /* L1RXDD1, BSDATA_ADC34 */
- /* PB9 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
- /* PB8 */ { CONF, SPEC, 1, DIN, ACTV, 0 }, /* L1RSYNCD1, LRCLK */
- /* PB7 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
- /* PB6 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* XCITE_SHDN */
- /* PB5 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* TRIGGER */
- /* PB4 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* ARM */
- /* PB3 */ { SKIP, GPIO, 0, DIN, ACTV, 0 }, /* pin doesn't exist */
- /* PB2 */ { SKIP, GPIO, 0, DIN, ACTV, 0 }, /* pin doesn't exist */
- /* PB1 */ { SKIP, GPIO, 0, DIN, ACTV, 0 }, /* pin doesn't exist */
- /* PB0 */ { SKIP, GPIO, 0, DIN, ACTV, 0 } /* pin doesn't exist */
- },
-
- /* Port C */
- { /* conf ppar psor pdir podr pdat */
- /* PC31 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
- /* PC30 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
- /* PC29 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* CLK3, MCLK */
- /* PC28 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* TOUT2* */
-#ifdef QQQ
- /* PC28 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* TOUT2* */
-#endif
- /* PC27 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* CLK5, SCLK */
- /* PC26 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
- /* PC25 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* CLK7, SCLK */
- /* PC24 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
- /* PC23 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* CLK9, MCLK */
- /* PC22 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
- /* PC21 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* BRGO6 (LRCLK) */
- /* PC20 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
- /* PC19 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* CLK13, MII_RXCLK */
- /* PC18 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* CLK14, MII_TXCLK */
- /* PC17 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* BRGO8 (SCLK) */
- /* PC16 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
- /* PC15 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* SMC2_TX */
- /* PC14 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
- /* PC13 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
- /* PC12 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* TDM_STRB3 */
- /* PC11 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
- /* PC10 */ { CONF, SPEC, 1, DOUT, ACTV, 0 }, /* TDM_STRB4 */
- /* PC9 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* BPDIS_IN3 */
- /* PC8 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* BPDIS_IN2 */
- /* PC7 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* BPDIS_IN1 */
- /* PC6 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
- /* PC5 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* BTST_IN2* */
- /* PC4 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* BTST_IN1* */
- /* PC3 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* MUSH_STAT */
- /* PC2 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* OUTDRV_STAT */
- /* PC1 */ { CONF, GPIO, 0, DOUT, OPEN, 1 }, /* PHY_MDIO */
- /* PC0 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* PHY_MDC */
- },
-
- /* Port D */
- { /* conf ppar psor pdir podr pdat */
- /* PD31 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* SCC1_RX */
- /* PD30 */ { CONF, SPEC, 1, DOUT, ACTV, 0 }, /* SCC1_TX */
- /* PD29 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
- /* PD28 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
- /* PD27 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
- /* PD26 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
- /* PD25 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
- /* PD24 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
- /* PD23 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
- /* PD22 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
- /* PD21 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
- /* PD20 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* SPI_ADC_CS* */
- /* PD19 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* SPI_DAC_CS* */
-#if defined(CONFIG_SOFT_SPI)
- /* PD18 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* SPI_CLK */
- /* PD17 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* SPI_MOSI */
- /* PD16 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* SPI_MISO */
-#else
- /* PD18 */ { CONF, SPEC, 1, DOUT, ACTV, 0 }, /* SPI_CLK */
- /* PD17 */ { CONF, SPEC, 1, DOUT, ACTV, 0 }, /* SPI_MOSI */
- /* PD16 */ { CONF, SPEC, 1, DIN, ACTV, 0 }, /* SPI_MISO */
-#endif
-#if defined(CONFIG_SYS_I2C_SOFT)
- /* PD15 */ { CONF, GPIO, 0, DOUT, OPEN, 1 }, /* I2C_SDA */
- /* PD14 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* I2C_SCL */
-#else
-#if defined(CONFIG_HARD_I2C)
- /* PD15 */ { CONF, SPEC, 1, DIN, OPEN, 0 }, /* I2C_SDA */
- /* PD14 */ { CONF, SPEC, 1, DIN, OPEN, 0 }, /* I2C_SCL */
-#else /* normal I/O port pins */
- /* PD15 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* I2C_SDA */
- /* PD14 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* I2C_SCL */
-#endif
-#endif
- /* PD13 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* TDM_STRB1 */
- /* PD12 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* TDM_STRB2 */
- /* PD11 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
- /* PD10 */ { CONF, SPEC, 1, DOUT, ACTV, 0 }, /* BRGO4 (MCLK) */
- /* PD9 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* SMC1_TX */
- /* PD8 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* SMC1_RX */
- /* PD7 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* N/C */
- /* PD6 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* N/C */
- /* PD5 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* N/C */
- /* PD4 */ { CONF, SPEC, 1, DOUT, ACTV, 1 }, /* SMC2_RX */
- /* PD3 */ { SKIP, GPIO, 0, DIN, ACTV, 0 }, /* pin doesn't exist */
- /* PD2 */ { SKIP, GPIO, 0, DIN, ACTV, 0 }, /* pin doesn't exist */
- /* PD1 */ { SKIP, GPIO, 0, DIN, ACTV, 0 }, /* pin doesn't exist */
- /* PD0 */ { SKIP, GPIO, 0, DIN, ACTV, 0 } /* pin doesn't exist */
- }
-};
diff --git a/board/sacsng/sacsng.c b/board/sacsng/sacsng.c
deleted file mode 100644
index 91c4987..0000000
--- a/board/sacsng/sacsng.c
+++ /dev/null
@@ -1,848 +0,0 @@
-/*
- * (C) Copyright 2002
- * Custom IDEAS, Inc. <www.cideas.com>
- * Gerald Van Baren <vanbaren@cideas.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/u-boot.h>
-#include <ioports.h>
-#include <mpc8260.h>
-#include <i2c.h>
-#include <spi.h>
-#include <command.h>
-
-#ifdef CONFIG_SHOW_BOOT_PROGRESS
-#include <status_led.h>
-#endif
-
-#ifdef CONFIG_ETHER_LOOPBACK_TEST
-extern void eth_loopback_test(void);
-#endif /* CONFIG_ETHER_LOOPBACK_TEST */
-
-#include "clkinit.h"
-#include "ioconfig.h" /* I/O configuration table */
-
-/*
- * PBI Page Based Interleaving
- * PSDMR_PBI page based interleaving
- * 0 bank based interleaving
- * External Address Multiplexing (EAMUX) adds a clock to address cycles
- * (this can help with marginal board layouts)
- * PSDMR_EAMUX adds a clock
- * 0 no extra clock
- * Buffer Command (BUFCMD) adds a clock to command cycles.
- * PSDMR_BUFCMD adds a clock
- * 0 no extra clock
- */
-#define CONFIG_PBI PSDMR_PBI
-#define PESSIMISTIC_SDRAM 0
-#define EAMUX 0 /* EST requires EAMUX */
-#define BUFCMD 0
-
-/*
- * ADC/DAC Defines:
- */
-#define INITIAL_SAMPLE_RATE 10016 /* Initial Daq sample rate */
-#define INITIAL_RIGHT_JUST 0 /* Initial DAC right justification */
-#define INITIAL_MCLK_DIVIDE 0 /* Initial MCLK Divide */
-#define INITIAL_SAMPLE_64X 1 /* Initial 64x clocking mode */
-#define INITIAL_SAMPLE_128X 0 /* Initial 128x clocking mode */
-
-/*
- * ADC Defines:
- */
-#define I2C_ADC_1_ADDR 0x0E /* I2C Address of the ADC #1 */
-#define I2C_ADC_2_ADDR 0x0F /* I2C Address of the ADC #2 */
-
-#define ADC_SDATA1_MASK 0x00020000 /* PA14 - CH12SDATA_PU */
-#define ADC_SDATA2_MASK 0x00010000 /* PA15 - CH34SDATA_PU */
-
-#define ADC_VREF_CAP 100 /* VREF capacitor in uF */
-#define ADC_INITIAL_DELAY (10 * ADC_VREF_CAP) /* 10 usec per uF, in usec */
-#define ADC_SDATA_DELAY 100 /* ADC SDATA release delay in usec */
-#define ADC_CAL_DELAY (1000000 / INITIAL_SAMPLE_RATE * 4500)
- /* Wait at least 4100 LRCLK's */
-
-#define ADC_REG1_FRAME_START 0x80 /* Frame start */
-#define ADC_REG1_GROUND_CAL 0x40 /* Ground calibration enable */
-#define ADC_REG1_ANA_MOD_PDOWN 0x20 /* Analog modulator section in power down */
-#define ADC_REG1_DIG_MOD_PDOWN 0x10 /* Digital modulator section in power down */
-
-#define ADC_REG2_128x 0x80 /* Oversample at 128x */
-#define ADC_REG2_CAL 0x40 /* System calibration enable */
-#define ADC_REG2_CHANGE_SIGN 0x20 /* Change sign enable */
-#define ADC_REG2_LR_DISABLE 0x10 /* Left/Right output disable */
-#define ADC_REG2_HIGH_PASS_DIS 0x08 /* High pass filter disable */
-#define ADC_REG2_SLAVE_MODE 0x04 /* Slave mode */
-#define ADC_REG2_DFS 0x02 /* Digital format select */
-#define ADC_REG2_MUTE 0x01 /* Mute */
-
-#define ADC_REG7_ADDR_ENABLE 0x80 /* Address enable */
-#define ADC_REG7_PEAK_ENABLE 0x40 /* Peak enable */
-#define ADC_REG7_PEAK_UPDATE 0x20 /* Peak update */
-#define ADC_REG7_PEAK_FORMAT 0x10 /* Peak display format */
-#define ADC_REG7_DIG_FILT_PDOWN 0x04 /* Digital filter power down enable */
-#define ADC_REG7_FIR2_IN_EN 0x02 /* External FIR2 input enable */
-#define ADC_REG7_PSYCHO_EN 0x01 /* External pyscho filter input enable */
-
-/*
- * DAC Defines:
- */
-
-#define I2C_DAC_ADDR 0x11 /* I2C Address of the DAC */
-
-#define DAC_RST_MASK 0x00008000 /* PA16 - DAC_RST* */
-#define DAC_RESET_DELAY 100 /* DAC reset delay in usec */
-#define DAC_INITIAL_DELAY 5000 /* DAC initialization delay in usec */
-
-#define DAC_REG1_AMUTE 0x80 /* Auto-mute */
-
-#define DAC_REG1_LEFT_JUST_24_BIT (0 << 4) /* Fmt 0: Left justified 24 bit */
-#define DAC_REG1_I2S_24_BIT (1 << 4) /* Fmt 1: I2S up to 24 bit */
-#define DAC_REG1_RIGHT_JUST_16BIT (2 << 4) /* Fmt 2: Right justified 16 bit */
-#define DAC_REG1_RIGHT_JUST_24BIT (3 << 4) /* Fmt 3: Right justified 24 bit */
-#define DAC_REG1_RIGHT_JUST_20BIT (4 << 4) /* Fmt 4: Right justified 20 bit */
-#define DAC_REG1_RIGHT_JUST_18BIT (5 << 4) /* Fmt 5: Right justified 18 bit */
-
-#define DAC_REG1_DEM_NO (0 << 2) /* No De-emphasis */
-#define DAC_REG1_DEM_44KHZ (1 << 2) /* 44.1KHz De-emphasis */
-#define DAC_REG1_DEM_48KHZ (2 << 2) /* 48KHz De-emphasis */
-#define DAC_REG1_DEM_32KHZ (3 << 2) /* 32KHz De-emphasis */
-
-#define DAC_REG1_SINGLE 0 /* 4- 50KHz sample rate */
-#define DAC_REG1_DOUBLE 1 /* 50-100KHz sample rate */
-#define DAC_REG1_QUAD 2 /* 100-200KHz sample rate */
-#define DAC_REG1_DSD 3 /* Direct Stream Data, DSD */
-
-#define DAC_REG5_INVERT_A 0x80 /* Invert channel A */
-#define DAC_REG5_INVERT_B 0x40 /* Invert channel B */
-#define DAC_REG5_I2C_MODE 0x20 /* Control port (I2C) mode */
-#define DAC_REG5_POWER_DOWN 0x10 /* Power down mode */
-#define DAC_REG5_MUTEC_A_B 0x08 /* Mutec A=B */
-#define DAC_REG5_FREEZE 0x04 /* Freeze */
-#define DAC_REG5_MCLK_DIV 0x02 /* MCLK divide by 2 */
-#define DAC_REG5_RESERVED 0x01 /* Reserved */
-
-/*
- * Check Board Identity:
- */
-
-int checkboard(void)
-{
- printf("SACSng\n");
-
- return 0;
-}
-
-phys_size_t initdram(int board_type)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8260_t *memctl = &immap->im_memctl;
- volatile uchar c = 0;
- volatile uchar *ramaddr = (uchar *)(CONFIG_SYS_SDRAM_BASE + 0x8);
- uint psdmr = CONFIG_SYS_PSDMR;
- int i;
- uint psrt = 14; /* for no SPD */
- uint chipselects = 1; /* for no SPD */
- uint sdram_size = CONFIG_SYS_SDRAM0_SIZE * 1024 * 1024; /* for no SPD */
- uint or = CONFIG_SYS_OR2_PRELIM; /* for no SPD */
-
-#ifdef SDRAM_SPD_ADDR
- uint data_width;
- uint rows;
- uint banks;
- uint cols;
- uint caslatency;
- uint width;
- uint rowst;
- uint sdam;
- uint bsma;
- uint sda10;
- u_char data;
- u_char cksum;
- int j;
-#endif
-
-#ifdef SDRAM_SPD_ADDR
- /* Keep the compiler from complaining about potentially uninitialized vars */
- data_width = chipselects = rows = banks = cols = caslatency = psrt =
- 0;
-
- /*
- * Read the SDRAM SPD EEPROM via I2C.
- */
- i2c_read(SDRAM_SPD_ADDR, 0, 1, &data, 1);
- cksum = data;
- for (j = 1; j < 64; j++) { /* read only the checksummed bytes */
- /* note: the I2C address autoincrements when alen == 0 */
- i2c_read(SDRAM_SPD_ADDR, 0, 0, &data, 1);
- if (j == 5)
- chipselects = data & 0x0F;
- else if (j == 6)
- data_width = data;
- else if (j == 7)
- data_width |= data << 8;
- else if (j == 3)
- rows = data & 0x0F;
- else if (j == 4)
- cols = data & 0x0F;
- else if (j == 12) {
- /*
- * Refresh rate: this assumes the prescaler is set to
- * approximately 1uSec per tick.
- */
- switch (data & 0x7F) {
- default:
- case 0:
- psrt = 14; /* 15.625uS */
- break;
- case 1:
- psrt = 2; /* 3.9uS */
- break;
- case 2:
- psrt = 6; /* 7.8uS */
- break;
- case 3:
- psrt = 29; /* 31.3uS */
- break;
- case 4:
- psrt = 60; /* 62.5uS */
- break;
- case 5:
- psrt = 120; /* 125uS */
- break;
- }
- } else if (j == 17)
- banks = data;
- else if (j == 18) {
- caslatency = 3; /* default CL */
-#if(PESSIMISTIC_SDRAM)
- if ((data & 0x04) != 0)
- caslatency = 3;
- else if ((data & 0x02) != 0)
- caslatency = 2;
- else if ((data & 0x01) != 0)
- caslatency = 1;
-#else
- if ((data & 0x01) != 0)
- caslatency = 1;
- else if ((data & 0x02) != 0)
- caslatency = 2;
- else if ((data & 0x04) != 0)
- caslatency = 3;
-#endif
- else {
- printf("WARNING: Unknown CAS latency 0x%02X, using 3\n", data);
- }
- } else if (j == 63) {
- if (data != cksum) {
- printf("WARNING: Configuration data checksum failure:" " is 0x%02x, calculated 0x%02x\n", data, cksum);
- }
- }
- cksum += data;
- }
-
- /* We don't trust CL less than 2 (only saw it on an old 16MByte DIMM) */
- if (caslatency < 2) {
- printf("WARNING: CL was %d, forcing to 2\n", caslatency);
- caslatency = 2;
- }
- if (rows > 14) {
- printf("WARNING: This doesn't look good, rows = %d, should be <= 14\n",
- rows);
- rows = 14;
- }
- if (cols > 11) {
- printf("WARNING: This doesn't look good, columns = %d, should be <= 11\n",
- cols);
- cols = 11;
- }
-
- if ((data_width != 64) && (data_width != 72)) {
- printf("WARNING: SDRAM width unsupported, is %d, expected 64 or 72.\n",
- data_width);
- }
- width = 3; /* 2^3 = 8 bytes = 64 bits wide */
- /*
- * Convert banks into log2(banks)
- */
- if (banks == 2)
- banks = 1;
- else if (banks == 4)
- banks = 2;
- else if (banks == 8)
- banks = 3;
-
- sdram_size = 1 << (rows + cols + banks + width);
-
-#if(CONFIG_PBI == 0) /* bank-based interleaving */
- rowst = ((32 - 6) - (rows + cols + width)) * 2;
-#else
- rowst = 32 - (rows + banks + cols + width);
-#endif
-
- or = ~(sdram_size - 1) | /* SDAM address mask */
- ((banks - 1) << 13) | /* banks per device */
- (rowst << 9) | /* rowst */
- ((rows - 9) << 6); /* numr */
-
- memctl->memc_or2 = or;
-
- /*
- * SDAM specifies the number of columns that are multiplexed
- * (reference AN2165/D), defined to be (columns - 6) for page
- * interleave, (columns - 8) for bank interleave.
- *
- * BSMA is 14 - max(rows, cols). The bank select lines come
- * into play above the highest "address" line going into the
- * the SDRAM.
- */
-#if(CONFIG_PBI == 0) /* bank-based interleaving */
- sdam = cols - 8;
- bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
- sda10 = sdam + 2;
-#else
- sdam = cols - 6;
- bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
- sda10 = sdam;
-#endif
-#if(PESSIMISTIC_SDRAM)
- psdmr = (CONFIG_PBI | PSDMR_RFEN | PSDMR_RFRC_16_CLK |
- PSDMR_PRETOACT_8W | PSDMR_ACTTORW_8W | PSDMR_WRC_4C |
- PSDMR_EAMUX | PSDMR_BUFCMD) | caslatency |
- ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */
- (sdam << 24) | (bsma << 21) | (sda10 << 18);
-#else
- psdmr = (CONFIG_PBI | PSDMR_RFEN | PSDMR_RFRC_7_CLK |
- PSDMR_PRETOACT_3W | /* 1 for 7E parts (fast PC-133) */
- PSDMR_ACTTORW_2W | /* 1 for 7E parts (fast PC-133) */
- PSDMR_WRC_1C | /* 1 clock + 7nSec */
- EAMUX | BUFCMD) |
- caslatency | ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */
- (sdam << 24) | (bsma << 21) | (sda10 << 18);
-#endif
-#endif
-
- /*
- * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
- *
- * "At system reset, initialization software must set up the
- * programmable parameters in the memory controller banks registers
- * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
- * system software should execute the following initialization sequence
- * for each SDRAM device.
- *
- * 1. Issue a PRECHARGE-ALL-BANKS command
- * 2. Issue eight CBR REFRESH commands
- * 3. Issue a MODE-SET command to initialize the mode register
- *
- * Quote from Micron MT48LC8M16A2 data sheet:
- *
- * "...the SDRAM requires a 100uS delay prior to issuing any
- * command other than a COMMAND INHIBIT or NOP. Starting at some
- * point during this 100uS period and continuing at least through
- * the end of this period, COMMAND INHIBIT or NOP commands should
- * be applied."
- *
- * "Once the 100uS delay has been satisfied with at least one COMMAND
- * INHIBIT or NOP command having been applied, a /PRECHARGE command/
- * should be applied. All banks must then be precharged, thereby
- * placing the device in the all banks idle state."
- *
- * "Once in the idle state, /two/ AUTO REFRESH cycles must be
- * performed. After the AUTO REFRESH cycles are complete, the
- * SDRAM is ready for mode register programming."
- *
- * (/emphasis/ mine, gvb)
- *
- * The way I interpret this, Micron start up sequence is:
- * 1. Issue a PRECHARGE-BANK command (initial precharge)
- * 2. Issue a PRECHARGE-ALL-BANKS command ("all banks ... precharged")
- * 3. Issue two (presumably, doing eight is OK) CBR REFRESH commands
- * 4. Issue a MODE-SET command to initialize the mode register
- *
- * --------
- *
- * The initial commands are executed by setting P/LSDMR[OP] and
- * accessing the SDRAM with a single-byte transaction."
- *
- * The appropriate BRx/ORx registers have already been set when we
- * get here. The SDRAM can be accessed@the address CONFIG_SYS_SDRAM_BASE.
- */
-
- memctl->memc_mptpr = CONFIG_SYS_MPTPR;
- memctl->memc_psrt = psrt;
-
- memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
- *ramaddr = c;
-
- memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
- for (i = 0; i < 8; i++)
- *ramaddr = c;
-
- memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
- *ramaddr = c;
-
- memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
- *ramaddr = c;
-
- /*
- * Do it a second time for the second set of chips if the DIMM has
- * two chip selects (double sided).
- */
- if (chipselects > 1) {
- ramaddr += sdram_size;
-
- memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM + sdram_size;
- memctl->memc_or3 = or;
-
- memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
- *ramaddr = c;
-
- memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
- for (i = 0; i < 8; i++)
- *ramaddr = c;
-
- memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
- *ramaddr = c;
-
- memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
- *ramaddr = c;
- }
-
- /* return total ram size */
- return (sdram_size * chipselects);
-}
-
-/*-----------------------------------------------------------------------
- * Board Control Functions
- */
-void board_poweroff(void)
-{
- while (1); /* hang forever */
-}
-
-
-#ifdef CONFIG_MISC_INIT_R
-/* ------------------------------------------------------------------------- */
-int misc_init_r(void)
-{
- /*
- * Note: iop is used by the I2C macros, and iopa by the ADC/DAC initialization.
- */
- volatile ioport_t *iopa =
- ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0 /* port A */ );
- volatile ioport_t *iop =
- ioport_addr((immap_t *)CONFIG_SYS_IMMR, I2C_PORT);
-
- int reg; /* I2C register value */
- char *ep; /* Environment pointer */
- char str_buf[12]; /* sprintf output buffer */
- int sample_rate; /* ADC/DAC sample rate */
- int sample_64x; /* Use 64/4 clocking for the ADC/DAC */
- int sample_128x; /* Use 128/4 clocking for the ADC/DAC */
- int right_just; /* Is the data to the DAC right justified? */
- int mclk_divide; /* MCLK Divide */
- int quiet; /* Quiet or minimal output mode */
-
- quiet = 0;
-
- if ((ep = getenv("quiet")) != NULL)
- quiet = simple_strtol(ep, NULL, 10);
- else
- setenv("quiet", "0");
-
- /*
- * SACSng custom initialization:
- * Start the ADC and DAC clocks, since the Crystal parts do not
- * work on the I2C bus until the clocks are running.
- */
-
- sample_rate = INITIAL_SAMPLE_RATE;
- if ((ep = getenv("DaqSampleRate")) != NULL)
- sample_rate = simple_strtol(ep, NULL, 10);
-
- sample_64x = INITIAL_SAMPLE_64X;
- sample_128x = INITIAL_SAMPLE_128X;
- if ((ep = getenv("Daq64xSampling")) != NULL) {
- sample_64x = simple_strtol(ep, NULL, 10);
- if (sample_64x)
- sample_128x = 0;
- else
- sample_128x = 1;
- } else {
- if ((ep = getenv("Daq128xSampling")) != NULL) {
- sample_128x = simple_strtol(ep, NULL, 10);
- if (sample_128x)
- sample_64x = 0;
- else
- sample_64x = 1;
- }
- }
-
- /*
- * Stop the clocks and wait for at least 1 LRCLK period
- * to make sure the clocking has really stopped.
- */
- Daq_Stop_Clocks();
- udelay((1000000 / sample_rate) * NUM_LRCLKS_TO_STABILIZE);
-
- /*
- * Initialize the clocks with the new rates
- */
- Daq_Init_Clocks(sample_rate, sample_64x);
- sample_rate = Daq_Get_SampleRate();
-
- /*
- * Start the clocks and wait for at least 1 LRCLK period
- * to make sure the clocking has become stable.
- */
- Daq_Start_Clocks(sample_rate);
- udelay((1000000 / sample_rate) * NUM_LRCLKS_TO_STABILIZE);
-
- sprintf(str_buf, "%d", sample_rate);
- setenv("DaqSampleRate", str_buf);
-
- if (sample_64x) {
- setenv("Daq64xSampling", "1");
- setenv("Daq128xSampling", NULL);
- } else {
- setenv("Daq64xSampling", NULL);
- setenv("Daq128xSampling", "1");
- }
-
- /*
- * Display the ADC/DAC clocking information
- */
- if (!quiet)
- Daq_Display_Clocks();
-
- /*
- * Determine the DAC data justification
- */
-
- right_just = INITIAL_RIGHT_JUST;
- if ((ep = getenv("DaqDACRightJustified")) != NULL)
- right_just = simple_strtol(ep, NULL, 10);
-
- sprintf(str_buf, "%d", right_just);
- setenv("DaqDACRightJustified", str_buf);
-
- /*
- * Determine the DAC MCLK Divide
- */
-
- mclk_divide = INITIAL_MCLK_DIVIDE;
- if ((ep = getenv("DaqDACMClockDivide")) != NULL)
- mclk_divide = simple_strtol(ep, NULL, 10);
-
- sprintf(str_buf, "%d", mclk_divide);
- setenv("DaqDACMClockDivide", str_buf);
-
- /*
- * Initializing the I2C address in the Crystal A/Ds:
- *
- * 1) Wait for VREF cap to settle (10uSec per uF)
- * 2) Release pullup on SDATA
- * 3) Write the I2C address to register 6
- * 4) Enable address matching by setting the MSB in register 7
- */
-
- if (!quiet)
- printf("Initializing the ADC...\n");
-
- udelay(ADC_INITIAL_DELAY); /* 10uSec per uF of VREF cap */
-
- iopa->pdat &= ~ADC_SDATA1_MASK; /* release SDATA1 */
- udelay(ADC_SDATA_DELAY); /* arbitrary settling time */
-
- i2c_reg_write(0x00, 0x06, I2C_ADC_1_ADDR); /* set address */
- i2c_reg_write(I2C_ADC_1_ADDR, 0x07, /* turn on ADDREN */
- ADC_REG7_ADDR_ENABLE);
-
- i2c_reg_write(I2C_ADC_1_ADDR, 0x02, /* 128x, slave mode, !HPEN */
- (sample_64x ? 0 : ADC_REG2_128x) |
- ADC_REG2_HIGH_PASS_DIS | ADC_REG2_SLAVE_MODE);
-
- reg = i2c_reg_read(I2C_ADC_1_ADDR, 0x06) & 0x7F;
- if (reg != I2C_ADC_1_ADDR) {
- printf("Init of ADC U10 failed: address is 0x%02X should be 0x%02X\n",
- reg, I2C_ADC_1_ADDR);
- }
-
- iopa->pdat &= ~ADC_SDATA2_MASK; /* release SDATA2 */
- udelay(ADC_SDATA_DELAY); /* arbitrary settling time */
-
- /* set address (do not set ADDREN yet) */
- i2c_reg_write(0x00, 0x06, I2C_ADC_2_ADDR);
-
- i2c_reg_write(I2C_ADC_2_ADDR, 0x02, /* 64x, slave mode, !HPEN */
- (sample_64x ? 0 : ADC_REG2_128x) |
- ADC_REG2_HIGH_PASS_DIS | ADC_REG2_SLAVE_MODE);
-
- reg = i2c_reg_read(I2C_ADC_2_ADDR, 0x06) & 0x7F;
- if (reg != I2C_ADC_2_ADDR) {
- printf("Init of ADC U15 failed: address is 0x%02X should be 0x%02X\n",
- reg, I2C_ADC_2_ADDR);
- }
-
- i2c_reg_write(I2C_ADC_1_ADDR, 0x01, /* set FSTART and GNDCAL */
- ADC_REG1_FRAME_START | ADC_REG1_GROUND_CAL);
-
- i2c_reg_write(I2C_ADC_1_ADDR, 0x02, /* Start calibration */
- (sample_64x ? 0 : ADC_REG2_128x) |
- ADC_REG2_CAL |
- ADC_REG2_HIGH_PASS_DIS | ADC_REG2_SLAVE_MODE);
-
- udelay(ADC_CAL_DELAY); /* a minimum of 4100 LRCLKs */
- i2c_reg_write(I2C_ADC_1_ADDR, 0x01, 0x00); /* remove GNDCAL */
-
- /*
- * Now that we have synchronized the ADC's, enable address
- * selection on the second ADC as well as the first.
- */
- i2c_reg_write(I2C_ADC_2_ADDR, 0x07, ADC_REG7_ADDR_ENABLE);
-
- /*
- * Initialize the Crystal DAC
- *
- * Two of the config lines are used for I2C so we have to set them
- * to the proper initialization state without inadvertantly
- * sending an I2C "start" sequence. When we bring the I2C back to
- * the normal state, we send an I2C "stop" sequence.
- */
- if (!quiet)
- printf("Initializing the DAC...\n");
-
- /*
- * Bring the I2C clock and data lines low for initialization
- */
- I2C_SCL(0);
- I2C_DELAY;
- I2C_SDA(0);
- I2C_ACTIVE;
- I2C_DELAY;
-
- /* Reset the DAC */
- iopa->pdat &= ~DAC_RST_MASK;
- udelay(DAC_RESET_DELAY);
-
- /* Release the DAC reset */
- iopa->pdat |= DAC_RST_MASK;
- udelay(DAC_INITIAL_DELAY);
-
- /*
- * Cause the DAC to:
- * Enable control port (I2C mode)
- * Going into power down
- */
- i2c_reg_write(I2C_DAC_ADDR, 0x05,
- DAC_REG5_I2C_MODE | DAC_REG5_POWER_DOWN);
-
- /*
- * Cause the DAC to:
- * Enable control port (I2C mode)
- * Going into power down
- * . MCLK divide by 1
- * . MCLK divide by 2
- */
- i2c_reg_write(I2C_DAC_ADDR, 0x05,
- DAC_REG5_I2C_MODE |
- DAC_REG5_POWER_DOWN |
- (mclk_divide ? DAC_REG5_MCLK_DIV : 0));
-
- /*
- * Cause the DAC to:
- * Auto-mute disabled
- * . Format 0, left justified 24 bits
- * . Format 3, right justified 24 bits
- * No de-emphasis
- * . Single speed mode
- * . Double speed mode
- */
- i2c_reg_write(I2C_DAC_ADDR, 0x01,
- (right_just ? DAC_REG1_RIGHT_JUST_24BIT :
- DAC_REG1_LEFT_JUST_24_BIT) |
- DAC_REG1_DEM_NO |
- (sample_rate >=
- 50000 ? DAC_REG1_DOUBLE : DAC_REG1_SINGLE));
-
- sprintf(str_buf, "%d",
- sample_rate >= 50000 ? DAC_REG1_DOUBLE : DAC_REG1_SINGLE);
- setenv("DaqDACFunctionalMode", str_buf);
-
- /*
- * Cause the DAC to:
- * Enable control port (I2C mode)
- * Remove power down
- * . MCLK divide by 1
- * . MCLK divide by 2
- */
- i2c_reg_write(I2C_DAC_ADDR, 0x05,
- DAC_REG5_I2C_MODE |
- (mclk_divide ? DAC_REG5_MCLK_DIV : 0));
-
- /*
- * Create a I2C stop condition:
- * low->high on data while clock is high.
- */
- I2C_SCL(1);
- I2C_DELAY;
- I2C_SDA(1);
- I2C_DELAY;
- I2C_TRISTATE;
-
- if (!quiet)
- printf("\n");
-#ifdef CONFIG_ETHER_LOOPBACK_TEST
- /*
- * Run the Ethernet loopback test
- */
- eth_loopback_test();
-#endif /* CONFIG_ETHER_LOOPBACK_TEST */
-
-#ifdef CONFIG_SHOW_BOOT_PROGRESS
- /*
- * Turn off the RED fail LED now that we are up and running.
- */
- status_led_set(STATUS_LED_RED, STATUS_LED_OFF);
-#endif
-
- return 0;
-}
-
-#ifdef CONFIG_SHOW_BOOT_PROGRESS
-/*
- * Show boot status: flash the LED if something goes wrong, indicating
- * that last thing that worked and thus, by implication, what is broken.
- *
- * This stores the last OK value in RAM so this will not work properly
- * before RAM is initialized. Since it is being used for indicating
- * boot status (i.e. after RAM is initialized), that is OK.
- */
-static void flash_code(uchar number, uchar modulo, uchar digits)
-{
- int j;
-
- /*
- * Recursively do upper digits.
- */
- if (digits > 1)
- flash_code(number / modulo, modulo, digits - 1);
-
- number = number % modulo;
-
- /*
- * Zero is indicated by one long flash (dash).
- */
- if (number == 0) {
- status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
- udelay(1000000);
- status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF);
- udelay(200000);
- } else {
- /*
- * Non-zero is indicated by short flashes, one per count.
- */
- for (j = 0; j < number; j++) {
- status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
- udelay(100000);
- status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF);
- udelay(200000);
- }
- }
- /*
- * Inter-digit pause: we've already waited 200 mSec, wait 1 sec total
- */
- udelay(700000);
-}
-
-static int last_boot_progress;
-
-void show_boot_progress(int status)
-{
- int i, j;
-
- if (status > 0) {
- last_boot_progress = status;
- } else {
- /*
- * If a specific failure code is given, flash this code
- * else just use the last success code we've seen
- */
- if (status < -1)
- last_boot_progress = -status;
-
- /*
- * Flash this code 5 times
- */
- for (j = 0; j < 5; j++) {
- /*
- * Houston, we have a problem.
- * Blink the last OK status which indicates where things failed.
- */
- status_led_set(STATUS_LED_RED, STATUS_LED_ON);
- flash_code(last_boot_progress, 5, 3);
-
- /*
- * Delay 5 seconds between repetitions,
- * with the fault LED blinking
- */
- for (i = 0; i < 5; i++) {
- status_led_set(STATUS_LED_RED,
- STATUS_LED_OFF);
- udelay(500000);
- status_led_set(STATUS_LED_RED, STATUS_LED_ON);
- udelay(500000);
- }
- }
-
- /*
- * Reset the board to retry initialization.
- */
- do_reset(NULL, 0, 0, NULL);
- }
-}
-#endif /* CONFIG_SHOW_BOOT_PROGRESS */
-
-
-/*
- * The following are used to control the SPI chip selects for the SPI command.
- */
-#if defined(CONFIG_CMD_SPI)
-
-#define SPI_ADC_CS_MASK 0x00000800
-#define SPI_DAC_CS_MASK 0x00001000
-
-static const u32 cs_mask[] = {
- SPI_ADC_CS_MASK,
- SPI_DAC_CS_MASK,
-};
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- return bus == 0 && cs < sizeof(cs_mask) / sizeof(cs_mask[0]);
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
- volatile ioport_t *iopd =
- ioport_addr((immap_t *) CONFIG_SYS_IMMR, 3 /* port D */ );
-
- iopd->pdat &= ~cs_mask[slave->cs];
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- volatile ioport_t *iopd =
- ioport_addr((immap_t *) CONFIG_SYS_IMMR, 3 /* port D */ );
-
- iopd->pdat |= cs_mask[slave->cs];
-}
-
-#endif
-
-#endif /* CONFIG_MISC_INIT_R */
diff --git a/configs/sacsng_defconfig b/configs/sacsng_defconfig
deleted file mode 100644
index 91cca23..0000000
--- a/configs/sacsng_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_SACSNG=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index c9b4b17..5b71bc9 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+sacsng powerpc mpc8260 - - Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
cogent_mpc8260 powerpc mpc8260 - - Murray Jensen <Murray.Jensen@csiro.au>
cogent_8xx powerpc mpc8xx - - Murray Jensen <Murray.Jensen@csiro.au>
ESTEEM192E powerpc mpc8xx - - Conn Clark <clark@esteem.com>
diff --git a/include/configs/sacsng.h b/include/configs/sacsng.h
deleted file mode 100644
index 2dee315..0000000
--- a/include/configs/sacsng.h
+++ /dev/null
@@ -1,1038 +0,0 @@
-/*
- * (C) Copyright 2000
- * Murray Jensen <Murray.Jensen@cmst.csiro.au>
- *
- * (C) Copyright 2000
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2001
- * Advent Networks, Inc. <http://www.adventnetworks.com>
- * Jay Monkman <jtm@smoothsmoothie.com>
- *
- * Configuration settings for the SACSng 8260 board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_SYS_TEXT_BASE 0x40000000
-
-#undef DEBUG_BOOTP_EXT /* Debug received vendor fields */
-
-#undef CONFIG_LOGBUFFER /* External logbuffer support */
-
-/*****************************************************************************
- *
- * These settings must match the way _your_ board is set up
- *
- *****************************************************************************/
-
-/* What is the oscillator's (UX2) frequency in Hz? */
-#define CONFIG_8260_CLKIN 66666600
-
-/*-----------------------------------------------------------------------
- * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
- *-----------------------------------------------------------------------
- * What should MODCK_H be? It is dependent on the oscillator
- * frequency, MODCK[1-3], and desired CPM and core frequencies.
- * Here are some example values (all frequencies are in MHz):
- *
- * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8
- * ------- ---------- --- --- ---- ----- ----- -----
- * 0x1 0x5 33 100 133 Open Close Open
- * 0x1 0x6 33 100 166 Open Open Close
- * 0x1 0x7 33 100 200 Open Open Open
- *
- * 0x2 0x2 33 133 133 Close Open Close
- * 0x2 0x3 33 133 166 Close Open Open
- * 0x2 0x4 33 133 200 Open Close Close
- * 0x2 0x5 33 133 233 Open Close Open
- * 0x2 0x6 33 133 266 Open Open Close
- *
- * 0x5 0x5 66 133 133 Open Close Open
- * 0x5 0x6 66 133 166 Open Open Close
- * 0x5 0x7 66 133 200 Open Open Open
- * 0x6 0x0 66 133 233 Close Close Close
- * 0x6 0x1 66 133 266 Close Close Open
- * 0x6 0x2 66 133 300 Close Open Close
- */
-#define CONFIG_SYS_SBC_MODCK_H 0x05
-
-/* Define this if you want to boot from 0x00000100. If you don't define
- * this, you will need to program the bootloader to 0xfff00000, and
- * get the hardware reset config words at 0xfe000000. The simplest
- * way to do that is to program the bootloader at both addresses.
- * It is suggested that you just let U-Boot live at 0x00000000.
- */
-#define CONFIG_SYS_SBC_BOOT_LOW 1
-
-/* What should the base address of the main FLASH be and how big is
- * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/sacsng/config.mk
- * The main FLASH is whichever is connected to *CS0.
- */
-#define CONFIG_SYS_FLASH0_BASE 0x40000000
-#define CONFIG_SYS_FLASH0_SIZE 2
-
-/* What should the base address of the secondary FLASH be and how big
- * is it (in Mbytes)? The secondary FLASH is whichever is connected
- * to *CS6.
- */
-#define CONFIG_SYS_FLASH1_BASE 0x60000000
-#define CONFIG_SYS_FLASH1_SIZE 2
-
-/* Define CONFIG_VERY_BIG_RAM to allow use of SDRAMs larger than 256MBytes
- */
-#define CONFIG_VERY_BIG_RAM 1
-
-/* What should be the base address of SDRAM DIMM and how big is
- * it (in Mbytes)? This will normally auto-configure via the SPD.
-*/
-#define CONFIG_SYS_SDRAM0_BASE 0x00000000
-#define CONFIG_SYS_SDRAM0_SIZE 64
-
-/*
- * Memory map example with 64 MB DIMM:
- *
- * 0x0000 0000 Exception Vector code, 8k
- * :
- * 0x0000 1FFF
- * 0x0000 2000 Free for Application Use
- * :
- * :
- *
- * :
- * :
- * 0x03F5 FF30 Monitor Stack (Growing downward)
- * Monitor Stack Buffer (0x80)
- * 0x03F5 FFB0 Board Info Data
- * 0x03F6 0000 Malloc Arena
- * : CONFIG_ENV_SECT_SIZE, 16k
- * : CONFIG_SYS_MALLOC_LEN, 128k
- * 0x03FC 0000 RAM Copy of Monitor Code
- * : CONFIG_SYS_MONITOR_LEN, 256k
- * 0x03FF FFFF [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1
- */
-
-#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
- CONFIG_SYS_POST_CPU)
-
-
-/*
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * if CONFIG_CONS_NONE is defined, then the serial console routines must
- * defined elsewhere.
- */
-#define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */
-#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
-#undef CONFIG_CONS_NONE /* define if console on neither */
-#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
-
-/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
- */
-
-#undef CONFIG_ETHER_ON_SCC
-#define CONFIG_ETHER_ON_FCC
-#undef CONFIG_ETHER_NONE /* define if ethernet on neither */
-
-#ifdef CONFIG_ETHER_ON_SCC
-#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
-#endif /* CONFIG_ETHER_ON_SCC */
-
-#ifdef CONFIG_ETHER_ON_FCC
-#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
-#undef CONFIG_ETHER_LOOPBACK_TEST /* Ethernet external loopback test */
-#define CONFIG_MII /* MII PHY management */
-#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
-/*
- * Port pins used for bit-banged MII communictions (if applicable).
- */
-
-#define MDIO_PORT 2 /* Port A=0, B=1, C=2, D=3 */
-#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
- (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
-#define MDC_DECLARE MDIO_DECLARE
-
-#define MDIO_ACTIVE (iop->pdir |= 0x40000000)
-#define MDIO_TRISTATE (iop->pdir &= ~0x40000000)
-#define MDIO_READ ((iop->pdat & 0x40000000) != 0)
-
-#define MDIO(bit) if(bit) iop->pdat |= 0x40000000; \
- else iop->pdat &= ~0x40000000
-
-#define MDC(bit) if(bit) iop->pdat |= 0x80000000; \
- else iop->pdat &= ~0x80000000
-
-#define MIIDELAY udelay(50)
-#endif /* CONFIG_ETHER_ON_FCC */
-
-#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
-
-/*
- * - RX clk is CLK11
- * - TX clk is CLK12
- */
-# define CONFIG_SYS_CMXSCR_VALUE1 (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
-
-#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
-
-/*
- * - Rx-CLK is CLK13
- * - Tx-CLK is CLK14
- * - Select bus for bd/buffers (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
-# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
-# define CONFIG_SYS_CPMFCR_RAMTYPE 0
-# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
-
-#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
-
-#define CONFIG_SHOW_BOOT_PROGRESS 1 /* boot progress enabled */
-
-/*
- * Configure for RAM tests.
- */
-#undef CONFIG_SYS_DRAM_TEST /* calls other tests in board.c */
-
-
-/*
- * Status LED for power up status feedback.
- */
-#define CONFIG_STATUS_LED 1 /* Status LED enabled */
-
-#define STATUS_LED_PAR im_ioport.iop_ppara
-#define STATUS_LED_DIR im_ioport.iop_pdira
-#define STATUS_LED_ODR im_ioport.iop_podra
-#define STATUS_LED_DAT im_ioport.iop_pdata
-
-#define STATUS_LED_BIT 0x00000800 /* LED 0 is on PA.20 */
-#define STATUS_LED_PERIOD (CONFIG_SYS_HZ)
-#define STATUS_LED_STATE STATUS_LED_OFF
-#define STATUS_LED_BIT1 0x00001000 /* LED 1 is on PA.19 */
-#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ)
-#define STATUS_LED_STATE1 STATUS_LED_OFF
-#define STATUS_LED_BIT2 0x00002000 /* LED 2 is on PA.18 */
-#define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ/2)
-#define STATUS_LED_STATE2 STATUS_LED_ON
-
-#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
-
-#define STATUS_LED_YELLOW 0
-#define STATUS_LED_GREEN 1
-#define STATUS_LED_RED 2
-#define STATUS_LED_BOOT 1
-
-
-/*
- * Select SPI support configuration
- */
-#define CONFIG_SOFT_SPI /* Enable SPI driver */
-#define MAX_SPI_BYTES 4 /* Maximum number of bytes we can handle */
-#undef DEBUG_SPI /* Disable SPI debugging */
-
-/*
- * Software (bit-bang) SPI driver configuration
- */
-#ifdef CONFIG_SOFT_SPI
-
-/*
- * Software (bit-bang) SPI driver configuration
- */
-#define I2C_SCLK 0x00002000 /* PD 18: Shift clock */
-#define I2C_MOSI 0x00004000 /* PD 17: Master Out, Slave In */
-#define I2C_MISO 0x00008000 /* PD 16: Master In, Slave Out */
-
-#define SPI_READ ((immr->im_ioport.iop_pdatd & I2C_MISO) != 0)
-#define SPI_SDA(bit) do { \
- if(bit) immr->im_ioport.iop_pdatd |= I2C_MOSI; \
- else immr->im_ioport.iop_pdatd &= ~I2C_MOSI; \
- } while (0)
-#define SPI_SCL(bit) do { \
- if(bit) immr->im_ioport.iop_pdatd |= I2C_SCLK; \
- else immr->im_ioport.iop_pdatd &= ~I2C_SCLK; \
- } while (0)
-#define SPI_DELAY /* No delay is needed */
-#endif /* CONFIG_SOFT_SPI */
-
-
-/*
- * select I2C support configuration
- *
- * Supported configurations are {none, software, hardware} drivers.
- * If the software driver is chosen, there are some additional
- * configuration items that the driver uses to drive the port pins.
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED 400000
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE (iop->pdir |= 0x00010000)
-#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
-#define I2C_READ ((iop->pdat & 0x00010000) != 0)
-#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
- else iop->pdat &= ~0x00010000
-#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
- else iop->pdat &= ~0x00020000
-#define I2C_DELAY udelay(20) /* 1/4 I2C clock duration */
-
-/* Define this to reserve an entire FLASH sector for
- * environment variables. Otherwise, the environment will be
- * put in the same sector as U-Boot, and changing variables
- * will erase U-Boot temporarily
- */
-#define CONFIG_ENV_IN_OWN_SECT 1
-
-/* Define this to contain any number of null terminated strings that
- * will be part of the default environment compiled into the boot image.
- */
-#define CONFIG_EXTRA_ENV_SETTINGS \
-"quiet=0\0" \
-"serverip=192.168.123.205\0" \
-"ipaddr=192.168.123.203\0" \
-"checkhostname=VR8500\0" \
-"reprog="\
- "bootp; " \
- "tftpboot 0x140000 /bdi2000/u-boot.bin; " \
- "protect off 60000000 6003FFFF; " \
- "erase 60000000 6003FFFF; " \
- "cp.b 140000 60000000 ${filesize}; " \
- "protect on 60000000 6003FFFF\0" \
-"copyenv="\
- "protect off 60040000 6004FFFF; " \
- "erase 60040000 6004FFFF; " \
- "cp.b 40040000 60040000 10000; " \
- "protect on 60040000 6004FFFF\0" \
-"copyprog="\
- "protect off 60000000 6003FFFF; " \
- "erase 60000000 6003FFFF; " \
- "cp.b 40000000 60000000 40000; " \
- "protect on 60000000 6003FFFF\0" \
-"zapenv="\
- "protect off 40040000 4004FFFF; " \
- "erase 40040000 4004FFFF; " \
- "protect on 40040000 4004FFFF\0" \
-"zapotherenv="\
- "protect off 60040000 6004FFFF; " \
- "erase 60040000 6004FFFF; " \
- "protect on 60040000 6004FFFF\0" \
-"root-on-initrd="\
- "setenv bootcmd "\
- "version\\;" \
- "echo\\;" \
- "bootp\\;" \
- "setenv bootargs root=/dev/ram0 rw quiet " \
- "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
- "run boot-hook\\;" \
- "bootm\0" \
-"root-on-initrd-debug="\
- "setenv bootcmd "\
- "version\\;" \
- "echo\\;" \
- "bootp\\;" \
- "setenv bootargs root=/dev/ram0 rw debug " \
- "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
- "run debug-hook\\;" \
- "run boot-hook\\;" \
- "bootm\0" \
-"root-on-nfs="\
- "setenv bootcmd "\
- "version\\;" \
- "echo\\;" \
- "bootp\\;" \
- "setenv bootargs root=/dev/nfs rw quiet " \
- "nfsroot=\\${serverip}:\\${rootpath} " \
- "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
- "run boot-hook\\;" \
- "bootm\0" \
-"root-on-nfs-debug="\
- "setenv bootcmd "\
- "version\\;" \
- "echo\\;" \
- "bootp\\;" \
- "setenv bootargs root=/dev/nfs rw debug " \
- "nfsroot=\\${serverip}:\\${rootpath} " \
- "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
- "run debug-hook\\;" \
- "run boot-hook\\;" \
- "bootm\0" \
-"debug-checkout="\
- "setenv checkhostname;" \
- "setenv ethaddr 00:09:70:00:00:01;" \
- "bootp;" \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} debug " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
- "run debug-hook;" \
- "run boot-hook;" \
- "bootm\0" \
-"debug-hook="\
- "echo ipaddr ${ipaddr};" \
- "echo serverip ${serverip};" \
- "echo gatewayip ${gatewayip};" \
- "echo netmask ${netmask};" \
- "echo hostname ${hostname}\0" \
-"ana=run adc ; run dac\0" \
-"adc=run adc-12 ; run adc-34\0" \
-"adc-12=echo ### ADC-12 ; i2c md e 81 e\0" \
-"adc-34=echo ### ADC-34 ; i2c md f 81 e\0" \
-"dac=echo ### DAC ; i2c md 11 81 5\0" \
-"boot-hook=echo\0"
-
-/* What should the console's baud rate be? */
-#define CONFIG_BAUDRATE 9600
-
-/* Ethernet MAC address */
-#define CONFIG_ETHADDR 00:09:70:00:00:00
-
-/* The default Ethernet MAC address can be overwritten just once */
-#ifdef CONFIG_ETHADDR
-#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
-#endif
-
-/*
- * Define this to do some miscellaneous board-specific initialization.
- */
-#define CONFIG_MISC_INIT_R
-
-/* Set to a positive value to delay for running BOOTCOMMAND */
-#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
-
-/* Be selective on what keys can delay or stop the autoboot process
- * To stop use: " "
- */
-#define CONFIG_AUTOBOOT_KEYED
-#define CONFIG_AUTOBOOT_PROMPT "Autobooting...\n"
-#define CONFIG_AUTOBOOT_STOP_STR " "
-#undef CONFIG_AUTOBOOT_DELAY_STR
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-#define DEBUG_BOOTKEYS 0
-
-/* Define a command string that is automatically executed when no character
- * is read on the console interface withing "Boot Delay" after reset.
- */
-#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */
-#define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */
-
-#ifdef CONFIG_BOOT_ROOT_INITRD
-#define CONFIG_BOOTCOMMAND \
- "version;" \
- "echo;" \
- "bootp;" \
- "setenv bootargs root=/dev/ram0 rw quiet " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
- "run boot-hook;" \
- "bootm"
-#endif /* CONFIG_BOOT_ROOT_INITRD */
-
-#ifdef CONFIG_BOOT_ROOT_NFS
-#define CONFIG_BOOTCOMMAND \
- "version;" \
- "echo;" \
- "bootp;" \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} quiet " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
- "run boot-hook;" \
- "bootm"
-#endif /* CONFIG_BOOT_ROOT_NFS */
-
-#define CONFIG_BOOTP_RANDOM_DELAY /* Randomize the BOOTP retry delay */
-#define CONFIG_LIB_RAND
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-
-
-/* undef this to save memory */
-#define CONFIG_SYS_LONGHELP
-
-/* Monitor Command Prompt */
-
-#undef CONFIG_SYS_HUSH_PARSER
-#ifdef CONFIG_SYS_HUSH_PARSER
-#endif
-
-/* When CONFIG_TIMESTAMP is selected, the timestamp (date and time)
- * of an image is printed by image commands like bootm or iminfo.
- */
-#define CONFIG_TIMESTAMP
-
-/* If this variable is defined, an environment variable named "ver"
- * is created by U-Boot showing the U-Boot version.
- */
-#define CONFIG_VERSION_VARIABLE
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_PING
-
-#undef CONFIG_CMD_KGDB
-
-#ifdef CONFIG_ETHER_ON_FCC
-#define CONFIG_CMD_MII
-#endif
-
-
-/* Where do the internal registers live? */
-#define CONFIG_SYS_IMMR 0xF0000000
-
-#undef CONFIG_WATCHDOG /* disable the watchdog */
-
-/*****************************************************************************
- *
- * You should not have to modify any of the following settings
- *
- *****************************************************************************/
-
-#define CONFIG_SACSng 1 /* munged for the SACSng */
-#define CONFIG_CPM2 1 /* Has a CPM2 */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_BOOTM_HEADER_QUIET 1 /* Suppress the image header dump */
- /* in the bootm command. */
-#define CONFIG_SYS_BOOTM_PROGESS_QUIET 1 /* Suppress the progress displays, */
- /* "## <message>" from the bootm cmd */
-#define CONFIG_SYS_BOOTP_CHECK_HOSTNAME 1 /* If checkhostname environment is */
- /* defined, then the hostname param */
- /* validated against checkhostname. */
-#define CONFIG_SYS_BOOTP_RETRY_COUNT 0x40000000 /* # of timeouts before giving up */
-#define CONFIG_SYS_BOOTP_SHORT_RANDOM_DELAY 1 /* Use a short random delay value */
- /* (limited to maximum of 1024 msec) */
-#define CONFIG_SYS_CHK_FOR_ABORT_AT_LEAST_ONCE 1
- /* Check for abort key presses */
- /* at least once in dependent of the */
- /* CONFIG_BOOTDELAY value. */
-#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* Don't print console @ startup */
-#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1 /* Echo the inverted Ethernet link */
- /* state to the fault LED. */
-#define CONFIG_SYS_FAULT_MII_ADDR 0x02 /* MII addr of the PHY to check for */
- /* the Ethernet link state. */
-#define CONFIG_SYS_STATUS_FLASH_UNTIL_TFTP_OK 1 /* Keeping the status LED flashing */
- /* until the TFTP is successful. */
-#define CONFIG_SYS_STATUS_OFF_AFTER_NETBOOT 1 /* After a successful netboot, */
- /* turn off the STATUS LEDs. */
-#define CONFIG_SYS_TFTP_BLINK_STATUS_ON_DATA_IN 1 /* Blink status LED based on */
- /* incoming data. */
-#define CONFIG_SYS_TFTP_BLOCKS_PER_HASH 100 /* For every XX blocks, output a '#' */
- /* to signify that tftp is moving. */
-#define CONFIG_SYS_TFTP_HASHES_PER_FLASH 200 /* For every '#' hashes, */
- /* flash the status LED. */
-#define CONFIG_SYS_TFTP_HASHES_PER_LINE 65 /* Only output XX '#'s per line */
- /* during the tftp file transfer. */
-#define CONFIG_SYS_TFTP_PROGESS_QUIET 1 /* Suppress the progress displays */
- /* '#'s from the tftp command. */
-#define CONFIG_SYS_TFTP_STATUS_QUIET 1 /* Suppress the status displays */
- /* issued during the tftp command. */
-#define CONFIG_SYS_TFTP_TIMEOUT_COUNT 5 /* How many timeouts TFTP will allow */
- /* before it gives up. */
-
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
-
-#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
-
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
-
-#define CONFIG_SYS_ALT_MEMTEST /* Select full-featured memory test */
-#define CONFIG_SYS_MEMTEST_START 0x2000 /* memtest works from the end of */
- /* the exception vector table */
- /* to the end of the DRAM */
- /* less monitor and malloc area */
-#define CONFIG_SYS_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */
-#define CONFIG_SYS_MEM_END_USAGE ( CONFIG_SYS_MONITOR_LEN \
- + CONFIG_SYS_MALLOC_LEN \
- + CONFIG_ENV_SECT_SIZE \
- + CONFIG_SYS_STACK_USAGE )
-
-#define CONFIG_SYS_MEMTEST_END ( CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 \
- - CONFIG_SYS_MEM_END_USAGE )
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
-#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM0_BASE
-#define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM0_SIZE
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
- */
-#if defined(CONFIG_SYS_SBC_BOOT_LOW)
-# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
-#else
-# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (0)
-#endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */
-
-/* get the HRCW ISB field from CONFIG_SYS_IMMR */
-#define CONFIG_SYS_SBC_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) | \
- ((CONFIG_SYS_IMMR & 0x01000000) >> 7) | \
- ((CONFIG_SYS_IMMR & 0x00100000) >> 4) )
-
-#define CONFIG_SYS_HRCW_MASTER ( HRCW_BPS10 | \
- HRCW_DPPC11 | \
- CONFIG_SYS_SBC_HRCW_IMMR | \
- HRCW_MMR00 | \
- HRCW_LBPC11 | \
- HRCW_APPC10 | \
- HRCW_CS10PC00 | \
- (CONFIG_SYS_SBC_MODCK_H & HRCW_MODCK_H1111) | \
- CONFIG_SYS_SBC_HRCW_BOOT_FLAGS )
-
-/* no slaves */
-#define CONFIG_SYS_HRCW_SLAVE1 0
-#define CONFIG_SYS_HRCW_SLAVE2 0
-#define CONFIG_SYS_HRCW_SLAVE3 0
-#define CONFIG_SYS_HRCW_SLAVE4 0
-#define CONFIG_SYS_HRCW_SLAVE5 0
-#define CONFIG_SYS_HRCW_SLAVE6 0
-#define CONFIG_SYS_HRCW_SLAVE7 0
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent.
- */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH0_BASE
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-# define CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-
-#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
-#undef CONFIG_SYS_FLASH_PROTECTION /* use hardware protection */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT (64+4) /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
-
-#ifndef CONFIG_SYS_RAMBOOT
-# define CONFIG_ENV_IS_IN_FLASH 1
-
-# ifdef CONFIG_ENV_IN_OWN_SECT
-# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-# define CONFIG_ENV_SECT_SIZE 0x10000
-# else
-# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE)
-# define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
-# define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */
-# endif /* CONFIG_ENV_IN_OWN_SECT */
-
-#else
-# define CONFIG_ENV_IS_IN_NVRAM 1
-# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
-# define CONFIG_ENV_SIZE 0x200
-#endif /* CONFIG_SYS_RAMBOOT */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers 2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-#define CONFIG_SYS_HID0_INIT (HID0_ICE |\
- HID0_DCE |\
- HID0_ICFI |\
- HID0_DCI |\
- HID0_IFEM |\
- HID0_ABE)
-
-#define CONFIG_SYS_HID0_FINAL (HID0_ICE |\
- HID0_IFEM |\
- HID0_ABE |\
- HID0_EMCP)
-#define CONFIG_SYS_HID2 0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RMR 0
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration 4-25
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_BCR (BCR_ETM)
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 4-31
- *-----------------------------------------------------------------------
- */
-
-#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC11 |\
- SIUMCR_L2CPC00 |\
- SIUMCR_APPC10 |\
- SIUMCR_MMR00)
-
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC |\
- SYPCR_BMT |\
- SYPCR_PBME |\
- SYPCR_LBME |\
- SYPCR_SWRI |\
- SYPCR_SWP |\
- SYPCR_SWE)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC |\
- SYPCR_BMT |\
- SYPCR_PBME |\
- SYPCR_LBME |\
- SYPCR_SWRI |\
- SYPCR_SWP)
-#endif /* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control 4-40
- *-----------------------------------------------------------------------
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- */
-#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC |\
- TMCNTSC_ALR |\
- TMCNTSC_TCF |\
- TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CONFIG_SYS_PISCR (PISCR_PS |\
- PISCR_PTF |\
- PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control 9-8
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_SCCR 0
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration 13-7
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RCCR 0
-
-/*
- * Initialize Memory Controller:
- *
- * Bank Bus Machine PortSz Device
- * ---- --- ------- ------ ------
- * 0 60x GPCM 16 bit FLASH (primary flash - 2MB)
- * 1 60x GPCM -- bit (Unused)
- * 2 60x SDRAM 64 bit SDRAM (DIMM)
- * 3 60x SDRAM 64 bit SDRAM (DIMM)
- * 4 60x GPCM -- bit (Unused)
- * 5 60x GPCM -- bit (Unused)
- * 6 60x GPCM 16 bit FLASH (secondary flash - 2MB)
- */
-
-/*-----------------------------------------------------------------------
- * BR0,BR1 - Base Register
- * Ref: Section 10.3.1 on page 10-14
- * OR0,OR1 - Option Register
- * Ref: Section 10.3.2 on page 10-18
- *-----------------------------------------------------------------------
- */
-
-/* Bank 0 - Primary FLASH
- */
-
-/* BR0 is configured as follows:
- *
- * - Base address of 0x40000000
- * - 16 bit port size
- * - Data errors checking is disabled
- * - Read and write access
- * - GPCM 60x bus
- * - Access are handled by the memory controller according to MSEL
- * - Not used for atomic operations
- * - No data pipelining is done
- * - Valid
- */
-#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\
- BRx_PS_16 |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-/* OR0 is configured as follows:
- *
- * - 4 MB
- * - *BCTL0 is asserted upon access to the current memory bank
- * - *CW / *WE are negated a quarter of a clock earlier
- * - *CS is output@the same time as the address lines
- * - Uses a clock cycle length of 5
- * - *PSDVAL is generated internally by the memory controller
- * unless *GTA is asserted earlier externally.
- * - Relaxed timing is generated by the GPCM for accesses
- * initiated to this memory region.
- * - One idle clock is inserted between a read access from the
- * current bank and the next access.
- */
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE) |\
- ORxG_CSNT |\
- ORxG_ACS_DIV1 |\
- ORxG_SCY_5_CLK |\
- ORxG_TRLX |\
- ORxG_EHTR)
-
-/*-----------------------------------------------------------------------
- * BR2,BR3 - Base Register
- * Ref: Section 10.3.1 on page 10-14
- * OR2,OR3 - Option Register
- * Ref: Section 10.3.2 on page 10-16
- *-----------------------------------------------------------------------
- */
-
-/* Bank 2,3 - SDRAM DIMM
- */
-
-/* The BR2 is configured as follows:
- *
- * - Base address of 0x00000000
- * - 64 bit port size (60x bus only)
- * - Data errors checking is disabled
- * - Read and write access
- * - SDRAM 60x bus
- * - Access are handled by the memory controller according to MSEL
- * - Not used for atomic operations
- * - No data pipelining is done
- * - Valid
- */
-#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
- BRx_PS_64 |\
- BRx_MS_SDRAM_P |\
- BRx_V)
-
-#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
- BRx_PS_64 |\
- BRx_MS_SDRAM_P |\
- BRx_V)
-
-/* With a 64 MB DIMM, the OR2 is configured as follows:
- *
- * - 64 MB
- * - 4 internal banks per device
- * - Row start address bit is A8 with PSDMR[PBI] = 0
- * - 12 row address lines
- * - Back-to-back page mode
- * - Internal bank interleaving within save device enabled
- */
-#if (CONFIG_SYS_SDRAM0_SIZE == 64)
-#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\
- ORxS_BPD_4 |\
- ORxS_ROWST_PBI0_A8 |\
- ORxS_NUMR_12)
-#else
-#error "INVALID SDRAM CONFIGURATION"
-#endif
-
-/*-----------------------------------------------------------------------
- * PSDMR - 60x Bus SDRAM Mode Register
- * Ref: Section 10.3.3 on page 10-21
- *-----------------------------------------------------------------------
- */
-
-/* Address that the DIMM SPD memory lives at.
- */
-#define SDRAM_SPD_ADDR 0x50
-
-#if (CONFIG_SYS_SDRAM0_SIZE == 64)
-/* With a 64 MB DIMM, the PSDMR is configured as follows:
- *
- * - Bank Based Interleaving,
- * - Refresh Enable,
- * - Address Multiplexing where A5 is output on A14 pin
- * (A6 on A15, and so on),
- * - use address pins A14-A16 as bank select,
- * - A9 is output on SDA10 during an ACTIVATE command,
- * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
- * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
- * is 3 clocks,
- * - earliest timing for READ/WRITE command after ACTIVATE command is
- * 2 clocks,
- * - earliest timing for PRECHARGE after last data was read is 1 clock,
- * - earliest timing for PRECHARGE after last data was written is 1 clock,
- * - CAS Latency is 2.
- */
-#define CONFIG_SYS_PSDMR (PSDMR_RFEN |\
- PSDMR_SDAM_A14_IS_A5 |\
- PSDMR_BSMA_A14_A16 |\
- PSDMR_SDA10_PBI0_A9 |\
- PSDMR_RFRC_7_CLK |\
- PSDMR_PRETOACT_3W |\
- PSDMR_ACTTORW_2W |\
- PSDMR_LDOTOPRE_1C |\
- PSDMR_WRC_1C |\
- PSDMR_CL_2)
-#else
-#error "INVALID SDRAM CONFIGURATION"
-#endif
-
-/*
- * Shoot for approximately 1MHz on the prescaler.
- */
-#if (CONFIG_8260_CLKIN >= (60 * 1000 * 1000))
-#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV64
-#elif (CONFIG_8260_CLKIN >= (30 * 1000 * 1000))
-#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32
-#else
-#warning "Unconfigured bus clock freq: check CONFIG_SYS_MPTPR and CONFIG_SYS_PSRT are OK"
-#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32
-#endif
-#define CONFIG_SYS_PSRT 14
-
-
-/*-----------------------------------------------------------------------
- * BR6 - Base Register
- * Ref: Section 10.3.1 on page 10-14
- * OR6 - Option Register
- * Ref: Section 10.3.2 on page 10-18
- *-----------------------------------------------------------------------
- */
-
-/* Bank 6 - Secondary FLASH
- *
- * The secondary FLASH is connected to *CS6
- */
-#if (defined(CONFIG_SYS_FLASH1_BASE) && defined(CONFIG_SYS_FLASH1_SIZE))
-
-/* BR6 is configured as follows:
- *
- * - Base address of 0x60000000
- * - 16 bit port size
- * - Data errors checking is disabled
- * - Read and write access
- * - GPCM 60x bus
- * - Access are handled by the memory controller according to MSEL
- * - Not used for atomic operations
- * - No data pipelining is done
- * - Valid
- */
-# define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_FLASH1_BASE & BRx_BA_MSK) |\
- BRx_PS_16 |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-/* OR6 is configured as follows:
- *
- * - 2 MB
- * - *BCTL0 is asserted upon access to the current memory bank
- * - *CW / *WE are negated a quarter of a clock earlier
- * - *CS is output at the same time as the address lines
- * - Uses a clock cycle length of 5
- * - *PSDVAL is generated internally by the memory controller
- * unless *GTA is asserted earlier externally.
- * - Relaxed timing is generated by the GPCM for accesses
- * initiated to this memory region.
- * - One idle clock is inserted between a read access from the
- * current bank and the next access.
- */
-# define CONFIG_SYS_OR6_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH1_SIZE) |\
- ORxG_CSNT |\
- ORxG_ACS_DIV1 |\
- ORxG_SCY_5_CLK |\
- ORxG_TRLX |\
- ORxG_EHTR)
-#endif /* (defined(CONFIG_SYS_FLASH1_BASE) && defined(CONFIG_SYS_FLASH1_SIZE)) */
-
-#endif /* __CONFIG_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [U-Boot] [PATCH 15/26] mpc8260: remove ppmc8260 board support
2014-12-15 14:26 [U-Boot] [PATCH 0/26] Start removing non-generic boards Masahiro Yamada
` (13 preceding siblings ...)
2014-12-15 14:26 ` [U-Boot] [PATCH 14/26] mpc8260: remove sacsng " Masahiro Yamada
@ 2014-12-15 14:26 ` Masahiro Yamada
2015-01-05 18:21 ` Tom Rini
2014-12-15 14:26 ` [U-Boot] [PATCH 16/26] mpc8260: remove ep8260 " Masahiro Yamada
` (12 subsequent siblings)
27 siblings, 1 reply; 55+ messages in thread
From: Masahiro Yamada @ 2014-12-15 14:26 UTC (permalink / raw)
To: u-boot
This board is still a non-generic board.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Brad Kemp <Brad.Kemp@seranoa.com>
---
arch/powerpc/cpu/mpc8260/Kconfig | 4 -
board/ppmc8260/Kconfig | 9 -
board/ppmc8260/MAINTAINERS | 6 -
board/ppmc8260/Makefile | 8 -
board/ppmc8260/ppmc8260.c | 291 ------------
configs/ppmc8260_defconfig | 3 -
doc/README.scrapyard | 1 +
include/configs/ppmc8260.h | 986 ---------------------------------------
8 files changed, 1 insertion(+), 1307 deletions(-)
delete mode 100644 board/ppmc8260/Kconfig
delete mode 100644 board/ppmc8260/MAINTAINERS
delete mode 100644 board/ppmc8260/Makefile
delete mode 100644 board/ppmc8260/ppmc8260.c
delete mode 100644 configs/ppmc8260_defconfig
delete mode 100644 include/configs/ppmc8260.h
diff --git a/arch/powerpc/cpu/mpc8260/Kconfig b/arch/powerpc/cpu/mpc8260/Kconfig
index bdaf126..d4132a0 100644
--- a/arch/powerpc/cpu/mpc8260/Kconfig
+++ b/arch/powerpc/cpu/mpc8260/Kconfig
@@ -37,9 +37,6 @@ config TARGET_PM826
config TARGET_PM828
bool "Support PM828"
-config TARGET_PPMC8260
- bool "Support ppmc8260"
-
config TARGET_MPC8266ADS
bool "Support MPC8266ADS"
@@ -64,6 +61,5 @@ source "board/keymile/km82xx/Kconfig"
source "board/muas3001/Kconfig"
source "board/pm826/Kconfig"
source "board/pm828/Kconfig"
-source "board/ppmc8260/Kconfig"
endmenu
diff --git a/board/ppmc8260/Kconfig b/board/ppmc8260/Kconfig
deleted file mode 100644
index 1a6dcd3..0000000
--- a/board/ppmc8260/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_PPMC8260
-
-config SYS_BOARD
- default "ppmc8260"
-
-config SYS_CONFIG_NAME
- default "ppmc8260"
-
-endif
diff --git a/board/ppmc8260/MAINTAINERS b/board/ppmc8260/MAINTAINERS
deleted file mode 100644
index 8b896af..0000000
--- a/board/ppmc8260/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-PPMC8260 BOARD
-#M: Brad Kemp <Brad.Kemp@seranoa.com>
-S: Orphan (since 2014-04)
-F: board/ppmc8260/
-F: include/configs/ppmc8260.h
-F: configs/ppmc8260_defconfig
diff --git a/board/ppmc8260/Makefile b/board/ppmc8260/Makefile
deleted file mode 100644
index 3072fb4..0000000
--- a/board/ppmc8260/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := ppmc8260.o
diff --git a/board/ppmc8260/ppmc8260.c b/board/ppmc8260/ppmc8260.c
deleted file mode 100644
index f0f29b2..0000000
--- a/board/ppmc8260/ppmc8260.c
+++ /dev/null
@@ -1,291 +0,0 @@
-/*
- * (C) Copyright 2000
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2001
- * Advent Networks, Inc. <http://www.adventnetworks.com>
- * Jay Monkman <jtm@smoothsmoothie.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc8260.h>
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
-
- /* Port A configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PA31 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 *ATMTXEN */
- /* PA30 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTCA */
- /* PA29 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTSOC */
- /* PA28 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 *ATMRXEN */
- /* PA27 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRSOC */
- /* PA26 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRCA */
- /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[0] */
- /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[1] */
- /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[2] */
- /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[3] */
- /* PA21 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[4] */
- /* PA20 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[5] */
- /* PA19 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[6] */
- /* PA18 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[7] */
- /* PA17 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
- /* PA16 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
- /* PA15 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
- /* PA14 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
- /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
- /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
- /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
- /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
- /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
- /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
- /* PA7 */ { 1, 0, 0, 1, 0, 0 }, /* TDM_A1:L1TSYNC */
- /* PA6 */ { 1, 0, 0, 1, 0, 0 }, /* TDN_A1:L1RSYNC */
- /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */
- /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */
- /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */
- /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */
- /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */
- /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */
- },
-
- /* Port B configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
- /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
- /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
- /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
- /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
- /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
- /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
- /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
- /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
- /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
- /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
- /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
- /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
- /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
- /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */
- /* PB16 */ { 1, 0, 0, 0, 0, 0 }, /* TDM_A1:L1CLK0 */
- /* PB15 */ { 1, 0, 0, 1, 0, 1 }, /* /FETHRST */
- /* PB14 */ { 1, 0, 0, 1, 0, 0 }, /* FETHDIS */
- /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */
- /* PB12 */ { 1, 0, 0, 1, 0, 0 }, /* TDM_B1:L1CLK0 */
- /* PB11 */ { 1, 0, 0, 1, 0, 0 }, /* TDM_D1:L1TXD */
- /* PB10 */ { 1, 0, 0, 1, 0, 0 }, /* TDM_D1:L1RXD */
- /* PB9 */ { 1, 0, 0, 1, 0, 0 }, /* TDM_D1:L1TSYNC */
- /* PB8 */ { 1, 0, 0, 1, 0, 0 }, /* TDM_D1:L1RSYNC */
- /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
- /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */
- /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */
- /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */
- /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- },
-
- /* Port C */
- { /* conf ppar psor pdir podr pdat */
- /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
- /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
- /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
- /* PC28 */ { 1, 1, 0, 0, 0, 0 }, /* CLK4 */
- /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
- /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
- /* PC25 */ { 1, 1, 0, 0, 0, 0 }, /* CLK7 */
- /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
- /* PC23 */ { 1, 0, 0, 1, 0, 0 }, /* ATMTFCLK */
- /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* PC22 */
- /* PC21 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
- /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
- /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */
- /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */
- /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
- /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */
- /* PC15 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1:TxAddr[0] */
- /* PC14 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1:RxAddr[0] */
- /* PC13 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1:TxAddr[1] */
- /* PC12 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1:RxAddr[1] */
- /* PC11 */ { 1, 1, 0, 1, 0, 0 }, /* TDM_D1:L1CLK0 */
- /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MDC */
- /* PC9 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MDIO */
- /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */
- /* PC7 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1:TxAddr[2]*/
- /* PC6 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1:RxAddr[2] */
- /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
- /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
- /* PC3 */ { 1, 0, 0, 1, 0, 0 }, /* IDMA2:DACK */
- /* PC2 */ { 1, 0, 0, 1, 0, 0 }, /* IDMA2:DONE */
- /* PC1 */ { 1, 0, 0, 1, 0, 0 }, /* IDMA2:DREQ */
- /* PC0 */ { 1, 0, 0, 1, 0, 0 }, /* IDMA1:DREQ */
- },
-
- /* Port D */
- { /* conf ppar psor pdir podr pdat */
- /* PD31 */ { 0, 0, 0, 0, 0, 0 }, /* PD31 */
- /* PD30 */ { 0, 0, 0, 0, 0, 0 }, /* PD30 */
- /* PD29 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1:RxAddr[3] */
- /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */
- /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */
- /* PD26 */ { 1, 0, 0, 1, 0, 0 }, /* TDM_C1:L1RSYNC */
- /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */
- /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */
- /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */
- /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */
- /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */
- /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */
- /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */
- /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */
- /* PD17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
- /* PD16 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
- /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
- /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
- /* PD13 */ { 1, 0, 0, 0, 0, 0 }, /* TDM_B1:L1TXD */
- /* PD12 */ { 1, 0, 0, 0, 0, 0 }, /* TDM_B1:L1RXD */
- /* PD11 */ { 1, 0, 0, 0, 0, 0 }, /* TDM_B1:L1TSYNC */
- /* PD10 */ { 1, 0, 0, 0, 0, 0 }, /* TDM_B1:L1RSYNC*/
- /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1:TXD */
- /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1:RXD */
- /* PD7 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1:SMSYN */
- /* PD6 */ { 1, 0, 0, 1, 0, 0 }, /* IDMA1:DACK */
- /* PD5 */ { 1, 0, 0, 1, 0, 0 }, /* IDMA1:DONE */
- /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */
- /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- }
-};
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check Board Identity:
- */
-
-int checkboard (void)
-{
- puts ("Board: Wind River PPMC8260\n");
- return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8260_t *memctl = &immap->im_memctl;
- volatile uchar c = 0xff;
- volatile uchar *ramaddr0 = (uchar *) (CONFIG_SYS_SDRAM0_BASE);
- volatile uchar *ramaddr1 = (uchar *) (CONFIG_SYS_SDRAM1_BASE);
- ulong psdmr = CONFIG_SYS_PSDMR;
- volatile uchar *ramaddr2 = (uchar *) (CONFIG_SYS_SDRAM2_BASE);
- ulong lsdmr = CONFIG_SYS_LSDMR;
- int i;
-
- /*
- * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
- *
- * "At system reset, initialization software must set up the
- * programmable parameters in the memory controller banks registers
- * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
- * system software should execute the following initialization sequence
- * for each SDRAM device.
- *
- * 1. Issue a PRECHARGE-ALL-BANKS command
- * 2. Issue eight CBR REFRESH commands
- * 3. Issue a MODE-SET command to initialize the mode register
- *
- * The initial commands are executed by setting P/LSDMR[OP] and
- * accessing the SDRAM with a single-byte transaction."
- *
- * The appropriate BRx/ORx registers have already been set when we
- * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
- */
-
- memctl->memc_psrt = CONFIG_SYS_PSRT;
- memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-
-#ifndef CONFIG_SYS_RAMBOOT
- memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
- *ramaddr0++ = c;
- *ramaddr1++ = c;
-
- memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
- for (i = 0; i < 8; i++) {
- *ramaddr0++ = c;
- *ramaddr1++ = c;
- }
-
- memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
- ramaddr0 = (uchar *) (CONFIG_SYS_SDRAM0_BASE + 0x110);
- ramaddr1 = (uchar *) (CONFIG_SYS_SDRAM1_BASE + 0x110);
- *ramaddr0 = c;
- *ramaddr1 = c;
-
- memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
- *ramaddr0 = c;
- *ramaddr1 = c;
-
- memctl->memc_lsdmr = lsdmr | PSDMR_OP_PREA;
- *ramaddr2++ = c;
-
- memctl->memc_lsdmr = lsdmr | PSDMR_OP_CBRR;
- for (i = 0; i < 8; i++) {
- *ramaddr2++ = c;
- }
-
- memctl->memc_lsdmr = lsdmr | PSDMR_OP_MRW;
- *ramaddr2++ = c;
-
- memctl->memc_lsdmr = lsdmr | PSDMR_OP_NORM | PSDMR_RFEN;
- *ramaddr2 = c;
-#endif
-
- /* return total ram size */
- return ((CONFIG_SYS_SDRAM0_SIZE + CONFIG_SYS_SDRAM1_SIZE) * 1024 * 1024);
-}
-
-#ifdef CONFIG_MISC_INIT_R
-/* ------------------------------------------------------------------------- */
-int misc_init_r (void)
-{
-#ifdef CONFIG_SYS_LED_BASE
- uchar ds = *(unsigned char *) (CONFIG_SYS_LED_BASE + 1);
- uchar ss;
- uchar tmp[64];
- int res;
-
- if ((ds != 0) && (ds != 0xff)) {
- res = getenv_f("ethaddr", (char *)tmp, sizeof (tmp));
- if (res > 0) {
- ss = ((ds >> 4) & 0x0f);
- ss += ss < 0x0a ? '0' : ('a' - 10);
- tmp[15] = ss;
-
- ss = (ds & 0x0f);
- ss += ss < 0x0a ? '0' : ('a' - 10);
- tmp[16] = ss;
-
- tmp[17] = '\0';
- setenv ("ethaddr", (char *)tmp);
- /* set the led to show the address */
- *((unsigned char *) (CONFIG_SYS_LED_BASE + 1)) = ds;
- }
- }
-#endif /* CONFIG_SYS_LED_BASE */
- return (0);
-}
-#endif /* CONFIG_MISC_INIT_R */
diff --git a/configs/ppmc8260_defconfig b/configs/ppmc8260_defconfig
deleted file mode 100644
index e8eb4f7..0000000
--- a/configs/ppmc8260_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_PPMC8260=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 5b71bc9..0845651 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+ppmc8260 powerpc mpc8260 - - Brad Kemp <Brad.Kemp@seranoa.com>
sacsng powerpc mpc8260 - - Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
cogent_mpc8260 powerpc mpc8260 - - Murray Jensen <Murray.Jensen@csiro.au>
cogent_8xx powerpc mpc8xx - - Murray Jensen <Murray.Jensen@csiro.au>
diff --git a/include/configs/ppmc8260.h b/include/configs/ppmc8260.h
deleted file mode 100644
index 5dcd9cc..0000000
--- a/include/configs/ppmc8260.h
+++ /dev/null
@@ -1,986 +0,0 @@
-/*
- * (C) Copyright 2000
- * Murray Jensen <Murray.Jensen@cmst.csiro.au>
- *
- * (C) Copyright 2000
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2001
- * Advent Networks, Inc. <http://www.adventnetworks.com>
- * Jay Monkman <jtm@smoothsmoothie.com>
- *
- * Configuation settings for the WindRiver PPMC8260 board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_SYS_TEXT_BASE 0xfe000000
-
-/*****************************************************************************
- *
- * These settings must match the way _your_ board is set up
- *
- *****************************************************************************/
-
-/* What is the oscillator's (UX2) frequency in Hz? */
-#define CONFIG_8260_CLKIN (66 * 1000 * 1000)
-
-/*-----------------------------------------------------------------------
- * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
- *-----------------------------------------------------------------------
- * What should MODCK_H be? It is dependent on the oscillator
- * frequency, MODCK[1-3], and desired CPM and core frequencies.
- * Here are some example values (all frequencies are in MHz):
- *
- * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8
- * ------- ---------- --- --- ---- ----- ----- -----
- * 0x2 0x2 33 133 133 Close Open Close
- * 0x2 0x3 33 133 166 Close Open Open
- * 0x2 0x4 33 133 200 Open Close Close
- * 0x2 0x5 33 133 233 Open Close Open
- * 0x2 0x6 33 133 266 Open Open Close
- *
- * 0x5 0x5 66 133 133 Open Close Open
- * 0x5 0x6 66 133 166 Open Open Close
- * 0x5 0x7 66 133 200 Open Open Open
- * 0x6 0x0 66 133 233 Close Close Close
- * 0x6 0x1 66 133 266 Close Close Open
- * 0x6 0x2 66 133 300 Close Open Close
- */
-#define CONFIG_SYS_PPMC_MODCK_H 0x05
-
-/* Define this if you want to boot from 0x00000100. If you don't define
- * this, you will need to program the bootloader to 0xfff00000, and
- * get the hardware reset config words at 0xfe000000. The simplest
- * way to do that is to program the bootloader at both addresses.
- * It is suggested that you just let U-Boot live at 0x00000000.
- */
-#define CONFIG_SYS_PPMC_BOOT_LOW 1
-
-/* What should the base address of the main FLASH be and how big is
- * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/ppmc8260/config.mk
- * The main FLASH is whichever is connected to *CS0. U-Boot expects
- * this to be the SIMM.
- */
-#define CONFIG_SYS_FLASH0_BASE 0xFE000000
-#define CONFIG_SYS_FLASH0_SIZE 16
-
-/* What should be the base address of the first SDRAM DIMM and how big is
- * it (in Mbytes)?
-*/
-#define CONFIG_SYS_SDRAM0_BASE 0x00000000
-#define CONFIG_SYS_SDRAM0_SIZE 128
-
-/* What should be the base address of the second SDRAM DIMM and how big is
- * it (in Mbytes)?
-*/
-#define CONFIG_SYS_SDRAM1_BASE 0x08000000
-#define CONFIG_SYS_SDRAM1_SIZE 128
-
-/* What should be the base address of the on board SDRAM and how big is
- * it (in Mbytes)?
-*/
-#define CONFIG_SYS_SDRAM2_BASE 0x38000000
-#define CONFIG_SYS_SDRAM2_SIZE 16
-
-/* What should be the base address of the MAILBOX and how big is it
- * (in Bytes)
- * The eeprom lives at CONFIG_SYS_MAILBOX_BASE + 0x80000000
- */
-#define CONFIG_SYS_MAILBOX_BASE 0x32000000
-#define CONFIG_SYS_MAILBOX_SIZE 8192
-
-/* What is the base address of the I/O select lines and how big is it
- * (In Mbytes)?
- */
-
-#define CONFIG_SYS_IOSELECT_BASE 0xE0000000
-#define CONFIG_SYS_IOSELECT_SIZE 32
-
-
-/* What should be the base address of the LEDs and switch S0?
- * If you don't want them enabled, don't define this.
- */
-#define CONFIG_SYS_LED_BASE 0xF1000000
-
-/*
- * PPMC8260 with 256 16 MB DIMM:
- *
- * 0x0000 0000 Exception Vector code, 8k
- * :
- * 0x0000 1FFF
- * 0x0000 2000 Free for Application Use
- * :
- * :
- *
- * :
- * :
- * 0x0FF5 FF30 Monitor Stack (Growing downward)
- * Monitor Stack Buffer (0x80)
- * 0x0FF5 FFB0 Board Info Data
- * 0x0FF6 0000 Malloc Arena
- * : CONFIG_ENV_SECT_SIZE, 256k
- * : CONFIG_SYS_MALLOC_LEN, 128k
- * 0x0FFC 0000 RAM Copy of Monitor Code
- * : CONFIG_SYS_MONITOR_LEN, 256k
- * 0x0FFF FFFF [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1
- */
-
-
-/*
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * if CONFIG_CONS_NONE is defined, then the serial console routines must
- * defined elsewhere.
- * The console can be on SMC1 or SMC2
- */
-#define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */
-#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
-#undef CONFIG_CONS_NONE /* define if console on neither */
-#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
-
-/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
- */
-
-#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */
-#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */
-#undef CONFIG_ETHER_NONE /* define if ethernet on neither */
-#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
-#define CONFIG_MII /* MII PHY management */
-#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
-/*
- * Port pins used for bit-banged MII communictions (if applicable).
- */
-#define MDIO_PORT 2 /* Port C */
-#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
- (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
-#define MDC_DECLARE MDIO_DECLARE
-
-#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
-#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
-#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
-
-#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
- else iop->pdat &= ~0x00400000
-
-#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
- else iop->pdat &= ~0x00200000
-
-#define MIIDELAY udelay(1)
-
-
-/* Define this to reserve an entire FLASH sector (256 KB) for
- * environment variables. Otherwise, the environment will be
- * put in the same sector as U-Boot, and changing variables
- * will erase U-Boot temporarily
- */
-#define CONFIG_ENV_IN_OWN_SECT 1
-
-/* Define to allow the user to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-/* What should the console's baud rate be? */
-#define CONFIG_BAUDRATE 9600
-
-/* Ethernet MAC address */
-
-#define CONFIG_ETHADDR 00:a0:1e:90:2b:00
-
-/* Define this to set the last octet of the ethernet address
- * from the DS0-DS7 switch and light the leds with the result
- * The DS0-DS7 switch and the leds are backwards with respect
- * to each other. DS7 is on the board edge side of both the
- * led strip and the DS0-DS7 switch.
- */
-#define CONFIG_MISC_INIT_R
-
-/* Set to a positive value to delay for running BOOTCOMMAND */
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#if 0
-/* Be selective on what keys can delay or stop the autoboot process
- * To stop use: " "
- */
-# define CONFIG_AUTOBOOT_KEYED
-# define CONFIG_AUTOBOOT_PROMPT \
- "Autobooting in %d seconds, press \" \" to stop\n", bootdelay
-# define CONFIG_AUTOBOOT_STOP_STR " "
-# undef CONFIG_AUTOBOOT_DELAY_STR
-# define DEBUG_BOOTKEYS 0
-#endif
-
-/* Define a command string that is automatically executed when no character
- * is read on the console interface withing "Boot Delay" after reset.
- */
-#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */
-#define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */
-
-#ifdef CONFIG_BOOT_ROOT_INITRD
-#define CONFIG_BOOTCOMMAND \
- "version;" \
- "echo;" \
- "bootp;" \
- "setenv bootargs root=/dev/ram0 rw " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
- "bootm"
-#endif /* CONFIG_BOOT_ROOT_INITRD */
-
-#ifdef CONFIG_BOOT_ROOT_NFS
-#define CONFIG_BOOTCOMMAND \
- "version;" \
- "echo;" \
- "bootp;" \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
- "bootm"
-#endif /* CONFIG_BOOT_ROOT_NFS */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_DNS
-
-
-/* undef this to save memory */
-#define CONFIG_SYS_LONGHELP
-
-/* Monitor Command Prompt */
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_MEMTEST
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_IMMAP
-
-#undef CONFIG_CMD_KGDB
-
-
-/* Where do the internal registers live? */
-#define CONFIG_SYS_IMMR 0xf0000000
-
-/*****************************************************************************
- *
- * You should not have to modify any of the following settings
- *
- *****************************************************************************/
-
-#define CONFIG_PPMC8260 1 /* on an Wind River PPMC8260 Board */
-#define CONFIG_CPM2 1 /* Has a CPM2 */
-
-/*
- * Miscellaneous configurable options
- */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
-
-#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
-
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_LOAD_ADDR 0x140000 /* default load address */
-
-#define CONFIG_SYS_MEMTEST_START 0x2000 /* memtest works from the end of */
- /* the exception vector table */
- /* to the end of the DRAM */
- /* less monitor and malloc area */
-#define CONFIG_SYS_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */
-#define CONFIG_SYS_MEM_END_USAGE ( CONFIG_SYS_MONITOR_LEN \
- + CONFIG_SYS_MALLOC_LEN \
- + CONFIG_ENV_SECT_SIZE \
- + CONFIG_SYS_STACK_USAGE )
-
-#define CONFIG_SYS_MEMTEST_END ( CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 \
- - CONFIG_SYS_MEM_END_USAGE )
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
-/*
- * Attention: This is board specific
- * - RX clk is CLK11
- * - TX clk is CLK12
- */
-#define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 |\
- CMXSCR_TS1CS_CLK12)
-
-#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
-/*
- * Attention: this is board-specific
- * - Rx-CLK is CLK13
- * - Tx-CLK is CLK14
- * - Select bus for bd/buffers (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-#define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
-#define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
-#define CONFIG_SYS_CPMFCR_RAMTYPE 0
-#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
-#endif /* CONFIG_ETHER_INDEX */
-
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
-#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM0_BASE
-#define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_SDRAM0_SIZE + CONFIG_SYS_SDRAM1_SIZE)
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
- */
-#if defined(CONFIG_SYS_PPMC_BOOT_LOW)
-# define CONFIG_SYS_PPMC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
-#else
-# define CONFIG_SYS_PPMC_HRCW_BOOT_FLAGS (0)
-#endif /* defined(CONFIG_SYS_PPMC_BOOT_LOW) */
-
-/* get the HRCW ISB field from CONFIG_SYS_IMMR */
-#define CONFIG_SYS_PPMC_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) | \
- ((CONFIG_SYS_IMMR & 0x01000000) >> 7) | \
- ((CONFIG_SYS_IMMR & 0x00100000) >> 4) )
-
-#define CONFIG_SYS_HRCW_MASTER ( HRCW_EBM | \
- HRCW_BPS11 | \
- HRCW_L2CPC10 | \
- HRCW_DPPC00 | \
- CONFIG_SYS_PPMC_HRCW_IMMR | \
- HRCW_MMR00 | \
- HRCW_LBPC00 | \
- HRCW_APPC10 | \
- HRCW_CS10PC00 | \
- (CONFIG_SYS_PPMC_MODCK_H & HRCW_MODCK_H1111) | \
- CONFIG_SYS_PPMC_HRCW_BOOT_FLAGS )
-
-/* no slaves */
-#define CONFIG_SYS_HRCW_SLAVE1 0
-#define CONFIG_SYS_HRCW_SLAVE2 0
-#define CONFIG_SYS_HRCW_SLAVE3 0
-#define CONFIG_SYS_HRCW_SLAVE4 0
-#define CONFIG_SYS_HRCW_SLAVE5 0
-#define CONFIG_SYS_HRCW_SLAVE6 0
-#define CONFIG_SYS_HRCW_SLAVE7 0
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent.
- */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH0_BASE
-
-#ifndef CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE 0x0ff80000
-#endif
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-# define CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 374 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-
-#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
-
-
-#ifndef CONFIG_SYS_RAMBOOT
-
-# define CONFIG_ENV_IS_IN_FLASH 1
-# ifdef CONFIG_ENV_IN_OWN_SECT
-# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
-# define CONFIG_ENV_SECT_SIZE 0x40000
-# else
-# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE)
-# define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
-# define CONFIG_ENV_SECT_SIZE 0x40000 /* see README - env sect real size */
-# endif /* CONFIG_ENV_IN_OWN_SECT */
-
-#else
-# define CONFIG_ENV_IS_IN_FLASH 1
-# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
-#define CONFIG_ENV_SIZE 0x1000
-# define CONFIG_ENV_SECT_SIZE 0x40000
-#endif /* CONFIG_SYS_RAMBOOT */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers 2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-#define CONFIG_SYS_HID0_INIT (HID0_ICE |\
- HID0_DCE |\
- HID0_ICFI |\
- HID0_DCI |\
- HID0_IFEM |\
- HID0_ABE)
-
-#define CONFIG_SYS_HID0_FINAL (HID0_ICE |\
- HID0_IFEM |\
- HID0_ABE |\
- HID0_EMCP)
-#define CONFIG_SYS_HID2 0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RMR 0
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration 4-25
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_BCR (BCR_EBM |\
- 0x30000000)
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 4-31
- * Ref Section 4.3.2.6 page 4-31
- *-----------------------------------------------------------------------
- */
-
-#define CONFIG_SYS_SIUMCR (SIUMCR_ESE |\
- SIUMCR_DPPC00 |\
- SIUMCR_L2CPC10 |\
- SIUMCR_LBPC00 |\
- SIUMCR_APPC10 |\
- SIUMCR_CS10PC00 |\
- SIUMCR_BCTLC00 |\
- SIUMCR_MMR00)
-
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
- */
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC |\
- SYPCR_BMT |\
- SYPCR_PBME |\
- SYPCR_LBME |\
- SYPCR_SWRI |\
- SYPCR_SWP)
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control 4-40
- *-----------------------------------------------------------------------
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- */
-#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC |\
- TMCNTSC_ALR |\
- TMCNTSC_TCF |\
- TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CONFIG_SYS_PISCR (PISCR_PS |\
- PISCR_PTF |\
- PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control 9-8
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_SCCR 0
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration 13-7
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RCCR 0
-
-/*
- * Initialize Memory Controller:
- *
- * Bank Bus Machine PortSz Device
- * ---- --- ------- ------ ------
- * 0 60x GPCM 32 bit FLASH (SIMM - 32MB) *
- * 1 unused
- * 2 60x SDRAM 64 bit SDRAM (DIMM - 128MB)
- * 3 60x SDRAM 64 bit SDRAM (DIMM - 128MB)
- * 4 Local SDRAM 32 bit SDRAM (on board - 16MB)
- * 5 60x GPCM 8 bit Mailbox/EEPROM (8KB)
- * 6 60x GPCM 8 bit FLASH (on board - 2MB) *
- * 7 60x GPCM 8 bit LEDs, switches
- *
- * (*) This configuration requires the PPMC8260 be configured
- * so that *CS0 goes to the FLASH SIMM, and *CS6 goes to
- * the on board FLASH. In other words, JP24 should have
- * pins 1 and 2 jumpered and pins 3 and 4 jumpered.
- *
- */
-
-/*-----------------------------------------------------------------------
- * BR0,BR1 - Base Register
- * Ref: Section 10.3.1 on page 10-14
- * OR0,OR1 - Option Register
- * Ref: Section 10.3.2 on page 10-18
- *-----------------------------------------------------------------------
- */
-
-/* Bank 0,1 - FLASH SIMM
- *
- * This expects the FLASH SIMM to be connected to *CS0
- * It consists of 4 AM29F080B parts.
- *
- * Note: For the 4 MB SIMM, *CS1 is unused.
- */
-
-/* BR0 is configured as follows:
- *
- * - Base address of 0xFE000000
- * - 32 bit port size
- * - Data errors checking is disabled
- * - Read and write access
- * - GPCM 60x bus
- * - Access are handled by the memory controller according to MSEL
- * - Not used for atomic operations
- * - No data pipelining is done
- * - Valid
- */
-#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\
- BRx_PS_32 |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-/* OR0 is configured as follows:
- *
- * - 32 MB
- * - *BCTL0 is asserted upon access to the current memory bank
- * - *CW / *WE are negated a quarter of a clock earlier
- * - *CS is output at the same time as the address lines
- * - Uses a clock cycle length of 5
- * - *PSDVAL is generated internally by the memory controller
- * unless *GTA is asserted earlier externally.
- * - Relaxed timing is generated by the GPCM for accesses
- * initiated to this memory region.
- * - One idle clock is inserted between a read access from the
- * current bank and the next access.
- */
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE) |\
- ORxG_CSNT |\
- ORxG_ACS_DIV1 |\
- ORxG_SCY_5_CLK |\
- ORxG_TRLX |\
- ORxG_EHTR)
-
-/*-----------------------------------------------------------------------
- * BR2,BR3 - Base Register
- * Ref: Section 10.3.1 on page 10-14
- * OR2,OR3 - Option Register
- * Ref: Section 10.3.2 on page 10-16
- *-----------------------------------------------------------------------
- */
-
-/*
- * Bank 2,3 - 128 MB SDRAM DIMM
- */
-
-/* With a 128 MB DIMM, the BR2 is configured as follows:
- *
- * - Base address of 0x00000000/0x08000000
- * - 64 bit port size (60x bus only)
- * - Data errors checking is disabled
- * - Read and write access
- * - SDRAM 60x bus
- * - Access are handled by the memory controller according to MSEL
- * - Not used for atomic operations
- * - No data pipelining is done
- * - Valid
- */
-#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
- BRx_PS_64 |\
- BRx_MS_SDRAM_P |\
- BRx_V)
-
-#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_SDRAM1_BASE & BRx_BA_MSK) |\
- BRx_PS_64 |\
- BRx_MS_SDRAM_P |\
- BRx_V)
-
-/* With a 128 MB DIMM, the OR2 is configured as follows:
- *
- * - 128 MB
- * - 4 internal banks per device
- * - Row start address bit is A8 with PSDMR[PBI] = 0
- * - 13 row address lines
- * - Back-to-back page mode
- * - Internal bank interleaving within save device enabled
- */
-
-#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\
- ORxS_BPD_4 |\
- ORxS_ROWST_PBI0_A7 |\
- ORxS_NUMR_13)
-
-#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM1_SIZE) |\
- ORxS_BPD_4 |\
- ORxS_ROWST_PBI0_A7 |\
- ORxS_NUMR_13)
-
-
-/*-----------------------------------------------------------------------
- * PSDMR - 60x Bus SDRAM Mode Register
- * Ref: Section 10.3.3 on page 10-21
- *-----------------------------------------------------------------------
- */
-
-/* With a 128 MB DIMM, the PSDMR is configured as follows:
- *
- * - Page Based Interleaving,
- * - Refresh Enable,
- * - Normal Operation
- * - Address Multiplexing where A5 is output on A14 pin
- * (A6 on A15, and so on),
- * - use address pins A13-A15 as bank select,
- * - A9 is output on SDA10 during an ACTIVATE command,
- * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
- * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
- * is 3 clocks,
- * - earliest timing for READ/WRITE command after ACTIVATE command is
- * 2 clocks,
- * - earliest timing for PRECHARGE after last data was read is 1 clock,
- * - earliest timing for PRECHARGE after last data was written is 1 clock,
- * - External Address Multiplexing enabled
- * - CAS Latency is 2.
- */
-#define CONFIG_SYS_PSDMR (PSDMR_RFEN |\
- PSDMR_SDAM_A14_IS_A5 |\
- PSDMR_BSMA_A13_A15 |\
- PSDMR_SDA10_PBI0_A9 |\
- PSDMR_RFRC_7_CLK |\
- PSDMR_PRETOACT_3W |\
- PSDMR_ACTTORW_2W |\
- PSDMR_LDOTOPRE_1C |\
- PSDMR_WRC_1C |\
- PSDMR_EAMUX |\
- PSDMR_CL_2)
-
-
-#define CONFIG_SYS_PSRT 0x0e
-#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32
-
-
-/*-----------------------------------------------------------------------
- * BR4 - Base Register
- * Ref: Section 10.3.1 on page 10-14
- * OR4 - Option Register
- * Ref: Section 10.3.2 on page 10-16
- *-----------------------------------------------------------------------
- */
-
-/*
- * Bank 4 - On board SDRAM
- *
- */
-/* With 16 MB of onboard SDRAM BR4 is configured as follows
- *
- * - Base address 0x38000000
- * - 32 bit port size
- * - Data error checking disabled
- * - Read/Write access
- * - SDRAM local bus
- * - Not used for atomic operations
- * - No data pipelining is done
- * - Valid
- *
- */
-
-#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_SDRAM2_BASE & BRx_BA_MSK) |\
- BRx_PS_32 |\
- BRx_DECC_NONE |\
- BRx_MS_SDRAM_L |\
- BRx_V)
-
-/*
- * With 16MB SDRAM, OR4 is configured as follows
- * - 4 internal banks per device
- * - Row start address bit is A10 with LSDMR[PBI] = 0
- * - 12 row address lines
- * - Back-to-back page mode
- * - Internal bank interleaving within save device enabled
- */
-
-#define CONFIG_SYS_OR4_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM2_SIZE) |\
- ORxS_BPD_4 |\
- ORxS_ROWST_PBI0_A10 |\
- ORxS_NUMR_12)
-
-
-/*-----------------------------------------------------------------------
- * LSDMR - Local Bus SDRAM Mode Register
- * Ref: Section 10.3.4 on page 10-24
- *-----------------------------------------------------------------------
- */
-
-/* With a 16 MB onboard SDRAM, the LSDMR is configured as follows:
- *
- * - Page Based Interleaving,
- * - Refresh Enable,
- * - Normal Operation
- * - Address Multiplexing where A5 is output on A13 pin
- * (A6 on A15, and so on),
- * - use address pins A15-A17 as bank select,
- * - A11 is output on SDA10 during an ACTIVATE command,
- * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
- * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
- * is 2 clocks,
- * - earliest timing for READ/WRITE command after ACTIVATE command is
- * 2 clocks,
- * - SDRAM burst length is 8
- * - earliest timing for PRECHARGE after last data was read is 1 clock,
- * - earliest timing for PRECHARGE after last data was written is 1 clock,
- * - External Address Multiplexing disabled
- * - CAS Latency is 2.
- */
-#define CONFIG_SYS_LSDMR (PSDMR_RFEN |\
- PSDMR_SDAM_A13_IS_A5 |\
- PSDMR_BSMA_A15_A17 |\
- PSDMR_SDA10_PBI0_A11 |\
- PSDMR_RFRC_7_CLK |\
- PSDMR_PRETOACT_2W |\
- PSDMR_ACTTORW_2W |\
- PSDMR_BL |\
- PSDMR_LDOTOPRE_1C |\
- PSDMR_WRC_1C |\
- PSDMR_CL_2)
-
-#define CONFIG_SYS_LSRT 0x0e
-
-/*-----------------------------------------------------------------------
- * BR5 - Base Register
- * Ref: Section 10.3.1 on page 10-14
- * OR5 - Option Register
- * Ref: Section 10.3.2 on page 10-16
- *-----------------------------------------------------------------------
- */
-
-/*
- * Bank 5 EEProm and Mailbox
- *
- * The EEPROM and mailbox live on the same chip select.
- * the eeprom is selected if the MSb of the address is set and the mailbox is
- * selected if the MSb of the address is clear.
- *
- */
-
-/* BR5 is configured as follows:
- *
- * - Base address of 0x32000000/0xF2000000
- * - 8 bit
- * - Data error checking disabled
- * - Read/Write access
- * - GPCM 60x Bus
- * - SDRAM local bus
- * - No data pipelining is done
- * - Valid
- */
-
-#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_MAILBOX_BASE & BRx_BA_MSK) |\
- BRx_PS_8 |\
- BRx_DECC_NONE |\
- BRx_MS_GPCM_P |\
- BRx_V)
-/* OR5 is configured as follows
- * - buffer control enabled
- * - chip select negated normally
- * - CS output 1/2 clock after address
- * - 15 wait states
- * - *PSDVAL is generated internally by the memory controller
- * unless *GTA is asserted earlier externally.
- * - Relaxed timing is generated by the GPCM for accesses
- * initiated to this memory region.
- * - One idle clock is inserted between a read access from the
- * current bank and the next access.
- */
-
-#define CONFIG_SYS_OR5_PRELIM ((P2SZ_TO_AM(CONFIG_SYS_MAILBOX_SIZE) & ~0x80000000) |\
- ORxG_ACS_DIV2 |\
- ORxG_SCY_15_CLK |\
- ORxG_TRLX |\
- ORxG_EHTR)
-
-/*-----------------------------------------------------------------------
- * BR6 - Base Register
- * Ref: Section 10.3.1 on page 10-14
- * OR6 - Option Register
- * Ref: Section 10.3.2 on page 10-18
- *-----------------------------------------------------------------------
- */
-
-/* Bank 6 - I/O select
- *
- */
-
-/* BR6 is configured as follows:
- *
- * - Base address of 0xE0000000
- * - 16 bit port size
- * - Data errors checking is disabled
- * - Read and write access
- * - GPCM 60x bus
- * - Access are handled by the memory controller according to MSEL
- * - Not used for atomic operations
- * - No data pipelining is done
- * - Valid
- */
-#define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_IOSELECT_BASE & BRx_BA_MSK) |\
- BRx_PS_16 |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-/* OR6 is configured as follows
- * - buffer control enabled
- * - chip select negated normally
- * - CS output 1/2 clock after address
- * - 15 wait states
- * - *PSDVAL is generated internally by the memory controller
- * unless *GTA is asserted earlier externally.
- * - Relaxed timing is generated by the GPCM for accesses
- * initiated to this memory region.
- * - One idle clock is inserted between a read access from the
- * current bank and the next access.
- */
-
-#define CONFIG_SYS_OR6_PRELIM (MEG_TO_AM(CONFIG_SYS_IOSELECT_SIZE) |\
- ORxG_ACS_DIV2 |\
- ORxG_SCY_15_CLK |\
- ORxG_TRLX |\
- ORxG_EHTR)
-
-
-/*-----------------------------------------------------------------------
- * BR7 - Base Register
- * Ref: Section 10.3.1 on page 10-14
- * OR7 - Option Register
- * Ref: Section 10.3.2 on page 10-18
- *-----------------------------------------------------------------------
- */
-
-/* Bank 7 - LEDs and switches
- *
- * LEDs are at 0x00001 (write only)
- * switches are at 0x00001 (read only)
- */
-#ifdef CONFIG_SYS_LED_BASE
-
-/* BR7 is configured as follows:
- *
- * - Base address of 0xA0000000
- * - 8 bit port size
- * - Data errors checking is disabled
- * - Read and write access
- * - GPCM 60x bus
- * - Access are handled by the memory controller according to MSEL
- * - Not used for atomic operations
- * - No data pipelining is done
- * - Valid
- */
-#define CONFIG_SYS_BR7_PRELIM ((CONFIG_SYS_LED_BASE & BRx_BA_MSK) |\
- BRx_PS_8 |\
- BRx_DECC_NONE |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-/* OR7 is configured as follows:
- *
- * - 1 byte
- * - *BCTL0 is asserted upon access to the current memory bank
- * - *CW / *WE are negated a quarter of a clock earlier
- * - *CS is output@the same time as the address lines
- * - Uses a clock cycle length of 15
- * - *PSDVAL is generated internally by the memory controller
- * unless *GTA is asserted earlier externally.
- * - Relaxed timing is generated by the GPCM for accesses
- * initiated to this memory region.
- * - One idle clock is inserted between a read access from the
- * current bank and the next access.
- */
-#define CONFIG_SYS_OR7_PRELIM (ORxG_AM_MSK |\
- ORxG_CSNT |\
- ORxG_ACS_DIV1 |\
- ORxG_SCY_15_CLK |\
- ORxG_TRLX |\
- ORxG_EHTR)
-#endif /* CONFIG_SYS_LED_BASE */
-#endif /* __CONFIG_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [U-Boot] [PATCH 16/26] mpc8260: remove ep8260 board support
2014-12-15 14:26 [U-Boot] [PATCH 0/26] Start removing non-generic boards Masahiro Yamada
` (14 preceding siblings ...)
2014-12-15 14:26 ` [U-Boot] [PATCH 15/26] mpc8260: remove ppmc8260 " Masahiro Yamada
@ 2014-12-15 14:26 ` Masahiro Yamada
2015-01-05 18:21 ` Tom Rini
2014-12-15 14:26 ` [U-Boot] [PATCH 17/26] mpc8260: remove VoVPN-GW " Masahiro Yamada
` (11 subsequent siblings)
27 siblings, 1 reply; 55+ messages in thread
From: Masahiro Yamada @ 2014-12-15 14:26 UTC (permalink / raw)
To: u-boot
This board is still a non-generic board.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Frank Panno <fpanno@delphintech.com>
---
arch/powerpc/cpu/mpc8260/Kconfig | 4 -
board/ep8260/Kconfig | 9 -
board/ep8260/MAINTAINERS | 6 -
board/ep8260/Makefile | 8 -
board/ep8260/ep8260.c | 304 ----------------
board/ep8260/ep8260.h | 24 --
board/ep8260/flash.c | 395 ---------------------
board/ep8260/mii_phy.c | 107 ------
configs/ep8260_defconfig | 3 -
doc/README.scrapyard | 1 +
include/configs/ep8260.h | 744 ---------------------------------------
11 files changed, 1 insertion(+), 1604 deletions(-)
delete mode 100644 board/ep8260/Kconfig
delete mode 100644 board/ep8260/MAINTAINERS
delete mode 100644 board/ep8260/Makefile
delete mode 100644 board/ep8260/ep8260.c
delete mode 100644 board/ep8260/ep8260.h
delete mode 100644 board/ep8260/flash.c
delete mode 100644 board/ep8260/mii_phy.c
delete mode 100644 configs/ep8260_defconfig
delete mode 100644 include/configs/ep8260.h
diff --git a/arch/powerpc/cpu/mpc8260/Kconfig b/arch/powerpc/cpu/mpc8260/Kconfig
index d4132a0..1032712 100644
--- a/arch/powerpc/cpu/mpc8260/Kconfig
+++ b/arch/powerpc/cpu/mpc8260/Kconfig
@@ -16,9 +16,6 @@ config TARGET_CPU86
config TARGET_CPU87
bool "Support CPU87"
-config TARGET_EP8260
- bool "Support ep8260"
-
config TARGET_EP82XXM
bool "Support ep82xxm"
@@ -51,7 +48,6 @@ endchoice
source "board/atc/Kconfig"
source "board/cpu86/Kconfig"
source "board/cpu87/Kconfig"
-source "board/ep8260/Kconfig"
source "board/ep82xxm/Kconfig"
source "board/freescale/mpc8266ads/Kconfig"
source "board/funkwerk/vovpn-gw/Kconfig"
diff --git a/board/ep8260/Kconfig b/board/ep8260/Kconfig
deleted file mode 100644
index 5d876f4..0000000
--- a/board/ep8260/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_EP8260
-
-config SYS_BOARD
- default "ep8260"
-
-config SYS_CONFIG_NAME
- default "ep8260"
-
-endif
diff --git a/board/ep8260/MAINTAINERS b/board/ep8260/MAINTAINERS
deleted file mode 100644
index bfa923c..0000000
--- a/board/ep8260/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-EP8260 BOARD
-#M: Frank Panno <fpanno@delphintech.com>
-S: Orphan (since 2014-06)
-F: board/ep8260/
-F: include/configs/ep8260.h
-F: configs/ep8260_defconfig
diff --git a/board/ep8260/Makefile b/board/ep8260/Makefile
deleted file mode 100644
index dd08b74..0000000
--- a/board/ep8260/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2002-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = ep8260.o flash.o mii_phy.o
diff --git a/board/ep8260/ep8260.c b/board/ep8260/ep8260.c
deleted file mode 100644
index 3697d24..0000000
--- a/board/ep8260/ep8260.c
+++ /dev/null
@@ -1,304 +0,0 @@
-/*
- * (C) Copyright 2001, 2002
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * (C) Copyright 2002
- * Frank Panno <fpanno@delphintech.com>, Delphin Technology AG
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc8260.h>
-#include "ep8260.h"
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
- /* Port A configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PA31 */ { 0, 0, 0, 1, 0, 0 }, /* */
- /* PA30 */ { 0, 0, 0, 1, 0, 0 }, /* */
- /* PA29 */ { 0, 0, 0, 1, 0, 0 }, /* */
- /* PA28 */ { 0, 0, 0, 1, 0, 0 }, /* */
- /* PA27 */ { 0, 0, 0, 1, 0, 0 }, /* */
- /* PA26 */ { 0, 0, 0, 1, 0, 0 }, /* */
- /* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* */
- /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* */
- /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* */
- /* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* */
- /* PA21 */ { 0, 0, 0, 1, 0, 0 }, /* */
- /* PA20 */ { 0, 0, 0, 1, 0, 0 }, /* */
- /* PA19 */ { 0, 0, 0, 1, 0, 0 }, /* */
- /* PA18 */ { 0, 0, 0, 1, 0, 0 }, /* */
- /* PA17 */ { 0, 0, 0, 1, 0, 0 }, /* */
- /* PA16 */ { 0, 0, 0, 1, 0, 0 }, /* */
- /* PA15 */ { 0, 0, 0, 1, 0, 0 }, /* */
- /* PA14 */ { 0, 0, 0, 1, 0, 0 }, /* */
- /* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* */
- /* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* */
- /* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* */
- /* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* */
- /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* */
- /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* */
- /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
- /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */
- /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
- /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
- /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
- /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
- /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */
- /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
- },
-
- /* Port B configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PB31 */ { 0, 1, 0, 1, 0, 0 }, /* */
- /* PB30 */ { 0, 1, 0, 0, 0, 0 }, /* */
- /* PB29 */ { 0, 1, 1, 1, 0, 0 }, /* */
- /* PB28 */ { 0, 1, 0, 0, 0, 0 }, /* */
- /* PB27 */ { 0, 1, 0, 0, 0, 0 }, /* */
- /* PB26 */ { 0, 1, 0, 0, 0, 0 }, /* */
- /* PB25 */ { 0, 1, 0, 1, 0, 0 }, /* */
- /* PB24 */ { 0, 1, 0, 1, 0, 0 }, /* */
- /* PB23 */ { 0, 1, 0, 1, 0, 0 }, /* */
- /* PB22 */ { 0, 1, 0, 1, 0, 0 }, /* */
- /* PB21 */ { 0, 1, 0, 0, 0, 0 }, /* */
- /* PB20 */ { 0, 1, 0, 0, 0, 0 }, /* */
- /* PB19 */ { 0, 1, 0, 0, 0, 0 }, /* */
- /* PB18 */ { 0, 1, 0, 0, 0, 0 }, /* */
- /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_DV */
- /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_ER */
- /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_ER */
- /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_EN */
- /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII COL */
- /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CRS */
- /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[3] */
- /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[2] */
- /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[1] */
- /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[0] */
- /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
- /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[1] */
- /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[2] */
- /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[3] */
- /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- },
-
- /* Port C */
- { /* conf ppar psor pdir podr pdat */
- /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
- /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
- /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* */
- /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
- /* PC27 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[0] */
- /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
- /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
- /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
- /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* */
- /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* */
- /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* */
- /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* */
- /* PC19 */ { 0, 1, 0, 0, 0, 0 }, /* */
- /* PC18 */ { 0, 1, 0, 0, 0, 0 }, /* */
- /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CLK15 */
- /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CLK16 */
- /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */
- /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* */
- /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
- /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */
- /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */
- /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* */
- /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* */
- /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
- /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
- /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
- /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
- /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
- /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
- /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* */
- /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* */
- /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* */
- },
-
- /* Port D */
- { /* conf ppar psor pdir podr pdat */
- /* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* */
- /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* */
- /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* */
- /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */
- /* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */
- /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
- /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
- /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
- /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
- /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
- /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
- /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
- /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
- /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
- /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* */
- /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* */
- /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
- /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
- /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
- /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
- /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
- /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
- /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
- /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
- /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
- /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
- /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
- /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
- /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- }
-};
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Setup CS4 to enable the Board Control/Status registers.
- * Otherwise the smcs won't work.
-*/
-int board_early_init_f (void)
-{
- volatile t_ep_regs *regs = (t_ep_regs *) CONFIG_SYS_REGS_BASE;
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8260_t *memctl = &immap->im_memctl;
-
- memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM;
- memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM;
- regs->bcsr1 = 0x62; /* to enable terminal on SMC1 */
- regs->bcsr2 = 0x30; /* enable NVRAM and writing FLASH */
- return 0;
-}
-
-void reset_phy (void)
-{
- volatile t_ep_regs *regs = (t_ep_regs *) CONFIG_SYS_REGS_BASE;
-
- regs->bcsr4 = 0xC0;
-}
-
-/*
- * Check Board Identity:
- * I don' know, how the next board revisions will be coded.
- * Thats why its a static interpretation ...
-*/
-
-int checkboard (void)
-{
- volatile t_ep_regs *regs = (t_ep_regs *) CONFIG_SYS_REGS_BASE;
- uint major = 0, minor = 0;
-
- switch (regs->bcsr0) {
- case 0x02:
- major = 1;
- break;
- case 0x03:
- major = 1;
- minor = 1;
- break;
- case 0x06:
- major = 1;
- minor = 3;
- break;
- default:
- break;
- }
- printf ("Board: Embedded Planet EP8260, Revision %d.%d\n",
- major, minor);
- return 0;
-}
-
-
-/* ------------------------------------------------------------------------- */
-
-
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8260_t *memctl = &immap->im_memctl;
- volatile uchar c = 0;
- volatile uchar *ramaddr = (uchar *) (CONFIG_SYS_SDRAM_BASE) + 0x110;
-
-/*
- ulong psdmr = CONFIG_SYS_PSDMR;
-#ifdef CONFIG_SYS_LSDRAM
- ulong lsdmr = CONFIG_SYS_LSDMR;
-#endif
-*/
- long size = CONFIG_SYS_SDRAM0_SIZE;
- int i;
-
-
-/*
-* Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
-*
-* "At system reset, initialization software must set up the
-* programmable parameters in the memory controller banks registers
-* (ORx, BRx, P/LSDMR). After all memory parameters are configured,
-* system software should execute the following initialization sequence
-* for each SDRAM device.
-*
-* 1. Issue a PRECHARGE-ALL-BANKS command
-* 2. Issue eight CBR REFRESH commands
-* 3. Issue a MODE-SET command to initialize the mode register
-*
-* The initial commands are executed by setting P/LSDMR[OP] and
-* accessing the SDRAM with a single-byte transaction."
-*
-* The appropriate BRx/ORx registers have already been set when we
-* get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
-*/
-
- memctl->memc_psrt = CONFIG_SYS_PSRT;
- memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-
- memctl->memc_psdmr = (ulong) CONFIG_SYS_PSDMR | PSDMR_OP_PREA;
- *ramaddr = c;
-
- memctl->memc_psdmr = (ulong) CONFIG_SYS_PSDMR | PSDMR_OP_CBRR;
- for (i = 0; i < 8; i++)
- *ramaddr = c;
-
- memctl->memc_psdmr = (ulong) CONFIG_SYS_PSDMR | PSDMR_OP_MRW;
- *ramaddr = c;
-
- memctl->memc_psdmr = (ulong) CONFIG_SYS_PSDMR | PSDMR_OP_NORM | PSDMR_RFEN;
- *ramaddr = c;
-
-#ifndef CONFIG_SYS_RAMBOOT
-#ifdef CONFIG_SYS_LSDRAM
- size += CONFIG_SYS_SDRAM1_SIZE;
- ramaddr = (uchar *) (CONFIG_SYS_SDRAM1_BASE) + 0x8c;
- memctl->memc_lsrt = CONFIG_SYS_LSRT;
-
- memctl->memc_lsdmr = (ulong) CONFIG_SYS_LSDMR | PSDMR_OP_PREA;
- *ramaddr = c;
-
- memctl->memc_lsdmr = (ulong) CONFIG_SYS_LSDMR | PSDMR_OP_CBRR;
- for (i = 0; i < 8; i++)
- *ramaddr = c;
-
- memctl->memc_lsdmr = (ulong) CONFIG_SYS_LSDMR | PSDMR_OP_MRW;
- *ramaddr = c;
-
- memctl->memc_lsdmr = (ulong) CONFIG_SYS_LSDMR | PSDMR_OP_NORM | PSDMR_RFEN;
- *ramaddr = c;
-#endif /* CONFIG_SYS_LSDRAM */
-#endif /* CONFIG_SYS_RAMBOOT */
- return (size * 1024 * 1024);
-}
diff --git a/board/ep8260/ep8260.h b/board/ep8260/ep8260.h
deleted file mode 100644
index 3032b14..0000000
--- a/board/ep8260/ep8260.h
+++ /dev/null
@@ -1,24 +0,0 @@
-#ifndef __EP8260_H__
-#define __EP8260_H__
-
-typedef struct tt_ep_regs {
- volatile unsigned char bcsr0;
- volatile unsigned char bcsr1;
- volatile unsigned char bcsr2;
- volatile unsigned char bcsr3;
- volatile unsigned char bcsr4;
- volatile unsigned char bcsr5;
- volatile unsigned char bcsr6;
- volatile unsigned char bcsr7;
- volatile unsigned char bcsr8;
- volatile unsigned char bcsr9;
- volatile unsigned char bcsr10;
- volatile unsigned char bcsr11;
- volatile unsigned char bcsr12;
- volatile unsigned char bcsr13;
- volatile unsigned char bcsr14;
- volatile unsigned char bcsr15;
-} t_ep_regs;
-typedef t_ep_regs *tp_ep_regs;
-
-#endif
diff --git a/board/ep8260/flash.c b/board/ep8260/flash.c
deleted file mode 100644
index 44f63ee..0000000
--- a/board/ep8260/flash.c
+++ /dev/null
@@ -1,395 +0,0 @@
-/*
- * (C) Copyright 2001, 2002
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * (C) Copyright 2002
- * Frank Panno <fpanno@delphintech.com>, Delphin Technology AG
- *
- * Flash Routines for AMD device AM29DL323DB on the EP8260 board.
- *
- * This file is based on board/tqm8260/flash.c.
- *--------------------------------------------------------------------
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-#define V_ULONG(a) (*(volatile unsigned long *)( a ))
-#define V_BYTE(a) (*(volatile unsigned char *)( a ))
-
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-
-/*-----------------------------------------------------------------------
- */
-void flash_reset(void)
-{
- if( flash_info[0].flash_id != FLASH_UNKNOWN ) {
- V_ULONG( flash_info[0].start[0] ) = 0x00F000F0;
- V_ULONG( flash_info[0].start[0] + 4 ) = 0x00F000F0;
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-ulong flash_get_size( ulong baseaddr, flash_info_t *info )
-{
- short i;
- unsigned long flashtest_h, flashtest_l;
-
- /* Write auto select command sequence and test FLASH answer */
- V_ULONG(baseaddr + ((ulong)0x0555 << 3)) = 0x00AA00AA;
- V_ULONG(baseaddr + ((ulong)0x02AA << 3)) = 0x00550055;
- V_ULONG(baseaddr + ((ulong)0x0555 << 3)) = 0x00900090;
- V_ULONG(baseaddr + 4 + ((ulong)0x0555 << 3)) = 0x00AA00AA;
- V_ULONG(baseaddr + 4 + ((ulong)0x02AA << 3)) = 0x00550055;
- V_ULONG(baseaddr + 4 + ((ulong)0x0555 << 3)) = 0x00900090;
-
- flashtest_h = V_ULONG(baseaddr); /* manufacturer ID */
- flashtest_l = V_ULONG(baseaddr + 4);
-
- if ((int)flashtest_h == AMD_MANUFACT) {
- info->flash_id = FLASH_MAN_AMD;
- } else {
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
- flashtest_h = V_ULONG(baseaddr + 8); /* device ID */
- flashtest_l = V_ULONG(baseaddr + 12);
- if (flashtest_h != flashtest_l) {
- info->flash_id = FLASH_UNKNOWN;
- return(0);
- }
-
- switch((int)flashtest_h) {
- case AMD_ID_DL323B:
- info->flash_id += FLASH_AMDL323B;
- info->sector_count = 71;
- info->size = 0x01000000; /* 4 * 4 MB = 16 MB */
- break;
- case AMD_ID_LV640U: /* AMDLV640 and AMDLV641 have same ID */
- info->flash_id += FLASH_AMLV640U;
- info->sector_count = 128;
- info->size = 0x02000000; /* 4 * 8 MB = 32 MB */
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- return(0); /* no or unknown flash */
- }
-
- if(flashtest_h == AMD_ID_LV640U) {
- /* set up sector start adress table (uniform sector type) */
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = baseaddr + (i * 0x00040000);
- } else {
- /* set up sector start adress table (bottom sector type) */
- for (i = 0; i < 8; i++) {
- info->start[i] = baseaddr + (i * 0x00008000);
- }
- for (i = 8; i < info->sector_count; i++) {
- info->start[i] = baseaddr + (i * 0x00040000) - 0x001C0000;
- }
- }
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- if ((V_ULONG( info->start[i] + 16 ) & 0x00010001) ||
- (V_ULONG( info->start[i] + 20 ) & 0x00010001)) {
- info->protect[i] = 1; /* D0 = 1 if protected */
- } else {
- info->protect[i] = 0;
- }
- }
-
- flash_reset();
- return(info->size);
-}
-
-/*-----------------------------------------------------------------------
- */
-unsigned long flash_init (void)
-{
- unsigned long size_b0 = 0;
- int i;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here (only one bank) */
-
- size_b0 = flash_get_size(CONFIG_SYS_FLASH0_BASE, &flash_info[0]);
- if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0>>20);
- }
-
- /*
- * protect monitor and environment sectors
- */
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[0]);
-#endif
-
-#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
-# ifndef CONFIG_ENV_SIZE
-# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-# endif
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
- &flash_info[0]);
-#endif
-
- return (size_b0);
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch ((info->flash_id >> 16) & 0xff) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AMDL323B: printf ("29DL323B (32 M, bottom sector)\n");
- break;
- case FLASH_AMLV640U: printf ("29LV640U (64 M, uniform sector)\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
- return;
-}
-
-/*-----------------------------------------------------------------------
- */
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- int flag, prot, sect, l_sect;
- ulong start, now, last;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect])
- prot++;
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00AA00AA;
- V_ULONG( info->start[0] + (0x02AA << 3) ) = 0x00550055;
- V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00800080;
- V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00AA00AA;
- V_ULONG( info->start[0] + (0x02AA << 3) ) = 0x00550055;
- V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00AA00AA;
- V_ULONG( info->start[0] + 4 + (0x02AA << 3) ) = 0x00550055;
- V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00800080;
- V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00AA00AA;
- V_ULONG( info->start[0] + 4 + (0x02AA << 3) ) = 0x00550055;
- udelay (1000);
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- V_ULONG( info->start[sect] ) = 0x00300030;
- V_ULONG( info->start[sect] + 4 ) = 0x00300030;
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer (0);
- last = start;
- while ((V_ULONG( info->start[l_sect] ) & 0x00800080) != 0x00800080 ||
- (V_ULONG( info->start[l_sect] + 4 ) & 0x00800080) != 0x00800080)
- {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- serial_putc ('.');
- last = now;
- }
- }
-
- DONE:
- /* reset to read mode */
- flash_reset ();
-
- printf (" done\n");
- return 0;
-}
-
-static int write_dword (flash_info_t *, ulong, unsigned char *);
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong dp;
- static unsigned char bb[8];
- int i, l, rc, cc = cnt;
-
- dp = (addr & ~7); /* get lower dword aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - dp) != 0) {
- for (i = 0; i < 8; i++)
- bb[i] = (i < l || (i-l) >= cc) ? V_BYTE(dp+i) : *src++;
- if ((rc = write_dword(info, dp, bb)) != 0)
- {
- return (rc);
- }
- dp += 8;
- cc -= 8 - l;
- }
-
- /*
- * handle word aligned part
- */
- while (cc >= 8) {
- if ((rc = write_dword(info, dp, src)) != 0) {
- return (rc);
- }
- dp += 8;
- src += 8;
- cc -= 8;
- }
-
- if (cc <= 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- for (i = 0; i < 8; i++) {
- bb[i] = (i < cc) ? *src++ : V_BYTE(dp+i);
- }
- return (write_dword(info, dp, bb));
-}
-
-/*-----------------------------------------------------------------------
- * Write a dword to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_dword (flash_info_t *info, ulong dest, unsigned char * pdata)
-{
- ulong start;
- ulong cl = 0, ch =0;
- int flag, i;
-
- for (ch=0, i=0; i < 4; i++)
- ch = (ch << 8) + *pdata++; /* high word */
- for (cl=0, i=0; i < 4; i++)
- cl = (cl << 8) + *pdata++; /* low word */
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((vu_long *)dest) & ch) != ch
- ||(*((vu_long *)(dest + 4)) & cl) != cl)
- {
- return (2);
- }
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00AA00AA;
- V_ULONG( info->start[0] + (0x02AA << 3) ) = 0x00550055;
- V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00A000A0;
- V_ULONG( dest ) = ch;
- V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00AA00AA;
- V_ULONG( info->start[0] + 4 + (0x02AA << 3) ) = 0x00550055;
- V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00A000A0;
- V_ULONG( dest + 4 ) = cl;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
- while (((V_ULONG( dest ) & 0x00800080) != (ch & 0x00800080)) ||
- ((V_ULONG( dest + 4 ) & 0x00800080) != (cl & 0x00800080))) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- return (0);
-}
diff --git a/board/ep8260/mii_phy.c b/board/ep8260/mii_phy.c
deleted file mode 100644
index c7aa275..0000000
--- a/board/ep8260/mii_phy.c
+++ /dev/null
@@ -1,107 +0,0 @@
-#include <common.h>
-#include <mii_phy.h>
-#include "ep8260.h"
-
-#define MII_MDIO 0x01
-#define MII_MDCK 0x02
-#define MII_MDIR 0x04
-
-void
-mii_discover_phy(void)
-{
- int known;
- unsigned short phy_reg;
- unsigned long phy_id;
-
- known = 0;
- printf("Discovering phy @ 0: ");
- phy_id = mii_phy_read(2) << 16;
- phy_id |= mii_phy_read(3);
- if ((phy_id & 0xFFFFFC00) == 0x00137800) {
- printf("Level One ");
- if ((phy_id & 0x000003F0) == 0xE0) {
- printf("LXT971A Revision %d\n", (int)(phy_id & 0xF));
- known = 1;
- }
- else printf("unknown type\n");
- }
- else printf("unknown OUI = 0x%08lX\n", phy_id);
-
- phy_reg = mii_phy_read(1);
- if (!(phy_reg & 0x0004)) printf("Link is down\n");
- if (!(phy_reg & 0x0020)) printf("Auto-negotiation not complete\n");
- if (phy_reg & 0x0002) printf("Jabber condition detected\n");
- if (phy_reg & 0x0010) printf("Remote fault condition detected \n");
-
- if (known) {
- phy_reg = mii_phy_read(17);
- if (phy_reg & 0x0400)
- printf("Phy operating@%d MBit/s in %s-duplex mode\n",
- phy_reg & 0x4000 ? 100 : 10,
- phy_reg & 0x0200 ? "full" : "half");
- else
- printf("bad link!!\n");
-/*
-left off: no link, green 100MBit, yellow 10MBit
-right off: no activity, green full-duplex, yellow half-duplex
-*/
- mii_phy_write(20, 0x0452);
- }
-}
-
-unsigned short
-mii_phy_read(unsigned short reg)
-{
- int i;
- unsigned short tmp, val = 0, adr = 0;
- t_ep_regs *regs = (t_ep_regs*)CONFIG_SYS_REGS_BASE;
-
- tmp = 0x6002 | (adr << 7) | (reg << 2);
- regs->bcsr4 = 0xC3;
- for (i = 0; i < 64; i++) {
- regs->bcsr4 ^= MII_MDCK;
- }
- for (i = 0; i < 16; i++) {
- regs->bcsr4 &= ~MII_MDCK;
- if (tmp & 0x8000) regs->bcsr4 |= MII_MDIO;
- else regs->bcsr4 &= ~MII_MDIO;
- regs->bcsr4 |= MII_MDCK;
- tmp <<= 1;
- }
- regs->bcsr4 |= MII_MDIR;
- for (i = 0; i < 16; i++) {
- val <<= 1;
- regs->bcsr4 = MII_MDIO | (regs->bcsr4 | MII_MDCK);
- if (regs->bcsr4 & MII_MDIO) val |= 1;
- regs->bcsr4 = MII_MDIO | (regs->bcsr4 &= ~MII_MDCK);
- }
- return val;
-}
-
-void
-mii_phy_write(unsigned short reg, unsigned short val)
-{
- int i;
- unsigned short tmp, adr = 0;
- t_ep_regs *regs = (t_ep_regs*)CONFIG_SYS_REGS_BASE;
-
- tmp = 0x5002 | (adr << 7) | (reg << 2);
- regs->bcsr4 = 0xC3;
- for (i = 0; i < 64; i++) {
- regs->bcsr4 ^= MII_MDCK;
- }
- for (i = 0; i < 16; i++) {
- regs->bcsr4 &= ~MII_MDCK;
- if (tmp & 0x8000) regs->bcsr4 |= MII_MDIO;
- else regs->bcsr4 &= ~MII_MDIO;
- regs->bcsr4 |= MII_MDCK;
- tmp <<= 1;
- }
- for (i = 0; i < 16; i++) {
- regs->bcsr4 &= ~MII_MDCK;
- if (val & 0x8000) regs->bcsr4 |= MII_MDIO;
- else regs->bcsr4 &= ~MII_MDIO;
- regs->bcsr4 |= MII_MDCK;
- val <<= 1;
- }
-}
diff --git a/configs/ep8260_defconfig b/configs/ep8260_defconfig
deleted file mode 100644
index 1cce900..0000000
--- a/configs/ep8260_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_EP8260=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 0845651..46b6dbe 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+ep8260 powerpc mpc8260 - - Frank Panno <fpanno@delphintech.com>
ppmc8260 powerpc mpc8260 - - Brad Kemp <Brad.Kemp@seranoa.com>
sacsng powerpc mpc8260 - - Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
cogent_mpc8260 powerpc mpc8260 - - Murray Jensen <Murray.Jensen@csiro.au>
diff --git a/include/configs/ep8260.h b/include/configs/ep8260.h
deleted file mode 100644
index 9cd3054..0000000
--- a/include/configs/ep8260.h
+++ /dev/null
@@ -1,744 +0,0 @@
-/*
- * (C) Copyright 2002
- * Frank Panno <fpanno@delphintech.com>, Delphin Technology AG
- *
- * This file is based on similar values for other boards found in other
- * U-Boot config files, and some that I found in the EP8260 manual.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- *
- * "EP8260 H, V.1.1"
- * - 64M 60x Bus SDRAM
- * - 32M Local Bus SDRAM
- * - 16M Flash (4 x AM29DL323DB90WDI)
- * - 128k NVRAM with RTC
- *
- * "EP8260 H2, V.1.3" (CONFIG_SYS_EP8260_H2)
- * - 300MHz/133MHz/66MHz
- * - 64M 60x Bus SDRAM
- * - 32M Local Bus SDRAM
- * - 32M Flash
- * - 128k NVRAM with RTC
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* Define this to enable support the EP8260 H2 version */
-#define CONFIG_SYS_EP8260_H2 1
-/* #undef CONFIG_SYS_EP8260_H2 */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFF00000
-
-#define CONFIG_CPM2 1 /* Has a CPM2 */
-
-/* What is the oscillator's (UX2) frequency in Hz? */
-#define CONFIG_8260_CLKIN (66 * 1000 * 1000)
-
-/*-----------------------------------------------------------------------
- * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
- *-----------------------------------------------------------------------
- * What should MODCK_H be? It is dependent on the oscillator
- * frequency, MODCK[1-3], and desired CPM and core frequencies.
- * Here are some example values (all frequencies are in MHz):
- *
- * MODCK_H MODCK[1-3] Osc CPM Core
- * ------- ---------- --- --- ----
- * 0x2 0x2 33 133 133
- * 0x2 0x3 33 133 166
- * 0x2 0x4 33 133 200
- * 0x2 0x5 33 133 233
- * 0x2 0x6 33 133 266
- *
- * 0x5 0x5 66 133 133
- * 0x5 0x6 66 133 166
- * 0x5 0x7 66 133 200 *
- * 0x6 0x0 66 133 233
- * 0x6 0x1 66 133 266
- * 0x6 0x2 66 133 300
- */
-#ifdef CONFIG_SYS_EP8260_H2
-#define CONFIG_SYS_SBC_MODCK_H (HRCW_MODCK_H0110)
-#else
-#define CONFIG_SYS_SBC_MODCK_H (HRCW_MODCK_H0110)
-#endif
-
-/* Define this if you want to boot from 0x00000100. If you don't define
- * this, you will need to program the bootloader to 0xfff00000, and
- * get the hardware reset config words at 0xfe000000. The simplest
- * way to do that is to program the bootloader at both addresses.
- * It is suggested that you just let U-Boot live at 0x00000000.
- */
-/* #define CONFIG_SYS_SBC_BOOT_LOW 1 */ /* only for HRCW */
-/* #undef CONFIG_SYS_SBC_BOOT_LOW */
-
-/* The reset command will not work as expected if the reset address does
- * not point to the correct address.
- */
-
-#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
-
-/* What should the base address of the main FLASH be and how big is
- * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/ep8260/config.mk
- * The main FLASH is whichever is connected to *CS0. U-Boot expects
- * this to be the SIMM.
- */
-#ifdef CONFIG_SYS_EP8260_H2
-#define CONFIG_SYS_FLASH0_BASE 0xFE000000
-#define CONFIG_SYS_FLASH0_SIZE 32
-#else
-#define CONFIG_SYS_FLASH0_BASE 0xFF000000
-#define CONFIG_SYS_FLASH0_SIZE 16
-#endif
-
-/* What should the base address of the secondary FLASH be and how big
- * is it (in Mbytes)? The secondary FLASH is whichever is connected
- * to *CS6. U-Boot expects this to be the on board FLASH. If you don't
- * want it enabled, don't define these constants.
- */
-#define CONFIG_SYS_FLASH1_BASE 0
-#define CONFIG_SYS_FLASH1_SIZE 0
-#undef CONFIG_SYS_FLASH1_BASE
-#undef CONFIG_SYS_FLASH1_SIZE
-
-/* What should be the base address of SDRAM DIMM (60x bus) and how big is
- * it (in Mbytes)?
-*/
-#define CONFIG_SYS_SDRAM0_BASE 0x00000000
-#define CONFIG_SYS_SDRAM0_SIZE 64
-
-/* define CONFIG_SYS_LSDRAM if you want to enable the 32M SDRAM on the
- * local bus (8260 local bus is NOT cacheable!)
-*/
-/* #define CONFIG_SYS_LSDRAM */
-#undef CONFIG_SYS_LSDRAM
-
-#ifdef CONFIG_SYS_LSDRAM
-/* What should be the base address of SDRAM DIMM (local bus) and how big is
- * it (in Mbytes)?
-*/
- #define CONFIG_SYS_SDRAM1_BASE 0x04000000
- #define CONFIG_SYS_SDRAM1_SIZE 32
-#else
- #define CONFIG_SYS_SDRAM1_BASE 0
- #define CONFIG_SYS_SDRAM1_SIZE 0
- #undef CONFIG_SYS_SDRAM1_BASE
- #undef CONFIG_SYS_SDRAM1_SIZE
-#endif /* CONFIG_SYS_LSDRAM */
-
-/* What should be the base address of NVRAM and how big is
- * it (in Bytes)
- */
-#define CONFIG_SYS_NVRAM_BASE_ADDR 0xFA080000
-#define CONFIG_SYS_NVRAM_SIZE (128*1024)-16
-
-/* The RTC is a Dallas DS1556
- */
-#define CONFIG_RTC_DS1556
-
-/* What should be the base address of the LEDs and switch S0?
- * If you don't want them enabled, don't define this.
- */
-#define CONFIG_SYS_LED_BASE 0x00000000
-#undef CONFIG_SYS_LED_BASE
-
-/*
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * if CONFIG_CONS_NONE is defined, then the serial console routines must
- * defined elsewhere.
- */
-#define CONFIG_CONS_ON_SMC /* define if console on SMC */
-#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
-#undef CONFIG_CONS_NONE /* define if console on neither */
-#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
-
-/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
- */
-#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */
-#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */
-#undef CONFIG_ETHER_NONE /* define if ethernet on neither */
-#define CONFIG_ETHER_INDEX 3 /* which SCC/FCC channel for ethernet */
-
-#if ( CONFIG_ETHER_INDEX == 3 )
-
-/*
- * - Rx-CLK is CLK15
- * - Tx-CLK is CLK16
- * - RAM for BD/Buffers is on the local Bus (see 28-13)
- * - Enable Half Duplex in FSMR
- */
-# define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
-# define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
-
-/*
- * - RAM for BD/Buffers is on the local Bus (see 28-13)
- */
-#ifdef CONFIG_SYS_LSDRAM
- #define CONFIG_SYS_CPMFCR_RAMTYPE 3
-#else /* CONFIG_SYS_LSDRAM */
- #define CONFIG_SYS_CPMFCR_RAMTYPE 0
-#endif /* CONFIG_SYS_LSDRAM */
-
-/* - Enable Half Duplex in FSMR */
-/* # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) */
-# define CONFIG_SYS_FCC_PSMR 0
-
-#else /* CONFIG_ETHER_INDEX */
-# error "on EP8260 ethernet must be FCC3"
-#endif /* CONFIG_ETHER_INDEX */
-
-/*
- * select i2c support configuration
- *
- * Supported configurations are {none, software, hardware} drivers.
- * If the software driver is chosen, there are some additional
- * configuration items that the driver uses to drive the port pins.
- */
-#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F /* This is for HARD, must go */
-
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#ifdef CONFIG_SYS_I2C_SOFT
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT_SPEED 50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
-#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE (iop->pdir |= 0x00010000)
-#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
-#define I2C_READ ((iop->pdat & 0x00010000) != 0)
-#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
- else iop->pdat &= ~0x00010000
-#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
- else iop->pdat &= ~0x00020000
-#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
-#endif /* CONFIG_SYS_I2C_SOFT */
-
-/* #define CONFIG_RTC_DS174x */
-
-/* Define this to reserve an entire FLASH sector (256 KB) for
- * environment variables. Otherwise, the environment will be
- * put in the same sector as U-Boot, and changing variables
- * will erase U-Boot temporarily
- */
-#define CONFIG_ENV_IN_OWN_SECT
-
-/* Define to allow the user to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-/* What should the console's baud rate be? */
-#ifdef CONFIG_SYS_EP8260_H2
-#define CONFIG_BAUDRATE 9600
-#else
-#define CONFIG_BAUDRATE 115200
-#endif
-
-/* Ethernet MAC address */
-#define CONFIG_ETHADDR 00:10:EC:00:30:8C
-
-#define CONFIG_IPADDR 192.168.254.130
-#define CONFIG_SERVERIP 192.168.254.49
-
-/* Set to a positive value to delay for running BOOTCOMMAND */
-#define CONFIG_BOOTDELAY -1
-
-/* undef this to save memory */
-#define CONFIG_SYS_LONGHELP
-
-/* Monitor Command Prompt */
-
-/* Define this variable to enable the "hush" shell (from
- Busybox) as command line interpreter, thus enabling
- powerful command line syntax like
- if...then...else...fi conditionals or `&&' and '||'
- constructs ("shell scripts").
- If undefined, you get the old, much simpler behaviour
- with a somewhat smapper memory footprint.
-*/
-#define CONFIG_SYS_HUSH_PARSER
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_BEDBUG
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_CDP
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_PORTIO
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_SNTP
-
-#undef CONFIG_CMD_XIMG
-
-/* Where do the internal registers live? */
-#define CONFIG_SYS_IMMR 0xF0000000
-#define CONFIG_SYS_DEFAULT_IMMR 0x00010000
-
-/* Where do the on board registers (CS4) live? */
-#define CONFIG_SYS_REGS_BASE 0xFA000000
-
-/*****************************************************************************
- *
- * You should not have to modify any of the following settings
- *
- *****************************************************************************/
-
-#define CONFIG_EP8260 11 /* on an Embedded Planet EP8260 Board, Rev. 11 */
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-
-/*
- * Miscellaneous configurable options
- */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
-
-#define CONFIG_SYS_MAXARGS 8 /* max number of command args */
-
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#ifdef CONFIG_SYS_LSDRAM
- #define CONFIG_SYS_MEMTEST_START 0x04000000 /* memtest works on */
- #define CONFIG_SYS_MEMTEST_END 0x06000000 /* 64-96 MB in SDRAM */
-#else
- #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
- #define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0-32 MB in SDRAM */
-#endif /* CONFIG_SYS_LSDRAM */
-
-#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
-
-#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM0_BASE
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
- */
-
-#if defined(CONFIG_SYS_SBC_BOOT_LOW)
-# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
-#else
-# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (0x00000000)
-#endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */
-
-#ifdef CONFIG_SYS_EP8260_H2
-/* get the HRCW ISB field from CONFIG_SYS_DEFAULT_IMMR */
-#define CONFIG_SYS_SBC_HRCW_IMMR ( ((CONFIG_SYS_DEFAULT_IMMR & 0x10000000) >> 10) |\
- ((CONFIG_SYS_DEFAULT_IMMR & 0x01000000) >> 7) |\
- ((CONFIG_SYS_DEFAULT_IMMR & 0x00100000) >> 4) )
-
-#define CONFIG_SYS_HRCW_MASTER (HRCW_EBM |\
- HRCW_L2CPC01 |\
- CONFIG_SYS_SBC_HRCW_IMMR |\
- HRCW_APPC10 |\
- HRCW_CS10PC01 |\
- CONFIG_SYS_SBC_MODCK_H |\
- CONFIG_SYS_SBC_HRCW_BOOT_FLAGS)
-#else
-#define CONFIG_SYS_HRCW_MASTER 0x10400245
-#endif
-
-/* no slaves */
-#define CONFIG_SYS_HRCW_SLAVE1 0
-#define CONFIG_SYS_HRCW_SLAVE2 0
-#define CONFIG_SYS_HRCW_SLAVE3 0
-#define CONFIG_SYS_HRCW_SLAVE4 0
-#define CONFIG_SYS_HRCW_SLAVE5 0
-#define CONFIG_SYS_HRCW_SLAVE6 0
-#define CONFIG_SYS_HRCW_SLAVE7 0
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent.
- */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-# define CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#ifdef CONFIG_SYS_EP8260_H2
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
-#else
-#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
-#endif
-
-#ifdef CONFIG_SYS_EP8260_H2
-#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-#else
-#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
-#endif
-
-#ifndef CONFIG_SYS_RAMBOOT
-# define CONFIG_ENV_IS_IN_FLASH 1
-
-# ifdef CONFIG_ENV_IN_OWN_SECT
-# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
-# define CONFIG_ENV_SECT_SIZE 0x40000
-# else
-# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE)
-# define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
-# define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */
-# endif /* CONFIG_ENV_IN_OWN_SECT */
-#else
-# define CONFIG_ENV_IS_IN_NVRAM 1
-# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
-# define CONFIG_ENV_SIZE 0x200
-#endif /* CONFIG_SYS_RAMBOOT */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers 2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-#define CONFIG_SYS_HID0_INIT (HID0_ICE |\
- HID0_DCE |\
- HID0_ICFI |\
- HID0_DCI |\
- HID0_IFEM |\
- HID0_ABE)
-#ifdef CONFIG_SYS_LSDRAM
-/* 8260 local bus is NOT cacheable */
-#define CONFIG_SYS_HID0_FINAL (/*HID0_ICE |*/\
- HID0_IFEM |\
- HID0_ABE |\
- HID0_EMCP)
-#else /* !CONFIG_SYS_LSDRAM */
-#define CONFIG_SYS_HID0_FINAL (HID0_ICE |\
- HID0_IFEM |\
- HID0_ABE |\
- HID0_EMCP)
-#endif /* CONFIG_SYS_LSDRAM */
-
-#define CONFIG_SYS_HID2 0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RMR 0
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration 4-25
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_BCR (BCR_EBM |\
- BCR_PLDP |\
- BCR_EAV |\
- BCR_NPQM0)
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 4-31
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_SIUMCR (SIUMCR_L2CPC01 |\
- SIUMCR_APPC10 |\
- SIUMCR_CS10PC01)
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
- */
-#ifdef CONFIG_SYS_EP8260_H2
-/* TBD: Find out why setting the BMT to 0xff causes the FCC to
- * generate TX buffer underrun errors for large packets under
- * Linux
- */
-#define CONFIG_SYS_SYPCR_BMT 0x00000600
-#else
-#define CONFIG_SYS_SYPCR_BMT SYPCR_BMT
-#endif
-
-#ifdef CONFIG_SYS_LSDRAM
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC |\
- CONFIG_SYS_SYPCR_BMT |\
- SYPCR_PBME |\
- SYPCR_LBME |\
- SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC |\
- CONFIG_SYS_SYPCR_BMT |\
- SYPCR_PBME |\
- SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control 4-40
- *-----------------------------------------------------------------------
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- */
-#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC |\
- TMCNTSC_ALR |\
- TMCNTSC_TCF |\
- TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#ifdef CONFIG_SYS_EP8260_H2
-#define CONFIG_SYS_PISCR (PISCR_PS |\
- PISCR_PTF |\
- PISCR_PTE)
-#else
-#define CONFIG_SYS_PISCR 0
-#endif
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control 9-8
- *-----------------------------------------------------------------------
- */
-#ifdef CONFIG_SYS_EP8260_H2
-#define CONFIG_SYS_SCCR (SCCR_DFBRG00)
-#else
-#define CONFIG_SYS_SCCR (SCCR_DFBRG01)
-#endif
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration 13-7
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RCCR 0
-
-/*-----------------------------------------------------------------------
- * MPTPR - Memory Refresh Timer Prescale Register 10-32
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_MPTPR (0x0A00 & MPTPR_PTP_MSK)
-
-/*
- * Init Memory Controller:
- *
- * Bank Bus Machine PortSz Device
- * ---- --- ------- ------ ------
- * 0 60x GPCM 64 bit FLASH (BGA - 16MB AMD AM29DL323DB90WDI)
- * 1 60x SDRAM 64 bit SDRAM (BGA - 64MB Micron 48LC8M16A2TG)
- * 2 Local SDRAM 32 bit SDRAM (BGA - 32MB Micron 48LC8M16A2TG)
- * 3 unused
- * 4 60x GPCM 8 bit Board Regs, NVRTC
- * 5 unused
- * 6 unused
- * 7 unused
- * 8 PCMCIA
- * 9 unused
- * 10 unused
- * 11 unused
-*/
-
-/*-----------------------------------------------------------------------
- * BRx - Base Register
- * Ref: Section 10.3.1 on page 10-14
- * ORx - Option Register
- * Ref: Section 10.3.2 on page 10-18
- *-----------------------------------------------------------------------
- */
-
-/* Bank 0 - FLASH
- *
- */
-#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\
- BRx_PS_64 |\
- BRx_DECC_NONE |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE) |\
- ORxG_CSNT |\
- ORxG_ACS_DIV1 |\
- ORxG_SCY_8_CLK |\
- ORxG_EHTR)
-
-/* Bank 1 - SDRAM
- * PSDRAM
- */
-#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
- BRx_PS_64 |\
- BRx_MS_SDRAM_P |\
- BRx_V)
-
-#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\
- ORxS_BPD_4 |\
- ORxS_ROWST_PBI1_A6 |\
- ORxS_NUMR_12)
-
-#ifdef CONFIG_SYS_EP8260_H2
-#define CONFIG_SYS_PSDMR 0xC34E246E
-#else
-#define CONFIG_SYS_PSDMR 0xC34E2462
-#endif
-
-#define CONFIG_SYS_PSRT 0x64
-
-#ifdef CONFIG_SYS_LSDRAM
-/* Bank 2 - SDRAM
- * LSDRAM
- */
-
- #define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM1_BASE & BRx_BA_MSK) |\
- BRx_PS_32 |\
- BRx_MS_SDRAM_L |\
- BRx_V)
-
- #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM1_SIZE) |\
- ORxS_BPD_4 |\
- ORxS_ROWST_PBI0_A9 |\
- ORxS_NUMR_12)
-
- #define CONFIG_SYS_LSDMR 0x416A2562
- #define CONFIG_SYS_LSRT 0x64
-#else
- #define CONFIG_SYS_LSRT 0x0
-#endif /* CONFIG_SYS_LSDRAM */
-
-/* Bank 4 - On board registers
- * NVRTC and BCSR
- */
-#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_REGS_BASE & BRx_BA_MSK) |\
- BRx_PS_8 |\
- BRx_MS_GPCM_P |\
- BRx_V)
-/*
-#define CONFIG_SYS_OR4_PRELIM (ORxG_AM_MSK |\
- ORxG_CSNT |\
- ORxG_ACS_DIV1 |\
- ORxG_SCY_10_CLK |\
- ORxG_TRLX)
-*/
-#define CONFIG_SYS_OR4_PRELIM 0xfff00854
-
-#ifdef _NOT_USED_SINCE_NOT_WORKING_
-/* Bank 8 - On board registers
- * PCMCIA (currently not working!)
- */
-#define CONFIG_SYS_BR8_PRELIM ((CONFIG_SYS_REGS_BASE & BRx_BA_MSK) |\
- BRx_PS_16 |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-#define CONFIG_SYS_OR8_PRELIM (ORxG_AM_MSK |\
- ORxG_CSNT |\
- ORxG_ACS_DIV1 |\
- ORxG_SETA |\
- ORxG_SCY_10_CLK)
-#endif
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV "nor0"
-#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET 0x00000000
-
-/* mtdparts command line support */
-/* Note: fake mtd_id used, no linux mtd map file */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT ""
-#define MTDPARTS_DEFAULT ""
-*/
-
-#endif /* __CONFIG_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [U-Boot] [PATCH 17/26] mpc8260: remove VoVPN-GW board support
2014-12-15 14:26 [U-Boot] [PATCH 0/26] Start removing non-generic boards Masahiro Yamada
` (15 preceding siblings ...)
2014-12-15 14:26 ` [U-Boot] [PATCH 16/26] mpc8260: remove ep8260 " Masahiro Yamada
@ 2014-12-15 14:26 ` Masahiro Yamada
2015-01-05 18:21 ` Tom Rini
2014-12-15 14:26 ` [U-Boot] [PATCH 18/26] mpc8260: remove MPC8266ADS " Masahiro Yamada
` (10 subsequent siblings)
27 siblings, 1 reply; 55+ messages in thread
From: Masahiro Yamada @ 2014-12-15 14:26 UTC (permalink / raw)
To: u-boot
This board is still a non-generic board.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
---
arch/powerpc/cpu/mpc8260/Kconfig | 4 -
board/funkwerk/vovpn-gw/Kconfig | 12 -
board/funkwerk/vovpn-gw/MAINTAINERS | 6 -
board/funkwerk/vovpn-gw/Makefile | 8 -
board/funkwerk/vovpn-gw/flash.c | 436 ------------------------------------
board/funkwerk/vovpn-gw/m88e6060.c | 249 --------------------
board/funkwerk/vovpn-gw/m88e6060.h | 75 -------
board/funkwerk/vovpn-gw/vovpn-gw.c | 363 ------------------------------
configs/VoVPN-GW_66MHz_defconfig | 4 -
doc/README.scrapyard | 1 +
include/configs/VoVPN-GW.h | 399 ---------------------------------
11 files changed, 1 insertion(+), 1556 deletions(-)
delete mode 100644 board/funkwerk/vovpn-gw/Kconfig
delete mode 100644 board/funkwerk/vovpn-gw/MAINTAINERS
delete mode 100644 board/funkwerk/vovpn-gw/Makefile
delete mode 100644 board/funkwerk/vovpn-gw/flash.c
delete mode 100644 board/funkwerk/vovpn-gw/m88e6060.c
delete mode 100644 board/funkwerk/vovpn-gw/m88e6060.h
delete mode 100644 board/funkwerk/vovpn-gw/vovpn-gw.c
delete mode 100644 configs/VoVPN-GW_66MHz_defconfig
delete mode 100644 include/configs/VoVPN-GW.h
diff --git a/arch/powerpc/cpu/mpc8260/Kconfig b/arch/powerpc/cpu/mpc8260/Kconfig
index 1032712..15742d9 100644
--- a/arch/powerpc/cpu/mpc8260/Kconfig
+++ b/arch/powerpc/cpu/mpc8260/Kconfig
@@ -37,9 +37,6 @@ config TARGET_PM828
config TARGET_MPC8266ADS
bool "Support MPC8266ADS"
-config TARGET_VOVPN_GW
- bool "Support VoVPN-GW"
-
config TARGET_KM82XX
bool "Support km82xx"
@@ -50,7 +47,6 @@ source "board/cpu86/Kconfig"
source "board/cpu87/Kconfig"
source "board/ep82xxm/Kconfig"
source "board/freescale/mpc8266ads/Kconfig"
-source "board/funkwerk/vovpn-gw/Kconfig"
source "board/gw8260/Kconfig"
source "board/iphase4539/Kconfig"
source "board/keymile/km82xx/Kconfig"
diff --git a/board/funkwerk/vovpn-gw/Kconfig b/board/funkwerk/vovpn-gw/Kconfig
deleted file mode 100644
index 6b6c328..0000000
--- a/board/funkwerk/vovpn-gw/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_VOVPN_GW
-
-config SYS_BOARD
- default "vovpn-gw"
-
-config SYS_VENDOR
- default "funkwerk"
-
-config SYS_CONFIG_NAME
- default "VoVPN-GW"
-
-endif
diff --git a/board/funkwerk/vovpn-gw/MAINTAINERS b/board/funkwerk/vovpn-gw/MAINTAINERS
deleted file mode 100644
index 34d1cc1..0000000
--- a/board/funkwerk/vovpn-gw/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-VOVPN-GW BOARD
-#M: -
-S: Maintained
-F: board/funkwerk/vovpn-gw/
-F: include/configs/VoVPN-GW.h
-F: configs/VoVPN-GW_66MHz_defconfig
diff --git a/board/funkwerk/vovpn-gw/Makefile b/board/funkwerk/vovpn-gw/Makefile
deleted file mode 100644
index 3253247..0000000
--- a/board/funkwerk/vovpn-gw/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := vovpn-gw.o flash.o m88e6060.o
diff --git a/board/funkwerk/vovpn-gw/flash.c b/board/funkwerk/vovpn-gw/flash.c
deleted file mode 100644
index 829514c..0000000
--- a/board/funkwerk/vovpn-gw/flash.c
+++ /dev/null
@@ -1,436 +0,0 @@
-/*
- * (C) Copyright 2004
- * Elmeg Communications Systems GmbH, Juergen Selent (j.selent at elmeg.de)
- *
- * Support for the Elmeg VoVPN Gateway Module
- * ------------------------------------------
- * This is a signle bank flashdriver for INTEL 28F320J3, 28F640J3
- * and 28F128J3A flashs working in 8 Bit mode.
- *
- * Most of this code is taken from existing u-boot source code.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-#define FLASH_CMD_READ_ID 0x90
-#define FLASH_CMD_READ_STATUS 0x70
-#define FLASH_CMD_RESET 0xff
-#define FLASH_CMD_BLOCK_ERASE 0x20
-#define FLASH_CMD_ERASE_CONFIRM 0xd0
-#define FLASH_CMD_CLEAR_STATUS 0x50
-#define FLASH_CMD_SUSPEND_ERASE 0xb0
-#define FLASH_CMD_WRITE 0x40
-#define FLASH_CMD_WRITE_BUFF 0xe8
-#define FLASH_CMD_PROG_RESUME 0xd0
-#define FLASH_CMD_PROTECT 0x60
-#define FLASH_CMD_PROTECT_SET 0x01
-#define FLASH_CMD_PROTECT_CLEAR 0xd0
-#define FLASH_STATUS_DONE 0x80
-
-#define FLASH_WRITE_BUFFER_SIZE 32
-
-#ifdef CONFIG_SYS_FLASH_16BIT
-#define FLASH_WORD_SIZE unsigned short
-#define FLASH_ID_MASK 0xffff
-#define FLASH_CMD_ADDR_SHIFT 0
-#else
-#define FLASH_WORD_SIZE unsigned char
-#define FLASH_ID_MASK 0xff
-/* A0 is not used in either 8x or 16x for READ ID */
-#define FLASH_CMD_ADDR_SHIFT 1
-#endif
-
-
-static unsigned long
-flash_get(volatile FLASH_WORD_SIZE *addr, flash_info_t *info)
-{
- volatile FLASH_WORD_SIZE *p;
- FLASH_WORD_SIZE value;
- int i;
-
- addr[0] = FLASH_CMD_READ_ID;
-
- /* manufactor */
- value = addr[0 << FLASH_CMD_ADDR_SHIFT];
- switch (value) {
- case (INTEL_MANUFACT & FLASH_ID_MASK):
- info->flash_id = FLASH_MAN_INTEL;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- *addr = FLASH_CMD_RESET;
- return (0);
-
- }
-
- /* device */
- value = addr[1 << FLASH_CMD_ADDR_SHIFT];
- switch (value) {
- case (INTEL_ID_28F320J3A & FLASH_ID_MASK):
- info->flash_id += FLASH_28F320J3A;
- info->sector_count = 32;
- info->size = 0x00400000;
- break;
- case (INTEL_ID_28F640J3A & FLASH_ID_MASK):
- info->flash_id += FLASH_28F640J3A;
- info->sector_count = 64;
- info->size = 0x00800000;
- break;
- case (INTEL_ID_28F128J3A & FLASH_ID_MASK):
- info->flash_id += FLASH_28F128J3A;
- info->sector_count = 128;
- info->size = 0x01000000;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- *addr = FLASH_CMD_RESET;
- return (0);
- }
-
- /* setup sectors */
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = (unsigned long)addr + (i * info->size/info->sector_count);
- }
-
- /* check protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- p = (volatile FLASH_WORD_SIZE *)(info->start[i]);
- info->protect[i] = p[2 << FLASH_CMD_ADDR_SHIFT] & 1;
- }
-
- /* reset bank */
- *addr = FLASH_CMD_RESET;
- return (info->size);
-}
-
-unsigned long
-flash_init(void)
-{
- unsigned long size;
- int i;
-
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
- size = flash_get((volatile FLASH_WORD_SIZE *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH Size=0x%08lx\n", size);
- return (0);
- }
-
- /* always protect 1 sector containing the HRCW */
- flash_protect(FLAG_PROTECT_SET,
- flash_info[0].start[0],
- flash_info[0].start[1] - 1,
- &flash_info[0]);
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_FLASH,
- CONFIG_SYS_MONITOR_FLASH+CONFIG_SYS_MONITOR_LEN-1,
- &flash_info[0]);
-#endif
-#ifdef CONFIG_ENV_IS_IN_FLASH
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
- &flash_info[0]);
-#endif
- return (size);
-}
-
-void
-flash_print_info(flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_INTEL: printf ("INTEL "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F320J3A: printf ("28F320JA3 (32 Mbit)\n");
- break;
- case FLASH_28F640J3A: printf ("28F640JA3 (64 Mbit)\n");
- break;
- case FLASH_28F128J3A: printf ("28F128JA3 (128 Mbit)\n");
- break;
- default: printf ("Unknown Chip Type");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
-}
-
-int
-flash_erase(flash_info_t *info, int s_first, int s_last)
-{
- unsigned long start, now, last;
- int flag, prot, sect;
- volatile FLASH_WORD_SIZE *addr;
- FLASH_WORD_SIZE status;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return (1);
- }
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("Cannot erase unknown flash - aborted\n");
- return (1);
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n", prot);
- } else {
- printf ("\n");
- }
-
- start = get_timer (0);
- last = start;
-
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect]) {
- continue;
- }
-
- addr = (volatile FLASH_WORD_SIZE *)(info->start[sect]);
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
-#ifdef DEBUG
- printf("Erase sector %d at start addr 0x%08X", sect, (unsigned int)info->start[sect]);
-#endif
-
- *addr = FLASH_CMD_CLEAR_STATUS;
- *addr = FLASH_CMD_BLOCK_ERASE;
- *addr = FLASH_CMD_ERASE_CONFIRM;
-
- /* re-enable interrupts if necessary */
- if (flag) {
- enable_interrupts();
- }
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- while (((status = *addr) & FLASH_STATUS_DONE) != FLASH_STATUS_DONE) {
- if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf("Flash erase timeout at address %lx\n", info->start[sect]);
- *addr = FLASH_CMD_SUSPEND_ERASE;
- *addr = FLASH_CMD_RESET;
- return (1);
- }
-
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
- *addr = FLASH_CMD_RESET;
- }
- printf (" done\n");
- return (0);
-}
-
-static int
-write_buff2( volatile FLASH_WORD_SIZE *dst,
- volatile FLASH_WORD_SIZE *src,
- unsigned long cnt )
-{
- unsigned long start;
- FLASH_WORD_SIZE status;
- int flag, i;
-
- start = get_timer (0);
- while (1) {
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
- dst[0] = FLASH_CMD_WRITE_BUFF;
- if ((status = *dst) & FLASH_STATUS_DONE) {
- break;
- }
-
- /* re-enable interrupts if necessary */
- if (flag) {
- enable_interrupts();
- }
-
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (-1);
- }
- }
- dst[0] = (FLASH_WORD_SIZE)(cnt - 1);
- for (i=0; i<cnt; i++) {
- dst[i] = src[i];
- }
- dst[0] = FLASH_CMD_PROG_RESUME;
-
- if (flag) {
- enable_interrupts();
- }
-
- return( 0 );
-}
-
-static int
-poll_status( volatile FLASH_WORD_SIZE *addr )
-{
- unsigned long start;
-
- start = get_timer (0);
- /* wait for error or finish */
- while (1) {
- if (*addr == FLASH_STATUS_DONE) {
- if (*addr == FLASH_STATUS_DONE) {
- break;
- }
- }
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- *addr = FLASH_CMD_RESET;
- return (-1);
- }
- }
- *addr = FLASH_CMD_RESET;
- return (0);
-}
-
-/*
- * write_buff return values:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 4 - Flash not identified
- */
-int
-write_buff(flash_info_t *info, uchar *src, ulong udst, ulong cnt)
-{
- volatile FLASH_WORD_SIZE *addr, *dst;
- unsigned long bcnt;
- int flag, i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- return (4);
- }
-
- addr = (volatile FLASH_WORD_SIZE *)(info->start[0]);
- dst = (volatile FLASH_WORD_SIZE *) udst;
-
-#ifdef CONFIG_SYS_FLASH_16BIT
-#error NYI
-#else
- while (cnt > 0) {
- /* Check if buffer write is possible */
- if (cnt > 1 && (((unsigned long)dst & (FLASH_WRITE_BUFFER_SIZE - 1)) == 0)) {
- bcnt = cnt > FLASH_WRITE_BUFFER_SIZE ? FLASH_WRITE_BUFFER_SIZE : cnt;
- /* Check if Flash is (sufficiently) erased */
- for (i=0; i<bcnt; i++) {
- if ((dst[i] & src[i]) != src[i]) {
- return (2);
- }
- }
- if (write_buff2( dst,src,bcnt ) != 0) {
- addr[0] = FLASH_CMD_READ_STATUS;
- }
- if (poll_status( dst ) != 0) {
- return (1);
- }
- cnt -= bcnt;
- dst += bcnt;
- src += bcnt;
- continue;
- }
-
- /* Check if Flash is (sufficiently) erased */
- if ((*dst & *src) != *src) {
- return (2);
- }
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
- addr[0] = FLASH_CMD_ERASE_CONFIRM;
- addr[0] = FLASH_CMD_WRITE;
- *dst++ = *src++;
- /* re-enable interrupts if necessary */
- if (flag) {
- enable_interrupts();
- }
-
- if (poll_status( dst ) != 0) {
- return (1);
- }
- cnt --;
- }
-#endif
- return (0);
-}
-
-int
-flash_real_protect(flash_info_t *info, long sector, int prot)
-{
- volatile FLASH_WORD_SIZE *addr;
- unsigned long start;
-
- addr = (volatile FLASH_WORD_SIZE *)(info->start[sector]);
- *addr = FLASH_CMD_CLEAR_STATUS;
- *addr = FLASH_CMD_PROTECT;
-
- if(prot) {
- *addr = FLASH_CMD_PROTECT_SET;
- } else {
- *addr = FLASH_CMD_PROTECT_CLEAR;
- }
-
- /* wait for error or finish */
- start = get_timer (0);
- while(!(addr[0] & FLASH_STATUS_DONE)){
- if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf("Flash protect timeout at address %lx\n", info->start[sector]);
- addr[0] = FLASH_CMD_RESET;
- return (1);
- }
- }
-
- /* Set software protect flag */
- info->protect[sector] = prot;
- *addr = FLASH_CMD_RESET;
- return (0);
-}
diff --git a/board/funkwerk/vovpn-gw/m88e6060.c b/board/funkwerk/vovpn-gw/m88e6060.c
deleted file mode 100644
index 7aa9593..0000000
--- a/board/funkwerk/vovpn-gw/m88e6060.c
+++ /dev/null
@@ -1,249 +0,0 @@
-/*
- * (C) Copyright 2004
- * Elmeg Communications Systems GmbH, Juergen Selent (j.selent at elmeg.de)
- *
- * Support for the Elmeg VoVPN Gateway Module
- * ------------------------------------------
- * Initialize Marvell M88E6060 Switch
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc8260.h>
-#include <asm/m8260_pci.h>
-#include <net.h>
-#include <miiphy.h>
-
-#include "m88e6060.h"
-
-#if defined(CONFIG_CMD_NET)
-static int prtTab[M88X_PRT_CNT] = { 8, 9, 10, 11, 12, 13 };
-static int phyTab[M88X_PHY_CNT] = { 0, 1, 2, 3, 4 };
-
-static m88x_regCfg_t prtCfg0[] = {
- { 4, 0x3e7c, 0x8000 },
- { 4, 0x3e7c, 0x8003 },
- { 6, 0x0fc0, 0x001e },
- { -1, 0xffff, 0x0000 }
-};
-
-static m88x_regCfg_t prtCfg1[] = {
- { 4, 0x3e7c, 0x8000 },
- { 4, 0x3e7c, 0x8003 },
- { 6, 0x0fc0, 0x001d },
- { -1, 0xffff, 0x0000 }
-};
-
-static m88x_regCfg_t prtCfg2[] = {
- { 4, 0x3e7c, 0x8000 },
- { 4, 0x3e7c, 0x8003 },
- { 6, 0x0fc0, 0x001b },
- { -1, 0xffff, 0x0000 }
-};
-
-static m88x_regCfg_t prtCfg3[] = {
- { 4, 0x3e7c, 0x8000 },
- { 4, 0x3e7c, 0x8003 },
- { 6, 0x0fc0, 0x0017 },
- { -1, 0xffff, 0x0000 }
-};
-
-static m88x_regCfg_t prtCfg4[] = {
- { 4, 0x3e7c, 0x8000 },
- { 4, 0x3e7c, 0x8003 },
- { 6, 0x0fc0, 0x000f },
- { -1, 0xffff, 0x0000 }
-};
-
-static m88x_regCfg_t *prtCfg[M88X_PRT_CNT] = {
- prtCfg0,prtCfg1,prtCfg2,prtCfg3,prtCfg4,NULL
-};
-
-static m88x_regCfg_t phyCfgX[] = {
- { 4, 0xfa1f, 0x01e0 },
- { 0, 0x213f, 0x1200 },
- { 24, 0x81ff, 0x1200 },
- { -1, 0xffff, 0x0000 }
-};
-
-static m88x_regCfg_t *phyCfg[M88X_PHY_CNT] = {
- phyCfgX,phyCfgX,phyCfgX,phyCfgX,NULL
-};
-
-#if 0
-static void
-m88e6060_dump( int devAddr )
-{
- int i, j;
- unsigned short val[6];
-
- printf( "M88E6060 Register Dump\n" );
- printf( "====================================\n" );
- printf( "PortNo 0 1 2 3 4 5\n" );
- for (i=0; i<6; i++)
- miiphy_read( devAddr+prtTab[i],M88X_PRT_STAT,&val[i] );
- printf( "STAT %04hx %04hx %04hx %04hx %04hx %04hx\n",
- val[0],val[1],val[2],val[3],val[4],val[5] );
-
- for (i=0; i<6; i++)
- miiphy_read( devAddr+prtTab[i],M88X_PRT_ID,&val[i] );
- printf( "ID %04hx %04hx %04hx %04hx %04hx %04hx\n",
- val[0],val[1],val[2],val[3],val[4],val[5] );
-
- for (i=0; i<6; i++)
- miiphy_read( devAddr+prtTab[i],M88X_PRT_CNTL,&val[i] );
- printf( "CNTL %04hx %04hx %04hx %04hx %04hx %04hx\n",
- val[0],val[1],val[2],val[3],val[4],val[5] );
-
- for (i=0; i<6; i++)
- miiphy_read( devAddr+prtTab[i],M88X_PRT_VLAN,&val[i] );
- printf( "VLAN %04hx %04hx %04hx %04hx %04hx %04hx\n",
- val[0],val[1],val[2],val[3],val[4],val[5] );
-
- for (i=0; i<6; i++)
- miiphy_read( devAddr+prtTab[i],M88X_PRT_PAV,&val[i] );
- printf( "PAV %04hx %04hx %04hx %04hx %04hx %04hx\n",
- val[0],val[1],val[2],val[3],val[4],val[5] );
-
- for (i=0; i<6; i++)
- miiphy_read( devAddr+prtTab[i],M88X_PRT_RX,&val[i] );
- printf( "RX %04hx %04hx %04hx %04hx %04hx %04hx\n",
- val[0],val[1],val[2],val[3],val[4],val[5] );
-
- for (i=0; i<6; i++)
- miiphy_read( devAddr+prtTab[i],M88X_PRT_TX,&val[i] );
- printf( "TX %04hx %04hx %04hx %04hx %04hx %04hx\n",
- val[0],val[1],val[2],val[3],val[4],val[5] );
-
- printf( "------------------------------------\n" );
- printf( "PhyNo 0 1 2 3 4\n" );
- for (i=0; i<9; i++) {
- for (j=0; j<5; j++) {
- miiphy_read( devAddr+phyTab[j],i,&val[j] );
- }
- printf( "0x%02x %04hx %04hx %04hx %04hx %04hx\n",
- i,val[0],val[1],val[2],val[3],val[4] );
- }
- for (i=0x10; i<0x1d; i++) {
- for (j=0; j<5; j++) {
- miiphy_read( devAddr+phyTab[j],i,&val[j] );
- }
- printf( "0x%02x %04hx %04hx %04hx %04hx %04hx\n",
- i,val[0],val[1],val[2],val[3],val[4] );
- }
-}
-#endif
-
-int
-m88e6060_initialize( int devAddr )
-{
- static char *_f = "m88e6060_initialize:";
- m88x_regCfg_t *p;
- int err;
- int i;
- unsigned short val;
-
- /*** reset all phys into powerdown ************************************/
- for (i=0, err=0; i<M88X_PHY_CNT; i++) {
- err += bb_miiphy_read(NULL, devAddr+phyTab[i],M88X_PHY_CNTL,&val );
- /* keep SpeedLSB, Duplex */
- val &= 0x2100;
- /* set SWReset, AnegEn, PwrDwn, RestartAneg */
- val |= 0x9a00;
- err += bb_miiphy_write(NULL, devAddr+phyTab[i],M88X_PHY_CNTL,val );
- }
- if (err) {
- printf( "%s [ERR] reset phys\n",_f );
- return( -1 );
- }
-
- /*** disable all ports ************************************************/
- for (i=0, err=0; i<M88X_PRT_CNT; i++) {
- err += bb_miiphy_read(NULL, devAddr+prtTab[i],M88X_PRT_CNTL,&val );
- val &= 0xfffc;
- err += bb_miiphy_write(NULL, devAddr+prtTab[i],M88X_PRT_CNTL,val );
- }
- if (err) {
- printf( "%s [ERR] disable ports\n",_f );
- return( -1 );
- }
-
- /*** initialize switch ************************************************/
- /* set switch mac addr */
-#define ea eth_get_dev()->enetaddr
- val = (ea[4] << 8) | ea[5];
- err = bb_miiphy_write(NULL, devAddr+15,M88X_GLB_MAC45,val );
- val = (ea[2] << 8) | ea[3];
- err += bb_miiphy_write(NULL, devAddr+15,M88X_GLB_MAC23,val );
- val = (ea[0] << 8) | ea[1];
-#undef ea
- val &= 0xfeff; /* clear DiffAddr */
- err += bb_miiphy_write(NULL, devAddr+15,M88X_GLB_MAC01,val );
- if (err) {
- printf( "%s [ERR] switch mac address register\n",_f );
- return( -1 );
- }
-
- /* !DiscardExcessive, MaxFrameSize, CtrMode */
- err = bb_miiphy_read(NULL, devAddr+15,M88X_GLB_CNTL,&val );
- val &= 0xd870;
- val |= 0x0500;
- err += bb_miiphy_write(NULL, devAddr+15,M88X_GLB_CNTL,val );
- if (err) {
- printf( "%s [ERR] switch global control register\n",_f );
- return( -1 );
- }
-
- /* LernDis off, ATUSize 1024, AgeTime 5min */
- err = bb_miiphy_read(NULL, devAddr+15,M88X_ATU_CNTL,&val );
- val &= 0x000f;
- val |= 0x2130;
- err += bb_miiphy_write(NULL, devAddr+15,M88X_ATU_CNTL,val );
- if (err) {
- printf( "%s [ERR] atu control register\n",_f );
- return( -1 );
- }
-
- /*** initialize ports *************************************************/
- for (i=0; i<M88X_PRT_CNT; i++) {
- if ((p = prtCfg[i]) == NULL) {
- continue;
- }
- while (p->reg != -1) {
- err = 0;
- err += bb_miiphy_read(NULL, devAddr+prtTab[i],p->reg,&val );
- val &= p->msk;
- val |= p->val;
- err += bb_miiphy_write(NULL, devAddr+prtTab[i],p->reg,val );
- if (err) {
- printf( "%s [ERR] config port %d register %d\n",_f,i,p->reg );
- /* XXX what todo */
- }
- p++;
- }
- }
-
- /*** initialize phys **************************************************/
- for (i=0; i<M88X_PHY_CNT; i++) {
- if ((p = phyCfg[i]) == NULL) {
- continue;
- }
- while (p->reg != -1) {
- err = 0;
- err += bb_miiphy_read(NULL, devAddr+phyTab[i],p->reg,&val );
- val &= p->msk;
- val |= p->val;
- err += bb_miiphy_write(NULL, devAddr+phyTab[i],p->reg,val );
- if (err) {
- printf( "%s [ERR] config phy %d register %d\n",_f,i,p->reg );
- /* XXX what todo */
- }
- p++;
- }
- }
- udelay(100000);
- return( 0 );
-}
-#endif
diff --git a/board/funkwerk/vovpn-gw/m88e6060.h b/board/funkwerk/vovpn-gw/m88e6060.h
deleted file mode 100644
index 5f7f6d1..0000000
--- a/board/funkwerk/vovpn-gw/m88e6060.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * (C) Copyright 2004
- * Elmeg Communications Systems GmbH, Juergen Selent (j.selent at elmeg.de)
- *
- * Support for the Elmeg VoVPN Gateway Module
- * ------------------------------------------
- * Initialize Marvell M88E6060 Switch
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _INC_m88e6060_h_
-#define _INC_m88e6060_h_
-
-/* ************************************************************************** */
-/* *** DEFINES ************************************************************** */
-
-/* switch hw */
-#define M88X_PRT_CNT 6
-#define M88X_PHY_CNT 5
-
-/* phy register offsets */
-#define M88X_PHY_CNTL 0x00
-#define M88X_PHY_STAT 0x00
-#define M88X_PHY_ID0 0x02
-#define M88X_PHY_ID1 0x03
-#define M88X_PHY_ANEG_ADV 0x04
-#define M88X_PHY_LPA 0x05
-#define M88X_PHY_ANEG_EXP 0x06
-#define M88X_PHY_NPT 0x07
-#define M88X_PHY_LPNP 0x08
-
-/* port register offsets */
-#define M88X_PRT_STAT 0x00
-#define M88X_PRT_ID 0x03
-#define M88X_PRT_CNTL 0x04
-#define M88X_PRT_VLAN 0x06
-#define M88X_PRT_PAV 0x0b
-#define M88X_PRT_RX 0x10
-#define M88X_PRT_TX 0x11
-
-/* global/atu register offsets */
-#define M88X_GLB_STAT 0x00
-#define M88X_GLB_MAC01 0x01
-#define M88X_GLB_MAC23 0x02
-#define M88X_GLB_MAC45 0x03
-#define M88X_GLB_CNTL 0x04
-#define M88X_ATU_CNTL 0x0a
-#define M88X_ATU_OP 0x0b
-
-/* id0 register - 0x02 */
-#define M88X_PHY_ID0_VALUE 0x0141
-
-/* id1 register - 0x03 */
-#define M88X_PHY_ID1_VALUE 0x0c80 /* without revision ! */
-
-
-/* misc */
-#define M88E6060_ID ((M88X_PHY_ID0_VALUE<<16) | M88X_PHY_ID1_VALUE)
-
-/* ************************************************************************** */
-/* *** TYPEDEFS ************************************************************* */
-
-typedef struct {
- int reg;
- unsigned short msk;
- unsigned short val;
-} m88x_regCfg_t;
-
-/* ************************************************************************** */
-/* *** PROTOTYPES *********************************************************** */
-
-extern int m88e6060_initialize( int );
-
-#endif /* _INC_m88e6060_h_ */
diff --git a/board/funkwerk/vovpn-gw/vovpn-gw.c b/board/funkwerk/vovpn-gw/vovpn-gw.c
deleted file mode 100644
index c2aad6e..0000000
--- a/board/funkwerk/vovpn-gw/vovpn-gw.c
+++ /dev/null
@@ -1,363 +0,0 @@
-/*
- * (C) Copyright 2004
- * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de)
- *
- * Support for the Elmeg VoVPN Gateway Module
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc8260.h>
-#include <asm/m8260_pci.h>
-#include <miiphy.h>
-#include <linux/compiler.h>
-
-#include "m88e6060.h"
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-const iop_conf_t iop_conf_tab[4][32] = {
- /* Port A configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PA31 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1252 */
- /* PA30 */ { 1, 0, 0, 0, 0, 0 }, /* GPI BP_RES */
- /* PA29 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1253 */
- /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 RMII TX_EN */
- /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RMII CRS_DV */
- /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RMII RX_ERR */
- /* PA25 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */
- /* PA24 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */
- /* PA23 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */
- /* PA22 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */
- /* PA21 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */
- /* PA20 */ { 1, 0, 0, 1, 0, 1 }, /* GPO LED STATUS */
- /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 RMII TxD[1] */
- /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 RMII TxD[0] */
- /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RMII RxD[0] */
- /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RMII RxD[1] */
- /* PA15 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1255 */
- /* PA14 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP???? */
- /* PA13 */ { 1, 0, 0, 1, 0, 1 }, /* GPO EN_BCTL1 XXX jse */
- /* PA12 */ { 1, 0, 0, 1, 0, 0 }, /* GPO SWITCH RESET */
- /* PA11 */ { 1, 0, 0, 1, 0, 0 }, /* GPO DSP SL1 RESET */
- /* PA10 */ { 1, 0, 0, 1, 0, 0 }, /* GPO DSP SL2 RESET */
- /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
- /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
- /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */
- /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */
- /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */
- /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */
- /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */
- /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */
- /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */
- /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* pin does not exit */
- },
-
- /* Port B configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PB31 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1257 */
- /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RMII CRS_DV */
- /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 RMII TX_EN */
- /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RMII RX_ERR */
- /* PB27 */ { 1, 1, 1, 0, 1, 0 }, /* TDM_B2 L1TXD XXX val=0 */
- /* PB26 */ { 1, 1, 1, 0, 1, 0 }, /* TDM_B2 L1RXD XXX val,dr */
- /* PB25 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1259 */
- /* PB24 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_B2 L1RSYNC */
- /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 RMII TxD[1] */
- /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 RMII TxD[0] */
- /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RMII RxD[0] */
- /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RMII RxD[1] */
- /* PB19 */ { 1, 0, 0, 1, 0, 1 }, /* GPO PHY MDC */
- /* PB18 */ { 1, 0, 0, 0, 0, 0 }, /* GPIO PHY MDIO */
- /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin does not exist */
- },
-
- /* Port C */
- { /* conf ppar psor pdir podr pdat */
- /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PC29 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1183 */
- /* PC28 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1184 */
- /* PC27 */ { 1, 1, 0, 0, 0, 0 }, /* CLK5 TDM_A1 RX */
- /* PC26 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1185 */
- /* PC25 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1178 */
- /* PC24 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1186 */
- /* PC23 */ { 1, 1, 0, 0, 0, 0 }, /* CLK9 TDM_B2 RX */
- /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* CLK10 FCC1 RMII REFCLK */
- /* PC21 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1187 */
- /* PC20 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1182 */
- /* PC19 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1188 */
- /* PC18 */ { 1, 0, 0, 1, 0, 0 }, /* GPO HW RESET */
- /* PC17 */ { 1, 1, 0, 1, 0, 0 }, /* BRG8 SWITCH CLKIN */
- /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* CLK16 FCC2 RMII REFCLK */
- /* PC15 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL1_MTYPE_3 */
- /* PC14 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL1_MTYPE_2 */
- /* PC13 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL1_MTYPE_1 */
- /* PC12 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL1_MTYPE_0 */
- /* PC11 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1176 */
- /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1177 */
- /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL2_MTYPE_3 */
- /* PC8 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL2_MTYPE_2 */
- /* PC7 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL2_MTYPE_1 */
- /* PC6 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL2_MTYPE_0 */
- /* PC5 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
- /* PC4 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
- /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PC1 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1192 */
- /* PC0 */ { 1, 0, 0, 0, 0, 0 }, /* GPI RACK */
- },
-
- /* Port D */
- { /* conf ppar psor pdir podr pdat */
- /* PD31 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1193 */
- /* PD30 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1194 */
- /* PD29 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1195 */
- /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PD25 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1179 */
- /* PD24 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1180 */
- /* PD23 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1181 */
- /* PD22 */ { 1, 1, 1, 0, 1, 0 }, /* TDM_A2 L1TXD */
- /* PD21 */ { 1, 1, 1, 0, 1, 0 }, /* TDM_A2 L1RXD */
- /* PD20 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A2 L1RSYNC */
- /* PD19 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1196 */
- /* PD18 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1197 */
- /* PD17 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1198 */
- /* PD16 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1199 */
- /* PD15 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1250 */
- /* PD14 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1251 */
- /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PD7 */ { 0, 0, 0, 1, 0, 0 }, /* GPO FL_BYTE */
- /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
- /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin does not exist */
- }
-};
-
-void reset_phy (void)
-{
- volatile ioport_t *iop;
-#if defined(CONFIG_CMD_NET)
- int i;
- unsigned short val;
-#endif
-
- iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0);
-
- /* Reset the PHY */
- iop->pdat &= 0xfff7ffff; /* PA12 = |SWITCH_RESET */
-#if defined(CONFIG_CMD_NET)
- udelay(20000);
- iop->pdat |= 0x00080000;
- for (i=0; i<100; i++) {
- udelay(20000);
- if (bb_miiphy_read("FCC1", CONFIG_SYS_PHY_ADDR,2,&val ) == 0) {
- break;
- }
- }
- /* initialize switch */
- m88e6060_initialize( CONFIG_SYS_PHY_ADDR );
-#endif
-}
-
-static unsigned long UPMATable[] = {
- 0x8fffec00, 0x0ffcfc00, 0x0ffcfc00, 0x0ffcfc00, /* Words 0 to 3 */
- 0x0ffcfc04, 0x3ffdfc00, 0xfffffc01, 0xfffffc01, /* Words 4 to 7 */
- 0xfffffc00, 0xfffffc04, 0xfffffc01, 0xfffffc00, /* Words 8 to 11 */
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 12 to 15 */
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 16 to 19 */
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 20 to 23 */
- 0x8fffec00, 0x00fffc00, 0x00fffc00, 0x00fffc00, /* Words 24 to 27 */
- 0x0ffffc04, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 28 to 31 */
- 0xfffffc00, 0xfffffc01, 0xfffffc01, 0xfffffc00, /* Words 32 to 35 */
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 36 to 39 */
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 40 to 43 */
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 44 to 47 */
- 0xfffffc00, 0xfffffc04, 0xfffffc01, 0xfffffc00, /* Words 48 to 51 */
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 52 to 55 */
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 56 to 59 */
- 0xffffec00, 0xffffec04, 0xffffec00, 0xfffffc01 /* Words 60 to 63 */
-};
-
-int board_early_init_f (void)
-{
- volatile immap_t *immap;
- volatile memctl8260_t *memctl;
- volatile unsigned char *dummy;
- int i;
-
- immap = (immap_t *) CONFIG_SYS_IMMR;
- memctl = &immap->im_memctl;
-
-#if 0
- /* CS2-5 - DSP via UPMA */
- dummy = (volatile unsigned char *) (memctl->memc_br2 & BRx_BA_MSK);
- memctl->memc_mar = 0;
- memctl->memc_mamr = MxMR_OP_WARR;
- for (i = 0; i < 64; i++) {
- memctl->memc_mdr = UPMATable[i];
- *dummy = 0;
- }
- memctl->memc_mamr = 0x00044440;
-#else
- /* CS7 - DPRAM via UPMA */
- dummy = (volatile unsigned char *) (memctl->memc_br7 & BRx_BA_MSK);
- memctl->memc_mar = 0;
- memctl->memc_mamr = MxMR_OP_WARR;
- for (i = 0; i < 64; i++) {
- memctl->memc_mdr = UPMATable[i];
- *dummy = 0;
- }
- memctl->memc_mamr = 0x00044440;
-#endif
- return 0;
-}
-
-int misc_init_r (void)
-{
- volatile ioport_t *iop;
- __maybe_unused unsigned char temp;
-#if 0
- /* DUMP UPMA RAM */
- volatile immap_t *immap;
- volatile memctl8260_t *memctl;
- volatile unsigned char *dummy;
- unsigned char c;
- int i;
-
- immap = (immap_t *) CONFIG_SYS_IMMR;
- memctl = &immap->im_memctl;
-
-
- dummy = (volatile unsigned char *) (memctl->memc_br7 & BRx_BA_MSK);
- memctl->memc_mar = 0;
- memctl->memc_mamr = MxMR_OP_RARR;
- for (i = 0; i < 64; i++) {
- c = *dummy;
- printf( "UPMA[%02d]: 0x%08lx,0x%08lx: 0x%08lx\n",i,
- memctl->memc_mamr,
- memctl->memc_mar,
- memctl->memc_mdr );
- }
- memctl->memc_mamr = 0x00044440;
-#endif
- /* enable buffers (DSP, DPRAM) */
- iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0);
- iop->pdat &= 0xfffbffff; /* PA13 = |EN_M_BCTL1 */
-
- /* destroy DPRAM magic */
- *(volatile unsigned char *)0xf0500000 = 0x00;
-
- /* clear any pending DPRAM irq */
- temp = *(volatile unsigned char *)0xf05003ff;
-
- /* write module-id into DPRAM */
- *(volatile unsigned char *)0xf0500201 = 0x50;
-
- return 0;
-}
-
-#if defined(CONFIG_HAVE_OWN_RESET)
-int
-do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- volatile ioport_t *iop;
-
- iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 2);
- iop->pdat |= 0x00002000; /* PC18 = HW_RESET */
- return 1;
-}
-#endif /* CONFIG_HAVE_OWN_RESET */
-
-#define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1)
-
-phys_size_t initdram (int board_type)
-{
-#ifndef CONFIG_SYS_RAMBOOT
- volatile immap_t *immap;
- volatile memctl8260_t *memctl;
- volatile uchar *ramaddr;
- int i;
- uchar c;
-
- immap = (immap_t *) CONFIG_SYS_IMMR;
- memctl = &immap->im_memctl;
- ramaddr = (uchar *) CONFIG_SYS_SDRAM_BASE;
- c = 0xff;
-
- immap->im_siu_conf.sc_ppc_acr = 0x02;
- immap->im_siu_conf.sc_ppc_alrh = 0x01267893;
- immap->im_siu_conf.sc_ppc_alrl = 0x89abcdef;
- immap->im_siu_conf.sc_tescr1 = 0x00000000;
- immap->im_siu_conf.sc_tescr2 = 0x00000000;
-
- memctl->memc_mptpr = CONFIG_SYS_MPTPR;
- memctl->memc_psrt = CONFIG_SYS_PSRT;
- memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
- memctl->memc_br1 = CONFIG_SYS_SDRAM_BASE | CONFIG_SYS_BR1_PRELIM;
-
- /* Precharge all banks */
- memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x28000000;
- *ramaddr = c;
-
- /* CBR refresh */
- memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x08000000;
- for (i = 0; i < 8; i++)
- *ramaddr = c;
-
- /* Mode Register write */
- memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x18000000;
- *ramaddr = c;
-
- /* Refresh enable */
- memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x40000000;
- *ramaddr = c;
-#endif /* CONFIG_SYS_RAMBOOT */
-
- return (CONFIG_SYS_SDRAM_SIZE);
-}
-
-int checkboard (void)
-{
-#ifdef CONFIG_CLKIN_66MHz
- puts ("Board: Elmeg VoVPN Gateway Module (66MHz)\n");
-#else
- puts ("Board: Elmeg VoVPN Gateway Module (100MHz)\n");
-#endif
- return 0;
-}
diff --git a/configs/VoVPN-GW_66MHz_defconfig b/configs/VoVPN-GW_66MHz_defconfig
deleted file mode 100644
index 4eb931e..0000000
--- a/configs/VoVPN-GW_66MHz_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="CLKIN_66MHz"
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_VOVPN_GW=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 46b6dbe..7e4eaef 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+VoVPN-GW powerpc mpc8260 - -
ep8260 powerpc mpc8260 - - Frank Panno <fpanno@delphintech.com>
ppmc8260 powerpc mpc8260 - - Brad Kemp <Brad.Kemp@seranoa.com>
sacsng powerpc mpc8260 - - Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
diff --git a/include/configs/VoVPN-GW.h b/include/configs/VoVPN-GW.h
deleted file mode 100644
index 1ceef11..0000000
--- a/include/configs/VoVPN-GW.h
+++ /dev/null
@@ -1,399 +0,0 @@
-/*
- * (C) Copyright 2004
- * Elmeg Communications Systems GmbH, Juergen Selent (j.selent at elmeg.de)
- *
- * Support for the Elmeg VoVPN Gateway Module
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* define cpu used */
-#define CONFIG_MPC8272 1
-
-/* define busmode: 8260 */
-#undef CONFIG_BUSMODE_60x
-
-#define CONFIG_SYS_TEXT_BASE 0xfff00000
-
-/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
-#ifdef CONFIG_CLKIN_66MHz
-#define CONFIG_8260_CLKIN 66666666 /* in Hz */
-#else
-#define CONFIG_8260_CLKIN 100000000 /* in Hz */
-#endif
-
-/* call board_early_init_f */
-#define CONFIG_BOARD_EARLY_INIT_F 1
-
-/* have misc_init_r() function */
-#define CONFIG_MISC_INIT_R 1
-
-/* have reset_phy_r() function */
-#define CONFIG_RESET_PHY_R 1
-
-/* have special reset function */
-#define CONFIG_HAVE_OWN_RESET 1
-
-/* allow serial and ethaddr to be overwritten */
-#define CONFIG_ENV_OVERWRITE
-
-/* watchdog disabled */
-#undef CONFIG_WATCHDOG
-
-/* include support for bzip2 compressed images */
-#undef CONFIG_BZIP2
-
-/* status led */
-#undef CONFIG_STATUS_LED /* XXX jse */
-
-/* vendor parameter protection */
-#define CONFIG_ENV_OVERWRITE
-
-/*
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- */
-#define CONFIG_CONS_ON_SMC
-#undef CONFIG_CONS_ON_SCC
-#undef CONFIG_CONS_NONE
-#define CONFIG_CONS_INDEX 1
-
-/* serial port default baudrate */
-#define CONFIG_BAUDRATE 115200
-
-/* echo on for serial download */
-#define CONFIG_LOADS_ECHO 1
-
-/* don't allow baudrate change */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE
-
-/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
- */
-#undef CONFIG_ETHER_ON_SCC
-#define CONFIG_ETHER_ON_FCC
-#undef CONFIG_ETHER_NONE
-
-#ifdef CONFIG_ETHER_ON_FCC
-
-/* which SCC/FCC channel for ethernet */
-#define CONFIG_ETHER_INDEX 1
-
-/* Marvell Switch SMI base addr */
-#define CONFIG_SYS_PHY_ADDR 0x10
-
-/* FCC1 RMII REFCLK is CLK10 */
-#define CONFIG_SYS_CMXFCR_VALUE CMXFCR_TF1CS_CLK10
-#define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_TF1CS_MSK)
-
-/* BDs and buffers on 60x bus */
-#define CONFIG_SYS_CPMFCR_RAMTYPE 0
-
-/* Local Protect, Full duplex, Flowcontrol, RMII */
-#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_LPB|FCC_PSMR_FDE|\
- FCC_PSMR_FCE|FCC_PSMR_RMII)
-
-/* bit-bang MII PHY management */
-#define CONFIG_BITBANGMII
-
-#define MDIO_PORT 1 /* Port B */
-
-#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
- (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
-#define MDC_DECLARE MDIO_DECLARE
-
-#define CONFIG_SYS_MDIO_PIN 0x00002000 /* PB18 */
-#define CONFIG_SYS_MDC_PIN 0x00001000 /* PB19 */
-#define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN)
-#define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
-#define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0)
-#define MDIO(bit) if(bit) iop->pdat |= CONFIG_SYS_MDIO_PIN; \
- else iop->pdat &= ~CONFIG_SYS_MDIO_PIN
-#define MDC(bit) if(bit) iop->pdat |= CONFIG_SYS_MDC_PIN; \
- else iop->pdat &= ~CONFIG_SYS_MDC_PIN
-#define MIIDELAY udelay(1)
-
-#endif
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-
-#define CONFIG_CMD_BDI
-#define CONFIG_CMD_CONSOLE
-#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_IMI
-#define CONFIG_CMD_IMLS
-#define CONFIG_CMD_LOADB
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_MISC
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_RUN
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_SOURCE
-
-
-/*
- * boot options & environment
- */
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_BOOTCOMMAND "run flash_self"
-#undef CONFIG_BOOTARGS
-#define CONFIG_EXTRA_ENV_SETTINGS \
-"clean_nv=erase fff20000 ffffffff\0" \
-"update_boss=tftp 100000 PPC/logic157.bin; protect off fff00000 ffffffff; erase fff00000 ffffffff; cp.b 100000 fff00000 ${filesize}; tftp 100000 PPC/bootmon157.bin; cp.b 100000 fff20000 ${filesize}\0" \
-"update_lx=tftp 100000 ${kernel}; erase ${kernel_addr} ffefffff; cp.b 100000 ${kernel_addr} ${filesize}\0" \
-"update_fs=tftp 100000 ${fs}.${fstype}; erase ff840000 ffdfffff; cp.b 100000 ff840000 ${filesize}\0" \
-"update_ub=tftp 100000 ${uboot}; protect off fff00000 fff1ffff; erase fff00000 fff1ffff; cp.b 100000 fff00000 ${filesize}; protect off ff820000 ff83ffff; erase ff820000 ff83ffff\0" \
-"flashargs=setenv bootargs root=${rootdev} rw rootfstype=${fstype}\0" \
-"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
-"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off\0" \
-"addmisc=setenv bootargs ${bootargs} console=${console},${baudrate} ethaddr=${ethaddr} panic=1\0" \
-"net_nfs=tftpboot 400000 ${kernel}; run nfsargs addip addmisc; bootm\0" \
-"net_self=tftpboot 400000 ${kernel}; run flashargs addmisc; bootm\0" \
-"flash_self=run flashargs addmisc; bootm ${kernel_addr}\0" \
-"flash_nfs=run nfsargs addip addmisc; bootm ${kernel_addr}\0" \
-"fstype=cramfs\0" \
-"rootpath=/root_fs\0" \
-"uboot=PPC/u-boot.bin\0" \
-"kernel=PPC/uImage\0" \
-"kernel_addr=ffe00000\0" \
-"fs=PPC/root_fs\0" \
-"console=ttyS0\0" \
-"netdev=eth0\0" \
-"rootdev=31:3\0" \
-"ethaddr=00:09:4f:01:02:03\0" \
-"ipaddr=10.0.0.201\0" \
-"netmask=255.255.255.0\0" \
-"serverip=10.0.0.136\0" \
-"gatewayip=10.0.0.10\0" \
-"hostname=bastard\0" \
-""
-
-
-/*
- * miscellaneous configurable options
- */
-
-/* undef to save memory */
-#define CONFIG_SYS_LONGHELP
-
-/* monitor command prompt */
-
-/* console i/o buffer size */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024
-#else
-#define CONFIG_SYS_CBSIZE 256
-#endif
-
-/* print buffer size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-
-/* max number of command args */
-#define CONFIG_SYS_MAXARGS 16
-
-/* boot argument buffer size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-/* memtest works on */
-#define CONFIG_SYS_MEMTEST_START 0x00100000
-/* 1 ... 15 MB in DRAM */
-#define CONFIG_SYS_MEMTEST_END 0x00f00000
-/* full featured memtest */
-#define CONFIG_SYS_ALT_MEMTEST
-
-/* default load address */
-#define CONFIG_SYS_LOAD_ADDR 0x00100000
-
-/* decrementer freq: 1 ms ticks */
-
-/* configure flash */
-#define CONFIG_SYS_FLASH_BASE 0xff800000
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 64
-#define CONFIG_SYS_FLASH_SIZE 8
-#undef CONFIG_SYS_FLASH_16BIT
-#define CONFIG_SYS_FLASH_ERASE_TOUT 240000
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500
-#define CONFIG_SYS_FLASH_LOCK_TOUT 500
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000
-#define CONFIG_SYS_FLASH_PROTECTION
-
-/* monitor in flash */
-#define CONFIG_SYS_MONITOR_OFFSET 0x00700000
-
-/* environment in flash */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00020000)
-#define CONFIG_ENV_SIZE 0x00020000
-#define CONFIG_ENV_SECT_SIZE 0x00020000
-
-/*
- * Initial memory map for linux
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
-
-/* hard reset configuration words */
-#ifdef CONFIG_CLKIN_66MHz
-#define CONFIG_SYS_HRCW_MASTER 0x04643050
-#else
-#error NO HRCW FOR 100MHZ SPECIFIED !!!
-#endif
-#define CONFIG_SYS_HRCW_SLAVE1 0x00000000
-#define CONFIG_SYS_HRCW_SLAVE2 0x00000000
-#define CONFIG_SYS_HRCW_SLAVE3 0x00000000
-#define CONFIG_SYS_HRCW_SLAVE4 0x00000000
-#define CONFIG_SYS_HRCW_SLAVE5 0x00000000
-#define CONFIG_SYS_HRCW_SLAVE6 0x00000000
-#define CONFIG_SYS_HRCW_SLAVE7 0x00000000
-
-/* internal memory mapped register */
-#define CONFIG_SYS_IMMR 0xF0000000
-
-/* definitions for initial stack pointer and data area (in DPRAM) */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start@0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_SIZE (32*1024*1024)
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_FLASH (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_OFFSET)
-#define CONFIG_SYS_MONITOR_LEN 0x00020000
-#define CONFIG_SYS_MALLOC_LEN 0x00020000
-
-/* cache configuration */
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* for MPC8260 */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of above */
-#endif
-
-/*
- * HIDx - Hardware Implementation-dependent Registers
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|\
- HID0_ICFI|HID0_DCI|HID0_IFEM|HID0_ABE)
-#define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE)
-#define CONFIG_SYS_HID2 0
-
-/* RMR - reset mode register - turn on checkstop reset enable */
-#define CONFIG_SYS_RMR RMR_CSRE
-
-/* BCR - bus configuration */
-#define CONFIG_SYS_BCR 0x00000000
-
-/* SIUMCR - siu module configuration */
-#define CONFIG_SYS_SIUMCR 0x4905c000
-
-/* SYPCR - system protection control */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR 0xffffff87
-#else
-#define CONFIG_SYS_SYPCR 0xffffff83
-#endif
-
-/* TMCNTSC - time counter status and control */
-/* clear interrupts XXX jse */
-/*#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR) */
-#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|\
- TMCNTSC_TCF|TMCNTSC_TCE)
-
-/* PISCR - periodic interrupt status and control */
-/* clear interrupts XXX jse */
-/*#define CONFIG_SYS_PISCR (PISCR_PS) */
-#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
-
-/* SCCR - system clock control */
-#define CONFIG_SYS_SCCR 0x000001a9
-
-/* RCCR - risc controller configuration */
-#define CONFIG_SYS_RCCR 0
-
-/*
- * MEMORY MAP
- * ----------
- * CS0 - FLASH 8MB/8Bit base=0xff800000 (boot: 0xfe000000, 8x mirrored)
- * CS1 - SDRAM 32MB/64Bit base=0x00000000
- * CS2 - DSP/SL1 1MB/16Bit base=0xf0100000
- * CS3 - DSP/SL2 1MB/16Bit base=0xf0200000
- * CS4 - DSP/SL3 1MB/16Bit base=0xf0300000
- * CS5 - DSP/SL4 1MB/16Bit base=0xf0400000
- * CS7 - DPRAM 1KB/8Bit base=0xf0500000, size=32KB (32x mirrored)
- * x - IMMR 384KB base=0xf0000000
- */
-/* XXX jse 100MHz TODO */
-#define CONFIG_SYS_BR0_PRELIM 0xff800801
-#define CONFIG_SYS_OR0_PRELIM 0xff801e44
-#define CONFIG_SYS_BR1_PRELIM 0x00000041
-#define CONFIG_SYS_OR1_PRELIM 0xfe002ec0
-#if 1
-#define CONFIG_SYS_BR2_PRELIM 0xf0101001
-#define CONFIG_SYS_OR2_PRELIM 0xfff00ef4
-#define CONFIG_SYS_BR3_PRELIM 0xf0201001
-#define CONFIG_SYS_OR3_PRELIM 0xfff00ef4
-#define CONFIG_SYS_BR4_PRELIM 0xf0301001
-#define CONFIG_SYS_OR4_PRELIM 0xfff00ef4
-#define CONFIG_SYS_BR5_PRELIM 0xf0401001
-#define CONFIG_SYS_OR5_PRELIM 0xfff00ef4
-#else
-#define CONFIG_SYS_BR2_PRELIM 0xf0101081
-#define CONFIG_SYS_OR2_PRELIM 0xfff00104
-#define CONFIG_SYS_BR3_PRELIM 0xf0201081
-#define CONFIG_SYS_OR3_PRELIM 0xfff00104
-#define CONFIG_SYS_BR4_PRELIM 0xf0301081
-#define CONFIG_SYS_OR4_PRELIM 0xfff00104
-#define CONFIG_SYS_BR5_PRELIM 0xf0401081
-#define CONFIG_SYS_OR5_PRELIM 0xfff00104
-#endif
-#define CONFIG_SYS_BR7_PRELIM 0xf0500881
-#define CONFIG_SYS_OR7_PRELIM 0xffff8104
-#define CONFIG_SYS_MPTPR 0x2700
-#define CONFIG_SYS_PSDMR 0x822a2452 /* optimal */
-/*#define CONFIG_SYS_PSDMR 0x822a48a3 */ /* relaxed */
-#define CONFIG_SYS_PSRT 0x1a
-
-/* "bad" address */
-#define CONFIG_SYS_RESET_ADDRESS 0x40000000
-
-#endif /* __CONFIG_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [U-Boot] [PATCH 18/26] mpc8260: remove MPC8266ADS board support
2014-12-15 14:26 [U-Boot] [PATCH 0/26] Start removing non-generic boards Masahiro Yamada
` (16 preceding siblings ...)
2014-12-15 14:26 ` [U-Boot] [PATCH 17/26] mpc8260: remove VoVPN-GW " Masahiro Yamada
@ 2014-12-15 14:26 ` Masahiro Yamada
2015-01-05 18:21 ` Tom Rini
2014-12-15 14:26 ` [U-Boot] [PATCH 19/26] mpc8260: remove PM825, PM826, PM828 " Masahiro Yamada
` (9 subsequent siblings)
27 siblings, 1 reply; 55+ messages in thread
From: Masahiro Yamada @ 2014-12-15 14:26 UTC (permalink / raw)
To: u-boot
This board is still a non-generic board.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Rune Torgersen <runet@innovsys.com>
---
arch/powerpc/cpu/mpc8260/Kconfig | 4 -
arch/powerpc/cpu/mpc8260/pci.c | 57 +---
board/freescale/mpc8266ads/Kconfig | 12 -
board/freescale/mpc8266ads/MAINTAINERS | 6 -
board/freescale/mpc8266ads/Makefile | 8 -
board/freescale/mpc8266ads/flash.c | 493 ---------------------------
board/freescale/mpc8266ads/mpc8266ads.c | 582 --------------------------------
configs/MPC8266ADS_defconfig | 3 -
doc/README.scrapyard | 1 +
include/configs/MPC8266ADS.h | 563 ------------------------------
10 files changed, 3 insertions(+), 1726 deletions(-)
delete mode 100644 board/freescale/mpc8266ads/Kconfig
delete mode 100644 board/freescale/mpc8266ads/MAINTAINERS
delete mode 100644 board/freescale/mpc8266ads/Makefile
delete mode 100644 board/freescale/mpc8266ads/flash.c
delete mode 100644 board/freescale/mpc8266ads/mpc8266ads.c
delete mode 100644 configs/MPC8266ADS_defconfig
delete mode 100644 include/configs/MPC8266ADS.h
diff --git a/arch/powerpc/cpu/mpc8260/Kconfig b/arch/powerpc/cpu/mpc8260/Kconfig
index 15742d9..d9dba83 100644
--- a/arch/powerpc/cpu/mpc8260/Kconfig
+++ b/arch/powerpc/cpu/mpc8260/Kconfig
@@ -34,9 +34,6 @@ config TARGET_PM826
config TARGET_PM828
bool "Support PM828"
-config TARGET_MPC8266ADS
- bool "Support MPC8266ADS"
-
config TARGET_KM82XX
bool "Support km82xx"
@@ -46,7 +43,6 @@ source "board/atc/Kconfig"
source "board/cpu86/Kconfig"
source "board/cpu87/Kconfig"
source "board/ep82xxm/Kconfig"
-source "board/freescale/mpc8266ads/Kconfig"
source "board/gw8260/Kconfig"
source "board/iphase4539/Kconfig"
source "board/keymile/km82xx/Kconfig"
diff --git a/arch/powerpc/cpu/mpc8260/pci.c b/arch/powerpc/cpu/mpc8260/pci.c
index f7bb05d..079b6e6 100644
--- a/arch/powerpc/cpu/mpc8260/pci.c
+++ b/arch/powerpc/cpu/mpc8260/pci.c
@@ -22,7 +22,7 @@
#include <fdt_support.h>
#endif
-#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 || defined CONFIG_PM826
+#if defined CONFIG_PM826
DECLARE_GLOBAL_DATA_PTR;
#endif
@@ -236,34 +236,6 @@ void pci_mpc8250_init (struct pci_controller *hose)
CONFIG_SYS_IMMR + PCI_CFG_DATA_REG);
/*
- * Setting required to enable local bus for PCI (SIUMCR [LBPC]).
- */
-#ifdef CONFIG_MPC8266ADS
- immap->im_siu_conf.sc_siumcr =
- (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
- | SIUMCR_LBPC01;
-#elif defined CONFIG_MPC8272
- immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
- ~SIUMCR_BBD &
- ~SIUMCR_ESE &
- ~SIUMCR_PBSE &
- ~SIUMCR_CDIS &
- ~SIUMCR_DPPC11 &
- ~SIUMCR_L2CPC11 &
- ~SIUMCR_LBPC11 &
- ~SIUMCR_APPC11 &
- ~SIUMCR_CS10PC11 &
- ~SIUMCR_BCTLC11 &
- ~SIUMCR_MMR11)
- | SIUMCR_DPPC11
- | SIUMCR_L2CPC01
- | SIUMCR_LBPC00
- | SIUMCR_APPC10
- | SIUMCR_CS10PC00
- | SIUMCR_BCTLC00
- | SIUMCR_MMR11;
-#else
- /*
* Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
* and local bus for PCI (SIUMCR [LBPC]).
*/
@@ -274,7 +246,6 @@ void pci_mpc8250_init (struct pci_controller *hose)
SIUMCR_LBPC01 |
SIUMCR_CS10PC01 |
SIUMCR_APPC10;
-#endif
/* Make PCI lowest priority */
/* Each 4 bits is a device bus request and the MS 4bits
@@ -304,24 +275,11 @@ void pci_mpc8250_init (struct pci_controller *hose)
immap->im_memctl.memc_pcimsk0 = PCIMSK0_MASK;
immap->im_memctl.memc_pcibr0 = PCI_MSTR0_LOCAL | PCIBR_ENABLE;
-#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
- immap->im_memctl.memc_pcimsk1 = PCIMSK1_MASK;
- immap->im_memctl.memc_pcibr1 = PCI_MSTR1_LOCAL | PCIBR_ENABLE;
-#endif
-
/* Release PCI RST (by default the PCI RST signal is held low) */
immap->im_pci.pci_gcr = cpu_to_le32 (PCIGCR_PCI_BUS_EN);
/* give it some time */
{
-#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
- /* Give the PCI cards more time to initialize before query
- This might be good for other boards also
- */
- int i;
-
- for (i = 0; i < 1000; ++i)
-#endif
udelay (1000);
}
@@ -358,11 +316,7 @@ void pci_mpc8250_init (struct pci_controller *hose)
immap->im_pci.pci_picmr0 = cpu_to_le32 (PICMR0_MASK_ATTRIB); /* Size & attribute */
/* See above for description - puts PCI request as highest priority */
-#ifdef CONFIG_MPC8272
- immap->im_siu_conf.sc_ppc_alrh = 0x01236745;
-#else
immap->im_siu_conf.sc_ppc_alrh = 0x03124567;
-#endif
/* Park the bus on the PCI */
immap->im_siu_conf.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;
@@ -388,7 +342,7 @@ void pci_mpc8250_init (struct pci_controller *hose)
hose->last_busno = 0xff;
/* System memory space */
-#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 || defined CONFIG_PM826
+#if defined CONFIG_PM826
pci_set_region (hose->regions + 0,
PCI_SLV_MEM_BUS,
PCI_SLV_MEM_LOCAL,
@@ -401,17 +355,10 @@ void pci_mpc8250_init (struct pci_controller *hose)
#endif
/* PCI memory space */
-#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
- pci_set_region (hose->regions + 1,
- PCI_MSTR_MEMIO_BUS,
- PCI_MSTR_MEMIO_LOCAL,
- PCI_MSTR_MEMIO_SIZE, PCI_REGION_MEM);
-#else
pci_set_region (hose->regions + 1,
PCI_MSTR_MEM_BUS,
PCI_MSTR_MEM_LOCAL,
PCI_MSTR_MEM_SIZE, PCI_REGION_MEM);
-#endif
/* PCI I/O space */
pci_set_region (hose->regions + 2,
diff --git a/board/freescale/mpc8266ads/Kconfig b/board/freescale/mpc8266ads/Kconfig
deleted file mode 100644
index 78963b9..0000000
--- a/board/freescale/mpc8266ads/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC8266ADS
-
-config SYS_BOARD
- default "mpc8266ads"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "MPC8266ADS"
-
-endif
diff --git a/board/freescale/mpc8266ads/MAINTAINERS b/board/freescale/mpc8266ads/MAINTAINERS
deleted file mode 100644
index bdea02d..0000000
--- a/board/freescale/mpc8266ads/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MPC8266ADS BOARD
-M: Rune Torgersen <runet@innovsys.com>
-S: Maintained
-F: board/freescale/mpc8266ads/
-F: include/configs/MPC8266ADS.h
-F: configs/MPC8266ADS_defconfig
diff --git a/board/freescale/mpc8266ads/Makefile b/board/freescale/mpc8266ads/Makefile
deleted file mode 100644
index ee63dc0..0000000
--- a/board/freescale/mpc8266ads/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := mpc8266ads.o flash.o
diff --git a/board/freescale/mpc8266ads/flash.c b/board/freescale/mpc8266ads/flash.c
deleted file mode 100644
index ef28194..0000000
--- a/board/freescale/mpc8266ads/flash.c
+++ /dev/null
@@ -1,493 +0,0 @@
-/*
- * (C) Copyright 2000, 2001
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth at lineo.com
- * Add support the Sharp chips on the mpc8260ads.
- * I started with board/ip860/flash.c and made changes I found in
- * the MTD project by David Schleef.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-# ifndef CONFIG_ENV_ADDR
-# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-# endif
-# ifndef CONFIG_ENV_SIZE
-# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-# endif
-# ifndef CONFIG_ENV_SECT_SIZE
-# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
-# endif
-#endif
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static int clear_block_lock_bit(vu_long * addr);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
-#ifndef CONFIG_MPC8266ADS
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- volatile ip860_bcsr_t *bcsr = (ip860_bcsr_t *)BCSR_BASE;
-#endif
- unsigned long size;
- int i;
-
- /* Init: enable write,
- * or we cannot even write flash commands
- */
-#ifndef CONFIG_MPC8266ADS
- bcsr->bd_ctrl |= BD_CTRL_FLWE;
-#endif
-
-
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
-
- /* set the default sector offset */
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size = flash_get_size((vu_long *)FLASH_BASE, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size, size<<20);
- }
-
-#ifndef CONFIG_MPC8266ADS
- /* Remap FLASH according to real size */
- memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000);
- memctl->memc_br1 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) |
- (memctl->memc_br1 & ~(BR_BA_MSK));
-#endif
- /* Re-do sizing to get full correct info */
- size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
- flash_info[0].size = size;
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[0]);
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
- &flash_info[0]);
-#endif
- return (size);
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_INTEL: printf ("Intel "); break;
- case FLASH_MAN_SHARP: printf ("Sharp "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n");
- break;
- case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n");
- break;
- case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n");
- break;
- case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
- short i;
- ulong value;
- ulong base = (ulong)addr;
- ulong sector_offset;
-
- /* Write "Intelligent Identifier" command: read Manufacturer ID */
- *addr = 0x90909090;
-
- value = addr[0] & 0x00FF00FF;
- switch (value) {
- case MT_MANUFACT: /* SHARP, MT or => Intel */
- case INTEL_ALT_MANU:
- info->flash_id = FLASH_MAN_INTEL;
- break;
- default:
- printf("unknown manufacturer: %x\n", (unsigned int)value);
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
- value = addr[1]; /* device ID */
-
- switch (value) {
- case (INTEL_ID_28F016S):
- info->flash_id += FLASH_28F016SV;
- info->sector_count = 32;
- info->size = 0x00400000;
- sector_offset = 0x20000;
- break; /* => 2x2 MB */
-
- case (INTEL_ID_28F160S3):
- info->flash_id += FLASH_28F160S3;
- info->sector_count = 32;
- info->size = 0x00400000;
- sector_offset = 0x20000;
- break; /* => 2x2 MB */
-
- case (INTEL_ID_28F320S3):
- info->flash_id += FLASH_28F320S3;
- info->sector_count = 64;
- info->size = 0x00800000;
- sector_offset = 0x20000;
- break; /* => 2x4 MB */
-
- case SHARP_ID_28F016SCL:
- case SHARP_ID_28F016SCZ:
- info->flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT;
- info->sector_count = 32;
- info->size = 0x00800000;
- sector_offset = 0x40000;
- break; /* => 4x2 MB */
-
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
-
- }
-
- /* set up sector start address table */
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base;
- base += sector_offset;
- /* don't know how to check sector protection */
- info->protect[i] = 0;
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- addr = (vu_long *)info->start[0];
-
- *addr = 0xFFFFFF; /* reset bank to read array mode */
- }
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- int flag, prot, sect;
- ulong start, now, last;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL)
- && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- /* Make Sure Block Lock Bit is not set. */
- if(clear_block_lock_bit((vu_long *)(info->start[s_first]))){
- return 1;
- }
-
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- vu_long *addr = (vu_long *)(info->start[sect]);
-
- last = start = get_timer (0);
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- /* Reset Array */
- *addr = 0xffffffff;
- /* Clear Status Register */
- *addr = 0x50505050;
- /* Single Block Erase Command */
- *addr = 0x20202020;
- /* Confirm */
- *addr = 0xD0D0D0D0;
-
- if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) {
- /* Resume Command, as per errata update */
- *addr = 0xD0D0D0D0;
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
- while ((*addr & 0x80808080) != 0x80808080) {
- if(*addr & 0x20202020){
- printf("Error in Block Erase - Lock Bit may be set!\n");
- printf("Status Register = 0x%X\n", (uint)*addr);
- *addr = 0xFFFFFFFF; /* reset bank */
- return 1;
- }
- if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- *addr = 0xFFFFFFFF; /* reset bank */
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
- /* reset to read mode */
- *addr = 0xFFFFFFFF;
- }
- }
-
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i=0; i<4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
- vu_long *addr = (vu_long *)dest;
- ulong start, csr;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*addr & data) != data) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- /* Write Command */
- *addr = 0x10101010;
-
- /* Write Data */
- *addr = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
- flag = 0;
- while (((csr = *addr) & 0x80808080) != 0x80808080) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- flag = 1;
- break;
- }
- }
- if (csr & 0x40404040) {
- printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr);
- flag = 1;
- }
-
- /* Clear Status Registers Command */
- *addr = 0x50505050;
- /* Reset to read array mode */
- *addr = 0xFFFFFFFF;
-
- return (flag);
-}
-
-/*-----------------------------------------------------------------------
- * Clear Block Lock Bit, returns:
- * 0 - OK
- * 1 - Timeout
- */
-
-static int clear_block_lock_bit(vu_long * addr)
-{
- ulong start, now;
-
- /* Reset Array */
- *addr = 0xffffffff;
- /* Clear Status Register */
- *addr = 0x50505050;
-
- *addr = 0x60606060;
- *addr = 0xd0d0d0d0;
-
- start = get_timer (0);
- while(*addr != 0x80808080){
- if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout on clearing Block Lock Bit\n");
- *addr = 0xFFFFFFFF; /* reset bank */
- return 1;
- }
- }
- return 0;
-}
diff --git a/board/freescale/mpc8266ads/mpc8266ads.c b/board/freescale/mpc8266ads/mpc8266ads.c
deleted file mode 100644
index 1eeec3f..0000000
--- a/board/freescale/mpc8266ads/mpc8266ads.c
+++ /dev/null
@@ -1,582 +0,0 @@
-/*
- * (C) Copyright 2001-2011
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * Modified during 2001 by
- * Advanced Communications Technologies (Australia) Pty. Ltd.
- * Howard Walker, Tuong Vu-Dinh
- *
- * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth at lineo.com
- * Added support for the 16M dram simm on the 8260ads boards
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <i2c.h>
-#include <mpc8260.h>
-#include <pci.h>
-
-/*
- * PBI Page Based Interleaving
- * PSDMR_PBI page based interleaving
- * 0 bank based interleaving
- * External Address Multiplexing (EAMUX) adds a clock to address cycles
- * (this can help with marginal board layouts)
- * PSDMR_EAMUX adds a clock
- * 0 no extra clock
- * Buffer Command (BUFCMD) adds a clock to command cycles.
- * PSDMR_BUFCMD adds a clock
- * 0 no extra clock
- */
-#define CONFIG_PBI 0
-#define PESSIMISTIC_SDRAM 0
-#define EAMUX 0 /* EST requires EAMUX */
-#define BUFCMD 0
-
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
- /* Port A configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
- /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
- /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
- /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
- /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
- /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
- /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
- /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
- /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
- /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
- /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
- /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
- /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
- /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
- /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
- /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
- /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
- /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
- /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
- /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
- /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
- /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
- /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
- /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
- /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
- /* PA6 */ { 1, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
- /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
- /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
- /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
- /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
- /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
- /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
- },
-
- /* Port B configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
- /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
- /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
- /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
- /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
- /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
- /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
- /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
- /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
- /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
- /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
- /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
- /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
- /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
- /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
- /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
- /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
- /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
- /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
- /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
- /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- },
-
- /* Port C */
- { /* conf ppar psor pdir podr pdat */
- /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
- /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
- /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
- /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
- /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
- /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
- /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
- /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
- /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
- /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
- /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
- /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
- /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
- /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
- /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
- /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
- /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */
- /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
- /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
- /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
- /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
- /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* LXT970 FETHMDC */
- /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* LXT970 FETHMDIO */
- /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
- /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
- /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
- /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
- /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
- /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
- /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
- /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
- /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
- },
-
- /* Port D */
- { /* conf ppar psor pdir podr pdat */
- /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
- /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
- /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
- /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
- /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
- /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
- /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
- /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
- /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
- /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
- /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
- /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
- /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
- /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
- /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
- /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
- /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
- /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
- /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
- /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
- /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
- /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
- /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
- /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
- /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
- /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
- /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
- /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
- /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- }
-};
-
-typedef struct bscr_ {
- unsigned long bcsr0;
- unsigned long bcsr1;
- unsigned long bcsr2;
- unsigned long bcsr3;
- unsigned long bcsr4;
- unsigned long bcsr5;
- unsigned long bcsr6;
- unsigned long bcsr7;
-} bcsr_t;
-
-typedef struct pci_ic_s {
- unsigned long pci_int_stat;
- unsigned long pci_int_mask;
-} pci_ic_t;
-
-void reset_phy(void)
-{
- volatile bcsr_t *bcsr = (bcsr_t *)CONFIG_SYS_BCSR;
-
- /* reset the FEC port */
- bcsr->bcsr1 &= ~FETH_RST;
- bcsr->bcsr1 |= FETH_RST;
-}
-
-
-int board_early_init_f(void)
-{
- volatile bcsr_t *bcsr = (bcsr_t *)CONFIG_SYS_BCSR;
- volatile pci_ic_t *pci_ic = (pci_ic_t *)CONFIG_SYS_PCI_INT;
-
- bcsr->bcsr1 = ~FETHIEN & ~RS232EN_1 & ~RS232EN_2;
-
- /* mask all PCI interrupts */
- pci_ic->pci_int_mask |= 0xfff00000;
-
- return 0;
-}
-
-int checkboard(void)
-{
- puts("Board: Motorola MPC8266ADS\n");
- return 0;
-}
-
-phys_size_t initdram(int board_type)
-{
- /* Autoinit part stolen from board/sacsng/sacsng.c */
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8260_t *memctl = &immap->im_memctl;
- volatile uchar c = 0xff;
- volatile uchar *ramaddr = (uchar *) (CONFIG_SYS_SDRAM_BASE + 0x8);
- uint psdmr = CONFIG_SYS_PSDMR;
- int i;
-
- uint psrt = 0x21; /* for no SPD */
- uint chipselects = 1; /* for no SPD */
- uint sdram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; /* for no SPD */
- uint or = CONFIG_SYS_OR2_PRELIM; /* for no SPD */
- uint data_width;
- uint rows;
- uint banks;
- uint cols;
- uint caslatency;
- uint width;
- uint rowst;
- uint sdam;
- uint bsma;
- uint sda10;
- u_char data;
- u_char cksum;
- int j;
-
- /*
- * Keep the compiler from complaining about
- * potentially uninitialized vars
- */
- data_width = rows = banks = cols = caslatency = 0;
-
- /*
- * Read the SDRAM SPD EEPROM via I2C.
- */
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-
- i2c_read(SDRAM_SPD_ADDR, 0, 1, &data, 1);
- cksum = data;
- for (j = 1; j < 64; j++) { /* read only the checksummed bytes */
- /* note: the I2C address autoincrements when alen == 0 */
- i2c_read(SDRAM_SPD_ADDR, 0, 0, &data, 1);
- /*printf("addr %d = 0x%02x\n", j, data); */
- if (j == 5)
- chipselects = data & 0x0F;
- else if (j == 6)
- data_width = data;
- else if (j == 7)
- data_width |= data << 8;
- else if (j == 3)
- rows = data & 0x0F;
- else if (j == 4)
- cols = data & 0x0F;
- else if (j == 12) {
- /*
- * Refresh rate: this assumes the prescaler is set to
- * approximately 0.39uSec per tick and the target
- * refresh period is about 85% of maximum.
- */
- switch (data & 0x7F) {
- default:
- case 0:
- psrt = 0x21; /* 15.625uS */
- break;
- case 1:
- psrt = 0x07; /* 3.9uS */
- break;
- case 2:
- psrt = 0x0F; /* 7.8uS */
- break;
- case 3:
- psrt = 0x43; /* 31.3uS */
- break;
- case 4:
- psrt = 0x87; /* 62.5uS */
- break;
- case 5:
- psrt = 0xFF; /* 125uS */
- break;
- }
- } else if (j == 17)
- banks = data;
- else if (j == 18) {
- caslatency = 3; /* default CL */
-#if (PESSIMISTIC_SDRAM)
- if ((data & 0x04) != 0)
- caslatency = 3;
- else if ((data & 0x02) != 0)
- caslatency = 2;
- else if ((data & 0x01) != 0)
- caslatency = 1;
-#else
- if ((data & 0x01) != 0)
- caslatency = 1;
- else if ((data & 0x02) != 0)
- caslatency = 2;
- else if ((data & 0x04) != 0)
- caslatency = 3;
-#endif
- else {
- printf("WARNING: Unknown CAS latency 0x%02X, using 3\n",
- data);
- }
- } else if (j == 63) {
- if (data != cksum) {
- printf("WARNING: Configuration data checksum failure:"
- " is 0x%02x, calculated 0x%02x\n",
- data, cksum);
- }
- }
- cksum += data;
- }
-
- /* We don't trust CL less than 2 (only saw it on an old 16MByte DIMM) */
- if (caslatency < 2) {
- printf("CL was %d, forcing to 2\n", caslatency);
- caslatency = 2;
- }
- if (rows > 14) {
- printf("This doesn't look good, rows = %d, should be <= 14\n",
- rows);
- rows = 14;
- }
- if (cols > 11) {
- printf("This doesn't look good, columns = %d, should be <= 11\n",
- cols);
- cols = 11;
- }
-
- if ((data_width != 64) && (data_width != 72)) {
- printf("WARNING: SDRAM width unsupported, is %d, expected 64 or 72.\n",
- data_width);
- }
- width = 3; /* 2^3 = 8 bytes = 64 bits wide */
- /*
- * Convert banks into log2(banks)
- */
- if (banks == 2)
- banks = 1;
- else if (banks == 4)
- banks = 2;
- else if (banks == 8)
- banks = 3;
-
-
- sdram_size = 1 << (rows + cols + banks + width);
- /* hack for high density memory (512MB per CS) */
- /* !!!!! Will ONLY work with Page Based Interleave !!!!!
- ( PSDMR[PBI] = 1 )
- */
- /*
- * memory actually has 11 column addresses, but the memory
- * controller doesn't really care.
- *
- * the calculations that follow will however move the rows so
- * that they are muxed one bit off if you use 11 bit columns.
- *
- * The solution is to tell the memory controller the correct
- * size of the memory but change the number of columns to 10
- * afterwards.
- *
- * The 11th column addre will still be mucxed correctly onto
- * the bus.
- *
- * Also be aware that the MPC8266ADS board Rev B has not
- * connected Row address 13 to anything.
- *
- * The fix is to connect ADD16 (from U37-47) to SADDR12 (U28-126)
- */
- if (cols > 10)
- cols = 10;
-
-#if (CONFIG_PBI == 0) /* bank-based interleaving */
- rowst = ((32 - 6) - (rows + cols + width)) * 2;
-#else
- rowst = 32 - (rows + banks + cols + width);
-#endif
-
- or = ~(sdram_size - 1) | /* SDAM address mask */
- ((banks - 1) << 13) | /* banks per device */
- (rowst << 9) | /* rowst */
- ((rows - 9) << 6); /* numr */
-
-
- /*printf("memctl->memc_or2 = 0x%08x\n", or); */
-
- /*
- * SDAM specifies the number of columns that are multiplexed
- * (reference AN2165/D), defined to be (columns - 6) for page
- * interleave, (columns - 8) for bank interleave.
- *
- * BSMA is 14 - max(rows, cols). The bank select lines come
- * into play above the highest "address" line going into the
- * the SDRAM.
- */
-#if (CONFIG_PBI == 0) /* bank-based interleaving */
- sdam = cols - 8;
- bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
- sda10 = sdam + 2;
-#else
- sdam = cols + banks - 8;
- bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
- sda10 = sdam;
-#endif
-#if (PESSIMISTIC_SDRAM)
- psdmr = (CONFIG_PBI | PSDMR_RFEN | PSDMR_RFRC_16_CLK |
- PSDMR_PRETOACT_8W | PSDMR_ACTTORW_8W | PSDMR_WRC_4C |
- PSDMR_EAMUX | PSDMR_BUFCMD) | caslatency |
- ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */
- (sdam << 24) | (bsma << 21) | (sda10 << 18);
-#else
- psdmr = (CONFIG_PBI | PSDMR_RFEN | PSDMR_RFRC_7_CLK |
- PSDMR_PRETOACT_3W | /* 1 for 7E parts (fast PC-133) */
- PSDMR_ACTTORW_2W | /* 1 for 7E parts (fast PC-133) */
- PSDMR_WRC_1C | /* 1 clock + 7nSec */
- EAMUX | BUFCMD) | caslatency |
- ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */
- (sdam << 24) | (bsma << 21) | (sda10 << 18);
-#endif
- /*printf("psdmr = 0x%08x\n", psdmr); */
-
- /*
- * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
- *
- * "At system reset, initialization software must set up the
- * programmable parameters in the memory controller banks registers
- * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
- * system software should execute the following initialization sequence
- * for each SDRAM device.
- *
- * 1. Issue a PRECHARGE-ALL-BANKS command
- * 2. Issue eight CBR REFRESH commands
- * 3. Issue a MODE-SET command to initialize the mode register
- *
- * Quote from Micron MT48LC8M16A2 data sheet:
- *
- * "...the SDRAM requires a 100uS delay prior to issuing any
- * command other than a COMMAND INHIBIT or NOP. Starting at some
- * point during this 100uS period and continuing at least through
- * the end of this period, COMMAND INHIBIT or NOP commands should
- * be applied."
- *
- * "Once the 100uS delay has been satisfied with at least one COMMAND
- * INHIBIT or NOP command having been applied, a /PRECHARGE command/
- * should be applied. All banks must then be precharged, thereby
- * placing the device in the all banks idle state."
- *
- * "Once in the idle state, /two/ AUTO REFRESH cycles must be
- * performed. After the AUTO REFRESH cycles are complete, the
- * SDRAM is ready for mode register programming."
- *
- * (/emphasis/ mine, gvb)
- *
- * The way I interpret this, Micron start up sequence is:
- * 1. Issue a PRECHARGE-BANK command (initial precharge)
- * 2. Issue a PRECHARGE-ALL-BANKS command ("all banks ... precharged")
- * 3. Issue two (presumably, doing eight is OK) CBR REFRESH commands
- * 4. Issue a MODE-SET command to initialize the mode register
- *
- * --------
- *
- * The initial commands are executed by setting P/LSDMR[OP] and
- * accessing the SDRAM with a single-byte transaction."
- *
- * The appropriate BRx/ORx registers have already been set
- * when we get here. The SDRAM can be accessed@the address
- * CONFIG_SYS_SDRAM_BASE.
- */
-
- memctl->memc_mptpr = CONFIG_SYS_MPTPR;
- memctl->memc_psrt = psrt;
-
- memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
- memctl->memc_or2 = or;
-
- memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
- *ramaddr = c;
-
- memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
- for (i = 0; i < 8; i++)
- *ramaddr = c;
-
- memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
- *ramaddr = c;
-
- memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
- *ramaddr = c;
-
- /*
- * Do it a second time for the second set of chips if the DIMM has
- * two chip selects (double sided).
- */
- if (chipselects > 1) {
- ramaddr += sdram_size;
-
- memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM + sdram_size;
- memctl->memc_or3 = or;
-
- memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
- *ramaddr = c;
-
- memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
- for (i = 0; i < 8; i++)
- *ramaddr = c;
-
- memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
- *ramaddr = c;
-
- memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
- *ramaddr = c;
- }
-
- /* print info */
- printf("SDRAM configuration read from SPD\n");
- printf("\tSize per side = %dMB\n", sdram_size >> 20);
- printf("\tOrganization: %d sides, %d banks, %d Columns, %d Rows, Data width = %d bits\n",
- chipselects, 1 << (banks), cols, rows, data_width);
- printf("\tRefresh rate = %d, CAS latency = %d", psrt, caslatency);
-#if (CONFIG_PBI == 0) /* bank-based interleaving */
- printf(", Using Bank Based Interleave\n");
-#else
- printf(", Using Page Based Interleave\n");
-#endif
- printf("\tTotal size: ");
-
- /* this delay only needed for original 16MB DIMM...
- * Not needed for any other memory configuration */
- if ((sdram_size * chipselects) == (16 * 1024 * 1024))
- udelay(250000);
-
- return sdram_size * chipselects;
-}
-
-#ifdef CONFIG_PCI
-struct pci_controller hose;
-
-extern void pci_mpc8250_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
- pci_mpc8250_init(&hose);
-}
-#endif
diff --git a/configs/MPC8266ADS_defconfig b/configs/MPC8266ADS_defconfig
deleted file mode 100644
index 485c842..0000000
--- a/configs/MPC8266ADS_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_MPC8266ADS=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 7e4eaef..d358d62 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+MPC8266ADS powerpc mpc8260 - - Rune Torgersen <runet@innovsys.com>
VoVPN-GW powerpc mpc8260 - -
ep8260 powerpc mpc8260 - - Frank Panno <fpanno@delphintech.com>
ppmc8260 powerpc mpc8260 - - Brad Kemp <Brad.Kemp@seranoa.com>
diff --git a/include/configs/MPC8266ADS.h b/include/configs/MPC8266ADS.h
deleted file mode 100644
index 8d9c8fb..0000000
--- a/include/configs/MPC8266ADS.h
+++ /dev/null
@@ -1,563 +0,0 @@
-/*
- * (C) Copyright 2001
- * Stuart Hughes <stuarth@lineo.com>
- * This file is based on similar values for other boards found in other
- * U-Boot config files, and some that I found in the mpc8260ads manual.
- *
- * Note: my board is a PILOT rev.
- * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Config header file for a MPC8266ADS Pilot 16M Ram Simm, 8Mbytes Flash Simm
- */
-
-/* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
- !! !!
- !! This configuration requires JP3 to be in position 1-2 to work !!
- !! To make it work for the default, the CONFIG_SYS_TEXT_BASE define in !!
- !! board/mpc8266ads/config.mk must be changed from 0xfe000000 to !!
- !! 0xfff00000 !!
- !! The CONFIG_SYS_HRCW_MASTER define below must also be changed to match !!
- !! !!
- !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC8266ADS 1 /* ...on motorola ADS board */
-#define CONFIG_CPM2 1 /* Has a CPM2 */
-
-#define CONFIG_SYS_TEXT_BASE 0xfe000000
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
-
-/* allow serial and ethaddr to be overwritten */
-#define CONFIG_ENV_OVERWRITE
-
-/*
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * if CONFIG_CONS_NONE is defined, then the serial console routines must
- * defined elsewhere (for example, on the cogent platform, there are serial
- * ports on the motherboard which are used for the serial console - see
- * cogent/cma101/serial.[ch]).
- */
-#undef CONFIG_CONS_ON_SMC /* define if console on SMC */
-#define CONFIG_CONS_ON_SCC /* define if console on SCC */
-#undef CONFIG_CONS_NONE /* define if console on something else */
-#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
-
-/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
- */
-#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
-#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
-#undef CONFIG_ETHER_NONE /* define if ether on something else */
-#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
-#define CONFIG_MII /* MII PHY management */
-#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
-/*
- * Port pins used for bit-banged MII communictions (if applicable).
- */
-#define MDIO_PORT 2 /* Port C */
-#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
- (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
-#define MDC_DECLARE MDIO_DECLARE
-
-#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
-#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
-#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
-
-#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
- else iop->pdat &= ~0x00400000
-
-#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
- else iop->pdat &= ~0x00200000
-
-#define MIIDELAY udelay(1)
-
-#if (CONFIG_ETHER_INDEX == 2)
-
-/*
- * - Rx-CLK is CLK13
- * - Tx-CLK is CLK14
- * - Select bus for bd/buffers (see 28-13)
- * - Half duplex
- */
-# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
-# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
-# define CONFIG_SYS_CPMFCR_RAMTYPE 0
-# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
-
-#endif /* CONFIG_ETHER_INDEX */
-
-/* other options */
-#define CONFIG_HARD_I2C 1 /* To enable I2C support */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-
-/* PCI */
-#define CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_PCI_PNP
-#define CONFIG_PCI_BOOTDELAY 0
-#undef CONFIG_PCI_SCAN_SHOW
-
-/*-----------------------------------------------------------------------
- * Definitions for Serial Presence Detect EEPROM address
- * (to get SDRAM settings)
- */
-#define SPD_EEPROM_ADDRESS 0x50
-
-#define CONFIG_8260_CLKIN 66000000 /* in Hz */
-#define CONFIG_BAUDRATE 115200
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-/* Commands we want, that are not part of default set */
-#define CONFIG_CMD_ASKENV /* ask for env variable */
-#define CONFIG_CMD_CACHE /* icache, dcache */
-#define CONFIG_CMD_DHCP /* DHCP Support */
-#define CONFIG_CMD_DIAG /* Diagnostics */
-#define CONFIG_CMD_IMMAP /* IMMR dump support */
-#define CONFIG_CMD_IRQ /* irqinfo */
-#define CONFIG_CMD_MII /* MII support */
-#define CONFIG_CMD_PCI /* pciinfo */
-#define CONFIG_CMD_PING /* ping support */
-#define CONFIG_CMD_PORTIO /* Port I/O */
-#define CONFIG_CMD_REGINFO /* Register dump */
-#define CONFIG_CMD_SAVES /* save S record dump */
-#define CONFIG_CMD_SDRAM /* SDRAM DIMM SPD info printout */
-
-/* Commands from default set we don't need */
-#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
-#undef CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
-
-/* Define a command string that is automatically executed when no character
- * is read on the console interface withing "Boot Delay" after reset.
- */
-#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */
-#define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */
-
-#ifdef CONFIG_BOOT_ROOT_INITRD
-#define CONFIG_BOOTCOMMAND \
- "version;" \
- "echo;" \
- "bootp;" \
- "setenv bootargs root=/dev/ram0 rw " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
- "bootm"
-#endif /* CONFIG_BOOT_ROOT_INITRD */
-
-#ifdef CONFIG_BOOT_ROOT_NFS
-#define CONFIG_BOOTCOMMAND \
- "version;" \
- "echo;" \
- "bootp;" \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
- "bootm"
-#endif /* CONFIG_BOOT_ROOT_NFS */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_DNS
-
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#if defined(CONFIG_CMD_KGDB)
-#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
-#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
-#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
-#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
-#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
-#endif
-
-#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
-
-#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in MHz */
- /* for versions < 2.4.5-pre5 */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#define CONFIG_SYS_FLASH_BASE 0xFE000000
-#define FLASH_BASE 0xFE000000
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 32 /* max num of sects on one chip */
-#define CONFIG_SYS_FLASH_SIZE 8
-#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 5 /* Timeout for Flash Write (in ms) */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-
-/* this is stuff came out of the Motorola docs */
-/* Only change this if you also change the Hardware configuration Word */
-#define CONFIG_SYS_DEFAULT_IMMR 0x0F010000
-
-/* Set IMMR to 0xF0000000 or above to boot Linux */
-#define CONFIG_SYS_IMMR 0xF0000000
-#define CONFIG_SYS_BCSR 0xF8000000
-#define CONFIG_SYS_PCI_INT 0xF8200000 /* PCI interrupt controller */
-
-/* Define CONFIG_VERY_BIG_RAM to allow use of SDRAMs larger than 256MBytes
- */
-/*#define CONFIG_VERY_BIG_RAM 1*/
-
-/* What should be the base address of SDRAM DIMM and how big is
- * it (in Mbytes)? This will normally auto-configure via the SPD.
-*/
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_SIZE 16
-
-#define SDRAM_SPD_ADDR 0x50
-
-/*-----------------------------------------------------------------------
- * BR2,BR3 - Base Register
- * Ref: Section 10.3.1 on page 10-14
- * OR2,OR3 - Option Register
- * Ref: Section 10.3.2 on page 10-16
- *-----------------------------------------------------------------------
- */
-
-/* Bank 2,3 - SDRAM DIMM
- */
-
-/* The BR2 is configured as follows:
- *
- * - Base address of 0x00000000
- * - 64 bit port size (60x bus only)
- * - Data errors checking is disabled
- * - Read and write access
- * - SDRAM 60x bus
- * - Access are handled by the memory controller according to MSEL
- * - Not used for atomic operations
- * - No data pipelining is done
- * - Valid
- */
-#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
- BRx_PS_64 |\
- BRx_MS_SDRAM_P |\
- BRx_V)
-
-#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
- BRx_PS_64 |\
- BRx_MS_SDRAM_P |\
- BRx_V)
-
-/* With a 64 MB DIMM, the OR2 is configured as follows:
- *
- * - 64 MB
- * - 4 internal banks per device
- * - Row start address bit is A8 with PSDMR[PBI] = 0
- * - 12 row address lines
- * - Back-to-back page mode
- * - Internal bank interleaving within save device enabled
- */
-#if (CONFIG_SYS_SDRAM_SIZE == 64)
-#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM_SIZE) |\
- ORxS_BPD_4 |\
- ORxS_ROWST_PBI0_A8 |\
- ORxS_NUMR_12)
-#elif (CONFIG_SYS_SDRAM_SIZE == 16)
-#define CONFIG_SYS_OR2_PRELIM (0xFF000C80)
-#else
-#error "INVALID SDRAM CONFIGURATION"
-#endif
-
-/*-----------------------------------------------------------------------
- * PSDMR - 60x Bus SDRAM Mode Register
- * Ref: Section 10.3.3 on page 10-21
- *-----------------------------------------------------------------------
- */
-
-#if (CONFIG_SYS_SDRAM_SIZE == 64)
-/* With a 64 MB DIMM, the PSDMR is configured as follows:
- *
- * - Bank Based Interleaving,
- * - Refresh Enable,
- * - Address Multiplexing where A5 is output on A14 pin
- * (A6 on A15, and so on),
- * - use address pins A14-A16 as bank select,
- * - A9 is output on SDA10 during an ACTIVATE command,
- * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
- * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
- * is 3 clocks,
- * - earliest timing for READ/WRITE command after ACTIVATE command is
- * 2 clocks,
- * - earliest timing for PRECHARGE after last data was read is 1 clock,
- * - earliest timing for PRECHARGE after last data was written is 1 clock,
- * - CAS Latency is 2.
- */
-#define CONFIG_SYS_PSDMR (PSDMR_RFEN |\
- PSDMR_SDAM_A14_IS_A5 |\
- PSDMR_BSMA_A14_A16 |\
- PSDMR_SDA10_PBI0_A9 |\
- PSDMR_RFRC_7_CLK |\
- PSDMR_PRETOACT_3W |\
- PSDMR_ACTTORW_2W |\
- PSDMR_LDOTOPRE_1C |\
- PSDMR_WRC_1C |\
- PSDMR_CL_2)
-#elif (CONFIG_SYS_SDRAM_SIZE == 16)
-/* With a 16 MB DIMM, the PSDMR is configured as follows:
- *
- * configuration parameters found in Motorola documentation
- */
-#define CONFIG_SYS_PSDMR (0x016EB452)
-#else
-#error "INVALID SDRAM CONFIGURATION"
-#endif
-
-#define RS232EN_1 0x02000002
-#define RS232EN_2 0x01000001
-#define FETHIEN 0x08000008
-#define FETH_RST 0x04000004
-
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/* Use this HRCW for booting from address 0xfe00000 (JP3 in setting 1-2) */
-/* 0x0EB2B645 */
-#define CONFIG_SYS_HRCW_MASTER (( HRCW_BPS11 | HRCW_CIP ) |\
- ( HRCW_L2CPC10 | HRCW_DPPC11 | HRCW_ISB010 ) |\
- ( HRCW_BMS | HRCW_MMR11 | HRCW_LBPC01 | HRCW_APPC10 ) |\
- ( HRCW_CS10PC01 | HRCW_MODCK_H0101 ) \
- )
-
-/* Use this HRCW for booting from address 0xfff0000 (JP3 in setting 2-3) */
-/* #define CONFIG_SYS_HRCW_MASTER 0x0cb23645 */
-
-/* This value should actually be situated in the first 256 bytes of the FLASH
- which on the standard MPC8266ADS board is at address 0xFF800000
- The linker script places it@0xFFF00000 instead.
-
- It still works, however, as long as the ADS board jumper JP3 is set to
- position 2-3 so the board is using the BCSR as Hardware Configuration Word
-
- If you want to use the one defined here instead, ust copy the first 256 bytes from
- 0xfff00000 to 0xff800000 (for 8MB flash)
-
- - Rune
-
-*/
-
-/* no slaves */
-#define CONFIG_SYS_HRCW_SLAVE1 0
-#define CONFIG_SYS_HRCW_SLAVE2 0
-#define CONFIG_SYS_HRCW_SLAVE3 0
-#define CONFIG_SYS_HRCW_SLAVE4 0
-#define CONFIG_SYS_HRCW_SLAVE5 0
-#define CONFIG_SYS_HRCW_SLAVE6 0
-#define CONFIG_SYS_HRCW_SLAVE7 0
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-# define CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-#ifndef CONFIG_SYS_RAMBOOT
-# define CONFIG_ENV_IS_IN_FLASH 1
-# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
-# define CONFIG_ENV_SECT_SIZE 0x40000
-#else
-# define CONFIG_ENV_IS_IN_NVRAM 1
-# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
-# define CONFIG_ENV_SIZE 0x200
-#endif /* CONFIG_SYS_RAMBOOT */
-
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers 2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-/*#define CONFIG_SYS_HID0_INIT 0 */
-#define CONFIG_SYS_HID0_INIT (HID0_ICE |\
- HID0_DCE |\
- HID0_ICFI |\
- HID0_DCI |\
- HID0_IFEM |\
- HID0_ABE)
-
-#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE )
-
-#define CONFIG_SYS_HID2 0
-
-#define CONFIG_SYS_SYPCR 0xFFFFFFC3
-#define CONFIG_SYS_BCR 0x004C0000
-#define CONFIG_SYS_SIUMCR 0x4E64C000
-#define CONFIG_SYS_SCCR 0x00000000
-
-/* local bus memory map
- *
- * 0x00000000-0x03FFFFFF 64MB SDRAM
- * 0x80000000-0x9FFFFFFF 512MB outbound prefetchable PCI memory window
- * 0xA0000000-0xBFFFFFFF 512MB outbound non-prefetchable PCI memory window
- * 0xF0000000-0xF001FFFF 128KB MPC8266 internal memory
- * 0xF4000000-0xF7FFFFFF 64MB outbound PCI I/O window
- * 0xF8000000-0xF8007FFF 32KB BCSR
- * 0xF8100000-0xF8107FFF 32KB ATM UNI
- * 0xF8200000-0xF8207FFF 32KB PCI interrupt controller
- * 0xF8300000-0xF8307FFF 32KB EEPROM
- * 0xFE000000-0xFFFFFFFF 32MB flash
- */
-#define CONFIG_SYS_BR0_PRELIM 0xFE001801 /* flash */
-#define CONFIG_SYS_OR0_PRELIM 0xFE000836
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR | 0x1801) /* BCSR */
-#define CONFIG_SYS_OR1_PRELIM 0xFFFF8010
-#define CONFIG_SYS_BR4_PRELIM 0xF8300801 /* EEPROM */
-#define CONFIG_SYS_OR4_PRELIM 0xFFFF8846
-#define CONFIG_SYS_BR5_PRELIM 0xF8100801 /* PM5350 ATM UNI */
-#define CONFIG_SYS_OR5_PRELIM 0xFFFF8E36
-#define CONFIG_SYS_BR8_PRELIM (CONFIG_SYS_PCI_INT | 0x1801) /* PCI interrupt controller */
-#define CONFIG_SYS_OR8_PRELIM 0xFFFF8010
-
-#define CONFIG_SYS_RMR 0x0001
-#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
-#define CONFIG_SYS_RCCR 0
-#define CONFIG_SYS_MPTPR 0x00001900
-#define CONFIG_SYS_PSRT 0x00000021
-
-/* This address must not exist */
-#define CONFIG_SYS_RESET_ADDRESS 0xFCFFFF00
-
-/* PCI Memory map (if different from default map */
-#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE /* Local base */
-#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
-#define CONFIG_SYS_PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \
- PICMR_PREFETCH_EN)
-
-/*
- * These are the windows that allow the CPU to access PCI address space.
- * All three PCI master windows, which allow the CPU to access PCI
- * prefetch, non prefetch, and IO space (see below), must all fit within
- * these windows.
- */
-
-/* PCIBR0 */
-#define CONFIG_SYS_PCI_MSTR0_LOCAL 0x80000000 /* Local base */
-#define CONFIG_SYS_PCIMSK0_MASK PCIMSK_1GB /* Size of window */
-/* PCIBR1 */
-#define CONFIG_SYS_PCI_MSTR1_LOCAL 0xF4000000 /* Local base */
-#define CONFIG_SYS_PCIMSK1_MASK PCIMSK_64MB /* Size of window */
-
-/*
- * Master window that allows the CPU to access PCI Memory (prefetch).
- * This window will be setup with the first set of Outbound ATU registers
- * in the bridge.
- */
-
-#define CONFIG_SYS_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
-#define CONFIG_SYS_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
-#define CONFIG_SYS_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
-#define CONFIG_SYS_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */
-#define CONFIG_SYS_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
-
-/*
- * Master window that allows the CPU to access PCI Memory (non-prefetch).
- * This window will be setup with the second set of Outbound ATU registers
- * in the bridge.
- */
-
-#define CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */
-#define CONFIG_SYS_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */
-#define CONFIG_SYS_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
-#define CONFIG_SYS_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */
-#define CONFIG_SYS_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE)
-
-/*
- * Master window that allows the CPU to access PCI IO space.
- * This window will be setup with the third set of Outbound ATU registers
- * in the bridge.
- */
-
-#define CONFIG_SYS_PCI_MSTR_IO_LOCAL 0xF4000000 /* Local base */
-#define CONFIG_SYS_PCI_MSTR_IO_BUS 0xF4000000 /* PCI base */
-#define CONFIG_SYS_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
-#define CONFIG_SYS_PCI_MSTR_IO_SIZE 0x04000000 /* 64MB */
-#define CONFIG_SYS_POCMR2_MASK_ATTRIB (POCMR_MASK_64MB | POCMR_ENABLE | POCMR_PCI_IO)
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV "nor0"
-#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET 0x00000000
-
-/* mtdparts command line support */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT ""
-#define MTDPARTS_DEFAULT ""
-*/
-
-#endif /* __CONFIG_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [U-Boot] [PATCH 19/26] mpc8260: remove PM825, PM826, PM828 board support
2014-12-15 14:26 [U-Boot] [PATCH 0/26] Start removing non-generic boards Masahiro Yamada
` (17 preceding siblings ...)
2014-12-15 14:26 ` [U-Boot] [PATCH 18/26] mpc8260: remove MPC8266ADS " Masahiro Yamada
@ 2014-12-15 14:26 ` Masahiro Yamada
2015-01-05 18:21 ` Tom Rini
2014-12-15 14:26 ` [U-Boot] [PATCH 20/26] mpc8260: remove muas3001 " Masahiro Yamada
` (8 subsequent siblings)
27 siblings, 1 reply; 55+ messages in thread
From: Masahiro Yamada @ 2014-12-15 14:26 UTC (permalink / raw)
To: u-boot
These boards are still non-generic boards.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
---
arch/powerpc/cpu/mpc8260/Kconfig | 8 -
arch/powerpc/cpu/mpc8260/pci.c | 11 -
board/pm826/Kconfig | 9 -
board/pm826/MAINTAINERS | 13 -
board/pm826/Makefile | 8 -
board/pm826/flash.c | 370 ---------------------
board/pm826/pm826.c | 319 ------------------
board/pm828/Kconfig | 9 -
board/pm828/MAINTAINERS | 9 -
board/pm828/Makefile | 8 -
board/pm828/flash.c | 370 ---------------------
board/pm828/pm828.c | 352 --------------------
configs/PM825_BIGFLASH_defconfig | 4 -
configs/PM825_ROMBOOT_BIGFLASH_defconfig | 4 -
configs/PM825_ROMBOOT_defconfig | 4 -
configs/PM825_defconfig | 4 -
configs/PM826_BIGFLASH_defconfig | 4 -
configs/PM826_ROMBOOT_BIGFLASH_defconfig | 4 -
configs/PM826_ROMBOOT_defconfig | 4 -
configs/PM826_defconfig | 4 -
configs/PM828_PCI_defconfig | 4 -
configs/PM828_ROMBOOT_PCI_defconfig | 4 -
configs/PM828_ROMBOOT_defconfig | 4 -
configs/PM828_defconfig | 3 -
doc/README.scrapyard | 3 +
include/configs/PM826.h | 534 -------------------------------
include/configs/PM828.h | 528 ------------------------------
27 files changed, 3 insertions(+), 2595 deletions(-)
delete mode 100644 board/pm826/Kconfig
delete mode 100644 board/pm826/MAINTAINERS
delete mode 100644 board/pm826/Makefile
delete mode 100644 board/pm826/flash.c
delete mode 100644 board/pm826/pm826.c
delete mode 100644 board/pm828/Kconfig
delete mode 100644 board/pm828/MAINTAINERS
delete mode 100644 board/pm828/Makefile
delete mode 100644 board/pm828/flash.c
delete mode 100644 board/pm828/pm828.c
delete mode 100644 configs/PM825_BIGFLASH_defconfig
delete mode 100644 configs/PM825_ROMBOOT_BIGFLASH_defconfig
delete mode 100644 configs/PM825_ROMBOOT_defconfig
delete mode 100644 configs/PM825_defconfig
delete mode 100644 configs/PM826_BIGFLASH_defconfig
delete mode 100644 configs/PM826_ROMBOOT_BIGFLASH_defconfig
delete mode 100644 configs/PM826_ROMBOOT_defconfig
delete mode 100644 configs/PM826_defconfig
delete mode 100644 configs/PM828_PCI_defconfig
delete mode 100644 configs/PM828_ROMBOOT_PCI_defconfig
delete mode 100644 configs/PM828_ROMBOOT_defconfig
delete mode 100644 configs/PM828_defconfig
delete mode 100644 include/configs/PM826.h
delete mode 100644 include/configs/PM828.h
diff --git a/arch/powerpc/cpu/mpc8260/Kconfig b/arch/powerpc/cpu/mpc8260/Kconfig
index d9dba83..cb81cdc 100644
--- a/arch/powerpc/cpu/mpc8260/Kconfig
+++ b/arch/powerpc/cpu/mpc8260/Kconfig
@@ -28,12 +28,6 @@ config TARGET_IPHASE4539
config TARGET_MUAS3001
bool "Support muas3001"
-config TARGET_PM826
- bool "Support PM826"
-
-config TARGET_PM828
- bool "Support PM828"
-
config TARGET_KM82XX
bool "Support km82xx"
@@ -47,7 +41,5 @@ source "board/gw8260/Kconfig"
source "board/iphase4539/Kconfig"
source "board/keymile/km82xx/Kconfig"
source "board/muas3001/Kconfig"
-source "board/pm826/Kconfig"
-source "board/pm828/Kconfig"
endmenu
diff --git a/arch/powerpc/cpu/mpc8260/pci.c b/arch/powerpc/cpu/mpc8260/pci.c
index 079b6e6..56f290c 100644
--- a/arch/powerpc/cpu/mpc8260/pci.c
+++ b/arch/powerpc/cpu/mpc8260/pci.c
@@ -22,10 +22,6 @@
#include <fdt_support.h>
#endif
-#if defined CONFIG_PM826
-DECLARE_GLOBAL_DATA_PTR;
-#endif
-
/*
* Local->PCI map (from CPU) controlled by
* MPC826x master window
@@ -342,17 +338,10 @@ void pci_mpc8250_init (struct pci_controller *hose)
hose->last_busno = 0xff;
/* System memory space */
-#if defined CONFIG_PM826
- pci_set_region (hose->regions + 0,
- PCI_SLV_MEM_BUS,
- PCI_SLV_MEM_LOCAL,
- gd->ram_size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-#else
pci_set_region (hose->regions + 0,
CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_BASE,
0x4000000, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-#endif
/* PCI memory space */
pci_set_region (hose->regions + 1,
diff --git a/board/pm826/Kconfig b/board/pm826/Kconfig
deleted file mode 100644
index dd11b7a..0000000
--- a/board/pm826/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_PM826
-
-config SYS_BOARD
- default "pm826"
-
-config SYS_CONFIG_NAME
- default "PM826"
-
-endif
diff --git a/board/pm826/MAINTAINERS b/board/pm826/MAINTAINERS
deleted file mode 100644
index 41df4c9..0000000
--- a/board/pm826/MAINTAINERS
+++ /dev/null
@@ -1,13 +0,0 @@
-PM826 BOARD
-M: Wolfgang Denk <wd@denx.de>
-S: Maintained
-F: board/pm826/
-F: include/configs/PM826.h
-F: configs/PM825_defconfig
-F: configs/PM825_BIGFLASH_defconfig
-F: configs/PM825_ROMBOOT_defconfig
-F: configs/PM825_ROMBOOT_BIGFLASH_defconfig
-F: configs/PM826_defconfig
-F: configs/PM826_BIGFLASH_defconfig
-F: configs/PM826_ROMBOOT_defconfig
-F: configs/PM826_ROMBOOT_BIGFLASH_defconfig
diff --git a/board/pm826/Makefile b/board/pm826/Makefile
deleted file mode 100644
index c515f81..0000000
--- a/board/pm826/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = pm826.o flash.o
diff --git a/board/pm826/flash.c b/board/pm826/flash.c
deleted file mode 100644
index 786a29b..0000000
--- a/board/pm826/flash.c
+++ /dev/null
@@ -1,370 +0,0 @@
-/*
- * (C) Copyright 2001, 2002
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * Flash Routines for Intel devices
- *
- *--------------------------------------------------------------------
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-/*-----------------------------------------------------------------------
- */
-ulong flash_get_size (volatile unsigned long *baseaddr,
- flash_info_t * info)
-{
- short i;
- unsigned long flashtest_h, flashtest_l;
-
- info->sector_count = info->size = 0;
- info->flash_id = FLASH_UNKNOWN;
-
- /* Write query command sequence and test FLASH answer
- */
- baseaddr[0] = 0x00980098;
- baseaddr[1] = 0x00980098;
-
- flashtest_h = baseaddr[0]; /* manufacturer ID */
- flashtest_l = baseaddr[1];
-
- if (flashtest_h != INTEL_MANUFACT || flashtest_l != INTEL_MANUFACT)
- return (0); /* no or unknown flash */
-
- flashtest_h = baseaddr[2]; /* device ID */
- flashtest_l = baseaddr[3];
-
- if (flashtest_h != flashtest_l)
- return (0);
-
- switch (flashtest_h) {
- case INTEL_ID_28F160C3B:
- info->flash_id = FLASH_28F160C3B;
- info->sector_count = 39;
- info->size = 0x00800000; /* 4 * 2 MB = 8 MB */
- break;
- case INTEL_ID_28F160F3B:
- info->flash_id = FLASH_28F160F3B;
- info->sector_count = 39;
- info->size = 0x00800000; /* 4 * 2 MB = 8 MB */
- break;
- case INTEL_ID_28F640C3B:
- info->flash_id = FLASH_28F640C3B;
- info->sector_count = 135;
- info->size = 0x02000000; /* 16 * 2 MB = 32 MB */
- break;
- default:
- return (0); /* no or unknown flash */
- }
-
- info->flash_id |= INTEL_MANUFACT << 16; /* set manufacturer offset */
-
- if (info->flash_id & FLASH_BTYPE) {
- volatile unsigned long *tmp = baseaddr;
-
- /* set up sector start adress table (bottom sector type)
- * AND unlock the sectors (if our chip is 160C3 or 640C3)
- */
- for (i = 0; i < info->sector_count; i++) {
- if (((info->flash_id & FLASH_TYPEMASK) == FLASH_28F160C3B) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_28F640C3B)) {
- tmp[0] = 0x00600060;
- tmp[1] = 0x00600060;
- tmp[0] = 0x00D000D0;
- tmp[1] = 0x00D000D0;
- }
- info->start[i] = (uint) tmp;
- tmp += i < 8 ? 0x2000 : 0x10000; /* pointer arith */
- }
- }
-
- memset (info->protect, 0, info->sector_count);
-
- baseaddr[0] = 0x00FF00FF;
- baseaddr[1] = 0x00FF00FF;
-
- return (info->size);
-}
-
-/*-----------------------------------------------------------------------
- */
-unsigned long flash_init (void)
-{
- unsigned long size_b0 = 0;
- int i;
-
- /* Init: no FLASHes known
- */
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here (only one bank) */
-
- size_b0 = flash_get_size ((ulong *) CONFIG_SYS_FLASH0_BASE, &flash_info[0]);
- if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0 >> 20);
- }
-
- /* protect monitor and environment sectors
- */
-
-#ifndef CONFIG_BOOT_ROM
- /* If U-Boot is booted from ROM the CONFIG_SYS_MONITOR_BASE > CONFIG_SYS_FLASH0_BASE
- * but we shouldn't protect it.
- */
-
-# if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]
- );
-# endif
-#endif /* CONFIG_BOOT_ROM */
-
-#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
-# ifndef CONFIG_ENV_SIZE
-# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-# endif
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
-#endif
-
- return (size_b0);
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch ((info->flash_id >> 16) & 0xff) {
- case 0x89:
- printf ("INTEL ");
- break;
- default:
- printf ("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F160C3B:
- printf ("28F160C3B (16 M, bottom sector)\n");
- break;
- case FLASH_28F160F3B:
- printf ("28F160F3B (16 M, bottom sector)\n");
- break;
- case FLASH_28F640C3B:
- printf ("28F640C3B (64 M, bottom sector)\n");
- break;
- default:
- printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
-}
-
-/*-----------------------------------------------------------------------
- */
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
- int flag, prot, sect;
- ulong start, now, last;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect])
- prot++;
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- /* Start erase on unprotected sectors
- */
- for (sect = s_first; sect <= s_last; sect++) {
- volatile ulong *addr =
- (volatile unsigned long *) info->start[sect];
-
- start = get_timer (0);
- last = start;
- if (info->protect[sect] == 0) {
- /* Disable interrupts which might cause a timeout here
- */
- flag = disable_interrupts ();
-
- /* Erase the block
- */
- addr[0] = 0x00200020;
- addr[1] = 0x00200020;
- addr[0] = 0x00D000D0;
- addr[1] = 0x00D000D0;
-
- /* re-enable interrupts if necessary
- */
- if (flag)
- enable_interrupts ();
-
- /* wait at least 80us - let's wait 1 ms
- */
- udelay (1000);
-
- last = start;
- while ((addr[0] & 0x00800080) != 0x00800080 ||
- (addr[1] & 0x00800080) != 0x00800080) {
- if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout (erase suspended!)\n");
- /* Suspend erase
- */
- addr[0] = 0x00B000B0;
- addr[1] = 0x00B000B0;
- goto DONE;
- }
- /* show that we're waiting
- */
- if ((now - last) > 1000) { /* every second */
- serial_putc ('.');
- last = now;
- }
- }
- if (addr[0] & 0x00220022 || addr[1] & 0x00220022) {
- printf ("*** ERROR: erase failed!\n");
- goto DONE;
- }
- }
- /* Clear status register and reset to read mode
- */
- addr[0] = 0x00500050;
- addr[1] = 0x00500050;
- addr[0] = 0x00FF00FF;
- addr[1] = 0x00FF00FF;
- }
-
- printf (" done\n");
-
-DONE:
- return 0;
-}
-
-static int write_word (flash_info_t *, volatile unsigned long *, ulong);
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- ulong v;
- int i, l, cc = cnt, res = 0;
-
-
- for (v=0; cc > 0; addr += 4, cc -= 4 - l) {
- l = (addr & 3);
- addr &= ~3;
-
- for (i = 0; i < 4; i++) {
- v = (v << 8) + (i < l || i - l >= cc ?
- *((unsigned char *) addr + i) : *src++);
- }
-
- if ((res = write_word (info, (volatile unsigned long *) addr, v)) != 0)
- break;
- }
-
- return (res);
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t * info, volatile unsigned long *addr,
- ulong data)
-{
- int flag, res = 0;
- ulong start;
-
- /* Check if Flash is (sufficiently) erased
- */
- if ((*addr & data) != data)
- return (2);
-
- /* Disable interrupts which might cause a timeout here
- */
- flag = disable_interrupts ();
-
- *addr = 0x00400040;
- *addr = data;
-
- /* re-enable interrupts if necessary
- */
- if (flag)
- enable_interrupts ();
-
- start = get_timer (0);
- while ((*addr & 0x00800080) != 0x00800080) {
- if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- /* Suspend program
- */
- *addr = 0x00B000B0;
- res = 1;
- goto OUT;
- }
- }
-
- if (*addr & 0x00220022) {
- printf ("*** ERROR: program failed!\n");
- res = 1;
- }
-
-OUT:
- /* Clear status register and reset to read mode
- */
- *addr = 0x00500050;
- *addr = 0x00FF00FF;
-
- return (res);
-}
diff --git a/board/pm826/pm826.c b/board/pm826/pm826.c
deleted file mode 100644
index 93bb1b4..0000000
--- a/board/pm826/pm826.c
+++ /dev/null
@@ -1,319 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc8260.h>
-#include <pci.h>
-#include <netdev.h>
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
- /* Port A configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 COL */
- /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 CRS */
- /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXER */
- /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */
- /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */
- /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXER */
- /* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* PA25 */
- /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* PA24 */
- /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* PA23 */
- /* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* PA22 */
- /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */
- /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */
- /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */
- /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */
- /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */
- /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD1*/
- /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */
- /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */
- /* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* PA13 */
- /* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* PA12 */
- /* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* PA11 */
- /* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* PA10 */
- /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* PA9 */
- /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* PA8 */
- /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
- /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */
- /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
- /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
- /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
- /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
- /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */
- /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
- },
-
- /* Port B configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TX_ER */
- /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RX_DV */
- /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 TX_EN */
-#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
-#ifdef CONFIG_ETHER_ON_FCC2
-#error "SCC1 conflicts with FCC2"
-#endif
- /* PB28 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TXD */
-#else
- /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RX_ER */
-#endif
- /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 COL */
- /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 CRS */
- /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[3] */
- /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[2] */
- /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[1] */
- /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[0] */
- /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[0] */
- /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[1] */
- /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[2] */
- /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[3] */
- /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */
- /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */
- /* PB15 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */
- /* PB14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC3 RXD */
- /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */
- /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */
- /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */
- /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */
- /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */
- /* PB8 */ { 1, 1, 1, 1, 0, 0 }, /* SCC3 TXD */
- /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
- /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */
- /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */
- /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */
- /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- },
-
- /* Port C */
- { /* conf ppar psor pdir podr pdat */
- /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
- /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
- /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 CTS */
- /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* SCC2 CTS */
- /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */
- /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
- /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
- /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
- /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* PC23 */
- /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 TXCK */
- /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXCK */
- /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 TXCK(2) */
- /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RXCK */
- /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 TXCK */
- /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
- /* PC16 */ { 0, 0, 0, 1, 0, 0 }, /* PC16 */
- /* PC15 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
- /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 DCD */
- /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
- /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* SCC2 DCD */
- /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 CTS */
- /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 DCD */
- /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* SCC4 CTS */
- /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* SCC4 DCD */
- /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
- /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
- /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
- /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
- /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
- /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* PC2 */
- /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* PC1 */
- /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* PC0 */
- },
-
- /* Port D */
- { /* conf ppar psor pdir podr pdat */
- /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RXD */
- /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* PD30 */
- /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 RTS */
- /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */
- /* PD27 */ { 0, 1, 0, 1, 0, 0 }, /* SCC2 RTS */
- /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
- /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
- /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
- /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 RTS */
- /* PD22 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4 RXD */
- /* PD21 */ { 1, 1, 0, 1, 0, 0 }, /* SCC4 TXD */
- /* PD20 */ { 0, 0, 1, 1, 0, 0 }, /* SCC4 RTS */
- /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
- /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
- /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* PD17 */
- /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* PD16 */
-#if defined(CONFIG_SYS_I2C_SOFT)
- /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */
- /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */
-#else
-#if defined(CONFIG_HARD_I2C)
- /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
- /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
-#else /* normal I/O port pins */
- /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
- /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */
-#endif
-#endif
- /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
- /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
- /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
- /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
- /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* PD9 */
- /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* PD8 */
- /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
- /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
- /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
- /* PD4 */ { 1, 1, 1, 0, 0, 0 }, /* SMC2 RXD */
- /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- }
-};
-
-/* ------------------------------------------------------------------------- */
-
-/* Check Board Identity:
- */
-int checkboard (void)
-{
- puts ("Board: PM826\n");
- return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-
-/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
- *
- * This routine performs standard 8260 initialization sequence
- * and calculates the available memory size. It may be called
- * several times to try different SDRAM configurations on both
- * 60x and local buses.
- */
-static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
- ulong orx, volatile uchar * base)
-{
- volatile uchar c = 0xff;
- volatile uint *sdmr_ptr;
- volatile uint *orx_ptr;
- ulong maxsize, size;
- int i;
-
- /* We must be able to test a location outsize the maximum legal size
- * to find out THAT we are outside; but this address still has to be
- * mapped by the controller. That means, that the initial mapping has
- * to be (at least) twice as large as the maximum expected size.
- */
- maxsize = (1 + (~orx | 0x7fff)) / 2;
-
- sdmr_ptr = &memctl->memc_psdmr;
- orx_ptr = &memctl->memc_or2;
-
- *orx_ptr = orx;
-
- /*
- * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
- *
- * "At system reset, initialization software must set up the
- * programmable parameters in the memory controller banks registers
- * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
- * system software should execute the following initialization sequence
- * for each SDRAM device.
- *
- * 1. Issue a PRECHARGE-ALL-BANKS command
- * 2. Issue eight CBR REFRESH commands
- * 3. Issue a MODE-SET command to initialize the mode register
- *
- * The initial commands are executed by setting P/LSDMR[OP] and
- * accessing the SDRAM with a single-byte transaction."
- *
- * The appropriate BRx/ORx registers have already been set when we
- * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
- */
-
- *sdmr_ptr = sdmr | PSDMR_OP_PREA;
- *base = c;
-
- *sdmr_ptr = sdmr | PSDMR_OP_CBRR;
- for (i = 0; i < 8; i++)
- *base = c;
-
- *sdmr_ptr = sdmr | PSDMR_OP_MRW;
- *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */
-
- *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
- *base = c;
-
- size = get_ram_size((long *)base, maxsize);
-
- *orx_ptr = orx | ~(size - 1);
-
- return (size);
-}
-
-
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8260_t *memctl = &immap->im_memctl;
-
-#ifndef CONFIG_SYS_RAMBOOT
- ulong size8, size9;
-#endif
- ulong psize = 32 * 1024 * 1024;
-
- memctl->memc_psrt = CONFIG_SYS_PSRT;
- memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-
-#ifndef CONFIG_SYS_RAMBOOT
- size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
- (uchar *) CONFIG_SYS_SDRAM_BASE);
- size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL,
- (uchar *) CONFIG_SYS_SDRAM_BASE);
-
- if (size8 < size9) {
- psize = size9;
- printf ("(60x:9COL) ");
- } else {
- psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
- (uchar *) CONFIG_SYS_SDRAM_BASE);
- printf ("(60x:8COL) ");
- }
-#endif
- return (psize);
-}
-
-#if defined(CONFIG_CMD_DOC)
-void doc_init (void)
-{
- doc_probe (CONFIG_SYS_DOC_BASE);
-}
-#endif
-
-#ifdef CONFIG_PCI
-struct pci_controller hose;
-
-extern void pci_mpc8250_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
- pci_mpc8250_init(&hose);
-}
-#endif
-
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
diff --git a/board/pm828/Kconfig b/board/pm828/Kconfig
deleted file mode 100644
index e7970a3..0000000
--- a/board/pm828/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_PM828
-
-config SYS_BOARD
- default "pm828"
-
-config SYS_CONFIG_NAME
- default "PM828"
-
-endif
diff --git a/board/pm828/MAINTAINERS b/board/pm828/MAINTAINERS
deleted file mode 100644
index 97c1ccc..0000000
--- a/board/pm828/MAINTAINERS
+++ /dev/null
@@ -1,9 +0,0 @@
-PM828 BOARD
-#M: -
-S: Maintained
-F: board/pm828/
-F: include/configs/PM828.h
-F: configs/PM828_defconfig
-F: configs/PM828_PCI_defconfig
-F: configs/PM828_ROMBOOT_defconfig
-F: configs/PM828_ROMBOOT_PCI_defconfig
diff --git a/board/pm828/Makefile b/board/pm828/Makefile
deleted file mode 100644
index 0afffb7..0000000
--- a/board/pm828/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = pm828.o flash.o
diff --git a/board/pm828/flash.c b/board/pm828/flash.c
deleted file mode 100644
index 8888560..0000000
--- a/board/pm828/flash.c
+++ /dev/null
@@ -1,370 +0,0 @@
-/*
- * (C) Copyright 2001-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Flash Routines for Intel devices
- *
- *--------------------------------------------------------------------
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-/*-----------------------------------------------------------------------
- */
-ulong flash_get_size (volatile unsigned long *baseaddr,
- flash_info_t * info)
-{
- short i;
- unsigned long flashtest_h, flashtest_l;
-
- info->sector_count = info->size = 0;
- info->flash_id = FLASH_UNKNOWN;
-
- /* Write query command sequence and test FLASH answer
- */
- baseaddr[0] = 0x00980098;
- baseaddr[1] = 0x00980098;
-
- flashtest_h = baseaddr[0]; /* manufacturer ID */
- flashtest_l = baseaddr[1];
-
- if (flashtest_h != INTEL_MANUFACT || flashtest_l != INTEL_MANUFACT)
- return (0); /* no or unknown flash */
-
- flashtest_h = baseaddr[2]; /* device ID */
- flashtest_l = baseaddr[3];
-
- if (flashtest_h != flashtest_l)
- return (0);
-
- switch (flashtest_h) {
- case INTEL_ID_28F160C3B:
- info->flash_id = FLASH_28F160C3B;
- info->sector_count = 39;
- info->size = 0x00800000; /* 4 * 2 MB = 8 MB */
- break;
- case INTEL_ID_28F160F3B:
- info->flash_id = FLASH_28F160F3B;
- info->sector_count = 39;
- info->size = 0x00800000; /* 4 * 2 MB = 8 MB */
- break;
- case INTEL_ID_28F640C3B:
- info->flash_id = FLASH_28F640C3B;
- info->sector_count = 135;
- info->size = 0x02000000; /* 16 * 2 MB = 32 MB */
- break;
- default:
- return (0); /* no or unknown flash */
- }
-
- info->flash_id |= INTEL_MANUFACT << 16; /* set manufacturer offset */
-
- if (info->flash_id & FLASH_BTYPE) {
- volatile unsigned long *tmp = baseaddr;
-
- /* set up sector start adress table (bottom sector type)
- * AND unlock the sectors (if our chip is 160C3 or 640c3)
- */
- for (i = 0; i < info->sector_count; i++) {
- if (((info->flash_id & FLASH_TYPEMASK) == FLASH_28F160C3B) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_28F640C3B)) {
- tmp[0] = 0x00600060;
- tmp[1] = 0x00600060;
- tmp[0] = 0x00D000D0;
- tmp[1] = 0x00D000D0;
- }
- info->start[i] = (uint) tmp;
- tmp += i < 8 ? 0x2000 : 0x10000; /* pointer arith */
- }
- }
-
- memset (info->protect, 0, info->sector_count);
-
- baseaddr[0] = 0x00FF00FF;
- baseaddr[1] = 0x00FF00FF;
-
- return (info->size);
-}
-
-/*-----------------------------------------------------------------------
- */
-unsigned long flash_init (void)
-{
- unsigned long size_b0 = 0;
- int i;
-
- /* Init: no FLASHes known
- */
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here (only one bank) */
-
- size_b0 = flash_get_size ((ulong *) CONFIG_SYS_FLASH0_BASE, &flash_info[0]);
- if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0 >> 20);
- }
-
- /* protect monitor and environment sectors
- */
-
-#ifndef CONFIG_BOOT_ROM
- /* If U-Boot is booted from ROM the CONFIG_SYS_MONITOR_BASE > CONFIG_SYS_FLASH0_BASE
- * but we shouldn't protect it.
- */
-
-# if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]
- );
-# endif
-#endif /* CONFIG_BOOT_ROM */
-
-#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
-# ifndef CONFIG_ENV_SIZE
-# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-# endif
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
-#endif
-
- return (size_b0);
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch ((info->flash_id >> 16) & 0xff) {
- case 0x89:
- printf ("INTEL ");
- break;
- default:
- printf ("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F160C3B:
- printf ("28F160C3B (16 M, bottom sector)\n");
- break;
- case FLASH_28F160F3B:
- printf ("28F160F3B (16 M, bottom sector)\n");
- break;
- case FLASH_28F640C3B:
- printf ("28F640C3B (64 M, bottom sector)\n");
- break;
- default:
- printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
-}
-
-/*-----------------------------------------------------------------------
- */
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
- int flag, prot, sect;
- ulong start, now, last;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect])
- prot++;
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- /* Start erase on unprotected sectors
- */
- for (sect = s_first; sect <= s_last; sect++) {
- volatile ulong *addr =
- (volatile unsigned long *) info->start[sect];
-
- start = get_timer (0);
- last = start;
- if (info->protect[sect] == 0) {
- /* Disable interrupts which might cause a timeout here
- */
- flag = disable_interrupts ();
-
- /* Erase the block
- */
- addr[0] = 0x00200020;
- addr[1] = 0x00200020;
- addr[0] = 0x00D000D0;
- addr[1] = 0x00D000D0;
-
- /* re-enable interrupts if necessary
- */
- if (flag)
- enable_interrupts ();
-
- /* wait at least 80us - let's wait 1 ms
- */
- udelay (1000);
-
- last = start;
- while ((addr[0] & 0x00800080) != 0x00800080 ||
- (addr[1] & 0x00800080) != 0x00800080) {
- if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout (erase suspended!)\n");
- /* Suspend erase
- */
- addr[0] = 0x00B000B0;
- addr[1] = 0x00B000B0;
- goto DONE;
- }
- /* show that we're waiting
- */
- if ((now - last) > 1000) { /* every second */
- serial_putc ('.');
- last = now;
- }
- }
- if (addr[0] & 0x00220022 || addr[1] & 0x00220022) {
- printf ("*** ERROR: erase failed!\n");
- goto DONE;
- }
- }
- /* Clear status register and reset to read mode
- */
- addr[0] = 0x00500050;
- addr[1] = 0x00500050;
- addr[0] = 0x00FF00FF;
- addr[1] = 0x00FF00FF;
- }
-
- printf (" done\n");
-
-DONE:
- return 0;
-}
-
-static int write_word (flash_info_t *, volatile unsigned long *, ulong);
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- ulong v;
- int i, l, cc = cnt, res = 0;
-
-
- for (v=0; cc > 0; addr += 4, cc -= 4 - l) {
- l = (addr & 3);
- addr &= ~3;
-
- for (i = 0; i < 4; i++) {
- v = (v << 8) + (i < l || i - l >= cc ?
- *((unsigned char *) addr + i) : *src++);
- }
-
- if ((res = write_word (info, (volatile unsigned long *) addr, v)) != 0)
- break;
- }
-
- return (res);
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t * info, volatile unsigned long *addr,
- ulong data)
-{
- int flag, res = 0;
- ulong start;
-
- /* Check if Flash is (sufficiently) erased
- */
- if ((*addr & data) != data)
- return (2);
-
- /* Disable interrupts which might cause a timeout here
- */
- flag = disable_interrupts ();
-
- *addr = 0x00400040;
- *addr = data;
-
- /* re-enable interrupts if necessary
- */
- if (flag)
- enable_interrupts ();
-
- start = get_timer (0);
- while ((*addr & 0x00800080) != 0x00800080) {
- if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- /* Suspend program
- */
- *addr = 0x00B000B0;
- res = 1;
- goto OUT;
- }
- }
-
- if (*addr & 0x00220022) {
- printf ("*** ERROR: program failed!\n");
- res = 1;
- }
-
-OUT:
- /* Clear status register and reset to read mode
- */
- *addr = 0x00500050;
- *addr = 0x00FF00FF;
-
- return (res);
-}
diff --git a/board/pm828/pm828.c b/board/pm828/pm828.c
deleted file mode 100644
index f446543..0000000
--- a/board/pm828/pm828.c
+++ /dev/null
@@ -1,352 +0,0 @@
-/*
- * (C) Copyright 2001-2004
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc8260.h>
-#include <pci.h>
-#include <netdev.h>
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
- /* Port A configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 COL */
- /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 CRS */
- /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXER */
- /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */
- /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */
- /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXER */
- /* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* PA25 */
- /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* PA24 */
- /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* PA23 */
- /* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* PA22 */
- /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */
- /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */
- /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */
- /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */
- /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */
- /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD1*/
- /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */
- /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */
- /* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* PA13 */
- /* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* PA12 */
- /* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* PA11 */
- /* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* PA10 */
- /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* PA9 */
- /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* PA8 */
- /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
- /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */
- /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
- /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
- /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
- /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
- /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */
- /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
- },
-
- /* Port B configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TX_ER */
- /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RX_DV */
- /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 TX_EN */
-#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
-#ifdef CONFIG_ETHER_ON_FCC2
-#error "SCC1 conflicts with FCC2"
-#endif
- /* PB28 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TXD */
-#else
- /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RX_ER */
-#endif
- /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 COL */
- /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 CRS */
- /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[3] */
- /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[2] */
- /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[1] */
- /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[0] */
- /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[0] */
- /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[1] */
- /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[2] */
- /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[3] */
- /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */
- /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */
- /* PB15 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */
- /* PB14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC3 RXD */
- /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */
- /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */
- /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */
- /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */
- /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */
- /* PB8 */ { 1, 1, 1, 1, 0, 0 }, /* SCC3 TXD */
- /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
- /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */
- /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */
- /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */
- /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- },
-
- /* Port C */
- { /* conf ppar psor pdir podr pdat */
- /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
- /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
- /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 CTS */
- /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* SCC2 CTS */
- /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */
- /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
- /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
- /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
- /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* PC23 */
- /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 TXCK */
- /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXCK */
- /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 TXCK(2) */
- /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RXCK */
- /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 TXCK */
- /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
- /* PC16 */ { 0, 0, 0, 1, 0, 0 }, /* PC16 */
- /* PC15 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
- /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 DCD */
- /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
- /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* SCC2 DCD */
- /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 CTS */
- /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 DCD */
- /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* SCC4 CTS */
- /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* SCC4 DCD */
- /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
- /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
- /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
- /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
- /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
- /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* PC2 */
- /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* PC1 */
- /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* PC0 */
- },
-
- /* Port D */
- { /* conf ppar psor pdir podr pdat */
- /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RXD */
- /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* PD30 */
- /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 RTS */
- /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */
- /* PD27 */ { 0, 1, 0, 1, 0, 0 }, /* SCC2 RTS */
- /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
- /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
- /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
- /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 RTS */
- /* PD22 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4 RXD */
- /* PD21 */ { 1, 1, 0, 1, 0, 0 }, /* SCC4 TXD */
- /* PD20 */ { 0, 0, 1, 1, 0, 0 }, /* SCC4 RTS */
- /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
- /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
- /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* PD17 */
- /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* PD16 */
-#if defined(CONFIG_SYS_I2C_SOFT)
- /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */
- /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */
-#else
-#if defined(CONFIG_HARD_I2C)
- /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
- /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
-#else /* normal I/O port pins */
- /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
- /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */
-#endif
-#endif
- /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
- /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
- /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
- /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
- /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* PD9 */
- /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* PD8 */
- /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
- /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
- /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
- /* PD4 */ { 1, 1, 1, 0, 0, 0 }, /* SMC2 RXD */
- /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- }
-};
-
-/* ------------------------------------------------------------------------- */
-
-/* Check Board Identity:
- */
-int checkboard (void)
-{
- puts ("Board: PM828\n");
- return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-
-/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
- *
- * This routine performs standard 8260 initialization sequence
- * and calculates the available memory size. It may be called
- * several times to try different SDRAM configurations on both
- * 60x and local buses.
- */
-static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
- ulong orx, volatile uchar * base)
-{
- volatile uchar c = 0xff;
- volatile ulong cnt, val;
- volatile ulong *addr;
- volatile uint *sdmr_ptr;
- volatile uint *orx_ptr;
- int i;
- ulong save[32]; /* to make test non-destructive */
- ulong maxsize;
-
- /* We must be able to test a location outsize the maximum legal size
- * to find out THAT we are outside; but this address still has to be
- * mapped by the controller. That means, that the initial mapping has
- * to be (at least) twice as large as the maximum expected size.
- */
- maxsize = (1 + (~orx | 0x7fff)) / 2;
-
- sdmr_ptr = &memctl->memc_psdmr;
- orx_ptr = &memctl->memc_or2;
-
- *orx_ptr = orx;
-
- /*
- * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
- *
- * "At system reset, initialization software must set up the
- * programmable parameters in the memory controller banks registers
- * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
- * system software should execute the following initialization sequence
- * for each SDRAM device.
- *
- * 1. Issue a PRECHARGE-ALL-BANKS command
- * 2. Issue eight CBR REFRESH commands
- * 3. Issue a MODE-SET command to initialize the mode register
- *
- * The initial commands are executed by setting P/LSDMR[OP] and
- * accessing the SDRAM with a single-byte transaction."
- *
- * The appropriate BRx/ORx registers have already been set when we
- * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
- */
-
- *sdmr_ptr = sdmr | PSDMR_OP_PREA;
- *base = c;
-
- *sdmr_ptr = sdmr | PSDMR_OP_CBRR;
- for (i = 0; i < 8; i++)
- *base = c;
-
- *sdmr_ptr = sdmr | PSDMR_OP_MRW;
- *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */
-
- *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
- *base = c;
-
- /*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
- i = 0;
- for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
- addr = (volatile ulong *) base + cnt; /* pointer arith! */
- save[i++] = *addr;
- *addr = ~cnt;
- }
-
- addr = (volatile ulong *) base;
- save[i] = *addr;
- *addr = 0;
-
- if ((val = *addr) != 0) {
- *addr = save[i];
- return (0);
- }
-
- for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
- addr = (volatile ulong *) base + cnt; /* pointer arith! */
- val = *addr;
- *addr = save[--i];
- if (val != ~cnt) {
- /* Write the actual size to ORx
- */
- *orx_ptr = orx | ~(cnt * sizeof (long) - 1);
- return (cnt * sizeof (long));
- }
- }
- return (maxsize);
-}
-
-
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8260_t *memctl = &immap->im_memctl;
-
-#ifndef CONFIG_SYS_RAMBOOT
- ulong size8, size9;
-#endif
- ulong psize = 32 * 1024 * 1024;
-
- memctl->memc_psrt = CONFIG_SYS_PSRT;
- memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-
-#ifndef CONFIG_SYS_RAMBOOT
- size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
- (uchar *) CONFIG_SYS_SDRAM_BASE);
- size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL,
- (uchar *) CONFIG_SYS_SDRAM_BASE);
-
- if (size8 < size9) {
- psize = size9;
- printf ("(60x:9COL) ");
- } else {
- psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
- (uchar *) CONFIG_SYS_SDRAM_BASE);
- printf ("(60x:8COL) ");
- }
-#endif
- return (psize);
-}
-
-#if defined(CONFIG_CMD_DOC)
-void doc_init (void)
-{
- doc_probe (CONFIG_SYS_DOC_BASE);
-}
-#endif
-
-#ifdef CONFIG_PCI
-struct pci_controller hose;
-
-extern void pci_mpc8250_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
- pci_mpc8250_init(&hose);
-}
-#endif
-
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
diff --git a/configs/PM825_BIGFLASH_defconfig b/configs/PM825_BIGFLASH_defconfig
deleted file mode 100644
index 75efcdd..0000000
--- a/configs/PM825_BIGFLASH_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="PCI,FLASH_32MB,SYS_TEXT_BASE=0x40000000"
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_PM826=y
diff --git a/configs/PM825_ROMBOOT_BIGFLASH_defconfig b/configs/PM825_ROMBOOT_BIGFLASH_defconfig
deleted file mode 100644
index 28ff17f..0000000
--- a/configs/PM825_ROMBOOT_BIGFLASH_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="PCI,BOOT_ROM,FLASH_32MB,SYS_TEXT_BASE=0xFF800000"
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_PM826=y
diff --git a/configs/PM825_ROMBOOT_defconfig b/configs/PM825_ROMBOOT_defconfig
deleted file mode 100644
index f5233fa..0000000
--- a/configs/PM825_ROMBOOT_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="PCI,BOOT_ROM,SYS_TEXT_BASE=0xFF800000"
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_PM826=y
diff --git a/configs/PM825_defconfig b/configs/PM825_defconfig
deleted file mode 100644
index 459cdba..0000000
--- a/configs/PM825_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="PCI,SYS_TEXT_BASE=0xFF000000"
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_PM826=y
diff --git a/configs/PM826_BIGFLASH_defconfig b/configs/PM826_BIGFLASH_defconfig
deleted file mode 100644
index 0acf9d2..0000000
--- a/configs/PM826_BIGFLASH_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="FLASH_32MB,SYS_TEXT_BASE=0x40000000"
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_PM826=y
diff --git a/configs/PM826_ROMBOOT_BIGFLASH_defconfig b/configs/PM826_ROMBOOT_BIGFLASH_defconfig
deleted file mode 100644
index af8d4c9..0000000
--- a/configs/PM826_ROMBOOT_BIGFLASH_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="BOOT_ROM,FLASH_32MB,SYS_TEXT_BASE=0xFF800000"
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_PM826=y
diff --git a/configs/PM826_ROMBOOT_defconfig b/configs/PM826_ROMBOOT_defconfig
deleted file mode 100644
index 7d3e1c3..0000000
--- a/configs/PM826_ROMBOOT_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="BOOT_ROM,SYS_TEXT_BASE=0xFF800000"
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_PM826=y
diff --git a/configs/PM826_defconfig b/configs/PM826_defconfig
deleted file mode 100644
index b2f9d34..0000000
--- a/configs/PM826_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFF000000"
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_PM826=y
diff --git a/configs/PM828_PCI_defconfig b/configs/PM828_PCI_defconfig
deleted file mode 100644
index 9b68562..0000000
--- a/configs/PM828_PCI_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="PCI"
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_PM828=y
diff --git a/configs/PM828_ROMBOOT_PCI_defconfig b/configs/PM828_ROMBOOT_PCI_defconfig
deleted file mode 100644
index 8120058..0000000
--- a/configs/PM828_ROMBOOT_PCI_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="PCI,BOOT_ROM,SYS_TEXT_BASE=0xFF800000"
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_PM828=y
diff --git a/configs/PM828_ROMBOOT_defconfig b/configs/PM828_ROMBOOT_defconfig
deleted file mode 100644
index 7c8980e..0000000
--- a/configs/PM828_ROMBOOT_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="BOOT_ROM,SYS_TEXT_BASE=0xFF800000"
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_PM828=y
diff --git a/configs/PM828_defconfig b/configs/PM828_defconfig
deleted file mode 100644
index 15887ca..0000000
--- a/configs/PM828_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_PM828=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index d358d62..f1c2f8b 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,9 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+PM825 powerpc mpc8260 - - Wolfgang Denk <wd@denx.de>
+PM826 powerpc mpc8260 - - Wolfgang Denk <wd@denx.de>
+PM828 powerpc mpc8260 - -
MPC8266ADS powerpc mpc8260 - - Rune Torgersen <runet@innovsys.com>
VoVPN-GW powerpc mpc8260 - -
ep8260 powerpc mpc8260 - - Frank Panno <fpanno@delphintech.com>
diff --git a/include/configs/PM826.h b/include/configs/PM826.h
deleted file mode 100644
index 6416ad5..0000000
--- a/include/configs/PM826.h
+++ /dev/null
@@ -1,534 +0,0 @@
-/*
- * (C) Copyright 2001-2005
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#undef CONFIG_SYS_RAMBOOT
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_PM826 1 /* ...on a PM8260 module */
-#define CONFIG_CPM2 1 /* Has a CPM2 */
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xFF000000 /* Standard: boot 64-bit flash */
-#endif
-
-#undef CONFIG_DB_CR826_J30x_ON /* J30x jumpers on D.B. carrier */
-
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
-
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND \
- "bootp; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
- "bootm"
-
-/* enable I2C and select the hardware/software driver */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED 50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE (iop->pdir |= 0x00010000)
-#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
-#define I2C_READ ((iop->pdat & 0x00010000) != 0)
-#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
- else iop->pdat &= ~0x00010000
-#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
- else iop->pdat &= ~0x00020000
-#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
-
-
-#define CONFIG_RTC_PCF8563
-#define CONFIG_SYS_I2C_RTC_ADDR 0x51
-
-/*
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * if CONFIG_CONS_NONE is defined, then the serial console routines must
- * defined elsewhere (for example, on the cogent platform, there are serial
- * ports on the motherboard which are used for the serial console - see
- * cogent/cma101/serial.[ch]).
- */
-#define CONFIG_CONS_ON_SMC /* define if console on SMC */
-#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
-#undef CONFIG_CONS_NONE /* define if console on something else*/
-#define CONFIG_CONS_INDEX 2 /* which serial channel for console */
-
-/*
- * select ethernet configuration
- *
- * if CONFIG_ETHER_ON_SCC is selected, then
- * - CONFIG_ETHER_INDEX must be set to the channel number (1-4)
- *
- * if CONFIG_ETHER_ON_FCC is selected, then
- * - one or more CONFIG_ETHER_ON_FCCx (x=1,2,3) must also be selected
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
- */
-#undef CONFIG_ETHER_NONE /* define if ether on something else */
-
-#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
-#define CONFIG_ETHER_INDEX 1 /* which SCC channel for ethernet */
-
-#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
-/*
- * - Rx-CLK is CLK11
- * - Tx-CLK is CLK10
- */
-#define CONFIG_ETHER_ON_FCC1
-# define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
-#ifndef CONFIG_DB_CR826_J30x_ON
-# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK10)
-#else
-# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
-#endif
-/*
- * - Rx-CLK is CLK15
- * - Tx-CLK is CLK14
- */
-#define CONFIG_ETHER_ON_FCC2
-# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
-# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
-/*
- * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CONFIG_SYS_CPMFCR_RAMTYPE 0
-# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
-
-/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
-#define CONFIG_8260_CLKIN 64000000 /* in Hz */
-
-#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
-#define CONFIG_BAUDRATE 230400
-#else
-#define CONFIG_BAUDRATE 9600
-#endif
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BEDBUG
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_SNTP
-
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_CMD_PCI
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * Flash and Boot ROM mapping
- */
-#ifdef CONFIG_FLASH_32MB
-#define CONFIG_SYS_FLASH0_BASE 0x40000000
-#define CONFIG_SYS_FLASH0_SIZE 0x02000000
-#else
-#define CONFIG_SYS_FLASH0_BASE 0xFF000000
-#define CONFIG_SYS_FLASH0_SIZE 0x00800000
-#endif
-#define CONFIG_SYS_BOOTROM_BASE 0xFF800000
-#define CONFIG_SYS_BOOTROM_SIZE 0x00080000
-#define CONFIG_SYS_DOC_BASE 0xFF800000
-#define CONFIG_SYS_DOC_SIZE 0x00100000
-
-/* Flash bank size (for preliminary settings)
- */
-#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
-#ifdef CONFIG_FLASH_32MB
-#define CONFIG_SYS_MAX_FLASH_SECT 135 /* max num of sects on one chip */
-#else
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
-#endif
-#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
-
-#if 0
-/* Start port with environment in flash; switch to EEPROM later */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x40000)
-#define CONFIG_ENV_SIZE 0x40000
-#define CONFIG_ENV_SECT_SIZE 0x40000
-#else
-/* Final version: environment in EEPROM */
-#define CONFIG_ENV_IS_IN_EEPROM 1
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-#define CONFIG_ENV_OFFSET 512
-#define CONFIG_ENV_SIZE (2048 - 512)
-#endif
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
- *
- * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
- * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
- */
-#if defined(CONFIG_BOOT_ROM)
-#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS01 | HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
-#else
-#define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
-#endif
-
-/* no slaves so just fill with zeros */
-#define CONFIG_SYS_HRCW_SLAVE1 0
-#define CONFIG_SYS_HRCW_SLAVE2 0
-#define CONFIG_SYS_HRCW_SLAVE3 0
-#define CONFIG_SYS_HRCW_SLAVE4 0
-#define CONFIG_SYS_HRCW_SLAVE5 0
-#define CONFIG_SYS_HRCW_SLAVE6 0
-#define CONFIG_SYS_HRCW_SLAVE7 0
-
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xF0000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- *
- * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE, local SDRAM
- * is mapped at SDRAM_BASE2_PRELIM.
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-# define CONFIG_SYS_RAMBOOT
-#endif
-
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_PNP
-#define CONFIG_EEPRO100
-#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
-#endif
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers 2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
- HID0_IFEM|HID0_ABE)
-#define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE)
-#define CONFIG_SYS_HID2 0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register 5-5
- *-----------------------------------------------------------------------
- * turn on Checkstop Reset Enable
- */
-#define CONFIG_SYS_RMR RMR_CSRE
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration 4-25
- *-----------------------------------------------------------------------
- */
-
-#define BCR_APD01 0x10000000
-#define CONFIG_SYS_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 4-31
- *-----------------------------------------------------------------------
- */
-#if 0
-#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_CS10PC01)
-#else
-#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10)
-#endif
-
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 4-35
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
- SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
- SYPCR_SWRI|SYPCR_SWP)
-#endif /* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control 4-40
- *-----------------------------------------------------------------------
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- */
-#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control 9-8
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_SCCR (SCCR_DFBRG00)
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration 13-7
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RCCR 0
-
-/*
- * Init Memory Controller:
- *
- * Bank Bus Machine PortSz Device
- * ---- --- ------- ------ ------
- * 0 60x GPCM 64 bit FLASH
- * 1 60x SDRAM 64 bit SDRAM
- *
- */
-
- /* Initialize SDRAM on local bus
- */
-#define CONFIG_SYS_INIT_LOCAL_SDRAM
-
-
-/* Minimum mask to separate preliminary
- * address ranges for CS[0:2]
- */
-#define CONFIG_SYS_MIN_AM_MASK 0xC0000000
-
-/*
- * we use the same values for 32 MB and 128 MB SDRAM
- * refresh rate = 7.73 uS (64 MHz Bus Clock)
- */
-#define CONFIG_SYS_MPTPR 0x2000
-#define CONFIG_SYS_PSRT 0x0E
-
-#define CONFIG_SYS_MRS_OFFS 0x00000000
-
-
-#if defined(CONFIG_BOOT_ROM)
-/*
- * Bank 0 - Boot ROM (8 bit wide)
- */
-#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
- BRx_PS_8 |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE) |\
- ORxG_CSNT |\
- ORxG_ACS_DIV1 |\
- ORxG_SCY_3_CLK |\
- ORxG_EHTR |\
- ORxG_TRLX)
-
-/*
- * Bank 1 - Flash (64 bit wide)
- */
-#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
- BRx_PS_64 |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
- ORxG_CSNT |\
- ORxG_ACS_DIV1 |\
- ORxG_SCY_3_CLK |\
- ORxG_EHTR |\
- ORxG_TRLX)
-
-#else /* ! CONFIG_BOOT_ROM */
-
-/*
- * Bank 0 - Flash (64 bit wide)
- */
-#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
- BRx_PS_64 |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
- ORxG_CSNT |\
- ORxG_ACS_DIV1 |\
- ORxG_SCY_3_CLK |\
- ORxG_EHTR |\
- ORxG_TRLX)
-
-/*
- * Bank 1 - Disk-On-Chip
- */
-#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_DOC_BASE & BRx_BA_MSK) |\
- BRx_PS_8 |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE) |\
- ORxG_CSNT |\
- ORxG_ACS_DIV1 |\
- ORxG_SCY_3_CLK |\
- ORxG_EHTR |\
- ORxG_TRLX)
-
-#endif /* CONFIG_BOOT_ROM */
-
-/* Bank 2 - SDRAM
- */
-
-#ifndef CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
- BRx_PS_64 |\
- BRx_MS_SDRAM_P |\
- BRx_V)
-
- /* SDRAM initialization values for 8-column chips
- */
-#define CONFIG_SYS_OR2_8COL (CONFIG_SYS_MIN_AM_MASK |\
- ORxS_BPD_4 |\
- ORxS_ROWST_PBI0_A9 |\
- ORxS_NUMR_12)
-
-#define CONFIG_SYS_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\
- PSDMR_BSMA_A14_A16 |\
- PSDMR_SDA10_PBI0_A10 |\
- PSDMR_RFRC_7_CLK |\
- PSDMR_PRETOACT_2W |\
- PSDMR_ACTTORW_1W |\
- PSDMR_LDOTOPRE_1C |\
- PSDMR_WRC_1C |\
- PSDMR_CL_2)
-
- /* SDRAM initialization values for 9-column chips
- */
-#define CONFIG_SYS_OR2_9COL (CONFIG_SYS_MIN_AM_MASK |\
- ORxS_BPD_4 |\
- ORxS_ROWST_PBI0_A7 |\
- ORxS_NUMR_13)
-
-#define CONFIG_SYS_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\
- PSDMR_BSMA_A13_A15 |\
- PSDMR_SDA10_PBI0_A9 |\
- PSDMR_RFRC_7_CLK |\
- PSDMR_PRETOACT_2W |\
- PSDMR_ACTTORW_1W |\
- PSDMR_LDOTOPRE_1C |\
- PSDMR_WRC_1C |\
- PSDMR_CL_2)
-
-#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_9COL
-#define CONFIG_SYS_PSDMR CONFIG_SYS_PSDMR_9COL
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/PM828.h b/include/configs/PM828.h
deleted file mode 100644
index e17fbfb..0000000
--- a/include/configs/PM828.h
+++ /dev/null
@@ -1,528 +0,0 @@
-/*
- * (C) Copyright 2001-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#undef CONFIG_SYS_RAMBOOT
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_PM828 1 /* ...on a PM828 module */
-#define CONFIG_CPM2 1 /* Has a CPM2 */
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0x40000000 /* Standard: boot 64-bit flash */
-#endif
-
-#undef CONFIG_DB_CR826_J30x_ON /* J30x jumpers on D.B. carrier */
-
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
-
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND \
- "bootp;" \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
- "bootm"
-
-/* enable I2C and select the hardware/software driver */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED 50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE (iop->pdir |= 0x00010000)
-#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
-#define I2C_READ ((iop->pdat & 0x00010000) != 0)
-#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
- else iop->pdat &= ~0x00010000
-#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
- else iop->pdat &= ~0x00020000
-#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
-
-
-#define CONFIG_RTC_PCF8563
-#define CONFIG_SYS_I2C_RTC_ADDR 0x51
-
-/*
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * if CONFIG_CONS_NONE is defined, then the serial console routines must
- * defined elsewhere (for example, on the cogent platform, there are serial
- * ports on the motherboard which are used for the serial console - see
- * cogent/cma101/serial.[ch]).
- */
-#define CONFIG_CONS_ON_SMC /* define if console on SMC */
-#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
-#undef CONFIG_CONS_NONE /* define if console on something else*/
-#define CONFIG_CONS_INDEX 2 /* which serial channel for console */
-
-/*
- * select ethernet configuration
- *
- * if CONFIG_ETHER_ON_SCC is selected, then
- * - CONFIG_ETHER_INDEX must be set to the channel number (1-4)
- *
- * if CONFIG_ETHER_ON_FCC is selected, then
- * - one or more CONFIG_ETHER_ON_FCCx (x=1,2,3) must also be selected
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
- */
-#undef CONFIG_ETHER_NONE /* define if ether on something else */
-
-#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
-#define CONFIG_ETHER_INDEX 1 /* which SCC channel for ethernet */
-
-#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
-/*
- * - Rx-CLK is CLK11
- * - Tx-CLK is CLK10
- */
-#define CONFIG_ETHER_ON_FCC1
-# define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
-#ifndef CONFIG_DB_CR826_J30x_ON
-# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK10)
-#else
-# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
-#endif
-/*
- * - Rx-CLK is CLK15
- * - Tx-CLK is CLK14
- */
-#define CONFIG_ETHER_ON_FCC2
-# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
-# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
-/*
- * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CONFIG_SYS_CPMFCR_RAMTYPE 0
-# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
-
-/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
-#define CONFIG_8260_CLKIN 100000000 /* in Hz */
-
-#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
-#define CONFIG_BAUDRATE 230400
-#else
-#define CONFIG_BAUDRATE 9600
-#endif
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BEDBUG
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_SNTP
-
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_CMD_PCI
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * Flash and Boot ROM mapping
- */
-
-#define CONFIG_SYS_BOOTROM_BASE 0xFF800000
-#define CONFIG_SYS_BOOTROM_SIZE 0x00080000
-#define CONFIG_SYS_FLASH0_BASE 0x40000000
-#define CONFIG_SYS_FLASH0_SIZE 0x02000000
-#define CONFIG_SYS_DOC_BASE 0xFF800000
-#define CONFIG_SYS_DOC_SIZE 0x00100000
-
-
-/* Flash bank size (for preliminary settings)
- */
-#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 135 /* max num of sects on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
-
-#if 0
-/* Start port with environment in flash; switch to EEPROM later */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x40000)
-#define CONFIG_ENV_SIZE 0x40000
-#define CONFIG_ENV_SECT_SIZE 0x40000
-#else
-/* Final version: environment in EEPROM */
-#define CONFIG_ENV_IS_IN_EEPROM 1
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-#define CONFIG_ENV_OFFSET 512
-#define CONFIG_ENV_SIZE (2048 - 512)
-#endif
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
- *
- * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
- * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
- */
-#if defined(CONFIG_BOOT_ROM)
-#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS01 | HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
-#else
-#define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
-#endif
-
-/* no slaves so just fill with zeros */
-#define CONFIG_SYS_HRCW_SLAVE1 0
-#define CONFIG_SYS_HRCW_SLAVE2 0
-#define CONFIG_SYS_HRCW_SLAVE3 0
-#define CONFIG_SYS_HRCW_SLAVE4 0
-#define CONFIG_SYS_HRCW_SLAVE5 0
-#define CONFIG_SYS_HRCW_SLAVE6 0
-#define CONFIG_SYS_HRCW_SLAVE7 0
-
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xF0000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- *
- * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE, local SDRAM
- * is mapped@SDRAM_BASE2_PRELIM.
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-# define CONFIG_SYS_RAMBOOT
-#endif
-
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_PNP
-#define CONFIG_EEPRO100
-#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
-#endif
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers 2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
- HID0_IFEM|HID0_ABE)
-#define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE)
-#define CONFIG_SYS_HID2 0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register 5-5
- *-----------------------------------------------------------------------
- * turn on Checkstop Reset Enable
- */
-#define CONFIG_SYS_RMR RMR_CSRE
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration 4-25
- *-----------------------------------------------------------------------
- */
-
-#define BCR_APD01 0x10000000
-#define CONFIG_SYS_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 4-31
- *-----------------------------------------------------------------------
- */
-#if 0
-#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_CS10PC01)
-#else
-#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10)
-#endif
-
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 4-35
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
- SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
- SYPCR_SWRI|SYPCR_SWP)
-#endif /* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control 4-40
- *-----------------------------------------------------------------------
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- */
-#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control 9-8
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_SCCR (SCCR_DFBRG00)
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration 13-7
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RCCR 0
-
-/*
- * Init Memory Controller:
- *
- * Bank Bus Machine PortSz Device
- * ---- --- ------- ------ ------
- * 0 60x GPCM 64 bit FLASH
- * 1 60x SDRAM 64 bit SDRAM
- *
- */
-
- /* Initialize SDRAM on local bus
- */
-#define CONFIG_SYS_INIT_LOCAL_SDRAM
-
-
-/* Minimum mask to separate preliminary
- * address ranges for CS[0:2]
- */
-#define CONFIG_SYS_MIN_AM_MASK 0xC0000000
-
-/*
- * we use the same values for 32 MB and 128 MB SDRAM
- * refresh rate = 7.68 uS (100 MHz Bus Clock)
- */
-#define CONFIG_SYS_MPTPR 0x2000
-#define CONFIG_SYS_PSRT 0x16
-
-#define CONFIG_SYS_MRS_OFFS 0x00000000
-
-
-#if defined(CONFIG_BOOT_ROM)
-/*
- * Bank 0 - Boot ROM (8 bit wide)
- */
-#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
- BRx_PS_8 |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE) |\
- ORxG_CSNT |\
- ORxG_ACS_DIV1 |\
- ORxG_SCY_5_CLK |\
- ORxG_EHTR |\
- ORxG_TRLX)
-
-/*
- * Bank 1 - Flash (64 bit wide)
- */
-#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
- BRx_PS_64 |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
- ORxG_CSNT |\
- ORxG_ACS_DIV1 |\
- ORxG_SCY_5_CLK |\
- ORxG_EHTR |\
- ORxG_TRLX)
-
-#else /* ! CONFIG_BOOT_ROM */
-
-/*
- * Bank 0 - Flash (64 bit wide)
- */
-#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
- BRx_PS_64 |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
- ORxG_CSNT |\
- ORxG_ACS_DIV1 |\
- ORxG_SCY_5_CLK |\
- ORxG_EHTR |\
- ORxG_TRLX)
-
-/*
- * Bank 1 - Disk-On-Chip
- */
-#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_DOC_BASE & BRx_BA_MSK) |\
- BRx_PS_8 |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE) |\
- ORxG_CSNT |\
- ORxG_ACS_DIV1 |\
- ORxG_SCY_5_CLK |\
- ORxG_EHTR |\
- ORxG_TRLX)
-
-#endif /* CONFIG_BOOT_ROM */
-
-/* Bank 2 - SDRAM
- */
-
-#ifndef CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
- BRx_PS_64 |\
- BRx_MS_SDRAM_P |\
- BRx_V)
-
- /* SDRAM initialization values for 8-column chips
- */
-#define CONFIG_SYS_OR2_8COL (CONFIG_SYS_MIN_AM_MASK |\
- ORxS_BPD_4 |\
- ORxS_ROWST_PBI0_A9 |\
- ORxS_NUMR_12)
-
-#define CONFIG_SYS_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\
- PSDMR_BSMA_A14_A16 |\
- PSDMR_SDA10_PBI0_A10 |\
- PSDMR_RFRC_7_CLK |\
- PSDMR_PRETOACT_2W |\
- PSDMR_ACTTORW_2W |\
- PSDMR_LDOTOPRE_1C |\
- PSDMR_WRC_1C |\
- PSDMR_CL_2)
-
- /* SDRAM initialization values for 9-column chips
- */
-#define CONFIG_SYS_OR2_9COL (CONFIG_SYS_MIN_AM_MASK |\
- ORxS_BPD_4 |\
- ORxS_ROWST_PBI0_A7 |\
- ORxS_NUMR_13)
-
-#define CONFIG_SYS_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\
- PSDMR_BSMA_A13_A15 |\
- PSDMR_SDA10_PBI0_A9 |\
- PSDMR_RFRC_7_CLK |\
- PSDMR_PRETOACT_2W |\
- PSDMR_ACTTORW_2W |\
- PSDMR_LDOTOPRE_1C |\
- PSDMR_WRC_1C |\
- PSDMR_CL_2)
-
-#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_9COL
-#define CONFIG_SYS_PSDMR CONFIG_SYS_PSDMR_9COL
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-#endif /* __CONFIG_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [U-Boot] [PATCH 20/26] mpc8260: remove muas3001 board support
2014-12-15 14:26 [U-Boot] [PATCH 0/26] Start removing non-generic boards Masahiro Yamada
` (18 preceding siblings ...)
2014-12-15 14:26 ` [U-Boot] [PATCH 19/26] mpc8260: remove PM825, PM826, PM828 " Masahiro Yamada
@ 2014-12-15 14:26 ` Masahiro Yamada
2015-01-05 18:21 ` Tom Rini
2014-12-15 14:26 ` [U-Boot] [PATCH 21/26] mpc8260: remove IPHASE4539 " Masahiro Yamada
` (7 subsequent siblings)
27 siblings, 1 reply; 55+ messages in thread
From: Masahiro Yamada @ 2014-12-15 14:26 UTC (permalink / raw)
To: u-boot
This board is still a non-generic board.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Heiko Schocher <hs@denx.de>
---
arch/powerpc/cpu/mpc8260/Kconfig | 4 -
board/muas3001/Kconfig | 9 -
board/muas3001/MAINTAINERS | 7 -
board/muas3001/Makefile | 8 -
board/muas3001/muas3001.c | 335 ---------------------------------
configs/muas3001_defconfig | 3 -
configs/muas3001_dev_defconfig | 4 -
doc/README.scrapyard | 1 +
include/configs/muas3001.h | 391 ---------------------------------------
9 files changed, 1 insertion(+), 761 deletions(-)
delete mode 100644 board/muas3001/Kconfig
delete mode 100644 board/muas3001/MAINTAINERS
delete mode 100644 board/muas3001/Makefile
delete mode 100644 board/muas3001/muas3001.c
delete mode 100644 configs/muas3001_defconfig
delete mode 100644 configs/muas3001_dev_defconfig
delete mode 100644 include/configs/muas3001.h
diff --git a/arch/powerpc/cpu/mpc8260/Kconfig b/arch/powerpc/cpu/mpc8260/Kconfig
index cb81cdc..2b3c9c2 100644
--- a/arch/powerpc/cpu/mpc8260/Kconfig
+++ b/arch/powerpc/cpu/mpc8260/Kconfig
@@ -25,9 +25,6 @@ config TARGET_GW8260
config TARGET_IPHASE4539
bool "Support IPHASE4539"
-config TARGET_MUAS3001
- bool "Support muas3001"
-
config TARGET_KM82XX
bool "Support km82xx"
@@ -40,6 +37,5 @@ source "board/ep82xxm/Kconfig"
source "board/gw8260/Kconfig"
source "board/iphase4539/Kconfig"
source "board/keymile/km82xx/Kconfig"
-source "board/muas3001/Kconfig"
endmenu
diff --git a/board/muas3001/Kconfig b/board/muas3001/Kconfig
deleted file mode 100644
index 94a00b3..0000000
--- a/board/muas3001/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_MUAS3001
-
-config SYS_BOARD
- default "muas3001"
-
-config SYS_CONFIG_NAME
- default "muas3001"
-
-endif
diff --git a/board/muas3001/MAINTAINERS b/board/muas3001/MAINTAINERS
deleted file mode 100644
index cfb5983..0000000
--- a/board/muas3001/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-MUAS3001 BOARD
-M: Heiko Schocher <hs@denx.de>
-S: Maintained
-F: board/muas3001/
-F: include/configs/muas3001.h
-F: configs/muas3001_defconfig
-F: configs/muas3001_dev_defconfig
diff --git a/board/muas3001/Makefile b/board/muas3001/Makefile
deleted file mode 100644
index ef04960..0000000
--- a/board/muas3001/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2001-2008
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := muas3001.o
diff --git a/board/muas3001/muas3001.c b/board/muas3001/muas3001.c
deleted file mode 100644
index e0c4dba..0000000
--- a/board/muas3001/muas3001.c
+++ /dev/null
@@ -1,335 +0,0 @@
-/*
- * (C) Copyright 2008
- * Heiko Schocher, DENX Software Engineering, hs at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8260.h>
-#include <ioports.h>
-
-#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
-#include <libfdt.h>
-#endif
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-const iop_conf_t iop_conf_tab[4][32] = {
-
- /* Port A */
- { /* conf ppar psor pdir podr pdat */
- /* PA31 */ { 0, 0, 0, 0, 0, 0 }, /* PA31 */
- /* PA30 */ { 0, 0, 0, 0, 0, 0 }, /* PA30 */
- /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXER */
- /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */
- /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */
- /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXER */
- /* PA25 */ { 1, 0, 0, 1, 0, 0 }, /* ETH_PWRDWN */
- /* PA24 */ { 1, 0, 0, 1, 0, 1 }, /* ETH_RESET */
- /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */
- /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */
- /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */
- /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */
- /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */
- /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */
- /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */
- /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD1 */
- /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */
- /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */
- /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */
- /* PA12 */ { 1, 0, 0, 1, 0, 0 }, /* ETH_SLEEP */
- /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */
- /* PA10 */ { 1, 0, 0, 1, 0, 0 }, /* MDIO */
- /* PA9 */ { 1, 0, 0, 1, 0, 0 }, /* MDC */
- /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RxD */
- /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */
- /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */
- /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */
- /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */
- /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */
- /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */
- /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */
- /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */
- },
-
- /* Port B */
- { /* conf ppar psor pdir podr pdat */
- /* PB31 */ { 0, 0, 0, 0, 0, 0 }, /* PB31 */
- /* PB30 */ { 0, 0, 0, 0, 0, 0 }, /* PB30 */
- /* PB29 */ { 0, 0, 0, 0, 0, 0 }, /* PB29 */
- /* PB28 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TxD */
- /* PB27 */ { 0, 0, 0, 0, 0, 0 }, /* PB27 */
- /* PB26 */ { 0, 0, 0, 0, 0, 0 }, /* PB26 */
- /* PB25 */ { 0, 0, 0, 0, 0, 0 }, /* PB25 */
- /* PB24 */ { 0, 0, 0, 0, 0, 0 }, /* PB24 */
- /* PB23 */ { 0, 0, 0, 0, 0, 0 }, /* PB23 */
- /* PB22 */ { 0, 0, 0, 0, 0, 0 }, /* PB22 */
- /* PB21 */ { 0, 0, 0, 0, 0, 0 }, /* PB21 */
- /* PB20 */ { 0, 0, 0, 0, 0, 0 }, /* PB20 */
- /* PB19 */ { 0, 0, 0, 0, 0, 0 }, /* PB19 */
- /* PB18 */ { 0, 0, 0, 0, 0, 0 }, /* PB18 */
- /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB15 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RxD */
- /* PB14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC3 RxD */
- /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB12 */ { 1, 1, 1, 1, 0, 0 }, /* SCC2 TxD */
- /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB8 */ { 1, 1, 1, 1, 0, 0 }, /* SCC3 TxD */
- /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
- },
-
- /* Port C */
- { /* conf ppar psor pdir podr pdat */
- /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
- /* PC30 */ { 1, 1, 1, 1, 0, 0 }, /* Timer1 OUT */
- /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */
- /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
- /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
- /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
- /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
- /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
- /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
- /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* PC22 */
- /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC RxCLK 11 */
- /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC TxCLK 12 */
- /* PC19 */ { 0, 0, 0, 0, 0, 0 }, /* PC19 */
- /* PC18 */ { 0, 0, 0, 0, 0, 0 }, /* PC18 */
- /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
- /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */
- /* PC15 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TxD */
- /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
- /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
- /* PC12 */ { 1, 0, 0, 1, 0, 0 }, /* TX OUTPUT SLEW1 */
- /* PC11 */ { 1, 0, 0, 1, 0, 0 }, /* TX OUTPUT SLEW0 */
- /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
- /* PC9 */ { 1, 0, 0, 1, 0, 1 }, /* SPA_TX_EN */
- /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */
- /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
- /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
- /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
- /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
- /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
- /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
- /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
- /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */
- },
-
- /* Port D */
- { /* conf ppar psor pdir podr pdat */
- /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RxD */
- /* PD30 */ { 0, 0, 0, 0, 0, 0 }, /* PD30 */
- /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */
- /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */
- /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */
- /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */
- /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */
- /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */
- /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */
- /* PD22 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4: RXD */
- /* PD21 */ { 1, 1, 0, 1, 0, 0 }, /* SCC4: TXD */
- /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */
- /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */
- /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */
- /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */
- /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */
-#if defined(CONFIG_HARD_I2C)
- /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
- /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
-#else
- /* PD15 */ { 1, 0, 0, 0, 1, 1 }, /* PD15 */
- /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* PD14 */
-#endif
- /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
- /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
- /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
- /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
- /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TxD */
- /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RxD */
- /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */
- /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */
- /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */
- /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */
- /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
- }
-};
-
-/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
- *
- * This routine performs standard 8260 initialization sequence
- * and calculates the available memory size. It may be called
- * several times to try different SDRAM configurations on both
- * 60x and local buses.
- */
-static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
- ulong orx, volatile uchar * base)
-{
- volatile uchar c = 0xff;
- volatile uint *sdmr_ptr;
- volatile uint *orx_ptr;
- ulong maxsize, size;
- int i;
-
- /* We must be able to test a location outsize the maximum legal size
- * to find out THAT we are outside; but this address still has to be
- * mapped by the controller. That means, that the initial mapping has
- * to be (at least) twice as large as the maximum expected size.
- */
- maxsize = (1 + (~orx | 0x7fff))/* / 2*/;
-
- sdmr_ptr = &memctl->memc_psdmr;
- orx_ptr = &memctl->memc_or1;
-
- *orx_ptr = orx;
-
- /*
- * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
- *
- * "At system reset, initialization software must set up the
- * programmable parameters in the memory controller banks registers
- * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
- * system software should execute the following initialization sequence
- * for each SDRAM device.
- *
- * 1. Issue a PRECHARGE-ALL-BANKS command
- * 2. Issue eight CBR REFRESH commands
- * 3. Issue a MODE-SET command to initialize the mode register
- *
- * The initial commands are executed by setting P/LSDMR[OP] and
- * accessing the SDRAM with a single-byte transaction."
- *
- * The appropriate BRx/ORx registers have already been set when we
- * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
- */
-
- *sdmr_ptr = sdmr | PSDMR_OP_PREA;
- *base = c;
-
- *sdmr_ptr = sdmr | PSDMR_OP_CBRR;
- for (i = 0; i < 8; i++)
- *base = c;
-
- *sdmr_ptr = sdmr | PSDMR_OP_MRW;
- *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */
-
- *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
- *base = c;
-
- size = get_ram_size ((long *)base, maxsize);
- *orx_ptr = orx | ~(size - 1);
-
- return (size);
-}
-
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8260_t *memctl = &immap->im_memctl;
- long psize;
- long sizelittle, sizebig;
-
- memctl->memc_psrt = CONFIG_SYS_PSRT;
- memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-
- /* 60x SDRAM setup:
- */
- sizelittle = try_init (memctl, CONFIG_SYS_PSDMR_LITTLE, CONFIG_SYS_OR1_LITTLE,
- (uchar *) CONFIG_SYS_SDRAM_BASE);
- sizebig = try_init (memctl, CONFIG_SYS_PSDMR_BIG, CONFIG_SYS_OR1_BIG,
- (uchar *) CONFIG_SYS_SDRAM_BASE);
- if (sizelittle < sizebig) {
- psize = sizebig;
- } else {
- psize = try_init (memctl, CONFIG_SYS_PSDMR_LITTLE, CONFIG_SYS_OR1_LITTLE,
- (uchar *) CONFIG_SYS_SDRAM_BASE);
- }
-
- icache_enable ();
-
- return (psize);
-}
-
-int checkboard (void)
-{
- puts ("Board: MUAS3001\n");
-
- return 0;
-}
-
-/*
- * Early board initalization.
- */
-int board_early_init_r (void)
-{
- return 0;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * update "memory" property in the blob
- */
-void ft_blob_update (void *blob, bd_t *bd)
-{
- int ret, nodeoffset = 0;
- ulong flash_data[4] = {0};
- ulong speed = 0;
-
- /* update Flash addr, size */
- flash_data[2] = cpu_to_be32 (CONFIG_SYS_FLASH_BASE);
- flash_data[3] = cpu_to_be32 (CONFIG_SYS_FLASH_SIZE);
- nodeoffset = fdt_path_offset (blob, "/localbus");
- if (nodeoffset >= 0) {
- ret = fdt_setprop (blob, nodeoffset, "ranges", flash_data,
- sizeof (flash_data));
- if (ret < 0)
- printf ("ft_blob_update): cannot set /localbus/ranges "
- "property err:%s\n", fdt_strerror(ret));
- } else {
- /* memory node is required in dts */
- printf ("ft_blob_update(): cannot find /localbus node "
- "err:%s\n", fdt_strerror (nodeoffset));
- }
-
- /* baudrate */
- nodeoffset = fdt_path_offset (blob, "/soc/cpm/serial");
- if (nodeoffset >= 0) {
- speed = cpu_to_be32 (gd->baudrate);
- ret = fdt_setprop (blob, nodeoffset, "current-speed", &speed,
- sizeof (unsigned long));
- if (ret < 0)
- printf ("ft_blob_update): cannot set /soc/cpm/serial/current-speed "
- "property err:%s\n", fdt_strerror (ret));
- } else {
- /* baudrate is required in dts */
- printf ("ft_blob_update(): cannot find /soc/cpm/smc2/current-speed node "
- "err:%s\n", fdt_strerror (nodeoffset));
- }
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup (blob, bd);
- ft_blob_update (blob, bd);
-
- return 0;
-}
-#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
diff --git a/configs/muas3001_defconfig b/configs/muas3001_defconfig
deleted file mode 100644
index e1056bd..0000000
--- a/configs/muas3001_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_MUAS3001=y
diff --git a/configs/muas3001_dev_defconfig b/configs/muas3001_dev_defconfig
deleted file mode 100644
index a62019c..0000000
--- a/configs/muas3001_dev_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="MUAS_DEV_BOARD"
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_MUAS3001=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index f1c2f8b..7f76aae 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+muas3001 powerpc mpc8260 - - Heiko Schocher <hs@denx.de>
PM825 powerpc mpc8260 - - Wolfgang Denk <wd@denx.de>
PM826 powerpc mpc8260 - - Wolfgang Denk <wd@denx.de>
PM828 powerpc mpc8260 - -
diff --git a/include/configs/muas3001.h b/include/configs/muas3001.h
deleted file mode 100644
index df2ecc1..0000000
--- a/include/configs/muas3001.h
+++ /dev/null
@@ -1,391 +0,0 @@
-/*
- * (C) Copyright 2008
- * Heiko Schocher, DENX Software Engineering, hs at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MUAS3001 1
-
-#define CONFIG_SYS_TEXT_BASE 0xFF000000
-
-#define CONFIG_CPM2 1 /* Has a CPM2 */
-
-/* Do boardspecific init */
-#define CONFIG_BOARD_EARLY_INIT_R 1
-
-/* enable Watchdog */
-#define CONFIG_WATCHDOG 1
-
-/*
- * Select serial console configuration
- *
- * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- */
-#define CONFIG_CONS_ON_SMC /* Console is on SMC */
-#undef CONFIG_CONS_ON_SCC /* It's not on SCC */
-#undef CONFIG_CONS_NONE /* It's not on external UART */
-#if defined(CONFIG_MUAS_DEV_BOARD)
-#define CONFIG_CONS_INDEX 2 /* SMC2 is used for console */
-#else
-#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */
-#endif
-
-/*
- * Select ethernet configuration
- *
- * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
- * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
- * SCC, 1-3 for FCC)
- *
- * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
- * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
- * must be unset.
- */
-#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
-#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
-#undef CONFIG_ETHER_NONE /* No external Ethernet */
-
-#define CONFIG_ETHER_INDEX 1
-#define CONFIG_ETHER_ON_FCC1
-#define CONFIG_HAS_ETH0
-#define FCC_ENET
-
-/*
- * - Rx-CLK is CLK11
- * - Tx-CLK is CLK12
- */
-# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12)
-# define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
-/*
- * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
- */
-# define CONFIG_SYS_CPMFCR_RAMTYPE (0)
-/* know on local Bus */
-/* define CONFIG_SYS_CPMFCR_RAMTYPE (CPMFCR_DTB | CPMFCR_BDB) */
-/*
- * - Enable Full Duplex in FSMR
- */
-# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
-
-#define CONFIG_MII /* MII PHY management */
-#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
-# define CONFIG_SYS_PHY_ADDR 1
-/*
- * GPIO pins used for bit-banged MII communications
- */
-#define MDIO_PORT 0 /* Port A */
-#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
- (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
-#define MDC_DECLARE MDIO_DECLARE
-
-
-#define CONFIG_SYS_MDIO_PIN 0x00200000 /* PA10 */
-#define CONFIG_SYS_MDC_PIN 0x00400000 /* PA9 */
-
-#define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN)
-#define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
-#define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0)
-
-#define MDIO(bit) if(bit) iop->pdat |= CONFIG_SYS_MDIO_PIN; \
- else iop->pdat &= ~CONFIG_SYS_MDIO_PIN
-
-#define MDC(bit) if(bit) iop->pdat |= CONFIG_SYS_MDC_PIN; \
- else iop->pdat &= ~CONFIG_SYS_MDC_PIN
-
-#define MIIDELAY udelay(1)
-
-#ifndef CONFIG_8260_CLKIN
-#define CONFIG_8260_CLKIN 66000000 /* in Hz */
-#endif
-
-#define CONFIG_BAUDRATE 115200
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DTT
-#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
-
-/*
- * Default environment settings
- */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "u-boot_addr_r=100000\0" \
- "kernel_addr_r=200000\0" \
- "fdt_addr_r=400000\0" \
- "rootpath=/opt/eldk/ppc_6xx\0" \
- "u-boot=muas3001/u-boot.bin\0" \
- "bootfile=muas3001/uImage\0" \
- "fdt_file=muas3001/muas3001.dtb\0" \
- "ramdisk_file=uRamdisk\0" \
- "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
- "update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; " \
- "cp.b ${u-boot_addr_r} ff000000 ${filesize};" \
- "prot on ff000000 ff03ffff\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "addcons=setenv bootargs ${bootargs} console=ttyCPM0,${baudrate}\0" \
- "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:" \
- "${netmask}:${hostname}:${netdev}:off panic=1\0" \
- "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
- "tftp ${fdt_addr_r} ${fdt_file}; run nfsargs addip addcons;" \
- "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
- "net_self=tftp ${kernel_addr_r} ${bootfile}; " \
- "tftp ${fdt_addr_r} ${fdt_file}; " \
- "tftp ${ramdisk_addr} ${ramdisk_file}; " \
- "run ramargs addip; " \
- "bootm ${kernel_addr_r} ${ramdisk_addr} ${fdt_addr_r}\0" \
- "ramdisk_addr=ff210000\0" \
- "kernel_addr=ff050000\0" \
- "fdt_addr=ff200000\0" \
- "flash_self=run ramargs addip addcons;bootm ${kernel_addr}" \
- " ${ramdisk_addr} ${fdt_addr}\0" \
- "updateramdisk=era ${ramdisk_addr} +1f0000;tftpb ${kernel_addr_r}" \
- " ${ramdisk_file};" \
- "cp.b ${kernel_addr_r} ${ramdisk_addr} ${filesize}\0" \
- "updatekernel=era ${kernel_addr} +1b0000;tftpb ${kernel_addr_r}" \
- " ${bootfile};" \
- "cp.b ${kernel_addr_r} ${kernel_addr} ${filesize}\0" \
- "updatefdt=era ${fdt_addr} +10000;tftpb ${fdt_addr_r} ${fdt_file};" \
- "cp.b ${fdt_addr_r} ${fdt_addr} ${filesize}\0" \
- ""
-
-#define CONFIG_BOOTCOMMAND "run net_nfs"
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFF000000
-#define CONFIG_SYS_FLASH_SIZE 32
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
-
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256KB for Monitor */
-
-#define CONFIG_ENV_IS_IN_FLASH
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE 0x10000
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#endif /* CONFIG_ENV_IS_IN_FLASH */
-
-/*
- * I2C Bus
- */
-#define CONFIG_HARD_I2C 1 /* To enable I2C support */
-#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-/* I2C SYSMON (LM75, AD7414 is almost compatible) */
-#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
-#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
-#define CONFIG_SYS_DTT_MAX_TEMP 70
-#define CONFIG_SYS_DTT_LOW_TEMP -30
-#define CONFIG_SYS_DTT_HYSTERESIS 3
-
-#define CONFIG_SYS_IMMR 0xF0000000
-#define CONFIG_SYS_DEFAULT_IMMR 0x0F010000
-
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/* Hard reset configuration word */
-#define CONFIG_SYS_HRCW_MASTER 0x0E028200 /* BPS=11 CIP=1 ISB=010 BMS=1 */
-
-/* No slaves */
-#define CONFIG_SYS_HRCW_SLAVE1 0
-#define CONFIG_SYS_HRCW_SLAVE2 0
-#define CONFIG_SYS_HRCW_SLAVE3 0
-#define CONFIG_SYS_HRCW_SLAVE4 0
-#define CONFIG_SYS_HRCW_SLAVE5 0
-#define CONFIG_SYS_HRCW_SLAVE6 0
-#define CONFIG_SYS_HRCW_SLAVE7 0
-
-#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-#define CONFIG_SYS_HID0_INIT 0
-#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
-
-#define CONFIG_SYS_HID2 0
-
-#define CONFIG_SYS_SIUMCR 0x00200000
-#define CONFIG_SYS_BCR 0x004c0000
-#define CONFIG_SYS_SCCR 0x0
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 4-35
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
- SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
- SYPCR_SWRI|SYPCR_SWP)
-#endif /* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register 5-5
- *-----------------------------------------------------------------------
- * turn on Checkstop Reset Enable
- */
-#define CONFIG_SYS_RMR 0
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control 4-40
- *-----------------------------------------------------------------------
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- */
-#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration 13-7
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RCCR 0
-
-/*
- * Init Memory Controller:
- *
- * Bank Bus Machine PortSz Device
- * ---- --- ------- ------ ------
- * 0 60x GPCM 32 bit FLASH
- * 1 60x SDRAM 64 bit SDRAM
- * 4 60x GPCM 16 bit I/O Ctrl
- *
- */
-/* Bank 0 - FLASH
- */
-#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
- BRx_PS_32 |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-#define CONFIG_SYS_OR0_PRELIM (0xff000020)
-
-/* Bank 1 - 60x bus SDRAM
- */
-#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (256 << 20) /* less than 256 MB */
-
-#define CONFIG_SYS_MPTPR 0x2800
-
-/*-----------------------------------------------------------------------------
- * Address for Mode Register Set (MRS) command
- *-----------------------------------------------------------------------------
- */
-#define CONFIG_SYS_MRS_OFFS 0x00000110
-#define CONFIG_SYS_PSRT 0x13
-
-#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
- BRx_PS_64 |\
- BRx_MS_SDRAM_P |\
- BRx_V)
-
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1_LITTLE
-
-/* SDRAM initialization values
-*/
-#define CONFIG_SYS_OR1_LITTLE ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
- ORxS_BPD_4 |\
- ORxS_ROWST_PBI1_A7 |\
- ORxS_NUMR_12)
-
-#define CONFIG_SYS_PSDMR_LITTLE 0x004b36a3
-
-#define CONFIG_SYS_OR1_BIG ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
- ORxS_BPD_4 |\
- ORxS_ROWST_PBI1_A4 |\
- ORxS_NUMR_12)
-
-#define CONFIG_SYS_PSDMR_BIG 0x014f36a3
-
-/* IO on CS4 initialization values
-*/
-#define CONFIG_SYS_IO_BASE 0xc0000000
-#define CONFIG_SYS_IO_SIZE 1
-
-#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_IO_BASE & BRx_BA_MSK) |\
- BRx_PS_16 | BRx_MS_GPCM_L | BRx_V)
-
-#define CONFIG_SYS_OR4_PRELIM (0xfff80020)
-
-#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-
-#define OF_TBCLK (bd->bi_busfreq / 4)
-#if defined(CONFIG_MUAS_DEV_BOARD)
-#define OF_STDOUT_PATH "/soc/cpm/serial at 11a90"
-#else
-#define OF_STDOUT_PATH "/soc/cpm/serial at 11a80"
-#endif
-
-#endif /* __CONFIG_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [U-Boot] [PATCH 21/26] mpc8260: remove IPHASE4539 board support
2014-12-15 14:26 [U-Boot] [PATCH 0/26] Start removing non-generic boards Masahiro Yamada
` (19 preceding siblings ...)
2014-12-15 14:26 ` [U-Boot] [PATCH 20/26] mpc8260: remove muas3001 " Masahiro Yamada
@ 2014-12-15 14:26 ` Masahiro Yamada
2015-01-05 18:21 ` Tom Rini
2014-12-15 14:26 ` [U-Boot] [PATCH 22/26] mpc8260: remove gw8260 " Masahiro Yamada
` (6 subsequent siblings)
27 siblings, 1 reply; 55+ messages in thread
From: Masahiro Yamada @ 2014-12-15 14:26 UTC (permalink / raw)
To: u-boot
This board is still a non-generic board.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Grandegger <wg@denx.de>
---
arch/powerpc/cpu/mpc8260/Kconfig | 4 -
board/iphase4539/Kconfig | 9 -
board/iphase4539/MAINTAINERS | 6 -
board/iphase4539/Makefile | 10 -
board/iphase4539/README | 358 -----------------------------
board/iphase4539/flash.c | 474 ---------------------------------------
board/iphase4539/iphase4539.c | 408 ---------------------------------
configs/IPHASE4539_defconfig | 3 -
doc/README.scrapyard | 1 +
include/configs/IPHASE4539.h | 328 ---------------------------
10 files changed, 1 insertion(+), 1600 deletions(-)
delete mode 100644 board/iphase4539/Kconfig
delete mode 100644 board/iphase4539/MAINTAINERS
delete mode 100644 board/iphase4539/Makefile
delete mode 100644 board/iphase4539/README
delete mode 100644 board/iphase4539/flash.c
delete mode 100644 board/iphase4539/iphase4539.c
delete mode 100644 configs/IPHASE4539_defconfig
delete mode 100644 include/configs/IPHASE4539.h
diff --git a/arch/powerpc/cpu/mpc8260/Kconfig b/arch/powerpc/cpu/mpc8260/Kconfig
index 2b3c9c2..56b79ac 100644
--- a/arch/powerpc/cpu/mpc8260/Kconfig
+++ b/arch/powerpc/cpu/mpc8260/Kconfig
@@ -22,9 +22,6 @@ config TARGET_EP82XXM
config TARGET_GW8260
bool "Support gw8260"
-config TARGET_IPHASE4539
- bool "Support IPHASE4539"
-
config TARGET_KM82XX
bool "Support km82xx"
@@ -35,7 +32,6 @@ source "board/cpu86/Kconfig"
source "board/cpu87/Kconfig"
source "board/ep82xxm/Kconfig"
source "board/gw8260/Kconfig"
-source "board/iphase4539/Kconfig"
source "board/keymile/km82xx/Kconfig"
endmenu
diff --git a/board/iphase4539/Kconfig b/board/iphase4539/Kconfig
deleted file mode 100644
index 74594d2..0000000
--- a/board/iphase4539/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_IPHASE4539
-
-config SYS_BOARD
- default "iphase4539"
-
-config SYS_CONFIG_NAME
- default "IPHASE4539"
-
-endif
diff --git a/board/iphase4539/MAINTAINERS b/board/iphase4539/MAINTAINERS
deleted file mode 100644
index ddf6814..0000000
--- a/board/iphase4539/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-IPHASE4539 BOARD
-M: Wolfgang Grandegger <wg@denx.de>
-S: Maintained
-F: board/iphase4539/
-F: include/configs/IPHASE4539.h
-F: configs/IPHASE4539_defconfig
diff --git a/board/iphase4539/Makefile b/board/iphase4539/Makefile
deleted file mode 100644
index 9197b84..0000000
--- a/board/iphase4539/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := iphase4539.o flash.o
diff --git a/board/iphase4539/README b/board/iphase4539/README
deleted file mode 100644
index c5146d9..0000000
--- a/board/iphase4539/README
+++ /dev/null
@@ -1,358 +0,0 @@
-
-This file contains basic information on the port of U-Boot to IPHASE4539
-(Interphase 4539 T1/E1/J1 PMC Communications Controller).
-All the changes fit in the common U-Boot infrastructure, providing a new
-IPHASE4539-specific entry in makefiles. To build U-Boot for IPHASE4539,
-type "make IPHASE4539_config", edit the "include/config_IPHASE4539.h"
-file if necessary, then type "make".
-
-
-Common file modifications:
---------------------------
-
-The following common files have been modified by this project:
-(starting from the ppcboot-1.1.5/ directory)
-
-MAKEALL - IPHASE4539 entry added
-Makefile - IPHASE4539_config entry added
-
-
-New files:
-----------
-
-The following new files have been added by this project:
-(starting from the ppcboot-1.1.5/ directory)
-
-board/iphase4539/ - board-specific directory
-board/iphase4539/Makefile - board-specific makefile
-board/iphase4539/config.mk - config file
-board/iphase4539/flash.c - flash driver (for AM29LV033C)
-board/iphase4539/ppcboot.lds - linker script
-board/iphase4539/iphase4539.c - ioport and memory initialization
-include/config_IPHASE4539.h - main configuration file
-
-
-New configuration options:
---------------------------
-
-CONFIG_IPHASE4539
-
- Main board-specific option (should be defined for IPHASE4539).
-
-
-Acceptance criteria tests:
---------------------------
-
-The following tests have been conducted to validate the port of U-Boot
-to IPHASE4539:
-
-1. Operation on serial console:
-
-With SMC1 defined as console in the main configuration file, the U-Boot
-output appeared on the serial terminal connected to the 2.5mm stereo jack
-connector as follows:
-
-------------------------------------------------------------------------------
-=> help
-base - print or set address offset
-bdinfo - print Board Info structure
-bootm - boot application image from memory
-bootp - boot image via network using BootP/TFTP protocol
-bootd - boot default, i.e., run 'bootcmd'
-cmp - memory compare
-coninfo - print console devices and informations
-cp - memory copy
-crc32 - checksum calculation
-dcache - enable or disable data cache
-echo - echo args to console
-erase - erase FLASH memory
-flinfo - print FLASH memory information
-go - start application at address 'addr'
-help - print online help
-icache - enable or disable instruction cache
-iminfo - print header information for application image
-loadb - load binary file over serial line (kermit mode)
-loads - load S-Record file over serial line
-loop - infinite loop on address range
-md - memory display
-mm - memory modify (auto-incrementing)
-mtest - simple RAM test
-mw - memory write (fill)
-nm - memory modify (constant address)
-printenv- print environment variables
-protect - enable or disable FLASH write protection
-rarpboot- boot image via network using RARP/TFTP protocol
-reset - Perform RESET of the CPU
-run - run commands in an environment variable
-saveenv - save environment variables to persistent storage
-setenv - set environment variables
-sleep - delay execution for some time
-source - run script from memory
-tftpboot- boot image via network using TFTP protocol
- and env variables ipaddr and serverip
-version - print monitor version
-? - alias for 'help'
-=>
-------------------------------------------------------------------------------
-
-
-2. Flash driver operation
-
-The following sequence was performed to test the "flinfo" command:
-
-------------------------------------------------------------------------------
-=> flinfo
-
-Bank # 1: AMD AM29LV033C (32 Mbit, uniform sectors)
- Size: 4 MB in 64 Sectors
- Sector Start Addresses:
- FF800000 (RO) FF810000 (RO) FF820000 FF830000 FF840000
- FF850000 FF860000 FF870000 FF880000 FF890000
- FF8A0000 FF8B0000 FF8C0000 FF8D0000 FF8E0000
- FF8F0000 FF900000 FF910000 FF920000 FF930000
- FF940000 FF950000 FF960000 FF970000 FF980000
- FF990000 FF9A0000 FF9B0000 FF9C0000 FF9D0000
- FF9E0000 FF9F0000 FFA00000 FFA10000 FFA20000
- FFA30000 FFA40000 FFA50000 FFA60000 FFA70000
- FFA80000 FFA90000 FFAA0000 FFAB0000 FFAC0000
- FFAD0000 FFAE0000 FFAF0000 FFB00000 (RO) FFB10000 (RO)
- FFB20000 (RO) FFB30000 (RO) FFB40000 FFB50000 FFB60000
- FFB70000 FFB80000 FFB90000 FFBA0000 FFBB0000
- FFBC0000 FFBD0000 FFBE0000 FFBF0000
-------------------------------------------------------------------------------
-
-Note: the Hardware Configuration Word (HWC) of the 8260 is on the
-first sector of the flash and should not be touched. The U-Boot
-environment variables are stored on second sector and U-Boot
-starts at the address 0xFFB00000.
-
-
-The following sequence was performed to test the erase command:
-
-------------------------------------------------------------------------------
-=> cp 0 ff880000 10
-Copy to Flash... done
-=> md ff880000 20
-ff880000: ff000000 60000000 60000000 7c7f1b78 ....`...`...|..x
-ff880010: 7c9e2378 7cbd2b78 7cdc3378 7cfb3b78 |.#x|.+x|.3x|.;x
-ff880020: 3b000000 4811e0f5 48003719 480036a5 ;...H...H.7.H.6.
-ff880030: 480036f9 48003731 48005c5d 7c7a1b78 H.6.H.71H.\]|z.x
-ff880040: ffffffff ffffffff ffffffff ffffffff ................
-ff880050: ffffffff ffffffff ffffffff ffffffff ................
-ff880060: ffffffff ffffffff ffffffff ffffffff ................
-ff880070: ffffffff ffffffff ffffffff ffffffff ................
-=> erase ff880000 ff88ffff
-Erase Flash from 0xff880000 to 0xff88ffff
-.. done
-Erased 1 sectors
-=> md ff880000
-ff880000: ffffffff ffffffff ffffffff ffffffff ................
-ff880010: ffffffff ffffffff ffffffff ffffffff ................
-ff880020: ffffffff ffffffff ffffffff ffffffff ................
-ff880030: ffffffff ffffffff ffffffff ffffffff ................
-ff880040: ffffffff ffffffff ffffffff ffffffff ................
-ff880050: ffffffff ffffffff ffffffff ffffffff ................
-ff880060: ffffffff ffffffff ffffffff ffffffff ................
-ff880070: ffffffff ffffffff ffffffff ffffffff ................
-=> cp 0 ff880000 10
-Copy to Flash... done
-=> md ff880000 20
-ff880000: ff000000 60000000 60000000 7c7f1b78 ....`...`...|..x
-ff880010: 7c9e2378 7cbd2b78 7cdc3378 7cfb3b78 |.#x|.+x|.3x|.;x
-ff880020: 3b000000 4811e0f5 48003719 480036a5 ;...H...H.7.H.6.
-ff880030: 480036f9 48003731 48005c5d 7c7a1b78 H.6.H.71H.\]|z.x
-ff880040: ffffffff ffffffff ffffffff ffffffff ................
-ff880050: ffffffff ffffffff ffffffff ffffffff ................
-ff880060: ffffffff ffffffff ffffffff ffffffff ................
-ff880070: ffffffff ffffffff ffffffff ffffffff ................
-=> erase 1:8
-Erase Flash Sectors 8-8 in Bank # 1
-.. done
-=> md ff880000 20
-ff880000: ffffffff ffffffff ffffffff ffffffff ................
-ff880010: ffffffff ffffffff ffffffff ffffffff ................
-ff880020: ffffffff ffffffff ffffffff ffffffff ................
-ff880030: ffffffff ffffffff ffffffff ffffffff ................
-ff880040: ffffffff ffffffff ffffffff ffffffff ................
-ff880050: ffffffff ffffffff ffffffff ffffffff ................
-ff880060: ffffffff ffffffff ffffffff ffffffff ................
-ff880070: ffffffff ffffffff ffffffff ffffffff ................
-=> cp 0 ff880000 10
-Copy to Flash... done
-=> cp 0 ff890000 10
-=> md ff880000 20
-ff880000: ff000000 60000000 60000000 7c7f1b78 ....`...`...|..x
-ff880010: 7c9e2378 7cbd2b78 7cdc3378 7cfb3b78 |.#x|.+x|.3x|.;x
-ff880020: 3b000000 4811e0f5 48003719 480036a5 ;...H...H.7.H.6.
-ff880030: 480036f9 48003731 48005c5d 7c7a1b78 H.6.H.71H.\]|z.x
-ff880040: ffffffff ffffffff ffffffff ffffffff ................
-ff880050: ffffffff ffffffff ffffffff ffffffff ................
-ff880060: ffffffff ffffffff ffffffff ffffffff ................
-ff880070: ffffffff ffffffff ffffffff ffffffff ................
-=> md ff890000
-ff890000: ff000000 60000000 60000000 7c7f1b78 ....`...`...|..x
-ff890010: 7c9e2378 7cbd2b78 7cdc3378 7cfb3b78 |.#x|.+x|.3x|.;x
-ff890020: 3b000000 4811e0f5 48003719 480036a5 ;...H...H.7.H.6.
-ff890030: 480036f9 48003731 48005c5d 7c7a1b78 H.6.H.71H.\]|z.x
-ff890040: ffffffff ffffffff ffffffff ffffffff ................
-ff890050: ffffffff ffffffff ffffffff ffffffff ................
-ff890060: ffffffff ffffffff ffffffff ffffffff ................
-ff890070: ffffffff ffffffff ffffffff ffffffff ................
-=> erase 1:8-9
-Erase Flash Sectors 8-9 in Bank # 1
-.... done
-=> md ff880000 20
-ff880000: ffffffff ffffffff ffffffff ffffffff ................
-ff880010: ffffffff ffffffff ffffffff ffffffff ................
-ff880020: ffffffff ffffffff ffffffff ffffffff ................
-ff880030: ffffffff ffffffff ffffffff ffffffff ................
-ff880040: ffffffff ffffffff ffffffff ffffffff ................
-ff880050: ffffffff ffffffff ffffffff ffffffff ................
-ff880060: ffffffff ffffffff ffffffff ffffffff ................
-ff880070: ffffffff ffffffff ffffffff ffffffff ................
-=> md ff890000
-ff890000: ffffffff ffffffff ffffffff ffffffff ................
-ff890010: ffffffff ffffffff ffffffff ffffffff ................
-ff890020: ffffffff ffffffff ffffffff ffffffff ................
-ff890030: ffffffff ffffffff ffffffff ffffffff ................
-ff890040: ffffffff ffffffff ffffffff ffffffff ................
-ff890050: ffffffff ffffffff ffffffff ffffffff ................
-ff890060: ffffffff ffffffff ffffffff ffffffff ................
-ff890070: ffffffff ffffffff ffffffff ffffffff ................
-=>
-------------------------------------------------------------------------------
-
-
-The following sequence was performed to test the Flash programming commands:
-
-------------------------------------------------------------------------------
-=> erase ff880000 ff88ffff
-Erase Flash from 0xff880000 to 0xff88ffff
-.. done
-Erased 1 sectors
-=> cp 0 ff880000 10
-Copy to Flash... done
-=> md 0 20
-00000000: ff000000 60000000 60000000 7c7f1b78 ....`...`...|..x
-00000010: 7c9e2378 7cbd2b78 7cdc3378 7cfb3b78 |.#x|.+x|.3x|.;x
-00000020: 3b000000 4811e0f5 48003719 480036a5 ;...H...H.7.H.6.
-00000030: 480036f9 48003731 48005c5d 7c7a1b78 H.6.H.71H.\]|z.x
-00000040: 3c83c000 2c040000 40823378 7c0000a6 <...,...@.3x|...
-00000050: 60000030 7c1b03a6 3c00c000 600035ec `..0|...<...`.5.
-00000060: 7c1a03a6 4c000064 00000000 00000000 |...L..d........
-00000070: 00000000 00000000 00000000 00000000 ................
-=> md ff880000 20
-ff880000: ff000000 60000000 60000000 7c7f1b78 ....`...`...|..x
-ff880010: 7c9e2378 7cbd2b78 7cdc3378 7cfb3b78 |.#x|.+x|.3x|.;x
-ff880020: 3b000000 4811e0f5 48003719 480036a5 ;...H...H.7.H.6.
-ff880030: 480036f9 48003731 48005c5d 7c7a1b78 H.6.H.71H.\]|z.x
-ff880040: ffffffff ffffffff ffffffff ffffffff ................
-ff880050: ffffffff ffffffff ffffffff ffffffff ................
-ff880060: ffffffff ffffffff ffffffff ffffffff ................
-ff880070: ffffffff ffffffff ffffffff ffffffff ................
-=>
-------------------------------------------------------------------------------
-
-
-The following sequence was performed to test storage of the environment
-variables in Flash:
-
-------------------------------------------------------------------------------
-=> setenv foo bar
-=> saveenv
-Un-Protected 1 sectors
-Erasing Flash...
-.. done
-Erased 1 sectors
-Saving Environment to Flash...
-Protected 1 sectors
-=> reset
-...
-=> printenv
-...
-foo=bar
-...
-Environment size: 339/65532 bytes
-=>
-------------------------------------------------------------------------------
-
-
-The following sequence was performed to test image download and run over
-Ethernet interface (both interfaces were tested):
-
-------------------------------------------------------------------------------
-=> tftpboot 40000 hello_world.bin
-ARP broadcast 1
-TFTP from server 10.0.0.1; our IP address is 10.0.0.8
-Filename 'hello_world.bin'.
-Load address: 0x40000
-Loading: #############
-done
-Bytes transferred = 65932 (1018c hex)
-=> go 40004
-## Starting application at 0x00040004 ...
-Hello World
-argc = 1
-argv[0] = "40004"
-argv[1] = "<NULL>"
-Hit any key to exit ...
-
-## Application terminated, rc = 0x0
-=>
-------------------------------------------------------------------------------
-
-
-3. Known Problems
-
-None for the moment.
-
-
-----------------------------------------------------------------------------
-U-Boot and Linux for Interphase 4539 T1/E1/J1 PMC Communications Controller
-----------------------------------------------------------------------------
-
-U-Boot:
-
- Configure and make U-Boot:
-
- $ cd <path>/u-boot
- $ make IPHASE4539_config
- $ make dep
- $ make
- $ cp -p u-boot.bin /tftpboot
-
- Load u-boot.bin into the Flash memory at 0xffb00000.
-
-
-Linux:
-
- Configure and make Linux:
-
- $ cd <patch>/linux-2.4
- $ make IPHASE4539_config
- $ make oldconfig
- $ make dep
- $ make uImage
- $ cp -p arch/powerpc/mbxboot/uImage /tftpboot
-
- Load uImage via tftp and boot it.
-
-
-Flash organisation:
-
- The following preliminary layout of the Flash memory
- is defined:
-
- 0xff800000 ( 0 - 64 kB): Hardware Configuration Word.
- 0xff810000 ( 64 kB - 128 kB): U-Boot Environment.
- 0xff820000 ( 128 kB - 3 MB): RAMdisk.
- 0xffb00000 ( 3 MB - 3328 kB): U-Boot.
- 0xffb40000 (3328 KB - 4 MB): Linux Kernel.
-
-
-For further information concerning U-Boot and Linux please consult
-the "DENX U-Boot and Linux Guide".
-
-
-(C) 2002 Wolfgang Grandegger, DENX Software Engineering, wg at denx.de
-===================================================================
diff --git a/board/iphase4539/flash.c b/board/iphase4539/flash.c
deleted file mode 100644
index 3c2dad6..0000000
--- a/board/iphase4539/flash.c
+++ /dev/null
@@ -1,474 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * Adapted for Interphase 4539 by Wolfgang Grandegger <wg@denx.de>.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <common.h>
-#include <flash.h>
-#include <asm/io.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-extern int hwc_flash_size(void);
-static ulong flash_get_size (u32 addr, flash_info_t *info);
-static int flash_get_offsets (u32 base, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static void flash_reset (u32 addr);
-
-#define out8(a,v) *(volatile unsigned char*)(a) = v
-#define in8(a) *(volatile unsigned char*)(a)
-#define in32(a) *(volatile unsigned long*)(a)
-#define iobarrier_rw() eieio()
-
-unsigned long flash_init (void)
-{
- unsigned int i;
- unsigned long flash_size = 0;
- unsigned long bank_size;
- unsigned int bank = 0;
-
- /* Init: no FLASHes known */
- for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- flash_info[i].sector_count = 0;
- flash_info[i].size = 0;
- }
-
- /* Initialise the BOOT Flash */
- if (bank == CONFIG_SYS_MAX_FLASH_BANKS) {
- puts ("Warning: not all Flashes are initialised !");
- return flash_size;
- }
-
- bank_size = flash_get_size (CONFIG_SYS_FLASH_BASE, flash_info + bank);
- if (bank_size) {
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE && \
- CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MAX_FLASH_SIZE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
- flash_info + bank);
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
- flash_info + bank);
-#endif
-
- /* HWC protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_FLASH_BASE,
- CONFIG_SYS_FLASH_BASE + 0x10000 - 1,
- flash_info + bank);
-
- flash_size += bank_size;
- bank++;
- } else {
- puts ("Warning: the BOOT Flash is not initialised !");
- }
-
- return flash_size;
-}
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size (u32 addr, flash_info_t *info)
-{
- volatile uchar value;
-#if 0
- int i;
-#endif
-
- /* Write auto select command: read Manufacturer ID */
- out8(addr + 0x0555, 0xAA);
- iobarrier_rw();
- udelay(10);
- out8(addr + 0x02AA, 0x55);
- iobarrier_rw();
- udelay(10);
- out8(addr + 0x0555, 0x90);
- iobarrier_rw();
- udelay(10);
-
- value = in8(addr);
- iobarrier_rw();
- udelay(10);
- switch (value | (value << 16)) {
- case AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
-
- case FUJ_MANUFACT:
- info->flash_id = FLASH_MAN_FUJ;
- break;
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- flash_reset (addr);
- return 0;
- }
-
- value = in8(addr + 1); /* device ID */
- iobarrier_rw();
-
- switch (value) {
- case AMD_ID_LV033C:
- info->flash_id += FLASH_AM033C;
- info->size = hwc_flash_size();
- if (info->size > CONFIG_SYS_MAX_FLASH_SIZE) {
- printf("U-Boot supports only %d MB\n",
- CONFIG_SYS_MAX_FLASH_SIZE);
- info->size = CONFIG_SYS_MAX_FLASH_SIZE;
- }
- info->sector_count = info->size / 0x10000;
- break; /* => 4 MB */
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- flash_reset (addr);
- return (0); /* => no or unknown flash */
-
- }
-
- if (!flash_get_offsets (addr, info)) {
- flash_reset (addr);
- return 0;
- }
-
-#if 0
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- value = in8(info->start[i] + 2);
- iobarrier_rw();
- info->protect[i] = (value & 1) != 0;
- }
-#endif
-
- /*
- * Reset bank to read mode
- */
- flash_reset (addr);
-
- return (info->size);
-}
-
-static int flash_get_offsets (u32 base, flash_info_t *info)
-{
- unsigned int i, size;
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM033C:
- /* set sector offsets for uniform sector type */
- size = info->size / info->sector_count;
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base + i * size;
- }
- break;
- default:
- return 0;
- }
-
- return 1;
-}
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- volatile u32 addr = info->start[0];
- int flag, prot, sect, l_sect;
- ulong start, now, last;
-
- if (s_first < 0 || s_first > s_last) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if (info->flash_id == FLASH_UNKNOWN ||
- info->flash_id > FLASH_AMD_COMP) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- out8(addr + 0x555, 0xAA);
- iobarrier_rw();
- out8(addr + 0x2AA, 0x55);
- iobarrier_rw();
- out8(addr + 0x555, 0x80);
- iobarrier_rw();
- out8(addr + 0x555, 0xAA);
- iobarrier_rw();
- out8(addr + 0x2AA, 0x55);
- iobarrier_rw();
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = info->start[sect];
- out8(addr, 0x30);
- iobarrier_rw();
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer (0);
- last = start;
- addr = info->start[l_sect];
- while ((in8(addr) & 0x80) != 0x80) {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- iobarrier_rw();
- }
-
-DONE:
- /* reset to read mode */
- flash_reset (info->start[0]);
-
- printf (" done\n");
- return 0;
-}
-
-/*
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i=0; i<4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_word(info, wp, data));
-}
-
-/*
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
- volatile u32 addr = info->start[0];
- ulong start;
- int flag, i;
-
- /* Check if Flash is (sufficiently) erased */
- if ((in32(dest) & data) != data) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- /* first, perform an unlock bypass command to speed up flash writes */
- out8(addr + 0x555, 0xAA);
- iobarrier_rw();
- out8(addr + 0x2AA, 0x55);
- iobarrier_rw();
- out8(addr + 0x555, 0x20);
- iobarrier_rw();
-
- /* write each byte out */
- for (i = 0; i < 4; i++) {
- char *data_ch = (char *)&data;
- out8(addr, 0xA0);
- iobarrier_rw();
- out8(dest+i, data_ch[i]);
- iobarrier_rw();
- udelay(10); /* XXX */
- }
-
- /* we're done, now do an unlock bypass reset */
- out8(addr, 0x90);
- iobarrier_rw();
- out8(addr, 0x00);
- iobarrier_rw();
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((in32(dest) & 0x80808080) != (data & 0x80808080)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- iobarrier_rw();
- }
-
- flash_reset (addr);
-
- return (0);
-}
-
-/*
- * Reset bank to read mode
- */
-static void flash_reset (u32 addr)
-{
- out8(addr, 0xF0); /* reset bank */
- iobarrier_rw();
-}
-
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
- case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM033C: printf ("AM29LV033C (32 Mbit, uniform sectors)\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- if (info->size % 0x100000 == 0) {
- printf (" Size: %ld MB in %d Sectors\n",
- info->size / 0x100000, info->sector_count);
- }
- else if (info->size % 0x400 == 0) {
- printf (" Size: %ld KB in %d Sectors\n",
- info->size / 0x400, info->sector_count);
- }
- else {
- printf (" Size: %ld B in %d Sectors\n",
- info->size, info->sector_count);
- }
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
-}
diff --git a/board/iphase4539/iphase4539.c b/board/iphase4539/iphase4539.c
deleted file mode 100644
index d40d2b6..0000000
--- a/board/iphase4539/iphase4539.c
+++ /dev/null
@@ -1,408 +0,0 @@
-/*
- * (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc8260.h>
-#include <asm/io.h>
-#include <asm/immap_8260.h>
-
-int hwc_flash_size (void);
-int hwc_local_sdram_size (void);
-int hwc_main_sdram_size (void);
-int hwc_serial_number (void);
-int hwc_mac_address (char *str);
-int hwc_manufact_date (char *str);
-int seeprom_read (int addr, uchar * data, int size);
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- *
- * The port definitions are taken from the old firmware (see
- * also SYS/H/4539.H):
- *
- * ppar psor pdir podr pdat
- * PA: 0x02ffffff 0x02c00000 0xfc403fe6 0x00000000 0x02403fc0
- * PB: 0x0fffdeb0 0x000000b0 0x0f032347 0x00000000 0x0f000290
- * PC: 0x030ffa55 0x030f0040 0xbcf005ea 0x00000000 0xc0c0ba7d
- * PD: 0x09c04e3c 0x01000e3c 0x0a7ff1c3 0x00000000 0x00ce0ae9
- */
-const iop_conf_t iop_conf_tab[4][32] = {
-
- /* Port A configuration */
- { /* conf ppar psor pdir podr pdat */
- {0, 1, 0, 0, 0, 0}, /* PA31 FCC1_TXENB SLAVE */
- {0, 1, 0, 1, 0, 0}, /* PA30 FCC1_TXCLAV SLAVE */
- {0, 1, 0, 1, 0, 0}, /* PA29 FCC1_TXSOC */
- {0, 1, 0, 0, 0, 0}, /* PA28 FCC1_RXENB SLAVE */
- {0, 1, 0, 0, 0, 0}, /* PA27 FCC1_RXSOC */
- {0, 1, 0, 1, 0, 0}, /* PA26 FCC1_RXCLAV SLAVE */
- {0, 1, 0, 1, 0, 1}, /* PA25 FCC1_TXD0 */
- {0, 1, 0, 1, 0, 1}, /* PA24 FCC1_TXD1 */
- {0, 1, 0, 1, 0, 1}, /* PA23 FCC1_TXD2 */
- {0, 1, 0, 1, 0, 1}, /* PA22 FCC1_TXD3 */
- {0, 1, 0, 1, 0, 1}, /* PA21 FCC1_TXD4 */
- {0, 1, 0, 1, 0, 1}, /* PA20 FCC1_TXD5 */
- {0, 1, 0, 1, 0, 1}, /* PA19 FCC1_TXD6 */
- {0, 1, 0, 1, 0, 1}, /* PA18 FCC1_TXD7 */
- {0, 1, 0, 0, 0, 0}, /* PA17 FCC1_RXD7 */
- {0, 1, 0, 0, 0, 0}, /* PA16 FCC1_RXD6 */
- {0, 1, 0, 0, 0, 0}, /* PA15 FCC1_RXD5 */
- {0, 1, 0, 0, 0, 0}, /* PA14 FCC1_RXD4 */
- {0, 1, 0, 0, 0, 0}, /* PA13 FCC1_RXD3 */
- {0, 1, 0, 0, 0, 0}, /* PA12 FCC1_RXD2 */
- {0, 1, 0, 0, 0, 0}, /* PA11 FCC1_RXD1 */
- {0, 1, 0, 0, 0, 0}, /* PA10 FCC1_RXD0 */
- {0, 1, 1, 1, 0, 1}, /* PA9 TDMA1_L1TXD */
- {0, 1, 1, 0, 0, 0}, /* PA8 TDMA1_L1RXD */
- {0, 0, 0, 0, 0, 0}, /* PA7 CONFIG0 */
- {0, 1, 1, 0, 0, 1}, /* PA6 TDMA1_L1RSYNC */
- {0, 0, 0, 1, 0, 0}, /* PA5 FCC2:RxAddr[2] */
- {0, 0, 0, 1, 0, 0}, /* PA4 FCC2:RxAddr[1] */
- {0, 0, 0, 1, 0, 0}, /* PA3 FCC2:RxAddr[0] */
- {0, 0, 0, 1, 0, 0}, /* PA2 FCC2:TxAddr[0] */
- {0, 0, 0, 1, 0, 0}, /* PA1 FCC2:TxAddr[1] */
- {0, 0, 0, 1, 0, 0} /* PA0 FCC2:TxAddr[2] */
- },
- /* Port B configuration */
- { /* conf ppar psor pdir podr pdat */
- {0, 0, 0, 1, 0, 0}, /* PB31 FCC2_RXSOC */
- {0, 0, 0, 1, 0, 0}, /* PB30 FCC2_TXSOC */
- {0, 0, 0, 1, 0, 0}, /* PB29 FCC2_RXCLAV */
- {0, 0, 0, 0, 0, 0}, /* PB28 CONFIG2 */
- {0, 1, 1, 0, 0, 1}, /* PB27 FCC2_TXD0 */
- {0, 1, 1, 0, 0, 0}, /* PB26 FCC2_TXD1 */
- {0, 0, 0, 1, 0, 0}, /* PB25 FCC2_TXD4 */
- {0, 1, 1, 0, 0, 1}, /* PB24 FCC2_TXD5 */
- {0, 0, 0, 1, 0, 0}, /* PB23 FCC2_TXD6 */
- {0, 1, 0, 1, 0, 1}, /* PB22 FCC2_TXD7 */
- {0, 1, 0, 0, 0, 0}, /* PB21 FCC2_RXD7 */
- {0, 1, 0, 0, 0, 0}, /* PB20 FCC2_RXD6 */
- {0, 1, 0, 0, 0, 0}, /* PB19 FCC2_RXD5 */
- {0, 0, 0, 1, 0, 0}, /* PB18 FCC2_RXD4 */
- {1, 1, 0, 0, 0, 0}, /* PB17 FCC3_RX_DV */
- {1, 1, 0, 0, 0, 0}, /* PB16 FCC3_RX_ER */
- {1, 1, 0, 1, 0, 0}, /* PB15 FCC3_TX_ER */
- {1, 1, 0, 1, 0, 0}, /* PB14 FCC3_TX_EN */
- {1, 1, 0, 0, 0, 0}, /* PB13 FCC3_COL */
- {1, 1, 0, 0, 0, 0}, /* PB12 FCC3_CRS */
- {1, 1, 0, 0, 0, 0}, /* PB11 FCC3_RXD3 */
- {1, 1, 0, 0, 0, 0}, /* PB10 FCC3_RXD2 */
- {1, 1, 0, 0, 0, 0}, /* PB9 FCC3_RXD1 */
- {1, 1, 0, 0, 0, 0}, /* PB8 FCC3_RXD0 */
- {1, 1, 0, 1, 0, 1}, /* PB7 FCC3_TXD0 */
- {1, 1, 0, 1, 0, 1}, /* PB6 FCC3_TXD1 */
- {1, 1, 0, 1, 0, 1}, /* PB5 FCC3_TXD2 */
- {1, 1, 0, 1, 0, 1}, /* PB4 FCC3_TXD3 */
- {0, 0, 0, 0, 0, 0}, /* PB3 */
- {0, 0, 0, 0, 0, 0}, /* PB2 */
- {0, 0, 0, 0, 0, 0}, /* PB1 */
- {0, 0, 0, 0, 0, 0}, /* PB0 */
- },
- /* Port C configuration */
- { /* conf ppar psor pdir podr pdat */
- {0, 1, 0, 0, 0, 1}, /* PC31 CLK1 */
- {0, 0, 0, 1, 0, 0}, /* PC30 U1MASTER_N */
- {0, 1, 0, 0, 0, 1}, /* PC29 CLK3 */
- {0, 0, 0, 1, 0, 1}, /* PC28 -MT90220_RST */
- {0, 1, 0, 0, 0, 1}, /* PC27 CLK5 */
- {0, 0, 0, 1, 0, 1}, /* PC26 -QUADFALC_RST */
- {0, 1, 1, 1, 0, 1}, /* PC25 BRG4 */
- {1, 0, 0, 1, 0, 0}, /* PC24 MDIO */
- {1, 0, 0, 1, 0, 0}, /* PC23 MDC */
- {0, 1, 0, 0, 0, 1}, /* PC22 CLK10 */
- {0, 0, 0, 1, 0, 0}, /* PC21 */
- {0, 1, 0, 0, 0, 1}, /* PC20 CLK12 */
- {0, 1, 0, 0, 0, 1}, /* PC19 CLK13 */
- {1, 1, 0, 0, 0, 1}, /* PC18 CLK14 */
- {0, 1, 0, 0, 0, 0}, /* PC17 CLK15 */
- {1, 1, 0, 0, 0, 1}, /* PC16 CLK16 */
- {0, 1, 1, 0, 0, 0}, /* PC15 FCC1_TXADDR0 SLAVE */
- {0, 1, 1, 0, 0, 0}, /* PC14 FCC1_RXADDR0 SLAVE */
- {0, 1, 1, 0, 0, 0}, /* PC13 FCC1_TXADDR1 SLAVE */
- {0, 1, 1, 0, 0, 0}, /* PC12 FCC1_RXADDR1 SLAVE */
- {0, 0, 0, 1, 0, 0}, /* PC11 FCC2_RXD2 */
- {0, 0, 0, 1, 0, 0}, /* PC10 FCC2_RXD3 */
- {0, 0, 0, 1, 0, 1}, /* PC9 LTMODE */
- {0, 0, 0, 1, 0, 1}, /* PC8 SELSYNC */
- {0, 1, 1, 0, 0, 0}, /* PC7 FCC1_TXADDR2 SLAVE */
- {0, 1, 1, 0, 0, 0}, /* PC6 FCC1_RXADDR2 SLAVE */
- {0, 0, 0, 1, 0, 0}, /* PC5 FCC2_TXCLAV MASTER */
- {0, 0, 0, 1, 0, 0}, /* PC4 FCC2_RXENB MASTER */
- {0, 0, 0, 1, 0, 0}, /* PC3 FCC2_TXD2 */
- {0, 0, 0, 1, 0, 0}, /* PC2 FCC2_TXD3 */
- {0, 0, 0, 0, 0, 1}, /* PC1 PTMC -PTEENB */
- {0, 0, 0, 1, 0, 1}, /* PC0 COMCLK_N */
- },
- /* Port D configuration */
- { /* conf ppar psor pdir podr pdat */
- {0, 0, 0, 1, 0, 1}, /* PD31 -CAM_RST */
- {0, 0, 0, 1, 0, 0}, /* PD30 FCC2_TXENB */
- {0, 1, 1, 0, 0, 0}, /* PD29 FCC1_RXADDR3 SLAVE */
- {0, 1, 1, 0, 0, 1}, /* PD28 TDMC1_L1TXD */
- {0, 1, 1, 0, 0, 0}, /* PD27 TDMC1_L1RXD */
- {0, 1, 1, 0, 0, 1}, /* PD26 TDMC1_L1RSYNC */
- {0, 0, 0, 1, 0, 1}, /* PD25 LED0 -OFF */
- {0, 0, 0, 1, 0, 1}, /* PD24 LED5 -OFF */
- {1, 0, 0, 1, 0, 1}, /* PD23 -LXT971_RST */
- {0, 1, 1, 0, 0, 1}, /* PD22 TDMA2_L1TXD */
- {0, 1, 1, 0, 0, 0}, /* PD21 TDMA2_L1RXD */
- {0, 1, 1, 0, 0, 1}, /* PD20 TDMA2_L1RSYNC */
- {0, 0, 0, 1, 0, 0}, /* PD19 FCC2_TXADDR3 */
- {0, 0, 0, 1, 0, 0}, /* PD18 FCC2_RXADDR3 */
- {0, 1, 0, 1, 0, 0}, /* PD17 BRG2 */
- {0, 0, 0, 1, 0, 0}, /* PD16 */
- {0, 0, 0, 1, 0, 0}, /* PD15 PT2TO1 */
- {0, 0, 0, 1, 0, 1}, /* PD14 PT4TO3 */
- {0, 0, 0, 1, 0, 1}, /* PD13 -SWMODE */
- {0, 0, 0, 1, 0, 1}, /* PD12 -PTMODE */
- {0, 0, 0, 1, 0, 0}, /* PD11 FCC2_RXD0 */
- {0, 0, 0, 1, 0, 0}, /* PD10 FCC2_RXD1 */
- {1, 1, 0, 1, 0, 1}, /* PD9 SMC1_SMTXD */
- {1, 1, 0, 0, 0, 1}, /* PD8 SMC1_SMRXD */
- {0, 1, 1, 0, 0, 0}, /* PD7 FCC1_TXADDR3 SLAVE */
- {0, 0, 0, 1, 0, 0}, /* PD6 IMAMODE */
- {0, 0, 0, 0, 0, 0}, /* PD5 CONFIG2 */
- {0, 1, 0, 1, 0, 0}, /* PD4 BRG8 */
- {0, 0, 0, 0, 0, 0}, /* PD3 */
- {0, 0, 0, 0, 0, 0}, /* PD2 */
- {0, 0, 0, 0, 0, 0}, /* PD1 */
- {0, 0, 0, 0, 0, 0}, /* PD0 */
- }
-};
-
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8260_t *memctl = &immap->im_memctl;
- volatile uchar *base;
- ulong maxsize;
- int i;
-
- memctl->memc_psrt = CONFIG_SYS_PSRT;
- memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-
-#ifndef CONFIG_SYS_RAMBOOT
- immap->im_siu_conf.sc_ppc_acr = 0x00000026;
- immap->im_siu_conf.sc_ppc_alrh = 0x01276345;
- immap->im_siu_conf.sc_ppc_alrl = 0x89ABCDEF;
- immap->im_siu_conf.sc_lcl_acr = 0x00000000;
- immap->im_siu_conf.sc_lcl_alrh = 0x01234567;
- immap->im_siu_conf.sc_lcl_alrl = 0x89ABCDEF;
- immap->im_siu_conf.sc_tescr1 = 0x00004000;
- immap->im_siu_conf.sc_ltescr1 = 0x00004000;
-
- /* Init Main SDRAM */
-#define OP_VALUE 0x404A241A
-#define OP_VALUE_M (OP_VALUE & 0x87FFFFFF);
- base = (uchar *) CONFIG_SYS_SDRAM_BASE;
- memctl->memc_psdmr = 0x28000000 | OP_VALUE_M;
- *base = 0xFF;
- memctl->memc_psdmr = 0x08000000 | OP_VALUE_M;
- for (i = 0; i < 8; i++)
- *base = 0xFF;
- memctl->memc_psdmr = 0x18000000 | OP_VALUE_M;
- *(base + 0x110) = 0xFF;
- memctl->memc_psdmr = OP_VALUE;
- memctl->memc_lsdmr = 0x4086A522;
- *base = 0xFF;
-
- /* We must be able to test a location outsize the maximum legal size
- * to find out THAT we are outside; but this address still has to be
- * mapped by the controller. That means, that the initial mapping has
- * to be (at least) twice as large as the maximum expected size.
- */
- maxsize = (1 + (~memctl->memc_or1 | 0x7fff)) / 2;
-
- maxsize = get_ram_size((long *)base, maxsize);
-
- memctl->memc_or1 |= ~(maxsize - 1);
-
- if (maxsize != hwc_main_sdram_size ())
- printf ("Oops: memory test has not found all memory!\n");
-#endif
-
- icache_enable ();
- /* return total ram size of SDRAM */
- return (maxsize);
-}
-
-int checkboard (void)
-{
- char string[32];
-
- hwc_manufact_date (string);
-
- printf ("Board: Interphase 4539 (#%d %s)\n",
- hwc_serial_number (),
- string);
-
-#ifdef DEBUG
- printf ("Manufacturing date: %s\n", string);
- printf ("Serial number : %d\n", hwc_serial_number ());
- printf ("FLASH size : %d MB\n", hwc_flash_size () >> 20);
- printf ("Main SDRAM size : %d MB\n", hwc_main_sdram_size () >> 20);
- printf ("Local SDRAM size : %d MB\n", hwc_local_sdram_size () >> 20);
- hwc_mac_address (string);
- printf ("MAC address : %s\n", string);
-#endif
-
- return 0;
-}
-
-int misc_init_r (void)
-{
- char *s, str[32];
- int num;
-
- if ((s = getenv ("serial#")) == NULL &&
- (num = hwc_serial_number ()) != -1) {
- sprintf (str, "%06d", num);
- setenv ("serial#", str);
- }
- if ((s = getenv ("ethaddr")) == NULL && hwc_mac_address (str) == 0) {
- setenv ("ethaddr", str);
- }
- return (0);
-}
-
-/***************************************************************
- * We take some basic Hardware Configuration Parameter from the
- * Serial EEPROM conected to the PSpan bridge. We keep it as
- * simple as possible.
- */
-int hwc_flash_size (void)
-{
- uchar byte;
-
- if (!seeprom_read (0x40, &byte, sizeof (byte))) {
- switch ((byte >> 2) & 0x3) {
- case 0x1:
- return 0x0400000;
- break;
- case 0x2:
- return 0x0800000;
- break;
- case 0x3:
- return 0x1000000;
- default:
- return 0x0100000;
- }
- }
- return -1;
-}
-int hwc_local_sdram_size (void)
-{
- uchar byte;
-
- if (!seeprom_read (0x40, &byte, sizeof (byte))) {
- switch ((byte & 0x03)) {
- case 0x1:
- return 0x0800000;
- case 0x2:
- return 0x1000000;
- default:
- return 0; /* not present */
- }
- }
- return -1;
-}
-int hwc_main_sdram_size (void)
-{
- uchar byte;
-
- if (!seeprom_read (0x41, &byte, sizeof (byte))) {
- return 0x1000000 << ((byte >> 5) & 0x7);
- }
- return -1;
-}
-int hwc_serial_number (void)
-{
- int sn = -1;
-
- if (!seeprom_read (0xa0, (uchar *) &sn, sizeof (sn))) {
- sn = cpu_to_le32 (sn);
- }
- return sn;
-}
-int hwc_mac_address (char *str)
-{
- char mac[6];
-
- if (!seeprom_read (0xb0, (uchar *)mac, sizeof (mac))) {
- sprintf (str, "%02x:%02x:%02x:%02x:%02x:%02x\n",
- mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
- } else {
- strcpy (str, "ERROR");
- return -1;
- }
- return 0;
-}
-int hwc_manufact_date (char *str)
-{
- uchar byte;
- int value;
-
- if (seeprom_read (0x92, &byte, sizeof (byte)))
- goto out;
- value = byte;
- if (seeprom_read (0x93, &byte, sizeof (byte)))
- goto out;
- value += byte << 8;
- sprintf (str, "%02d/%02d/%04d",
- value & 0x1F, (value >> 5) & 0xF,
- 1980 + ((value >> 9) & 0x1FF));
- return 0;
-
- out:
- strcpy (str, "ERROR");
- return -1;
-}
-
-#define PSPAN_ADDR 0xF0020000
-#define EEPROM_REG 0x408
-#define EEPROM_READ_CMD 0xA000
-#define PSPAN_WRITE(a,v) \
- *((volatile unsigned long *)(PSPAN_ADDR+(a))) = v; eieio()
-#define PSPAN_READ(a) \
- *((volatile unsigned long *)(PSPAN_ADDR+(a)))
-
-int seeprom_read (int addr, uchar * data, int size)
-{
- ulong val, cmd;
- int i;
-
- for (i = 0; i < size; i++) {
-
- cmd = EEPROM_READ_CMD;
- cmd |= ((addr + i) << 24) & 0xff000000;
-
- /* Wait for ACT to authorize write */
- while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
- eieio ();
-
- /* Write command */
- PSPAN_WRITE (EEPROM_REG, cmd);
-
- /* Wait for data to be valid */
- while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
- eieio ();
- /* Do it twice, first read might be erratic */
- while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
- eieio ();
-
- /* Read error */
- if (val & 0x00000040) {
- return -1;
- } else {
- data[i] = (val >> 16) & 0xff;
- }
- }
- return 0;
-}
diff --git a/configs/IPHASE4539_defconfig b/configs/IPHASE4539_defconfig
deleted file mode 100644
index d49ea52..0000000
--- a/configs/IPHASE4539_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_IPHASE4539=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 7f76aae..af4b00c 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+IPHASE4539 powerpc mpc8260 - - Wolfgang Grandegger <wg@denx.de>
muas3001 powerpc mpc8260 - - Heiko Schocher <hs@denx.de>
PM825 powerpc mpc8260 - - Wolfgang Denk <wd@denx.de>
PM826 powerpc mpc8260 - - Wolfgang Denk <wd@denx.de>
diff --git a/include/configs/IPHASE4539.h b/include/configs/IPHASE4539.h
deleted file mode 100644
index e402075..0000000
--- a/include/configs/IPHASE4539.h
+++ /dev/null
@@ -1,328 +0,0 @@
-/*
- * (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de>
- *
- * This file is based on similar values for other boards found in
- * other U-Boot config files, mainly tqm8260.h and mpc8260ads.h.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Config header file for a Interphase 4539 PMC, 64 MB SDRAM, 4MB Flash.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_IPHASE4539 1 /* ...on a Interphase 4539 PMC */
-
-#define CONFIG_SYS_TEXT_BASE 0xffb00000
-
-#define CONFIG_CPM2 1 /* Has a CPM2 */
-
-/*-----------------------------------------------------------------------
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * if CONFIG_CONS_NONE is defined, then the serial console routines must
- * defined elsewhere (for example, on the cogent platform, there are serial
- * ports on the motherboard which are used for the serial console - see
- * cogent/cma101/serial.[ch]).
- */
-#define CONFIG_CONS_ON_SMC /* define if console on SMC */
-#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
-#undef CONFIG_CONS_NONE /* define if console on something else */
-#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
-
-/*-----------------------------------------------------------------------
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
- */
-#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
-#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
-#undef CONFIG_ETHER_NONE /* define if ether on something else */
-#define CONFIG_ETHER_INDEX 3 /* which channel for ether */
-
-#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
-
-/*-----------------------------------------------------------------------
- * - Rx-CLK is CLK14
- * - Tx-CLK is CLK16
- * - Select bus for bd/buffers (see 28-13)
- * - Half duplex
- */
-# define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
-# define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK14 | CMXFCR_TF3CS_CLK16)
-# define CONFIG_SYS_CPMFCR_RAMTYPE 0
-# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
-
-#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
-
-/* other options */
-
-#define CONFIG_8260_CLKIN 66666666 /* in Hz */
-#define CONFIG_BAUDRATE 19200
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-/*
- * select i2c support configuration
- *
- * Supported configurations are {none, software, hardware} drivers.
- * If the software driver is chosen, there are some additional
- * configuration items that the driver uses to drive the port pins.
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED 400000
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE (iop->pdir |= 0x00010000)
-#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
-#define I2C_READ ((iop->pdat & 0x00010000) != 0)
-#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
- else iop->pdat &= ~0x00010000
-#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
- else iop->pdat &= ~0x00020000
-#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#define CONFIG_BOOTCOMMAND "bootm 100000" /* autoboot command */
-#define CONFIG_BOOTARGS "root=/dev/ram rw"
-
-#if defined(CONFIG_CMD_KGDB)
-#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
-#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
-#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
-#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
-#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
-#endif
-
-#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15 MB in DRAM */
-
-#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passed to Linux in MHz */
- /* for versions < 2.4.5-pre5 */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_RESET_ADDRESS 0x04400000
-
-#define CONFIG_MISC_INIT_R 1 /* We need misc_init_r() */
-
-/*-----------------------------------------------------------------------
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration (Setup by the
- * startup code). Please note that CONFIG_SYS_SDRAM_BASE _must_ start@0.
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFF800000
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max num of sects on one chip */
-#define CONFIG_SYS_MAX_FLASH_SIZE (CONFIG_SYS_MAX_FLASH_SECT * 0x10000) /* 4 MB */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 2400000 /* Flash Erase Timeout (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
-
-/* Environment in FLASH, there is little space left in Serial EEPROM */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x10000) /* 2. sector */
-
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
- *
- * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
- * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
- */
-#define CONFIG_SYS_HRCW_MASTER ( ( HRCW_BPS01 | HRCW_EBM ) |\
- ( HRCW_L2CPC10 | HRCW_ISB110 ) |\
- ( HRCW_MMR11 | HRCW_APPC10 ) |\
- ( HRCW_CS10PC01 | HRCW_MODCK_H0101 ) \
- ) /* 0x14863245 */
-
-/* no slaves */
-#define CONFIG_SYS_HRCW_SLAVE1 0
-#define CONFIG_SYS_HRCW_SLAVE2 0
-#define CONFIG_SYS_HRCW_SLAVE3 0
-#define CONFIG_SYS_HRCW_SLAVE4 0
-#define CONFIG_SYS_HRCW_SLAVE5 0
-#define CONFIG_SYS_HRCW_SLAVE6 0
-#define CONFIG_SYS_HRCW_SLAVE7 0
-
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xFF000000 /* We keep original value */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers 2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control.
- *
- * HID1 has only read-only information - nothing to set.
- */
-#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
- HID0_IFEM|HID0_ABE)
-#define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE)
-#define CONFIG_SYS_HID2 0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register 5-5
- *-----------------------------------------------------------------------
- * turn on Checkstop Reset Enable
- */
-#define CONFIG_SYS_RMR RMR_CSRE
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration 4-25
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_BCR 0xA01C0000
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 4-31
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_SIUMCR 0X4205C000
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 4-35
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
- */
-#if defined (CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
- SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
- SYPCR_SWRI|SYPCR_SWP)
-#endif /* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control 4-40
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control 9-8
- *-----------------------------------------------------------------------
- * Ensure DFBRG is Divide by 16
- */
-#define CONFIG_SYS_SCCR 0
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration 13-7
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RCCR 0
-
-/*-----------------------------------------------------------------------
- * Init Memory Controller:
- *
- * Bank Bus Machine PortSz Device
- * ---- --- ------- ------ ------
- * 0 60x GPCM 64 bit FLASH
- * 1 60x SDRAM 64 bit SDRAM
- */
-
-#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) | 0x0801)
-#define CONFIG_SYS_OR0_PRELIM 0xFF800882
-#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) | 0x0041)
-#define CONFIG_SYS_OR1_PRELIM 0xF8002CD0
-
-#define CONFIG_SYS_PSDMR 0x404A241A
-#define CONFIG_SYS_MPTPR 0x00007400
-#define CONFIG_SYS_PSRT 0x00000007
-
-#endif /* __CONFIG_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [U-Boot] [PATCH 22/26] mpc8260: remove gw8260 board support
2014-12-15 14:26 [U-Boot] [PATCH 0/26] Start removing non-generic boards Masahiro Yamada
` (20 preceding siblings ...)
2014-12-15 14:26 ` [U-Boot] [PATCH 21/26] mpc8260: remove IPHASE4539 " Masahiro Yamada
@ 2014-12-15 14:26 ` Masahiro Yamada
2015-01-05 18:21 ` Tom Rini
2014-12-15 14:26 ` [U-Boot] [PATCH 23/26] mpc8260: remove ep82xxm " Masahiro Yamada
` (5 subsequent siblings)
27 siblings, 1 reply; 55+ messages in thread
From: Masahiro Yamada @ 2014-12-15 14:26 UTC (permalink / raw)
To: u-boot
This board is still a non-generic board.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Oliver Brown <obrown@adventnetworks.com>
---
arch/powerpc/cpu/mpc8260/Kconfig | 4 -
board/gw8260/Kconfig | 9 -
board/gw8260/MAINTAINERS | 6 -
board/gw8260/Makefile | 8 -
board/gw8260/flash.c | 502 ------------------------
board/gw8260/gw8260.c | 639 -------------------------------
configs/gw8260_defconfig | 3 -
doc/README.scrapyard | 1 +
include/configs/gw8260.h | 800 ---------------------------------------
9 files changed, 1 insertion(+), 1971 deletions(-)
delete mode 100644 board/gw8260/Kconfig
delete mode 100644 board/gw8260/MAINTAINERS
delete mode 100644 board/gw8260/Makefile
delete mode 100644 board/gw8260/flash.c
delete mode 100644 board/gw8260/gw8260.c
delete mode 100644 configs/gw8260_defconfig
delete mode 100644 include/configs/gw8260.h
diff --git a/arch/powerpc/cpu/mpc8260/Kconfig b/arch/powerpc/cpu/mpc8260/Kconfig
index 56b79ac..59e2bed 100644
--- a/arch/powerpc/cpu/mpc8260/Kconfig
+++ b/arch/powerpc/cpu/mpc8260/Kconfig
@@ -19,9 +19,6 @@ config TARGET_CPU87
config TARGET_EP82XXM
bool "Support ep82xxm"
-config TARGET_GW8260
- bool "Support gw8260"
-
config TARGET_KM82XX
bool "Support km82xx"
@@ -31,7 +28,6 @@ source "board/atc/Kconfig"
source "board/cpu86/Kconfig"
source "board/cpu87/Kconfig"
source "board/ep82xxm/Kconfig"
-source "board/gw8260/Kconfig"
source "board/keymile/km82xx/Kconfig"
endmenu
diff --git a/board/gw8260/Kconfig b/board/gw8260/Kconfig
deleted file mode 100644
index 1d6aa80..0000000
--- a/board/gw8260/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_GW8260
-
-config SYS_BOARD
- default "gw8260"
-
-config SYS_CONFIG_NAME
- default "gw8260"
-
-endif
diff --git a/board/gw8260/MAINTAINERS b/board/gw8260/MAINTAINERS
deleted file mode 100644
index 5268d19..0000000
--- a/board/gw8260/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-GW8260 BOARD
-M: Oliver Brown <obrown@adventnetworks.com>
-S: Maintained
-F: board/gw8260/
-F: include/configs/gw8260.h
-F: configs/gw8260_defconfig
diff --git a/board/gw8260/Makefile b/board/gw8260/Makefile
deleted file mode 100644
index 2e23f39..0000000
--- a/board/gw8260/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := gw8260.o flash.o
diff --git a/board/gw8260/flash.c b/board/gw8260/flash.c
deleted file mode 100644
index 0c4a943..0000000
--- a/board/gw8260/flash.c
+++ /dev/null
@@ -1,502 +0,0 @@
-/*
- * (C) Copyright 2000
- * Marius Groeger <mgroeger@sysgo.de>
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- *
- * (C) Copyright 2000, 2001
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * (C) Copyright 2001
- * Advent Networks, Inc. <http://www.adventnetworks.com>
- * Oliver Brown <oliverb@alumni.utexas.net>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*********************************************************************/
-/* DESCRIPTION:
- * This file contains the flash routines for the GW8260 board.
- *
- *
- *
- * MODULE DEPENDENCY:
- * None
- *
- *
- * RESTRICTIONS/LIMITATIONS:
- *
- * Only supports the following flash devices:
- * AMD 29F080B
- * AMD 29F016D
- *
- * Copyright (c) 2001, Advent Networks, Inc.
- *
- */
-/*********************************************************************/
-
-#include <common.h>
-#include <mpc8260.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-
-/*********************************************************************/
-/* functions */
-/*********************************************************************/
-
-/*
- * NAME: flash_init() - initializes flash banks
- *
- * DESCRIPTION:
- * This function initializes the flash bank(s).
- *
- * RETURNS:
- * The size in bytes of the flash
- *
- * RESTRICTIONS/LIMITATIONS:
- *
- *
- */
-unsigned long flash_init(void)
-{
- int i;
-
- /* Init: no FLASHes known */
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i)
- flash_info[i].flash_id = FLASH_UNKNOWN;
-
- /* for now, only support the 4 MB Flash SIMM */
- (void)flash_get_size((vu_long *) CONFIG_SYS_FLASH0_BASE,
- &flash_info[0]);
- /*
- * protect monitor and environment sectors
- */
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
- &flash_info[0]);
-#endif
-
-#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
-#ifndef CONFIG_ENV_SIZE
-#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-#endif
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
-#endif
-
- return CONFIG_SYS_FLASH0_SIZE * 1024 * 1024; /*size */
-}
-
-/*********************************************************************/
-/* NAME: flash_print_info() - prints flash imformation */
-/* */
-/* DESCRIPTION: */
-/* This function prints the flash information. */
-/* */
-/* INPUTS: */
-/* flash_info_t *info - flash information structure */
-/* */
-/* OUTPUTS: */
-/* Displays flash information to console */
-/* */
-/* RETURNS: */
-/* None */
-/* */
-/* RESTRICTIONS/LIMITATIONS: */
-/* */
-/* */
-/*********************************************************************/
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch ((info->flash_id >> 16) & 0xff) {
- case 0x1:
- printf ("AMD ");
- break;
- default:
- printf ("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case AMD_ID_F040B:
- printf ("AM29F040B (4 Mbit)\n");
- break;
- case AMD_ID_F080B:
- printf ("AM29F080B (8 Mbit)\n");
- break;
- case AMD_ID_F016D:
- printf ("AM29F016D (16 Mbit)\n");
- break;
- default:
- printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
- return;
-}
-
-/*********************************************************************/
-/* The following code cannot be run from FLASH! */
-/*********************************************************************/
-
-/*********************************************************************/
-/* NAME: flash_get_size() - detects the flash size */
-/* */
-/* DESCRIPTION: */
-/* 1) Reads vendor ID and devices ID from the flash devices. */
-/* 2) Initializes flash info struct. */
-/* 3) Return the flash size */
-/* */
-/* INPUTS: */
-/* vu_long *addr - pointer to start of flash */
-/* flash_info_t *info - flash information structure */
-/* */
-/* OUTPUTS: */
-/* None */
-/* */
-/* RETURNS: */
-/* Size of the flash in bytes, or 0 if device id is unknown. */
-/* */
-/* RESTRICTIONS/LIMITATIONS: */
-/* Only supports the following devices: */
-/* AM29F080D */
-/* AM29F016D */
-/* */
-/*********************************************************************/
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
- short i;
- vu_long vendor, devid;
- ulong base = (ulong)addr;
-
- /*printf("addr = %08lx\n", (unsigned long)addr); */
-
- /* Reset and Write auto select command: read Manufacturer ID */
- addr[0x0000] = 0xf0f0f0f0;
- addr[0x0555] = 0xAAAAAAAA;
- addr[0x02AA] = 0x55555555;
- addr[0x0555] = 0x90909090;
- udelay (1000);
-
- vendor = addr[0];
- /*printf("vendor = %08lx\n", vendor); */
- if (vendor != 0x01010101) {
- info->size = 0;
- goto out;
- }
-
- devid = addr[1];
- /*printf("devid = %08lx\n", devid); */
-
- if ((devid & 0xff) == AMD_ID_F080B) {
- info->flash_id = (vendor & 0xff) << 16 | AMD_ID_F080B;
- /* we have 16 sectors with 64KB each x 4 */
- info->sector_count = 16;
- info->size = 4 * info->sector_count * 64*1024;
- } else if ((devid & 0xff) == AMD_ID_F016D){
- info->flash_id = (vendor & 0xff) << 16 | AMD_ID_F016D;
- /* we have 32 sectors with 64KB each x 4 */
- info->sector_count = 32;
- info->size = 4 * info->sector_count * 64*1024;
- } else {
- info->size = 0;
- goto out;
- }
- /*printf("sector count = %08x\n", info->sector_count); */
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* sector base address */
- info->start[i] = base + i * (info->size / info->sector_count);
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- addr = (volatile unsigned long *)(info->start[i]);
- info->protect[i] = addr[2] & 1;
- }
-
- /* reset command */
- addr = (vu_long *)info->start[0];
-
- out:
- addr[0] = 0xf0f0f0f0;
-
- /*printf("size = %08x\n", info->size); */
- return info->size;
-}
-
-/*********************************************************************/
-/* NAME: flash_erase() - erases flash by sector */
-/* */
-/* DESCRIPTION: */
-/* This function erases flash sectors starting for s_first to */
-/* s_last. */
-/* */
-/* INPUTS: */
-/* flash_info_t *info - flash information structure */
-/* int s_first - first sector to erase */
-/* int s_last - last sector to erase */
-/* */
-/* OUTPUTS: */
-/* None */
-/* */
-/* RETURNS: */
-/* Returns 0 for success, 1 for failure. */
-/* */
-/* RESTRICTIONS/LIMITATIONS: */
-/* */
-/*********************************************************************/
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- vu_long *addr = (vu_long*)(info->start[0]);
- int flag, prot, sect, l_sect;
- ulong start, now, last;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x0555] = 0xAAAAAAAA;
- addr[0x02AA] = 0x55555555;
- addr[0x0555] = 0x80808080;
- addr[0x0555] = 0xAAAAAAAA;
- addr[0x02AA] = 0x55555555;
- udelay (100);
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = (vu_long*)(info->start[sect]);
- addr[0] = 0x30303030;
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer (0);
- last = start;
- addr = (vu_long*)(info->start[l_sect]);
- while ((addr[0] & 0x80808080) != 0x80808080) {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- serial_putc ('.');
- last = now;
- }
- }
-
- DONE:
- /* reset to read mode */
- addr = (volatile unsigned long *)info->start[0];
- addr[0] = 0xF0F0F0F0; /* reset bank */
-
- printf (" done\n");
- return 0;
-}
-
-/*********************************************************************/
-/* NAME: write_buff() - writes a buffer to flash */
-/* */
-/* DESCRIPTION: */
-/* This function copies a buffer, *src, to flash. */
-/* */
-/* INPUTS: */
-/* flash_info_t *info - flash information structure */
-/* uchar *src - pointer to buffer to write to flash */
-/* ulong addr - address to start write at */
-/* ulong cnt - number of bytes to write to flash */
-/* */
-/* OUTPUTS: */
-/* None */
-/* */
-/* RETURNS: */
-/* 0 - OK */
-/* 1 - write timeout */
-/* 2 - Flash not erased */
-/* */
-/* RESTRICTIONS/LIMITATIONS: */
-/* */
-/*********************************************************************/
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i = 0, cp = wp; i < l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; (i < 4) && (cnt > 0); ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; (cnt == 0) && (i < 4); ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i = 0; i < 4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i = 0, cp = wp; (i < 4) && (cnt > 0); ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; (i < 4); ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_word(info, wp, data));
-}
-
-/*********************************************************************/
-/* NAME: write_word() - writes a word to flash */
-/* */
-/* DESCRIPTION: */
-/* This writes a single word to flash. */
-/* */
-/* INPUTS: */
-/* flash_info_t *info - flash information structure */
-/* ulong dest - address to write */
-/* ulong data - data to write */
-/* */
-/* OUTPUTS: */
-/* None */
-/* */
-/* RETURNS: */
-/* 0 - OK */
-/* 1 - write timeout */
-/* 2 - Flash not erased */
-/* */
-/* RESTRICTIONS/LIMITATIONS: */
-/* */
-/*********************************************************************/
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
- vu_long *addr = (vu_long*)(info->start[0]);
- ulong start;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((vu_long *)dest) & data) != data) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x0555] = 0xAAAAAAAA;
- addr[0x02AA] = 0x55555555;
- addr[0x0555] = 0xA0A0A0A0;
-
- *((vu_long *)dest) = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- return (0);
-}
-/*********************************************************************/
-/* End of flash.c */
-/*********************************************************************/
diff --git a/board/gw8260/gw8260.c b/board/gw8260/gw8260.c
deleted file mode 100644
index bbae0a8..0000000
--- a/board/gw8260/gw8260.c
+++ /dev/null
@@ -1,639 +0,0 @@
-/*
- * (C) Copyright 2000
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2001
- * Advent Networks, Inc. <http://www.adventnetworks.com>
- * Jay Monkman <jtm@smoothsmoothie.com>
- *
- * (C) Copyright 2001
- * Advent Networks, Inc. <http://www.adventnetworks.com>
- * Oliver Brown <oliverb@alumni.utexas.net>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*********************************************************************/
-/* DESCRIPTION:
- * This file contains the board routines for the GW8260 board.
- *
- * MODULE DEPENDENCY:
- * None
- *
- * RESTRICTIONS/LIMITATIONS:
- * None
- *
- * Copyright (c) 2001, Advent Networks, Inc.
- */
-/*********************************************************************/
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc8260.h>
-
-/*
- * I/O Port configuration table
- *
- */
-const iop_conf_t iop_conf_tab[4][32] = {
-
- /* Port A configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PA31 */ { 1, 0, 0, 1, 0, 0 }, /* TP14 */
- /* PA30 */ { 1, 1, 1, 1, 0, 0 }, /* US_RTS */
- /* PA29 */ { 1, 0, 0, 1, 0, 1 }, /* LSSI_DATA */
- /* PA28 */ { 1, 0, 0, 1, 0, 1 }, /* LSSI_CLK */
- /* PA27 */ { 1, 0, 0, 1, 0, 0 }, /* TP12 */
- /* PA26 */ { 1, 0, 0, 0, 0, 0 }, /* IO_STATUS */
- /* PA25 */ { 1, 0, 0, 0, 0, 0 }, /* IO_CLOCK */
- /* PA24 */ { 1, 0, 0, 0, 0, 0 }, /* IO_CONFIG */
- /* PA23 */ { 1, 0, 0, 0, 0, 0 }, /* IO_DONE */
- /* PA22 */ { 1, 0, 0, 0, 0, 0 }, /* IO_DATA */
- /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* US_TXD3 */
- /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* US_TXD2 */
- /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* US_TXD1 */
- /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* US_TXD0 */
- /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* DS_RXD0 */
- /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* DS_RXD1 */
- /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* DS_RXD2 */
- /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* DS_RXD3 */
- /* PA13 */ { 1, 0, 0, 1, 0, 0 }, /* SPARE7 */
- /* PA12 */ { 1, 0, 0, 1, 0, 0 }, /* SPARE6 */
- /* PA11 */ { 1, 0, 0, 1, 0, 0 }, /* SPARE5 */
- /* PA10 */ { 1, 0, 0, 1, 0, 0 }, /* SPARE4 */
- /* PA9 */ { 1, 0, 0, 1, 0, 0 }, /* SPARE3 */
- /* PA8 */ { 1, 0, 0, 1, 0, 0 }, /* SPARE2 */
- /* PA7 */ { 1, 0, 0, 0, 0, 0 }, /* LSSI_IN */
- /* PA6 */ { 1, 0, 0, 1, 0, 0 }, /* SPARE0 */
- /* PA5 */ { 1, 0, 0, 1, 0, 0 }, /* DEMOD_RESET_ */
- /* PA4 */ { 1, 0, 0, 1, 0, 0 }, /* MOD_RESET_ */
- /* PA3 */ { 1, 0, 0, 1, 0, 0 }, /* IO_RESET */
- /* PA2 */ { 1, 0, 0, 1, 0, 0 }, /* TX_ENABLE */
- /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* RX_LOCK */
- /* PA0 */ { 1, 0, 0, 1, 0, 1 } /* MPC_RESET_ */
- },
-
- /* Port B configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FETH0_TX_ER */
- /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_RX_DV */
- /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FETH0_TX_EN */
- /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_RX_ER */
- /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_COL */
- /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_CRS */
- /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FETH0_TXD3 */
- /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FETH0_TXD2 */
- /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FETH0_TXD1 */
- /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FETH0_TXD0 */
- /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_RXD0 */
- /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_RXD1 */
- /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_RXD2 */
- /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_RXD3 */
- /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_RX_DV */
- /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_RX_ER */
- /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FETH1_TX_ER */
- /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FETH1_TX_EN */
- /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_COL */
- /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_CRS */
- /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_RXD3 */
- /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_RXD2 */
- /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_RXD1 */
- /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_RXD0 */
- /* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FETH1_TXD0 */
- /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FETH1_TXD1 */
- /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FETH1_TXD2 */
- /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FETH1_TXD3 */
- /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- },
-
- /* Port C */
- { /* conf ppar psor pdir podr pdat */
- /* PC31 */ { 1, 0, 0, 1, 0, 1 }, /* FAST_RESET_ */
- /* PC30 */ { 1, 0, 0, 1, 0, 1 }, /* FAST_PAUSE_ */
- /* PC29 */ { 1, 0, 0, 1, 0, 0 }, /* FAST_SLEW1 */
- /* PC28 */ { 1, 0, 0, 1, 0, 0 }, /* FAST_SLEW0 */
- /* PC27 */ { 1, 0, 0, 1, 0, 0 }, /* TP13 */
- /* PC26 */ { 1, 0, 0, 0, 0, 0 }, /* RXDECDFLG */
- /* PC25 */ { 1, 0, 0, 0, 0, 0 }, /* RXACQFAIL */
- /* PC24 */ { 1, 0, 0, 0, 0, 0 }, /* RXACQFLG */
- /* PC23 */ { 1, 0, 0, 1, 0, 0 }, /* WD_TCL */
- /* PC22 */ { 1, 0, 0, 1, 0, 0 }, /* WD_EN */
- /* PC21 */ { 1, 0, 0, 1, 0, 0 }, /* US_TXCLK */
- /* PC20 */ { 1, 0, 0, 0, 0, 0 }, /* DS_RXCLK */
- /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_RX_CLK */
- /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_TX_CLK */
- /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_RX_CLK */
- /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_TX_CLK */
- /* PC15 */ { 1, 0, 0, 1, 0, 0 }, /* TX_SHUTDOWN_ */
- /* PC14 */ { 1, 0, 0, 0, 0, 0 }, /* RS_232_DTR_ */
- /* PC13 */ { 1, 0, 0, 0, 0, 0 }, /* TXERR */
- /* PC12 */ { 1, 0, 0, 1, 0, 1 }, /* FETH1_MDDIS */
- /* PC11 */ { 1, 0, 0, 1, 0, 1 }, /* FETH0_MDDIS */
- /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* MDC */
- /* PC9 */ { 1, 0, 0, 1, 1, 1 }, /* MDIO */
- /* PC8 */ { 1, 0, 0, 1, 1, 1 }, /* SER_NUM */
- /* PC7 */ { 1, 1, 0, 0, 0, 0 }, /* US_CTS */
- /* PC6 */ { 1, 1, 0, 0, 0, 0 }, /* DS_CD_ */
- /* PC5 */ { 1, 0, 0, 1, 0, 0 }, /* FETH1_PWRDWN */
- /* PC4 */ { 1, 0, 0, 1, 0, 0 }, /* FETH0_PWRDWN */
- /* PC3 */ { 1, 0, 0, 1, 0, 0 }, /* MPULED3 */
- /* PC2 */ { 1, 0, 0, 1, 0, 0 }, /* MPULED2 */
- /* PC1 */ { 1, 0, 0, 1, 0, 0 }, /* MPULED1 */
- /* PC0 */ { 1, 0, 0, 1, 0, 1 }, /* MPULED0 */
- },
-
- /* Port D */
- { /* conf ppar psor pdir podr pdat */
- /* PD31 */ { 1, 0, 0, 0, 0, 0 }, /* not used */
- /* PD30 */ { 1, 0, 0, 0, 0, 0 }, /* not used */
- /* PD29 */ { 1, 0, 0, 0, 0, 0 }, /* not used */
- /* PD28 */ { 1, 0, 0, 0, 0, 0 }, /* not used */
- /* PD27 */ { 1, 0, 0, 0, 0, 0 }, /* not used */
- /* PD26 */ { 1, 0, 0, 0, 0, 0 }, /* not used */
- /* PD25 */ { 1, 0, 0, 0, 0, 0 }, /* not used */
- /* PD24 */ { 1, 0, 0, 0, 0, 0 }, /* not used */
- /* PD23 */ { 1, 0, 0, 0, 0, 0 }, /* not used */
- /* PD22 */ { 1, 0, 0, 0, 0, 0 }, /* not used */
- /* PD21 */ { 1, 0, 0, 0, 0, 0 }, /* not used */
- /* PD20 */ { 1, 0, 0, 0, 0, 0 }, /* not used */
- /* PD19 */ { 1, 1, 1, 0, 0, 0 }, /* not used */
- /* PD18 */ { 1, 1, 1, 0, 0, 0 }, /* not used */
- /* PD17 */ { 1, 1, 1, 0, 0, 0 }, /* not used */
- /* PD16 */ { 1, 1, 1, 0, 0, 0 }, /* not used */
- /* PD15 */ { 1, 1, 1, 0, 1, 1 }, /* SDRAM_SDA */
- /* PD14 */ { 1, 1, 1, 0, 1, 1 }, /* SDRAM_SCL */
- /* PD13 */ { 1, 0, 0, 1, 0, 0 }, /* MPULED7 */
- /* PD12 */ { 1, 0, 0, 1, 0, 0 }, /* MPULED6 */
- /* PD11 */ { 1, 0, 0, 1, 0, 0 }, /* MPULED5 */
- /* PD10 */ { 1, 0, 0, 1, 0, 0 }, /* MPULED4 */
- /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* RS232_TXD */
- /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* RD232_RXD */
- /* PD7 */ { 1, 0, 0, 0, 0, 0 }, /* not used */
- /* PD6 */ { 1, 0, 0, 0, 0, 0 }, /* not used */
- /* PD5 */ { 1, 0, 0, 0, 0, 0 }, /* not used */
- /* PD4 */ { 1, 0, 0, 0, 0, 0 }, /* not used */
- /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- }
-};
-
-/*********************************************************************/
-/* NAME: checkboard() - Displays the board type and serial number */
-/* */
-/* OUTPUTS: */
-/* Displays the board type and serial number */
-/* */
-/* RETURNS: */
-/* Always returns 1 */
-/* */
-/* RESTRICTIONS/LIMITATIONS: */
-/* */
-/* */
-/*********************************************************************/
-int checkboard (void)
-{
- char buf[64];
- int i = getenv_f("serial#", buf, sizeof(buf));
-
- puts ("Board: Advent Networks gw8260\n");
-
- if (i > 0) {
- printf("SN: %s\n", buf);
- }
- return 0;
-}
-
-
-#if defined (CONFIG_SYS_DRAM_TEST)
-/*********************************************************************/
-/* NAME: move64() - moves a double word (64-bit) */
-/* */
-/* DESCRIPTION: */
-/* this function performs a double word move from the data at */
-/* the source pointer to the location at the destination pointer. */
-/* */
-/* INPUTS: */
-/* unsigned long long *src - pointer to data to move */
-/* */
-/* OUTPUTS: */
-/* unsigned long long *dest - pointer to locate to move data */
-/* */
-/* RETURNS: */
-/* None */
-/* */
-/* RESTRICTIONS/LIMITATIONS: */
-/* May cloober fr0. */
-/* */
-/*********************************************************************/
-static void move64 (unsigned long long *src, unsigned long long *dest)
-{
- asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */
- "stfd 0, 0(4)" /* *dest = fpr0 */
- : : : "fr0"); /* Clobbers fr0 */
- return;
-}
-
-
-#if defined (CONFIG_SYS_DRAM_TEST_DATA)
-
-unsigned long long pattern[] = {
- 0xaaaaaaaaaaaaaaaaULL,
- 0xccccccccccccccccULL,
- 0xf0f0f0f0f0f0f0f0ULL,
- 0xff00ff00ff00ff00ULL,
- 0xffff0000ffff0000ULL,
- 0xffffffff00000000ULL,
- 0x00000000ffffffffULL,
- 0x0000ffff0000ffffULL,
- 0x00ff00ff00ff00ffULL,
- 0x0f0f0f0f0f0f0f0fULL,
- 0x3333333333333333ULL,
- 0x5555555555555555ULL,
-};
-
-/*********************************************************************/
-/* NAME: mem_test_data() - test data lines for shorts and opens */
-/* */
-/* DESCRIPTION: */
-/* Tests data lines for shorts and opens by forcing adjacent data */
-/* to opposite states. Because the data lines could be routed in */
-/* an arbitrary manner the must ensure test patterns ensure that */
-/* every case is tested. By using the following series of binary */
-/* patterns every combination of adjacent bits is test regardless */
-/* of routing. */
-/* */
-/* ...101010101010101010101010 */
-/* ...110011001100110011001100 */
-/* ...111100001111000011110000 */
-/* ...111111110000000011111111 */
-/* */
-/* Carrying this out, gives us six hex patterns as follows: */
-/* */
-/* 0xaaaaaaaaaaaaaaaa */
-/* 0xcccccccccccccccc */
-/* 0xf0f0f0f0f0f0f0f0 */
-/* 0xff00ff00ff00ff00 */
-/* 0xffff0000ffff0000 */
-/* 0xffffffff00000000 */
-/* */
-/* The number test patterns will always be given by: */
-/* */
-/* log(base 2)(number data bits) = log2 (64) = 6 */
-/* */
-/* To test for short and opens to other signals on our boards. we */
-/* simply */
-/* test with the 1's complemnt of the paterns as well. */
-/* */
-/* OUTPUTS: */
-/* Displays failing test pattern */
-/* */
-/* RETURNS: */
-/* 0 - Passed test */
-/* 1 - Failed test */
-/* */
-/* RESTRICTIONS/LIMITATIONS: */
-/* Assumes only one one SDRAM bank */
-/* */
-/*********************************************************************/
-int mem_test_data (void)
-{
- unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_SDRAM_BASE;
- unsigned long long temp64 = 0;
- int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
- int i;
- unsigned int hi, lo;
-
- for (i = 0; i < num_patterns; i++) {
- move64 (&(pattern[i]), pmem);
- move64 (pmem, &temp64);
-
- /* hi = (temp64>>32) & 0xffffffff; */
- /* lo = temp64 & 0xffffffff; */
- /* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
-
- hi = (pattern[i] >> 32) & 0xffffffff;
- lo = pattern[i] & 0xffffffff;
- /* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo); */
-
- if (temp64 != pattern[i]) {
- printf ("\n Data Test Failed, pattern 0x%08x%08x",
- hi, lo);
- return 1;
- }
- }
-
- return 0;
-}
-#endif /* CONFIG_SYS_DRAM_TEST_DATA */
-
-#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS)
-/*********************************************************************/
-/* NAME: mem_test_address() - test address lines */
-/* */
-/* DESCRIPTION: */
-/* This function performs a test to verify that each word im */
-/* memory is uniquly addressable. The test sequence is as follows: */
-/* */
-/* 1) write the address of each word to each word. */
-/* 2) verify that each location equals its address */
-/* */
-/* OUTPUTS: */
-/* Displays failing test pattern and address */
-/* */
-/* RETURNS: */
-/* 0 - Passed test */
-/* 1 - Failed test */
-/* */
-/* RESTRICTIONS/LIMITATIONS: */
-/* */
-/* */
-/*********************************************************************/
-int mem_test_address (void)
-{
- volatile unsigned int *pmem =
- (volatile unsigned int *) CONFIG_SYS_SDRAM_BASE;
- const unsigned int size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024) / 4;
- unsigned int i;
-
- /* write address to each location */
- for (i = 0; i < size; i++) {
- pmem[i] = i;
- }
-
- /* verify each loaction */
- for (i = 0; i < size; i++) {
- if (pmem[i] != i) {
- printf ("\n Address Test Failed@0x%x", i);
- return 1;
- }
- }
- return 0;
-}
-#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */
-
-#if defined (CONFIG_SYS_DRAM_TEST_WALK)
-/*********************************************************************/
-/* NAME: mem_march() - memory march */
-/* */
-/* DESCRIPTION: */
-/* Marches up through memory. At each location verifies rmask if */
-/* read = 1. At each location write wmask if write = 1. Displays */
-/* failing address and pattern. */
-/* */
-/* INPUTS: */
-/* volatile unsigned long long * base - start address of test */
-/* unsigned int size - number of dwords(64-bit) to test */
-/* unsigned long long rmask - read verify mask */
-/* unsigned long long wmask - wrtie verify mask */
-/* short read - verifies rmask if read = 1 */
-/* short write - writes wmask if write = 1 */
-/* */
-/* OUTPUTS: */
-/* Displays failing test pattern and address */
-/* */
-/* RETURNS: */
-/* 0 - Passed test */
-/* 1 - Failed test */
-/* */
-/* RESTRICTIONS/LIMITATIONS: */
-/* */
-/* */
-/*********************************************************************/
-int mem_march (volatile unsigned long long *base,
- unsigned int size,
- unsigned long long rmask,
- unsigned long long wmask, short read, short write)
-{
- unsigned int i;
- unsigned long long temp = 0;
- unsigned int hitemp, lotemp, himask, lomask;
-
- for (i = 0; i < size; i++) {
- if (read != 0) {
- /* temp = base[i]; */
- move64 ((unsigned long long *) &(base[i]), &temp);
- if (rmask != temp) {
- hitemp = (temp >> 32) & 0xffffffff;
- lotemp = temp & 0xffffffff;
- himask = (rmask >> 32) & 0xffffffff;
- lomask = rmask & 0xffffffff;
-
- printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp);
- return 1;
- }
- }
- if (write != 0) {
- /* base[i] = wmask; */
- move64 (&wmask, (unsigned long long *) &(base[i]));
- }
- }
- return 0;
-}
-#endif /* CONFIG_SYS_DRAM_TEST_WALK */
-
-/*********************************************************************/
-/* NAME: mem_test_walk() - a simple walking ones test */
-/* */
-/* DESCRIPTION: */
-/* Performs a walking ones through entire physical memory. The */
-/* test uses as series of memory marches, mem_march(), to verify */
-/* and write the test patterns to memory. The test sequence is as */
-/* follows: */
-/* 1) march writing 0000...0001 */
-/* 2) march verifying 0000...0001 , writing 0000...0010 */
-/* 3) repeat step 2 shifting masks left 1 bit each time unitl */
-/* the write mask equals 1000...0000 */
-/* 4) march verifying 1000...0000 */
-/* The test fails if any of the memory marches return a failure. */
-/* */
-/* OUTPUTS: */
-/* Displays which pass on the memory test is executing */
-/* */
-/* RETURNS: */
-/* 0 - Passed test */
-/* 1 - Failed test */
-/* */
-/* RESTRICTIONS/LIMITATIONS: */
-/* */
-/* */
-/*********************************************************************/
-int mem_test_walk (void)
-{
- unsigned long long mask;
- volatile unsigned long long *pmem =
- (volatile unsigned long long *) CONFIG_SYS_SDRAM_BASE;
- const unsigned long size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024) / 8;
-
- unsigned int i;
-
- mask = 0x01;
-
- printf ("Initial Pass");
- mem_march (pmem, size, 0x0, 0x1, 0, 1);
-
- printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
- printf (" ");
- printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
-
- for (i = 0; i < 63; i++) {
- printf ("Pass %2d", i + 2);
- if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) {
- /*printf("mask: 0x%x, pass: %d, ", mask, i); */
- return 1;
- }
- mask = mask << 1;
- printf ("\b\b\b\b\b\b\b");
- }
-
- printf ("Last Pass");
- if (mem_march (pmem, size, 0, mask, 0, 1) != 0) {
- /* printf("mask: 0x%x", mask); */
- return 1;
- }
- printf ("\b\b\b\b\b\b\b\b\b");
- printf (" ");
- printf ("\b\b\b\b\b\b\b\b\b");
-
- return 0;
-}
-
-/*********************************************************************/
-/* NAME: testdram() - calls any enabled memory tests */
-/* */
-/* DESCRIPTION: */
-/* Runs memory tests if the environment test variables are set to */
-/* 'y'. */
-/* */
-/* INPUTS: */
-/* testdramdata - If set to 'y', data test is run. */
-/* testdramaddress - If set to 'y', address test is run. */
-/* testdramwalk - If set to 'y', walking ones test is run */
-/* */
-/* OUTPUTS: */
-/* None */
-/* */
-/* RETURNS: */
-/* 0 - Passed test */
-/* 1 - Failed test */
-/* */
-/* RESTRICTIONS/LIMITATIONS: */
-/* */
-/* */
-/*********************************************************************/
-int testdram (void)
-{
- int rundata, runaddress, runwalk;
-
- rundata = getenv_yesno("testdramdata") == 1;
- runaddress = getenv_yesno("testdramaddress") == 1;
- runwalk = getenv_yesno("testdramwalk") == 1;
-
- if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
- printf ("Testing RAM ... ");
- }
-#ifdef CONFIG_SYS_DRAM_TEST_DATA
- if (rundata == 1) {
- if (mem_test_data () == 1) {
- return 1;
- }
- }
-#endif
-#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
- if (runaddress == 1) {
- if (mem_test_address () == 1) {
- return 1;
- }
- }
-#endif
-#ifdef CONFIG_SYS_DRAM_TEST_WALK
- if (runwalk == 1) {
- if (mem_test_walk () == 1) {
- return 1;
- }
- }
-#endif
- if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
- printf ("passed");
- }
- return 0;
-
-}
-#endif /* CONFIG_SYS_DRAM_TEST */
-
-/*********************************************************************/
-/* NAME: initdram() - initializes SDRAM controller */
-/* */
-/* DESCRIPTION: */
-/* Initializes the MPC8260's SDRAM controller. */
-/* */
-/* INPUTS: */
-/* CONFIG_SYS_IMMR - MPC8260 Internal memory map */
-/* CONFIG_SYS_SDRAM_BASE - Physical start address of SDRAM */
-/* CONFIG_SYS_PSDMR - SDRAM mode register */
-/* CONFIG_SYS_MPTPR - Memory refresh timer prescaler register */
-/* CONFIG_SYS_SDRAM0_SIZE - SDRAM size */
-/* */
-/* RETURNS: */
-/* SDRAM size in bytes */
-/* */
-/* RESTRICTIONS/LIMITATIONS: */
-/* */
-/* */
-/*********************************************************************/
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8260_t *memctl = &immap->im_memctl;
- volatile uchar c = 0, *ramaddr = (uchar *) (CONFIG_SYS_SDRAM_BASE + 0x8);
- ulong psdmr = CONFIG_SYS_PSDMR;
- int i;
-
- /*
- * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
- *
- * "At system reset, initialization software must set up the
- * programmable parameters in the memory controller banks registers
- * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
- * system software should execute the following initialization sequence
- * for each SDRAM device.
- *
- * 1. Issue a PRECHARGE-ALL-BANKS command
- * 2. Issue eight CBR REFRESH commands
- * 3. Issue a MODE-SET command to initialize the mode register
- *
- * The initial commands are executed by setting P/LSDMR[OP] and
- * accessing the SDRAM with a single-byte transaction."
- *
- * The appropriate BRx/ORx registers have already been set when we
- * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
- */
-
- memctl->memc_psrt = CONFIG_SYS_PSRT;
- memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-
- memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
- *ramaddr = c;
-
- memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
- for (i = 0; i < 8; i++) {
- *ramaddr = c;
- }
- memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
- *ramaddr = c;
-
- memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
- *ramaddr = c;
-
- /* return total ram size */
- return (CONFIG_SYS_SDRAM0_SIZE * 1024 * 1024);
-}
-
-/*********************************************************************/
-/* End of gw8260.c */
-/*********************************************************************/
diff --git a/configs/gw8260_defconfig b/configs/gw8260_defconfig
deleted file mode 100644
index a59ec3a..0000000
--- a/configs/gw8260_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_GW8260=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index af4b00c..0c47ebd 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+gw8260 powerpc mpc8260 - - Oliver Brown <obrown@adventnetworks.com>
IPHASE4539 powerpc mpc8260 - - Wolfgang Grandegger <wg@denx.de>
muas3001 powerpc mpc8260 - - Heiko Schocher <hs@denx.de>
PM825 powerpc mpc8260 - - Wolfgang Denk <wd@denx.de>
diff --git a/include/configs/gw8260.h b/include/configs/gw8260.h
deleted file mode 100644
index 262c9e9..0000000
--- a/include/configs/gw8260.h
+++ /dev/null
@@ -1,800 +0,0 @@
-/*
- * (C) Copyright 2000
- * Murray Jensen <Murray.Jensen@cmst.csiro.au>
- *
- * (C) Copyright 2000
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2001
- * Advent Networks, Inc. <http://www.adventnetworks.com>
- * Jay Monkman <jmonkman@adventnetworks.com>
- *
- * (C) Copyright 2001
- * Advent Networks, Inc. <http://www.adventnetworks.com>
- * Oliver Brown <obrown@adventnetworks.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*********************************************************************/
-/* DESCRIPTION:
- * This file contains the board configuartion for the GW8260 board.
- *
- * MODULE DEPENDENCY:
- * None
- *
- * RESTRICTIONS/LIMITATIONS:
- * None
- *
- * Copyright (c) 2001, Advent Networks, Inc.
- */
-/*********************************************************************/
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_SYS_TEXT_BASE 0x40000000
-
-/* Enable debug prints */
-#undef DEBUG_BOOTP_EXT /* Debug received vendor fields */
-
-/* What is the oscillator's (UX2) frequency in Hz? */
-#define CONFIG_8260_CLKIN (66 * 1000 * 1000)
-
-/*-----------------------------------------------------------------------
- * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
- *-----------------------------------------------------------------------
- * What should MODCK_H be? It is dependent on the oscillator
- * frequency, MODCK[1-3], and desired CPM and core frequencies.
- * Here are some example values (all frequencies are in MHz):
- *
- * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8
- * ------- ---------- --- --- ---- ----- ----- -----
- * 0x5 0x5 66 133 133 Open Close Open
- * 0x5 0x6 66 133 166 Open Open Close
- * 0x5 0x7 66 133 200 Open Open Open
- * 0x6 0x0 66 133 233 Close Close Close
- * 0x6 0x1 66 133 266 Close Close Open
- * 0x6 0x2 66 133 300 Close Open Close
- */
-#define CONFIG_SYS_SBC_MODCK_H 0x05
-
-/* Define this if you want to boot from 0x00000100. If you don't define
- * this, you will need to program the bootloader to 0xfff00000, and
- * get the hardware reset config words at 0xfe000000. The simplest
- * way to do that is to program the bootloader at both addresses.
- * It is suggested that you just let U-Boot live at 0x00000000.
- */
-#define CONFIG_SYS_SBC_BOOT_LOW 1
-
-/* What should the base address of the main FLASH be and how big is
- * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE.
- * The main FLASH is whichever is connected to *CS0. U-Boot expects
- * this to be the SIMM.
- */
-#define CONFIG_SYS_FLASH0_BASE 0x40000000
-#define CONFIG_SYS_FLASH0_SIZE 8
-
-/* Define CONFIG_SYS_FLASH_CHECKSUM to enable flash checksum during boot.
- * Note: the 'flashchecksum' environment variable must also be set to 'y'.
- */
-#define CONFIG_SYS_FLASH_CHECKSUM
-
-/* What should be the base address of SDRAM DIMM and how big is
- * it (in Mbytes)?
- */
-#define CONFIG_SYS_SDRAM0_BASE 0x00000000
-#define CONFIG_SYS_SDRAM0_SIZE 64
-
-/*
- * DRAM tests
- * CONFIG_SYS_DRAM_TEST - enables the following tests.
- *
- * CONFIG_SYS_DRAM_TEST_DATA - Enables test for shorted or open data lines
- * Environment variable 'test_dram_data' must be
- * set to 'y'.
- * CONFIG_SYS_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
- * addressable. Environment variable
- * 'test_dram_address' must be set to 'y'.
- * CONFIG_SYS_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
- * This test takes about 6 minutes to test 64 MB.
- * Environment variable 'test_dram_walk' must be
- * set to 'y'.
- */
-#define CONFIG_SYS_DRAM_TEST
-#if defined(CONFIG_SYS_DRAM_TEST)
-#define CONFIG_SYS_DRAM_TEST_DATA
-#define CONFIG_SYS_DRAM_TEST_ADDRESS
-#define CONFIG_SYS_DRAM_TEST_WALK
-#endif /* CONFIG_SYS_DRAM_TEST */
-
-/*
- * GW8260 with 16 MB DIMM:
- *
- * 0x0000 0000 Exception Vector code, 8k
- * :
- * 0x0000 1FFF
- * 0x0000 2000 Free for Application Use
- * :
- * :
- *
- * :
- * :
- * 0x00F5 FF30 Monitor Stack (Growing downward)
- * Monitor Stack Buffer (0x80)
- * 0x00F5 FFB0 Board Info Data
- * 0x00F6 0000 Malloc Arena
- * : CONFIG_ENV_SECT_SIZE, 256k
- * : CONFIG_SYS_MALLOC_LEN, 128k
- * 0x00FC 0000 RAM Copy of Monitor Code
- * : CONFIG_SYS_MONITOR_LEN, 256k
- * 0x00FF FFFF [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1
- */
-
-/*
- * GW8260 with 64 MB DIMM:
- *
- * 0x0000 0000 Exception Vector code, 8k
- * :
- * 0x0000 1FFF
- * 0x0000 2000 Free for Application Use
- * :
- * :
- *
- * :
- * :
- * 0x03F5 FF30 Monitor Stack (Growing downward)
- * Monitor Stack Buffer (0x80)
- * 0x03F5 FFB0 Board Info Data
- * 0x03F6 0000 Malloc Arena
- * : CONFIG_ENV_SECT_SIZE, 256k
- * : CONFIG_SYS_MALLOC_LEN, 128k
- * 0x03FC 0000 RAM Copy of Monitor Code
- * : CONFIG_SYS_MONITOR_LEN, 256k
- * 0x03FF FFFF [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1
- */
-
-
-/*
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * if CONFIG_CONS_NONE is defined, then the serial console routines must
- * defined elsewhere.
- */
-#define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */
-#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
-#undef CONFIG_CONS_NONE /* define if console on neither */
-#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
-
-/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
- */
-
-#undef CONFIG_ETHER_ON_SCC
-#define CONFIG_ETHER_ON_FCC
-#undef CONFIG_ETHER_NONE /* define if ethernet on neither */
-
-#ifdef CONFIG_ETHER_ON_SCC
-#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
-#endif /* CONFIG_ETHER_ON_SCC */
-
-#ifdef CONFIG_ETHER_ON_FCC
-#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
-#define CONFIG_MII /* MII PHY management */
-#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
-/*
- * Port pins used for bit-banged MII communictions (if applicable).
- */
-#define MDIO_PORT 2 /* Port C */
-
-#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
- (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
-#define MDC_DECLARE MDIO_DECLARE
-
-#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
-#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
-#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
-
-#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
- else iop->pdat &= ~0x00400000
-
-#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
- else iop->pdat &= ~0x00200000
-
-#define MIIDELAY udelay(1)
-#endif /* CONFIG_ETHER_ON_FCC */
-
-#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
-
-/*
- * - Rx-CLK is CLK13
- * - Tx-CLK is CLK14
- * - Select bus for bd/buffers (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
-# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
-# define CONFIG_SYS_CPMFCR_RAMTYPE 0
-# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
-
-#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
-
-/*
- * - Rx-CLK is CLK15
- * - Tx-CLK is CLK16
- * - Select bus for bd/buffers (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
-# define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
-# define CONFIG_SYS_CPMFCR_RAMTYPE 0
-# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
-
-#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
-
-/* Define this to reserve an entire FLASH sector (256 KB) for
- * environment variables. Otherwise, the environment will be
- * put in the same sector as U-Boot, and changing variables
- * will erase U-Boot temporarily
- */
-#define CONFIG_ENV_IN_OWN_SECT
-
-/* Define to allow the user to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-/* What should the console's baud rate be? */
-#define CONFIG_BAUDRATE 115200
-
-/* Ethernet MAC address - This is set to all zeros to force an
- * an error if we use BOOTP without setting
- * the MAC address
- */
-#define CONFIG_ETHADDR 00:00:00:00:00:00
-
-/* Set to a positive value to delay for running BOOTCOMMAND */
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-/* Be selective on what keys can delay or stop the autoboot process
- * To stop use: " "
- */
-#define CONFIG_AUTOBOOT_KEYED
-#define CONFIG_AUTOBOOT_PROMPT \
- "Autobooting in %d seconds, press \" \" to stop\n", bootdelay
-#define CONFIG_AUTOBOOT_STOP_STR " "
-#undef CONFIG_AUTOBOOT_DELAY_STR
-#define DEBUG_BOOTKEYS 0
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_DNS
-
-/* undef this to save memory */
-#define CONFIG_SYS_LONGHELP
-
-/* Monitor Command Prompt */
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BEDBUG
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_MII
-
-#undef CONFIG_CMD_KGDB
-
-
-/* Where do the internal registers live? */
-#define CONFIG_SYS_IMMR 0xf0000000
-
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-#ifdef CONFIG_SYS_HUSH_PARSER
-#endif
-
-/* What is the address of IO controller */
-#define CONFIG_SYS_IO_BASE 0xe0000000
-
-/*****************************************************************************
- *
- * You should not have to modify any of the following settings
- *
- *****************************************************************************/
-
-#define CONFIG_GW8260 1 /* on an GW8260 Board */
-#define CONFIG_CPM2 1 /* Has a CPM2 */
-
-/*
- * Miscellaneous configurable options
- */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
-
-#define CONFIG_SYS_MAXARGS 8 /* max number of command args */
-
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-/* Convert clocks to MHZ when passing board info to kernel.
- * This must be defined for eariler 2.4 kernels (~2.4.4).
- */
-#define CONFIG_CLOCKS_IN_MHZ
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-
-/* memtest works from the end of the exception vector table
- * to the end of the DRAM less monitor and malloc area
- */
-#define CONFIG_SYS_MEMTEST_START 0x2000
-
-#define CONFIG_SYS_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */
-
-#define CONFIG_SYS_MEM_END_USAGE ( CONFIG_SYS_MONITOR_LEN \
- + CONFIG_SYS_MALLOC_LEN \
- + CONFIG_ENV_SECT_SIZE \
- + CONFIG_SYS_STACK_USAGE )
-
-#define CONFIG_SYS_MEMTEST_END ( CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 \
- - CONFIG_SYS_MEM_END_USAGE )
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
-#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM0_BASE
-#define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM0_SIZE
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
- */
-#if defined(CONFIG_SYS_SBC_BOOT_LOW)
-# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
-#else
-# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (0)
-#endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */
-
-/* get the HRCW ISB field from CONFIG_SYS_IMMR */
-#define CONFIG_SYS_SBC_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) | \
- ((CONFIG_SYS_IMMR & 0x01000000) >> 7) | \
- ((CONFIG_SYS_IMMR & 0x00100000) >> 4) )
-
-#define CONFIG_SYS_HRCW_MASTER ( HRCW_BPS11 | \
- HRCW_DPPC11 | \
- CONFIG_SYS_SBC_HRCW_IMMR | \
- HRCW_MMR00 | \
- HRCW_LBPC11 | \
- HRCW_APPC10 | \
- HRCW_CS10PC00 | \
- (CONFIG_SYS_SBC_MODCK_H & HRCW_MODCK_H1111) | \
- CONFIG_SYS_SBC_HRCW_BOOT_FLAGS )
-
-/* no slaves */
-#define CONFIG_SYS_HRCW_SLAVE1 0
-#define CONFIG_SYS_HRCW_SLAVE2 0
-#define CONFIG_SYS_HRCW_SLAVE3 0
-#define CONFIG_SYS_HRCW_SLAVE4 0
-#define CONFIG_SYS_HRCW_SLAVE5 0
-#define CONFIG_SYS_HRCW_SLAVE6 0
-#define CONFIG_SYS_HRCW_SLAVE7 0
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent.
- */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH0_BASE
-
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 32 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-
-#ifdef CONFIG_ENV_IN_OWN_SECT
-# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + (256 * 1024))
-# define CONFIG_ENV_SECT_SIZE (256 * 1024)
-#else
-# define CONFIG_ENV_SIZE (16 * 1024)/* Size of Environment Sector */
-# define CONFIG_ENV_ADD ((CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) - CONFIG_ENV_SIZE)
-# define CONFIG_ENV_SECT_SIZE (256 * 1024)/* see README - env sect real size */
-#endif /* CONFIG_ENV_IN_OWN_SECT */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers 2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-#define CONFIG_SYS_HID0_INIT (HID0_ICE |\
- HID0_DCE |\
- HID0_ICFI |\
- HID0_DCI |\
- HID0_IFEM |\
- HID0_ABE)
-
-#define CONFIG_SYS_HID0_FINAL (HID0_ICE |\
- HID0_IFEM |\
- HID0_ABE |\
- HID0_EMCP)
-#define CONFIG_SYS_HID2 0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RMR 0
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration 4-25
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_BCR (BCR_ETM)
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 4-31
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC11 |\
- SIUMCR_L2CPC00 |\
- SIUMCR_APPC10 |\
- SIUMCR_MMR00)
-
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
- */
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC |\
- SYPCR_BMT |\
- SYPCR_PBME |\
- SYPCR_LBME |\
- SYPCR_SWRI |\
- SYPCR_SWP)
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control 4-40
- *-----------------------------------------------------------------------
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- */
-#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC |\
- TMCNTSC_ALR |\
- TMCNTSC_TCF |\
- TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CONFIG_SYS_PISCR (PISCR_PS |\
- PISCR_PTF |\
- PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control 9-8
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_SCCR 0
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration 13-7
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RCCR 0
-
-/*
- * Initialize Memory Controller:
- *
- * Bank Bus Machine PortSz Device
- * ---- --- ------- ------ ------
- * 0 60x GPCM 32 bit FLASH (SIMM - 4MB)
- * 1 60x GPCM 32 bit unused
- * 2 60x SDRAM 64 bit SDRAM (DIMM - 16MB or 64MB)
- * 3 60x SDRAM 64 bit unused
- * 4 Local GPCM 8 bit IO (on board - 64k)
- * 5 60x GPCM 8 bit unused
- * 6 60x GPCM 8 bit unused
- * 7 60x GPCM 8 bit unused
- *
- */
-
-/*-----------------------------------------------------------------------
- * BR0 - Base Register
- * Ref: Section 10.3.1 on page 10-14
- * OR0 - Option Register
- * Ref: Section 10.3.2 on page 10-18
- *-----------------------------------------------------------------------
- */
-
-/* Bank 0,1 - FLASH SIMM
- *
- * This expects the FLASH SIMM to be connected to *CS0
- * It consists of 4 AM29F016D parts.
- *
- * Note: For the 8 MB SIMM, *CS1 is unused.
- */
-
-/* BR0 is configured as follows:
- *
- * - Base address of 0x40000000
- * - 32 bit port size
- * - Data errors checking is disabled
- * - Read and write access
- * - GPCM 60x bus
- * - Access are handled by the memory controller according to MSEL
- * - Not used for atomic operations
- * - No data pipelining is done
- * - Valid
- */
-#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\
- BRx_PS_32 |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-/* OR0 is configured as follows:
- *
- * - 8 MB
- * - *BCTL0 is asserted upon access to the current memory bank
- * - *CW / *WE are negated a quarter of a clock earlier
- * - *CS is output at the same time as the address lines
- * - Uses a clock cycle length of 5
- * - *PSDVAL is generated internally by the memory controller
- * unless *GTA is asserted earlier externally.
- * - Relaxed timing is generated by the GPCM for accesses
- * initiated to this memory region.
- * - One idle clock is inserted between a read access from the
- * current bank and the next access.
- */
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE) |\
- ORxG_CSNT |\
- ORxG_ACS_DIV1 |\
- ORxG_SCY_5_CLK |\
- ORxG_TRLX |\
- ORxG_EHTR)
-
-/*-----------------------------------------------------------------------
- * BR2 - Base Register
- * Ref: Section 10.3.1 on page 10-14
- * OR2 - Option Register
- * Ref: Section 10.3.2 on page 10-16
- *-----------------------------------------------------------------------
- */
-
-/* Bank 2 - SDRAM DIMM
- *
- * 16MB DIMM: P/N
- * 64MB DIMM: P/N 1W-8864X8-4-P1-EST or
- * MT4LSDT864AG-10EB1 (Micron)
- *
- * Note: *CS3 is unused for this DIMM
- */
-
-/* With a 16 MB or 64 MB DIMM, the BR2 is configured as follows:
- *
- * - Base address of 0x00000000
- * - 64 bit port size (60x bus only)
- * - Data errors checking is disabled
- * - Read and write access
- * - SDRAM 60x bus
- * - Access are handled by the memory controller according to MSEL
- * - Not used for atomic operations
- * - No data pipelining is done
- * - Valid
- */
-#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
- BRx_PS_64 |\
- BRx_MS_SDRAM_P |\
- BRx_V)
-
-/* With a 16 MB DIMM, the OR2 is configured as follows:
- *
- * - 16 MB
- * - 2 internal banks per device
- * - Row start address bit is A9 with PSDMR[PBI] = 0
- * - 11 row address lines
- * - Back-to-back page mode
- * - Internal bank interleaving within save device enabled
- */
-#if (CONFIG_SYS_SDRAM0_SIZE == 16)
-#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\
- ORxS_BPD_2 |\
- ORxS_ROWST_PBI0_A9 |\
- ORxS_NUMR_11)
-
-/* With a 16 MB DIMM, the PSDMR is configured as follows:
- *
- * - Page Based Interleaving,
- * - Refresh Enable,
- * - Address Multiplexing where A5 is output on A14 pin
- * (A6 on A15, and so on),
- * - use address pins A16-A18 as bank select,
- * - A9 is output on SDA10 during an ACTIVATE command,
- * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
- * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
- * is 3 clocks,
- * - earliest timing for READ/WRITE command after ACTIVATE command is
- * 2 clocks,
- * - earliest timing for PRECHARGE after last data was read is 1 clock,
- * - earliest timing for PRECHARGE after last data was written is 1 clock,
- * - CAS Latency is 2.
- */
-
-/*-----------------------------------------------------------------------
- * PSDMR - 60x Bus SDRAM Mode Register
- * Ref: Section 10.3.3 on page 10-21
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_PSDMR (PSDMR_RFEN |\
- PSDMR_SDAM_A14_IS_A5 |\
- PSDMR_BSMA_A16_A18 |\
- PSDMR_SDA10_PBI0_A9 |\
- PSDMR_RFRC_7_CLK |\
- PSDMR_PRETOACT_3W |\
- PSDMR_ACTTORW_2W |\
- PSDMR_LDOTOPRE_1C |\
- PSDMR_WRC_1C |\
- PSDMR_CL_2)
-#endif /* (CONFIG_SYS_SDRAM0_SIZE == 16) */
-
-/* With a 64 MB DIMM, the OR2 is configured as follows:
- *
- * - 64 MB
- * - 4 internal banks per device
- * - Row start address bit is A8 with PSDMR[PBI] = 0
- * - 12 row address lines
- * - Back-to-back page mode
- * - Internal bank interleaving within save device enabled
- */
-#if (CONFIG_SYS_SDRAM0_SIZE == 64)
-#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\
- ORxS_BPD_4 |\
- ORxS_ROWST_PBI0_A8 |\
- ORxS_NUMR_12)
-
-/* With a 64 MB DIMM, the PSDMR is configured as follows:
- *
- * - Page Based Interleaving,
- * - Refresh Enable,
- * - Address Multiplexing where A5 is output on A14 pin
- * (A6 on A15, and so on),
- * - use address pins A14-A16 as bank select,
- * - A9 is output on SDA10 during an ACTIVATE command,
- * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
- * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
- * is 3 clocks,
- * - earliest timing for READ/WRITE command after ACTIVATE command is
- * 2 clocks,
- * - earliest timing for PRECHARGE after last data was read is 1 clock,
- * - earliest timing for PRECHARGE after last data was written is 1 clock,
- * - CAS Latency is 2.
- */
-
-/*-----------------------------------------------------------------------
- * PSDMR - 60x Bus SDRAM Mode Register
- * Ref: Section 10.3.3 on page 10-21
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_PSDMR (PSDMR_RFEN |\
- PSDMR_SDAM_A14_IS_A5 |\
- PSDMR_BSMA_A14_A16 |\
- PSDMR_SDA10_PBI0_A9 |\
- PSDMR_RFRC_7_CLK |\
- PSDMR_PRETOACT_3W |\
- PSDMR_ACTTORW_2W |\
- PSDMR_LDOTOPRE_1C |\
- PSDMR_WRC_1C |\
- PSDMR_CL_2)
-#endif /* (CONFIG_SYS_SDRAM0_SIZE == 64) */
-
-#define CONFIG_SYS_PSRT 0x0e
-#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32
-
-
-/*-----------------------------------------------------------------------
- * BR4 - Base Register
- * Ref: Section 10.3.1 on page 10-14
- * OR4 - Option Register
- * Ref: Section 10.3.2 on page 10-18
- *-----------------------------------------------------------------------
- */
-/* Bank 4 - Onboard Memory Mapped IO controller
- *
- * This expects the onboard IO controller to connected to *CS4 and
- * the local bus.
- * - Base address of 0xe0000000
- * - 8 bit port size (local bus only)
- * - Read and write access
- * - GPCM local bus
- * - Not used for atomic operations
- * - No data pipelining is done
- * - Valid
- * - extended hold time
- * - 11 wait states
- */
-
-#ifdef CONFIG_SYS_IO_BASE
-# define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_IO_BASE & BRx_BA_MSK) |\
- BRx_PS_8 |\
- BRx_MS_GPCM_L |\
- BRx_V)
-
-# define CONFIG_SYS_OR4_PRELIM (ORxG_AM_MSK |\
- ORxG_SCY_11_CLK |\
- ORxG_EHTR)
-#endif /* CONFIG_SYS_IO_BASE */
-#endif /* __CONFIG_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [U-Boot] [PATCH 23/26] mpc8260: remove ep82xxm board support
2014-12-15 14:26 [U-Boot] [PATCH 0/26] Start removing non-generic boards Masahiro Yamada
` (21 preceding siblings ...)
2014-12-15 14:26 ` [U-Boot] [PATCH 22/26] mpc8260: remove gw8260 " Masahiro Yamada
@ 2014-12-15 14:26 ` Masahiro Yamada
2015-01-05 18:21 ` Tom Rini
2014-12-15 14:26 ` [U-Boot] [PATCH 24/26] mpc8260: remove CPU86, CPU87 " Masahiro Yamada
` (4 subsequent siblings)
27 siblings, 1 reply; 55+ messages in thread
From: Masahiro Yamada @ 2014-12-15 14:26 UTC (permalink / raw)
To: u-boot
This board is still a non-generic board.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
---
arch/powerpc/cpu/mpc8260/Kconfig | 4 -
board/ep82xxm/Kconfig | 9 -
board/ep82xxm/MAINTAINERS | 6 -
board/ep82xxm/Makefile | 8 -
board/ep82xxm/ep82xxm.c | 274 ----------------------------
configs/ep82xxm_defconfig | 3 -
doc/README.scrapyard | 1 +
include/configs/ep82xxm.h | 383 ---------------------------------------
8 files changed, 1 insertion(+), 687 deletions(-)
delete mode 100644 board/ep82xxm/Kconfig
delete mode 100644 board/ep82xxm/MAINTAINERS
delete mode 100644 board/ep82xxm/Makefile
delete mode 100644 board/ep82xxm/ep82xxm.c
delete mode 100644 configs/ep82xxm_defconfig
delete mode 100644 include/configs/ep82xxm.h
diff --git a/arch/powerpc/cpu/mpc8260/Kconfig b/arch/powerpc/cpu/mpc8260/Kconfig
index 59e2bed..599b021 100644
--- a/arch/powerpc/cpu/mpc8260/Kconfig
+++ b/arch/powerpc/cpu/mpc8260/Kconfig
@@ -16,9 +16,6 @@ config TARGET_CPU86
config TARGET_CPU87
bool "Support CPU87"
-config TARGET_EP82XXM
- bool "Support ep82xxm"
-
config TARGET_KM82XX
bool "Support km82xx"
@@ -27,7 +24,6 @@ endchoice
source "board/atc/Kconfig"
source "board/cpu86/Kconfig"
source "board/cpu87/Kconfig"
-source "board/ep82xxm/Kconfig"
source "board/keymile/km82xx/Kconfig"
endmenu
diff --git a/board/ep82xxm/Kconfig b/board/ep82xxm/Kconfig
deleted file mode 100644
index d842091..0000000
--- a/board/ep82xxm/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_EP82XXM
-
-config SYS_BOARD
- default "ep82xxm"
-
-config SYS_CONFIG_NAME
- default "ep82xxm"
-
-endif
diff --git a/board/ep82xxm/MAINTAINERS b/board/ep82xxm/MAINTAINERS
deleted file mode 100644
index c053df9..0000000
--- a/board/ep82xxm/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-EP82XXM BOARD
-#M: -
-S: Maintained
-F: board/ep82xxm/
-F: include/configs/ep82xxm.h
-F: configs/ep82xxm_defconfig
diff --git a/board/ep82xxm/Makefile b/board/ep82xxm/Makefile
deleted file mode 100644
index f9d3891..0000000
--- a/board/ep82xxm/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := ep82xxm.o
diff --git a/board/ep82xxm/ep82xxm.c b/board/ep82xxm/ep82xxm.c
deleted file mode 100644
index fdde535..0000000
--- a/board/ep82xxm/ep82xxm.c
+++ /dev/null
@@ -1,274 +0,0 @@
-/*
- * Copyright (C) 2006 Embedded Planet, LLC.
- *
- * Support for Embedded Planet EP82xxM boards.
- * Tested on EP82xxM (MPC8270).
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8260.h>
-#include <ioports.h>
-#include <asm/m8260_pci.h>
-#ifdef CONFIG_PCI
-#include <pci.h>
-#endif
-#include <miiphy.h>
-#include <linux/compiler.h>
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-#define CONFIG_SYS_FCC2 1
-#define CONFIG_SYS_FCC3 1
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
- /* Port A */
- { /* conf ppar psor pdir podr pdat */
- /* PA31 */ { 0, 0, 0, 0, 0, 1 }, /* PA31 */
- /* PA30 */ { 0, 0, 0, 0, 0, 1 }, /* PA30 */
- /* PA29 */ { 0, 0, 0, 0, 0, 1 }, /* PA29 */
- /* PA28 */ { 0, 0, 0, 0, 0, 1 }, /* PA28 */
- /* PA27 */ { 0, 0, 0, 0, 0, 1 }, /* PA27 */
- /* PA26 */ { 0, 0, 0, 0, 0, 1 }, /* PA26 */
- /* PA25 */ { 0, 0, 0, 0, 0, 1 }, /* PA25 */
- /* PA24 */ { 0, 0, 0, 0, 0, 1 }, /* PA24 */
- /* PA23 */ { 0, 0, 0, 0, 0, 1 }, /* PA23 */
- /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */
- /* PA21 */ { 0, 0, 0, 0, 0, 1 }, /* PA21 */
- /* PA20 */ { 0, 0, 0, 0, 0, 1 }, /* PA20 */
- /* PA19 */ { 0, 0, 0, 0, 0, 1 }, /* PA19 */
- /* PA18 */ { 0, 0, 0, 0, 0, 1 }, /* PA18 */
- /* PA17 */ { 0, 0, 0, 0, 0, 1 }, /* PA17 */
- /* PA16 */ { 0, 0, 0, 0, 0, 1 }, /* PA16 */
- /* PA15 */ { 0, 0, 0, 0, 0, 1 }, /* PA15 */
- /* PA14 */ { 0, 0, 0, 0, 0, 1 }, /* PA14 */
- /* PA13 */ { 0, 0, 0, 0, 0, 1 }, /* PA13 */
- /* PA12 */ { 0, 0, 0, 0, 0, 1 }, /* PA12 */
- /* PA11 */ { 0, 0, 0, 0, 0, 1 }, /* PA11 */
- /* PA10 */ { 0, 0, 0, 0, 0, 1 }, /* PA10 */
- /* PA9 */ { 1, 1, 0, 1, 0, 1 }, /* SMC2 TxD */
- /* PA8 */ { 1, 1, 0, 0, 0, 1 }, /* SMC2 RxD */
- /* PA7 */ { 0, 0, 0, 0, 0, 1 }, /* PA7 */
- /* PA6 */ { 0, 0, 0, 0, 0, 1 }, /* PA6 */
- /* PA5 */ { 0, 0, 0, 0, 0, 1 }, /* PA5 */
- /* PA4 */ { 0, 0, 0, 0, 0, 1 }, /* PA4 */
- /* PA3 */ { 0, 0, 0, 0, 0, 1 }, /* PA3 */
- /* PA2 */ { 0, 0, 0, 0, 0, 1 }, /* PA2 */
- /* PA1 */ { 0, 0, 0, 0, 0, 1 }, /* PA1 */
- /* PA0 */ { 0, 0, 0, 0, 0, 1 } /* PA0 */
- },
-
- /* Port B */
- { /* conf ppar psor pdir podr pdat */
- /* PB31 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
- /* PB30 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
- /* PB29 */ { CONFIG_SYS_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
- /* PB28 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
- /* PB27 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
- /* PB26 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
- /* PB25 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
- /* PB24 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
- /* PB23 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
- /* PB22 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
- /* PB21 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
- /* PB20 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
- /* PB19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
- /* PB18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
- /* PB17 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
- /* PB16 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
- /* PB15 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
- /* PB14 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
- /* PB13 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:COL */
- /* PB12 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
- /* PB11 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB10 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB9 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB8 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
- /* PB6 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB5 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB4 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
- },
-
- /* Port C */
- { /* conf ppar psor pdir podr pdat */
- /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
- /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
- /* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 CTS# */
- /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
- /* PC27 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3: TXD[0] */
- /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
- /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
- /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
- /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
- /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* PC22 */
- /* PC21 */ { 0, 0, 0, 0, 0, 0 }, /* PC21 */
- /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
- /* PC19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* RxClk (CLK13) */
- /* PC18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* TxClk (CLK14) */
- /* PC17 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* RxClk (CLK15) */
- /* PC16 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* TxClk (CLK16) */
- /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
- /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 CD# */
- /* PC13 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 CTS# */
- /* PC12 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 CD# */
- /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
- /* PC10 */ { 1, 1, 0, 0, 0, 0 }, /* SCC3 CD# */
- /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* PC9 */
- /* PC8 */ { 1, 1, 1, 0, 0, 0 }, /* SCC3 CTS# */
- /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
- /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
- /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
- /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
- /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
- /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
- /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
- /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */
- },
-
- /* Port D */
- { /* conf ppar psor pdir podr pdat */
- /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RXD */
- /* PD30 */ { 1, 1, 1, 1, 0, 1 }, /* SCC1 TXD */
- /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 RTS# */
- /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */
- /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TXD */
- /* PD26 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 RTS# */
- /* PD25 */ { 1, 1, 0, 0, 0, 0 }, /* SCC3 RXD */
- /* PD24 */ { 1, 1, 0, 1, 0, 0 }, /* SCC3 TXD */
- /* PD23 */ { 1, 1, 0, 1, 0, 0 }, /* SCC3 RTS# */
- /* PD22 */ { 0, 0, 0, 0, 0, 1 }, /* PD22 */
- /* PD21 */ { 0, 0, 0, 0, 0, 1 }, /* PD21 */
- /* PD20 */ { 0, 0, 0, 0, 0, 1 }, /* PD20 */
- /* PD19 */ { 0, 0, 0, 0, 0, 1 }, /* PD19 */
- /* PD18 */ { 0, 0, 0, 0, 0, 1 }, /* PD18 */
- /* PD17 */ { 0, 0, 0, 0, 0, 1 }, /* PD17 */
- /* PD16 */ { 0, 0, 0, 0, 0, 1 }, /* PD16 */
- /* PD15 */ { 1, 1, 1, 0, 1, 1 }, /* I2C SDA */
- /* PD14 */ { 1, 1, 1, 0, 1, 1 }, /* I2C SCL */
- /* PD13 */ { 0, 0, 0, 0, 0, 1 }, /* PD13 */
- /* PD12 */ { 0, 0, 0, 0, 0, 1 }, /* PD12 */
- /* PD11 */ { 0, 0, 0, 0, 0, 1 }, /* PD11 */
- /* PD10 */ { 0, 0, 0, 0, 0, 1 }, /* PD10 */
- /* PD9 */ { 1, 1, 0, 1, 0, 1 }, /* SMC1 TxD */
- /* PD8 */ { 1, 1, 0, 0, 0, 1 }, /* SMC1 RxD */
- /* PD7 */ { 1, 1, 0, 0, 0, 1 }, /* SMC1 SMSYN */
- /* PD6 */ { 0, 0, 0, 0, 0, 1 }, /* PD6 */
- /* PD5 */ { 0, 0, 0, 0, 0, 1 }, /* PD5 */
- /* PD4 */ { 0, 0, 0, 0, 0, 1 }, /* PD4 */
- /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
- }
-};
-
-#ifdef CONFIG_PCI
-typedef struct pci_ic_s {
- unsigned long pci_int_stat;
- unsigned long pci_int_mask;
-}pci_ic_t;
-#endif
-
-int board_early_init_f (void)
-{
- vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
-
- bcsr[4] |= 0x30; /* Turn the LEDs off */
-
-#if defined(CONFIG_CONS_ON_SMC) || defined(CONFIG_KGDB_ON_SMC)
- bcsr[6] |= 0x10;
-#endif
-#if defined(CONFIG_CONS_ON_SCC) || defined(CONFIG_KGDB_ON_SCC)
- bcsr[7] |= 0x10;
-#endif
-
-#if CONFIG_SYS_FCC3
- bcsr[8] |= 0xC0;
-#endif /* CONFIG_SYS_FCC3 */
-#if CONFIG_SYS_FCC2
- bcsr[8] |= 0x30;
-#endif /* CONFIG_SYS_FCC2 */
-
- return 0;
-}
-
-phys_size_t initdram(int board_type)
-{
- /* Size in MB of SDRAM populated on board*/
- long int msize = 256;
-
-#ifndef CONFIG_SYS_RAMBOOT
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8260_t *memctl = &immap->im_memctl;
- uint psdmr = CONFIG_SYS_PSDMR;
- int i;
-
- unsigned char *ramptr1 = (unsigned char *)0x00000110;
- __maybe_unused unsigned char ramtmp;
-
- memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-
-udelay(400);
-
- /* Initialise 60x bus SDRAM */
- memctl->memc_psrt = CONFIG_SYS_PSRT;
- memctl->memc_or1 = CONFIG_SYS_SDRAM_OR;
- memctl->memc_br1 = CONFIG_SYS_SDRAM_BR;
- memctl->memc_psdmr = psdmr;
-
-udelay(400);
-
- memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */
- ramtmp = *ramptr1;
- memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */
- for (i = 0; i < 8; i++) {
- memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */
- }
- ramtmp = *ramptr1;
- memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; /* Mode Register write */
- *ramptr1 = 0xFF;
- memctl->memc_psdmr = psdmr | PSDMR_RFEN; /* Refresh enable */
-#endif /* !CONFIG_SYS_RAMBOOT */
-
- /* Return total 60x bus SDRAM size */
- return msize * 1024 * 1024;
-}
-
-int checkboard(void)
-{
- vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
-
- puts("Board: ");
- switch (bcsr[0]) {
- case 0x0A:
- printf("EP82xxM 1.0 CPLD revision %d\n", bcsr[1]);
- break;
- default:
- printf("unknown: ID=%02X\n", bcsr[0]);
- }
-
- return 0;
-}
-
-#ifdef CONFIG_PCI
-struct pci_controller hose;
-
-extern void pci_mpc8250_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
- pci_mpc8250_init(&hose);
-}
-#endif
diff --git a/configs/ep82xxm_defconfig b/configs/ep82xxm_defconfig
deleted file mode 100644
index 0842d2d..0000000
--- a/configs/ep82xxm_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_EP82XXM=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 0c47ebd..400eea1 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+ep82xxm powerpc mpc8260 - -
gw8260 powerpc mpc8260 - - Oliver Brown <obrown@adventnetworks.com>
IPHASE4539 powerpc mpc8260 - - Wolfgang Grandegger <wg@denx.de>
muas3001 powerpc mpc8260 - - Heiko Schocher <hs@denx.de>
diff --git a/include/configs/ep82xxm.h b/include/configs/ep82xxm.h
deleted file mode 100644
index cf31f0f..0000000
--- a/include/configs/ep82xxm.h
+++ /dev/null
@@ -1,383 +0,0 @@
-/*
- * Copyright (C) 2006 Embedded Planet, LLC.
- *
- * U-Boot configuration for Embedded Planet EP82xxM boards.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CPU_ID_STR "MPC8270"
-
-#define CONFIG_EP82XXM /* Embedded Planet EP82xxM H 1.0 board */
- /* 256MB SDRAM / 64MB FLASH */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFF00000
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-
-/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
-#define CONFIG_ENV_OVERWRITE
-
-/*
- * Select serial console configuration
- *
- * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- */
-#define CONFIG_CONS_ON_SMC /* Console is on SMC */
-#undef CONFIG_CONS_ON_SCC /* It's not on SCC */
-#undef CONFIG_CONS_NONE /* It's not on external UART */
-#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */
-
-#define CONFIG_SYS_BCSR 0xFA000000
-
-/*
- * Select ethernet configuration
- *
- * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
- * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
- * SCC, 1-3 for FCC)
- *
- * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
- * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
- * must be unset.
- */
-#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
-#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
-#undef CONFIG_ETHER_NONE /* No external Ethernet */
-
-
-#define CONFIG_ETHER_ON_FCC2
-#define CONFIG_ETHER_ON_FCC3
-
-#define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
-#define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK16)
-#define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
-#define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
-
-#define CONFIG_SYS_CPMFCR_RAMTYPE 0
-#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
-
-#define CONFIG_MII /* MII PHY management */
-#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */
-
-/*
- * GPIO pins used for bit-banged MII communications
- */
-#define MDIO_PORT 0 /* Not used - implemented in BCSR */
-
-#define MDIO_ACTIVE (*(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFB)
-#define MDIO_TRISTATE (*(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x04)
-#define MDIO_READ (*(vu_char *)(CONFIG_SYS_BCSR + 8) & 1)
-
-#define MDIO(bit) if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x01; \
- else *(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFE
-
-#define MDC(bit) if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x02; \
- else *(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFD
-
-#define MIIDELAY udelay(1)
-
-
-#ifndef CONFIG_8260_CLKIN
-#define CONFIG_8260_CLKIN 66000000 /* in Hz */
-#endif
-
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_SYS_VXWORKS_MAC_PTR 0x4300 /* Pass Ethernet MAC to VxWorks */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DTT
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_DIAG
-
-
-#define CONFIG_ETHADDR 00:10:EC:00:88:65
-#define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR 00:10:EC:80:88:65
-#define CONFIG_IPADDR 10.0.0.245
-#define CONFIG_HOSTNAME EP82xxM
-#define CONFIG_SERVERIP 10.0.0.26
-#define CONFIG_GATEWAYIP 10.0.0.1
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#define CONFIG_ENV_IN_OWN_SECT 1
-#define CONFIG_AUTO_COMPLETE 1
-#define CONFIG_EXTRA_ENV_SETTINGS "ethprime=FCC3"
-
-#if defined(CONFIG_CMD_KGDB)
-#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
-#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
-#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
-#define CONFIG_KGDB_INDEX 1 /* which serial channel for kgdb */
-#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
-#endif
-
-#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
-#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "ep82xxm=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-/*
- * Define here the location of the environment variables (FLASH or EEPROM).
- * Note: DENX encourages to use redundant environment in FLASH.
- */
-#if 1
-#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
-#else
-#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
-#endif
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_BASE 0xFC000000
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector in flinfo */
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE 0x20000
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#endif /* CONFIG_ENV_IS_IN_FLASH */
-
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-/* EEPROM Configuration */
-#define CONFIG_SYS_EEPROM_SIZE 0x1000
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-#ifdef CONFIG_ENV_IS_IN_EEPROM
-#define CONFIG_ENV_SIZE 0x200 /* Size of Environment vars */
-#define CONFIG_ENV_OFFSET 0x0
-#endif /* CONFIG_ENV_IS_IN_EEPROM */
-
-/* RTC Configuration */
-#define CONFIG_RTC_M41T11 1 /* uses a M41T81 */
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-#define CONFIG_M41T11_BASE_YEAR 1900
-
-/* I2C SYSMON (LM75) */
-#define CONFIG_DTT_LM75 1
-#define CONFIG_DTT_SENSORS {0}
-#define CONFIG_SYS_DTT_MAX_TEMP 70
-#define CONFIG_SYS_DTT_LOW_TEMP -30
-#define CONFIG_SYS_DTT_HYSTERESIS 3
-
-/*-----------------------------------------------------------------------
- * NVRAM Configuration
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_NVRAM_BASE_ADDR 0xFA080000
-#define CONFIG_SYS_NVRAM_SIZE (128*1024)-16
-
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-/* General PCI */
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_PCI_BOOTDELAY 0
-
-/* PCI Memory map (if different from default map */
-#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE /* Local base */
-#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
-#define CONFIG_SYS_PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \
- PICMR_PREFETCH_EN)
-
-/*
- * These are the windows that allow the CPU to access PCI address space.
- * All three PCI master windows, which allow the CPU to access PCI
- * prefetch, non prefetch, and IO space (see below), must all fit within
- * these windows.
- */
-
-/*
- * Master window that allows the CPU to access PCI Memory (prefetch).
- * This window will be setup with the second set of Outbound ATU registers
- * in the bridge.
- */
-
-#define CONFIG_SYS_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
-#define CONFIG_SYS_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
-#define CONFIG_SYS_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
-#define CONFIG_SYS_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */
-#define CONFIG_SYS_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
-
-/*
- * Master window that allows the CPU to access PCI Memory (non-prefetch).
- * This window will be setup with the second set of Outbound ATU registers
- * in the bridge.
- */
-
-#define CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */
-#define CONFIG_SYS_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */
-#define CONFIG_SYS_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
-#define CONFIG_SYS_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */
-#define CONFIG_SYS_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE)
-
-/*
- * Master window that allows the CPU to access PCI IO space.
- * This window will be setup with the first set of Outbound ATU registers
- * in the bridge.
- */
-
-#define CONFIG_SYS_PCI_MSTR_IO_LOCAL 0xF6000000 /* Local base */
-#define CONFIG_SYS_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */
-#define CONFIG_SYS_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
-#define CONFIG_SYS_PCI_MSTR_IO_SIZE 0x02000000 /* 64MB */
-#define CONFIG_SYS_POCMR2_MASK_ATTRIB (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO)
-
-
-/* PCIBR0 - for PCI IO*/
-#define CONFIG_SYS_PCI_MSTR0_LOCAL CONFIG_SYS_PCI_MSTR_IO_LOCAL /* Local base */
-#define CONFIG_SYS_PCIMSK0_MASK ~(CONFIG_SYS_PCI_MSTR_IO_SIZE - 1U) /* Size of window */
-/* PCIBR1 - prefetch and non-prefetch regions joined together */
-#define CONFIG_SYS_PCI_MSTR1_LOCAL CONFIG_SYS_PCI_MSTR_MEM_LOCAL
-#define CONFIG_SYS_PCIMSK1_MASK ~(CONFIG_SYS_PCI_MSTR_MEM_SIZE + CONFIG_SYS_PCI_MSTR_MEMIO_SIZE - 1U)
-
-
-#define CONFIG_SYS_DIRECT_FLASH_TFTP
-
-#if defined(CONFIG_CMD_JFFS2)
-#define CONFIG_SYS_JFFS2_FIRST_BANK 0
-#define CONFIG_SYS_JFFS2_NUM_BANKS CONFIG_SYS_MAX_FLASH_BANKS
-#define CONFIG_SYS_JFFS2_FIRST_SECTOR 0
-#define CONFIG_SYS_JFFS2_LAST_SECTOR 62
-#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
-#define CONFIG_SYS_JFFS_CUSTOM_PART
-#endif
-
-#if defined(CONFIG_CMD_I2C)
-#define CONFIG_HARD_I2C 1 /* To enable I2C support */
-#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */
-#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */
-#endif
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 256KB for Monitor */
-
-#define CONFIG_SYS_DEFAULT_IMMR 0x00010000
-#define CONFIG_SYS_IMMR 0xF0000000
-
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-
-/* Hard reset configuration word */
-#define CONFIG_SYS_HRCW_MASTER 0 /*0x1C800641*/ /* Not used - provided by CPLD */
-/* No slaves */
-#define CONFIG_SYS_HRCW_SLAVE1 0
-#define CONFIG_SYS_HRCW_SLAVE2 0
-#define CONFIG_SYS_HRCW_SLAVE3 0
-#define CONFIG_SYS_HRCW_SLAVE4 0
-#define CONFIG_SYS_HRCW_SLAVE5 0
-#define CONFIG_SYS_HRCW_SLAVE6 0
-#define CONFIG_SYS_HRCW_SLAVE7 0
-
-#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-#define CONFIG_SYS_HID0_INIT 0
-#define CONFIG_SYS_HID0_FINAL 0
-
-#define CONFIG_SYS_HID2 0
-
-#define CONFIG_SYS_SIUMCR 0x02610000
-#define CONFIG_SYS_SYPCR 0xFFFF0689
-#define CONFIG_SYS_BCR 0x8080E000
-#define CONFIG_SYS_SCCR 0x00000001
-
-#define CONFIG_SYS_RMR 0
-#define CONFIG_SYS_TMCNTSC 0x000000C3
-#define CONFIG_SYS_PISCR 0x00000083
-#define CONFIG_SYS_RCCR 0
-
-#define CONFIG_SYS_MPTPR 0x0A00
-#define CONFIG_SYS_PSDMR 0xC432246E
-#define CONFIG_SYS_PSRT 0x32
-
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BR (CONFIG_SYS_SDRAM_BASE | 0x00000041)
-#define CONFIG_SYS_SDRAM_OR 0xF0002900
-
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x00001801)
-#define CONFIG_SYS_OR0_PRELIM 0xFC000882
-#define CONFIG_SYS_BR4_PRELIM (CONFIG_SYS_BCSR | 0x00001001)
-#define CONFIG_SYS_OR4_PRELIM 0xFFF00050
-
-#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
-
-#endif /* __CONFIG_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [U-Boot] [PATCH 24/26] mpc8260: remove CPU86, CPU87 board support
2014-12-15 14:26 [U-Boot] [PATCH 0/26] Start removing non-generic boards Masahiro Yamada
` (22 preceding siblings ...)
2014-12-15 14:26 ` [U-Boot] [PATCH 23/26] mpc8260: remove ep82xxm " Masahiro Yamada
@ 2014-12-15 14:26 ` Masahiro Yamada
2015-01-05 18:22 ` Tom Rini
2014-12-15 14:26 ` [U-Boot] [PATCH 25/26] mpc8260: remove atc " Masahiro Yamada
` (3 subsequent siblings)
27 siblings, 1 reply; 55+ messages in thread
From: Masahiro Yamada @ 2014-12-15 14:26 UTC (permalink / raw)
To: u-boot
These boards are still non-generic boards.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
---
arch/powerpc/cpu/mpc8260/Kconfig | 8 -
board/cpu86/Kconfig | 9 -
board/cpu86/MAINTAINERS | 7 -
board/cpu86/Makefile | 8 -
board/cpu86/cpu86.c | 304 ------------------
board/cpu86/cpu86.h | 27 --
board/cpu86/flash.c | 599 ----------------------------------
board/cpu87/Kconfig | 9 -
board/cpu87/MAINTAINERS | 7 -
board/cpu87/Makefile | 8 -
board/cpu87/cpu87.c | 330 -------------------
board/cpu87/cpu87.h | 27 --
board/cpu87/flash.c | 608 -----------------------------------
configs/CPU86_ROMBOOT_defconfig | 4 -
configs/CPU86_defconfig | 3 -
configs/CPU87_ROMBOOT_defconfig | 4 -
configs/CPU87_defconfig | 3 -
doc/README.scrapyard | 2 +
include/configs/CPU86.h | 629 ------------------------------------
include/configs/CPU87.h | 676 ---------------------------------------
20 files changed, 2 insertions(+), 3270 deletions(-)
delete mode 100644 board/cpu86/Kconfig
delete mode 100644 board/cpu86/MAINTAINERS
delete mode 100644 board/cpu86/Makefile
delete mode 100644 board/cpu86/cpu86.c
delete mode 100644 board/cpu86/cpu86.h
delete mode 100644 board/cpu86/flash.c
delete mode 100644 board/cpu87/Kconfig
delete mode 100644 board/cpu87/MAINTAINERS
delete mode 100644 board/cpu87/Makefile
delete mode 100644 board/cpu87/cpu87.c
delete mode 100644 board/cpu87/cpu87.h
delete mode 100644 board/cpu87/flash.c
delete mode 100644 configs/CPU86_ROMBOOT_defconfig
delete mode 100644 configs/CPU86_defconfig
delete mode 100644 configs/CPU87_ROMBOOT_defconfig
delete mode 100644 configs/CPU87_defconfig
delete mode 100644 include/configs/CPU86.h
delete mode 100644 include/configs/CPU87.h
diff --git a/arch/powerpc/cpu/mpc8260/Kconfig b/arch/powerpc/cpu/mpc8260/Kconfig
index 599b021..eab4514 100644
--- a/arch/powerpc/cpu/mpc8260/Kconfig
+++ b/arch/powerpc/cpu/mpc8260/Kconfig
@@ -10,20 +10,12 @@ choice
config TARGET_ATC
bool "Support atc"
-config TARGET_CPU86
- bool "Support CPU86"
-
-config TARGET_CPU87
- bool "Support CPU87"
-
config TARGET_KM82XX
bool "Support km82xx"
endchoice
source "board/atc/Kconfig"
-source "board/cpu86/Kconfig"
-source "board/cpu87/Kconfig"
source "board/keymile/km82xx/Kconfig"
endmenu
diff --git a/board/cpu86/Kconfig b/board/cpu86/Kconfig
deleted file mode 100644
index ac3ae98..0000000
--- a/board/cpu86/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_CPU86
-
-config SYS_BOARD
- default "cpu86"
-
-config SYS_CONFIG_NAME
- default "CPU86"
-
-endif
diff --git a/board/cpu86/MAINTAINERS b/board/cpu86/MAINTAINERS
deleted file mode 100644
index 06bdd0d..0000000
--- a/board/cpu86/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-CPU86 BOARD
-M: Wolfgang Denk <wd@denx.de>
-S: Maintained
-F: board/cpu86/
-F: include/configs/CPU86.h
-F: configs/CPU86_defconfig
-F: configs/CPU86_ROMBOOT_defconfig
diff --git a/board/cpu86/Makefile b/board/cpu86/Makefile
deleted file mode 100644
index da83afd..0000000
--- a/board/cpu86/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = cpu86.o flash.o
diff --git a/board/cpu86/cpu86.c b/board/cpu86/cpu86.c
deleted file mode 100644
index 9292910..0000000
--- a/board/cpu86/cpu86.c
+++ /dev/null
@@ -1,304 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc8260.h>
-#include "cpu86.h"
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
- /* Port A configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
- /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
- /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
- /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
- /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
- /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
- /* PA25 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII MDIO */
- /* PA24 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII MDC */
- /* PA23 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII MDIO */
- /* PA22 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII MDC */
- /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
- /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
- /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
- /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
- /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
- /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */
- /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
- /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
- /* PA13 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII TXSL1 */
- /* PA12 */ { 1, 0, 0, 1, 0, 1 }, /* FCC2 MII TXSL0 */
- /* PA11 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII TXSL1 */
- /* PA10 */ { 1, 0, 0, 1, 0, 1 }, /* FCC1 MII TXSL0 */
- /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
- /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
- /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */
- /* PA6 */ { 1, 0, 0, 1, 0, 1 }, /* FCC2 MII PAUSE */
- /* PA5 */ { 1, 0, 0, 1, 0, 1 }, /* FCC1 MII PAUSE */
- /* PA4 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII PWRDN */
- /* PA3 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII PWRDN */
- /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */
- /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FCC2 MII MDINT */
- /* PA0 */ { 1, 0, 0, 1, 0, 0 } /* FCC1 MII MDINT */
- },
-
- /* Port B configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
- /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
- /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
- /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
- /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
- /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
- /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
- /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
- /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
- /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
- /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
- /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
- /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
- /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
- /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */
- /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */
- /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */
- /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */
- /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */
- /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */
- /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */
- /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */
- /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */
- /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */
- /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
- /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */
- /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */
- /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */
- /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* PB3 */
- /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* PB2 */
- /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* PB1 */
- /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* PB0 */
- },
-
- /* Port C */
- { /* conf ppar psor pdir podr pdat */
- /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
- /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
- /* PC29 */ { 1, 0, 0, 0, 0, 0 }, /* SCC1 CTS */
- /* PC28 */ { 1, 0, 0, 0, 0, 0 }, /* SCC2 CTS */
- /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
- /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
- /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
- /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
- /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DACFD */
- /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DNFD */
- /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */
- /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII TX_CLK */
- /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */
- /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */
- /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
- /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */
- /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
- /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
- /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
- /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
- /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
- /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
- /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FC9 */
- /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */
- /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
- /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
- /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
- /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
- /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
- /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
- /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
- /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DRQFD */
- },
-
- /* Port D */
- { /* conf ppar psor pdir podr pdat */
- /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RXD */
- /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TXD */
- /* PD29 */ { 1, 0, 0, 1, 0, 0 }, /* SCC1 RTS */
- /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */
- /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TXD */
- /* PD26 */ { 1, 0, 0, 1, 0, 0 }, /* SCC2 RTS */
- /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */
- /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */
- /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */
- /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */
- /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */
- /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */
- /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */
- /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */
- /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */
- /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */
-#if defined(CONFIG_SYS_I2C_SOFT)
- /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */
- /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */
-#else
-#if defined(CONFIG_HARD_I2C)
- /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
- /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
-#else /* normal I/O port pins */
- /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
- /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
-#endif
-#endif
- /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
- /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
- /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
- /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
- /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
- /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
- /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */
- /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */
- /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */
- /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */
- /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* PD3 */
- /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* PD2 */
- /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* PD1 */
- /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* PD0 */
- }
-};
-
-/* ------------------------------------------------------------------------- */
-
-/* Check Board Identity:
- */
-int checkboard (void)
-{
- printf ("Board: CPU86 (Rev %02x)\n", CPU86_REV);
- return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
- *
- * This routine performs standard 8260 initialization sequence
- * and calculates the available memory size. It may be called
- * several times to try different SDRAM configurations on both
- * 60x and local buses.
- */
-static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
- ulong orx, volatile uchar * base)
-{
- volatile uchar c = 0xff;
- volatile uint *sdmr_ptr;
- volatile uint *orx_ptr;
- ulong maxsize, size;
- int i;
-
- /* We must be able to test a location outsize the maximum legal size
- * to find out THAT we are outside; but this address still has to be
- * mapped by the controller. That means, that the initial mapping has
- * to be (at least) twice as large as the maximum expected size.
- */
- maxsize = (1 + (~orx | 0x7fff)) / 2;
-
- /* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that
- * we are configuring CS1 if base != 0
- */
- sdmr_ptr = &memctl->memc_psdmr;
- orx_ptr = &memctl->memc_or2;
-
- *orx_ptr = orx;
-
- /*
- * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
- *
- * "At system reset, initialization software must set up the
- * programmable parameters in the memory controller banks registers
- * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
- * system software should execute the following initialization sequence
- * for each SDRAM device.
- *
- * 1. Issue a PRECHARGE-ALL-BANKS command
- * 2. Issue eight CBR REFRESH commands
- * 3. Issue a MODE-SET command to initialize the mode register
- *
- * The initial commands are executed by setting P/LSDMR[OP] and
- * accessing the SDRAM with a single-byte transaction."
- *
- * The appropriate BRx/ORx registers have already been set when we
- * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
- */
-
- *sdmr_ptr = sdmr | PSDMR_OP_PREA;
- *base = c;
-
- *sdmr_ptr = sdmr | PSDMR_OP_CBRR;
- for (i = 0; i < 8; i++)
- *base = c;
-
- *sdmr_ptr = sdmr | PSDMR_OP_MRW;
- *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */
-
- *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
- *base = c;
-
- size = get_ram_size((long *)base, maxsize);
-
- *orx_ptr = orx | ~(size - 1);
-
- return (size);
-}
-
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8260_t *memctl = &immap->im_memctl;
-
-#ifndef CONFIG_SYS_RAMBOOT
- ulong size8, size9;
-#endif
- long psize;
-
- psize = 32 * 1024 * 1024;
-
- memctl->memc_mptpr = CONFIG_SYS_MPTPR;
- memctl->memc_psrt = CONFIG_SYS_PSRT;
-
-#ifndef CONFIG_SYS_RAMBOOT
- /* 60x SDRAM setup:
- */
- size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
- (uchar *) CONFIG_SYS_SDRAM_BASE);
- size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL,
- (uchar *) CONFIG_SYS_SDRAM_BASE);
-
- if (size8 < size9) {
- psize = size9;
- printf ("(60x:9COL) ");
- } else {
- psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
- (uchar *) CONFIG_SYS_SDRAM_BASE);
- printf ("(60x:8COL) ");
- }
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
- icache_enable ();
-
- return (psize);
-}
-
-#if defined(CONFIG_CMD_DOC)
-void doc_init (void)
-{
- doc_probe (CONFIG_SYS_DOC_BASE);
-}
-#endif
diff --git a/board/cpu86/cpu86.h b/board/cpu86/cpu86.h
deleted file mode 100644
index ca0c39f..0000000
--- a/board/cpu86/cpu86.h
+++ /dev/null
@@ -1,27 +0,0 @@
-#ifndef __BOARD_CPU86__
-#define __BOARD_CPU86__
-
-#include <config.h>
-
-#define REG8(x) (*(volatile unsigned char *)(x))
-
-/* CPU86 register definitions */
-#define CPU86_VME_EAC REG8(CONFIG_SYS_BCRS_BASE + 0x00)
-#define CPU86_VME_SAC REG8(CONFIG_SYS_BCRS_BASE + 0x01)
-#define CPU86_VME_MAC REG8(CONFIG_SYS_BCRS_BASE + 0x02)
-#define CPU86_BCR REG8(CONFIG_SYS_BCRS_BASE + 0x03)
-#define CPU86_BSR REG8(CONFIG_SYS_BCRS_BASE + 0x04)
-#define CPU86_WDOG_RPORT REG8(CONFIG_SYS_BCRS_BASE + 0x05)
-#define CPU86_MBOX_IRQ REG8(CONFIG_SYS_BCRS_BASE + 0x04)
-#define CPU86_REV REG8(CONFIG_SYS_BCRS_BASE + 0x07)
-#define CPU86_VME_IRQMASK REG8(CONFIG_SYS_BCRS_BASE + 0x80)
-#define CPU86_VME_IRQSTATUS REG8(CONFIG_SYS_BCRS_BASE + 0x81)
-#define CPU86_LOCAL_IRQMASK REG8(CONFIG_SYS_BCRS_BASE + 0x82)
-#define CPU86_LOCAL_IRQSTATUS REG8(CONFIG_SYS_BCRS_BASE + 0x83)
-#define CPU86_PMCL_IRQSTATUS REG8(CONFIG_SYS_BCRS_BASE + 0x84)
-
-/* Board Control Register bits */
-#define CPU86_BCR_FWPT 0x01
-#define CPU86_BCR_FWRE 0x02
-
-#endif /* __BOARD_CPU86__ */
diff --git a/board/cpu86/flash.c b/board/cpu86/flash.c
deleted file mode 100644
index b99a9a0..0000000
--- a/board/cpu86/flash.c
+++ /dev/null
@@ -1,599 +0,0 @@
-/*
- * (C) Copyright 2001, 2002
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * Flash Routines for Intel devices
- *
- *--------------------------------------------------------------------
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-#include "cpu86.h"
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-/*-----------------------------------------------------------------------
- */
-ulong flash_int_get_size (volatile unsigned long *baseaddr,
- flash_info_t * info)
-{
- short i;
- unsigned long flashtest_h, flashtest_l;
-
- info->sector_count = info->size = 0;
- info->flash_id = FLASH_UNKNOWN;
-
- /* Write identify command sequence and test FLASH answer
- */
- baseaddr[0] = 0x00900090;
- baseaddr[1] = 0x00900090;
-
- flashtest_h = baseaddr[0]; /* manufacturer ID */
- flashtest_l = baseaddr[1];
-
- if (flashtest_h != INTEL_MANUFACT || flashtest_l != INTEL_MANUFACT)
- return (0); /* no or unknown flash */
-
- flashtest_h = baseaddr[2]; /* device ID */
- flashtest_l = baseaddr[3];
-
- if (flashtest_h != flashtest_l)
- return (0);
-
- switch (flashtest_h) {
- case INTEL_ID_28F160C3B:
- info->flash_id = FLASH_28F160C3B;
- info->sector_count = 39;
- info->size = 0x00800000; /* 4 * 2 MB = 8 MB */
- break;
- case INTEL_ID_28F160F3B:
- info->flash_id = FLASH_28F160F3B;
- info->sector_count = 39;
- info->size = 0x00800000; /* 4 * 2 MB = 8 MB */
- break;
- default:
- return (0); /* no or unknown flash */
- }
-
- info->flash_id |= INTEL_MANUFACT << 16; /* set manufacturer offset */
-
- if (info->flash_id & FLASH_BTYPE) {
- volatile unsigned long *tmp = baseaddr;
-
- /* set up sector start adress table (bottom sector type)
- * AND unlock the sectors (if our chip is 160C3)
- */
- for (i = 0; i < info->sector_count; i++) {
- if ((info->flash_id & FLASH_TYPEMASK) == FLASH_28F160C3B) {
- tmp[0] = 0x00600060;
- tmp[1] = 0x00600060;
- tmp[0] = 0x00D000D0;
- tmp[1] = 0x00D000D0;
- }
- info->start[i] = (uint) tmp;
- tmp += i < 8 ? 0x2000 : 0x10000; /* pointer arith */
- }
- }
-
- memset (info->protect, 0, info->sector_count);
-
- baseaddr[0] = 0x00FF00FF;
- baseaddr[1] = 0x00FF00FF;
-
- return (info->size);
-}
-
-static ulong flash_amd_get_size (vu_char *addr, flash_info_t *info)
-{
- short i;
- uchar vendor, devid;
- ulong base = (ulong)addr;
-
- /* Write auto select command: read Manufacturer ID */
- addr[0x0555] = 0xAA;
- addr[0x02AA] = 0x55;
- addr[0x0555] = 0x90;
-
- udelay(1000);
-
- vendor = addr[0];
- devid = addr[1] & 0xff;
-
- /* only support AMD */
- if (vendor != 0x01) {
- return 0;
- }
-
- vendor &= 0xf;
- devid &= 0xff;
-
- if (devid == AMD_ID_F040B) {
- info->flash_id = vendor << 16 | devid;
- info->sector_count = 8;
- info->size = info->sector_count * 0x10000;
- }
- else if (devid == AMD_ID_F080B) {
- info->flash_id = vendor << 16 | devid;
- info->sector_count = 16;
- info->size = 4 * info->sector_count * 0x10000;
- }
- else if (devid == AMD_ID_F016D) {
- info->flash_id = vendor << 16 | devid;
- info->sector_count = 32;
- info->size = 4 * info->sector_count * 0x10000;
- }
- else {
- printf ("## Unknown Flash Type: %02x\n", devid);
- return 0;
- }
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* sector base address */
- info->start[i] = base + i * (info->size / info->sector_count);
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- addr = (volatile unsigned char *)(info->start[i]);
- info->protect[i] = addr[2] & 1;
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- addr = (vu_char *)info->start[0];
- addr[0] = 0xF0; /* reset bank */
- }
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-unsigned long flash_init (void)
-{
- unsigned long size_b0 = 0;
- unsigned long size_b1 = 0;
- int i;
-
- /* Init: no FLASHes known
- */
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Disable flash protection */
- CPU86_BCR |= (CPU86_BCR_FWPT | CPU86_BCR_FWRE);
-
- /* Static FLASH Bank configuration here (only one bank) */
-
- size_b0 = flash_int_get_size ((ulong *) CONFIG_SYS_FLASH_BASE, &flash_info[0]);
- size_b1 = flash_amd_get_size ((uchar *) CONFIG_SYS_BOOTROM_BASE, &flash_info[1]);
-
- if (size_b0 > 0 || size_b1 > 0) {
-
- printf("(");
-
- if (size_b0 > 0) {
- puts ("Bank#1 - ");
- print_size (size_b0, (size_b1 > 0) ? ", " : ") ");
- }
-
- if (size_b1 > 0) {
- puts ("Bank#2 - ");
- print_size (size_b1, ") ");
- }
- }
- else {
- printf ("## No FLASH found.\n");
- return 0;
- }
- /* protect monitor and environment sectors
- */
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_BOOTROM_BASE
- if (size_b1) {
- /* If U-Boot is booted from ROM the CONFIG_SYS_MONITOR_BASE > CONFIG_SYS_FLASH_BASE
- * but we shouldn't protect it.
- */
-
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[1]
- );
- }
-#else
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]
- );
-#endif
-#endif
-
-#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
-# ifndef CONFIG_ENV_SIZE
-# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-# endif
-# if CONFIG_ENV_ADDR >= CONFIG_SYS_BOOTROM_BASE
- if (size_b1) {
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[1]);
- }
-# else
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
-# endif
-#endif
-
- return (size_b0 + size_b1);
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch ((info->flash_id >> 16) & 0xff) {
- case 0x89:
- printf ("INTEL ");
- break;
- case 0x1:
- printf ("AMD ");
- break;
- default:
- printf ("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F160C3B:
- printf ("28F160C3B (16 Mbit, bottom sector)\n");
- break;
- case FLASH_28F160F3B:
- printf ("28F160F3B (16 Mbit, bottom sector)\n");
- break;
- case AMD_ID_F040B:
- printf ("AM29F040B (4 Mbit)\n");
- break;
- default:
- printf ("Unknown Chip Type\n");
- break;
- }
-
- if (info->size < 0x100000)
- printf (" Size: %ld KB in %d Sectors\n",
- info->size >> 10, info->sector_count);
- else
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
-}
-
-/*-----------------------------------------------------------------------
- */
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
- vu_char *addr = (vu_char *)(info->start[0]);
- int flag, prot, sect, l_sect;
- ulong start, now, last;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect])
- prot++;
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- /* Check the type of erased flash
- */
- if (info->flash_id >> 16 == 0x1) {
- /* Erase AMD flash
- */
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x0555] = 0xAA;
- addr[0x02AA] = 0x55;
- addr[0x0555] = 0x80;
- addr[0x0555] = 0xAA;
- addr[0x02AA] = 0x55;
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = (vu_char *)(info->start[sect]);
- addr[0] = 0x30;
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto AMD_DONE;
-
- start = get_timer (0);
- last = start;
- addr = (vu_char *)(info->start[l_sect]);
- while ((addr[0] & 0x80) != 0x80) {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- serial_putc ('.');
- last = now;
- }
- }
-
-AMD_DONE:
- /* reset to read mode */
- addr = (volatile unsigned char *)info->start[0];
- addr[0] = 0xF0; /* reset bank */
-
- } else {
- /* Erase Intel flash
- */
-
- /* Start erase on unprotected sectors
- */
- for (sect = s_first; sect <= s_last; sect++) {
- volatile ulong *addr =
- (volatile unsigned long *) info->start[sect];
-
- start = get_timer (0);
- last = start;
- if (info->protect[sect] == 0) {
- /* Disable interrupts which might cause a timeout here
- */
- flag = disable_interrupts ();
-
- /* Erase the block
- */
- addr[0] = 0x00200020;
- addr[1] = 0x00200020;
- addr[0] = 0x00D000D0;
- addr[1] = 0x00D000D0;
-
- /* re-enable interrupts if necessary
- */
- if (flag)
- enable_interrupts ();
-
- /* wait at least 80us - let's wait 1 ms
- */
- udelay (1000);
-
- last = start;
- while ((addr[0] & 0x00800080) != 0x00800080 ||
- (addr[1] & 0x00800080) != 0x00800080) {
- if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout (erase suspended!)\n");
- /* Suspend erase
- */
- addr[0] = 0x00B000B0;
- addr[1] = 0x00B000B0;
- goto DONE;
- }
- /* show that we're waiting
- */
- if ((now - last) > 1000) { /* every second */
- serial_putc ('.');
- last = now;
- }
- }
- if (addr[0] & 0x00220022 || addr[1] & 0x00220022) {
- printf ("*** ERROR: erase failed!\n");
- goto DONE;
- }
- }
- /* Clear status register and reset to read mode
- */
- addr[0] = 0x00500050;
- addr[1] = 0x00500050;
- addr[0] = 0x00FF00FF;
- addr[1] = 0x00FF00FF;
- }
- }
-
- printf (" done\n");
-
-DONE:
- return 0;
-}
-
-static int write_word (flash_info_t *, volatile unsigned long *, ulong);
-static int write_byte (flash_info_t *info, ulong dest, uchar data);
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- ulong v;
- int i, l, rc, cc = cnt, res = 0;
-
- if (info->flash_id >> 16 == 0x1) {
-
- /* Write to AMD 8-bit flash
- */
- while (cnt > 0) {
- if ((rc = write_byte(info, addr, *src)) != 0) {
- return (rc);
- }
- addr++;
- src++;
- cnt--;
- }
-
- return (0);
- } else {
-
- /* Write to Intel 64-bit flash
- */
- for (v=0; cc > 0; addr += 4, cc -= 4 - l) {
- l = (addr & 3);
- addr &= ~3;
-
- for (i = 0; i < 4; i++) {
- v = (v << 8) + (i < l || i - l >= cc ?
- *((unsigned char *) addr + i) : *src++);
- }
-
- if ((res = write_word (info, (volatile unsigned long *) addr, v)) != 0)
- break;
- }
- }
-
- return (res);
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t * info, volatile unsigned long *addr,
- ulong data)
-{
- int flag, res = 0;
- ulong start;
-
- /* Check if Flash is (sufficiently) erased
- */
- if ((*addr & data) != data)
- return (2);
-
- /* Disable interrupts which might cause a timeout here
- */
- flag = disable_interrupts ();
-
- *addr = 0x00400040;
- *addr = data;
-
- /* re-enable interrupts if necessary
- */
- if (flag)
- enable_interrupts ();
-
- start = get_timer (0);
- while ((*addr & 0x00800080) != 0x00800080) {
- if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- /* Suspend program
- */
- *addr = 0x00B000B0;
- res = 1;
- goto OUT;
- }
- }
-
- if (*addr & 0x00220022) {
- printf ("*** ERROR: program failed!\n");
- res = 1;
- }
-
-OUT:
- /* Clear status register and reset to read mode
- */
- *addr = 0x00500050;
- *addr = 0x00FF00FF;
-
- return (res);
-}
-
-/*-----------------------------------------------------------------------
- * Write a byte to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_byte (flash_info_t *info, ulong dest, uchar data)
-{
- vu_char *addr = (vu_char *)(info->start[0]);
- ulong start;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((vu_char *)dest) & data) != data) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x0555] = 0xAA;
- addr[0x02AA] = 0x55;
- addr[0x0555] = 0xA0;
-
- *((vu_char *)dest) = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((*((vu_char *)dest) & 0x80) != (data & 0x80)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
diff --git a/board/cpu87/Kconfig b/board/cpu87/Kconfig
deleted file mode 100644
index a4f2768..0000000
--- a/board/cpu87/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_CPU87
-
-config SYS_BOARD
- default "cpu87"
-
-config SYS_CONFIG_NAME
- default "CPU87"
-
-endif
diff --git a/board/cpu87/MAINTAINERS b/board/cpu87/MAINTAINERS
deleted file mode 100644
index 32804ea..0000000
--- a/board/cpu87/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-CPU87 BOARD
-#M: -
-S: Maintained
-F: board/cpu87/
-F: include/configs/CPU87.h
-F: configs/CPU87_defconfig
-F: configs/CPU87_ROMBOOT_defconfig
diff --git a/board/cpu87/Makefile b/board/cpu87/Makefile
deleted file mode 100644
index 0d59bbb..0000000
--- a/board/cpu87/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = cpu87.o flash.o
diff --git a/board/cpu87/cpu87.c b/board/cpu87/cpu87.c
deleted file mode 100644
index 01f90d2..0000000
--- a/board/cpu87/cpu87.c
+++ /dev/null
@@ -1,330 +0,0 @@
-/*
- * (C) Copyright 2001-2005
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc8260.h>
-#include "cpu87.h"
-#include <pci.h>
-#include <netdev.h>
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
- /* Port A configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
- /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
- /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
- /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
- /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
- /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
- /* PA25 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII MDIO */
- /* PA24 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII MDC */
- /* PA23 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII MDIO */
- /* PA22 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII MDC */
- /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
- /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
- /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
- /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
- /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
- /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */
- /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
- /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
- /* PA13 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII TXSL1 */
- /* PA12 */ { 1, 0, 0, 1, 0, 1 }, /* FCC2 MII TXSL0 */
- /* PA11 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII TXSL1 */
- /* PA10 */ { 1, 0, 0, 1, 0, 1 }, /* FCC1 MII TXSL0 */
- /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
- /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
- /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */
- /* PA6 */ { 1, 0, 0, 1, 0, 1 }, /* FCC2 MII PAUSE */
- /* PA5 */ { 1, 0, 0, 1, 0, 1 }, /* FCC1 MII PAUSE */
- /* PA4 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII PWRDN */
- /* PA3 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII PWRDN */
- /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */
- /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FCC2 MII MDINT */
- /* PA0 */ { 1, 0, 0, 1, 0, 0 } /* FCC1 MII MDINT */
- },
-
- /* Port B configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
- /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
- /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
- /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
- /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
- /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
- /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
- /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
- /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
- /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
- /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
- /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
- /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
- /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
- /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */
- /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */
- /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */
- /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */
- /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */
- /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */
- /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */
- /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */
- /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */
- /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */
- /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
- /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */
- /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */
- /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */
- /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* PB3 */
- /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* PB2 */
- /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* PB1 */
- /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* PB0 */
- },
-
- /* Port C */
- { /* conf ppar psor pdir podr pdat */
- /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
- /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
- /* PC29 */ { 1, 0, 0, 0, 0, 0 }, /* SCC1 CTS */
- /* PC28 */ { 1, 0, 0, 0, 0, 0 }, /* SCC2 CTS */
- /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
- /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
- /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
- /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
- /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DACFD */
- /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DNFD */
- /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */
- /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII TX_CLK */
- /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */
- /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */
- /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
- /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */
- /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
- /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
- /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
- /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
- /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
- /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
- /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FC9 */
- /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */
- /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
- /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
- /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
- /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
- /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
- /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
- /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
- /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DRQFD */
- },
-
- /* Port D */
- { /* conf ppar psor pdir podr pdat */
- /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RXD */
- /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TXD */
- /* PD29 */ { 1, 0, 0, 1, 0, 0 }, /* SCC1 RTS */
- /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */
- /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TXD */
- /* PD26 */ { 1, 0, 0, 1, 0, 0 }, /* SCC2 RTS */
- /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */
- /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */
- /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */
- /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */
- /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */
- /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */
- /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */
- /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */
- /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */
- /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */
-#if defined(CONFIG_SYS_I2C_SOFT)
- /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */
- /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */
-#else
-#if defined(CONFIG_HARD_I2C)
- /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
- /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
-#else /* normal I/O port pins */
- /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
- /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
-#endif
-#endif
- /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
- /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
- /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
- /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
- /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
- /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
- /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */
- /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */
- /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */
- /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */
- /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* PD3 */
- /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* PD2 */
- /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* PD1 */
- /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* PD0 */
- }
-};
-
-/* ------------------------------------------------------------------------- */
-
-/* Check Board Identity:
- */
-int checkboard (void)
-{
- printf ("Board: CPU87 (Rev %02x)\n", CPU86_REV & 0x7f);
- return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
- *
- * This routine performs standard 8260 initialization sequence
- * and calculates the available memory size. It may be called
- * several times to try different SDRAM configurations on both
- * 60x and local buses.
- */
-static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
- ulong orx, volatile uchar * base)
-{
- volatile uchar c = 0xff;
- volatile uint *sdmr_ptr;
- volatile uint *orx_ptr;
- ulong maxsize, size;
- int i;
-
- /* We must be able to test a location outsize the maximum legal size
- * to find out THAT we are outside; but this address still has to be
- * mapped by the controller. That means, that the initial mapping has
- * to be (at least) twice as large as the maximum expected size.
- */
- maxsize = (1 + (~orx | 0x7fff)) / 2;
-
- /* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that
- * we are configuring CS1 if base != 0
- */
- sdmr_ptr = &memctl->memc_psdmr;
- orx_ptr = &memctl->memc_or2;
-
- *orx_ptr = orx;
-
- /*
- * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
- *
- * "At system reset, initialization software must set up the
- * programmable parameters in the memory controller banks registers
- * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
- * system software should execute the following initialization sequence
- * for each SDRAM device.
- *
- * 1. Issue a PRECHARGE-ALL-BANKS command
- * 2. Issue eight CBR REFRESH commands
- * 3. Issue a MODE-SET command to initialize the mode register
- *
- * The initial commands are executed by setting P/LSDMR[OP] and
- * accessing the SDRAM with a single-byte transaction."
- *
- * The appropriate BRx/ORx registers have already been set when we
- * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
- */
-
- *sdmr_ptr = sdmr | PSDMR_OP_PREA;
- *base = c;
-
- *sdmr_ptr = sdmr | PSDMR_OP_CBRR;
- for (i = 0; i < 8; i++)
- *base = c;
-
- *sdmr_ptr = sdmr | PSDMR_OP_MRW;
- *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */
-
- *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
- *base = c;
-
- size = get_ram_size((long *)base, maxsize);
-
- *orx_ptr = orx | ~(size - 1);
-
- return (size);
-}
-
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8260_t *memctl = &immap->im_memctl;
-
-#ifndef CONFIG_SYS_RAMBOOT
- ulong size8, size9, size10;
-#endif
- long psize;
-
- psize = 32 * 1024 * 1024;
-
- memctl->memc_mptpr = CONFIG_SYS_MPTPR;
- memctl->memc_psrt = CONFIG_SYS_PSRT;
-
-#ifndef CONFIG_SYS_RAMBOOT
- /* 60x SDRAM setup:
- */
- size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
- (uchar *) CONFIG_SYS_SDRAM_BASE);
-
- size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL,
- (uchar *) CONFIG_SYS_SDRAM_BASE);
-
- size10 = try_init (memctl, CONFIG_SYS_PSDMR_10COL, CONFIG_SYS_OR2_10COL,
- (uchar *) CONFIG_SYS_SDRAM_BASE);
-
- psize = max(size8,max(size9,size10));
-
- if (psize == size8) {
- psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
- (uchar *) CONFIG_SYS_SDRAM_BASE);
- printf ("(60x:8COL) ");
- } else if (psize == size9){
- psize = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL,
- (uchar *) CONFIG_SYS_SDRAM_BASE);
- printf ("(60x:9COL) ");
- } else
- printf ("(60x:10COL) ");
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
- icache_enable ();
-
- return (psize);
-}
-
-#if defined(CONFIG_CMD_DOC)
-void doc_init (void)
-{
- doc_probe (CONFIG_SYS_DOC_BASE);
-}
-#endif
-
-#ifdef CONFIG_PCI
-struct pci_controller hose;
-
-extern void pci_mpc8250_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
- pci_mpc8250_init(&hose);
-}
-#endif
-
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
diff --git a/board/cpu87/cpu87.h b/board/cpu87/cpu87.h
deleted file mode 100644
index 45cb853..0000000
--- a/board/cpu87/cpu87.h
+++ /dev/null
@@ -1,27 +0,0 @@
-#ifndef __BOARD_CPU87__
-#define __BOARD_CPU87__
-
-#include <config.h>
-
-#define REG8(x) (*(volatile unsigned char *)(x))
-
-/* CPU86 register definitions */
-#define CPU86_VME_EAC REG8(CONFIG_SYS_BCRS_BASE + 0x00)
-#define CPU86_VME_SAC REG8(CONFIG_SYS_BCRS_BASE + 0x01)
-#define CPU86_VME_MAC REG8(CONFIG_SYS_BCRS_BASE + 0x02)
-#define CPU86_BCR REG8(CONFIG_SYS_BCRS_BASE + 0x03)
-#define CPU86_BSR REG8(CONFIG_SYS_BCRS_BASE + 0x04)
-#define CPU86_WDOG_RPORT REG8(CONFIG_SYS_BCRS_BASE + 0x05)
-#define CPU86_MBOX_IRQ REG8(CONFIG_SYS_BCRS_BASE + 0x04)
-#define CPU86_REV REG8(CONFIG_SYS_BCRS_BASE + 0x07)
-#define CPU86_VME_IRQMASK REG8(CONFIG_SYS_BCRS_BASE + 0x80)
-#define CPU86_VME_IRQSTATUS REG8(CONFIG_SYS_BCRS_BASE + 0x81)
-#define CPU86_LOCAL_IRQMASK REG8(CONFIG_SYS_BCRS_BASE + 0x82)
-#define CPU86_LOCAL_IRQSTATUS REG8(CONFIG_SYS_BCRS_BASE + 0x83)
-#define CPU86_PMCL_IRQSTATUS REG8(CONFIG_SYS_BCRS_BASE + 0x84)
-
-/* Board Control Register bits */
-#define CPU86_BCR_FWPT 0x01
-#define CPU86_BCR_FWRE 0x02
-
-#endif /* __BOARD_CPU87__ */
diff --git a/board/cpu87/flash.c b/board/cpu87/flash.c
deleted file mode 100644
index 96ba7d9..0000000
--- a/board/cpu87/flash.c
+++ /dev/null
@@ -1,608 +0,0 @@
-/*
- * (C) Copyright 2001-2005
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * Flash Routines for Intel devices
- *
- *--------------------------------------------------------------------
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-#include "cpu87.h"
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-/*-----------------------------------------------------------------------
- */
-ulong flash_int_get_size (volatile unsigned long *baseaddr,
- flash_info_t * info)
-{
- short i;
- unsigned long flashtest_h, flashtest_l;
-
- info->sector_count = info->size = 0;
- info->flash_id = FLASH_UNKNOWN;
-
- /* Write identify command sequence and test FLASH answer
- */
- baseaddr[0] = 0x00900090;
- baseaddr[1] = 0x00900090;
-
- flashtest_h = baseaddr[0]; /* manufacturer ID */
- flashtest_l = baseaddr[1];
-
- if (flashtest_h != INTEL_MANUFACT || flashtest_l != INTEL_MANUFACT)
- return (0); /* no or unknown flash */
-
- flashtest_h = baseaddr[2]; /* device ID */
- flashtest_l = baseaddr[3];
-
- if (flashtest_h != flashtest_l)
- return (0);
-
- switch (flashtest_h) {
- case INTEL_ID_28F160C3B:
- info->flash_id = FLASH_28F160C3B;
- info->sector_count = 39;
- info->size = 0x00800000; /* 4 * 2 MB = 8 MB */
- break;
- case INTEL_ID_28F160F3B:
- info->flash_id = FLASH_28F160F3B;
- info->sector_count = 39;
- info->size = 0x00800000; /* 4 * 2 MB = 8 MB */
- break;
- case INTEL_ID_28F640C3B:
- info->flash_id = FLASH_28F640C3B;
- info->sector_count = 135;
- info->size = 0x02000000; /* 16 * 2 MB = 32 MB */
- break;
- default:
- return (0); /* no or unknown flash */
- }
-
- info->flash_id |= INTEL_MANUFACT << 16; /* set manufacturer offset */
-
- if (info->flash_id & FLASH_BTYPE) {
- volatile unsigned long *tmp = baseaddr;
-
- /* set up sector start adress table (bottom sector type)
- * AND unlock the sectors (if our chip is 160C3)
- */
- for (i = 0; i < info->sector_count; i++) {
- if (((info->flash_id & FLASH_TYPEMASK) == FLASH_28F160C3B) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_28F640C3B)) {
- tmp[0] = 0x00600060;
- tmp[1] = 0x00600060;
- tmp[0] = 0x00D000D0;
- tmp[1] = 0x00D000D0;
- }
- info->start[i] = (uint) tmp;
- tmp += i < 8 ? 0x2000 : 0x10000; /* pointer arith */
- }
- }
-
- memset (info->protect, 0, info->sector_count);
-
- baseaddr[0] = 0x00FF00FF;
- baseaddr[1] = 0x00FF00FF;
-
- return (info->size);
-}
-
-static ulong flash_amd_get_size (vu_char *addr, flash_info_t *info)
-{
- short i;
- uchar vendor, devid;
- ulong base = (ulong)addr;
-
- /* Write auto select command: read Manufacturer ID */
- addr[0x0555] = 0xAA;
- addr[0x02AA] = 0x55;
- addr[0x0555] = 0x90;
-
- udelay(1000);
-
- vendor = addr[0];
- devid = addr[1] & 0xff;
-
- /* only support AMD */
- if (vendor != 0x01) {
- return 0;
- }
-
- vendor &= 0xf;
- devid &= 0xff;
-
- if (devid == AMD_ID_F040B) {
- info->flash_id = vendor << 16 | devid;
- info->sector_count = 8;
- info->size = info->sector_count * 0x10000;
- }
- else if (devid == AMD_ID_F080B) {
- info->flash_id = vendor << 16 | devid;
- info->sector_count = 16;
- info->size = 4 * info->sector_count * 0x10000;
- }
- else if (devid == AMD_ID_F016D) {
- info->flash_id = vendor << 16 | devid;
- info->sector_count = 32;
- info->size = 4 * info->sector_count * 0x10000;
- }
- else {
- printf ("## Unknown Flash Type: %02x\n", devid);
- return 0;
- }
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* sector base address */
- info->start[i] = base + i * (info->size / info->sector_count);
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- addr = (volatile unsigned char *)(info->start[i]);
- info->protect[i] = addr[2] & 1;
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- addr = (vu_char *)info->start[0];
- addr[0] = 0xF0; /* reset bank */
- }
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-unsigned long flash_init (void)
-{
- unsigned long size_b0 = 0;
- unsigned long size_b1 = 0;
- int i;
-
- /* Init: no FLASHes known
- */
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Disable flash protection */
- CPU86_BCR |= (CPU86_BCR_FWPT | CPU86_BCR_FWRE);
-
- /* Static FLASH Bank configuration here (only one bank) */
-
- size_b0 = flash_int_get_size ((ulong *) CONFIG_SYS_FLASH_BASE, &flash_info[0]);
- size_b1 = flash_amd_get_size ((uchar *) CONFIG_SYS_BOOTROM_BASE, &flash_info[1]);
-
- if (size_b0 > 0 || size_b1 > 0) {
-
- printf("(");
-
- if (size_b0 > 0) {
- puts ("Bank#1 - ");
- print_size (size_b0, (size_b1 > 0) ? ", " : ") ");
- }
-
- if (size_b1 > 0) {
- puts ("Bank#2 - ");
- print_size (size_b1, ") ");
- }
- }
- else {
- printf ("## No FLASH found.\n");
- return 0;
- }
- /* protect monitor and environment sectors
- */
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_BOOTROM_BASE
- if (size_b1) {
- /* If U-Boot is booted from ROM the CONFIG_SYS_MONITOR_BASE > CONFIG_SYS_FLASH_BASE
- * but we shouldn't protect it.
- */
-
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[1]
- );
- }
-#else
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]
- );
-#endif
-#endif
-
-#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
-# ifndef CONFIG_ENV_SIZE
-# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-# endif
-# if CONFIG_ENV_ADDR >= CONFIG_SYS_BOOTROM_BASE
- if (size_b1) {
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[1]);
- }
-# else
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
-# endif
-#endif
-
- return (size_b0 + size_b1);
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch ((info->flash_id >> 16) & 0xff) {
- case 0x89:
- printf ("INTEL ");
- break;
- case 0x1:
- printf ("AMD ");
- break;
- default:
- printf ("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F160C3B:
- printf ("28F160C3B (16 Mbit, bottom sector)\n");
- break;
- case FLASH_28F160F3B:
- printf ("28F160F3B (16 Mbit, bottom sector)\n");
- break;
- case FLASH_28F640C3B:
- printf ("28F640C3B (64 M, bottom sector)\n");
- break;
- case AMD_ID_F040B:
- printf ("AM29F040B (4 Mbit)\n");
- break;
- default:
- printf ("Unknown Chip Type\n");
- break;
- }
-
- if (info->size < 0x100000)
- printf (" Size: %ld KB in %d Sectors\n",
- info->size >> 10, info->sector_count);
- else
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
-}
-
-/*-----------------------------------------------------------------------
- */
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
- vu_char *addr = (vu_char *)(info->start[0]);
- int flag, prot, sect, l_sect;
- ulong start, now, last;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect])
- prot++;
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- /* Check the type of erased flash
- */
- if (info->flash_id >> 16 == 0x1) {
- /* Erase AMD flash
- */
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x0555] = 0xAA;
- addr[0x02AA] = 0x55;
- addr[0x0555] = 0x80;
- addr[0x0555] = 0xAA;
- addr[0x02AA] = 0x55;
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = (vu_char *)(info->start[sect]);
- addr[0] = 0x30;
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto AMD_DONE;
-
- start = get_timer (0);
- last = start;
- addr = (vu_char *)(info->start[l_sect]);
- while ((addr[0] & 0x80) != 0x80) {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- serial_putc ('.');
- last = now;
- }
- }
-
-AMD_DONE:
- /* reset to read mode */
- addr = (volatile unsigned char *)info->start[0];
- addr[0] = 0xF0; /* reset bank */
-
- } else {
- /* Erase Intel flash
- */
-
- /* Start erase on unprotected sectors
- */
- for (sect = s_first; sect <= s_last; sect++) {
- volatile ulong *addr =
- (volatile unsigned long *) info->start[sect];
-
- start = get_timer (0);
- last = start;
- if (info->protect[sect] == 0) {
- /* Disable interrupts which might cause a timeout here
- */
- flag = disable_interrupts ();
-
- /* Erase the block
- */
- addr[0] = 0x00200020;
- addr[1] = 0x00200020;
- addr[0] = 0x00D000D0;
- addr[1] = 0x00D000D0;
-
- /* re-enable interrupts if necessary
- */
- if (flag)
- enable_interrupts ();
-
- /* wait at least 80us - let's wait 1 ms
- */
- udelay (1000);
-
- last = start;
- while ((addr[0] & 0x00800080) != 0x00800080 ||
- (addr[1] & 0x00800080) != 0x00800080) {
- if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout (erase suspended!)\n");
- /* Suspend erase
- */
- addr[0] = 0x00B000B0;
- addr[1] = 0x00B000B0;
- goto DONE;
- }
- /* show that we're waiting
- */
- if ((now - last) > 1000) { /* every second */
- serial_putc ('.');
- last = now;
- }
- }
- if (addr[0] & 0x00220022 || addr[1] & 0x00220022) {
- printf ("*** ERROR: erase failed!\n");
- goto DONE;
- }
- }
- /* Clear status register and reset to read mode
- */
- addr[0] = 0x00500050;
- addr[1] = 0x00500050;
- addr[0] = 0x00FF00FF;
- addr[1] = 0x00FF00FF;
- }
- }
-
- printf (" done\n");
-
-DONE:
- return 0;
-}
-
-static int write_word (flash_info_t *, volatile unsigned long *, ulong);
-static int write_byte (flash_info_t *info, ulong dest, uchar data);
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- ulong v;
- int i, l, rc, cc = cnt, res = 0;
-
- if (info->flash_id >> 16 == 0x1) {
-
- /* Write to AMD 8-bit flash
- */
- while (cnt > 0) {
- if ((rc = write_byte(info, addr, *src)) != 0) {
- return (rc);
- }
- addr++;
- src++;
- cnt--;
- }
-
- return (0);
- } else {
-
- /* Write to Intel 64-bit flash
- */
- for (v=0; cc > 0; addr += 4, cc -= 4 - l) {
- l = (addr & 3);
- addr &= ~3;
-
- for (i = 0; i < 4; i++) {
- v = (v << 8) + (i < l || i - l >= cc ?
- *((unsigned char *) addr + i) : *src++);
- }
-
- if ((res = write_word (info, (volatile unsigned long *) addr, v)) != 0)
- break;
- }
- }
-
- return (res);
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t * info, volatile unsigned long *addr,
- ulong data)
-{
- int flag, res = 0;
- ulong start;
-
- /* Check if Flash is (sufficiently) erased
- */
- if ((*addr & data) != data)
- return (2);
-
- /* Disable interrupts which might cause a timeout here
- */
- flag = disable_interrupts ();
-
- *addr = 0x00400040;
- *addr = data;
-
- /* re-enable interrupts if necessary
- */
- if (flag)
- enable_interrupts ();
-
- start = get_timer (0);
- while ((*addr & 0x00800080) != 0x00800080) {
- if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- /* Suspend program
- */
- *addr = 0x00B000B0;
- res = 1;
- goto OUT;
- }
- }
-
- if (*addr & 0x00220022) {
- printf ("*** ERROR: program failed!\n");
- res = 1;
- }
-
-OUT:
- /* Clear status register and reset to read mode
- */
- *addr = 0x00500050;
- *addr = 0x00FF00FF;
-
- return (res);
-}
-
-/*-----------------------------------------------------------------------
- * Write a byte to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_byte (flash_info_t *info, ulong dest, uchar data)
-{
- vu_char *addr = (vu_char *)(info->start[0]);
- ulong start;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((vu_char *)dest) & data) != data) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x0555] = 0xAA;
- addr[0x02AA] = 0x55;
- addr[0x0555] = 0xA0;
-
- *((vu_char *)dest) = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((*((vu_char *)dest) & 0x80) != (data & 0x80)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
diff --git a/configs/CPU86_ROMBOOT_defconfig b/configs/CPU86_ROMBOOT_defconfig
deleted file mode 100644
index 41aa7df..0000000
--- a/configs/CPU86_ROMBOOT_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="BOOT_ROM"
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_CPU86=y
diff --git a/configs/CPU86_defconfig b/configs/CPU86_defconfig
deleted file mode 100644
index f0a4049..0000000
--- a/configs/CPU86_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_CPU86=y
diff --git a/configs/CPU87_ROMBOOT_defconfig b/configs/CPU87_ROMBOOT_defconfig
deleted file mode 100644
index ba13b40..0000000
--- a/configs/CPU87_ROMBOOT_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="BOOT_ROM"
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_CPU87=y
diff --git a/configs/CPU87_defconfig b/configs/CPU87_defconfig
deleted file mode 100644
index 86a5737..0000000
--- a/configs/CPU87_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_CPU87=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 400eea1..c0d0cd9 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,8 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+CPU86 powerpc mpc8260 - - Wolfgang Denk <wd@denx.de>
+CPU87 powerpc mpc8260 - -
ep82xxm powerpc mpc8260 - -
gw8260 powerpc mpc8260 - - Oliver Brown <obrown@adventnetworks.com>
IPHASE4539 powerpc mpc8260 - - Wolfgang Grandegger <wg@denx.de>
diff --git a/include/configs/CPU86.h b/include/configs/CPU86.h
deleted file mode 100644
index 7be83b0..0000000
--- a/include/configs/CPU86.h
+++ /dev/null
@@ -1,629 +0,0 @@
-/*
- * (C) Copyright 2001-2005
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_CPU86 1 /* ...on a CPU86 board */
-#define CONFIG_CPM2 1 /* Has a CPM2 */
-
-#ifdef CONFIG_BOOT_ROM
-#define CONFIG_SYS_TEXT_BASE 0xFF800000
-#else
-#define CONFIG_SYS_TEXT_BASE 0xFF000000
-#endif
-
-/*
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * if CONFIG_CONS_NONE is defined, then the serial console routines must
- * defined elsewhere (for example, on the cogent platform, there are serial
- * ports on the motherboard which are used for the serial console - see
- * cogent/cma101/serial.[ch]).
- */
-#undef CONFIG_CONS_ON_SMC /* define if console on SMC */
-#define CONFIG_CONS_ON_SCC /* define if console on SCC */
-#undef CONFIG_CONS_NONE /* define if console on something else*/
-#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
-
-#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
-#define CONFIG_BAUDRATE 230400
-#else
-#define CONFIG_BAUDRATE 9600
-#endif
-
-/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
- */
-#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
-#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
-#undef CONFIG_ETHER_NONE /* define if ether on something else */
-#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
-
-#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
-
-/*
- * - Rx-CLK is CLK11
- * - Tx-CLK is CLK12
- * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
-# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
-# define CONFIG_SYS_CPMFCR_RAMTYPE 0
-# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
-
-#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
-
-/*
- * - Rx-CLK is CLK13
- * - Tx-CLK is CLK14
- * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
-# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
-# define CONFIG_SYS_CPMFCR_RAMTYPE 0
-# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
-
-#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
-
-/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
-#define CONFIG_8260_CLKIN 64000000 /* in Hz */
-
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#define CONFIG_PREBOOT \
- "echo; " \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS; " \
- "echo"
-
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND \
- "bootp; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
- "bootm"
-
-/*-----------------------------------------------------------------------
- * I2C/EEPROM/RTC configuration
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED 50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
-
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE (iop->pdir |= 0x00010000)
-#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
-#define I2C_READ ((iop->pdat & 0x00010000) != 0)
-#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
- else iop->pdat &= ~0x00010000
-#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
- else iop->pdat &= ~0x00020000
-#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
-
-#define CONFIG_RTC_PCF8563
-#define CONFIG_SYS_I2C_RTC_ADDR 0x51
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configuration options
- */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BEDBUG
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_SNTP
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 /* "bad" address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * Flash configuration
- */
-
-#define CONFIG_SYS_BOOTROM_BASE 0xFF800000
-#define CONFIG_SYS_BOOTROM_SIZE 0x00080000
-#define CONFIG_SYS_FLASH_BASE 0xFF000000
-#define CONFIG_SYS_FLASH_SIZE 0x00800000
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
-
-/*-----------------------------------------------------------------------
- * Other areas to be mapped
- */
-
-/* CS3: Dual ported SRAM */
-#define CONFIG_SYS_DPSRAM_BASE 0x40000000
-#define CONFIG_SYS_DPSRAM_SIZE 0x00020000
-
-/* CS4: DiskOnChip */
-#define CONFIG_SYS_DOC_BASE 0xF4000000
-#define CONFIG_SYS_DOC_SIZE 0x00100000
-
-/* CS5: FDC37C78 controller */
-#define CONFIG_SYS_FDC37C78_BASE 0xF1000000
-#define CONFIG_SYS_FDC37C78_SIZE 0x00100000
-
-/* CS6: Board configuration registers */
-#define CONFIG_SYS_BCRS_BASE 0xF2000000
-#define CONFIG_SYS_BCRS_SIZE 0x00010000
-
-/* CS7: VME Extended Access Range */
-#define CONFIG_SYS_VMEEAR_BASE 0x80000000
-#define CONFIG_SYS_VMEEAR_SIZE 0x01000000
-
-/* CS8: VME Standard Access Range */
-#define CONFIG_SYS_VMESAR_BASE 0xFE000000
-#define CONFIG_SYS_VMESAR_SIZE 0x01000000
-
-/* CS9: VME Short I/O Access Range */
-#define CONFIG_SYS_VMESIOAR_BASE 0xFD000000
-#define CONFIG_SYS_VMESIOAR_SIZE 0x01000000
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
- *
- * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
- * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
- */
-#if defined(CONFIG_BOOT_ROM)
-#define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
- HRCW_BPS01 | HRCW_CS10PC01)
-#else
-#define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | HRCW_CS10PC01)
-#endif
-
-/* no slaves so just fill with zeros */
-#define CONFIG_SYS_HRCW_SLAVE1 0
-#define CONFIG_SYS_HRCW_SLAVE2 0
-#define CONFIG_SYS_HRCW_SLAVE3 0
-#define CONFIG_SYS_HRCW_SLAVE4 0
-#define CONFIG_SYS_HRCW_SLAVE5 0
-#define CONFIG_SYS_HRCW_SLAVE6 0
-#define CONFIG_SYS_HRCW_SLAVE7 0
-
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xF0000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- *
- * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE.
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-# define CONFIG_SYS_RAMBOOT
-#endif
-
-#if 0
-/* environment is in Flash */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#ifdef CONFIG_BOOT_ROM
-# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x70000)
-# define CONFIG_ENV_SIZE 0x10000
-# define CONFIG_ENV_SECT_SIZE 0x10000
-#endif
-#else
-/* environment is in EEPROM */
-#define CONFIG_ENV_IS_IN_EEPROM 1
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 /* EEPROM X24C16 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-/* mask of address bits that overflow into the "EEPROM chip address" */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-#define CONFIG_ENV_OFFSET 512
-#define CONFIG_ENV_SIZE (2048 - 512)
-#endif
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers 2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|\
- HID0_DCI|HID0_IFEM|HID0_ABE)
-#define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE)
-#define CONFIG_SYS_HID2 0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register 5-5
- *-----------------------------------------------------------------------
- * turn on Checkstop Reset Enable
- */
-#define CONFIG_SYS_RMR RMR_CSRE
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration 4-25
- *-----------------------------------------------------------------------
- */
-#define BCR_APD01 0x10000000
-#define CONFIG_SYS_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 4-31
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_SIUMCR (SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\
- SIUMCR_CS10PC01|SIUMCR_BCTLC10)
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 4-35
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
- SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
- SYPCR_SWRI|SYPCR_SWP)
-#endif /* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control 4-40
- *-----------------------------------------------------------------------
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- */
-#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control 9-8
- *-----------------------------------------------------------------------
- * Ensure DFBRG is Divide by 16
- */
-#define CONFIG_SYS_SCCR SCCR_DFBRG01
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration 13-7
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RCCR 0
-
-#define CONFIG_SYS_MIN_AM_MASK 0xC0000000
-/*-----------------------------------------------------------------------
- * MPTPR - Memory Refresh Timer Prescaler Register 10-18
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_MPTPR 0x1F00
-
-/*-----------------------------------------------------------------------
- * PSRT - Refresh Timer Register 10-16
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_PSRT 0x0f
-
-/*-----------------------------------------------------------------------
- * PSRT - SDRAM Mode Register 10-10
- *-----------------------------------------------------------------------
- */
-
- /* SDRAM initialization values for 8-column chips
- */
-#define CONFIG_SYS_OR2_8COL (CONFIG_SYS_MIN_AM_MASK |\
- ORxS_BPD_4 |\
- ORxS_ROWST_PBI0_A9 |\
- ORxS_NUMR_12)
-
-#define CONFIG_SYS_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\
- PSDMR_BSMA_A14_A16 |\
- PSDMR_SDA10_PBI0_A10 |\
- PSDMR_RFRC_7_CLK |\
- PSDMR_PRETOACT_2W |\
- PSDMR_ACTTORW_1W |\
- PSDMR_LDOTOPRE_1C |\
- PSDMR_WRC_1C |\
- PSDMR_CL_2)
-
- /* SDRAM initialization values for 9-column chips
- */
-#define CONFIG_SYS_OR2_9COL (CONFIG_SYS_MIN_AM_MASK |\
- ORxS_BPD_4 |\
- ORxS_ROWST_PBI0_A7 |\
- ORxS_NUMR_13)
-
-#define CONFIG_SYS_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\
- PSDMR_BSMA_A13_A15 |\
- PSDMR_SDA10_PBI0_A9 |\
- PSDMR_RFRC_7_CLK |\
- PSDMR_PRETOACT_2W |\
- PSDMR_ACTTORW_1W |\
- PSDMR_LDOTOPRE_1C |\
- PSDMR_WRC_1C |\
- PSDMR_CL_2)
-
-/*
- * Init Memory Controller:
- *
- * Bank Bus Machine PortSz Device
- * ---- --- ------- ------ ------
- * 0 60x GPCM 8 bit Boot ROM
- * 1 60x GPCM 64 bit FLASH
- * 2 60x SDRAM 64 bit SDRAM
- *
- */
-
-#define CONFIG_SYS_MRS_OFFS 0x00000000
-
-#ifdef CONFIG_BOOT_ROM
-/* Bank 0 - Boot ROM
- */
-#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
- BRx_PS_8 |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE) |\
- ORxG_CSNT |\
- ORxG_ACS_DIV1 |\
- ORxG_SCY_3_CLK |\
- ORxU_EHTR_8IDLE)
-
-/* Bank 1 - FLASH
- */
-#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
- BRx_PS_64 |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
- ORxG_CSNT |\
- ORxG_ACS_DIV1 |\
- ORxG_SCY_3_CLK |\
- ORxU_EHTR_8IDLE)
-
-#else /* CONFIG_BOOT_ROM */
-/* Bank 0 - FLASH
- */
-#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
- BRx_PS_64 |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
- ORxG_CSNT |\
- ORxG_ACS_DIV1 |\
- ORxG_SCY_3_CLK |\
- ORxU_EHTR_8IDLE)
-
-/* Bank 1 - Boot ROM
- */
-#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
- BRx_PS_8 |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE) |\
- ORxG_CSNT |\
- ORxG_ACS_DIV1 |\
- ORxG_SCY_3_CLK |\
- ORxU_EHTR_8IDLE)
-
-#endif /* CONFIG_BOOT_ROM */
-
-
-/* Bank 2 - 60x bus SDRAM
- */
-#ifndef CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
- BRx_PS_64 |\
- BRx_MS_SDRAM_P |\
- BRx_V)
-
-#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_9COL
-
-#define CONFIG_SYS_PSDMR CONFIG_SYS_PSDMR_9COL
-#endif /* CONFIG_SYS_RAMBOOT */
-
-/* Bank 3 - Dual Ported SRAM
- */
-#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_DPSRAM_BASE & BRx_BA_MSK) |\
- BRx_PS_16 |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_DPSRAM_SIZE) |\
- ORxG_CSNT |\
- ORxG_ACS_DIV1 |\
- ORxG_SCY_5_CLK |\
- ORxG_SETA)
-
-/* Bank 4 - DiskOnChip
- */
-#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_DOC_BASE & BRx_BA_MSK) |\
- BRx_PS_8 |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-#define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE) |\
- ORxG_ACS_DIV2 |\
- ORxG_SCY_5_CLK |\
- ORxU_EHTR_8IDLE)
-
-/* Bank 5 - FDC37C78 controller
- */
-#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_FDC37C78_BASE & BRx_BA_MSK) |\
- BRx_PS_8 |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-#define CONFIG_SYS_OR5_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FDC37C78_SIZE) |\
- ORxG_ACS_DIV2 |\
- ORxG_SCY_8_CLK |\
- ORxU_EHTR_8IDLE)
-
-/* Bank 6 - Board control registers
- */
-#define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_BCRS_BASE & BRx_BA_MSK) |\
- BRx_PS_8 |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-#define CONFIG_SYS_OR6_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCRS_SIZE) |\
- ORxG_CSNT |\
- ORxG_SCY_5_CLK)
-
-/* Bank 7 - VME Extended Access Range
- */
-#define CONFIG_SYS_BR7_PRELIM ((CONFIG_SYS_VMEEAR_BASE & BRx_BA_MSK) |\
- BRx_PS_32 |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-#define CONFIG_SYS_OR7_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VMEEAR_SIZE) |\
- ORxG_CSNT |\
- ORxG_ACS_DIV1 |\
- ORxG_SCY_5_CLK |\
- ORxG_SETA)
-
-/* Bank 8 - VME Standard Access Range
- */
-#define CONFIG_SYS_BR8_PRELIM ((CONFIG_SYS_VMESAR_BASE & BRx_BA_MSK) |\
- BRx_PS_16 |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-#define CONFIG_SYS_OR8_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VMESAR_SIZE) |\
- ORxG_CSNT |\
- ORxG_ACS_DIV1 |\
- ORxG_SCY_5_CLK |\
- ORxG_SETA)
-
-/* Bank 9 - VME Short I/O Access Range
- */
-#define CONFIG_SYS_BR9_PRELIM ((CONFIG_SYS_VMESIOAR_BASE & BRx_BA_MSK) |\
- BRx_PS_16 |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-#define CONFIG_SYS_OR9_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VMESIOAR_SIZE) |\
- ORxG_CSNT |\
- ORxG_ACS_DIV1 |\
- ORxG_SCY_5_CLK |\
- ORxG_SETA)
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/CPU87.h b/include/configs/CPU87.h
deleted file mode 100644
index d3a59e8..0000000
--- a/include/configs/CPU87.h
+++ /dev/null
@@ -1,676 +0,0 @@
-/*
- * (C) Copyright 2001-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_CPU87 1 /* ...on a CPU87 board */
-#define CONFIG_PCI
-#define CONFIG_CPM2 1 /* Has a CPM2 */
-
-#ifdef CONFIG_BOOT_ROM
-#define CONFIG_SYS_TEXT_BASE 0xFF800000
-#else
-#define CONFIG_SYS_TEXT_BASE 0xFF000000
-#endif
-
-/*
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * if CONFIG_CONS_NONE is defined, then the serial console routines must
- * defined elsewhere (for example, on the cogent platform, there are serial
- * ports on the motherboard which are used for the serial console - see
- * cogent/cma101/serial.[ch]).
- */
-#undef CONFIG_CONS_ON_SMC /* define if console on SMC */
-#define CONFIG_CONS_ON_SCC /* define if console on SCC */
-#undef CONFIG_CONS_NONE /* define if console on something else*/
-#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
-
-#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
-#define CONFIG_BAUDRATE 230400
-#else
-#define CONFIG_BAUDRATE 9600
-#endif
-
-/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
- */
-#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
-#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
-#undef CONFIG_ETHER_NONE /* define if ether on something else */
-#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
-
-#define CONFIG_HAS_ETH1 1
-#define CONFIG_HAS_ETH2 1
-
-#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
-
-/*
- * - Rx-CLK is CLK11
- * - Tx-CLK is CLK12
- * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
-# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
-# define CONFIG_SYS_CPMFCR_RAMTYPE 0
-# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
-
-#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
-
-/*
- * - Rx-CLK is CLK13
- * - Tx-CLK is CLK14
- * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
-# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
-# define CONFIG_SYS_CPMFCR_RAMTYPE 0
-# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
-
-#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
-
-/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
-#define CONFIG_8260_CLKIN 100000000 /* in Hz */
-
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#define CONFIG_PREBOOT \
- "echo; " \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS; " \
- "echo"
-
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND \
- "bootp; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
- "bootm"
-
-/*-----------------------------------------------------------------------
- * I2C/EEPROM/RTC configuration
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED 50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
-
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE (iop->pdir |= 0x00010000)
-#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
-#define I2C_READ ((iop->pdat & 0x00010000) != 0)
-#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
- else iop->pdat &= ~0x00010000
-#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
- else iop->pdat &= ~0x00020000
-#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
-
-#define CONFIG_RTC_PCF8563
-#define CONFIG_SYS_I2C_RTC_ADDR 0x51
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*-----------------------------------------------------------------------
- * Disk-On-Chip configuration
- */
-
-#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
-
-#define CONFIG_SYS_DOC_SUPPORT_2000
-#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configuration options
- */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BEDBUG
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
- #define CONFIG_CMD_PCI
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 /* "bad" address */
-
-#define CONFIG_LOOPW
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * Flash configuration
- */
-
-#define CONFIG_SYS_BOOTROM_BASE 0xFF800000
-#define CONFIG_SYS_BOOTROM_SIZE 0x00080000
-#define CONFIG_SYS_FLASH_BASE 0xFF000000
-#define CONFIG_SYS_FLASH_SIZE 0x00800000
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 135 /* max num of sects on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
-
-/*-----------------------------------------------------------------------
- * Other areas to be mapped
- */
-
-/* CS3: Dual ported SRAM */
-#define CONFIG_SYS_DPSRAM_BASE 0x40000000
-#define CONFIG_SYS_DPSRAM_SIZE 0x00100000
-
-/* CS4: DiskOnChip */
-#define CONFIG_SYS_DOC_BASE 0xF4000000
-#define CONFIG_SYS_DOC_SIZE 0x00100000
-
-/* CS5: FDC37C78 controller */
-#define CONFIG_SYS_FDC37C78_BASE 0xF1000000
-#define CONFIG_SYS_FDC37C78_SIZE 0x00100000
-
-/* CS6: Board configuration registers */
-#define CONFIG_SYS_BCRS_BASE 0xF2000000
-#define CONFIG_SYS_BCRS_SIZE 0x00010000
-
-/* CS7: VME Extended Access Range */
-#define CONFIG_SYS_VMEEAR_BASE 0x60000000
-#define CONFIG_SYS_VMEEAR_SIZE 0x01000000
-
-/* CS8: VME Standard Access Range */
-#define CONFIG_SYS_VMESAR_BASE 0xFE000000
-#define CONFIG_SYS_VMESAR_SIZE 0x01000000
-
-/* CS9: VME Short I/O Access Range */
-#define CONFIG_SYS_VMESIOAR_BASE 0xFD000000
-#define CONFIG_SYS_VMESIOAR_SIZE 0x01000000
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
- *
- * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
- * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
- */
-#if defined(CONFIG_BOOT_ROM)
-#define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
- HRCW_BPS01 | HRCW_CS10PC01)
-#else
-#define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | HRCW_CS10PC01)
-#endif
-
-/* no slaves so just fill with zeros */
-#define CONFIG_SYS_HRCW_SLAVE1 0
-#define CONFIG_SYS_HRCW_SLAVE2 0
-#define CONFIG_SYS_HRCW_SLAVE3 0
-#define CONFIG_SYS_HRCW_SLAVE4 0
-#define CONFIG_SYS_HRCW_SLAVE5 0
-#define CONFIG_SYS_HRCW_SLAVE6 0
-#define CONFIG_SYS_HRCW_SLAVE7 0
-
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xF0000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- *
- * 60x SDRAM is mapped@CONFIG_SYS_SDRAM_BASE.
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-# define CONFIG_SYS_RAMBOOT
-#endif
-
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_PNP
-#define CONFIG_EEPRO100
-#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
-#endif
-
-#if 0
-/* environment is in Flash */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#ifdef CONFIG_BOOT_ROM
-# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x70000)
-# define CONFIG_ENV_SIZE 0x10000
-# define CONFIG_ENV_SECT_SIZE 0x10000
-#endif
-#else
-/* environment is in EEPROM */
-#define CONFIG_ENV_IS_IN_EEPROM 1
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 /* EEPROM X24C16 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-/* mask of address bits that overflow into the "EEPROM chip address" */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-#define CONFIG_ENV_OFFSET 512
-#define CONFIG_ENV_SIZE (2048 - 512)
-#endif
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers 2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|\
- HID0_DCI|HID0_IFEM|HID0_ABE)
-#define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE)
-#define CONFIG_SYS_HID2 0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register 5-5
- *-----------------------------------------------------------------------
- * turn on Checkstop Reset Enable
- */
-#define CONFIG_SYS_RMR RMR_CSRE
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration 4-25
- *-----------------------------------------------------------------------
- */
-#define BCR_APD01 0x10000000
-#define CONFIG_SYS_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 4-31
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_SIUMCR (SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\
- SIUMCR_CS10PC01|SIUMCR_BCTLC10)
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 4-35
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
- SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
- SYPCR_SWRI|SYPCR_SWP)
-#endif /* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control 4-40
- *-----------------------------------------------------------------------
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- */
-#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control 9-8
- *-----------------------------------------------------------------------
- * Ensure DFBRG is Divide by 16
- */
-#define CONFIG_SYS_SCCR SCCR_DFBRG01
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration 13-7
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RCCR 0
-
-#define CONFIG_SYS_MIN_AM_MASK 0xC0000000
-
-/*
- * we use the same values for 32 MB, 128 MB and 256 MB SDRAM
- * refresh rate = 7.68 uS (100 MHz Bus Clock)
- */
-
-/*-----------------------------------------------------------------------
- * MPTPR - Memory Refresh Timer Prescaler Register 10-18
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_MPTPR 0x2000
-
-/*-----------------------------------------------------------------------
- * PSRT - Refresh Timer Register 10-16
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_PSRT 0x16
-
-/*-----------------------------------------------------------------------
- * PSRT - SDRAM Mode Register 10-10
- *-----------------------------------------------------------------------
- */
-
- /* SDRAM initialization values for 8-column chips
- */
-#define CONFIG_SYS_OR2_8COL (CONFIG_SYS_MIN_AM_MASK |\
- ORxS_BPD_4 |\
- ORxS_ROWST_PBI0_A9 |\
- ORxS_NUMR_12)
-
-#define CONFIG_SYS_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\
- PSDMR_BSMA_A14_A16 |\
- PSDMR_SDA10_PBI0_A10 |\
- PSDMR_RFRC_7_CLK |\
- PSDMR_PRETOACT_2W |\
- PSDMR_ACTTORW_2W |\
- PSDMR_LDOTOPRE_1C |\
- PSDMR_WRC_1C |\
- PSDMR_CL_2)
-
- /* SDRAM initialization values for 9-column chips
- */
-#define CONFIG_SYS_OR2_9COL (CONFIG_SYS_MIN_AM_MASK |\
- ORxS_BPD_4 |\
- ORxS_ROWST_PBI0_A7 |\
- ORxS_NUMR_13)
-
-#define CONFIG_SYS_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\
- PSDMR_BSMA_A13_A15 |\
- PSDMR_SDA10_PBI0_A9 |\
- PSDMR_RFRC_7_CLK |\
- PSDMR_PRETOACT_2W |\
- PSDMR_ACTTORW_2W |\
- PSDMR_LDOTOPRE_1C |\
- PSDMR_WRC_1C |\
- PSDMR_CL_2)
-
- /* SDRAM initialization values for 10-column chips
- */
-#define CONFIG_SYS_OR2_10COL (CONFIG_SYS_MIN_AM_MASK |\
- ORxS_BPD_4 |\
- ORxS_ROWST_PBI1_A4 |\
- ORxS_NUMR_13)
-
-#define CONFIG_SYS_PSDMR_10COL (PSDMR_PBI |\
- PSDMR_SDAM_A17_IS_A5 |\
- PSDMR_BSMA_A13_A15 |\
- PSDMR_SDA10_PBI1_A6 |\
- PSDMR_RFRC_7_CLK |\
- PSDMR_PRETOACT_2W |\
- PSDMR_ACTTORW_2W |\
- PSDMR_LDOTOPRE_1C |\
- PSDMR_WRC_1C |\
- PSDMR_CL_2)
-
-/*
- * Init Memory Controller:
- *
- * Bank Bus Machine PortSz Device
- * ---- --- ------- ------ ------
- * 0 60x GPCM 8 bit Boot ROM
- * 1 60x GPCM 64 bit FLASH
- * 2 60x SDRAM 64 bit SDRAM
- *
- */
-
-#define CONFIG_SYS_MRS_OFFS 0x00000000
-
-#ifdef CONFIG_BOOT_ROM
-/* Bank 0 - Boot ROM
- */
-#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
- BRx_PS_8 |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE) |\
- ORxG_CSNT |\
- ORxG_ACS_DIV1 |\
- ORxG_SCY_5_CLK |\
- ORxU_EHTR_8IDLE)
-
-/* Bank 1 - FLASH
- */
-#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
- BRx_PS_64 |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
- ORxG_CSNT |\
- ORxG_ACS_DIV1 |\
- ORxG_SCY_5_CLK |\
- ORxU_EHTR_8IDLE)
-
-#else /* CONFIG_BOOT_ROM */
-/* Bank 0 - FLASH
- */
-#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
- BRx_PS_64 |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
- ORxG_CSNT |\
- ORxG_ACS_DIV1 |\
- ORxG_SCY_5_CLK |\
- ORxU_EHTR_8IDLE)
-
-/* Bank 1 - Boot ROM
- */
-#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
- BRx_PS_8 |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE) |\
- ORxG_CSNT |\
- ORxG_ACS_DIV1 |\
- ORxG_SCY_5_CLK |\
- ORxU_EHTR_8IDLE)
-
-#endif /* CONFIG_BOOT_ROM */
-
-
-/* Bank 2 - 60x bus SDRAM
- */
-#ifndef CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
- BRx_PS_64 |\
- BRx_MS_SDRAM_P |\
- BRx_V)
-
-#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_8COL
-
-#define CONFIG_SYS_PSDMR CONFIG_SYS_PSDMR_8COL
-#endif /* CONFIG_SYS_RAMBOOT */
-
-/* Bank 3 - Dual Ported SRAM
- */
-#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_DPSRAM_BASE & BRx_BA_MSK) |\
- BRx_PS_16 |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_DPSRAM_SIZE) |\
- ORxG_CSNT |\
- ORxG_ACS_DIV1 |\
- ORxG_SCY_7_CLK |\
- ORxG_SETA)
-
-/* Bank 4 - DiskOnChip
- */
-#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_DOC_BASE & BRx_BA_MSK) |\
- BRx_PS_8 |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-#define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE) |\
- ORxG_CSNT |\
- ORxG_ACS_DIV2 |\
- ORxG_SCY_9_CLK |\
- ORxU_EHTR_8IDLE)
-
-/* Bank 5 - FDC37C78 controller
- */
-#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_FDC37C78_BASE & BRx_BA_MSK) |\
- BRx_PS_8 |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-#define CONFIG_SYS_OR5_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FDC37C78_SIZE) |\
- ORxG_ACS_DIV2 |\
- ORxG_SCY_10_CLK |\
- ORxU_EHTR_8IDLE)
-
-/* Bank 6 - Board control registers
- */
-#define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_BCRS_BASE & BRx_BA_MSK) |\
- BRx_PS_8 |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-#define CONFIG_SYS_OR6_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCRS_SIZE) |\
- ORxG_CSNT |\
- ORxG_SCY_7_CLK)
-
-/* Bank 7 - VME Extended Access Range
- */
-#define CONFIG_SYS_BR7_PRELIM ((CONFIG_SYS_VMEEAR_BASE & BRx_BA_MSK) |\
- BRx_PS_32 |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-#define CONFIG_SYS_OR7_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VMEEAR_SIZE) |\
- ORxG_CSNT |\
- ORxG_ACS_DIV1 |\
- ORxG_SCY_7_CLK |\
- ORxG_SETA)
-
-/* Bank 8 - VME Standard Access Range
- */
-#define CONFIG_SYS_BR8_PRELIM ((CONFIG_SYS_VMESAR_BASE & BRx_BA_MSK) |\
- BRx_PS_16 |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-#define CONFIG_SYS_OR8_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VMESAR_SIZE) |\
- ORxG_CSNT |\
- ORxG_ACS_DIV1 |\
- ORxG_SCY_7_CLK |\
- ORxG_SETA)
-
-/* Bank 9 - VME Short I/O Access Range
- */
-#define CONFIG_SYS_BR9_PRELIM ((CONFIG_SYS_VMESIOAR_BASE & BRx_BA_MSK) |\
- BRx_PS_16 |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-#define CONFIG_SYS_OR9_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VMESIOAR_SIZE) |\
- ORxG_CSNT |\
- ORxG_ACS_DIV1 |\
- ORxG_SCY_7_CLK |\
- ORxG_SETA)
-
-#endif /* __CONFIG_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [U-Boot] [PATCH 25/26] mpc8260: remove atc board support
2014-12-15 14:26 [U-Boot] [PATCH 0/26] Start removing non-generic boards Masahiro Yamada
` (23 preceding siblings ...)
2014-12-15 14:26 ` [U-Boot] [PATCH 24/26] mpc8260: remove CPU86, CPU87 " Masahiro Yamada
@ 2014-12-15 14:26 ` Masahiro Yamada
2014-12-15 14:26 ` [U-Boot] [PATCH 26/26] powerpc: mpc824x: remove MPC824X cpu support Masahiro Yamada
` (2 subsequent siblings)
27 siblings, 0 replies; 55+ messages in thread
From: Masahiro Yamada @ 2014-12-15 14:26 UTC (permalink / raw)
To: u-boot
These boards are still non-generic boards.
drivers/rtc/ds12887.c should also be removed because it can not
be built without CONFIG_ATC.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
---
arch/powerpc/cpu/mpc8260/Kconfig | 4 -
board/atc/Kconfig | 9 -
board/atc/MAINTAINERS | 6 -
board/atc/Makefile | 8 -
board/atc/atc.c | 382 -----------------------
board/atc/flash.c | 647 ---------------------------------------
board/atc/ti113x.c | 620 -------------------------------------
configs/atc_defconfig | 3 -
doc/README.scrapyard | 1 +
drivers/rtc/Makefile | 1 -
drivers/rtc/ds12887.c | 217 -------------
include/configs/atc.h | 489 -----------------------------
include/pcmcia.h | 2 -
13 files changed, 1 insertion(+), 2388 deletions(-)
delete mode 100644 board/atc/Kconfig
delete mode 100644 board/atc/MAINTAINERS
delete mode 100644 board/atc/Makefile
delete mode 100644 board/atc/atc.c
delete mode 100644 board/atc/flash.c
delete mode 100644 board/atc/ti113x.c
delete mode 100644 configs/atc_defconfig
delete mode 100644 drivers/rtc/ds12887.c
delete mode 100644 include/configs/atc.h
diff --git a/arch/powerpc/cpu/mpc8260/Kconfig b/arch/powerpc/cpu/mpc8260/Kconfig
index eab4514..55941c8 100644
--- a/arch/powerpc/cpu/mpc8260/Kconfig
+++ b/arch/powerpc/cpu/mpc8260/Kconfig
@@ -7,15 +7,11 @@ config SYS_CPU
choice
prompt "Target select"
-config TARGET_ATC
- bool "Support atc"
-
config TARGET_KM82XX
bool "Support km82xx"
endchoice
-source "board/atc/Kconfig"
source "board/keymile/km82xx/Kconfig"
endmenu
diff --git a/board/atc/Kconfig b/board/atc/Kconfig
deleted file mode 100644
index 9b336ca..0000000
--- a/board/atc/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_ATC
-
-config SYS_BOARD
- default "atc"
-
-config SYS_CONFIG_NAME
- default "atc"
-
-endif
diff --git a/board/atc/MAINTAINERS b/board/atc/MAINTAINERS
deleted file mode 100644
index 1c5d61e..0000000
--- a/board/atc/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-ATC BOARD
-M: Wolfgang Denk <wd@denx.de>
-S: Maintained
-F: board/atc/
-F: include/configs/atc.h
-F: configs/atc_defconfig
diff --git a/board/atc/Makefile b/board/atc/Makefile
deleted file mode 100644
index 3a163c4..0000000
--- a/board/atc/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = atc.o flash.o ti113x.o
diff --git a/board/atc/atc.c b/board/atc/atc.c
deleted file mode 100644
index 0038561..0000000
--- a/board/atc/atc.c
+++ /dev/null
@@ -1,382 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc8260.h>
-#include <pci.h>
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
- /* Port A configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
- /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
- /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
- /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
- /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
- /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
- /* PA25 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII MDIO */
- /* PA24 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII MDC */
- /* PA23 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII MDIO */
- /* PA22 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII MDC */
- /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
- /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
- /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
- /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
- /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
- /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */
- /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
- /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
- /* PA13 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII TXSL1 */
- /* PA12 */ { 1, 0, 0, 1, 0, 1 }, /* FCC2 MII TXSL0 */
- /* PA11 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII TXSL1 */
- /* PA10 */ { 1, 0, 0, 1, 0, 1 }, /* FCC1 MII TXSL0 */
-#if 1
- /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
- /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
-#else
- /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
- /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
-#endif
- /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */
- /* PA6 */ { 1, 0, 0, 1, 0, 1 }, /* FCC2 MII PAUSE */
- /* PA5 */ { 1, 0, 0, 1, 0, 1 }, /* FCC1 MII PAUSE */
- /* PA4 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII PWRDN */
- /* PA3 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII PWRDN */
- /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */
- /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FCC2 MII MDINT */
- /* PA0 */ { 1, 0, 0, 1, 0, 0 } /* FCC1 MII MDINT */
- },
-
- /* Port B configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
- /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
- /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
- /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
- /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
- /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
- /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
- /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
- /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
- /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
- /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
- /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
- /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
- /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
- /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_DV */
- /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_ER */
- /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_ER */
- /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_EN */
- /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII COL */
- /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CRS */
- /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD */
- /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD */
- /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD */
- /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD */
- /* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD */
- /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD */
- /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD */
- /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD */
- /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* PB3 */
- /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* PB2 */
- /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* PB1 */
- /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* PB0 */
- },
-
- /* Port C */
- { /* conf ppar psor pdir podr pdat */
- /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
- /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
- /* PC29 */ { 1, 0, 0, 0, 0, 0 }, /* SCC1 CTS */
- /* PC28 */ { 1, 0, 0, 0, 0, 0 }, /* SCC2 CTS */
- /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
- /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
- /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
- /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
- /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DACFD */
- /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DNFD */
- /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */
- /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII TX_CLK */
- /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */
- /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */
- /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_CLK */
- /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII TX_CLK */
-#if 0
- /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
-#else
- /* PC15 */ { 1, 1, 0, 1, 0, 0 }, /* PC15 */
-#endif
- /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
- /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
- /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
- /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
- /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
- /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FC9 */
- /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */
- /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
- /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
- /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
- /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
- /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
- /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
- /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
- /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DRQFD */
- },
-
- /* Port D */
- { /* conf ppar psor pdir podr pdat */
- /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RXD */
- /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TXD */
- /* PD29 */ { 1, 0, 0, 1, 0, 0 }, /* SCC1 RTS */
- /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */
- /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TXD */
- /* PD26 */ { 1, 0, 0, 1, 0, 0 }, /* SCC2 RTS */
- /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */
- /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */
- /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */
- /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */
- /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */
- /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */
- /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */
- /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */
- /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */
- /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */
-#if defined(CONFIG_SYS_I2C_SOFT)
- /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */
- /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */
-#else
-#if defined(CONFIG_HARD_I2C)
- /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
- /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
-#else /* normal I/O port pins */
- /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
- /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
-#endif
-#endif
- /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
- /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
- /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
- /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
- /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
- /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
- /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */
- /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */
- /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */
-#if 0
- /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */
-#else
- /* PD4 */ { 1, 1, 1, 0, 0, 0 }, /* PD4 */
-#endif
- /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* PD3 */
- /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* PD2 */
- /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* PD1 */
- /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* PD0 */
- }
-};
-
-/*
- * UPMB initialization table
- */
-#define _NOT_USED_ 0xFFFFFFFF
-
-static const uint rtc_table[] =
-{
- /*
- * Single Read. (Offset 0 in UPMA RAM)
- */
- 0xfffec00, 0xfffac00, 0xfff2d00, 0xfef2800,
- 0xfaf2080, 0xfaf2080, 0xfff2400, 0x1fff6c05, /* last */
- /*
- * Burst Read. (Offset 8 in UPMA RAM)
- */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Single Write. (Offset 18 in UPMA RAM)
- */
- 0xfffec00, 0xfffac00, 0xfff2d00, 0xfef2800,
- 0xfaf2080, 0xfaf2080, 0xfaf2400, 0x1fbf6c05, /* last */
- /*
- * Burst Write. (Offset 20 in UPMA RAM)
- */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Refresh (Offset 30 in UPMA RAM)
- */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Exception. (Offset 3c in UPMA RAM)
- */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-};
-
-/* ------------------------------------------------------------------------- */
-
-/* Check Board Identity:
- */
-int checkboard (void)
-{
- printf ("Board: ATC\n");
- return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
- *
- * This routine performs standard 8260 initialization sequence
- * and calculates the available memory size. It may be called
- * several times to try different SDRAM configurations on both
- * 60x and local buses.
- */
-static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
- ulong orx, volatile uchar * base)
-{
- volatile uchar c = 0xff;
- volatile uint *sdmr_ptr;
- volatile uint *orx_ptr;
- ulong maxsize, size;
- int i;
-
- /* We must be able to test a location outsize the maximum legal size
- * to find out THAT we are outside; but this address still has to be
- * mapped by the controller. That means, that the initial mapping has
- * to be (at least) twice as large as the maximum expected size.
- */
- maxsize = (1 + (~orx | 0x7fff)) / 2;
-
- /* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that
- * we are configuring CS1 if base != 0
- */
- sdmr_ptr = &memctl->memc_psdmr;
- orx_ptr = &memctl->memc_or2;
-
- *orx_ptr = orx;
-
- /*
- * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
- *
- * "At system reset, initialization software must set up the
- * programmable parameters in the memory controller banks registers
- * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
- * system software should execute the following initialization sequence
- * for each SDRAM device.
- *
- * 1. Issue a PRECHARGE-ALL-BANKS command
- * 2. Issue eight CBR REFRESH commands
- * 3. Issue a MODE-SET command to initialize the mode register
- *
- * The initial commands are executed by setting P/LSDMR[OP] and
- * accessing the SDRAM with a single-byte transaction."
- *
- * The appropriate BRx/ORx registers have already been set when we
- * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
- */
-
- *sdmr_ptr = sdmr | PSDMR_OP_PREA;
- *base = c;
-
- *sdmr_ptr = sdmr | PSDMR_OP_CBRR;
- for (i = 0; i < 8; i++)
- *base = c;
-
- *sdmr_ptr = sdmr | PSDMR_OP_MRW;
- *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */
-
- *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
- *base = c;
-
- size = get_ram_size((long *)base, maxsize);
-
- *orx_ptr = orx | ~(size - 1);
-
- return (size);
-}
-
-int misc_init_r(void)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8260_t *memctl = &immap->im_memctl;
-
- upmconfig(UPMA, (uint *)rtc_table, sizeof(rtc_table) / sizeof(uint));
- memctl->memc_mamr = MxMR_RLFx_6X | MxMR_WLFx_6X | MxMR_OP_NORM;
-
- return (0);
-}
-
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8260_t *memctl = &immap->im_memctl;
-
-#ifndef CONFIG_SYS_RAMBOOT
- ulong size8, size9;
-#endif
- long psize;
-
- psize = 8 * 1024 * 1024;
-
- memctl->memc_mptpr = CONFIG_SYS_MPTPR;
- memctl->memc_psrt = CONFIG_SYS_PSRT;
-
-#ifndef CONFIG_SYS_RAMBOOT
- /* 60x SDRAM setup:
- */
- size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
- (uchar *) CONFIG_SYS_SDRAM_BASE);
- size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL,
- (uchar *) CONFIG_SYS_SDRAM_BASE);
-
- if (size8 < size9) {
- psize = size9;
- printf ("(60x:9COL) ");
- } else {
- psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
- (uchar *) CONFIG_SYS_SDRAM_BASE);
- printf ("(60x:8COL) ");
- }
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
- icache_enable ();
-
- return (psize);
-}
-
-#if defined(CONFIG_CMD_DOC)
-void doc_init (void)
-{
- doc_probe (CONFIG_SYS_DOC_BASE);
-}
-#endif
-
-#ifdef CONFIG_PCI
-struct pci_controller hose;
-
-extern void pci_mpc8250_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
- pci_mpc8250_init(&hose);
-}
-#endif
diff --git a/board/atc/flash.c b/board/atc/flash.c
deleted file mode 100644
index 5a9c510..0000000
--- a/board/atc/flash.c
+++ /dev/null
@@ -1,647 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
- * has nothing to do with the flash chip being 8-bit or 16-bit.
- */
-#ifdef CONFIG_FLASH_16BIT
-typedef unsigned short FLASH_PORT_WIDTH;
-typedef volatile unsigned short FLASH_PORT_WIDTHV;
-#define FLASH_ID_MASK 0xFFFF
-#else
-typedef unsigned long FLASH_PORT_WIDTH;
-typedef volatile unsigned long FLASH_PORT_WIDTHV;
-#define FLASH_ID_MASK 0xFFFFFFFF
-#endif
-
-#define FPW FLASH_PORT_WIDTH
-#define FPWV FLASH_PORT_WIDTHV
-
-#define ORMASK(size) ((-size) & OR_AM_MSK)
-
-#define FLASH_CYCLE1 0x0555
-#define FLASH_CYCLE2 0x02aa
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size(FPWV *addr, flash_info_t *info);
-static void flash_reset(flash_info_t *info);
-static int write_word_intel(flash_info_t *info, FPWV *dest, FPW data);
-static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
-static void flash_get_offsets(ulong base, flash_info_t *info);
-static flash_info_t *flash_get_info(ulong base);
-
-/*-----------------------------------------------------------------------
- * flash_init()
- *
- * sets up flash_info and returns size of FLASH (bytes)
- */
-unsigned long flash_init (void)
-{
- unsigned long size = 0;
- int i;
-
- /* Init: no FLASHes known */
- for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
-#if 0
- ulong flashbase = (i == 0) ? PHYS_FLASH_1 : PHYS_FLASH_2;
-#else
- ulong flashbase = CONFIG_SYS_FLASH_BASE;
-#endif
-
- memset(&flash_info[i], 0, sizeof(flash_info_t));
-
- flash_info[i].size =
- flash_get_size((FPW *)flashbase, &flash_info[i]);
-
- if (flash_info[i].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx\n",
- i, flash_info[i].size);
- }
-
- size += flash_info[i].size;
- }
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- flash_get_info(CONFIG_SYS_MONITOR_BASE));
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
- flash_get_info(CONFIG_ENV_ADDR));
-#endif
-
-
- return size ? size : 1;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_reset(flash_info_t *info)
-{
- FPWV *base = (FPWV *)(info->start[0]);
-
- /* Put FLASH back in read mode */
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
- *base = (FPW)0x00FF00FF; /* Intel Read Mode */
- else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
- *base = (FPW)0x00F000F0; /* AMD Read Mode */
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
- int i;
-
- /* set up sector start address table */
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL
- && (info->flash_id & FLASH_BTYPE)) {
- int bootsect_size; /* number of bytes/boot sector */
- int sect_size; /* number of bytes/regular sector */
-
- bootsect_size = 0x00002000 * (sizeof(FPW)/2);
- sect_size = 0x00010000 * (sizeof(FPW)/2);
-
- /* set sector offsets for bottom boot block type */
- for (i = 0; i < 8; ++i) {
- info->start[i] = base + (i * bootsect_size);
- }
- for (i = 8; i < info->sector_count; i++) {
- info->start[i] = base + ((i - 7) * sect_size);
- }
- }
- else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD
- && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) {
-
- int sect_size; /* number of bytes/sector */
-
- sect_size = 0x00010000 * (sizeof(FPW)/2);
-
- /* set up sector start address table (uniform sector type) */
- for( i = 0; i < info->sector_count; i++ )
- info->start[i] = base + (i * sect_size);
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-
-static flash_info_t *flash_get_info(ulong base)
-{
- int i;
- flash_info_t * info;
-
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) {
- info = & flash_info[i];
- if (info->start[0] <= base && base < info->start[0] + info->size)
- break;
- }
-
- return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-void flash_print_info (flash_info_t *info)
-{
- int i;
- uchar *boottype;
- uchar *bootletter;
- char *fmt;
- uchar botbootletter[] = "B";
- uchar topbootletter[] = "T";
- uchar botboottype[] = "bottom boot sector";
- uchar topboottype[] = "top boot sector";
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break;
- case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
- case FLASH_MAN_SST: printf ("SST "); break;
- case FLASH_MAN_STM: printf ("STM "); break;
- case FLASH_MAN_INTEL: printf ("INTEL "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- /* check for top or bottom boot, if it applies */
- if (info->flash_id & FLASH_BTYPE) {
- boottype = botboottype;
- bootletter = botbootletter;
- }
- else {
- boottype = topboottype;
- bootletter = topbootletter;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM640U:
- fmt = "29LV641D (64 Mbit, uniform sectors)\n";
- break;
- case FLASH_28F800C3B:
- case FLASH_28F800C3T:
- fmt = "28F800C3%s (8 Mbit, %s)\n";
- break;
- case FLASH_INTEL800B:
- case FLASH_INTEL800T:
- fmt = "28F800B3%s (8 Mbit, %s)\n";
- break;
- case FLASH_28F160C3B:
- case FLASH_28F160C3T:
- fmt = "28F160C3%s (16 Mbit, %s)\n";
- break;
- case FLASH_INTEL160B:
- case FLASH_INTEL160T:
- fmt = "28F160B3%s (16 Mbit, %s)\n";
- break;
- case FLASH_28F320C3B:
- case FLASH_28F320C3T:
- fmt = "28F320C3%s (32 Mbit, %s)\n";
- break;
- case FLASH_INTEL320B:
- case FLASH_INTEL320T:
- fmt = "28F320B3%s (32 Mbit, %s)\n";
- break;
- case FLASH_28F640C3B:
- case FLASH_28F640C3T:
- fmt = "28F640C3%s (64 Mbit, %s)\n";
- break;
- case FLASH_INTEL640B:
- case FLASH_INTEL640T:
- fmt = "28F640B3%s (64 Mbit, %s)\n";
- break;
- default:
- fmt = "Unknown Chip Type\n";
- break;
- }
-
- printf (fmt, bootletter, boottype);
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20,
- info->sector_count);
-
- printf (" Sector Start Addresses:");
-
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0) {
- printf ("\n ");
- }
-
- printf (" %08lX%s", info->start[i],
- info->protect[i] ? " (RO)" : " ");
- }
-
- printf ("\n");
-}
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-ulong flash_get_size (FPWV *addr, flash_info_t *info)
-{
- /* Write auto select command: read Manufacturer ID */
-
- /* Write auto select command sequence and test FLASH answer */
- addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */
- addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */
- addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */
-
- /* The manufacturer codes are only 1 byte, so just use 1 byte.
- * This works for any bus width and any FLASH device width.
- */
- udelay(100);
- switch (addr[0] & 0xff) {
-
- case (uchar)AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
-
- case (uchar)INTEL_MANUFACT:
- info->flash_id = FLASH_MAN_INTEL;
- break;
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- break;
- }
-
- /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
- if (info->flash_id != FLASH_UNKNOWN) switch (addr[1]) {
-
- case (FPW)AMD_ID_LV640U: /* 29LV640 and 29LV641 have same ID */
- info->flash_id += FLASH_AM640U;
- info->sector_count = 128;
- info->size = 0x00800000 * (sizeof(FPW)/2);
- break; /* => 8 or 16 MB */
-
- case (FPW)INTEL_ID_28F800C3B:
- info->flash_id += FLASH_28F800C3B;
- info->sector_count = 23;
- info->size = 0x00100000 * (sizeof(FPW)/2);
- break; /* => 1 or 2 MB */
-
- case (FPW)INTEL_ID_28F800B3B:
- info->flash_id += FLASH_INTEL800B;
- info->sector_count = 23;
- info->size = 0x00100000 * (sizeof(FPW)/2);
- break; /* => 1 or 2 MB */
-
- case (FPW)INTEL_ID_28F160C3B:
- info->flash_id += FLASH_28F160C3B;
- info->sector_count = 39;
- info->size = 0x00200000 * (sizeof(FPW)/2);
- break; /* => 2 or 4 MB */
-
- case (FPW)INTEL_ID_28F160B3B:
- info->flash_id += FLASH_INTEL160B;
- info->sector_count = 39;
- info->size = 0x00200000 * (sizeof(FPW)/2);
- break; /* => 2 or 4 MB */
-
- case (FPW)INTEL_ID_28F320C3B:
- info->flash_id += FLASH_28F320C3B;
- info->sector_count = 71;
- info->size = 0x00400000 * (sizeof(FPW)/2);
- break; /* => 4 or 8 MB */
-
- case (FPW)INTEL_ID_28F320B3B:
- info->flash_id += FLASH_INTEL320B;
- info->sector_count = 71;
- info->size = 0x00400000 * (sizeof(FPW)/2);
- break; /* => 4 or 8 MB */
-
- case (FPW)INTEL_ID_28F640C3B:
- info->flash_id += FLASH_28F640C3B;
- info->sector_count = 135;
- info->size = 0x00800000 * (sizeof(FPW)/2);
- break; /* => 8 or 16 MB */
-
- case (FPW)INTEL_ID_28F640B3B:
- info->flash_id += FLASH_INTEL640B;
- info->sector_count = 135;
- info->size = 0x00800000 * (sizeof(FPW)/2);
- break; /* => 8 or 16 MB */
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* => no or unknown flash */
- }
-
- flash_get_offsets((ulong)addr, info);
-
- /* Put FLASH back in read mode */
- flash_reset(info);
-
- return (info->size);
-}
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- FPWV *addr;
- int flag, prot, sect;
- int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
- ulong start, now, last;
- int rcode = 0;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_INTEL800B:
- case FLASH_INTEL160B:
- case FLASH_INTEL320B:
- case FLASH_INTEL640B:
- case FLASH_28F800C3B:
- case FLASH_28F160C3B:
- case FLASH_28F320C3B:
- case FLASH_28F640C3B:
- case FLASH_AM640U:
- break;
- case FLASH_UNKNOWN:
- default:
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- last = get_timer(0);
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last && rcode == 0; sect++) {
-
- if (info->protect[sect] != 0) /* protected, skip it */
- continue;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr = (FPWV *)(info->start[sect]);
- if (intel) {
- *addr = (FPW)0x00500050; /* clear status register */
- *addr = (FPW)0x00200020; /* erase setup */
- *addr = (FPW)0x00D000D0; /* erase confirm */
- }
- else {
- /* must be AMD style if not Intel */
- FPWV *base; /* first address in bank */
-
- base = (FPWV *)(info->start[0]);
- base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
- base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
- base[FLASH_CYCLE1] = (FPW)0x00800080; /* erase mode */
- base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
- base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
- *addr = (FPW)0x00300030; /* erase sector */
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- start = get_timer(0);
-
- /* wait at least 50us for AMD, 80us for Intel.
- * Let's wait 1 ms.
- */
- udelay (1000);
-
- while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
-
- if (intel) {
- /* suspend erase */
- *addr = (FPW)0x00B000B0;
- }
-
- flash_reset(info); /* reset to read mode */
- rcode = 1; /* failed */
- break;
- }
-
- /* show that we're waiting */
- if ((get_timer(last)) > CONFIG_SYS_HZ) {/* every second */
- putc ('.');
- last = get_timer(0);
- }
- }
-
- /* show that we're waiting */
- if ((get_timer(last)) > CONFIG_SYS_HZ) { /* every second */
- putc ('.');
- last = get_timer(0);
- }
-
- flash_reset(info); /* reset to read mode */
- }
-
- printf (" done\n");
- return rcode;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
- int bytes; /* number of bytes to program in current word */
- int left; /* number of bytes left to program */
- int i, res;
-
- for (left = cnt, res = 0;
- left > 0 && res == 0;
- addr += sizeof(data), left -= sizeof(data) - bytes) {
-
- bytes = addr & (sizeof(data) - 1);
- addr &= ~(sizeof(data) - 1);
-
- /* combine source and destination data so can program
- * an entire word of 16 or 32 bits
- */
- for (i = 0; i < sizeof(data); i++) {
- data <<= 8;
- if (i < bytes || i - bytes >= left )
- data += *((uchar *)addr + i);
- else
- data += *src++;
- }
-
- /* write one word to the flash */
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD:
- res = write_word_amd(info, (FPWV *)addr, data);
- break;
- case FLASH_MAN_INTEL:
- res = write_word_intel(info, (FPWV *)addr, data);
- break;
- default:
- /* unknown flash type, error! */
- printf ("missing or unknown FLASH type\n");
- res = 1; /* not really a timeout, but gives error */
- break;
- }
- }
-
- return (res);
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash for AMD FLASH
- * A word is 16 or 32 bits, whichever the bus width of the flash bank
- * (not an individual chip) is.
- *
- * returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
-{
- ulong start;
- int flag;
- int res = 0; /* result, assume success */
- FPWV *base; /* first address in flash bank */
-
- /* Check if Flash is (sufficiently) erased */
- if ((*dest & data) != data) {
- return (2);
- }
-
-
- base = (FPWV *)(info->start[0]);
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
- base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
- base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */
-
- *dest = data; /* start programming the data */
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- start = get_timer (0);
-
- /* data polling for D7 */
- while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- *dest = (FPW)0x00F000F0; /* reset bank */
- res = 1;
- }
- }
-
- return (res);
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash for Intel FLASH
- * A word is 16 or 32 bits, whichever the bus width of the flash bank
- * (not an individual chip) is.
- *
- * returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data)
-{
- ulong start;
- int flag;
- int res = 0; /* result, assume success */
-
- /* Check if Flash is (sufficiently) erased */
- if ((*dest & data) != data) {
- return (2);
- }
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- *dest = (FPW)0x00500050; /* clear status register */
- *dest = (FPW)0x00FF00FF; /* make sure in read mode */
- *dest = (FPW)0x00400040; /* program setup */
-
- *dest = data; /* start programming the data */
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- start = get_timer (0);
-
- while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- *dest = (FPW)0x00B000B0; /* Suspend program */
- res = 1;
- }
- }
-
- if (res == 0 && (*dest & (FPW)0x00100010))
- res = 1; /* write failed, time out error is close enough */
-
- *dest = (FPW)0x00500050; /* clear status register */
- *dest = (FPW)0x00FF00FF; /* make sure in read mode */
-
- return (res);
-}
diff --git a/board/atc/ti113x.c b/board/atc/ti113x.c
deleted file mode 100644
index c7c502c..0000000
--- a/board/atc/ti113x.c
+++ /dev/null
@@ -1,620 +0,0 @@
-/*
- * (C) Copyright 2003-2005
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- ********************************************************************
- *
- * Lots of code copied from:
- *
- * i82365.c 1.352 - Linux driver for Intel 82365 and compatible
- * PC Card controllers, and Yenta-compatible PCI-to-CardBus controllers.
- * (C) 1999 David A. Hinds <dahinds@users.sourceforge.net>
- */
-
-#include <common.h>
-
-#ifdef CONFIG_I82365
-
-#include <command.h>
-#include <pci.h>
-#include <pcmcia.h>
-#include <asm/io.h>
-
-#include <pcmcia/ss.h>
-#include <pcmcia/i82365.h>
-#include <pcmcia/yenta.h>
-#include <pcmcia/ti113x.h>
-
-static struct pci_device_id supported[] = {
- {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1510},
- {0, 0}
-};
-
-#define CYCLE_TIME 120
-
-#ifdef DEBUG
-static void i82365_dump_regions (pci_dev_t dev);
-#endif
-
-typedef struct socket_info_t {
- pci_dev_t dev;
- u_short bcr;
- u_char pci_lat, cb_lat, sub_bus, cache;
- u_int cb_phys;
-
- socket_cap_t cap;
- u_short type;
- u_int flags;
- ti113x_state_t state;
-} socket_info_t;
-
-static socket_info_t socket;
-static socket_state_t state;
-static struct pccard_mem_map mem;
-static struct pccard_io_map io;
-
-/*====================================================================*/
-
-/* Some PCI shortcuts */
-
-static int pci_readb (socket_info_t * s, int r, u_char * v)
-{
- return pci_read_config_byte (s->dev, r, v);
-}
-static int pci_writeb (socket_info_t * s, int r, u_char v)
-{
- return pci_write_config_byte (s->dev, r, v);
-}
-static int pci_readw (socket_info_t * s, int r, u_short * v)
-{
- return pci_read_config_word (s->dev, r, v);
-}
-static int pci_writew (socket_info_t * s, int r, u_short v)
-{
- return pci_write_config_word (s->dev, r, v);
-}
-static int pci_readl (socket_info_t * s, int r, u_int * v)
-{
- return pci_read_config_dword (s->dev, r, v);
-}
-static int pci_writel (socket_info_t * s, int r, u_int v)
-{
- return pci_write_config_dword (s->dev, r, v);
-}
-
-/*====================================================================*/
-
-#define cb_readb(s, r) readb((s)->cb_phys + (r))
-#define cb_readl(s, r) readl((s)->cb_phys + (r))
-#define cb_writeb(s, r, v) writeb(v, (s)->cb_phys + (r))
-#define cb_writel(s, r, v) writel(v, (s)->cb_phys + (r))
-
-static u_char i365_get (socket_info_t * s, u_short reg)
-{
- return cb_readb (s, 0x0800 + reg);
-}
-
-static void i365_set (socket_info_t * s, u_short reg, u_char data)
-{
- cb_writeb (s, 0x0800 + reg, data);
-}
-
-static void i365_bset (socket_info_t * s, u_short reg, u_char mask)
-{
- i365_set (s, reg, i365_get (s, reg) | mask);
-}
-
-static void i365_bclr (socket_info_t * s, u_short reg, u_char mask)
-{
- i365_set (s, reg, i365_get (s, reg) & ~mask);
-}
-
-#if 0 /* not used */
-static void i365_bflip (socket_info_t * s, u_short reg, u_char mask, int b)
-{
- u_char d = i365_get (s, reg);
-
- i365_set (s, reg, (b) ? (d | mask) : (d & ~mask));
-}
-
-static u_short i365_get_pair (socket_info_t * s, u_short reg)
-{
- return (i365_get (s, reg) + (i365_get (s, reg + 1) << 8));
-}
-#endif /* not used */
-
-static void i365_set_pair (socket_info_t * s, u_short reg, u_short data)
-{
- i365_set (s, reg, data & 0xff);
- i365_set (s, reg + 1, data >> 8);
-}
-
-/*======================================================================
-
- Code to save and restore global state information for TI 1130 and
- TI 1131 controllers, and to set and report global configuration
- options.
-
-======================================================================*/
-
-static void ti113x_get_state (socket_info_t * s)
-{
- ti113x_state_t *p = &s->state;
-
- pci_readl (s, TI113X_SYSTEM_CONTROL, &p->sysctl);
- pci_readb (s, TI113X_CARD_CONTROL, &p->cardctl);
- pci_readb (s, TI113X_DEVICE_CONTROL, &p->devctl);
- pci_readb (s, TI1250_DIAGNOSTIC, &p->diag);
- pci_readl (s, TI12XX_IRQMUX, &p->irqmux);
-}
-
-static void ti113x_set_state (socket_info_t * s)
-{
- ti113x_state_t *p = &s->state;
-
- pci_writel (s, TI113X_SYSTEM_CONTROL, p->sysctl);
- pci_writeb (s, TI113X_CARD_CONTROL, p->cardctl);
- pci_writeb (s, TI113X_DEVICE_CONTROL, p->devctl);
- pci_writeb (s, TI1250_MULTIMEDIA_CTL, 0);
- pci_writeb (s, TI1250_DIAGNOSTIC, p->diag);
- pci_writel (s, TI12XX_IRQMUX, p->irqmux);
- i365_set_pair (s, TI113X_IO_OFFSET (0), 0);
- i365_set_pair (s, TI113X_IO_OFFSET (1), 0);
-}
-
-static u_int ti113x_set_opts (socket_info_t * s)
-{
- ti113x_state_t *p = &s->state;
- u_int mask = 0xffff;
-
- p->cardctl &= ~TI113X_CCR_ZVENABLE;
- p->cardctl |= TI113X_CCR_SPKROUTEN;
-
- return mask;
-}
-
-/*======================================================================
-
- Routines to handle common CardBus options
-
-======================================================================*/
-
-/* Default settings for PCI command configuration register */
-#define CMD_DFLT (PCI_COMMAND_IO|PCI_COMMAND_MEMORY| \
- PCI_COMMAND_MASTER|PCI_COMMAND_WAIT)
-
-static void cb_get_state (socket_info_t * s)
-{
- pci_readb (s, PCI_CACHE_LINE_SIZE, &s->cache);
- pci_readb (s, PCI_LATENCY_TIMER, &s->pci_lat);
- pci_readb (s, CB_LATENCY_TIMER, &s->cb_lat);
- pci_readb (s, CB_CARDBUS_BUS, &s->cap.cardbus);
- pci_readb (s, CB_SUBORD_BUS, &s->sub_bus);
- pci_readw (s, CB_BRIDGE_CONTROL, &s->bcr);
-}
-
-static void cb_set_state (socket_info_t * s)
-{
- pci_writel (s, CB_LEGACY_MODE_BASE, 0);
- pci_writel (s, PCI_BASE_ADDRESS_0, s->cb_phys);
- pci_writew (s, PCI_COMMAND, CMD_DFLT);
- pci_writeb (s, PCI_CACHE_LINE_SIZE, s->cache);
- pci_writeb (s, PCI_LATENCY_TIMER, s->pci_lat);
- pci_writeb (s, CB_LATENCY_TIMER, s->cb_lat);
- pci_writeb (s, CB_CARDBUS_BUS, s->cap.cardbus);
- pci_writeb (s, CB_SUBORD_BUS, s->sub_bus);
- pci_writew (s, CB_BRIDGE_CONTROL, s->bcr);
-}
-
-static void cb_set_opts (socket_info_t * s)
-{
- if (s->cache == 0)
- s->cache = 8;
- if (s->pci_lat == 0)
- s->pci_lat = 0xa8;
- if (s->cb_lat == 0)
- s->cb_lat = 0xb0;
-}
-
-/*======================================================================
-
- Power control for Cardbus controllers: used both for 16-bit and
- Cardbus cards.
-
-======================================================================*/
-
-static int cb_set_power (socket_info_t * s, socket_state_t * state)
-{
- u_int reg = 0;
-
- /* restart card voltage detection if it seems appropriate */
- if ((state->Vcc == 0) && (state->Vpp == 0) &&
- !(cb_readl (s, CB_SOCKET_STATE) & CB_SS_VSENSE))
- cb_writel (s, CB_SOCKET_FORCE, CB_SF_CVSTEST);
- switch (state->Vcc) {
- case 0:
- reg = 0;
- break;
- case 33:
- reg = CB_SC_VCC_3V;
- break;
- case 50:
- reg = CB_SC_VCC_5V;
- break;
- default:
- return -1;
- }
- switch (state->Vpp) {
- case 0:
- break;
- case 33:
- reg |= CB_SC_VPP_3V;
- break;
- case 50:
- reg |= CB_SC_VPP_5V;
- break;
- case 120:
- reg |= CB_SC_VPP_12V;
- break;
- default:
- return -1;
- }
- if (reg != cb_readl (s, CB_SOCKET_CONTROL))
- cb_writel (s, CB_SOCKET_CONTROL, reg);
-
- return 0;
-}
-
-/*======================================================================
-
- Generic routines to get and set controller options
-
-======================================================================*/
-
-static void get_bridge_state (socket_info_t * s)
-{
- ti113x_get_state (s);
- cb_get_state (s);
-}
-
-static void set_bridge_state (socket_info_t * s)
-{
- cb_set_state (s);
- i365_set (s, I365_GBLCTL, 0x00);
- i365_set (s, I365_GENCTL, 0x00);
- ti113x_set_state (s);
-}
-
-static void set_bridge_opts (socket_info_t * s)
-{
- ti113x_set_opts (s);
- cb_set_opts (s);
-}
-
-/*====================================================================*/
-#define PD67_EXT_INDEX 0x2e /* Extension index */
-#define PD67_EXT_DATA 0x2f /* Extension data */
-#define PD67_EXD_VS1(s) (0x01 << ((s)<<1))
-
-#define pd67_ext_get(s, r) \
- (i365_set(s, PD67_EXT_INDEX, r), i365_get(s, PD67_EXT_DATA))
-
-static int i365_get_status (socket_info_t * s, u_int * value)
-{
- u_int status;
-
- status = i365_get (s, I365_IDENT);
- status = i365_get (s, I365_STATUS);
- *value = ((status & I365_CS_DETECT) == I365_CS_DETECT) ? SS_DETECT : 0;
- if (i365_get (s, I365_INTCTL) & I365_PC_IOCARD) {
- *value |= (status & I365_CS_STSCHG) ? 0 : SS_STSCHG;
- } else {
- *value |= (status & I365_CS_BVD1) ? 0 : SS_BATDEAD;
- *value |= (status & I365_CS_BVD2) ? 0 : SS_BATWARN;
- }
- *value |= (status & I365_CS_WRPROT) ? SS_WRPROT : 0;
- *value |= (status & I365_CS_READY) ? SS_READY : 0;
- *value |= (status & I365_CS_POWERON) ? SS_POWERON : 0;
-
- status = cb_readl (s, CB_SOCKET_STATE);
- *value |= (status & CB_SS_32BIT) ? SS_CARDBUS : 0;
- *value |= (status & CB_SS_3VCARD) ? SS_3VCARD : 0;
- *value |= (status & CB_SS_XVCARD) ? SS_XVCARD : 0;
- *value |= (status & CB_SS_VSENSE) ? 0 : SS_PENDING;
- /* For now, ignore cards with unsupported voltage keys */
- if (*value & SS_XVCARD)
- *value &= ~(SS_DETECT | SS_3VCARD | SS_XVCARD);
-
- return 0;
-} /* i365_get_status */
-
-static int i365_set_socket (socket_info_t * s, socket_state_t * state)
-{
- u_char reg;
-
- set_bridge_state (s);
-
- /* IO card, RESET flag */
- reg = 0;
- reg |= (state->flags & SS_RESET) ? 0 : I365_PC_RESET;
- reg |= (state->flags & SS_IOCARD) ? I365_PC_IOCARD : 0;
- i365_set (s, I365_INTCTL, reg);
-
- reg = I365_PWR_NORESET;
- if (state->flags & SS_PWR_AUTO)
- reg |= I365_PWR_AUTO;
- if (state->flags & SS_OUTPUT_ENA)
- reg |= I365_PWR_OUT;
-
- cb_set_power (s, state);
- reg |= i365_get (s, I365_POWER) & (I365_VCC_MASK | I365_VPP1_MASK);
-
- if (reg != i365_get (s, I365_POWER))
- i365_set (s, I365_POWER, reg);
-
- return 0;
-} /* i365_set_socket */
-
-/*====================================================================*/
-
-static int i365_set_mem_map (socket_info_t * s, struct pccard_mem_map *mem)
-{
- u_short base, i;
- u_char map;
-
- debug ("i82365: SetMemMap(%d, %#2.2x, %d ns, %#5.5lx-%#5.5lx, %#5.5x)\n",
- mem->map, mem->flags, mem->speed,
- mem->sys_start, mem->sys_stop, mem->card_start);
-
- map = mem->map;
- if ((map > 4) ||
- (mem->card_start > 0x3ffffff) ||
- (mem->sys_start > mem->sys_stop) ||
- (mem->speed > 1000)) {
- return -1;
- }
-
- /* Turn off the window before changing anything */
- if (i365_get (s, I365_ADDRWIN) & I365_ENA_MEM (map))
- i365_bclr (s, I365_ADDRWIN, I365_ENA_MEM (map));
-
- /* Take care of high byte, for PCI controllers */
- i365_set (s, CB_MEM_PAGE (map), mem->sys_start >> 24);
-
- base = I365_MEM (map);
- i = (mem->sys_start >> 12) & 0x0fff;
- if (mem->flags & MAP_16BIT)
- i |= I365_MEM_16BIT;
- if (mem->flags & MAP_0WS)
- i |= I365_MEM_0WS;
- i365_set_pair (s, base + I365_W_START, i);
-
- i = (mem->sys_stop >> 12) & 0x0fff;
- switch (mem->speed / CYCLE_TIME) {
- case 0:
- break;
- case 1:
- i |= I365_MEM_WS0;
- break;
- case 2:
- i |= I365_MEM_WS1;
- break;
- default:
- i |= I365_MEM_WS1 | I365_MEM_WS0;
- break;
- }
- i365_set_pair (s, base + I365_W_STOP, i);
-
- i = ((mem->card_start - mem->sys_start) >> 12) & 0x3fff;
- if (mem->flags & MAP_WRPROT)
- i |= I365_MEM_WRPROT;
- if (mem->flags & MAP_ATTRIB)
- i |= I365_MEM_REG;
- i365_set_pair (s, base + I365_W_OFF, i);
-
- /* Turn on the window if necessary */
- if (mem->flags & MAP_ACTIVE)
- i365_bset (s, I365_ADDRWIN, I365_ENA_MEM (map));
- return 0;
-} /* i365_set_mem_map */
-
-static int i365_set_io_map (socket_info_t * s, struct pccard_io_map *io)
-{
- u_char map, ioctl;
-
- map = io->map;
- /* comment out: comparison is always false due to limited range of data type */
- if ((map > 1) || /* (io->start > 0xffff) || (io->stop > 0xffff) || */
- (io->stop < io->start))
- return -1;
- /* Turn off the window before changing anything */
- if (i365_get (s, I365_ADDRWIN) & I365_ENA_IO (map))
- i365_bclr (s, I365_ADDRWIN, I365_ENA_IO (map));
- i365_set_pair (s, I365_IO (map) + I365_W_START, io->start);
- i365_set_pair (s, I365_IO (map) + I365_W_STOP, io->stop);
- ioctl = i365_get (s, I365_IOCTL) & ~I365_IOCTL_MASK (map);
- if (io->speed)
- ioctl |= I365_IOCTL_WAIT (map);
- if (io->flags & MAP_0WS)
- ioctl |= I365_IOCTL_0WS (map);
- if (io->flags & MAP_16BIT)
- ioctl |= I365_IOCTL_16BIT (map);
- if (io->flags & MAP_AUTOSZ)
- ioctl |= I365_IOCTL_IOCS16 (map);
- i365_set (s, I365_IOCTL, ioctl);
- /* Turn on the window if necessary */
- if (io->flags & MAP_ACTIVE)
- i365_bset (s, I365_ADDRWIN, I365_ENA_IO (map));
- return 0;
-} /* i365_set_io_map */
-
-/*====================================================================*/
-
-static int i82365_init (void)
-{
- u_int val;
- int i;
-
- if ((socket.dev = pci_find_devices (supported, 0)) < 0) {
- /* Controller not found */
- return 1;
- }
- debug ("i82365 Device Found!\n");
-
- pci_read_config_dword (socket.dev, PCI_BASE_ADDRESS_0, &socket.cb_phys);
- socket.cb_phys &= ~0xf;
-
- get_bridge_state (&socket);
- set_bridge_opts (&socket);
-
- i = i365_get_status (&socket, &val);
-
- if (val & SS_DETECT) {
- if (val & SS_3VCARD) {
- state.Vcc = state.Vpp = 33;
- puts (" 3.3V card found: ");
- } else if (!(val & SS_XVCARD)) {
- state.Vcc = state.Vpp = 50;
- puts (" 5.0V card found: ");
- } else {
- puts ("i82365: unsupported voltage key\n");
- state.Vcc = state.Vpp = 0;
- }
- } else {
- /* No card inserted */
- puts ("No card\n");
- return 1;
- }
-
- state.flags = SS_IOCARD | SS_OUTPUT_ENA;
- state.csc_mask = 0;
- state.io_irq = 0;
-
- i365_set_socket (&socket, &state);
-
- for (i = 500; i; i--) {
- if ((i365_get (&socket, I365_STATUS) & I365_CS_READY))
- break;
- udelay (1000);
- }
-
- if (i == 0) {
- /* PC Card not ready for data transfer */
- puts ("i82365 PC Card not ready for data transfer\n");
- return 1;
- }
- debug (" PC Card ready for data transfer: ");
-
- mem.map = 0;
- mem.flags = MAP_ATTRIB | MAP_ACTIVE;
- mem.speed = 300;
- mem.sys_start = CONFIG_SYS_PCMCIA_MEM_ADDR;
- mem.sys_stop = CONFIG_SYS_PCMCIA_MEM_ADDR + CONFIG_SYS_PCMCIA_MEM_SIZE - 1;
- mem.card_start = 0;
- i365_set_mem_map (&socket, &mem);
-
- io.map = 0;
- io.flags = MAP_AUTOSZ | MAP_ACTIVE;
- io.speed = 0;
- io.start = 0x0100;
- io.stop = 0x010F;
- i365_set_io_map (&socket, &io);
-
-#ifdef DEBUG
- i82365_dump_regions (socket.dev);
-#endif
-
- return 0;
-}
-
-static void i82365_exit (void)
-{
- io.map = 0;
- io.flags = 0;
- io.speed = 0;
- io.start = 0;
- io.stop = 0x1;
-
- i365_set_io_map (&socket, &io);
-
- mem.map = 0;
- mem.flags = 0;
- mem.speed = 0;
- mem.sys_start = 0;
- mem.sys_stop = 0x1000;
- mem.card_start = 0;
-
- i365_set_mem_map (&socket, &mem);
-
- socket.state.sysctl &= 0xFFFF00FF;
-
- state.Vcc = state.Vpp = 0;
-
- i365_set_socket (&socket, &state);
-}
-
-int pcmcia_on (void)
-{
- u_int rc;
-
- debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n");
-
- rc = i82365_init();
- if (rc)
- goto exit;
-
- rc = check_ide_device(0);
- if (rc == 0)
- goto exit;
-
- i82365_exit();
-
-exit:
- return rc;
-}
-
-#if defined(CONFIG_CMD_PCMCIA)
-int pcmcia_off (void)
-{
- printf ("Disable PCMCIA " PCMCIA_SLOT_MSG "\n");
-
- i82365_exit();
-
- return 0;
-}
-#endif
-
-/*======================================================================
-
- Debug stuff
-
-======================================================================*/
-
-#ifdef DEBUG
-static void i82365_dump_regions (pci_dev_t dev)
-{
- u_int tmp[2];
- u_int *mem = (void *) socket.cb_phys;
- u_char *cis = (void *) CONFIG_SYS_PCMCIA_MEM_ADDR;
- u_char *ide = (void *) (CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_REG_OFFSET);
-
- pci_read_config_dword (dev, 0x00, tmp + 0);
- pci_read_config_dword (dev, 0x80, tmp + 1);
-
- printf ("PCI CONF: %08X ... %08X\n",
- tmp[0], tmp[1]);
- printf ("PCI MEM: ... %08X ... %08X\n",
- mem[0x8 / 4], mem[0x800 / 4]);
- printf ("CIS: ...%c%c%c%c%c%c%c%c...\n",
- cis[0x38], cis[0x3a], cis[0x3c], cis[0x3e],
- cis[0x40], cis[0x42], cis[0x44], cis[0x48]);
- printf ("CIS CONF: %02X %02X %02X ...\n",
- cis[0x200], cis[0x202], cis[0x204]);
- printf ("IDE: %02X %02X %02X %02X %02X %02X %02X %02X\n",
- ide[0], ide[1], ide[2], ide[3],
- ide[4], ide[5], ide[6], ide[7]);
-}
-#endif /* DEBUG */
-
-#endif /* CONFIG_I82365 */
diff --git a/configs/atc_defconfig b/configs/atc_defconfig
deleted file mode 100644
index 967be47..0000000
--- a/configs/atc_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_ATC=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index c0d0cd9..5df0664 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+atc powerpc mpc8260 - - Wolfgang Denk <wd@denx.de>
CPU86 powerpc mpc8260 - - Wolfgang Denk <wd@denx.de>
CPU87 powerpc mpc8260 - -
ep82xxm powerpc mpc8260 - -
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 43f8546..fdcbc00 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -11,7 +11,6 @@ obj-$(CONFIG_RTC_AT91SAM9_RTT) += at91sam9_rtt.o
obj-$(CONFIG_RTC_BFIN) += bfin_rtc.o
obj-y += date.o
obj-$(CONFIG_RTC_DAVINCI) += davinci.o
-obj-$(CONFIG_RTC_DS12887) += ds12887.o
obj-$(CONFIG_RTC_DS1302) += ds1302.o
obj-$(CONFIG_RTC_DS1306) += ds1306.o
obj-$(CONFIG_RTC_DS1307) += ds1307.o
diff --git a/drivers/rtc/ds12887.c b/drivers/rtc/ds12887.c
deleted file mode 100644
index d8a519b..0000000
--- a/drivers/rtc/ds12887.c
+++ /dev/null
@@ -1,217 +0,0 @@
-/*
- * (C) Copyright 2003
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Date & Time support for the DS12887 RTC
- */
-
-#undef RTC_DEBUG
-
-#include <common.h>
-#include <command.h>
-#include <config.h>
-#include <rtc.h>
-
-#if defined(CONFIG_CMD_DATE)
-
-#define RTC_SECONDS 0x00
-#define RTC_SECONDS_ALARM 0x01
-#define RTC_MINUTES 0x02
-#define RTC_MINUTES_ALARM 0x03
-#define RTC_HOURS 0x04
-#define RTC_HOURS_ALARM 0x05
-#define RTC_DAY_OF_WEEK 0x06
-#define RTC_DATE_OF_MONTH 0x07
-#define RTC_MONTH 0x08
-#define RTC_YEAR 0x09
-#define RTC_CONTROL_A 0x0A
-#define RTC_CONTROL_B 0x0B
-#define RTC_CONTROL_C 0x0C
-#define RTC_CONTROL_D 0x0D
-
-#define RTC_CA_UIP 0x80
-#define RTC_CB_DM 0x04
-#define RTC_CB_24_12 0x02
-#define RTC_CB_SET 0x80
-
-#if defined(CONFIG_ATC)
-
-static uchar rtc_read (uchar reg)
-{
- uchar val;
-
- *(volatile unsigned char*)(RTC_PORT_ADDR) = reg;
- __asm__ __volatile__ ("sync");
-
- val = *(volatile unsigned char*)(RTC_PORT_DATA);
- return (val);
-}
-
-static void rtc_write (uchar reg, uchar val)
-{
- *(volatile unsigned char*)(RTC_PORT_ADDR) = reg;
- __asm__ __volatile__ ("sync");
-
- *(volatile unsigned char*)(RTC_PORT_DATA) = val;
- __asm__ __volatile__ ("sync");
-}
-
-#else
-# error Board specific rtc access functions should be supplied
-#endif
-
-int rtc_get (struct rtc_time *tmp)
-{
- uchar sec, min, hour, mday, wday, mon, year;
-
- /* check if rtc is available for access */
- while( rtc_read(RTC_CONTROL_A) & RTC_CA_UIP)
- ;
-
- sec = rtc_read(RTC_SECONDS);
- min = rtc_read(RTC_MINUTES);
- hour = rtc_read(RTC_HOURS);
- mday = rtc_read(RTC_DATE_OF_MONTH);
- wday = rtc_read(RTC_DAY_OF_WEEK);
- mon = rtc_read(RTC_MONTH);
- year = rtc_read(RTC_YEAR);
-
-#ifdef RTC_DEBUG
- printf( "Get RTC year: %d; mon: %d; mday: %d; wday: %d; "
- "hr: %d; min: %d; sec: %d\n",
- year, mon, mday, wday, hour, min, sec );
-
- printf ( "Alarms: hour: %02x min: %02x sec: %02x\n",
- rtc_read (RTC_HOURS_ALARM),
- rtc_read (RTC_MINUTES_ALARM),
- rtc_read (RTC_SECONDS_ALARM) );
-#endif
-
- if( !(rtc_read(RTC_CONTROL_B) & RTC_CB_DM))
- { /* Information is in BCD format */
-printf(" Get: Convert BSD to BIN\n");
- tmp->tm_sec = bcd2bin (sec & 0x7F);
- tmp->tm_min = bcd2bin (min & 0x7F);
- tmp->tm_hour = bcd2bin (hour & 0x3F);
- tmp->tm_mday = bcd2bin (mday & 0x3F);
- tmp->tm_mon = bcd2bin (mon & 0x1F);
- tmp->tm_year = bcd2bin (year);
- tmp->tm_wday = bcd2bin (wday & 0x07);
- }
-else
- {
- tmp->tm_sec = sec & 0x7F;
- tmp->tm_min = min & 0x7F;
- tmp->tm_hour = hour & 0x3F;
- tmp->tm_mday = mday & 0x3F;
- tmp->tm_mon = mon & 0x1F;
- tmp->tm_year = year;
- tmp->tm_wday = wday & 0x07;
- }
-
-
- if(tmp->tm_year<70)
- tmp->tm_year+=2000;
- else
- tmp->tm_year+=1900;
-
- tmp->tm_yday = 0;
- tmp->tm_isdst= 0;
-#ifdef RTC_DEBUG
- printf ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
- tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
- tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
-#endif
-
- return 0;
-}
-
-int rtc_set (struct rtc_time *tmp)
-{
- uchar save_ctrl_b;
- uchar sec, min, hour, mday, wday, mon, year;
-
-#ifdef RTC_DEBUG
- printf ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
- tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
- tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
-#endif
-
- if( !(rtc_read(RTC_CONTROL_B) & RTC_CB_DM))
- { /* Information is in BCD format */
- year = bin2bcd(tmp->tm_year % 100);
- mon = bin2bcd(tmp->tm_mon);
- wday = bin2bcd(tmp->tm_wday);
- mday = bin2bcd(tmp->tm_mday);
- hour = bin2bcd(tmp->tm_hour);
- min = bin2bcd(tmp->tm_min);
- sec = bin2bcd(tmp->tm_sec);
- }
- else
- {
- year = tmp->tm_year % 100;
- mon = tmp->tm_mon;
- wday = tmp->tm_wday;
- mday = tmp->tm_mday;
- hour = tmp->tm_hour;
- min = tmp->tm_min;
- sec = tmp->tm_sec;
- }
-
- /* disables the RTC to update the regs */
- save_ctrl_b = rtc_read(RTC_CONTROL_B);
- save_ctrl_b |= RTC_CB_SET;
- rtc_write(RTC_CONTROL_B, save_ctrl_b);
-
- rtc_write (RTC_YEAR, year);
- rtc_write (RTC_MONTH, mon);
- rtc_write (RTC_DAY_OF_WEEK, wday);
- rtc_write (RTC_DATE_OF_MONTH, mday);
- rtc_write (RTC_HOURS, hour);
- rtc_write (RTC_MINUTES, min);
- rtc_write (RTC_SECONDS, sec);
-
- /* enables the RTC to update the regs */
- save_ctrl_b &= ~RTC_CB_SET;
- rtc_write(RTC_CONTROL_B, save_ctrl_b);
-
- return 0;
-}
-
-void rtc_reset (void)
-{
- struct rtc_time tmp;
- uchar ctrl_rg;
-
- ctrl_rg = RTC_CB_SET;
- rtc_write(RTC_CONTROL_B,ctrl_rg);
-
- tmp.tm_year = 1970 % 100;
- tmp.tm_mon = 1;
- tmp.tm_mday= 1;
- tmp.tm_hour = 0;
- tmp.tm_min = 0;
- tmp.tm_sec = 0;
-
-#ifdef RTC_DEBUG
- printf ( "RTC: %4d-%02d-%02d %2d:%02d:%02d UTC\n",
- tmp.tm_year, tmp.tm_mon, tmp.tm_mday,
- tmp.tm_hour, tmp.tm_min, tmp.tm_sec);
-#endif
-
- ctrl_rg = RTC_CB_SET | RTC_CB_24_12 | RTC_CB_DM;
- rtc_write(RTC_CONTROL_B,ctrl_rg);
- rtc_set(&tmp);
-
- rtc_write(RTC_HOURS_ALARM, 0),
- rtc_write(RTC_MINUTES_ALARM, 0),
- rtc_write(RTC_SECONDS_ALARM, 0);
-
- ctrl_rg = RTC_CB_24_12 | RTC_CB_DM;
- rtc_write(RTC_CONTROL_B,ctrl_rg);
-}
-
-#endif
diff --git a/include/configs/atc.h b/include/configs/atc.h
deleted file mode 100644
index 77fa79a..0000000
--- a/include/configs/atc.h
+++ /dev/null
@@ -1,489 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_ATC 1 /* ...on a ATC board */
-#define CONFIG_CPM2 1 /* Has a CPM2 */
-
-#define CONFIG_SYS_TEXT_BASE 0xFF000000
-
-/*
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * if CONFIG_CONS_NONE is defined, then the serial console routines must
- * defined elsewhere (for example, on the cogent platform, there are serial
- * ports on the motherboard which are used for the serial console - see
- * cogent/cma101/serial.[ch]).
- */
-#define CONFIG_CONS_ON_SMC /* define if console on SMC */
-#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
-#undef CONFIG_CONS_NONE /* define if console on something else*/
-#define CONFIG_CONS_INDEX 2 /* which serial channel for console */
-
-#define CONFIG_BAUDRATE 115200
-
-/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
- */
-#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
-#undef CONFIG_ETHER_NONE /* define if ether on something else */
-#define CONFIG_ETHER_ON_FCC
-
-#define CONFIG_ETHER_ON_FCC2
-
-/*
- * - Rx-CLK is CLK13
- * - Tx-CLK is CLK14
- * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
-# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
-# define CONFIG_SYS_CPMFCR_RAMTYPE 0
-# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
-
-#define CONFIG_ETHER_ON_FCC3
-
-/*
- * - Rx-CLK is CLK15
- * - Tx-CLK is CLK16
- * - RAM for BD/Buffers is on the local Bus (see 28-13)
- * - Enable Half Duplex in FSMR
- */
-# define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
-# define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
-
-/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
-#define CONFIG_8260_CLKIN 64000000 /* in Hz */
-
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in Hz */
-
-#define CONFIG_PREBOOT \
- "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;"\
- "echo"
-
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND \
- "bootp;" \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"\
- "bootm"
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configuration options
- */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PCMCIA
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_IDE
-
-
-#define CONFIG_DOS_PARTITION
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
-
-#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 /* "bad" address */
-
-#define CONFIG_SYS_ALLOC_DPRAM
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_SPI
-
-#define CONFIG_RTC_DS12887
-
-#define RTC_BASE_ADDR 0xF5000000
-#define RTC_PORT_ADDR RTC_BASE_ADDR + 0x800
-#define RTC_PORT_DATA RTC_BASE_ADDR + 0x808
-
-#define CONFIG_MISC_INIT_R
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * Flash configuration
- */
-
-#define CONFIG_SYS_FLASH_BASE 0xFF000000
-#define CONFIG_SYS_FLASH_SIZE 0x00800000
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
-
-#define CONFIG_FLASH_16BIT
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
- *
- * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
- * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
- */
-#define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
- HRCW_BPS10 |\
- HRCW_APPC10)
-
-/* no slaves so just fill with zeros */
-#define CONFIG_SYS_HRCW_SLAVE1 0
-#define CONFIG_SYS_HRCW_SLAVE2 0
-#define CONFIG_SYS_HRCW_SLAVE3 0
-#define CONFIG_SYS_HRCW_SLAVE4 0
-#define CONFIG_SYS_HRCW_SLAVE5 0
-#define CONFIG_SYS_HRCW_SLAVE6 0
-#define CONFIG_SYS_HRCW_SLAVE7 0
-
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xF0000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- *
- * 60x SDRAM is mapped@CONFIG_SYS_SDRAM_BASE.
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-# define CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_PCI_PNP
-#define CONFIG_SYS_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */
-
-#if 1
-/* environment is in Flash */
-#define CONFIG_ENV_IS_IN_FLASH 1
-# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x30000)
-# define CONFIG_ENV_SIZE 0x10000
-# define CONFIG_ENV_SECT_SIZE 0x10000
-#else
-#define CONFIG_ENV_IS_IN_EEPROM 1
-#define CONFIG_ENV_OFFSET 0
-#define CONFIG_ENV_SIZE 2048
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */
-#endif
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers 2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|\
- HID0_DCI|HID0_IFEM|HID0_ABE)
-#define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE)
-#define CONFIG_SYS_HID2 0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register 5-5
- *-----------------------------------------------------------------------
- * turn on Checkstop Reset Enable
- */
-#define CONFIG_SYS_RMR RMR_CSRE
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration 4-25
- *-----------------------------------------------------------------------
- */
-#define BCR_APD01 0x10000000
-#define CONFIG_SYS_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 4-31
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_SIUMCR (SIUMCR_BBD|SIUMCR_APPC10|\
- SIUMCR_CS10PC00|SIUMCR_BCTLC10)
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 4-35
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
- SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
- SYPCR_SWRI|SYPCR_SWP)
-#endif /* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control 4-40
- *-----------------------------------------------------------------------
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- */
-#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control 9-8
- *-----------------------------------------------------------------------
- * Ensure DFBRG is Divide by 16
- */
-#define CONFIG_SYS_SCCR SCCR_DFBRG01
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration 13-7
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RCCR 0
-
-#define CONFIG_SYS_MIN_AM_MASK 0xC0000000
-/*-----------------------------------------------------------------------
- * MPTPR - Memory Refresh Timer Prescaler Register 10-18
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_MPTPR 0x1F00
-
-/*-----------------------------------------------------------------------
- * PSRT - Refresh Timer Register 10-16
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_PSRT 0x0f
-
-/*-----------------------------------------------------------------------
- * PSRT - SDRAM Mode Register 10-10
- *-----------------------------------------------------------------------
- */
-
- /* SDRAM initialization values for 8-column chips
- */
-#define CONFIG_SYS_OR2_8COL (CONFIG_SYS_MIN_AM_MASK |\
- ORxS_BPD_4 |\
- ORxS_ROWST_PBI1_A7 |\
- ORxS_NUMR_12)
-
-#define CONFIG_SYS_PSDMR_8COL (PSDMR_PBI |\
- PSDMR_SDAM_A15_IS_A5 |\
- PSDMR_BSMA_A15_A17 |\
- PSDMR_SDA10_PBI1_A7 |\
- PSDMR_RFRC_7_CLK |\
- PSDMR_PRETOACT_3W |\
- PSDMR_ACTTORW_2W |\
- PSDMR_LDOTOPRE_1C |\
- PSDMR_WRC_1C |\
- PSDMR_CL_2)
-
- /* SDRAM initialization values for 9-column chips
- */
-#define CONFIG_SYS_OR2_9COL (CONFIG_SYS_MIN_AM_MASK |\
- ORxS_BPD_4 |\
- ORxS_ROWST_PBI1_A6 |\
- ORxS_NUMR_12)
-
-#define CONFIG_SYS_PSDMR_9COL (PSDMR_PBI |\
- PSDMR_SDAM_A16_IS_A5 |\
- PSDMR_BSMA_A15_A17 |\
- PSDMR_SDA10_PBI1_A6 |\
- PSDMR_RFRC_7_CLK |\
- PSDMR_PRETOACT_3W |\
- PSDMR_ACTTORW_2W |\
- PSDMR_LDOTOPRE_1C |\
- PSDMR_WRC_1C |\
- PSDMR_CL_2)
-
-/*
- * Init Memory Controller:
- *
- * Bank Bus Machine PortSz Device
- * ---- --- ------- ------ ------
- * 0 60x GPCM 8 bit Boot ROM
- * 1 60x GPCM 64 bit FLASH
- * 2 60x SDRAM 64 bit SDRAM
- *
- */
-
-#define CONFIG_SYS_MRS_OFFS 0x00000000
-
-/* Bank 0 - FLASH
- */
-#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
- BRx_PS_16 |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
- ORxG_CSNT |\
- ORxG_ACS_DIV1 |\
- ORxG_SCY_3_CLK |\
- ORxU_EHTR_8IDLE)
-
-
-/* Bank 2 - 60x bus SDRAM
- */
-#ifndef CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
- BRx_PS_64 |\
- BRx_MS_SDRAM_P |\
- BRx_V)
-
-#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_8COL
-
-#define CONFIG_SYS_PSDMR CONFIG_SYS_PSDMR_8COL
-#endif /* CONFIG_SYS_RAMBOOT */
-
-#define CONFIG_SYS_BR4_PRELIM ((RTC_BASE_ADDR & BRx_BA_MSK) |\
- BRx_PS_8 |\
- BRx_MS_UPMA |\
- BRx_V)
-
-#define CONFIG_SYS_OR4_PRELIM (ORxU_AM_MSK | ORxU_BI)
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_I82365
-
-#define CONFIG_SYS_PCMCIA_MEM_ADDR 0x81000000
-#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x1000
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
- *-----------------------------------------------------------------------
- */
-
-#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
-#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
-
-#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
-#undef CONFIG_IDE_LED /* LED for ide not supported */
-#undef CONFIG_IDE_RESET /* reset for ide not supported */
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR 0xa0000000
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET 0x100
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET 0x100
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x108
-
-#endif /* __CONFIG_H */
diff --git a/include/pcmcia.h b/include/pcmcia.h
index 8e8831f..c8a730c 100644
--- a/include/pcmcia.h
+++ b/include/pcmcia.h
@@ -23,8 +23,6 @@
#if defined(CONFIG_TQM8xxL)
# define CONFIG_PCMCIA_SLOT_B /* The TQM8xxL use SLOT_B */
-#elif defined(CONFIG_ATC) /* The ATC use SLOT_A */
-# define CONFIG_PCMCIA_SLOT_A
#else
# error "PCMCIA Slot not configured"
#endif
--
1.9.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [U-Boot] [PATCH 26/26] powerpc: mpc824x: remove MPC824X cpu support
2014-12-15 14:26 [U-Boot] [PATCH 0/26] Start removing non-generic boards Masahiro Yamada
` (24 preceding siblings ...)
2014-12-15 14:26 ` [U-Boot] [PATCH 25/26] mpc8260: remove atc " Masahiro Yamada
@ 2014-12-15 14:26 ` Masahiro Yamada
2014-12-15 16:46 ` York Sun
2015-01-05 18:22 ` Tom Rini
2015-01-05 15:44 ` [U-Boot] [PATCH 0/26] Start removing non-generic boards Masahiro YAMADA
2015-01-05 18:28 ` Tom Rini
27 siblings, 2 replies; 55+ messages in thread
From: Masahiro Yamada @ 2014-12-15 14:26 UTC (permalink / raw)
To: u-boot
All the MPC824X boards are still non-generic boards:
A3000, CPC45, CU824, eXalion, MVBLUE, MUSENKI, Sandpoint824x, utx8245
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Josef Wagner <Wagner@Microsys.de>
Cc: Torsten Demke <torsten.demke@fci.com>
Cc: Jim Thompson <jim@musenki.com>
Cc: Greg Allen <gallen@arlut.utexas.edu>
---
MAKEALL | 6 -
README | 5 -
arch/powerpc/Kconfig | 4 -
arch/powerpc/cpu/mpc824x/Kconfig | 48 --
arch/powerpc/cpu/mpc824x/Makefile | 11 -
arch/powerpc/cpu/mpc824x/config.mk | 8 -
arch/powerpc/cpu/mpc824x/cpu.c | 262 ------
arch/powerpc/cpu/mpc824x/cpu_init.c | 311 -------
arch/powerpc/cpu/mpc824x/drivers/epic.h | 1 -
arch/powerpc/cpu/mpc824x/drivers/epic/README | 102 ---
arch/powerpc/cpu/mpc824x/drivers/epic/epic.h | 163 ----
arch/powerpc/cpu/mpc824x/drivers/epic/epic1.c | 517 ------------
arch/powerpc/cpu/mpc824x/drivers/epic/epic2.S | 196 -----
arch/powerpc/cpu/mpc824x/drivers/epic/epicutil.S | 57 --
arch/powerpc/cpu/mpc824x/drivers/errors.h | 212 -----
arch/powerpc/cpu/mpc824x/drivers/i2c/i2c.c | 254 ------
arch/powerpc/cpu/mpc824x/interrupts.c | 77 --
arch/powerpc/cpu/mpc824x/pci.c | 75 --
arch/powerpc/cpu/mpc824x/speed.c | 102 ---
arch/powerpc/cpu/mpc824x/start.S | 724 -----------------
arch/powerpc/cpu/mpc824x/traps.c | 194 -----
arch/powerpc/cpu/mpc824x/u-boot.lds | 76 --
arch/powerpc/include/asm/processor.h | 2 -
board/a3000/Kconfig | 9 -
board/a3000/MAINTAINERS | 6 -
board/a3000/Makefile | 8 -
board/a3000/README | 17 -
board/a3000/a3000.c | 101 ---
board/a3000/flash.c | 438 ----------
board/cpc45/Kconfig | 9 -
board/cpc45/MAINTAINERS | 7 -
board/cpc45/Makefile | 8 -
board/cpc45/cpc45.c | 250 ------
board/cpc45/flash.c | 506 ------------
board/cpc45/ide.c | 128 ---
board/cpc45/pd67290.c | 797 ------------------
board/cpc45/plx9030.c | 156 ----
board/cu824/Kconfig | 9 -
board/cu824/MAINTAINERS | 6 -
board/cu824/Makefile | 8 -
board/cu824/README | 453 -----------
board/cu824/cu824.c | 83 --
board/cu824/flash.c | 470 -----------
board/eXalion/Kconfig | 9 -
board/eXalion/MAINTAINERS | 6 -
board/eXalion/Makefile | 8 -
board/eXalion/eXalion.c | 283 -------
board/eXalion/eXalion.h | 36 -
board/eXalion/piix_pci.h | 156 ----
board/musenki/Kconfig | 9 -
board/musenki/MAINTAINERS | 6 -
board/musenki/Makefile | 8 -
board/musenki/README | 298 -------
board/musenki/flash.c | 496 ------------
board/musenki/musenki.c | 94 ---
board/mvblue/Kconfig | 9 -
board/mvblue/MAINTAINERS | 6 -
board/mvblue/Makefile | 8 -
board/mvblue/flash.c | 570 -------------
board/mvblue/mvblue.c | 253 ------
board/mvblue/u-boot.lds | 86 --
board/sandpoint/Kconfig | 19 -
board/sandpoint/MAINTAINERS | 12 -
board/sandpoint/Makefile | 8 -
board/sandpoint/README | 411 ----------
board/sandpoint/dinkdl | 2 -
board/sandpoint/flash.c | 748 -----------------
board/sandpoint/sandpoint.c | 91 ---
board/sandpoint/u-boot.lds | 84 --
board/utx8245/Kconfig | 9 -
board/utx8245/MAINTAINERS | 6 -
board/utx8245/Makefile | 13 -
board/utx8245/flash.c | 544 -------------
board/utx8245/utx8245.c | 119 ---
common/cmd_pcmcia.c | 3 -
configs/A3000_defconfig | 3 -
configs/CPC45_ROMBOOT_defconfig | 4 -
configs/CPC45_defconfig | 3 -
configs/CU824_defconfig | 3 -
configs/MUSENKI_defconfig | 3 -
configs/MVBLUE_defconfig | 3 -
configs/Sandpoint8240_defconfig | 3 -
configs/Sandpoint8245_defconfig | 3 -
configs/eXalion_defconfig | 3 -
configs/utx8245_defconfig | 3 -
doc/README.scrapyard | 9 +
drivers/pcmcia/Makefile | 1 -
drivers/pcmcia/i82365.c | 989 -----------------------
include/configs/A3000.h | 293 -------
include/configs/CPC45.h | 489 -----------
include/configs/CU824.h | 286 -------
include/configs/MUSENKI.h | 275 -------
include/configs/MVBLUE.h | 325 --------
include/configs/Sandpoint8240.h | 398 ---------
include/configs/Sandpoint8245.h | 376 ---------
include/configs/eXalion.h | 433 ----------
include/configs/utx8245.h | 408 ----------
include/mpc824x.h | 523 ------------
include/pci.h | 4 -
include/pcmcia/cirrus.h | 180 -----
include/pcmcia/i82365.h | 154 ----
include/pcmcia/ss.h | 133 ---
include/pcmcia/ti113x.h | 234 ------
include/ppc_asm.tmpl | 4 +-
post/drivers/memory.c | 2 +-
105 files changed, 12 insertions(+), 16821 deletions(-)
delete mode 100644 arch/powerpc/cpu/mpc824x/Kconfig
delete mode 100644 arch/powerpc/cpu/mpc824x/Makefile
delete mode 100644 arch/powerpc/cpu/mpc824x/config.mk
delete mode 100644 arch/powerpc/cpu/mpc824x/cpu.c
delete mode 100644 arch/powerpc/cpu/mpc824x/cpu_init.c
delete mode 100644 arch/powerpc/cpu/mpc824x/drivers/epic.h
delete mode 100644 arch/powerpc/cpu/mpc824x/drivers/epic/README
delete mode 100644 arch/powerpc/cpu/mpc824x/drivers/epic/epic.h
delete mode 100644 arch/powerpc/cpu/mpc824x/drivers/epic/epic1.c
delete mode 100644 arch/powerpc/cpu/mpc824x/drivers/epic/epic2.S
delete mode 100644 arch/powerpc/cpu/mpc824x/drivers/epic/epicutil.S
delete mode 100644 arch/powerpc/cpu/mpc824x/drivers/errors.h
delete mode 100644 arch/powerpc/cpu/mpc824x/drivers/i2c/i2c.c
delete mode 100644 arch/powerpc/cpu/mpc824x/interrupts.c
delete mode 100644 arch/powerpc/cpu/mpc824x/pci.c
delete mode 100644 arch/powerpc/cpu/mpc824x/speed.c
delete mode 100644 arch/powerpc/cpu/mpc824x/start.S
delete mode 100644 arch/powerpc/cpu/mpc824x/traps.c
delete mode 100644 arch/powerpc/cpu/mpc824x/u-boot.lds
delete mode 100644 board/a3000/Kconfig
delete mode 100644 board/a3000/MAINTAINERS
delete mode 100644 board/a3000/Makefile
delete mode 100644 board/a3000/README
delete mode 100644 board/a3000/a3000.c
delete mode 100644 board/a3000/flash.c
delete mode 100644 board/cpc45/Kconfig
delete mode 100644 board/cpc45/MAINTAINERS
delete mode 100644 board/cpc45/Makefile
delete mode 100644 board/cpc45/cpc45.c
delete mode 100644 board/cpc45/flash.c
delete mode 100644 board/cpc45/ide.c
delete mode 100644 board/cpc45/pd67290.c
delete mode 100644 board/cpc45/plx9030.c
delete mode 100644 board/cu824/Kconfig
delete mode 100644 board/cu824/MAINTAINERS
delete mode 100644 board/cu824/Makefile
delete mode 100644 board/cu824/README
delete mode 100644 board/cu824/cu824.c
delete mode 100644 board/cu824/flash.c
delete mode 100644 board/eXalion/Kconfig
delete mode 100644 board/eXalion/MAINTAINERS
delete mode 100644 board/eXalion/Makefile
delete mode 100644 board/eXalion/eXalion.c
delete mode 100644 board/eXalion/eXalion.h
delete mode 100644 board/eXalion/piix_pci.h
delete mode 100644 board/musenki/Kconfig
delete mode 100644 board/musenki/MAINTAINERS
delete mode 100644 board/musenki/Makefile
delete mode 100644 board/musenki/README
delete mode 100644 board/musenki/flash.c
delete mode 100644 board/musenki/musenki.c
delete mode 100644 board/mvblue/Kconfig
delete mode 100644 board/mvblue/MAINTAINERS
delete mode 100644 board/mvblue/Makefile
delete mode 100644 board/mvblue/flash.c
delete mode 100644 board/mvblue/mvblue.c
delete mode 100644 board/mvblue/u-boot.lds
delete mode 100644 board/sandpoint/Kconfig
delete mode 100644 board/sandpoint/MAINTAINERS
delete mode 100644 board/sandpoint/Makefile
delete mode 100644 board/sandpoint/README
delete mode 100644 board/sandpoint/dinkdl
delete mode 100644 board/sandpoint/flash.c
delete mode 100644 board/sandpoint/sandpoint.c
delete mode 100644 board/sandpoint/u-boot.lds
delete mode 100644 board/utx8245/Kconfig
delete mode 100644 board/utx8245/MAINTAINERS
delete mode 100644 board/utx8245/Makefile
delete mode 100644 board/utx8245/flash.c
delete mode 100644 board/utx8245/utx8245.c
delete mode 100644 configs/A3000_defconfig
delete mode 100644 configs/CPC45_ROMBOOT_defconfig
delete mode 100644 configs/CPC45_defconfig
delete mode 100644 configs/CU824_defconfig
delete mode 100644 configs/MUSENKI_defconfig
delete mode 100644 configs/MVBLUE_defconfig
delete mode 100644 configs/Sandpoint8240_defconfig
delete mode 100644 configs/Sandpoint8245_defconfig
delete mode 100644 configs/eXalion_defconfig
delete mode 100644 configs/utx8245_defconfig
delete mode 100644 drivers/pcmcia/i82365.c
delete mode 100644 include/configs/A3000.h
delete mode 100644 include/configs/CPC45.h
delete mode 100644 include/configs/CU824.h
delete mode 100644 include/configs/MUSENKI.h
delete mode 100644 include/configs/MVBLUE.h
delete mode 100644 include/configs/Sandpoint8240.h
delete mode 100644 include/configs/Sandpoint8245.h
delete mode 100644 include/configs/eXalion.h
delete mode 100644 include/configs/utx8245.h
delete mode 100644 include/mpc824x.h
delete mode 100644 include/pcmcia/cirrus.h
delete mode 100644 include/pcmcia/i82365.h
delete mode 100644 include/pcmcia/ss.h
delete mode 100644 include/pcmcia/ti113x.h
diff --git a/MAKEALL b/MAKEALL
index 4822054..208232e 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -292,12 +292,6 @@ LIST_8xx="$(targets_by_cpu mpc8xx)"
LIST_4xx="$(targets_by_cpu ppc4xx)"
#########################################################################
-## MPC824x Systems
-#########################################################################
-
-LIST_824x="$(targets_by_cpu mpc824x)"
-
-#########################################################################
## MPC8260 Systems (includes 8250, 8255 etc.)
#########################################################################
diff --git a/README b/README
index 4ca04d0..43aa3af 100644
--- a/README
+++ b/README
@@ -186,7 +186,6 @@ Directory Hierarchy:
/mpc5xx Files specific to Freescale MPC5xx CPUs
/mpc5xxx Files specific to Freescale MPC5xxx CPUs
/mpc8xx Files specific to Freescale MPC8xx CPUs
- /mpc824x Files specific to Freescale MPC824x CPUs
/mpc8260 Files specific to Freescale MPC8260 CPUs
/mpc85xx Files specific to Freescale MPC85xx CPUs
/ppc4xx Files specific to AMCC PowerPC 4xx CPUs
@@ -326,10 +325,6 @@ The following options need to be configured:
multiple fs option at one time
for marvell soc family
-- MPC824X Family Member (if CONFIG_MPC824X is defined)
- Define exactly one of
- CONFIG_MPC8240, CONFIG_MPC8245
-
- 8xx CPU Options: (if using an MPC8xx CPU)
CONFIG_8xx_GCLK_FREQ - deprecated: CPU clock if
get_gclk_freq() cannot work
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 6f96c7c..7a50301 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -19,9 +19,6 @@ config 5xx
config MPC5xxx
bool "MPC5xxx"
-config MPC824X
- bool "MPC824X"
-
config MPC8260
bool "MPC8260"
@@ -46,7 +43,6 @@ source "arch/powerpc/cpu/74xx_7xx/Kconfig"
source "arch/powerpc/cpu/mpc512x/Kconfig"
source "arch/powerpc/cpu/mpc5xx/Kconfig"
source "arch/powerpc/cpu/mpc5xxx/Kconfig"
-source "arch/powerpc/cpu/mpc824x/Kconfig"
source "arch/powerpc/cpu/mpc8260/Kconfig"
source "arch/powerpc/cpu/mpc83xx/Kconfig"
source "arch/powerpc/cpu/mpc85xx/Kconfig"
diff --git a/arch/powerpc/cpu/mpc824x/Kconfig b/arch/powerpc/cpu/mpc824x/Kconfig
deleted file mode 100644
index 4f98423..0000000
--- a/arch/powerpc/cpu/mpc824x/Kconfig
+++ /dev/null
@@ -1,48 +0,0 @@
-menu "mpc824x CPU"
- depends on MPC824X
-
-config SYS_CPU
- default "mpc824x"
-
-choice
- prompt "Target select"
-
-config TARGET_A3000
- bool "Support A3000"
-
-config TARGET_CPC45
- bool "Support CPC45"
-
-config TARGET_CU824
- bool "Support CU824"
-
-config TARGET_EXALION
- bool "Support eXalion"
-
-config TARGET_MUSENKI
- bool "Support MUSENKI"
-
-config TARGET_MVBLUE
- bool "Support MVBLUE"
-
-config TARGET_SANDPOINT8240
- bool "Support Sandpoint8240"
-
-config TARGET_SANDPOINT8245
- bool "Support Sandpoint8245"
-
-config TARGET_UTX8245
- bool "Support utx8245"
-
-endchoice
-
-source "board/a3000/Kconfig"
-source "board/cpc45/Kconfig"
-source "board/cu824/Kconfig"
-source "board/eXalion/Kconfig"
-source "board/musenki/Kconfig"
-source "board/mvblue/Kconfig"
-source "board/sandpoint/Kconfig"
-source "board/utx8245/Kconfig"
-
-endmenu
diff --git a/arch/powerpc/cpu/mpc824x/Makefile b/arch/powerpc/cpu/mpc824x/Makefile
deleted file mode 100644
index 2c8be92..0000000
--- a/arch/powerpc/cpu/mpc824x/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-extra-y = start.o
-obj-y = traps.o cpu.o cpu_init.o interrupts.o speed.o \
- drivers/epic/epic1.o drivers/i2c/i2c.o pci.o
-obj-y += ../mpc8260/bedbug_603e.o
diff --git a/arch/powerpc/cpu/mpc824x/config.mk b/arch/powerpc/cpu/mpc824x/config.mk
deleted file mode 100644
index ecfb07e..0000000
--- a/arch/powerpc/cpu/mpc824x/config.mk
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2010
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -mstring -mcpu=603e -msoft-float
diff --git a/arch/powerpc/cpu/mpc824x/cpu.c b/arch/powerpc/cpu/mpc824x/cpu.c
deleted file mode 100644
index eaa4e87..0000000
--- a/arch/powerpc/cpu/mpc824x/cpu.c
+++ /dev/null
@@ -1,262 +0,0 @@
-/*
- * (C) Copyright 2000 - 2002
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <mpc824x.h>
-#include <common.h>
-#include <command.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkcpu (void)
-{
- unsigned int pvr = get_pvr ();
- unsigned int version = pvr >> 16;
- unsigned char revision;
- ulong clock = gd->cpu_clk;
- char buf[32];
-
- puts ("CPU: ");
-
- switch (version) {
- case CPU_TYPE_8240:
- puts ("MPC8240");
- break;
-
- case CPU_TYPE_8245:
- puts ("MPC8245");
- break;
-
- default:
- return -1; /*not valid for this source */
- }
-
- CONFIG_READ_BYTE (REVID, revision);
-
- if (revision) {
- printf (" Revision %d.%d",
- (revision & 0xf0) >> 4,
- (revision & 0x0f));
- } else {
- return -1; /* no valid CPU revision info */
- }
-
- printf(" at %s MHz: ", strmhz(buf, clock));
-
- print_size(checkicache(), " I-Cache ");
- print_size(checkdcache(), " D-Cache\n");
-
- return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-/* L1 i-cache */
-
-int checkicache (void)
-{
- /*TODO*/
- return 128 * 4 * 32;
-};
-
-/* ------------------------------------------------------------------------- */
-/* L1 d-cache */
-
-int checkdcache (void)
-{
- /*TODO*/
- return 128 * 4 * 32;
-
-};
-
-/*------------------------------------------------------------------- */
-
-int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- ulong msr, addr;
-
- /* Interrupts and MMU off */
- __asm__ ("mtspr 81, 0");
-
- /* Interrupts and MMU off */
- __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
-
- msr &= ~0x1030;
- __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
-
- /*
- * Trying to execute the next instruction at a non-existing address
- * should cause a machine check, resulting in reset
- */
-#ifdef CONFIG_SYS_RESET_ADDRESS
- addr = CONFIG_SYS_RESET_ADDRESS;
-#else
- /*
- * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address,
- * CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid
- * address. Better pick an address known to be invalid on
- * your system and assign it to CONFIG_SYS_RESET_ADDRESS.
- * "(ulong)-1" used to be a good choice for many systems...
- */
- addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong);
-#endif
- ((void (*)(void)) addr) ();
- return 1;
-
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Get timebase clock frequency (like cpu_clk in Hz)
- * This is the sys_logic_clk (memory bus) divided by 4
- */
-unsigned long get_tbclk (void)
-{
- return ((get_bus_freq (0) + 2L) / 4L);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * The MPC824x has an integrated PCI controller known as the MPC107.
- * The following are MPC107 Bridge Controller and PCI Support functions
- *
- */
-
-/*
- * This procedure reads a 32-bit address MPC107 register, and returns
- * a 32 bit value. It swaps the address to little endian before
- * writing it to config address, and swaps the value to big endian
- * before returning to the caller.
- */
-unsigned int mpc824x_mpc107_getreg (unsigned int regNum)
-{
- unsigned int temp;
-
- /* swap the addr. to little endian */
- *(volatile unsigned int *) CHRP_REG_ADDR = PCISWAP (regNum);
- temp = *(volatile unsigned int *) CHRP_REG_DATA;
- return PCISWAP (temp); /* swap the data upon return */
-}
-
-/*
- * This procedure writes a 32-bit address MPC107 register. It swaps
- * the address to little endian before writing it to config address.
- */
-
-void mpc824x_mpc107_setreg (unsigned int regNum, unsigned int regVal)
-{
- /* swap the addr. to little endian */
- *(volatile unsigned int *) CHRP_REG_ADDR = PCISWAP (regNum);
- *(volatile unsigned int *) CHRP_REG_DATA = PCISWAP (regVal);
- return;
-}
-
-
-/*
- * Write a byte (8 bits) to a memory location.
- */
-void mpc824x_mpc107_write8 (unsigned int addr, unsigned char data)
-{
- *(unsigned char *) addr = data;
- __asm__ ("sync");
-}
-
-/*
- * Write a word (16 bits) to a memory location after the value
- * has been byte swapped (big to little endian or vice versa)
- */
-
-void mpc824x_mpc107_write16 (unsigned int address, unsigned short data)
-{
- *(volatile unsigned short *) address = BYTE_SWAP_16_BIT (data);
- __asm__ ("sync");
-}
-
-/*
- * Write a long word (32 bits) to a memory location after the value
- * has been byte swapped (big to little endian or vice versa)
- */
-
-void mpc824x_mpc107_write32 (unsigned int address, unsigned int data)
-{
- *(volatile unsigned int *) address = LONGSWAP (data);
- __asm__ ("sync");
-}
-
-/*
- * Read a byte (8 bits) from a memory location.
- */
-unsigned char mpc824x_mpc107_read8 (unsigned int addr)
-{
- return *(volatile unsigned char *) addr;
-}
-
-
-/*
- * Read a word (16 bits) from a memory location, and byte swap the
- * value before returning to the caller.
- */
-unsigned short mpc824x_mpc107_read16 (unsigned int address)
-{
- unsigned short retVal;
-
- retVal = BYTE_SWAP_16_BIT (*(unsigned short *) address);
- return retVal;
-}
-
-
-/*
- * Read a long word (32 bits) from a memory location, and byte
- * swap the value before returning to the caller.
- */
-unsigned int mpc824x_mpc107_read32 (unsigned int address)
-{
- unsigned int retVal;
-
- retVal = LONGSWAP (*(unsigned int *) address);
- return (retVal);
-}
-
-
-/*
- * Read a register in the Embedded Utilities Memory Block address
- * space.
- * Input: regNum - register number + utility base address. Example,
- * the base address of EPIC is 0x40000, the register number
- * being passed is 0x40000+the address of the target register.
- * (See epic.h for register addresses).
- * Output: The 32 bit little endian value of the register.
- */
-
-unsigned int mpc824x_eummbar_read (unsigned int regNum)
-{
- unsigned int temp;
-
- temp = *(volatile unsigned int *) (EUMBBAR_VAL + regNum);
- temp = PCISWAP (temp);
- return temp;
-}
-
-
-/*
- * Write a value to a register in the Embedded Utilities Memory
- * Block address space.
- * Input: regNum - register number + utility base address. Example,
- * the base address of EPIC is 0x40000, the register
- * number is 0x40000+the address of the target register.
- * (See epic.h for register addresses).
- * regVal - value to be written to the register.
- */
-
-void mpc824x_eummbar_write (unsigned int regNum, unsigned int regVal)
-{
- *(volatile unsigned int *) (EUMBBAR_VAL + regNum) = PCISWAP (regVal);
- return;
-}
-
-/* ------------------------------------------------------------------------- */
diff --git a/arch/powerpc/cpu/mpc824x/cpu_init.c b/arch/powerpc/cpu/mpc824x/cpu_init.c
deleted file mode 100644
index 68d88e9..0000000
--- a/arch/powerpc/cpu/mpc824x/cpu_init.c
+++ /dev/null
@@ -1,311 +0,0 @@
-/*
- * (C) Copyright 2000
- * Rob Taylor. Flying Pig Systems. robt at flyingpig.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <mpc824x.h>
-
-#ifndef CONFIG_SYS_BANK0_ROW
-#define CONFIG_SYS_BANK0_ROW 0
-#endif
-#ifndef CONFIG_SYS_BANK1_ROW
-#define CONFIG_SYS_BANK1_ROW 0
-#endif
-#ifndef CONFIG_SYS_BANK2_ROW
-#define CONFIG_SYS_BANK2_ROW 0
-#endif
-#ifndef CONFIG_SYS_BANK3_ROW
-#define CONFIG_SYS_BANK3_ROW 0
-#endif
-#ifndef CONFIG_SYS_BANK4_ROW
-#define CONFIG_SYS_BANK4_ROW 0
-#endif
-#ifndef CONFIG_SYS_BANK5_ROW
-#define CONFIG_SYS_BANK5_ROW 0
-#endif
-#ifndef CONFIG_SYS_BANK6_ROW
-#define CONFIG_SYS_BANK6_ROW 0
-#endif
-#ifndef CONFIG_SYS_BANK7_ROW
-#define CONFIG_SYS_BANK7_ROW 0
-#endif
-#ifndef CONFIG_SYS_DBUS_SIZE2
-#define CONFIG_SYS_DBUS_SIZE2 0
-#endif
-
-/*
- * Breath some life into the CPU...
- *
- * Set up the memory map,
- * initialize a bunch of registers,
- */
-void
-cpu_init_f (void)
-{
- register unsigned long val;
- CONFIG_WRITE_HALFWORD(PCICR, 0x06); /* Bus Master, respond to PCI memory space acesses*/
-/* CONFIG_WRITE_HALFWORD(PCISR, 0xffff); */ /*reset PCISR*/
-
-#if defined(CONFIG_MUSENKI)
-/* Why is this here, you ask? Try, just try setting 0x8000
- * in PCIACR with CONFIG_WRITE_HALFWORD()
- * this one was a stumper, and we are annoyed
- */
-
-#define M_CONFIG_WRITE_HALFWORD( addr, data ) \
- __asm__ __volatile__(" \
- stw %2,0(%0)\n \
- sync\n \
- sth %3,2(%1)\n \
- sync\n \
- " \
- : /* no output */ \
- : "r" (CONFIG_ADDR), "r" (CONFIG_DATA), \
- "r" (PCISWAP(addr & ~3)), "r" (PCISWAP(data << 16)) \
- );
-
- M_CONFIG_WRITE_HALFWORD(PCIACR, 0x8000);
-#endif
-
- CONFIG_WRITE_BYTE(PCLSR, 0x8); /* set PCI cache line size */
- CONFIG_WRITE_BYTE (PLTR, 0x40); /* set PCI latency timer */
- /*
- * Note that although this bit is cleared after a hard reset, it
- * must be explicitly set and then cleared by software during
- * initialization in order to guarantee correct operation of the
- * DLL and the SDRAM_CLK[0:3] signals (if they are used).
- */
- CONFIG_READ_BYTE (AMBOR, val);
- CONFIG_WRITE_BYTE(AMBOR, val & 0xDF);
- CONFIG_WRITE_BYTE(AMBOR, val | 0x20);
- CONFIG_WRITE_BYTE(AMBOR, val & 0xDF);
-#ifdef CONFIG_MPC8245
- /* silicon bug 28 MPC8245 */
- CONFIG_READ_BYTE(AMBOR,val);
- CONFIG_WRITE_BYTE(AMBOR,val|0x1);
-
-#if 0
- /*
- * The following bug only affects older (XPC8245) processors.
- * DMA transfers initiated by external devices get corrupted due
- * to a hardware scheduling problem.
- *
- * The effect is:
- * when transferring X words, the first 32 words are transferred
- * OK, the next 3 x 32 words are 'old' data (from previous DMA)
- * while the rest of the X words is xferred fine.
- *
- * Disabling 3 of the 4 32 word hardware buffers solves the problem
- * with no significant performance loss.
- */
-
- CONFIG_READ_BYTE(PCMBCR,val);
- /* in order not to corrupt data which is being read over the PCI bus
- * with the PPC as slave, we need to reduce the number of PCMRBs to 1,
- * 4.11 in the processor user manual
- * */
-
-#if 1
- CONFIG_WRITE_BYTE(PCMBCR,(val|0xC0)); /* 1 PCMRB */
-#else
- CONFIG_WRITE_BYTE(PCMBCR,(val|0x80)); /* 2 PCMRBs */
- CONFIG_WRITE_BYTE(PCMBCR,(val|0x40)); /* 3 PCMRBs */
- /* default, 4 PCMRBs are used */
-#endif
-#endif
-#endif
-
- CONFIG_READ_WORD(PICR1, val);
-#if defined(CONFIG_MPC8240)
- CONFIG_WRITE_WORD( PICR1,
- (val & (PICR1_ADDRESS_MAP | PICR1_RCS0)) |
- PIRC1_MSK | PICR1_PROC_TYPE_603E |
- PICR1_FLASH_WR_EN | PICR1_MCP_EN |
- PICR1_CF_DPARK | PICR1_EN_PCS |
- PICR1_CF_APARK );
-#elif defined(CONFIG_MPC8245)
- CONFIG_WRITE_WORD( PICR1,
- (val & (PICR1_RCS0)) |
- PICR1_PROC_TYPE_603E |
- PICR1_FLASH_WR_EN | PICR1_MCP_EN |
- PICR1_CF_DPARK | PICR1_NO_BUSW_CK |
- PICR1_DEC| PICR1_CF_APARK | 0x10); /* 8245 UM says bit 4 must be set */
-#else
-#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
-#endif
-
- CONFIG_READ_WORD(PICR2, val);
- val= val & ~ (PICR2_CF_SNOOP_WS_MASK | PICR2_CF_APHASE_WS_MASK); /*mask off waitstate bits*/
- val |= PICR2_CF_SNOOP_WS_1WS | PICR2_CF_APHASE_WS_1WS; /*1 wait state*/
- CONFIG_WRITE_WORD(PICR2, val);
-
- CONFIG_WRITE_WORD(EUMBBAR, CONFIG_SYS_EUMB_ADDR);
-#ifndef CONFIG_SYS_RAMBOOT
- CONFIG_WRITE_WORD(MCCR1, (CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) |
- (CONFIG_SYS_BANK0_ROW) |
- (CONFIG_SYS_BANK1_ROW << MCCR1_BANK1ROW_SHIFT) |
- (CONFIG_SYS_BANK2_ROW << MCCR1_BANK2ROW_SHIFT) |
- (CONFIG_SYS_BANK3_ROW << MCCR1_BANK3ROW_SHIFT) |
- (CONFIG_SYS_BANK4_ROW << MCCR1_BANK4ROW_SHIFT) |
- (CONFIG_SYS_BANK5_ROW << MCCR1_BANK5ROW_SHIFT) |
- (CONFIG_SYS_BANK6_ROW << MCCR1_BANK6ROW_SHIFT) |
- (CONFIG_SYS_BANK7_ROW << MCCR1_BANK7ROW_SHIFT) |
- (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT));
-#endif
-
-#if defined(CONFIG_SYS_ASRISE) && defined(CONFIG_SYS_ASFALL)
- CONFIG_WRITE_WORD(MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT |
- CONFIG_SYS_ASRISE << MCCR2_ASRISE_SHIFT |
- CONFIG_SYS_ASFALL << MCCR2_ASFALL_SHIFT);
-#else
- CONFIG_WRITE_WORD(MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT);
-#endif
-
-#if defined(CONFIG_MPC8240)
- CONFIG_WRITE_WORD(MCCR3,
- (((CONFIG_SYS_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) |
- (CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT) |
- (CONFIG_SYS_RDLAT << MCCR3_RDLAT_SHIFT));
-#elif defined(CONFIG_MPC8245)
- CONFIG_WRITE_WORD(MCCR3,
- (((CONFIG_SYS_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) |
- (CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT));
-#else
-#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
-#endif
-
-/* this is gross. We think these should all be the same, and various boards
- * should define CONFIG_SYS_ACTORW to 0 if they don't want to set it, or even, if
- * its not set, we define it to zero in this file
- */
-#if defined(CONFIG_CU824)
- CONFIG_WRITE_WORD(MCCR4,
- (CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) |
- (CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
- MCCR4_BIT21 |
- (CONFIG_SYS_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) |
- ((CONFIG_SYS_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) |
- (((CONFIG_SYS_SDMODE_CAS_LAT <<4) | (CONFIG_SYS_SDMODE_WRAP <<3) |
- CONFIG_SYS_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) |
- (CONFIG_SYS_ACTORW << MCCR4_ACTTORW_SHIFT) |
- (((CONFIG_SYS_BSTOPRE & 0x03c0) >> 6) << MCCR4_BSTOPRE6TO9_SHIFT));
-#elif defined(CONFIG_MPC8240)
- CONFIG_WRITE_WORD(MCCR4,
- (CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) |
- (CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
- MCCR4_BIT21 |
- (CONFIG_SYS_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) |
- ((CONFIG_SYS_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) |
- (((CONFIG_SYS_SDMODE_CAS_LAT <<4) | (CONFIG_SYS_SDMODE_WRAP <<3) |
- (CONFIG_SYS_SDMODE_BURSTLEN)) <<MCCR4_SDMODE_SHIFT) |
- (((CONFIG_SYS_BSTOPRE & 0x03c0) >> 6) <<MCCR4_BSTOPRE6TO9_SHIFT ));
-#elif defined(CONFIG_MPC8245)
- CONFIG_READ_WORD(MCCR1, val);
- val &= MCCR1_DBUS_SIZE0; /* test for 64-bit mem bus */
-
- CONFIG_WRITE_WORD(MCCR4,
- (CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) |
- (CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
- (CONFIG_SYS_EXTROM ? MCCR4_EXTROM : 0) |
- (CONFIG_SYS_REGDIMM ? MCCR4_REGDIMM : 0) |
- (CONFIG_SYS_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) |
- ((CONFIG_SYS_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) |
- (CONFIG_SYS_DBUS_SIZE2 << MCCR4_DBUS_SIZE2_SHIFT) |
- (((CONFIG_SYS_SDMODE_CAS_LAT <<4) | (CONFIG_SYS_SDMODE_WRAP <<3) |
- (val ? 2 : 3)) << MCCR4_SDMODE_SHIFT) |
- (CONFIG_SYS_ACTORW << MCCR4_ACTTORW_SHIFT) |
- (((CONFIG_SYS_BSTOPRE & 0x03c0) >> 6) <<MCCR4_BSTOPRE6TO9_SHIFT ));
-#else
-#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
-#endif
-
- CONFIG_WRITE_WORD(MSAR1,
- ( (CONFIG_SYS_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
- (((CONFIG_SYS_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
- (((CONFIG_SYS_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
- (((CONFIG_SYS_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
- CONFIG_WRITE_WORD(EMSAR1,
- ( (CONFIG_SYS_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
- (((CONFIG_SYS_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
- (((CONFIG_SYS_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
- (((CONFIG_SYS_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
- CONFIG_WRITE_WORD(MSAR2,
- ( (CONFIG_SYS_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
- (((CONFIG_SYS_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
- (((CONFIG_SYS_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
- (((CONFIG_SYS_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
- CONFIG_WRITE_WORD(EMSAR2,
- ( (CONFIG_SYS_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
- (((CONFIG_SYS_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
- (((CONFIG_SYS_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
- (((CONFIG_SYS_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
- CONFIG_WRITE_WORD(MEAR1,
- ( (CONFIG_SYS_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
- (((CONFIG_SYS_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
- (((CONFIG_SYS_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
- (((CONFIG_SYS_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
- CONFIG_WRITE_WORD(EMEAR1,
- ( (CONFIG_SYS_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
- (((CONFIG_SYS_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
- (((CONFIG_SYS_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
- (((CONFIG_SYS_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
- CONFIG_WRITE_WORD(MEAR2,
- ( (CONFIG_SYS_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
- (((CONFIG_SYS_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
- (((CONFIG_SYS_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
- (((CONFIG_SYS_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
- CONFIG_WRITE_WORD(EMEAR2,
- ( (CONFIG_SYS_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
- (((CONFIG_SYS_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
- (((CONFIG_SYS_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
- (((CONFIG_SYS_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
-
- CONFIG_WRITE_BYTE(ODCR, CONFIG_SYS_ODCR);
-#ifdef CONFIG_SYS_DLL_MAX_DELAY
- CONFIG_WRITE_BYTE(MIOCR1, CONFIG_SYS_DLL_MAX_DELAY); /* needed to make DLL lock */
-#endif
-#if defined(CONFIG_SYS_DLL_EXTEND) && defined(CONFIG_SYS_PCI_HOLD_DEL)
- CONFIG_WRITE_BYTE(PMCR2, CONFIG_SYS_DLL_EXTEND | CONFIG_SYS_PCI_HOLD_DEL);
-#endif
-#if defined(MIOCR2) && defined(CONFIG_SYS_SDRAM_DSCD)
- CONFIG_WRITE_BYTE(MIOCR2, CONFIG_SYS_SDRAM_DSCD); /* change memory input */
-#endif /* setup & hold time */
-
- CONFIG_WRITE_BYTE(MBER,
- CONFIG_SYS_BANK0_ENABLE |
- (CONFIG_SYS_BANK1_ENABLE << 1) |
- (CONFIG_SYS_BANK2_ENABLE << 2) |
- (CONFIG_SYS_BANK3_ENABLE << 3) |
- (CONFIG_SYS_BANK4_ENABLE << 4) |
- (CONFIG_SYS_BANK5_ENABLE << 5) |
- (CONFIG_SYS_BANK6_ENABLE << 6) |
- (CONFIG_SYS_BANK7_ENABLE << 7));
-
-#ifdef CONFIG_SYS_PGMAX
- CONFIG_WRITE_BYTE(MPMR, CONFIG_SYS_PGMAX);
-#endif
-
- /* ! Wait 200us before initialize other registers */
- /*FIXME: write a decent udelay wait */
- __asm__ __volatile__(
- " mtctr %0 \n \
- 0: bdnz 0b\n"
- :
- : "r" (0x10000));
-
- CONFIG_READ_WORD(MCCR1, val);
- CONFIG_WRITE_WORD(MCCR1, val | MCCR1_MEMGO); /* set memory access going */
- __asm__ __volatile__("eieio");
-}
-
-/*
- * initialize higher level parts of CPU like time base and timers
- */
-int cpu_init_r (void)
-{
- return (0);
-}
diff --git a/arch/powerpc/cpu/mpc824x/drivers/epic.h b/arch/powerpc/cpu/mpc824x/drivers/epic.h
deleted file mode 100644
index 2803f63..0000000
--- a/arch/powerpc/cpu/mpc824x/drivers/epic.h
+++ /dev/null
@@ -1 +0,0 @@
-#include "epic/epic.h"
diff --git a/arch/powerpc/cpu/mpc824x/drivers/epic/README b/arch/powerpc/cpu/mpc824x/drivers/epic/README
deleted file mode 100644
index 5798996..0000000
--- a/arch/powerpc/cpu/mpc824x/drivers/epic/README
+++ /dev/null
@@ -1,102 +0,0 @@
-CONTENT:
-
- epic.h
- epic1.c
- epic2.s
-
-WHAT ARE THESE FILES:
-
-These files contain MPC8240 (Kahlua) EPIC
-driver routines. The driver routines are not
-written for any specific operating system.
-They serves the purpose of code sample, and
-jump-start for using the MPC8240 EPIC unit.
-
-For the reason of correctness of C language
-syntax, these files are compiled by Metaware
-C compiler and assembler.
-
-ENDIAN NOTATION:
-
-The algorithm is designed for big-endian mode,
-software is responsible for byte swapping.
-
-USAGE:
-
-1. The host system that is running on MPC8240
- shall link the files listed here. The memory
- location of driver routines shall take into
- account of that driver routines need to run
- in supervisor mode and they process external
- interrupts.
-
- The routine epic_exception shall be called by
- exception vector at location 0x500, i.e.,
- 603e core external exception vector.
-
-2. The host system is responsible for configuring
- the MPC8240 including Embedded Utilities Memory
- Block. All EPIC driver functions require the
- content of Embedded Utilities Memory Block
- Base Address Register, EUMBBAR, as the first
- parameter.
-
-3. Before EPIC unit of MPC8240 can be used,
- initialize EPIC unit by calling epicInit
- with the corresponding parameters.
-
- The initialization shall disable the 603e
- core External Exception by calling CoreExtIntDisable( ).
- Next, call epicInit( ). Last, enable the 603e core
- External Exception by calling CoreExtIntEnable( ).
-
-4. After EPIC unit has been successfully initialized,
- epicIntSourceSet( ) shall be used to register each
- external interrupt source. Anytime, an external
- interrupt source can be disabled or enabled by
- calling corresponding function, epicIntDisable( ),
- or epicIntEnable( ).
-
- Global Timers' resource, base count and frequency,
- can be changed by calling epicTmFrequencySet( )
- and epicTmBaseSet( ).
-
- To stop counting a specific global timer, use
- the function, epicTmInhibit while epicTmEnable
- can be used to start counting a timer.
-
-5. To mask a set of external interrupts that are
- are certain level below, epicIntPrioritySet( )
- can be used. For example, if the processor's
- current task priority register is set to 0x7,
- only interrupts of priority 0x8 or higher will
- be passed to the processor.
-
- Be careful when using this function. It may
- corrupt the current interrupt pending, selector,
- and request registers, resulting an invalid vetor.
-
- After enabling an interrupt, disable it may also
- cause an invalid vector. User may consider using
- the spurious vector interrupt service routine to
- handle this case.
-
-6. The EPIC driver routines contains a set
- of utilities, Set and Get, for host system
- to query and modify the desired EPIC source
- registers.
-
-7. Each external interrupt source shall register
- its interrupt service routine. The routine
- shall contain all interrupt source specific
- processes and keep as short as possible.
-
- Special customized end of interrupt routine
- is optional. If it is needed, it shall contain
- the external interrupt source specific end of
- interrupt process.
-
- External interrupt exception vector@0x500
- shall always call the epicEOI just before
- rfi instruction. Refer to the routine,
- epic_exception, for a code sample.
diff --git a/arch/powerpc/cpu/mpc824x/drivers/epic/epic.h b/arch/powerpc/cpu/mpc824x/drivers/epic/epic.h
deleted file mode 100644
index 58f81c5..0000000
--- a/arch/powerpc/cpu/mpc824x/drivers/epic/epic.h
+++ /dev/null
@@ -1,163 +0,0 @@
-/*********************************************************************
- * mpc8240epic.h - EPIC module of the MPC8240 micro-controller
- *
- * Copyrigh 1999 Motorola Inc.
- *
- * Modification History:
- * =====================
- * 01a,04Feb99,My Created.
- * 15Nov200, robt -modified to use in U-Boot
- *
-*/
-
-#ifndef __INCEPICh
-#define __INCEPICh
-
-#define ULONG unsigned long
-#define MAXVEC 20
-#define MAXIRQ 5 /* IRQs */
-#define EPIC_DIRECT_IRQ 0 /* Direct interrupt type */
-
-/* EPIC register addresses */
-
-#define EPIC_EUMBBAR 0x40000 /* EUMBBAR of EPIC */
-#define EPIC_FEATURES_REG (EPIC_EUMBBAR + 0x01000)/* Feature reporting */
-#define EPIC_GLOBAL_REG (EPIC_EUMBBAR + 0x01020)/* Global config. */
-#define EPIC_INT_CONF_REG (EPIC_EUMBBAR + 0x01030)/* Interrupt config. */
-#define EPIC_VENDOR_ID_REG (EPIC_EUMBBAR + 0x01080)/* Vendor id */
-#define EPIC_PROC_INIT_REG (EPIC_EUMBBAR + 0x01090)/* Processor init. */
-#define EPIC_SPUR_VEC_REG (EPIC_EUMBBAR + 0x010e0)/* Spurious vector */
-#define EPIC_TM_FREQ_REG (EPIC_EUMBBAR + 0x010f0)/* Timer Frequency */
-
-#define EPIC_TM0_CUR_COUNT_REG (EPIC_EUMBBAR + 0x01100)/* Gbl TM0 Cur. Count*/
-#define EPIC_TM0_BASE_COUNT_REG (EPIC_EUMBBAR + 0x01110)/* Gbl TM0 Base Count*/
-#define EPIC_TM0_VEC_REG (EPIC_EUMBBAR + 0x01120)/* Gbl TM0 Vector Pri*/
-#define EPIC_TM0_DES_REG (EPIC_EUMBBAR + 0x01130)/* Gbl TM0 Dest. */
-
-#define EPIC_TM1_CUR_COUNT_REG (EPIC_EUMBBAR + 0x01140)/* Gbl TM1 Cur. Count*/
-#define EPIC_TM1_BASE_COUNT_REG (EPIC_EUMBBAR + 0x01150)/* Gbl TM1 Base Count*/
-#define EPIC_TM1_VEC_REG (EPIC_EUMBBAR + 0x01160)/* Gbl TM1 Vector Pri*/
-#define EPIC_TM1_DES_REG (EPIC_EUMBBAR + 0x01170)/* Gbl TM1 Dest. */
-
-#define EPIC_TM2_CUR_COUNT_REG (EPIC_EUMBBAR + 0x01180)/* Gbl TM2 Cur. Count*/
-#define EPIC_TM2_BASE_COUNT_REG (EPIC_EUMBBAR + 0x01190)/* Gbl TM2 Base Count*/
-#define EPIC_TM2_VEC_REG (EPIC_EUMBBAR + 0x011a0)/* Gbl TM2 Vector Pri*/
-#define EPIC_TM2_DES_REG (EPIC_EUMBBAR + 0x011b0)/* Gbl TM2 Dest */
-
-#define EPIC_TM3_CUR_COUNT_REG (EPIC_EUMBBAR + 0x011c0)/* Gbl TM3 Cur. Count*/
-#define EPIC_TM3_BASE_COUNT_REG (EPIC_EUMBBAR + 0x011d0)/* Gbl TM3 Base Count*/
-#define EPIC_TM3_VEC_REG (EPIC_EUMBBAR + 0x011e0)/* Gbl TM3 Vector Pri*/
-#define EPIC_TM3_DES_REG (EPIC_EUMBBAR + 0x011f0)/* Gbl TM3 Dest. */
-
-#define EPIC_EX_INT0_VEC_REG (EPIC_EUMBBAR + 0x10200)/* Ext. Int. Sr0 Des */
-#define EPIC_EX_INT0_DES_REG (EPIC_EUMBBAR + 0x10210)/* Ext. Int. Sr0 Vect*/
-#define EPIC_EX_INT1_VEC_REG (EPIC_EUMBBAR + 0x10220)/* Ext. Int. Sr1 Des */
-#define EPIC_EX_INT1_DES_REG (EPIC_EUMBBAR + 0x10230)/* Ext. Int. Sr1 Vect*/
-#define EPIC_EX_INT2_VEC_REG (EPIC_EUMBBAR + 0x10240)/* Ext. Int. Sr2 Des */
-#define EPIC_EX_INT2_DES_REG (EPIC_EUMBBAR + 0x10250)/* Ext. Int. Sr2 Vect*/
-#define EPIC_EX_INT3_VEC_REG (EPIC_EUMBBAR + 0x10260)/* Ext. Int. Sr3 Des */
-#define EPIC_EX_INT3_DES_REG (EPIC_EUMBBAR + 0x10270)/* Ext. Int. Sr3 Vect*/
-#define EPIC_EX_INT4_VEC_REG (EPIC_EUMBBAR + 0x10280)/* Ext. Int. Sr4 Des */
-#define EPIC_EX_INT4_DES_REG (EPIC_EUMBBAR + 0x10290)/* Ext. Int. Sr4 Vect*/
-
-#define EPIC_SR_INT0_VEC_REG (EPIC_EUMBBAR + 0x10200)/* Sr. Int. Sr0 Des */
-#define EPIC_SR_INT0_DES_REG (EPIC_EUMBBAR + 0x10210)/* Sr. Int. Sr0 Vect */
-#define EPIC_SR_INT1_VEC_REG (EPIC_EUMBBAR + 0x10220)/* Sr. Int. Sr1 Des */
-#define EPIC_SR_INT1_DES_REG (EPIC_EUMBBAR + 0x10230)/* Sr. Int. Sr1 Vect.*/
-#define EPIC_SR_INT2_VEC_REG (EPIC_EUMBBAR + 0x10240)/* Sr. Int. Sr2 Des */
-#define EPIC_SR_INT2_DES_REG (EPIC_EUMBBAR + 0x10250)/* Sr. Int. Sr2 Vect.*/
-#define EPIC_SR_INT3_VEC_REG (EPIC_EUMBBAR + 0x10260)/* Sr. Int. Sr3 Des */
-#define EPIC_SR_INT3_DES_REG (EPIC_EUMBBAR + 0x10270)/* Sr. Int. Sr3 Vect.*/
-#define EPIC_SR_INT4_VEC_REG (EPIC_EUMBBAR + 0x10280)/* Sr. Int. Sr4 Des */
-#define EPIC_SR_INT4_DES_REG (EPIC_EUMBBAR + 0x10290)/* Sr. Int. Sr4 Vect.*/
-
-#define EPIC_SR_INT5_VEC_REG (EPIC_EUMBBAR + 0x102a0)/* Sr. Int. Sr5 Des */
-#define EPIC_SR_INT5_DES_REG (EPIC_EUMBBAR + 0x102b0)/* Sr. Int. Sr5 Vect.*/
-#define EPIC_SR_INT6_VEC_REG (EPIC_EUMBBAR + 0x102c0)/* Sr. Int. Sr6 Des */
-#define EPIC_SR_INT6_DES_REG (EPIC_EUMBBAR + 0x102d0)/* Sr. Int. Sr6 Vect.*/
-#define EPIC_SR_INT7_VEC_REG (EPIC_EUMBBAR + 0x102e0)/* Sr. Int. Sr7 Des */
-#define EPIC_SR_INT7_DES_REG (EPIC_EUMBBAR + 0x102f0)/* Sr. Int. Sr7 Vect.*/
-#define EPIC_SR_INT8_VEC_REG (EPIC_EUMBBAR + 0x10300)/* Sr. Int. Sr8 Des */
-#define EPIC_SR_INT8_DES_REG (EPIC_EUMBBAR + 0x10310)/* Sr. Int. Sr8 Vect.*/
-#define EPIC_SR_INT9_VEC_REG (EPIC_EUMBBAR + 0x10320)/* Sr. Int. Sr9 Des */
-#define EPIC_SR_INT9_DES_REG (EPIC_EUMBBAR + 0x10330)/* Sr. Int. Sr9 Vect.*/
-
-#define EPIC_SR_INT10_VEC_REG (EPIC_EUMBBAR + 0x10340)/* Sr. Int. Sr10 Des */
-#define EPIC_SR_INT10_DES_REG (EPIC_EUMBBAR + 0x10350)/* Sr. Int. Sr10 Vect*/
-#define EPIC_SR_INT11_VEC_REG (EPIC_EUMBBAR + 0x10360)/* Sr. Int. Sr11 Des */
-#define EPIC_SR_INT11_DES_REG (EPIC_EUMBBAR + 0x10370)/* Sr. Int. Sr11 Vect*/
-#define EPIC_SR_INT12_VEC_REG (EPIC_EUMBBAR + 0x10380)/* Sr. Int. Sr12 Des */
-#define EPIC_SR_INT12_DES_REG (EPIC_EUMBBAR + 0x10390)/* Sr. Int. Sr12 Vect*/
-#define EPIC_SR_INT13_VEC_REG (EPIC_EUMBBAR + 0x103a0)/* Sr. Int. Sr13 Des */
-#define EPIC_SR_INT13_DES_REG (EPIC_EUMBBAR + 0x103b0)/* Sr. Int. Sr13 Vect*/
-#define EPIC_SR_INT14_VEC_REG (EPIC_EUMBBAR + 0x103c0)/* Sr. Int. Sr14 Des */
-#define EPIC_SR_INT14_DES_REG (EPIC_EUMBBAR + 0x103d0)/* Sr. Int. Sr14 Vect*/
-#define EPIC_SR_INT15_VEC_REG (EPIC_EUMBBAR + 0x103e0)/* Sr. Int. Sr15 Des */
-#define EPIC_SR_INT15_DES_REG (EPIC_EUMBBAR + 0x103f0)/* Sr. Int. Sr15 Vect*/
-
-#define EPIC_I2C_INT_VEC_REG (EPIC_EUMBBAR + 0x11020)/* I2C Int. Vect Pri.*/
-#define EPIC_I2C_INT_DES_REG (EPIC_EUMBBAR + 0x11030)/* I2C Int. Dest */
-#define EPIC_DMA0_INT_VEC_REG (EPIC_EUMBBAR + 0x11040)/* DMA0 Int. Vect Pri*/
-#define EPIC_DMA0_INT_DES_REG (EPIC_EUMBBAR + 0x11050)/* DMA0 Int. Dest */
-#define EPIC_DMA1_INT_VEC_REG (EPIC_EUMBBAR + 0x11060)/* DMA1 Int. Vect Pri*/
-#define EPIC_DMA1_INT_DES_REG (EPIC_EUMBBAR + 0x11070)/* DMA1 Int. Dest */
-#define EPIC_MSG_INT_VEC_REG (EPIC_EUMBBAR + 0x110c0)/* Msg Int. Vect Pri*/
-#define EPIC_MSG_INT_DES_REG (EPIC_EUMBBAR + 0x110d0)/* Msg Int. Dest */
-
-#define EPIC_PROC_CTASK_PRI_REG (EPIC_EUMBBAR + 0x20080)/* Proc. current task*/
-#define EPIC_PROC_INT_ACK_REG (EPIC_EUMBBAR + 0x200a0)/* Int. acknowledge */
-#define EPIC_PROC_EOI_REG (EPIC_EUMBBAR + 0x200b0)/* End of interrupt */
-
-#define EPIC_VEC_PRI_MASK 0x80000000 /* Mask Interrupt bit in IVPR */
-#define EPIC_VEC_PRI_DFLT_PRI 8 /* Interrupt Priority in IVPR */
-
-/* Error code */
-
-#define OK 0
-#define ERROR -1
-
-/* function prototypes */
-
-void epicVendorId( unsigned int *step,
- unsigned int *devId,
- unsigned int *venId
- );
-void epicFeatures( unsigned int *noIRQs,
- unsigned int *noCPUs,
- unsigned int *VerId );
-extern void epicInit( unsigned int IRQType, unsigned int clkRatio);
-ULONG sysEUMBBARRead ( ULONG regNum );
-void sysEUMBBARWrite ( ULONG regNum, ULONG regVal);
-extern void epicTmFrequencySet( unsigned int frq );
-extern unsigned int epicTmFrequencyGet(void);
-extern unsigned int epicTmBaseSet( ULONG srcAddr,
- unsigned int cnt,
- unsigned int inhibit );
-extern unsigned int epicTmBaseGet ( ULONG srcAddr, unsigned int *val );
-extern unsigned int epicTmCountGet( ULONG srcAddr, unsigned int *val );
-extern unsigned int epicTmInhibit( unsigned int timer );
-extern unsigned int epicTmEnable( ULONG srcAdr );
-extern void CoreExtIntEnable(void); /* Enable 603e external interrupts */
-extern void CoreExtIntDisable(void); /* Disable 603e external interrupts */
-extern unsigned char epicIntTaskGet(void);
-extern void epicIntTaskSet( unsigned char val );
-extern unsigned int epicIntAck(void);
-extern void epicSprSet( unsigned int eumbbar, unsigned char );
-extern void epicConfigGet( unsigned int *clkRatio,
- unsigned int *serEnable );
-extern void SrcVecTableInit(void);
-extern unsigned int epicModeGet(void);
-extern void epicIntEnable(int Vect);
-extern void epicIntDisable(int Vect);
-extern int epicIntSourceConfig(int Vect, int Polarity, int Sense, int Prio);
-extern unsigned int epicIntAck(void);
-extern void epicEOI(void);
-extern int epicCurTaskPrioSet(int Vect);
-
-struct SrcVecTable
- {
- ULONG srcAddr;
- char srcName[40];
- };
-
-#endif /* EPIC_H */
diff --git a/arch/powerpc/cpu/mpc824x/drivers/epic/epic1.c b/arch/powerpc/cpu/mpc824x/drivers/epic/epic1.c
deleted file mode 100644
index ecbb42d..0000000
--- a/arch/powerpc/cpu/mpc824x/drivers/epic/epic1.c
+++ /dev/null
@@ -1,517 +0,0 @@
-/**************************************************
- *
- * copyright @ motorola, 1999
- *
- *************************************************/
-#include <mpc824x.h>
-#include <common.h>
-#include "epic.h"
-
-
-#define PRINT(format, args...) printf(format , ## args)
-
-typedef void (*VOIDFUNCPTR) (void); /* ptr to function returning void */
-struct SrcVecTable SrcVecTable[MAXVEC] = /* Addr/Vector cross-reference tbl */
- {
- { EPIC_EX_INT0_VEC_REG, "External Direct/Serial Source 0"},
- { EPIC_EX_INT1_VEC_REG, "External Direct/Serial Source 1"},
- { EPIC_EX_INT2_VEC_REG, "External Direct/Serial Source 2"},
- { EPIC_EX_INT3_VEC_REG, "External Direct/Serial Source 3"},
- { EPIC_EX_INT4_VEC_REG, "External Direct/Serial Source 4"},
-
- { EPIC_SR_INT5_VEC_REG, "External Serial Source 5"},
- { EPIC_SR_INT6_VEC_REG, "External Serial Source 6"},
- { EPIC_SR_INT7_VEC_REG, "External Serial Source 7"},
- { EPIC_SR_INT8_VEC_REG, "External Serial Source 8"},
- { EPIC_SR_INT9_VEC_REG, "External Serial Source 9"},
- { EPIC_SR_INT10_VEC_REG, "External Serial Source 10"},
- { EPIC_SR_INT11_VEC_REG, "External Serial Source 11"},
- { EPIC_SR_INT12_VEC_REG, "External Serial Source 12"},
- { EPIC_SR_INT13_VEC_REG, "External Serial Source 13"},
- { EPIC_SR_INT14_VEC_REG, "External Serial Source 14"},
- { EPIC_SR_INT15_VEC_REG, "External Serial Source 15"},
-
- { EPIC_I2C_INT_VEC_REG, "Internal I2C Source"},
- { EPIC_DMA0_INT_VEC_REG, "Internal DMA0 Source"},
- { EPIC_DMA1_INT_VEC_REG, "Internal DMA1 Source"},
- { EPIC_MSG_INT_VEC_REG, "Internal Message Source"},
- };
-
-VOIDFUNCPTR intVecTbl[MAXVEC]; /* Interrupt vector table */
-
-
-/****************************************************************************
-* epicInit - Initialize the EPIC registers
-*
-* This routine resets the Global Configuration Register, thus it:
-* - Disables all interrupts
-* - Sets epic registers to reset values
-* - Sets the value of the Processor Current Task Priority to the
-* highest priority (0xF).
-* epicInit then sets the EPIC operation mode to Mixed Mode (vs. Pass
-* Through or 8259 compatible mode).
-*
-* If IRQType (input) is Direct IRQs:
-* - IRQType is written to the SIE bit of the EPIC Interrupt
-* Configuration register (ICR).
-* - clkRatio is ignored.
-* If IRQType is Serial IRQs:
-* - both IRQType and clkRatio will be written to the ICR register
-*/
-
-void epicInit
- (
- unsigned int IRQType, /* Direct or Serial */
- unsigned int clkRatio /* Clk Ratio for Serial IRQs */
- )
- {
- ULONG tmp;
-
- tmp = sysEUMBBARRead(EPIC_GLOBAL_REG);
- tmp |= 0xa0000000; /* Set the Global Conf. register */
- sysEUMBBARWrite(EPIC_GLOBAL_REG, tmp);
- /*
- * Wait for EPIC to reset - CLH
- */
- while( (sysEUMBBARRead(EPIC_GLOBAL_REG) & 0x80000000) == 1);
- sysEUMBBARWrite(EPIC_GLOBAL_REG, 0x20000000);
- tmp = sysEUMBBARRead(EPIC_INT_CONF_REG); /* Read interrupt conf. reg */
-
- if (IRQType == EPIC_DIRECT_IRQ) /* direct mode */
- sysEUMBBARWrite(EPIC_INT_CONF_REG, tmp & 0xf7ffffff);
- else /* Serial mode */
- {
- tmp = (clkRatio << 28) | 0x08000000; /* Set clock ratio */
- sysEUMBBARWrite(EPIC_INT_CONF_REG, tmp);
- }
-
- while (epicIntAck() != 0xff) /* Clear all pending interrupts */
- epicEOI();
-}
-
-/****************************************************************************
- * epicIntEnable - Enable an interrupt source
- *
- * This routine clears the mask bit of an external, an internal or
- * a Timer register to enable the interrupt.
- *
- * RETURNS: None
- */
-void epicIntEnable(int intVec)
-{
- ULONG tmp;
- ULONG srAddr;
-
- srAddr = SrcVecTable[intVec].srcAddr; /* Retrieve src Vec/Prio register */
- tmp = sysEUMBBARRead(srAddr);
- tmp &= ~EPIC_VEC_PRI_MASK; /* Clear the mask bit */
- tmp |= (EPIC_VEC_PRI_DFLT_PRI << 16); /* Set priority to Default - CLH */
- tmp |= intVec; /* Set Vector number */
- sysEUMBBARWrite(srAddr, tmp);
-
- return;
- }
-
-/****************************************************************************
- * epicIntDisable - Disable an interrupt source
- *
- * This routine sets the mask bit of an external, an internal or
- * a Timer register to disable the interrupt.
- *
- * RETURNS: OK or ERROR
- *
- */
-
-void epicIntDisable
- (
- int intVec /* Interrupt vector number */
- )
- {
-
- ULONG tmp, srAddr;
-
- srAddr = SrcVecTable[intVec].srcAddr;
- tmp = sysEUMBBARRead(srAddr);
- tmp |= 0x80000000; /* Set the mask bit */
- sysEUMBBARWrite(srAddr, tmp);
- return;
- }
-
-/****************************************************************************
- * epicIntSourceConfig - Set properties of an interrupt source
- *
- * This function sets interrupt properites (Polarity, Sense, Interrupt
- * Prority, and Interrupt Vector) of an Interrupt Source. The properties
- * can be set when the current source is not in-request or in-service,
- * which is determined by the Activity bit. This routine return ERROR
- * if the the Activity bit is 1 (in-request or in-service).
- *
- * This function assumes that the Source Vector/Priority register (input)
- * is a valid address.
- *
- * RETURNS: OK or ERROR
- */
-
-int epicIntSourceConfig
- (
- int Vect, /* interrupt source vector number */
- int Polarity, /* interrupt source polarity */
- int Sense, /* interrupt source Sense */
- int Prio /* interrupt source priority */
- )
-
- {
- ULONG tmp, newVal;
- ULONG actBit, srAddr;
-
- srAddr = SrcVecTable[Vect].srcAddr;
- tmp = sysEUMBBARRead(srAddr);
- actBit = (tmp & 40000000) >> 30; /* retrieve activity bit - bit 30 */
- if (actBit == 1)
- return ERROR;
-
- tmp &= 0xff30ff00; /* Erase previously set P,S,Prio,Vector bits */
- newVal = (Polarity << 23) | (Sense << 22) | (Prio << 16) | Vect;
- sysEUMBBARWrite(srAddr, tmp | newVal );
- return (OK);
- }
-
-/****************************************************************************
- * epicIntAck - acknowledge an interrupt
- *
- * This function reads the Interrupt acknowldge register and return
- * the vector number of the highest pending interrupt.
- *
- * RETURNS: Interrupt Vector number.
- */
-
-unsigned int epicIntAck(void)
-{
- return(sysEUMBBARRead( EPIC_PROC_INT_ACK_REG ));
-}
-
-/****************************************************************************
- * epicEOI - signal an end of interrupt
- *
- * This function writes 0x0 to the EOI register to signal end of interrupt.
- * It is usually called after an interrupt routine is served.
- *
- * RETURNS: None
- */
-
-void epicEOI(void)
- {
- sysEUMBBARWrite(EPIC_PROC_EOI_REG, 0x0);
- }
-
-/****************************************************************************
- * epicCurTaskPrioSet - sets the priority of the Processor Current Task
- *
- * This function should be called after epicInit() to lower the priority
- * of the processor current task.
- *
- * RETURNS: OK or ERROR
- */
-
-int epicCurTaskPrioSet
- (
- int prioNum /* New priority value */
- )
- {
-
- if ( (prioNum < 0) || (prioNum > 0xF))
- return ERROR;
- sysEUMBBARWrite(EPIC_PROC_CTASK_PRI_REG, prioNum);
- return OK;
- }
-
-
-/************************************************************************
- * function: epicIntTaskGet
- *
- * description: Get value of processor current interrupt task priority register
- *
- * note:
- ***********************************************************************/
-unsigned char epicIntTaskGet()
-{
- /* get the interrupt task priority register */
- ULONG reg;
- unsigned char rec;
-
- reg = sysEUMBBARRead( EPIC_PROC_CTASK_PRI_REG );
- rec = ( reg & 0x0F );
- return rec;
-}
-
-
-/**************************************************************
- * function: epicISR
- *
- * description: EPIC service routine called by the core exception
- * at 0x500
- *
- * note:
- **************************************************************/
-unsigned int epicISR(void)
-{
- return 0;
-}
-
-
-/************************************************************
- * function: epicModeGet
- *
- * description: query EPIC mode, return 0 if pass through mode
- * return 1 if mixed mode
- *
- * note:
- *************************************************************/
-unsigned int epicModeGet(void)
-{
- ULONG val;
-
- val = sysEUMBBARRead( EPIC_GLOBAL_REG );
- return (( val & 0x20000000 ) >> 29);
-}
-
-
-/*********************************************
- * function: epicConfigGet
- *
- * description: Get the EPIC interrupt Configuration
- * return 0 if not error, otherwise return 1
- *
- * note:
- ********************************************/
-void epicConfigGet( unsigned int *clkRatio, unsigned int *serEnable)
-{
- ULONG val;
-
- val = sysEUMBBARRead( EPIC_INT_CONF_REG );
- *clkRatio = ( val & 0x70000000 ) >> 28;
- *serEnable = ( val & 0x8000000 ) >> 27;
-}
-
-
-/*******************************************************************
- * sysEUMBBARRead - Read a 32-bit EUMBBAR register
- *
- * This routine reads the content of a register in the Embedded
- * Utilities Memory Block, and swaps to big endian before returning
- * the value.
- *
- * RETURNS: The content of the specified EUMBBAR register.
- */
-
-ULONG sysEUMBBARRead
- (
- ULONG regNum
- )
- {
- ULONG temp;
-
- temp = *(ULONG *) (CONFIG_SYS_EUMB_ADDR + regNum);
- return ( LONGSWAP(temp));
- }
-
-/*******************************************************************
- * sysEUMBBARWrite - Write a 32-bit EUMBBAR register
- *
- * This routine swaps the value to little endian then writes it to
- * a register in the Embedded Utilities Memory Block address space.
- *
- * RETURNS: N/A
- */
-
-void sysEUMBBARWrite
- (
- ULONG regNum, /* EUMBBAR register address */
- ULONG regVal /* Value to be written */
- )
- {
-
- *(ULONG *) (CONFIG_SYS_EUMB_ADDR + regNum) = LONGSWAP(regVal);
- return ;
- }
-
-
-/********************************************************
- * function: epicVendorId
- *
- * description: return the EPIC Vendor Identification
- * register:
- *
- * siliccon version, device id, and vendor id
- *
- * note:
- ********************************************************/
-void epicVendorId
- (
- unsigned int *step,
- unsigned int *devId,
- unsigned int *venId
- )
- {
- ULONG val;
- val = sysEUMBBARRead( EPIC_VENDOR_ID_REG );
- *step = ( val & 0x00FF0000 ) >> 16;
- *devId = ( val & 0x0000FF00 ) >> 8;
- *venId = ( val & 0x000000FF );
- }
-
-/**************************************************
- * function: epicFeatures
- *
- * description: return the number of IRQ supported,
- * number of CPU, and the version of the
- * OpenEPIC
- *
- * note:
- *************************************************/
-void epicFeatures
- (
- unsigned int *noIRQs,
- unsigned int *noCPUs,
- unsigned int *verId
- )
- {
- ULONG val;
-
- val = sysEUMBBARRead( EPIC_FEATURES_REG );
- *noIRQs = ( val & 0x07FF0000 ) >> 16;
- *noCPUs = ( val & 0x00001F00 ) >> 8;
- *verId = ( val & 0x000000FF );
-}
-
-
-/*********************************************************
- * function: epciTmFrequncySet
- *
- * description: Set the timer frequency reporting register
- ********************************************************/
-void epicTmFrequencySet( unsigned int frq )
-{
- sysEUMBBARWrite(EPIC_TM_FREQ_REG, frq);
-}
-
-/*******************************************************
- * function: epicTmFrequncyGet
- *
- * description: Get the current value of the Timer Frequency
- * Reporting register
- *
- ******************************************************/
-unsigned int epicTmFrequencyGet(void)
-{
- return( sysEUMBBARRead(EPIC_TM_FREQ_REG)) ;
-}
-
-
-/****************************************************
- * function: epicTmBaseSet
- *
- * description: Set the #n global timer base count register
- * return 0 if no error, otherwise return 1.
- *
- * note:
- ****************************************************/
-unsigned int epicTmBaseSet
- (
- ULONG srcAddr, /* Address of the Timer Base register */
- unsigned int cnt, /* Base count */
- unsigned int inhibit /* 1 - count inhibit */
- )
-{
-
- unsigned int val = 0x80000000;
- /* First inhibit counting the timer */
- sysEUMBBARWrite(srcAddr, val) ;
-
- /* set the new value */
- val = (cnt & 0x7fffffff) | ((inhibit & 0x1) << 31);
- sysEUMBBARWrite(srcAddr, val) ;
- return 0;
-}
-
-/***********************************************************************
- * function: epicTmBaseGet
- *
- * description: Get the current value of the global timer base count register
- * return 0 if no error, otherwise return 1.
- *
- * note:
- ***********************************************************************/
-unsigned int epicTmBaseGet( ULONG srcAddr, unsigned int *val )
-{
- *val = sysEUMBBARRead( srcAddr );
- *val = *val & 0x7fffffff;
- return 0;
-}
-
-/***********************************************************
- * function: epicTmCountGet
- *
- * description: Get the value of a given global timer
- * current count register
- * return 0 if no error, otherwise return 1
- * note:
- **********************************************************/
-unsigned int epicTmCountGet( ULONG srcAddr, unsigned int *val )
-{
- *val = sysEUMBBARRead( srcAddr );
- *val = *val & 0x7fffffff;
- return 0;
-}
-
-
-/***********************************************************
- * function: epicTmInhibit
- *
- * description: Stop counting of a given global timer
- * return 0 if no error, otherwise return 1
- *
- * note:
- ***********************************************************/
-unsigned int epicTmInhibit( unsigned int srcAddr )
-{
- ULONG val;
-
- val = sysEUMBBARRead( srcAddr );
- val |= 0x80000000;
- sysEUMBBARWrite( srcAddr, val );
- return 0;
-}
-
-/******************************************************************
- * function: epicTmEnable
- *
- * description: Enable counting of a given global timer
- * return 0 if no error, otherwise return 1
- *
- * note:
- *****************************************************************/
-unsigned int epicTmEnable( ULONG srcAddr )
-{
- ULONG val;
-
- val = sysEUMBBARRead( srcAddr );
- val &= 0x7fffffff;
- sysEUMBBARWrite( srcAddr, val );
- return 0;
-}
-
-void epicSourcePrint(int Vect)
- {
- ULONG srcVal;
-
- srcVal = sysEUMBBARRead(SrcVecTable[Vect].srcAddr);
- PRINT("%s\n", SrcVecTable[Vect].srcName);
- PRINT("Address = 0x%lx\n", SrcVecTable[Vect].srcAddr);
- PRINT("Vector = %ld\n", (srcVal & 0x000000FF) );
- PRINT("Mask = %ld\n", srcVal >> 31);
- PRINT("Activitiy = %ld\n", (srcVal & 40000000) >> 30);
- PRINT("Polarity = %ld\n", (srcVal & 0x00800000) >> 23);
- PRINT("Sense = %ld\n", (srcVal & 0x00400000) >> 22);
- PRINT("Priority = %ld\n", (srcVal & 0x000F0000) >> 16);
- }
diff --git a/arch/powerpc/cpu/mpc824x/drivers/epic/epic2.S b/arch/powerpc/cpu/mpc824x/drivers/epic/epic2.S
deleted file mode 100644
index 52d19aa..0000000
--- a/arch/powerpc/cpu/mpc824x/drivers/epic/epic2.S
+++ /dev/null
@@ -1,196 +0,0 @@
-/**************************************
- *
- * copyright @ Motorola, 1999
- *
- **************************************/
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-#include <asm/processor.h>
-
-/*********************************************
- * function: CoreExtIntEnable
- *
- * description: Enable 603e core external interrupt
- *
- * note: mtmsr is context-synchronization
- **********************************************/
- .text
- .align 2
- .global CoreExtIntEnable
-CoreExtIntEnable:
- mfmsr r3
-
- ori r3,r3,0x8000 /* enable external interrupt */
- mtmsr r3
-
- bclr 20, 0
-
-/*******************************************
- * function: CoreExtIntDisable
- *
- * description: Disable 603e core external interrupt
- *
- * note:
- *******************************************/
- .text
- .align 2
- .global CoreExtIntDisable
-CoreExtIntDisable:
- mfmsr r4
-
- xor r3,r3,r3
- or r3,r3,r4
-
- andis. r4,r4,0xffff
- andi. r3,r3,0x7fff /* disable external interrupt */
-
- or r3,r3,r4
- mtmsr r3
-
- bclr 20, 0
-
-/*********************************************************
- * function: epicEOI
- *
- * description: signal the EOI and restore machine status
- * Input: r3 - value of eumbbar
- * Output: r3 - value of eumbbar
- * r4 - ISR vector value
- * note:
- ********************************************************/
- .text
- .align 2
- .global epicEOI
-epicEOI:
- lis r5,0x0006 /* Build End Of Interrupt Register offset */
- ori r5,r5,0x00b0
- xor r7,r7,r7 /* Clear r7 */
- stwbrx r7,r5,r3 /* Save r7, writing to this register will
- * intidate the end of processing the
- * highest interrupt.
- */
- sync
-
- /* ---RESTORE MACHINE STATE */
- mfmsr r13 /* Clear Recoverable Interrupt bit in MSR */
- or r7,r7,r13
-
- andis. r7,r7,0xffff
- andi. r13,r13,0x7ffd /* (and disable interrupts) */
- or r13,r13,r7
- mtmsr r13
-
- lwz r13,0x1c(r1) /* pull ctr */
- mtctr r13
-
- lwz r13,0x18(r1) /* pull xer */
- mtctr r13
-
- lwz r13,0x14(r1) /* pull lr */
- mtctr r13
-
- lwz r13,0x10(r1) /* Pull SRR1 from stack */
- mtspr SRR1,r13 /* Restore SRR1 */
-
- lwz r13,0xc(r1) /* Pull SRR0 from stack */
- mtspr SRR0,r13 /* Restore SRR0 */
-
- lwz r13,0x8(r1) /* Pull User stack pointer from stack */
- mtspr SPRG1,r13 /* Restore SPRG1 */
-
- lwz r4,0x4(r1) /* vector value */
- lwz r3,0x0(r1) /* eumbbar */
- sync
-
- addi r1,r1,0x20 /* Deallocate stack */
- mtspr SPRG0,r1 /* Save updated Supervisor stack pointer */
- mfspr r1,SPRG1 /* Restore User stack pointer */
-
- bclr 20,0
-
-/***********************************************************
- * function: exception routine called by exception vector
- * at 0x500, external interrupt
- *
- * description: Kahlua EPIC controller
- *
- * input: r3 - content of eumbbar
- * output: r3 - ISR return value
- * r4 - Interrupt vector number
- * note:
- ***********************************************************/
-
- .text
- .align 2
- .global epic_exception
-
-epic_exception:
-
- /*---SAVE MACHINE STATE TO A STACK */
- mtspr SPRG1,r1 /* Save User stack pointer to SPRG1 */
- mfspr r1,SPRG0 /* Load Supervisor stack pointer into r1 */
-
- stwu r3,-0x20(r1) /* Push the value of eumbbar onto stack */
-
- mfspr r3,SPRG1 /* Push User stack pointer onto stack */
- stw r3,0x8(r1)
- mfspr r3,SRR0 /* Push SRR0 onto stack */
- stw r1,0xc(r1)
- mfspr r3,SRR1 /* Push SRR1 onto stack */
- stw r3,0x10(r1)
- mflr r3
- stw r3,0x14(r1) /* Push LR */
- mfxer r3
- stw r3,0x18(r1) /* Push Xer */
- mfctr r3
- stw r3,0x1c(r1) /* Push CTR */
-
- mtspr SPRG0,r1 /* Save updated Supervisor stack pointer
- * value to SPRG0
- */
- mfmsr r3
- ori r3,r3,0x0002 /* Set Recoverable Interrupt bit in MSR */
- mtmsr r3
-
- /* ---READ IN THE EUMBAR REGISTER */
- lwz r6,0(r1) /* this is eumbbar */
- sync
-
- /* ---READ EPIC REGISTER: PROCESSOR INTERRUPT ACKNOWLEDGE REGISTER */
- lis r5,0x0006 /* Build Interrupt Acknowledge Register
- * offset
- */
- ori r5,r5,0x00a0
- lwbrx r7,r5,r6 /* Load interrupt vector into r7 */
- sync
-
- /* --MASK OFF ALL BITS EXCEPT THE VECTOR */
- xor r3,r3,r3
- xor r4,r4,r4
- or r3, r3, r6 /* eumbbar in r3 */
- andi. r4,r7,0x00ff /* Mask off bits, vector in r4 */
-
- stw r4,0x04(r1) /* save the vector value */
-
- lis r5,epicISR at ha
- ori r5,r5,epicISR at l
- mtlr r5
- blrl
-
- xor r30,r30,r30
- or r30,r30,r3 /* save the r3 which containts the return value from epicISR */
-
- /* ---READ IN THE EUMBAR REGISTER */
- lwz r3,0(r1)
- sync
-
- lis r5,epicEOI at ha
- ori r5,r5,epicEOI at l
- mtlr r5
- blrl
-
- xor r3,r3,r3
- or r3,r3,r30 /* restore the ISR return value */
-
- bclr 20,0
diff --git a/arch/powerpc/cpu/mpc824x/drivers/epic/epicutil.S b/arch/powerpc/cpu/mpc824x/drivers/epic/epicutil.S
deleted file mode 100644
index 4877050..0000000
--- a/arch/powerpc/cpu/mpc824x/drivers/epic/epicutil.S
+++ /dev/null
@@ -1,57 +0,0 @@
-/**************************************
- *
- * copyright @ Motorola, 1999
- *
- *
- * This file contains two commonly used
- * lower level utility routines.
- *
- * The utility routines are also in other
- * Kahlua device driver libraries. The
- * need to be linked in only once.
- **************************************/
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-/**********************************************************
- * function: load_runtime_reg
- *
- * input: r3 - value of eumbbar
- * r4 - register offset in embedded utility space
- *
- * output: r3 - register content
- **********************************************************/
- .text
- .align 2
- .global load_runtime_reg
-
-load_runtime_reg:
-
- xor r5,r5,r5
- or r5,r5,r3 /* save eumbbar */
-
- lwbrx r3,r4,r5
- sync
-
- bclr 20, 0
-
-/****************************************************************
- * function: store_runtime_reg
- *
- * input: r3 - value of eumbbar
- * r4 - register offset in embedded utility space
- * r5 - new value to be stored
- *
- ****************************************************************/
- .text
- .align 2
- .global store_runtime_reg
-store_runtime_reg:
-
- xor r0,r0,r0
-
- stwbrx r5, r4, r3
- sync
-
- bclr 20,0
diff --git a/arch/powerpc/cpu/mpc824x/drivers/errors.h b/arch/powerpc/cpu/mpc824x/drivers/errors.h
deleted file mode 100644
index 20794a2..0000000
--- a/arch/powerpc/cpu/mpc824x/drivers/errors.h
+++ /dev/null
@@ -1,212 +0,0 @@
-/* Copyright Motorola, Inc. 1993, 1994
- ALL RIGHTS RESERVED
-
- You are hereby granted a copyright license to use, modify, and
- distribute the SOFTWARE so long as this entire notice is retained
- without alteration in any modified and/or redistributed versions,
- and that such modified versions are clearly identified as such.
- No licenses are granted by implication, estoppel or otherwise under
- any patents or trademarks of Motorola, Inc.
-
- The SOFTWARE is provided on an "AS IS" basis and without warranty.
- To the maximum extent permitted by applicable law, MOTOROLA DISCLAIMS
- ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING IMPLIED
- WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR
- PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH
- REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS
- THEREOF) AND ANY ACCOMPANYING WRITTEN MATERIALS.
-
- To the maximum extent permitted by applicable law, IN NO EVENT SHALL
- MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER
- (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF
- BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS
- INFORMATION, OR OTHER PECUNIARY LOSS) ARISING OF THE USE OR
- INABILITY TO USE THE SOFTWARE. Motorola assumes no responsibility
- for the maintenance and support of the SOFTWARE.
-
-*/
-
-
-#include "config.h"
-
-/*
- 1 2 3 4 5 6 7 8
-01234567890123456789012345678901234567890123456789012345678901234567890123456789
-*/
-/* List define statements here */
-
-/* These are for all the toolboxes and functions to use. These will help
-to standardize the error handling in the current project */
-
- /* this is the "data type" for the error
- messages in the system */
-#define STATUS unsigned int
-
- /* this is a success status code */
-#define SUCCESS 1
-
- /* likewise this is failure */
-#define FAILURE 0
-
-#define NUM_ERRORS 47
-
-/* This first section of "defines" are for error codes ONLY. The called
- routine will return one of these error codes to the caller. If the final
- returned code is "VALID", then everything is a-okay. However, if one
- of the functions returns a non-valid status, that error code should be
- propogated back to all the callers. At the end, the last caller will
- call an error_processing function, and send in the status which was
- returned. It's up to the error_processing function to determine which
- error occured (as indicated by the status), and print an appropriate
- message back to the user.
-*/
-/*----------------------------------------------------------------------*/
-/* these are specifically for the parser routines */
-
-#define UNKNOWN_COMMAND 0xfb00 /* "unrecognized command " */
-#define UNKNOWN_REGISTER 0xfb01 /* "unknown register "*/
-#define ILLEGAL_RD_STAGE 0xfb02 /* cannot specify reg. family in range*/
-#define ILLEGAL_REG_FAMILY 0xfb03 /* "cannot specify a range of special
- or miscellaneous registers"*/
-#define RANGE_CROSS_FAMILY 0xfb04 /* "cannot specify a range across
- register families" */
-#define UNIMPLEMENTED_STAGE 0xfb05 /* invalid rd or rmm parameter format */
-#define REG_NOT_WRITEABLE 0xfb06 /* "unknown operator in arguements"*/
-#define INVALID_FILENAME 0xfb07 /* "invalid download filename" */
-#define INVALID_BAUD_RATE 0xfb08 /* invalid baud rate from sb command */
-#define UNSUPPORTED_REGISTER 0xfb09 /* Special register is not supported */
-#define FOR_BOARD_ONLY 0xfb0a /* "Not available for Unix." */
-
-
-/*----------------------------------------------------------------------*/
-/* these are for the error checking toolbox */
-
-#define INVALID 0xfd00 /* NOT valid */
-#define VALID 0xfd01 /* valid */
-
- /* This error is found in the fcn:
- is_right_size_input() to indicate
- that the input was not 8 characters
- long. */
-#define INVALID_SIZE 0xfd02
-
- /* This error is found in the fcn:
- is_valid_address_range() to indicate
- that the address given falls outside
- of valid memory defined by MEM_START
- to MEM_END.
- */
-#define OUT_OF_BOUNDS_ADDRESS 0xfd03
-
- /* This error is found in the fcn:
- is_valid_hex_input() to indicate that
- one of more of the characters entered
- are not valid hex characters. Valid
- hex characters are 0-9, A-F, a-f.
- */
-#define INVALID_HEX_INPUT 0xfd04
-
- /* This error is found in the fcn:
- is_valid_register_number() to indicate
- that a given register does not exist.
- */
-#define REG_NOT_READABLE 0xfd05
-
- /* This error is found in the fcn:
- is_word_aligned_address() to indicate
- that the given address is not word-
- aligned. A word-aligned address ends
- in 0x0,0x4,0x8,0xc.
- */
-#define NOT_WORD_ALIGNED 0xfd07
-
- /* This error is found in the fcn:
- is_valid_address_range() to indicate
- that the starting address is greater
- than the ending address.
- */
-#define REVERSED_ADDRESS 0xfd08
-
- /* this error tells us that the address
- specified as the destination is within
- the source addresses */
-#define RANGE_OVERLAP 0xfd09
-
-
-#define ERROR 0xfd0a /* An error occured */
-#define INVALID_PARAM 0xfd0b /* "invalid input parameter " */
-
-
-#define INVALID_FLAG 0xfd0c /* invalid flag */
-
-/*----------------------------------------------------------------------*/
-/* these are for the getarg toolbox */
-
-#define INVALID_NUMBER_ARGS 0xFE00 /* invalid number of commd arguements */
-#define UNKNOWN_PARAMETER 0xFE01 /* "unknown type of parameter "*/
-
-
-/*----------------------------------------------------------------------*/
-/* these are for the tokenizer toolbox */
-
-#define ILLEGAL_CHARACTER 0xFF00 /* unrecognized char. in input stream*/
-#define TTL_NOT_SORTED 0xFF01 /* token translation list not sorted */
-#define TTL_NOT_DEFINED 0xFF02 /* token translation list not assigned*/
-#define INVALID_STRING 0xFF03 /* unable to extract string from input */
-#define BUFFER_EMPTY 0xFF04 /* "input buffer is empty" */
-#define INVALID_MODE 0xFF05 /* input buf is in an unrecognized mode*/
-#define TOK_INTERNAL_ERROR 0xFF06 /* "internal tokenizer error" */
-#define TOO_MANY_IBS 0xFF07 /* "too many open input buffers" */
-#define NO_OPEN_IBS 0xFF08 /* "no open input buffers" */
-
-
-/* these are for the read from screen toolbox */
-
-#define RESERVED_WORD 0xFC00 /* used a reserved word as an arguement*/
-
-
-/* these are for the breakpoint routines */
-
-#define FULL_BPDS 0xFA00 /* breakpoint data structure is full */
-
-
-/* THESE are for the downloader */
-
-#define NOT_IN_S_RECORD_FORMAT 0xf900 /* "not in S-Record Format" */
-#define UNREC_RECORD_TYPE 0xf901 /* "unrecognized record type" */
-#define CONVERSION_ERROR 0xf902 /* "ascii to int conversion error" */
-#define INVALID_MEMORY 0xf903 /* "bad s-record memory address " */
-
-
-/* these are for the compression and decompression stuff */
-
-#define COMP_UNK_CHARACTER 0xf800 /* "unknown compressed character " */
-
-#define COMP_UNKNOWN_STATE 0xf801 /* "unknown binary state" */
-
-#define NOT_IN_COMPRESSED_FORMAT 0xf802 /* not in compressed S-Record format */
-
-
-/* these are for the DUART handling things */
-
- /* "unrecognized serial port configuration" */
-#define UNKNOWN_PORT_STATE 0xf700
-
-
-/* these are for the register toolbox */
-
- /* "cannot find register in special
- purpose register file " */
-#define SPR_NOT_FOUND 0xf600
-
-
-/* these are for the duart specific stuff */
-
- /* "transparent mode needs access to
- two serial ports" */
-#define TM_NEEDS_BOTH_PORTS 0xf500
-
-
-/*----------------------------------------------------------------------*/
-/* these are specifically for the flash routines */
-#define FLASH_ERROR 0xf100 /* general flash error */
diff --git a/arch/powerpc/cpu/mpc824x/drivers/i2c/i2c.c b/arch/powerpc/cpu/mpc824x/drivers/i2c/i2c.c
deleted file mode 100644
index 3638ab0..0000000
--- a/arch/powerpc/cpu/mpc824x/drivers/i2c/i2c.c
+++ /dev/null
@@ -1,254 +0,0 @@
-/*
- * (C) Copyright 2003
- * Gleb Natapov <gnatapov@mrv.com>
- * Some bits are taken from linux driver writen by adrian at humboldt.co.uk
- *
- * Hardware I2C driver for MPC107 PCI bridge.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-#undef I2CDBG
-
-#ifdef CONFIG_HARD_I2C
-#include <i2c.h>
-
-#define TIMEOUT (CONFIG_SYS_HZ/4)
-
-#define I2C_Addr ((unsigned *)(CONFIG_SYS_EUMB_ADDR + 0x3000))
-
-#define I2CADR &I2C_Addr[0]
-#define I2CFDR &I2C_Addr[1]
-#define I2CCCR &I2C_Addr[2]
-#define I2CCSR &I2C_Addr[3]
-#define I2CCDR &I2C_Addr[4]
-
-#define MPC107_CCR_MEN 0x80
-#define MPC107_CCR_MIEN 0x40
-#define MPC107_CCR_MSTA 0x20
-#define MPC107_CCR_MTX 0x10
-#define MPC107_CCR_TXAK 0x08
-#define MPC107_CCR_RSTA 0x04
-
-#define MPC107_CSR_MCF 0x80
-#define MPC107_CSR_MAAS 0x40
-#define MPC107_CSR_MBB 0x20
-#define MPC107_CSR_MAL 0x10
-#define MPC107_CSR_SRW 0x04
-#define MPC107_CSR_MIF 0x02
-#define MPC107_CSR_RXAK 0x01
-
-#define I2C_READ 1
-#define I2C_WRITE 0
-
-/* taken from linux include/asm-ppc/io.h */
-inline unsigned in_le32 (volatile unsigned *addr)
-{
- unsigned ret;
-
- __asm__ __volatile__ ("lwbrx %0,0,%1;\n"
- "twi 0,%0,0;\n"
- "isync":"=r" (ret): "r" (addr), "m" (*addr));
- return ret;
-}
-
-inline void out_le32 (volatile unsigned *addr, int val)
-{
- __asm__ __volatile__ ("stwbrx %1,0,%2; eieio":"=m" (*addr):"r" (val),
- "r" (addr));
-}
-
-#define writel(val, addr) out_le32(addr, val)
-#define readl(addr) in_le32(addr)
-
-void i2c_init (int speed, int slaveadd)
-{
- /* stop I2C controller */
- writel (0x0, I2CCCR);
- /* set clock */
- writel (0x1020, I2CFDR);
- /* write slave address */
- writel (slaveadd, I2CADR);
- /* clear status register */
- writel (0x0, I2CCSR);
- /* start I2C controller */
- writel (MPC107_CCR_MEN, I2CCCR);
-
- return;
-}
-
-static __inline__ int i2c_wait4bus (void)
-{
- ulong timeval = get_timer (0);
-
- while (readl (I2CCSR) & MPC107_CSR_MBB)
- if (get_timer (timeval) > TIMEOUT)
- return -1;
-
- return 0;
-}
-
-static __inline__ int i2c_wait (int write)
-{
- u32 csr;
- ulong timeval = get_timer (0);
-
- do {
- csr = readl (I2CCSR);
-
- if (!(csr & MPC107_CSR_MIF))
- continue;
-
- writel (0x0, I2CCSR);
-
- if (csr & MPC107_CSR_MAL) {
-#ifdef I2CDBG
- printf ("i2c_wait: MAL\n");
-#endif
- return -1;
- }
-
- if (!(csr & MPC107_CSR_MCF)) {
-#ifdef I2CDBG
- printf ("i2c_wait: unfinished\n");
-#endif
- return -1;
- }
-
- if (write == I2C_WRITE && (csr & MPC107_CSR_RXAK)) {
-#ifdef I2CDBG
- printf ("i2c_wait: No RXACK\n");
-#endif
- return -1;
- }
-
- return 0;
- } while (get_timer (timeval) < TIMEOUT);
-
-#ifdef I2CDBG
- printf ("i2c_wait: timed out\n");
-#endif
- return -1;
-}
-
-static __inline__ int i2c_write_addr (u8 dev, u8 dir, int rsta)
-{
- writel (MPC107_CCR_MEN | MPC107_CCR_MSTA | MPC107_CCR_MTX |
- (rsta ? MPC107_CCR_RSTA : 0), I2CCCR);
-
- writel ((dev << 1) | dir, I2CCDR);
-
- if (i2c_wait (I2C_WRITE) < 0)
- return 0;
-
- return 1;
-}
-
-static __inline__ int __i2c_write (u8 * data, int length)
-{
- int i;
-
- writel (MPC107_CCR_MEN | MPC107_CCR_MSTA | MPC107_CCR_MTX, I2CCCR);
-
- for (i = 0; i < length; i++) {
- writel (data[i], I2CCDR);
-
- if (i2c_wait (I2C_WRITE) < 0)
- break;
- }
-
- return i;
-}
-
-static __inline__ int __i2c_read (u8 * data, int length)
-{
- int i;
-
- writel (MPC107_CCR_MEN | MPC107_CCR_MSTA |
- ((length == 1) ? MPC107_CCR_TXAK : 0), I2CCCR);
-
- /* dummy read */
- readl (I2CCDR);
-
- for (i = 0; i < length; i++) {
- if (i2c_wait (I2C_READ) < 0)
- break;
-
- /* Generate ack on last next to last byte */
- if (i == length - 2)
- writel (MPC107_CCR_MEN | MPC107_CCR_MSTA |
- MPC107_CCR_TXAK, I2CCCR);
-
- /* Generate stop on last byte */
- if (i == length - 1)
- writel (MPC107_CCR_MEN | MPC107_CCR_TXAK, I2CCCR);
-
- data[i] = readl (I2CCDR);
- }
-
- return i;
-}
-
-int i2c_read (u8 dev, uint addr, int alen, u8 * data, int length)
-{
- int i = 0;
- u8 *a = (u8 *) & addr;
-
- if (i2c_wait4bus () < 0)
- goto exit;
-
- if (i2c_write_addr (dev, I2C_WRITE, 0) == 0)
- goto exit;
-
- if (__i2c_write (&a[4 - alen], alen) != alen)
- goto exit;
-
- if (i2c_write_addr (dev, I2C_READ, 1) == 0)
- goto exit;
-
- i = __i2c_read (data, length);
-
-exit:
- writel (MPC107_CCR_MEN, I2CCCR);
-
- return !(i == length);
-}
-
-int i2c_write (u8 dev, uint addr, int alen, u8 * data, int length)
-{
- int i = 0;
- u8 *a = (u8 *) & addr;
-
- if (i2c_wait4bus () < 0)
- goto exit;
-
- if (i2c_write_addr (dev, I2C_WRITE, 0) == 0)
- goto exit;
-
- if (__i2c_write (&a[4 - alen], alen) != alen)
- goto exit;
-
- i = __i2c_write (data, length);
-
-exit:
- writel (MPC107_CCR_MEN, I2CCCR);
-
- return !(i == length);
-}
-
-int i2c_probe (uchar chip)
-{
- int tmp;
-
- /*
- * Try to read the first location of the chip. The underlying
- * driver doesn't appear to support sending just the chip address
- * and looking for an <ACK> back.
- */
- udelay (10000);
- return i2c_read (chip, 0, 1, (uchar *) &tmp, 1);
-}
-
-#endif /* CONFIG_HARD_I2C */
diff --git a/arch/powerpc/cpu/mpc824x/interrupts.c b/arch/powerpc/cpu/mpc824x/interrupts.c
deleted file mode 100644
index fad103f..0000000
--- a/arch/powerpc/cpu/mpc824x/interrupts.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * (C) Copyright 2000-2002
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- * Rob Taylor, Flying Pig Systems. robt at flyingpig.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc824x.h>
-#include <asm/processor.h>
-#include <asm/pci_io.h>
-#include <commproc.h>
-#include "drivers/epic.h"
-
-int interrupt_init_cpu (unsigned *decrementer_count)
-{
- *decrementer_count = (get_bus_freq (0) / 4) / CONFIG_SYS_HZ;
-
- /*
- * It's all broken at the moment and I currently don't need
- * interrupts. If you want to fix it, have a look at the epic
- * drivers in dink32 v12. They do everthing and Motorola said
- * I could use the dink source in this project as long as
- * copyright notices remain intact.
- */
-
- epicInit (EPIC_DIRECT_IRQ, 0);
- /* EPIC won't generate INT unless Current Task Pri < 15 */
- epicCurTaskPrioSet(0);
-
- return (0);
-}
-
-/****************************************************************************/
-
-/*
- * Handle external interrupts
- */
-void external_interrupt (struct pt_regs *regs)
-{
- register unsigned long temp;
-
- pci_readl (CONFIG_SYS_EUMB_ADDR + EPIC_PROC_INT_ACK_REG, temp);
- sync (); /* i'm not convinced this is needed, but dink source has it */
- temp &= 0xff; /*get vector */
-
- /*TODO: handle them -... */
- epicEOI ();
-}
-
-/****************************************************************************/
-
-/*
- * blank int handlers.
- */
-
-void
-irq_install_handler (int vec, interrupt_handler_t * handler, void *arg)
-{
-}
-
-void irq_free_handler (int vec)
-{
-
-}
-
-/*TODO: some handlers for winbond and 87308 interrupts
- and what about generic pci inteerupts?
- vga?
- */
-
-void timer_interrupt_cpu (struct pt_regs *regs)
-{
- /* nothing to do here */
- return;
-}
diff --git a/arch/powerpc/cpu/mpc824x/pci.c b/arch/powerpc/cpu/mpc824x/pci.c
deleted file mode 100644
index 1257b08..0000000
--- a/arch/powerpc/cpu/mpc824x/pci.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * arch/powerpc/kernel/mpc10x_common.c
- *
- * Common routines for the Motorola SPS MPC106, MPC107 and MPC8240 Host bridge,
- * Mem ctlr, EPIC, etc.
- *
- * Author: Mark A. Greer
- * mgreer@mvista.com
- *
- * Copyright 2001 MontaVista Software Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-#ifdef CONFIG_PCI
-
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <pci.h>
-#include <mpc824x.h>
-
-void pci_mpc824x_init (struct pci_controller *hose)
-{
- hose->first_busno = 0;
- hose->last_busno = 0xff;
-
- /* System memory space */
- pci_set_region(hose->regions + 0,
- CHRP_PCI_MEMORY_BUS,
- CHRP_PCI_MEMORY_PHYS,
- CHRP_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-
- /* PCI memory space */
- pci_set_region(hose->regions + 1,
- CHRP_PCI_MEM_BUS,
- CHRP_PCI_MEM_PHYS,
- CHRP_PCI_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* ISA/PCI memory space */
- pci_set_region(hose->regions + 2,
- CHRP_ISA_MEM_BUS,
- CHRP_ISA_MEM_PHYS,
- CHRP_ISA_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* PCI I/O space */
- pci_set_region(hose->regions + 3,
- CHRP_PCI_IO_BUS,
- CHRP_PCI_IO_PHYS,
- CHRP_PCI_IO_SIZE,
- PCI_REGION_IO);
-
- /* ISA/PCI I/O space */
- pci_set_region(hose->regions + 4,
- CHRP_ISA_IO_BUS,
- CHRP_ISA_IO_PHYS,
- CHRP_ISA_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = 5;
-
- pci_setup_indirect(hose,
- CHRP_REG_ADDR,
- CHRP_REG_DATA);
-
- pci_register_hose(hose);
-
- hose->last_busno = pci_hose_scan(hose);
-}
-
-#endif
diff --git a/arch/powerpc/cpu/mpc824x/speed.c b/arch/powerpc/cpu/mpc824x/speed.c
deleted file mode 100644
index e6064a1..0000000
--- a/arch/powerpc/cpu/mpc824x/speed.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * (C) Copyright 2002
- * Gregory E. Allen, gallen at arlut.utexas.edu
- * Applied Research Laboratories, The University of Texas at Austin
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc824x.h>
-#include <asm/processor.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* ------------------------------------------------------------------------- */
-/* NOTE: This describes the proper use of this file.
- *
- * CONFIG_SYS_CLK_FREQ should be defined as the input frequency on
- * PCI_SYNC_IN .
- *
- * CONFIG_PLL_PCI_TO_MEM_MULTIPLIER is only required on MPC8240
- * boards. It should be defined as the PCI to Memory Multiplier as
- * documented in the MPC8240 Hardware Specs.
- *
- * Other mpc824x boards don't need CONFIG_PLL_PCI_TO_MEM_MULTIPLIER
- * because they can determine it from the PCR.
- *
- * Gary Milliorn <gary.milliorn@motorola.com> (who should know since
- * he designed the Sandpoint) told us that the PCR is not in all revs
- * of the MPC8240 CPU, so it's not guaranteeable and we cannot do
- * away with CONFIG_PLL_PCI_TO_MEM_MULTIPLIER altogether.
- */
-/* ------------------------------------------------------------------------- */
-
-/* This gives the PCI to Memory multiplier times 10 */
-/* The index is the value of PLL_CFG[0:4] */
-/* This is documented in the MPC8240/5 Hardware Specs */
-
-short pll_pci_to_mem_multiplier[] = {
-#if defined(CONFIG_MPC8240)
- 30, 30, 10, 10, 20, 10, 0, 10,
- 10, 0, 20, 0, 20, 0, 20, 0,
- 30, 0, 15, 0, 20, 0, 20, 0,
- 25, 0, 10, 0, 15, 15, 0, 0,
-#elif defined(CONFIG_MPC8245)
- 30, 30, 10, 10, 20, 10, 10, 10,
- 10, 20, 20, 15, 20, 15, 20, 30,
- 30, 40, 15, 40, 20, 25, 20, 40,
- 25, 20, 10, 20, 15, 15, 15, 0,
-#else
-#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
-#endif
-};
-
-#define CU824_PLL_STATE_REG 0xFE80002F
-#define PCR 0x800000E2
-
-/* ------------------------------------------------------------------------- */
-
-/* compute the memory bus clock frequency */
-ulong get_bus_freq (ulong dummy)
-{
- unsigned char pll_cfg;
-#if defined(CONFIG_MPC8240) && !defined(CONFIG_CU824)
- return (CONFIG_SYS_CLK_FREQ) * (CONFIG_PLL_PCI_TO_MEM_MULTIPLIER);
-#elif defined(CONFIG_CU824)
- pll_cfg = *(volatile unsigned char *) (CU824_PLL_STATE_REG);
- pll_cfg &= 0x1f;
-#else
- CONFIG_READ_BYTE(PCR, pll_cfg);
- pll_cfg = (pll_cfg >> 3) & 0x1f;
-#endif
- return ((CONFIG_SYS_CLK_FREQ) * pll_pci_to_mem_multiplier[pll_cfg] + 5) / 10;
-}
-
-
-/* ------------------------------------------------------------------------- */
-
-/* This gives the Memory to CPU Core multiplier times 10 */
-/* The index is the value of PLLRATIO in HID1 */
-/* This is documented in the MPC8240 Hardware Specs */
-/* This is not documented for MPC8245 ? FIXME */
-short pllratio_to_factor[] = {
- 0, 0, 0, 10, 20, 20, 25, 45,
- 30, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 10, 0, 0, 0, 45,
- 30, 0, 40, 0, 0, 0, 35, 0,
-};
-
-/* compute the CPU and memory bus clock frequencies */
-int get_clocks (void)
-{
- uint hid1 = mfspr(HID1);
- hid1 = (hid1 >> (32-5)) & 0x1f;
- gd->cpu_clk = (pllratio_to_factor[hid1] * get_bus_freq(0) + 5)
- / 10;
- gd->bus_clk = get_bus_freq(0);
- return (0);
-}
diff --git a/arch/powerpc/cpu/mpc824x/start.S b/arch/powerpc/cpu/mpc824x/start.S
deleted file mode 100644
index 55238df..0000000
--- a/arch/powerpc/cpu/mpc824x/start.S
+++ /dev/null
@@ -1,724 +0,0 @@
-/*
- * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
- * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
- * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* U-Boot - Startup Code for PowerPC based Embedded Boards
- *
- *
- * The processor starts at 0x00000100 and the code is executed
- * from flash. The code is organized to be at an other address
- * in memory, but as long we don't jump around before relocating.
- * board_init lies at a quite high address and when the cpu has
- * jumped there, everything is ok.
- * This works because the cpu gives the FLASH (CS0) the whole
- * address space at startup, and board_init lies as a echo of
- * the flash somewhere up there in the memorymap.
- *
- * board_init will change CS0 to be positioned at the correct
- * address and (s)dram will be positioned at address 0
- */
-#include <asm-offsets.h>
-#include <config.h>
-#include <mpc824x.h>
-#include <version.h>
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-#include <asm/u-boot.h>
-
-/* We don't want the MMU yet.
-*/
-#undef MSR_KERNEL
-/* FP, Machine Check and Recoverable Interr. */
-#define MSR_KERNEL ( MSR_FP | MSR_ME | MSR_RI )
-
-/*
- * Set up GOT: Global Offset Table
- *
- * Use r12 to access the GOT
- */
- START_GOT
- GOT_ENTRY(_GOT2_TABLE_)
- GOT_ENTRY(_FIXUP_TABLE_)
-
- GOT_ENTRY(_start)
- GOT_ENTRY(_start_of_vectors)
- GOT_ENTRY(_end_of_vectors)
- GOT_ENTRY(transfer_to_handler)
-
- GOT_ENTRY(__init_end)
- GOT_ENTRY(__bss_end)
- GOT_ENTRY(__bss_start)
- END_GOT
-
-/*
- * r3 - 1st arg to board_init(): IMMP pointer
- * r4 - 2nd arg to board_init(): boot flag
- */
- .text
- .long 0x27051956 /* U-Boot Magic Number */
- .globl version_string
-version_string:
- .ascii U_BOOT_VERSION_STRING, "\0"
-
- . = EXC_OFF_SYS_RESET
- .globl _start
-_start:
- /* Initialize machine status; enable machine check interrupt */
- /*----------------------------------------------------------------------*/
- li r3, MSR_KERNEL /* Set FP, ME, RI flags */
- mtmsr r3
- mtspr SRR1, r3 /* Make SRR1 match MSR */
-
- addis r0,0,0x0000 /* lets make sure that r0 is really 0 */
- mtspr HID0, r0 /* disable I and D caches */
-
- mfspr r3, ICR /* clear Interrupt Cause Register */
-
- mfmsr r3 /* turn off address translation */
- addis r4,0,0xffff
- ori r4,r4,0xffcf
- and r3,r3,r4
- mtmsr r3
- isync
- sync /* the MMU should be off... */
-
-
-in_flash:
- /*
- * Setup BATs - cannot be done in C since we don't have a stack yet
- */
- bl setup_bats
-
- /* Enable MMU.
- */
- mfmsr r3
- ori r3, r3, (MSR_IR | MSR_DR)
- mtmsr r3
-
- /* Enable and invalidate data cache.
- */
- mfspr r3, HID0
- mr r2, r3
- ori r3, r3, HID0_DCE | HID0_DCI
- ori r2, r2, HID0_DCE
- sync
- mtspr HID0, r3
- mtspr HID0, r2
- sync
-
- /* Allocate Initial RAM in data cache.
- */
- lis r3, CONFIG_SYS_INIT_RAM_ADDR at h
- ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR at l
- li r2, 128
- mtctr r2
-1:
- dcbz r0, r3
- addi r3, r3, 32
- bdnz 1b
-
- /* Lock way0 in data cache.
- */
- mfspr r3, 1011
- lis r2, 0xffff
- ori r2, r2, 0xff1f
- and r3, r3, r2
- ori r3, r3, 0x0080
- sync
- mtspr 1011, r3
-
- /*
- * Thisk the stack pointer *somewhere* sensible. Doesnt
- * matter much where as we'll move it when we relocate
- */
- lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
- ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
-
- li r0, 0 /* Make room for stack frame header and */
- stwu r0, -4(r1) /* clear final stack frame so that */
- stwu r0, -4(r1) /* stack backtraces terminate cleanly */
-
- /* let the C-code set up the rest */
- /* */
- /* Be careful to keep code relocatable ! */
- /*----------------------------------------------------------------------*/
-
- GET_GOT /* initialize GOT access */
-
- /* r3: IMMR */
- bl cpu_init_f /* run low-level CPU init code (from Flash) */
-
- bl board_init_f /* run 1st part of board init code (from Flash) */
-
- /* NOTREACHED - board_init_f() does not return */
-
-
- .globl _start_of_vectors
-_start_of_vectors:
-
-/* Machine check */
- STD_EXCEPTION(EXC_OFF_MACH_CHCK, MachineCheck, MachineCheckException)
-
-/* Data Storage exception. "Never" generated on the 860. */
- STD_EXCEPTION(EXC_OFF_DATA_STOR, DataStorage, UnknownException)
-
-/* Instruction Storage exception. "Never" generated on the 860. */
- STD_EXCEPTION(EXC_OFF_INS_STOR, InstStorage, UnknownException)
-
-/* External Interrupt exception. */
- STD_EXCEPTION(EXC_OFF_EXTERNAL, ExtInterrupt, external_interrupt)
-
-/* Alignment exception. */
- . = EXC_OFF_ALIGN
-Alignment:
- EXCEPTION_PROLOG(SRR0, SRR1)
- mfspr r4,DAR
- stw r4,_DAR(r21)
- mfspr r5,DSISR
- stw r5,_DSISR(r21)
- addi r3,r1,STACK_FRAME_OVERHEAD
- EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
-
-/* Program check exception */
- . = EXC_OFF_PROGRAM
-ProgramCheck:
- EXCEPTION_PROLOG(SRR0, SRR1)
- addi r3,r1,STACK_FRAME_OVERHEAD
- EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
- MSR_KERNEL, COPY_EE)
-
- /* No FPU on MPC8xx. This exception is not supposed to happen.
- */
- STD_EXCEPTION(EXC_OFF_FPUNAVAIL, FPUnavailable, UnknownException)
-
- /* I guess we could implement decrementer, and may have
- * to someday for timekeeping.
- */
- STD_EXCEPTION(EXC_OFF_DECR, Decrementer, timer_interrupt)
- STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
- STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
- STD_EXCEPTION(0xc00, SystemCall, UnknownException)
-
- STD_EXCEPTION(EXC_OFF_TRACE, SingleStep, UnknownException)
-
- STD_EXCEPTION(EXC_OFF_FPUNASSIST, Trap_0e, UnknownException)
- STD_EXCEPTION(EXC_OFF_PMI, Trap_0f, UnknownException)
-
- STD_EXCEPTION(EXC_OFF_ITME, InstructionTransMiss, UnknownException)
- STD_EXCEPTION(EXC_OFF_DLTME, DataLoadTransMiss, UnknownException)
- STD_EXCEPTION(EXC_OFF_DSTME, DataStoreTransMiss, UnknownException)
- STD_EXCEPTION(EXC_OFF_IABE, InstructionBreakpoint, DebugException)
- STD_EXCEPTION(EXC_OFF_SMIE, SysManageInt, UnknownException)
- STD_EXCEPTION(0x1500, Reserved5, UnknownException)
- STD_EXCEPTION(0x1600, Reserved6, UnknownException)
- STD_EXCEPTION(0x1700, Reserved7, UnknownException)
- STD_EXCEPTION(0x1800, Reserved8, UnknownException)
- STD_EXCEPTION(0x1900, Reserved9, UnknownException)
- STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
- STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
- STD_EXCEPTION(0x1c00, ReservedC, UnknownException)
- STD_EXCEPTION(0x1d00, ReservedD, UnknownException)
- STD_EXCEPTION(0x1e00, ReservedE, UnknownException)
- STD_EXCEPTION(0x1f00, ReservedF, UnknownException)
-
- STD_EXCEPTION(EXC_OFF_RMTE, RunModeTrace, UnknownException)
-
- .globl _end_of_vectors
-_end_of_vectors:
-
-
- . = 0x3000
-
-/*
- * This code finishes saving the registers to the exception frame
- * and jumps to the appropriate handler for the exception.
- * Register r21 is pointer into trap frame, r1 has new stack pointer.
- */
- .globl transfer_to_handler
-transfer_to_handler:
- stw r22,_NIP(r21)
- lis r22,MSR_POW at h
- andc r23,r23,r22
- stw r23,_MSR(r21)
- SAVE_GPR(7, r21)
- SAVE_4GPRS(8, r21)
- SAVE_8GPRS(12, r21)
- SAVE_8GPRS(24, r21)
-#if 0
- andi. r23,r23,MSR_PR
- mfspr r23,SPRG3 /* if from user, fix up tss.regs */
- beq 2f
- addi r24,r1,STACK_FRAME_OVERHEAD
- stw r24,PT_REGS(r23)
-2: addi r2,r23,-TSS /* set r2 to current */
- tovirt(r2,r2,r23)
-#endif
- mflr r23
- andi. r24,r23,0x3f00 /* get vector offset */
- stw r24,TRAP(r21)
- li r22,0
- stw r22,RESULT(r21)
- mtspr SPRG2,r22 /* r1 is now kernel sp */
-#if 0
- addi r24,r2,TASK_STRUCT_SIZE /* check for kernel stack overflow */
- cmplw 0,r1,r2
- cmplw 1,r1,r24
- crand 1,1,4
- bgt stack_ovf /* if r2 < r1 < r2+TASK_STRUCT_SIZE */
-#endif
- lwz r24,0(r23) /* virtual address of handler */
- lwz r23,4(r23) /* where to go when done */
- mtspr SRR0,r24
- ori r20,r20,0x30 /* enable IR, DR */
- mtspr SRR1,r20
- mtlr r23
- SYNC
- rfi /* jump to handler, enable MMU */
-
-int_return:
- mfmsr r28 /* Disable interrupts */
- li r4,0
- ori r4,r4,MSR_EE
- andc r28,r28,r4
- SYNC /* Some chip revs need this... */
- mtmsr r28
- SYNC
- lwz r2,_CTR(r1)
- lwz r0,_LINK(r1)
- mtctr r2
- mtlr r0
- lwz r2,_XER(r1)
- lwz r0,_CCR(r1)
- mtspr XER,r2
- mtcrf 0xFF,r0
- REST_10GPRS(3, r1)
- REST_10GPRS(13, r1)
- REST_8GPRS(23, r1)
- REST_GPR(31, r1)
- lwz r2,_NIP(r1) /* Restore environment */
- lwz r0,_MSR(r1)
- mtspr SRR0,r2
- mtspr SRR1,r0
- lwz r0,GPR0(r1)
- lwz r2,GPR2(r1)
- lwz r1,GPR1(r1)
- SYNC
- rfi
-
-/* Cache functions.
-*/
- .globl icache_enable
-icache_enable:
- mfspr r5,HID0 /* turn on the I cache. */
- ori r5,r5,0x8800 /* Instruction cache only! */
- addis r6,0,0xFFFF
- ori r6,r6,0xF7FF
- and r6,r5,r6 /* clear the invalidate bit */
- sync
- mtspr HID0,r5
- mtspr HID0,r6
- isync
- sync
- blr
-
- .globl icache_disable
-icache_disable:
- mfspr r5,HID0
- addis r6,0,0xFFFF
- ori r6,r6,0x7FFF
- and r5,r5,r6
- sync
- mtspr HID0,r5
- isync
- sync
- blr
-
- .globl icache_status
-icache_status:
- mfspr r3, HID0
- srwi r3, r3, 15 /* >>15 & 1=> select bit 16 */
- andi. r3, r3, 1
- blr
-
- .globl dcache_enable
-dcache_enable:
- mfspr r5,HID0 /* turn on the D cache. */
- ori r5,r5,0x4400 /* Data cache only! */
- mfspr r4, PVR /* read PVR */
- srawi r3, r4, 16 /* shift off the least 16 bits */
- cmpi 0, 0, r3, 0xC /* Check for Max pvr */
- bne NotMax
- ori r5,r5,0x0040 /* setting the DCFA bit, for Max rev 1 errata */
-NotMax:
- addis r6,0,0xFFFF
- ori r6,r6,0xFBFF
- and r6,r5,r6 /* clear the invalidate bit */
- sync
- mtspr HID0,r5
- mtspr HID0,r6
- isync
- sync
- blr
-
- .globl dcache_disable
-dcache_disable:
- mfspr r5,HID0
- addis r6,0,0xFFFF
- ori r6,r6,0xBFFF
- and r5,r5,r6
- sync
- mtspr HID0,r5
- isync
- sync
- blr
-
- .globl dcache_status
-dcache_status:
- mfspr r3, HID0
- srwi r3, r3, 14 /* >>14 & 1=> select bit 17 */
- andi. r3, r3, 1
- blr
-
- .globl dc_read
-dc_read:
-/*TODO : who uses this, what should it do?
-*/
- blr
-
-
- .globl get_pvr
-get_pvr:
- mfspr r3, PVR
- blr
-
-
-/*------------------------------------------------------------------------------*/
-
-/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
- *
- * r3 = dest
- * r4 = src
- * r5 = length in bytes
- * r6 = cachelinesize
- */
- .globl relocate_code
-relocate_code:
-
- mr r1, r3 /* Set new stack pointer */
- mr r9, r4 /* Save copy of Global Data pointer */
- mr r10, r5 /* Save copy of Destination Address */
-
- GET_GOT
- mr r3, r5 /* Destination Address */
-#ifdef CONFIG_SYS_RAMBOOT
- lis r4, CONFIG_SYS_SDRAM_BASE at h /* Source Address */
- ori r4, r4, CONFIG_SYS_SDRAM_BASE at l
-#else
- lis r4, CONFIG_SYS_MONITOR_BASE at h /* Source Address */
- ori r4, r4, CONFIG_SYS_MONITOR_BASE at l
-#endif
- lwz r5, GOT(__init_end)
- sub r5, r5, r4
- li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
-
- /*
- * Fix GOT pointer:
- *
- * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
- *
- * Offset:
- */
- sub r15, r10, r4
-
- /* First our own GOT */
- add r12, r12, r15
- /* the the one used by the C code */
- add r30, r30, r15
-
- /*
- * Now relocate code
- */
-
- cmplw cr1,r3,r4
- addi r0,r5,3
- srwi. r0,r0,2
- beq cr1,4f /* In place copy is not necessary */
- beq 7f /* Protect against 0 count */
- mtctr r0
- bge cr1,2f
-
- la r8,-4(r4)
- la r7,-4(r3)
-1: lwzu r0,4(r8)
- stwu r0,4(r7)
- bdnz 1b
- b 4f
-
-2: slwi r0,r0,2
- add r8,r4,r0
- add r7,r3,r0
-3: lwzu r0,-4(r8)
- stwu r0,-4(r7)
- bdnz 3b
-
-4:
-/* Unlock the data cache and invalidate locked area */
- xor r0, r0, r0
- mtspr 1011, r0
- lis r4, CONFIG_SYS_INIT_RAM_ADDR at h
- ori r4, r4, CONFIG_SYS_INIT_RAM_ADDR at l
- li r0, 128
- mtctr r0
-41:
- dcbi r0, r4
- addi r4, r4, 32
- bdnz 41b
-
-/*
- * Now flush the cache: note that we must start from a cache aligned
- * address. Otherwise we might miss one cache line.
- */
- cmpwi r6,0
- add r5,r3,r5
- beq 7f /* Always flush prefetch queue in any case */
- subi r0,r6,1
- andc r3,r3,r0
- mr r4,r3
-5: dcbst 0,r4
- add r4,r4,r6
- cmplw r4,r5
- blt 5b
- sync /* Wait for all dcbst to complete on bus */
- mr r4,r3
-6: icbi 0,r4
- add r4,r4,r6
- cmplw r4,r5
- blt 6b
-7: sync /* Wait for all icbi to complete on bus */
- isync
-
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
-
- addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
- mtlr r0
- blr
-
-in_ram:
-
- /*
- * Relocation Function, r12 point to got2+0x8000
- *
- * Adjust got2 pointers, no need to check for 0, this code
- * already puts a few entries in the table.
- */
- li r0,__got2_entries at sectoff@l
- la r3,GOT(_GOT2_TABLE_)
- lwz r11,GOT(_GOT2_TABLE_)
- mtctr r0
- sub r11,r3,r11
- addi r3,r3,-4
-1: lwzu r0,4(r3)
- cmpwi r0,0
- beq- 2f
- add r0,r0,r11
- stw r0,0(r3)
-2: bdnz 1b
-
- /*
- * Now adjust the fixups and the pointers to the fixups
- * in case we need to move ourselves again.
- */
- li r0,__fixup_entries at sectoff@l
- lwz r3,GOT(_FIXUP_TABLE_)
- cmpwi r0,0
- mtctr r0
- addi r3,r3,-4
- beq 4f
-3: lwzu r4,4(r3)
- lwzux r0,r4,r11
- cmpwi r0,0
- add r0,r0,r11
- stw r4,0(r3)
- beq- 5f
- stw r0,0(r4)
-5: bdnz 3b
-4:
-clear_bss:
- /*
- * Now clear BSS segment
- */
- lwz r3,GOT(__bss_start)
- lwz r4,GOT(__bss_end)
-
- cmplw 0, r3, r4
- beq 6f
-
- li r0, 0
-5:
- stw r0, 0(r3)
- addi r3, r3, 4
- cmplw 0, r3, r4
- blt 5b
-6:
-
- mr r3, r9 /* Global Data pointer */
- mr r4, r10 /* Destination Address */
- bl board_init_r
-
- /*
- * Copy exception vector code to low memory
- *
- * r3: dest_addr
- * r7: source address, r8: end address, r9: target address
- */
- .globl trap_init
-trap_init:
- mflr r4 /* save link register */
- GET_GOT
- lwz r7, GOT(_start)
- lwz r8, GOT(_end_of_vectors)
-
- li r9, 0x100 /* reset vector always at 0x100 */
-
- cmplw 0, r7, r8
- bgelr /* return if r7>=r8 - just in case */
-1:
- lwz r0, 0(r7)
- stw r0, 0(r9)
- addi r7, r7, 4
- addi r9, r9, 4
- cmplw 0, r7, r8
- bne 1b
-
- /*
- * relocate `hdlr' and `int_return' entries
- */
- li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
- li r8, Alignment - _start + EXC_OFF_SYS_RESET
-2:
- bl trap_reloc
- addi r7, r7, 0x100 /* next exception vector */
- cmplw 0, r7, r8
- blt 2b
-
- li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
- bl trap_reloc
-
- li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
- bl trap_reloc
-
- li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
- li r8, SystemCall - _start + EXC_OFF_SYS_RESET
-3:
- bl trap_reloc
- addi r7, r7, 0x100 /* next exception vector */
- cmplw 0, r7, r8
- blt 3b
-
- li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
- li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
-4:
- bl trap_reloc
- addi r7, r7, 0x100 /* next exception vector */
- cmplw 0, r7, r8
- blt 4b
-
- mtlr r4 /* restore link register */
- blr
-
- /* Setup the BAT registers.
- */
-setup_bats:
- lis r4, CONFIG_SYS_IBAT0L at h
- ori r4, r4, CONFIG_SYS_IBAT0L at l
- lis r3, CONFIG_SYS_IBAT0U at h
- ori r3, r3, CONFIG_SYS_IBAT0U at l
- mtspr IBAT0L, r4
- mtspr IBAT0U, r3
- isync
-
- lis r4, CONFIG_SYS_DBAT0L at h
- ori r4, r4, CONFIG_SYS_DBAT0L at l
- lis r3, CONFIG_SYS_DBAT0U at h
- ori r3, r3, CONFIG_SYS_DBAT0U at l
- mtspr DBAT0L, r4
- mtspr DBAT0U, r3
- isync
-
- lis r4, CONFIG_SYS_IBAT1L at h
- ori r4, r4, CONFIG_SYS_IBAT1L at l
- lis r3, CONFIG_SYS_IBAT1U at h
- ori r3, r3, CONFIG_SYS_IBAT1U at l
- mtspr IBAT1L, r4
- mtspr IBAT1U, r3
- isync
-
- lis r4, CONFIG_SYS_DBAT1L at h
- ori r4, r4, CONFIG_SYS_DBAT1L at l
- lis r3, CONFIG_SYS_DBAT1U at h
- ori r3, r3, CONFIG_SYS_DBAT1U at l
- mtspr DBAT1L, r4
- mtspr DBAT1U, r3
- isync
-
- lis r4, CONFIG_SYS_IBAT2L at h
- ori r4, r4, CONFIG_SYS_IBAT2L at l
- lis r3, CONFIG_SYS_IBAT2U at h
- ori r3, r3, CONFIG_SYS_IBAT2U at l
- mtspr IBAT2L, r4
- mtspr IBAT2U, r3
- isync
-
- lis r4, CONFIG_SYS_DBAT2L at h
- ori r4, r4, CONFIG_SYS_DBAT2L at l
- lis r3, CONFIG_SYS_DBAT2U at h
- ori r3, r3, CONFIG_SYS_DBAT2U at l
- mtspr DBAT2L, r4
- mtspr DBAT2U, r3
- isync
-
- lis r4, CONFIG_SYS_IBAT3L at h
- ori r4, r4, CONFIG_SYS_IBAT3L at l
- lis r3, CONFIG_SYS_IBAT3U at h
- ori r3, r3, CONFIG_SYS_IBAT3U at l
- mtspr IBAT3L, r4
- mtspr IBAT3U, r3
- isync
-
- lis r4, CONFIG_SYS_DBAT3L at h
- ori r4, r4, CONFIG_SYS_DBAT3L at l
- lis r3, CONFIG_SYS_DBAT3U at h
- ori r3, r3, CONFIG_SYS_DBAT3U at l
- mtspr DBAT3L, r4
- mtspr DBAT3U, r3
- isync
-
- /* Invalidate TLBs.
- * -> for (val = 0; val < 0x20000; val+=0x1000)
- * -> tlbie(val);
- */
- lis r3, 0
- lis r5, 2
-
-1:
- tlbie r3
- addi r3, r3, 0x1000
- cmp 0, 0, r3, r5
- blt 1b
-
- blr
diff --git a/arch/powerpc/cpu/mpc824x/traps.c b/arch/powerpc/cpu/mpc824x/traps.c
deleted file mode 100644
index 6abf41d..0000000
--- a/arch/powerpc/cpu/mpc824x/traps.c
+++ /dev/null
@@ -1,194 +0,0 @@
-/*
- * linux/arch/powerpc/kernel/traps.c
- *
- * Copyright (C) 1995-1996 Gary Thomas (gdt at linuxppc.org)
- *
- * Modified by Cort Dougan (cort at cs.nmt.edu)
- * and Paul Mackerras (paulus at cs.anu.edu.au)
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * This file handles the architecture-dependent parts of hardware exceptions
- */
-
-#include <common.h>
-#include <asm/processor.h>
-
-/* Returns 0 if exception not found and fixup otherwise. */
-extern unsigned long search_exception_table(unsigned long);
-
-/* THIS NEEDS CHANGING to use the board info structure.
-*/
-#define END_OF_MEM 0x00400000
-
-/*
- * Trap & Exception support
- */
-
-static void print_backtrace(unsigned long *sp)
-{
- int cnt = 0;
- unsigned long i;
-
- printf("Call backtrace: ");
- while (sp) {
- if ((uint)sp > END_OF_MEM)
- break;
-
- i = sp[1];
- if (cnt++ % 7 == 0)
- printf("\n");
- printf("%08lX ", i);
- if (cnt > 32) break;
- sp = (unsigned long *)*sp;
- }
- printf("\n");
-}
-
-void show_regs(struct pt_regs *regs)
-{
- int i;
-
- printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n",
- regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar);
- printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n",
- regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0,
- regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0,
- regs->msr&MSR_IR ? 1 : 0,
- regs->msr&MSR_DR ? 1 : 0);
-
- printf("\n");
- for (i = 0; i < 32; i++) {
- if ((i % 8) == 0)
- {
- printf("GPR%02d: ", i);
- }
-
- printf("%08lX ", regs->gpr[i]);
- if ((i % 8) == 7)
- {
- printf("\n");
- }
- }
-}
-
-
-static void _exception(int signr, struct pt_regs *regs)
-{
- show_regs(regs);
- print_backtrace((unsigned long *)regs->gpr[1]);
- panic("Exception in kernel pc %lx signal %d",regs->nip,signr);
-}
-
-void MachineCheckException(struct pt_regs *regs)
-{
- unsigned long fixup;
-
- /* Probing PCI using config cycles cause this exception
- * when a device is not present. Catch it and return to
- * the PCI exception handler.
- */
- if ((fixup = search_exception_table(regs->nip)) != 0) {
- regs->nip = fixup;
- return;
- }
-
- printf("Machine check in kernel mode.\n");
- printf("Caused by (from msr): ");
- printf("regs %p ",regs);
- switch( regs->msr & 0x000F0000) {
- case (0x80000000>>12):
- printf("Machine check signal - probably due to mm fault\n"
- "with mmu off\n");
- break;
- case (0x80000000>>13):
- printf("Transfer error ack signal\n");
- break;
- case (0x80000000>>14):
- printf("Data parity signal\n");
- break;
- case (0x80000000>>15):
- printf("Address parity signal\n");
- break;
- default:
- printf("Unknown values in msr\n");
- }
- show_regs(regs);
- print_backtrace((unsigned long *)regs->gpr[1]);
- panic("machine check");
-}
-
-void AlignmentException(struct pt_regs *regs)
-{
- show_regs(regs);
- print_backtrace((unsigned long *)regs->gpr[1]);
- panic("Alignment Exception");
-}
-
-void ProgramCheckException(struct pt_regs *regs)
-{
- show_regs(regs);
- print_backtrace((unsigned long *)regs->gpr[1]);
- panic("Program Check Exception");
-}
-
-void SoftEmuException(struct pt_regs *regs)
-{
- show_regs(regs);
- print_backtrace((unsigned long *)regs->gpr[1]);
- panic("Software Emulation Exception");
-}
-
-
-void UnknownException(struct pt_regs *regs)
-{
- printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
- regs->nip, regs->msr, regs->trap);
- _exception(0, regs);
-}
-
-#if defined(CONFIG_CMD_BEDBUG)
-extern void do_bedbug_breakpoint(struct pt_regs *);
-#endif
-
-void DebugException(struct pt_regs *regs)
-{
-
- printf("Debugger trap at @ %lx\n", regs->nip );
- show_regs(regs);
-#if defined(CONFIG_CMD_BEDBUG)
- do_bedbug_breakpoint( regs );
-#endif
-}
-
-/* Probe an address by reading. If not present, return -1, otherwise
- * return 0.
- */
-int addr_probe(uint *addr)
-{
-#if 0
- int retval;
-
- __asm__ __volatile__( \
- "1: lwz %0,0(%1)\n" \
- " eieio\n" \
- " li %0,0\n" \
- "2:\n" \
- ".section .fixup,\"ax\"\n" \
- "3: li %0,-1\n" \
- " b 2b\n" \
- ".section __ex_table,\"a\"\n" \
- " .align 2\n" \
- " .long 1b,3b\n" \
- ".text" \
- : "=r" (retval) : "r"(addr));
-
- return (retval);
-#endif
- return 0;
-}
diff --git a/arch/powerpc/cpu/mpc824x/u-boot.lds b/arch/powerpc/cpu/mpc824x/u-boot.lds
deleted file mode 100644
index 04aba84..0000000
--- a/arch/powerpc/cpu/mpc824x/u-boot.lds
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * (C) Copyright 2001-2010
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- .text :
- {
- arch/powerpc/cpu/mpc824x/start.o (.text*)
- *(.text*)
- . = ALIGN(16);
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 2ed51b1..db8cc8c 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -1360,8 +1360,6 @@ void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
#elif defined(CONFIG_MPC8260)
#define _machine _MACH_8260
#define have_of 0
-#elif defined(CONFIG_SANDPOINT)
-#define _machine _MACH_sandpoint
#else
#error "Machine not defined correctly"
#endif
diff --git a/board/a3000/Kconfig b/board/a3000/Kconfig
deleted file mode 100644
index 21a9e48..0000000
--- a/board/a3000/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_A3000
-
-config SYS_BOARD
- default "a3000"
-
-config SYS_CONFIG_NAME
- default "A3000"
-
-endif
diff --git a/board/a3000/MAINTAINERS b/board/a3000/MAINTAINERS
deleted file mode 100644
index 303e5fd..0000000
--- a/board/a3000/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-A3000 BOARD
-#M: -
-S: Maintained
-F: board/a3000/
-F: include/configs/A3000.h
-F: configs/A3000_defconfig
diff --git a/board/a3000/Makefile b/board/a3000/Makefile
deleted file mode 100644
index 9b9b048..0000000
--- a/board/a3000/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = a3000.o flash.o
diff --git a/board/a3000/README b/board/a3000/README
deleted file mode 100644
index f0e92c5..0000000
--- a/board/a3000/README
+++ /dev/null
@@ -1,17 +0,0 @@
-U-Boot for Artis SBC-A3000
----------------------------
-
-Artis SBC-A3000 has one flash socket that the user uses Intel 28F128J3A (16MB)
-or 28F064J3A (8MB) chips.
-
-In board's notation, bank 0 is the one at the address of 0xFF000000.
-bank 1 is the one at the address of 0xFF800000
-
-On power-up the processor jumps to the address of 0xFFF00100, the last
-megabyte of the bank 0 of flash.
-
-Thus, U-Boot is configured to reside in flash starting at the address of
-0xFFF00000. The environment space is located in flash separately from
-U-Boot, at the address of 0xFFFE0000.
-
-There is a National ns83815 10/100M ethernet controller on-board.
diff --git a/board/a3000/a3000.c b/board/a3000/a3000.c
deleted file mode 100644
index 3e2f6b0..0000000
--- a/board/a3000/a3000.c
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * (C) Copyright 2001
- * Rob Taylor, Flying Pig Systems. robt at flyingpig.com.
- *
- * Modified during 2003 by
- * Ken Chou, kchou at ieee.org
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc824x.h>
-#include <pci.h>
-#include <netdev.h>
-
-int checkboard (void)
-{
- ulong busfreq = get_bus_freq(0);
- char buf[32];
-
- printf("Board: A3000 Local Bus at %s MHz\n", strmhz(buf, busfreq));
- return 0;
-
-}
-
-phys_size_t initdram (int board_type)
-{
- long size;
- long new_bank0_end;
- long mear1;
- long emear1;
-
- size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
-
- new_bank0_end = size - 1;
- mear1 = mpc824x_mpc107_getreg(MEAR1);
- emear1 = mpc824x_mpc107_getreg(EMEAR1);
- mear1 = (mear1 & 0xFFFFFF00) |
- ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
- emear1 = (emear1 & 0xFFFFFF00) |
- ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
- mpc824x_mpc107_setreg(MEAR1, mear1);
- mpc824x_mpc107_setreg(EMEAR1, emear1);
-
- return (size);
-}
-
-/*
- * Initialize PCI Devices
- */
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_a3000_config_table[] = {
- /* vendor, device, class */
- /* bus, dev, func */
- { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_83815, PCI_ANY_ID,
- PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, /* dp83815 eth0 divice */
- pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
- PCI_ENET0_MEMADDR,
- PCI_COMMAND_IO |
- PCI_COMMAND_MEMORY |
- PCI_COMMAND_MASTER }},
- { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
- PCI_ANY_ID, 0x14, PCI_ANY_ID, /* PCI slot1 */
- pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
- PCI_ENET1_MEMADDR,
- PCI_COMMAND_IO |
- PCI_COMMAND_MEMORY |
- PCI_COMMAND_MASTER }},
- { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
- PCI_ANY_ID, 0x15, PCI_ANY_ID, /* PCI slot2 */
- pci_cfgfunc_config_device, { PCI_ENET2_IOADDR,
- PCI_ENET2_MEMADDR,
- PCI_COMMAND_IO |
- PCI_COMMAND_MEMORY |
- PCI_COMMAND_MASTER }},
- { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
- PCI_ANY_ID, 0x16, PCI_ANY_ID, /* PCI slot3 */
- pci_cfgfunc_config_device, { PCI_ENET3_IOADDR,
- PCI_ENET3_MEMADDR,
- PCI_COMMAND_IO |
- PCI_COMMAND_MEMORY |
- PCI_COMMAND_MASTER }},
- { }
-};
-#endif
-
-struct pci_controller hose = {
-#ifndef CONFIG_PCI_PNP
- config_table: pci_a3000_config_table,
-#endif
-};
-
-void pci_init_board(void)
-{
- pci_mpc824x_init(&hose);
-}
-
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
diff --git a/board/a3000/flash.c b/board/a3000/flash.c
deleted file mode 100644
index f2dd3c2..0000000
--- a/board/a3000/flash.c
+++ /dev/null
@@ -1,438 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-
-#include <common.h>
-#include <mpc824x.h>
-
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-# ifndef CONFIG_ENV_ADDR
-# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-# endif
-# ifndef CONFIG_ENV_SIZE
-# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-# endif
-# ifndef CONFIG_ENV_SECT_SIZE
-# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
-# endif
-#endif
-
-
-/*---------------------------------------------------------------------*/
-#define DEBUG_FLASH
-
-#ifdef DEBUG_FLASH
-#define DEBUGF(fmt,args...) printf(fmt ,##args)
-#else
-#define DEBUGF(fmt,args...)
-#endif
-/*---------------------------------------------------------------------*/
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_char *addr, flash_info_t *info);
-static int write_data (flash_info_t *info, uchar *dest, uchar data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-#define BS(b) (b)
-#define BYTEME(x) ((x) & 0xFF)
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- unsigned long flash_banks[CONFIG_SYS_MAX_FLASH_BANKS] = CONFIG_SYS_FLASH_BANKS;
- unsigned long size, size_b[CONFIG_SYS_MAX_FLASH_BANKS];
-
- int i;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i)
- {
- flash_info[i].flash_id = FLASH_UNKNOWN;
-
- DEBUGF("Get flash bank %d @ 0x%08lx\n", i, flash_banks[i]);
-/*
- size_b[i] = flash_get_size((vu_char *)flash_banks[i], &flash_info[i]);
-*/
- size_b[i] = flash_get_size((vu_char *) 0xff800000 , &flash_info[i]);
-
- if (flash_info[i].flash_id == FLASH_UNKNOWN)
- {
- printf ("## Unknown FLASH on Bank %d: "
- "ID 0x%lx, Size = 0x%08lx = %ld MB\n",
- i, flash_info[i].flash_id,
- size_b[i], size_b[i]<<20);
- }
- else
- {
- DEBUGF("## Flash bank %d@0x%08lx sizes: 0x%08lx \n",
- i, flash_banks[i], size_b[i]);
-
- flash_get_offsets (flash_banks[i], &flash_info[i]);
- flash_info[i].size = size_b[i];
- }
- }
-
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- DEBUGF("protect monitor %x @ %x\n", CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN);
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1,
- &flash_info[0]);
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- DEBUGF("protect environtment %x @ %x\n", CONFIG_ENV_ADDR, CONFIG_ENV_SECT_SIZE);
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
- &flash_info[0]);
-#endif
-
- size = 0;
- DEBUGF("## Final Flash bank sizes: ");
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i)
- {
- DEBUGF("%08lx ", size_b[i]);
- size += size_b[i];
- }
- DEBUGF("\n");
- return (size);
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_INTEL:
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base;
- base += 0x00020000; /* 128k per bank */
- }
- return;
-
- default:
- printf ("Don't know sector ofsets for flash type 0x%lx\n", info->flash_id);
- return;
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_FUJ: printf ("Fujitsu "); break;
- case FLASH_MAN_SST: printf ("SST "); break;
- case FLASH_MAN_STM: printf ("STM "); break;
- case FLASH_MAN_INTEL: printf ("Intel "); break;
- case FLASH_MAN_MT: printf ("MT "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F320J3A:
- printf ("28F320J3A (32Mbit = 128K x 32)\n");
- break;
- case FLASH_28F640J3A:
- printf ("28F640J3A (64Mbit = 128K x 64)\n");
- break;
- case FLASH_28F128J3A:
- printf ("28F128J3A (128Mbit = 128K x 128)\n");
- break;
- default:
- printf ("Unknown Chip Type\n");
- break;
- }
-
-#if 1
- if (info->size >= (1 << 20)) {
- i = 20;
- } else {
- i = 10;
- }
- printf (" Size: %ld %cB in %d Sectors\n",
- info->size >> i,
- (i == 20) ? 'M' : 'k',
- info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
-#endif
- return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size (vu_char *addr, flash_info_t *info)
-{
- vu_char manuf, device;
-
- addr[0] = BS(0x90);
- manuf = BS(addr[0]);
- DEBUGF("Manuf. ID @ 0x%08lx: 0x%08x\n", (ulong)addr, manuf);
-
- switch (manuf) {
- case BYTEME(AMD_MANUFACT):
- info->flash_id = FLASH_MAN_AMD;
- break;
- case BYTEME(FUJ_MANUFACT):
- info->flash_id = FLASH_MAN_FUJ;
- break;
- case BYTEME(SST_MANUFACT):
- info->flash_id = FLASH_MAN_SST;
- break;
- case BYTEME(STM_MANUFACT):
- info->flash_id = FLASH_MAN_STM;
- break;
- case BYTEME(INTEL_MANUFACT):
- info->flash_id = FLASH_MAN_INTEL;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- addr[0] = BS(0xFF); /* restore read mode, (yes, BS is a NOP) */
- return 0; /* no or unknown flash */
- }
-
- device = BS(addr[2]); /* device ID */
-
- DEBUGF("Device ID @ 0x%08lx: 0x%08x\n", (ulong)(&addr[1]), device);
-
- switch (device) {
- case BYTEME(INTEL_ID_28F320J3A):
- info->flash_id += FLASH_28F320J3A;
- info->sector_count = 32;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case BYTEME(INTEL_ID_28F640J3A):
- info->flash_id += FLASH_28F640J3A;
- info->sector_count = 64;
- info->size = 0x00800000;
- break; /* => 8 MB */
-
- case BYTEME(INTEL_ID_28F128J3A):
- info->flash_id += FLASH_28F128J3A;
- info->sector_count = 128;
- info->size = 0x01000000;
- break; /* => 16 MB */
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- addr[0] = BS(0xFF); /* restore read mode (yes, a NOP) */
- return 0; /* => no or unknown flash */
-
- }
-
- if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
- printf ("** ERROR: sector count %d > max (%d) **\n",
- info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
- info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- }
-
- addr[0] = BS(0xFF); /* restore read mode */
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- int flag, prot, sect;
- ulong start, now, last;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) {
- printf ("Can erase only Intel flash types - aborted\n");
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n", prot);
- } else {
- printf ("\n");
- }
-
- start = get_timer (0);
- last = start;
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- vu_char *addr = (vu_char *)(info->start[sect]);
- unsigned long status;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- *addr = BS(0x50); /* clear status register */
- *addr = BS(0x20); /* erase setup */
- *addr = BS(0xD0); /* erase confirm */
-
- /* re-enable interrupts if necessary */
- if (flag) {
- enable_interrupts();
- }
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- while (((status = BS(*addr)) & BYTEME(0x00800080)) != BYTEME(0x00800080)) {
- if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- *addr = BS(0xB0); /* suspend erase */
- *addr = BS(0xFF); /* reset to read mode */
- return 1;
- }
-
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
- *addr = BS(0xFF); /* reset to read mode */
- }
- }
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 4 - Flash not identified
- */
-
-#define FLASH_WIDTH 1 /* flash bus width in bytes */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- uchar *wp = (uchar *)addr;
- int rc;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- return 4;
- }
-
- while (cnt > 0) {
- if ((rc = write_data(info, wp, *src)) != 0) {
- return rc;
- }
- wp++;
- src++;
- cnt--;
- }
-
- return cnt;
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_data (flash_info_t *info, uchar *dest, uchar data)
-{
- vu_char *addr = (vu_char *)dest;
- ulong status;
- ulong start;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((BS(*addr) & data) != data) {
- return 2;
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- *addr = BS(0x40); /* write setup */
- *addr = data;
-
- /* re-enable interrupts if necessary */
- if (flag) {
- enable_interrupts();
- }
-
- start = get_timer (0);
-
- while (((status = BS(*addr)) & BYTEME(0x00800080)) != BYTEME(0x00800080)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- *addr = BS(0xFF); /* restore read mode */
- return 1;
- }
- }
-
- *addr = BS(0xFF); /* restore read mode */
-
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- */
diff --git a/board/cpc45/Kconfig b/board/cpc45/Kconfig
deleted file mode 100644
index c564caf..0000000
--- a/board/cpc45/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_CPC45
-
-config SYS_BOARD
- default "cpc45"
-
-config SYS_CONFIG_NAME
- default "CPC45"
-
-endif
diff --git a/board/cpc45/MAINTAINERS b/board/cpc45/MAINTAINERS
deleted file mode 100644
index 163e09c..0000000
--- a/board/cpc45/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-CPC45 BOARD
-M: Josef Wagner <Wagner@Microsys.de>
-S: Maintained
-F: board/cpc45/
-F: include/configs/CPC45.h
-F: configs/CPC45_defconfig
-F: configs/CPC45_ROMBOOT_defconfig
diff --git a/board/cpc45/Makefile b/board/cpc45/Makefile
deleted file mode 100644
index 1310f93..0000000
--- a/board/cpc45/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = cpc45.o flash.o plx9030.o pd67290.o ide.o
diff --git a/board/cpc45/cpc45.c b/board/cpc45/cpc45.c
deleted file mode 100644
index f182e79..0000000
--- a/board/cpc45/cpc45.c
+++ /dev/null
@@ -1,250 +0,0 @@
-/*
- * (C) Copyright 2001
- * Rob Taylor, Flying Pig Systems. robt at flyingpig.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc824x.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <pci.h>
-#include <i2c.h>
-#include <netdev.h>
-
-int sysControlDisplay(int digit, uchar ascii_code);
-extern void Plx9030Init(void);
-extern void SPD67290Init(void);
-
- /* We have to clear the initial data area here. Couldn't have done it
- * earlier because DRAM had not been initialized.
- */
-int board_early_init_f(void)
-{
-
- /* enable DUAL UART Mode on CPC45 */
- *(uchar*)DUART_DCR |= 0x1; /* set DCM bit */
-
- return 0;
-}
-
-int checkboard(void)
-{
-/*
- char revision = BOARD_REV;
-*/
- ulong busfreq = get_bus_freq(0);
- char buf[32];
-
- puts ("CPC45 ");
-/*
- printf("Revision %d ", revision);
-*/
- printf("Local Bus at %s MHz\n", strmhz(buf, busfreq));
-
- return 0;
-}
-
-phys_size_t initdram (int board_type)
-{
- int m, row, col, bank, i, ref;
- unsigned long start, end;
- uint32_t mccr1, mccr2;
- uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0;
- uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0;
- uint8_t mber = 0;
- unsigned int tmp;
-
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-
- if (i2c_reg_read (0x50, 2) != 0x04)
- return 0; /* Memory type */
-
- m = i2c_reg_read (0x50, 5); /* # of physical banks */
- row = i2c_reg_read (0x50, 3); /* # of rows */
- col = i2c_reg_read (0x50, 4); /* # of columns */
- bank = i2c_reg_read (0x50, 17); /* # of logical banks */
- ref = i2c_reg_read (0x50, 12); /* refresh rate / type */
-
- CONFIG_READ_WORD(MCCR1, mccr1);
- mccr1 &= 0xffff0000;
-
- CONFIG_READ_WORD(MCCR2, mccr2);
- mccr2 &= 0xffff0000;
-
- start = CONFIG_SYS_SDRAM_BASE;
- end = start + (1 << (col + row + 3) ) * bank - 1;
-
- for (i = 0; i < m; i++) {
- mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2;
- if (i < 4) {
- msar1 |= ((start >> 20) & 0xff) << i * 8;
- emsar1 |= ((start >> 28) & 0xff) << i * 8;
- mear1 |= ((end >> 20) & 0xff) << i * 8;
- emear1 |= ((end >> 28) & 0xff) << i * 8;
- } else {
- msar2 |= ((start >> 20) & 0xff) << (i-4) * 8;
- emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8;
- mear2 |= ((end >> 20) & 0xff) << (i-4) * 8;
- emear2 |= ((end >> 28) & 0xff) << (i-4) * 8;
- }
- mber |= 1 << i;
- start += (1 << (col + row + 3) ) * bank;
- end += (1 << (col + row + 3) ) * bank;
- }
- for (; i < 8; i++) {
- if (i < 4) {
- msar1 |= 0xff << i * 8;
- emsar1 |= 0x30 << i * 8;
- mear1 |= 0xff << i * 8;
- emear1 |= 0x30 << i * 8;
- } else {
- msar2 |= 0xff << (i-4) * 8;
- emsar2 |= 0x30 << (i-4) * 8;
- mear2 |= 0xff << (i-4) * 8;
- emear2 |= 0x30 << (i-4) * 8;
- }
- }
-
- switch(ref) {
- case 0x00:
- case 0x80:
- tmp = get_bus_freq(0) / 1000000 * 15625 / 1000 - 22;
- break;
- case 0x01:
- case 0x81:
- tmp = get_bus_freq(0) / 1000000 * 3900 / 1000 - 22;
- break;
- case 0x02:
- case 0x82:
- tmp = get_bus_freq(0) / 1000000 * 7800 / 1000 - 22;
- break;
- case 0x03:
- case 0x83:
- tmp = get_bus_freq(0) / 1000000 * 31300 / 1000 - 22;
- break;
- case 0x04:
- case 0x84:
- tmp = get_bus_freq(0) / 1000000 * 62500 / 1000 - 22;
- break;
- case 0x05:
- case 0x85:
- tmp = get_bus_freq(0) / 1000000 * 125000 / 1000 - 22;
- break;
- default:
- tmp = 0x512;
- break;
- }
-
- CONFIG_WRITE_WORD(MCCR1, mccr1);
- CONFIG_WRITE_WORD(MCCR2, tmp << MCCR2_REFINT_SHIFT);
- CONFIG_WRITE_WORD(MSAR1, msar1);
- CONFIG_WRITE_WORD(EMSAR1, emsar1);
- CONFIG_WRITE_WORD(MEAR1, mear1);
- CONFIG_WRITE_WORD(EMEAR1, emear1);
- CONFIG_WRITE_WORD(MSAR2, msar2);
- CONFIG_WRITE_WORD(EMSAR2, emsar2);
- CONFIG_WRITE_WORD(MEAR2, mear2);
- CONFIG_WRITE_WORD(EMEAR2, emear2);
- CONFIG_WRITE_BYTE(MBER, mber);
-
- return (1 << (col + row + 3) ) * bank * m;
-}
-
-
-/*
- * Initialize PCI Devices, report devices found.
- */
-
-static struct pci_config_table pci_cpc45_config_table[] = {
-#ifndef CONFIG_PCI_PNP
- { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0F, PCI_ANY_ID,
- pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
- PCI_ENET0_MEMADDR,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
- { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0D, PCI_ANY_ID,
- pci_cfgfunc_config_device, { PCI_PLX9030_IOADDR,
- PCI_PLX9030_MEMADDR,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
- { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0E, PCI_ANY_ID,
- pci_cfgfunc_config_device, { PCMCIA_IO_BASE,
- PCMCIA_IO_BASE,
- PCI_COMMAND_MEMORY | PCI_COMMAND_IO }},
-#endif /*CONFIG_PCI_PNP*/
- { }
-};
-
-struct pci_controller hose = {
-#ifndef CONFIG_PCI_PNP
- config_table: pci_cpc45_config_table,
-#endif
-};
-
-void pci_init_board(void)
-{
- pci_mpc824x_init(&hose);
-
- /* init PCI_to_LOCAL Bus BRIDGE */
- Plx9030Init();
-
- /* Clear Display */
- DISP_CWORD = 0x0;
-
- sysControlDisplay(0,' ');
- sysControlDisplay(1,'C');
- sysControlDisplay(2,'P');
- sysControlDisplay(3,'C');
- sysControlDisplay(4,' ');
- sysControlDisplay(5,'4');
- sysControlDisplay(6,'5');
- sysControlDisplay(7,' ');
-
-}
-
-/**************************************************************************
-*
-* sysControlDisplay - controls one of the Alphanum. Display digits.
-*
-* This routine will write an ASCII character to the display digit requested.
-*
-* SEE ALSO:
-*
-* RETURNS: NA
-*/
-
-int sysControlDisplay (int digit, /* number of digit 0..7 */
- uchar ascii_code /* ASCII code */
- )
-{
- if ((digit < 0) || (digit > 7))
- return (-1);
-
- *((volatile uchar *) (DISP_CHR_RAM + digit)) = ascii_code;
-
- return (0);
-}
-
-#if defined(CONFIG_CMD_PCMCIA)
-
-#ifdef CONFIG_SYS_PCMCIA_MEM_ADDR
-volatile unsigned char *pcmcia_mem = (unsigned char*)CONFIG_SYS_PCMCIA_MEM_ADDR;
-#endif
-
-int pcmcia_init(void)
-{
- u_int rc;
-
- debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n");
-
- rc = i82365_init();
-
- return rc;
-}
-
-#endif
-
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
diff --git a/board/cpc45/flash.c b/board/cpc45/flash.c
deleted file mode 100644
index 917db34..0000000
--- a/board/cpc45/flash.c
+++ /dev/null
@@ -1,506 +0,0 @@
-/*
- * (C) Copyright 2001-2003
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc824x.h>
-#include <asm/processor.h>
-
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-# ifndef CONFIG_ENV_ADDR
-# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-# endif
-# ifndef CONFIG_ENV_SIZE
-# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-# endif
-# ifndef CONFIG_ENV_SECT_SIZE
-# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
-# endif
-#endif
-
-#define FLASH_BANK_SIZE 0x800000
-#define MAIN_SECT_SIZE 0x40000
-#define PARAM_SECT_SIZE 0x8000
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-static int write_data (flash_info_t * info, ulong dest, ulong * data);
-static void write_via_fpu (vu_long * addr, ulong * data);
-static __inline__ unsigned long get_msr (void);
-static __inline__ void set_msr (unsigned long msr);
-
-/*---------------------------------------------------------------------*/
-#undef DEBUG_FLASH
-
-/*---------------------------------------------------------------------*/
-#ifdef DEBUG_FLASH
-#define DEBUGF(fmt,args...) printf(fmt ,##args)
-#else
-#define DEBUGF(fmt,args...)
-#endif
-/*---------------------------------------------------------------------*/
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- int i, j;
- ulong size = 0;
- uchar tempChar;
- vu_long *tmpaddr;
-
- /* Enable flash writes on CPC45 */
-
- tempChar = BOARD_CTRL;
-
- tempChar |= (B_CTRL_FWPT_1 | B_CTRL_FWRE_1);
-
- tempChar &= ~(B_CTRL_FWPT_0 | B_CTRL_FWRE_0);
-
- BOARD_CTRL = tempChar;
-
- __asm__ volatile ("sync\n eieio");
-
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
- vu_long *addr = (vu_long *) (CONFIG_SYS_FLASH_BASE + i * FLASH_BANK_SIZE);
-
- addr[0] = 0x00900090;
-
- __asm__ volatile ("sync\n eieio");
-
- udelay (100);
-
- DEBUGF ("Flash bank # %d:\n"
- "\tManuf. ID @ 0x%08lX: 0x%08lX\n"
- "\tDevice ID @ 0x%08lX: 0x%08lX\n",
- i,
- (ulong) (&addr[0]), addr[0],
- (ulong) (&addr[2]), addr[2]);
-
-
- if ((addr[0] == addr[1]) && (addr[0] == INTEL_MANUFACT) &&
- (addr[2] == addr[3]) && (addr[2] == INTEL_ID_28F160F3T)) {
-
- flash_info[i].flash_id =
- (FLASH_MAN_INTEL & FLASH_VENDMASK) |
- (INTEL_ID_28F160F3T & FLASH_TYPEMASK);
-
- } else if ((addr[0] == addr[1]) && (addr[0] == INTEL_MANUFACT)
- && (addr[2] == addr[3])
- && (addr[2] == INTEL_ID_28F160C3T)) {
-
- flash_info[i].flash_id =
- (FLASH_MAN_INTEL & FLASH_VENDMASK) |
- (INTEL_ID_28F160C3T & FLASH_TYPEMASK);
-
- } else {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- addr[0] = 0xFFFFFFFF;
- goto Done;
- }
-
- DEBUGF ("flash_id = 0x%08lX\n", flash_info[i].flash_id);
-
- addr[0] = 0xFFFFFFFF;
-
- flash_info[i].size = FLASH_BANK_SIZE;
- flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
- for (j = 0; j < flash_info[i].sector_count; j++) {
- if (j > 30) {
- flash_info[i].start[j] = CONFIG_SYS_FLASH_BASE +
- i * FLASH_BANK_SIZE +
- (MAIN_SECT_SIZE * 31) + (j -
- 31) *
- PARAM_SECT_SIZE;
- } else {
- flash_info[i].start[j] = CONFIG_SYS_FLASH_BASE +
- i * FLASH_BANK_SIZE +
- j * MAIN_SECT_SIZE;
- }
- }
-
- /* unlock sectors, if 160C3T */
-
- for (j = 0; j < flash_info[i].sector_count; j++) {
- tmpaddr = (vu_long *) flash_info[i].start[j];
-
- if ((flash_info[i].flash_id & FLASH_TYPEMASK) ==
- (INTEL_ID_28F160C3T & FLASH_TYPEMASK)) {
- tmpaddr[0] = 0x00600060;
- tmpaddr[0] = 0x00D000D0;
- tmpaddr[1] = 0x00600060;
- tmpaddr[1] = 0x00D000D0;
- }
- }
-
- size += flash_info[i].size;
-
- addr[0] = 0x00FF00FF;
- addr[1] = 0x00FF00FF;
- }
-
- /* Protect monitor and environment sectors
- */
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE + FLASH_BANK_SIZE
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
- &flash_info[1]);
-#else
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
- &flash_info[0]);
-#endif
-
-#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
-#if CONFIG_ENV_ADDR >= CONFIG_SYS_FLASH_BASE + FLASH_BANK_SIZE
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[1]);
-#else
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
-#endif
-#endif
-
-Done:
- return size;
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
- int i;
-
- switch ((i = info->flash_id & FLASH_VENDMASK)) {
- case (FLASH_MAN_INTEL & FLASH_VENDMASK):
- printf ("Intel: ");
- break;
- default:
- printf ("Unknown Vendor 0x%04x ", i);
- break;
- }
-
- switch ((i = info->flash_id & FLASH_TYPEMASK)) {
- case (INTEL_ID_28F160F3T & FLASH_TYPEMASK):
- printf ("28F160F3T (16Mbit)\n");
- break;
-
- case (INTEL_ID_28F160C3T & FLASH_TYPEMASK):
- printf ("28F160C3T (16Mbit)\n");
- break;
-
- default:
- printf ("Unknown Chip Type 0x%04x\n", i);
- goto Done;
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; i++) {
- if ((i % 5) == 0) {
- printf ("\n ");
- }
- printf (" %08lX%s", info->start[i],
- info->protect[i] ? " (RO)" : " ");
- }
- printf ("\n");
-
-Done:
- return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
- int flag, prot, sect;
- ulong start, now, last;
-
- DEBUGF ("Erase flash bank %d sect %d ... %d\n",
- info - &flash_info[0], s_first, s_last);
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id & FLASH_VENDMASK) !=
- (FLASH_MAN_INTEL & FLASH_VENDMASK)) {
- printf ("Can erase only Intel flash types - aborted\n");
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n", prot);
- } else {
- printf ("\n");
- }
-
- start = get_timer (0);
- last = start;
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- vu_long *addr = (vu_long *) (info->start[sect]);
-
- DEBUGF ("Erase sect %d @ 0x%08lX\n",
- sect, (ulong) addr);
-
- /* Disable interrupts which might cause a timeout
- * here.
- */
- flag = disable_interrupts ();
-
- addr[0] = 0x00500050; /* clear status register */
- addr[0] = 0x00200020; /* erase setup */
- addr[0] = 0x00D000D0; /* erase confirm */
-
- addr[1] = 0x00500050; /* clear status register */
- addr[1] = 0x00200020; /* erase setup */
- addr[1] = 0x00D000D0; /* erase confirm */
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- while (((addr[0] & 0x00800080) != 0x00800080) ||
- ((addr[1] & 0x00800080) != 0x00800080)) {
- if ((now = get_timer (start)) >
- CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- addr[0] = 0x00B000B0; /* suspend erase */
- addr[0] = 0x00FF00FF; /* to read mode */
- return 1;
- }
-
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
- addr[0] = 0x00FF00FF;
- }
- }
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 4 - Flash not identified
- */
-
-#define FLASH_WIDTH 8 /* flash bus width in bytes */
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- ulong wp, cp, msr;
- int l, rc, i;
- ulong data[2];
- ulong *datah = &data[0];
- ulong *datal = &data[1];
-
- DEBUGF ("Flash write_buff: @ 0x%08lx, src 0x%08lx len %ld\n",
- addr, (ulong) src, cnt);
-
- if (info->flash_id == FLASH_UNKNOWN) {
- return 4;
- }
-
- msr = get_msr ();
- set_msr (msr | MSR_FP);
-
- wp = (addr & ~(FLASH_WIDTH - 1)); /* get lower aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- *datah = *datal = 0;
-
- for (i = 0, cp = wp; i < l; i++, cp++) {
- if (i >= 4) {
- *datah = (*datah << 8) |
- ((*datal & 0xFF000000) >> 24);
- }
-
- *datal = (*datal << 8) | (*(uchar *) cp);
- }
- for (; i < FLASH_WIDTH && cnt > 0; ++i) {
- char tmp = *src++;
-
- if (i >= 4) {
- *datah = (*datah << 8) |
- ((*datal & 0xFF000000) >> 24);
- }
-
- *datal = (*datal << 8) | tmp;
- --cnt;
- ++cp;
- }
-
- for (; cnt == 0 && i < FLASH_WIDTH; ++i, ++cp) {
- if (i >= 4) {
- *datah = (*datah << 8) |
- ((*datal & 0xFF000000) >> 24);
- }
-
- *datal = (*datah << 8) | (*(uchar *) cp);
- }
-
- if ((rc = write_data (info, wp, data)) != 0) {
- set_msr (msr);
- return (rc);
- }
-
- wp += FLASH_WIDTH;
- }
-
- /*
- * handle FLASH_WIDTH aligned part
- */
- while (cnt >= FLASH_WIDTH) {
- *datah = *(ulong *) src;
- *datal = *(ulong *) (src + 4);
- if ((rc = write_data (info, wp, data)) != 0) {
- set_msr (msr);
- return (rc);
- }
- wp += FLASH_WIDTH;
- cnt -= FLASH_WIDTH;
- src += FLASH_WIDTH;
- }
-
- if (cnt == 0) {
- set_msr (msr);
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- *datah = *datal = 0;
- for (i = 0, cp = wp; i < FLASH_WIDTH && cnt > 0; ++i, ++cp) {
- char tmp = *src++;
-
- if (i >= 4) {
- *datah = (*datah << 8) | ((*datal & 0xFF000000) >>
- 24);
- }
-
- *datal = (*datal << 8) | tmp;
- --cnt;
- }
-
- for (; i < FLASH_WIDTH; ++i, ++cp) {
- if (i >= 4) {
- *datah = (*datah << 8) | ((*datal & 0xFF000000) >>
- 24);
- }
-
- *datal = (*datal << 8) | (*(uchar *) cp);
- }
-
- rc = write_data (info, wp, data);
- set_msr (msr);
-
- return (rc);
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_data (flash_info_t * info, ulong dest, ulong * data)
-{
- vu_long *addr = (vu_long *) dest;
- ulong start;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if (((addr[0] & data[0]) != data[0]) ||
- ((addr[1] & data[1]) != data[1])) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- addr[0] = 0x00400040; /* write setup */
- write_via_fpu (addr, data);
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- start = get_timer (0);
-
- while (((addr[0] & 0x00800080) != 0x00800080) ||
- ((addr[1] & 0x00800080) != 0x00800080)) {
- if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- addr[0] = 0x00FF00FF; /* restore read mode */
- return (1);
- }
- }
-
- addr[0] = 0x00FF00FF; /* restore read mode */
-
- return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
-static void write_via_fpu (vu_long * addr, ulong * data)
-{
- __asm__ __volatile__ ("lfd 1, 0(%0)"::"r" (data));
- __asm__ __volatile__ ("stfd 1, 0(%0)"::"r" (addr));
-}
-
-/*-----------------------------------------------------------------------
- */
-static __inline__ unsigned long get_msr (void)
-{
- unsigned long msr;
-
- __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
-
- return msr;
-}
-
-static __inline__ void set_msr (unsigned long msr)
-{
- __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
-}
diff --git a/board/cpc45/ide.c b/board/cpc45/ide.c
deleted file mode 100644
index 1944e36..0000000
--- a/board/cpc45/ide.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * (C) Copyright 2001
- * Rob Taylor, Flying Pig Systems. robt at flyingpig.com.
- *
- * (C) Copyright 2000-2011
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ide.h>
-#include <ata.h>
-#include <asm/io.h>
-
-#define EIEIO __asm__ volatile ("eieio")
-#define SYNC __asm__ volatile ("sync")
-
-void ide_input_swap_data(int dev, ulong *sect_buf, int words)
-{
- uchar i;
- volatile uchar *pbuf_even =
- (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN);
- volatile uchar *pbuf_odd =
- (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD);
- ushort *dbuf = (ushort *) sect_buf;
-
- while (words--) {
- for (i = 0; i < 2; i++) {
- *(((uchar *) (dbuf)) + 1) = *pbuf_even;
- *(uchar *) dbuf = *pbuf_odd;
- dbuf += 1;
- }
- }
-}
-
-void ide_input_data(int dev, ulong *sect_buf, int words)
-{
- uchar *dbuf;
- volatile uchar *pbuf_even;
- volatile uchar *pbuf_odd;
-
- pbuf_even = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN);
- pbuf_odd = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD);
- dbuf = (uchar *) sect_buf;
- while (words--) {
- *dbuf++ = *pbuf_even;
- EIEIO;
- SYNC;
- *dbuf++ = *pbuf_odd;
- EIEIO;
- SYNC;
- *dbuf++ = *pbuf_even;
- EIEIO;
- SYNC;
- *dbuf++ = *pbuf_odd;
- EIEIO;
- SYNC;
- }
-}
-
-void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
-{
- uchar *dbuf;
- volatile uchar *pbuf_even;
- volatile uchar *pbuf_odd;
-
- pbuf_even = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN);
- pbuf_odd = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD);
- dbuf = (uchar *) sect_buf;
- while (shorts--) {
- EIEIO;
- *dbuf++ = *pbuf_even;
- EIEIO;
- *dbuf++ = *pbuf_odd;
- }
-}
-
-void ide_output_data(int dev, const ulong *sect_buf, int words)
-{
- uchar *dbuf;
- volatile uchar *pbuf_even;
- volatile uchar *pbuf_odd;
-
- pbuf_even = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN);
- pbuf_odd = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD);
- dbuf = (uchar *) sect_buf;
- while (words--) {
- EIEIO;
- *pbuf_even = *dbuf++;
- EIEIO;
- *pbuf_odd = *dbuf++;
- EIEIO;
- *pbuf_even = *dbuf++;
- EIEIO;
- *pbuf_odd = *dbuf++;
- }
-}
-
-void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
-{
- uchar *dbuf;
- volatile uchar *pbuf_even;
- volatile uchar *pbuf_odd;
-
- pbuf_even = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN);
- pbuf_odd = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD);
- dbuf = (uchar *) sect_buf;
- while (shorts--) {
- EIEIO;
- *pbuf_even = *dbuf++;
- EIEIO;
- *pbuf_odd = *dbuf++;
- }
-}
-
-void ide_led(uchar led, uchar status)
-{
- u_char val;
- /* We have one PCMCIA slot and use LED H4 for the IDE Interface */
- val = readb(BCSR_BASE + 0x04);
- if (status) /* led on */
- val |= B_CTRL_LED0;
- else
- val &= ~B_CTRL_LED0;
-
- writeb(val, BCSR_BASE + 0x04);
-}
diff --git a/board/cpc45/pd67290.c b/board/cpc45/pd67290.c
deleted file mode 100644
index 23d87f6..0000000
--- a/board/cpc45/pd67290.c
+++ /dev/null
@@ -1,797 +0,0 @@
-/*
- * (C) Copyright 2003-2005
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- ********************************************************************
- *
- * Lots of code copied from:
- *
- * i82365.c 1.352 - Linux driver for Intel 82365 and compatible
- * PC Card controllers, and Yenta-compatible PCI-to-CardBus controllers.
- * (C) 1999 David A. Hinds <dahinds@users.sourceforge.net>
- */
-
-#include <common.h>
-
-#ifdef CONFIG_I82365
-
-#include <command.h>
-#include <pci.h>
-#include <pcmcia.h>
-#include <asm/io.h>
-
-#include <pcmcia/ss.h>
-#include <pcmcia/i82365.h>
-#include <pcmcia/yenta.h>
-#include <pcmcia/cirrus.h>
-
-static struct pci_device_id supported[] = {
- {PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CIRRUS_6729},
- {0, 0}
-};
-
-#define CYCLE_TIME 120
-
-#ifdef DEBUG
-static void i82365_dump_regions (pci_dev_t dev);
-#endif
-
-typedef struct socket_info_t {
- pci_dev_t dev;
- u_short bcr;
- u_char pci_lat, cb_lat, sub_bus, cache;
- u_int cb_phys;
-
- socket_cap_t cap;
- u_short type;
- u_int flags;
- cirrus_state_t c_state;
-} socket_info_t;
-
-/* These definitions must match the pcic table! */
-typedef enum pcic_id {
- IS_PD6710, IS_PD672X, IS_VT83C469
-} pcic_id;
-
-typedef struct pcic_t {
- char *name;
-} pcic_t;
-
-static pcic_t pcic[] = {
- {" Cirrus PD6710: "},
- {" Cirrus PD672x: "},
- {" VIA VT83C469: "},
-};
-
-static socket_info_t socket;
-static socket_state_t state;
-static struct pccard_mem_map mem;
-static struct pccard_io_map io;
-
-/*====================================================================*/
-
-/* Some PCI shortcuts */
-
-static int pci_readb (socket_info_t * s, int r, u_char * v)
-{
- return pci_read_config_byte (s->dev, r, v);
-}
-static int pci_writeb (socket_info_t * s, int r, u_char v)
-{
- return pci_write_config_byte (s->dev, r, v);
-}
-static int pci_readw (socket_info_t * s, int r, u_short * v)
-{
- return pci_read_config_word (s->dev, r, v);
-}
-static int pci_writew (socket_info_t * s, int r, u_short v)
-{
- return pci_write_config_word (s->dev, r, v);
-}
-
-/*====================================================================*/
-
-#define cb_readb(s) readb((s)->cb_phys + 1)
-#define cb_writeb(s, v) writeb(v, (s)->cb_phys)
-#define cb_writeb2(s, v) writeb(v, (s)->cb_phys + 1)
-#define cb_readl(s, r) readl((s)->cb_phys + (r))
-#define cb_writel(s, r, v) writel(v, (s)->cb_phys + (r))
-
-
-static u_char i365_get (socket_info_t * s, u_short reg)
-{
- u_char val;
-#ifdef CONFIG_PCMCIA_SLOT_A
- int slot = 0;
-#else
- int slot = 1;
-#endif
-
- val = I365_REG (slot, reg);
-
- cb_writeb (s, val);
- val = cb_readb (s);
-
- debug ("i365_get slot:%x reg: %x val: %x\n", slot, reg, val);
- return val;
-}
-
-static void i365_set (socket_info_t * s, u_short reg, u_char data)
-{
-#ifdef CONFIG_PCMCIA_SLOT_A
- int slot = 0;
-#else
- int slot = 1;
-#endif
- u_char val;
-
- val = I365_REG (slot, reg);
-
- cb_writeb (s, val);
- cb_writeb2 (s, data);
-
- debug ("i365_set slot:%x reg: %x data:%x\n", slot, reg, data);
-}
-
-static void i365_bset (socket_info_t * s, u_short reg, u_char mask)
-{
- i365_set (s, reg, i365_get (s, reg) | mask);
-}
-
-static void i365_bclr (socket_info_t * s, u_short reg, u_char mask)
-{
- i365_set (s, reg, i365_get (s, reg) & ~mask);
-}
-
-#if 0 /* not used */
-static void i365_bflip (socket_info_t * s, u_short reg, u_char mask, int b)
-{
- u_char d = i365_get (s, reg);
-
- i365_set (s, reg, (b) ? (d | mask) : (d & ~mask));
-}
-
-static u_short i365_get_pair (socket_info_t * s, u_short reg)
-{
- return (i365_get (s, reg) + (i365_get (s, reg + 1) << 8));
-}
-#endif /* not used */
-
-static void i365_set_pair (socket_info_t * s, u_short reg, u_short data)
-{
- i365_set (s, reg, data & 0xff);
- i365_set (s, reg + 1, data >> 8);
-}
-
-/*======================================================================
-
- Code to save and restore global state information for Cirrus
- PD67xx controllers, and to set and report global configuration
- options.
-
-======================================================================*/
-
-#define flip(v,b,f) (v = ((f)<0) ? v : ((f) ? ((v)|(b)) : ((v)&(~b))))
-
-static void cirrus_get_state (socket_info_t * s)
-{
- int i;
- cirrus_state_t *p = &s->c_state;
-
- p->misc1 = i365_get (s, PD67_MISC_CTL_1);
- p->misc1 &= (PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA);
- p->misc2 = i365_get (s, PD67_MISC_CTL_2);
- for (i = 0; i < 6; i++)
- p->timer[i] = i365_get (s, PD67_TIME_SETUP (0) + i);
-
-}
-
-static void cirrus_set_state (socket_info_t * s)
-{
- int i;
- u_char misc;
- cirrus_state_t *p = &s->c_state;
-
- misc = i365_get (s, PD67_MISC_CTL_2);
- i365_set (s, PD67_MISC_CTL_2, p->misc2);
- if (misc & PD67_MC2_SUSPEND)
- udelay (50000);
- misc = i365_get (s, PD67_MISC_CTL_1);
- misc &= ~(PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA);
- i365_set (s, PD67_MISC_CTL_1, misc | p->misc1);
- for (i = 0; i < 6; i++)
- i365_set (s, PD67_TIME_SETUP (0) + i, p->timer[i]);
-}
-
-static u_int cirrus_set_opts (socket_info_t * s)
-{
- cirrus_state_t *p = &s->c_state;
- u_int mask = 0xffff;
- char buf[200] = {0};
-
- if (has_ring == -1)
- has_ring = 1;
- flip (p->misc2, PD67_MC2_IRQ15_RI, has_ring);
- flip (p->misc2, PD67_MC2_DYNAMIC_MODE, dynamic_mode);
-#if DEBUG
- if (p->misc2 & PD67_MC2_IRQ15_RI)
- strcat (buf, " [ring]");
- if (p->misc2 & PD67_MC2_DYNAMIC_MODE)
- strcat (buf, " [dyn mode]");
- if (p->misc1 & PD67_MC1_INPACK_ENA)
- strcat (buf, " [inpack]");
-#endif
-
- if (p->misc2 & PD67_MC2_IRQ15_RI)
- mask &= ~0x8000;
- if (has_led > 0) {
-#if DEBUG
- strcat (buf, " [led]");
-#endif
- mask &= ~0x1000;
- }
- if (has_dma > 0) {
-#if DEBUG
- strcat (buf, " [dma]");
-#endif
- mask &= ~0x0600;
- flip (p->misc2, PD67_MC2_FREQ_BYPASS, freq_bypass);
-#if DEBUG
- if (p->misc2 & PD67_MC2_FREQ_BYPASS)
- strcat (buf, " [freq bypass]");
-#endif
- }
-
- if (setup_time >= 0)
- p->timer[0] = p->timer[3] = setup_time;
- if (cmd_time > 0) {
- p->timer[1] = cmd_time;
- p->timer[4] = cmd_time * 2 + 4;
- }
- if (p->timer[1] == 0) {
- p->timer[1] = 6;
- p->timer[4] = 16;
- if (p->timer[0] == 0)
- p->timer[0] = p->timer[3] = 1;
- }
- if (recov_time >= 0)
- p->timer[2] = p->timer[5] = recov_time;
-
- debug ("i82365 Opt: %s [%d/%d/%d] [%d/%d/%d]\n",
- buf,
- p->timer[0], p->timer[1], p->timer[2],
- p->timer[3], p->timer[4], p->timer[5]);
-
- return mask;
-}
-
-/*======================================================================
-
- Routines to handle common CardBus options
-
-======================================================================*/
-
-/* Default settings for PCI command configuration register */
-#define CMD_DFLT (PCI_COMMAND_IO|PCI_COMMAND_MEMORY| \
- PCI_COMMAND_MASTER|PCI_COMMAND_WAIT)
-
-static void cb_get_state (socket_info_t * s)
-{
- pci_readb (s, PCI_CACHE_LINE_SIZE, &s->cache);
- pci_readb (s, PCI_LATENCY_TIMER, &s->pci_lat);
- pci_readb (s, CB_LATENCY_TIMER, &s->cb_lat);
- pci_readb (s, CB_CARDBUS_BUS, &s->cap.cardbus);
- pci_readb (s, CB_SUBORD_BUS, &s->sub_bus);
- pci_readw (s, CB_BRIDGE_CONTROL, &s->bcr);
-}
-
-static void cb_set_state (socket_info_t * s)
-{
- pci_writew (s, PCI_COMMAND, CMD_DFLT);
- pci_writeb (s, PCI_CACHE_LINE_SIZE, s->cache);
- pci_writeb (s, PCI_LATENCY_TIMER, s->pci_lat);
- pci_writeb (s, CB_LATENCY_TIMER, s->cb_lat);
- pci_writeb (s, CB_CARDBUS_BUS, s->cap.cardbus);
- pci_writeb (s, CB_SUBORD_BUS, s->sub_bus);
- pci_writew (s, CB_BRIDGE_CONTROL, s->bcr);
-}
-
-static void cb_set_opts (socket_info_t * s)
-{
-}
-
-/*======================================================================
-
- Power control for Cardbus controllers: used both for 16-bit and
- Cardbus cards.
-
-======================================================================*/
-
-static int cb_set_power (socket_info_t * s, socket_state_t * state)
-{
- u_int reg = 0;
-
- reg = I365_PWR_NORESET;
- if (state->flags & SS_PWR_AUTO)
- reg |= I365_PWR_AUTO;
- if (state->flags & SS_OUTPUT_ENA)
- reg |= I365_PWR_OUT;
- if (state->Vpp != 0) {
- if (state->Vpp == 120) {
- reg |= I365_VPP1_12V;
- puts (" 12V card found: ");
- } else if (state->Vpp == state->Vcc) {
- reg |= I365_VPP1_5V;
- } else {
- puts (" power not found: ");
- return -1;
- }
- }
- if (state->Vcc != 0) {
- reg |= I365_VCC_5V;
- if (state->Vcc == 33) {
- puts (" 3.3V card found: ");
- i365_bset (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
- } else if (state->Vcc == 50) {
- puts (" 5V card found: ");
- i365_bclr (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
- } else {
- puts (" power not found: ");
- return -1;
- }
- }
-
- if (reg != i365_get (s, I365_POWER)) {
- reg = (I365_PWR_OUT | I365_PWR_NORESET | I365_VCC_5V | I365_VPP1_5V);
- i365_set (s, I365_POWER, reg);
- }
-
- return 0;
-}
-
-/*======================================================================
-
- Generic routines to get and set controller options
-
-======================================================================*/
-
-static void get_bridge_state (socket_info_t * s)
-{
- cirrus_get_state (s);
- cb_get_state (s);
-}
-
-static void set_bridge_state (socket_info_t * s)
-{
- cb_set_state (s);
- i365_set (s, I365_GBLCTL, 0x00);
- i365_set (s, I365_GENCTL, 0x00);
- cirrus_set_state (s);
-}
-
-static void set_bridge_opts (socket_info_t * s)
-{
- cirrus_set_opts (s);
- cb_set_opts (s);
-}
-
-/*====================================================================*/
-#define PD67_EXT_INDEX 0x2e /* Extension index */
-#define PD67_EXT_DATA 0x2f /* Extension data */
-#define PD67_EXD_VS1(s) (0x01 << ((s)<<1))
-
-#define pd67_ext_get(s, r) \
- (i365_set(s, PD67_EXT_INDEX, r), i365_get(s, PD67_EXT_DATA))
-
-static int i365_get_status (socket_info_t * s, u_int * value)
-{
- u_int status;
- u_char val;
- u_char power, vcc, vpp;
- u_int powerstate;
-
- status = i365_get (s, I365_IDENT);
- status = i365_get (s, I365_STATUS);
- *value = ((status & I365_CS_DETECT) == I365_CS_DETECT) ? SS_DETECT : 0;
- if (i365_get (s, I365_INTCTL) & I365_PC_IOCARD) {
- *value |= (status & I365_CS_STSCHG) ? 0 : SS_STSCHG;
- } else {
- *value |= (status & I365_CS_BVD1) ? 0 : SS_BATDEAD;
- *value |= (status & I365_CS_BVD2) ? 0 : SS_BATWARN;
- }
- *value |= (status & I365_CS_WRPROT) ? SS_WRPROT : 0;
- *value |= (status & I365_CS_READY) ? SS_READY : 0;
- *value |= (status & I365_CS_POWERON) ? SS_POWERON : 0;
-
- /* Check for Cirrus CL-PD67xx chips */
- i365_set (s, PD67_CHIP_INFO, 0);
- val = i365_get (s, PD67_CHIP_INFO);
- s->type = -1;
- if ((val & PD67_INFO_CHIP_ID) == PD67_INFO_CHIP_ID) {
- val = i365_get (s, PD67_CHIP_INFO);
- if ((val & PD67_INFO_CHIP_ID) == 0) {
- s->type = (val & PD67_INFO_SLOTS) ? IS_PD672X : IS_PD6710;
- i365_set (s, PD67_EXT_INDEX, 0xe5);
- if (i365_get (s, PD67_EXT_INDEX) != 0xe5)
- s->type = IS_VT83C469;
- }
- } else {
- printf ("no Cirrus Chip found\n");
- *value = 0;
- return -1;
- }
-
- power = i365_get (s, I365_POWER);
- state.flags |= (power & I365_PWR_AUTO) ? SS_PWR_AUTO : 0;
- state.flags |= (power & I365_PWR_OUT) ? SS_OUTPUT_ENA : 0;
- vcc = power & I365_VCC_MASK;
- vpp = power & I365_VPP1_MASK;
- state.Vcc = state.Vpp = 0;
- if((vcc== 0) || (vpp == 0)) {
- /*
- * On the Cirrus we get the info which card voltage
- * we have in EXTERN DATA and write it to MISC_CTL1
- */
- powerstate = pd67_ext_get(s, PD67_EXTERN_DATA);
- if (powerstate & PD67_EXD_VS1(0)) {
- /* 5V Card */
- i365_bclr (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
- } else {
- /* 3.3V Card */
- i365_bset (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
- }
- i365_set (s, I365_POWER, (I365_PWR_OUT | I365_PWR_NORESET | I365_VCC_5V | I365_VPP1_5V));
- power = i365_get (s, I365_POWER);
- }
- if (power & I365_VCC_5V) {
- state.Vcc = (i365_get(s, PD67_MISC_CTL_1) & PD67_MC1_VCC_3V) ? 33 : 50;
- }
-
- if (power == I365_VPP1_12V)
- state.Vpp = 120;
-
- /* IO card, RESET flags, IO interrupt */
- power = i365_get (s, I365_INTCTL);
- state.flags |= (power & I365_PC_RESET) ? 0 : SS_RESET;
- if (power & I365_PC_IOCARD)
- state.flags |= SS_IOCARD;
- state.io_irq = power & I365_IRQ_MASK;
-
- /* Card status change mask */
- power = i365_get (s, I365_CSCINT);
- state.csc_mask = (power & I365_CSC_DETECT) ? SS_DETECT : 0;
- if (state.flags & SS_IOCARD)
- state.csc_mask |= (power & I365_CSC_STSCHG) ? SS_STSCHG : 0;
- else {
- state.csc_mask |= (power & I365_CSC_BVD1) ? SS_BATDEAD : 0;
- state.csc_mask |= (power & I365_CSC_BVD2) ? SS_BATWARN : 0;
- state.csc_mask |= (power & I365_CSC_READY) ? SS_READY : 0;
- }
- debug ("i82365: GetStatus(0) = flags %#3.3x, Vcc %d, Vpp %d, "
- "io_irq %d, csc_mask %#2.2x\n", state.flags,
- state.Vcc, state.Vpp, state.io_irq, state.csc_mask);
-
- return 0;
-} /* i365_get_status */
-
-static int i365_set_socket (socket_info_t * s, socket_state_t * state)
-{
- u_char reg;
-
- set_bridge_state (s);
-
- /* IO card, RESET flag */
- reg = 0;
- reg |= (state->flags & SS_RESET) ? 0 : I365_PC_RESET;
- reg |= (state->flags & SS_IOCARD) ? I365_PC_IOCARD : 0;
- i365_set (s, I365_INTCTL, reg);
-
- cb_set_power (s, state);
-
-#if 0
- /* Card status change interrupt mask */
- reg = s->cs_irq << 4;
- if (state->csc_mask & SS_DETECT)
- reg |= I365_CSC_DETECT;
- if (state->flags & SS_IOCARD) {
- if (state->csc_mask & SS_STSCHG)
- reg |= I365_CSC_STSCHG;
- } else {
- if (state->csc_mask & SS_BATDEAD)
- reg |= I365_CSC_BVD1;
- if (state->csc_mask & SS_BATWARN)
- reg |= I365_CSC_BVD2;
- if (state->csc_mask & SS_READY)
- reg |= I365_CSC_READY;
- }
- i365_set (s, I365_CSCINT, reg);
- i365_get (s, I365_CSC);
-#endif /* 0 */
-
- return 0;
-} /* i365_set_socket */
-
-/*====================================================================*/
-
-static int i365_set_mem_map (socket_info_t * s, struct pccard_mem_map *mem)
-{
- u_short base, i;
- u_char map;
-
- debug ("i82365: SetMemMap(%d, %#2.2x, %d ns, %#5.5lx-%#5.5lx, %#5.5x)\n",
- mem->map, mem->flags, mem->speed,
- mem->sys_start, mem->sys_stop, mem->card_start);
-
- map = mem->map;
- if ((map > 4) ||
- (mem->card_start > 0x3ffffff) ||
- (mem->sys_start > mem->sys_stop) ||
- (mem->speed > 1000)) {
- return -1;
- }
-
- /* Turn off the window before changing anything */
- if (i365_get (s, I365_ADDRWIN) & I365_ENA_MEM (map))
- i365_bclr (s, I365_ADDRWIN, I365_ENA_MEM (map));
-
- /* Take care of high byte, for PCI controllers */
- i365_set (s, CB_MEM_PAGE (map), mem->sys_start >> 24);
-
- base = I365_MEM (map);
- i = (mem->sys_start >> 12) & 0x0fff;
- if (mem->flags & MAP_16BIT)
- i |= I365_MEM_16BIT;
- if (mem->flags & MAP_0WS)
- i |= I365_MEM_0WS;
- i365_set_pair (s, base + I365_W_START, i);
-
- i = (mem->sys_stop >> 12) & 0x0fff;
- switch (mem->speed / CYCLE_TIME) {
- case 0:
- break;
- case 1:
- i |= I365_MEM_WS0;
- break;
- case 2:
- i |= I365_MEM_WS1;
- break;
- default:
- i |= I365_MEM_WS1 | I365_MEM_WS0;
- break;
- }
- i365_set_pair (s, base + I365_W_STOP, i);
-
- i = 0;
- if (mem->flags & MAP_WRPROT)
- i |= I365_MEM_WRPROT;
- if (mem->flags & MAP_ATTRIB)
- i |= I365_MEM_REG;
- i365_set_pair (s, base + I365_W_OFF, i);
-
- /* set System Memory map Upper Adress */
- i365_set(s, PD67_EXT_INDEX, PD67_MEM_PAGE(map));
- i365_set(s, PD67_EXT_DATA, ((mem->sys_start >> 24) & 0xff));
-
- /* Turn on the window if necessary */
- if (mem->flags & MAP_ACTIVE)
- i365_bset (s, I365_ADDRWIN, I365_ENA_MEM (map));
- return 0;
-} /* i365_set_mem_map */
-
-static int i365_set_io_map (socket_info_t * s, struct pccard_io_map *io)
-{
- u_char map, ioctl;
-
- map = io->map;
- /* comment out: comparison is always false due to limited range of data type */
- if ((map > 1) || /* (io->start > 0xffff) || (io->stop > 0xffff) || */
- (io->stop < io->start))
- return -1;
- /* Turn off the window before changing anything */
- if (i365_get (s, I365_ADDRWIN) & I365_ENA_IO (map))
- i365_bclr (s, I365_ADDRWIN, I365_ENA_IO (map));
- i365_set_pair (s, I365_IO (map) + I365_W_START, io->start);
- i365_set_pair (s, I365_IO (map) + I365_W_STOP, io->stop);
- ioctl = i365_get (s, I365_IOCTL) & ~I365_IOCTL_MASK (map);
- if (io->speed)
- ioctl |= I365_IOCTL_WAIT (map);
- if (io->flags & MAP_0WS)
- ioctl |= I365_IOCTL_0WS (map);
- if (io->flags & MAP_16BIT)
- ioctl |= I365_IOCTL_16BIT (map);
- if (io->flags & MAP_AUTOSZ)
- ioctl |= I365_IOCTL_IOCS16 (map);
- i365_set (s, I365_IOCTL, ioctl);
- /* Turn on the window if necessary */
- if (io->flags & MAP_ACTIVE)
- i365_bset (s, I365_ADDRWIN, I365_ENA_IO (map));
- return 0;
-} /* i365_set_io_map */
-
-/*====================================================================*/
-
-/*
- * PCI_ADDR = (HOST_ADDR - 0xfe000000)
- * see MPC 8245 Users Manual Adress Map B
- */
-#define HOST_TO_PCI(addr) ((addr) - 0xfe000000)
-#define PCI_TO_HOST(addr) ((addr) + 0xfe000000)
-
-static int i82365_init (void)
-{
- u_int val;
- int i;
-
- if ((socket.dev = pci_find_devices (supported, 0)) < 0) {
- /* Controller not found */
- printf ("No PD67290 device found !!\n");
- return 1;
- }
- debug ("i82365 Device Found!\n");
-
- socket.cb_phys = PCMCIA_IO_BASE;
-
- /* set base address */
- pci_write_config_dword (socket.dev, PCI_BASE_ADDRESS_0,
- HOST_TO_PCI(socket.cb_phys));
-
- /* enable mapped memory and IO addresses */
- pci_write_config_dword (socket.dev,
- PCI_COMMAND,
- PCI_COMMAND_MEMORY |
- PCI_COMMAND_IO | PCI_COMMAND_WAIT);
-
- get_bridge_state (&socket);
- set_bridge_opts (&socket);
-
- i = i365_get_status (&socket, &val);
-
- if (i > -1) {
- puts (pcic[socket.type].name);
- } else {
- printf ("i82365: Controller not found.\n");
- return 1;
- }
- if((val & SS_DETECT) != SS_DETECT){
- puts ("No card\n");
- return 1;
- }
-
- state.flags |= SS_OUTPUT_ENA;
-
- i365_set_socket (&socket, &state);
-
- for (i = 500; i; i--) {
- if ((i365_get (&socket, I365_STATUS) & I365_CS_READY))
- break;
- udelay (1000);
- }
-
- if (i == 0) {
- /* PC Card not ready for data transfer */
- puts ("i82365 PC Card not ready for data transfer\n");
- return 1;
- }
- debug (" PC Card ready for data transfer: ");
-
- mem.map = 0;
- mem.flags = MAP_ATTRIB | MAP_ACTIVE;
- mem.speed = 300;
- mem.sys_start = CONFIG_SYS_PCMCIA_MEM_ADDR;
- mem.sys_stop = CONFIG_SYS_PCMCIA_MEM_ADDR + CONFIG_SYS_PCMCIA_MEM_SIZE - 1;
- mem.card_start = 0;
- i365_set_mem_map (&socket, &mem);
-
- mem.map = 1;
- mem.flags = MAP_ACTIVE;
- mem.speed = 300;
- mem.sys_start = CONFIG_SYS_PCMCIA_MEM_ADDR + CONFIG_SYS_PCMCIA_MEM_SIZE;
- mem.sys_stop = CONFIG_SYS_PCMCIA_MEM_ADDR + (2 * CONFIG_SYS_PCMCIA_MEM_SIZE) - 1;
- mem.card_start = 0;
- i365_set_mem_map (&socket, &mem);
-
-#ifdef DEBUG
- i82365_dump_regions (socket.dev);
-#endif
-
- return 0;
-}
-
-static void i82365_exit (void)
-{
- io.map = 0;
- io.flags = 0;
- io.speed = 0;
- io.start = 0;
- io.stop = 0x1;
-
- i365_set_io_map (&socket, &io);
-
- mem.map = 0;
- mem.flags = 0;
- mem.speed = 0;
- mem.sys_start = 0;
- mem.sys_stop = 0x1000;
- mem.card_start = 0;
-
- i365_set_mem_map (&socket, &mem);
-
- mem.map = 1;
- mem.flags = 0;
- mem.speed = 0;
- mem.sys_start = 0;
- mem.sys_stop = 0x1000;
- mem.card_start = 0;
-
- i365_set_mem_map (&socket, &mem);
-
- state.Vcc = state.Vpp = 0;
-
- i365_set_socket (&socket, &state);
-}
-
-int pcmcia_on (void)
-{
- u_int rc;
-
- debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n");
-
- rc = i82365_init();
- if (rc)
- goto exit;
-
- rc = check_ide_device(0);
- if (rc == 0)
- goto exit;
-
- i82365_exit();
-
-exit:
- return rc;
-}
-
-#if defined(CONFIG_CMD_PCMCIA)
-int pcmcia_off (void)
-{
- printf ("Disable PCMCIA " PCMCIA_SLOT_MSG "\n");
-
- i82365_exit();
-
- return 0;
-}
-#endif
-
-/*======================================================================
-
- Debug stuff
-
-======================================================================*/
-
-#ifdef DEBUG
-static void i82365_dump_regions (pci_dev_t dev)
-{
- u_int tmp[2];
- u_int *mem = (void *) socket.cb_phys;
- u_char *cis = (void *) CONFIG_SYS_PCMCIA_MEM_ADDR;
- u_char *ide = (void *) (CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_REG_OFFSET);
-
- pci_read_config_dword (dev, 0x00, tmp + 0);
- pci_read_config_dword (dev, 0x80, tmp + 1);
-
- printf ("PCI CONF: %08X ... %08X\n",
- tmp[0], tmp[1]);
- printf ("PCI MEM: ... %08X ... %08X\n",
- mem[0x8 / 4], mem[0x800 / 4]);
- printf ("CIS: ...%c%c%c%c%c%c%c%c...\n",
- cis[0x38], cis[0x3a], cis[0x3c], cis[0x3e],
- cis[0x40], cis[0x42], cis[0x44], cis[0x48]);
- printf ("CIS CONF: %02X %02X %02X ...\n",
- cis[0x200], cis[0x202], cis[0x204]);
- printf ("IDE: %02X %02X %02X %02X %02X %02X %02X %02X\n",
- ide[0], ide[1], ide[2], ide[3],
- ide[4], ide[5], ide[6], ide[7]);
-}
-#endif /* DEBUG */
-
-#endif /* CONFIG_I82365 */
diff --git a/board/cpc45/plx9030.c b/board/cpc45/plx9030.c
deleted file mode 100644
index 06fb8d6..0000000
--- a/board/cpc45/plx9030.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/* Plx9030.c - system configuration module for PLX9030 PCI to Local Bus Bridge */
-/*
- * (C) Copyright 2002-2003
- * Josef Wagner, MicroSys GmbH, wagner at microsys.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- * Date Modification by
- * ------- ---------------------------------------------- ---
- * 30sep02 converted from VxWorks to LINUX wa
-*/
-
-
-/*
-DESCRIPTION
-
-This is the configuration module for the PLX9030 PCI to Local Bus Bridge.
-It configures the Chip select lines for SRAM (CS0), ST16C552 (CS1,CS2), Display and local
-registers (CS3) on CPC45.
-*/
-
-/* includes */
-
-#include <common.h>
-#include <malloc.h>
-#include <net.h>
-#include <asm/io.h>
-#include <pci.h>
-
-/* imports */
-
-
-/* defines */
-#define PLX9030_VENDOR_ID 0x10B5
-#define PLX9030_DEVICE_ID 0x9030
-
-#undef PLX_DEBUG
-
-/* PLX9030 register offsets */
-#define P9030_LAS0RR 0x00
-#define P9030_LAS1RR 0x04
-#define P9030_LAS2RR 0x08
-#define P9030_LAS3RR 0x0c
-#define P9030_EROMRR 0x10
-#define P9030_LAS0BA 0x14
-#define P9030_LAS1BA 0x18
-#define P9030_LAS2BA 0x1c
-#define P9030_LAS3BA 0x20
-#define P9030_EROMBA 0x24
-#define P9030_LAS0BRD 0x28
-#define P9030_LAS1BRD 0x2c
-#define P9030_LAS2BRD 0x30
-#define P9030_LAS3BRD 0x34
-#define P9030_EROMBRD 0x38
-#define P9030_CS0BASE 0x3C
-#define P9030_CS1BASE 0x40
-#define P9030_CS2BASE 0x44
-#define P9030_CS3BASE 0x48
-#define P9030_INTCSR 0x4c
-#define P9030_CNTRL 0x50
-#define P9030_GPIOC 0x54
-
-/* typedefs */
-
-
-/* locals */
-
-static struct pci_device_id supported[] = {
- { PLX9030_VENDOR_ID, PLX9030_DEVICE_ID },
- { }
-};
-
-/* forward declarations */
-void sysOutLong(ulong address, ulong value);
-
-
-/***************************************************************************
-*
-* Plx9030Init - init CS0..CS3 for CPC45
-*
-*
-* RETURNS: N/A
-*/
-
-void Plx9030Init (void)
-{
- pci_dev_t devno;
- ulong membaseCsr; /* base address of device memory space */
- int idx = 0; /* general index */
-
-
- /* find plx9030 device */
-
- if ((devno = pci_find_devices(supported, idx++)) < 0)
- {
- printf("No PLX9030 device found !!\n");
- return;
- }
-
-
-#ifdef PLX_DEBUG
- printf("PLX 9030 device found ! devno = 0x%x\n",devno);
-#endif
-
- membaseCsr = PCI_PLX9030_MEMADDR;
-
- /* set base address */
- pci_write_config_dword(devno, PCI_BASE_ADDRESS_0, membaseCsr);
-
- /* enable mapped memory and IO addresses */
- pci_write_config_dword(devno,
- PCI_COMMAND,
- PCI_COMMAND_MEMORY |
- PCI_COMMAND_MASTER);
-
-
- /* configure GBIOC */
- sysOutLong((membaseCsr + P9030_GPIOC), 0x00000FC0); /* CS2/CS3 enable */
-
- /* configure CS0 (SRAM) */
- sysOutLong((membaseCsr + P9030_LAS0BA), 0x00000001); /* enable space base */
- sysOutLong((membaseCsr + P9030_LAS0RR), 0x0FE00000); /* 2 MByte */
- sysOutLong((membaseCsr + P9030_LAS0BRD), 0x51928900); /* 4 wait states */
- sysOutLong((membaseCsr + P9030_CS0BASE), 0x00100001); /* enable 2 MByte */
- /* remap CS0 (SRAM) */
- pci_write_config_dword(devno, PCI_BASE_ADDRESS_2, SRAM_BASE);
-
- /* configure CS1 (ST16552 / CHAN A) */
- sysOutLong((membaseCsr + P9030_LAS1BA), 0x00400001); /* enable space base */
- sysOutLong((membaseCsr + P9030_LAS1RR), 0x0FFFFF00); /* 256 byte */
- sysOutLong((membaseCsr + P9030_LAS1BRD), 0x55122900); /* 4 wait states */
- sysOutLong((membaseCsr + P9030_CS1BASE), 0x00400081); /* enable 256 Byte */
- /* remap CS1 (ST16552 / CHAN A) */
- /* remap CS1 (ST16552 / CHAN A) */
- pci_write_config_dword(devno, PCI_BASE_ADDRESS_3, ST16552_A_BASE);
-
- /* configure CS2 (ST16552 / CHAN B) */
- sysOutLong((membaseCsr + P9030_LAS2BA), 0x00800001); /* enable space base */
- sysOutLong((membaseCsr + P9030_LAS2RR), 0x0FFFFF00); /* 256 byte */
- sysOutLong((membaseCsr + P9030_LAS2BRD), 0x55122900); /* 4 wait states */
- sysOutLong((membaseCsr + P9030_CS2BASE), 0x00800081); /* enable 256 Byte */
- /* remap CS2 (ST16552 / CHAN B) */
- pci_write_config_dword(devno, PCI_BASE_ADDRESS_4, ST16552_B_BASE);
-
- /* configure CS3 (BCSR) */
- sysOutLong((membaseCsr + P9030_LAS3BA), 0x00C00001); /* enable space base */
- sysOutLong((membaseCsr + P9030_LAS3RR), 0x0FFFFF00); /* 256 byte */
- sysOutLong((membaseCsr + P9030_LAS3BRD), 0x55357A80); /* 9 wait states */
- sysOutLong((membaseCsr + P9030_CS3BASE), 0x00C00081); /* enable 256 Byte */
- /* remap CS3 (DISPLAY and BCSR) */
- pci_write_config_dword(devno, PCI_BASE_ADDRESS_5, BCSR_BASE);
-}
-
-void sysOutLong(ulong address, ulong value)
-{
- *(ulong*)address = cpu_to_le32(value);
-}
diff --git a/board/cu824/Kconfig b/board/cu824/Kconfig
deleted file mode 100644
index 7927b05..0000000
--- a/board/cu824/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_CU824
-
-config SYS_BOARD
- default "cu824"
-
-config SYS_CONFIG_NAME
- default "CU824"
-
-endif
diff --git a/board/cu824/MAINTAINERS b/board/cu824/MAINTAINERS
deleted file mode 100644
index b1b7190..0000000
--- a/board/cu824/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-CU824 BOARD
-M: Wolfgang Denk <wd@denx.de>
-S: Maintained
-F: board/cu824/
-F: include/configs/CU824.h
-F: configs/CU824_defconfig
diff --git a/board/cu824/Makefile b/board/cu824/Makefile
deleted file mode 100644
index e7bd7ca..0000000
--- a/board/cu824/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = cu824.o flash.o
diff --git a/board/cu824/README b/board/cu824/README
deleted file mode 100644
index cc0d207..0000000
--- a/board/cu824/README
+++ /dev/null
@@ -1,453 +0,0 @@
-ppcboot for a CU824 board
----------------------------
-
-CU824 has two banks of flash 8MB each. In board's notation, bank 0 is
-the one at the address of 0xFF800000 and bank 1 is the one at the
-address of 0xFF000000. On power-up the processor jumps to the address
-of 0xFFF00100, the last megabyte of the bank 0 of flash. Thus,
-U-Boot is configured to reside in flash starting at the address of
-0xFFF00000. The environment space is not embedded in the U-Boot code
-and is located in flash separately from U-Boot, at the address of
-0xFF008000.
-
-
-U-Boot test results
---------------------
-
-x.x Operation on all available serial consoles
-
-x.x.x CONFIG_CONS_INDEX 1
-
-
-ppcboot 0.9.2 (May 13 2001 - 17:56:46)
-
-Initializing...
- CPU: MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache
- Board: CU824 Revision 1 Local Bus at 99 MHz
- DRAM: 64 MB
- FLASH: 16 MB
- In: serial
- Out: serial
- Err: serial
-
-Hit any key to stop autoboot: 0
-=>
-=>he
-go - start application at address 'addr'
-run - run commands in an environment variable
-bootm - boot application image from memory
-bootp - boot image via network using BootP/TFTP protocol
-tftpboot- boot image via network using TFTP protocol
- and env variables ipaddr and serverip
-rarpboot- boot image via network using RARP/TFTP protocol
-bootd - boot default, i.e., run 'bootcmd'
-loads - load S-Record file over serial line
-loadb - load binary file over serial line (kermit mode)
-md - memory display
-mm - memory modify (auto-incrementing)
-nm - memory modify (constant address)
-mw - memory write (fill)
-cp - memory copy
-cmp - memory compare
-crc32 - checksum calculation
-base - print or set address offset
-printenv- print environment variables
-setenv - set environment variables
-saveenv - save environment variables to persistent storage
-protect - enable or disable FLASH write protection
-erase - erase FLASH memory
-flinfo - print FLASH memory information
-bdinfo - print Board Info structure
-iminfo - print header information for application image
-coninfo - print console devices and informations
-loop - infinite loop on address range
-mtest - simple RAM test
-icache - enable or disable instruction cache
-dcache - enable or disable data cache
-reset - Perform RESET of the CPU
-echo - echo args to console
-version - print monitor version
-help - print online help
-? - alias for 'help'
-=>
-
-
-x.x.x CONFIG_CONS_INDEX 2
-
-**** NOT TESTED ****
-
-x.x Flash Driver Operation
-
-x.x.x Erase Operation
-
-
-ppcboot 0.9.2 (May 13 2001 - 17:56:46)
-
-Initializing...
- CPU: MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache
- Board: CU824 Revision 1 Local Bus at 99 MHz
- DRAM: 64 MB
- FLASH: 16 MB
- In: serial
- Out: serial
- Err: serial
-
-Hit any key to stop autoboot: 0
-=>
-=>
-=>
-=>md ff000000
-ff000000: 27051956 70706362 6f6f7420 302e382e '..Vppcboot 0.8.
-ff000010: 3320284d 61792031 31203230 3031202d 3 (May 11 2001 -
-ff000020: 2031343a 35373a30 33290000 00000000 14:57:03)......
-ff000030: 00000000 00000000 00000000 00000000 ................
-ff000040: 00000000 00000000 00000000 00000000 ................
-ff000050: 00000000 00000000 00000000 00000000 ................
-ff000060: 00000000 00000000 00000000 00000000 ................
-ff000070: 00000000 00000000 00000000 00000000 ................
-ff000080: 00000000 00000000 00000000 00000000 ................
-ff000090: 00000000 00000000 00000000 00000000 ................
-ff0000a0: 00000000 00000000 00000000 00000000 ................
-ff0000b0: 00000000 00000000 00000000 00000000 ................
-ff0000c0: 00000000 00000000 00000000 00000000 ................
-ff0000d0: 00000000 00000000 00000000 00000000 ................
-ff0000e0: 00000000 00000000 00000000 00000000 ................
-ff0000f0: 00000000 00000000 00000000 00000000 ................
-=>erase ff000000 ff007fff
-Erase Flash from 0xff000000 to 0xff007fff
- done
-Erased 1 sectors
-=>md ff000000
-ff000000: ffffffff ffffffff ffffffff ffffffff ................
-ff000010: ffffffff ffffffff ffffffff ffffffff ................
-ff000020: ffffffff ffffffff ffffffff ffffffff ................
-ff000030: ffffffff ffffffff ffffffff ffffffff ................
-ff000040: ffffffff ffffffff ffffffff ffffffff ................
-ff000050: ffffffff ffffffff ffffffff ffffffff ................
-ff000060: ffffffff ffffffff ffffffff ffffffff ................
-ff000070: ffffffff ffffffff ffffffff ffffffff ................
-ff000080: ffffffff ffffffff ffffffff ffffffff ................
-ff000090: ffffffff ffffffff ffffffff ffffffff ................
-ff0000a0: ffffffff ffffffff ffffffff ffffffff ................
-ff0000b0: ffffffff ffffffff ffffffff ffffffff ................
-ff0000c0: ffffffff ffffffff ffffffff ffffffff ................
-ff0000d0: ffffffff ffffffff ffffffff ffffffff ................
-ff0000e0: ffffffff ffffffff ffffffff ffffffff ................
-ff0000f0: ffffffff ffffffff ffffffff ffffffff ................
-=>
-
-x.x.x Information
-
-
-ppcboot 0.9.2 (May 13 2001 - 17:56:46)
-
-Initializing...
- CPU: MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache
- Board: CU824 Revision 1 Local Bus at 99 MHz
- DRAM: 64 MB
- FLASH: 16 MB
- In: serial
- Out: serial
- Err: serial
-
-Hit any key to stop autoboot: 0
-=>
-=>
-=>
-=>
-=>flinfo
-
-Bank # 1: Intel: 28F160F3B (16Mbit)
- Size: 8 MB in 39 Sectors
- Sector Start Addresses:
- FF000000 FF008000 (RO) FF010000 FF018000 FF020000
- FF028000 FF030000 FF038000 FF040000 FF080000
- FF0C0000 FF100000 FF140000 FF180000 FF1C0000
- FF200000 FF240000 FF280000 FF2C0000 FF300000
- FF340000 FF380000 FF3C0000 FF400000 FF440000
- FF480000 FF4C0000 FF500000 FF540000 FF580000
- FF5C0000 FF600000 FF640000 FF680000 FF6C0000
- FF700000 FF740000 FF780000 FF7C0000
-
-Bank # 2: Intel: 28F160F3B (16Mbit)
- Size: 8 MB in 39 Sectors
- Sector Start Addresses:
- FF800000 FF808000 FF810000 FF818000 FF820000
- FF828000 FF830000 FF838000 FF840000 FF880000
- FF8C0000 FF900000 FF940000 FF980000 FF9C0000
- FFA00000 FFA40000 FFA80000 FFAC0000 FFB00000
- FFB40000 FFB80000 FFBC0000 FFC00000 FFC40000
- FFC80000 FFCC0000 FFD00000 FFD40000 FFD80000
- FFDC0000 FFE00000 FFE40000 FFE80000 FFEC0000
- FFF00000 (RO) FFF40000 FFF80000 FFFC0000
-=>
-
-x.x.x Flash Programming
-
-
-ppcboot 0.9.2 (May 13 2001 - 17:56:46)
-
-Initializing...
- CPU: MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache
- Board: CU824 Revision 1 Local Bus at 99 MHz
- DRAM: 64 MB
- FLASH: 16 MB
- In: serial
- Out: serial
- Err: serial
-
-Hit any key to stop autoboot: 0
-=>
-=>
-=>
-=>
-=>cp 0 ff000000 20
-Copy to Flash... done
-=>md 0
-00000000: 0ec08ce0 03f9800c 00000001 040c0000 ................
-00000010: 00000001 03fd1aa0 03fd1ae4 03fd1a00 ................
-00000020: 03fd1a58 03fceb04 03fd34cc 03fd34d0 ...X......4...4.
-00000030: 03fcd5bc 03fcdabc 00000000 00000000 ................
-00000040: 00000000 00000000 00000000 00000000 ................
-00000050: 00000000 00000000 00000000 00000000 ................
-00000060: 00000000 00000000 00000000 00000000 ................
-00000070: 00000000 00000000 00000000 00000000 ................
-00000080: 00000000 00000000 00000000 00000000 ................
-00000090: 00000000 00000000 00000000 00000000 ................
-000000a0: 00000000 00000000 00000000 00000000 ................
-000000b0: 00000000 00000000 00000000 00000000 ................
-000000c0: 00000000 00000000 00000000 00000000 ................
-000000d0: 00000000 00000000 00000000 00000000 ................
-000000e0: 00000000 00000000 00000000 00000000 ................
-000000f0: 00000000 00000000 00000000 00000000 ................
-=>md ff000000
-ff000000: 0ec08ce0 03f9800c 00000001 040c0000 ................
-ff000010: 00000001 03fd1aa0 03fd1ae4 03fd1a00 ................
-ff000020: 03fd1a58 03fceb04 03fd34cc 03fd34d0 ...X......4...4.
-ff000030: 03fcd5bc 03fcdabc 00000000 00000000 ................
-ff000040: 00000000 00000000 00000000 00000000 ................
-ff000050: 00000000 00000000 00000000 00000000 ................
-ff000060: 00000000 00000000 00000000 00000000 ................
-ff000070: 00000000 00000000 00000000 00000000 ................
-ff000080: ffffffff ffffffff ffffffff ffffffff ................
-ff000090: ffffffff ffffffff ffffffff ffffffff ................
-ff0000a0: ffffffff ffffffff ffffffff ffffffff ................
-ff0000b0: ffffffff ffffffff ffffffff ffffffff ................
-ff0000c0: ffffffff ffffffff ffffffff ffffffff ................
-ff0000d0: ffffffff ffffffff ffffffff ffffffff ................
-ff0000e0: ffffffff ffffffff ffffffff ffffffff ................
-ff0000f0: ffffffff ffffffff ffffffff ffffffff ................
-=>
-
-x.x.x Storage of environment variables in flash
-
-
-ppcboot 0.9.2 (May 13 2001 - 17:56:46)
-
-Initializing...
- CPU: MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache
- Board: CU824 Revision 1 Local Bus at 99 MHz
- DRAM: 64 MB
- FLASH: 16 MB
- In: serial
- Out: serial
- Err: serial
-
-Hit any key to stop autoboot: 0
-=>
-=>printenv
-bootargs=
-bootcmd=bootm FE020000
-bootdelay=5
-baudrate=9600
-ipaddr=192.168.4.2
-serverip=192.168.4.1
-ethaddr=00:40:42:01:00:a0
-stdin=serial
-stdout=serial
-stderr=serial
-
-Environment size: 167/32764 bytes
-=>setenv myvar 1234
-=>save_env
-Un-Protected 1 sectors
-Erasing Flash...
- done
-Erased 1 sectors
-Saving Environment to Flash...
-Protected 1 sectors
-=>reset
-
-
-ppcboot 0.9.2 (May 13 2001 - 17:56:46)
-
-Initializing...
- CPU: MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache
- Board: CU824 Revision 1 Local Bus at 99 MHz
- DRAM: 64 MB
- FLASH: 16 MB
- In: serial
- Out: serial
- Err: serial
-
-Hit any key to stop autoboot: 0
-=>
-=>printenv
-bootargs=
-bootcmd=bootm FE020000
-bootdelay=5
-baudrate=9600
-ipaddr=192.168.4.2
-serverip=192.168.4.1
-ethaddr=00:40:42:01:00:a0
-myvar=1234
-stdin=serial
-stdout=serial
-stderr=serial
-
-Environment size: 178/32764 bytes
-=>
-
-x.x Image Download and run over serial port
-
-
-ppcboot 0.9.2 (May 13 2001 - 17:56:46)
-
-Initializing...
- CPU: MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache
- Board: CU824 Revision 1 Local Bus at 99 MHz
- DRAM: 64 MB
- FLASH: 16 MB
- In: serial
- Out: serial
- Err: serial
-
-Hit any key to stop autoboot: 0
-=>
-=>
-=>mw 40000 0 10000
-=>md 40000
-00040000: 00000000 00000000 00000000 00000000 ................
-00040010: 00000000 00000000 00000000 00000000 ................
-00040020: 00000000 00000000 00000000 00000000 ................
-00040030: 00000000 00000000 00000000 00000000 ................
-00040040: 00000000 00000000 00000000 00000000 ................
-00040050: 00000000 00000000 00000000 00000000 ................
-00040060: 00000000 00000000 00000000 00000000 ................
-00040070: 00000000 00000000 00000000 00000000 ................
-00040080: 00000000 00000000 00000000 00000000 ................
-00040090: 00000000 00000000 00000000 00000000 ................
-000400a0: 00000000 00000000 00000000 00000000 ................
-000400b0: 00000000 00000000 00000000 00000000 ................
-000400c0: 00000000 00000000 00000000 00000000 ................
-000400d0: 00000000 00000000 00000000 00000000 ................
-000400e0: 00000000 00000000 00000000 00000000 ................
-000400f0: 00000000 00000000 00000000 00000000 ................
-=>loads
-## Ready for S-Record download ...
-
-(Back at xpert.denx.de)
-[vlad at xpert vlad]$ cat hello_world.srec >/dev/ttyS0
-[vlad at xpert vlad]$ kermit -l /dev/ttyS0 -b 9600 -c
-Connecting to /dev/ttyS0, speed 9600.
-The escape character is Ctrl-\ (ASCII 28, FS)
-Type the escape character followed by C to get back,
-or followed by ? to see other options.
-md 40000
-00040000: 00018148 9421ffe0 7c0802a6 bf61000c ...H.!..|....a..
-00040010: 90010024 48000005 7fc802a6 801effe8 ...$H...........
-00040020: 7fc0f214 7c7f1b78 813f0038 7c9c2378 ....|..x.?.8|.#x
-00040030: 807e8000 7cbd2b78 80090010 3b600000 .~..|.+x....;`..
-00040040: 7c0803a6 4e800021 813f0038 7f84e378 |...N..!.?.8...x
-00040050: 807e8004 80090010 7c0803a6 4e800021 .~......|...N..!
-00040060: 7c1be000 4181003c 80bd0000 813f0038 |...A..<.....?.8
-00040070: 3bbd0004 2c050000 40820008 80be8008 ;...,... at .......
-00040080: 80090010 7f64db78 807e800c 3b7b0001 .....d.x.~..;{..
-00040090: 7c0803a6 4e800021 7c1be000 4081ffcc |...N..!|...@...
-000400a0: 813f0038 807e8010 80090010 7c0803a6 .?.8.~......|...
-000400b0: 4e800021 813f0038 80090004 7c0803a6 N..!.?.8....|...
-000400c0: 4e800021 2c030000 4182ffec 813f0038 N..!,...A....?.8
-000400d0: 80090000 7c0803a6 4e800021 813f0038 ....|...N..!.?.8
-000400e0: 807e8014 80090010 7c0803a6 4e800021 .~......|...N..!
-000400f0: 38600000 80010024 7c0803a6 bb61000c 8`.....$|....a..
-=>go 40004
-## Starting application at 0x00040004 ...
-Hello World
-argc = 1
-argv[0] = "40004"
-argv[1] = "<NULL>"
-Hit any key to exit ...
-
-## Application terminated, rc = 0x0
-=>
-
-x.x Image download and run over ethernet interface
-
-
-ppcboot 0.9.2 (May 13 2001 - 17:56:46)
-
-Initializing...
- CPU: MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache
- Board: CU824 Revision 1 Local Bus at 99 MHz
- DRAM: 64 MB
- FLASH: 16 MB
- In: serial
- Out: serial
- Err: serial
-
-Hit any key to stop autoboot: 0
-=>
-=>
-=>mw 40000 0 10000
-=>md 40000
-00040000: 00000000 00000000 00000000 00000000 ................
-00040010: 00000000 00000000 00000000 00000000 ................
-00040020: 00000000 00000000 00000000 00000000 ................
-00040030: 00000000 00000000 00000000 00000000 ................
-00040040: 00000000 00000000 00000000 00000000 ................
-00040050: 00000000 00000000 00000000 00000000 ................
-00040060: 00000000 00000000 00000000 00000000 ................
-00040070: 00000000 00000000 00000000 00000000 ................
-00040080: 00000000 00000000 00000000 00000000 ................
-00040090: 00000000 00000000 00000000 00000000 ................
-000400a0: 00000000 00000000 00000000 00000000 ................
-000400b0: 00000000 00000000 00000000 00000000 ................
-000400c0: 00000000 00000000 00000000 00000000 ................
-000400d0: 00000000 00000000 00000000 00000000 ................
-000400e0: 00000000 00000000 00000000 00000000 ................
-000400f0: 00000000 00000000 00000000 00000000 ................
-=>tftpboot 40000 hello_world.bin
-ARP broadcast 1
-TFTP from server 192.168.4.1; our IP address is 192.168.4.2
-Filename 'hello_world.bin'.
-Load address: 0x40000
-Loading: #############
-done
-Bytes transferred = 65912 (10178 hex)
-=>md 40000
-00040000: 00018148 9421ffe0 7c0802a6 bf61000c ...H.!..|....a..
-00040010: 90010024 48000005 7fc802a6 801effe8 ...$H...........
-00040020: 7fc0f214 7c7f1b78 813f0038 7c9c2378 ....|..x.?.8|.#x
-00040030: 807e8000 7cbd2b78 80090010 3b600000 .~..|.+x....;`..
-00040040: 7c0803a6 4e800021 813f0038 7f84e378 |...N..!.?.8...x
-00040050: 807e8004 80090010 7c0803a6 4e800021 .~......|...N..!
-00040060: 7c1be000 4181003c 80bd0000 813f0038 |...A..<.....?.8
-00040070: 3bbd0004 2c050000 40820008 80be8008 ;...,... at .......
-00040080: 80090010 7f64db78 807e800c 3b7b0001 .....d.x.~..;{..
-00040090: 7c0803a6 4e800021 7c1be000 4081ffcc |...N..!|...@...
-000400a0: 813f0038 807e8010 80090010 7c0803a6 .?.8.~......|...
-000400b0: 4e800021 813f0038 80090004 7c0803a6 N..!.?.8....|...
-000400c0: 4e800021 2c030000 4182ffec 813f0038 N..!,...A....?.8
-000400d0: 80090000 7c0803a6 4e800021 813f0038 ....|...N..!.?.8
-000400e0: 807e8014 80090010 7c0803a6 4e800021 .~......|...N..!
-000400f0: 38600000 80010024 7c0803a6 bb61000c 8`.....$|....a..
-=>go 40004
-## Starting application at 0x00040004 ...
-Hello World
-argc = 1
-argv[0] = "40004"
-argv[1] = "<NULL>"
-Hit any key to exit ...
-
-## Application terminated, rc = 0x0
-=>
diff --git a/board/cu824/cu824.c b/board/cu824/cu824.c
deleted file mode 100644
index 6b23c53..0000000
--- a/board/cu824/cu824.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * (C) Copyright 2001
- * Rob Taylor, Flying Pig Systems. robt at flyingpig.com.
- *
- * (C) Copyright 2001-2006
- * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
-
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc824x.h>
-#include <asm/processor.h>
-#include <pci.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define BOARD_REV_REG 0xFE80002B
-
-int checkboard (void)
-{
- char revision = *(volatile char *)(BOARD_REV_REG);
- char buf[32];
-
- puts ("Board: CU824 ");
- printf("Revision %d ", revision);
- printf("Local Bus at %s MHz\n", strmhz(buf, gd->bus_clk));
-
- return 0;
-}
-
-phys_size_t initdram(int board_type)
-{
- long size;
- long new_bank0_end;
- long mear1;
- long emear1;
-
- size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
-
- new_bank0_end = size - 1;
- mear1 = mpc824x_mpc107_getreg(MEAR1);
- emear1 = mpc824x_mpc107_getreg(EMEAR1);
- mear1 = (mear1 & 0xFFFFFF00) |
- ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
- emear1 = (emear1 & 0xFFFFFF00) |
- ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
- mpc824x_mpc107_setreg(MEAR1, mear1);
- mpc824x_mpc107_setreg(EMEAR1, emear1);
-
- return (size);
-}
-
-/*
- * Initialize PCI Devices, report devices found.
- */
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_sandpoint_config_table[] = {
- { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
- pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
- PCI_ENET0_MEMADDR,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
-
- { }
-};
-#endif
-
-struct pci_controller hose = {
-#ifndef CONFIG_PCI_PNP
- config_table: pci_sandpoint_config_table,
-#endif
-};
-
-void pci_init_board(void)
-{
- pci_mpc824x_init(&hose);
-}
-
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
diff --git a/board/cu824/flash.c b/board/cu824/flash.c
deleted file mode 100644
index 3a6d954..0000000
--- a/board/cu824/flash.c
+++ /dev/null
@@ -1,470 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc824x.h>
-#include <asm/processor.h>
-
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-# ifndef CONFIG_ENV_ADDR
-# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-# endif
-# ifndef CONFIG_ENV_SIZE
-# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-# endif
-# ifndef CONFIG_ENV_SECT_SIZE
-# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
-# endif
-#endif
-
-#define FLASH_BANK_SIZE 0x800000
-#define MAIN_SECT_SIZE 0x40000
-#define PARAM_SECT_SIZE 0x8000
-
-#define BOARD_CTRL_REG 0xFE800013
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-static int write_data (flash_info_t *info, ulong dest, ulong *data);
-static void write_via_fpu(vu_long *addr, ulong *data);
-static __inline__ unsigned long get_msr(void);
-static __inline__ void set_msr(unsigned long msr);
-
-/*---------------------------------------------------------------------*/
-#undef DEBUG_FLASH
-
-/*---------------------------------------------------------------------*/
-#ifdef DEBUG_FLASH
-#define DEBUGF(fmt,args...) printf(fmt ,##args)
-#else
-#define DEBUGF(fmt,args...)
-#endif
-/*---------------------------------------------------------------------*/
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init(void)
-{
- int i, j;
- ulong size = 0;
- volatile unsigned char *bcr = (volatile unsigned char *)(BOARD_CTRL_REG);
-
- DEBUGF("Write protect was: 0x%02X\n", *bcr);
- *bcr &= 0x1; /* FWPT must be 0 */
- *bcr |= 0x6; /* FWP0 = FWP1 = 1 */
- DEBUGF("Write protect is: 0x%02X\n", *bcr);
-
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
- vu_long *addr = (vu_long *)(CONFIG_SYS_FLASH_BASE + i * FLASH_BANK_SIZE);
-
- addr[0] = 0x00900090;
-
- DEBUGF ("Flash bank # %d:\n"
- "\tManuf. ID @ 0x%08lX: 0x%08lX\n"
- "\tDevice ID @ 0x%08lX: 0x%08lX\n",
- i,
- (ulong)(&addr[0]), addr[0],
- (ulong)(&addr[2]), addr[2]);
-
- if ((addr[0] == addr[1]) && (addr[0] == INTEL_MANUFACT) &&
- (addr[2] == addr[3]) && (addr[2] == INTEL_ID_28F160F3B))
- {
- flash_info[i].flash_id = (FLASH_MAN_INTEL & FLASH_VENDMASK) |
- (INTEL_ID_28F160F3B & FLASH_TYPEMASK);
- } else {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- addr[0] = 0xFFFFFFFF;
- goto Done;
- }
-
- DEBUGF ("flash_id = 0x%08lX\n", flash_info[i].flash_id);
-
- addr[0] = 0xFFFFFFFF;
-
- flash_info[i].size = FLASH_BANK_SIZE;
- flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
- for (j = 0; j < flash_info[i].sector_count; j++) {
- if (j <= 7) {
- flash_info[i].start[j] = CONFIG_SYS_FLASH_BASE +
- i * FLASH_BANK_SIZE +
- j * PARAM_SECT_SIZE;
- } else {
- flash_info[i].start[j] = CONFIG_SYS_FLASH_BASE +
- i * FLASH_BANK_SIZE +
- (j - 7)*MAIN_SECT_SIZE;
- }
- }
- size += flash_info[i].size;
- }
-
- /* Protect monitor and environment sectors
- */
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE + FLASH_BANK_SIZE
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
- &flash_info[1]);
-#else
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
- &flash_info[0]);
-#endif
-#endif
-
-#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
-#if CONFIG_ENV_ADDR >= CONFIG_SYS_FLASH_BASE + FLASH_BANK_SIZE
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
- &flash_info[1]);
-#else
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
- &flash_info[0]);
-#endif
-#endif
-
-Done:
- return size;
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
- int i;
-
- switch ((i = info->flash_id & FLASH_VENDMASK)) {
- case (FLASH_MAN_INTEL & FLASH_VENDMASK):
- printf ("Intel: ");
- break;
- default:
- printf ("Unknown Vendor 0x%04x ", i);
- break;
- }
-
- switch ((i = info->flash_id & FLASH_TYPEMASK)) {
- case (INTEL_ID_28F160F3B & FLASH_TYPEMASK):
- printf ("28F160F3B (16Mbit)\n");
- break;
- default:
- printf ("Unknown Chip Type 0x%04x\n", i);
- goto Done;
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; i++) {
- if ((i % 5) == 0) {
- printf ("\n ");
- }
- printf (" %08lX%s", info->start[i],
- info->protect[i] ? " (RO)" : " ");
- }
- printf ("\n");
-
-Done:
- return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- int flag, prot, sect;
- ulong start, now, last;
-
- DEBUGF ("Erase flash bank %d sect %d ... %d\n",
- info - &flash_info[0], s_first, s_last);
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id & FLASH_VENDMASK) !=
- (FLASH_MAN_INTEL & FLASH_VENDMASK)) {
- printf ("Can erase only Intel flash types - aborted\n");
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- start = get_timer (0);
- last = start;
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- vu_long *addr = (vu_long *)(info->start[sect]);
-
- DEBUGF ("Erase sect %d @ 0x%08lX\n",
- sect, (ulong)addr);
-
- /* Disable interrupts which might cause a timeout
- * here.
- */
- flag = disable_interrupts();
-
- addr[0] = 0x00500050; /* clear status register */
- addr[0] = 0x00200020; /* erase setup */
- addr[0] = 0x00D000D0; /* erase confirm */
-
- addr[1] = 0x00500050; /* clear status register */
- addr[1] = 0x00200020; /* erase setup */
- addr[1] = 0x00D000D0; /* erase confirm */
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- while (((addr[0] & 0x00800080) != 0x00800080) ||
- ((addr[1] & 0x00800080) != 0x00800080) ) {
- if ((now=get_timer(start)) >
- CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- addr[0] = 0x00B000B0; /* suspend erase */
- addr[0] = 0x00FF00FF; /* to read mode */
- return 1;
- }
-
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
- addr[0] = 0x00FF00FF;
- }
- }
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 4 - Flash not identified
- */
-
-#define FLASH_WIDTH 8 /* flash bus width in bytes */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong wp, cp, msr;
- int l, rc, i;
- ulong data[2];
- ulong *datah = &data[0];
- ulong *datal = &data[1];
-
- DEBUGF ("Flash write_buff: @ 0x%08lx, src 0x%08lx len %ld\n",
- addr, (ulong)src, cnt);
-
- if (info->flash_id == FLASH_UNKNOWN) {
- return 4;
- }
-
- msr = get_msr();
- set_msr(msr | MSR_FP);
-
- wp = (addr & ~(FLASH_WIDTH-1)); /* get lower aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- *datah = *datal = 0;
-
- for (i = 0, cp = wp; i < l; i++, cp++) {
- if (i >= 4) {
- *datah = (*datah << 8) |
- ((*datal & 0xFF000000) >> 24);
- }
-
- *datal = (*datal << 8) | (*(uchar *)cp);
- }
- for (; i < FLASH_WIDTH && cnt > 0; ++i) {
- char tmp;
-
- tmp = *src;
-
- src++;
-
- if (i >= 4) {
- *datah = (*datah << 8) |
- ((*datal & 0xFF000000) >> 24);
- }
-
- *datal = (*datal << 8) | tmp;
-
- --cnt; ++cp;
- }
-
- for (; cnt == 0 && i < FLASH_WIDTH; ++i, ++cp) {
- if (i >= 4) {
- *datah = (*datah << 8) |
- ((*datal & 0xFF000000) >> 24);
- }
-
- *datal = (*datah << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_data(info, wp, data)) != 0) {
- set_msr(msr);
- return (rc);
- }
-
- wp += FLASH_WIDTH;
- }
-
- /*
- * handle FLASH_WIDTH aligned part
- */
- while (cnt >= FLASH_WIDTH) {
- *datah = *(ulong *)src;
- *datal = *(ulong *)(src + 4);
- if ((rc = write_data(info, wp, data)) != 0) {
- set_msr(msr);
- return (rc);
- }
- wp += FLASH_WIDTH;
- cnt -= FLASH_WIDTH;
- src += FLASH_WIDTH;
- }
-
- if (cnt == 0) {
- set_msr(msr);
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- *datah = *datal = 0;
- for (i = 0, cp = wp; i < FLASH_WIDTH && cnt > 0; ++i, ++cp) {
- char tmp;
-
- tmp = *src;
-
- src++;
-
- if (i >= 4) {
- *datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24);
- }
-
- *datal = (*datal << 8) | tmp;
-
- --cnt;
- }
-
- for (; i < FLASH_WIDTH; ++i, ++cp) {
- if (i >= 4) {
- *datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24);
- }
-
- *datal = (*datal << 8) | (*(uchar *)cp);
- }
-
- rc = write_data(info, wp, data);
- set_msr(msr);
-
- return (rc);
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_data (flash_info_t *info, ulong dest, ulong *data)
-{
- vu_long *addr = (vu_long *)dest;
- ulong start;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if (((addr[0] & data[0]) != data[0]) ||
- ((addr[1] & data[1]) != data[1]) ) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0] = 0x00400040; /* write setup */
- write_via_fpu(addr, data);
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- start = get_timer (0);
-
- while (((addr[0] & 0x00800080) != 0x00800080) ||
- ((addr[1] & 0x00800080) != 0x00800080) ) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- addr[0] = 0x00FF00FF; /* restore read mode */
- return (1);
- }
- }
-
- addr[0] = 0x00FF00FF; /* restore read mode */
-
- return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
-static void write_via_fpu(vu_long *addr, ulong *data)
-{
- __asm__ __volatile__ ("lfd 1, 0(%0)" : : "r" (data));
- __asm__ __volatile__ ("stfd 1, 0(%0)" : : "r" (addr));
-}
-/*-----------------------------------------------------------------------
- */
-static __inline__ unsigned long get_msr(void)
-{
- unsigned long msr;
-
- __asm__ __volatile__ ("mfmsr %0" : "=r" (msr) :);
- return msr;
-}
-
-static __inline__ void set_msr(unsigned long msr)
-{
- __asm__ __volatile__ ("mtmsr %0" : : "r" (msr));
-}
diff --git a/board/eXalion/Kconfig b/board/eXalion/Kconfig
deleted file mode 100644
index a22f58a..0000000
--- a/board/eXalion/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_EXALION
-
-config SYS_BOARD
- default "eXalion"
-
-config SYS_CONFIG_NAME
- default "eXalion"
-
-endif
diff --git a/board/eXalion/MAINTAINERS b/board/eXalion/MAINTAINERS
deleted file mode 100644
index 0ea74ca..0000000
--- a/board/eXalion/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-EXALION BOARD
-M: Torsten Demke <torsten.demke@fci.com>
-S: Maintained
-F: board/eXalion/
-F: include/configs/eXalion.h
-F: configs/eXalion_defconfig
diff --git a/board/eXalion/Makefile b/board/eXalion/Makefile
deleted file mode 100644
index 9192e28..0000000
--- a/board/eXalion/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = eXalion.o
diff --git a/board/eXalion/eXalion.c b/board/eXalion/eXalion.c
deleted file mode 100644
index 304ff21..0000000
--- a/board/eXalion/eXalion.c
+++ /dev/null
@@ -1,283 +0,0 @@
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * (C) Copyright 2002
- * Torsten Demke, FORCE Computers GmbH. torsten.demke at fci.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc824x.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <pci.h>
-#include <ide.h>
-#include <netdev.h>
-#include <timestamp.h>
-#include "piix_pci.h"
-#include "eXalion.h"
-
-int checkboard (void)
-{
- ulong busfreq = get_bus_freq (0);
- char buf[32];
-
- printf ("Board: eXalion MPC824x - CHRP (MAP B)\n");
- printf ("Built: %s at %s\n", U_BOOT_DATE, U_BOOT_TIME);
- printf ("Local Bus: %s MHz\n", strmhz (buf, busfreq));
-
- return 0;
-}
-
-int checkflash (void)
-{
- printf ("checkflash\n");
- flash_init ();
- return (0);
-}
-
-phys_size_t initdram (int board_type)
-{
- int i, cnt;
- volatile uchar *base = CONFIG_SYS_SDRAM_BASE;
- volatile ulong *addr;
- ulong save[32];
- ulong val, ret = 0;
-
- for (i = 0, cnt = (CONFIG_SYS_MAX_RAM_SIZE / sizeof (long)) >> 1; cnt > 0;
- cnt >>= 1) {
- addr = (volatile ulong *) base + cnt;
- save[i++] = *addr;
- *addr = ~cnt;
- }
-
- addr = (volatile ulong *) base;
- save[i] = *addr;
- *addr = 0;
-
- if (*addr != 0) {
- *addr = save[i];
- goto Done;
- }
-
- for (cnt = 1; cnt <= CONFIG_SYS_MAX_RAM_SIZE / sizeof (long); cnt <<= 1) {
- addr = (volatile ulong *) base + cnt;
- val = *addr;
- *addr = save[--i];
- if (val != ~cnt) {
- ulong new_bank0_end = cnt * sizeof (long) - 1;
- ulong mear1 = mpc824x_mpc107_getreg (MEAR1);
- ulong emear1 = mpc824x_mpc107_getreg (EMEAR1);
-
- mear1 = (mear1 & 0xFFFFFF00) |
- ((new_bank0_end & MICR_ADDR_MASK) >>
- MICR_ADDR_SHIFT);
- emear1 = (emear1 & 0xFFFFFF00) |
- ((new_bank0_end & MICR_ADDR_MASK) >>
- MICR_EADDR_SHIFT);
- mpc824x_mpc107_setreg (MEAR1, mear1);
- mpc824x_mpc107_setreg (EMEAR1, emear1);
-
- ret = cnt * sizeof (long);
- goto Done;
- }
- }
-
- ret = CONFIG_SYS_MAX_RAM_SIZE;
- Done:
- return ret;
-}
-
-int misc_init_r (void)
-{
- pci_dev_t bdf;
- u32 val32;
- u8 val8;
-
- puts ("ISA: ");
- bdf = pci_find_device (PIIX4_VENDOR_ID, PIIX4_ISA_DEV_ID, 0);
- if (bdf == -1) {
- puts ("Unable to find PIIX4 ISA bridge !\n");
- hang ();
- }
-
- /* set device for normal ISA instead EIO */
- pci_read_config_dword (bdf, PCI_CFG_PIIX4_GENCFG, &val32);
- val32 |= 0x00000001;
- pci_write_config_dword (bdf, PCI_CFG_PIIX4_GENCFG, val32);
- printf ("PIIX4 ISA bridge (%d,%d,%d)\n", PCI_BUS (bdf),
- PCI_DEV (bdf), PCI_FUNC (bdf));
-
- puts ("ISA: ");
- bdf = pci_find_device (PIIX4_VENDOR_ID, PIIX4_IDE_DEV_ID, 0);
- if (bdf == -1) {
- puts ("Unable to find PIIX4 IDE controller !\n");
- hang ();
- }
-
- /* Init BMIBA register */
- /* pci_read_config_dword(bdf, PCI_CFG_PIIX4_BMIBA, &val32); */
- /* val32 |= 0x1000; */
- /* pci_write_config_dword(bdf, PCI_CFG_PIIX4_BMIBA, val32); */
-
- /* Enable BUS master and IO access */
- val32 = PCI_COMMAND_MASTER | PCI_COMMAND_IO;
- pci_write_config_dword (bdf, PCI_COMMAND, val32);
-
- /* Set latency */
- pci_read_config_byte (bdf, PCI_LATENCY_TIMER, &val8);
- val8 = 0x40;
- pci_write_config_byte (bdf, PCI_LATENCY_TIMER, val8);
-
- /* Enable Primary ATA/IDE */
- pci_read_config_dword (bdf, PCI_CFG_PIIX4_IDETIM, &val32);
- /* val32 = 0xa307a307; */
- val32 = 0x00008000;
- pci_write_config_dword (bdf, PCI_CFG_PIIX4_IDETIM, val32);
-
-
- printf ("PIIX4 IDE controller (%d,%d,%d)\n", PCI_BUS (bdf),
- PCI_DEV (bdf), PCI_FUNC (bdf));
-
- /* Try to get FAT working... */
- /* fat_register_read(ide_read); */
-
-
- return (0);
-}
-
-/*
- * Show/Init PCI devices on the specified bus number.
- */
-
-void pci_eXalion_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
-{
- unsigned char line;
-
- switch (PCI_DEV (dev)) {
- case 16:
- line = PCI_INT_A;
- break;
- case 17:
- line = PCI_INT_B;
- break;
- case 18:
- line = PCI_INT_C;
- break;
- case 19:
- line = PCI_INT_D;
- break;
-#if defined (CONFIG_MPC8245)
- case 20:
- line = PCI_INT_A;
- break;
- case 21:
- line = PCI_INT_B;
- break;
- case 22:
- line = PCI_INT_NA;
- break;
-#endif
- default:
- line = PCI_INT_A;
- break;
- }
- pci_hose_write_config_byte (hose, dev, PCI_INTERRUPT_LINE, line);
-}
-
-
-/*
- * Initialize PCI Devices, report devices found.
- */
-#ifndef CONFIG_PCI_PNP
-#if defined (CONFIG_MPC8240)
-static struct pci_config_table pci_eXalion_config_table[] = {
- {
- /* Intel 82559ER ethernet controller */
- PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 18, 0x00,
- pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
- PCI_ENET0_MEMADDR,
- PCI_COMMAND_MEMORY |
- PCI_COMMAND_MASTER}},
- {
- /* Intel 82371AB PIIX4 PCI to ISA bridge */
- PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 20, 0x00,
- pci_cfgfunc_config_device, {0,
- 0,
- PCI_COMMAND_IO | PCI_COMMAND_MASTER}},
- {
- /* Intel 82371AB PIIX4 IDE controller */
- PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 20, 0x01,
- pci_cfgfunc_config_device, {0,
- 0,
- PCI_COMMAND_IO | PCI_COMMAND_MASTER}},
- {}
-};
-#elif defined (CONFIG_MPC8245)
-static struct pci_config_table pci_eXalion_config_table[] = {
- {
- /* Intel 82559ER ethernet controller */
- PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 17, 0x00,
- pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
- PCI_ENET0_MEMADDR,
- PCI_COMMAND_MEMORY |
- PCI_COMMAND_MASTER}},
- {
- /* Intel 82559ER ethernet controller */
- PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 18, 0x00,
- pci_cfgfunc_config_device, {PCI_ENET1_IOADDR,
- PCI_ENET1_MEMADDR,
- PCI_COMMAND_MEMORY |
- PCI_COMMAND_MASTER}},
- {
- /* Broadcom BCM5690 Gigabit switch */
- PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 20, 0x00,
- pci_cfgfunc_config_device, {PCI_ENET2_IOADDR,
- PCI_ENET2_MEMADDR,
- PCI_COMMAND_MEMORY |
- PCI_COMMAND_MASTER}},
- {
- /* Broadcom BCM5690 Gigabit switch */
- PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 21, 0x00,
- pci_cfgfunc_config_device, {PCI_ENET3_IOADDR,
- PCI_ENET3_MEMADDR,
- PCI_COMMAND_MEMORY |
- PCI_COMMAND_MASTER}},
- {
- /* Intel 82371AB PIIX4 PCI to ISA bridge */
- PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 22, 0x00,
- pci_cfgfunc_config_device, {0,
- 0,
- PCI_COMMAND_IO | PCI_COMMAND_MASTER}},
- {
- /* Intel 82371AB PIIX4 IDE controller */
- PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 22, 0x01,
- pci_cfgfunc_config_device, {0,
- 0,
- PCI_COMMAND_IO | PCI_COMMAND_MASTER}},
- {}
-};
-#else
-#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
-#endif
-
-#endif /* #ifndef CONFIG_PCI_PNP */
-
-struct pci_controller hose = {
-#ifndef CONFIG_PCI_PNP
- config_table:pci_eXalion_config_table,
- fixup_irq:pci_eXalion_fixup_irq,
-#endif
-};
-
-void pci_init_board (void)
-{
- pci_mpc824x_init (&hose);
-}
-
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
diff --git a/board/eXalion/eXalion.h b/board/eXalion/eXalion.h
deleted file mode 100644
index 7804f4f..0000000
--- a/board/eXalion/eXalion.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * (C) Copyright 2002
- * Torsten Demke, FORCE Computers GmbH. torsten.demke at fci.com
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * (C) Copyright 2002
- * James Dougherty (jfd at broadcom.com)
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __EXALION_H
-#define __EXALION_H
-
-/* IRQ settings */
-#define PCI_INT_NA (0xff) /* PCI Intr. not used */
-#define PCI_INT_A (0x09) /* PCI Intr. A Interrupt Request Line Nr. */
-#define PCI_INT_B (0x0a) /* PCI Intr. B Interrupt Request Line Nr. */
-#define PCI_INT_C (0x0b) /* PCI Intr. C Interrupt Request Line Nr. */
-#define PCI_INT_D (0x0c) /* PCI Intr. D Interrupt Request Line Nr. */
-#if defined (CPU_MPC8245)
-#define LN_1_INT PCI_INT_B /* ethernet interrupt level */
-#define LN_2_INT PCI_INT_C /* ethernet interrupt level */
-#define BCM_1_INT PCI_INT_A /* BCM5690 interrupt level */
-#define BCM_2_INT PCI_INT_B /* BCM5690 interrupt level */
-#elif defined (CPU_MPC8240)
-#define BCM_INT PCI_INT_B /* BCM5600 interrupt level */
-#define LN_INT PCI_INT_C /* ethernet interrupt level */
-#endif
-
-#ifndef __ASSEMBLY__
-#endif /* !__ASSEMBLY__ */
-
-#endif /* __EXALION_H */
diff --git a/board/eXalion/piix_pci.h b/board/eXalion/piix_pci.h
deleted file mode 100644
index 21c636f..0000000
--- a/board/eXalion/piix_pci.h
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * (C) Copyright 2002
- * Torsten Demke, FORCE Computers GmbH. torsten.demke at fci.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef _PIIX4_PCI_H
-#define _PIIX4_PCI_H
-
-#include <common.h>
-#include <mpc824x.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <pci.h>
-
-#define PIIX4_VENDOR_ID 0x8086
-#define PIIX4_ISA_DEV_ID 0x7110
-#define PIIX4_IDE_DEV_ID 0x7111
-
-/* Function 0 ISA Bridge */
-#define PCI_CFG_PIIX4_IORT 0x4C /* 8 bit ISA Recovery Timer Reg (default 0x4D) */
-#define PCI_CFG_PIIX4_XBCS 0x4E /* 16 bit XBus Chip select reg (default 0x0003) */
-#define PCI_CFG_PIIX4_PIRQC 0x60 /* PCI IRQ Route Register 4 x 8bit (default )*/
-#define PCI_CFG_PIIX4_SERIRQ 0x64
-#define PCI_CFG_PIIX4_TOM 0x69
-#define PCI_CFG_PIIX4_MSTAT 0x6A
-#define PCI_CFG_PIIX4_MBDMA 0x76
-#define PCI_CFG_PIIX4_APICBS 0x80
-#define PCI_CFG_PIIX4_DLC 0x82
-#define PCI_CFG_PIIX4_PDMACFG 0x90
-#define PCI_CFG_PIIX4_DDMABS 0x92
-#define PCI_CFG_PIIX4_GENCFG 0xB0
-#define PCI_CFG_PIIX4_RTCCFG 0xCB
-
-/* IO Addresses */
-#define PIIX4_ISA_DMA1_CH0BA 0x00
-#define PIIX4_ISA_DMA1_CH0CA 0x01
-#define PIIX4_ISA_DMA1_CH1BA 0x02
-#define PIIX4_ISA_DMA1_CH1CA 0x03
-#define PIIX4_ISA_DMA1_CH2BA 0x04
-#define PIIX4_ISA_DMA1_CH2CA 0x05
-#define PIIX4_ISA_DMA1_CH3BA 0x06
-#define PIIX4_ISA_DMA1_CH3CA 0x07
-#define PIIX4_ISA_DMA1_CMDST 0x08
-#define PIIX4_ISA_DMA1_REQ 0x09
-#define PIIX4_ISA_DMA1_WSBM 0x0A
-#define PIIX4_ISA_DMA1_CH_MOD 0x0B
-#define PIIX4_ISA_DMA1_CLR_PT 0x0C
-#define PIIX4_ISA_DMA1_M_CLR 0x0D
-#define PIIX4_ISA_DMA1_CLR_M 0x0E
-#define PIIX4_ISA_DMA1_RWAMB 0x0F
-
-#define PIIX4_ISA_DMA2_CH0BA 0xC0
-#define PIIX4_ISA_DMA2_CH0CA 0xC1
-#define PIIX4_ISA_DMA2_CH1BA 0xC2
-#define PIIX4_ISA_DMA2_CH1CA 0xC3
-#define PIIX4_ISA_DMA2_CH2BA 0xC4
-#define PIIX4_ISA_DMA2_CH2CA 0xC5
-#define PIIX4_ISA_DMA2_CH3BA 0xC6
-#define PIIX4_ISA_DMA2_CH3CA 0xC7
-#define PIIX4_ISA_DMA2_CMDST 0xD0
-#define PIIX4_ISA_DMA2_REQ 0xD2
-#define PIIX4_ISA_DMA2_WSBM 0xD4
-#define PIIX4_ISA_DMA2_CH_MOD 0xD6
-#define PIIX4_ISA_DMA2_CLR_PT 0xD8
-#define PIIX4_ISA_DMA2_M_CLR 0xDA
-#define PIIX4_ISA_DMA2_CLR_M 0xDC
-#define PIIX4_ISA_DMA2_RWAMB 0xDE
-
-#define PIIX4_ISA_INT1_ICW1 0x20
-#define PIIX4_ISA_INT1_OCW2 0x20
-#define PIIX4_ISA_INT1_OCW3 0x20
-#define PIIX4_ISA_INT1_ICW2 0x21
-#define PIIX4_ISA_INT1_ICW3 0x21
-#define PIIX4_ISA_INT1_ICW4 0x21
-#define PIIX4_ISA_INT1_OCW1 0x21
-
-#define PIIX4_ISA_INT1_ELCR 0x4D0
-
-#define PIIX4_ISA_INT2_ICW1 0xA0
-#define PIIX4_ISA_INT2_OCW2 0xA0
-#define PIIX4_ISA_INT2_OCW3 0xA0
-#define PIIX4_ISA_INT2_ICW2 0xA1
-#define PIIX4_ISA_INT2_ICW3 0xA1
-#define PIIX4_ISA_INT2_ICW4 0xA1
-#define PIIX4_ISA_INT2_OCW1 0xA1
-#define PIIX4_ISA_INT2_IMR 0xA1 /* read only */
-
-#define PIIX4_ISA_INT2_ELCR 0x4D1
-
-#define PIIX4_ISA_TMR0_CNT_ST 0x40
-#define PIIX4_ISA_TMR1_CNT_ST 0x41
-#define PIIX4_ISA_TMR2_CNT_ST 0x42
-#define PIIX4_ISA_TMR_TCW 0x43
-
-#define PIIX4_ISA_RST_XBUS 0x60
-
-#define PIIX4_ISA_NMI_CNT_ST 0x61
-#define PIIX4_ISA_NMI_ENABLE 0x70
-
-#define PIIX4_ISA_RTC_INDEX 0x70
-#define PIIX4_ISA_RTC_DATA 0x71
-#define PIIX4_ISA_RTCEXT_IND 0x70
-#define PIIX4_ISA_RTCEXT_DATA 0x71
-
-#define PIIX4_ISA_DMA1_CH2LPG 0x81
-#define PIIX4_ISA_DMA1_CH3LPG 0x82
-#define PIIX4_ISA_DMA1_CH1LPG 0x83
-#define PIIX4_ISA_DMA1_CH0LPG 0x87
-#define PIIX4_ISA_DMA2_CH2LPG 0x89
-#define PIIX4_ISA_DMA2_CH3LPG 0x8A
-#define PIIX4_ISA_DMA2_CH1LPG 0x8B
-#define PIIX4_ISA_DMA2_LPGRFR 0x8F
-
-#define PIIX4_ISA_PORT_92 0x92
-
-#define PIIX4_ISA_APM_CONTRL 0xB2
-#define PIIX4_ISA_APM_STATUS 0xB3
-
-#define PIIX4_ISA_COCPU_ERROR 0xF0
-
-/* Function 1 IDE Controller */
-#define PCI_CFG_PIIX4_BMIBA 0x20
-#define PCI_CFG_PIIX4_IDETIM 0x40
-#define PCI_CFG_PIIX4_SIDETIM 0x44
-#define PCI_CFG_PIIX4_UDMACTL 0x48
-#define PCI_CFG_PIIX4_UDMATIM 0x4A
-
-/* Function 2 USB Controller */
-#define PCI_CFG_PIIX4_SBRNUM 0x60
-#define PCI_CFG_PIIX4_LEGSUP 0xC0
-
-/* Function 3 Power Management */
-#define PCI_CFG_PIIX4_PMAB 0x40
-#define PCI_CFG_PIIX4_CNTA 0x44
-#define PCI_CFG_PIIX4_CNTB 0x48
-#define PCI_CFG_PIIX4_GPICTL 0x4C
-#define PCI_CFG_PIIX4_DEVRESD 0x50
-#define PCI_CFG_PIIX4_DEVACTA 0x54
-#define PCI_CFG_PIIX4_DEVACTB 0x58
-#define PCI_CFG_PIIX4_DEVRESA 0x5C
-#define PCI_CFG_PIIX4_DEVRESB 0x60
-#define PCI_CFG_PIIX4_DEVRESC 0x64
-#define PCI_CFG_PIIX4_DEVRESE 0x68
-#define PCI_CFG_PIIX4_DEVRESF 0x6C
-#define PCI_CFG_PIIX4_DEVRESG 0x70
-#define PCI_CFG_PIIX4_DEVRESH 0x74
-#define PCI_CFG_PIIX4_DEVRESI 0x78
-#define PCI_CFG_PIIX4_PMMISC 0x80
-#define PCI_CFG_PIIX4_SMBBA 0x90
-
-
-#endif /* _PIIX4_PCI_H */
diff --git a/board/musenki/Kconfig b/board/musenki/Kconfig
deleted file mode 100644
index 26b680f..0000000
--- a/board/musenki/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_MUSENKI
-
-config SYS_BOARD
- default "musenki"
-
-config SYS_CONFIG_NAME
- default "MUSENKI"
-
-endif
diff --git a/board/musenki/MAINTAINERS b/board/musenki/MAINTAINERS
deleted file mode 100644
index 4196c80..0000000
--- a/board/musenki/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MUSENKI BOARD
-#M: Jim Thompson <jim@musenki.com>
-S: Orphan (since 2014-04)
-F: board/musenki/
-F: include/configs/MUSENKI.h
-F: configs/MUSENKI_defconfig
diff --git a/board/musenki/Makefile b/board/musenki/Makefile
deleted file mode 100644
index d2b79ff..0000000
--- a/board/musenki/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = musenki.o flash.o
diff --git a/board/musenki/README b/board/musenki/README
deleted file mode 100644
index 084ab54..0000000
--- a/board/musenki/README
+++ /dev/null
@@ -1,298 +0,0 @@
-U-Boot for a Musenki M-3/M-1 board
----------------------------
-
-Musenki M-1 and M-3 have two banks of flash of 4MB or 8MB each.
-
-In board's notation, bank 0 is the one at the address of 0xFF800000
-and bank 1 is the one at the address of 0xFF000000.
-
-On power-up the processor jumps to the address of 0xFFF00100, the last
-megabyte of the bank 0 of flash.
-
-Thus, U-Boot is configured to reside in flash starting at the address of
-0xFFF00000. The environment space is located in flash separately from
-U-Boot, at the address of 0xFF800000.
-
-There is a Davicom 9102A on-board, but I don't have it working yet.
-
-U-Boot test results
---------------------
-
-x.x Operation on all available serial consoles
-
-x.x.x CONFIG_CONS_INDEX 1
-
-
-U-Boot 1.1.1 (Nov 20 2001 - 15:55:32)
-
-CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache
-Board: MUSENKI Local Bus at 100 MHz
-DRAM: 32 MB
-FLASH: 4 MB
-In: serial
-Out: serial
-Err: serial
-Hit any key to stop autoboot: 0
-=> help
-base - print or set address offset
-bdinfo - print Board Info structure
-bootm - boot application image from memory
-bootp - boot image via network using BootP/TFTP protocol
-bootd - boot default, i.e., run 'bootcmd'
-cmp - memory compare
-coninfo - print console devices and informations
-cp - memory copy
-crc32 - checksum calculation
-dcache - enable or disable data cache
-echo - echo args to console
-erase - erase FLASH memory
-flinfo - print FLASH memory information
-go - start application at address 'addr'
-help - print online help
-icache - enable or disable instruction cache
-iminfo - print header information for application image
-loadb - load binary file over serial line (kermit mode)
-loads - load S-Record file over serial line
-loop - infinite loop on address range
-md - memory display
-mm - memory modify (auto-incrementing)
-mtest - simple RAM test
-mw - memory write (fill)
-nm - memory modify (constant address)
-printenv- print environment variables
-protect - enable or disable FLASH write protection
-rarpboot- boot image via network using RARP/TFTP protocol
-reset - Perform RESET of the CPU
-run - run commands in an environment variable
-saveenv - save environment variables to persistent storage
-setenv - set environment variables
-source - run script from memory
-tftpboot- boot image via network using TFTP protocol
- and env variables ipaddr and serverip
-version - print monitor version
-? - alias for 'help'
-
-
-x.x.x CONFIG_CONS_INDEX 2
-
-**** NOT TESTED ****
-
-x.x Flash Driver Operation
-
-
-Boot 1.1.1 (Nov 20 2001 - 15:55:32)
-
-CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache
-Board: MUSENKI Local Bus at 100 MHz
-DRAM: 32 MB
-FLASH: 4 MB
-*** Warning - bad CRC, using default environment
-
-In: serial
-Out: serial
-Err: serial
-Hit any key to stop autoboot: 0
-=>
-=> md ff800000
-ff800000: 46989bf8 626f6f74 636d643d 626f6f74 F...bootcmd=boot
-ff800010: 6d204646 38323030 30300062 6f6f7464 m FF820000.bootd
-ff800020: 656c6179 3d350062 61756472 6174653d elay=5.baudrate=
-ff800030: 39363030 00636c6f 636b735f 696e5f6d 9600.clocks_in_m
-ff800040: 687a3d31 00737464 696e3d73 65726961 hz=1.stdin=seria
-ff800050: 6c007374 646f7574 3d736572 69616c00 l.stdout=serial.
-ff800060: 73746465 72723d73 65726961 6c006970 stderr=serial.ip
-ff800070: 61646472 3d313932 2e313638 2e302e34 addr=192.168.0.4
-ff800080: 32007365 72766572 69703d31 39322e31 2.serverip=192.1
-ff800090: 36382e30 2e380000 00000000 00000000 68.0.8..........
-ff8000a0: 00000000 00000000 00000000 00000000 ................
-ff8000b0: 00000000 00000000 00000000 00000000 ................
-ff8000c0: 00000000 00000000 00000000 00000000 ................
-ff8000d0: 00000000 00000000 00000000 00000000 ................
-ff8000e0: 00000000 00000000 00000000 00000000 ................
-ff8000f0: 00000000 00000000 00000000 00000000 ................
-=> protect off ff800000 ff81ffff
-Un-Protected 1 sectors
-=> erase ff800000 ff81ffff
-Erase Flash from 0xff800000 to 0xff81ffff
- done
-Erased 1 sectors
-=> md ff800000
-ff800000: ffffffff ffffffff ffffffff ffffffff ................
-ff800010: ffffffff ffffffff ffffffff ffffffff ................
-ff800020: ffffffff ffffffff ffffffff ffffffff ................
-ff800030: ffffffff ffffffff ffffffff ffffffff ................
-ff800040: ffffffff ffffffff ffffffff ffffffff ................
-ff800050: ffffffff ffffffff ffffffff ffffffff ................
-ff800060: ffffffff ffffffff ffffffff ffffffff ................
-ff800070: ffffffff ffffffff ffffffff ffffffff ................
-ff800080: ffffffff ffffffff ffffffff ffffffff ................
-ff800090: ffffffff ffffffff ffffffff ffffffff ................
-ff8000a0: ffffffff ffffffff ffffffff ffffffff ................
-ff8000b0: ffffffff ffffffff ffffffff ffffffff ................
-ff8000c0: ffffffff ffffffff ffffffff ffffffff ................
-ff8000d0: ffffffff ffffffff ffffffff ffffffff ................
-ff8000e0: ffffffff ffffffff ffffffff ffffffff ................
-ff8000f0: ffffffff ffffffff ffffffff ffffffff ................
-
-x.x.x Information
-
-
-U-Boot 1.1.1 (Nov 20 2001 - 15:55:32)
-
-CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache
-Board: MUSENKI Local Bus at 100 MHz
-DRAM: 32 MB
-FLASH: 4 MB
-*** Warning - bad CRC, using default environment
-
-In: serial
-Out: serial
-Err: serial
-Hit any key to stop autoboot: 0
-=> flinfo
-
-Bank # 1: Intel 28F320J3A (32Mbit = 128K x 32)
- Size: 4 MB in 32 Sectors
- Sector Start Addresses:
- FF800000 (RO) FF820000 FF840000 FF860000 FF880000
- FF8A0000 FF8C0000 FF8E0000 FF900000 FF920000
- FF940000 FF960000 FF980000 FF9A0000 FF9C0000
- FF9E0000 FFA00000 FFA20000 FFA40000 FFA60000
- FFA80000 FFAA0000 FFAC0000 FFAE0000 FFB00000
- FFB20000 FFB40000 FFB60000 FFB80000 FFBA0000
- FFBC0000 FFBE0000
-
-Bank # 2: missing or unknown FLASH type
-=>
-
-
-x.x.x Flash Programming
-
-
-U-Boot 1.1.1 (Nov 20 2001 - 15:55:32)
-
-CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache
-Board: MUSENKI Local Bus at 100 MHz
-DRAM: 32 MB
-FLASH: 4 MB
-
-In: serial
-Out: serial
-Err: serial
-Hit any key to stop autoboot: 0
-=>
-=>
-=>
-=> protect off ff800000 ff81ffff
-Un-Protected 1 sectors
-=> cp 0 ff800000 20
-Copy to Flash... done
-=> md ff800000
-ff800000: 37ce33ec 33cc334c 33c031cc 33cc35cc 7.3.3.3L3.1.3.5.
-ff800010: 33ec13ce 30ccb3ec b3c833c4 31c836cc 3...0.....3.1.6.
-ff800020: 33cc3b9d 31ec33ee 13ecf3cc 338833ec 3.;.1.3.....3.3.
-ff800030: 234c33ec 32cc22cc 33883bdc 534433cc #L3.2.".3.;.SD3.
-ff800040: 33cc30c8 31cc32ec 338c33cc 330c33dc 3.0.1.2.3.3.3.3.
-ff800050: 33cc13dc 334c534c b1c433d8 128c13cc 3...3LSL..3.....
-ff800060: 37ec36cd 33dc33cc bbc9f7e8 bbcc77cc 7.6.3.3.......w.
-ff800070: 314c0adc 139c30ed 33cc334c 33c833ec 1L....0.3.3L3.3.
-ff800080: ffffffff ffffffff ffffffff ffffffff ................
-ff800090: ffffffff ffffffff ffffffff ffffffff ................
-ff8000a0: ffffffff ffffffff ffffffff ffffffff ................
-ff8000b0: ffffffff ffffffff ffffffff ffffffff ................
-ff8000c0: ffffffff ffffffff ffffffff ffffffff ................
-ff8000d0: ffffffff ffffffff ffffffff ffffffff ................
-ff8000e0: ffffffff ffffffff ffffffff ffffffff ................
-ff8000f0: ffffffff ffffffff ffffffff ffffffff ................
-
-
-x.x.x Storage of environment variables in flash
-
-
-U-Boot 1.1.1 (Nov 20 2001 - 15:55:32)
-
-CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache
-Board: MUSENKI Local Bus at 100 MHz
-DRAM: 32 MB
-FLASH: 4 MB
-In: serial
-Out: serial
-Err: serial
-Hit any key to stop autoboot: 0
-=> printenv
-bootcmd=bootm FF820000
-bootdelay=5
-baudrate=9600
-clocks_in_mhz=1
-stdin=serial
-stdout=serial
-stderr=serial
-
-Environment size: 106/16380 bytes
-=> setenv myvar 1234
-=> saveenv
-Un-Protected 1 sectors
-Erasing Flash...
- done
-Erased 1 sectors
-Saving Environment to Flash...
-Protected 1 sectors
-=> reset
-
-
-U-Boot 1.1.1 (Nov 20 2001 - 15:55:32)
-
-CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache
-Board: MUSENKI Local Bus at 100 MHz
-DRAM: 32 MB
-FLASH: 4 MB
-In: serial
-Out: serial
-Err: serial
-Hit any key to stop autoboot: 0
-=> printenv
-bootcmd=bootm FF820000
-bootdelay=5
-baudrate=9600
-clocks_in_mhz=1
-myvar=1234
-stdin=serial
-stdout=serial
-stderr=serial
-
-Environment size: 117/16380 bytes
-
-x.x Image Download and run over serial port
-
-
-U-Boot 1.1.1 (Nov 20 2001 - 15:55:32)
-
-CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache
-Board: MUSENKI Local Bus at 100 MHz
-DRAM: 32 MB
-FLASH: 4 MB
-In: serial
-Out: serial
-Err: serial
-Hit any key to stop autoboot: 0
-=> loads
-## Ready for S-Record download ...
-
-## First Load Addr = 0x00040000
-## Last Load Addr = 0x00050177
-## Total Size = 0x00010178 = 65912 Bytes
-## Start Addr = 0x00040004
-=> go 40004
-## Starting application at 0x00040004 ...
-Hello World
-argc = 1
-argv[0] = "40004"
-argv[1] = "<NULL>"
-Hit any key to exit ...
-
-## Application terminated, rc = 0x0
-
-
-x.x Image download and run over ethernet interface
-
-untested (not working yet, actually)
diff --git a/board/musenki/flash.c b/board/musenki/flash.c
deleted file mode 100644
index 080ec7f..0000000
--- a/board/musenki/flash.c
+++ /dev/null
@@ -1,496 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc824x.h>
-
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-# ifndef CONFIG_ENV_ADDR
-# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-# endif
-# ifndef CONFIG_ENV_SIZE
-# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-# endif
-# ifndef CONFIG_ENV_SECT_SIZE
-# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
-# endif
-#endif
-
-/*---------------------------------------------------------------------*/
-#undef DEBUG_FLASH
-
-#ifdef DEBUG_FLASH
-#define DEBUGF(fmt,args...) printf(fmt ,##args)
-#else
-#define DEBUGF(fmt,args...)
-#endif
-/*---------------------------------------------------------------------*/
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_char *addr, flash_info_t *info);
-static int write_data (flash_info_t *info, uchar *dest, uchar data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-
-/*
- * don't ask. its stupid, but more than one soul has had to live with this mistake
- * "swaptab[i]" is the value of "i" with the bits reversed.
- */
-
-#define MUSENKI_BROKEN_FLASH 1
-
-#ifdef MUSENKI_BROKEN_FLASH
-unsigned char swaptab[256] = {
- 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,
- 0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0,
- 0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8,
- 0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8,
- 0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4,
- 0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4,
- 0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec,
- 0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc,
- 0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2,
- 0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2,
- 0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea,
- 0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa,
- 0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6,
- 0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6,
- 0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee,
- 0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe,
- 0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1,
- 0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1,
- 0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9,
- 0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9,
- 0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5,
- 0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5,
- 0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed,
- 0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd,
- 0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3,
- 0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3,
- 0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb,
- 0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb,
- 0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7,
- 0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7,
- 0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef,
- 0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff,
-};
-
-#define BS(b) (swaptab[b])
-
-#else
-
-#define BS(b) (b)
-
-#endif
-
-#define BYTEME(x) ((x) & 0xFF)
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- unsigned long size_b0, size_b1;
- int i;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- DEBUGF("\n## Get flash bank 1 size @ 0x%08x\n",CONFIG_SYS_FLASH_BASE0_PRELIM);
-
- size_b0 = flash_get_size((vu_char *)CONFIG_SYS_FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0: "
- "ID 0x%lx, Size = 0x%08lx = %ld MB\n",
- flash_info[0].flash_id,
- size_b0, size_b0<<20);
- }
-
- DEBUGF("## Get flash bank 2 size @ 0x%08x\n",CONFIG_SYS_FLASH_BASE1_PRELIM);
- size_b1 = flash_get_size((vu_char *)CONFIG_SYS_FLASH_BASE1_PRELIM, &flash_info[1]);
-
- DEBUGF("## Prelim. Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
-
- flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
- flash_info[0].size = size_b0;
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- DEBUGF("protect monitor %x @ %x\n", CONFIG_SYS_MONITOR_BASE, monitor_flash_len);
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[0]);
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- DEBUGF("protect environtment %x @ %x\n", CONFIG_ENV_ADDR, CONFIG_ENV_SECT_SIZE);
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
- &flash_info[0]);
-#endif
-
- if (size_b1) {
- flash_info[1].size = size_b1;
- flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]);
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[1]);
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
- &flash_info[1]);
-#endif
- } else {
- flash_info[1].flash_id = FLASH_UNKNOWN;
- flash_info[1].sector_count = -1;
- flash_info[1].size = 0;
- }
-
- DEBUGF("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
-
- return (size_b0 + size_b1);
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_INTEL:
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base;
- base += 0x00020000; /* 128k per bank */
- }
- return;
-
- default:
- printf ("Don't know sector ofsets for flash type 0x%lx\n", info->flash_id);
- return;
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_FUJ: printf ("Fujitsu "); break;
- case FLASH_MAN_SST: printf ("SST "); break;
- case FLASH_MAN_STM: printf ("STM "); break;
- case FLASH_MAN_INTEL: printf ("Intel "); break;
- case FLASH_MAN_MT: printf ("MT "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F320J3A: printf ("28F320J3A (32Mbit = 128K x 32)\n");
- break;
- case FLASH_28F640J3A: printf ("28F640J3A (64Mbit = 128K x 64)\n");
- break;
- case FLASH_28F128J3A: printf ("28F128J3A (128Mbit = 128K x 128)\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- if (info->size >= (1 << 20)) {
- i = 20;
- } else {
- i = 10;
- }
- printf (" Size: %ld %cB in %d Sectors\n",
- info->size >> i,
- (i == 20) ? 'M' : 'k',
- info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
- return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size (vu_char *addr, flash_info_t *info)
-{
- vu_char manuf, device;
-
- addr[0] = BS(0x90);
- manuf = BS(addr[0]);
- DEBUGF("Manuf. ID @ 0x%08lx: 0x%08x\n", (vu_char *)addr, manuf);
-
- switch (manuf) {
- case BYTEME(AMD_MANUFACT):
- info->flash_id = FLASH_MAN_AMD;
- break;
- case BYTEME(FUJ_MANUFACT):
- info->flash_id = FLASH_MAN_FUJ;
- break;
- case BYTEME(SST_MANUFACT):
- info->flash_id = FLASH_MAN_SST;
- break;
- case BYTEME(STM_MANUFACT):
- info->flash_id = FLASH_MAN_STM;
- break;
- case BYTEME(INTEL_MANUFACT):
- info->flash_id = FLASH_MAN_INTEL;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- addr[0] = BS(0xFF); /* restore read mode, (yes, BS is a NOP) */
- return 0; /* no or unknown flash */
- }
-
- device = BS(addr[2]); /* device ID */
-
- DEBUGF("Device ID @ 0x%08x: 0x%08x\n", (&addr[1]), device);
-
- switch (device) {
- case BYTEME(INTEL_ID_28F320J3A):
- info->flash_id += FLASH_28F320J3A;
- info->sector_count = 32;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case BYTEME(INTEL_ID_28F640J3A):
- info->flash_id += FLASH_28F640J3A;
- info->sector_count = 64;
- info->size = 0x00800000;
- break; /* => 8 MB */
-
- case BYTEME(INTEL_ID_28F128J3A):
- info->flash_id += FLASH_28F128J3A;
- info->sector_count = 128;
- info->size = 0x01000000;
- break; /* => 16 MB */
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- addr[0] = BS(0xFF); /* restore read mode (yes, a NOP) */
- return 0; /* => no or unknown flash */
-
- }
-
- if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
- printf ("** ERROR: sector count %d > max (%d) **\n",
- info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
- info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- }
-
- addr[0] = BS(0xFF); /* restore read mode */
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- int flag, prot, sect;
- ulong start, now, last;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) {
- printf ("Can erase only Intel flash types - aborted\n");
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n", prot);
- } else {
- printf ("\n");
- }
-
- start = get_timer (0);
- last = start;
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- vu_char *addr = (vu_char *)(info->start[sect]);
- unsigned long status;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- *addr = BS(0x50); /* clear status register */
- *addr = BS(0x20); /* erase setup */
- *addr = BS(0xD0); /* erase confirm */
-
- /* re-enable interrupts if necessary */
- if (flag) {
- enable_interrupts();
- }
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- while (((status = BS(*addr)) & BYTEME(0x00800080)) != BYTEME(0x00800080)) {
- if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- *addr = BS(0xB0); /* suspend erase */
- *addr = BS(0xFF); /* reset to read mode */
- return 1;
- }
-
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
- *addr = BS(0xFF); /* reset to read mode */
- }
- }
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 4 - Flash not identified
- */
-
-#define FLASH_WIDTH 1 /* flash bus width in bytes */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- uchar *wp = (uchar *)addr;
- int rc;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- return 4;
- }
-
- while (cnt > 0) {
- if ((rc = write_data(info, wp, *src)) != 0) {
- return rc;
- }
- wp++;
- src++;
- cnt--;
- }
-
- return cnt;
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_data (flash_info_t *info, uchar *dest, uchar data)
-{
- vu_char *addr = (vu_char *)dest;
- ulong status;
- ulong start;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((BS(*addr) & data) != data) {
- return 2;
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- *addr = BS(0x40); /* write setup */
- *addr = data;
-
- /* re-enable interrupts if necessary */
- if (flag) {
- enable_interrupts();
- }
-
- start = get_timer (0);
-
- while (((status = BS(*addr)) & BYTEME(0x00800080)) != BYTEME(0x00800080)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- *addr = BS(0xFF); /* restore read mode */
- return 1;
- }
- }
-
- *addr = BS(0xFF); /* restore read mode */
-
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- */
diff --git a/board/musenki/musenki.c b/board/musenki/musenki.c
deleted file mode 100644
index aa92fc4..0000000
--- a/board/musenki/musenki.c
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * (C) Copyright 2001
- * Rob Taylor, Flying Pig Systems. robt at flyingpig.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc824x.h>
-#include <pci.h>
-#include <netdev.h>
-
-int checkboard (void)
-{
- ulong busfreq = get_bus_freq(0);
- char buf[32];
-
- printf("Board: MUSENKI Local Bus at %s MHz\n", strmhz(buf, busfreq));
- return 0;
-
-}
-
-#if 0 /* NOT USED */
-int checkflash (void)
-{
- /* TODO: XXX XXX XXX */
- printf ("## Test not implemented yet ##\n");
-
- return (0);
-}
-#endif
-
-phys_size_t initdram (int board_type)
-{
- long size;
- long new_bank0_end;
- long mear1;
- long emear1;
-
- size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
-
- new_bank0_end = size - 1;
- mear1 = mpc824x_mpc107_getreg(MEAR1);
- emear1 = mpc824x_mpc107_getreg(EMEAR1);
- mear1 = (mear1 & 0xFFFFFF00) |
- ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
- emear1 = (emear1 & 0xFFFFFF00) |
- ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
- mpc824x_mpc107_setreg(MEAR1, mear1);
- mpc824x_mpc107_setreg(EMEAR1, emear1);
-
- return (size);
-}
-
-/*
- * Initialize PCI Devices
- */
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_sandpoint_config_table[] = {
-#if 0
- { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
- 0x0, 0x0, 0x0, /* unknown eth0 divice */
- pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
- PCI_ENET0_MEMADDR,
- PCI_COMMAND_IO |
- PCI_COMMAND_MEMORY |
- PCI_COMMAND_MASTER }},
- { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
- 0x0, 0x0, 0x0, /* unknown eth1 device */
- pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
- PCI_ENET1_MEMADDR,
- PCI_COMMAND_IO |
- PCI_COMMAND_MEMORY |
- PCI_COMMAND_MASTER }},
-#endif
- { }
-};
-#endif
-
-struct pci_controller hose = {
-#ifndef CONFIG_PCI_PNP
- config_table: pci_sandpoint_config_table,
-#endif
-};
-
-void pci_init_board(void)
-{
- pci_mpc824x_init(&hose);
-}
-
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
diff --git a/board/mvblue/Kconfig b/board/mvblue/Kconfig
deleted file mode 100644
index cee206b..0000000
--- a/board/mvblue/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_MVBLUE
-
-config SYS_BOARD
- default "mvblue"
-
-config SYS_CONFIG_NAME
- default "MVBLUE"
-
-endif
diff --git a/board/mvblue/MAINTAINERS b/board/mvblue/MAINTAINERS
deleted file mode 100644
index 5955f1a..0000000
--- a/board/mvblue/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MVBLUE BOARD
-#M: -
-S: Maintained
-F: board/mvblue/
-F: include/configs/MVBLUE.h
-F: configs/MVBLUE_defconfig
diff --git a/board/mvblue/Makefile b/board/mvblue/Makefile
deleted file mode 100644
index 76c10f8..0000000
--- a/board/mvblue/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = mvblue.o flash.o
diff --git a/board/mvblue/flash.c b/board/mvblue/flash.c
deleted file mode 100644
index 5dd658f..0000000
--- a/board/mvblue/flash.c
+++ /dev/null
@@ -1,570 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- * (C) Copyright 2001-2003
- *
- * Changes for MATRIX Vision mvBLUE devices
- * MATRIX Vision GmbH / hg,as info at matrix-vision.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc824x.h>
-
-#if 0
- #define mvdebug(p) printf ##p
-#else
- #define mvdebug(p)
-#endif
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-#define FLASH_BUS_WIDTH 8
-
-#if (FLASH_BUS_WIDTH==32)
- #define FLASH_DATA_MASK 0xffffffff
- #define FLASH_SHIFT 1
- #define FDT vu_long
-#elif (FLASH_BUS_WIDTH==16)
- #define FLASH_DATA_MASK 0xff
- #define FLASH_SHIFT 0
- #define FDT vu_short
-#elif (FLASH_BUS_WIDTH==8)
- #define FLASH_DATA_MASK 0xff
- #define FLASH_SHIFT 0
- #define FDT vu_char
-#else
- #error FLASH_BUS_WIDTH undefined
-#endif
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *address, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-/*-----------------------------------------------------------------------
- */
-unsigned long flash_init (void)
-{
- unsigned long size_b0;
- int i;
-
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- size_b0 = flash_get_size((vu_long *)0xffc00000, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH : Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0<<20);
- }
-
- flash_get_offsets (0xffc00000, &flash_info[0]);
- flash_info[0].size = size_b0;
-
- /* monitor protection OFF by default */
- flash_protect ( FLAG_PROTECT_CLEAR, 0xffc00000, 0x2000, flash_info );
-
- return size_b0;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
- int i;
-
- /* set up sector start address table */
- if (info->flash_id & FLASH_BTYPE)
- { /* bottom boot sector types - these are the useful ones! */
- /* set sector offsets for bottom boot block type */
- if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B)
- { /* AMDLV320B has 8 x 8k bottom boot sectors */
- for (i = 0; i < 8; i++) /* +8k */
- info->start[i] = base + (i * (0x00002000 << FLASH_SHIFT));
- for (; i < info->sector_count; i++) /* +64k */
- info->start[i] = base + (i * (0x00010000 << FLASH_SHIFT)) - (0x00070000 << FLASH_SHIFT);
- }
- else
- { /* other types have 4 bottom boot sectors (16,8,8,32) */
- i = 0;
- info->start[i++] = base + 0x00000000; /* - */
- info->start[i++] = base + (0x00004000 << FLASH_SHIFT); /* +16k */
- info->start[i++] = base + (0x00006000 << FLASH_SHIFT); /* +8k */
- info->start[i++] = base + (0x00008000 << FLASH_SHIFT); /* +8k */
- info->start[i++] = base + (0x00010000 << FLASH_SHIFT); /* +32k */
- for (; i < info->sector_count; i++) /* +64k */
- info->start[i] = base + (i * (0x00010000 << FLASH_SHIFT)) - (0x00030000 << FLASH_SHIFT);
- }
- }
- else
- { /* top boot sector types - not so useful */
- /* set sector offsets for top boot block type */
- if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T)
- { /* AMDLV320T has 8 x 8k top boot sectors */
- for (i = 0; i < info->sector_count - 8; i++) /* +64k */
- info->start[i] = base + (i * (0x00010000 << FLASH_SHIFT));
- for (; i < info->sector_count; i++) /* +8k */
- info->start[i] = base + (i * (0x00002000 << FLASH_SHIFT));
- }
- else
- { /* other types have 4 top boot sectors (32,8,8,16) */
- for (i = 0; i < info->sector_count - 4; i++) /* +64k */
- info->start[i] = base + (i * (0x00010000 << FLASH_SHIFT));
-
- info->start[i++] = base + info->size - (0x00010000 << FLASH_SHIFT); /* -32k */
- info->start[i++] = base + info->size - (0x00008000 << FLASH_SHIFT); /* -8k */
- info->start[i++] = base + info->size - (0x00006000 << FLASH_SHIFT); /* -8k */
- info->start[i] = base + info->size - (0x00004000 << FLASH_SHIFT); /* -16k */
- }
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
- case FLASH_MAN_STM: printf ("ST "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
- break;
- case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
- break;
- case FLASH_STMW320DB: printf ("M29W320B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_STMW320DT: printf ("M29W320T (32 Mbit, top boot sector)\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : " ");
- }
- printf ("\n");
-}
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-#define AMD_ID_LV160T_MVS (AMD_ID_LV160T & FLASH_DATA_MASK)
-#define AMD_ID_LV160B_MVS (AMD_ID_LV160B & FLASH_DATA_MASK)
-#define AMD_ID_LV320T_MVS (AMD_ID_LV320T & FLASH_DATA_MASK)
-#define AMD_ID_LV320B_MVS (AMD_ID_LV320B & FLASH_DATA_MASK)
-#define STM_ID_W320DT_MVS (STM_ID_29W320DT & FLASH_DATA_MASK)
-#define STM_ID_W320DB_MVS (STM_ID_29W320DB & FLASH_DATA_MASK)
-#define AMD_MANUFACT_MVS (AMD_MANUFACT & FLASH_DATA_MASK)
-#define FUJ_MANUFACT_MVS (FUJ_MANUFACT & FLASH_DATA_MASK)
-#define STM_MANUFACT_MVS (STM_MANUFACT & FLASH_DATA_MASK)
-
-#if (FLASH_BUS_WIDTH >= 16)
- #define AUTOSELECT_ADDR1 0x0555
- #define AUTOSELECT_ADDR2 0x02AA
- #define AUTOSELECT_ADDR3 AUTOSELECT_ADDR1
-#else
- #define AUTOSELECT_ADDR1 0x0AAA
- #define AUTOSELECT_ADDR2 0x0555
- #define AUTOSELECT_ADDR3 AUTOSELECT_ADDR1
-#endif
-
-#define AUTOSELECT_DATA1 (0x00AA00AA & FLASH_DATA_MASK)
-#define AUTOSELECT_DATA2 (0x00550055 & FLASH_DATA_MASK)
-#define AUTOSELECT_DATA3 (0x00900090 & FLASH_DATA_MASK)
-
-#define RESET_BANK_DATA (0x00F000F0 & FLASH_DATA_MASK)
-
-
-static ulong flash_get_size (vu_long *address, flash_info_t *info)
-{
- short i;
- FDT value;
- FDT *addr = (FDT *)address;
-
- ulong base = (ulong)address;
- addr[AUTOSELECT_ADDR1] = AUTOSELECT_DATA1;
- addr[AUTOSELECT_ADDR2] = AUTOSELECT_DATA2;
- addr[AUTOSELECT_ADDR3] = AUTOSELECT_DATA3;
- __asm__ __volatile__("sync");
-
- udelay(180);
-
- value = addr[0]; /* manufacturer ID */
- switch (value) {
- case AMD_MANUFACT_MVS:
- info->flash_id = FLASH_MAN_AMD;
- break;
- case FUJ_MANUFACT_MVS:
- info->flash_id = FLASH_MAN_FUJ;
- break;
- case STM_MANUFACT_MVS:
- info->flash_id = FLASH_MAN_STM;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-#if (FLASH_BUS_WIDTH >= 16)
- value = addr[1]; /* device ID */
-#else
- value = addr[2]; /* device ID */
-#endif
-
- switch (value) {
- case AMD_ID_LV160T_MVS:
- info->flash_id += FLASH_AM160T;
- info->sector_count = 37;
- info->size = (0x00200000 << FLASH_SHIFT);
- break; /* => 2 or 4 MB */
-
- case AMD_ID_LV160B_MVS:
- info->flash_id += FLASH_AM160B;
- info->sector_count = 37;
- info->size = (0x00200000 << FLASH_SHIFT);
- break; /* => 2 or 4 MB */
-
- case AMD_ID_LV320T_MVS:
- info->flash_id += FLASH_AM320T;
- info->sector_count = 71;
- info->size = (0x00400000 << FLASH_SHIFT);
- break; /* => 4 or 8 MB */
-
- case AMD_ID_LV320B_MVS:
- info->flash_id += FLASH_AM320B;
- info->sector_count = 71;
- info->size = (0x00400000 << FLASH_SHIFT);
- break; /* => 4 or 8MB */
-
- case STM_ID_W320DT_MVS:
- info->flash_id += FLASH_STMW320DT;
- info->sector_count = 67;
- info->size = (0x00400000 << FLASH_SHIFT);
- break; /* => 4 or 8 MB */
-
- case STM_ID_W320DB_MVS:
- info->flash_id += FLASH_STMW320DB;
- info->sector_count = 67;
- info->size = (0x00400000 << FLASH_SHIFT);
- break; /* => 4 or 8MB */
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
-
- }
-
- /* set up sector start address table */
- flash_get_offsets (base, info);
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- addr = (FDT *)(info->start[i]);
- info->protect[i] = addr[2] & 1;
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- addr = (FDT *)info->start[0];
- *addr = RESET_BANK_DATA; /* reset bank */
- }
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-#if (FLASH_BUS_WIDTH >= 16)
- #define ERASE_ADDR1 0x0555
- #define ERASE_ADDR2 0x02AA
-#else
- #define ERASE_ADDR1 0x0AAA
- #define ERASE_ADDR2 0x0555
-#endif
-
-#define ERASE_ADDR3 ERASE_ADDR1
-#define ERASE_ADDR4 ERASE_ADDR1
-#define ERASE_ADDR5 ERASE_ADDR2
-
-#define ERASE_DATA1 (0x00AA00AA & FLASH_DATA_MASK)
-#define ERASE_DATA2 (0x00550055 & FLASH_DATA_MASK)
-#define ERASE_DATA3 (0x00800080 & FLASH_DATA_MASK)
-#define ERASE_DATA4 ERASE_DATA1
-#define ERASE_DATA5 ERASE_DATA2
-
-#define ERASE_SECTOR_DATA (0x00300030 & FLASH_DATA_MASK)
-#define ERASE_CHIP_DATA (0x00100010 & FLASH_DATA_MASK)
-#define ERASE_CONFIRM_DATA (0x00800080 & FLASH_DATA_MASK)
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- FDT *addr = (FDT *)(info->start[0]);
-
- int prot, sect, l_sect, flag;
- ulong start, now, last;
-
- __asm__ __volatile__ ("sync");
- addr[0] = 0xf0;
- udelay(1000);
-
- printf("\nflash_erase: first = %d @ 0x%08lx\n", s_first, info->start[s_first] );
- printf(" last = %d @ 0x%08lx\n", s_last , info->start[s_last ] );
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id == FLASH_UNKNOWN) || (info->flash_id > FLASH_AMD_COMP)) {
- printf ("Can't erase unknown flash type %08lx - aborted\n", info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[ERASE_ADDR1] = ERASE_DATA1;
- addr[ERASE_ADDR2] = ERASE_DATA2;
- addr[ERASE_ADDR3] = ERASE_DATA3;
- addr[ERASE_ADDR4] = ERASE_DATA4;
- addr[ERASE_ADDR5] = ERASE_DATA5;
-
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) {
- addr = (FDT *)(info->start[sect]);
- addr[0] = ERASE_SECTOR_DATA;
- l_sect = sect;
- }
- }
-
- if (flag)
- enable_interrupts();
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer (0);
- last = start;
- addr = (FDT *)(info->start[l_sect]);
-
- while ((addr[0] & ERASE_CONFIRM_DATA) != ERASE_CONFIRM_DATA) {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
-DONE:
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
-#define BUFF_INC 4
- ulong cp, wp, data;
- int i, l, rc;
-
- mvdebug (("+write_buff %p ==> 0x%08lx, count = 0x%08lx\n", src, addr, cnt));
-
- wp = (addr & ~3); /* get lower word aligned address */
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- mvdebug ((" handle unaligned start bytes (cnt = 0x%08lx)\n", cnt));
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<BUFF_INC && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<BUFF_INC; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += BUFF_INC;
- }
-
- /*
- * handle (half)word aligned part
- */
- mvdebug ((" handle word aligned part (cnt = 0x%08lx)\n", cnt));
- while (cnt >= BUFF_INC) {
- data = 0;
- for (i=0; i<BUFF_INC; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += BUFF_INC;
- cnt -= BUFF_INC;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- mvdebug ((" handle unaligned tail bytes (cnt = 0x%08lx)\n", cnt));
- data = 0;
- for (i=0, cp=wp; i<BUFF_INC && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<BUFF_INC; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_word(info, wp, data));
-}
-
-#if (FLASH_BUS_WIDTH >= 16)
- #define WRITE_ADDR1 0x0555
- #define WRITE_ADDR2 0x02AA
-#else
- #define WRITE_ADDR1 0x0AAA
- #define WRITE_ADDR2 0x0555
- #define WRITE_ADDR3 WRITE_ADDR1
-#endif
-
-#define WRITE_DATA1 (0x00AA00AA & FLASH_DATA_MASK)
-#define WRITE_DATA2 (0x00550055 & FLASH_DATA_MASK)
-#define WRITE_DATA3 (0x00A000A0 & FLASH_DATA_MASK)
-
-#define WRITE_CONFIRM_DATA ERASE_CONFIRM_DATA
-
-/*-----------------------------------------------------------------------
- * Write a byte to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_char (flash_info_t *info, ulong dest, uchar data)
-{
- vu_char *addr = (vu_char *)(info->start[0]);
- ulong start;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((vu_char *)dest) & data) != data) {
- printf(" *** ERROR: Flash not erased !\n");
- return (2);
- }
- flag = disable_interrupts();
-
- addr[WRITE_ADDR1] = WRITE_DATA1;
- addr[WRITE_ADDR2] = WRITE_DATA2;
- addr[WRITE_ADDR3] = WRITE_DATA3;
- *((vu_char *)dest) = data;
-
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
- addr = (vu_char *)dest;
- while (( (*addr) & WRITE_CONFIRM_DATA) != (data & WRITE_CONFIRM_DATA)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- printf(" *** ERROR: Flash write timeout !");
- return (1);
- }
- }
- mvdebug (("-write_byte\n"));
- return (0);
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
- int i,
- result = 0;
-
- mvdebug (("+write_word : 0x%08lx @ 0x%08lx\n", data, dest));
- for ( i=0; (i < 4) && (result == 0); i++, dest+=1 )
- result = write_char (info, dest, (data >> (8*(3-i))) & 0xff );
- mvdebug (("-write_word\n"));
- return result;
-}
-/*---------------------------------------------------------------- */
diff --git a/board/mvblue/mvblue.c b/board/mvblue/mvblue.c
deleted file mode 100644
index 63503e8..0000000
--- a/board/mvblue/mvblue.c
+++ /dev/null
@@ -1,253 +0,0 @@
-/*
- * GNU General Public License for more details.
- *
- * MATRIX Vision GmbH / June 2002-Nov 2003
- * Andre Schwarz
- */
-
-#include <common.h>
-#include <mpc824x.h>
-#include <asm/io.h>
-#include <ns16550.h>
-#include <netdev.h>
-
-#ifdef CONFIG_PCI
-#include <pci.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-u32 get_BoardType (void);
-
-#define PCI_CONFIG(b,d,f,r) cpu_to_le32(0x80000000 | ((b&0xff)<<16) \
- | ((d&0x1f)<<11) \
- | ((f&0x7)<<7) \
- | (r&0xfc) )
-
-int mv_pci_read (int bus, int dev, int func, int reg)
-{
- *(u32 *) (0xfec00cf8) = PCI_CONFIG (bus, dev, func, reg);
- asm ("sync");
- return cpu_to_le32 (*(u32 *) (0xfee00cfc));
-}
-
-u32 get_BoardType ()
-{
- return (mv_pci_read (0, 0xe, 0, 0) == 0x06801095 ? 0 : 1);
-}
-
-void init_2nd_DUART (void)
-{
- NS16550_t console = (NS16550_t) CONFIG_SYS_NS16550_COM2;
- int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE;
-
- *(u8 *) (0xfc004511) = 0x1;
- NS16550_init (console, clock_divisor);
-}
-void hw_watchdog_reset (void)
-{
- if (get_BoardType () == 0) {
- *(u32 *) (0xff000005) = 0;
- asm ("sync");
- }
-}
-int checkboard (void)
-{
- ulong busfreq = get_bus_freq (0);
- char buf[32];
- u32 BoardType = get_BoardType ();
- char *BoardName[2] = { "mvBlueBOX", "mvBlueLYNX" };
- char *p;
-
- hw_watchdog_reset ();
-
- printf ("U-Boot (%s) running on mvBLUE device.\n", MV_VERSION);
- printf (" Found %s running@%s MHz memory clock.\n",
- BoardName[BoardType], strmhz (buf, busfreq));
-
- init_2nd_DUART ();
-
- if ((p = getenv ("console_nr")) != NULL) {
- unsigned long con_nr = simple_strtoul (p, NULL, 10) & 3;
-
- gd->baudrate &= ~3;
- gd->baudrate |= con_nr & 3;
- }
- return 0;
-}
-
-phys_size_t initdram (int board_type)
-{
- long size;
- long new_bank0_end;
- long mear1;
- long emear1;
-
- size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
-
- new_bank0_end = size - 1;
- mear1 = mpc824x_mpc107_getreg(MEAR1);
- emear1 = mpc824x_mpc107_getreg(EMEAR1);
- mear1 = (mear1 & 0xFFFFFF00) |
- ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
- emear1 = (emear1 & 0xFFFFFF00) |
- ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
- mpc824x_mpc107_setreg(MEAR1, mear1);
- mpc824x_mpc107_setreg(EMEAR1, emear1);
-
- return (size);
-}
-
-/* ------------------------------------------------------------------------- */
-u8 *dhcp_vendorex_prep (u8 * e)
-{
- char *ptr;
-
- /* DHCP vendor-class-identifier = 60 */
- if ((ptr = getenv ("dhcp_vendor-class-identifier"))) {
- *e++ = 60;
- *e++ = strlen (ptr);
- while (*ptr)
- *e++ = *ptr++;
- }
- /* my DHCP_CLIENT_IDENTIFIER = 61 */
- if ((ptr = getenv ("dhcp_client_id"))) {
- *e++ = 61;
- *e++ = strlen (ptr);
- while (*ptr)
- *e++ = *ptr++;
- }
- return e;
-}
-
-u8 *dhcp_vendorex_proc (u8 * popt)
-{
- return NULL;
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Initialize PCI Devices
- */
-#ifdef CONFIG_PCI
-void pci_mvblue_clear_base (struct pci_controller *hose, pci_dev_t dev)
-{
- u32 cnt;
-
- printf ("clear base @ dev/func 0x%02x/0x%02x ... ", PCI_DEV (dev),
- PCI_FUNC (dev));
- for (cnt = 0; cnt < 6; cnt++)
- pci_hose_write_config_dword (hose, dev, 0x10 + (4 * cnt),
- 0x0);
- printf ("done\n");
-}
-
-void duart_setup (u32 base, u16 divisor)
-{
- printf ("duart setup ...");
- out_8 ((u8 *) (CONFIG_SYS_ISA_IO + base + 3), 0x80);
- out_8 ((u8 *) (CONFIG_SYS_ISA_IO + base + 0), divisor & 0xff);
- out_8 ((u8 *) (CONFIG_SYS_ISA_IO + base + 1), divisor >> 8);
- out_8 ((u8 *) (CONFIG_SYS_ISA_IO + base + 3), 0x03);
- out_8 ((u8 *) (CONFIG_SYS_ISA_IO + base + 4), 0x03);
- out_8 ((u8 *) (CONFIG_SYS_ISA_IO + base + 2), 0x07);
- printf ("done\n");
-}
-
-void pci_mvblue_fixup_irq_behind_bridge (struct pci_controller *hose,
- pci_dev_t bridge, unsigned char irq)
-{
- pci_dev_t d;
- unsigned char bus;
- unsigned short vendor, class;
-
- pci_hose_read_config_byte (hose, bridge, PCI_SECONDARY_BUS, &bus);
- for (d = PCI_BDF (bus, 0, 0);
- d < PCI_BDF (bus, PCI_MAX_PCI_DEVICES - 1,
- PCI_MAX_PCI_FUNCTIONS - 1);
- d += PCI_BDF (0, 0, 1)) {
- pci_hose_read_config_word (hose, d, PCI_VENDOR_ID, &vendor);
- if (vendor != 0xffff && vendor != 0x0000) {
- pci_hose_read_config_word (hose, d, PCI_CLASS_DEVICE,
- &class);
- if (class == PCI_CLASS_BRIDGE_PCI)
- pci_mvblue_fixup_irq_behind_bridge (hose, d,
- irq);
- else
- pci_hose_write_config_byte (hose, d,
- PCI_INTERRUPT_LINE,
- irq);
- }
- }
-}
-
-#define MV_MAX_PCI_BUSSES 3
-#define SLOT0_IRQ 3
-#define SLOT1_IRQ 4
-void pci_mvblue_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
-{
- unsigned char line = 0xff;
- unsigned short class;
-
- if (PCI_BUS (dev) == 0) {
- switch (PCI_DEV (dev)) {
- case 0xd:
- if (get_BoardType () == 0) {
- line = 1;
- } else
- /* mvBL */
- line = 2;
- break;
- case 0xe:
- /* mvBB: IDE */
- line = 2;
- pci_hose_write_config_byte (hose, dev, 0x8a, 0x20);
- break;
- case 0xf:
- /* mvBB: Slot0 (Grabber) */
- pci_hose_read_config_word (hose, dev,
- PCI_CLASS_DEVICE, &class);
- if (class == PCI_CLASS_BRIDGE_PCI) {
- pci_mvblue_fixup_irq_behind_bridge (hose, dev,
- SLOT0_IRQ);
- line = 0xff;
- } else
- line = SLOT0_IRQ;
- break;
- case 0x10:
- /* mvBB: Slot1 */
- pci_hose_read_config_word (hose, dev,
- PCI_CLASS_DEVICE, &class);
- if (class == PCI_CLASS_BRIDGE_PCI) {
- pci_mvblue_fixup_irq_behind_bridge (hose, dev,
- SLOT1_IRQ);
- line = 0xff;
- } else
- line = SLOT1_IRQ;
- break;
- default:
- printf ("***pci_scan: illegal dev = 0x%08x\n",
- PCI_DEV (dev));
- line = 0xff;
- break;
- }
- pci_hose_write_config_byte (hose, dev, PCI_INTERRUPT_LINE,
- line);
- }
-}
-
-struct pci_controller hose = {
- fixup_irq:pci_mvblue_fixup_irq
-};
-
-void pci_init_board (void)
-{
- pci_mpc824x_init (&hose);
-}
-
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
-#endif
diff --git a/board/mvblue/u-boot.lds b/board/mvblue/u-boot.lds
deleted file mode 100644
index 5034a96..0000000
--- a/board/mvblue/u-boot.lds
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * (C) Copyright 2001-2007
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- .text :
- {
- arch/powerpc/cpu/mpc824x/start.o (.text*)
- lib/built-in.o (.text*)
- net/built-in.o (.text*)
- drivers/pci/built-in.o (.text*)
- arch/powerpc/cpu/mpc824x/built-in.o (.text*)
- board/mvblue/built-in.o (.text*)
- arch/powerpc/lib/built-in.o (.text*)
-
- . = DEFINED(env_offset) ? env_offset : .;
- common/env_embedded.o (.ppcenv*)
-
- *(.text*)
- . = ALIGN(16);
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
diff --git a/board/sandpoint/Kconfig b/board/sandpoint/Kconfig
deleted file mode 100644
index c19b63e..0000000
--- a/board/sandpoint/Kconfig
+++ /dev/null
@@ -1,19 +0,0 @@
-if TARGET_SANDPOINT8240
-
-config SYS_BOARD
- default "sandpoint"
-
-config SYS_CONFIG_NAME
- default "Sandpoint8240"
-
-endif
-
-if TARGET_SANDPOINT8245
-
-config SYS_BOARD
- default "sandpoint"
-
-config SYS_CONFIG_NAME
- default "Sandpoint8245"
-
-endif
diff --git a/board/sandpoint/MAINTAINERS b/board/sandpoint/MAINTAINERS
deleted file mode 100644
index 569cf42..0000000
--- a/board/sandpoint/MAINTAINERS
+++ /dev/null
@@ -1,12 +0,0 @@
-SANDPOINT BOARD
-M: Wolfgang Denk <wd@denx.de>
-S: Maintained
-F: board/sandpoint/
-F: include/configs/Sandpoint8240.h
-F: configs/Sandpoint8240_defconfig
-
-SANDPOINT8245 BOARD
-#M: Jim Thompson <jim@musenki.com>
-S: Orphan (since 2014-04)
-F: include/configs/Sandpoint8245.h
-F: configs/Sandpoint8245_defconfig
diff --git a/board/sandpoint/Makefile b/board/sandpoint/Makefile
deleted file mode 100644
index 58f5a89..0000000
--- a/board/sandpoint/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = sandpoint.o flash.o
diff --git a/board/sandpoint/README b/board/sandpoint/README
deleted file mode 100644
index c9996a8..0000000
--- a/board/sandpoint/README
+++ /dev/null
@@ -1,411 +0,0 @@
-This port of U-Boot will run on a Motorola Sandpoint 3 development
-system equipped with a Unity X4 PPMC card (MPC8240 CPU) only. It is a
-snapshot of work in progress and far from being completed. In order
-to run it on the target system, it has to be downloaded using the
-DINK32 monitor program that came with your Sandpoint system. Please
-note that DINK32 does not accept the S-Record file created by the
-U-Boot build process unmodified, because it contains CR/LF line
-terminators. You have to strip the CR characters first. There is a
-tiny script named 'dinkdl' I created for this purpose.
-
-The Sandpoint port is based on the work of Rob Taylor, who does not
-seem to maintain it any more. I can be reached by mail as
-tkoeller at gmx.net.
-
-Thomas Koeller
-
-
-The port was tested on a Sandpoint 8240 X3 board, with U-Boot
-installed in the flash memory of the CPU card. Please use the
-following DIP switch settings:
-
-Motherboard:
-
-SW1.1: on SW1.2: on SW1.3: on SW1.4: on
-SW1.5: on SW1.6: on SW1.7: on SW1.8: on
-
-SW2.1: on SW2.2: on SW2.3: on SW2.4: on
-SW2.5: on SW2.6: on SW2.7: on SW2.8: on
-
-
-CPU Card:
-
-SW2.1: OFF SW2.2: OFF SW2.3: on SW2.4: on
-SW2.5: OFF SW2.6: OFF SW2.7: OFF SW2.8: OFF
-
-SW3.1: OFF SW3.2: on SW3.3: OFF SW3.4: OFF
-SW3.5: on SW3.6: OFF SW3.7: OFF SW3.8: on
-
-
-The followind detailed description of installation and initial steps
-with U-Boot and QNX was provided by Jim Sandoz <sandoz@lucent.com>:
-
-
-Directions for installing U-Boot on Sandpoint+Unity8240
-using the Abatron BDI2000 BDM/JTAG debugger ...
-
-Background and Reference info:
-http://u-boot.sourceforge.net/
-http://www.abatron.ch/
-http://www.abatron.ch/BDI/bdihw.html
-http://www.abatron.ch/DataSheets/BDI2000.pdf
-http://www.abatron.ch/Manuals/ManGdbCOP-2000C.pdf
-http://e-www.motorola.com/collateral/SPX3UM.pdf
-http://e-www.motorola.com/collateral/UNITYX4CONFIG.pdf
-
-
-Connection Diagram:
- ===========
- === ===== |----- |
-| | <---------------> | | | | |
-|PC | rs232 | BDI |=============[] | |
-| | |2000 | BDM probe | | |
-| | <---------------> | | |----- |
- === ethernet ===== | |
- | |
- ===========
- Sandpoint X3 with
- Unity 8240 proc
-
-
-PART 1)
- DIP Switch Settings:
-
-Sandpoint X3 8240 processor board DIP switch settings, with
-U-Boot to be installed in the flash memory of the CPU card:
-
-Motorola Sandpoint X3 Motherboard:
-SW1.1: on SW1.2: on SW1.3: on SW1.4: on
-SW1.5: on SW1.6: on SW1.7: on SW1.8: on
-SW2.1: on SW2.2: on SW2.3: on SW2.4: on
-SW2.5: on SW2.6: on SW2.7: on SW2.8: on
-
-Motorola Unity 8240 CPU Card:
-SW2.1: OFF SW2.2: OFF SW2.3: on SW2.4: on
-SW2.5: OFF SW2.6: OFF SW2.7: OFF SW2.8: OFF
-SW3.1: OFF SW3.2: on SW3.3: OFF SW3.4: OFF
-SW3.5: on SW3.6: OFF SW3.7: OFF SW3.8: on
-
-
-PART 2)
- Connect the BDI2000 Cable to the Sandpoint/Unity 8240:
-
-BDM Pin 1 on the Unity 8240 processor board is towards the
-PCI PMC connectors, or away from the socketed SDRAM, i.e.:
-
- ====================
- | ---------------- |
- | | SDRAM | |
- | | | |
- | ---------------- |
- | |~| |
- | |B| ++++++ |
- | |D| + uP + |
- | |M| +8240+ |
- | ~ 1 ++++++ |
- | |
- | |
- | |
- | PMC conn ====== |
- | ===== ====== |
- | |
- ====================
-
-
-PART 3)
- Setting up the BDI2000, and preparing for TCP/IP network comms:
-
-Connect the BDI2000 to the PC using the supplied serial cable.
-Download the BDI2000 software and install it using setup.exe.
-
-[Note: of course you can also use the Linux command line tool
-"bdisetup" to configure your BDI2000 - the sources are included on
-the floppy disk that comes with your BDI2000. Just in case you don't
-have any Windows PC's - like me :-) -- wd ]
-
-Power up the BDI2000; then follow directions to assign the IP
-address and related network information. Note that U-Boot
-will be loaded to the Sandpoint via tftp. You need to either
-use the Abatron-provided tftp application or provide a tftp
-server (e.g. Linux/Solaris/*BSD) somewhere on your network.
-Once the IP address etc are assigned via the RS232 port,
-further communication with the BDI2000 will happen via the
-ethernet connection.
-
-PART 4)
- Making a TCP/IP network connection to the Abatron BDI2000:
-
-Telnet to the Abatron BDI2000. Assuming that all of the
-networking info was loaded via RS232 correctly, you will see
-the following (scrolling):
-
-- TARGET: waiting for target Vcc
-- TARGET: waiting for target Vcc
-
-
-PART 5)
- Power up the target Sandpoint:
-If the BDM connections are correct, the following will now appear:
-
-- TARGET: waiting for target Vcc
-- TARGET: waiting for target Vcc
-- TARGET: processing power-up delay
-- TARGET: processing user reset request
-- BDI asserts HRESET
-- Reset JTAG controller passed
-- Bypass check: 0x55 => 0xAA
-- Bypass check: 0x55 => 0xAA
-- JTAG exists check passed
-- Target PVR is 0x00810101
-- COP status is 0x01
-- Check running state passed
-- BDI scans COP freeze command
-- BDI removes HRESET
-- COP status is 0x05
-- Check stopped state passed
-- Check LSRL length passed
-- BDI sets breakpoint at 0xFFF00100
-- BDI resumes program execution
-- Waiting for target stop passed
-- TARGET: Target PVR is 0x00810101
-- TARGET: reseting target passed
-- TARGET: processing target startup ....
-- TARGET: processing target startup passed
-BDI>
-
-
-PART 6)
- Erase the current contents of the flash memory:
-
-BDI>era 0xFFF00000
- Erasing flash at 0xfff00000
- Erasing flash passed
-BDI>era 0xFFF04000
- Erasing flash at 0xfff04000
- Erasing flash passed
-BDI>era 0xFFF06000
- Erasing flash at 0xfff06000
- Erasing flash passed
-BDI>era 0xFFF08000
- Erasing flash at 0xfff08000
- Erasing flash passed
-BDI>era 0xFFF10000
- Erasing flash at 0xfff10000
- Erasing flash passed
-BDI>era 0xFFF20000
- Erasing flash at 0xfff20000
- Erasing flash passed
-
-
-PART 7)
- Program the flash memory with the U-Boot image:
-
-BDI>prog 0xFFF00000 u-boot.bin bin
- Programming u-boot.bin , please wait ....
- Programming flash passed
-
-
-PART 8)
- Connect PC to Sandpoint:
-Using a crossover serial cable, attach the PC serial port to the
-Sandpoint's COM1. Set communications parameters to 8N1 / 9600 baud.
-
-
-PART 9)
- Reset the Unity and begin U-Boot execution:
-
-BDI>reset
-- TARGET: processing user reset request
-- TARGET: Target PVR is 0x00810101
-- TARGET: reseting target passed
-- TARGET: processing target init list ....
-- TARGET: processing target init list passed
-
-BDI>go
-
-Now see output from U-Boot running, sent via serial port:
-
-U-Boot 1.1.4 (Jan 23 2002 - 18:29:19)
-
-CPU: MPC8240 Revision 1.1 at 264 MHz: 16 kB I-Cache 16 kB D-Cache
-Board: Sandpoint 8240 Unity
-DRAM: 64 MB
-FLASH: 2 MB
-PCI: scanning bus0 ...
- bus dev fn venID devID class rev MBAR0 MBAR1 IPIN ILINE
- 00 00 00 1057 0003 060000 13 00000008 00000000 01 00
- 00 0b 00 10ad 0565 060100 10 00000000 00000000 00 00
- 00 0f 00 8086 1229 020000 08 80000000 80000001 01 00
-In: serial
-Out: serial
-Err: serial
-=>
-
-
-PART 10)
- Set and save any required environmental variables, examples of some:
-
-=> setenv ethaddr 00:03:47:97:D0:79
-=> setenv bootfile your_qnx_image_here
-=> setenv hostname sandpointX
-=> setenv netmask 255.255.255.0
-=> setenv ipaddr 192.168.0.11
-=> setenv serverip 192.168.0.10
-=> setenv gatewayip=192.168.0.1
-=> saveenv
-Saving Environment to Flash...
-Un-Protected 1 sectors
-Erasing Flash...
- done
-Erased 1 sectors
-Writing to Flash... done
-Protected 1 sectors
-=>
-
-**** Example environment: ****
-
-=> printenv
-baudrate=9600
-bootfile=telemetry
-hostname=sp1
-ethaddr=00:03:47:97:E4:6B
-load=tftp 100000 u-boot.bin
-update=protect off all;era FFF00000 FFF3FFFF;cp.b 100000 FFF00000 ${filesize};saveenv
-filesize=1f304
-gatewayip=145.17.228.1
-netmask=255.255.255.0
-ipaddr=145.17.228.42
-serverip=145.17.242.46
-stdin=serial
-stdout=serial
-stderr=serial
-
-Environment size: 332/8188 bytes
-=>
-
-here's some text useful stuff for cut-n-paste:
-setenv hostname sandpoint1
-setenv netmask 255.255.255.0
-setenv ipaddr 145.17.228.81
-setenv serverip 145.17.242.46
-setenv gatewayip 145.17.228.1
-saveenv
-
-PART 11)
- Test U-Boot by tftp'ing new U-Boot, overwriting current:
-
-=> protect off all
-Un-Protect Flash Bank # 1
-=> tftp 100000 u-boot.bin
-eth: Intel i82559 PCI EtherExpressPro @0x80000000(bus=0, device=15, func=0)
-ARP broadcast 1
-TFTP from server 145.17.242.46; our IP address is 145.17.228.42; sending through
- gateway 145.17.228.1
-Filename 'u-boot.bin'.
-Load address: 0x100000
-Loading: #########################
-done
-Bytes transferred = 127628 (1f28c hex)
-=> era all
-Erase Flash Bank # 1
- done
-Erase Flash Bank # 2 - missing
-=> cp.b 0x100000 FFF00000 1f28c
-Copy to Flash... done
-=> saveenv
-Saving Environment to Flash...
-Un-Protected 1 sectors
-Erasing Flash...
- done
-Erased 1 sectors
-Writing to Flash... done
-Protected 1 sectors
-=> reset
-
-You can put these commands into some environment variables;
-
-=> setenv load tftp 100000 u-boot.bin
-=> setenv update protect off all\;era FFF00000 FFF3FFFF\;cp.b 100000 FFF00000 \${filesize}\;saveenv
-=> saveenv
-
-Then you just have to type "run load" then "run update"
-
-=> run load
-eth: Intel i82559 PCI EtherExpressPro @0x80000000(bus=0, device=15, func=0)
-ARP broadcast 1
-TFTP from server 145.17.242.46; our IP address is 145.17.228.42; sending through
- gateway 145.17.228.1
-Filename 'u-boot.bin'.
-Load address: 0x100000
-Loading: #########################
-done
-Bytes transferred = 127748 (1f304 hex)
-=> run update
-Un-Protect Flash Bank # 1
-Un-Protect Flash Bank # 2
-Erase Flash from 0xfff00000 to 0xfff3ffff
- done
-Erased 7 sectors
-Copy to Flash... done
-Saving Environment to Flash...
-Un-Protected 1 sectors
-Erasing Flash...
- done
-Erased 1 sectors
-Writing to Flash... done
-Protected 1 sectors
-=>
-
-
-PART 12)
- Load OS image (ELF format) via U-Boot using tftp
-
-
-=> tftp 800000 sandpoint-simple.elf
-eth: Intel i82559 PCI EtherExpressPro @0x80000000(bus=0, device=15, func=0)
-ARP broadcast 1
-TFTP from server 145.17.242.46; our IP address is 145.17.228.42; sending through
- gateway 145.17.228.1
-Filename 'sandpoint-simple.elf'.
-Load address: 0x800000
-Loading: #################################################################
- #################################################################
- #################################################################
- ########################
-done
-Bytes transferred = 1120284 (11181c hex)
-==>
-
-PART 13)
- Begin OS image execution: (note that unless you have the
-serial parameters of your OS image set to 9600 (i.e. same as
-the U-Boot binary) you will get garbage here until you change
-the serial communications speed.
-
-=> bootelf 800000
-Loading @ 0x001f0100 (1120028 bytes)
-## Starting application at 0x001f1d28 ...
-Replace init_hwinfo() with a board specific version
-
-Loading QNX6....
-
-Header size=0x0000009c, Total Size=0x000005c0, #Cpu=1, Type=1
-<...loader and kernel messages snipped...>
-
-Welcome to Neutrino on the Sandpoint
-#
-
-
-other information:
-
-CVS Retrieval Notes:
-
-U-Boot's SourceForge CVS repository can be checked out
-through anonymous (pserver) CVS with the following
-instruction set. The module you wish to check out must
-be specified as the modulename. When prompted for a
-password for anonymous, simply press the Enter key.
-
-cvs -d:pserver:anonymous at cvs.u-boot.sourceforge.net:/cvsroot/u-boot login
-
-cvs -z6 -d:pserver:anonymous at cvs.u-boot.sourceforge.net:/cvsroot/u-boot co -P u-boot
diff --git a/board/sandpoint/dinkdl b/board/sandpoint/dinkdl
deleted file mode 100644
index f281452..0000000
--- a/board/sandpoint/dinkdl
+++ /dev/null
@@ -1,2 +0,0 @@
-#! /bin/bash
-tr -d "\r" <$1 >/dev/tts/1
diff --git a/board/sandpoint/flash.c b/board/sandpoint/flash.c
deleted file mode 100644
index 1ab668c..0000000
--- a/board/sandpoint/flash.c
+++ /dev/null
@@ -1,748 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc824x.h>
-#include <asm/processor.h>
-#include <asm/pci_io.h>
-#include <w83c553f.h>
-
-#define ROM_CS0_START 0xFF800000
-#define ROM_CS1_START 0xFF000000
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-# ifndef CONFIG_ENV_ADDR
-# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-# endif
-# ifndef CONFIG_ENV_SIZE
-# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-# endif
-# ifndef CONFIG_ENV_SECT_SIZE
-# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
-# endif
-#endif
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-#if 0
-static void flash_get_offsets (ulong base, flash_info_t *info);
-#endif /* 0 */
-
-/*flash command address offsets*/
-
-#if 0
-#define ADDR0 (0x555)
-#define ADDR1 (0x2AA)
-#define ADDR3 (0x001)
-#else
-#define ADDR0 (0xAAA)
-#define ADDR1 (0x555)
-#define ADDR3 (0x001)
-#endif
-
-#define FLASH_WORD_SIZE unsigned char
-
-/*-----------------------------------------------------------------------
- */
-
-#if 0
-static int byte_parity_odd(unsigned char x) __attribute__ ((const));
-#endif /* 0 */
-static unsigned long flash_id(unsigned char mfct, unsigned char chip) __attribute__ ((const));
-
-typedef struct
-{
- FLASH_WORD_SIZE extval;
- unsigned short intval;
-} map_entry;
-
-#if 0
-static int
-byte_parity_odd(unsigned char x)
-{
- x ^= x >> 4;
- x ^= x >> 2;
- x ^= x >> 1;
- return (x & 0x1) != 0;
-}
-#endif /* 0 */
-
-
-static unsigned long
-flash_id(unsigned char mfct, unsigned char chip)
-{
- static const map_entry mfct_map[] =
- {
- {(FLASH_WORD_SIZE) AMD_MANUFACT, (unsigned short) ((unsigned long) FLASH_MAN_AMD >> 16)},
- {(FLASH_WORD_SIZE) FUJ_MANUFACT, (unsigned short) ((unsigned long) FLASH_MAN_FUJ >> 16)},
- {(FLASH_WORD_SIZE) STM_MANUFACT, (unsigned short) ((unsigned long) FLASH_MAN_STM >> 16)},
- {(FLASH_WORD_SIZE) MT_MANUFACT, (unsigned short) ((unsigned long) FLASH_MAN_MT >> 16)},
- {(FLASH_WORD_SIZE) INTEL_MANUFACT,(unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)},
- {(FLASH_WORD_SIZE) INTEL_ALT_MANU,(unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)}
- };
-
- static const map_entry chip_map[] =
- {
- {AMD_ID_F040B, FLASH_AM040},
- {(FLASH_WORD_SIZE) STM_ID_x800AB, FLASH_STM800AB}
- };
-
- const map_entry *p;
- unsigned long result = FLASH_UNKNOWN;
-
- /* find chip id */
- for(p = &chip_map[0]; p < &chip_map[sizeof chip_map / sizeof chip_map[0]]; p++)
- if(p->extval == chip)
- {
- result = FLASH_VENDMASK | p->intval;
- break;
- }
-
- /* find vendor id */
- for(p = &mfct_map[0]; p < &mfct_map[sizeof mfct_map / sizeof mfct_map[0]]; p++)
- if(p->extval == mfct)
- {
- result &= ~FLASH_VENDMASK;
- result |= (unsigned long) p->intval << 16;
- break;
- }
-
- return result;
-}
-
-
-unsigned long
-flash_init(void)
-{
- unsigned long i;
- unsigned char j;
- static const ulong flash_banks[] = CONFIG_SYS_FLASH_BANKS;
-
- /* Init: no FLASHes known */
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
- {
- flash_info_t * const pflinfo = &flash_info[i];
- pflinfo->flash_id = FLASH_UNKNOWN;
- pflinfo->size = 0;
- pflinfo->sector_count = 0;
- }
-
- /* Enable writes to Sandpoint flash */
- {
- register unsigned char temp;
- CONFIG_READ_BYTE(CONFIG_SYS_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR, temp);
- temp &= ~0x20; /* clear BIOSWP bit */
- CONFIG_WRITE_BYTE(CONFIG_SYS_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR, temp);
- }
-
- for(i = 0; i < sizeof flash_banks / sizeof flash_banks[0]; i++)
- {
- flash_info_t * const pflinfo = &flash_info[i];
- const unsigned long base_address = flash_banks[i];
- volatile FLASH_WORD_SIZE * const flash = (FLASH_WORD_SIZE *) base_address;
-#if 0
- volatile FLASH_WORD_SIZE * addr2;
-#endif
-#if 0
- /* write autoselect sequence */
- flash[0x5555] = 0xaa;
- flash[0x2aaa] = 0x55;
- flash[0x5555] = 0x90;
-#else
- flash[0xAAA << (3 * i)] = 0xaa;
- flash[0x555 << (3 * i)] = 0x55;
- flash[0xAAA << (3 * i)] = 0x90;
-#endif
- __asm__ __volatile__("sync");
-
-#if 0
- pflinfo->flash_id = flash_id(flash[0x0], flash[0x1]);
-#else
- pflinfo->flash_id = flash_id(flash[0x0], flash[0x2 + 14 * i]);
-#endif
-
- switch(pflinfo->flash_id & FLASH_TYPEMASK)
- {
- case FLASH_AM040:
- pflinfo->size = 0x00080000;
- pflinfo->sector_count = 8;
- for(j = 0; j < 8; j++)
- {
- pflinfo->start[j] = base_address + 0x00010000 * j;
- pflinfo->protect[j] = flash[(j << 16) | 0x2];
- }
- break;
- case FLASH_STM800AB:
- pflinfo->size = 0x00100000;
- pflinfo->sector_count = 19;
- pflinfo->start[0] = base_address;
- pflinfo->start[1] = base_address + 0x4000;
- pflinfo->start[2] = base_address + 0x6000;
- pflinfo->start[3] = base_address + 0x8000;
- for(j = 1; j < 16; j++)
- {
- pflinfo->start[j+3] = base_address + 0x00010000 * j;
- }
-#if 0
- /* check for protected sectors */
- for (j = 0; j < pflinfo->sector_count; j++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- addr2 = (volatile FLASH_WORD_SIZE *)(pflinfo->start[j]);
- if (pflinfo->flash_id & FLASH_MAN_SST)
- pflinfo->protect[j] = 0;
- else
- pflinfo->protect[j] = addr2[2] & 1;
- }
-#endif
- break;
- }
- /* Protect monitor and environment sectors
- */
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
- &flash_info[0]);
-#endif
-
-#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
- &flash_info[0]);
-#endif
-
- /* reset device to read mode */
- flash[0x0000] = 0xf0;
- __asm__ __volatile__("sync");
- }
-
- return flash_info[0].size + flash_info[1].size;
-}
-
-#if 0
-static void
-flash_get_offsets (ulong base, flash_info_t *info)
-{
- int i;
-
- /* set up sector start address table */
- if (info->flash_id & FLASH_MAN_SST)
- {
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = base + (i * 0x00010000);
- }
- else
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000) - 0x00030000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- }
-
-}
-#endif /* 0 */
-
-/*-----------------------------------------------------------------------
- */
-void
-flash_print_info(flash_info_t *info)
-{
- static const char unk[] = "Unknown";
- const char *mfct = unk, *type = unk;
- unsigned int i;
-
- if(info->flash_id != FLASH_UNKNOWN)
- {
- switch(info->flash_id & FLASH_VENDMASK)
- {
- case FLASH_MAN_AMD: mfct = "AMD"; break;
- case FLASH_MAN_FUJ: mfct = "FUJITSU"; break;
- case FLASH_MAN_STM: mfct = "STM"; break;
- case FLASH_MAN_SST: mfct = "SST"; break;
- case FLASH_MAN_BM: mfct = "Bright Microelectonics"; break;
- case FLASH_MAN_INTEL: mfct = "Intel"; break;
- }
-
- switch(info->flash_id & FLASH_TYPEMASK)
- {
- case FLASH_AM040: type = "AM29F040B (512K * 8, uniform sector size)"; break;
- case FLASH_AM400B: type = "AM29LV400B (4 Mbit, bottom boot sect)"; break;
- case FLASH_AM400T: type = "AM29LV400T (4 Mbit, top boot sector)"; break;
- case FLASH_AM800B: type = "AM29LV800B (8 Mbit, bottom boot sect)"; break;
- case FLASH_AM800T: type = "AM29LV800T (8 Mbit, top boot sector)"; break;
- case FLASH_AM160T: type = "AM29LV160T (16 Mbit, top boot sector)"; break;
- case FLASH_AM320B: type = "AM29LV320B (32 Mbit, bottom boot sect)"; break;
- case FLASH_AM320T: type = "AM29LV320T (32 Mbit, top boot sector)"; break;
- case FLASH_STM800AB: type = "M29W800AB (8 Mbit, bottom boot sect)"; break;
- case FLASH_SST800A: type = "SST39LF/VF800 (8 Mbit, uniform sector size)"; break;
- case FLASH_SST160A: type = "SST39LF/VF160 (16 Mbit, uniform sector size)"; break;
- }
- }
-
- printf(
- "\n Brand: %s Type: %s\n"
- " Size: %lu KB in %d Sectors\n",
- mfct,
- type,
- info->size >> 10,
- info->sector_count
- );
-
- printf (" Sector Start Addresses:");
-
- for (i = 0; i < info->sector_count; i++)
- {
- unsigned long size;
- unsigned int erased;
- unsigned long * flash = (unsigned long *) info->start[i];
-
- /*
- * Check if whole sector is erased
- */
- size =
- (i != (info->sector_count - 1)) ?
- (info->start[i + 1] - info->start[i]) >> 2 :
- (info->start[0] + info->size - info->start[i]) >> 2;
-
- for(
- flash = (unsigned long *) info->start[i], erased = 1;
- (flash != (unsigned long *) info->start[i] + size) && erased;
- flash++
- )
- erased = *flash == ~0x0UL;
-
- printf(
- "%s %08lX %s %s",
- (i % 5) ? "" : "\n ",
- info->start[i],
- erased ? "E" : " ",
- info->protect[i] ? "RO" : " "
- );
- }
-
- puts("\n");
- return;
-}
-
-#if 0
-
-/*
- * The following code cannot be run from FLASH!
- */
-ulong
-flash_get_size (vu_long *addr, flash_info_t *info)
-{
- short i;
- FLASH_WORD_SIZE value;
- ulong base = (ulong)addr;
- volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr;
-
- printf("flash_get_size: \n");
- /* Write auto select command: read Manufacturer ID */
- eieio();
- addr2[ADDR0] = (FLASH_WORD_SIZE)0xAA;
- addr2[ADDR1] = (FLASH_WORD_SIZE)0x55;
- addr2[ADDR0] = (FLASH_WORD_SIZE)0x90;
- value = addr2[0];
-
- switch (value) {
- case (FLASH_WORD_SIZE)AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
- case (FLASH_WORD_SIZE)FUJ_MANUFACT:
- info->flash_id = FLASH_MAN_FUJ;
- break;
- case (FLASH_WORD_SIZE)SST_MANUFACT:
- info->flash_id = FLASH_MAN_SST;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
- printf("recognised manufacturer");
-
- value = addr2[ADDR3]; /* device ID */
- debug ("\ndev_code=%x\n", value);
-
- switch (value) {
- case (FLASH_WORD_SIZE)AMD_ID_LV400T:
- info->flash_id += FLASH_AM400T;
- info->sector_count = 11;
- info->size = 0x00080000;
- break; /* => 0.5 MB */
-
- case (FLASH_WORD_SIZE)AMD_ID_LV400B:
- info->flash_id += FLASH_AM400B;
- info->sector_count = 11;
- info->size = 0x00080000;
- break; /* => 0.5 MB */
-
- case (FLASH_WORD_SIZE)AMD_ID_LV800T:
- info->flash_id += FLASH_AM800T;
- info->sector_count = 19;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (FLASH_WORD_SIZE)AMD_ID_LV800B:
- info->flash_id += FLASH_AM800B;
- info->sector_count = 19;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (FLASH_WORD_SIZE)AMD_ID_LV160T:
- info->flash_id += FLASH_AM160T;
- info->sector_count = 35;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (FLASH_WORD_SIZE)AMD_ID_LV160B:
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (FLASH_WORD_SIZE)SST_ID_xF800A:
- info->flash_id += FLASH_SST800A;
- info->sector_count = 16;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (FLASH_WORD_SIZE)SST_ID_xF160A:
- info->flash_id += FLASH_SST160A;
- info->sector_count = 32;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (FLASH_WORD_SIZE)AMD_ID_F040B:
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x00080000;
- break; /* => 0.5 MB */
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
-
- }
-
- printf("flash id %lx; sector count %x, size %lx\n", info->flash_id,info->sector_count,info->size);
- /* set up sector start address table */
- if (info->flash_id & FLASH_MAN_SST)
- {
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = base + (i * 0x00010000);
- }
- else
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000) - 0x00030000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- }
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
- if (info->flash_id & FLASH_MAN_SST)
- info->protect[i] = 0;
- else
- info->protect[i] = addr2[2] & 1;
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- addr2 = (FLASH_WORD_SIZE *)info->start[0];
- *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
- }
-
- return (info->size);
-}
-
-#endif
-
-
-int
-flash_erase(flash_info_t *info, int s_first, int s_last)
-{
- volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
- int flag, prot, sect, l_sect;
- ulong start, now, last;
- unsigned char sh8b;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id == FLASH_UNKNOWN) ||
- (info->flash_id > (FLASH_MAN_STM | FLASH_AMD_COMP))) {
- printf ("Can't erase unknown flash type - aborted\n");
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Check the ROM CS */
- if ((info->start[0] >= ROM_CS1_START) && (info->start[0] < ROM_CS0_START))
- sh8b = 3;
- else
- sh8b = 0;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA;
- addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055;
- addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00800080;
- addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA;
- addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055;
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = (FLASH_WORD_SIZE *)(info->start[0] + (
- (info->start[sect] - info->start[0]) << sh8b));
- if (info->flash_id & FLASH_MAN_SST)
- {
- addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA;
- addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055;
- addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00800080;
- addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA;
- addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055;
- addr[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */
- udelay(30000); /* wait 30 ms */
- }
- else
- addr[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait@least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer (0);
- last = start;
- addr = (FLASH_WORD_SIZE *)(info->start[0] + (
- (info->start[l_sect] - info->start[0]) << sh8b));
- while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- serial_putc ('.');
- last = now;
- }
- }
-
-DONE:
- /* reset to read mode */
- addr = (FLASH_WORD_SIZE *)info->start[0];
- addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
-
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i=0; i<4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
- volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)info->start[0];
- volatile FLASH_WORD_SIZE *dest2;
- volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data;
- ulong start;
- int flag;
- int i;
- unsigned char sh8b;
-
- /* Check the ROM CS */
- if ((info->start[0] >= ROM_CS1_START) && (info->start[0] < ROM_CS0_START))
- sh8b = 3;
- else
- sh8b = 0;
-
- dest2 = (FLASH_WORD_SIZE *)(((dest - info->start[0]) << sh8b) +
- info->start[0]);
-
- /* Check if Flash is (sufficiently) erased */
- if ((*dest2 & (FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++)
- {
- addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA;
- addr2[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055;
- addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00A000A0;
-
- dest2[i << sh8b] = data2[i];
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((dest2[i << sh8b] & (FLASH_WORD_SIZE)0x00800080) !=
- (data2[i] & (FLASH_WORD_SIZE)0x00800080)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- }
-
- return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
diff --git a/board/sandpoint/sandpoint.c b/board/sandpoint/sandpoint.c
deleted file mode 100644
index 16237bd..0000000
--- a/board/sandpoint/sandpoint.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * (C) Copyright 2000
- * Rob Taylor, Flying Pig Systems. robt at flyingpig.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc824x.h>
-#include <pci.h>
-#include <netdev.h>
-
-int checkboard (void)
-{
- /*TODO: Check processor type */
-
- puts ( "Board: Sandpoint "
-#ifdef CONFIG_MPC8240
- "8240"
-#endif
-#ifdef CONFIG_MPC8245
- "8245"
-#endif
- " Unity ##Test not implemented yet##\n");
- return 0;
-}
-
-#if 0 /* NOT USED */
-int checkflash (void)
-{
- /* TODO: XXX XXX XXX */
- printf ("## Test not implemented yet ##\n");
-
- return (0);
-}
-#endif
-
-phys_size_t initdram (int board_type)
-{
- long size;
- long new_bank0_end;
- long mear1;
- long emear1;
-
- size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
-
- new_bank0_end = size - 1;
- mear1 = mpc824x_mpc107_getreg(MEAR1);
- emear1 = mpc824x_mpc107_getreg(EMEAR1);
- mear1 = (mear1 & 0xFFFFFF00) |
- ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
- emear1 = (emear1 & 0xFFFFFF00) |
- ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
- mpc824x_mpc107_setreg(MEAR1, mear1);
- mpc824x_mpc107_setreg(EMEAR1, emear1);
-
- return (size);
-}
-
-/*
- * Initialize PCI Devices, report devices found.
- */
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_sandpoint_config_table[] = {
- { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
- pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
- PCI_ENET0_MEMADDR,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
- { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID,
- pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
- PCI_ENET1_MEMADDR,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
- { }
-};
-#endif
-
-struct pci_controller hose = {
-#ifndef CONFIG_PCI_PNP
- config_table: pci_sandpoint_config_table,
-#endif
-};
-
-void pci_init_board(void)
-{
- pci_mpc824x_init(&hose);
-}
-
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
diff --git a/board/sandpoint/u-boot.lds b/board/sandpoint/u-boot.lds
deleted file mode 100644
index cd9f07c..0000000
--- a/board/sandpoint/u-boot.lds
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * (C) Copyright 2001-2007
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc824x/start.o (.text*)
- *(.text.v*printf)
-
- . = DEFINED(env_offset) ? env_offset : .;
- common/env_embedded.o (.ppcenv*)
-
- *(.text*)
- . = ALIGN(16);
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
diff --git a/board/utx8245/Kconfig b/board/utx8245/Kconfig
deleted file mode 100644
index aec0eb9..0000000
--- a/board/utx8245/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_UTX8245
-
-config SYS_BOARD
- default "utx8245"
-
-config SYS_CONFIG_NAME
- default "utx8245"
-
-endif
diff --git a/board/utx8245/MAINTAINERS b/board/utx8245/MAINTAINERS
deleted file mode 100644
index bed69c8..0000000
--- a/board/utx8245/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-UTX8245 BOARD
-M: Greg Allen <gallen@arlut.utexas.edu>
-S: Maintained
-F: board/utx8245/
-F: include/configs/utx8245.h
-F: configs/utx8245_defconfig
diff --git a/board/utx8245/Makefile b/board/utx8245/Makefile
deleted file mode 100644
index f12e545..0000000
--- a/board/utx8245/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# (C) Copyright 2002
-# Gregory E. Allen, gallen at arlut.utexas.edu
-# Matthew E. Karger, karger at arlut.utexas.edu
-# Applied Research Laboratories, The University of Texas at Austin
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = utx8245.o flash.o
diff --git a/board/utx8245/flash.c b/board/utx8245/flash.c
deleted file mode 100644
index 1dfcb41..0000000
--- a/board/utx8245/flash.c
+++ /dev/null
@@ -1,544 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * (C) Copyright 2002
- * Gregory E. Allen, gallen at arlut.utexas.edu
- * Matthew E. Karger, karger at arlut.utexas.edu
- * Applied Research Laboratories, The University of Texas at Austin
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc824x.h>
-#include <asm/processor.h>
-
-#define ROM_CS0_START 0xFF800000
-#define ROM_CS1_START 0xFF000000
-
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-# ifndef CONFIG_ENV_ADDR
-# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-# endif
-# ifndef CONFIG_ENV_SIZE
-# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-# endif
-# ifndef CONFIG_ENV_SECT_SIZE
-# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
-# endif
-#endif
-
-#define FLASH_BANK_SIZE ((uint)(16 * 1024 * 1024)) /* max 16Mbyte */
-#define MAIN_SECT_SIZE 0x10000
-#define SECT_SIZE_32KB 0x8000
-#define SECT_SIZE_8KB 0x2000
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-static int write_word (flash_info_t * info, ulong dest, ulong data);
-#if 0
-static void write_via_fpu (vu_long * addr, ulong * data);
-#endif
-static __inline__ unsigned long get_msr (void);
-static __inline__ void set_msr (unsigned long msr);
-
-/*flash command address offsets*/
-#define ADDR0 (0x555)
-#define ADDR1 (0xAAA)
-#define ADDR3 (0x001)
-
-#define FLASH_WORD_SIZE unsigned char
-
-/*---------------------------------------------------------------------*/
-/*#define DEBUG_FLASH 1 */
-
-/*---------------------------------------------------------------------*/
-
-unsigned long flash_init (void)
-{
- int i; /* flash bank counter */
- int j; /* flash device sector counter */
- int k; /* flash size calculation loop counter */
- int N; /* pow(2,N) is flash size, but we don't have <math.h> */
- ulong total_size = 0, device_size = 1;
- unsigned char manuf_id, device_id;
-
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
- vu_char *addr = (vu_char *) (CONFIG_SYS_FLASH_BASE + i * FLASH_BANK_SIZE);
-
- addr[0x555] = 0xAA; /* get manuf/device info command */
- addr[0x2AA] = 0x55; /* 3-cycle command */
- addr[0x555] = 0x90;
-
- manuf_id = addr[0]; /* read back manuf/device info */
- device_id = addr[1];
-
- addr[0x55] = 0x98; /* CFI command */
- N = addr[0x27]; /* read back device_size = pow(2,N) */
-
- for (k = 0; k < N; k++) /* calculate device_size = pow(2,N) */
- device_size *= 2;
-
- flash_info[i].size = device_size;
- flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
-
-#if defined DEBUG_FLASH
- printf ("manuf_id = %x, device_id = %x\n", manuf_id, device_id);
-#endif
- /* find out what kind of flash we are using */
- if ((manuf_id == (uchar) (AMD_MANUFACT))
- && (device_id == AMD_ID_LV033C)) {
- flash_info[i].flash_id =
- ((FLASH_MAN_AMD & FLASH_VENDMASK) << 16) |
- (FLASH_AM033C & FLASH_TYPEMASK);
-
- /* set individual sector start addresses */
- for (j = 0; j < flash_info[i].sector_count; j++) {
- flash_info[i].start[j] =
- (CONFIG_SYS_FLASH_BASE + i * FLASH_BANK_SIZE +
- j * MAIN_SECT_SIZE);
- }
- }
-
- else if ((manuf_id == (uchar) (AMD_MANUFACT)) &&
- (device_id == AMD_ID_LV116DT)) {
- flash_info[i].flash_id =
- ((FLASH_MAN_AMD & FLASH_VENDMASK) << 16) |
- (FLASH_AM160T & FLASH_TYPEMASK);
-
- /* set individual sector start addresses */
- for (j = 0; j < flash_info[i].sector_count; j++) {
- flash_info[i].start[j] =
- (CONFIG_SYS_FLASH_BASE + i * FLASH_BANK_SIZE +
- j * MAIN_SECT_SIZE);
-
- if (j < (CONFIG_SYS_MAX_FLASH_SECT - 3)) {
- flash_info[i].start[j] =
- (CONFIG_SYS_FLASH_BASE + i * FLASH_BANK_SIZE +
- j * MAIN_SECT_SIZE);
- } else if (j == (CONFIG_SYS_MAX_FLASH_SECT - 3)) {
- flash_info[i].start[j] =
- (flash_info[i].start[j - 1] + SECT_SIZE_32KB);
-
- } else {
- flash_info[i].start[j] =
- (flash_info[i].start[j - 1] + SECT_SIZE_8KB);
- }
- }
- }
-
- else {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- addr[0] = 0xFF;
- goto Done;
- }
-
-#if defined DEBUG_FLASH
- printf ("flash_id = 0x%08lX\n", flash_info[i].flash_id);
-#endif
-
- addr[0] = 0xFF;
-
- memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
-
- total_size += flash_info[i].size;
- }
-
- /* Protect monitor and environment sectors
- */
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- flash_protect (FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
- &flash_info[0]);
-#endif
-
-#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
- flash_protect (FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
-#endif
-
- Done:
- return total_size;
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
- static const char unk[] = "Unknown";
- const char *mfct = unk, *type = unk;
- unsigned int i;
-
- if (info->flash_id != FLASH_UNKNOWN) {
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD:
- mfct = "AMD";
- break;
- case FLASH_MAN_FUJ:
- mfct = "FUJITSU";
- break;
- case FLASH_MAN_STM:
- mfct = "STM";
- break;
- case FLASH_MAN_SST:
- mfct = "SST";
- break;
- case FLASH_MAN_BM:
- mfct = "Bright Microelectonics";
- break;
- case FLASH_MAN_INTEL:
- mfct = "Intel";
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM033C:
- type = "AM29LV033C (32 Mbit, uniform sector size)";
- break;
- case FLASH_AM160T:
- type = "AM29LV160T (16 Mbit, top boot sector)";
- break;
- case FLASH_AM040:
- type = "AM29F040B (512K * 8, uniform sector size)";
- break;
- case FLASH_AM400B:
- type = "AM29LV400B (4 Mbit, bottom boot sect)";
- break;
- case FLASH_AM400T:
- type = "AM29LV400T (4 Mbit, top boot sector)";
- break;
- case FLASH_AM800B:
- type = "AM29LV800B (8 Mbit, bottom boot sect)";
- break;
- case FLASH_AM800T:
- type = "AM29LV800T (8 Mbit, top boot sector)";
- break;
- case FLASH_AM320B:
- type = "AM29LV320B (32 Mbit, bottom boot sect)";
- break;
- case FLASH_AM320T:
- type = "AM29LV320T (32 Mbit, top boot sector)";
- break;
- case FLASH_STM800AB:
- type = "M29W800AB (8 Mbit, bottom boot sect)";
- break;
- case FLASH_SST800A:
- type = "SST39LF/VF800 (8 Mbit, uniform sector size)";
- break;
- case FLASH_SST160A:
- type = "SST39LF/VF160 (16 Mbit, uniform sector size)";
- break;
- }
- }
-
- printf ("\n Brand: %s Type: %s\n"
- " Size: %lu KB in %d Sectors\n",
- mfct, type, info->size >> 10, info->sector_count);
-
- printf (" Sector Start Addresses:");
-
- for (i = 0; i < info->sector_count; i++) {
- unsigned long size;
- unsigned int erased;
- unsigned long *flash = (unsigned long *) info->start[i];
-
- /*
- * Check if whole sector is erased
- */
- size = (i != (info->sector_count - 1)) ?
- (info->start[i + 1] - info->start[i]) >> 2 :
- (info->start[0] + info->size - info->start[i]) >> 2;
-
- for (flash = (unsigned long *) info->start[i], erased = 1;
- (flash != (unsigned long *) info->start[i] + size) && erased;
- flash++)
- erased = *flash == ~0x0UL;
-
- printf ("%s %08lX %s %s",
- (i % 5) ? "" : "\n ",
- info->start[i],
- erased ? "E" : " ", info->protect[i] ? "RO" : " ");
- }
-
- puts ("\n");
- return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
- volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]);
- int flag, prot, sect, l_sect;
- ulong start, now, last;
- unsigned char sh8b;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id == FLASH_UNKNOWN) ||
- (info->flash_id > (FLASH_MAN_STM | FLASH_AMD_COMP))) {
- printf ("Can't erase unknown flash type - aborted\n");
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Check the ROM CS */
- if ((info->start[0] >= ROM_CS1_START)
- && (info->start[0] < ROM_CS0_START))
- sh8b = 3;
- else
- sh8b = 0;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
- addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00800080;
- addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = (FLASH_WORD_SIZE *) (info->start[0] + ((info->
- start[sect] -
- info->
- start[0]) <<
- sh8b));
-
- if (info->flash_id & FLASH_MAN_SST) {
- addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
- addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00800080;
- addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
- addr[0] = (FLASH_WORD_SIZE) 0x00500050; /* block erase */
- udelay (30000); /* wait 30 ms */
- } else {
- addr[0] = (FLASH_WORD_SIZE) 0x00300030; /* sector erase */
- }
-
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- /* wait@least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer (0);
- last = start;
- addr = (FLASH_WORD_SIZE *) (info->start[0] + ((info->start[l_sect] -
- info->
- start[0]) << sh8b));
- while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) !=
- (FLASH_WORD_SIZE) 0x00800080) {
- if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- serial_putc ('.');
- last = now;
- }
- }
-
- DONE:
- /* reset to read mode */
- addr = (FLASH_WORD_SIZE *) info->start[0];
- addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
-
- printf (" done\n");
- return 0;
-}
-
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i = 0, cp = wp; i < l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
- for (; i < 4 && cnt > 0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt == 0 && i < 4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- if ((rc = write_word (info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i = 0; i < 4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word (info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i < 4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- return (write_word (info, wp, data));
-}
-
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t * info, ulong dest, ulong data)
-{
- volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) info->start[0];
- volatile FLASH_WORD_SIZE *dest2;
- volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
- ulong start;
- int flag;
- int i;
- unsigned char sh8b;
-
- /* Check the ROM CS */
- if ((info->start[0] >= ROM_CS1_START)
- && (info->start[0] < ROM_CS0_START))
- sh8b = 3;
- else
- sh8b = 0;
-
- dest2 = (FLASH_WORD_SIZE *) (((dest - info->start[0]) << sh8b) +
- info->start[0]);
-
- /* Check if Flash is (sufficiently) erased */
- if ((*dest2 & (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
- addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr2[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
- addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00A000A0;
-
- dest2[i << sh8b] = data2[i];
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((dest2[i << sh8b] & (FLASH_WORD_SIZE) 0x00800080) !=
- (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
- if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- }
-
- return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
-#if 0
-static void write_via_fpu (vu_long * addr, ulong * data)
-{
- __asm__ __volatile__ ("lfd 1, 0(%0)"::"r" (data));
- __asm__ __volatile__ ("stfd 1, 0(%0)"::"r" (addr));
-}
-#endif
-
-/*-----------------------------------------------------------------------
- */
-static __inline__ unsigned long get_msr (void)
-{
- unsigned long msr;
-
- __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
-
- return msr;
-}
-
-static __inline__ void set_msr (unsigned long msr)
-{
- __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
-}
diff --git a/board/utx8245/utx8245.c b/board/utx8245/utx8245.c
deleted file mode 100644
index 69d19e3..0000000
--- a/board/utx8245/utx8245.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/*
- * (C) Copyright 2001
- * Rob Taylor, Flying Pig Systems. robt at flyingpig.com.
- *
- * (C) Copyright 2002
- * Gregory E. Allen, gallen at arlut.utexas.edu
- * Matthew E. Karger, karger at arlut.utexas.edu
- * Applied Research Laboratories, The University of Texas at Austin
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc824x.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/mmu.h>
-#include <pci.h>
-#include <netdev.h>
-
-#define SAVE_SZ 32
-
-
-int checkboard(void)
-{
- ulong busfreq = get_bus_freq(0);
- char buf[32];
-
- printf("Board: UTX8245 Local Bus at %s MHz\n", strmhz(buf, busfreq));
- return 0;
-}
-
-
-phys_size_t initdram(int board_type)
-{
- long size;
- long new_bank0_end;
- long new_bank1_end;
- long mear1;
- long emear1;
-
- size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
-
- new_bank0_end = size/2 - 1;
- new_bank1_end = size - 1;
- mear1 = mpc824x_mpc107_getreg(MEAR1);
- emear1 = mpc824x_mpc107_getreg(EMEAR1);
-
- mear1 = (mear1 & 0xFFFF0000) |
- ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
- ((new_bank1_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT << 8);
- emear1 = (emear1 & 0xFFFF0000) |
- ((new_bank0_end & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
- ((new_bank1_end & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT << 8);
-
- mpc824x_mpc107_setreg(MEAR1, mear1);
- mpc824x_mpc107_setreg(EMEAR1, emear1);
-
- return (size);
-}
-
-
-/*
- * Initialize PCI Devices, report devices found.
- */
-
-static struct pci_config_table pci_utx8245_config_table[] = {
-#ifndef CONFIG_PCI_PNP
- { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0C, PCI_ANY_ID,
- pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
- PCI_ENET0_MEMADDR,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
- { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0B, PCI_ANY_ID,
- pci_cfgfunc_config_device, { PCI_FIREWIRE_IOADDR,
- PCI_FIREWIRE_MEMADDR,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
-#endif /*CONFIG_PCI_PNP*/
- { }
-};
-
-
-static void pci_utx8245_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
-{
- if (PCI_DEV(dev) == 11)
- /* assign serial interrupt line 9 (int25) to FireWire */
- pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 25);
-
- else if (PCI_DEV(dev) == 12)
- /* assign serial interrupt line 8 (int24) to Ethernet */
- pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 24);
-
- else if (PCI_DEV(dev) == 14)
- /* assign serial interrupt line 0 (int16) to PMC slot 0 */
- pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 16);
-
- else if (PCI_DEV(dev) == 15)
- /* assign serial interrupt line 1 (int17) to PMC slot 1 */
- pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 17);
-}
-
-static struct pci_controller utx8245_hose = {
-#ifndef CONFIG_PCI_PNP
- config_table: pci_utx8245_config_table,
- fixup_irq: pci_utx8245_fixup_irq,
- write_byte: pci_hose_write_config_byte
-#endif /*CONFIG_PCI_PNP*/
-};
-
-void pci_init_board (void)
-{
- pci_mpc824x_init(&utx8245_hose);
-
- icache_enable();
-}
-
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
diff --git a/common/cmd_pcmcia.c b/common/cmd_pcmcia.c
index ddc24be..682d18f 100644
--- a/common/cmd_pcmcia.c
+++ b/common/cmd_pcmcia.c
@@ -331,11 +331,8 @@ int check_ide_device (int slot)
ide_devices_found |= (1 << slot);
-#if CONFIG_CPC45
-#else
/* set I/O area in config reg -> only valid for ARGOSY D5!!! */
*((uchar *)(addr + config_base)) = 1;
-#endif
#if 0
printf("\n## Config_base = %04x ###\n", config_base);
printf("Configuration Option Register: %02x @ %x\n", readb(addr + config_base), addr + config_base);
diff --git a/configs/A3000_defconfig b/configs/A3000_defconfig
deleted file mode 100644
index e1923de..0000000
--- a/configs/A3000_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC824X=y
-CONFIG_TARGET_A3000=y
diff --git a/configs/CPC45_ROMBOOT_defconfig b/configs/CPC45_ROMBOOT_defconfig
deleted file mode 100644
index 4aae7f6..0000000
--- a/configs/CPC45_ROMBOOT_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="BOOT_ROM"
-CONFIG_PPC=y
-CONFIG_MPC824X=y
-CONFIG_TARGET_CPC45=y
diff --git a/configs/CPC45_defconfig b/configs/CPC45_defconfig
deleted file mode 100644
index 77ae66c..0000000
--- a/configs/CPC45_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC824X=y
-CONFIG_TARGET_CPC45=y
diff --git a/configs/CU824_defconfig b/configs/CU824_defconfig
deleted file mode 100644
index 0f22188..0000000
--- a/configs/CU824_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC824X=y
-CONFIG_TARGET_CU824=y
diff --git a/configs/MUSENKI_defconfig b/configs/MUSENKI_defconfig
deleted file mode 100644
index 586364c..0000000
--- a/configs/MUSENKI_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC824X=y
-CONFIG_TARGET_MUSENKI=y
diff --git a/configs/MVBLUE_defconfig b/configs/MVBLUE_defconfig
deleted file mode 100644
index f979983..0000000
--- a/configs/MVBLUE_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC824X=y
-CONFIG_TARGET_MVBLUE=y
diff --git a/configs/Sandpoint8240_defconfig b/configs/Sandpoint8240_defconfig
deleted file mode 100644
index 332e4c0..0000000
--- a/configs/Sandpoint8240_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC824X=y
-CONFIG_TARGET_SANDPOINT8240=y
diff --git a/configs/Sandpoint8245_defconfig b/configs/Sandpoint8245_defconfig
deleted file mode 100644
index b36757c..0000000
--- a/configs/Sandpoint8245_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC824X=y
-CONFIG_TARGET_SANDPOINT8245=y
diff --git a/configs/eXalion_defconfig b/configs/eXalion_defconfig
deleted file mode 100644
index 9d7e090..0000000
--- a/configs/eXalion_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC824X=y
-CONFIG_TARGET_EXALION=y
diff --git a/configs/utx8245_defconfig b/configs/utx8245_defconfig
deleted file mode 100644
index c2107cc..0000000
--- a/configs/utx8245_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC824X=y
-CONFIG_TARGET_UTX8245=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 5df0664..5d2875c 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,15 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+A3000 powerpc mpc824x - -
+CPC45 powerpc mpc824x - - Josef Wagner <Wagner@Microsys.de>
+CU824 powerpc mpc824x - - Wolfgang Denk <wd@denx.de>
+eXalion powerpc mpc824x - - Torsten Demke <torsten.demke@fci.com>
+MVBLUE powerpc mpc824x - -
+MUSENKI powerpc mpc824x - - Jim Thompson <jim@musenki.com>
+Sandpoint8240 powerpc mpc824x - - Wolfgang Denk <wd@denx.de>
+Sandpoint8245 powerpc mpc824x - - Jim Thompson <jim@musenki.com>
+utx8245 powerpc mpc824x - - Greg Allen <gallen@arlut.utexas.edu>
atc powerpc mpc8260 - - Wolfgang Denk <wd@denx.de>
CPU86 powerpc mpc8260 - - Wolfgang Denk <wd@denx.de>
CPU87 powerpc mpc8260 - -
diff --git a/drivers/pcmcia/Makefile b/drivers/pcmcia/Makefile
index 91821f4..c506f79 100644
--- a/drivers/pcmcia/Makefile
+++ b/drivers/pcmcia/Makefile
@@ -5,7 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_I82365) += i82365.o
obj-$(CONFIG_8xx) += mpc8xx_pcmcia.o
obj-$(CONFIG_IDE_TI_CARDBUS) += ti_pci1410a.o
obj-y += tqm8xx_pcmcia.o
diff --git a/drivers/pcmcia/i82365.c b/drivers/pcmcia/i82365.c
deleted file mode 100644
index 84a3d2e..0000000
--- a/drivers/pcmcia/i82365.c
+++ /dev/null
@@ -1,989 +0,0 @@
-/*
- * (C) Copyright 2003-2005
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- ********************************************************************
- *
- * Lots of code copied from:
- *
- * i82365.c 1.352 - Linux driver for Intel 82365 and compatible
- * PC Card controllers, and Yenta-compatible PCI-to-CardBus controllers.
- * (C) 1999 David A. Hinds <dahinds@users.sourceforge.net>
- */
-
-#include <common.h>
-
-#include <command.h>
-#include <pci.h>
-#include <pcmcia.h>
-#include <asm/io.h>
-
-#include <pcmcia/ss.h>
-#include <pcmcia/i82365.h>
-#include <pcmcia/yenta.h>
-#ifdef CONFIG_CPC45
-#include <pcmcia/cirrus.h>
-#else
-#include <pcmcia/ti113x.h>
-#endif
-
-static struct pci_device_id supported[] = {
-#ifdef CONFIG_CPC45
- {PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CIRRUS_6729},
-#else
- {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1510},
-#endif
- {0, 0}
-};
-
-#define CYCLE_TIME 120
-
-#ifdef CONFIG_CPC45
-extern int SPD67290Init (void);
-#endif
-
-#ifdef DEBUG
-static void i82365_dump_regions (pci_dev_t dev);
-#endif
-
-typedef struct socket_info_t {
- pci_dev_t dev;
- u_short bcr;
- u_char pci_lat, cb_lat, sub_bus, cache;
- u_int cb_phys;
-
- socket_cap_t cap;
- u_short type;
- u_int flags;
-#ifdef CONFIG_CPC45
- cirrus_state_t c_state;
-#else
- ti113x_state_t state;
-#endif
-} socket_info_t;
-
-#ifdef CONFIG_CPC45
-/* These definitions must match the pcic table! */
-typedef enum pcic_id {
- IS_PD6710, IS_PD672X, IS_VT83C469
-} pcic_id;
-
-typedef struct pcic_t {
- char *name;
-} pcic_t;
-
-static pcic_t pcic[] = {
- {" Cirrus PD6710: "},
- {" Cirrus PD672x: "},
- {" VIA VT83C469: "},
-};
-#endif
-
-static socket_info_t socket;
-static socket_state_t state;
-static struct pccard_mem_map mem;
-static struct pccard_io_map io;
-
-/*====================================================================*/
-
-/* Some PCI shortcuts */
-
-static int pci_readb (socket_info_t * s, int r, u_char * v)
-{
- return pci_read_config_byte (s->dev, r, v);
-}
-static int pci_writeb (socket_info_t * s, int r, u_char v)
-{
- return pci_write_config_byte (s->dev, r, v);
-}
-static int pci_readw (socket_info_t * s, int r, u_short * v)
-{
- return pci_read_config_word (s->dev, r, v);
-}
-static int pci_writew (socket_info_t * s, int r, u_short v)
-{
- return pci_write_config_word (s->dev, r, v);
-}
-#ifndef CONFIG_CPC45
-static int pci_readl (socket_info_t * s, int r, u_int * v)
-{
- return pci_read_config_dword (s->dev, r, v);
-}
-static int pci_writel (socket_info_t * s, int r, u_int v)
-{
- return pci_write_config_dword (s->dev, r, v);
-}
-#endif /* !CONFIG_CPC45 */
-
-/*====================================================================*/
-
-#ifdef CONFIG_CPC45
-
-#define cb_readb(s) readb((s)->cb_phys + 1)
-#define cb_writeb(s, v) writeb(v, (s)->cb_phys)
-#define cb_writeb2(s, v) writeb(v, (s)->cb_phys + 1)
-#define cb_readl(s, r) readl((s)->cb_phys + (r))
-#define cb_writel(s, r, v) writel(v, (s)->cb_phys + (r))
-
-
-static u_char i365_get (socket_info_t * s, u_short reg)
-{
- u_char val;
-#ifdef CONFIG_PCMCIA_SLOT_A
- int slot = 0;
-#else
- int slot = 1;
-#endif
-
- val = I365_REG (slot, reg);
-
- cb_writeb (s, val);
- val = cb_readb (s);
-
- debug ("i365_get slot:%x reg: %x val: %x\n", slot, reg, val);
- return val;
-}
-
-static void i365_set (socket_info_t * s, u_short reg, u_char data)
-{
-#ifdef CONFIG_PCMCIA_SLOT_A
- int slot = 0;
-#else
- int slot = 1;
-#endif
- u_char val;
-
- val = I365_REG (slot, reg);
-
- cb_writeb (s, val);
- cb_writeb2 (s, data);
-
- debug ("i365_set slot:%x reg: %x data:%x\n", slot, reg, data);
-}
-
-#else /* ! CONFIG_CPC45 */
-
-#define cb_readb(s, r) readb((s)->cb_phys + (r))
-#define cb_readl(s, r) readl((s)->cb_phys + (r))
-#define cb_writeb(s, r, v) writeb(v, (s)->cb_phys + (r))
-#define cb_writel(s, r, v) writel(v, (s)->cb_phys + (r))
-
-static u_char i365_get (socket_info_t * s, u_short reg)
-{
- return cb_readb (s, 0x0800 + reg);
-}
-
-static void i365_set (socket_info_t * s, u_short reg, u_char data)
-{
- cb_writeb (s, 0x0800 + reg, data);
-}
-#endif /* CONFIG_CPC45 */
-
-static void i365_bset (socket_info_t * s, u_short reg, u_char mask)
-{
- i365_set (s, reg, i365_get (s, reg) | mask);
-}
-
-static void i365_bclr (socket_info_t * s, u_short reg, u_char mask)
-{
- i365_set (s, reg, i365_get (s, reg) & ~mask);
-}
-
-#if 0 /* not used */
-static void i365_bflip (socket_info_t * s, u_short reg, u_char mask, int b)
-{
- u_char d = i365_get (s, reg);
-
- i365_set (s, reg, (b) ? (d | mask) : (d & ~mask));
-}
-
-static u_short i365_get_pair (socket_info_t * s, u_short reg)
-{
- return (i365_get (s, reg) + (i365_get (s, reg + 1) << 8));
-}
-#endif /* not used */
-
-static void i365_set_pair (socket_info_t * s, u_short reg, u_short data)
-{
- i365_set (s, reg, data & 0xff);
- i365_set (s, reg + 1, data >> 8);
-}
-
-#ifdef CONFIG_CPC45
-/*======================================================================
-
- Code to save and restore global state information for Cirrus
- PD67xx controllers, and to set and report global configuration
- options.
-
-======================================================================*/
-
-#define flip(v,b,f) (v = ((f)<0) ? v : ((f) ? ((v)|(b)) : ((v)&(~b))))
-
-static void cirrus_get_state (socket_info_t * s)
-{
- int i;
- cirrus_state_t *p = &s->c_state;
-
- p->misc1 = i365_get (s, PD67_MISC_CTL_1);
- p->misc1 &= (PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA);
- p->misc2 = i365_get (s, PD67_MISC_CTL_2);
- for (i = 0; i < 6; i++)
- p->timer[i] = i365_get (s, PD67_TIME_SETUP (0) + i);
-
-}
-
-static void cirrus_set_state (socket_info_t * s)
-{
- int i;
- u_char misc;
- cirrus_state_t *p = &s->c_state;
-
- misc = i365_get (s, PD67_MISC_CTL_2);
- i365_set (s, PD67_MISC_CTL_2, p->misc2);
- if (misc & PD67_MC2_SUSPEND)
- udelay (50000);
- misc = i365_get (s, PD67_MISC_CTL_1);
- misc &= ~(PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA);
- i365_set (s, PD67_MISC_CTL_1, misc | p->misc1);
- for (i = 0; i < 6; i++)
- i365_set (s, PD67_TIME_SETUP (0) + i, p->timer[i]);
-}
-
-static u_int cirrus_set_opts (socket_info_t * s)
-{
- cirrus_state_t *p = &s->c_state;
- u_int mask = 0xffff;
- char buf[200] = {0};
-
- if (has_ring == -1)
- has_ring = 1;
- flip (p->misc2, PD67_MC2_IRQ15_RI, has_ring);
- flip (p->misc2, PD67_MC2_DYNAMIC_MODE, dynamic_mode);
-#if DEBUG
- if (p->misc2 & PD67_MC2_IRQ15_RI)
- strcat (buf, " [ring]");
- if (p->misc2 & PD67_MC2_DYNAMIC_MODE)
- strcat (buf, " [dyn mode]");
- if (p->misc1 & PD67_MC1_INPACK_ENA)
- strcat (buf, " [inpack]");
-#endif
-
- if (p->misc2 & PD67_MC2_IRQ15_RI)
- mask &= ~0x8000;
- if (has_led > 0) {
-#if DEBUG
- strcat (buf, " [led]");
-#endif
- mask &= ~0x1000;
- }
- if (has_dma > 0) {
-#if DEBUG
- strcat (buf, " [dma]");
-#endif
- mask &= ~0x0600;
- flip (p->misc2, PD67_MC2_FREQ_BYPASS, freq_bypass);
-#if DEBUG
- if (p->misc2 & PD67_MC2_FREQ_BYPASS)
- strcat (buf, " [freq bypass]");
-#endif
- }
-
- if (setup_time >= 0)
- p->timer[0] = p->timer[3] = setup_time;
- if (cmd_time > 0) {
- p->timer[1] = cmd_time;
- p->timer[4] = cmd_time * 2 + 4;
- }
- if (p->timer[1] == 0) {
- p->timer[1] = 6;
- p->timer[4] = 16;
- if (p->timer[0] == 0)
- p->timer[0] = p->timer[3] = 1;
- }
- if (recov_time >= 0)
- p->timer[2] = p->timer[5] = recov_time;
-
- debug ("i82365 Opt: %s [%d/%d/%d] [%d/%d/%d]\n",
- buf,
- p->timer[0], p->timer[1], p->timer[2],
- p->timer[3], p->timer[4], p->timer[5]);
-
- return mask;
-}
-
-#else /* !CONFIG_CPC45 */
-
-/*======================================================================
-
- Code to save and restore global state information for TI 1130 and
- TI 1131 controllers, and to set and report global configuration
- options.
-
-======================================================================*/
-
-static void ti113x_get_state (socket_info_t * s)
-{
- ti113x_state_t *p = &s->state;
-
- pci_readl (s, TI113X_SYSTEM_CONTROL, &p->sysctl);
- pci_readb (s, TI113X_CARD_CONTROL, &p->cardctl);
- pci_readb (s, TI113X_DEVICE_CONTROL, &p->devctl);
- pci_readb (s, TI1250_DIAGNOSTIC, &p->diag);
- pci_readl (s, TI12XX_IRQMUX, &p->irqmux);
-}
-
-static void ti113x_set_state (socket_info_t * s)
-{
- ti113x_state_t *p = &s->state;
-
- pci_writel (s, TI113X_SYSTEM_CONTROL, p->sysctl);
- pci_writeb (s, TI113X_CARD_CONTROL, p->cardctl);
- pci_writeb (s, TI113X_DEVICE_CONTROL, p->devctl);
- pci_writeb (s, TI1250_MULTIMEDIA_CTL, 0);
- pci_writeb (s, TI1250_DIAGNOSTIC, p->diag);
- pci_writel (s, TI12XX_IRQMUX, p->irqmux);
- i365_set_pair (s, TI113X_IO_OFFSET (0), 0);
- i365_set_pair (s, TI113X_IO_OFFSET (1), 0);
-}
-
-static u_int ti113x_set_opts (socket_info_t * s)
-{
- ti113x_state_t *p = &s->state;
- u_int mask = 0xffff;
-
- p->cardctl &= ~TI113X_CCR_ZVENABLE;
- p->cardctl |= TI113X_CCR_SPKROUTEN;
-
- return mask;
-}
-#endif /* CONFIG_CPC45 */
-
-/*======================================================================
-
- Routines to handle common CardBus options
-
-======================================================================*/
-
-/* Default settings for PCI command configuration register */
-#define CMD_DFLT (PCI_COMMAND_IO|PCI_COMMAND_MEMORY| \
- PCI_COMMAND_MASTER|PCI_COMMAND_WAIT)
-
-static void cb_get_state (socket_info_t * s)
-{
- pci_readb (s, PCI_CACHE_LINE_SIZE, &s->cache);
- pci_readb (s, PCI_LATENCY_TIMER, &s->pci_lat);
- pci_readb (s, CB_LATENCY_TIMER, &s->cb_lat);
- pci_readb (s, CB_CARDBUS_BUS, &s->cap.cardbus);
- pci_readb (s, CB_SUBORD_BUS, &s->sub_bus);
- pci_readw (s, CB_BRIDGE_CONTROL, &s->bcr);
-}
-
-static void cb_set_state (socket_info_t * s)
-{
-#ifndef CONFIG_CPC45
- pci_writel (s, CB_LEGACY_MODE_BASE, 0);
- pci_writel (s, PCI_BASE_ADDRESS_0, s->cb_phys);
-#endif
- pci_writew (s, PCI_COMMAND, CMD_DFLT);
- pci_writeb (s, PCI_CACHE_LINE_SIZE, s->cache);
- pci_writeb (s, PCI_LATENCY_TIMER, s->pci_lat);
- pci_writeb (s, CB_LATENCY_TIMER, s->cb_lat);
- pci_writeb (s, CB_CARDBUS_BUS, s->cap.cardbus);
- pci_writeb (s, CB_SUBORD_BUS, s->sub_bus);
- pci_writew (s, CB_BRIDGE_CONTROL, s->bcr);
-}
-
-static void cb_set_opts (socket_info_t * s)
-{
-#ifndef CONFIG_CPC45
- if (s->cache == 0)
- s->cache = 8;
- if (s->pci_lat == 0)
- s->pci_lat = 0xa8;
- if (s->cb_lat == 0)
- s->cb_lat = 0xb0;
-#endif
-}
-
-/*======================================================================
-
- Power control for Cardbus controllers: used both for 16-bit and
- Cardbus cards.
-
-======================================================================*/
-
-static int cb_set_power (socket_info_t * s, socket_state_t * state)
-{
- u_int reg = 0;
-
-#ifdef CONFIG_CPC45
-
- reg = I365_PWR_NORESET;
- if (state->flags & SS_PWR_AUTO)
- reg |= I365_PWR_AUTO;
- if (state->flags & SS_OUTPUT_ENA)
- reg |= I365_PWR_OUT;
- if (state->Vpp != 0) {
- if (state->Vpp == 120) {
- reg |= I365_VPP1_12V;
- puts (" 12V card found: ");
- } else if (state->Vpp == state->Vcc) {
- reg |= I365_VPP1_5V;
- } else {
- puts (" power not found: ");
- return -1;
- }
- }
- if (state->Vcc != 0) {
- reg |= I365_VCC_5V;
- if (state->Vcc == 33) {
- puts (" 3.3V card found: ");
- i365_bset (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
- } else if (state->Vcc == 50) {
- puts (" 5V card found: ");
- i365_bclr (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
- } else {
- puts (" power not found: ");
- return -1;
- }
- }
-
- if (reg != i365_get (s, I365_POWER)) {
- reg = (I365_PWR_OUT | I365_PWR_NORESET | I365_VCC_5V | I365_VPP1_5V);
- i365_set (s, I365_POWER, reg);
- }
-
-#else /* ! CONFIG_CPC45 */
-
- /* restart card voltage detection if it seems appropriate */
- if ((state->Vcc == 0) && (state->Vpp == 0) &&
- !(cb_readl (s, CB_SOCKET_STATE) & CB_SS_VSENSE))
- cb_writel (s, CB_SOCKET_FORCE, CB_SF_CVSTEST);
- switch (state->Vcc) {
- case 0:
- reg = 0;
- break;
- case 33:
- reg = CB_SC_VCC_3V;
- break;
- case 50:
- reg = CB_SC_VCC_5V;
- break;
- default:
- return -1;
- }
- switch (state->Vpp) {
- case 0:
- break;
- case 33:
- reg |= CB_SC_VPP_3V;
- break;
- case 50:
- reg |= CB_SC_VPP_5V;
- break;
- case 120:
- reg |= CB_SC_VPP_12V;
- break;
- default:
- return -1;
- }
- if (reg != cb_readl (s, CB_SOCKET_CONTROL))
- cb_writel (s, CB_SOCKET_CONTROL, reg);
-#endif /* CONFIG_CPC45 */
- return 0;
-}
-
-/*======================================================================
-
- Generic routines to get and set controller options
-
-======================================================================*/
-
-static void get_bridge_state (socket_info_t * s)
-{
-#ifdef CONFIG_CPC45
- cirrus_get_state (s);
-#else
- ti113x_get_state (s);
-#endif
- cb_get_state (s);
-}
-
-static void set_bridge_state (socket_info_t * s)
-{
- cb_set_state (s);
- i365_set (s, I365_GBLCTL, 0x00);
- i365_set (s, I365_GENCTL, 0x00);
-#ifdef CONFIG_CPC45
- cirrus_set_state (s);
-#else
- ti113x_set_state (s);
-#endif
-}
-
-static void set_bridge_opts (socket_info_t * s)
-{
-#ifdef CONFIG_CPC45
- cirrus_set_opts (s);
-#else
- ti113x_set_opts (s);
-#endif
- cb_set_opts (s);
-}
-
-/*====================================================================*/
-#define PD67_EXT_INDEX 0x2e /* Extension index */
-#define PD67_EXT_DATA 0x2f /* Extension data */
-#define PD67_EXD_VS1(s) (0x01 << ((s)<<1))
-
-#define pd67_ext_get(s, r) \
- (i365_set(s, PD67_EXT_INDEX, r), i365_get(s, PD67_EXT_DATA))
-
-static int i365_get_status (socket_info_t * s, u_int * value)
-{
- u_int status;
-#ifdef CONFIG_CPC45
- u_char val;
- u_char power, vcc, vpp;
- u_int powerstate;
-#endif
-
- status = i365_get (s, I365_IDENT);
- status = i365_get (s, I365_STATUS);
- *value = ((status & I365_CS_DETECT) == I365_CS_DETECT) ? SS_DETECT : 0;
- if (i365_get (s, I365_INTCTL) & I365_PC_IOCARD) {
- *value |= (status & I365_CS_STSCHG) ? 0 : SS_STSCHG;
- } else {
- *value |= (status & I365_CS_BVD1) ? 0 : SS_BATDEAD;
- *value |= (status & I365_CS_BVD2) ? 0 : SS_BATWARN;
- }
- *value |= (status & I365_CS_WRPROT) ? SS_WRPROT : 0;
- *value |= (status & I365_CS_READY) ? SS_READY : 0;
- *value |= (status & I365_CS_POWERON) ? SS_POWERON : 0;
-
-#ifdef CONFIG_CPC45
- /* Check for Cirrus CL-PD67xx chips */
- i365_set (s, PD67_CHIP_INFO, 0);
- val = i365_get (s, PD67_CHIP_INFO);
- s->type = -1;
- if ((val & PD67_INFO_CHIP_ID) == PD67_INFO_CHIP_ID) {
- val = i365_get (s, PD67_CHIP_INFO);
- if ((val & PD67_INFO_CHIP_ID) == 0) {
- s->type = (val & PD67_INFO_SLOTS) ? IS_PD672X : IS_PD6710;
- i365_set (s, PD67_EXT_INDEX, 0xe5);
- if (i365_get (s, PD67_EXT_INDEX) != 0xe5)
- s->type = IS_VT83C469;
- }
- } else {
- printf ("no Cirrus Chip found\n");
- *value = 0;
- return -1;
- }
-
- power = i365_get (s, I365_POWER);
- state.flags |= (power & I365_PWR_AUTO) ? SS_PWR_AUTO : 0;
- state.flags |= (power & I365_PWR_OUT) ? SS_OUTPUT_ENA : 0;
- vcc = power & I365_VCC_MASK;
- vpp = power & I365_VPP1_MASK;
- state.Vcc = state.Vpp = 0;
- if((vcc== 0) || (vpp == 0)) {
- /*
- * On the Cirrus we get the info which card voltage
- * we have in EXTERN DATA and write it to MISC_CTL1
- */
- powerstate = pd67_ext_get(s, PD67_EXTERN_DATA);
- if (powerstate & PD67_EXD_VS1(0)) {
- /* 5V Card */
- i365_bclr (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
- } else {
- /* 3.3V Card */
- i365_bset (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
- }
- i365_set (s, I365_POWER, (I365_PWR_OUT | I365_PWR_NORESET | I365_VCC_5V | I365_VPP1_5V));
- power = i365_get (s, I365_POWER);
- }
- if (power & I365_VCC_5V) {
- state.Vcc = (i365_get(s, PD67_MISC_CTL_1) & PD67_MC1_VCC_3V) ? 33 : 50;
- }
-
- if (power == I365_VPP1_12V)
- state.Vpp = 120;
-
- /* IO card, RESET flags, IO interrupt */
- power = i365_get (s, I365_INTCTL);
- state.flags |= (power & I365_PC_RESET) ? 0 : SS_RESET;
- if (power & I365_PC_IOCARD)
- state.flags |= SS_IOCARD;
- state.io_irq = power & I365_IRQ_MASK;
-
- /* Card status change mask */
- power = i365_get (s, I365_CSCINT);
- state.csc_mask = (power & I365_CSC_DETECT) ? SS_DETECT : 0;
- if (state.flags & SS_IOCARD)
- state.csc_mask |= (power & I365_CSC_STSCHG) ? SS_STSCHG : 0;
- else {
- state.csc_mask |= (power & I365_CSC_BVD1) ? SS_BATDEAD : 0;
- state.csc_mask |= (power & I365_CSC_BVD2) ? SS_BATWARN : 0;
- state.csc_mask |= (power & I365_CSC_READY) ? SS_READY : 0;
- }
- debug ("i82365: GetStatus(0) = flags %#3.3x, Vcc %d, Vpp %d, "
- "io_irq %d, csc_mask %#2.2x\n", state.flags,
- state.Vcc, state.Vpp, state.io_irq, state.csc_mask);
-
-#else /* !CONFIG_CPC45 */
-
- status = cb_readl (s, CB_SOCKET_STATE);
- *value |= (status & CB_SS_32BIT) ? SS_CARDBUS : 0;
- *value |= (status & CB_SS_3VCARD) ? SS_3VCARD : 0;
- *value |= (status & CB_SS_XVCARD) ? SS_XVCARD : 0;
- *value |= (status & CB_SS_VSENSE) ? 0 : SS_PENDING;
- /* For now, ignore cards with unsupported voltage keys */
- if (*value & SS_XVCARD)
- *value &= ~(SS_DETECT | SS_3VCARD | SS_XVCARD);
-#endif /* CONFIG_CPC45 */
- return 0;
-} /* i365_get_status */
-
-static int i365_set_socket (socket_info_t * s, socket_state_t * state)
-{
- u_char reg;
-
- set_bridge_state (s);
-
- /* IO card, RESET flag */
- reg = 0;
- reg |= (state->flags & SS_RESET) ? 0 : I365_PC_RESET;
- reg |= (state->flags & SS_IOCARD) ? I365_PC_IOCARD : 0;
- i365_set (s, I365_INTCTL, reg);
-
-#ifdef CONFIG_CPC45
- cb_set_power (s, state);
-
-#if 0
- /* Card status change interrupt mask */
- reg = s->cs_irq << 4;
- if (state->csc_mask & SS_DETECT)
- reg |= I365_CSC_DETECT;
- if (state->flags & SS_IOCARD) {
- if (state->csc_mask & SS_STSCHG)
- reg |= I365_CSC_STSCHG;
- } else {
- if (state->csc_mask & SS_BATDEAD)
- reg |= I365_CSC_BVD1;
- if (state->csc_mask & SS_BATWARN)
- reg |= I365_CSC_BVD2;
- if (state->csc_mask & SS_READY)
- reg |= I365_CSC_READY;
- }
- i365_set (s, I365_CSCINT, reg);
- i365_get (s, I365_CSC);
-#endif /* 0 */
-
-#else /* !CONFIG_CPC45 */
-
- reg = I365_PWR_NORESET;
- if (state->flags & SS_PWR_AUTO)
- reg |= I365_PWR_AUTO;
- if (state->flags & SS_OUTPUT_ENA)
- reg |= I365_PWR_OUT;
-
- cb_set_power (s, state);
- reg |= i365_get (s, I365_POWER) & (I365_VCC_MASK | I365_VPP1_MASK);
-
- if (reg != i365_get (s, I365_POWER))
- i365_set (s, I365_POWER, reg);
-#endif /* CONFIG_CPC45 */
-
- return 0;
-} /* i365_set_socket */
-
-/*====================================================================*/
-
-static int i365_set_mem_map (socket_info_t * s, struct pccard_mem_map *mem)
-{
- u_short base, i;
- u_char map;
-
- debug ("i82365: SetMemMap(%d, %#2.2x, %d ns, %#5.5lx-%#5.5lx, %#5.5x)\n",
- mem->map, mem->flags, mem->speed,
- mem->sys_start, mem->sys_stop, mem->card_start);
-
- map = mem->map;
- if ((map > 4) ||
- (mem->card_start > 0x3ffffff) ||
- (mem->sys_start > mem->sys_stop) ||
- (mem->speed > 1000)) {
- return -1;
- }
-
- /* Turn off the window before changing anything */
- if (i365_get (s, I365_ADDRWIN) & I365_ENA_MEM (map))
- i365_bclr (s, I365_ADDRWIN, I365_ENA_MEM (map));
-
- /* Take care of high byte, for PCI controllers */
- i365_set (s, CB_MEM_PAGE (map), mem->sys_start >> 24);
-
- base = I365_MEM (map);
- i = (mem->sys_start >> 12) & 0x0fff;
- if (mem->flags & MAP_16BIT)
- i |= I365_MEM_16BIT;
- if (mem->flags & MAP_0WS)
- i |= I365_MEM_0WS;
- i365_set_pair (s, base + I365_W_START, i);
-
- i = (mem->sys_stop >> 12) & 0x0fff;
- switch (mem->speed / CYCLE_TIME) {
- case 0:
- break;
- case 1:
- i |= I365_MEM_WS0;
- break;
- case 2:
- i |= I365_MEM_WS1;
- break;
- default:
- i |= I365_MEM_WS1 | I365_MEM_WS0;
- break;
- }
- i365_set_pair (s, base + I365_W_STOP, i);
-
-#ifdef CONFIG_CPC45
- i = 0;
-#else
- i = ((mem->card_start - mem->sys_start) >> 12) & 0x3fff;
-#endif
- if (mem->flags & MAP_WRPROT)
- i |= I365_MEM_WRPROT;
- if (mem->flags & MAP_ATTRIB)
- i |= I365_MEM_REG;
- i365_set_pair (s, base + I365_W_OFF, i);
-
-#ifdef CONFIG_CPC45
- /* set System Memory map Upper Adress */
- i365_set(s, PD67_EXT_INDEX, PD67_MEM_PAGE(map));
- i365_set(s, PD67_EXT_DATA, ((mem->sys_start >> 24) & 0xff));
-#endif
-
- /* Turn on the window if necessary */
- if (mem->flags & MAP_ACTIVE)
- i365_bset (s, I365_ADDRWIN, I365_ENA_MEM (map));
- return 0;
-} /* i365_set_mem_map */
-
-static int i365_set_io_map (socket_info_t * s, struct pccard_io_map *io)
-{
- u_char map, ioctl;
-
- map = io->map;
- /* comment out: comparison is always false due to limited range of data type */
- if ((map > 1) || /* (io->start > 0xffff) || (io->stop > 0xffff) || */
- (io->stop < io->start))
- return -1;
- /* Turn off the window before changing anything */
- if (i365_get (s, I365_ADDRWIN) & I365_ENA_IO (map))
- i365_bclr (s, I365_ADDRWIN, I365_ENA_IO (map));
- i365_set_pair (s, I365_IO (map) + I365_W_START, io->start);
- i365_set_pair (s, I365_IO (map) + I365_W_STOP, io->stop);
- ioctl = i365_get (s, I365_IOCTL) & ~I365_IOCTL_MASK (map);
- if (io->speed)
- ioctl |= I365_IOCTL_WAIT (map);
- if (io->flags & MAP_0WS)
- ioctl |= I365_IOCTL_0WS (map);
- if (io->flags & MAP_16BIT)
- ioctl |= I365_IOCTL_16BIT (map);
- if (io->flags & MAP_AUTOSZ)
- ioctl |= I365_IOCTL_IOCS16 (map);
- i365_set (s, I365_IOCTL, ioctl);
- /* Turn on the window if necessary */
- if (io->flags & MAP_ACTIVE)
- i365_bset (s, I365_ADDRWIN, I365_ENA_IO (map));
- return 0;
-} /* i365_set_io_map */
-
-/*====================================================================*/
-
-int i82365_init (void)
-{
- u_int val;
- int i;
-
-#ifdef CONFIG_CPC45
- if (SPD67290Init () != 0)
- return 1;
-#endif
- if ((socket.dev = pci_find_devices (supported, 0)) < 0) {
- /* Controller not found */
- return 1;
- }
- debug ("i82365 Device Found!\n");
-
- pci_read_config_dword (socket.dev, PCI_BASE_ADDRESS_0, &socket.cb_phys);
- socket.cb_phys &= ~0xf;
-
-#ifdef CONFIG_CPC45
- /* + 0xfe000000 see MPC 8245 Users Manual Adress Map B */
- socket.cb_phys += 0xfe000000;
-#endif
-
- get_bridge_state (&socket);
- set_bridge_opts (&socket);
-
- i = i365_get_status (&socket, &val);
-
-#ifdef CONFIG_CPC45
- if (i > -1) {
- puts (pcic[socket.type].name);
- } else {
- printf ("i82365: Controller not found.\n");
- return 1;
- }
- if((val & SS_DETECT) != SS_DETECT){
- puts ("No card\n");
- return 1;
- }
-#else /* !CONFIG_CPC45 */
- if (val & SS_DETECT) {
- if (val & SS_3VCARD) {
- state.Vcc = state.Vpp = 33;
- puts (" 3.3V card found: ");
- } else if (!(val & SS_XVCARD)) {
- state.Vcc = state.Vpp = 50;
- puts (" 5.0V card found: ");
- } else {
- puts ("i82365: unsupported voltage key\n");
- state.Vcc = state.Vpp = 0;
- }
- } else {
- /* No card inserted */
- puts ("No card\n");
- return 1;
- }
-#endif /* CONFIG_CPC45 */
-
-#ifdef CONFIG_CPC45
- state.flags |= SS_OUTPUT_ENA;
-#else
- state.flags = SS_IOCARD | SS_OUTPUT_ENA;
- state.csc_mask = 0;
- state.io_irq = 0;
-#endif
-
- i365_set_socket (&socket, &state);
-
- for (i = 500; i; i--) {
- if ((i365_get (&socket, I365_STATUS) & I365_CS_READY))
- break;
- udelay (1000);
- }
-
- if (i == 0) {
- /* PC Card not ready for data transfer */
- puts ("i82365 PC Card not ready for data transfer\n");
- return 1;
- }
- debug (" PC Card ready for data transfer: ");
-
- mem.map = 0;
- mem.flags = MAP_ATTRIB | MAP_ACTIVE;
- mem.speed = 300;
- mem.sys_start = CONFIG_SYS_PCMCIA_MEM_ADDR;
- mem.sys_stop = CONFIG_SYS_PCMCIA_MEM_ADDR + CONFIG_SYS_PCMCIA_MEM_SIZE - 1;
- mem.card_start = 0;
- i365_set_mem_map (&socket, &mem);
-
-#ifdef CONFIG_CPC45
- mem.map = 1;
- mem.flags = MAP_ACTIVE;
- mem.speed = 300;
- mem.sys_start = CONFIG_SYS_PCMCIA_MEM_ADDR + CONFIG_SYS_PCMCIA_MEM_SIZE;
- mem.sys_stop = CONFIG_SYS_PCMCIA_MEM_ADDR + (2 * CONFIG_SYS_PCMCIA_MEM_SIZE) - 1;
- mem.card_start = 0;
- i365_set_mem_map (&socket, &mem);
-
-#else /* !CONFIG_CPC45 */
-
- io.map = 0;
- io.flags = MAP_AUTOSZ | MAP_ACTIVE;
- io.speed = 0;
- io.start = 0x0100;
- io.stop = 0x010F;
- i365_set_io_map (&socket, &io);
-
-#endif /* CONFIG_CPC45 */
-
-#ifdef DEBUG
- i82365_dump_regions (socket.dev);
-#endif
-
- return 0;
-}
-
-void i82365_exit (void)
-{
- io.map = 0;
- io.flags = 0;
- io.speed = 0;
- io.start = 0;
- io.stop = 0x1;
-
- i365_set_io_map (&socket, &io);
-
- mem.map = 0;
- mem.flags = 0;
- mem.speed = 0;
- mem.sys_start = 0;
- mem.sys_stop = 0x1000;
- mem.card_start = 0;
-
- i365_set_mem_map (&socket, &mem);
-
-#ifdef CONFIG_CPC45
- mem.map = 1;
- mem.flags = 0;
- mem.speed = 0;
- mem.sys_start = 0;
- mem.sys_stop = 0x1000;
- mem.card_start = 0;
-
- i365_set_mem_map (&socket, &mem);
-#else /* !CONFIG_CPC45 */
- socket.state.sysctl &= 0xFFFF00FF;
-#endif
- state.Vcc = state.Vpp = 0;
-
- i365_set_socket (&socket, &state);
-}
-
-/*======================================================================
-
- Debug stuff
-
-======================================================================*/
-
-#ifdef DEBUG
-static void i82365_dump_regions (pci_dev_t dev)
-{
- u_int tmp[2];
- u_int *mem = (void *) socket.cb_phys;
- u_char *cis = (void *) CONFIG_SYS_PCMCIA_MEM_ADDR;
- u_char *ide = (void *) (CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_REG_OFFSET);
-
- pci_read_config_dword (dev, 0x00, tmp + 0);
- pci_read_config_dword (dev, 0x80, tmp + 1);
-
- printf ("PCI CONF: %08X ... %08X\n",
- tmp[0], tmp[1]);
- printf ("PCI MEM: ... %08X ... %08X\n",
- mem[0x8 / 4], mem[0x800 / 4]);
- printf ("CIS: ...%c%c%c%c%c%c%c%c...\n",
- cis[0x38], cis[0x3a], cis[0x3c], cis[0x3e],
- cis[0x40], cis[0x42], cis[0x44], cis[0x48]);
- printf ("CIS CONF: %02X %02X %02X ...\n",
- cis[0x200], cis[0x202], cis[0x204]);
- printf ("IDE: %02X %02X %02X %02X %02X %02X %02X %02X\n",
- ide[0], ide[1], ide[2], ide[3],
- ide[4], ide[5], ide[6], ide[7]);
-}
-#endif /* DEBUG */
diff --git a/include/configs/A3000.h b/include/configs/A3000.h
deleted file mode 100644
index 35e3e6f..0000000
--- a/include/configs/A3000.h
+++ /dev/null
@@ -1,293 +0,0 @@
-/*
- * (C) Copyright 2001, 2002, 2003
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* ------------------------------------------------------------------------- */
-/*
- * Configuration settings for the A-3000 board (Artis Microsystems Inc.).
- * http://artismicro.com
- */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC8245 1
-#define CONFIG_A3000 1
-
-#define CONFIG_SYS_TEXT_BASE 0xFFF00000
-
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 9600
-
-#define CONFIG_BOOTDELAY 5
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-
-/*
- * Miscellaneous configurable options
- */
-#undef CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "A3000> " /* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-
-/* Print Buffer Size
- */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 8 /* Max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR 0x00400000 /* Default load address */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_HARD_I2C 1 /* To enable I2C support */
-#undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#undef CONFIG_PCI_PNP
-#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
-
-
-/* #define CONFIG_TULIP */
-/* #define CONFIG_EEPRO100 */
-#define CONFIG_NATSEMI
-
-#define PCI_ENET0_IOADDR 0x80000000
-#define PCI_ENET0_MEMADDR 0x80000000
-#define PCI_ENET1_IOADDR 0x81000000
-#define PCI_ENET1_MEMADDR 0x81000000
-#define PCI_ENET2_IOADDR 0x82000000
-#define PCI_ENET2_MEMADDR 0x82000000
-#define PCI_ENET3_IOADDR 0x83000000
-#define PCI_ENET3_MEMADDR 0x83000000
-
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-
-#define CONFIG_SYS_FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank on RCS#0 */
-#define CONFIG_SYS_FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank on RCS#1 */
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH_BASE0_PRELIM
-#define CONFIG_SYS_FLASH_BANKS { CONFIG_SYS_FLASH_BASE0_PRELIM }
-
-/* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the
- * reset vector is actually located at FFB00100, but the 8245
- * takes care of us.
- */
-#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
-
-#define CONFIG_SYS_EUMB_ADDR 0xFC000000
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
-
- /* Maximum amount of RAM.
- */
-#define CONFIG_SYS_MAX_RAM_SIZE 0x04000000 /* 0 .. 128 MB of (S)DRAM */
-
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
-#undef CONFIG_SYS_RAMBOOT
-#else
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-/*
- * NS16550 Configuration
- */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4600)
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area
- */
-
-/* #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- * For the detail description refer to the MPC8240 user's manual.
- */
-
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
-
- /* Bit-field values for MCCR1.
- */
-#define CONFIG_SYS_ROMNAL 7
-#define CONFIG_SYS_ROMFAL 11
-#define CONFIG_SYS_DBUS_SIZE 0x3
-
- /* Bit-field values for MCCR2.
- */
-#define CONFIG_SYS_TSWAIT 0x5 /* Transaction Start Wait States timer */
-#define CONFIG_SYS_REFINT 0x400 /* Refresh interval FIXME: was 0t430 */
-
- /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
- */
-#define CONFIG_SYS_BSTOPRE 121
-
- /* Bit-field values for MCCR3.
- */
-#define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */
-
- /* Bit-field values for MCCR4.
- */
-#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval FIXME: was 2 */
-#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval FIXME: was 5 */
-#define CONFIG_SYS_ACTORW 3 /* FIXME was 2 */
-#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */
-#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
-#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
-#define CONFIG_SYS_EXTROM 1
-#define CONFIG_SYS_REGDIMM 0
-
-#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/
-
-#define CONFIG_SYS_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */
-
-/* Memory bank settings.
- * Only bits 20-29 are actually used from these vales to set the
- * start/end addresses. The upper two bits will always be 0, and the lower
- * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
- * address. Refer to the MPC8240 book.
- */
-
-#define CONFIG_SYS_BANK0_START 0x00000000
-#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
-#define CONFIG_SYS_BANK0_ENABLE 1
-#define CONFIG_SYS_BANK1_START 0x3ff00000
-#define CONFIG_SYS_BANK1_END 0x3fffffff
-#define CONFIG_SYS_BANK1_ENABLE 0
-#define CONFIG_SYS_BANK2_START 0x3ff00000
-#define CONFIG_SYS_BANK2_END 0x3fffffff
-#define CONFIG_SYS_BANK2_ENABLE 0
-#define CONFIG_SYS_BANK3_START 0x3ff00000
-#define CONFIG_SYS_BANK3_END 0x3fffffff
-#define CONFIG_SYS_BANK3_ENABLE 0
-#define CONFIG_SYS_BANK4_START 0x3ff00000
-#define CONFIG_SYS_BANK4_END 0x3fffffff
-#define CONFIG_SYS_BANK4_ENABLE 0
-#define CONFIG_SYS_BANK5_START 0x3ff00000
-#define CONFIG_SYS_BANK5_END 0x3fffffff
-#define CONFIG_SYS_BANK5_ENABLE 0
-#define CONFIG_SYS_BANK6_START 0x3ff00000
-#define CONFIG_SYS_BANK6_END 0x3fffffff
-#define CONFIG_SYS_BANK6_ENABLE 0
-#define CONFIG_SYS_BANK7_START 0x3ff00000
-#define CONFIG_SYS_BANK7_END 0x3fffffff
-#define CONFIG_SYS_BANK7_ENABLE 0
-
-#define CONFIG_SYS_ODCR 0xff
-
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max number of sectors per flash */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-
- /* Warining: environment is not EMBEDDED in the U-Boot code.
- * It's stored in flash separately.
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR 0xFFFE0000
-#define CONFIG_ENV_SIZE 0x00020000 /* Size of the Environment */
-#define CONFIG_ENV_SECT_SIZE 0x00020000 /* Size of the Environment Sector */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 32
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/CPC45.h b/include/configs/CPC45.h
deleted file mode 100644
index a75c52f..0000000
--- a/include/configs/CPC45.h
+++ /dev/null
@@ -1,489 +0,0 @@
-/*
- * (C) Copyright 2001-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- *
- * Configuration settings for the CPC45 board.
- *
- */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC8245 1
-#define CONFIG_CPC45 1
-
-#define CONFIG_SYS_TEXT_BASE 0xFFF00000
-
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 9600
-
-#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
-
-#define CONFIG_BOOTDELAY 5
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BEDBUG
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_SNTP
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-
-#if 1
-#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
-#endif
-
-/* Print Buffer Size
- */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-
-#if defined(CONFIG_BOOT_ROM)
-#define CONFIG_SYS_FLASH_BASE 0xFF000000
-#else
-#define CONFIG_SYS_FLASH_BASE 0xFF800000
-#endif
-
-#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
-
-#define CONFIG_SYS_EUMB_ADDR 0xFCE00000
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
-
-/* Maximum amount of RAM.
- */
-#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000
-
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
-#undef CONFIG_SYS_RAMBOOT
-#else
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area
- */
-
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-/*
- * NS16550 Configuration
- */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4600)
-#define DUART_DCR (CONFIG_SYS_EUMB_ADDR + 0x4511)
-
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-
-#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-/*
- * RTC configuration
- */
-#define CONFIG_RTC_PCF8563
-#define CONFIG_SYS_I2C_RTC_ADDR 0x51
-
-/*
- * EEPROM configuration
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- * For the detail description refer to the MPC8240 user's manual.
- */
-
-#define CONFIG_SYS_CLK_FREQ 33000000
-
-
-/* Bit-field values for MCCR1.
- */
-#define CONFIG_SYS_ROMNAL 0
-#define CONFIG_SYS_ROMFAL 8
-
-#define CONFIG_SYS_BANK0_ROW 0 /* SDRAM bank 7-0 row address */
-#define CONFIG_SYS_BANK1_ROW 0
-#define CONFIG_SYS_BANK2_ROW 0
-#define CONFIG_SYS_BANK3_ROW 0
-#define CONFIG_SYS_BANK4_ROW 0
-#define CONFIG_SYS_BANK5_ROW 0
-#define CONFIG_SYS_BANK6_ROW 0
-#define CONFIG_SYS_BANK7_ROW 0
-
-/* Bit-field values for MCCR2.
- */
-
-#define CONFIG_SYS_REFINT 0x2ec
-
-/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
- */
-#define CONFIG_SYS_BSTOPRE 160
-
-/* Bit-field values for MCCR3.
- */
-#define CONFIG_SYS_REFREC 2 /* Refresh to activate interval */
-#define CONFIG_SYS_RDLAT 0 /* Data latancy from read command */
-
-/* Bit-field values for MCCR4.
- */
-#define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval */
-#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
-#define CONFIG_SYS_SDMODE_CAS_LAT 2 /* SDMODE CAS latancy */
-#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
-#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length */
-#define CONFIG_SYS_ACTORW 2
-#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
-#define CONFIG_SYS_EXTROM 0
-#define CONFIG_SYS_REGDIMM 0
-
-/* Memory bank settings.
- * Only bits 20-29 are actually used from these vales to set the
- * start/end addresses. The upper two bits will always be 0, and the lower
- * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
- * address. Refer to the MPC8240 book.
- */
-
-#define CONFIG_SYS_BANK0_START 0x00000000
-#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
-#define CONFIG_SYS_BANK0_ENABLE 1
-#define CONFIG_SYS_BANK1_START 0x3ff00000
-#define CONFIG_SYS_BANK1_END 0x3fffffff
-#define CONFIG_SYS_BANK1_ENABLE 0
-#define CONFIG_SYS_BANK2_START 0x3ff00000
-#define CONFIG_SYS_BANK2_END 0x3fffffff
-#define CONFIG_SYS_BANK2_ENABLE 0
-#define CONFIG_SYS_BANK3_START 0x3ff00000
-#define CONFIG_SYS_BANK3_END 0x3fffffff
-#define CONFIG_SYS_BANK3_ENABLE 0
-#define CONFIG_SYS_BANK4_START 0x3ff00000
-#define CONFIG_SYS_BANK4_END 0x3fffffff
-#define CONFIG_SYS_BANK4_ENABLE 0
-#define CONFIG_SYS_BANK5_START 0x3ff00000
-#define CONFIG_SYS_BANK5_END 0x3fffffff
-#define CONFIG_SYS_BANK5_ENABLE 0
-#define CONFIG_SYS_BANK6_START 0x3ff00000
-#define CONFIG_SYS_BANK6_END 0x3fffffff
-#define CONFIG_SYS_BANK6_ENABLE 0
-#define CONFIG_SYS_BANK7_START 0x3ff00000
-#define CONFIG_SYS_BANK7_END 0x3fffffff
-#define CONFIG_SYS_BANK7_ENABLE 0
-
-#define CONFIG_SYS_ODCR 0xff
-#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */
- /* currently accessed page in memory */
- /* see 8240 book for details */
-
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT3L (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT3U (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 39 /* Max number of sectors in one bank */
-#define INTEL_ID_28F160F3T 0x88F388F3 /* 16M = 1M x 16 top boot sector */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
- /* Warining: environment is not EMBEDDED in the ppcboot code.
- * It's stored in flash separately.
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x7F8000)
-#define CONFIG_ENV_SIZE 0x4000 /* Size of the Environment */
-#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */
-#define CONFIG_ENV_SECT_SIZE 0x8000 /* Size of the Environment Sector */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 32
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*----------------------------------------------------------------------*/
-/* CPC45 Memory Map */
-/*----------------------------------------------------------------------*/
-#define SRAM_BASE 0x80000000 /* SRAM base address */
-#define SRAM_END 0x801FFFFF
-#define ST16552_A_BASE 0x80200000 /* ST16552 channel A */
-#define ST16552_B_BASE 0x80400000 /* ST16552 channel A */
-#define BCSR_BASE 0x80600000 /* board control / status registers */
-#define DISPLAY_BASE 0x80600040 /* DISPLAY base */
-#define PCMCIA_MEM_BASE 0x83000000 /* PCMCIA memory window base */
-#define PCMCIA_IO_BASE 0xFE000000 /* PCMCIA IO window base */
-
-#define CONFIG_SYS_SRAM_BASE SRAM_BASE
-#define CONFIG_SYS_SRAM_SIZE (SRAM_END - SRAM_BASE + 1)
-
-/*---------------------------------------------------------------------*/
-/* CPC45 Control/Status Registers */
-/*---------------------------------------------------------------------*/
-#define IRQ_ENA_1 *((volatile uchar*)(BCSR_BASE + 0x00))
-#define IRQ_STAT_1 *((volatile uchar*)(BCSR_BASE + 0x01))
-#define IRQ_ENA_2 *((volatile uchar*)(BCSR_BASE + 0x02))
-#define IRQ_STAT_2 *((volatile uchar*)(BCSR_BASE + 0x03))
-#define BOARD_CTRL *((volatile uchar*)(BCSR_BASE + 0x04))
-#define BOARD_STAT *((volatile uchar*)(BCSR_BASE + 0x05))
-#define WDG_START *((volatile uchar*)(BCSR_BASE + 0x06))
-#define WDG_PRESTOP *((volatile uchar*)(BCSR_BASE + 0x06))
-#define WDG_STOP *((volatile uchar*)(BCSR_BASE + 0x06))
-#define BOARD_REV *((volatile uchar*)(BCSR_BASE + 0x07))
-
-/* IRQ_ENA_1 bit definitions */
-#define I_ENA_1_IERA 0x80 /* INTA enable */
-#define I_ENA_1_IERB 0x40 /* INTB enable */
-#define I_ENA_1_IERC 0x20 /* INTC enable */
-#define I_ENA_1_IERD 0x10 /* INTD enable */
-
-/* IRQ_STAT_1 bit definitions */
-#define I_STAT_1_INTA 0x80 /* INTA status */
-#define I_STAT_1_INTB 0x40 /* INTB status */
-#define I_STAT_1_INTC 0x20 /* INTC status */
-#define I_STAT_1_INTD 0x10 /* INTD status */
-
-/* IRQ_ENA_2 bit definitions */
-#define I_ENA_2_IEAB 0x80 /* ABORT IRQ enable */
-#define I_ENA_2_IEK1 0x40 /* KEY1 IRQ enable */
-#define I_ENA_2_IEK2 0x20 /* KEY2 IRQ enable */
-#define I_ENA_2_IERT 0x10 /* RTC IRQ enable */
-#define I_ENA_2_IESM 0x08 /* LM81 IRQ enable */
-#define I_ENA_2_IEDG 0x04 /* DEGENERATING IRQ enable */
-#define I_ENA_2_IES2 0x02 /* ST16552/B IRQ enable */
-#define I_ENA_2_IES1 0x01 /* ST16552/A IRQ enable */
-
-/* IRQ_STAT_2 bit definitions */
-#define I_STAT_2_ABO 0x80 /* ABORT IRQ status */
-#define I_STAT_2_KY1 0x40 /* KEY1 IRQ status */
-#define I_STAT_2_KY2 0x20 /* KEY2 IRQ status */
-#define I_STAT_2_RTC 0x10 /* RTC IRQ status */
-#define I_STAT_2_SMN 0x08 /* LM81 IRQ status */
-#define I_STAT_2_DEG 0x04 /* DEGENERATING IRQ status */
-#define I_STAT_2_SIO2 0x02 /* ST16552/B IRQ status */
-#define I_STAT_2_SIO1 0x01 /* ST16552/A IRQ status */
-
-/* BOARD_CTRL bit definitions */
-#define USER_LEDS 2 /* 2 user LEDs */
-
-#if (USER_LEDS == 4)
-#define B_CTRL_WRSE 0x80
-#define B_CTRL_KRSE 0x40
-#define B_CTRL_FWRE 0x20 /* Flash write enable */
-#define B_CTRL_FWPT 0x10 /* Flash write protect */
-#define B_CTRL_LED3 0x08 /* LED 3 control */
-#define B_CTRL_LED2 0x04 /* LED 2 control */
-#define B_CTRL_LED1 0x02 /* LED 1 control */
-#define B_CTRL_LED0 0x01 /* LED 0 control */
-#else
-#define B_CTRL_WRSE 0x80
-#define B_CTRL_KRSE 0x40
-#define B_CTRL_FWRE_1 0x20 /* Flash write enable */
-#define B_CTRL_FWPT_1 0x10 /* Flash write protect */
-#define B_CTRL_LED1 0x08 /* LED 1 control */
-#define B_CTRL_LED0 0x04 /* LED 0 control */
-#define B_CTRL_FWRE_0 0x02 /* Flash write enable */
-#define B_CTRL_FWPT_0 0x01 /* Flash write protect */
-#endif
-
-/* BOARD_STAT bit definitions */
-#define B_STAT_WDGE 0x80
-#define B_STAT_WDGS 0x40
-#define B_STAT_WRST 0x20
-#define B_STAT_KRST 0x10
-#define B_STAT_CSW3 0x08 /* sitch bit 3 status */
-#define B_STAT_CSW2 0x04 /* sitch bit 2 status */
-#define B_STAT_CSW1 0x02 /* sitch bit 1 status */
-#define B_STAT_CSW0 0x01 /* sitch bit 0 status */
-
-/*---------------------------------------------------------------------*/
-/* Display addresses */
-/*---------------------------------------------------------------------*/
-#define DISP_UDC_RAM (DISPLAY_BASE + 0x08) /* UDC RAM */
-#define DISP_CHR_RAM (DISPLAY_BASE + 0x18) /* character Ram */
-#define DISP_FLASH (DISPLAY_BASE + 0x20) /* Flash Ram */
-
-#define DISP_UDC_ADR *((volatile uchar*)(DISPLAY_BASE + 0x00)) /* UDC Address Reg. */
-#define DISP_CWORD *((volatile uchar*)(DISPLAY_BASE + 0x10)) /* Control Word Reg. */
-
-#define DISP_DIG0 *((volatile uchar*)(DISP_CHR_RAM + 0x00)) /* Digit 0 address */
-#define DISP_DIG1 *((volatile uchar*)(DISP_CHR_RAM + 0x01)) /* Digit 0 address */
-#define DISP_DIG2 *((volatile uchar*)(DISP_CHR_RAM + 0x02)) /* Digit 0 address */
-#define DISP_DIG3 *((volatile uchar*)(DISP_CHR_RAM + 0x03)) /* Digit 0 address */
-#define DISP_DIG4 *((volatile uchar*)(DISP_CHR_RAM + 0x04)) /* Digit 0 address */
-#define DISP_DIG5 *((volatile uchar*)(DISP_CHR_RAM + 0x05)) /* Digit 0 address */
-#define DISP_DIG6 *((volatile uchar*)(DISP_CHR_RAM + 0x06)) /* Digit 0 address */
-#define DISP_DIG7 *((volatile uchar*)(DISP_CHR_RAM + 0x07)) /* Digit 0 address */
-
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_SYS_EARLY_PCI_INIT
-#undef CONFIG_PCI_PNP
-#undef CONFIG_PCI_SCAN_SHOW
-
-
-#define CONFIG_EEPRO100
-#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
-
-#define PCI_ENET0_IOADDR 0x82000000
-#define PCI_ENET0_MEMADDR 0x82000000
-#define PCI_PLX9030_IOADDR 0x82100000
-#define PCI_PLX9030_MEMADDR 0x82100000
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- */
-
-#define CONFIG_I82365
-
-#define CONFIG_SYS_PCMCIA_MEM_ADDR PCMCIA_MEM_BASE
-#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x1000
-
-#define CONFIG_PCMCIA_SLOT_A
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
- *-----------------------------------------------------------------------
- */
-
-#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
-#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
-
-#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
-#undef CONFIG_IDE_RESET /* reset for IDE not supported */
-#define CONFIG_IDE_LED /* LED for IDE is supported */
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
-
-#define CONFIG_SYS_ATA_DATA_OFFSET CONFIG_SYS_PCMCIA_MEM_SIZE
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x400)
-
-#define CONFIG_DOS_PARTITION
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/CU824.h b/include/configs/CU824.h
deleted file mode 100644
index dc98a56..0000000
--- a/include/configs/CU824.h
+++ /dev/null
@@ -1,286 +0,0 @@
-/*
- * (C) Copyright 2001-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- *
- * Configuration settings for the CU824 board.
- *
- */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC8240 1
-#define CONFIG_CU824 1
-
-#define CONFIG_SYS_TEXT_BASE 0xFFF00000
-
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 9600
-
-#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
-
-#define CONFIG_BOOTCOMMAND "bootm FE020000" /* autoboot command */
-#define CONFIG_BOOTDELAY 5
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BEDBUG
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_SNTP
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-
-#if 1
-#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
-#endif
-
-/* Print Buffer Size
- */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFF000000
-
-#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
-
-#define CONFIG_SYS_EUMB_ADDR 0xFCE00000
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
-
- /* Maximum amount of RAM.
- */
-#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000
-
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
-#undef CONFIG_SYS_RAMBOOT
-#else
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area
- */
-
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-/*
- * NS16550 Configuration
- */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-
-#define CONFIG_SYS_NS16550_REG_SIZE 4
-
-#define CONFIG_SYS_NS16550_CLK (14745600 / 2)
-
-#define CONFIG_SYS_NS16550_COM1 0xFE800080
-#define CONFIG_SYS_NS16550_COM2 0xFE8000C0
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- * For the detail description refer to the MPC8240 user's manual.
- */
-
-#define CONFIG_SYS_CLK_FREQ 33000000
-
- /* Bit-field values for MCCR1.
- */
-#define CONFIG_SYS_ROMNAL 0
-#define CONFIG_SYS_ROMFAL 7
-
- /* Bit-field values for MCCR2.
- */
-#define CONFIG_SYS_REFINT 430 /* Refresh interval */
-
- /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
- */
-#define CONFIG_SYS_BSTOPRE 192
-
- /* Bit-field values for MCCR3.
- */
-#define CONFIG_SYS_REFREC 2 /* Refresh to activate interval */
-#define CONFIG_SYS_RDLAT 3 /* Data latancy from read command */
-
- /* Bit-field values for MCCR4.
- */
-#define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval */
-#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
-#define CONFIG_SYS_SDMODE_CAS_LAT 2 /* SDMODE CAS latancy */
-#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
-#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length */
-#define CONFIG_SYS_ACTORW 2
-#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
-
-/* Memory bank settings.
- * Only bits 20-29 are actually used from these vales to set the
- * start/end addresses. The upper two bits will always be 0, and the lower
- * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
- * address. Refer to the MPC8240 book.
- */
-
-#define CONFIG_SYS_BANK0_START 0x00000000
-#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
-#define CONFIG_SYS_BANK0_ENABLE 1
-#define CONFIG_SYS_BANK1_START 0x3ff00000
-#define CONFIG_SYS_BANK1_END 0x3fffffff
-#define CONFIG_SYS_BANK1_ENABLE 0
-#define CONFIG_SYS_BANK2_START 0x3ff00000
-#define CONFIG_SYS_BANK2_END 0x3fffffff
-#define CONFIG_SYS_BANK2_ENABLE 0
-#define CONFIG_SYS_BANK3_START 0x3ff00000
-#define CONFIG_SYS_BANK3_END 0x3fffffff
-#define CONFIG_SYS_BANK3_ENABLE 0
-#define CONFIG_SYS_BANK4_START 0x3ff00000
-#define CONFIG_SYS_BANK4_END 0x3fffffff
-#define CONFIG_SYS_BANK4_ENABLE 0
-#define CONFIG_SYS_BANK5_START 0x3ff00000
-#define CONFIG_SYS_BANK5_END 0x3fffffff
-#define CONFIG_SYS_BANK5_ENABLE 0
-#define CONFIG_SYS_BANK6_START 0x3ff00000
-#define CONFIG_SYS_BANK6_END 0x3fffffff
-#define CONFIG_SYS_BANK6_ENABLE 0
-#define CONFIG_SYS_BANK7_START 0x3ff00000
-#define CONFIG_SYS_BANK7_END 0x3fffffff
-#define CONFIG_SYS_BANK7_ENABLE 0
-
-#define CONFIG_SYS_ODCR 0xff
-
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT3L (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT3U (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* Max number of flash banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 39 /* Max number of sectors in one bank */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
- /* Warining: environment is not EMBEDDED in the U-Boot code.
- * It's stored in flash separately.
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#if 0
-#define CONFIG_ENV_ADDR 0xFF008000
-#define CONFIG_ENV_SIZE 0x8000 /* Size of the Environment Sector */
-#else
-#define CONFIG_ENV_ADDR 0xFFFC0000
-#define CONFIG_ENV_SIZE 0x4000 /* Size of the Environment */
-#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */
-#define CONFIG_ENV_SECT_SIZE 0x40000 /* Size of the Environment Sector */
-#endif
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 32
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#undef CONFIG_PCI_PNP
-
-
-#define CONFIG_TULIP
-#define CONFIG_TULIP_USE_IO
-
-#define CONFIG_SYS_ETH_DEV_FN 0x7800
-#define CONFIG_SYS_ETH_IOBASE 0x00104000
-
-#define CONFIG_EEPRO100
-#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
-#define PCI_ENET0_IOADDR 0x00104000
-#define PCI_ENET0_MEMADDR 0x80000000
-#endif /* __CONFIG_H */
diff --git a/include/configs/MUSENKI.h b/include/configs/MUSENKI.h
deleted file mode 100644
index c5c9290..0000000
--- a/include/configs/MUSENKI.h
+++ /dev/null
@@ -1,275 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- *
- * Configuration settings for the MUSENKI board.
- *
- */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC8245 1
-#define CONFIG_MUSENKI 1
-
-#define CONFIG_SYS_TEXT_BASE 0xFFF00000
-
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 9600
-
-#define CONFIG_BOOTDELAY 5
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-
-/*
- * Miscellaneous configurable options
- */
-#undef CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-
-/* Print Buffer Size
- */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 8 /* Max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#undef CONFIG_PCI_PNP
-
-
-#define CONFIG_TULIP
-
-#define PCI_ENET0_IOADDR 0x80000000
-#define PCI_ENET0_MEMADDR 0x80000000
-#define PCI_ENET1_IOADDR 0x81000000
-#define PCI_ENET1_MEMADDR 0x81000000
-
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-
-#define CONFIG_SYS_FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank on RCS#0 */
-#define CONFIG_SYS_FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank on RCS#1 */
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH_BASE0_PRELIM
-
-/* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the
- * reset vector is actually located at FFB00100, but the 8245
- * takes care of us.
- */
-#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
-
-#define CONFIG_SYS_EUMB_ADDR 0xFC000000
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
-
- /* Maximum amount of RAM.
- */
-#define CONFIG_SYS_MAX_RAM_SIZE 0x08000000 /* 0 .. 128 MB of (S)DRAM */
-
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
-#undef CONFIG_SYS_RAMBOOT
-#else
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-/*
- * NS16550 Configuration
- */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4600)
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area
- */
-
-/* #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- * For the detail description refer to the MPC8240 user's manual.
- */
-
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
-
- /* Bit-field values for MCCR1.
- */
-#define CONFIG_SYS_ROMNAL 7
-#define CONFIG_SYS_ROMFAL 11
-#define CONFIG_SYS_DBUS_SIZE 0x3
-
- /* Bit-field values for MCCR2.
- */
-#define CONFIG_SYS_TSWAIT 0x5 /* Transaction Start Wait States timer */
-#define CONFIG_SYS_REFINT 0x400 /* Refresh interval FIXME: was 0t430 */
-
- /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
- */
-#define CONFIG_SYS_BSTOPRE 121
-
- /* Bit-field values for MCCR3.
- */
-#define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */
-
- /* Bit-field values for MCCR4.
- */
-#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval FIXME: was 2 */
-#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval FIXME: was 5 */
-#define CONFIG_SYS_ACTORW 3 /* FIXME was 2 */
-#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */
-#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
-#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
-#define CONFIG_SYS_EXTROM 1
-#define CONFIG_SYS_REGDIMM 0
-
-#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/
-
-#define CONFIG_SYS_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */
-
-/* Memory bank settings.
- * Only bits 20-29 are actually used from these vales to set the
- * start/end addresses. The upper two bits will always be 0, and the lower
- * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
- * address. Refer to the MPC8240 book.
- */
-
-#define CONFIG_SYS_BANK0_START 0x00000000
-#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
-#define CONFIG_SYS_BANK0_ENABLE 1
-#define CONFIG_SYS_BANK1_START 0x3ff00000
-#define CONFIG_SYS_BANK1_END 0x3fffffff
-#define CONFIG_SYS_BANK1_ENABLE 0
-#define CONFIG_SYS_BANK2_START 0x3ff00000
-#define CONFIG_SYS_BANK2_END 0x3fffffff
-#define CONFIG_SYS_BANK2_ENABLE 0
-#define CONFIG_SYS_BANK3_START 0x3ff00000
-#define CONFIG_SYS_BANK3_END 0x3fffffff
-#define CONFIG_SYS_BANK3_ENABLE 0
-#define CONFIG_SYS_BANK4_START 0x3ff00000
-#define CONFIG_SYS_BANK4_END 0x3fffffff
-#define CONFIG_SYS_BANK4_ENABLE 0
-#define CONFIG_SYS_BANK5_START 0x3ff00000
-#define CONFIG_SYS_BANK5_END 0x3fffffff
-#define CONFIG_SYS_BANK5_ENABLE 0
-#define CONFIG_SYS_BANK6_START 0x3ff00000
-#define CONFIG_SYS_BANK6_END 0x3fffffff
-#define CONFIG_SYS_BANK6_ENABLE 0
-#define CONFIG_SYS_BANK7_START 0x3ff00000
-#define CONFIG_SYS_BANK7_END 0x3fffffff
-#define CONFIG_SYS_BANK7_ENABLE 0
-
-#define CONFIG_SYS_ODCR 0xff
-
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* Max number of flash banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 64 /* Max number of sectors per flash */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-
- /* Warining: environment is not EMBEDDED in the U-Boot code.
- * It's stored in flash separately.
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR 0xFFFF0000
-#define CONFIG_ENV_SIZE 0x00010000 /* Size of the Environment */
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* Size of the Environment Sector */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 32
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/MVBLUE.h b/include/configs/MVBLUE.h
deleted file mode 100644
index aa2d9c0..0000000
--- a/include/configs/MVBLUE.h
+++ /dev/null
@@ -1,325 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define MV_VERSION "v0.2.0"
-
-/* LED0 = Power , LED1 = Error , LED2-5 = error code, LED6-7=00 -->PPCBoot error */
-#define ERR_NONE 0
-#define ERR_ENV 1
-#define ERR_BOOTM_BADMAGIC 2
-#define ERR_BOOTM_BADCRC 3
-#define ERR_BOOTM_GUNZIP 4
-#define ERR_BOOTP_TIMEOUT 5
-#define ERR_DHCP 6
-#define ERR_TFTP 7
-#define ERR_NOLAN 8
-#define ERR_LANDRV 9
-
-#define CONFIG_BOARD_TYPES 1
-#define MVBLUE_BOARD_BOX 1
-#define MVBLUE_BOARD_LYNX 2
-
-#define CONFIG_SYS_TEXT_BASE 0xFFF00000
-#define CONFIG_SYS_LDSCRIPT "board/mvblue/u-boot.lds"
-
-#if 0
-#define ERR_LED(code) do { if (code) \
- *(volatile char *)(0xff000003) = ( 3 | (code<<4) ) & 0xf3; \
- else \
- *(volatile char *)(0xff000003) = ( 1 ); \
-} while(0)
-#else
-#define ERR_LED(code)
-#endif
-
-#define CONFIG_MPC8245 1
-#define CONFIG_MVBLUE 1
-
-#define CONFIG_CLOCKS_IN_MHZ 1
-
-#define CONFIG_BOARD_TYPES 1
-
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_BOOT_RETRY_TIME -1
-
-#define CONFIG_AUTOBOOT_KEYED
-#define CONFIG_AUTOBOOT_PROMPT \
- "autoboot in %d seconds (stop with 's')...\n", bootdelay
-#define CONFIG_AUTOBOOT_STOP_STR "s"
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-#define CONFIG_RESET_TO_RETRY 60
-
-
-/*
- * Command line configuration.
- */
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_BOOTD
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_IMI
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_RUN
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_NISDOMAIN
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_BOOTP_NTPSERVER
-#define CONFIG_BOOTP_TIMEOFFSET
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */
-
-#define CONFIG_BOOTCOMMAND "run nfsboot"
-#define CONFIG_BOOTARGS "root=/dev/mtdblock5 ro rootfstype=jffs2"
-
-#define CONFIG_NFSBOOTCOMMAND "bootp; run nfsargs addcons;bootm"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "console_nr=0\0" \
- "dhcp_client_id=mvBOX-XP\0" \
- "dhcp_vendor-class-identifier=mvBOX\0" \
- "adminboot=setenv bootargs root=/dev/mtdblock5 rw rootfstype=jffs2;run addcons;bootm ffc00000\0" \
- "flashboot=setenv bootargs root=/dev/mtdblock5 ro rootfstype=jffs2;run addcons;bootm ffc00000\0" \
- "safeboot=setenv bootargs root=/dev/mtdblock2 rw rootfstype=cramfs;run addcons;bootm ffc00000\0" \
- "hdboot=setenv bootargs root=/dev/hda1;run addcons;bootm ffc00000\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" \
- "addcons=setenv bootargs ${bootargs} console=ttyS${console_nr},${baudrate}N8\0" \
- "mv_version=" MV_VERSION "\0" \
- "bootretry=30\0"
-
-#define CONFIG_OVERWRITE_ETHADDR_ONCE
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-
-#define CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_PCI_PNP
-#define CONFIG_PCI_SCAN_SHOW
-
-#define CONFIG_NET_RETRY_COUNT 5
-
-#define CONFIG_TULIP
-#define CONFIG_TULIP_FIX_DAVICOM 1
-#define CONFIG_ETHADDR b6:b4:45:eb:fb:c0
-
-#define CONFIG_HW_WATCHDOG
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start@0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-
-#define CONFIG_SYS_FLASH_BASE 0xFFF00000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-
-#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
-#define CONFIG_SYS_EUMB_ADDR 0xFC000000
-
-#define CONFIG_SYS_MONITOR_LEN 0x00100000
-#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve some kB for malloc() */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00800000 /* 1M ... 8M in DRAM */
-
-/* Maximum amount of RAM. */
-#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000 /* 0 .. 256MB of (S)DRAM */
-
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
-#undef CONFIG_SYS_RAMBOOT
-#else
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_SYS_ISA_IO 0xFE000000
-
-/*
- * serial configuration
- */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4600)
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area
- */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- * For the detail description refer to the MPC8240 user's manual.
- */
-
-#define CONFIG_SYS_CLK_FREQ 33000000
-
-/* Bit-field values for MCCR1. */
-#define CONFIG_SYS_ROMNAL 7
-#define CONFIG_SYS_ROMFAL 11
-
-/* Bit-field values for MCCR2. */
-#define CONFIG_SYS_TSWAIT 0x5
-#define CONFIG_SYS_REFINT 430
-
-/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */
-#define CONFIG_SYS_BSTOPRE 121
-
-/* Bit-field values for MCCR3. */
-#define CONFIG_SYS_REFREC 8
-
-/* Bit-field values for MCCR4. */
-#define CONFIG_SYS_PRETOACT 3
-#define CONFIG_SYS_ACTTOPRE 5
-#define CONFIG_SYS_ACTORW 3
-#define CONFIG_SYS_SDMODE_CAS_LAT 3
-#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
-#define CONFIG_SYS_EXTROM 1
-#define CONFIG_SYS_REGDIMM 0
-#define CONFIG_SYS_DBUS_SIZE2 1
-#define CONFIG_SYS_SDMODE_WRAP 0
-
-#define CONFIG_SYS_PGMAX 0x32
-#define CONFIG_SYS_SDRAM_DSCD 0x20
-
-/* Memory bank settings.
- * Only bits 20-29 are actually used from these vales to set the
- * start/end addresses. The upper two bits will always be 0, and the lower
- * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
- * address. Refer to the MPC8240 book.
- */
-
-#define CONFIG_SYS_BANK0_START 0x00000000
-#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
-#define CONFIG_SYS_BANK0_ENABLE 1
-#define CONFIG_SYS_BANK1_START 0x3ff00000
-#define CONFIG_SYS_BANK1_END 0x3fffffff
-#define CONFIG_SYS_BANK1_ENABLE 0
-#define CONFIG_SYS_BANK2_START 0x3ff00000
-#define CONFIG_SYS_BANK2_END 0x3fffffff
-#define CONFIG_SYS_BANK2_ENABLE 0
-#define CONFIG_SYS_BANK3_START 0x3ff00000
-#define CONFIG_SYS_BANK3_END 0x3fffffff
-#define CONFIG_SYS_BANK3_ENABLE 0
-#define CONFIG_SYS_BANK4_START 0x3ff00000
-#define CONFIG_SYS_BANK4_END 0x3fffffff
-#define CONFIG_SYS_BANK4_ENABLE 0
-#define CONFIG_SYS_BANK5_START 0x3ff00000
-#define CONFIG_SYS_BANK5_END 0x3fffffff
-#define CONFIG_SYS_BANK5_ENABLE 0
-#define CONFIG_SYS_BANK6_START 0x3ff00000
-#define CONFIG_SYS_BANK6_END 0x3fffffff
-#define CONFIG_SYS_BANK6_ENABLE 0
-#define CONFIG_SYS_BANK7_START 0x3ff00000
-#define CONFIG_SYS_BANK7_END 0x3fffffff
-#define CONFIG_SYS_BANK7_ENABLE 0
-
-#define CONFIG_SYS_ODCR 0xff
-
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#undef CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 63 /* Max number of sectors per flash */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 12000
-#define CONFIG_SYS_FLASH_WRITE_TOUT 1000
-
-
-#define CONFIG_ENV_IS_IN_FLASH
-
-#define CONFIG_ENV_OFFSET 0x00010000
-#define CONFIG_ENV_SIZE 0x00010000
-#define CONFIG_ENV_SECT_SIZE 0x00010000
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 32
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-#endif /* __CONFIG_H */
diff --git a/include/configs/Sandpoint8240.h b/include/configs/Sandpoint8240.h
deleted file mode 100644
index 2c0cb89..0000000
--- a/include/configs/Sandpoint8240.h
+++ /dev/null
@@ -1,398 +0,0 @@
-/*
- * (C) Copyright 2001-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC8240 1
-#define CONFIG_SANDPOINT 1
-
-#define CONFIG_SYS_TEXT_BASE 0xFFF00000
-#define CONFIG_SYS_LDSCRIPT "board/sandpoint/u-boot.lds"
-
-#if 0
-#define USE_DINK32 1
-#else
-#undef USE_DINK32
-#endif
-
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 9600
-
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run net_nfs\" to mount root filesystem over NFS;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "net_self=tftp ${kernel_addr} ${bootfile};" \
- "tftp ${ramdisk_addr} ${ramdisk};" \
- "run ramargs addip;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp ${kernel_addr} ${bootfile};" \
- "run nfsargs addip;bootm\0" \
- "rootpath=/opt/eldk/ppc_82xx\0" \
- "bootfile=/tftpboot/SP8240/uImage\0" \
- "ramdisk=/tftpboot/SP8240/uRamdisk\0" \
- "kernel_addr=200000\0" \
- "ramdisk_addr=400000\0" \
- ""
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_SNTP
-
-
-#define CONFIG_DRAM_SPEED 100 /* MHz */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#undef CONFIG_PCI_PNP
-
-
-#define CONFIG_EEPRO100
-#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
-
-#define PCI_ENET0_IOADDR 0x80000000
-#define PCI_ENET0_MEMADDR 0x80000000
-#define PCI_ENET1_IOADDR 0x81000000
-#define PCI_ENET1_MEMADDR 0x81000000
-
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000
-
-#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
-
-#if defined (USE_DINK32)
-#define CONFIG_SYS_MONITOR_LEN 0x00030000
-#define CONFIG_SYS_MONITOR_BASE 0x00090000
-#define CONFIG_SYS_RAMBOOT 1
-#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#else
-#undef CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_MONITOR_LEN 0x00030000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-
-
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-#endif
-
-#define CONFIG_SYS_FLASH_BASE 0xFFF00000
-#if 0
-#define CONFIG_SYS_FLASH_SIZE (512 * 1024) /* sandpoint has tiny eeprom */
-#else
-#define CONFIG_SYS_FLASH_SIZE (1024 * 1024) /* Unity has onboard 1MByte flash */
-#endif
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */
-
-#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
-
-#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */
-
-#define CONFIG_SYS_EUMB_ADDR 0xFC000000
-
-#define CONFIG_SYS_ISA_MEM 0xFD000000
-#define CONFIG_SYS_ISA_IO 0xFE000000
-
-#define CONFIG_SYS_FLASH_RANGE_BASE 0xFF000000 /* flash memory address range */
-#define CONFIG_SYS_FLASH_RANGE_SIZE 0x01000000
-#define FLASH_BASE0_PRELIM 0xFFF00000 /* sandpoint flash */
-#define FLASH_BASE1_PRELIM 0xFF000000 /* PMC onboard flash */
-
-/*
- * select i2c support configuration
- *
- * Supported configurations are {none, software, hardware} drivers.
- * If the software driver is chosen, there are some additional
- * configuration items that the driver uses to drive the port pins.
- */
-#define CONFIG_HARD_I2C 1 /* To enable I2C support */
-#undef CONFIG_SYS_I2C_SOFT
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_SPEED 400000
-
-#ifdef CONFIG_SYS_I2C_SOFT
-#error "Soft I2C is not configured properly. Please review!"
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT_SPEED 50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
-#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE (iop->pdir |= 0x00010000)
-#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
-#define I2C_READ ((iop->pdat & 0x00010000) != 0)
-#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
- else iop->pdat &= ~0x00010000
-#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
- else iop->pdat &= ~0x00020000
-#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
-#endif /* CONFIG_SYS_I2C_SOFT */
-
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* write page size */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */
-
-
-#define CONFIG_SYS_FLASH_BANKS { FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM }
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-
-
-/* #define CONFIG_WINBOND_83C553 1 / *has a winbond bridge */
-#define CONFIG_SYS_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */
-#define CONFIG_SYS_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */
-#define CONFIG_SYS_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */
-
-#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */
-#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
-
-/*
- * NS87308 Configuration
- */
-#define CONFIG_NS87308 /* Nat Semi super-io controller on ISA bus */
-
-#define CONFIG_SYS_NS87308_BADDR_10 1
-
-#define CONFIG_SYS_NS87308_DEVS ( CONFIG_SYS_NS87308_UART1 | \
- CONFIG_SYS_NS87308_UART2 | \
- CONFIG_SYS_NS87308_POWRMAN | \
- CONFIG_SYS_NS87308_RTC_APC )
-
-#undef CONFIG_SYS_NS87308_PS2MOD
-
-#define CONFIG_SYS_NS87308_CS0_BASE 0x0076
-#define CONFIG_SYS_NS87308_CS0_CONF 0x30
-#define CONFIG_SYS_NS87308_CS1_BASE 0x0075
-#define CONFIG_SYS_NS87308_CS1_CONF 0x30
-#define CONFIG_SYS_NS87308_CS2_BASE 0x0074
-#define CONFIG_SYS_NS87308_CS2_CONF 0x30
-
-/*
- * NS16550 Configuration
- */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-
-#define CONFIG_SYS_NS16550_CLK 1843200
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART1_BASE)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART2_BASE)
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
-#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 1
-
-#define CONFIG_SYS_ROMNAL 7 /*rom/flash next access time */
-#define CONFIG_SYS_ROMFAL 11 /*rom/flash access time */
-
-#define CONFIG_SYS_REFINT 430 /* no of clock cycles between CBR refresh cycles */
-
-/* the following are for SDRAM only*/
-#define CONFIG_SYS_BSTOPRE 121 /* Burst To Precharge, sets open page interval */
-#define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */
-#define CONFIG_SYS_RDLAT 4 /* data latency from read command */
-#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */
-#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
-#define CONFIG_SYS_ACTORW 3 /* Activate to R/W */
-#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
-#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
-#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length 2=4, 3=8 */
-
-#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
-
-/* memory bank settings*/
-/*
- * only bits 20-29 are actually used from these vales to set the
- * start/end address the upper two bits will be 0, and the lower 20
- * bits will be set to 0x00000 for a start address, or 0xfffff for an
- * end address
- */
-#define CONFIG_SYS_BANK0_START 0x00000000
-#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
-#define CONFIG_SYS_BANK0_ENABLE 1
-#define CONFIG_SYS_BANK1_START 0x3ff00000
-#define CONFIG_SYS_BANK1_END 0x3fffffff
-#define CONFIG_SYS_BANK1_ENABLE 0
-#define CONFIG_SYS_BANK2_START 0x3ff00000
-#define CONFIG_SYS_BANK2_END 0x3fffffff
-#define CONFIG_SYS_BANK2_ENABLE 0
-#define CONFIG_SYS_BANK3_START 0x3ff00000
-#define CONFIG_SYS_BANK3_END 0x3fffffff
-#define CONFIG_SYS_BANK3_ENABLE 0
-#define CONFIG_SYS_BANK4_START 0x00000000
-#define CONFIG_SYS_BANK4_END 0x00000000
-#define CONFIG_SYS_BANK4_ENABLE 0
-#define CONFIG_SYS_BANK5_START 0x00000000
-#define CONFIG_SYS_BANK5_END 0x00000000
-#define CONFIG_SYS_BANK5_ENABLE 0
-#define CONFIG_SYS_BANK6_START 0x00000000
-#define CONFIG_SYS_BANK6_END 0x00000000
-#define CONFIG_SYS_BANK6_ENABLE 0
-#define CONFIG_SYS_BANK7_START 0x00000000
-#define CONFIG_SYS_BANK7_END 0x00000000
-#define CONFIG_SYS_BANK7_ENABLE 0
-/*
- * Memory bank enable bitmask, specifying which of the banks defined above
- are actually present. MSB is for bank #7, LSB is for bank #0.
- */
-#define CONFIG_SYS_BANK_ENABLE 0x01
-
-#define CONFIG_SYS_ODCR 0xff /* configures line driver impedances, */
- /* see 8240 book for bit definitions */
-#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */
- /* currently accessed page in memory */
- /* see 8240 book for details */
-
-/* SDRAM 0 - 256MB */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* stack in DCACHE @ 1GB (no backing mem) */
-#if defined(USE_DINK32)
-#define CONFIG_SYS_IBAT1L (0x40000000 | BATL_PP_00 )
-#define CONFIG_SYS_IBAT1U (0x40000000 | BATU_BL_128K )
-#else
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-#endif
-
-/* PCI memory */
-#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* Flash, config addrs, etc */
-#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 20 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/* values according to the manual */
-
-#define CONFIG_DRAM_50MHZ 1
-#define CONFIG_SDRAM_50MHZ
-
-#undef NR_8259_INTS
-#define NR_8259_INTS 1
-
-
-#define CONFIG_DISK_SPINUP_TIME 1000000
-
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/Sandpoint8245.h b/include/configs/Sandpoint8245.h
deleted file mode 100644
index 2664d5b..0000000
--- a/include/configs/Sandpoint8245.h
+++ /dev/null
@@ -1,376 +0,0 @@
-/*
- * (C) Copyright 2001-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC8245 1
-#define CONFIG_SANDPOINT 1
-
-#define CONFIG_SYS_TEXT_BASE 0xFFF00000
-#define CONFIG_SYS_LDSCRIPT "board/sandpoint/u-boot.lds"
-
-#if 0
-#define USE_DINK32 1
-#else
-#undef USE_DINK32
-#endif
-
-#define CONFIG_CONS_INDEX 3 /* set to '3' for on-chip DUART */
-#define CONFIG_BAUDRATE 9600
-#define CONFIG_DRAM_SPEED 100 /* MHz */
-
-#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_SNTP
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#undef CONFIG_PCI_PNP
-
-
-#define CONFIG_EEPRO100
-#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
-#define CONFIG_NATSEMI
-#define CONFIG_NS8382X
-
-#define PCI_ENET0_IOADDR 0x80000000
-#define PCI_ENET0_MEMADDR 0x80000000
-#define PCI_ENET1_IOADDR 0x81000000
-#define PCI_ENET1_MEMADDR 0x81000000
-
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000
-
-#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
-
-#if defined (USE_DINK32)
-#define CONFIG_SYS_MONITOR_LEN 0x00030000
-#define CONFIG_SYS_MONITOR_BASE 0x00090000
-#define CONFIG_SYS_RAMBOOT 1
-#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#else
-#undef CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_MONITOR_LEN 0x00030000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-
-
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-#endif
-
-#define CONFIG_SYS_FLASH_BASE 0xFFF00000
-#if 0
-#define CONFIG_SYS_FLASH_SIZE (512 * 1024) /* sandpoint has tiny eeprom */
-#else
-#define CONFIG_SYS_FLASH_SIZE (1024 * 1024) /* Unity has onboard 1MByte flash */
-#endif
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */
-
-#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
-
-#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */
-
-#define CONFIG_SYS_EUMB_ADDR 0xFC000000
-
-#define CONFIG_SYS_ISA_MEM 0xFD000000
-#define CONFIG_SYS_ISA_IO 0xFE000000
-
-#define CONFIG_SYS_FLASH_RANGE_BASE 0xFF000000 /* flash memory address range */
-#define CONFIG_SYS_FLASH_RANGE_SIZE 0x01000000
-#define FLASH_BASE0_PRELIM 0xFFF00000 /* sandpoint flash */
-#define FLASH_BASE1_PRELIM 0xFF000000 /* PMC onboard flash */
-
-/*
- * select i2c support configuration
- *
- * Supported configurations are {none, software, hardware} drivers.
- * If the software driver is chosen, there are some additional
- * configuration items that the driver uses to drive the port pins.
- */
-#define CONFIG_HARD_I2C 1 /* To enable I2C support */
-#undef CONFIG_SYS_I2C_SOFT
-#define CONFIG_SYS_I2C_SPEED 400000
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-#ifdef CONFIG_SYS_I2C_SOFT
-#error "Soft I2C is not configured properly. Please review!"
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT_SPEED 50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
-#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE (iop->pdir |= 0x00010000)
-#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
-#define I2C_READ ((iop->pdat & 0x00010000) != 0)
-#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
- else iop->pdat &= ~0x00010000
-#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
- else iop->pdat &= ~0x00020000
-#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
-#endif /* CONFIG_SYS_I2C_SOFT */
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-
-#define CONFIG_SYS_FLASH_BANKS { FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM }
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-
-
-/* #define CONFIG_WINBOND_83C553 1 / *has a winbond bridge */
-#define CONFIG_SYS_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */
-#define CONFIG_SYS_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */
-#define CONFIG_SYS_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */
-
-#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */
-#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
-
-/*
- * NS87308 Configuration
- */
-#define CONFIG_NS87308 /* Nat Semi super-io controller on ISA bus */
-
-#define CONFIG_SYS_NS87308_BADDR_10 1
-
-#define CONFIG_SYS_NS87308_DEVS ( CONFIG_SYS_NS87308_UART1 | \
- CONFIG_SYS_NS87308_UART2 | \
- CONFIG_SYS_NS87308_POWRMAN | \
- CONFIG_SYS_NS87308_RTC_APC )
-
-#undef CONFIG_SYS_NS87308_PS2MOD
-
-#define CONFIG_SYS_NS87308_CS0_BASE 0x0076
-#define CONFIG_SYS_NS87308_CS0_CONF 0x30
-#define CONFIG_SYS_NS87308_CS1_BASE 0x0075
-#define CONFIG_SYS_NS87308_CS1_CONF 0x30
-#define CONFIG_SYS_NS87308_CS2_BASE 0x0074
-#define CONFIG_SYS_NS87308_CS2_CONF 0x30
-
-/*
- * NS16550 Configuration
- */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-
-#if (CONFIG_CONS_INDEX > 2)
-#define CONFIG_SYS_NS16550_CLK CONFIG_DRAM_SPEED*1000000
-#else
-#define CONFIG_SYS_NS16550_CLK 1843200
-#endif
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART1_BASE)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART2_BASE)
-#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_EUMB_ADDR + 0x4500)
-#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_EUMB_ADDR + 0x4600)
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
-
-#define CONFIG_SYS_ROMNAL 7 /*rom/flash next access time */
-#define CONFIG_SYS_ROMFAL 11 /*rom/flash access time */
-
-#define CONFIG_SYS_REFINT 430 /* no of clock cycles between CBR refresh cycles */
-
-/* the following are for SDRAM only*/
-#define CONFIG_SYS_BSTOPRE 121 /* Burst To Precharge, sets open page interval */
-#define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */
-#define CONFIG_SYS_RDLAT 4 /* data latency from read command */
-#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */
-#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
-#define CONFIG_SYS_ACTORW 3 /* Activate to R/W */
-#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
-#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
-#if 0
-#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* OBSOLETE! SDMODE Burst length 2=4, 3=8 */
-#endif
-
-#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
-#define CONFIG_SYS_EXTROM 1
-#define CONFIG_SYS_REGDIMM 0
-
-
-/* memory bank settings*/
-/*
- * only bits 20-29 are actually used from these vales to set the
- * start/end address the upper two bits will be 0, and the lower 20
- * bits will be set to 0x00000 for a start address, or 0xfffff for an
- * end address
- */
-#define CONFIG_SYS_BANK0_START 0x00000000
-#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
-#define CONFIG_SYS_BANK0_ENABLE 1
-#define CONFIG_SYS_BANK1_START 0x3ff00000
-#define CONFIG_SYS_BANK1_END 0x3fffffff
-#define CONFIG_SYS_BANK1_ENABLE 0
-#define CONFIG_SYS_BANK2_START 0x3ff00000
-#define CONFIG_SYS_BANK2_END 0x3fffffff
-#define CONFIG_SYS_BANK2_ENABLE 0
-#define CONFIG_SYS_BANK3_START 0x3ff00000
-#define CONFIG_SYS_BANK3_END 0x3fffffff
-#define CONFIG_SYS_BANK3_ENABLE 0
-#define CONFIG_SYS_BANK4_START 0x00000000
-#define CONFIG_SYS_BANK4_END 0x00000000
-#define CONFIG_SYS_BANK4_ENABLE 0
-#define CONFIG_SYS_BANK5_START 0x00000000
-#define CONFIG_SYS_BANK5_END 0x00000000
-#define CONFIG_SYS_BANK5_ENABLE 0
-#define CONFIG_SYS_BANK6_START 0x00000000
-#define CONFIG_SYS_BANK6_END 0x00000000
-#define CONFIG_SYS_BANK6_ENABLE 0
-#define CONFIG_SYS_BANK7_START 0x00000000
-#define CONFIG_SYS_BANK7_END 0x00000000
-#define CONFIG_SYS_BANK7_ENABLE 0
-/*
- * Memory bank enable bitmask, specifying which of the banks defined above
- are actually present. MSB is for bank #7, LSB is for bank #0.
- */
-#define CONFIG_SYS_BANK_ENABLE 0x01
-
-#define CONFIG_SYS_ODCR 0xff /* configures line driver impedances, */
- /* see 8240 book for bit definitions */
-#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */
- /* currently accessed page in memory */
- /* see 8240 book for details */
-
-/* SDRAM 0 - 256MB */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* stack in DCACHE @ 1GB (no backing mem) */
-#if defined(USE_DINK32)
-#define CONFIG_SYS_IBAT1L (0x40000000 | BATL_PP_00 )
-#define CONFIG_SYS_IBAT1U (0x40000000 | BATU_BL_128K )
-#else
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-#endif
-
-/* PCI memory */
-#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* Flash, config addrs, etc */
-#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 20 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/* values according to the manual */
-
-#define CONFIG_DRAM_50MHZ 1
-#define CONFIG_SDRAM_50MHZ
-
-#undef NR_8259_INTS
-#define NR_8259_INTS 1
-
-
-#define CONFIG_DISK_SPINUP_TIME 1000000
-
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/eXalion.h b/include/configs/eXalion.h
deleted file mode 100644
index 940be1f..0000000
--- a/include/configs/eXalion.h
+++ /dev/null
@@ -1,433 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-/* #define CONFIG_MPC8240 1 */
-#define CONFIG_MPC8245 1
-#define CONFIG_EXALION 1
-
-#define CONFIG_SYS_TEXT_BASE 0xFFF00000
-
-#if defined (CONFIG_MPC8240)
- /* #warning ---------- eXalion with MPC8240 --------------- */
-#elif defined (CONFIG_MPC8245)
- /* #warning ++++++++++ eXalion with MPC8245 +++++++++++++++ */
-#elif defined (CONFIG_MPC8245) && defined (CONFIG_MPC8245)
-#error #### Both types of MPC824x defined (CONFIG_8240 and CONFIG_8245)
-#else
-#error #### Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
-#endif
-/* older kernels need clock in MHz newer in Hz */
- /* #define CONFIG_CLOCKS_IN_MHZ 1 */ /* clocks passsed to Linux in MHz */
-#undef CONFIG_CLOCKS_IN_MHZ
-
-#define CONFIG_BOOTDELAY 10
-
-
- /*#define CONFIG_DRAM_SPEED 66 */ /* MHz */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_PCI
-
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 8 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
-#define CONFIG_MISC_INIT_R 1
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000 /* 1 GBytes - initdram() will */
- /* return real value. */
-
-#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
-
-#undef CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area
- */
-#define CONFIG_SYS_INIT_DATA_SIZE 128
-
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
-#define CONFIG_SYS_INIT_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_DATA_SIZE)
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-
-#if defined (CONFIG_MPC8240)
-#define CONFIG_SYS_FLASH_BASE 0xFFE00000
-#define CONFIG_SYS_FLASH_SIZE (2 * 1024 * 1024) /* onboard 2MByte flash */
-#elif defined (CONFIG_MPC8245)
-#define CONFIG_SYS_FLASH_BASE 0xFFC00000
-#define CONFIG_SYS_FLASH_SIZE (4 * 1024 * 1024) /* onboard 4MByte flash */
-#else
-#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
-#endif
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* Size of one Flash sector */
-#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE /* Use one Flash sector for environment */
-#define CONFIG_ENV_ADDR 0xFFFC0000
-#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */
-
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
-
-#define CONFIG_SYS_ALT_MEMTEST 1 /* use real memory test */
-#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
-
-#define CONFIG_SYS_EUMB_ADDR 0xFC000000
-
-/* #define CONFIG_SYS_ISA_MEM 0xFD000000 */
-#define CONFIG_SYS_ISA_IO 0xFE000000
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 64 /* Max number of sectors per flash */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE
-#define FLASH_BASE1_PRELIM 0
-
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-
-#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
-#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
-
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- */
-#define CONFIG_PCI 1 /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
-#undef CONFIG_PCI_PNP
-
-
-#define CONFIG_EEPRO100 1
-
-#define PCI_ENET0_MEMADDR 0x80000000 /* Intel 82559ER */
-#define PCI_ENET0_IOADDR 0x80000000
-#define PCI_ENET1_MEMADDR 0x81000000 /* Intel 82559ER */
-#define PCI_ENET1_IOADDR 0x81000000
-#define PCI_ENET2_MEMADDR 0x82000000 /* Broadcom BCM569xx */
-#define PCI_ENET2_IOADDR 0x82000000
-#define PCI_ENET3_MEMADDR 0x83000000 /* Broadcom BCM56xx */
-#define PCI_ENET3_IOADDR 0x83000000
-
-/*-----------------------------------------------------------------------
- * NS16550 Configuration
- */
-#define CONFIG_SYS_NS16550 1
-#define CONFIG_SYS_NS16550_SERIAL 1
-
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 38400
-
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-
-#if (CONFIG_CONS_INDEX == 1)
-#define CONFIG_SYS_NS16550_CLK 1843200 /* COM1 only ! */
-#else
-#define CONFIG_SYS_NS16550_CLK ({ extern ulong get_bus_freq (ulong); get_bus_freq (0); })
-#endif
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_ISA_IO + 0x3F8)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4500)
-#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_EUMB_ADDR + 0x4600)
-
-/*-----------------------------------------------------------------------
- * select i2c support configuration
- *
- * Supported configurations are {none, software, hardware} drivers.
- * If the software driver is chosen, there are some additional
- * configuration items that the driver uses to drive the port pins.
- */
-#define CONFIG_HARD_I2C 1 /* To enable I2C support */
-#undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-/*-----------------------------------------------------------------------
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
-#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 2 /* for MPC8240 only */
-
- /*#define CONFIG_133MHZ_DRAM 1 */ /* For 133 MHZ DRAM only !!!!!!!!!!! */
-
-#if defined (CONFIG_MPC8245)
-/* Bit-field values for PMCR2. */
-#if defined (CONFIG_133MHZ_DRAM)
-#define CONFIG_SYS_DLL_EXTEND 0x80 /* use DLL extended range - 133MHz only */
-#define CONFIG_SYS_PCI_HOLD_DEL 0x20 /* delay and hold timing - 133MHz only */
-#endif
-
-/* Bit-field values for MIOCR1. */
-#if !defined (CONFIG_133MHZ_DRAM)
-#define CONFIG_SYS_DLL_MAX_DELAY 0x04 /* longer DLL delay line - 66MHz only */
-#endif
-/* Bit-field values for MIOCR2. */
-#define CONFIG_SYS_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay */
- /* - note bottom 3 bits MUST be 0 */
-#endif
-
-/* Bit-field values for MCCR1. */
-#define CONFIG_SYS_ROMNAL 7 /*rom/flash next access time */
-#define CONFIG_SYS_ROMFAL 11 /*rom/flash access time */
-
-/* Bit-field values for MCCR2. */
-#define CONFIG_SYS_TSWAIT 0x5 /* Transaction Start Wait States timer */
-#if defined (CONFIG_133MHZ_DRAM)
-#define CONFIG_SYS_REFINT 1300 /* no of clock cycles between CBR */
-#else /* refresh cycles */
-#define CONFIG_SYS_REFINT 750
-#endif
-
-/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */
-#if defined (CONFIG_133MHZ_DRAM)
-#define CONFIG_SYS_BSTOPRE 1023
-#else
-#define CONFIG_SYS_BSTOPRE 250
-#endif
-
-/* Bit-field values for MCCR3. */
-/* the following are for SDRAM only */
-
-#if defined (CONFIG_133MHZ_DRAM)
-#define CONFIG_SYS_REFREC 9 /* Refresh to activate interval */
-#else
-#define CONFIG_SYS_REFREC 5 /* Refresh to activate interval */
-#endif
-#if defined (CONFIG_MPC8240)
-#define CONFIG_SYS_RDLAT 2 /* data latency from read command */
-#endif
-
-/* Bit-field values for MCCR4. */
-#if defined (CONFIG_133MHZ_DRAM)
-#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */
-#define CONFIG_SYS_ACTTOPRE 7 /* Activate to Precharge interval */
-#define CONFIG_SYS_ACTORW 5 /* Activate to R/W */
-#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
-#else
-#if 0
-#define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval */
-#define CONFIG_SYS_ACTTOPRE 3 /* Activate to Precharge interval */
-#define CONFIG_SYS_ACTORW 3 /* Activate to R/W */
-#define CONFIG_SYS_SDMODE_CAS_LAT 2 /* SDMODE CAS latency */
-#endif
-#define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval */
-#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
-#define CONFIG_SYS_ACTORW 3 /* Activate to R/W */
-#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
-#endif
-#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
-#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length 2=4, 3=8 */
-#define CONFIG_SYS_REGDIMM 0
-#if defined (CONFIG_MPC8240)
-#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 0
-#elif defined (CONFIG_MPC8245)
-#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
-#define CONFIG_SYS_EXTROM 0
-#else
-#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
-#endif
-
-
-/*-----------------------------------------------------------------------
- memory bank settings
- * only bits 20-29 are actually used from these vales to set the
- * start/end address the upper two bits will be 0, and the lower 20
- * bits will be set to 0x00000 for a start address, or 0xfffff for an
- * end address
- */
-#define CONFIG_SYS_BANK0_START 0x00000000
-#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
-#define CONFIG_SYS_BANK0_ENABLE 1
-#define CONFIG_SYS_BANK1_START 0x3ff00000
-#define CONFIG_SYS_BANK1_END 0x3fffffff
-#define CONFIG_SYS_BANK1_ENABLE 0
-#define CONFIG_SYS_BANK2_START 0x3ff00000
-#define CONFIG_SYS_BANK2_END 0x3fffffff
-#define CONFIG_SYS_BANK2_ENABLE 0
-#define CONFIG_SYS_BANK3_START 0x3ff00000
-#define CONFIG_SYS_BANK3_END 0x3fffffff
-#define CONFIG_SYS_BANK3_ENABLE 0
-#define CONFIG_SYS_BANK4_START 0x00000000
-#define CONFIG_SYS_BANK4_END 0x00000000
-#define CONFIG_SYS_BANK4_ENABLE 0
-#define CONFIG_SYS_BANK5_START 0x00000000
-#define CONFIG_SYS_BANK5_END 0x00000000
-#define CONFIG_SYS_BANK5_ENABLE 0
-#define CONFIG_SYS_BANK6_START 0x00000000
-#define CONFIG_SYS_BANK6_END 0x00000000
-#define CONFIG_SYS_BANK6_ENABLE 0
-#define CONFIG_SYS_BANK7_START 0x00000000
-#define CONFIG_SYS_BANK7_END 0x00000000
-#define CONFIG_SYS_BANK7_ENABLE 0
-
-/*-----------------------------------------------------------------------
- * Memory bank enable bitmask, specifying which of the banks defined above
- are actually present. MSB is for bank #7, LSB is for bank #0.
- */
-#define CONFIG_SYS_BANK_ENABLE 0x01
-
-#if defined (CONFIG_MPC8240)
-#define CONFIG_SYS_ODCR 0xDF /* configures line driver impedances, */
- /* see 8240 book for bit definitions */
-#elif defined (CONFIG_MPC8245)
-#if defined (CONFIG_133MHZ_DRAM)
-#define CONFIG_SYS_ODCR 0xFE /* configures line driver impedances - 133MHz */
-#else
-#define CONFIG_SYS_ODCR 0xDE /* configures line driver impedances - 66MHz */
-#endif
-#else
-#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
-#endif
-
-#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */
- /* currently accessed page in memory */
- /* see 8240 book for details */
-
-/*-----------------------------------------------------------------------
- * Block Address Translation (BAT) register settings.
- */
-/* SDRAM 0 - 256MB */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* stack in DCACHE @ 1GB (no backing mem) */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-
-/* PCI memory */
-#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* Flash, config addrs, etc */
-#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 32
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/* values according to the manual */
-#define CONFIG_DRAM_50MHZ 1
-#define CONFIG_SDRAM_50MHZ
-
-#undef NR_8259_INTS
-#define NR_8259_INTS 1
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff
- */
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 2 IDE busses */
-#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 2 drives per IDE bus */
-
-#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO /* base address */
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
-#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */
-#define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */
-#define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */
-
-#define CONFIG_ATAPI
-
-#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
-#undef CONFIG_IDE_LED /* no led for ide supported */
-#undef CONFIG_IDE_RESET /* reset for ide supported... */
-#undef CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
-
-/*-----------------------------------------------------------------------
- * DISK Partition support
- */
-#define CONFIG_DOS_PARTITION
-
-/*-----------------------------------------------------------------------
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/utx8245.h b/include/configs/utx8245.h
deleted file mode 100644
index 5be62ec..0000000
--- a/include/configs/utx8245.h
+++ /dev/null
@@ -1,408 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * (C) Copyright 2002
- * Gregory E. Allen, gallen at arlut.utexas.edu
- * Matthew E. Karger, karger at arlut.utexas.edu
- * Applied Research Laboratories, The University of Texas@Austin
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- *
- * Configuration settings for the utx8245 board.
- *
- */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC8245 1
-#define CONFIG_UTX8245 1
-
-#define CONFIG_SYS_TEXT_BASE 0xFFF00000
-
-#define DEBUG 1
-
-#define CONFIG_IDENT_STRING " [UTX5] "
-
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 57600
-
-#define CONFIG_BOOTDELAY 2
-#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n", bootdelay
-#define CONFIG_BOOTCOMMAND "run nfsboot" /* autoboot command */
-#define CONFIG_BOOTARGS "root=/dev/ram console=ttyS0,57600" /* RAMdisk */
-#define CONFIG_ETHADDR 00:AA:00:14:00:05 /* UTX5 */
-#define CONFIG_SERVERIP 10.8.17.105 /* Spree */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "kernel_addr=FFA00000\0" \
- "ramdisk_addr=FF800000\0" \
- "u-boot_startaddr=FFB00000\0" \
- "u-boot_endaddr=FFB2FFFF\0" \
- "nfsargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/nfs rw \
-nfsroot=${nfsrootip}:${rootpath} ip=dhcp\0" \
- "ramargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/ram0\0" \
- "smargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/mtdblock1 ro\0" \
- "fwargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/sda2 ro\0" \
- "nfsboot=run nfsargs;bootm ${kernel_addr}\0" \
- "ramboot=run ramargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "smboot=run smargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "fwboot=run fwargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "update_u-boot=tftp ${loadaddr} /bdi2000/u-boot.bin;protect off \
-${u-boot_startaddr} ${u-boot_endaddr};era ${u-boot_startaddr} \
-${u-boot_endaddr};cp.b ${loadaddr} ${u-boot_startaddr} ${filesize};\
-protect on ${u-boot_startaddr} ${u-boot_endaddr}"
-
-#define CONFIG_ENV_OVERWRITE
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BDI
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_CONSOLE
-#define CONFIG_CMD_LOADS
-#define CONFIG_CMD_LOADB
-#define CONFIG_CMD_IMI
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_DATE
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */
-
-
-/*-----------------------------------------------------------------------
- * PCI configuration
- *-----------------------------------------------------------------------
- */
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
-#undef CONFIG_PCI_PNP
-#define CONFIG_PCI_SCAN_SHOW
-#define CONFIG_EEPRO100
-#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
-#define CONFIG_EEPRO100_SROM_WRITE
-
-#define PCI_ENET0_IOADDR 0xF0000000
-#define PCI_ENET0_MEMADDR 0xF0000000
-
-#define PCI_FIREWIRE_IOADDR 0xF1000000
-#define PCI_FIREWIRE_MEMADDR 0xF1000000
-/*
-#define PCI_ENET0_IOADDR 0xFE000000
-#define PCI_ENET0_MEMADDR 0x80000000
-
-#define PCI_FIREWIRE_IOADDR 0x81000000
-#define PCI_FIREWIRE_MEMADDR 0x81000000
-*/
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000 /* 256MB */
-/*#define CONFIG_SYS_VERY_BIG_RAM 1 */
-
-/* FLASH_BASE is FF800000, with 4MB on RCS0, but the reset vector
- * is actually located at FFF00100. Therefore, U-Boot is
- * physically located at 0xFFB0_0000, but is also mirrored at
- * 0xFFF0_0000.
- */
-#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
-
-#define CONFIG_SYS_EUMB_ADDR 0xFC000000
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*#define CONFIG_SYS_DRAM_TEST 1 */
-#define CONFIG_SYS_MEMTEST_START 0x00003000 /* memtest works on 0...256 MB */
-#define CONFIG_SYS_MEMTEST_END 0x0ff8ffa7 /* in SDRAM, skips exception */
- /* vectors and U-Boot */
-
-
-/*--------------------------------------------------------------------
- * Definitions for initial stack pointer and data area
- *------------------------------------------------------------------*/
-#define CONFIG_SYS_INIT_DATA_SIZE 128 /* Size in bytes reserved for */
- /* initial data */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
-#define CONFIG_SYS_INIT_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_DATA_SIZE)
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-/*--------------------------------------------------------------------
- * NS16550 Configuration
- *------------------------------------------------------------------*/
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-
-#if (CONFIG_CONS_INDEX == 1 || CONFIG_CONS_INDEX == 2)
-# define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-#else
-# define CONFIG_SYS_NS16550_CLK 33000000
-#endif
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4600)
-#define CONFIG_SYS_NS16550_COM3 0xFF000000
-#define CONFIG_SYS_NS16550_COM4 0xFF000008
-
-/*--------------------------------------------------------------------
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- * For the detail description refer to the MPC8240 user's manual.
- *------------------------------------------------------------------*/
-
-#define CONFIG_SYS_CLK_FREQ 33000000
-
-/*#define CONFIG_SYS_ETH_DEV_FN 0x7800 */
-/*#define CONFIG_SYS_ETH_IOBASE 0x00104000 */
-
-/*--------------------------------------------------------------------
- * I2C Configuration
- *------------------------------------------------------------------*/
-#if 1
-#define CONFIG_HARD_I2C 1 /* To enable I2C support */
-#define CONFIG_SYS_I2C_SPEED 400000
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#endif
-
-#define CONFIG_RTC_PCF8563 1 /* enable I2C support for */
- /* Philips PCF8563 RTC */
-#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */
-
-/*--------------------------------------------------------------------
- * Memory Control Configuration Register values
- * - see sec. 4.12 of MPC8245 UM
- *------------------------------------------------------------------*/
-
-/**** MCCR1 ****/
-#define CONFIG_SYS_ROMNAL 0
-#define CONFIG_SYS_ROMFAL 10 /* (tacc=70ns)*mem_freq - 2,
- mem_freq = 100MHz */
-
-#define CONFIG_SYS_BANK7_ROW 0 /* SDRAM bank 7-0 row address */
-#define CONFIG_SYS_BANK6_ROW 0 /* bit count */
-#define CONFIG_SYS_BANK5_ROW 0
-#define CONFIG_SYS_BANK4_ROW 0
-#define CONFIG_SYS_BANK3_ROW 0
-#define CONFIG_SYS_BANK2_ROW 0
-#define CONFIG_SYS_BANK1_ROW 2
-#define CONFIG_SYS_BANK0_ROW 2
-
-/**** MCCR2, refresh interval clock cycles ****/
-#define CONFIG_SYS_REFINT 480 /* 33 MHz SDRAM clock was 480 */
-
-/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */
-#define CONFIG_SYS_BSTOPRE 1023 /* burst to precharge[0..9], */
- /* sets open page interval */
-
-/**** MCCR3 ****/
-#define CONFIG_SYS_REFREC 7 /* Refresh to activate interval, trc */
-
-/**** MCCR4 ****/
-#define CONFIG_SYS_PRETOACT 2 /* trp */
-#define CONFIG_SYS_ACTTOPRE 7 /* trcd + (burst length - 1) + trdl */
-#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */
-#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type, sequential */
-#define CONFIG_SYS_ACTORW 2 /* trcd min */
-#define CONFIG_SYS_DBUS_SIZE2 1 /* set for 8-bit RCS1, clear for 32,64 */
-#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
-#define CONFIG_SYS_EXTROM 0 /* we don't need extended ROM space */
-#define CONFIG_SYS_REGDIMM 0
-
-/* calculate according to formula in sec. 6-22 of 8245 UM */
-#define CONFIG_SYS_PGMAX 50 /* how long the 8245 retains the */
- /* currently accessed page in memory */
- /* was 45 */
-
-#define CONFIG_SYS_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note */
- /* bits 7,6, and 3-0 MUST be 0 */
-
-#if 0
-#define CONFIG_SYS_DLL_MAX_DELAY 0x04
-#else
-#define CONFIG_SYS_DLL_MAX_DELAY 0
-#endif
-#if 0 /* need for 33MHz SDRAM */
-#define CONFIG_SYS_DLL_EXTEND 0x80
-#else
-#define CONFIG_SYS_DLL_EXTEND 0
-#endif
-#define CONFIG_SYS_PCI_HOLD_DEL 0x20
-
-
-/* Memory bank settings.
- * Only bits 20-29 are actually used from these values to set the
- * start/end addresses. The upper two bits will always be 0, and the lower
- * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
- * address. Refer to the MPC8245 user manual.
- */
-
-#define CONFIG_SYS_BANK0_START 0x00000000
-#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE/2 - 1)
-#define CONFIG_SYS_BANK0_ENABLE 1
-#define CONFIG_SYS_BANK1_START CONFIG_SYS_MAX_RAM_SIZE/2
-#define CONFIG_SYS_BANK1_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
-#define CONFIG_SYS_BANK1_ENABLE 1
-#define CONFIG_SYS_BANK2_START 0x3ff00000 /* not available in this design */
-#define CONFIG_SYS_BANK2_END 0x3fffffff
-#define CONFIG_SYS_BANK2_ENABLE 0
-#define CONFIG_SYS_BANK3_START 0x3ff00000
-#define CONFIG_SYS_BANK3_END 0x3fffffff
-#define CONFIG_SYS_BANK3_ENABLE 0
-#define CONFIG_SYS_BANK4_START 0x3ff00000
-#define CONFIG_SYS_BANK4_END 0x3fffffff
-#define CONFIG_SYS_BANK4_ENABLE 0
-#define CONFIG_SYS_BANK5_START 0x3ff00000
-#define CONFIG_SYS_BANK5_END 0x3fffffff
-#define CONFIG_SYS_BANK5_ENABLE 0
-#define CONFIG_SYS_BANK6_START 0x3ff00000
-#define CONFIG_SYS_BANK6_END 0x3fffffff
-#define CONFIG_SYS_BANK6_ENABLE 0
-#define CONFIG_SYS_BANK7_START 0x3ff00000
-#define CONFIG_SYS_BANK7_END 0x3fffffff
-#define CONFIG_SYS_BANK7_ENABLE 0
-
-/*--------------------------------------------------------------------*/
-/* 4.4 - Output Driver Control Register */
-/*--------------------------------------------------------------------*/
-#define CONFIG_SYS_ODCR 0xe5
-
-/*--------------------------------------------------------------------*/
-/* 4.8 - Error Handling Registers */
-/*-------------------------------CONFIG_SYS_SDMODE_BURSTLEN-------------------------------------*/
-#define CONFIG_SYS_ERRENR1 0x11 /* enable SDRAM refresh overflow error */
-
-/* SDRAM 0-256 MB */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-/*#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_CACHEINHIBIT) */
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* stack in dcache */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-
-
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_SDRAM_BASE + 0x10000000| BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* PCI memory */
-/*#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) */
-/*#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) */
-
-/*Flash, config addrs, etc. */
-#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_BASE 0xFF800000
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */
-
-/* NOTE: environment is not EMBEDDED in the u-boot code.
- It's stored in flash in its own separate sector. */
-#define CONFIG_ENV_IS_IN_FLASH 1
-
-#if 1 /* AMD AM29LV033C */
-#define CONFIG_SYS_MAX_FLASH_SECT 64 /* Max number of sectors in one bank */
-#define CONFIG_ENV_ADDR 0xFFBF0000 /* flash sector SA63 */
-#define CONFIG_ENV_SECT_SIZE (64*1024) /* Size of the Environment Sector */
-#else /* AMD AM29LV116D */
-#define CONFIG_SYS_MAX_FLASH_SECT 35 /* Max number of sectors in one bank */
-#define CONFIG_ENV_ADDR 0xFF9FA000 /* flash sector SA33 */
-#define CONFIG_ENV_SECT_SIZE (8*1024) /* Size of the Environment Sector */
-#endif /* #if */
-
-#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE /* Size of the Environment */
-#define CONFIG_ENV_OFFSET 0 /* starting right@the beginning */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
-#undef CONFIG_SYS_RAMBOOT
-#else
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 32
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-#endif /* __CONFIG_H */
diff --git a/include/mpc824x.h b/include/mpc824x.h
deleted file mode 100644
index 31d6f69..0000000
--- a/include/mpc824x.h
+++ /dev/null
@@ -1,523 +0,0 @@
-/*
- * Copyright Rob Taylor, Flying Pig Systems Ltd. 2000.
- * Copyright (C) 2001, James Dougherty, jfd at cs.stanford.edu
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __MPC824X_H__
-#define __MPC824X_H__
-
-#include <config.h>
-
-/* CPU Types */
-#define CPU_TYPE_601 0x01 /* PPC 601 CPU */
-#define CPU_TYPE_602 0x02 /* PPC 602 CPU */
-#define CPU_TYPE_603 0x03 /* PPC 603 CPU */
-#define CPU_TYPE_603E 0x06 /* PPC 603e CPU */
-#define CPU_TYPE_603P 0x07 /* PPC 603p CPU */
-#define CPU_TYPE_604 0x04 /* PPC 604 CPU */
-#define CPU_TYPE_604E 0x09 /* PPC 604e CPU */
-#define CPU_TYPE_604R 0x0a /* PPC 604r CPU */
-#define CPU_TYPE_750 0x08 /* PPC 750 CPU */
-#define CPU_TYPE_8240 0x81 /* PPC 8240 CPU */
-#define CPU_TYPE_8245 0x8081 /* PPC 8245/8241 CPU */
-#define _CACHE_ALIGN_SIZE 32 /* cache line size */
-
-/* spr976 - DMISS data tlb miss address register
- * spr977 - DCMP data tlb miss compare register
- * spr978 - HASH1 PTEG1 address register
- * spr980 - HASH2 PTEG2 address register
- * IMISS - instruction tlb miss address register
- * ICMP - instruction TLB mis compare register
- * RPA - real page address register
- * HID0 - hardware implemntation register
- * HID2 - instruction address breakpoint register
- */
-
-/* Kahlua/MPC8240 defines */
-#define VEN_DEV_ID 0x00021057 /* Vendor and Dev. ID for MPC106 */
-#define KAHLUA_ID 0x00031057 /* Vendor & Dev Id for Kahlua's PCI */
-#define KAHLUA2_ID 0x00061057 /* 8245 is aka Kahlua-2 */
-#define BMC_BASE 0x80000000 /* Kahlua ID in PCI Memory space */
-#define CHRP_REG_ADDR 0xfec00000 /* MPC107 Config, Map B */
-#define CHRP_REG_DATA 0xfee00000 /* MPC107 Config, Map B */
-#define CHRP_ISA_MEM_PHYS 0xfd000000
-#define CHRP_ISA_MEM_BUS 0x00000000
-#define CHRP_ISA_MEM_SIZE 0x01000000
-#define CHRP_ISA_IO_PHYS 0xfe000000
-#define CHRP_ISA_IO_BUS 0x00000000
-#define CHRP_ISA_IO_SIZE 0x00800000
-#define CHRP_PCI_IO_PHYS 0xfe800000
-#define CHRP_PCI_IO_BUS 0x00800000
-#define CHRP_PCI_IO_SIZE 0x00400000
-#define CHRP_PCI_MEM_PHYS 0x80000000
-#define CHRP_PCI_MEM_BUS 0x80000000
-#define CHRP_PCI_MEM_SIZE 0x7d000000
-#define CHRP_PCI_MEMORY_PHYS 0x00000000
-#define CHRP_PCI_MEMORY_BUS 0x00000000
-#define CHRP_PCI_MEMORY_SIZE 0x40000000
-#define PREP_REG_ADDR 0x80000cf8 /* MPC107 Config, Map A */
-#define PREP_REG_DATA 0x80000cfc /* MPC107 Config, Map A */
-#define PREP_ISA_IO_PHYS 0x80000000
-#define PREP_ISA_IO_BUS 0x00000000
-#define PREP_ISA_IO_SIZE 0x00800000
-#define PREP_PCI_IO_PHYS 0x81000000
-#define PREP_PCI_IO_BUS 0x01000000
-#define PREP_PCI_IO_SIZE 0x3e800000
-#define PREP_PCI_MEM_PHYS 0xc0000000
-#define PREP_PCI_MEM_BUS 0x00000000
-#define PREP_PCI_MEM_SIZE 0x3f000000
-#define PREP_PCI_MEMORY_PHYS 0x00000000
-#define PREP_PCI_MEMORY_BUS 0x80000000
-#define PREP_PCI_MEMORY_SIZE 0x80000000
-#define MPC107_PCI_CMD 0x80000004 /* MPC107 PCI cmd reg */
-#define MPC107_PCI_STAT 0x80000006 /* MPC107 PCI status reg */
-#define PROC_INT1_ADR 0x800000a8 /* MPC107 Processor i/f cfg1 */
-#define PROC_INT2_ADR 0x800000ac /* MPC107 Processor i/f cfg2 */
-#define MEM_CONT1_ADR 0x800000f0 /* MPC107 Memory control config. 1 */
-#define MEM_CONT2_ADR 0x800000f4 /* MPC107 Memory control config. 2 */
-#define MEM_CONT3_ADR 0x800000f8 /* MPC107 Memory control config. 3 */
-#define MEM_CONT4_ADR 0x800000fc /* MPC107 Memory control config. 4 */
-#define MEM_ERREN1_ADR 0x800000c0 /* MPC107 Memory error enable 1 */
-#define MEM_START1_ADR 0x80000080 /* MPC107 Memory starting addr */
-#define MEM_START2_ADR 0x80000084 /* MPC107 Memory starting addr-lo */
-#define XMEM_START1_ADR 0x80000088 /* MPC107 Extended mem. start addr-hi*/
-#define XMEM_START2_ADR 0x8000008c /* MPC107 Extended mem. start addr-lo*/
-#define MEM_END1_ADR 0x80000090 /* MPC107 Memory ending address */
-#define MEM_END2_ADR 0x80000094 /* MPC107 Memory ending addr-lo */
-#define XMEM_END1_ADR 0x80000098 /* MPC107 Extended mem. end addrs-hi */
-#define XMEM_END2_ADR 0x8000009c /* MPC107 Extended mem. end addrs-lo*/
-#define OUT_DRV_CONT 0x80000073 /* MPC107 Output Driver Control reg */
-#define MEM_EN_ADR 0x800000a0 /* Memory bank enable */
-#define PAGE_MODE 0x800000a3 /* MPC107 Page Mode Counter/Timer */
-
-/*-----------------------------------------------------------------------
- * Exception offsets (PowerPC standard)
- */
-#define EXC_OFF_RESERVED0 0x0000 /* Reserved */
-#define EXC_OFF_SYS_RESET 0x0100 /* System reset */
-#define EXC_OFF_MACH_CHCK 0x0200 /* Machine Check */
-#define EXC_OFF_DATA_STOR 0x0300 /* Data Storage */
-#define EXC_OFF_INS_STOR 0x0400 /* Instruction Storage */
-#define EXC_OFF_EXTERNAL 0x0500 /* External */
-#define EXC_OFF_ALIGN 0x0600 /* Alignment */
-#define EXC_OFF_PROGRAM 0x0700 /* Program */
-#define EXC_OFF_FPUNAVAIL 0x0800 /* Floating-point Unavailable */
-#define EXC_OFF_DECR 0x0900 /* Decrementer */
-#define EXC_OFF_RESERVED1 0x0A00 /* Reserved */
-#define EXC_OFF_RESERVED2 0x0B00 /* Reserved */
-#define EXC_OFF_SYS_CALL 0x0C00 /* System Call */
-#define EXC_OFF_TRACE 0x0D00 /* Trace */
-#define EXC_OFF_FPUNASSIST 0x0E00 /* Floating-point Assist */
-
- /* 0x0E10 - 0x0FFF are marked reserved in The PowerPC Architecture book */
- /* these found in DINK code - may not apply to 8240*/
-#define EXC_OFF_PMI 0x0F00 /* Performance Monitoring Interrupt */
-#define EXC_OFF_VMXUI 0x0F20 /* VMX (AltiVec) Unavailable Interrupt */
-
- /* 0x1000 - 0x2FFF are implementation specific */
- /* these found in DINK code - may not apply to 8240 */
-#define EXC_OFF_ITME 0x1000 /* Instruction Translation Miss Exception */
-#define EXC_OFF_DLTME 0x1100 /* Data Load Translation Miss Exception */
-#define EXC_OFF_DSTME 0x1200 /* Data Store Translation Miss Exception */
-#define EXC_OFF_IABE 0x1300 /* Instruction Addr Breakpoint Exception */
-#define EXC_OFF_SMIE 0x1400 /* System Management Interrupt Exception */
-#define EXC_OFF_JMDDI 0x1600 /* Java Mode denorm detect Interr -- WTF??*/
-#define EXC_OFF_RMTE 0x2000 /* Run Mode or Trace Exception */
-
-#define _START_OFFSET EXC_OFF_SYS_RESET
-
-#define MAP_A_CONFIG_ADDR_HIGH 0x8000 /* Upper half of CONFIG_ADDR for Map A */
-#define MAP_A_CONFIG_ADDR_LOW 0x0CF8 /* Lower half of CONFIG_ADDR for Map A */
-#define MAP_A_CONFIG_DATA_HIGH 0x8000 /* Upper half of CONFIG_DAT for Map A */
-#define MAP_A_CONFIG_DATA_LOW 0x0CFC /* Lower half of CONFIG_DAT for Map A */
-#define MAP_B_CONFIG_ADDR_HIGH 0xfec0 /* Upper half of CONFIG_ADDR for Map B */
-#define MAP_B_CONFIG_ADDR_LOW 0x0000 /* Lower half of CONFIG_ADDR for Map B */
-#define MAP_B_CONFIG_DATA_HIGH 0xfee0 /* Upper half of CONFIG_DAT for Map B */
-#define MAP_B_CONFIG_DATA_LOW 0x0000 /* Lower half of CONFIG_DAT for Map B */
-
-
-#if defined(CONFIG_SYS_ADDR_MAP_A)
-#define CONFIG_ADDR_HIGH MAP_A_CONFIG_ADDR_HIGH /* Upper half of CONFIG_ADDR */
-#define CONFIG_ADDR_LOW MAP_A_CONFIG_ADDR_LOW /* Lower half of CONFIG_ADDR */
-#define CONFIG_DATA_HIGH MAP_A_CONFIG_DATA_HIGH /* Upper half of CONFIG_DAT */
-#define CONFIG_DATA_LOW MAP_A_CONFIG_DATA_LOW /* Lower half of CONFIG_DAT */
-#else /* Assume Map B, default */
-#define CONFIG_ADDR_HIGH MAP_B_CONFIG_ADDR_HIGH /* Upper half of CONFIG_ADDR */
-#define CONFIG_ADDR_LOW MAP_B_CONFIG_ADDR_LOW /* Lower half of CONFIG_ADDR */
-#define CONFIG_DATA_HIGH MAP_B_CONFIG_DATA_HIGH /* Upper half of CONFIG_DAT */
-#define CONFIG_DATA_LOW MAP_B_CONFIG_DATA_LOW /* Lower half of CONFIG_DAT */
-#endif
-
-#define CONFIG_ADDR (CONFIG_ADDR_HIGH << 16 | CONFIG_ADDR_LOW)
-
-#define CONFIG_DATA (CONFIG_DATA_HIGH << 16 | CONFIG_DATA_LOW)
-
-/* Macros to write to config registers. addr should be a constant in all cases */
-
-#define CONFIG_WRITE_BYTE( addr, data ) \
- __asm__ __volatile__( \
- " stwbrx %1, 0, %0\n \
- sync\n \
- stb %3, %4(%2)\n \
- sync " \
- : /* no output */ \
- : "r" (CONFIG_ADDR), "r" ((addr) & ~3), \
- "b" (CONFIG_DATA), "r" (data), \
- "n" ((addr) & 3));
-
-#define CONFIG_WRITE_HALFWORD( addr, data ) \
- __asm__ __volatile__( \
- " stwbrx %1, 0, %0\n \
- sync\n \
- sthbrx %3, %4, %2\n \
- sync " \
- : /* no output */ \
- : "r" (CONFIG_ADDR), "r" ((addr) & ~3), \
- "r" (CONFIG_DATA), "r" (data), \
- "b" ((addr) & 3));
-
-/* this assumes it's writeing on word boundaries*/
-#define CONFIG_WRITE_WORD( addr, data ) \
- __asm__ __volatile__( \
- " stwbrx %1, 0, %0\n \
- sync\n \
- stwbrx %3, 0, %2\n \
- sync " \
- : /* no output */ \
- : "r" (CONFIG_ADDR), "r" (addr), \
- "r" (CONFIG_DATA), "r" (data));
-
-/* Configuration register reads*/
-
-#define CONFIG_READ_BYTE( addr, reg ) \
- __asm__ ( \
- " stwbrx %1, 0, %2\n \
- sync\n \
- lbz %0, %4(%3)\n \
- sync " \
- : "=r" (reg) \
- : "r" ((addr) & ~3), "r" (CONFIG_ADDR), \
- "b" (CONFIG_DATA), "n" ((addr) & 3));
-
-
-#define CONFIG_READ_HALFWORD( addr, reg ) \
- __asm__ ( \
- " stwbrx %1, 0, %2\n \
- sync\n \
- lhbrx %0, %4, %3\n \
- sync " \
- : "=r" (reg) \
- : "r" ((addr) & ~3), "r" (CONFIG_ADDR), \
- "r" (CONFIG_DATA), \
- "b" ((addr) & 3));
-
-/* this assumes it's reading on word boundaries*/
-#define CONFIG_READ_WORD( addr, reg ) \
- __asm__ ( \
- " stwbrx %1, 0, %2\n \
- sync\n \
- lwbrx %0, 0, %3\n \
- sync " \
- : "=r" (reg) \
- : "r" (addr), "r" (CONFIG_ADDR),\
- "r" (CONFIG_DATA));
-
-/*
- * configuration register 'addresses'.
- * These are described in chaper 5 of the 8240 users manual.
- * Where the register has an abreviation in the manual, this has
- * been usaed here, otherwise a name in keeping with the norm has
- * been invented.
- * Note that some of these registers aren't documented in the manual.
- */
-
-#define PCICR 0x80000004 /* PCI Command Register */
-#define PCISR 0x80000006 /* PCI Status Register */
-#define REVID 0x80000008 /* CPU revision id */
-#define PIR 0x80000009 /* PCI Programming Interface Register */
-#define PBCCR 0x8000000b /* PCI Base Class Code Register */
-#define PCLSR 0x8000000c /* Processor Cache Line Size Register */
-#define PLTR 0x8000000d /* PCI Latancy Timer Register */
-#define PHTR 0x8000000e /* PCI Header Type Register */
-#define BISTCTRL 0x8000000f /* BIST Control */
-#define LMBAR 0x80000010 /* Local Base Address Register */
-#define PCSRBAR 0x80000014 /* PCSR Base Address Register */
-#define ILR 0x8000003c /* PCI Interrupt Line Register */
-#define IPR 0x8000003d /* Interrupt Pin Register */
-#define MINGNT 0x8000003e /* MIN GNI */
-#define MAXLAT 0x8000003f /* MAX LAT */
-#define PCIACR 0x80000046 /* PCI Arbiter Control Register */
-#define PMCR1 0x80000070 /* Power management config. 1 */
-#define PMCR2 0x80000072 /* Power management config. 2 */
-#define ODCR 0x80000073 /* Output Driver Control Register */
-#define CLKDCR 0x80000074 /* CLK Driver Control Register */
-#if defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241)
-#define MIOCR1 0x80000076 /* Miscellaneous I/O Control Register 1 */
-#define MIOCR2 0x80000077 /* Miscellaneous I/O Control Register 2 */
-#endif
-#define EUMBBAR 0x80000078 /* Embedded Utilities Memory Block Base Address Register */
-#define EUMBBAR_VAL 0x80500000 /* PCI Relocation offset for EUMB region */
-#define EUMBSIZE 0x00100000 /* Size of EUMB region */
-
-#define MSAR1 0x80000080 /* Memory Starting Address Register 1 */
-#define MSAR2 0x80000084 /* Memory Starting Address Register 2 */
-#define EMSAR1 0x80000088 /* Extended Memory Starting Address Register 1*/
-#define EMSAR2 0x8000008c /* Extended Memory Starting Address Register 2*/
-#define MEAR1 0x80000090 /* Memory Ending Address Register 1 */
-#define MEAR2 0x80000094 /* Memory Ending Address Register 2 */
-#define EMEAR1 0x80000098 /* Extended Memory Ending Address Register 1 */
-#define EMEAR2 0x8000009c /* Extended Memory Ending Address Register 2 */
-#define MBER 0x800000a0 /* Memory bank Enable Register*/
-#define MPMR 0x800000a3 /* Memory Page Mode Register (stores PGMAX) */
-#define PICR1 0x800000a8 /* Processor Interface Configuration Register 1 */
-#define PICR2 0x800000ac /* Processor Interface Configuration Register 2 */
-#define ECCSBECR 0x800000b8 /* ECC Single-Bit Error Counter Register */
-#define ECCSBETR 0x800000b8 /* ECC Single-Bit Error Trigger Register */
-#define ERRENR1 0x800000c0 /* Error Enableing Register 1 */
-#define ERRENR2 0x800000c4 /* Error Enableing Register 2 */
-#define ERRDR1 0x800000c1 /* Error Detection Register 1 */
-#define IPBESR 0x800000c3 /* Internal Processor Error Status Register */
-#define ERRDR2 0x800000c5 /* Error Detection Register 2 */
-#define PBESR 0x800000c7 /* PCI Bus Error Status Register */
-#define PBEAR 0x800000c8 /* Processor/PCI Bus Error Status Register */
-#define AMBOR 0x800000e0 /* Address Map B Options Register */
-#define PCMBCR 0x800000e1 /* PCI/Memory Buffer Configuration */
-#define MCCR1 0x800000f0 /* Memory Control Configuration Register 1 */
-#define MCCR2 0x800000f4 /* Memory Control Configuration Register 2 */
-#define MCCR3 0x800000f8 /* Memory Control Configuration Register 3 */
-#define MCCR4 0x800000fc /* Memory Control Configuration Register 4 */
-
-/* some values for some of the above */
-
-#define PICR1_CF_APARK 0x00000008
-#define PICR1_LE_MODE 0x00000020
-#define PICR1_ST_GATH_EN 0x00000040
-#if defined(CONFIG_MPC8240)
-#define PICR1_EN_PCS 0x00000080 /* according to dink code, sets the 8240 to handle pci config space */
-#elif defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241)
-#define PICR1_NO_BUSW_CK 0x00000080 /* no bus width check for flash writes */
-#define PICR1_DEC 0x00000100 /* Time Base enable on 8245/8241 */
-#define ERCR1 0x800000d0 /* Extended ROM Configuration Register 1 */
-#define ERCR2 0x800000d4 /* Extended ROM Configuration Register 2 */
-#define ERCR3 0x800000d8 /* Extended ROM Configuration Register 3 */
-#define ERCR4 0x800000dc /* Extended ROM Configuration Register 4 */
-#define MIOCR1 0x80000076 /* Miscellaneous I/O Control Register 1 */
-#define MIOCR1_ADR_X 0x80000074 /* Miscellaneous I/O Control Register 1 */
-#define MIOCR1_SHIFT 2
-#define MIOCR2 0x80000077 /* Miscellaneous I/O Control Register 2 */
-#define MIOCR2_ADR_X 0x80000074 /* Miscellaneous I/O Control Register 1 */
-#define MIOCR2_SHIFT 3
-#define ODCR_ADR_X 0x80000070 /* Output Driver Control register */
-#define ODCR_SHIFT 3
-#define PMCR2_ADR 0x80000072 /* Power Mgmnt Cfg 2 register */
-#define PMCR2_ADR_X 0x80000070
-#define PMCR2_SHIFT 3
-#define PMCR1_ADR 0x80000070 /* Power Mgmnt Cfg 1 reister */
-#else
-#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
-#endif
-#define PICR1_CF_DPARK 0x00000200
-#define PICR1_MCP_EN 0x00000800
-#define PICR1_FLASH_WR_EN 0x00001000
-#ifdef CONFIG_MPC8240
-#define PICR1_ADDRESS_MAP 0x00010000
-#define PIRC1_MSK 0xff000000
-#endif
-#define PICR1_PROC_TYPE_MSK 0x00060000
-#define PICR1_PROC_TYPE_603E 0x00040000
-#define PICR1_RCS0 0x00100000
-
-#define PICR2_CF_SNOOP_WS_MASK 0x000c0000
-#define PICR2_CF_SNOOP_WS_0WS 0x00000000
-#define PICR2_CF_SNOOP_WS_1WS 0x00040000
-#define PICR2_CF_SNOOP_WS_2WS 0x00080000
-#define PICR2_CF_SNOOP_WS_3WS 0x000c0000
-#define PICR2_CF_APHASE_WS_MASK 0x0000000c
-#define PICR2_CF_APHASE_WS_0WS 0x00000000
-#define PICR2_CF_APHASE_WS_1WS 0x00000004
-#define PICR2_CF_APHASE_WS_2WS 0x00000008
-#define PICR2_CF_APHASE_WS_3WS 0x0000000c
-
-#define MCCR1_ROMNAL_SHIFT 28
-#define MCCR1_ROMNAL_MSK 0xf0000000
-#define MCCR1_ROMFAL_SHIFT 23
-#define MCCR1_ROMFAL_MSK 0x0f800000
-#define MCCR1_DBUS_SIZE0 0x00400000
-#define MCCR1_BURST 0x00100000
-#define MCCR1_MEMGO 0x00080000
-#define MCCR1_SREN 0x00040000
-#if defined(CONFIG_MPC8240)
-#define MCCR1_RAM_TYPE 0x00020000
-#elif defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241)
-#define MCCR1_SDRAM_EN 0x00020000
-#else
-#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
-#endif
-#define MCCR1_PCKEN 0x00010000
-#define MCCR1_BANK1ROW_SHIFT 2
-#define MCCR1_BANK2ROW_SHIFT 4
-#define MCCR1_BANK3ROW_SHIFT 6
-#define MCCR1_BANK4ROW_SHIFT 8
-#define MCCR1_BANK5ROW_SHIFT 10
-#define MCCR1_BANK6ROW_SHIFT 12
-#define MCCR1_BANK7ROW_SHIFT 14
-
-#define MCCR2_TS_WAIT_TIMER_MSK 0xe0000000
-#define MCCR2_TS_WAIT_TIMER_SHIFT 29
-#define MCCR2_ASRISE_MSK 0x1e000000
-#define MCCR2_ASRISE_SHIFT 25
-#define MCCR2_ASFALL_MSK 0x01e00000
-#define MCCR2_ASFALL_SHIFT 21
-
-#define MCCR2_INLINE_PAR_NOT_ECC 0x00100000
-#define MCCR2_WRITE_PARITY_CHK 0x00080000
-#define MCCR2_INLFRD_PARECC_CHK_EN 0x00040000
-#ifdef CONFIG_MPC8240
-#define MCCR2_ECC_EN 0x00020000
-#define MCCR2_EDO 0x00010000
-#endif
-#define MCCR2_REFINT_MSK 0x0000fffc
-#define MCCR2_REFINT_SHIFT 2
-#define MCCR2_RSV_PG 0x00000002
-#define MCCR2_PMW_PAR 0x00000001
-
-#define MCCR3_BSTOPRE2TO5_MSK 0xf0000000 /*BSTOPRE[2-5]*/
-#define MCCR3_BSTOPRE2TO5_SHIFT 28
-#define MCCR3_REFREC_MSK 0x0f000000
-#define MCCR3_REFREC_SHIFT 24
-#ifdef CONFIG_MPC8240
-#define MCCR3_RDLAT_MSK 0x00f00000
-#define MCCR3_RDLAT_SHIFT 20
-#define MCCR3_CPX 0x00010000
-#define MCCR3_RAS6P_MSK 0x00078000
-#define MCCR3_RAS6P_SHIFT 15
-#define MCCR3_CAS5_MSK 0x00007000
-#define MCCR3_CAS5_SHIFT 12
-#define MCCR3_CP4_MSK 0x00000e00
-#define MCCR3_CP4_SHIFT 9
-#define MCCR3_CAS3_MSK 0x000001c0
-#define MCCR3_CAS3_SHIFT 6
-#define MCCR3_RCD2_MSK 0x00000038
-#define MCCR3_RCD2_SHIFT 3
-#define MCCR3_RP1_MSK 0x00000007
-#define MCCR3_RP1_SHIFT 0
-#endif
-
-#define MCCR4_PRETOACT_MSK 0xf0000000
-#define MCCR4_PRETOACT_SHIFT 28
-#define MCCR4_ACTTOPRE_MSK 0x0f000000
-#define MCCR4_ACTTOPRE_SHIFT 24
-#define MCCR4_WMODE 0x00800000
-#define MCCR4_INLINE 0x00400000
-#if defined(CONFIG_MPC8240)
-#define MCCR4_BIT21 0x00200000 /* this include cos DINK code sets it- unknown function*/
-#elif defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241)
-#define MCCR4_EXTROM 0x00200000 /* enables Extended ROM space */
-#else
-#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
-#endif
-#define MCCR4_REGISTERED 0x00100000
-#define MCCR4_BSTOPRE0TO1_MSK 0x000c0000 /*BSTOPRE[0-1]*/
-#define MCCR4_BSTOPRE0TO1_SHIFT 18
-#define MCCR4_REGDIMM 0x00008000
-#define MCCR4_SDMODE_MSK 0x00007f00
-#define MCCR4_SDMODE_SHIFT 8
-#define MCCR4_ACTTORW_MSK 0x000000f0
-#define MCCR4_ACTTORW_SHIFT 4
-#define MCCR4_BSTOPRE6TO9_MSK 0x0000000f /*BSTOPRE[6-9]*/
-#define MCCR4_BSTOPRE6TO9_SHIFT 0
-#define MCCR4_DBUS_SIZE2_SHIFT 17
-
-#define MICR_ADDR_MASK 0x0ff00000
-#define MICR_ADDR_SHIFT 20
-#define MICR_EADDR_MASK 0x30000000
-#define MICR_EADDR_SHIFT 28
-
-/*eumb and epic config*/
-
-#define EPIC_FPR 0x00041000
-#define EPIC_GCR 0x00041020
-#define EPIC_EICR 0x00041030
-#define EPIC_EVI 0x00041080
-#define EPIC_PI 0x00041090
-#define EPIC_SVR 0x000410E0
-#define EPIC_TFRR 0x000410F0
-
-/*
- * Note the information for these is rather mangled in the 8240 manual.
- * These are guesses.
- */
-
-#define EPIC_GTCCR0 0x00041100
-#define EPIC_GTCCR1 0x00041140
-#define EPIC_GTCCR2 0x00041180
-#define EPIC_GTCCR3 0x000411C0
-#define EPIC_GTBCR0 0x00041110
-#define EPIC_GTBCR1 0x00041150
-#define EPIC_GTBCR2 0x00041190
-#define EPIC_GTBCR3 0x000411D0
-#define EPIC_GTVPR0 0x00041120
-#define EPIC_GTVPR1 0x00041160
-#define EPIC_GTVPR2 0x000411a0
-#define EPIC_GTVPR3 0x000411e0
-#define EPIC_GTDR0 0x00041130
-#define EPIC_GTDR1 0x00041170
-#define EPIC_GTDR2 0x000411b0
-#define EPIC_GTDR3 0x000411f0
-
-#define EPIC_IVPR0 0x00050200
-#define EPIC_IVPR1 0x00050220
-#define EPIC_IVPR2 0x00050240
-#define EPIC_IVPR3 0x00050260
-#define EPIC_IVPR4 0x00050280
-
-#define EPIC_SVPR0 0x00050200
-#define EPIC_SVPR1 0x00050220
-#define EPIC_SVPR2 0x00050240
-#define EPIC_SVPR3 0x00050260
-#define EPIC_SVPR4 0x00050280
-#define EPIC_SVPR5 0x000502A0
-#define EPIC_SVPR6 0x000502C0
-#define EPIC_SVPR7 0x000502E0
-#define EPIC_SVPR8 0x00050300
-#define EPIC_SVPR9 0x00050320
-#define EPIC_SVPRa 0x00050340
-#define EPIC_SVPRb 0x00050360
-#define EPIC_SVPRc 0x00050380
-#define EPIC_SVPRd 0x000503A0
-#define EPIC_SVPRe 0x000503C0
-#define EPIC_SVPRf 0x000503E0
-
-/* MPC8240 Byte Swap/PCI Support Macros */
-#define BYTE_SWAP_16_BIT(x) ( (((x) & 0x00ff) << 8) | ( (x) >> 8) )
-#define LONGSWAP(x) ((((x) & 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8)|\
- (((x) & 0x00ff0000) >> 8) | (((x) & 0xff000000) >> 24) )
-#define PCISWAP(x) LONGSWAP(x)
-
-#ifndef __ASSEMBLY__
-
-/*
- * MPC107 Support
- *
- */
-unsigned int mpc824x_mpc107_getreg(unsigned int regNum);
-void mpc824x_mpc107_setreg(unsigned int regNum, unsigned int regVal);
-void mpc824x_mpc107_write8(unsigned int address, unsigned char data);
-void mpc824x_mpc107_write16(unsigned int address, unsigned short data);
-void mpc824x_mpc107_write32(unsigned int address, unsigned int data);
-unsigned char mpc824x_mpc107_read8(unsigned int address);
-unsigned short mpc824x_mpc107_read16(unsigned int address);
-unsigned int mpc824x_mpc107_read32(unsigned int address);
-unsigned int mpc824x_eummbar_read(unsigned int regNum);
-void mpc824x_eummbar_write(unsigned int regNum, unsigned int regVal);
-
-#ifdef CONFIG_PCI
-struct pci_controller;
-void pci_cpm824x_init(struct pci_controller* hose);
-#endif
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* __MPC824X_H__ */
diff --git a/include/pci.h b/include/pci.h
index 216f448..7f67ca6 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -670,10 +670,6 @@ extern void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
const char * pci_class_str(u8 class);
int pci_last_busno(void);
-#ifdef CONFIG_MPC824X
-extern void pci_mpc824x_init (struct pci_controller *hose);
-#endif
-
#ifdef CONFIG_MPC85xx
extern void pci_mpc85xx_init (struct pci_controller *hose);
#endif
diff --git a/include/pcmcia/cirrus.h b/include/pcmcia/cirrus.h
deleted file mode 100644
index cd34dd8..0000000
--- a/include/pcmcia/cirrus.h
+++ /dev/null
@@ -1,180 +0,0 @@
-/*
- * cirrus.h 1.4 1999/10/25 20:03:34
- *
- * The contents of this file are subject to the Mozilla Public License
- * Version 1.1 (the "License"); you may not use this file except in
- * compliance with the License. You may obtain a copy of the License
- * at http://www.mozilla.org/MPL/
- *
- * Software distributed under the License is distributed on an "AS IS"
- * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
- * the License for the specific language governing rights and
- * limitations under the License.
- *
- * The initial developer of the original code is David A. Hinds
- * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
- * are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
- *
- * Alternatively, the contents of this file may be used under the
- * terms of the GNU General Public License version 2 (the "GPL"), in which
- * case the provisions of the GPL are applicable instead of the
- * above. If you wish to allow the use of your version of this file
- * only under the terms of the GPL and not to allow others to use
- * your version of this file under the MPL, indicate your decision by
- * deleting the provisions above and replace them with the notice and
- * other provisions required by the GPL. If you do not delete the
- * provisions above, a recipient may use your version of this file
- * under either the MPL or the GPL.
- */
-
-#ifndef _LINUX_CIRRUS_H
-#define _LINUX_CIRRUS_H
-
-#ifndef PCI_VENDOR_ID_CIRRUS
-#define PCI_VENDOR_ID_CIRRUS 0x1013
-#endif
-#ifndef PCI_DEVICE_ID_CIRRUS_6729
-#define PCI_DEVICE_ID_CIRRUS_6729 0x1100
-#endif
-#ifndef PCI_DEVICE_ID_CIRRUS_6832
-#define PCI_DEVICE_ID_CIRRUS_6832 0x1110
-#endif
-
-#define PD67_MISC_CTL_1 0x16 /* Misc control 1 */
-#define PD67_FIFO_CTL 0x17 /* FIFO control */
-#define PD67_MISC_CTL_2 0x1E /* Misc control 2 */
-#define PD67_CHIP_INFO 0x1f /* Chip information */
-#define PD67_ATA_CTL 0x026 /* 6730: ATA control */
-#define PD67_EXT_INDEX 0x2e /* Extension index */
-#define PD67_EXT_DATA 0x2f /* Extension data */
-
-/* PD6722 extension registers -- indexed in PD67_EXT_INDEX */
-#define PD67_DATA_MASK0 0x01 /* Data mask 0 */
-#define PD67_DATA_MASK1 0x02 /* Data mask 1 */
-#define PD67_DMA_CTL 0x03 /* DMA control */
-
-/* PD6730 extension registers -- indexed in PD67_EXT_INDEX */
-#define PD67_EXT_CTL_1 0x03 /* Extension control 1 */
-#define PD67_MEM_PAGE(n) ((n)+5) /* PCI window bits 31:24 */
-#define PD67_EXTERN_DATA 0x0a
-#define PD67_MISC_CTL_3 0x25
-#define PD67_SMB_PWR_CTL 0x26
-
-/* I/O window address offset */
-#define PD67_IO_OFF(w) (0x36+((w)<<1))
-
-/* Timing register sets */
-#define PD67_TIME_SETUP(n) (0x3a + 3*(n))
-#define PD67_TIME_CMD(n) (0x3b + 3*(n))
-#define PD67_TIME_RECOV(n) (0x3c + 3*(n))
-
-/* Flags for PD67_MISC_CTL_1 */
-#define PD67_MC1_5V_DET 0x01 /* 5v detect */
-#define PD67_MC1_MEDIA_ENA 0x01 /* 6730: Multimedia enable */
-#define PD67_MC1_VCC_3V 0x02 /* 3.3v Vcc */
-#define PD67_MC1_PULSE_MGMT 0x04
-#define PD67_MC1_PULSE_IRQ 0x08
-#define PD67_MC1_SPKR_ENA 0x10
-#define PD67_MC1_INPACK_ENA 0x80
-
-/* Flags for PD67_FIFO_CTL */
-#define PD67_FIFO_EMPTY 0x80
-
-/* Flags for PD67_MISC_CTL_2 */
-#define PD67_MC2_FREQ_BYPASS 0x01
-#define PD67_MC2_DYNAMIC_MODE 0x02
-#define PD67_MC2_SUSPEND 0x04
-#define PD67_MC2_5V_CORE 0x08
-#define PD67_MC2_LED_ENA 0x10 /* IRQ 12 is LED enable */
-#define PD67_MC2_FAST_PCI 0x10 /* 6729: PCI bus > 25 MHz */
-#define PD67_MC2_3STATE_BIT7 0x20 /* Floppy change bit */
-#define PD67_MC2_DMA_MODE 0x40
-#define PD67_MC2_IRQ15_RI 0x80 /* IRQ 15 is ring enable */
-
-/* Flags for PD67_CHIP_INFO */
-#define PD67_INFO_SLOTS 0x20 /* 0 = 1 slot, 1 = 2 slots */
-#define PD67_INFO_CHIP_ID 0xc0
-#define PD67_INFO_REV 0x1c
-
-/* Fields in PD67_TIME_* registers */
-#define PD67_TIME_SCALE 0xc0
-#define PD67_TIME_SCALE_1 0x00
-#define PD67_TIME_SCALE_16 0x40
-#define PD67_TIME_SCALE_256 0x80
-#define PD67_TIME_SCALE_4096 0xc0
-#define PD67_TIME_MULT 0x3f
-
-/* Fields in PD67_DMA_CTL */
-#define PD67_DMA_MODE 0xc0
-#define PD67_DMA_OFF 0x00
-#define PD67_DMA_DREQ_INPACK 0x40
-#define PD67_DMA_DREQ_WP 0x80
-#define PD67_DMA_DREQ_BVD2 0xc0
-#define PD67_DMA_PULLUP 0x20 /* Disable socket pullups? */
-
-/* Fields in PD67_EXT_CTL_1 */
-#define PD67_EC1_VCC_PWR_LOCK 0x01
-#define PD67_EC1_AUTO_PWR_CLEAR 0x02
-#define PD67_EC1_LED_ENA 0x04
-#define PD67_EC1_INV_CARD_IRQ 0x08
-#define PD67_EC1_INV_MGMT_IRQ 0x10
-#define PD67_EC1_PULLUP_CTL 0x20
-
-/* Fields in PD67_MISC_CTL_3 */
-#define PD67_MC3_IRQ_MASK 0x03
-#define PD67_MC3_IRQ_PCPCI 0x00
-#define PD67_MC3_IRQ_EXTERN 0x01
-#define PD67_MC3_IRQ_PCIWAY 0x02
-#define PD67_MC3_IRQ_PCI 0x03
-#define PD67_MC3_PWR_MASK 0x0c
-#define PD67_MC3_PWR_SERIAL 0x00
-#define PD67_MC3_PWR_TI2202 0x08
-#define PD67_MC3_PWR_SMB 0x0c
-
-/* Register definitions for Cirrus PD6832 PCI-to-CardBus bridge */
-
-/* PD6832 extension registers -- indexed in PD67_EXT_INDEX */
-#define PD68_EXT_CTL_2 0x0b
-#define PD68_PCI_SPACE 0x22
-#define PD68_PCCARD_SPACE 0x23
-#define PD68_WINDOW_TYPE 0x24
-#define PD68_EXT_CSC 0x2e
-#define PD68_MISC_CTL_4 0x2f
-#define PD68_MISC_CTL_5 0x30
-#define PD68_MISC_CTL_6 0x31
-
-/* Extra flags in PD67_MISC_CTL_3 */
-#define PD68_MC3_HW_SUSP 0x10
-#define PD68_MC3_MM_EXPAND 0x40
-#define PD68_MC3_MM_ARM 0x80
-
-/* Bridge Control Register */
-#define PD6832_BCR_MGMT_IRQ_ENA 0x0800
-
-/* Socket Number Register */
-#define PD6832_SOCKET_NUMBER 0x004c /* 8 bit */
-
-
-typedef struct cirrus_state_t {
- u_char misc1, misc2;
- u_char timer[6];
-} cirrus_state_t;
-
-/* Cirrus options */
-static int has_dma = -1;
-static int has_led = -1;
-static int has_ring = -1;
-static int dynamic_mode = 0;
-static int freq_bypass = -1;
-#ifdef CONFIG_CPC45
-static int setup_time = 2;
-static int cmd_time = 6;
-static int recov_time = 1;
-#else
-static int setup_time = -1;
-static int cmd_time = -1;
-static int recov_time = -1;
-#endif
-
-
-#endif /* _LINUX_CIRRUS_H */
diff --git a/include/pcmcia/i82365.h b/include/pcmcia/i82365.h
deleted file mode 100644
index 0b432a8..0000000
--- a/include/pcmcia/i82365.h
+++ /dev/null
@@ -1,154 +0,0 @@
-/*
- * i82365.h 1.21 2001/08/24 12:15:33
- *
- * The contents of this file are subject to the Mozilla Public License
- * Version 1.1 (the "License"); you may not use this file except in
- * compliance with the License. You may obtain a copy of the License
- * at http://www.mozilla.org/MPL/
- *
- * Software distributed under the License is distributed on an "AS IS"
- * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
- * the License for the specific language governing rights and
- * limitations under the License.
- *
- * The initial developer of the original code is David A. Hinds
- * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
- * are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
- *
- * Alternatively, the contents of this file may be used under the
- * terms of the GNU General Public License version 2 (the "GPL"), in
- * which case the provisions of the GPL are applicable instead of the
- * above. If you wish to allow the use of your version of this file
- * only under the terms of the GPL and not to allow others to use
- * your version of this file under the MPL, indicate your decision by
- * deleting the provisions above and replace them with the notice and
- * other provisions required by the GPL. If you do not delete the
- * provisions above, a recipient may use your version of this file
- * under either the MPL or the GPL.
- */
-
-#ifndef _LINUX_I82365_H
-#define _LINUX_I82365_H
-
-/* register definitions for the Intel 82365SL PCMCIA controller */
-
-/* Offsets for PCIC registers */
-#define I365_IDENT 0x00 /* Identification and revision */
-#define I365_STATUS 0x01 /* Interface status */
-#define I365_POWER 0x02 /* Power and RESETDRV control */
-#define I365_INTCTL 0x03 /* Interrupt and general control */
-#define I365_CSC 0x04 /* Card status change */
-#define I365_CSCINT 0x05 /* Card status change interrupt control */
-#define I365_ADDRWIN 0x06 /* Address window enable */
-#define I365_IOCTL 0x07 /* I/O control */
-#define I365_GENCTL 0x16 /* Card detect and general control */
-#define I365_GBLCTL 0x1E /* Global control register */
-
-/* Offsets for I/O and memory window registers */
-#define I365_IO(map) (0x08+((map)<<2))
-#define I365_MEM(map) (0x10+((map)<<3))
-#define I365_W_START 0
-#define I365_W_STOP 2
-#define I365_W_OFF 4
-
-/* Flags for I365_STATUS */
-#define I365_CS_BVD1 0x01
-#define I365_CS_STSCHG 0x01
-#define I365_CS_BVD2 0x02
-#define I365_CS_SPKR 0x02
-#define I365_CS_DETECT 0x0C
-#define I365_CS_WRPROT 0x10
-#define I365_CS_READY 0x20 /* Inverted */
-#define I365_CS_POWERON 0x40
-#define I365_CS_GPI 0x80
-
-/* Flags for I365_POWER */
-#define I365_PWR_OFF 0x00 /* Turn off the socket */
-#define I365_PWR_OUT 0x80 /* Output enable */
-#define I365_PWR_NORESET 0x40 /* Disable RESETDRV on resume */
-#define I365_PWR_AUTO 0x20 /* Auto pwr switch enable */
-#define I365_VCC_MASK 0x18 /* Mask for turning off Vcc */
-/* There are different layouts for B-step and DF-step chips: the B
- step has independent Vpp1/Vpp2 control, and the DF step has only
- Vpp1 control, plus 3V control */
-#define I365_VCC_5V 0x10 /* Vcc = 5.0v */
-#define I365_VCC_3V 0x18 /* Vcc = 3.3v */
-#define I365_VPP2_MASK 0x0c /* Mask for turning off Vpp2 */
-#define I365_VPP2_5V 0x04 /* Vpp2 = 5.0v */
-#define I365_VPP2_12V 0x08 /* Vpp2 = 12.0v */
-#define I365_VPP1_MASK 0x03 /* Mask for turning off Vpp1 */
-#define I365_VPP1_5V 0x01 /* Vpp2 = 5.0v */
-#define I365_VPP1_12V 0x02 /* Vpp2 = 12.0v */
-
-/* Flags for I365_INTCTL */
-#define I365_RING_ENA 0x80
-#define I365_PC_RESET 0x40
-#define I365_PC_IOCARD 0x20
-#define I365_INTR_ENA 0x10
-#define I365_IRQ_MASK 0x0F
-
-/* Flags for I365_CSC and I365_CSCINT*/
-#define I365_CSC_BVD1 0x01
-#define I365_CSC_STSCHG 0x01
-#define I365_CSC_BVD2 0x02
-#define I365_CSC_READY 0x04
-#define I365_CSC_DETECT 0x08
-#define I365_CSC_ANY 0x0F
-#define I365_CSC_GPI 0x10
-
-/* Flags for I365_ADDRWIN */
-#define I365_ADDR_MEMCS16 0x20
-#define I365_ENA_IO(map) (0x40 << (map))
-#define I365_ENA_MEM(map) (0x01 << (map))
-
-/* Flags for I365_IOCTL */
-#define I365_IOCTL_MASK(map) (0x0F << (map<<2))
-#define I365_IOCTL_WAIT(map) (0x08 << (map<<2))
-#define I365_IOCTL_0WS(map) (0x04 << (map<<2))
-#define I365_IOCTL_IOCS16(map) (0x02 << (map<<2))
-#define I365_IOCTL_16BIT(map) (0x01 << (map<<2))
-
-/* Flags for I365_GENCTL */
-#define I365_CTL_16DELAY 0x01
-#define I365_CTL_RESET 0x02
-#define I365_CTL_GPI_ENA 0x04
-#define I365_CTL_GPI_CTL 0x08
-#define I365_CTL_RESUME 0x10
-#define I365_CTL_SW_IRQ 0x20
-
-/* Flags for I365_GBLCTL */
-#define I365_GBL_PWRDOWN 0x01
-#define I365_GBL_CSC_LEV 0x02
-#define I365_GBL_WRBACK 0x04
-#define I365_GBL_IRQ_0_LEV 0x08
-#define I365_GBL_IRQ_1_LEV 0x10
-
-/* Flags for memory window registers */
-#define I365_MEM_16BIT 0x8000 /* In memory start high byte */
-#define I365_MEM_0WS 0x4000
-#define I365_MEM_WS1 0x8000 /* In memory stop high byte */
-#define I365_MEM_WS0 0x4000
-#define I365_MEM_WRPROT 0x8000 /* In offset high byte */
-#define I365_MEM_REG 0x4000
-
-#define I365_REG(slot, reg) (((slot) << 6) | (reg))
-
-/* Default ISA interrupt mask */
-#define I365_ISA_IRQ_MASK 0xdeb8 /* irq's 3-5,7,9-12,14,15 */
-
-/* Device ID's for PCI-to-PCMCIA bridges */
-
-#ifndef PCI_VENDOR_ID_INTEL
-#define PCI_VENDOR_ID_INTEL 0x8086
-#endif
-#ifndef PCI_DEVICE_ID_INTEL_82092AA_0
-#define PCI_DEVICE_ID_INTEL_82092AA_0 0x1221
-#endif
-#ifndef PCI_VENDOR_ID_OMEGA
-#define PCI_VENDOR_ID_OMEGA 0x119b
-#endif
-#ifndef PCI_DEVICE_ID_OMEGA_82C092G
-#define PCI_DEVICE_ID_OMEGA_82C092G 0x1221
-#endif
-
-#endif /* _LINUX_I82365_H */
diff --git a/include/pcmcia/ss.h b/include/pcmcia/ss.h
deleted file mode 100644
index aafae8a..0000000
--- a/include/pcmcia/ss.h
+++ /dev/null
@@ -1,133 +0,0 @@
-/*
- * ss.h 1.31 2001/08/24 12:16:13
- *
- * The contents of this file are subject to the Mozilla Public License
- * Version 1.1 (the "License"); you may not use this file except in
- * compliance with the License. You may obtain a copy of the License
- * at http://www.mozilla.org/MPL/
- *
- * Software distributed under the License is distributed on an "AS IS"
- * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
- * the License for the specific language governing rights and
- * limitations under the License.
- *
- * The initial developer of the original code is David A. Hinds
- * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
- * are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
- *
- * Alternatively, the contents of this file may be used under the
- * terms of the GNU General Public License version 2 (the "GPL"), in
- * which case the provisions of the GPL are applicable instead of the
- * above. If you wish to allow the use of your version of this file
- * only under the terms of the GPL and not to allow others to use
- * your version of this file under the MPL, indicate your decision by
- * deleting the provisions above and replace them with the notice and
- * other provisions required by the GPL. If you do not delete the
- * provisions above, a recipient may use your version of this file
- * under either the MPL or the GPL.
- */
-
-#ifndef _LINUX_SS_H
-#define _LINUX_SS_H
-
-/* For RegisterCallback */
-typedef struct ss_callback_t {
- void (*handler)(void *info, u_int events);
- void *info;
-} ss_callback_t;
-
-/* Definitions for card status flags for GetStatus */
-#define SS_WRPROT 0x0001
-#define SS_CARDLOCK 0x0002
-#define SS_EJECTION 0x0004
-#define SS_INSERTION 0x0008
-#define SS_BATDEAD 0x0010
-#define SS_BATWARN 0x0020
-#define SS_READY 0x0040
-#define SS_DETECT 0x0080
-#define SS_POWERON 0x0100
-#define SS_GPI 0x0200
-#define SS_STSCHG 0x0400
-#define SS_CARDBUS 0x0800
-#define SS_3VCARD 0x1000
-#define SS_XVCARD 0x2000
-#define SS_PENDING 0x4000
-
-/* for InquireSocket */
-typedef struct socket_cap_t {
- u_int features;
- u_int irq_mask;
- u_int map_size;
- u_char pci_irq;
- u_char cardbus;
- struct pci_bus *cb_bus;
- struct bus_operations *bus;
-} socket_cap_t;
-
-/* InquireSocket capabilities */
-#define SS_CAP_PAGE_REGS 0x0001
-#define SS_CAP_VIRTUAL_BUS 0x0002
-#define SS_CAP_MEM_ALIGN 0x0004
-#define SS_CAP_STATIC_MAP 0x0008
-#define SS_CAP_PCCARD 0x4000
-#define SS_CAP_CARDBUS 0x8000
-
-/* for GetSocket, SetSocket */
-typedef struct socket_state_t {
- u_int flags;
- u_int csc_mask;
- u_char Vcc, Vpp;
- u_char io_irq;
-} socket_state_t;
-
-/* Socket configuration flags */
-#define SS_PWR_AUTO 0x0010
-#define SS_IOCARD 0x0020
-#define SS_RESET 0x0040
-#define SS_DMA_MODE 0x0080
-#define SS_SPKR_ENA 0x0100
-#define SS_OUTPUT_ENA 0x0200
-#define SS_ZVCARD 0x0400
-
-/* Flags for I/O port and memory windows */
-#define MAP_ACTIVE 0x01
-#define MAP_16BIT 0x02
-#define MAP_AUTOSZ 0x04
-#define MAP_0WS 0x08
-#define MAP_WRPROT 0x10
-#define MAP_ATTRIB 0x20
-#define MAP_USE_WAIT 0x40
-#define MAP_PREFETCH 0x80
-
-/* Use this just for bridge windows */
-#define MAP_IOSPACE 0x20
-
-typedef struct pccard_io_map {
- u_char map;
- u_char flags;
- u_short speed;
- u_short start, stop;
-} pccard_io_map;
-
-typedef struct pccard_mem_map {
- u_char map;
- u_char flags;
- u_short speed;
- u_long sys_start, sys_stop;
- u_int card_start;
-} pccard_mem_map;
-
-typedef struct cb_bridge_map {
- u_char map;
- u_char flags;
- u_int start, stop;
-} cb_bridge_map;
-
-enum ss_service {
- SS_RegisterCallback, SS_InquireSocket,
- SS_GetStatus, SS_GetSocket, SS_SetSocket,
- SS_GetIOMap, SS_SetIOMap, SS_GetMemMap, SS_SetMemMap,
- SS_GetBridge, SS_SetBridge, SS_ProcSetup
-};
-
-#endif /* _LINUX_SS_H */
diff --git a/include/pcmcia/ti113x.h b/include/pcmcia/ti113x.h
deleted file mode 100644
index 5453588..0000000
--- a/include/pcmcia/ti113x.h
+++ /dev/null
@@ -1,234 +0,0 @@
-/*
- * ti113x.h 1.31 2002/05/12 18:19:47
- *
- * The contents of this file are subject to the Mozilla Public License
- * Version 1.1 (the "License"); you may not use this file except in
- * compliance with the License. You may obtain a copy of the License
- * at http://www.mozilla.org/MPL/
- *
- * Software distributed under the License is distributed on an "AS IS"
- * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
- * the License for the specific language governing rights and
- * limitations under the License.
- *
- * The initial developer of the original code is David A. Hinds
- * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
- * are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
- *
- * Alternatively, the contents of this file may be used under the
- * terms of the GNU General Public License version 2 (the "GPL"), in
- * which case the provisions of the GPL are applicable instead of the
- * above. If you wish to allow the use of your version of this file
- * only under the terms of the GPL and not to allow others to use
- * your version of this file under the MPL, indicate your decision by
- * deleting the provisions above and replace them with the notice and
- * other provisions required by the GPL. If you do not delete the
- * provisions above, a recipient may use your version of this file
- * under either the MPL or the GPL.
- */
-
-#ifndef _LINUX_TI113X_H
-#define _LINUX_TI113X_H
-
-#ifndef PCI_VENDOR_ID_TI
-#define PCI_VENDOR_ID_TI 0x104c
-#endif
-
-#ifndef PCI_DEVICE_ID_TI_1130
-#define PCI_DEVICE_ID_TI_1130 0xac12
-#endif
-#ifndef PCI_DEVICE_ID_TI_1031
-#define PCI_DEVICE_ID_TI_1031 0xac13
-#endif
-#ifndef PCI_DEVICE_ID_TI_1131
-#define PCI_DEVICE_ID_TI_1131 0xac15
-#endif
-#ifndef PCI_DEVICE_ID_TI_1210
-#define PCI_DEVICE_ID_TI_1210 0xac1a
-#endif
-#ifndef PCI_DEVICE_ID_TI_1211
-#define PCI_DEVICE_ID_TI_1211 0xac1e
-#endif
-#ifndef PCI_DEVICE_ID_TI_1220
-#define PCI_DEVICE_ID_TI_1220 0xac17
-#endif
-#ifndef PCI_DEVICE_ID_TI_1221
-#define PCI_DEVICE_ID_TI_1221 0xac19
-#endif
-#ifndef PCI_DEVICE_ID_TI_1250A
-#define PCI_DEVICE_ID_TI_1250A 0xac16
-#endif
-#ifndef PCI_DEVICE_ID_TI_1225
-#define PCI_DEVICE_ID_TI_1225 0xac1c
-#endif
-#ifndef PCI_DEVICE_ID_TI_1251A
-#define PCI_DEVICE_ID_TI_1251A 0xac1d
-#endif
-#ifndef PCI_DEVICE_ID_TI_1251B
-#define PCI_DEVICE_ID_TI_1251B 0xac1f
-#endif
-#ifndef PCI_DEVICE_ID_TI_1410
-#define PCI_DEVICE_ID_TI_1410 0xac50
-#endif
-#ifndef PCI_DEVICE_ID_TI_1420
-#define PCI_DEVICE_ID_TI_1420 0xac51
-#endif
-#ifndef PCI_DEVICE_ID_TI_1450
-#define PCI_DEVICE_ID_TI_1450 0xac1b
-#endif
-#ifndef PCI_DEVICE_ID_TI_1451
-#define PCI_DEVICE_ID_TI_1451 0xac52
-#endif
-#ifndef PCI_DEVICE_ID_TI_1510
-#define PCI_DEVICE_ID_TI_1510 0xac56
-#endif
-#ifndef PCI_DEVICE_ID_TI_4410
-#define PCI_DEVICE_ID_TI_4410 0xac41
-#endif
-#ifndef PCI_DEVICE_ID_TI_4450
-#define PCI_DEVICE_ID_TI_4450 0xac40
-#endif
-#ifndef PCI_DEVICE_ID_TI_4451
-#define PCI_DEVICE_ID_TI_4451 0xac42
-#endif
-
-/* Register definitions for TI 113X PCI-to-CardBus bridges */
-
-/* System Control Register */
-#define TI113X_SYSTEM_CONTROL 0x80 /* 32 bit */
-#define TI113X_SCR_SMIROUTE 0x04000000
-#define TI113X_SCR_SMISTATUS 0x02000000
-#define TI113X_SCR_SMIENB 0x01000000
-#define TI113X_SCR_VCCPROT 0x00200000
-#define TI113X_SCR_REDUCEZV 0x00100000
-#define TI113X_SCR_CDREQEN 0x00080000
-#define TI113X_SCR_CDMACHAN 0x00070000
-#define TI113X_SCR_SOCACTIVE 0x00002000
-#define TI113X_SCR_PWRSTREAM 0x00000800
-#define TI113X_SCR_DELAYUP 0x00000400
-#define TI113X_SCR_DELAYDOWN 0x00000200
-#define TI113X_SCR_INTERROGATE 0x00000100
-#define TI113X_SCR_CLKRUN_SEL 0x00000080
-#define TI113X_SCR_PWRSAVINGS 0x00000040
-#define TI113X_SCR_SUBSYSRW 0x00000020
-#define TI113X_SCR_CB_DPAR 0x00000010
-#define TI113X_SCR_CDMA_EN 0x00000008
-#define TI113X_SCR_ASYNC_IRQ 0x00000004
-#define TI113X_SCR_KEEPCLK 0x00000002
-#define TI113X_SCR_CLKRUN_ENA 0x00000001
-
-#define TI122X_SCR_SER_STEP 0xc0000000
-#define TI122X_SCR_INTRTIE 0x20000000
-#define TI122X_SCR_P2CCLK 0x08000000
-#define TI122X_SCR_CBRSVD 0x00400000
-#define TI122X_SCR_MRBURSTDN 0x00008000
-#define TI122X_SCR_MRBURSTUP 0x00004000
-#define TI122X_SCR_RIMUX 0x00000001
-
-/* Multimedia Control Register */
-#define TI1250_MULTIMEDIA_CTL 0x84 /* 8 bit */
-#define TI1250_MMC_ZVOUTEN 0x80
-#define TI1250_MMC_PORTSEL 0x40
-#define TI1250_MMC_ZVEN1 0x02
-#define TI1250_MMC_ZVEN0 0x01
-
-#define TI1250_GENERAL_STATUS 0x85 /* 8 bit */
-#define TI1250_GPIO0_CONTROL 0x88 /* 8 bit */
-#define TI1250_GPIO1_CONTROL 0x89 /* 8 bit */
-#define TI1250_GPIO2_CONTROL 0x8a /* 8 bit */
-#define TI1250_GPIO3_CONTROL 0x8b /* 8 bit */
-#define TI12XX_IRQMUX 0x8c /* 32 bit */
-
-/* Retry Status Register */
-#define TI113X_RETRY_STATUS 0x90 /* 8 bit */
-#define TI113X_RSR_PCIRETRY 0x80
-#define TI113X_RSR_CBRETRY 0x40
-#define TI113X_RSR_TEXP_CBB 0x20
-#define TI113X_RSR_MEXP_CBB 0x10
-#define TI113X_RSR_TEXP_CBA 0x08
-#define TI113X_RSR_MEXP_CBA 0x04
-#define TI113X_RSR_TEXP_PCI 0x02
-#define TI113X_RSR_MEXP_PCI 0x01
-
-/* Card Control Register */
-#define TI113X_CARD_CONTROL 0x91 /* 8 bit */
-#define TI113X_CCR_RIENB 0x80
-#define TI113X_CCR_ZVENABLE 0x40
-#define TI113X_CCR_PCI_IRQ_ENA 0x20
-#define TI113X_CCR_PCI_IREQ 0x10
-#define TI113X_CCR_PCI_CSC 0x08
-#define TI113X_CCR_SPKROUTEN 0x02
-#define TI113X_CCR_IFG 0x01
-
-#define TI1220_CCR_PORT_SEL 0x20
-#define TI122X_CCR_AUD2MUX 0x04
-
-/* Device Control Register */
-#define TI113X_DEVICE_CONTROL 0x92 /* 8 bit */
-#define TI113X_DCR_5V_FORCE 0x40
-#define TI113X_DCR_3V_FORCE 0x20
-#define TI113X_DCR_IMODE_MASK 0x06
-#define TI113X_DCR_IMODE_ISA 0x02
-#define TI113X_DCR_IMODE_SERIAL 0x04
-
-#define TI12XX_DCR_IMODE_PCI_ONLY 0x00
-#define TI12XX_DCR_IMODE_ALL_SERIAL 0x06
-
-/* Buffer Control Register */
-#define TI113X_BUFFER_CONTROL 0x93 /* 8 bit */
-#define TI113X_BCR_CB_READ_DEPTH 0x08
-#define TI113X_BCR_CB_WRITE_DEPTH 0x04
-#define TI113X_BCR_PCI_READ_DEPTH 0x02
-#define TI113X_BCR_PCI_WRITE_DEPTH 0x01
-
-/* Diagnostic Register */
-#define TI1250_DIAGNOSTIC 0x93 /* 8 bit */
-#define TI1250_DIAG_TRUE_VALUE 0x80
-#define TI1250_DIAG_PCI_IREQ 0x40
-#define TI1250_DIAG_PCI_CSC 0x20
-#define TI1250_DIAG_ASYNC_CSC 0x01
-
-/* DMA Registers */
-#define TI113X_DMA_0 0x94 /* 32 bit */
-#define TI113X_DMA_1 0x98 /* 32 bit */
-
-/* ExCA IO offset registers */
-#define TI113X_IO_OFFSET(map) (0x36+((map)<<1))
-
-/* Data structure for tracking vendor-specific state */
-typedef struct ti113x_state_t {
- u32 sysctl; /* TI113X_SYSTEM_CONTROL */
- u8 cardctl; /* TI113X_CARD_CONTROL */
- u8 devctl; /* TI113X_DEVICE_CONTROL */
- u8 diag; /* TI1250_DIAGNOSTIC */
- u32 irqmux; /* TI12XX_IRQMUX */
-} ti113x_state_t;
-
-#define TI_PCIC_ID \
- IS_TI1130, IS_TI1131, IS_TI1031, IS_TI1210, IS_TI1211, \
- IS_TI1220, IS_TI1221, IS_TI1225, IS_TI1250A, IS_TI1251A, \
- IS_TI1251B, IS_TI1410, IS_TI1420, IS_TI1450, IS_TI1451, \
- IS_TI1510, IS_TI4410, IS_TI4450, IS_TI4451
-
-#define TI_PCIC_INFO \
- { "TI 1130", IS_TI|IS_CARDBUS, ID(TI, 1130) }, \
- { "TI 1131", IS_TI|IS_CARDBUS, ID(TI, 1131) }, \
- { "TI 1031", IS_TI|IS_CARDBUS, ID(TI, 1031) }, \
- { "TI 1210", IS_TI|IS_CARDBUS, ID(TI, 1210) }, \
- { "TI 1211", IS_TI|IS_CARDBUS, ID(TI, 1211) }, \
- { "TI 1220", IS_TI|IS_CARDBUS, ID(TI, 1220) }, \
- { "TI 1221", IS_TI|IS_CARDBUS, ID(TI, 1221) }, \
- { "TI 1225", IS_TI|IS_CARDBUS, ID(TI, 1225) }, \
- { "TI 1250A", IS_TI|IS_CARDBUS, ID(TI, 1250A) }, \
- { "TI 1251A", IS_TI|IS_CARDBUS, ID(TI, 1251A) }, \
- { "TI 1251B", IS_TI|IS_CARDBUS, ID(TI, 1251B) }, \
- { "TI 1410", IS_TI|IS_CARDBUS, ID(TI, 1410) }, \
- { "TI 1420", IS_TI|IS_CARDBUS, ID(TI, 1420) }, \
- { "TI 1450", IS_TI|IS_CARDBUS, ID(TI, 1450) }, \
- { "TI 1451", IS_TI|IS_CARDBUS, ID(TI, 1451) }, \
- { "TI 1510", IS_TI|IS_CARDBUS, ID(TI, 1510) }, \
- { "TI 4410", IS_TI|IS_CARDBUS, ID(TI, 4410) }, \
- { "TI 4450", IS_TI|IS_CARDBUS, ID(TI, 4450) }, \
- { "TI 4451", IS_TI|IS_CARDBUS, ID(TI, 4451) }
-
-#endif /* _LINUX_TI113X_H */
diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl
index 5fcef9c..36d5975 100644
--- a/include/ppc_asm.tmpl
+++ b/include/ppc_asm.tmpl
@@ -80,7 +80,7 @@
#define r31 31
-#if defined(CONFIG_8xx) || defined(CONFIG_MPC824X)
+#if defined(CONFIG_8xx)
/* Some special registers */
@@ -92,7 +92,7 @@
#define LCTRL2 157 /* Load/Store Support (37-41) */
#define ICTRL 158
-#endif /* CONFIG_8xx, CONFIG_MPC824X */
+#endif /* CONFIG_8xx */
#if defined(CONFIG_5xx)
diff --git a/post/drivers/memory.c b/post/drivers/memory.c
index d94a437..d512fa5 100644
--- a/post/drivers/memory.c
+++ b/post/drivers/memory.c
@@ -170,7 +170,7 @@ DECLARE_GLOBAL_DATA_PTR;
*/
static void move64(const unsigned long long *src, unsigned long long *dest)
{
-#if defined(CONFIG_MPC8260) || defined(CONFIG_MPC824X)
+#if defined(CONFIG_MPC8260)
asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */
"stfd 0, 0(4)" /* *dest = fpr0 */
: : : "fr0" ); /* Clobbers fr0 */
--
1.9.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [U-Boot] [PATCH 26/26] powerpc: mpc824x: remove MPC824X cpu support
2014-12-15 14:26 ` [U-Boot] [PATCH 26/26] powerpc: mpc824x: remove MPC824X cpu support Masahiro Yamada
@ 2014-12-15 16:46 ` York Sun
2015-01-05 18:22 ` Tom Rini
1 sibling, 0 replies; 55+ messages in thread
From: York Sun @ 2014-12-15 16:46 UTC (permalink / raw)
To: u-boot
On 12/15/2014 06:26 AM, Masahiro Yamada wrote:
> All the MPC824X boards are still non-generic boards:
> A3000, CPC45, CU824, eXalion, MVBLUE, MUSENKI, Sandpoint824x, utx8245
>
> Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
> Cc: Wolfgang Denk <wd@denx.de>
> Cc: Josef Wagner <Wagner@Microsys.de>
> Cc: Torsten Demke <torsten.demke@fci.com>
> Cc: Jim Thompson <jim@musenki.com>
> Cc: Greg Allen <gallen@arlut.utexas.edu>
> ---
>
824x is more than 10 years old. We can remove them if they are not maintained.
York
^ permalink raw reply [flat|nested] 55+ messages in thread
* [U-Boot] [PATCH 26/26] powerpc: mpc824x: remove MPC824X cpu support
2014-12-15 14:26 ` [U-Boot] [PATCH 26/26] powerpc: mpc824x: remove MPC824X cpu support Masahiro Yamada
2014-12-15 16:46 ` York Sun
@ 2015-01-05 18:22 ` Tom Rini
1 sibling, 0 replies; 55+ messages in thread
From: Tom Rini @ 2015-01-05 18:22 UTC (permalink / raw)
To: u-boot
On Mon, Dec 15, 2014 at 11:26:31PM +0900, Masahiro Yamada wrote:
> All the MPC824X boards are still non-generic boards:
> A3000, CPC45, CU824, eXalion, MVBLUE, MUSENKI, Sandpoint824x, utx8245
>
> Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
> Cc: Wolfgang Denk <wd@denx.de>
> Cc: Josef Wagner <Wagner@Microsys.de>
> Cc: Torsten Demke <torsten.demke@fci.com>
> Cc: Jim Thompson <jim@musenki.com>
> Cc: Greg Allen <gallen@arlut.utexas.edu>
Applied to u-boot/master, thanks!
--
Tom
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* [U-Boot] [PATCH 0/26] Start removing non-generic boards
2014-12-15 14:26 [U-Boot] [PATCH 0/26] Start removing non-generic boards Masahiro Yamada
` (25 preceding siblings ...)
2014-12-15 14:26 ` [U-Boot] [PATCH 26/26] powerpc: mpc824x: remove MPC824X cpu support Masahiro Yamada
@ 2015-01-05 15:44 ` Masahiro YAMADA
2015-01-05 18:28 ` Tom Rini
27 siblings, 0 replies; 55+ messages in thread
From: Masahiro YAMADA @ 2015-01-05 15:44 UTC (permalink / raw)
To: u-boot
Hi Tom,
Is this series applicable by the 2015.01 release?
The dead line of the conversion has passed.
I built the other PowerPC boards and I confirmed that
this series has no impact on them.
2014-12-15 23:26 GMT+09:00 Masahiro Yamada <yamada.m@jp.panasonic.com>:
>
> As doc/README.generic-board says, the dead line has already expired
> and we are supposed to remove all the non-generic boards by the
> end of this year.
>
> This series removes non-generic boards of mpc8xx, mpc8260, mpc824x
> platform.
>
>
>
> Masahiro Yamada (26):
> mpc8xx: remove FPS{850,860}L, NSCU, SM850, TK885D, virtlab2 support
> powerpc: manroland: remove uc100, uc101, mucmc52, hmi1001 support
> mpc8xx: remove ELPT860 board support
> mpc8xx: remove KUP4X, KUP4K board support
> mpc8xx: remove SPD823TS board support
> mpc8xx: remove RRvision board support
> mpc8xx: remove R360MPI board support
> mpc8xx: remove NETVIA board support
> mpc8xx: remove lwmon board support
> mpc8xx: remove IVMS8, IVML24 board support
> mpc8xx: remove IP860 board support
> mpc8xx: remove ESTEEM192E board support
> powerpc: remove cogent_8xx, cogent_mpc8260 board support
> mpc8260: remove sacsng board support
> mpc8260: remove ppmc8260 board support
> mpc8260: remove ep8260 board support
> mpc8260: remove VoVPN-GW board support
> mpc8260: remove MPC8266ADS board support
> mpc8260: remove PM825, PM826, PM828 board support
> mpc8260: remove muas3001 board support
> mpc8260: remove IPHASE4539 board support
> mpc8260: remove gw8260 board support
> mpc8260: remove ep82xxm board support
> mpc8260: remove CPU86, CPU87 board support
> mpc8260: remove atc board support
> powerpc: mpc824x: remove MPC824X cpu support
>
> MAKEALL | 6 -
> README | 5 -
> arch/powerpc/Kconfig | 4 -
> arch/powerpc/cpu/mpc5xxx/Kconfig | 12 -
> arch/powerpc/cpu/mpc5xxx/ide.c | 8 -
> arch/powerpc/cpu/mpc824x/Kconfig | 48 -
> arch/powerpc/cpu/mpc824x/Makefile | 11 -
> arch/powerpc/cpu/mpc824x/config.mk | 8 -
> arch/powerpc/cpu/mpc824x/cpu.c | 262 -----
> arch/powerpc/cpu/mpc824x/cpu_init.c | 311 ------
> arch/powerpc/cpu/mpc824x/drivers/epic.h | 1 -
> arch/powerpc/cpu/mpc824x/drivers/epic/README | 102 --
> arch/powerpc/cpu/mpc824x/drivers/epic/epic.h | 163 ----
> arch/powerpc/cpu/mpc824x/drivers/epic/epic1.c | 517 ----------
> arch/powerpc/cpu/mpc824x/drivers/epic/epic2.S | 196 ----
> arch/powerpc/cpu/mpc824x/drivers/epic/epicutil.S | 57 --
> arch/powerpc/cpu/mpc824x/drivers/errors.h | 212 ----
> arch/powerpc/cpu/mpc824x/drivers/i2c/i2c.c | 254 -----
> arch/powerpc/cpu/mpc824x/interrupts.c | 77 --
> arch/powerpc/cpu/mpc824x/pci.c | 75 --
> arch/powerpc/cpu/mpc824x/speed.c | 102 --
> arch/powerpc/cpu/mpc824x/start.S | 724 --------------
> arch/powerpc/cpu/mpc824x/traps.c | 194 ----
> arch/powerpc/cpu/mpc824x/u-boot.lds | 76 --
> arch/powerpc/cpu/mpc8260/Kconfig | 60 --
> arch/powerpc/cpu/mpc8260/cpu_init.c | 4 -
> arch/powerpc/cpu/mpc8260/pci.c | 64 --
> arch/powerpc/cpu/mpc8260/start.S | 61 --
> arch/powerpc/cpu/mpc8xx/Kconfig | 73 --
> arch/powerpc/cpu/mpc8xx/cpu.c | 57 +-
> arch/powerpc/cpu/mpc8xx/cpu_init.c | 15 -
> arch/powerpc/cpu/mpc8xx/i2c.c | 7 -
> arch/powerpc/cpu/mpc8xx/scc.c | 24 -
> arch/powerpc/cpu/mpc8xx/serial.c | 23 +-
> arch/powerpc/cpu/mpc8xx/video.c | 148 ---
> arch/powerpc/include/asm/global_data.h | 2 +-
> arch/powerpc/include/asm/processor.h | 2 -
> board/LEOX/elpt860/Kconfig | 12 -
> board/LEOX/elpt860/MAINTAINERS | 6 -
> board/LEOX/elpt860/Makefile | 21 -
> board/LEOX/elpt860/README.LEOX | 423 --------
> board/LEOX/elpt860/elpt860.c | 336 -------
> board/LEOX/elpt860/flash.c | 602 ------------
> board/LEOX/elpt860/u-boot.lds | 103 --
> board/LEOX/elpt860/u-boot.lds.debug | 126 ---
> board/RRvision/Kconfig | 9 -
> board/RRvision/MAINTAINERS | 7 -
> board/RRvision/Makefile | 8 -
> board/RRvision/RRvision.c | 222 -----
> board/RRvision/flash.c | 506 ----------
> board/RRvision/u-boot.lds | 87 --
> board/RRvision/video_ad7179.h | 52 -
> board/a3000/Kconfig | 9 -
> board/a3000/MAINTAINERS | 6 -
> board/a3000/Makefile | 8 -
> board/a3000/README | 17 -
> board/a3000/a3000.c | 101 --
> board/a3000/flash.c | 438 ---------
> board/atc/Kconfig | 9 -
> board/atc/MAINTAINERS | 6 -
> board/atc/Makefile | 8 -
> board/atc/atc.c | 382 --------
> board/atc/flash.c | 647 -------------
> board/atc/ti113x.c | 620 ------------
> board/cogent/Kconfig | 19 -
> board/cogent/MAINTAINERS | 8 -
> board/cogent/Makefile | 8 -
> board/cogent/README | 118 ---
> board/cogent/README.cma286 | 69 --
> board/cogent/dipsw.c | 50 -
> board/cogent/dipsw.h | 3 -
> board/cogent/flash.c | 633 ------------
> board/cogent/flash.h | 305 ------
> board/cogent/kbm.c | 3 -
> board/cogent/lcd.c | 245 -----
> board/cogent/lcd.h | 84 --
> board/cogent/mb.c | 280 ------
> board/cogent/mb.h | 513 ----------
> board/cogent/par.c | 3 -
> board/cogent/par.h | 3 -
> board/cogent/pci.c | 3 -
> board/cogent/pci.h | 3 -
> board/cogent/rtc.c | 3 -
> board/cogent/rtc.h | 3 -
> board/cogent/serial.c | 189 ----
> board/cogent/serial.h | 15 -
> board/cogent/u-boot.lds | 86 --
> board/cogent/u-boot.lds.debug | 121 ---
> board/cpc45/Kconfig | 9 -
> board/cpc45/MAINTAINERS | 7 -
> board/cpc45/Makefile | 8 -
> board/cpc45/cpc45.c | 250 -----
> board/cpc45/flash.c | 506 ----------
> board/cpc45/ide.c | 128 ---
> board/cpc45/pd67290.c | 797 ---------------
> board/cpc45/plx9030.c | 156 ---
> board/cpu86/Kconfig | 9 -
> board/cpu86/MAINTAINERS | 7 -
> board/cpu86/Makefile | 8 -
> board/cpu86/cpu86.c | 304 ------
> board/cpu86/cpu86.h | 27 -
> board/cpu86/flash.c | 599 ------------
> board/cpu87/Kconfig | 9 -
> board/cpu87/MAINTAINERS | 7 -
> board/cpu87/Makefile | 8 -
> board/cpu87/cpu87.c | 330 -------
> board/cpu87/cpu87.h | 27 -
> board/cpu87/flash.c | 608 ------------
> board/cu824/Kconfig | 9 -
> board/cu824/MAINTAINERS | 6 -
> board/cu824/Makefile | 8 -
> board/cu824/README | 453 ---------
> board/cu824/cu824.c | 83 --
> board/cu824/flash.c | 470 ---------
> board/eXalion/Kconfig | 9 -
> board/eXalion/MAINTAINERS | 6 -
> board/eXalion/Makefile | 8 -
> board/eXalion/eXalion.c | 283 ------
> board/eXalion/eXalion.h | 36 -
> board/eXalion/piix_pci.h | 156 ---
> board/ep8260/Kconfig | 9 -
> board/ep8260/MAINTAINERS | 6 -
> board/ep8260/Makefile | 8 -
> board/ep8260/ep8260.c | 304 ------
> board/ep8260/ep8260.h | 24 -
> board/ep8260/flash.c | 395 --------
> board/ep8260/mii_phy.c | 107 ---
> board/ep82xxm/Kconfig | 9 -
> board/ep82xxm/MAINTAINERS | 6 -
> board/ep82xxm/Makefile | 8 -
> board/ep82xxm/ep82xxm.c | 274 ------
> board/esteem192e/Kconfig | 9 -
> board/esteem192e/MAINTAINERS | 6 -
> board/esteem192e/Makefile | 8 -
> board/esteem192e/esteem192e.c | 225 -----
> board/esteem192e/flash.c | 1119 ----------------------
> board/esteem192e/u-boot.lds | 90 --
> board/freescale/mpc8266ads/Kconfig | 12 -
> board/freescale/mpc8266ads/MAINTAINERS | 6 -
> board/freescale/mpc8266ads/Makefile | 8 -
> board/freescale/mpc8266ads/flash.c | 493 ----------
> board/freescale/mpc8266ads/mpc8266ads.c | 582 -----------
> board/funkwerk/vovpn-gw/Kconfig | 12 -
> board/funkwerk/vovpn-gw/MAINTAINERS | 6 -
> board/funkwerk/vovpn-gw/Makefile | 8 -
> board/funkwerk/vovpn-gw/flash.c | 436 ---------
> board/funkwerk/vovpn-gw/m88e6060.c | 249 -----
> board/funkwerk/vovpn-gw/m88e6060.h | 75 --
> board/funkwerk/vovpn-gw/vovpn-gw.c | 363 -------
> board/gw8260/Kconfig | 9 -
> board/gw8260/MAINTAINERS | 6 -
> board/gw8260/Makefile | 8 -
> board/gw8260/flash.c | 502 ----------
> board/gw8260/gw8260.c | 639 ------------
> board/ip860/Kconfig | 9 -
> board/ip860/MAINTAINERS | 6 -
> board/ip860/Makefile | 8 -
> board/ip860/flash.c | 440 ---------
> board/ip860/ip860.c | 340 -------
> board/ip860/u-boot.lds.debug | 122 ---
> board/iphase4539/Kconfig | 9 -
> board/iphase4539/MAINTAINERS | 6 -
> board/iphase4539/Makefile | 10 -
> board/iphase4539/README | 358 -------
> board/iphase4539/flash.c | 474 ---------
> board/iphase4539/iphase4539.c | 408 --------
> board/ivm/Kconfig | 19 -
> board/ivm/MAINTAINERS | 12 -
> board/ivm/Makefile | 8 -
> board/ivm/flash.c | 582 -----------
> board/ivm/ivm.c | 382 --------
> board/ivm/u-boot.lds.debug | 122 ---
> board/kup/common/flash.c | 499 ----------
> board/kup/common/kup.c | 68 --
> board/kup/common/kup.h | 40 -
> board/kup/common/load_sernum_ethaddr.c | 78 --
> board/kup/common/pcmcia.c | 221 -----
> board/kup/kup4k/Kconfig | 12 -
> board/kup/kup4k/MAINTAINERS | 6 -
> board/kup/kup4k/Makefile | 8 -
> board/kup/kup4k/kup4k.c | 289 ------
> board/kup/kup4k/u-boot.lds.debug | 121 ---
> board/kup/kup4x/Kconfig | 12 -
> board/kup/kup4x/MAINTAINERS | 6 -
> board/kup/kup4x/Makefile | 8 -
> board/kup/kup4x/kup4x.c | 185 ----
> board/kup/kup4x/u-boot.lds | 82 --
> board/kup/kup4x/u-boot.lds.debug | 121 ---
> board/lwmon/Kconfig | 9 -
> board/lwmon/MAINTAINERS | 6 -
> board/lwmon/Makefile | 8 -
> board/lwmon/README.keybd | 126 ---
> board/lwmon/flash.c | 632 ------------
> board/lwmon/lwmon.c | 1071 ---------------------
> board/lwmon/pcmcia.c | 234 -----
> board/lwmon/u-boot.lds.debug | 122 ---
> board/manroland/hmi1001/Kconfig | 12 -
> board/manroland/hmi1001/MAINTAINERS | 6 -
> board/manroland/hmi1001/Makefile | 8 -
> board/manroland/hmi1001/hmi1001.c | 301 ------
> board/manroland/mucmc52/Kconfig | 12 -
> board/manroland/mucmc52/MAINTAINERS | 6 -
> board/manroland/mucmc52/Makefile | 11 -
> board/manroland/mucmc52/mucmc52.c | 394 --------
> board/manroland/uc100/Kconfig | 12 -
> board/manroland/uc100/MAINTAINERS | 6 -
> board/manroland/uc100/Makefile | 8 -
> board/manroland/uc100/pcmcia.c | 192 ----
> board/manroland/uc100/uc100.c | 254 -----
> board/manroland/uc101/Kconfig | 12 -
> board/manroland/uc101/MAINTAINERS | 6 -
> board/manroland/uc101/Makefile | 8 -
> board/manroland/uc101/uc101.c | 367 -------
> board/muas3001/Kconfig | 9 -
> board/muas3001/MAINTAINERS | 7 -
> board/muas3001/Makefile | 8 -
> board/muas3001/muas3001.c | 335 -------
> board/musenki/Kconfig | 9 -
> board/musenki/MAINTAINERS | 6 -
> board/musenki/Makefile | 8 -
> board/musenki/README | 298 ------
> board/musenki/flash.c | 496 ----------
> board/musenki/musenki.c | 94 --
> board/mvblue/Kconfig | 9 -
> board/mvblue/MAINTAINERS | 6 -
> board/mvblue/Makefile | 8 -
> board/mvblue/flash.c | 570 -----------
> board/mvblue/mvblue.c | 253 -----
> board/mvblue/u-boot.lds | 86 --
> board/netvia/Kconfig | 9 -
> board/netvia/MAINTAINERS | 7 -
> board/netvia/Makefile | 8 -
> board/netvia/flash.c | 495 ----------
> board/netvia/netvia.c | 401 --------
> board/netvia/u-boot.lds.debug | 121 ---
> board/pm826/Kconfig | 9 -
> board/pm826/MAINTAINERS | 13 -
> board/pm826/Makefile | 8 -
> board/pm826/flash.c | 370 -------
> board/pm826/pm826.c | 319 ------
> board/pm828/Kconfig | 9 -
> board/pm828/MAINTAINERS | 9 -
> board/pm828/Makefile | 8 -
> board/pm828/flash.c | 370 -------
> board/pm828/pm828.c | 352 -------
> board/ppmc8260/Kconfig | 9 -
> board/ppmc8260/MAINTAINERS | 6 -
> board/ppmc8260/Makefile | 8 -
> board/ppmc8260/ppmc8260.c | 291 ------
> board/r360mpi/Kconfig | 9 -
> board/r360mpi/MAINTAINERS | 6 -
> board/r360mpi/Makefile | 8 -
> board/r360mpi/flash.c | 468 ---------
> board/r360mpi/pcmcia.c | 232 -----
> board/r360mpi/r360mpi.c | 403 --------
> board/r360mpi/u-boot.lds | 89 --
> board/sacsng/Kconfig | 9 -
> board/sacsng/MAINTAINERS | 6 -
> board/sacsng/Makefile | 8 -
> board/sacsng/clkinit.c | 1009 -------------------
> board/sacsng/clkinit.h | 103 --
> board/sacsng/flash.c | 507 ----------
> board/sacsng/ioconfig.h | 217 -----
> board/sacsng/sacsng.c | 848 ----------------
> board/sandpoint/Kconfig | 19 -
> board/sandpoint/MAINTAINERS | 12 -
> board/sandpoint/Makefile | 8 -
> board/sandpoint/README | 411 --------
> board/sandpoint/dinkdl | 2 -
> board/sandpoint/flash.c | 748 ---------------
> board/sandpoint/sandpoint.c | 91 --
> board/sandpoint/u-boot.lds | 84 --
> board/spd8xx/Kconfig | 9 -
> board/spd8xx/MAINTAINERS | 6 -
> board/spd8xx/Makefile | 8 -
> board/spd8xx/flash.c | 41 -
> board/spd8xx/spd8xx.c | 278 ------
> board/spd8xx/u-boot.lds | 91 --
> board/spd8xx/u-boot.lds.debug | 122 ---
> board/tqc/tqm8xx/Kconfig | 78 --
> board/tqc/tqm8xx/MAINTAINERS | 16 -
> board/tqc/tqm8xx/tqm8xx.c | 58 +-
> board/utx8245/Kconfig | 9 -
> board/utx8245/MAINTAINERS | 6 -
> board/utx8245/Makefile | 13 -
> board/utx8245/flash.c | 544 -----------
> board/utx8245/utx8245.c | 119 ---
> common/cmd_pcmcia.c | 3 -
> common/flash.c | 6 -
> configs/A3000_defconfig | 3 -
> configs/CPC45_ROMBOOT_defconfig | 4 -
> configs/CPC45_defconfig | 3 -
> configs/CPU86_ROMBOOT_defconfig | 4 -
> configs/CPU86_defconfig | 3 -
> configs/CPU87_ROMBOOT_defconfig | 4 -
> configs/CPU87_defconfig | 3 -
> configs/CU824_defconfig | 3 -
> configs/ELPT860_defconfig | 3 -
> configs/ESTEEM192E_defconfig | 3 -
> configs/FPS850L_defconfig | 3 -
> configs/FPS860L_defconfig | 3 -
> configs/IP860_defconfig | 3 -
> configs/IPHASE4539_defconfig | 3 -
> configs/IVML24_128_defconfig | 4 -
> configs/IVML24_256_defconfig | 4 -
> configs/IVML24_defconfig | 4 -
> configs/IVMS8_128_defconfig | 4 -
> configs/IVMS8_256_defconfig | 4 -
> configs/IVMS8_defconfig | 4 -
> configs/KUP4K_defconfig | 3 -
> configs/KUP4X_defconfig | 3 -
> configs/MPC8266ADS_defconfig | 3 -
> configs/MUSENKI_defconfig | 3 -
> configs/MVBLUE_defconfig | 3 -
> configs/NETVIA_V2_defconfig | 4 -
> configs/NETVIA_defconfig | 4 -
> configs/NSCU_defconfig | 3 -
> configs/PM825_BIGFLASH_defconfig | 4 -
> configs/PM825_ROMBOOT_BIGFLASH_defconfig | 4 -
> configs/PM825_ROMBOOT_defconfig | 4 -
> configs/PM825_defconfig | 4 -
> configs/PM826_BIGFLASH_defconfig | 4 -
> configs/PM826_ROMBOOT_BIGFLASH_defconfig | 4 -
> configs/PM826_ROMBOOT_defconfig | 4 -
> configs/PM826_defconfig | 4 -
> configs/PM828_PCI_defconfig | 4 -
> configs/PM828_ROMBOOT_PCI_defconfig | 4 -
> configs/PM828_ROMBOOT_defconfig | 4 -
> configs/PM828_defconfig | 3 -
> configs/R360MPI_defconfig | 3 -
> configs/RRvision_LCD_defconfig | 4 -
> configs/RRvision_defconfig | 3 -
> configs/SM850_defconfig | 3 -
> configs/SPD823TS_defconfig | 3 -
> configs/Sandpoint8240_defconfig | 3 -
> configs/Sandpoint8245_defconfig | 3 -
> configs/TK885D_defconfig | 3 -
> configs/VoVPN-GW_66MHz_defconfig | 4 -
> configs/atc_defconfig | 3 -
> configs/cogent_mpc8260_defconfig | 3 -
> configs/cogent_mpc8xx_defconfig | 3 -
> configs/eXalion_defconfig | 3 -
> configs/ep8260_defconfig | 3 -
> configs/ep82xxm_defconfig | 3 -
> configs/gw8260_defconfig | 3 -
> configs/hmi1001_defconfig | 3 -
> configs/lwmon_defconfig | 3 -
> configs/muas3001_defconfig | 3 -
> configs/muas3001_dev_defconfig | 4 -
> configs/mucmc52_defconfig | 3 -
> configs/ppmc8260_defconfig | 3 -
> configs/sacsng_defconfig | 3 -
> configs/uc100_defconfig | 3 -
> configs/uc101_defconfig | 3 -
> configs/utx8245_defconfig | 3 -
> configs/virtlab2_defconfig | 3 -
> doc/README.scrapyard | 50 +-
> drivers/net/mpc5xxx_fec.c | 5 -
> drivers/pcmcia/Makefile | 1 -
> drivers/pcmcia/i82365.c | 989 -------------------
> drivers/pcmcia/mpc8xx_pcmcia.c | 6 -
> drivers/pcmcia/tqm8xx_pcmcia.c | 51 +-
> drivers/rtc/Makefile | 1 -
> drivers/rtc/ds12887.c | 217 -----
> drivers/video/mpc8xx_lcd.c | 53 -
> drivers/video/smiLynxEM.c | 3 -
> examples/standalone/test_burst.c | 19 -
> include/common.h | 4 -
> include/commproc.h | 293 +-----
> include/configs/A3000.h | 293 ------
> include/configs/CPC45.h | 489 ----------
> include/configs/CPU86.h | 629 ------------
> include/configs/CPU87.h | 676 -------------
> include/configs/CU824.h | 286 ------
> include/configs/ELPT860.h | 374 --------
> include/configs/ESTEEM192E.h | 292 ------
> include/configs/FPS850L.h | 413 --------
> include/configs/FPS860L.h | 415 --------
> include/configs/IP860.h | 438 ---------
> include/configs/IPHASE4539.h | 328 -------
> include/configs/IVML24.h | 458 ---------
> include/configs/IVMS8.h | 441 ---------
> include/configs/KUP4K.h | 488 ----------
> include/configs/KUP4X.h | 440 ---------
> include/configs/MPC8266ADS.h | 563 -----------
> include/configs/MUSENKI.h | 275 ------
> include/configs/MVBLUE.h | 325 -------
> include/configs/NETVIA.h | 435 ---------
> include/configs/NSCU.h | 463 ---------
> include/configs/PM826.h | 534 -----------
> include/configs/PM828.h | 528 ----------
> include/configs/R360MPI.h | 464 ---------
> include/configs/RRvision.h | 450 ---------
> include/configs/SM850.h | 351 -------
> include/configs/SPD823TS.h | 402 --------
> include/configs/Sandpoint8240.h | 398 --------
> include/configs/Sandpoint8245.h | 376 --------
> include/configs/TK885D.h | 490 ----------
> include/configs/VoVPN-GW.h | 399 --------
> include/configs/atc.h | 489 ----------
> include/configs/cogent_common.h | 192 ----
> include/configs/cogent_mpc8260.h | 392 --------
> include/configs/cogent_mpc8xx.h | 349 -------
> include/configs/eXalion.h | 433 ---------
> include/configs/ep8260.h | 744 --------------
> include/configs/ep82xxm.h | 383 --------
> include/configs/gw8260.h | 800 ----------------
> include/configs/hmi1001.h | 339 -------
> include/configs/lwmon.h | 587 ------------
> include/configs/muas3001.h | 391 --------
> include/configs/mucmc52.h | 126 ---
> include/configs/ppmc8260.h | 986 -------------------
> include/configs/sacsng.h | 1038 --------------------
> include/configs/uc100.h | 482 ----------
> include/configs/uc101.h | 103 --
> include/configs/utx8245.h | 408 --------
> include/configs/virtlab2.h | 469 ---------
> include/mpc824x.h | 523 ----------
> include/pci.h | 4 -
> include/pcmcia.h | 12 -
> include/pcmcia/cirrus.h | 180 ----
> include/pcmcia/i82365.h | 154 ---
> include/pcmcia/ss.h | 133 ---
> include/pcmcia/ti113x.h | 234 -----
> include/ppc_asm.tmpl | 4 +-
> include/status_led.h | 97 --
> include/video_ad7176.h | 89 --
> include/video_ad7177.h | 133 ---
> include/video_ad7179.h | 20 -
> post/drivers/memory.c | 2 +-
> 430 files changed, 59 insertions(+), 68545 deletions(-)
> delete mode 100644 arch/powerpc/cpu/mpc824x/Kconfig
> delete mode 100644 arch/powerpc/cpu/mpc824x/Makefile
> delete mode 100644 arch/powerpc/cpu/mpc824x/config.mk
> delete mode 100644 arch/powerpc/cpu/mpc824x/cpu.c
> delete mode 100644 arch/powerpc/cpu/mpc824x/cpu_init.c
> delete mode 100644 arch/powerpc/cpu/mpc824x/drivers/epic.h
> delete mode 100644 arch/powerpc/cpu/mpc824x/drivers/epic/README
> delete mode 100644 arch/powerpc/cpu/mpc824x/drivers/epic/epic.h
> delete mode 100644 arch/powerpc/cpu/mpc824x/drivers/epic/epic1.c
> delete mode 100644 arch/powerpc/cpu/mpc824x/drivers/epic/epic2.S
> delete mode 100644 arch/powerpc/cpu/mpc824x/drivers/epic/epicutil.S
> delete mode 100644 arch/powerpc/cpu/mpc824x/drivers/errors.h
> delete mode 100644 arch/powerpc/cpu/mpc824x/drivers/i2c/i2c.c
> delete mode 100644 arch/powerpc/cpu/mpc824x/interrupts.c
> delete mode 100644 arch/powerpc/cpu/mpc824x/pci.c
> delete mode 100644 arch/powerpc/cpu/mpc824x/speed.c
> delete mode 100644 arch/powerpc/cpu/mpc824x/start.S
> delete mode 100644 arch/powerpc/cpu/mpc824x/traps.c
> delete mode 100644 arch/powerpc/cpu/mpc824x/u-boot.lds
> delete mode 100644 board/LEOX/elpt860/Kconfig
> delete mode 100644 board/LEOX/elpt860/MAINTAINERS
> delete mode 100644 board/LEOX/elpt860/Makefile
> delete mode 100644 board/LEOX/elpt860/README.LEOX
> delete mode 100644 board/LEOX/elpt860/elpt860.c
> delete mode 100644 board/LEOX/elpt860/flash.c
> delete mode 100644 board/LEOX/elpt860/u-boot.lds
> delete mode 100644 board/LEOX/elpt860/u-boot.lds.debug
> delete mode 100644 board/RRvision/Kconfig
> delete mode 100644 board/RRvision/MAINTAINERS
> delete mode 100644 board/RRvision/Makefile
> delete mode 100644 board/RRvision/RRvision.c
> delete mode 100644 board/RRvision/flash.c
> delete mode 100644 board/RRvision/u-boot.lds
> delete mode 100644 board/RRvision/video_ad7179.h
> delete mode 100644 board/a3000/Kconfig
> delete mode 100644 board/a3000/MAINTAINERS
> delete mode 100644 board/a3000/Makefile
> delete mode 100644 board/a3000/README
> delete mode 100644 board/a3000/a3000.c
> delete mode 100644 board/a3000/flash.c
> delete mode 100644 board/atc/Kconfig
> delete mode 100644 board/atc/MAINTAINERS
> delete mode 100644 board/atc/Makefile
> delete mode 100644 board/atc/atc.c
> delete mode 100644 board/atc/flash.c
> delete mode 100644 board/atc/ti113x.c
> delete mode 100644 board/cogent/Kconfig
> delete mode 100644 board/cogent/MAINTAINERS
> delete mode 100644 board/cogent/Makefile
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> delete mode 100644 include/mpc824x.h
> delete mode 100644 include/pcmcia/cirrus.h
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> delete mode 100644 include/pcmcia/ss.h
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>
> --
> 1.9.1
>
--
Best Regards
Masahiro Yamada
^ permalink raw reply [flat|nested] 55+ messages in thread
* [U-Boot] [PATCH 0/26] Start removing non-generic boards
2014-12-15 14:26 [U-Boot] [PATCH 0/26] Start removing non-generic boards Masahiro Yamada
` (26 preceding siblings ...)
2015-01-05 15:44 ` [U-Boot] [PATCH 0/26] Start removing non-generic boards Masahiro YAMADA
@ 2015-01-05 18:28 ` Tom Rini
27 siblings, 0 replies; 55+ messages in thread
From: Tom Rini @ 2015-01-05 18:28 UTC (permalink / raw)
To: u-boot
On Mon, Dec 15, 2014 at 11:26:05PM +0900, Masahiro Yamada wrote:
> As doc/README.generic-board says, the dead line has already expired
> and we are supposed to remove all the non-generic boards by the
> end of this year.
>
> This series removes non-generic boards of mpc8xx, mpc8260, mpc824x
> platform.
25/26 was also applied but I forgot that in my bulk replying.
--
Tom
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^ permalink raw reply [flat|nested] 55+ messages in thread