* [U-Boot] [PATCH v2 1/7] dm: cache: Add enable and disable ops for cache uclass
2019-07-09 9:28 [U-Boot] [PATCH v2 0/7] Support Andes RISC-V l2cache on AE350 platform Andes
@ 2019-07-09 9:28 ` Andes
2019-07-11 2:49 ` Bin Meng
2019-07-09 9:28 ` [U-Boot] [PATCH v2 2/7] dm: cache: add v5l2 cache controller driver Andes
` (5 subsequent siblings)
6 siblings, 1 reply; 18+ messages in thread
From: Andes @ 2019-07-09 9:28 UTC (permalink / raw)
To: u-boot
From: Rick Chen <rick@andestech.com>
The L2 cache will be enabled in init flow of dm cache
driver when it detect L2 node in dtb.
When U-Boot jump to Linux Kernel, the disable ops will
be called to flush and disable the L2 cache via the dm
cache driver.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
---
drivers/cache/cache-uclass.c | 20 ++++++++++++++++++++
include/cache.h | 31 +++++++++++++++++++++++++++++++
test/dm/cache.c | 2 ++
3 files changed, 53 insertions(+)
diff --git a/drivers/cache/cache-uclass.c b/drivers/cache/cache-uclass.c
index 97ce024..3b20a10 100644
--- a/drivers/cache/cache-uclass.c
+++ b/drivers/cache/cache-uclass.c
@@ -17,6 +17,26 @@ int cache_get_info(struct udevice *dev, struct cache_info *info)
return ops->get_info(dev, info);
}
+int cache_enable(struct udevice *dev)
+{
+ struct cache_ops *ops = cache_get_ops(dev);
+
+ if (!ops->enable)
+ return -ENOSYS;
+
+ return ops->enable(dev);
+}
+
+int cache_disable(struct udevice *dev)
+{
+ struct cache_ops *ops = cache_get_ops(dev);
+
+ if (!ops->disable)
+ return -ENOSYS;
+
+ return ops->disable(dev);
+}
+
UCLASS_DRIVER(cache) = {
.id = UCLASS_CACHE,
.name = "cache",
diff --git a/include/cache.h b/include/cache.h
index c6334ca..32f59fd 100644
--- a/include/cache.h
+++ b/include/cache.h
@@ -22,6 +22,22 @@ struct cache_ops {
* @return 0 if OK, -ve on error
*/
int (*get_info)(struct udevice *dev, struct cache_info *info);
+
+ /**
+ * enable() - Enable cache
+ *
+ * @dev: Device to check (UCLASS_CACHE)
+ * @return 0 if OK, -ve on error
+ */
+ int (*enable)(struct udevice *dev);
+
+ /**
+ * disable() - Flush and disable cache
+ *
+ * @dev: Device to check (UCLASS_CACHE)
+ * @return 0 if OK, -ve on error
+ */
+ int (*disable)(struct udevice *dev);
};
#define cache_get_ops(dev) ((struct cache_ops *)(dev)->driver->ops)
@@ -35,4 +51,19 @@ struct cache_ops {
*/
int cache_get_info(struct udevice *dev, struct cache_info *info);
+/**
+ * cache_enable() - Enable cache
+ *
+ * @dev: Device to check (UCLASS_CACHE)
+ * @return 0 if OK, -ve on error
+ */
+int cache_enable(struct udevice *dev);
+
+/**
+ * cache_disable() - Flush and disable cache
+ *
+ * @dev: Device to check (UCLASS_CACHE)
+ * @return 0 if OK, -ve on error
+ */
+int cache_disable(struct udevice *dev);
#endif
diff --git a/test/dm/cache.c b/test/dm/cache.c
index d4144aa..2e244b1 100644
--- a/test/dm/cache.c
+++ b/test/dm/cache.c
@@ -14,6 +14,8 @@ static int dm_test_reset(struct unit_test_state *uts)
ut_assertok(uclass_get_device(UCLASS_CACHE, 0, &dev_cache));
ut_assertok(cache_get_info(dev, &info));
+ ut_assertok(cache_enable(dev));
+ ut_assertok(cache_disable(dev));
return 0;
}
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v2 1/7] dm: cache: Add enable and disable ops for cache uclass
2019-07-09 9:28 ` [U-Boot] [PATCH v2 1/7] dm: cache: Add enable and disable ops for cache uclass Andes
@ 2019-07-11 2:49 ` Bin Meng
2019-07-17 7:33 ` Rick Chen
0 siblings, 1 reply; 18+ messages in thread
From: Bin Meng @ 2019-07-11 2:49 UTC (permalink / raw)
To: u-boot
On Tue, Jul 9, 2019 at 5:33 PM Andes <uboot@andestech.com> wrote:
>
> From: Rick Chen <rick@andestech.com>
>
> The L2 cache will be enabled in init flow of dm cache
> driver when it detect L2 node in dtb.
>
> When U-Boot jump to Linux Kernel, the disable ops will
jumps
> be called to flush and disable the L2 cache via the dm
> cache driver.
>
> Signed-off-by: Rick Chen <rick@andestech.com>
> Cc: KC Lin <kclin@andestech.com>
> ---
> drivers/cache/cache-uclass.c | 20 ++++++++++++++++++++
> include/cache.h | 31 +++++++++++++++++++++++++++++++
> test/dm/cache.c | 2 ++
> 3 files changed, 53 insertions(+)
>
> diff --git a/drivers/cache/cache-uclass.c b/drivers/cache/cache-uclass.c
> index 97ce024..3b20a10 100644
> --- a/drivers/cache/cache-uclass.c
> +++ b/drivers/cache/cache-uclass.c
> @@ -17,6 +17,26 @@ int cache_get_info(struct udevice *dev, struct cache_info *info)
> return ops->get_info(dev, info);
> }
>
> +int cache_enable(struct udevice *dev)
> +{
> + struct cache_ops *ops = cache_get_ops(dev);
> +
> + if (!ops->enable)
> + return -ENOSYS;
> +
> + return ops->enable(dev);
> +}
> +
> +int cache_disable(struct udevice *dev)
> +{
> + struct cache_ops *ops = cache_get_ops(dev);
> +
> + if (!ops->disable)
> + return -ENOSYS;
> +
> + return ops->disable(dev);
> +}
> +
> UCLASS_DRIVER(cache) = {
> .id = UCLASS_CACHE,
> .name = "cache",
> diff --git a/include/cache.h b/include/cache.h
> index c6334ca..32f59fd 100644
> --- a/include/cache.h
> +++ b/include/cache.h
> @@ -22,6 +22,22 @@ struct cache_ops {
> * @return 0 if OK, -ve on error
> */
> int (*get_info)(struct udevice *dev, struct cache_info *info);
> +
> + /**
> + * enable() - Enable cache
> + *
> + * @dev: Device to check (UCLASS_CACHE)
> + * @return 0 if OK, -ve on error
> + */
> + int (*enable)(struct udevice *dev);
> +
> + /**
> + * disable() - Flush and disable cache
> + *
> + * @dev: Device to check (UCLASS_CACHE)
> + * @return 0 if OK, -ve on error
> + */
> + int (*disable)(struct udevice *dev);
> };
>
> #define cache_get_ops(dev) ((struct cache_ops *)(dev)->driver->ops)
> @@ -35,4 +51,19 @@ struct cache_ops {
> */
> int cache_get_info(struct udevice *dev, struct cache_info *info);
>
> +/**
> + * cache_enable() - Enable cache
> + *
> + * @dev: Device to check (UCLASS_CACHE)
> + * @return 0 if OK, -ve on error
> + */
> +int cache_enable(struct udevice *dev);
> +
> +/**
> + * cache_disable() - Flush and disable cache
> + *
> + * @dev: Device to check (UCLASS_CACHE)
> + * @return 0 if OK, -ve on error
> + */
> +int cache_disable(struct udevice *dev);
> #endif
> diff --git a/test/dm/cache.c b/test/dm/cache.c
Please separate the test case changes in another patch, together with
sandbox_cache.c changes. (see below)
> index d4144aa..2e244b1 100644
> --- a/test/dm/cache.c
> +++ b/test/dm/cache.c
> @@ -14,6 +14,8 @@ static int dm_test_reset(struct unit_test_state *uts)
>
> ut_assertok(uclass_get_device(UCLASS_CACHE, 0, &dev_cache));
> ut_assertok(cache_get_info(dev, &info));
> + ut_assertok(cache_enable(dev));
> + ut_assertok(cache_disable(dev));
This can't be passed as you did not update sandbox_cache.c to add the
enable/disable OP.
>
> return 0;
Regards,
Bin
^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v2 1/7] dm: cache: Add enable and disable ops for cache uclass
2019-07-11 2:49 ` Bin Meng
@ 2019-07-17 7:33 ` Rick Chen
0 siblings, 0 replies; 18+ messages in thread
From: Rick Chen @ 2019-07-17 7:33 UTC (permalink / raw)
To: u-boot
Hi Bin
>
> On Tue, Jul 9, 2019 at 5:33 PM Andes <uboot@andestech.com> wrote:
> >
> > From: Rick Chen <rick@andestech.com>
> >
> > The L2 cache will be enabled in init flow of dm cache
> > driver when it detect L2 node in dtb.
> >
> > When U-Boot jump to Linux Kernel, the disable ops will
>
> jumps
>
> > be called to flush and disable the L2 cache via the dm
> > cache driver.
> >
> > Signed-off-by: Rick Chen <rick@andestech.com>
> > Cc: KC Lin <kclin@andestech.com>
> > ---
> > drivers/cache/cache-uclass.c | 20 ++++++++++++++++++++
> > include/cache.h | 31 +++++++++++++++++++++++++++++++
> > test/dm/cache.c | 2 ++
> > 3 files changed, 53 insertions(+)
> >
> > diff --git a/drivers/cache/cache-uclass.c b/drivers/cache/cache-uclass.c
> > index 97ce024..3b20a10 100644
> > --- a/drivers/cache/cache-uclass.c
> > +++ b/drivers/cache/cache-uclass.c
> > @@ -17,6 +17,26 @@ int cache_get_info(struct udevice *dev, struct cache_info *info)
> > return ops->get_info(dev, info);
> > }
> >
> > +int cache_enable(struct udevice *dev)
> > +{
> > + struct cache_ops *ops = cache_get_ops(dev);
> > +
> > + if (!ops->enable)
> > + return -ENOSYS;
> > +
> > + return ops->enable(dev);
> > +}
> > +
> > +int cache_disable(struct udevice *dev)
> > +{
> > + struct cache_ops *ops = cache_get_ops(dev);
> > +
> > + if (!ops->disable)
> > + return -ENOSYS;
> > +
> > + return ops->disable(dev);
> > +}
> > +
> > UCLASS_DRIVER(cache) = {
> > .id = UCLASS_CACHE,
> > .name = "cache",
> > diff --git a/include/cache.h b/include/cache.h
> > index c6334ca..32f59fd 100644
> > --- a/include/cache.h
> > +++ b/include/cache.h
> > @@ -22,6 +22,22 @@ struct cache_ops {
> > * @return 0 if OK, -ve on error
> > */
> > int (*get_info)(struct udevice *dev, struct cache_info *info);
> > +
> > + /**
> > + * enable() - Enable cache
> > + *
> > + * @dev: Device to check (UCLASS_CACHE)
> > + * @return 0 if OK, -ve on error
> > + */
> > + int (*enable)(struct udevice *dev);
> > +
> > + /**
> > + * disable() - Flush and disable cache
> > + *
> > + * @dev: Device to check (UCLASS_CACHE)
> > + * @return 0 if OK, -ve on error
> > + */
> > + int (*disable)(struct udevice *dev);
> > };
> >
> > #define cache_get_ops(dev) ((struct cache_ops *)(dev)->driver->ops)
> > @@ -35,4 +51,19 @@ struct cache_ops {
> > */
> > int cache_get_info(struct udevice *dev, struct cache_info *info);
> >
> > +/**
> > + * cache_enable() - Enable cache
> > + *
> > + * @dev: Device to check (UCLASS_CACHE)
> > + * @return 0 if OK, -ve on error
> > + */
> > +int cache_enable(struct udevice *dev);
> > +
> > +/**
> > + * cache_disable() - Flush and disable cache
> > + *
> > + * @dev: Device to check (UCLASS_CACHE)
> > + * @return 0 if OK, -ve on error
> > + */
> > +int cache_disable(struct udevice *dev);
> > #endif
> > diff --git a/test/dm/cache.c b/test/dm/cache.c
>
> Please separate the test case changes in another patch, together with
> sandbox_cache.c changes. (see below)
OK
I will separate it.
>
> > index d4144aa..2e244b1 100644
> > --- a/test/dm/cache.c
> > +++ b/test/dm/cache.c
> > @@ -14,6 +14,8 @@ static int dm_test_reset(struct unit_test_state *uts)
> >
> > ut_assertok(uclass_get_device(UCLASS_CACHE, 0, &dev_cache));
> > ut_assertok(cache_get_info(dev, &info));
> > + ut_assertok(cache_enable(dev));
> > + ut_assertok(cache_disable(dev));
>
> This can't be passed as you did not update sandbox_cache.c to add the
> enable/disable OP.
OK
I will update sandbox_cache.c .
Thanks
Rick
>
> >
> > return 0;
>
> Regards,
> Bin
^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v2 2/7] dm: cache: add v5l2 cache controller driver
2019-07-09 9:28 [U-Boot] [PATCH v2 0/7] Support Andes RISC-V l2cache on AE350 platform Andes
2019-07-09 9:28 ` [U-Boot] [PATCH v2 1/7] dm: cache: Add enable and disable ops for cache uclass Andes
@ 2019-07-09 9:28 ` Andes
2019-07-11 3:04 ` Bin Meng
2019-07-09 9:28 ` [U-Boot] [PATCH v2 3/7] riscv: ae350: use the v5l2 driver to configure the cache Andes
` (4 subsequent siblings)
6 siblings, 1 reply; 18+ messages in thread
From: Andes @ 2019-07-09 9:28 UTC (permalink / raw)
To: u-boot
From: Rick Chen <rick@andestech.com>
Add a v5l2 cache controller driver that is usually found on
Andes RISC-V ae350 platform. It will parse the cache settings
from the dtb.
In this version tag and data ram control timing can be adjusted
by the requirement from the dtb.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Cc: KC Lin <kclin@andestech.com>
---
arch/riscv/include/asm/v5l2cache.h | 58 ++++++++++++++++++
drivers/cache/Kconfig | 9 +++
drivers/cache/Makefile | 1 +
drivers/cache/cache-v5l2.c | 121 +++++++++++++++++++++++++++++++++++++
4 files changed, 189 insertions(+)
create mode 100644 arch/riscv/include/asm/v5l2cache.h
create mode 100644 drivers/cache/cache-v5l2.c
diff --git a/arch/riscv/include/asm/v5l2cache.h b/arch/riscv/include/asm/v5l2cache.h
new file mode 100644
index 0000000..28e40f8
--- /dev/null
+++ b/arch/riscv/include/asm/v5l2cache.h
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ */
+
+#ifndef _ASM_V5_L2CACHE_H
+#define _ASM_V5_L2CACHE_H
+
+struct l2cache {
+ volatile u64 configure;
+ volatile u64 control;
+ volatile u64 hpm0;
+ volatile u64 hpm1;
+ volatile u64 hpm2;
+ volatile u64 hpm3;
+ volatile u64 error_status;
+ volatile u64 ecc_error;
+ volatile u64 cctl_command0;
+ volatile u64 cctl_access_line0;
+ volatile u64 cctl_command1;
+ volatile u64 cctl_access_line1;
+ volatile u64 cctl_command2;
+ volatile u64 cctl_access_line2;
+ volatile u64 cctl_command3;
+ volatile u64 cctl_access_line4;
+ volatile u64 cctl_status;
+};
+
+/* Control Register */
+#define L2_ENABLE 0x1
+/* prefetch */
+#define IPREPETCH_OFF 3
+#define DPREPETCH_OFF 5
+#define IPREPETCH_MSK (3 << IPREPETCH_OFF)
+#define DPREPETCH_MSK (3 << DPREPETCH_OFF)
+/* tag ram */
+#define TRAMOCTL_OFF 8
+#define TRAMICTL_OFF 10
+#define TRAMOCTL_MSK (3 << TRAMOCTL_OFF)
+#define TRAMICTL_MSK BIT(TRAMICTL_OFF)
+/* data ram */
+#define DRAMOCTL_OFF 11
+#define DRAMICTL_OFF 13
+#define DRAMOCTL_MSK (3 << DRAMOCTL_OFF)
+#define DRAMICTL_MSK BIT(DRAMICTL_OFF)
+
+/* CCTL Command Register */
+#define CCTL_CMD_REG(base, hart) ((ulong)(base) + 0x40 + (hart) * 0x10)
+#define L2_WBINVAL_ALL 0x12
+
+/* CCTL Status Register */
+#define CCTL_STATUS_MSK(hart) (0xf << ((hart) * 4))
+#define CCTL_STATUS_IDLE(hart) (0 << ((hart) * 4))
+#define CCTL_STATUS_PROCESS(hart) (1 << ((hart) * 4))
+#define CCTL_STATUS_ILLEGAL(hart) (2 << ((hart) * 4))
+
+#endif /* _ASM_V5_L2CACHE_H */
diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
index 24def7a..629039e 100644
--- a/drivers/cache/Kconfig
+++ b/drivers/cache/Kconfig
@@ -22,4 +22,13 @@ config L2X0_CACHE
ARMv7(32-bit) devices. The driver configures the cache settings
found in the device tree.
+config V5L2_CACHE
+ bool "Andes V5L2 cache driver"
+ select CACHE
+ depends on RISCV_NDS_CACHE
+ help
+ Support Andes V5L2 cache controller in AE350 platform.
+ It will configure tag and data ram timing control from the
+ device tree and enable L2 cache.
+
endmenu
diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
index 9deb961..4a6458c 100644
--- a/drivers/cache/Makefile
+++ b/drivers/cache/Makefile
@@ -2,3 +2,4 @@
obj-$(CONFIG_CACHE) += cache-uclass.o
obj-$(CONFIG_SANDBOX) += sandbox_cache.o
obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o
+obj-$(CONFIG_V5L2_CACHE) += cache-v5l2.o
diff --git a/drivers/cache/cache-v5l2.c b/drivers/cache/cache-v5l2.c
new file mode 100644
index 0000000..dd1e72f
--- /dev/null
+++ b/drivers/cache/cache-v5l2.c
@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <cache.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <dm/ofnode.h>
+#include <asm/v5l2cache.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct v5l2_plat {
+ struct l2cache *regs;
+};
+
+int v5l2_enable(struct udevice *dev)
+{
+ struct v5l2_plat *plat = dev_get_platdata(dev);
+ volatile struct l2cache *regs = plat->regs;
+
+ if (regs)
+ setbits_le32(®s->control, L2_ENABLE);
+
+ return 0;
+}
+
+int v5l2_disable(struct udevice *dev)
+{
+ struct v5l2_plat *plat = dev_get_platdata(dev);
+ volatile struct l2cache *regs = plat->regs;
+ u8 hart = gd->arch.boot_hart;
+ void __iomem *cctlcmd = (void __iomem *)CCTL_CMD_REG(regs, hart);
+
+ if ((regs) && (readl(®s->control) & L2_ENABLE)) {
+ writel(L2_WBINVAL_ALL, cctlcmd);
+
+ while ((readl(®s->cctl_status) & CCTL_STATUS_MSK(hart))) {
+ if ((readl(®s->cctl_status) & CCTL_STATUS_ILLEGAL(hart))) {
+ printf("L2 flush illegal! hanging...");
+ hang();
+ }
+ }
+ clrbits_le32(®s->control, L2_ENABLE);
+ }
+
+ return 0;
+}
+
+static void v5l2_of_parse_and_init(struct udevice *dev)
+{
+ struct l2cache *regs;
+ u32 ctl_val, prefetch;
+ u32 tram_ctl[2];
+ u32 dram_ctl[2];
+ struct v5l2_plat *plat = dev_get_platdata(dev);
+
+ regs = (struct l2cache *)dev_read_addr(dev);
+ plat->regs = regs;
+ ctl_val = readl(®s->control);
+
+ if (!(ctl_val & L2_ENABLE))
+ ctl_val |= L2_ENABLE;
+
+ /* Instruction and data fetch prefetch depth */
+ if (!dev_read_u32(dev, "andes,inst-prefetch", &prefetch)) {
+ ctl_val &= ~(IPREPETCH_MSK);
+ ctl_val |= (prefetch << IPREPETCH_OFF);
+ }
+
+ if (!dev_read_u32(dev, "andes,data-prefetch", &prefetch)) {
+ ctl_val &= ~(DPREPETCH_MSK);
+ ctl_val |= (prefetch << DPREPETCH_OFF);
+ }
+
+ /* Set tag RAM and data RAM setup and output cycle */
+ if (!dev_read_u32_array(dev, "andes,tag-ram-ctl", tram_ctl, 2)) {
+ ctl_val &= ~(TRAMOCTL_MSK | TRAMICTL_MSK);
+ ctl_val |= tram_ctl[0] << TRAMOCTL_OFF;
+ ctl_val |= tram_ctl[1] << TRAMICTL_OFF;
+ }
+
+ if (!dev_read_u32_array(dev, "andes,data-ram-ctl", dram_ctl, 2)) {
+ ctl_val &= ~(DRAMOCTL_MSK | DRAMICTL_MSK);
+ ctl_val |= dram_ctl[0] << DRAMOCTL_OFF;
+ ctl_val |= dram_ctl[1] << DRAMICTL_OFF;
+ }
+
+ writel(ctl_val, ®s->control);
+}
+
+static int v5l2_ofdata_to_platdata(struct udevice *dev)
+{
+ v5l2_of_parse_and_init(dev);
+
+ return 0;
+}
+
+static const struct udevice_id v5l2_cache_ids[] = {
+ { .compatible = "v5l2cache" },
+ {}
+};
+
+static const struct cache_ops v5l2_cache_ops = {
+ .enable = v5l2_enable,
+ .disable = v5l2_disable,
+};
+
+U_BOOT_DRIVER(v5l2_cache) = {
+ .name = "v5l2_cache",
+ .id = UCLASS_CACHE,
+ .of_match = v5l2_cache_ids,
+ .ofdata_to_platdata = v5l2_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct v5l2_plat),
+ .ops = &v5l2_cache_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v2 2/7] dm: cache: add v5l2 cache controller driver
2019-07-09 9:28 ` [U-Boot] [PATCH v2 2/7] dm: cache: add v5l2 cache controller driver Andes
@ 2019-07-11 3:04 ` Bin Meng
2019-07-17 7:30 ` Rick Chen
0 siblings, 1 reply; 18+ messages in thread
From: Bin Meng @ 2019-07-11 3:04 UTC (permalink / raw)
To: u-boot
On Tue, Jul 9, 2019 at 5:34 PM Andes <uboot@andestech.com> wrote:
>
> From: Rick Chen <rick@andestech.com>
>
> Add a v5l2 cache controller driver that is usually found on
> Andes RISC-V ae350 platform. It will parse the cache settings
> from the dtb.
>
> In this version tag and data ram control timing can be adjusted
> by the requirement from the dtb.
>
> Signed-off-by: Rick Chen <rick@andestech.com>
> Cc: Greentime Hu <greentime@andestech.com>
> Cc: KC Lin <kclin@andestech.com>
> ---
> arch/riscv/include/asm/v5l2cache.h | 58 ++++++++++++++++++
> drivers/cache/Kconfig | 9 +++
> drivers/cache/Makefile | 1 +
> drivers/cache/cache-v5l2.c | 121 +++++++++++++++++++++++++++++++++++++
> 4 files changed, 189 insertions(+)
> create mode 100644 arch/riscv/include/asm/v5l2cache.h
> create mode 100644 drivers/cache/cache-v5l2.c
>
> diff --git a/arch/riscv/include/asm/v5l2cache.h b/arch/riscv/include/asm/v5l2cache.h
> new file mode 100644
> index 0000000..28e40f8
> --- /dev/null
> +++ b/arch/riscv/include/asm/v5l2cache.h
> @@ -0,0 +1,58 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (C) 2019 Andes Technology Corporation
> + * Rick Chen, Andes Technology Corporation <rick@andestech.com>
> + */
> +
> +#ifndef _ASM_V5_L2CACHE_H
> +#define _ASM_V5_L2CACHE_H
> +
> +struct l2cache {
> + volatile u64 configure;
> + volatile u64 control;
> + volatile u64 hpm0;
> + volatile u64 hpm1;
> + volatile u64 hpm2;
> + volatile u64 hpm3;
> + volatile u64 error_status;
> + volatile u64 ecc_error;
> + volatile u64 cctl_command0;
> + volatile u64 cctl_access_line0;
> + volatile u64 cctl_command1;
> + volatile u64 cctl_access_line1;
> + volatile u64 cctl_command2;
> + volatile u64 cctl_access_line2;
> + volatile u64 cctl_command3;
> + volatile u64 cctl_access_line4;
> + volatile u64 cctl_status;
> +};
> +
> +/* Control Register */
> +#define L2_ENABLE 0x1
> +/* prefetch */
> +#define IPREPETCH_OFF 3
> +#define DPREPETCH_OFF 5
> +#define IPREPETCH_MSK (3 << IPREPETCH_OFF)
> +#define DPREPETCH_MSK (3 << DPREPETCH_OFF)
> +/* tag ram */
> +#define TRAMOCTL_OFF 8
> +#define TRAMICTL_OFF 10
> +#define TRAMOCTL_MSK (3 << TRAMOCTL_OFF)
> +#define TRAMICTL_MSK BIT(TRAMICTL_OFF)
> +/* data ram */
> +#define DRAMOCTL_OFF 11
> +#define DRAMICTL_OFF 13
> +#define DRAMOCTL_MSK (3 << DRAMOCTL_OFF)
> +#define DRAMICTL_MSK BIT(DRAMICTL_OFF)
> +
> +/* CCTL Command Register */
> +#define CCTL_CMD_REG(base, hart) ((ulong)(base) + 0x40 + (hart) * 0x10)
> +#define L2_WBINVAL_ALL 0x12
> +
> +/* CCTL Status Register */
> +#define CCTL_STATUS_MSK(hart) (0xf << ((hart) * 4))
> +#define CCTL_STATUS_IDLE(hart) (0 << ((hart) * 4))
> +#define CCTL_STATUS_PROCESS(hart) (1 << ((hart) * 4))
> +#define CCTL_STATUS_ILLEGAL(hart) (2 << ((hart) * 4))
> +
> +#endif /* _ASM_V5_L2CACHE_H */
> diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
> index 24def7a..629039e 100644
> --- a/drivers/cache/Kconfig
> +++ b/drivers/cache/Kconfig
> @@ -22,4 +22,13 @@ config L2X0_CACHE
> ARMv7(32-bit) devices. The driver configures the cache settings
> found in the device tree.
>
> +config V5L2_CACHE
> + bool "Andes V5L2 cache driver"
> + select CACHE
> + depends on RISCV_NDS_CACHE
> + help
> + Support Andes V5L2 cache controller in AE350 platform.
> + It will configure tag and data ram timing control from the
> + device tree and enable L2 cache.
> +
> endmenu
> diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
> index 9deb961..4a6458c 100644
> --- a/drivers/cache/Makefile
> +++ b/drivers/cache/Makefile
> @@ -2,3 +2,4 @@
> obj-$(CONFIG_CACHE) += cache-uclass.o
> obj-$(CONFIG_SANDBOX) += sandbox_cache.o
> obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o
> +obj-$(CONFIG_V5L2_CACHE) += cache-v5l2.o
> diff --git a/drivers/cache/cache-v5l2.c b/drivers/cache/cache-v5l2.c
> new file mode 100644
> index 0000000..dd1e72f
> --- /dev/null
> +++ b/drivers/cache/cache-v5l2.c
> @@ -0,0 +1,121 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2019 Andes Technology Corporation
> + * Rick Chen, Andes Technology Corporation <rick@andestech.com>
> + */
> +
> +#include <common.h>
> +#include <command.h>
> +#include <cache.h>
> +#include <dm.h>
> +#include <asm/io.h>
> +#include <dm/ofnode.h>
> +#include <asm/v5l2cache.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +struct v5l2_plat {
> + struct l2cache *regs;
> +};
> +
> +int v5l2_enable(struct udevice *dev)
This should be static.
> +{
> + struct v5l2_plat *plat = dev_get_platdata(dev);
> + volatile struct l2cache *regs = plat->regs;
> +
> + if (regs)
> + setbits_le32(®s->control, L2_ENABLE);
> +
> + return 0;
> +}
> +
> +int v5l2_disable(struct udevice *dev)
ditto
> +{
> + struct v5l2_plat *plat = dev_get_platdata(dev);
> + volatile struct l2cache *regs = plat->regs;
> + u8 hart = gd->arch.boot_hart;
> + void __iomem *cctlcmd = (void __iomem *)CCTL_CMD_REG(regs, hart);
> +
> + if ((regs) && (readl(®s->control) & L2_ENABLE)) {
> + writel(L2_WBINVAL_ALL, cctlcmd);
> +
> + while ((readl(®s->cctl_status) & CCTL_STATUS_MSK(hart))) {
> + if ((readl(®s->cctl_status) & CCTL_STATUS_ILLEGAL(hart))) {
> + printf("L2 flush illegal! hanging...");
> + hang();
> + }
> + }
> + clrbits_le32(®s->control, L2_ENABLE);
> + }
> +
> + return 0;
> +}
> +
> +static void v5l2_of_parse_and_init(struct udevice *dev)
> +{
> + struct l2cache *regs;
> + u32 ctl_val, prefetch;
> + u32 tram_ctl[2];
> + u32 dram_ctl[2];
> + struct v5l2_plat *plat = dev_get_platdata(dev);
> +
> + regs = (struct l2cache *)dev_read_addr(dev);
> + plat->regs = regs;
> + ctl_val = readl(®s->control);
> +
> + if (!(ctl_val & L2_ENABLE))
> + ctl_val |= L2_ENABLE;
This should only be done in the driver's probe() routine.
> +
> + /* Instruction and data fetch prefetch depth */
> + if (!dev_read_u32(dev, "andes,inst-prefetch", &prefetch)) {
> + ctl_val &= ~(IPREPETCH_MSK);
> + ctl_val |= (prefetch << IPREPETCH_OFF);
> + }
> +
> + if (!dev_read_u32(dev, "andes,data-prefetch", &prefetch)) {
> + ctl_val &= ~(DPREPETCH_MSK);
> + ctl_val |= (prefetch << DPREPETCH_OFF);
> + }
> +
> + /* Set tag RAM and data RAM setup and output cycle */
> + if (!dev_read_u32_array(dev, "andes,tag-ram-ctl", tram_ctl, 2)) {
> + ctl_val &= ~(TRAMOCTL_MSK | TRAMICTL_MSK);
> + ctl_val |= tram_ctl[0] << TRAMOCTL_OFF;
> + ctl_val |= tram_ctl[1] << TRAMICTL_OFF;
> + }
> +
> + if (!dev_read_u32_array(dev, "andes,data-ram-ctl", dram_ctl, 2)) {
> + ctl_val &= ~(DRAMOCTL_MSK | DRAMICTL_MSK);
> + ctl_val |= dram_ctl[0] << DRAMOCTL_OFF;
> + ctl_val |= dram_ctl[1] << DRAMICTL_OFF;
> + }
> +
I think you need add some members in the "struct v5l2_plat", to save
the DT parse result of "andes,inst-prefetch", "andes,data-prefetch",
"andes,tag-ram-ctl" and "andes,data-ram-ctl".
> + writel(ctl_val, ®s->control);
The register programming should only be done in the driver's probe() routine.
> +}
> +
> +static int v5l2_ofdata_to_platdata(struct udevice *dev)
> +{
> + v5l2_of_parse_and_init(dev);
There is no need to create another function to do the work.
> +
> + return 0;
> +}
> +
> +static const struct udevice_id v5l2_cache_ids[] = {
> + { .compatible = "v5l2cache" },
> + {}
> +};
> +
> +static const struct cache_ops v5l2_cache_ops = {
> + .enable = v5l2_enable,
> + .disable = v5l2_disable,
> +};
> +
> +U_BOOT_DRIVER(v5l2_cache) = {
> + .name = "v5l2_cache",
> + .id = UCLASS_CACHE,
> + .of_match = v5l2_cache_ids,
> + .ofdata_to_platdata = v5l2_ofdata_to_platdata,
> + .platdata_auto_alloc_size = sizeof(struct v5l2_plat),
> + .ops = &v5l2_cache_ops,
> + .flags = DM_FLAG_PRE_RELOC,
> +};
Regards,
Bin
^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v2 2/7] dm: cache: add v5l2 cache controller driver
2019-07-11 3:04 ` Bin Meng
@ 2019-07-17 7:30 ` Rick Chen
0 siblings, 0 replies; 18+ messages in thread
From: Rick Chen @ 2019-07-17 7:30 UTC (permalink / raw)
To: u-boot
Hi Bin
>
> On Tue, Jul 9, 2019 at 5:34 PM Andes <uboot@andestech.com> wrote:
> >
> > From: Rick Chen <rick@andestech.com>
> >
> > Add a v5l2 cache controller driver that is usually found on
> > Andes RISC-V ae350 platform. It will parse the cache settings
> > from the dtb.
> >
> > In this version tag and data ram control timing can be adjusted
> > by the requirement from the dtb.
> >
> > Signed-off-by: Rick Chen <rick@andestech.com>
> > Cc: Greentime Hu <greentime@andestech.com>
> > Cc: KC Lin <kclin@andestech.com>
> > ---
> > arch/riscv/include/asm/v5l2cache.h | 58 ++++++++++++++++++
> > drivers/cache/Kconfig | 9 +++
> > drivers/cache/Makefile | 1 +
> > drivers/cache/cache-v5l2.c | 121 +++++++++++++++++++++++++++++++++++++
> > 4 files changed, 189 insertions(+)
> > create mode 100644 arch/riscv/include/asm/v5l2cache.h
> > create mode 100644 drivers/cache/cache-v5l2.c
> >
> > diff --git a/arch/riscv/include/asm/v5l2cache.h b/arch/riscv/include/asm/v5l2cache.h
> > new file mode 100644
> > index 0000000..28e40f8
> > --- /dev/null
> > +++ b/arch/riscv/include/asm/v5l2cache.h
> > @@ -0,0 +1,58 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * Copyright (C) 2019 Andes Technology Corporation
> > + * Rick Chen, Andes Technology Corporation <rick@andestech.com>
> > + */
> > +
> > +#ifndef _ASM_V5_L2CACHE_H
> > +#define _ASM_V5_L2CACHE_H
> > +
> > +struct l2cache {
> > + volatile u64 configure;
> > + volatile u64 control;
> > + volatile u64 hpm0;
> > + volatile u64 hpm1;
> > + volatile u64 hpm2;
> > + volatile u64 hpm3;
> > + volatile u64 error_status;
> > + volatile u64 ecc_error;
> > + volatile u64 cctl_command0;
> > + volatile u64 cctl_access_line0;
> > + volatile u64 cctl_command1;
> > + volatile u64 cctl_access_line1;
> > + volatile u64 cctl_command2;
> > + volatile u64 cctl_access_line2;
> > + volatile u64 cctl_command3;
> > + volatile u64 cctl_access_line4;
> > + volatile u64 cctl_status;
> > +};
> > +
> > +/* Control Register */
> > +#define L2_ENABLE 0x1
> > +/* prefetch */
> > +#define IPREPETCH_OFF 3
> > +#define DPREPETCH_OFF 5
> > +#define IPREPETCH_MSK (3 << IPREPETCH_OFF)
> > +#define DPREPETCH_MSK (3 << DPREPETCH_OFF)
> > +/* tag ram */
> > +#define TRAMOCTL_OFF 8
> > +#define TRAMICTL_OFF 10
> > +#define TRAMOCTL_MSK (3 << TRAMOCTL_OFF)
> > +#define TRAMICTL_MSK BIT(TRAMICTL_OFF)
> > +/* data ram */
> > +#define DRAMOCTL_OFF 11
> > +#define DRAMICTL_OFF 13
> > +#define DRAMOCTL_MSK (3 << DRAMOCTL_OFF)
> > +#define DRAMICTL_MSK BIT(DRAMICTL_OFF)
> > +
> > +/* CCTL Command Register */
> > +#define CCTL_CMD_REG(base, hart) ((ulong)(base) + 0x40 + (hart) * 0x10)
> > +#define L2_WBINVAL_ALL 0x12
> > +
> > +/* CCTL Status Register */
> > +#define CCTL_STATUS_MSK(hart) (0xf << ((hart) * 4))
> > +#define CCTL_STATUS_IDLE(hart) (0 << ((hart) * 4))
> > +#define CCTL_STATUS_PROCESS(hart) (1 << ((hart) * 4))
> > +#define CCTL_STATUS_ILLEGAL(hart) (2 << ((hart) * 4))
> > +
> > +#endif /* _ASM_V5_L2CACHE_H */
> > diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
> > index 24def7a..629039e 100644
> > --- a/drivers/cache/Kconfig
> > +++ b/drivers/cache/Kconfig
> > @@ -22,4 +22,13 @@ config L2X0_CACHE
> > ARMv7(32-bit) devices. The driver configures the cache settings
> > found in the device tree.
> >
> > +config V5L2_CACHE
> > + bool "Andes V5L2 cache driver"
> > + select CACHE
> > + depends on RISCV_NDS_CACHE
> > + help
> > + Support Andes V5L2 cache controller in AE350 platform.
> > + It will configure tag and data ram timing control from the
> > + device tree and enable L2 cache.
> > +
> > endmenu
> > diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
> > index 9deb961..4a6458c 100644
> > --- a/drivers/cache/Makefile
> > +++ b/drivers/cache/Makefile
> > @@ -2,3 +2,4 @@
> > obj-$(CONFIG_CACHE) += cache-uclass.o
> > obj-$(CONFIG_SANDBOX) += sandbox_cache.o
> > obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o
> > +obj-$(CONFIG_V5L2_CACHE) += cache-v5l2.o
> > diff --git a/drivers/cache/cache-v5l2.c b/drivers/cache/cache-v5l2.c
> > new file mode 100644
> > index 0000000..dd1e72f
> > --- /dev/null
> > +++ b/drivers/cache/cache-v5l2.c
> > @@ -0,0 +1,121 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2019 Andes Technology Corporation
> > + * Rick Chen, Andes Technology Corporation <rick@andestech.com>
> > + */
> > +
> > +#include <common.h>
> > +#include <command.h>
> > +#include <cache.h>
> > +#include <dm.h>
> > +#include <asm/io.h>
> > +#include <dm/ofnode.h>
> > +#include <asm/v5l2cache.h>
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +struct v5l2_plat {
> > + struct l2cache *regs;
> > +};
> > +
> > +int v5l2_enable(struct udevice *dev)
>
> This should be static.
OK
>
> > +{
> > + struct v5l2_plat *plat = dev_get_platdata(dev);
> > + volatile struct l2cache *regs = plat->regs;
> > +
> > + if (regs)
> > + setbits_le32(®s->control, L2_ENABLE);
> > +
> > + return 0;
> > +}
> > +
> > +int v5l2_disable(struct udevice *dev)
>
> ditto
OK
>
> > +{
> > + struct v5l2_plat *plat = dev_get_platdata(dev);
> > + volatile struct l2cache *regs = plat->regs;
> > + u8 hart = gd->arch.boot_hart;
> > + void __iomem *cctlcmd = (void __iomem *)CCTL_CMD_REG(regs, hart);
> > +
> > + if ((regs) && (readl(®s->control) & L2_ENABLE)) {
> > + writel(L2_WBINVAL_ALL, cctlcmd);
> > +
> > + while ((readl(®s->cctl_status) & CCTL_STATUS_MSK(hart))) {
> > + if ((readl(®s->cctl_status) & CCTL_STATUS_ILLEGAL(hart))) {
> > + printf("L2 flush illegal! hanging...");
> > + hang();
> > + }
> > + }
> > + clrbits_le32(®s->control, L2_ENABLE);
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static void v5l2_of_parse_and_init(struct udevice *dev)
> > +{
> > + struct l2cache *regs;
> > + u32 ctl_val, prefetch;
> > + u32 tram_ctl[2];
> > + u32 dram_ctl[2];
> > + struct v5l2_plat *plat = dev_get_platdata(dev);
> > +
> > + regs = (struct l2cache *)dev_read_addr(dev);
> > + plat->regs = regs;
> > + ctl_val = readl(®s->control);
> > +
> > + if (!(ctl_val & L2_ENABLE))
> > + ctl_val |= L2_ENABLE;
>
> This should only be done in the driver's probe() routine.
OK
I will move it to probe().
>
> > +
> > + /* Instruction and data fetch prefetch depth */
> > + if (!dev_read_u32(dev, "andes,inst-prefetch", &prefetch)) {
> > + ctl_val &= ~(IPREPETCH_MSK);
> > + ctl_val |= (prefetch << IPREPETCH_OFF);
> > + }
> > +
> > + if (!dev_read_u32(dev, "andes,data-prefetch", &prefetch)) {
> > + ctl_val &= ~(DPREPETCH_MSK);
> > + ctl_val |= (prefetch << DPREPETCH_OFF);
> > + }
> > +
> > + /* Set tag RAM and data RAM setup and output cycle */
> > + if (!dev_read_u32_array(dev, "andes,tag-ram-ctl", tram_ctl, 2)) {
> > + ctl_val &= ~(TRAMOCTL_MSK | TRAMICTL_MSK);
> > + ctl_val |= tram_ctl[0] << TRAMOCTL_OFF;
> > + ctl_val |= tram_ctl[1] << TRAMICTL_OFF;
> > + }
> > +
> > + if (!dev_read_u32_array(dev, "andes,data-ram-ctl", dram_ctl, 2)) {
> > + ctl_val &= ~(DRAMOCTL_MSK | DRAMICTL_MSK);
> > + ctl_val |= dram_ctl[0] << DRAMOCTL_OFF;
> > + ctl_val |= dram_ctl[1] << DRAMICTL_OFF;
> > + }
> > +
>
> I think you need add some members in the "struct v5l2_plat", to save
> the DT parse result of "andes,inst-prefetch", "andes,data-prefetch",
> "andes,tag-ram-ctl" and "andes,data-ram-ctl".
>
OK
I will save them and configure the control register in probe().
> > + writel(ctl_val, ®s->control);
>
> The register programming should only be done in the driver's probe() routine.
>
> > +}
> > +
> > +static int v5l2_ofdata_to_platdata(struct udevice *dev)
> > +{
> > + v5l2_of_parse_and_init(dev);
>
> There is no need to create another function to do the work.
>
OK
I will remove it.
Thanks
Rick
> > +
> > + return 0;
> > +}
> > +
> > +static const struct udevice_id v5l2_cache_ids[] = {
> > + { .compatible = "v5l2cache" },
> > + {}
> > +};
> > +
> > +static const struct cache_ops v5l2_cache_ops = {
> > + .enable = v5l2_enable,
> > + .disable = v5l2_disable,
> > +};
> > +
> > +U_BOOT_DRIVER(v5l2_cache) = {
> > + .name = "v5l2_cache",
> > + .id = UCLASS_CACHE,
> > + .of_match = v5l2_cache_ids,
> > + .ofdata_to_platdata = v5l2_ofdata_to_platdata,
> > + .platdata_auto_alloc_size = sizeof(struct v5l2_plat),
> > + .ops = &v5l2_cache_ops,
> > + .flags = DM_FLAG_PRE_RELOC,
> > +};
>
> Regards,
> Bin
^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v2 3/7] riscv: ae350: use the v5l2 driver to configure the cache
2019-07-09 9:28 [U-Boot] [PATCH v2 0/7] Support Andes RISC-V l2cache on AE350 platform Andes
2019-07-09 9:28 ` [U-Boot] [PATCH v2 1/7] dm: cache: Add enable and disable ops for cache uclass Andes
2019-07-09 9:28 ` [U-Boot] [PATCH v2 2/7] dm: cache: add v5l2 cache controller driver Andes
@ 2019-07-09 9:28 ` Andes
2019-07-11 3:05 ` Bin Meng
2019-07-09 9:28 ` [U-Boot] [PATCH v2 4/7] riscv: ax25: add imply v5l2 cache controller Andes
` (3 subsequent siblings)
6 siblings, 1 reply; 18+ messages in thread
From: Andes @ 2019-07-09 9:28 UTC (permalink / raw)
To: u-boot
From: Rick Chen <rick@andestech.com>
Find the UCLASS_CACHE driver to configure the cache controller's
settings.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Cc: KC Lin <kclin@andestech.com>
---
board/AndesTech/ax25-ae350/ax25-ae350.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c b/board/AndesTech/ax25-ae350/ax25-ae350.c
index 3d65ce7..448ab0c 100644
--- a/board/AndesTech/ax25-ae350/ax25-ae350.c
+++ b/board/AndesTech/ax25-ae350/ax25-ae350.c
@@ -11,6 +11,7 @@
#include <linux/io.h>
#include <faraday/ftsmc020.h>
#include <fdtdec.h>
+#include <dm.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -93,10 +94,18 @@ int smc_init(void)
return 0;
}
+void v5l2_init(void)
+{
+ struct udevice *dev;
+
+ uclass_get_device(UCLASS_CACHE, 0, &dev);
+}
+
#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
smc_init();
+ v5l2_init();
return 0;
}
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v2 3/7] riscv: ae350: use the v5l2 driver to configure the cache
2019-07-09 9:28 ` [U-Boot] [PATCH v2 3/7] riscv: ae350: use the v5l2 driver to configure the cache Andes
@ 2019-07-11 3:05 ` Bin Meng
0 siblings, 0 replies; 18+ messages in thread
From: Bin Meng @ 2019-07-11 3:05 UTC (permalink / raw)
To: u-boot
On Tue, Jul 9, 2019 at 5:34 PM Andes <uboot@andestech.com> wrote:
>
> From: Rick Chen <rick@andestech.com>
>
> Find the UCLASS_CACHE driver to configure the cache controller's
> settings.
>
> Signed-off-by: Rick Chen <rick@andestech.com>
> Cc: Greentime Hu <greentime@andestech.com>
> Cc: KC Lin <kclin@andestech.com>
> ---
> board/AndesTech/ax25-ae350/ax25-ae350.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c b/board/AndesTech/ax25-ae350/ax25-ae350.c
> index 3d65ce7..448ab0c 100644
> --- a/board/AndesTech/ax25-ae350/ax25-ae350.c
> +++ b/board/AndesTech/ax25-ae350/ax25-ae350.c
> @@ -11,6 +11,7 @@
> #include <linux/io.h>
> #include <faraday/ftsmc020.h>
> #include <fdtdec.h>
> +#include <dm.h>
>
> DECLARE_GLOBAL_DATA_PTR;
>
> @@ -93,10 +94,18 @@ int smc_init(void)
> return 0;
> }
>
> +void v5l2_init(void)
This should be static.
> +{
> + struct udevice *dev;
> +
> + uclass_get_device(UCLASS_CACHE, 0, &dev);
> +}
> +
> #ifdef CONFIG_BOARD_EARLY_INIT_F
> int board_early_init_f(void)
> {
> smc_init();
> + v5l2_init();
>
> return 0;
> }
> --
Other than that,
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Regards,
Bin
^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v2 4/7] riscv: ax25: add imply v5l2 cache controller
2019-07-09 9:28 [U-Boot] [PATCH v2 0/7] Support Andes RISC-V l2cache on AE350 platform Andes
` (2 preceding siblings ...)
2019-07-09 9:28 ` [U-Boot] [PATCH v2 3/7] riscv: ae350: use the v5l2 driver to configure the cache Andes
@ 2019-07-09 9:28 ` Andes
2019-07-11 3:28 ` Bin Meng
2019-07-09 9:28 ` [U-Boot] [PATCH v2 5/7] riscv: cache: Flush L2 cache before jump to linux Andes
` (2 subsequent siblings)
6 siblings, 1 reply; 18+ messages in thread
From: Andes @ 2019-07-09 9:28 UTC (permalink / raw)
To: u-boot
From: Rick Chen <rick@andestech.com>
Select the v5l2 UCLASS_CACHE driver for ax25.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Cc: KC Lin <kclin@andestech.com>
---
arch/riscv/cpu/ax25/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
index 6b4b92e..49be775 100644
--- a/arch/riscv/cpu/ax25/Kconfig
+++ b/arch/riscv/cpu/ax25/Kconfig
@@ -4,6 +4,7 @@ config RISCV_NDS
imply CPU
imply CPU_RISCV
imply RISCV_TIMER
+ imply V5L2_CACHE
imply ANDES_PLIC if RISCV_MMODE
imply ANDES_PLMT if RISCV_MMODE
help
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v2 5/7] riscv: cache: Flush L2 cache before jump to linux
2019-07-09 9:28 [U-Boot] [PATCH v2 0/7] Support Andes RISC-V l2cache on AE350 platform Andes
` (3 preceding siblings ...)
2019-07-09 9:28 ` [U-Boot] [PATCH v2 4/7] riscv: ax25: add imply v5l2 cache controller Andes
@ 2019-07-09 9:28 ` Andes
2019-07-11 4:20 ` Bin Meng
2019-07-09 9:28 ` [U-Boot] [PATCH v2 6/7] riscv: dts: move out AE350 L2 node from cpus node Andes
2019-07-09 9:28 ` [U-Boot] [PATCH v2 7/7] riscv: ax25: use CCTL to flush d-cache Andes
6 siblings, 1 reply; 18+ messages in thread
From: Andes @ 2019-07-09 9:28 UTC (permalink / raw)
To: u-boot
From: Rick Chen <rick@andestech.com>
Flush and disable cache in cleanup_before_linux()
which will be called before jump to linux.
The sequence will be preferred as below:
L1 flush -> L1 disable -> L2 flush -> L2 disable
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Cc: KC Lin <kclin@andestech.com>
---
arch/riscv/cpu/ax25/cpu.c | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/ax25/cpu.c
index 76689b2..31a714e 100644
--- a/arch/riscv/cpu/ax25/cpu.c
+++ b/arch/riscv/cpu/ax25/cpu.c
@@ -7,6 +7,29 @@
/* CPU specific code */
#include <common.h>
#include <asm/cache.h>
+#include <dm.h>
+#include <dm/uclass-internal.h>
+#include <cache.h>
+
+void enable_v5l2(void)
+{
+ struct udevice *dev = NULL;
+
+ uclass_find_first_device(UCLASS_CACHE, &dev);
+
+ if (dev)
+ cache_enable(dev);
+}
+
+void disable_v5l2(void)
+{
+ struct udevice *dev = NULL;
+
+ uclass_find_first_device(UCLASS_CACHE, &dev);
+
+ if (dev)
+ cache_disable(dev);
+}
/*
* cleanup_before_linux() is called just before we call linux
@@ -22,6 +45,9 @@ int cleanup_before_linux(void)
cache_flush();
icache_disable();
dcache_disable();
+#ifdef CONFIG_RISCV_NDS_CACHE
+ disable_v5l2();
+#endif
return 0;
}
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v2 5/7] riscv: cache: Flush L2 cache before jump to linux
2019-07-09 9:28 ` [U-Boot] [PATCH v2 5/7] riscv: cache: Flush L2 cache before jump to linux Andes
@ 2019-07-11 4:20 ` Bin Meng
2019-07-17 7:24 ` Rick Chen
0 siblings, 1 reply; 18+ messages in thread
From: Bin Meng @ 2019-07-11 4:20 UTC (permalink / raw)
To: u-boot
On Tue, Jul 9, 2019 at 5:34 PM Andes <uboot@andestech.com> wrote:
>
> From: Rick Chen <rick@andestech.com>
>
> Flush and disable cache in cleanup_before_linux()
> which will be called before jump to linux.
>
> The sequence will be preferred as below:
> L1 flush -> L1 disable -> L2 flush -> L2 disable
>
> Signed-off-by: Rick Chen <rick@andestech.com>
> Cc: Greentime Hu <greentime@andestech.com>
> Cc: KC Lin <kclin@andestech.com>
> ---
> arch/riscv/cpu/ax25/cpu.c | 26 ++++++++++++++++++++++++++
> 1 file changed, 26 insertions(+)
>
> diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/ax25/cpu.c
> index 76689b2..31a714e 100644
> --- a/arch/riscv/cpu/ax25/cpu.c
> +++ b/arch/riscv/cpu/ax25/cpu.c
> @@ -7,6 +7,29 @@
> /* CPU specific code */
> #include <common.h>
> #include <asm/cache.h>
> +#include <dm.h>
> +#include <dm/uclass-internal.h>
> +#include <cache.h>
> +
> +void enable_v5l2(void)
> +{
> + struct udevice *dev = NULL;
> +
> + uclass_find_first_device(UCLASS_CACHE, &dev);
> +
> + if (dev)
> + cache_enable(dev);
> +}
> +
> +void disable_v5l2(void)
> +{
> + struct udevice *dev = NULL;
> +
> + uclass_find_first_device(UCLASS_CACHE, &dev);
> +
> + if (dev)
> + cache_disable(dev);
> +}
>
> /*
> * cleanup_before_linux() is called just before we call linux
> @@ -22,6 +45,9 @@ int cleanup_before_linux(void)
> cache_flush();
> icache_disable();
> dcache_disable();
> +#ifdef CONFIG_RISCV_NDS_CACHE
> + disable_v5l2();
> +#endif
Since dcache_disable() is a weak symbol, could you please move the
codes in disable_v5l2() to the AX25 specific implementation of
dcache_disable()?
Regards,
Bin
^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v2 5/7] riscv: cache: Flush L2 cache before jump to linux
2019-07-11 4:20 ` Bin Meng
@ 2019-07-17 7:24 ` Rick Chen
0 siblings, 0 replies; 18+ messages in thread
From: Rick Chen @ 2019-07-17 7:24 UTC (permalink / raw)
To: u-boot
Hi Bin
>
> On Tue, Jul 9, 2019 at 5:34 PM Andes <uboot@andestech.com> wrote:
> >
> > From: Rick Chen <rick@andestech.com>
> >
> > Flush and disable cache in cleanup_before_linux()
> > which will be called before jump to linux.
> >
> > The sequence will be preferred as below:
> > L1 flush -> L1 disable -> L2 flush -> L2 disable
> >
> > Signed-off-by: Rick Chen <rick@andestech.com>
> > Cc: Greentime Hu <greentime@andestech.com>
> > Cc: KC Lin <kclin@andestech.com>
> > ---
> > arch/riscv/cpu/ax25/cpu.c | 26 ++++++++++++++++++++++++++
> > 1 file changed, 26 insertions(+)
> >
> > diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/ax25/cpu.c
> > index 76689b2..31a714e 100644
> > --- a/arch/riscv/cpu/ax25/cpu.c
> > +++ b/arch/riscv/cpu/ax25/cpu.c
> > @@ -7,6 +7,29 @@
> > /* CPU specific code */
> > #include <common.h>
> > #include <asm/cache.h>
> > +#include <dm.h>
> > +#include <dm/uclass-internal.h>
> > +#include <cache.h>
> > +
> > +void enable_v5l2(void)
> > +{
> > + struct udevice *dev = NULL;
> > +
> > + uclass_find_first_device(UCLASS_CACHE, &dev);
> > +
> > + if (dev)
> > + cache_enable(dev);
> > +}
> > +
> > +void disable_v5l2(void)
> > +{
> > + struct udevice *dev = NULL;
> > +
> > + uclass_find_first_device(UCLASS_CACHE, &dev);
> > +
> > + if (dev)
> > + cache_disable(dev);
> > +}
> >
> > /*
> > * cleanup_before_linux() is called just before we call linux
> > @@ -22,6 +45,9 @@ int cleanup_before_linux(void)
> > cache_flush();
> > icache_disable();
> > dcache_disable();
> > +#ifdef CONFIG_RISCV_NDS_CACHE
> > + disable_v5l2();
> > +#endif
>
> Since dcache_disable() is a weak symbol, could you please move the
> codes in disable_v5l2() to the AX25 specific implementation of
> dcache_disable()?
>
OK.
I will the codes in disable_v5l2() into dcache_disable().
Thanks
Rick
> Regards,
> Bin
^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v2 6/7] riscv: dts: move out AE350 L2 node from cpus node
2019-07-09 9:28 [U-Boot] [PATCH v2 0/7] Support Andes RISC-V l2cache on AE350 platform Andes
` (4 preceding siblings ...)
2019-07-09 9:28 ` [U-Boot] [PATCH v2 5/7] riscv: cache: Flush L2 cache before jump to linux Andes
@ 2019-07-09 9:28 ` Andes
2019-07-11 4:21 ` Bin Meng
2019-07-09 9:28 ` [U-Boot] [PATCH v2 7/7] riscv: ax25: use CCTL to flush d-cache Andes
6 siblings, 1 reply; 18+ messages in thread
From: Andes @ 2019-07-09 9:28 UTC (permalink / raw)
To: u-boot
From: Rick Chen <rick@andestech.com>
When L2 node exists inside cpus node, uclass_get_device
can not parse L2 node successfully. So move it outside
from cpus node.
Also add tag-ram-ctl and data-ram-ctl attributes for
v5l2 cache controller driver. This can adjust timing
by requirement from dtb to improve performance.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Cc: KC Lin <kclin@andestech.com>
---
arch/riscv/dts/ae350_32.dts | 17 +++++++++++------
arch/riscv/dts/ae350_64.dts | 17 +++++++++++------
2 files changed, 22 insertions(+), 12 deletions(-)
diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
index cb6ee13..97b7cee 100644
--- a/arch/riscv/dts/ae350_32.dts
+++ b/arch/riscv/dts/ae350_32.dts
@@ -62,13 +62,18 @@
compatible = "riscv,cpu-intc";
};
};
+ };
- L2: l2-cache at e0500000 {
- compatible = "cache";
- cache-level = <2>;
- cache-size = <0x40000>;
- reg = <0x0 0xe0500000 0x0 0x40000>;
- };
+ L2: l2-cache at e0500000 {
+ compatible = "v5l2cache";
+ cache-level = <2>;
+ cache-size = <0x40000>;
+ reg = <0xe0500000 0x40000>;
+ andes,inst-prefetch = <3>;
+ andes,data-prefetch = <3>;
+ /* The value format is <XRAMOCTL XRAMICTL> */
+ andes,tag-ram-ctl = <0 0>;
+ andes,data-ram-ctl = <0 0>;
};
memory at 0 {
diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts
index 705491a..d8f00f8 100644
--- a/arch/riscv/dts/ae350_64.dts
+++ b/arch/riscv/dts/ae350_64.dts
@@ -62,13 +62,18 @@
compatible = "riscv,cpu-intc";
};
};
+ };
- L2: l2-cache at e0500000 {
- compatible = "cache";
- cache-level = <2>;
- cache-size = <0x40000>;
- reg = <0x0 0xe0500000 0x0 0x40000>;
- };
+ L2: l2-cache at e0500000 {
+ compatible = "v5l2cache";
+ cache-level = <2>;
+ cache-size = <0x40000>;
+ reg = <0x0 0xe0500000 0x0 0x40000>;
+ andes,inst-prefetch = <3>;
+ andes,data-prefetch = <3>;
+ /* The value format is <XRAMOCTL XRAMICTL> */
+ andes,tag-ram-ctl = <0 0>;
+ andes,data-ram-ctl = <0 0>;
};
memory at 0 {
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v2 6/7] riscv: dts: move out AE350 L2 node from cpus node
2019-07-09 9:28 ` [U-Boot] [PATCH v2 6/7] riscv: dts: move out AE350 L2 node from cpus node Andes
@ 2019-07-11 4:21 ` Bin Meng
0 siblings, 0 replies; 18+ messages in thread
From: Bin Meng @ 2019-07-11 4:21 UTC (permalink / raw)
To: u-boot
On Tue, Jul 9, 2019 at 5:34 PM Andes <uboot@andestech.com> wrote:
>
> From: Rick Chen <rick@andestech.com>
>
> When L2 node exists inside cpus node, uclass_get_device
> can not parse L2 node successfully. So move it outside
> from cpus node.
>
> Also add tag-ram-ctl and data-ram-ctl attributes for
> v5l2 cache controller driver. This can adjust timing
> by requirement from dtb to improve performance.
>
> Signed-off-by: Rick Chen <rick@andestech.com>
> Cc: Greentime Hu <greentime@andestech.com>
> Cc: KC Lin <kclin@andestech.com>
> ---
> arch/riscv/dts/ae350_32.dts | 17 +++++++++++------
> arch/riscv/dts/ae350_64.dts | 17 +++++++++++------
> 2 files changed, 22 insertions(+), 12 deletions(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v2 7/7] riscv: ax25: use CCTL to flush d-cache
2019-07-09 9:28 [U-Boot] [PATCH v2 0/7] Support Andes RISC-V l2cache on AE350 platform Andes
` (5 preceding siblings ...)
2019-07-09 9:28 ` [U-Boot] [PATCH v2 6/7] riscv: dts: move out AE350 L2 node from cpus node Andes
@ 2019-07-09 9:28 ` Andes
2019-07-11 5:35 ` Bin Meng
6 siblings, 1 reply; 18+ messages in thread
From: Andes @ 2019-07-09 9:28 UTC (permalink / raw)
To: u-boot
From: Rick Chen <rick@andestech.com>
Use CCTL command to do d-cache write back
and invalidate instead of fence.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Cc: KC Lin <kclin@andestech.com>
---
arch/riscv/cpu/ax25/cache.c | 22 +++++++++++++---------
1 file changed, 13 insertions(+), 9 deletions(-)
diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c
index cd95058..93f8d28 100644
--- a/arch/riscv/cpu/ax25/cache.c
+++ b/arch/riscv/cpu/ax25/cache.c
@@ -5,17 +5,21 @@
*/
#include <common.h>
+#include <asm/csr.h>
+
+#ifdef CONFIG_RISCV_NDS_CACHE
+/* mcctlcommand */
+#define CCTL_REG_MCCTLCOMMAND_NUM 0x7cc
+
+/* D-cache operation */
+#define CCTL_L1D_WBINVAL_ALL 6
+#endif
void flush_dcache_all(void)
{
- /*
- * Andes' AX25 does not have a coherence agent. U-Boot must use data
- * cache flush and invalidate functions to keep data in the system
- * coherent.
- * The implementation of the fence instruction in the AX25 flushes the
- * data cache and is used for this purpose.
- */
- asm volatile ("fence" ::: "memory");
+#ifdef CONFIG_RISCV_NDS_CACHE
+ csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL);
+#endif
}
void flush_dcache_range(unsigned long start, unsigned long end)
@@ -72,8 +76,8 @@ void dcache_disable(void)
{
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
#ifdef CONFIG_RISCV_NDS_CACHE
+ csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL);
asm volatile (
- "fence\n\t"
"csrr t1, mcache_ctl\n\t"
"andi t0, t1, ~0x2\n\t"
"csrw mcache_ctl, t0\n\t"
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v2 7/7] riscv: ax25: use CCTL to flush d-cache
2019-07-09 9:28 ` [U-Boot] [PATCH v2 7/7] riscv: ax25: use CCTL to flush d-cache Andes
@ 2019-07-11 5:35 ` Bin Meng
0 siblings, 0 replies; 18+ messages in thread
From: Bin Meng @ 2019-07-11 5:35 UTC (permalink / raw)
To: u-boot
On Tue, Jul 9, 2019 at 5:34 PM Andes <uboot@andestech.com> wrote:
>
> From: Rick Chen <rick@andestech.com>
>
> Use CCTL command to do d-cache write back
> and invalidate instead of fence.
>
> Signed-off-by: Rick Chen <rick@andestech.com>
> Cc: Greentime Hu <greentime@andestech.com>
> Cc: KC Lin <kclin@andestech.com>
> ---
> arch/riscv/cpu/ax25/cache.c | 22 +++++++++++++---------
> 1 file changed, 13 insertions(+), 9 deletions(-)
>
> diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c
> index cd95058..93f8d28 100644
> --- a/arch/riscv/cpu/ax25/cache.c
> +++ b/arch/riscv/cpu/ax25/cache.c
> @@ -5,17 +5,21 @@
> */
>
> #include <common.h>
> +#include <asm/csr.h>
> +
> +#ifdef CONFIG_RISCV_NDS_CACHE
> +/* mcctlcommand */
> +#define CCTL_REG_MCCTLCOMMAND_NUM 0x7cc
Please use tab before 0x7cc.
> +
> +/* D-cache operation */
> +#define CCTL_L1D_WBINVAL_ALL 6
> +#endif
>
Other than above,
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Regards,
Bin
^ permalink raw reply [flat|nested] 18+ messages in thread