* [PATCH 00/92] ram: rk3399: Add LPDDR4 support
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Yes, it can be possible to break this series into multiple sub series
but idea here is to mark all the required changes to support LPDDR4
in rk3399 in one set. if required we can break it from next versions.
This is the initial set for supporting LPDDR4 with associated
features.
Thanks to
- YouMin Chen
- Akash Gajjar
- Kever Yang
for supporting all the help on this work.
On summary this series support
- Code warning and fixes
- rank detection, this would required to probe single channel
sdram configured in NanoPI-NEO4
- LPDDR4 support, tested in Rockpro64 and Rock-PI-4
patch 0001 - 0033: fix code warnings, prints, new macros
patch 0034 - 0051: rank detection, sdram debug code
patch 0052: Use DDR3-1800 on NanoPI-NEO4
patch 0053 - 0089: lpddr4 support
patch 0090: LPDDR4-100 timings
patch 0091: Use LPDDR4-100 on Rockpro64
patch 0092: Use LPDDR4-100 on Rock-PI 4
Note: Puma rk3399 has SPL size overflow, better to enable TPL
for this board.
Any inputs?
Jagan.
Jagan Teki (92):
ram: rk3399: Fix code warnings
ram: rk3399: Add space between string with format specifier
ram: rk3399: Add proper spaces in data training
ram: rk3399: Handle data training return types
ram: rk3399: Order include files
ram: rk3399: Move macro after include files
ram: rk3399: Clear PI_175 interrupts in data training
ram: rk3399: Use rank mask in ca data training
ram: rk3399: Use rank mask in wdql data training
ram: rk3399: Add ddrtype enc macro
ram: rk3399: Add channel number encoder macro
ram: rk3399: Add row_3_4 enc macro
ram: rk3399: Add chipinfo macro
ram: rk3399: Add rank enc macro
ram: rk3399: Add column enc macro
ram: rk3399: Add bk enc macro
ram: rk3399: Add dbw enc macro
ram: rk3399: Add cs0_rw macro
ram: rk3399: Add cs1_rw macro
ram: rk3399: Add bw enc macro
ram: rk3399: Rename sys_reg with sys_reg2
ram: rk3399: Update cs0_row to use sys_reg3
ram: rk3399: Update cs1_row to use sys_reg3
ram: rk3399: Add cs1_col enc macro
ram: rk3399: Add ddr version enc macro
ram: rk3399: Add ddrtimingC0
ram: rk3399: Add DdrMode
ram: rk3399: Handle pctl_cfg return type
ram: rk3399: s/tsel_wr_select_n/tsel_wr_select_dq_n
ram: rk3399: s/tsel_wr_select_p/tsel_wr_select_dq_p
ram: rk3399: s/ca_tsel_wr_select_n/tsel_wr_select_ca_n
ram: rk3399: s/ca_tsel_wr_select_p/tsel_wr_select_ca_p
ram: rk3399: Order tsel variables
ram: rk3399: Add phy pctrl reset support
ram: rk3399: Move pwrup_srefresh_exit to dram_info
ram: rk3399: Add pctl start support
ram: rockchip: rk3399: Add cap_info structure
ram: rk3399: s/rk3399_base_params/sdram_base_params
ram: rk3399: Move common sdram structures in common header
arm: include: rockchip: Move dramtypes to common header
arm: include: rockchip: Add DDR4 enum
ram: rockchip: Add initial Kconfig
debug_uart: Add printdec
ram: rockchip: Add debug sdram driver
ram: rockchip: debug: Add sdram_print_ddr_info
ram: rockchip: debug: Get the cs capacity
ram: rk3399: debug: Add sdram_print_stride
ram: rk3399: Compute stride for 2 channels
ram: rk3399: Compute stride for 1 channel a
ram: rk3399: Add rank detection support
ram: rk3399: Enable sdram debug functions
rockchip: dts: rk3399: nanopi-neo4: Use DDR3-1866 dtsi
clk: rockchip: rk3399: Fix check patch warnings and checks
clk: rockchip: rk3399: Set 50MHz ddr clock
clk: rockchip: rk3399: Set 400MHz ddr clock
ram: rk3399: Add spaces in pctl_cfg
ram: rk3399: Configure phy IO in ds odt
ram: rk3399: Add lpddr4 rank mask for cs training
ram: rk3399: Add lpddr4 rank mask for wdql training
ram: rk3399: Move mode_sel assignment
ram: rk3399: Don't wait for PLL lock in lpddr4
ram: rk3399: Avoid two channel ZQ Cal Start at the same time
ram: rk3399: Configure PHY_898, PHY_919 for lpddr4
ram: rk3399: Configure BOOSTP_EN, BOOSTN_EN for lpddr4
ram: rk3399: Configure SLEWP_EN, SLEWN_EN for lpddr4
ram: rk3399: Configure PHY RX_CM_INPUT for lpddr4
ram: rk3399: Map chipselect for lpddr4
ram: rk3399: Configure tsel write ca for lpddr4
ram: rk3399: Don't disable dfi dram clk for lpddr4, rank 1
ram: rk3399: Add IO settings
ram: sdram: Configure lpddr4 tsel rd, wr based on IO settings
ram: rk3399: Add tsel control clock drive
ram: rk3399: Configure soc odt support
ram: rk3399: Get lpddr4 tsel_rd_en from io settings
ram: rk3399: Update lpddr4 vref based on io settings
ram: rk3399: Update lpddr4 mode_sel based on io settings
ram: rk3399: Update lpddr4 vref_mode_ac
ram: rk3399: Add LPPDR4 mr detection
arm: include: rockchip: Add rk3399 pmu file
rockchip: rk3399: syscon: Add pmu support
rockchip: dts: rk3399: Add u-boot,dm-pre-reloc for pmu
ram: rk3399: Add LPPDDR4-400 timings inc
ram: rk3399: Add LPPDDR4-800 timings inc
ram: rk3399: Add lpddr4 set rate support
ram: rk3399: Set lpddr4 dq odt
ram: rk3399: Set lpddr4 ca odt
ram: rk3399: Set lpddr4 MR3
ram: rk3399: Set lpddr4 MR12
ram: rk3399: Set lpddr4 MR14
rockchip: dts: rk3399: Add LPDDR4-100 timings
rockchip: dts: rk3399: rockpro64: Use LPDDR4-100 dtsi
rockchip: dts: rk3399: rock-pi-4: Use LPDDR4-100 dtsi
arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi | 1 +
arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi | 1 +
arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 1 +
arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi | 1537 ++++++++++++
arch/arm/dts/rk3399-u-boot.dtsi | 4 +
.../include/asm/arch-rockchip/pmu_rk3399.h | 72 +
arch/arm/include/asm/arch-rockchip/sdram.h | 6 -
.../include/asm/arch-rockchip/sdram_common.h | 89 +
.../include/asm/arch-rockchip/sdram_rk322x.h | 7 -
.../include/asm/arch-rockchip/sdram_rk3399.h | 65 +-
arch/arm/mach-rockchip/rk3399/syscon_rk3399.c | 8 +
drivers/clk/rockchip/clk_rk3399.c | 76 +-
drivers/ram/Kconfig | 1 +
drivers/ram/rockchip/Kconfig | 26 +
drivers/ram/rockchip/Makefile | 3 +-
.../ram/rockchip/sdram-rk3399-lpddr4-400.inc | 1570 ++++++++++++
.../ram/rockchip/sdram-rk3399-lpddr4-800.inc | 1570 ++++++++++++
drivers/ram/rockchip/sdram_debug.c | 147 ++
drivers/ram/rockchip/sdram_rk3399.c | 2176 ++++++++++++++---
include/debug_uart.h | 19 +
20 files changed, 6964 insertions(+), 415 deletions(-)
create mode 100644 arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi
create mode 100644 arch/arm/include/asm/arch-rockchip/pmu_rk3399.h
create mode 100644 drivers/ram/rockchip/Kconfig
create mode 100644 drivers/ram/rockchip/sdram-rk3399-lpddr4-400.inc
create mode 100644 drivers/ram/rockchip/sdram-rk3399-lpddr4-800.inc
create mode 100644 drivers/ram/rockchip/sdram_debug.c
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 00/92] ram: rk3399: Add LPDDR4 support
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
Yes, it can be possible to break this series into multiple sub series
but idea here is to mark all the required changes to support LPDDR4
in rk3399 in one set. if required we can break it from next versions.
This is the initial set for supporting LPDDR4 with associated
features.
Thanks to
- YouMin Chen
- Akash Gajjar
- Kever Yang
for supporting all the help on this work.
On summary this series support
- Code warning and fixes
- rank detection, this would required to probe single channel
sdram configured in NanoPI-NEO4
- LPDDR4 support, tested in Rockpro64 and Rock-PI-4
patch 0001 - 0033: fix code warnings, prints, new macros
patch 0034 - 0051: rank detection, sdram debug code
patch 0052: Use DDR3-1800 on NanoPI-NEO4
patch 0053 - 0089: lpddr4 support
patch 0090: LPDDR4-100 timings
patch 0091: Use LPDDR4-100 on Rockpro64
patch 0092: Use LPDDR4-100 on Rock-PI 4
Note: Puma rk3399 has SPL size overflow, better to enable TPL
for this board.
Any inputs?
Jagan.
Jagan Teki (92):
ram: rk3399: Fix code warnings
ram: rk3399: Add space between string with format specifier
ram: rk3399: Add proper spaces in data training
ram: rk3399: Handle data training return types
ram: rk3399: Order include files
ram: rk3399: Move macro after include files
ram: rk3399: Clear PI_175 interrupts in data training
ram: rk3399: Use rank mask in ca data training
ram: rk3399: Use rank mask in wdql data training
ram: rk3399: Add ddrtype enc macro
ram: rk3399: Add channel number encoder macro
ram: rk3399: Add row_3_4 enc macro
ram: rk3399: Add chipinfo macro
ram: rk3399: Add rank enc macro
ram: rk3399: Add column enc macro
ram: rk3399: Add bk enc macro
ram: rk3399: Add dbw enc macro
ram: rk3399: Add cs0_rw macro
ram: rk3399: Add cs1_rw macro
ram: rk3399: Add bw enc macro
ram: rk3399: Rename sys_reg with sys_reg2
ram: rk3399: Update cs0_row to use sys_reg3
ram: rk3399: Update cs1_row to use sys_reg3
ram: rk3399: Add cs1_col enc macro
ram: rk3399: Add ddr version enc macro
ram: rk3399: Add ddrtimingC0
ram: rk3399: Add DdrMode
ram: rk3399: Handle pctl_cfg return type
ram: rk3399: s/tsel_wr_select_n/tsel_wr_select_dq_n
ram: rk3399: s/tsel_wr_select_p/tsel_wr_select_dq_p
ram: rk3399: s/ca_tsel_wr_select_n/tsel_wr_select_ca_n
ram: rk3399: s/ca_tsel_wr_select_p/tsel_wr_select_ca_p
ram: rk3399: Order tsel variables
ram: rk3399: Add phy pctrl reset support
ram: rk3399: Move pwrup_srefresh_exit to dram_info
ram: rk3399: Add pctl start support
ram: rockchip: rk3399: Add cap_info structure
ram: rk3399: s/rk3399_base_params/sdram_base_params
ram: rk3399: Move common sdram structures in common header
arm: include: rockchip: Move dramtypes to common header
arm: include: rockchip: Add DDR4 enum
ram: rockchip: Add initial Kconfig
debug_uart: Add printdec
ram: rockchip: Add debug sdram driver
ram: rockchip: debug: Add sdram_print_ddr_info
ram: rockchip: debug: Get the cs capacity
ram: rk3399: debug: Add sdram_print_stride
ram: rk3399: Compute stride for 2 channels
ram: rk3399: Compute stride for 1 channel a
ram: rk3399: Add rank detection support
ram: rk3399: Enable sdram debug functions
rockchip: dts: rk3399: nanopi-neo4: Use DDR3-1866 dtsi
clk: rockchip: rk3399: Fix check patch warnings and checks
clk: rockchip: rk3399: Set 50MHz ddr clock
clk: rockchip: rk3399: Set 400MHz ddr clock
ram: rk3399: Add spaces in pctl_cfg
ram: rk3399: Configure phy IO in ds odt
ram: rk3399: Add lpddr4 rank mask for cs training
ram: rk3399: Add lpddr4 rank mask for wdql training
ram: rk3399: Move mode_sel assignment
ram: rk3399: Don't wait for PLL lock in lpddr4
ram: rk3399: Avoid two channel ZQ Cal Start at the same time
ram: rk3399: Configure PHY_898, PHY_919 for lpddr4
ram: rk3399: Configure BOOSTP_EN, BOOSTN_EN for lpddr4
ram: rk3399: Configure SLEWP_EN, SLEWN_EN for lpddr4
ram: rk3399: Configure PHY RX_CM_INPUT for lpddr4
ram: rk3399: Map chipselect for lpddr4
ram: rk3399: Configure tsel write ca for lpddr4
ram: rk3399: Don't disable dfi dram clk for lpddr4, rank 1
ram: rk3399: Add IO settings
ram: sdram: Configure lpddr4 tsel rd, wr based on IO settings
ram: rk3399: Add tsel control clock drive
ram: rk3399: Configure soc odt support
ram: rk3399: Get lpddr4 tsel_rd_en from io settings
ram: rk3399: Update lpddr4 vref based on io settings
ram: rk3399: Update lpddr4 mode_sel based on io settings
ram: rk3399: Update lpddr4 vref_mode_ac
ram: rk3399: Add LPPDR4 mr detection
arm: include: rockchip: Add rk3399 pmu file
rockchip: rk3399: syscon: Add pmu support
rockchip: dts: rk3399: Add u-boot,dm-pre-reloc for pmu
ram: rk3399: Add LPPDDR4-400 timings inc
ram: rk3399: Add LPPDDR4-800 timings inc
ram: rk3399: Add lpddr4 set rate support
ram: rk3399: Set lpddr4 dq odt
ram: rk3399: Set lpddr4 ca odt
ram: rk3399: Set lpddr4 MR3
ram: rk3399: Set lpddr4 MR12
ram: rk3399: Set lpddr4 MR14
rockchip: dts: rk3399: Add LPDDR4-100 timings
rockchip: dts: rk3399: rockpro64: Use LPDDR4-100 dtsi
rockchip: dts: rk3399: rock-pi-4: Use LPDDR4-100 dtsi
arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi | 1 +
arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi | 1 +
arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 1 +
arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi | 1537 ++++++++++++
arch/arm/dts/rk3399-u-boot.dtsi | 4 +
.../include/asm/arch-rockchip/pmu_rk3399.h | 72 +
arch/arm/include/asm/arch-rockchip/sdram.h | 6 -
.../include/asm/arch-rockchip/sdram_common.h | 89 +
.../include/asm/arch-rockchip/sdram_rk322x.h | 7 -
.../include/asm/arch-rockchip/sdram_rk3399.h | 65 +-
arch/arm/mach-rockchip/rk3399/syscon_rk3399.c | 8 +
drivers/clk/rockchip/clk_rk3399.c | 76 +-
drivers/ram/Kconfig | 1 +
drivers/ram/rockchip/Kconfig | 26 +
drivers/ram/rockchip/Makefile | 3 +-
.../ram/rockchip/sdram-rk3399-lpddr4-400.inc | 1570 ++++++++++++
.../ram/rockchip/sdram-rk3399-lpddr4-800.inc | 1570 ++++++++++++
drivers/ram/rockchip/sdram_debug.c | 147 ++
drivers/ram/rockchip/sdram_rk3399.c | 2176 ++++++++++++++---
include/debug_uart.h | 19 +
20 files changed, 6964 insertions(+), 415 deletions(-)
create mode 100644 arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi
create mode 100644 arch/arm/include/asm/arch-rockchip/pmu_rk3399.h
create mode 100644 drivers/ram/rockchip/Kconfig
create mode 100644 drivers/ram/rockchip/sdram-rk3399-lpddr4-400.inc
create mode 100644 drivers/ram/rockchip/sdram-rk3399-lpddr4-800.inc
create mode 100644 drivers/ram/rockchip/sdram_debug.c
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply [flat|nested] 204+ messages in thread
* [PATCH 01/92] ram: rk3399: Fix code warnings
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Fix checkpatch warninigs on sdram_rk3399.c like
- Avoid CamelCase
- Unnecessary parentheses
- Alignment should match open parenthesis
- multiple blank lines
- misspelled
- spaces preferred around that '>>'
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 48 ++++++++++++++---------------
1 file changed, 24 insertions(+), 24 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 52518656c4..541e4a4b1e 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -47,7 +47,7 @@ struct dram_info {
#define PRESET_GPIO0_HOLD(n) ((0x1 << (7 + 16)) | ((n) << 7))
#define PRESET_GPIO1_HOLD(n) ((0x1 << (8 + 16)) | ((n) << 8))
-#define PHY_DRV_ODT_Hi_Z 0x0
+#define PHY_DRV_ODT_HI_Z 0x0
#define PHY_DRV_ODT_240 0x1
#define PHY_DRV_ODT_120 0x8
#define PHY_DRV_ODT_80 0x9
@@ -150,7 +150,7 @@ static void set_memory_map(const struct chan_info *chan, u32 channel,
((16 - row) << 24));
/* PI_41 PI_CS_MAP:RW:24:4 */
clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24);
- if ((sdram_ch->rank == 1) && (sdram_params->base.dramtype == DDR3))
+ if (sdram_ch->rank == 1 && sdram_params->base.dramtype == DDR3)
writel(0x2EC7FFFF, &denali_pi[34]);
}
@@ -166,10 +166,10 @@ static void set_ds_odt(const struct chan_info *chan,
u32 reg_value;
if (sdram_params->base.dramtype == LPDDR4) {
- tsel_rd_select_p = PHY_DRV_ODT_Hi_Z;
+ tsel_rd_select_p = PHY_DRV_ODT_HI_Z;
tsel_wr_select_p = PHY_DRV_ODT_40;
ca_tsel_wr_select_p = PHY_DRV_ODT_40;
- tsel_idle_select_p = PHY_DRV_ODT_Hi_Z;
+ tsel_idle_select_p = PHY_DRV_ODT_HI_Z;
tsel_rd_select_n = PHY_DRV_ODT_240;
tsel_wr_select_n = PHY_DRV_ODT_40;
@@ -181,10 +181,10 @@ static void set_ds_odt(const struct chan_info *chan,
ca_tsel_wr_select_p = PHY_DRV_ODT_48;
tsel_idle_select_p = PHY_DRV_ODT_240;
- tsel_rd_select_n = PHY_DRV_ODT_Hi_Z;
+ tsel_rd_select_n = PHY_DRV_ODT_HI_Z;
tsel_wr_select_n = PHY_DRV_ODT_34_3;
ca_tsel_wr_select_n = PHY_DRV_ODT_48;
- tsel_idle_select_n = PHY_DRV_ODT_Hi_Z;
+ tsel_idle_select_n = PHY_DRV_ODT_HI_Z;
} else {
tsel_rd_select_p = PHY_DRV_ODT_240;
tsel_wr_select_p = PHY_DRV_ODT_34_3;
@@ -294,7 +294,7 @@ static void set_ds_odt(const struct chan_info *chan,
}
static int phy_io_config(const struct chan_info *chan,
- const struct rk3399_sdram_params *sdram_params)
+ const struct rk3399_sdram_params *sdram_params)
{
u32 *denali_phy = chan->publ->denali_phy;
u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac;
@@ -423,7 +423,6 @@ static int phy_io_config(const struct chan_info *chan,
/* PHY_939 PHY_PAD_CS_DRIVE */
clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14);
-
/* speed setting */
if (sdram_params->base.ddr_freq < 400)
speed = 0x0;
@@ -492,7 +491,7 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel,
setbits_le32(&denali_pi[0], START);
setbits_le32(&denali_ctl[0], START);
- /* Wating for phy DLL lock */
+ /* Waiting for phy DLL lock */
while (1) {
tmp = readl(&denali_phy[920]);
tmp1 = readl(&denali_phy[921]);
@@ -547,12 +546,12 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel,
/* PHY_DLL_RST_EN */
clrsetbits_le32(&denali_phy[957], 0x3 << 24, 0x2 << 24);
- /* Wating for PHY and DRAM init complete */
+ /* Waiting for PHY and DRAM init complete */
tmp = get_timer(0);
do {
if (get_timer(tmp) > timeout_ms) {
pr_err("DRAM (%s): phy failed to lock within %ld ms\n",
- __func__, timeout_ms);
+ __func__, timeout_ms);
return -ETIME;
}
} while (!(readl(&denali_ctl[203]) & (1 << 3)));
@@ -569,7 +568,7 @@ static void select_per_cs_training_index(const struct chan_info *chan,
u32 *denali_phy = chan->publ->denali_phy;
/* PHY_84 PHY_PER_CS_TRAINING_EN_0 1bit offset_16 */
- if ((readl(&denali_phy[84])>>16) & 1) {
+ if ((readl(&denali_phy[84]) >> 16) & 1) {
/*
* PHY_8/136/264/392
* phy_per_cs_training_index_X 1bit offset_24
@@ -646,7 +645,7 @@ static int data_training_ca(const struct chan_info *chan, u32 channel,
if ((((tmp >> 11) & 0x1) == 0x1) &&
(((tmp >> 13) & 0x1) == 0x1) &&
(((tmp >> 5) & 0x1) == 0x0) &&
- (obs_err == 0))
+ obs_err == 0)
break;
else if ((((tmp >> 5) & 0x1) == 0x1) ||
(obs_err == 1))
@@ -700,7 +699,7 @@ static int data_training_wl(const struct chan_info *chan, u32 channel,
if ((((tmp >> 10) & 0x1) == 0x1) &&
(((tmp >> 13) & 0x1) == 0x1) &&
(((tmp >> 4) & 0x1) == 0x0) &&
- (obs_err == 0))
+ obs_err == 0)
break;
else if ((((tmp >> 4) & 0x1) == 0x1) ||
(obs_err == 1))
@@ -759,7 +758,7 @@ static int data_training_rg(const struct chan_info *chan, u32 channel,
if ((((tmp >> 9) & 0x1) == 0x1) &&
(((tmp >> 13) & 0x1) == 0x1) &&
(((tmp >> 3) & 0x1) == 0x0) &&
- (obs_err == 0))
+ obs_err == 0)
break;
else if ((((tmp >> 3) & 0x1) == 0x1) ||
(obs_err == 1))
@@ -955,8 +954,10 @@ static void dram_all_config(struct dram_info *dram,
sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(channel);
sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(channel);
sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(channel);
- sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(channel);
- sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(channel);
+ sys_reg |= (info->cs0_row - 13) <<
+ SYS_REG_CS0_ROW_SHIFT(channel);
+ sys_reg |= (info->cs1_row - 13) <<
+ SYS_REG_CS1_ROW_SHIFT(channel);
sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(channel);
sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(channel);
@@ -991,7 +992,7 @@ static void dram_all_config(struct dram_info *dram,
}
static int switch_to_phy_index1(struct dram_info *dram,
- const struct rk3399_sdram_params *sdram_params)
+ const struct rk3399_sdram_params *sdram_params)
{
u32 channel;
u32 *denali_phy;
@@ -1026,7 +1027,7 @@ static int switch_to_phy_index1(struct dram_info *dram,
denali_phy = dram->chan[channel].publ->denali_phy;
clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8);
ret = data_training(&dram->chan[channel], channel,
- sdram_params, PI_FULL_TRAINING);
+ sdram_params, PI_FULL_TRAINING);
if (ret) {
debug("index1 training failed\n");
return ret;
@@ -1116,8 +1117,8 @@ static int conv_of_platdata(struct udevice *dev)
int ret;
ret = regmap_init_mem_platdata(dev, dtplat->reg,
- ARRAY_SIZE(dtplat->reg) / 2,
- &plat->map);
+ ARRAY_SIZE(dtplat->reg) / 2,
+ &plat->map);
if (ret)
return ret;
@@ -1199,8 +1200,8 @@ static int rk3399_dmc_probe(struct udevice *dev)
priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
debug("%s: pmugrf=%p\n", __func__, priv->pmugrf);
priv->info.base = CONFIG_SYS_SDRAM_BASE;
- priv->info.size = rockchip_sdram_size(
- (phys_addr_t)&priv->pmugrf->os_reg2);
+ priv->info.size =
+ rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg2);
#endif
return 0;
}
@@ -1218,7 +1219,6 @@ static struct ram_ops rk3399_dmc_ops = {
.get_info = rk3399_dmc_get_info,
};
-
static const struct udevice_id rk3399_dmc_ids[] = {
{ .compatible = "rockchip,rk3399-dmc" },
{ }
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 01/92] ram: rk3399: Fix code warnings
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
Fix checkpatch warninigs on sdram_rk3399.c like
- Avoid CamelCase
- Unnecessary parentheses
- Alignment should match open parenthesis
- multiple blank lines
- misspelled
- spaces preferred around that '>>'
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 48 ++++++++++++++---------------
1 file changed, 24 insertions(+), 24 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 52518656c4..541e4a4b1e 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -47,7 +47,7 @@ struct dram_info {
#define PRESET_GPIO0_HOLD(n) ((0x1 << (7 + 16)) | ((n) << 7))
#define PRESET_GPIO1_HOLD(n) ((0x1 << (8 + 16)) | ((n) << 8))
-#define PHY_DRV_ODT_Hi_Z 0x0
+#define PHY_DRV_ODT_HI_Z 0x0
#define PHY_DRV_ODT_240 0x1
#define PHY_DRV_ODT_120 0x8
#define PHY_DRV_ODT_80 0x9
@@ -150,7 +150,7 @@ static void set_memory_map(const struct chan_info *chan, u32 channel,
((16 - row) << 24));
/* PI_41 PI_CS_MAP:RW:24:4 */
clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24);
- if ((sdram_ch->rank == 1) && (sdram_params->base.dramtype == DDR3))
+ if (sdram_ch->rank == 1 && sdram_params->base.dramtype == DDR3)
writel(0x2EC7FFFF, &denali_pi[34]);
}
@@ -166,10 +166,10 @@ static void set_ds_odt(const struct chan_info *chan,
u32 reg_value;
if (sdram_params->base.dramtype == LPDDR4) {
- tsel_rd_select_p = PHY_DRV_ODT_Hi_Z;
+ tsel_rd_select_p = PHY_DRV_ODT_HI_Z;
tsel_wr_select_p = PHY_DRV_ODT_40;
ca_tsel_wr_select_p = PHY_DRV_ODT_40;
- tsel_idle_select_p = PHY_DRV_ODT_Hi_Z;
+ tsel_idle_select_p = PHY_DRV_ODT_HI_Z;
tsel_rd_select_n = PHY_DRV_ODT_240;
tsel_wr_select_n = PHY_DRV_ODT_40;
@@ -181,10 +181,10 @@ static void set_ds_odt(const struct chan_info *chan,
ca_tsel_wr_select_p = PHY_DRV_ODT_48;
tsel_idle_select_p = PHY_DRV_ODT_240;
- tsel_rd_select_n = PHY_DRV_ODT_Hi_Z;
+ tsel_rd_select_n = PHY_DRV_ODT_HI_Z;
tsel_wr_select_n = PHY_DRV_ODT_34_3;
ca_tsel_wr_select_n = PHY_DRV_ODT_48;
- tsel_idle_select_n = PHY_DRV_ODT_Hi_Z;
+ tsel_idle_select_n = PHY_DRV_ODT_HI_Z;
} else {
tsel_rd_select_p = PHY_DRV_ODT_240;
tsel_wr_select_p = PHY_DRV_ODT_34_3;
@@ -294,7 +294,7 @@ static void set_ds_odt(const struct chan_info *chan,
}
static int phy_io_config(const struct chan_info *chan,
- const struct rk3399_sdram_params *sdram_params)
+ const struct rk3399_sdram_params *sdram_params)
{
u32 *denali_phy = chan->publ->denali_phy;
u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac;
@@ -423,7 +423,6 @@ static int phy_io_config(const struct chan_info *chan,
/* PHY_939 PHY_PAD_CS_DRIVE */
clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14);
-
/* speed setting */
if (sdram_params->base.ddr_freq < 400)
speed = 0x0;
@@ -492,7 +491,7 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel,
setbits_le32(&denali_pi[0], START);
setbits_le32(&denali_ctl[0], START);
- /* Wating for phy DLL lock */
+ /* Waiting for phy DLL lock */
while (1) {
tmp = readl(&denali_phy[920]);
tmp1 = readl(&denali_phy[921]);
@@ -547,12 +546,12 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel,
/* PHY_DLL_RST_EN */
clrsetbits_le32(&denali_phy[957], 0x3 << 24, 0x2 << 24);
- /* Wating for PHY and DRAM init complete */
+ /* Waiting for PHY and DRAM init complete */
tmp = get_timer(0);
do {
if (get_timer(tmp) > timeout_ms) {
pr_err("DRAM (%s): phy failed to lock within %ld ms\n",
- __func__, timeout_ms);
+ __func__, timeout_ms);
return -ETIME;
}
} while (!(readl(&denali_ctl[203]) & (1 << 3)));
@@ -569,7 +568,7 @@ static void select_per_cs_training_index(const struct chan_info *chan,
u32 *denali_phy = chan->publ->denali_phy;
/* PHY_84 PHY_PER_CS_TRAINING_EN_0 1bit offset_16 */
- if ((readl(&denali_phy[84])>>16) & 1) {
+ if ((readl(&denali_phy[84]) >> 16) & 1) {
/*
* PHY_8/136/264/392
* phy_per_cs_training_index_X 1bit offset_24
@@ -646,7 +645,7 @@ static int data_training_ca(const struct chan_info *chan, u32 channel,
if ((((tmp >> 11) & 0x1) == 0x1) &&
(((tmp >> 13) & 0x1) == 0x1) &&
(((tmp >> 5) & 0x1) == 0x0) &&
- (obs_err == 0))
+ obs_err == 0)
break;
else if ((((tmp >> 5) & 0x1) == 0x1) ||
(obs_err == 1))
@@ -700,7 +699,7 @@ static int data_training_wl(const struct chan_info *chan, u32 channel,
if ((((tmp >> 10) & 0x1) == 0x1) &&
(((tmp >> 13) & 0x1) == 0x1) &&
(((tmp >> 4) & 0x1) == 0x0) &&
- (obs_err == 0))
+ obs_err == 0)
break;
else if ((((tmp >> 4) & 0x1) == 0x1) ||
(obs_err == 1))
@@ -759,7 +758,7 @@ static int data_training_rg(const struct chan_info *chan, u32 channel,
if ((((tmp >> 9) & 0x1) == 0x1) &&
(((tmp >> 13) & 0x1) == 0x1) &&
(((tmp >> 3) & 0x1) == 0x0) &&
- (obs_err == 0))
+ obs_err == 0)
break;
else if ((((tmp >> 3) & 0x1) == 0x1) ||
(obs_err == 1))
@@ -955,8 +954,10 @@ static void dram_all_config(struct dram_info *dram,
sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(channel);
sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(channel);
sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(channel);
- sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(channel);
- sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(channel);
+ sys_reg |= (info->cs0_row - 13) <<
+ SYS_REG_CS0_ROW_SHIFT(channel);
+ sys_reg |= (info->cs1_row - 13) <<
+ SYS_REG_CS1_ROW_SHIFT(channel);
sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(channel);
sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(channel);
@@ -991,7 +992,7 @@ static void dram_all_config(struct dram_info *dram,
}
static int switch_to_phy_index1(struct dram_info *dram,
- const struct rk3399_sdram_params *sdram_params)
+ const struct rk3399_sdram_params *sdram_params)
{
u32 channel;
u32 *denali_phy;
@@ -1026,7 +1027,7 @@ static int switch_to_phy_index1(struct dram_info *dram,
denali_phy = dram->chan[channel].publ->denali_phy;
clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8);
ret = data_training(&dram->chan[channel], channel,
- sdram_params, PI_FULL_TRAINING);
+ sdram_params, PI_FULL_TRAINING);
if (ret) {
debug("index1 training failed\n");
return ret;
@@ -1116,8 +1117,8 @@ static int conv_of_platdata(struct udevice *dev)
int ret;
ret = regmap_init_mem_platdata(dev, dtplat->reg,
- ARRAY_SIZE(dtplat->reg) / 2,
- &plat->map);
+ ARRAY_SIZE(dtplat->reg) / 2,
+ &plat->map);
if (ret)
return ret;
@@ -1199,8 +1200,8 @@ static int rk3399_dmc_probe(struct udevice *dev)
priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
debug("%s: pmugrf=%p\n", __func__, priv->pmugrf);
priv->info.base = CONFIG_SYS_SDRAM_BASE;
- priv->info.size = rockchip_sdram_size(
- (phys_addr_t)&priv->pmugrf->os_reg2);
+ priv->info.size =
+ rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg2);
#endif
return 0;
}
@@ -1218,7 +1219,6 @@ static struct ram_ops rk3399_dmc_ops = {
.get_info = rk3399_dmc_get_info,
};
-
static const struct udevice_id rk3399_dmc_ids[] = {
{ .compatible = "rockchip,rk3399-dmc" },
{ }
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 02/92] ram: rk3399: Add space between string with format specifier
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Add space between string with format specifier on missing
print and debug calls.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 541e4a4b1e..8191ab6176 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1180,7 +1180,7 @@ static int rk3399_dmc_init(struct udevice *dev)
}
ret = sdram_init(priv, params);
if (ret < 0) {
- printf("%s DRAM init failed%d\n", __func__, ret);
+ printf("%s DRAM init failed %d\n", __func__, ret);
return ret;
}
@@ -1198,7 +1198,7 @@ static int rk3399_dmc_probe(struct udevice *dev)
struct dram_info *priv = dev_get_priv(dev);
priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
- debug("%s: pmugrf=%p\n", __func__, priv->pmugrf);
+ debug("%s: pmugrf = %p\n", __func__, priv->pmugrf);
priv->info.base = CONFIG_SYS_SDRAM_BASE;
priv->info.size =
rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg2);
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 02/92] ram: rk3399: Add space between string with format specifier
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
Add space between string with format specifier on missing
print and debug calls.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 541e4a4b1e..8191ab6176 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1180,7 +1180,7 @@ static int rk3399_dmc_init(struct udevice *dev)
}
ret = sdram_init(priv, params);
if (ret < 0) {
- printf("%s DRAM init failed%d\n", __func__, ret);
+ printf("%s DRAM init failed %d\n", __func__, ret);
return ret;
}
@@ -1198,7 +1198,7 @@ static int rk3399_dmc_probe(struct udevice *dev)
struct dram_info *priv = dev_get_priv(dev);
priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
- debug("%s: pmugrf=%p\n", __func__, priv->pmugrf);
+ debug("%s: pmugrf = %p\n", __func__, priv->pmugrf);
priv->info.base = CONFIG_SYS_SDRAM_BASE;
priv->info.size =
rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg2);
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 03/92] ram: rk3399: Add proper spaces in data training
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Add proper spaces in the code of data training functions.
No functionality change.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 8191ab6176..b0850a88a0 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -620,8 +620,10 @@ static int data_training_ca(const struct chan_info *chan, u32 channel,
for (i = 0; i < rank; i++) {
select_per_cs_training_index(chan, i);
+
/* PI_100 PI_CALVL_EN:RW:8:2 */
clrsetbits_le32(&denali_pi[100], 0x3 << 8, 0x2 << 8);
+
/* PI_92 PI_CALVL_REQ:WR:16:1,PI_CALVL_CS:RW:24:2 */
clrsetbits_le32(&denali_pi[92],
(0x1 << 16) | (0x3 << 24),
@@ -651,9 +653,11 @@ static int data_training_ca(const struct chan_info *chan, u32 channel,
(obs_err == 1))
return -EIO;
}
+
/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
writel(0x00003f7c, (&denali_pi[175]));
}
+
clrbits_le32(&denali_pi[100], 0x3 << 8);
return 0;
@@ -670,8 +674,10 @@ static int data_training_wl(const struct chan_info *chan, u32 channel,
for (i = 0; i < rank; i++) {
select_per_cs_training_index(chan, i);
+
/* PI_60 PI_WRLVL_EN:RW:8:2 */
clrsetbits_le32(&denali_pi[60], 0x3 << 8, 0x2 << 8);
+
/* PI_59 PI_WRLVL_REQ:WR:8:1,PI_WRLVL_CS:RW:16:2 */
clrsetbits_le32(&denali_pi[59],
(0x1 << 8) | (0x3 << 16),
@@ -705,6 +711,7 @@ static int data_training_wl(const struct chan_info *chan, u32 channel,
(obs_err == 1))
return -EIO;
}
+
/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
writel(0x00003f7c, (&denali_pi[175]));
}
@@ -726,8 +733,10 @@ static int data_training_rg(const struct chan_info *chan, u32 channel,
for (i = 0; i < rank; i++) {
select_per_cs_training_index(chan, i);
+
/* PI_80 PI_RDLVL_GATE_EN:RW:24:2 */
clrsetbits_le32(&denali_pi[80], 0x3 << 24, 0x2 << 24);
+
/*
* PI_74 PI_RDLVL_GATE_REQ:WR:16:1
* PI_RDLVL_CS:RW:24:2
@@ -764,9 +773,11 @@ static int data_training_rg(const struct chan_info *chan, u32 channel,
(obs_err == 1))
return -EIO;
}
+
/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
writel(0x00003f7c, (&denali_pi[175]));
}
+
clrbits_le32(&denali_pi[80], 0x3 << 24);
return 0;
@@ -781,8 +792,10 @@ static int data_training_rl(const struct chan_info *chan, u32 channel,
for (i = 0; i < rank; i++) {
select_per_cs_training_index(chan, i);
+
/* PI_80 PI_RDLVL_EN:RW:16:2 */
clrsetbits_le32(&denali_pi[80], 0x3 << 16, 0x2 << 16);
+
/* PI_74 PI_RDLVL_REQ:WR:8:1,PI_RDLVL_CS:RW:24:2 */
clrsetbits_le32(&denali_pi[74],
(0x1 << 8) | (0x3 << 24),
@@ -805,9 +818,11 @@ static int data_training_rl(const struct chan_info *chan, u32 channel,
else if (((tmp >> 2) & 0x1) == 0x1)
return -EIO;
}
+
/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
writel(0x00003f7c, (&denali_pi[175]));
}
+
clrbits_le32(&denali_pi[80], 0x3 << 16);
return 0;
@@ -822,13 +837,16 @@ static int data_training_wdql(const struct chan_info *chan, u32 channel,
for (i = 0; i < rank; i++) {
select_per_cs_training_index(chan, i);
+
/*
* disable PI_WDQLVL_VREF_EN before wdq leveling?
* PI_181 PI_WDQLVL_VREF_EN:RW:8:1
*/
clrbits_le32(&denali_pi[181], 0x1 << 8);
+
/* PI_124 PI_WDQLVL_EN:RW:16:2 */
clrsetbits_le32(&denali_pi[124], 0x3 << 16, 0x2 << 16);
+
/* PI_121 PI_WDQLVL_REQ:WR:8:1,PI_WDQLVL_CS:RW:16:2 */
clrsetbits_le32(&denali_pi[121],
(0x1 << 8) | (0x3 << 16),
@@ -845,9 +863,11 @@ static int data_training_wdql(const struct chan_info *chan, u32 channel,
else if (((tmp >> 6) & 0x1) == 0x1)
return -EIO;
}
+
/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
writel(0x00003f7c, (&denali_pi[175]));
}
+
clrbits_le32(&denali_pi[124], 0x3 << 16);
return 0;
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 03/92] ram: rk3399: Add proper spaces in data training
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
Add proper spaces in the code of data training functions.
No functionality change.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 8191ab6176..b0850a88a0 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -620,8 +620,10 @@ static int data_training_ca(const struct chan_info *chan, u32 channel,
for (i = 0; i < rank; i++) {
select_per_cs_training_index(chan, i);
+
/* PI_100 PI_CALVL_EN:RW:8:2 */
clrsetbits_le32(&denali_pi[100], 0x3 << 8, 0x2 << 8);
+
/* PI_92 PI_CALVL_REQ:WR:16:1,PI_CALVL_CS:RW:24:2 */
clrsetbits_le32(&denali_pi[92],
(0x1 << 16) | (0x3 << 24),
@@ -651,9 +653,11 @@ static int data_training_ca(const struct chan_info *chan, u32 channel,
(obs_err == 1))
return -EIO;
}
+
/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
writel(0x00003f7c, (&denali_pi[175]));
}
+
clrbits_le32(&denali_pi[100], 0x3 << 8);
return 0;
@@ -670,8 +674,10 @@ static int data_training_wl(const struct chan_info *chan, u32 channel,
for (i = 0; i < rank; i++) {
select_per_cs_training_index(chan, i);
+
/* PI_60 PI_WRLVL_EN:RW:8:2 */
clrsetbits_le32(&denali_pi[60], 0x3 << 8, 0x2 << 8);
+
/* PI_59 PI_WRLVL_REQ:WR:8:1,PI_WRLVL_CS:RW:16:2 */
clrsetbits_le32(&denali_pi[59],
(0x1 << 8) | (0x3 << 16),
@@ -705,6 +711,7 @@ static int data_training_wl(const struct chan_info *chan, u32 channel,
(obs_err == 1))
return -EIO;
}
+
/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
writel(0x00003f7c, (&denali_pi[175]));
}
@@ -726,8 +733,10 @@ static int data_training_rg(const struct chan_info *chan, u32 channel,
for (i = 0; i < rank; i++) {
select_per_cs_training_index(chan, i);
+
/* PI_80 PI_RDLVL_GATE_EN:RW:24:2 */
clrsetbits_le32(&denali_pi[80], 0x3 << 24, 0x2 << 24);
+
/*
* PI_74 PI_RDLVL_GATE_REQ:WR:16:1
* PI_RDLVL_CS:RW:24:2
@@ -764,9 +773,11 @@ static int data_training_rg(const struct chan_info *chan, u32 channel,
(obs_err == 1))
return -EIO;
}
+
/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
writel(0x00003f7c, (&denali_pi[175]));
}
+
clrbits_le32(&denali_pi[80], 0x3 << 24);
return 0;
@@ -781,8 +792,10 @@ static int data_training_rl(const struct chan_info *chan, u32 channel,
for (i = 0; i < rank; i++) {
select_per_cs_training_index(chan, i);
+
/* PI_80 PI_RDLVL_EN:RW:16:2 */
clrsetbits_le32(&denali_pi[80], 0x3 << 16, 0x2 << 16);
+
/* PI_74 PI_RDLVL_REQ:WR:8:1,PI_RDLVL_CS:RW:24:2 */
clrsetbits_le32(&denali_pi[74],
(0x1 << 8) | (0x3 << 24),
@@ -805,9 +818,11 @@ static int data_training_rl(const struct chan_info *chan, u32 channel,
else if (((tmp >> 2) & 0x1) == 0x1)
return -EIO;
}
+
/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
writel(0x00003f7c, (&denali_pi[175]));
}
+
clrbits_le32(&denali_pi[80], 0x3 << 16);
return 0;
@@ -822,13 +837,16 @@ static int data_training_wdql(const struct chan_info *chan, u32 channel,
for (i = 0; i < rank; i++) {
select_per_cs_training_index(chan, i);
+
/*
* disable PI_WDQLVL_VREF_EN before wdq leveling?
* PI_181 PI_WDQLVL_VREF_EN:RW:8:1
*/
clrbits_le32(&denali_pi[181], 0x1 << 8);
+
/* PI_124 PI_WDQLVL_EN:RW:16:2 */
clrsetbits_le32(&denali_pi[124], 0x3 << 16, 0x2 << 16);
+
/* PI_121 PI_WDQLVL_REQ:WR:8:1,PI_WDQLVL_CS:RW:16:2 */
clrsetbits_le32(&denali_pi[121],
(0x1 << 8) | (0x3 << 16),
@@ -845,9 +863,11 @@ static int data_training_wdql(const struct chan_info *chan, u32 channel,
else if (((tmp >> 6) & 0x1) == 0x1)
return -EIO;
}
+
/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
writel(0x00003f7c, (&denali_pi[175]));
}
+
clrbits_le32(&denali_pi[124], 0x3 << 16);
return 0;
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 04/92] ram: rk3399: Handle data training return types
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
data trainings calls like ca, wl, rg, rl, wdql have proper
return types with -EIO and the return type missed to handle
in data_training function.
This patch, add proper return type checks along with useful
debug statement on each data training calls.
Incidentally this would help to prevent the sdram initialization
hang for single channel dram and when the code is trying to
initialize second channel with proper return type of relevant
data training call might failed.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 50 ++++++++++++++++++++++-------
1 file changed, 38 insertions(+), 12 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index b0850a88a0..73732e0767 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -878,6 +878,7 @@ static int data_training(const struct chan_info *chan, u32 channel,
u32 training_flag)
{
u32 *denali_phy = chan->publ->denali_phy;
+ int ret;
/* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */
setbits_le32(&denali_phy[927], (1 << 22));
@@ -898,24 +899,49 @@ static int data_training(const struct chan_info *chan, u32 channel,
}
/* ca training(LPDDR4,LPDDR3 support) */
- if ((training_flag & PI_CA_TRAINING) == PI_CA_TRAINING)
- data_training_ca(chan, channel, sdram_params);
+ if ((training_flag & PI_CA_TRAINING) == PI_CA_TRAINING) {
+ ret = data_training_ca(chan, channel, sdram_params);
+ if (ret < 0) {
+ debug("%s: data training ca failed\n", __func__);
+ return ret;
+ }
+ }
/* write leveling(LPDDR4,LPDDR3,DDR3 support) */
- if ((training_flag & PI_WRITE_LEVELING) == PI_WRITE_LEVELING)
- data_training_wl(chan, channel, sdram_params);
+ if ((training_flag & PI_WRITE_LEVELING) == PI_WRITE_LEVELING) {
+ ret = data_training_wl(chan, channel, sdram_params);
+ if (ret < 0) {
+ debug("%s: data training wl failed\n", __func__);
+ return ret;
+ }
+ }
/* read gate training(LPDDR4,LPDDR3,DDR3 support) */
- if ((training_flag & PI_READ_GATE_TRAINING) == PI_READ_GATE_TRAINING)
- data_training_rg(chan, channel, sdram_params);
+ if ((training_flag & PI_READ_GATE_TRAINING) == PI_READ_GATE_TRAINING) {
+ ret = data_training_rg(chan, channel, sdram_params);
+ if (ret < 0) {
+ debug("%s: data training rg failed\n", __func__);
+ return ret;
+ }
+ }
/* read leveling(LPDDR4,LPDDR3,DDR3 support) */
- if ((training_flag & PI_READ_LEVELING) == PI_READ_LEVELING)
- data_training_rl(chan, channel, sdram_params);
+ if ((training_flag & PI_READ_LEVELING) == PI_READ_LEVELING) {
+ ret = data_training_rl(chan, channel, sdram_params);
+ if (ret < 0) {
+ debug("%s: data training rl failed\n", __func__);
+ return ret;
+ }
+ }
/* wdq leveling(LPDDR4 support) */
- if ((training_flag & PI_WDQ_LEVELING) == PI_WDQ_LEVELING)
- data_training_wdql(chan, channel, sdram_params);
+ if ((training_flag & PI_WDQ_LEVELING) == PI_WDQ_LEVELING) {
+ ret = data_training_wdql(chan, channel, sdram_params);
+ if (ret < 0) {
+ debug("%s: data training wdql failed\n", __func__);
+ return ret;
+ }
+ }
/* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */
clrbits_le32(&denali_phy[927], (1 << 22));
@@ -1048,7 +1074,7 @@ static int switch_to_phy_index1(struct dram_info *dram,
clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8);
ret = data_training(&dram->chan[channel], channel,
sdram_params, PI_FULL_TRAINING);
- if (ret) {
+ if (ret < 0) {
debug("index1 training failed\n");
return ret;
}
@@ -1093,7 +1119,7 @@ static int sdram_init(struct dram_info *dram,
if (data_training(chan, channel,
sdram_params, PI_FULL_TRAINING)) {
- printf("SDRAM initialization failed, reset\n");
+ printf("%s: data training failed\n", __func__);
return -EIO;
}
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 04/92] ram: rk3399: Handle data training return types
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
data trainings calls like ca, wl, rg, rl, wdql have proper
return types with -EIO and the return type missed to handle
in data_training function.
This patch, add proper return type checks along with useful
debug statement on each data training calls.
Incidentally this would help to prevent the sdram initialization
hang for single channel dram and when the code is trying to
initialize second channel with proper return type of relevant
data training call might failed.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 50 ++++++++++++++++++++++-------
1 file changed, 38 insertions(+), 12 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index b0850a88a0..73732e0767 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -878,6 +878,7 @@ static int data_training(const struct chan_info *chan, u32 channel,
u32 training_flag)
{
u32 *denali_phy = chan->publ->denali_phy;
+ int ret;
/* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */
setbits_le32(&denali_phy[927], (1 << 22));
@@ -898,24 +899,49 @@ static int data_training(const struct chan_info *chan, u32 channel,
}
/* ca training(LPDDR4,LPDDR3 support) */
- if ((training_flag & PI_CA_TRAINING) == PI_CA_TRAINING)
- data_training_ca(chan, channel, sdram_params);
+ if ((training_flag & PI_CA_TRAINING) == PI_CA_TRAINING) {
+ ret = data_training_ca(chan, channel, sdram_params);
+ if (ret < 0) {
+ debug("%s: data training ca failed\n", __func__);
+ return ret;
+ }
+ }
/* write leveling(LPDDR4,LPDDR3,DDR3 support) */
- if ((training_flag & PI_WRITE_LEVELING) == PI_WRITE_LEVELING)
- data_training_wl(chan, channel, sdram_params);
+ if ((training_flag & PI_WRITE_LEVELING) == PI_WRITE_LEVELING) {
+ ret = data_training_wl(chan, channel, sdram_params);
+ if (ret < 0) {
+ debug("%s: data training wl failed\n", __func__);
+ return ret;
+ }
+ }
/* read gate training(LPDDR4,LPDDR3,DDR3 support) */
- if ((training_flag & PI_READ_GATE_TRAINING) == PI_READ_GATE_TRAINING)
- data_training_rg(chan, channel, sdram_params);
+ if ((training_flag & PI_READ_GATE_TRAINING) == PI_READ_GATE_TRAINING) {
+ ret = data_training_rg(chan, channel, sdram_params);
+ if (ret < 0) {
+ debug("%s: data training rg failed\n", __func__);
+ return ret;
+ }
+ }
/* read leveling(LPDDR4,LPDDR3,DDR3 support) */
- if ((training_flag & PI_READ_LEVELING) == PI_READ_LEVELING)
- data_training_rl(chan, channel, sdram_params);
+ if ((training_flag & PI_READ_LEVELING) == PI_READ_LEVELING) {
+ ret = data_training_rl(chan, channel, sdram_params);
+ if (ret < 0) {
+ debug("%s: data training rl failed\n", __func__);
+ return ret;
+ }
+ }
/* wdq leveling(LPDDR4 support) */
- if ((training_flag & PI_WDQ_LEVELING) == PI_WDQ_LEVELING)
- data_training_wdql(chan, channel, sdram_params);
+ if ((training_flag & PI_WDQ_LEVELING) == PI_WDQ_LEVELING) {
+ ret = data_training_wdql(chan, channel, sdram_params);
+ if (ret < 0) {
+ debug("%s: data training wdql failed\n", __func__);
+ return ret;
+ }
+ }
/* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */
clrbits_le32(&denali_phy[927], (1 << 22));
@@ -1048,7 +1074,7 @@ static int switch_to_phy_index1(struct dram_info *dram,
clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8);
ret = data_training(&dram->chan[channel], channel,
sdram_params, PI_FULL_TRAINING);
- if (ret) {
+ if (ret < 0) {
debug("index1 training failed\n");
return ret;
}
@@ -1093,7 +1119,7 @@ static int sdram_init(struct dram_info *dram,
if (data_training(chan, channel,
sdram_params, PI_FULL_TRAINING)) {
- printf("SDRAM initialization failed, reset\n");
+ printf("%s: data training failed\n", __func__);
return -EIO;
}
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 05/92] ram: rk3399: Order include files
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Order include files in ascending order, which would
avoid conflicting function definitions/prototypes if
any and also for better code readability.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 73732e0767..da04b11922 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -14,11 +14,11 @@
#include <syscon.h>
#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/sdram_common.h>
-#include <asm/arch-rockchip/sdram_rk3399.h>
#include <asm/arch-rockchip/cru_rk3399.h>
#include <asm/arch-rockchip/grf_rk3399.h>
#include <asm/arch-rockchip/hardware.h>
+#include <asm/arch-rockchip/sdram_common.h>
+#include <asm/arch-rockchip/sdram_rk3399.h>
#include <linux/err.h>
#include <time.h>
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 05/92] ram: rk3399: Order include files
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
Order include files in ascending order, which would
avoid conflicting function definitions/prototypes if
any and also for better code readability.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 73732e0767..da04b11922 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -14,11 +14,11 @@
#include <syscon.h>
#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/sdram_common.h>
-#include <asm/arch-rockchip/sdram_rk3399.h>
#include <asm/arch-rockchip/cru_rk3399.h>
#include <asm/arch-rockchip/grf_rk3399.h>
#include <asm/arch-rockchip/hardware.h>
+#include <asm/arch-rockchip/sdram_common.h>
+#include <asm/arch-rockchip/sdram_rk3399.h>
#include <linux/err.h>
#include <time.h>
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 06/92] ram: rk3399: Move macro after include files
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Move the macro definitions after include files for better
code readability and to satisfy coding style.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 26 +++++++++++++-------------
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index da04b11922..52633166c1 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -22,6 +22,19 @@
#include <linux/err.h>
#include <time.h>
+#define PRESET_SGRF_HOLD(n) ((0x1 << (6 + 16)) | ((n) << 6))
+#define PRESET_GPIO0_HOLD(n) ((0x1 << (7 + 16)) | ((n) << 7))
+#define PRESET_GPIO1_HOLD(n) ((0x1 << (8 + 16)) | ((n) << 8))
+
+#define PHY_DRV_ODT_HI_Z 0x0
+#define PHY_DRV_ODT_240 0x1
+#define PHY_DRV_ODT_120 0x8
+#define PHY_DRV_ODT_80 0x9
+#define PHY_DRV_ODT_60 0xc
+#define PHY_DRV_ODT_48 0xd
+#define PHY_DRV_ODT_40 0xe
+#define PHY_DRV_ODT_34_3 0xf
+
struct chan_info {
struct rk3399_ddr_pctl_regs *pctl;
struct rk3399_ddr_pi_regs *pi;
@@ -43,19 +56,6 @@ struct dram_info {
struct rk3399_pmugrf_regs *pmugrf;
};
-#define PRESET_SGRF_HOLD(n) ((0x1 << (6 + 16)) | ((n) << 6))
-#define PRESET_GPIO0_HOLD(n) ((0x1 << (7 + 16)) | ((n) << 7))
-#define PRESET_GPIO1_HOLD(n) ((0x1 << (8 + 16)) | ((n) << 8))
-
-#define PHY_DRV_ODT_HI_Z 0x0
-#define PHY_DRV_ODT_240 0x1
-#define PHY_DRV_ODT_120 0x8
-#define PHY_DRV_ODT_80 0x9
-#define PHY_DRV_ODT_60 0xc
-#define PHY_DRV_ODT_48 0xd
-#define PHY_DRV_ODT_40 0xe
-#define PHY_DRV_ODT_34_3 0xf
-
#if defined(CONFIG_TPL_BUILD) || \
(!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 06/92] ram: rk3399: Move macro after include files
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
Move the macro definitions after include files for better
code readability and to satisfy coding style.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 26 +++++++++++++-------------
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index da04b11922..52633166c1 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -22,6 +22,19 @@
#include <linux/err.h>
#include <time.h>
+#define PRESET_SGRF_HOLD(n) ((0x1 << (6 + 16)) | ((n) << 6))
+#define PRESET_GPIO0_HOLD(n) ((0x1 << (7 + 16)) | ((n) << 7))
+#define PRESET_GPIO1_HOLD(n) ((0x1 << (8 + 16)) | ((n) << 8))
+
+#define PHY_DRV_ODT_HI_Z 0x0
+#define PHY_DRV_ODT_240 0x1
+#define PHY_DRV_ODT_120 0x8
+#define PHY_DRV_ODT_80 0x9
+#define PHY_DRV_ODT_60 0xc
+#define PHY_DRV_ODT_48 0xd
+#define PHY_DRV_ODT_40 0xe
+#define PHY_DRV_ODT_34_3 0xf
+
struct chan_info {
struct rk3399_ddr_pctl_regs *pctl;
struct rk3399_ddr_pi_regs *pi;
@@ -43,19 +56,6 @@ struct dram_info {
struct rk3399_pmugrf_regs *pmugrf;
};
-#define PRESET_SGRF_HOLD(n) ((0x1 << (6 + 16)) | ((n) << 6))
-#define PRESET_GPIO0_HOLD(n) ((0x1 << (7 + 16)) | ((n) << 7))
-#define PRESET_GPIO1_HOLD(n) ((0x1 << (8 + 16)) | ((n) << 8))
-
-#define PHY_DRV_ODT_HI_Z 0x0
-#define PHY_DRV_ODT_240 0x1
-#define PHY_DRV_ODT_120 0x8
-#define PHY_DRV_ODT_80 0x9
-#define PHY_DRV_ODT_60 0xc
-#define PHY_DRV_ODT_48 0xd
-#define PHY_DRV_ODT_40 0xe
-#define PHY_DRV_ODT_34_3 0xf
-
#if defined(CONFIG_TPL_BUILD) || \
(!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 07/92] ram: rk3399: Clear PI_175 interrupts in data training
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Clear the PI_175 interrupts before processing actual
data training in all relevant calls.
This would help to clear interrupt from previous training.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 52633166c1..74392076f0 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -618,6 +618,9 @@ static int data_training_ca(const struct chan_info *chan, u32 channel,
u32 obs_0, obs_1, obs_2, obs_err = 0;
u32 rank = sdram_params->ch[channel].rank;
+ /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
+ writel(0x00003f7c, (&denali_pi[175]));
+
for (i = 0; i < rank; i++) {
select_per_cs_training_index(chan, i);
@@ -672,6 +675,9 @@ static int data_training_wl(const struct chan_info *chan, u32 channel,
u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
u32 rank = sdram_params->ch[channel].rank;
+ /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
+ writel(0x00003f7c, (&denali_pi[175]));
+
for (i = 0; i < rank; i++) {
select_per_cs_training_index(chan, i);
@@ -731,6 +737,9 @@ static int data_training_rg(const struct chan_info *chan, u32 channel,
u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
u32 rank = sdram_params->ch[channel].rank;
+ /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
+ writel(0x00003f7c, (&denali_pi[175]));
+
for (i = 0; i < rank; i++) {
select_per_cs_training_index(chan, i);
@@ -790,6 +799,9 @@ static int data_training_rl(const struct chan_info *chan, u32 channel,
u32 i, tmp;
u32 rank = sdram_params->ch[channel].rank;
+ /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
+ writel(0x00003f7c, (&denali_pi[175]));
+
for (i = 0; i < rank; i++) {
select_per_cs_training_index(chan, i);
@@ -835,6 +847,9 @@ static int data_training_wdql(const struct chan_info *chan, u32 channel,
u32 i, tmp;
u32 rank = sdram_params->ch[channel].rank;
+ /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
+ writel(0x00003f7c, (&denali_pi[175]));
+
for (i = 0; i < rank; i++) {
select_per_cs_training_index(chan, i);
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 07/92] ram: rk3399: Clear PI_175 interrupts in data training
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
Clear the PI_175 interrupts before processing actual
data training in all relevant calls.
This would help to clear interrupt from previous training.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 52633166c1..74392076f0 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -618,6 +618,9 @@ static int data_training_ca(const struct chan_info *chan, u32 channel,
u32 obs_0, obs_1, obs_2, obs_err = 0;
u32 rank = sdram_params->ch[channel].rank;
+ /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
+ writel(0x00003f7c, (&denali_pi[175]));
+
for (i = 0; i < rank; i++) {
select_per_cs_training_index(chan, i);
@@ -672,6 +675,9 @@ static int data_training_wl(const struct chan_info *chan, u32 channel,
u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
u32 rank = sdram_params->ch[channel].rank;
+ /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
+ writel(0x00003f7c, (&denali_pi[175]));
+
for (i = 0; i < rank; i++) {
select_per_cs_training_index(chan, i);
@@ -731,6 +737,9 @@ static int data_training_rg(const struct chan_info *chan, u32 channel,
u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
u32 rank = sdram_params->ch[channel].rank;
+ /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
+ writel(0x00003f7c, (&denali_pi[175]));
+
for (i = 0; i < rank; i++) {
select_per_cs_training_index(chan, i);
@@ -790,6 +799,9 @@ static int data_training_rl(const struct chan_info *chan, u32 channel,
u32 i, tmp;
u32 rank = sdram_params->ch[channel].rank;
+ /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
+ writel(0x00003f7c, (&denali_pi[175]));
+
for (i = 0; i < rank; i++) {
select_per_cs_training_index(chan, i);
@@ -835,6 +847,9 @@ static int data_training_wdql(const struct chan_info *chan, u32 channel,
u32 i, tmp;
u32 rank = sdram_params->ch[channel].rank;
+ /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
+ writel(0x00003f7c, (&denali_pi[175]));
+
for (i = 0; i < rank; i++) {
select_per_cs_training_index(chan, i);
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 08/92] ram: rk3399: Use rank mask in ca data training
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Add rank_mask based on the rank number, this would keep
the ca data training loop based on the desired rank mask
value instead of looping for all values.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 74392076f0..312d19f95f 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -617,11 +617,17 @@ static int data_training_ca(const struct chan_info *chan, u32 channel,
u32 i, tmp;
u32 obs_0, obs_1, obs_2, obs_err = 0;
u32 rank = sdram_params->ch[channel].rank;
+ u32 rank_mask;
/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
writel(0x00003f7c, (&denali_pi[175]));
- for (i = 0; i < rank; i++) {
+ rank_mask = (rank == 1) ? 0x1 : 0x3;
+
+ for (i = 0; i < 4; i++) {
+ if (!(rank_mask & (1 << i)))
+ continue;
+
select_per_cs_training_index(chan, i);
/* PI_100 PI_CALVL_EN:RW:8:2 */
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 08/92] ram: rk3399: Use rank mask in ca data training
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
Add rank_mask based on the rank number, this would keep
the ca data training loop based on the desired rank mask
value instead of looping for all values.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 74392076f0..312d19f95f 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -617,11 +617,17 @@ static int data_training_ca(const struct chan_info *chan, u32 channel,
u32 i, tmp;
u32 obs_0, obs_1, obs_2, obs_err = 0;
u32 rank = sdram_params->ch[channel].rank;
+ u32 rank_mask;
/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
writel(0x00003f7c, (&denali_pi[175]));
- for (i = 0; i < rank; i++) {
+ rank_mask = (rank == 1) ? 0x1 : 0x3;
+
+ for (i = 0; i < 4; i++) {
+ if (!(rank_mask & (1 << i)))
+ continue;
+
select_per_cs_training_index(chan, i);
/* PI_100 PI_CALVL_EN:RW:8:2 */
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 09/92] ram: rk3399: Use rank mask in wdql data training
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Add rank_mask based on the rank number, this would keep
the wdql data training loop based on the desired rank mask
value instead of looping for all values.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 312d19f95f..1541b34a7d 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -852,11 +852,17 @@ static int data_training_wdql(const struct chan_info *chan, u32 channel,
u32 *denali_pi = chan->pi->denali_pi;
u32 i, tmp;
u32 rank = sdram_params->ch[channel].rank;
+ u32 rank_mask;
/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
writel(0x00003f7c, (&denali_pi[175]));
- for (i = 0; i < rank; i++) {
+ rank_mask = (rank == 1) ? 0x1 : 0x3;
+
+ for (i = 0; i < 4; i++) {
+ if (!(rank_mask & (1 << i)))
+ continue;
+
select_per_cs_training_index(chan, i);
/*
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 09/92] ram: rk3399: Use rank mask in wdql data training
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
Add rank_mask based on the rank number, this would keep
the wdql data training loop based on the desired rank mask
value instead of looping for all values.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 312d19f95f..1541b34a7d 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -852,11 +852,17 @@ static int data_training_wdql(const struct chan_info *chan, u32 channel,
u32 *denali_pi = chan->pi->denali_pi;
u32 i, tmp;
u32 rank = sdram_params->ch[channel].rank;
+ u32 rank_mask;
/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
writel(0x00003f7c, (&denali_pi[175]));
- for (i = 0; i < rank; i++) {
+ rank_mask = (rank == 1) ? 0x1 : 0x3;
+
+ for (i = 0; i < 4; i++) {
+ if (!(rank_mask & (1 << i)))
+ continue;
+
select_per_cs_training_index(chan, i);
/*
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 10/92] ram: rk3399: Add ddrtype enc macro
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Add simplified and meaningful macro for ddrtype macro.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
arch/arm/include/asm/arch-rockchip/sdram_common.h | 1 +
drivers/ram/rockchip/sdram_rk3399.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index 671c318d50..83936d3679 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -34,6 +34,7 @@
#define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch))
#define SYS_REG_ROW_3_4_MASK 1
#define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch))
+#define SYS_REG_ENC_DDRTYPE(n) ((n) << 13)
#define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16)
#define SYS_REG_RANK_MASK 1
#define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 1541b34a7d..69c8d53314 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1008,7 +1008,7 @@ static void dram_all_config(struct dram_info *dram,
u32 sys_reg = 0;
unsigned int channel, idx;
- sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT;
+ sys_reg |= SYS_REG_ENC_DDRTYPE(sdram_params->base.dramtype);
sys_reg |= (sdram_params->base.num_channels - 1)
<< SYS_REG_NUM_CH_SHIFT;
for (channel = 0, idx = 0;
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 10/92] ram: rk3399: Add ddrtype enc macro
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
Add simplified and meaningful macro for ddrtype macro.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
arch/arm/include/asm/arch-rockchip/sdram_common.h | 1 +
drivers/ram/rockchip/sdram_rk3399.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index 671c318d50..83936d3679 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -34,6 +34,7 @@
#define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch))
#define SYS_REG_ROW_3_4_MASK 1
#define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch))
+#define SYS_REG_ENC_DDRTYPE(n) ((n) << 13)
#define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16)
#define SYS_REG_RANK_MASK 1
#define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 1541b34a7d..69c8d53314 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1008,7 +1008,7 @@ static void dram_all_config(struct dram_info *dram,
u32 sys_reg = 0;
unsigned int channel, idx;
- sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT;
+ sys_reg |= SYS_REG_ENC_DDRTYPE(sdram_params->base.dramtype);
sys_reg |= (sdram_params->base.num_channels - 1)
<< SYS_REG_NUM_CH_SHIFT;
for (channel = 0, idx = 0;
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 11/92] ram: rk3399: Add channel number encoder macro
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Add simplified and meaningful macro for channel number.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
arch/arm/include/asm/arch-rockchip/sdram_common.h | 1 +
drivers/ram/rockchip/sdram_rk3399.c | 3 +--
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index 83936d3679..38a8bb8642 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -35,6 +35,7 @@
#define SYS_REG_ROW_3_4_MASK 1
#define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch))
#define SYS_REG_ENC_DDRTYPE(n) ((n) << 13)
+#define SYS_REG_ENC_NUM_CH(n) (((n) - 1) << 12)
#define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16)
#define SYS_REG_RANK_MASK 1
#define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 69c8d53314..3d2447a24e 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1009,8 +1009,7 @@ static void dram_all_config(struct dram_info *dram,
unsigned int channel, idx;
sys_reg |= SYS_REG_ENC_DDRTYPE(sdram_params->base.dramtype);
- sys_reg |= (sdram_params->base.num_channels - 1)
- << SYS_REG_NUM_CH_SHIFT;
+ sys_reg |= SYS_REG_ENC_NUM_CH(sdram_params->base.num_channels);
for (channel = 0, idx = 0;
(idx < sdram_params->base.num_channels) && (channel < 2);
channel++) {
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 11/92] ram: rk3399: Add channel number encoder macro
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
Add simplified and meaningful macro for channel number.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
arch/arm/include/asm/arch-rockchip/sdram_common.h | 1 +
drivers/ram/rockchip/sdram_rk3399.c | 3 +--
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index 83936d3679..38a8bb8642 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -35,6 +35,7 @@
#define SYS_REG_ROW_3_4_MASK 1
#define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch))
#define SYS_REG_ENC_DDRTYPE(n) ((n) << 13)
+#define SYS_REG_ENC_NUM_CH(n) (((n) - 1) << 12)
#define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16)
#define SYS_REG_RANK_MASK 1
#define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 69c8d53314..3d2447a24e 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1009,8 +1009,7 @@ static void dram_all_config(struct dram_info *dram,
unsigned int channel, idx;
sys_reg |= SYS_REG_ENC_DDRTYPE(sdram_params->base.dramtype);
- sys_reg |= (sdram_params->base.num_channels - 1)
- << SYS_REG_NUM_CH_SHIFT;
+ sys_reg |= SYS_REG_ENC_NUM_CH(sdram_params->base.num_channels);
for (channel = 0, idx = 0;
(idx < sdram_params->base.num_channels) && (channel < 2);
channel++) {
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 12/92] ram: rk3399: Add row_3_4 enc macro
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Add simplified and meaningful macro for row_3_4.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
arch/arm/include/asm/arch-rockchip/sdram_common.h | 1 +
drivers/ram/rockchip/sdram_rk3399.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index 38a8bb8642..49a5d14821 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -33,6 +33,7 @@
#define SYS_REG_NUM_CH_MASK 1
#define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch))
#define SYS_REG_ROW_3_4_MASK 1
+#define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch)))
#define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch))
#define SYS_REG_ENC_DDRTYPE(n) ((n) << 13)
#define SYS_REG_ENC_NUM_CH(n) (((n) - 1) << 12)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 3d2447a24e..0a7137784e 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1021,7 +1021,7 @@ static void dram_all_config(struct dram_info *dram,
if (sdram_params->ch[channel].col == 0)
continue;
idx++;
- sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(channel);
+ sys_reg |= SYS_REG_ENC_ROW_3_4(info->row_3_4, channel);
sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(channel);
sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(channel);
sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(channel);
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 12/92] ram: rk3399: Add row_3_4 enc macro
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
Add simplified and meaningful macro for row_3_4.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
arch/arm/include/asm/arch-rockchip/sdram_common.h | 1 +
drivers/ram/rockchip/sdram_rk3399.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index 38a8bb8642..49a5d14821 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -33,6 +33,7 @@
#define SYS_REG_NUM_CH_MASK 1
#define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch))
#define SYS_REG_ROW_3_4_MASK 1
+#define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch)))
#define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch))
#define SYS_REG_ENC_DDRTYPE(n) ((n) << 13)
#define SYS_REG_ENC_NUM_CH(n) (((n) - 1) << 12)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 3d2447a24e..0a7137784e 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1021,7 +1021,7 @@ static void dram_all_config(struct dram_info *dram,
if (sdram_params->ch[channel].col == 0)
continue;
idx++;
- sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(channel);
+ sys_reg |= SYS_REG_ENC_ROW_3_4(info->row_3_4, channel);
sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(channel);
sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(channel);
sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(channel);
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 13/92] ram: rk3399: Add chipinfo macro
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Add simplified and meaningful macro for chip info.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
arch/arm/include/asm/arch-rockchip/sdram_common.h | 1 +
drivers/ram/rockchip/sdram_rk3399.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index 49a5d14821..68ae8e8371 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -35,6 +35,7 @@
#define SYS_REG_ROW_3_4_MASK 1
#define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch)))
#define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch))
+#define SYS_REG_ENC_CHINFO(ch) (1 << SYS_REG_CHINFO_SHIFT(ch))
#define SYS_REG_ENC_DDRTYPE(n) ((n) << 13)
#define SYS_REG_ENC_NUM_CH(n) (((n) - 1) << 12)
#define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 0a7137784e..0feb5d1e10 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1022,7 +1022,7 @@ static void dram_all_config(struct dram_info *dram,
continue;
idx++;
sys_reg |= SYS_REG_ENC_ROW_3_4(info->row_3_4, channel);
- sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(channel);
+ sys_reg |= SYS_REG_ENC_CHINFO(channel);
sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(channel);
sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(channel);
sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(channel);
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 13/92] ram: rk3399: Add chipinfo macro
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
Add simplified and meaningful macro for chip info.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
arch/arm/include/asm/arch-rockchip/sdram_common.h | 1 +
drivers/ram/rockchip/sdram_rk3399.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index 49a5d14821..68ae8e8371 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -35,6 +35,7 @@
#define SYS_REG_ROW_3_4_MASK 1
#define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch)))
#define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch))
+#define SYS_REG_ENC_CHINFO(ch) (1 << SYS_REG_CHINFO_SHIFT(ch))
#define SYS_REG_ENC_DDRTYPE(n) ((n) << 13)
#define SYS_REG_ENC_NUM_CH(n) (((n) - 1) << 12)
#define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 0a7137784e..0feb5d1e10 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1022,7 +1022,7 @@ static void dram_all_config(struct dram_info *dram,
continue;
idx++;
sys_reg |= SYS_REG_ENC_ROW_3_4(info->row_3_4, channel);
- sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(channel);
+ sys_reg |= SYS_REG_ENC_CHINFO(channel);
sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(channel);
sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(channel);
sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(channel);
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 14/92] ram: rk3399: Add rank enc macro
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Add simplified and meaningful macro for rank.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
arch/arm/include/asm/arch-rockchip/sdram_common.h | 2 ++
drivers/ram/rockchip/sdram_rk3399.c | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index 68ae8e8371..2dfbc75bb7 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -40,6 +40,8 @@
#define SYS_REG_ENC_NUM_CH(n) (((n) - 1) << 12)
#define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16)
#define SYS_REG_RANK_MASK 1
+#define SYS_REG_ENC_RANK(n, ch) (((n) - SYS_REG_RANK_MASK) << \
+ SYS_REG_RANK_SHIFT(ch))
#define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16)
#define SYS_REG_COL_MASK 3
#define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 0feb5d1e10..d801ee691c 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1023,7 +1023,7 @@ static void dram_all_config(struct dram_info *dram,
idx++;
sys_reg |= SYS_REG_ENC_ROW_3_4(info->row_3_4, channel);
sys_reg |= SYS_REG_ENC_CHINFO(channel);
- sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(channel);
+ sys_reg |= SYS_REG_ENC_RANK(info->rank, channel);
sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(channel);
sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(channel);
sys_reg |= (info->cs0_row - 13) <<
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 14/92] ram: rk3399: Add rank enc macro
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
Add simplified and meaningful macro for rank.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
arch/arm/include/asm/arch-rockchip/sdram_common.h | 2 ++
drivers/ram/rockchip/sdram_rk3399.c | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index 68ae8e8371..2dfbc75bb7 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -40,6 +40,8 @@
#define SYS_REG_ENC_NUM_CH(n) (((n) - 1) << 12)
#define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16)
#define SYS_REG_RANK_MASK 1
+#define SYS_REG_ENC_RANK(n, ch) (((n) - SYS_REG_RANK_MASK) << \
+ SYS_REG_RANK_SHIFT(ch))
#define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16)
#define SYS_REG_COL_MASK 3
#define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 0feb5d1e10..d801ee691c 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1023,7 +1023,7 @@ static void dram_all_config(struct dram_info *dram,
idx++;
sys_reg |= SYS_REG_ENC_ROW_3_4(info->row_3_4, channel);
sys_reg |= SYS_REG_ENC_CHINFO(channel);
- sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(channel);
+ sys_reg |= SYS_REG_ENC_RANK(info->rank, channel);
sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(channel);
sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(channel);
sys_reg |= (info->cs0_row - 13) <<
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 15/92] ram: rk3399: Add column enc macro
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Add simplified and meaningful macro for column.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
arch/arm/include/asm/arch-rockchip/sdram_common.h | 1 +
drivers/ram/rockchip/sdram_rk3399.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index 2dfbc75bb7..8e809e8dd6 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -44,6 +44,7 @@
SYS_REG_RANK_SHIFT(ch))
#define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16)
#define SYS_REG_COL_MASK 3
+#define SYS_REG_ENC_COL(n, ch) (((n) - 9) << SYS_REG_COL_SHIFT(ch))
#define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16)
#define SYS_REG_BK_MASK 1
#define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index d801ee691c..ad6c74374a 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1024,7 +1024,7 @@ static void dram_all_config(struct dram_info *dram,
sys_reg |= SYS_REG_ENC_ROW_3_4(info->row_3_4, channel);
sys_reg |= SYS_REG_ENC_CHINFO(channel);
sys_reg |= SYS_REG_ENC_RANK(info->rank, channel);
- sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(channel);
+ sys_reg |= SYS_REG_ENC_COL(info->col, channel);
sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(channel);
sys_reg |= (info->cs0_row - 13) <<
SYS_REG_CS0_ROW_SHIFT(channel);
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 15/92] ram: rk3399: Add column enc macro
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
Add simplified and meaningful macro for column.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
arch/arm/include/asm/arch-rockchip/sdram_common.h | 1 +
drivers/ram/rockchip/sdram_rk3399.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index 2dfbc75bb7..8e809e8dd6 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -44,6 +44,7 @@
SYS_REG_RANK_SHIFT(ch))
#define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16)
#define SYS_REG_COL_MASK 3
+#define SYS_REG_ENC_COL(n, ch) (((n) - 9) << SYS_REG_COL_SHIFT(ch))
#define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16)
#define SYS_REG_BK_MASK 1
#define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index d801ee691c..ad6c74374a 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1024,7 +1024,7 @@ static void dram_all_config(struct dram_info *dram,
sys_reg |= SYS_REG_ENC_ROW_3_4(info->row_3_4, channel);
sys_reg |= SYS_REG_ENC_CHINFO(channel);
sys_reg |= SYS_REG_ENC_RANK(info->rank, channel);
- sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(channel);
+ sys_reg |= SYS_REG_ENC_COL(info->col, channel);
sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(channel);
sys_reg |= (info->cs0_row - 13) <<
SYS_REG_CS0_ROW_SHIFT(channel);
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 16/92] ram: rk3399: Add bk enc macro
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Add simplified and meaningful macro for bk.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
arch/arm/include/asm/arch-rockchip/sdram_common.h | 2 ++
drivers/ram/rockchip/sdram_rk3399.c | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index 8e809e8dd6..8a71e8ad87 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -47,6 +47,8 @@
#define SYS_REG_ENC_COL(n, ch) (((n) - 9) << SYS_REG_COL_SHIFT(ch))
#define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16)
#define SYS_REG_BK_MASK 1
+#define SYS_REG_ENC_BK(n, ch) (((n) == 3 ? 0 : 1) << \
+ SYS_REG_BK_SHIFT(ch))
#define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16)
#define SYS_REG_CS0_ROW_MASK 3
#define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index ad6c74374a..2614fef407 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1025,7 +1025,7 @@ static void dram_all_config(struct dram_info *dram,
sys_reg |= SYS_REG_ENC_CHINFO(channel);
sys_reg |= SYS_REG_ENC_RANK(info->rank, channel);
sys_reg |= SYS_REG_ENC_COL(info->col, channel);
- sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(channel);
+ sys_reg |= SYS_REG_ENC_BK(info->bk, channel);
sys_reg |= (info->cs0_row - 13) <<
SYS_REG_CS0_ROW_SHIFT(channel);
sys_reg |= (info->cs1_row - 13) <<
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 16/92] ram: rk3399: Add bk enc macro
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
Add simplified and meaningful macro for bk.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
arch/arm/include/asm/arch-rockchip/sdram_common.h | 2 ++
drivers/ram/rockchip/sdram_rk3399.c | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index 8e809e8dd6..8a71e8ad87 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -47,6 +47,8 @@
#define SYS_REG_ENC_COL(n, ch) (((n) - 9) << SYS_REG_COL_SHIFT(ch))
#define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16)
#define SYS_REG_BK_MASK 1
+#define SYS_REG_ENC_BK(n, ch) (((n) == 3 ? 0 : 1) << \
+ SYS_REG_BK_SHIFT(ch))
#define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16)
#define SYS_REG_CS0_ROW_MASK 3
#define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index ad6c74374a..2614fef407 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1025,7 +1025,7 @@ static void dram_all_config(struct dram_info *dram,
sys_reg |= SYS_REG_ENC_CHINFO(channel);
sys_reg |= SYS_REG_ENC_RANK(info->rank, channel);
sys_reg |= SYS_REG_ENC_COL(info->col, channel);
- sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(channel);
+ sys_reg |= SYS_REG_ENC_BK(info->bk, channel);
sys_reg |= (info->cs0_row - 13) <<
SYS_REG_CS0_ROW_SHIFT(channel);
sys_reg |= (info->cs1_row - 13) <<
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 17/92] ram: rk3399: Add dbw enc macro
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Add simplified and meaningful macro for dbw.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
arch/arm/include/asm/arch-rockchip/sdram_common.h | 1 +
drivers/ram/rockchip/sdram_rk3399.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index 8a71e8ad87..3b0557cb6d 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -57,6 +57,7 @@
#define SYS_REG_BW_MASK 3
#define SYS_REG_DBW_SHIFT(ch) ((ch) * 16)
#define SYS_REG_DBW_MASK 3
+#define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << SYS_REG_DBW_SHIFT(ch))
/* Get sdram size decode from reg */
size_t rockchip_sdram_size(phys_addr_t reg);
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 2614fef407..4047b4b7e3 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1031,7 +1031,7 @@ static void dram_all_config(struct dram_info *dram,
sys_reg |= (info->cs1_row - 13) <<
SYS_REG_CS1_ROW_SHIFT(channel);
sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(channel);
- sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(channel);
+ sys_reg |= SYS_REG_ENC_DBW(info->dbw, channel);
ddr_msch_regs = dram->chan[channel].msch;
noc_timing = &sdram_params->ch[channel].noc_timings;
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 17/92] ram: rk3399: Add dbw enc macro
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
Add simplified and meaningful macro for dbw.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
arch/arm/include/asm/arch-rockchip/sdram_common.h | 1 +
drivers/ram/rockchip/sdram_rk3399.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index 8a71e8ad87..3b0557cb6d 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -57,6 +57,7 @@
#define SYS_REG_BW_MASK 3
#define SYS_REG_DBW_SHIFT(ch) ((ch) * 16)
#define SYS_REG_DBW_MASK 3
+#define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << SYS_REG_DBW_SHIFT(ch))
/* Get sdram size decode from reg */
size_t rockchip_sdram_size(phys_addr_t reg);
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 2614fef407..4047b4b7e3 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1031,7 +1031,7 @@ static void dram_all_config(struct dram_info *dram,
sys_reg |= (info->cs1_row - 13) <<
SYS_REG_CS1_ROW_SHIFT(channel);
sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(channel);
- sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(channel);
+ sys_reg |= SYS_REG_ENC_DBW(info->dbw, channel);
ddr_msch_regs = dram->chan[channel].msch;
noc_timing = &sdram_params->ch[channel].noc_timings;
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 18/92] ram: rk3399: Add cs0_rw macro
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Add simplified and meaningful macro for cs0_rw.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
arch/arm/include/asm/arch-rockchip/sdram_common.h | 2 ++
drivers/ram/rockchip/sdram_rk3399.c | 3 +--
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index 3b0557cb6d..5c94dba39e 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -51,6 +51,8 @@
SYS_REG_BK_SHIFT(ch))
#define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16)
#define SYS_REG_CS0_ROW_MASK 3
+#define SYS_REG_ENC_CS0_ROW(n, ch) (((n) - 13) << \
+ SYS_REG_CS0_ROW_SHIFT(ch))
#define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16)
#define SYS_REG_CS1_ROW_MASK 3
#define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 4047b4b7e3..e3555504b0 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1026,8 +1026,7 @@ static void dram_all_config(struct dram_info *dram,
sys_reg |= SYS_REG_ENC_RANK(info->rank, channel);
sys_reg |= SYS_REG_ENC_COL(info->col, channel);
sys_reg |= SYS_REG_ENC_BK(info->bk, channel);
- sys_reg |= (info->cs0_row - 13) <<
- SYS_REG_CS0_ROW_SHIFT(channel);
+ sys_reg |= SYS_REG_ENC_CS0_ROW(info->cs0_row, channel);
sys_reg |= (info->cs1_row - 13) <<
SYS_REG_CS1_ROW_SHIFT(channel);
sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(channel);
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 18/92] ram: rk3399: Add cs0_rw macro
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
Add simplified and meaningful macro for cs0_rw.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
arch/arm/include/asm/arch-rockchip/sdram_common.h | 2 ++
drivers/ram/rockchip/sdram_rk3399.c | 3 +--
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index 3b0557cb6d..5c94dba39e 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -51,6 +51,8 @@
SYS_REG_BK_SHIFT(ch))
#define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16)
#define SYS_REG_CS0_ROW_MASK 3
+#define SYS_REG_ENC_CS0_ROW(n, ch) (((n) - 13) << \
+ SYS_REG_CS0_ROW_SHIFT(ch))
#define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16)
#define SYS_REG_CS1_ROW_MASK 3
#define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 4047b4b7e3..e3555504b0 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1026,8 +1026,7 @@ static void dram_all_config(struct dram_info *dram,
sys_reg |= SYS_REG_ENC_RANK(info->rank, channel);
sys_reg |= SYS_REG_ENC_COL(info->col, channel);
sys_reg |= SYS_REG_ENC_BK(info->bk, channel);
- sys_reg |= (info->cs0_row - 13) <<
- SYS_REG_CS0_ROW_SHIFT(channel);
+ sys_reg |= SYS_REG_ENC_CS0_ROW(info->cs0_row, channel);
sys_reg |= (info->cs1_row - 13) <<
SYS_REG_CS1_ROW_SHIFT(channel);
sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(channel);
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 19/92] ram: rk3399: Add cs1_rw macro
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Add simplified and meaningful macro for cs1_rw.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
arch/arm/include/asm/arch-rockchip/sdram_common.h | 2 ++
drivers/ram/rockchip/sdram_rk3399.c | 3 +--
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index 5c94dba39e..a4b1742438 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -55,6 +55,8 @@
SYS_REG_CS0_ROW_SHIFT(ch))
#define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16)
#define SYS_REG_CS1_ROW_MASK 3
+#define SYS_REG_ENC_CS1_ROW(n, ch) (((n) - 13) << \
+ SYS_REG_CS1_ROW_SHIFT(ch))
#define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16)
#define SYS_REG_BW_MASK 3
#define SYS_REG_DBW_SHIFT(ch) ((ch) * 16)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index e3555504b0..f69194f29b 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1027,8 +1027,7 @@ static void dram_all_config(struct dram_info *dram,
sys_reg |= SYS_REG_ENC_COL(info->col, channel);
sys_reg |= SYS_REG_ENC_BK(info->bk, channel);
sys_reg |= SYS_REG_ENC_CS0_ROW(info->cs0_row, channel);
- sys_reg |= (info->cs1_row - 13) <<
- SYS_REG_CS1_ROW_SHIFT(channel);
+ sys_reg |= SYS_REG_ENC_CS1_ROW(info->cs1_row, channel);
sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(channel);
sys_reg |= SYS_REG_ENC_DBW(info->dbw, channel);
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 19/92] ram: rk3399: Add cs1_rw macro
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
Add simplified and meaningful macro for cs1_rw.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
arch/arm/include/asm/arch-rockchip/sdram_common.h | 2 ++
drivers/ram/rockchip/sdram_rk3399.c | 3 +--
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index 5c94dba39e..a4b1742438 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -55,6 +55,8 @@
SYS_REG_CS0_ROW_SHIFT(ch))
#define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16)
#define SYS_REG_CS1_ROW_MASK 3
+#define SYS_REG_ENC_CS1_ROW(n, ch) (((n) - 13) << \
+ SYS_REG_CS1_ROW_SHIFT(ch))
#define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16)
#define SYS_REG_BW_MASK 3
#define SYS_REG_DBW_SHIFT(ch) ((ch) * 16)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index e3555504b0..f69194f29b 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1027,8 +1027,7 @@ static void dram_all_config(struct dram_info *dram,
sys_reg |= SYS_REG_ENC_COL(info->col, channel);
sys_reg |= SYS_REG_ENC_BK(info->bk, channel);
sys_reg |= SYS_REG_ENC_CS0_ROW(info->cs0_row, channel);
- sys_reg |= (info->cs1_row - 13) <<
- SYS_REG_CS1_ROW_SHIFT(channel);
+ sys_reg |= SYS_REG_ENC_CS1_ROW(info->cs1_row, channel);
sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(channel);
sys_reg |= SYS_REG_ENC_DBW(info->dbw, channel);
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 20/92] ram: rk3399: Add bw enc macro
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Add simplified and meaningful macro for bw.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
arch/arm/include/asm/arch-rockchip/sdram_common.h | 1 +
drivers/ram/rockchip/sdram_rk3399.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index a4b1742438..7e0b491859 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -59,6 +59,7 @@
SYS_REG_CS1_ROW_SHIFT(ch))
#define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16)
#define SYS_REG_BW_MASK 3
+#define SYS_REG_ENC_BW(n, ch) ((2 >> (n)) << SYS_REG_BW_SHIFT(ch))
#define SYS_REG_DBW_SHIFT(ch) ((ch) * 16)
#define SYS_REG_DBW_MASK 3
#define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << SYS_REG_DBW_SHIFT(ch))
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index f69194f29b..3241bc285e 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1028,7 +1028,7 @@ static void dram_all_config(struct dram_info *dram,
sys_reg |= SYS_REG_ENC_BK(info->bk, channel);
sys_reg |= SYS_REG_ENC_CS0_ROW(info->cs0_row, channel);
sys_reg |= SYS_REG_ENC_CS1_ROW(info->cs1_row, channel);
- sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(channel);
+ sys_reg |= SYS_REG_ENC_BW(info->bw, channel);
sys_reg |= SYS_REG_ENC_DBW(info->dbw, channel);
ddr_msch_regs = dram->chan[channel].msch;
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 20/92] ram: rk3399: Add bw enc macro
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
Add simplified and meaningful macro for bw.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
arch/arm/include/asm/arch-rockchip/sdram_common.h | 1 +
drivers/ram/rockchip/sdram_rk3399.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index a4b1742438..7e0b491859 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -59,6 +59,7 @@
SYS_REG_CS1_ROW_SHIFT(ch))
#define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16)
#define SYS_REG_BW_MASK 3
+#define SYS_REG_ENC_BW(n, ch) ((2 >> (n)) << SYS_REG_BW_SHIFT(ch))
#define SYS_REG_DBW_SHIFT(ch) ((ch) * 16)
#define SYS_REG_DBW_MASK 3
#define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << SYS_REG_DBW_SHIFT(ch))
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index f69194f29b..3241bc285e 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1028,7 +1028,7 @@ static void dram_all_config(struct dram_info *dram,
sys_reg |= SYS_REG_ENC_BK(info->bk, channel);
sys_reg |= SYS_REG_ENC_CS0_ROW(info->cs0_row, channel);
sys_reg |= SYS_REG_ENC_CS1_ROW(info->cs1_row, channel);
- sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(channel);
+ sys_reg |= SYS_REG_ENC_BW(info->bw, channel);
sys_reg |= SYS_REG_ENC_DBW(info->dbw, channel);
ddr_msch_regs = dram->chan[channel].msch;
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 21/92] ram: rk3399: Rename sys_reg with sys_reg2
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Use dram config variable name as sys_reg2 instead of sys_reg
since the final variable value is to written into a pmugrf
register named as sys_reg2.
This reflect the both variable and associated register
names are same and also help to add next sys_reg's to
add it in future.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 26 +++++++++++++-------------
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 3241bc285e..4463fc84c8 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1005,11 +1005,11 @@ static void set_ddrconfig(const struct chan_info *chan,
static void dram_all_config(struct dram_info *dram,
const struct rk3399_sdram_params *sdram_params)
{
- u32 sys_reg = 0;
+ u32 sys_reg2 = 0;
unsigned int channel, idx;
- sys_reg |= SYS_REG_ENC_DDRTYPE(sdram_params->base.dramtype);
- sys_reg |= SYS_REG_ENC_NUM_CH(sdram_params->base.num_channels);
+ sys_reg2 |= SYS_REG_ENC_DDRTYPE(sdram_params->base.dramtype);
+ sys_reg2 |= SYS_REG_ENC_NUM_CH(sdram_params->base.num_channels);
for (channel = 0, idx = 0;
(idx < sdram_params->base.num_channels) && (channel < 2);
channel++) {
@@ -1021,15 +1021,15 @@ static void dram_all_config(struct dram_info *dram,
if (sdram_params->ch[channel].col == 0)
continue;
idx++;
- sys_reg |= SYS_REG_ENC_ROW_3_4(info->row_3_4, channel);
- sys_reg |= SYS_REG_ENC_CHINFO(channel);
- sys_reg |= SYS_REG_ENC_RANK(info->rank, channel);
- sys_reg |= SYS_REG_ENC_COL(info->col, channel);
- sys_reg |= SYS_REG_ENC_BK(info->bk, channel);
- sys_reg |= SYS_REG_ENC_CS0_ROW(info->cs0_row, channel);
- sys_reg |= SYS_REG_ENC_CS1_ROW(info->cs1_row, channel);
- sys_reg |= SYS_REG_ENC_BW(info->bw, channel);
- sys_reg |= SYS_REG_ENC_DBW(info->dbw, channel);
+ sys_reg2 |= SYS_REG_ENC_ROW_3_4(info->row_3_4, channel);
+ sys_reg2 |= SYS_REG_ENC_CHINFO(channel);
+ sys_reg2 |= SYS_REG_ENC_RANK(info->rank, channel);
+ sys_reg2 |= SYS_REG_ENC_COL(info->col, channel);
+ sys_reg2 |= SYS_REG_ENC_BK(info->bk, channel);
+ sys_reg2 |= SYS_REG_ENC_CS0_ROW(info->cs0_row, channel);
+ sys_reg2 |= SYS_REG_ENC_CS1_ROW(info->cs1_row, channel);
+ sys_reg2 |= SYS_REG_ENC_BW(info->bw, channel);
+ sys_reg2 |= SYS_REG_ENC_DBW(info->dbw, channel);
ddr_msch_regs = dram->chan[channel].msch;
noc_timing = &sdram_params->ch[channel].noc_timings;
@@ -1050,7 +1050,7 @@ static void dram_all_config(struct dram_info *dram,
1 << 17);
}
- writel(sys_reg, &dram->pmugrf->os_reg2);
+ writel(sys_reg2, &dram->pmugrf->os_reg2);
rk_clrsetreg(&dram->pmusgrf->soc_con4, 0x1f << 10,
sdram_params->base.stride << 10);
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 21/92] ram: rk3399: Rename sys_reg with sys_reg2
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
Use dram config variable name as sys_reg2 instead of sys_reg
since the final variable value is to written into a pmugrf
register named as sys_reg2.
This reflect the both variable and associated register
names are same and also help to add next sys_reg's to
add it in future.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 26 +++++++++++++-------------
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 3241bc285e..4463fc84c8 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1005,11 +1005,11 @@ static void set_ddrconfig(const struct chan_info *chan,
static void dram_all_config(struct dram_info *dram,
const struct rk3399_sdram_params *sdram_params)
{
- u32 sys_reg = 0;
+ u32 sys_reg2 = 0;
unsigned int channel, idx;
- sys_reg |= SYS_REG_ENC_DDRTYPE(sdram_params->base.dramtype);
- sys_reg |= SYS_REG_ENC_NUM_CH(sdram_params->base.num_channels);
+ sys_reg2 |= SYS_REG_ENC_DDRTYPE(sdram_params->base.dramtype);
+ sys_reg2 |= SYS_REG_ENC_NUM_CH(sdram_params->base.num_channels);
for (channel = 0, idx = 0;
(idx < sdram_params->base.num_channels) && (channel < 2);
channel++) {
@@ -1021,15 +1021,15 @@ static void dram_all_config(struct dram_info *dram,
if (sdram_params->ch[channel].col == 0)
continue;
idx++;
- sys_reg |= SYS_REG_ENC_ROW_3_4(info->row_3_4, channel);
- sys_reg |= SYS_REG_ENC_CHINFO(channel);
- sys_reg |= SYS_REG_ENC_RANK(info->rank, channel);
- sys_reg |= SYS_REG_ENC_COL(info->col, channel);
- sys_reg |= SYS_REG_ENC_BK(info->bk, channel);
- sys_reg |= SYS_REG_ENC_CS0_ROW(info->cs0_row, channel);
- sys_reg |= SYS_REG_ENC_CS1_ROW(info->cs1_row, channel);
- sys_reg |= SYS_REG_ENC_BW(info->bw, channel);
- sys_reg |= SYS_REG_ENC_DBW(info->dbw, channel);
+ sys_reg2 |= SYS_REG_ENC_ROW_3_4(info->row_3_4, channel);
+ sys_reg2 |= SYS_REG_ENC_CHINFO(channel);
+ sys_reg2 |= SYS_REG_ENC_RANK(info->rank, channel);
+ sys_reg2 |= SYS_REG_ENC_COL(info->col, channel);
+ sys_reg2 |= SYS_REG_ENC_BK(info->bk, channel);
+ sys_reg2 |= SYS_REG_ENC_CS0_ROW(info->cs0_row, channel);
+ sys_reg2 |= SYS_REG_ENC_CS1_ROW(info->cs1_row, channel);
+ sys_reg2 |= SYS_REG_ENC_BW(info->bw, channel);
+ sys_reg2 |= SYS_REG_ENC_DBW(info->dbw, channel);
ddr_msch_regs = dram->chan[channel].msch;
noc_timing = &sdram_params->ch[channel].noc_timings;
@@ -1050,7 +1050,7 @@ static void dram_all_config(struct dram_info *dram,
1 << 17);
}
- writel(sys_reg, &dram->pmugrf->os_reg2);
+ writel(sys_reg2, &dram->pmugrf->os_reg2);
rk_clrsetreg(&dram->pmusgrf->soc_con4, 0x1f << 10,
sdram_params->base.stride << 10);
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 22/92] ram: rk3399: Update cs0_row to use sys_reg3
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
cs0_row can handle the pmu via sys_reg2 and sys_reg3 while
configuring the dram instead of just sys_reg2.
So, update cs0_row macro to make use of both sys_reg2,
sys_reg3.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
arch/arm/include/asm/arch-rockchip/sdram_common.h | 8 ++++++--
drivers/ram/rockchip/sdram_rk3399.c | 4 +++-
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index 7e0b491859..3d1d5badb4 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -51,8 +51,6 @@
SYS_REG_BK_SHIFT(ch))
#define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16)
#define SYS_REG_CS0_ROW_MASK 3
-#define SYS_REG_ENC_CS0_ROW(n, ch) (((n) - 13) << \
- SYS_REG_CS0_ROW_SHIFT(ch))
#define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16)
#define SYS_REG_CS1_ROW_MASK 3
#define SYS_REG_ENC_CS1_ROW(n, ch) (((n) - 13) << \
@@ -64,6 +62,12 @@
#define SYS_REG_DBW_MASK 3
#define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << SYS_REG_DBW_SHIFT(ch))
+#define SYS_REG_ENC_CS0_ROW(n, os_reg2, os_reg3, ch) do { \
+ (os_reg2) |= (((n) - 13) & 0x3) << (6 + 16 * (ch)); \
+ (os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \
+ (5 + 2 * (ch)); \
+ } while (0)
+
/* Get sdram size decode from reg */
size_t rockchip_sdram_size(phys_addr_t reg);
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 4463fc84c8..2408246d0d 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1006,6 +1006,7 @@ static void dram_all_config(struct dram_info *dram,
const struct rk3399_sdram_params *sdram_params)
{
u32 sys_reg2 = 0;
+ u32 sys_reg3 = 0;
unsigned int channel, idx;
sys_reg2 |= SYS_REG_ENC_DDRTYPE(sdram_params->base.dramtype);
@@ -1026,10 +1027,10 @@ static void dram_all_config(struct dram_info *dram,
sys_reg2 |= SYS_REG_ENC_RANK(info->rank, channel);
sys_reg2 |= SYS_REG_ENC_COL(info->col, channel);
sys_reg2 |= SYS_REG_ENC_BK(info->bk, channel);
- sys_reg2 |= SYS_REG_ENC_CS0_ROW(info->cs0_row, channel);
sys_reg2 |= SYS_REG_ENC_CS1_ROW(info->cs1_row, channel);
sys_reg2 |= SYS_REG_ENC_BW(info->bw, channel);
sys_reg2 |= SYS_REG_ENC_DBW(info->dbw, channel);
+ SYS_REG_ENC_CS0_ROW(info->cs0_row, sys_reg2, sys_reg3, channel);
ddr_msch_regs = dram->chan[channel].msch;
noc_timing = &sdram_params->ch[channel].noc_timings;
@@ -1051,6 +1052,7 @@ static void dram_all_config(struct dram_info *dram,
}
writel(sys_reg2, &dram->pmugrf->os_reg2);
+ writel(sys_reg3, &dram->pmugrf->os_reg3);
rk_clrsetreg(&dram->pmusgrf->soc_con4, 0x1f << 10,
sdram_params->base.stride << 10);
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 22/92] ram: rk3399: Update cs0_row to use sys_reg3
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
cs0_row can handle the pmu via sys_reg2 and sys_reg3 while
configuring the dram instead of just sys_reg2.
So, update cs0_row macro to make use of both sys_reg2,
sys_reg3.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
arch/arm/include/asm/arch-rockchip/sdram_common.h | 8 ++++++--
drivers/ram/rockchip/sdram_rk3399.c | 4 +++-
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index 7e0b491859..3d1d5badb4 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -51,8 +51,6 @@
SYS_REG_BK_SHIFT(ch))
#define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16)
#define SYS_REG_CS0_ROW_MASK 3
-#define SYS_REG_ENC_CS0_ROW(n, ch) (((n) - 13) << \
- SYS_REG_CS0_ROW_SHIFT(ch))
#define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16)
#define SYS_REG_CS1_ROW_MASK 3
#define SYS_REG_ENC_CS1_ROW(n, ch) (((n) - 13) << \
@@ -64,6 +62,12 @@
#define SYS_REG_DBW_MASK 3
#define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << SYS_REG_DBW_SHIFT(ch))
+#define SYS_REG_ENC_CS0_ROW(n, os_reg2, os_reg3, ch) do { \
+ (os_reg2) |= (((n) - 13) & 0x3) << (6 + 16 * (ch)); \
+ (os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \
+ (5 + 2 * (ch)); \
+ } while (0)
+
/* Get sdram size decode from reg */
size_t rockchip_sdram_size(phys_addr_t reg);
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 4463fc84c8..2408246d0d 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1006,6 +1006,7 @@ static void dram_all_config(struct dram_info *dram,
const struct rk3399_sdram_params *sdram_params)
{
u32 sys_reg2 = 0;
+ u32 sys_reg3 = 0;
unsigned int channel, idx;
sys_reg2 |= SYS_REG_ENC_DDRTYPE(sdram_params->base.dramtype);
@@ -1026,10 +1027,10 @@ static void dram_all_config(struct dram_info *dram,
sys_reg2 |= SYS_REG_ENC_RANK(info->rank, channel);
sys_reg2 |= SYS_REG_ENC_COL(info->col, channel);
sys_reg2 |= SYS_REG_ENC_BK(info->bk, channel);
- sys_reg2 |= SYS_REG_ENC_CS0_ROW(info->cs0_row, channel);
sys_reg2 |= SYS_REG_ENC_CS1_ROW(info->cs1_row, channel);
sys_reg2 |= SYS_REG_ENC_BW(info->bw, channel);
sys_reg2 |= SYS_REG_ENC_DBW(info->dbw, channel);
+ SYS_REG_ENC_CS0_ROW(info->cs0_row, sys_reg2, sys_reg3, channel);
ddr_msch_regs = dram->chan[channel].msch;
noc_timing = &sdram_params->ch[channel].noc_timings;
@@ -1051,6 +1052,7 @@ static void dram_all_config(struct dram_info *dram,
}
writel(sys_reg2, &dram->pmugrf->os_reg2);
+ writel(sys_reg3, &dram->pmugrf->os_reg3);
rk_clrsetreg(&dram->pmusgrf->soc_con4, 0x1f << 10,
sdram_params->base.stride << 10);
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 23/92] ram: rk3399: Update cs1_row to use sys_reg3
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
cs1_row can handle the pmu via sys_reg2 and sys_reg3 while
configuring the dram instead of just sys_reg2.
So, update cs1_row macro to make use of both sys_reg2,
sys_reg3.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
arch/arm/include/asm/arch-rockchip/sdram_common.h | 10 ++++++++--
drivers/ram/rockchip/sdram_rk3399.c | 4 +++-
2 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index 3d1d5badb4..dc7275656e 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -53,8 +53,6 @@
#define SYS_REG_CS0_ROW_MASK 3
#define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16)
#define SYS_REG_CS1_ROW_MASK 3
-#define SYS_REG_ENC_CS1_ROW(n, ch) (((n) - 13) << \
- SYS_REG_CS1_ROW_SHIFT(ch))
#define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16)
#define SYS_REG_BW_MASK 3
#define SYS_REG_ENC_BW(n, ch) ((2 >> (n)) << SYS_REG_BW_SHIFT(ch))
@@ -68,6 +66,14 @@
(5 + 2 * (ch)); \
} while (0)
+#define SYS_REG_ENC_CS1_ROW(n, os_reg2, os_reg3, ch) do { \
+ (os_reg2) &= (~(0x3 << (4 + 16 * (ch)))); \
+ (os_reg3) &= (~(0x1 << (4 + 2 * (ch)))); \
+ (os_reg2) |= (((n) - 13) & 0x3) << (4 + 16 * (ch)); \
+ (os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \
+ (4 + 2 * (ch)); \
+ } while (0)
+
/* Get sdram size decode from reg */
size_t rockchip_sdram_size(phys_addr_t reg);
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 2408246d0d..772fde9732 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1027,10 +1027,12 @@ static void dram_all_config(struct dram_info *dram,
sys_reg2 |= SYS_REG_ENC_RANK(info->rank, channel);
sys_reg2 |= SYS_REG_ENC_COL(info->col, channel);
sys_reg2 |= SYS_REG_ENC_BK(info->bk, channel);
- sys_reg2 |= SYS_REG_ENC_CS1_ROW(info->cs1_row, channel);
sys_reg2 |= SYS_REG_ENC_BW(info->bw, channel);
sys_reg2 |= SYS_REG_ENC_DBW(info->dbw, channel);
SYS_REG_ENC_CS0_ROW(info->cs0_row, sys_reg2, sys_reg3, channel);
+ if (info->cs1_row)
+ SYS_REG_ENC_CS1_ROW(info->cs1_row, sys_reg2,
+ sys_reg3, channel);
ddr_msch_regs = dram->chan[channel].msch;
noc_timing = &sdram_params->ch[channel].noc_timings;
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 23/92] ram: rk3399: Update cs1_row to use sys_reg3
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
cs1_row can handle the pmu via sys_reg2 and sys_reg3 while
configuring the dram instead of just sys_reg2.
So, update cs1_row macro to make use of both sys_reg2,
sys_reg3.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
arch/arm/include/asm/arch-rockchip/sdram_common.h | 10 ++++++++--
drivers/ram/rockchip/sdram_rk3399.c | 4 +++-
2 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index 3d1d5badb4..dc7275656e 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -53,8 +53,6 @@
#define SYS_REG_CS0_ROW_MASK 3
#define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16)
#define SYS_REG_CS1_ROW_MASK 3
-#define SYS_REG_ENC_CS1_ROW(n, ch) (((n) - 13) << \
- SYS_REG_CS1_ROW_SHIFT(ch))
#define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16)
#define SYS_REG_BW_MASK 3
#define SYS_REG_ENC_BW(n, ch) ((2 >> (n)) << SYS_REG_BW_SHIFT(ch))
@@ -68,6 +66,14 @@
(5 + 2 * (ch)); \
} while (0)
+#define SYS_REG_ENC_CS1_ROW(n, os_reg2, os_reg3, ch) do { \
+ (os_reg2) &= (~(0x3 << (4 + 16 * (ch)))); \
+ (os_reg3) &= (~(0x1 << (4 + 2 * (ch)))); \
+ (os_reg2) |= (((n) - 13) & 0x3) << (4 + 16 * (ch)); \
+ (os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \
+ (4 + 2 * (ch)); \
+ } while (0)
+
/* Get sdram size decode from reg */
size_t rockchip_sdram_size(phys_addr_t reg);
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 2408246d0d..772fde9732 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1027,10 +1027,12 @@ static void dram_all_config(struct dram_info *dram,
sys_reg2 |= SYS_REG_ENC_RANK(info->rank, channel);
sys_reg2 |= SYS_REG_ENC_COL(info->col, channel);
sys_reg2 |= SYS_REG_ENC_BK(info->bk, channel);
- sys_reg2 |= SYS_REG_ENC_CS1_ROW(info->cs1_row, channel);
sys_reg2 |= SYS_REG_ENC_BW(info->bw, channel);
sys_reg2 |= SYS_REG_ENC_DBW(info->dbw, channel);
SYS_REG_ENC_CS0_ROW(info->cs0_row, sys_reg2, sys_reg3, channel);
+ if (info->cs1_row)
+ SYS_REG_ENC_CS1_ROW(info->cs1_row, sys_reg2,
+ sys_reg3, channel);
ddr_msch_regs = dram->chan[channel].msch;
noc_timing = &sdram_params->ch[channel].noc_timings;
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 24/92] ram: rk3399: Add cs1_col enc macro
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Add dram config macro for handling cs1 column.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
arch/arm/include/asm/arch-rockchip/sdram_common.h | 3 +++
drivers/ram/rockchip/sdram_rk3399.c | 1 +
2 files changed, 4 insertions(+)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index dc7275656e..637a0de902 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -74,6 +74,9 @@
(4 + 2 * (ch)); \
} while (0)
+#define SYS_REG_CS1_COL_SHIFT(ch) (0 + 2 * (ch))
+#define SYS_REG_ENC_CS1_COL(n, ch) (((n) - 9) << SYS_REG_CS1_COL_SHIFT(ch))
+
/* Get sdram size decode from reg */
size_t rockchip_sdram_size(phys_addr_t reg);
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 772fde9732..d77a8310cd 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1033,6 +1033,7 @@ static void dram_all_config(struct dram_info *dram,
if (info->cs1_row)
SYS_REG_ENC_CS1_ROW(info->cs1_row, sys_reg2,
sys_reg3, channel);
+ sys_reg3 |= SYS_REG_ENC_CS1_COL(info->col, channel);
ddr_msch_regs = dram->chan[channel].msch;
noc_timing = &sdram_params->ch[channel].noc_timings;
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 24/92] ram: rk3399: Add cs1_col enc macro
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
Add dram config macro for handling cs1 column.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
arch/arm/include/asm/arch-rockchip/sdram_common.h | 3 +++
drivers/ram/rockchip/sdram_rk3399.c | 1 +
2 files changed, 4 insertions(+)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index dc7275656e..637a0de902 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -74,6 +74,9 @@
(4 + 2 * (ch)); \
} while (0)
+#define SYS_REG_CS1_COL_SHIFT(ch) (0 + 2 * (ch))
+#define SYS_REG_ENC_CS1_COL(n, ch) (((n) - 9) << SYS_REG_CS1_COL_SHIFT(ch))
+
/* Get sdram size decode from reg */
size_t rockchip_sdram_size(phys_addr_t reg);
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 772fde9732..d77a8310cd 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1033,6 +1033,7 @@ static void dram_all_config(struct dram_info *dram,
if (info->cs1_row)
SYS_REG_ENC_CS1_ROW(info->cs1_row, sys_reg2,
sys_reg3, channel);
+ sys_reg3 |= SYS_REG_ENC_CS1_COL(info->col, channel);
ddr_msch_regs = dram->chan[channel].msch;
noc_timing = &sdram_params->ch[channel].noc_timings;
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 25/92] ram: rk3399: Add ddr version enc macro
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Add dram config macro for handling ddr version number.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
arch/arm/include/asm/arch-rockchip/sdram_common.h | 2 ++
drivers/ram/rockchip/sdram_rk3399.c | 2 ++
2 files changed, 4 insertions(+)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index 637a0de902..8021ca21ed 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -28,6 +28,7 @@
* [1:0] dbw_ch0
*/
#define SYS_REG_DDRTYPE_SHIFT 13
+#define DDR_SYS_REG_VERSION 2
#define SYS_REG_DDRTYPE_MASK 7
#define SYS_REG_NUM_CH_SHIFT 12
#define SYS_REG_NUM_CH_MASK 1
@@ -60,6 +61,7 @@
#define SYS_REG_DBW_MASK 3
#define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << SYS_REG_DBW_SHIFT(ch))
+#define SYS_REG_ENC_VERSION(n) ((n) << 28)
#define SYS_REG_ENC_CS0_ROW(n, os_reg2, os_reg3, ch) do { \
(os_reg2) |= (((n) - 13) & 0x3) << (6 + 16 * (ch)); \
(os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index d77a8310cd..5b87524b7c 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1033,7 +1033,9 @@ static void dram_all_config(struct dram_info *dram,
if (info->cs1_row)
SYS_REG_ENC_CS1_ROW(info->cs1_row, sys_reg2,
sys_reg3, channel);
+
sys_reg3 |= SYS_REG_ENC_CS1_COL(info->col, channel);
+ sys_reg3 |= SYS_REG_ENC_VERSION(DDR_SYS_REG_VERSION);
ddr_msch_regs = dram->chan[channel].msch;
noc_timing = &sdram_params->ch[channel].noc_timings;
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 25/92] ram: rk3399: Add ddr version enc macro
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
Add dram config macro for handling ddr version number.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
arch/arm/include/asm/arch-rockchip/sdram_common.h | 2 ++
drivers/ram/rockchip/sdram_rk3399.c | 2 ++
2 files changed, 4 insertions(+)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index 637a0de902..8021ca21ed 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -28,6 +28,7 @@
* [1:0] dbw_ch0
*/
#define SYS_REG_DDRTYPE_SHIFT 13
+#define DDR_SYS_REG_VERSION 2
#define SYS_REG_DDRTYPE_MASK 7
#define SYS_REG_NUM_CH_SHIFT 12
#define SYS_REG_NUM_CH_MASK 1
@@ -60,6 +61,7 @@
#define SYS_REG_DBW_MASK 3
#define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << SYS_REG_DBW_SHIFT(ch))
+#define SYS_REG_ENC_VERSION(n) ((n) << 28)
#define SYS_REG_ENC_CS0_ROW(n, os_reg2, os_reg3, ch) do { \
(os_reg2) |= (((n) - 13) & 0x3) << (6 + 16 * (ch)); \
(os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index d77a8310cd..5b87524b7c 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1033,7 +1033,9 @@ static void dram_all_config(struct dram_info *dram,
if (info->cs1_row)
SYS_REG_ENC_CS1_ROW(info->cs1_row, sys_reg2,
sys_reg3, channel);
+
sys_reg3 |= SYS_REG_ENC_CS1_COL(info->col, channel);
+ sys_reg3 |= SYS_REG_ENC_VERSION(DDR_SYS_REG_VERSION);
ddr_msch_regs = dram->chan[channel].msch;
noc_timing = &sdram_params->ch[channel].noc_timings;
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 26/92] ram: rk3399: Add ddrtimingC0
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Add DdrTimingC0 structure with associated bit fields.
These would help to reconfigure sdram capabilities during
lpddr4 setup related configs.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
arch/arm/include/asm/arch-rockchip/sdram_rk3399.h | 12 +++++++++++-
drivers/ram/rockchip/sdram_rk3399.c | 2 +-
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
index c6a260bad8..924eeb3bac 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
@@ -26,6 +26,16 @@ struct rk3399_ddr_pi_regs {
u32 denali_pi[200];
};
+union noc_ddrtimingc0 {
+ u32 d32;
+ struct {
+ unsigned burstpenalty : 4;
+ unsigned reserved0 : 4;
+ unsigned wrtomwr : 6;
+ unsigned reserved1 : 18;
+ } b;
+};
+
struct rk3399_msch_regs {
u32 coreid;
u32 revisionid;
@@ -44,7 +54,7 @@ struct rk3399_msch_regs {
struct rk3399_msch_timings {
u32 ddrtiminga0;
u32 ddrtimingb0;
- u32 ddrtimingc0;
+ union noc_ddrtimingc0 ddrtimingc0;
u32 devtodev0;
u32 ddrmode;
u32 agingx0;
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 5b87524b7c..f9fec14758 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1043,7 +1043,7 @@ static void dram_all_config(struct dram_info *dram,
&ddr_msch_regs->ddrtiminga0);
writel(noc_timing->ddrtimingb0,
&ddr_msch_regs->ddrtimingb0);
- writel(noc_timing->ddrtimingc0,
+ writel(noc_timing->ddrtimingc0.d32,
&ddr_msch_regs->ddrtimingc0);
writel(noc_timing->devtodev0,
&ddr_msch_regs->devtodev0);
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 26/92] ram: rk3399: Add ddrtimingC0
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
Add DdrTimingC0 structure with associated bit fields.
These would help to reconfigure sdram capabilities during
lpddr4 setup related configs.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/arm/include/asm/arch-rockchip/sdram_rk3399.h | 12 +++++++++++-
drivers/ram/rockchip/sdram_rk3399.c | 2 +-
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
index c6a260bad8..924eeb3bac 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
@@ -26,6 +26,16 @@ struct rk3399_ddr_pi_regs {
u32 denali_pi[200];
};
+union noc_ddrtimingc0 {
+ u32 d32;
+ struct {
+ unsigned burstpenalty : 4;
+ unsigned reserved0 : 4;
+ unsigned wrtomwr : 6;
+ unsigned reserved1 : 18;
+ } b;
+};
+
struct rk3399_msch_regs {
u32 coreid;
u32 revisionid;
@@ -44,7 +54,7 @@ struct rk3399_msch_regs {
struct rk3399_msch_timings {
u32 ddrtiminga0;
u32 ddrtimingb0;
- u32 ddrtimingc0;
+ union noc_ddrtimingc0 ddrtimingc0;
u32 devtodev0;
u32 ddrmode;
u32 agingx0;
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 5b87524b7c..f9fec14758 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1043,7 +1043,7 @@ static void dram_all_config(struct dram_info *dram,
&ddr_msch_regs->ddrtiminga0);
writel(noc_timing->ddrtimingb0,
&ddr_msch_regs->ddrtimingb0);
- writel(noc_timing->ddrtimingc0,
+ writel(noc_timing->ddrtimingc0.d32,
&ddr_msch_regs->ddrtimingc0);
writel(noc_timing->devtodev0,
&ddr_msch_regs->devtodev0);
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 27/92] ram: rk3399: Add DdrMode
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Add DdrMode structure with associated bit fields.
These would help to reconfigure sdram capabilities during
lpddr4 setup related configs.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
.../include/asm/arch-rockchip/sdram_rk3399.h | 17 ++++++++++++++++-
drivers/ram/rockchip/sdram_rk3399.c | 2 +-
2 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
index 924eeb3bac..a191d242f8 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
@@ -36,6 +36,21 @@ union noc_ddrtimingc0 {
} b;
};
+union noc_ddrmode {
+ u32 d32;
+ struct {
+ unsigned autoprecharge : 1;
+ unsigned bypassfiltering : 1;
+ unsigned fawbank : 1;
+ unsigned burstsize : 2;
+ unsigned mwrsize : 2;
+ unsigned reserved2 : 1;
+ unsigned forceorder : 8;
+ unsigned forceorderstate : 8;
+ unsigned reserved3 : 8;
+ } b;
+};
+
struct rk3399_msch_regs {
u32 coreid;
u32 revisionid;
@@ -56,7 +71,7 @@ struct rk3399_msch_timings {
u32 ddrtimingb0;
union noc_ddrtimingc0 ddrtimingc0;
u32 devtodev0;
- u32 ddrmode;
+ union noc_ddrmode ddrmode;
u32 agingx0;
};
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index f9fec14758..6bf8dce6e0 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1047,7 +1047,7 @@ static void dram_all_config(struct dram_info *dram,
&ddr_msch_regs->ddrtimingc0);
writel(noc_timing->devtodev0,
&ddr_msch_regs->devtodev0);
- writel(noc_timing->ddrmode,
+ writel(noc_timing->ddrmode.d32,
&ddr_msch_regs->ddrmode);
/* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 27/92] ram: rk3399: Add DdrMode
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
Add DdrMode structure with associated bit fields.
These would help to reconfigure sdram capabilities during
lpddr4 setup related configs.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
.../include/asm/arch-rockchip/sdram_rk3399.h | 17 ++++++++++++++++-
drivers/ram/rockchip/sdram_rk3399.c | 2 +-
2 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
index 924eeb3bac..a191d242f8 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
@@ -36,6 +36,21 @@ union noc_ddrtimingc0 {
} b;
};
+union noc_ddrmode {
+ u32 d32;
+ struct {
+ unsigned autoprecharge : 1;
+ unsigned bypassfiltering : 1;
+ unsigned fawbank : 1;
+ unsigned burstsize : 2;
+ unsigned mwrsize : 2;
+ unsigned reserved2 : 1;
+ unsigned forceorder : 8;
+ unsigned forceorderstate : 8;
+ unsigned reserved3 : 8;
+ } b;
+};
+
struct rk3399_msch_regs {
u32 coreid;
u32 revisionid;
@@ -56,7 +71,7 @@ struct rk3399_msch_timings {
u32 ddrtimingb0;
union noc_ddrtimingc0 ddrtimingc0;
u32 devtodev0;
- u32 ddrmode;
+ union noc_ddrmode ddrmode;
u32 agingx0;
};
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index f9fec14758..6bf8dce6e0 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1047,7 +1047,7 @@ static void dram_all_config(struct dram_info *dram,
&ddr_msch_regs->ddrtimingc0);
writel(noc_timing->devtodev0,
&ddr_msch_regs->devtodev0);
- writel(noc_timing->ddrmode,
+ writel(noc_timing->ddrmode.d32,
&ddr_msch_regs->ddrmode);
/* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 28/92] ram: rk3399: Handle pctl_cfg return type
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Add proper return type handling of pctl_cfg with
meaningful print statement.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 6bf8dce6e0..fab7515b2d 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1120,6 +1120,7 @@ static int sdram_init(struct dram_info *dram,
unsigned char dramtype = sdram_params->base.dramtype;
unsigned int ddr_freq = sdram_params->base.ddr_freq;
int channel;
+ int ret;
debug("Starting SDRAM initialization...\n");
@@ -1139,9 +1140,10 @@ static int sdram_init(struct dram_info *dram,
if (channel >= sdram_params->base.num_channels)
continue;
- if (pctl_cfg(chan, channel, sdram_params) != 0) {
- printf("pctl_cfg fail, reset\n");
- return -EIO;
+ ret = pctl_cfg(chan, channel, sdram_params);
+ if (ret < 0) {
+ printf("%s: pctl config failed\n", __func__);
+ return ret;
}
/* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 28/92] ram: rk3399: Handle pctl_cfg return type
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
Add proper return type handling of pctl_cfg with
meaningful print statement.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 6bf8dce6e0..fab7515b2d 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1120,6 +1120,7 @@ static int sdram_init(struct dram_info *dram,
unsigned char dramtype = sdram_params->base.dramtype;
unsigned int ddr_freq = sdram_params->base.ddr_freq;
int channel;
+ int ret;
debug("Starting SDRAM initialization...\n");
@@ -1139,9 +1140,10 @@ static int sdram_init(struct dram_info *dram,
if (channel >= sdram_params->base.num_channels)
continue;
- if (pctl_cfg(chan, channel, sdram_params) != 0) {
- printf("pctl_cfg fail, reset\n");
- return -EIO;
+ ret = pctl_cfg(chan, channel, sdram_params);
+ if (ret < 0) {
+ printf("%s: pctl config failed\n", __func__);
+ return ret;
}
/* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 29/92] ram: rk3399: s/tsel_wr_select_n/tsel_wr_select_dq_n
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Rename tsel_wr_select_n to tsel_wr_select_dq_n based
on the bsp code and associated datasheet.
No functionality change.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index fab7515b2d..7c05814f19 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -162,7 +162,7 @@ static void set_ds_odt(const struct chan_info *chan,
u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
u32 tsel_idle_select_p, tsel_wr_select_p, tsel_rd_select_p;
u32 ca_tsel_wr_select_p, ca_tsel_wr_select_n;
- u32 tsel_idle_select_n, tsel_wr_select_n, tsel_rd_select_n;
+ u32 tsel_idle_select_n, tsel_wr_select_dq_n, tsel_rd_select_n;
u32 reg_value;
if (sdram_params->base.dramtype == LPDDR4) {
@@ -172,7 +172,7 @@ static void set_ds_odt(const struct chan_info *chan,
tsel_idle_select_p = PHY_DRV_ODT_HI_Z;
tsel_rd_select_n = PHY_DRV_ODT_240;
- tsel_wr_select_n = PHY_DRV_ODT_40;
+ tsel_wr_select_dq_n = PHY_DRV_ODT_40;
ca_tsel_wr_select_n = PHY_DRV_ODT_40;
tsel_idle_select_n = PHY_DRV_ODT_240;
} else if (sdram_params->base.dramtype == LPDDR3) {
@@ -182,7 +182,7 @@ static void set_ds_odt(const struct chan_info *chan,
tsel_idle_select_p = PHY_DRV_ODT_240;
tsel_rd_select_n = PHY_DRV_ODT_HI_Z;
- tsel_wr_select_n = PHY_DRV_ODT_34_3;
+ tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
ca_tsel_wr_select_n = PHY_DRV_ODT_48;
tsel_idle_select_n = PHY_DRV_ODT_HI_Z;
} else {
@@ -192,7 +192,7 @@ static void set_ds_odt(const struct chan_info *chan,
tsel_idle_select_p = PHY_DRV_ODT_240;
tsel_rd_select_n = PHY_DRV_ODT_240;
- tsel_wr_select_n = PHY_DRV_ODT_34_3;
+ tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
ca_tsel_wr_select_n = PHY_DRV_ODT_34_3;
tsel_idle_select_n = PHY_DRV_ODT_240;
}
@@ -211,7 +211,7 @@ static void set_ds_odt(const struct chan_info *chan,
* for write cycles for DQ/DM
*/
reg_value = tsel_rd_select_n | (tsel_rd_select_p << 0x4) |
- (tsel_wr_select_n << 8) | (tsel_wr_select_p << 12) |
+ (tsel_wr_select_dq_n << 8) | (tsel_wr_select_p << 12) |
(tsel_idle_select_n << 16) | (tsel_idle_select_p << 20);
clrsetbits_le32(&denali_phy[6], 0xffffff, reg_value);
clrsetbits_le32(&denali_phy[134], 0xffffff, reg_value);
@@ -251,7 +251,7 @@ static void set_ds_odt(const struct chan_info *chan,
/* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */
clrsetbits_le32(&denali_phy[924], 0xff,
- tsel_wr_select_n | (tsel_wr_select_p << 4));
+ tsel_wr_select_dq_n | (tsel_wr_select_p << 4));
clrsetbits_le32(&denali_phy[925], 0xff,
tsel_rd_select_n | (tsel_rd_select_p << 4));
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 29/92] ram: rk3399: s/tsel_wr_select_n/tsel_wr_select_dq_n
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
Rename tsel_wr_select_n to tsel_wr_select_dq_n based
on the bsp code and associated datasheet.
No functionality change.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index fab7515b2d..7c05814f19 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -162,7 +162,7 @@ static void set_ds_odt(const struct chan_info *chan,
u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
u32 tsel_idle_select_p, tsel_wr_select_p, tsel_rd_select_p;
u32 ca_tsel_wr_select_p, ca_tsel_wr_select_n;
- u32 tsel_idle_select_n, tsel_wr_select_n, tsel_rd_select_n;
+ u32 tsel_idle_select_n, tsel_wr_select_dq_n, tsel_rd_select_n;
u32 reg_value;
if (sdram_params->base.dramtype == LPDDR4) {
@@ -172,7 +172,7 @@ static void set_ds_odt(const struct chan_info *chan,
tsel_idle_select_p = PHY_DRV_ODT_HI_Z;
tsel_rd_select_n = PHY_DRV_ODT_240;
- tsel_wr_select_n = PHY_DRV_ODT_40;
+ tsel_wr_select_dq_n = PHY_DRV_ODT_40;
ca_tsel_wr_select_n = PHY_DRV_ODT_40;
tsel_idle_select_n = PHY_DRV_ODT_240;
} else if (sdram_params->base.dramtype == LPDDR3) {
@@ -182,7 +182,7 @@ static void set_ds_odt(const struct chan_info *chan,
tsel_idle_select_p = PHY_DRV_ODT_240;
tsel_rd_select_n = PHY_DRV_ODT_HI_Z;
- tsel_wr_select_n = PHY_DRV_ODT_34_3;
+ tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
ca_tsel_wr_select_n = PHY_DRV_ODT_48;
tsel_idle_select_n = PHY_DRV_ODT_HI_Z;
} else {
@@ -192,7 +192,7 @@ static void set_ds_odt(const struct chan_info *chan,
tsel_idle_select_p = PHY_DRV_ODT_240;
tsel_rd_select_n = PHY_DRV_ODT_240;
- tsel_wr_select_n = PHY_DRV_ODT_34_3;
+ tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
ca_tsel_wr_select_n = PHY_DRV_ODT_34_3;
tsel_idle_select_n = PHY_DRV_ODT_240;
}
@@ -211,7 +211,7 @@ static void set_ds_odt(const struct chan_info *chan,
* for write cycles for DQ/DM
*/
reg_value = tsel_rd_select_n | (tsel_rd_select_p << 0x4) |
- (tsel_wr_select_n << 8) | (tsel_wr_select_p << 12) |
+ (tsel_wr_select_dq_n << 8) | (tsel_wr_select_p << 12) |
(tsel_idle_select_n << 16) | (tsel_idle_select_p << 20);
clrsetbits_le32(&denali_phy[6], 0xffffff, reg_value);
clrsetbits_le32(&denali_phy[134], 0xffffff, reg_value);
@@ -251,7 +251,7 @@ static void set_ds_odt(const struct chan_info *chan,
/* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */
clrsetbits_le32(&denali_phy[924], 0xff,
- tsel_wr_select_n | (tsel_wr_select_p << 4));
+ tsel_wr_select_dq_n | (tsel_wr_select_p << 4));
clrsetbits_le32(&denali_phy[925], 0xff,
tsel_rd_select_n | (tsel_rd_select_p << 4));
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 30/92] ram: rk3399: s/tsel_wr_select_p/tsel_wr_select_dq_p
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Rename tsel_wr_select_p to tsel_wr_select_dq_p based
on the bsp code and associated datasheet.
No functionality change.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 7c05814f19..780b18fa17 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -160,14 +160,14 @@ static void set_ds_odt(const struct chan_info *chan,
u32 *denali_phy = chan->publ->denali_phy;
u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
- u32 tsel_idle_select_p, tsel_wr_select_p, tsel_rd_select_p;
+ u32 tsel_idle_select_p, tsel_wr_select_dq_p, tsel_rd_select_p;
u32 ca_tsel_wr_select_p, ca_tsel_wr_select_n;
u32 tsel_idle_select_n, tsel_wr_select_dq_n, tsel_rd_select_n;
u32 reg_value;
if (sdram_params->base.dramtype == LPDDR4) {
tsel_rd_select_p = PHY_DRV_ODT_HI_Z;
- tsel_wr_select_p = PHY_DRV_ODT_40;
+ tsel_wr_select_dq_p = PHY_DRV_ODT_40;
ca_tsel_wr_select_p = PHY_DRV_ODT_40;
tsel_idle_select_p = PHY_DRV_ODT_HI_Z;
@@ -177,7 +177,7 @@ static void set_ds_odt(const struct chan_info *chan,
tsel_idle_select_n = PHY_DRV_ODT_240;
} else if (sdram_params->base.dramtype == LPDDR3) {
tsel_rd_select_p = PHY_DRV_ODT_240;
- tsel_wr_select_p = PHY_DRV_ODT_34_3;
+ tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
ca_tsel_wr_select_p = PHY_DRV_ODT_48;
tsel_idle_select_p = PHY_DRV_ODT_240;
@@ -187,7 +187,7 @@ static void set_ds_odt(const struct chan_info *chan,
tsel_idle_select_n = PHY_DRV_ODT_HI_Z;
} else {
tsel_rd_select_p = PHY_DRV_ODT_240;
- tsel_wr_select_p = PHY_DRV_ODT_34_3;
+ tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
ca_tsel_wr_select_p = PHY_DRV_ODT_34_3;
tsel_idle_select_p = PHY_DRV_ODT_240;
@@ -211,7 +211,7 @@ static void set_ds_odt(const struct chan_info *chan,
* for write cycles for DQ/DM
*/
reg_value = tsel_rd_select_n | (tsel_rd_select_p << 0x4) |
- (tsel_wr_select_dq_n << 8) | (tsel_wr_select_p << 12) |
+ (tsel_wr_select_dq_n << 8) | (tsel_wr_select_dq_p << 12) |
(tsel_idle_select_n << 16) | (tsel_idle_select_p << 20);
clrsetbits_le32(&denali_phy[6], 0xffffff, reg_value);
clrsetbits_le32(&denali_phy[134], 0xffffff, reg_value);
@@ -251,7 +251,7 @@ static void set_ds_odt(const struct chan_info *chan,
/* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */
clrsetbits_le32(&denali_phy[924], 0xff,
- tsel_wr_select_dq_n | (tsel_wr_select_p << 4));
+ tsel_wr_select_dq_n | (tsel_wr_select_dq_p << 4));
clrsetbits_le32(&denali_phy[925], 0xff,
tsel_rd_select_n | (tsel_rd_select_p << 4));
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 30/92] ram: rk3399: s/tsel_wr_select_p/tsel_wr_select_dq_p
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
Rename tsel_wr_select_p to tsel_wr_select_dq_p based
on the bsp code and associated datasheet.
No functionality change.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 7c05814f19..780b18fa17 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -160,14 +160,14 @@ static void set_ds_odt(const struct chan_info *chan,
u32 *denali_phy = chan->publ->denali_phy;
u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
- u32 tsel_idle_select_p, tsel_wr_select_p, tsel_rd_select_p;
+ u32 tsel_idle_select_p, tsel_wr_select_dq_p, tsel_rd_select_p;
u32 ca_tsel_wr_select_p, ca_tsel_wr_select_n;
u32 tsel_idle_select_n, tsel_wr_select_dq_n, tsel_rd_select_n;
u32 reg_value;
if (sdram_params->base.dramtype == LPDDR4) {
tsel_rd_select_p = PHY_DRV_ODT_HI_Z;
- tsel_wr_select_p = PHY_DRV_ODT_40;
+ tsel_wr_select_dq_p = PHY_DRV_ODT_40;
ca_tsel_wr_select_p = PHY_DRV_ODT_40;
tsel_idle_select_p = PHY_DRV_ODT_HI_Z;
@@ -177,7 +177,7 @@ static void set_ds_odt(const struct chan_info *chan,
tsel_idle_select_n = PHY_DRV_ODT_240;
} else if (sdram_params->base.dramtype == LPDDR3) {
tsel_rd_select_p = PHY_DRV_ODT_240;
- tsel_wr_select_p = PHY_DRV_ODT_34_3;
+ tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
ca_tsel_wr_select_p = PHY_DRV_ODT_48;
tsel_idle_select_p = PHY_DRV_ODT_240;
@@ -187,7 +187,7 @@ static void set_ds_odt(const struct chan_info *chan,
tsel_idle_select_n = PHY_DRV_ODT_HI_Z;
} else {
tsel_rd_select_p = PHY_DRV_ODT_240;
- tsel_wr_select_p = PHY_DRV_ODT_34_3;
+ tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
ca_tsel_wr_select_p = PHY_DRV_ODT_34_3;
tsel_idle_select_p = PHY_DRV_ODT_240;
@@ -211,7 +211,7 @@ static void set_ds_odt(const struct chan_info *chan,
* for write cycles for DQ/DM
*/
reg_value = tsel_rd_select_n | (tsel_rd_select_p << 0x4) |
- (tsel_wr_select_dq_n << 8) | (tsel_wr_select_p << 12) |
+ (tsel_wr_select_dq_n << 8) | (tsel_wr_select_dq_p << 12) |
(tsel_idle_select_n << 16) | (tsel_idle_select_p << 20);
clrsetbits_le32(&denali_phy[6], 0xffffff, reg_value);
clrsetbits_le32(&denali_phy[134], 0xffffff, reg_value);
@@ -251,7 +251,7 @@ static void set_ds_odt(const struct chan_info *chan,
/* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */
clrsetbits_le32(&denali_phy[924], 0xff,
- tsel_wr_select_dq_n | (tsel_wr_select_p << 4));
+ tsel_wr_select_dq_n | (tsel_wr_select_dq_p << 4));
clrsetbits_le32(&denali_phy[925], 0xff,
tsel_rd_select_n | (tsel_rd_select_p << 4));
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 31/92] ram: rk3399: s/ca_tsel_wr_select_n/tsel_wr_select_ca_n
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Rename ca_tsel_wr_select_n to tsel_wr_select_ca_n based
on the bsp code and associated datasheet.
No functionality change.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 780b18fa17..bfae4e78a9 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -161,7 +161,7 @@ static void set_ds_odt(const struct chan_info *chan,
u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
u32 tsel_idle_select_p, tsel_wr_select_dq_p, tsel_rd_select_p;
- u32 ca_tsel_wr_select_p, ca_tsel_wr_select_n;
+ u32 ca_tsel_wr_select_p, tsel_wr_select_ca_n;
u32 tsel_idle_select_n, tsel_wr_select_dq_n, tsel_rd_select_n;
u32 reg_value;
@@ -173,7 +173,7 @@ static void set_ds_odt(const struct chan_info *chan,
tsel_rd_select_n = PHY_DRV_ODT_240;
tsel_wr_select_dq_n = PHY_DRV_ODT_40;
- ca_tsel_wr_select_n = PHY_DRV_ODT_40;
+ tsel_wr_select_ca_n = PHY_DRV_ODT_40;
tsel_idle_select_n = PHY_DRV_ODT_240;
} else if (sdram_params->base.dramtype == LPDDR3) {
tsel_rd_select_p = PHY_DRV_ODT_240;
@@ -183,7 +183,7 @@ static void set_ds_odt(const struct chan_info *chan,
tsel_rd_select_n = PHY_DRV_ODT_HI_Z;
tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
- ca_tsel_wr_select_n = PHY_DRV_ODT_48;
+ tsel_wr_select_ca_n = PHY_DRV_ODT_48;
tsel_idle_select_n = PHY_DRV_ODT_HI_Z;
} else {
tsel_rd_select_p = PHY_DRV_ODT_240;
@@ -193,7 +193,7 @@ static void set_ds_odt(const struct chan_info *chan,
tsel_rd_select_n = PHY_DRV_ODT_240;
tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
- ca_tsel_wr_select_n = PHY_DRV_ODT_34_3;
+ tsel_wr_select_ca_n = PHY_DRV_ODT_34_3;
tsel_idle_select_n = PHY_DRV_ODT_240;
}
@@ -229,7 +229,7 @@ static void set_ds_odt(const struct chan_info *chan,
clrsetbits_le32(&denali_phy[391], 0xffffff, reg_value);
/* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */
- reg_value = ca_tsel_wr_select_n | (ca_tsel_wr_select_p << 0x4);
+ reg_value = tsel_wr_select_ca_n | (ca_tsel_wr_select_p << 0x4);
clrsetbits_le32(&denali_phy[544], 0xff, reg_value);
clrsetbits_le32(&denali_phy[672], 0xff, reg_value);
clrsetbits_le32(&denali_phy[800], 0xff, reg_value);
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 31/92] ram: rk3399: s/ca_tsel_wr_select_n/tsel_wr_select_ca_n
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
Rename ca_tsel_wr_select_n to tsel_wr_select_ca_n based
on the bsp code and associated datasheet.
No functionality change.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 780b18fa17..bfae4e78a9 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -161,7 +161,7 @@ static void set_ds_odt(const struct chan_info *chan,
u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
u32 tsel_idle_select_p, tsel_wr_select_dq_p, tsel_rd_select_p;
- u32 ca_tsel_wr_select_p, ca_tsel_wr_select_n;
+ u32 ca_tsel_wr_select_p, tsel_wr_select_ca_n;
u32 tsel_idle_select_n, tsel_wr_select_dq_n, tsel_rd_select_n;
u32 reg_value;
@@ -173,7 +173,7 @@ static void set_ds_odt(const struct chan_info *chan,
tsel_rd_select_n = PHY_DRV_ODT_240;
tsel_wr_select_dq_n = PHY_DRV_ODT_40;
- ca_tsel_wr_select_n = PHY_DRV_ODT_40;
+ tsel_wr_select_ca_n = PHY_DRV_ODT_40;
tsel_idle_select_n = PHY_DRV_ODT_240;
} else if (sdram_params->base.dramtype == LPDDR3) {
tsel_rd_select_p = PHY_DRV_ODT_240;
@@ -183,7 +183,7 @@ static void set_ds_odt(const struct chan_info *chan,
tsel_rd_select_n = PHY_DRV_ODT_HI_Z;
tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
- ca_tsel_wr_select_n = PHY_DRV_ODT_48;
+ tsel_wr_select_ca_n = PHY_DRV_ODT_48;
tsel_idle_select_n = PHY_DRV_ODT_HI_Z;
} else {
tsel_rd_select_p = PHY_DRV_ODT_240;
@@ -193,7 +193,7 @@ static void set_ds_odt(const struct chan_info *chan,
tsel_rd_select_n = PHY_DRV_ODT_240;
tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
- ca_tsel_wr_select_n = PHY_DRV_ODT_34_3;
+ tsel_wr_select_ca_n = PHY_DRV_ODT_34_3;
tsel_idle_select_n = PHY_DRV_ODT_240;
}
@@ -229,7 +229,7 @@ static void set_ds_odt(const struct chan_info *chan,
clrsetbits_le32(&denali_phy[391], 0xffffff, reg_value);
/* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */
- reg_value = ca_tsel_wr_select_n | (ca_tsel_wr_select_p << 0x4);
+ reg_value = tsel_wr_select_ca_n | (ca_tsel_wr_select_p << 0x4);
clrsetbits_le32(&denali_phy[544], 0xff, reg_value);
clrsetbits_le32(&denali_phy[672], 0xff, reg_value);
clrsetbits_le32(&denali_phy[800], 0xff, reg_value);
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 32/92] ram: rk3399: s/ca_tsel_wr_select_p/tsel_wr_select_ca_p
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Rename ca_tsel_wr_select_p to tsel_wr_select_ca_p based
on the bsp code and associated datasheet.
No functionality change.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index bfae4e78a9..d868621c93 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -161,14 +161,14 @@ static void set_ds_odt(const struct chan_info *chan,
u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
u32 tsel_idle_select_p, tsel_wr_select_dq_p, tsel_rd_select_p;
- u32 ca_tsel_wr_select_p, tsel_wr_select_ca_n;
+ u32 tsel_wr_select_ca_p, tsel_wr_select_ca_n;
u32 tsel_idle_select_n, tsel_wr_select_dq_n, tsel_rd_select_n;
u32 reg_value;
if (sdram_params->base.dramtype == LPDDR4) {
tsel_rd_select_p = PHY_DRV_ODT_HI_Z;
tsel_wr_select_dq_p = PHY_DRV_ODT_40;
- ca_tsel_wr_select_p = PHY_DRV_ODT_40;
+ tsel_wr_select_ca_p = PHY_DRV_ODT_40;
tsel_idle_select_p = PHY_DRV_ODT_HI_Z;
tsel_rd_select_n = PHY_DRV_ODT_240;
@@ -178,7 +178,7 @@ static void set_ds_odt(const struct chan_info *chan,
} else if (sdram_params->base.dramtype == LPDDR3) {
tsel_rd_select_p = PHY_DRV_ODT_240;
tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
- ca_tsel_wr_select_p = PHY_DRV_ODT_48;
+ tsel_wr_select_ca_p = PHY_DRV_ODT_48;
tsel_idle_select_p = PHY_DRV_ODT_240;
tsel_rd_select_n = PHY_DRV_ODT_HI_Z;
@@ -188,7 +188,7 @@ static void set_ds_odt(const struct chan_info *chan,
} else {
tsel_rd_select_p = PHY_DRV_ODT_240;
tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
- ca_tsel_wr_select_p = PHY_DRV_ODT_34_3;
+ tsel_wr_select_ca_p = PHY_DRV_ODT_34_3;
tsel_idle_select_p = PHY_DRV_ODT_240;
tsel_rd_select_n = PHY_DRV_ODT_240;
@@ -229,7 +229,7 @@ static void set_ds_odt(const struct chan_info *chan,
clrsetbits_le32(&denali_phy[391], 0xffffff, reg_value);
/* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */
- reg_value = tsel_wr_select_ca_n | (ca_tsel_wr_select_p << 0x4);
+ reg_value = tsel_wr_select_ca_n | (tsel_wr_select_ca_p << 0x4);
clrsetbits_le32(&denali_phy[544], 0xff, reg_value);
clrsetbits_le32(&denali_phy[672], 0xff, reg_value);
clrsetbits_le32(&denali_phy[800], 0xff, reg_value);
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 32/92] ram: rk3399: s/ca_tsel_wr_select_p/tsel_wr_select_ca_p
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
Rename ca_tsel_wr_select_p to tsel_wr_select_ca_p based
on the bsp code and associated datasheet.
No functionality change.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index bfae4e78a9..d868621c93 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -161,14 +161,14 @@ static void set_ds_odt(const struct chan_info *chan,
u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
u32 tsel_idle_select_p, tsel_wr_select_dq_p, tsel_rd_select_p;
- u32 ca_tsel_wr_select_p, tsel_wr_select_ca_n;
+ u32 tsel_wr_select_ca_p, tsel_wr_select_ca_n;
u32 tsel_idle_select_n, tsel_wr_select_dq_n, tsel_rd_select_n;
u32 reg_value;
if (sdram_params->base.dramtype == LPDDR4) {
tsel_rd_select_p = PHY_DRV_ODT_HI_Z;
tsel_wr_select_dq_p = PHY_DRV_ODT_40;
- ca_tsel_wr_select_p = PHY_DRV_ODT_40;
+ tsel_wr_select_ca_p = PHY_DRV_ODT_40;
tsel_idle_select_p = PHY_DRV_ODT_HI_Z;
tsel_rd_select_n = PHY_DRV_ODT_240;
@@ -178,7 +178,7 @@ static void set_ds_odt(const struct chan_info *chan,
} else if (sdram_params->base.dramtype == LPDDR3) {
tsel_rd_select_p = PHY_DRV_ODT_240;
tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
- ca_tsel_wr_select_p = PHY_DRV_ODT_48;
+ tsel_wr_select_ca_p = PHY_DRV_ODT_48;
tsel_idle_select_p = PHY_DRV_ODT_240;
tsel_rd_select_n = PHY_DRV_ODT_HI_Z;
@@ -188,7 +188,7 @@ static void set_ds_odt(const struct chan_info *chan,
} else {
tsel_rd_select_p = PHY_DRV_ODT_240;
tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
- ca_tsel_wr_select_p = PHY_DRV_ODT_34_3;
+ tsel_wr_select_ca_p = PHY_DRV_ODT_34_3;
tsel_idle_select_p = PHY_DRV_ODT_240;
tsel_rd_select_n = PHY_DRV_ODT_240;
@@ -229,7 +229,7 @@ static void set_ds_odt(const struct chan_info *chan,
clrsetbits_le32(&denali_phy[391], 0xffffff, reg_value);
/* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */
- reg_value = tsel_wr_select_ca_n | (ca_tsel_wr_select_p << 0x4);
+ reg_value = tsel_wr_select_ca_n | (tsel_wr_select_ca_p << 0x4);
clrsetbits_le32(&denali_phy[544], 0xff, reg_value);
clrsetbits_le32(&denali_phy[672], 0xff, reg_value);
clrsetbits_le32(&denali_phy[800], 0xff, reg_value);
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 33/92] ram: rk3399: Order tsel variables
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Order tsel* variable declarations and assignment in proper
and meaningful way.
No functionality change.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 37 +++++++++++++++++------------
1 file changed, 22 insertions(+), 15 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index d868621c93..e3945feca3 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -160,41 +160,48 @@ static void set_ds_odt(const struct chan_info *chan,
u32 *denali_phy = chan->publ->denali_phy;
u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
- u32 tsel_idle_select_p, tsel_wr_select_dq_p, tsel_rd_select_p;
- u32 tsel_wr_select_ca_p, tsel_wr_select_ca_n;
- u32 tsel_idle_select_n, tsel_wr_select_dq_n, tsel_rd_select_n;
+ u32 tsel_idle_select_p, tsel_rd_select_p;
+ u32 tsel_idle_select_n, tsel_rd_select_n;
+ u32 tsel_wr_select_dq_p, tsel_wr_select_ca_p;
+ u32 tsel_wr_select_dq_n, tsel_wr_select_ca_n;
u32 reg_value;
if (sdram_params->base.dramtype == LPDDR4) {
tsel_rd_select_p = PHY_DRV_ODT_HI_Z;
- tsel_wr_select_dq_p = PHY_DRV_ODT_40;
- tsel_wr_select_ca_p = PHY_DRV_ODT_40;
+ tsel_rd_select_n = PHY_DRV_ODT_240;
+
tsel_idle_select_p = PHY_DRV_ODT_HI_Z;
+ tsel_idle_select_n = PHY_DRV_ODT_240;
- tsel_rd_select_n = PHY_DRV_ODT_240;
+ tsel_wr_select_dq_p = PHY_DRV_ODT_40;
tsel_wr_select_dq_n = PHY_DRV_ODT_40;
+
+ tsel_wr_select_ca_p = PHY_DRV_ODT_40;
tsel_wr_select_ca_n = PHY_DRV_ODT_40;
- tsel_idle_select_n = PHY_DRV_ODT_240;
} else if (sdram_params->base.dramtype == LPDDR3) {
tsel_rd_select_p = PHY_DRV_ODT_240;
- tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
- tsel_wr_select_ca_p = PHY_DRV_ODT_48;
+ tsel_rd_select_n = PHY_DRV_ODT_HI_Z;
+
tsel_idle_select_p = PHY_DRV_ODT_240;
+ tsel_idle_select_n = PHY_DRV_ODT_HI_Z;
- tsel_rd_select_n = PHY_DRV_ODT_HI_Z;
+ tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
+
+ tsel_wr_select_ca_p = PHY_DRV_ODT_48;
tsel_wr_select_ca_n = PHY_DRV_ODT_48;
- tsel_idle_select_n = PHY_DRV_ODT_HI_Z;
} else {
tsel_rd_select_p = PHY_DRV_ODT_240;
- tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
- tsel_wr_select_ca_p = PHY_DRV_ODT_34_3;
+ tsel_rd_select_n = PHY_DRV_ODT_240;
+
tsel_idle_select_p = PHY_DRV_ODT_240;
+ tsel_idle_select_n = PHY_DRV_ODT_240;
- tsel_rd_select_n = PHY_DRV_ODT_240;
+ tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
+
+ tsel_wr_select_ca_p = PHY_DRV_ODT_34_3;
tsel_wr_select_ca_n = PHY_DRV_ODT_34_3;
- tsel_idle_select_n = PHY_DRV_ODT_240;
}
if (sdram_params->base.odt == 1)
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 33/92] ram: rk3399: Order tsel variables
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
Order tsel* variable declarations and assignment in proper
and meaningful way.
No functionality change.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 37 +++++++++++++++++------------
1 file changed, 22 insertions(+), 15 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index d868621c93..e3945feca3 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -160,41 +160,48 @@ static void set_ds_odt(const struct chan_info *chan,
u32 *denali_phy = chan->publ->denali_phy;
u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
- u32 tsel_idle_select_p, tsel_wr_select_dq_p, tsel_rd_select_p;
- u32 tsel_wr_select_ca_p, tsel_wr_select_ca_n;
- u32 tsel_idle_select_n, tsel_wr_select_dq_n, tsel_rd_select_n;
+ u32 tsel_idle_select_p, tsel_rd_select_p;
+ u32 tsel_idle_select_n, tsel_rd_select_n;
+ u32 tsel_wr_select_dq_p, tsel_wr_select_ca_p;
+ u32 tsel_wr_select_dq_n, tsel_wr_select_ca_n;
u32 reg_value;
if (sdram_params->base.dramtype == LPDDR4) {
tsel_rd_select_p = PHY_DRV_ODT_HI_Z;
- tsel_wr_select_dq_p = PHY_DRV_ODT_40;
- tsel_wr_select_ca_p = PHY_DRV_ODT_40;
+ tsel_rd_select_n = PHY_DRV_ODT_240;
+
tsel_idle_select_p = PHY_DRV_ODT_HI_Z;
+ tsel_idle_select_n = PHY_DRV_ODT_240;
- tsel_rd_select_n = PHY_DRV_ODT_240;
+ tsel_wr_select_dq_p = PHY_DRV_ODT_40;
tsel_wr_select_dq_n = PHY_DRV_ODT_40;
+
+ tsel_wr_select_ca_p = PHY_DRV_ODT_40;
tsel_wr_select_ca_n = PHY_DRV_ODT_40;
- tsel_idle_select_n = PHY_DRV_ODT_240;
} else if (sdram_params->base.dramtype == LPDDR3) {
tsel_rd_select_p = PHY_DRV_ODT_240;
- tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
- tsel_wr_select_ca_p = PHY_DRV_ODT_48;
+ tsel_rd_select_n = PHY_DRV_ODT_HI_Z;
+
tsel_idle_select_p = PHY_DRV_ODT_240;
+ tsel_idle_select_n = PHY_DRV_ODT_HI_Z;
- tsel_rd_select_n = PHY_DRV_ODT_HI_Z;
+ tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
+
+ tsel_wr_select_ca_p = PHY_DRV_ODT_48;
tsel_wr_select_ca_n = PHY_DRV_ODT_48;
- tsel_idle_select_n = PHY_DRV_ODT_HI_Z;
} else {
tsel_rd_select_p = PHY_DRV_ODT_240;
- tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
- tsel_wr_select_ca_p = PHY_DRV_ODT_34_3;
+ tsel_rd_select_n = PHY_DRV_ODT_240;
+
tsel_idle_select_p = PHY_DRV_ODT_240;
+ tsel_idle_select_n = PHY_DRV_ODT_240;
- tsel_rd_select_n = PHY_DRV_ODT_240;
+ tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
+
+ tsel_wr_select_ca_p = PHY_DRV_ODT_34_3;
tsel_wr_select_ca_n = PHY_DRV_ODT_34_3;
- tsel_idle_select_n = PHY_DRV_ODT_240;
}
if (sdram_params->base.odt == 1)
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 34/92] ram: rk3399: Add phy pctrl reset support
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Add support for phy pctrl reset support for both channel 0, 1.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index e3945feca3..bbf56f29ae 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -35,6 +35,10 @@
#define PHY_DRV_ODT_40 0xe
#define PHY_DRV_ODT_34_3 0xf
+#define CRU_SFTRST_DDR_CTRL(ch, n) ((0x1 << (8 + 16 + (ch) * 4)) | \
+ ((n) << (8 + (ch) * 4)))
+#define CRU_SFTRST_DDR_PHY(ch, n) ((0x1 << (9 + 16 + (ch) * 4)) | \
+ ((n) << (9 + (ch) * 4)))
struct chan_info {
struct rk3399_ddr_pctl_regs *pctl;
struct rk3399_ddr_pi_regs *pi;
@@ -79,6 +83,29 @@ static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
}
}
+static void rkclk_ddr_reset(struct rk3399_cru *cru, u32 channel, u32 ctl,
+ u32 phy)
+{
+ channel &= 0x1;
+ ctl &= 0x1;
+ phy &= 0x1;
+ writel(CRU_SFTRST_DDR_CTRL(channel, ctl) |
+ CRU_SFTRST_DDR_PHY(channel, phy),
+ &cru->softrst_con[4]);
+}
+
+static void phy_pctrl_reset(struct rk3399_cru *cru, u32 channel)
+{
+ rkclk_ddr_reset(cru, channel, 1, 1);
+ udelay(10);
+
+ rkclk_ddr_reset(cru, channel, 1, 0);
+ udelay(10);
+
+ rkclk_ddr_reset(cru, channel, 0, 0);
+ udelay(10);
+}
+
static void phy_dll_bypass_set(struct rk3399_ddr_publ_regs *ddr_publ_regs,
u32 freq)
{
@@ -1126,6 +1153,7 @@ static int sdram_init(struct dram_info *dram,
{
unsigned char dramtype = sdram_params->base.dramtype;
unsigned int ddr_freq = sdram_params->base.ddr_freq;
+ struct rk3399_cru *cru = dram->cru;
int channel;
int ret;
@@ -1142,6 +1170,7 @@ static int sdram_init(struct dram_info *dram,
const struct chan_info *chan = &dram->chan[channel];
struct rk3399_ddr_publ_regs *publ = chan->publ;
+ phy_pctrl_reset(cru, channel);
phy_dll_bypass_set(publ, ddr_freq);
if (channel >= sdram_params->base.num_channels)
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 34/92] ram: rk3399: Add phy pctrl reset support
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
Add support for phy pctrl reset support for both channel 0, 1.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index e3945feca3..bbf56f29ae 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -35,6 +35,10 @@
#define PHY_DRV_ODT_40 0xe
#define PHY_DRV_ODT_34_3 0xf
+#define CRU_SFTRST_DDR_CTRL(ch, n) ((0x1 << (8 + 16 + (ch) * 4)) | \
+ ((n) << (8 + (ch) * 4)))
+#define CRU_SFTRST_DDR_PHY(ch, n) ((0x1 << (9 + 16 + (ch) * 4)) | \
+ ((n) << (9 + (ch) * 4)))
struct chan_info {
struct rk3399_ddr_pctl_regs *pctl;
struct rk3399_ddr_pi_regs *pi;
@@ -79,6 +83,29 @@ static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
}
}
+static void rkclk_ddr_reset(struct rk3399_cru *cru, u32 channel, u32 ctl,
+ u32 phy)
+{
+ channel &= 0x1;
+ ctl &= 0x1;
+ phy &= 0x1;
+ writel(CRU_SFTRST_DDR_CTRL(channel, ctl) |
+ CRU_SFTRST_DDR_PHY(channel, phy),
+ &cru->softrst_con[4]);
+}
+
+static void phy_pctrl_reset(struct rk3399_cru *cru, u32 channel)
+{
+ rkclk_ddr_reset(cru, channel, 1, 1);
+ udelay(10);
+
+ rkclk_ddr_reset(cru, channel, 1, 0);
+ udelay(10);
+
+ rkclk_ddr_reset(cru, channel, 0, 0);
+ udelay(10);
+}
+
static void phy_dll_bypass_set(struct rk3399_ddr_publ_regs *ddr_publ_regs,
u32 freq)
{
@@ -1126,6 +1153,7 @@ static int sdram_init(struct dram_info *dram,
{
unsigned char dramtype = sdram_params->base.dramtype;
unsigned int ddr_freq = sdram_params->base.ddr_freq;
+ struct rk3399_cru *cru = dram->cru;
int channel;
int ret;
@@ -1142,6 +1170,7 @@ static int sdram_init(struct dram_info *dram,
const struct chan_info *chan = &dram->chan[channel];
struct rk3399_ddr_publ_regs *publ = chan->publ;
+ phy_pctrl_reset(cru, channel);
phy_dll_bypass_set(publ, ddr_freq);
if (channel >= sdram_params->base.num_channels)
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 35/92] ram: rk3399: Move pwrup_srefresh_exit to dram_info
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Add pwrup_srefresh_exit to be part of dram_info so-that
the it can help to support pwrup_srefresh_exit in individual
channels while starting pctl in future.
No functionality change.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 13 +++++++------
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index bbf56f29ae..7ca76d304f 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -49,6 +49,7 @@ struct chan_info {
struct dram_info {
#if defined(CONFIG_TPL_BUILD) || \
(!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
+ u32 pwrup_srefresh_exit;
struct chan_info chan[2];
struct clk ddr_clk;
struct rk3399_cru *cru;
@@ -487,8 +488,8 @@ static int phy_io_config(const struct chan_info *chan,
return 0;
}
-static int pctl_cfg(const struct chan_info *chan, u32 channel,
- const struct rk3399_sdram_params *sdram_params)
+static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
+ u32 channel, const struct rk3399_sdram_params *sdram_params)
{
u32 *denali_ctl = chan->pctl->denali_ctl;
u32 *denali_pi = chan->pi->denali_pi;
@@ -496,7 +497,6 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel,
const u32 *params_ctl = sdram_params->pctl_regs.denali_ctl;
const u32 *params_phy = sdram_params->phy_regs.denali_phy;
u32 tmp, tmp1, tmp2;
- u32 pwrup_srefresh_exit;
int ret;
const ulong timeout_ms = 200;
@@ -516,7 +516,8 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel,
writel(sdram_params->phy_regs.denali_phy[911], &denali_phy[911]);
writel(sdram_params->phy_regs.denali_phy[912], &denali_phy[912]);
- pwrup_srefresh_exit = readl(&denali_ctl[68]) & PWRUP_SREFRESH_EXIT;
+ dram->pwrup_srefresh_exit = readl(&denali_ctl[68]) &
+ PWRUP_SREFRESH_EXIT;
clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT);
/* PHY_DLL_RST_EN */
@@ -592,7 +593,7 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel,
debug("DRAM (%s): phy locked after %ld ms\n", __func__, get_timer(tmp));
clrsetbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT,
- pwrup_srefresh_exit);
+ dram->pwrup_srefresh_exit);
return 0;
}
@@ -1176,7 +1177,7 @@ static int sdram_init(struct dram_info *dram,
if (channel >= sdram_params->base.num_channels)
continue;
- ret = pctl_cfg(chan, channel, sdram_params);
+ ret = pctl_cfg(dram, chan, channel, sdram_params);
if (ret < 0) {
printf("%s: pctl config failed\n", __func__);
return ret;
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 35/92] ram: rk3399: Move pwrup_srefresh_exit to dram_info
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
Add pwrup_srefresh_exit to be part of dram_info so-that
the it can help to support pwrup_srefresh_exit in individual
channels while starting pctl in future.
No functionality change.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 13 +++++++------
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index bbf56f29ae..7ca76d304f 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -49,6 +49,7 @@ struct chan_info {
struct dram_info {
#if defined(CONFIG_TPL_BUILD) || \
(!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
+ u32 pwrup_srefresh_exit;
struct chan_info chan[2];
struct clk ddr_clk;
struct rk3399_cru *cru;
@@ -487,8 +488,8 @@ static int phy_io_config(const struct chan_info *chan,
return 0;
}
-static int pctl_cfg(const struct chan_info *chan, u32 channel,
- const struct rk3399_sdram_params *sdram_params)
+static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
+ u32 channel, const struct rk3399_sdram_params *sdram_params)
{
u32 *denali_ctl = chan->pctl->denali_ctl;
u32 *denali_pi = chan->pi->denali_pi;
@@ -496,7 +497,6 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel,
const u32 *params_ctl = sdram_params->pctl_regs.denali_ctl;
const u32 *params_phy = sdram_params->phy_regs.denali_phy;
u32 tmp, tmp1, tmp2;
- u32 pwrup_srefresh_exit;
int ret;
const ulong timeout_ms = 200;
@@ -516,7 +516,8 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel,
writel(sdram_params->phy_regs.denali_phy[911], &denali_phy[911]);
writel(sdram_params->phy_regs.denali_phy[912], &denali_phy[912]);
- pwrup_srefresh_exit = readl(&denali_ctl[68]) & PWRUP_SREFRESH_EXIT;
+ dram->pwrup_srefresh_exit = readl(&denali_ctl[68]) &
+ PWRUP_SREFRESH_EXIT;
clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT);
/* PHY_DLL_RST_EN */
@@ -592,7 +593,7 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel,
debug("DRAM (%s): phy locked after %ld ms\n", __func__, get_timer(tmp));
clrsetbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT,
- pwrup_srefresh_exit);
+ dram->pwrup_srefresh_exit);
return 0;
}
@@ -1176,7 +1177,7 @@ static int sdram_init(struct dram_info *dram,
if (channel >= sdram_params->base.num_channels)
continue;
- ret = pctl_cfg(chan, channel, sdram_params);
+ ret = pctl_cfg(dram, chan, channel, sdram_params);
if (ret < 0) {
printf("%s: pctl config failed\n", __func__);
return ret;
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 36/92] ram: rk3399: Add pctl start support
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Add support for pctl start for both channel 0, 1 control
and phy registers.
This would also handle pwrup_srefresh_exit init based
on the channel number.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 79 +++++++++++++++++++++--------
1 file changed, 59 insertions(+), 20 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 7ca76d304f..220197a42e 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -49,10 +49,11 @@ struct chan_info {
struct dram_info {
#if defined(CONFIG_TPL_BUILD) || \
(!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
- u32 pwrup_srefresh_exit;
+ u32 pwrup_srefresh_exit[2];
struct chan_info chan[2];
struct clk ddr_clk;
struct rk3399_cru *cru;
+ struct rk3399_grf_regs *grf;
struct rk3399_pmucru *pmucru;
struct rk3399_pmusgrf_regs *pmusgrf;
struct rk3399_ddr_cic_regs *cic;
@@ -73,6 +74,11 @@ struct rockchip_dmc_plat {
struct regmap *map;
};
+static void *get_ddrc0_con(struct dram_info *dram, u8 channel)
+{
+ return (channel == 0) ? &dram->grf->ddrc0_con0 : &dram->grf->ddrc0_con1;
+}
+
static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
{
int i;
@@ -328,6 +334,52 @@ static void set_ds_odt(const struct chan_info *chan,
clrsetbits_le32(&denali_phy[930], 0x1 << 17, reg_value);
}
+static void pctl_start(struct dram_info *dram,
+ const struct rk3399_sdram_params *sdram_params,
+ u8 channel)
+{
+ const struct chan_info *chan = &dram->chan[channel];
+ u32 *ddrc0_con = get_ddrc0_con(dram, channel);
+ u32 *denali_ctl, *denali_phy;
+ u32 count = 0;
+ u32 byte, tmp;
+
+ denali_ctl = chan->pctl->denali_ctl;
+ denali_phy = chan->publ->denali_phy;
+
+ writel(0x01000000, &ddrc0_con);
+
+ clrsetbits_le32(&denali_phy[957], 0x3 << 24, 0x2 << 24);
+
+ while (!(readl(&denali_ctl[203]) & (1 << 3))) {
+ if (count > 1000) {
+ printf("%s: Failed to init pctl for channel %d\n",
+ __func__, channel);
+ while (1)
+ ;
+ }
+
+ udelay(1);
+ count++;
+ }
+
+ writel(0x01000100, &ddrc0_con);
+
+ for (byte = 0; byte < 4; byte++) {
+ tmp = 0x820;
+ writel((tmp << 16) | tmp, &denali_phy[53 + (128 * byte)]);
+ writel((tmp << 16) | tmp, &denali_phy[54 + (128 * byte)]);
+ writel((tmp << 16) | tmp, &denali_phy[55 + (128 * byte)]);
+ writel((tmp << 16) | tmp, &denali_phy[56 + (128 * byte)]);
+ writel((tmp << 16) | tmp, &denali_phy[57 + (128 * byte)]);
+
+ clrsetbits_le32(&denali_phy[58 + (128 * byte)], 0xffff, tmp);
+ }
+
+ clrsetbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT,
+ dram->pwrup_srefresh_exit[channel]);
+}
+
static int phy_io_config(const struct chan_info *chan,
const struct rk3399_sdram_params *sdram_params)
{
@@ -498,7 +550,6 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
const u32 *params_phy = sdram_params->phy_regs.denali_phy;
u32 tmp, tmp1, tmp2;
int ret;
- const ulong timeout_ms = 200;
/*
* work around controller bug:
@@ -516,8 +567,8 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
writel(sdram_params->phy_regs.denali_phy[911], &denali_phy[911]);
writel(sdram_params->phy_regs.denali_phy[912], &denali_phy[912]);
- dram->pwrup_srefresh_exit = readl(&denali_ctl[68]) &
- PWRUP_SREFRESH_EXIT;
+ dram->pwrup_srefresh_exit[channel] = readl(&denali_ctl[68]) &
+ PWRUP_SREFRESH_EXIT;
clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT);
/* PHY_DLL_RST_EN */
@@ -578,22 +629,6 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
if (ret)
return ret;
- /* PHY_DLL_RST_EN */
- clrsetbits_le32(&denali_phy[957], 0x3 << 24, 0x2 << 24);
-
- /* Waiting for PHY and DRAM init complete */
- tmp = get_timer(0);
- do {
- if (get_timer(tmp) > timeout_ms) {
- pr_err("DRAM (%s): phy failed to lock within %ld ms\n",
- __func__, timeout_ms);
- return -ETIME;
- }
- } while (!(readl(&denali_ctl[203]) & (1 << 3)));
- debug("DRAM (%s): phy locked after %ld ms\n", __func__, get_timer(tmp));
-
- clrsetbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT,
- dram->pwrup_srefresh_exit);
return 0;
}
@@ -1183,6 +1218,9 @@ static int sdram_init(struct dram_info *dram,
return ret;
}
+ /* start to trigger initialization */
+ pctl_start(dram, sdram_params, channel);
+
/* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */
if (dramtype == LPDDR3)
udelay(10);
@@ -1260,6 +1298,7 @@ static int rk3399_dmc_init(struct udevice *dev)
#endif
priv->cic = syscon_get_first_range(ROCKCHIP_SYSCON_CIC);
+ priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
priv->pmusgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
priv->pmucru = rockchip_get_pmucru();
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 36/92] ram: rk3399: Add pctl start support
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
Add support for pctl start for both channel 0, 1 control
and phy registers.
This would also handle pwrup_srefresh_exit init based
on the channel number.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 79 +++++++++++++++++++++--------
1 file changed, 59 insertions(+), 20 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 7ca76d304f..220197a42e 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -49,10 +49,11 @@ struct chan_info {
struct dram_info {
#if defined(CONFIG_TPL_BUILD) || \
(!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
- u32 pwrup_srefresh_exit;
+ u32 pwrup_srefresh_exit[2];
struct chan_info chan[2];
struct clk ddr_clk;
struct rk3399_cru *cru;
+ struct rk3399_grf_regs *grf;
struct rk3399_pmucru *pmucru;
struct rk3399_pmusgrf_regs *pmusgrf;
struct rk3399_ddr_cic_regs *cic;
@@ -73,6 +74,11 @@ struct rockchip_dmc_plat {
struct regmap *map;
};
+static void *get_ddrc0_con(struct dram_info *dram, u8 channel)
+{
+ return (channel == 0) ? &dram->grf->ddrc0_con0 : &dram->grf->ddrc0_con1;
+}
+
static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
{
int i;
@@ -328,6 +334,52 @@ static void set_ds_odt(const struct chan_info *chan,
clrsetbits_le32(&denali_phy[930], 0x1 << 17, reg_value);
}
+static void pctl_start(struct dram_info *dram,
+ const struct rk3399_sdram_params *sdram_params,
+ u8 channel)
+{
+ const struct chan_info *chan = &dram->chan[channel];
+ u32 *ddrc0_con = get_ddrc0_con(dram, channel);
+ u32 *denali_ctl, *denali_phy;
+ u32 count = 0;
+ u32 byte, tmp;
+
+ denali_ctl = chan->pctl->denali_ctl;
+ denali_phy = chan->publ->denali_phy;
+
+ writel(0x01000000, &ddrc0_con);
+
+ clrsetbits_le32(&denali_phy[957], 0x3 << 24, 0x2 << 24);
+
+ while (!(readl(&denali_ctl[203]) & (1 << 3))) {
+ if (count > 1000) {
+ printf("%s: Failed to init pctl for channel %d\n",
+ __func__, channel);
+ while (1)
+ ;
+ }
+
+ udelay(1);
+ count++;
+ }
+
+ writel(0x01000100, &ddrc0_con);
+
+ for (byte = 0; byte < 4; byte++) {
+ tmp = 0x820;
+ writel((tmp << 16) | tmp, &denali_phy[53 + (128 * byte)]);
+ writel((tmp << 16) | tmp, &denali_phy[54 + (128 * byte)]);
+ writel((tmp << 16) | tmp, &denali_phy[55 + (128 * byte)]);
+ writel((tmp << 16) | tmp, &denali_phy[56 + (128 * byte)]);
+ writel((tmp << 16) | tmp, &denali_phy[57 + (128 * byte)]);
+
+ clrsetbits_le32(&denali_phy[58 + (128 * byte)], 0xffff, tmp);
+ }
+
+ clrsetbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT,
+ dram->pwrup_srefresh_exit[channel]);
+}
+
static int phy_io_config(const struct chan_info *chan,
const struct rk3399_sdram_params *sdram_params)
{
@@ -498,7 +550,6 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
const u32 *params_phy = sdram_params->phy_regs.denali_phy;
u32 tmp, tmp1, tmp2;
int ret;
- const ulong timeout_ms = 200;
/*
* work around controller bug:
@@ -516,8 +567,8 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
writel(sdram_params->phy_regs.denali_phy[911], &denali_phy[911]);
writel(sdram_params->phy_regs.denali_phy[912], &denali_phy[912]);
- dram->pwrup_srefresh_exit = readl(&denali_ctl[68]) &
- PWRUP_SREFRESH_EXIT;
+ dram->pwrup_srefresh_exit[channel] = readl(&denali_ctl[68]) &
+ PWRUP_SREFRESH_EXIT;
clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT);
/* PHY_DLL_RST_EN */
@@ -578,22 +629,6 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
if (ret)
return ret;
- /* PHY_DLL_RST_EN */
- clrsetbits_le32(&denali_phy[957], 0x3 << 24, 0x2 << 24);
-
- /* Waiting for PHY and DRAM init complete */
- tmp = get_timer(0);
- do {
- if (get_timer(tmp) > timeout_ms) {
- pr_err("DRAM (%s): phy failed to lock within %ld ms\n",
- __func__, timeout_ms);
- return -ETIME;
- }
- } while (!(readl(&denali_ctl[203]) & (1 << 3)));
- debug("DRAM (%s): phy locked after %ld ms\n", __func__, get_timer(tmp));
-
- clrsetbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT,
- dram->pwrup_srefresh_exit);
return 0;
}
@@ -1183,6 +1218,9 @@ static int sdram_init(struct dram_info *dram,
return ret;
}
+ /* start to trigger initialization */
+ pctl_start(dram, sdram_params, channel);
+
/* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */
if (dramtype == LPDDR3)
udelay(10);
@@ -1260,6 +1298,7 @@ static int rk3399_dmc_init(struct udevice *dev)
#endif
priv->cic = syscon_get_first_range(ROCKCHIP_SYSCON_CIC);
+ priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
priv->pmusgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
priv->pmucru = rockchip_get_pmucru();
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 37/92] ram: rockchip: rk3399: Add cap_info structure
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Group common ddr attributes like
- rank
- col
- bk
- bw
- dbw
- row_3_4
- cs0_row
- cs1_row
- ddrconfig
into a common cap_info structure for more code readability and extend
if possible based on the new features.
No functionality change.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
.../include/asm/arch-rockchip/sdram_rk3399.h | 6 +-
drivers/ram/rockchip/sdram_rk3399.c | 71 ++++++++++---------
2 files changed, 41 insertions(+), 36 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
index a191d242f8..67044f53e5 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
@@ -96,7 +96,7 @@ struct rk3399_ddr_cic_regs {
/* DENALI_CTL_274 */
#define MEM_RST_VALID 1
-struct rk3399_sdram_channel {
+struct sdram_cap_info {
unsigned int rank;
/* dram column number, 0 means this channel is invalid */
unsigned int col;
@@ -114,6 +114,10 @@ struct rk3399_sdram_channel {
unsigned int cs0_row;
unsigned int cs1_row;
unsigned int ddrconfig;
+};
+
+struct rk3399_sdram_channel {
+ struct sdram_cap_info cap_info;
struct rk3399_msch_timings noc_timings;
};
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 220197a42e..1acf9efe9c 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -156,35 +156,36 @@ static void set_memory_map(const struct chan_info *chan, u32 channel,
u32 row;
/* Get row number from ddrconfig setting */
- if (sdram_ch->ddrconfig < 2 || sdram_ch->ddrconfig == 4)
+ if (sdram_ch->cap_info.ddrconfig < 2 ||
+ sdram_ch->cap_info.ddrconfig == 4)
row = 16;
- else if (sdram_ch->ddrconfig == 3)
+ else if (sdram_ch->cap_info.ddrconfig == 3)
row = 14;
else
row = 15;
- cs_map = (sdram_ch->rank > 1) ? 3 : 1;
- reduc = (sdram_ch->bw == 2) ? 0 : 1;
+ cs_map = (sdram_ch->cap_info.rank > 1) ? 3 : 1;
+ reduc = (sdram_ch->cap_info.bw == 2) ? 0 : 1;
/* Set the dram configuration to ctrl */
- clrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->col));
+ clrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->cap_info.col));
clrsetbits_le32(&denali_ctl[190], (0x3 << 16) | (0x7 << 24),
- ((3 - sdram_ch->bk) << 16) |
+ ((3 - sdram_ch->cap_info.bk) << 16) |
((16 - row) << 24));
clrsetbits_le32(&denali_ctl[196], 0x3 | (1 << 16),
cs_map | (reduc << 16));
/* PI_199 PI_COL_DIFF:RW:0:4 */
- clrsetbits_le32(&denali_pi[199], 0xF, (12 - sdram_ch->col));
+ clrsetbits_le32(&denali_pi[199], 0xF, (12 - sdram_ch->cap_info.col));
/* PI_155 PI_ROW_DIFF:RW:24:3 PI_BANK_DIFF:RW:16:2 */
clrsetbits_le32(&denali_pi[155], (0x3 << 16) | (0x7 << 24),
- ((3 - sdram_ch->bk) << 16) |
+ ((3 - sdram_ch->cap_info.bk) << 16) |
((16 - row) << 24));
/* PI_41 PI_CS_MAP:RW:24:4 */
clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24);
- if (sdram_ch->rank == 1 && sdram_params->base.dramtype == DDR3)
+ if (sdram_ch->cap_info.rank == 1 && sdram_params->base.dramtype == DDR3)
writel(0x2EC7FFFF, &denali_pi[34]);
}
@@ -686,7 +687,7 @@ static int data_training_ca(const struct chan_info *chan, u32 channel,
u32 *denali_phy = chan->publ->denali_phy;
u32 i, tmp;
u32 obs_0, obs_1, obs_2, obs_err = 0;
- u32 rank = sdram_params->ch[channel].rank;
+ u32 rank = sdram_params->ch[channel].cap_info.rank;
u32 rank_mask;
/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
@@ -749,7 +750,7 @@ static int data_training_wl(const struct chan_info *chan, u32 channel,
u32 *denali_phy = chan->publ->denali_phy;
u32 i, tmp;
u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
- u32 rank = sdram_params->ch[channel].rank;
+ u32 rank = sdram_params->ch[channel].cap_info.rank;
/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
writel(0x00003f7c, (&denali_pi[175]));
@@ -811,7 +812,7 @@ static int data_training_rg(const struct chan_info *chan, u32 channel,
u32 *denali_phy = chan->publ->denali_phy;
u32 i, tmp;
u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
- u32 rank = sdram_params->ch[channel].rank;
+ u32 rank = sdram_params->ch[channel].cap_info.rank;
/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
writel(0x00003f7c, (&denali_pi[175]));
@@ -873,7 +874,7 @@ static int data_training_rl(const struct chan_info *chan, u32 channel,
{
u32 *denali_pi = chan->pi->denali_pi;
u32 i, tmp;
- u32 rank = sdram_params->ch[channel].rank;
+ u32 rank = sdram_params->ch[channel].cap_info.rank;
/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
writel(0x00003f7c, (&denali_pi[175]));
@@ -921,7 +922,7 @@ static int data_training_wdql(const struct chan_info *chan, u32 channel,
{
u32 *denali_pi = chan->pi->denali_pi;
u32 i, tmp;
- u32 rank = sdram_params->ch[channel].rank;
+ u32 rank = sdram_params->ch[channel].cap_info.rank;
u32 rank_mask;
/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
@@ -1055,14 +1056,14 @@ static void set_ddrconfig(const struct chan_info *chan,
unsigned int cs0_cap = 0;
unsigned int cs1_cap = 0;
- cs0_cap = (1 << (sdram_params->ch[channel].cs0_row
- + sdram_params->ch[channel].col
- + sdram_params->ch[channel].bk
- + sdram_params->ch[channel].bw - 20));
- if (sdram_params->ch[channel].rank > 1)
- cs1_cap = cs0_cap >> (sdram_params->ch[channel].cs0_row
- - sdram_params->ch[channel].cs1_row);
- if (sdram_params->ch[channel].row_3_4) {
+ cs0_cap = (1 << (sdram_params->ch[channel].cap_info.cs0_row
+ + sdram_params->ch[channel].cap_info.col
+ + sdram_params->ch[channel].cap_info.bk
+ + sdram_params->ch[channel].cap_info.bw - 20));
+ if (sdram_params->ch[channel].cap_info.rank > 1)
+ cs1_cap = cs0_cap >> (sdram_params->ch[channel].cap_info.cs0_row
+ - sdram_params->ch[channel].cap_info.cs1_row);
+ if (sdram_params->ch[channel].cap_info.row_3_4) {
cs0_cap = cs0_cap * 3 / 4;
cs1_cap = cs1_cap * 3 / 4;
}
@@ -1089,22 +1090,22 @@ static void dram_all_config(struct dram_info *dram,
struct rk3399_msch_regs *ddr_msch_regs;
const struct rk3399_msch_timings *noc_timing;
- if (sdram_params->ch[channel].col == 0)
+ if (sdram_params->ch[channel].cap_info.col == 0)
continue;
idx++;
- sys_reg2 |= SYS_REG_ENC_ROW_3_4(info->row_3_4, channel);
+ sys_reg2 |= SYS_REG_ENC_ROW_3_4(info->cap_info.row_3_4, channel);
sys_reg2 |= SYS_REG_ENC_CHINFO(channel);
- sys_reg2 |= SYS_REG_ENC_RANK(info->rank, channel);
- sys_reg2 |= SYS_REG_ENC_COL(info->col, channel);
- sys_reg2 |= SYS_REG_ENC_BK(info->bk, channel);
- sys_reg2 |= SYS_REG_ENC_BW(info->bw, channel);
- sys_reg2 |= SYS_REG_ENC_DBW(info->dbw, channel);
- SYS_REG_ENC_CS0_ROW(info->cs0_row, sys_reg2, sys_reg3, channel);
- if (info->cs1_row)
- SYS_REG_ENC_CS1_ROW(info->cs1_row, sys_reg2,
+ sys_reg2 |= SYS_REG_ENC_RANK(info->cap_info.rank, channel);
+ sys_reg2 |= SYS_REG_ENC_COL(info->cap_info.col, channel);
+ sys_reg2 |= SYS_REG_ENC_BK(info->cap_info.bk, channel);
+ sys_reg2 |= SYS_REG_ENC_BW(info->cap_info.bw, channel);
+ sys_reg2 |= SYS_REG_ENC_DBW(info->cap_info.dbw, channel);
+ SYS_REG_ENC_CS0_ROW(info->cap_info.cs0_row, sys_reg2, sys_reg3, channel);
+ if (info->cap_info.cs1_row)
+ SYS_REG_ENC_CS1_ROW(info->cap_info.cs1_row, sys_reg2,
sys_reg3, channel);
- sys_reg3 |= SYS_REG_ENC_CS1_COL(info->col, channel);
+ sys_reg3 |= SYS_REG_ENC_CS1_COL(info->cap_info.col, channel);
sys_reg3 |= SYS_REG_ENC_VERSION(DDR_SYS_REG_VERSION);
ddr_msch_regs = dram->chan[channel].msch;
@@ -1121,7 +1122,7 @@ static void dram_all_config(struct dram_info *dram,
&ddr_msch_regs->ddrmode);
/* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */
- if (sdram_params->ch[channel].rank == 1)
+ if (sdram_params->ch[channel].cap_info.rank == 1)
setbits_le32(&dram->chan[channel].pctl->denali_ctl[276],
1 << 17);
}
@@ -1232,7 +1233,7 @@ static int sdram_init(struct dram_info *dram,
}
set_ddrconfig(chan, sdram_params, channel,
- sdram_params->ch[channel].ddrconfig);
+ sdram_params->ch[channel].cap_info.ddrconfig);
}
dram_all_config(dram, sdram_params);
switch_to_phy_index1(dram, sdram_params);
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 37/92] ram: rockchip: rk3399: Add cap_info structure
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
Group common ddr attributes like
- rank
- col
- bk
- bw
- dbw
- row_3_4
- cs0_row
- cs1_row
- ddrconfig
into a common cap_info structure for more code readability and extend
if possible based on the new features.
No functionality change.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
.../include/asm/arch-rockchip/sdram_rk3399.h | 6 +-
drivers/ram/rockchip/sdram_rk3399.c | 71 ++++++++++---------
2 files changed, 41 insertions(+), 36 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
index a191d242f8..67044f53e5 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
@@ -96,7 +96,7 @@ struct rk3399_ddr_cic_regs {
/* DENALI_CTL_274 */
#define MEM_RST_VALID 1
-struct rk3399_sdram_channel {
+struct sdram_cap_info {
unsigned int rank;
/* dram column number, 0 means this channel is invalid */
unsigned int col;
@@ -114,6 +114,10 @@ struct rk3399_sdram_channel {
unsigned int cs0_row;
unsigned int cs1_row;
unsigned int ddrconfig;
+};
+
+struct rk3399_sdram_channel {
+ struct sdram_cap_info cap_info;
struct rk3399_msch_timings noc_timings;
};
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 220197a42e..1acf9efe9c 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -156,35 +156,36 @@ static void set_memory_map(const struct chan_info *chan, u32 channel,
u32 row;
/* Get row number from ddrconfig setting */
- if (sdram_ch->ddrconfig < 2 || sdram_ch->ddrconfig == 4)
+ if (sdram_ch->cap_info.ddrconfig < 2 ||
+ sdram_ch->cap_info.ddrconfig == 4)
row = 16;
- else if (sdram_ch->ddrconfig == 3)
+ else if (sdram_ch->cap_info.ddrconfig == 3)
row = 14;
else
row = 15;
- cs_map = (sdram_ch->rank > 1) ? 3 : 1;
- reduc = (sdram_ch->bw == 2) ? 0 : 1;
+ cs_map = (sdram_ch->cap_info.rank > 1) ? 3 : 1;
+ reduc = (sdram_ch->cap_info.bw == 2) ? 0 : 1;
/* Set the dram configuration to ctrl */
- clrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->col));
+ clrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->cap_info.col));
clrsetbits_le32(&denali_ctl[190], (0x3 << 16) | (0x7 << 24),
- ((3 - sdram_ch->bk) << 16) |
+ ((3 - sdram_ch->cap_info.bk) << 16) |
((16 - row) << 24));
clrsetbits_le32(&denali_ctl[196], 0x3 | (1 << 16),
cs_map | (reduc << 16));
/* PI_199 PI_COL_DIFF:RW:0:4 */
- clrsetbits_le32(&denali_pi[199], 0xF, (12 - sdram_ch->col));
+ clrsetbits_le32(&denali_pi[199], 0xF, (12 - sdram_ch->cap_info.col));
/* PI_155 PI_ROW_DIFF:RW:24:3 PI_BANK_DIFF:RW:16:2 */
clrsetbits_le32(&denali_pi[155], (0x3 << 16) | (0x7 << 24),
- ((3 - sdram_ch->bk) << 16) |
+ ((3 - sdram_ch->cap_info.bk) << 16) |
((16 - row) << 24));
/* PI_41 PI_CS_MAP:RW:24:4 */
clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24);
- if (sdram_ch->rank == 1 && sdram_params->base.dramtype == DDR3)
+ if (sdram_ch->cap_info.rank == 1 && sdram_params->base.dramtype == DDR3)
writel(0x2EC7FFFF, &denali_pi[34]);
}
@@ -686,7 +687,7 @@ static int data_training_ca(const struct chan_info *chan, u32 channel,
u32 *denali_phy = chan->publ->denali_phy;
u32 i, tmp;
u32 obs_0, obs_1, obs_2, obs_err = 0;
- u32 rank = sdram_params->ch[channel].rank;
+ u32 rank = sdram_params->ch[channel].cap_info.rank;
u32 rank_mask;
/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
@@ -749,7 +750,7 @@ static int data_training_wl(const struct chan_info *chan, u32 channel,
u32 *denali_phy = chan->publ->denali_phy;
u32 i, tmp;
u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
- u32 rank = sdram_params->ch[channel].rank;
+ u32 rank = sdram_params->ch[channel].cap_info.rank;
/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
writel(0x00003f7c, (&denali_pi[175]));
@@ -811,7 +812,7 @@ static int data_training_rg(const struct chan_info *chan, u32 channel,
u32 *denali_phy = chan->publ->denali_phy;
u32 i, tmp;
u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
- u32 rank = sdram_params->ch[channel].rank;
+ u32 rank = sdram_params->ch[channel].cap_info.rank;
/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
writel(0x00003f7c, (&denali_pi[175]));
@@ -873,7 +874,7 @@ static int data_training_rl(const struct chan_info *chan, u32 channel,
{
u32 *denali_pi = chan->pi->denali_pi;
u32 i, tmp;
- u32 rank = sdram_params->ch[channel].rank;
+ u32 rank = sdram_params->ch[channel].cap_info.rank;
/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
writel(0x00003f7c, (&denali_pi[175]));
@@ -921,7 +922,7 @@ static int data_training_wdql(const struct chan_info *chan, u32 channel,
{
u32 *denali_pi = chan->pi->denali_pi;
u32 i, tmp;
- u32 rank = sdram_params->ch[channel].rank;
+ u32 rank = sdram_params->ch[channel].cap_info.rank;
u32 rank_mask;
/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
@@ -1055,14 +1056,14 @@ static void set_ddrconfig(const struct chan_info *chan,
unsigned int cs0_cap = 0;
unsigned int cs1_cap = 0;
- cs0_cap = (1 << (sdram_params->ch[channel].cs0_row
- + sdram_params->ch[channel].col
- + sdram_params->ch[channel].bk
- + sdram_params->ch[channel].bw - 20));
- if (sdram_params->ch[channel].rank > 1)
- cs1_cap = cs0_cap >> (sdram_params->ch[channel].cs0_row
- - sdram_params->ch[channel].cs1_row);
- if (sdram_params->ch[channel].row_3_4) {
+ cs0_cap = (1 << (sdram_params->ch[channel].cap_info.cs0_row
+ + sdram_params->ch[channel].cap_info.col
+ + sdram_params->ch[channel].cap_info.bk
+ + sdram_params->ch[channel].cap_info.bw - 20));
+ if (sdram_params->ch[channel].cap_info.rank > 1)
+ cs1_cap = cs0_cap >> (sdram_params->ch[channel].cap_info.cs0_row
+ - sdram_params->ch[channel].cap_info.cs1_row);
+ if (sdram_params->ch[channel].cap_info.row_3_4) {
cs0_cap = cs0_cap * 3 / 4;
cs1_cap = cs1_cap * 3 / 4;
}
@@ -1089,22 +1090,22 @@ static void dram_all_config(struct dram_info *dram,
struct rk3399_msch_regs *ddr_msch_regs;
const struct rk3399_msch_timings *noc_timing;
- if (sdram_params->ch[channel].col == 0)
+ if (sdram_params->ch[channel].cap_info.col == 0)
continue;
idx++;
- sys_reg2 |= SYS_REG_ENC_ROW_3_4(info->row_3_4, channel);
+ sys_reg2 |= SYS_REG_ENC_ROW_3_4(info->cap_info.row_3_4, channel);
sys_reg2 |= SYS_REG_ENC_CHINFO(channel);
- sys_reg2 |= SYS_REG_ENC_RANK(info->rank, channel);
- sys_reg2 |= SYS_REG_ENC_COL(info->col, channel);
- sys_reg2 |= SYS_REG_ENC_BK(info->bk, channel);
- sys_reg2 |= SYS_REG_ENC_BW(info->bw, channel);
- sys_reg2 |= SYS_REG_ENC_DBW(info->dbw, channel);
- SYS_REG_ENC_CS0_ROW(info->cs0_row, sys_reg2, sys_reg3, channel);
- if (info->cs1_row)
- SYS_REG_ENC_CS1_ROW(info->cs1_row, sys_reg2,
+ sys_reg2 |= SYS_REG_ENC_RANK(info->cap_info.rank, channel);
+ sys_reg2 |= SYS_REG_ENC_COL(info->cap_info.col, channel);
+ sys_reg2 |= SYS_REG_ENC_BK(info->cap_info.bk, channel);
+ sys_reg2 |= SYS_REG_ENC_BW(info->cap_info.bw, channel);
+ sys_reg2 |= SYS_REG_ENC_DBW(info->cap_info.dbw, channel);
+ SYS_REG_ENC_CS0_ROW(info->cap_info.cs0_row, sys_reg2, sys_reg3, channel);
+ if (info->cap_info.cs1_row)
+ SYS_REG_ENC_CS1_ROW(info->cap_info.cs1_row, sys_reg2,
sys_reg3, channel);
- sys_reg3 |= SYS_REG_ENC_CS1_COL(info->col, channel);
+ sys_reg3 |= SYS_REG_ENC_CS1_COL(info->cap_info.col, channel);
sys_reg3 |= SYS_REG_ENC_VERSION(DDR_SYS_REG_VERSION);
ddr_msch_regs = dram->chan[channel].msch;
@@ -1121,7 +1122,7 @@ static void dram_all_config(struct dram_info *dram,
&ddr_msch_regs->ddrmode);
/* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */
- if (sdram_params->ch[channel].rank == 1)
+ if (sdram_params->ch[channel].cap_info.rank == 1)
setbits_le32(&dram->chan[channel].pctl->denali_ctl[276],
1 << 17);
}
@@ -1232,7 +1233,7 @@ static int sdram_init(struct dram_info *dram,
}
set_ddrconfig(chan, sdram_params, channel,
- sdram_params->ch[channel].ddrconfig);
+ sdram_params->ch[channel].cap_info.ddrconfig);
}
dram_all_config(dram, sdram_params);
switch_to_phy_index1(dram, sdram_params);
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 38/92] ram: rk3399: s/rk3399_base_params/sdram_base_params
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Most of the ddr parameters are common in rk3399_base_params
structure and which would reuse it in another controller like
px30 in future.
So, rename the structure from rk3399_base_params into
sdram_base_params.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
arch/arm/include/asm/arch-rockchip/sdram_rk3399.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
index 67044f53e5..fe25446cab 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
@@ -121,7 +121,7 @@ struct rk3399_sdram_channel {
struct rk3399_msch_timings noc_timings;
};
-struct rk3399_base_params {
+struct sdram_base_params {
unsigned int ddr_freq;
unsigned int dramtype;
unsigned int num_channels;
@@ -131,7 +131,7 @@ struct rk3399_base_params {
struct rk3399_sdram_params {
struct rk3399_sdram_channel ch[2];
- struct rk3399_base_params base;
+ struct sdram_base_params base;
struct rk3399_ddr_pctl_regs pctl_regs;
struct rk3399_ddr_pi_regs pi_regs;
struct rk3399_ddr_publ_regs phy_regs;
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 38/92] ram: rk3399: s/rk3399_base_params/sdram_base_params
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
Most of the ddr parameters are common in rk3399_base_params
structure and which would reuse it in another controller like
px30 in future.
So, rename the structure from rk3399_base_params into
sdram_base_params.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
arch/arm/include/asm/arch-rockchip/sdram_rk3399.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
index 67044f53e5..fe25446cab 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
@@ -121,7 +121,7 @@ struct rk3399_sdram_channel {
struct rk3399_msch_timings noc_timings;
};
-struct rk3399_base_params {
+struct sdram_base_params {
unsigned int ddr_freq;
unsigned int dramtype;
unsigned int num_channels;
@@ -131,7 +131,7 @@ struct rk3399_base_params {
struct rk3399_sdram_params {
struct rk3399_sdram_channel ch[2];
- struct rk3399_base_params base;
+ struct sdram_base_params base;
struct rk3399_ddr_pctl_regs pctl_regs;
struct rk3399_ddr_pi_regs pi_regs;
struct rk3399_ddr_publ_regs phy_regs;
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 39/92] ram: rk3399: Move common sdram structures in common header
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Move common sdram structures like sdram_cap_info, sdram_base_params
into sdram_common header, this would help to reuse the same
from another controllers like px30.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
.../include/asm/arch-rockchip/sdram_common.h | 29 +++++++++++++++++++
.../include/asm/arch-rockchip/sdram_rk3399.h | 28 ------------------
2 files changed, 29 insertions(+), 28 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index 8021ca21ed..200551fac5 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -5,6 +5,35 @@
#ifndef _ASM_ARCH_SDRAM_COMMON_H
#define _ASM_ARCH_SDRAM_COMMON_H
+
+struct sdram_cap_info {
+ unsigned int rank;
+ /* dram column number, 0 means this channel is invalid */
+ unsigned int col;
+ /* dram bank number, 3:8bank, 2:4bank */
+ unsigned int bk;
+ /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */
+ unsigned int bw;
+ /* die buswidth, 2:32bit, 1:16bit, 0:8bit */
+ unsigned int dbw;
+ /*
+ * row_3_4 = 1: 6Gb or 12Gb die
+ * row_3_4 = 0: normal die, power of 2
+ */
+ unsigned int row_3_4;
+ unsigned int cs0_row;
+ unsigned int cs1_row;
+ unsigned int ddrconfig;
+};
+
+struct sdram_base_params {
+ unsigned int ddr_freq;
+ unsigned int dramtype;
+ unsigned int num_channels;
+ unsigned int stride;
+ unsigned int odt;
+};
+
/*
* sys_reg bitfield struct
* [31] row_3_4_ch1
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
index fe25446cab..6258c811f5 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
@@ -96,39 +96,11 @@ struct rk3399_ddr_cic_regs {
/* DENALI_CTL_274 */
#define MEM_RST_VALID 1
-struct sdram_cap_info {
- unsigned int rank;
- /* dram column number, 0 means this channel is invalid */
- unsigned int col;
- /* dram bank number, 3:8bank, 2:4bank */
- unsigned int bk;
- /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */
- unsigned int bw;
- /* die buswidth, 2:32bit, 1:16bit, 0:8bit */
- unsigned int dbw;
- /*
- * row_3_4 = 1: 6Gb or 12Gb die
- * row_3_4 = 0: normal die, power of 2
- */
- unsigned int row_3_4;
- unsigned int cs0_row;
- unsigned int cs1_row;
- unsigned int ddrconfig;
-};
-
struct rk3399_sdram_channel {
struct sdram_cap_info cap_info;
struct rk3399_msch_timings noc_timings;
};
-struct sdram_base_params {
- unsigned int ddr_freq;
- unsigned int dramtype;
- unsigned int num_channels;
- unsigned int stride;
- unsigned int odt;
-};
-
struct rk3399_sdram_params {
struct rk3399_sdram_channel ch[2];
struct sdram_base_params base;
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 39/92] ram: rk3399: Move common sdram structures in common header
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
Move common sdram structures like sdram_cap_info, sdram_base_params
into sdram_common header, this would help to reuse the same
from another controllers like px30.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
.../include/asm/arch-rockchip/sdram_common.h | 29 +++++++++++++++++++
.../include/asm/arch-rockchip/sdram_rk3399.h | 28 ------------------
2 files changed, 29 insertions(+), 28 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index 8021ca21ed..200551fac5 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -5,6 +5,35 @@
#ifndef _ASM_ARCH_SDRAM_COMMON_H
#define _ASM_ARCH_SDRAM_COMMON_H
+
+struct sdram_cap_info {
+ unsigned int rank;
+ /* dram column number, 0 means this channel is invalid */
+ unsigned int col;
+ /* dram bank number, 3:8bank, 2:4bank */
+ unsigned int bk;
+ /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */
+ unsigned int bw;
+ /* die buswidth, 2:32bit, 1:16bit, 0:8bit */
+ unsigned int dbw;
+ /*
+ * row_3_4 = 1: 6Gb or 12Gb die
+ * row_3_4 = 0: normal die, power of 2
+ */
+ unsigned int row_3_4;
+ unsigned int cs0_row;
+ unsigned int cs1_row;
+ unsigned int ddrconfig;
+};
+
+struct sdram_base_params {
+ unsigned int ddr_freq;
+ unsigned int dramtype;
+ unsigned int num_channels;
+ unsigned int stride;
+ unsigned int odt;
+};
+
/*
* sys_reg bitfield struct
* [31] row_3_4_ch1
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
index fe25446cab..6258c811f5 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
@@ -96,39 +96,11 @@ struct rk3399_ddr_cic_regs {
/* DENALI_CTL_274 */
#define MEM_RST_VALID 1
-struct sdram_cap_info {
- unsigned int rank;
- /* dram column number, 0 means this channel is invalid */
- unsigned int col;
- /* dram bank number, 3:8bank, 2:4bank */
- unsigned int bk;
- /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */
- unsigned int bw;
- /* die buswidth, 2:32bit, 1:16bit, 0:8bit */
- unsigned int dbw;
- /*
- * row_3_4 = 1: 6Gb or 12Gb die
- * row_3_4 = 0: normal die, power of 2
- */
- unsigned int row_3_4;
- unsigned int cs0_row;
- unsigned int cs1_row;
- unsigned int ddrconfig;
-};
-
struct rk3399_sdram_channel {
struct sdram_cap_info cap_info;
struct rk3399_msch_timings noc_timings;
};
-struct sdram_base_params {
- unsigned int ddr_freq;
- unsigned int dramtype;
- unsigned int num_channels;
- unsigned int stride;
- unsigned int odt;
-};
-
struct rk3399_sdram_params {
struct rk3399_sdram_channel ch[2];
struct sdram_base_params base;
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 40/92] arm: include: rockchip: Move dramtypes to common header
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
dramtype enum numbers as common across all dram controllers
in rockchip, so move the eneum values in common header.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
arch/arm/include/asm/arch-rockchip/sdram.h | 6 ------
arch/arm/include/asm/arch-rockchip/sdram_common.h | 8 ++++++++
arch/arm/include/asm/arch-rockchip/sdram_rk322x.h | 7 -------
arch/arm/include/asm/arch-rockchip/sdram_rk3399.h | 8 --------
4 files changed, 8 insertions(+), 21 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram.h b/arch/arm/include/asm/arch-rockchip/sdram.h
index bbe425deb9..9220763fa7 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram.h
@@ -8,12 +8,6 @@
#ifndef _ASM_ARCH_RK3288_SDRAM_H__
#define _ASM_ARCH_RK3288_SDRAM_H__
-enum {
- DDR3 = 3,
- LPDDR3 = 6,
- UNUSED = 0xFF,
-};
-
struct rk3288_sdram_channel {
/*
* bit width in address, eg:
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index 200551fac5..e0a94f81a4 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -6,6 +6,14 @@
#ifndef _ASM_ARCH_SDRAM_COMMON_H
#define _ASM_ARCH_SDRAM_COMMON_H
+enum {
+ DDR3 = 0x3,
+ LPDDR2 = 0x5,
+ LPDDR3 = 0x6,
+ LPDDR4 = 0x7,
+ UNUSED = 0xFF
+};
+
struct sdram_cap_info {
unsigned int rank;
/* dram column number, 0 means this channel is invalid */
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h b/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h
index d0091a7aaf..336c5d7e8c 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h
@@ -7,13 +7,6 @@
#include <common.h>
-enum {
- DDR3 = 3,
- LPDDR2 = 5,
- LPDDR3 = 6,
- UNUSED = 0xFF,
-};
-
struct rk322x_sdram_channel {
/*
* bit width in address, eg:
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
index 6258c811f5..dc65ae7924 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
@@ -6,14 +6,6 @@
#ifndef _ASM_ARCH_SDRAM_RK3399_H
#define _ASM_ARCH_SDRAM_RK3399_H
-enum {
- DDR3 = 0x3,
- LPDDR2 = 0x5,
- LPDDR3 = 0x6,
- LPDDR4 = 0x7,
- UNUSED = 0xFF
-};
-
struct rk3399_ddr_pctl_regs {
u32 denali_ctl[332];
};
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 40/92] arm: include: rockchip: Move dramtypes to common header
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
dramtype enum numbers as common across all dram controllers
in rockchip, so move the eneum values in common header.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/arm/include/asm/arch-rockchip/sdram.h | 6 ------
arch/arm/include/asm/arch-rockchip/sdram_common.h | 8 ++++++++
arch/arm/include/asm/arch-rockchip/sdram_rk322x.h | 7 -------
arch/arm/include/asm/arch-rockchip/sdram_rk3399.h | 8 --------
4 files changed, 8 insertions(+), 21 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram.h b/arch/arm/include/asm/arch-rockchip/sdram.h
index bbe425deb9..9220763fa7 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram.h
@@ -8,12 +8,6 @@
#ifndef _ASM_ARCH_RK3288_SDRAM_H__
#define _ASM_ARCH_RK3288_SDRAM_H__
-enum {
- DDR3 = 3,
- LPDDR3 = 6,
- UNUSED = 0xFF,
-};
-
struct rk3288_sdram_channel {
/*
* bit width in address, eg:
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index 200551fac5..e0a94f81a4 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -6,6 +6,14 @@
#ifndef _ASM_ARCH_SDRAM_COMMON_H
#define _ASM_ARCH_SDRAM_COMMON_H
+enum {
+ DDR3 = 0x3,
+ LPDDR2 = 0x5,
+ LPDDR3 = 0x6,
+ LPDDR4 = 0x7,
+ UNUSED = 0xFF
+};
+
struct sdram_cap_info {
unsigned int rank;
/* dram column number, 0 means this channel is invalid */
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h b/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h
index d0091a7aaf..336c5d7e8c 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h
@@ -7,13 +7,6 @@
#include <common.h>
-enum {
- DDR3 = 3,
- LPDDR2 = 5,
- LPDDR3 = 6,
- UNUSED = 0xFF,
-};
-
struct rk322x_sdram_channel {
/*
* bit width in address, eg:
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
index 6258c811f5..dc65ae7924 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
@@ -6,14 +6,6 @@
#ifndef _ASM_ARCH_SDRAM_RK3399_H
#define _ASM_ARCH_SDRAM_RK3399_H
-enum {
- DDR3 = 0x3,
- LPDDR2 = 0x5,
- LPDDR3 = 0x6,
- LPDDR4 = 0x7,
- UNUSED = 0xFF
-};
-
struct rk3399_ddr_pctl_regs {
u32 denali_ctl[332];
};
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 41/92] arm: include: rockchip: Add DDR4 enum
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Add DDR4 enum number in common header.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
arch/arm/include/asm/arch-rockchip/sdram_common.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index e0a94f81a4..d723e6dacc 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -7,6 +7,7 @@
#define _ASM_ARCH_SDRAM_COMMON_H
enum {
+ DDR4 = 0,
DDR3 = 0x3,
LPDDR2 = 0x5,
LPDDR3 = 0x6,
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 41/92] arm: include: rockchip: Add DDR4 enum
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
Add DDR4 enum number in common header.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
arch/arm/include/asm/arch-rockchip/sdram_common.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index e0a94f81a4..d723e6dacc 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -7,6 +7,7 @@
#define _ASM_ARCH_SDRAM_COMMON_H
enum {
+ DDR4 = 0,
DDR3 = 0x3,
LPDDR2 = 0x5,
LPDDR3 = 0x6,
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 42/92] ram: rockchip: Add initial Kconfig
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Right now sdram drivers in rockchip SoC are built based
on the SoC configs which may not be an adequate solutions
while adding common or debug driver.
So, add meaningful Kconfig options start with rk3399.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
drivers/ram/Kconfig | 1 +
drivers/ram/rockchip/Kconfig | 17 +++++++++++++++++
drivers/ram/rockchip/Makefile | 2 +-
3 files changed, 19 insertions(+), 1 deletion(-)
create mode 100644 drivers/ram/rockchip/Kconfig
diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index fbf7d7b20f..568d8f2c6a 100644
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -54,4 +54,5 @@ config K3_AM654_DDRSS
config add support for the initialization of the external
SDRAM devices connected to DDR subsystem.
+source "drivers/ram/rockchip/Kconfig"
source "drivers/ram/stm32mp1/Kconfig"
diff --git a/drivers/ram/rockchip/Kconfig b/drivers/ram/rockchip/Kconfig
new file mode 100644
index 0000000000..995cb487b8
--- /dev/null
+++ b/drivers/ram/rockchip/Kconfig
@@ -0,0 +1,17 @@
+config RAM_ROCKCHIP
+ bool "Ram drivers support for Rockchip SoCs"
+ depends on RAM && ARCH_ROCKCHIP
+ default y
+ help
+ This enables support for ram drivers Rockchip SoCs.
+
+if RAM_ROCKCHIP
+
+config RAM_RK3399
+ bool "Ram driver for Rockchip RK3399"
+ default ROCKCHIP_RK3399
+ help
+ This enables ram drivers support for the platforms based on
+ Rockchip RK3399 SoC.
+
+endif # RAM_ROCKCHIP
diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile
index 5df196066d..07d4b62a9d 100644
--- a/drivers/ram/rockchip/Makefile
+++ b/drivers/ram/rockchip/Makefile
@@ -9,4 +9,4 @@ obj-$(CONFIG_ROCKCHIP_RK3188) = sdram_rk3188.o
obj-$(CONFIG_ROCKCHIP_RK322X) = sdram_rk322x.o
obj-$(CONFIG_ROCKCHIP_RK3288) = sdram_rk3288.o
obj-$(CONFIG_ROCKCHIP_RK3328) = sdram_rk3328.o
-obj-$(CONFIG_ROCKCHIP_RK3399) = sdram_rk3399.o
+obj-$(CONFIG_RAM_RK3399) += sdram_rk3399.o
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 42/92] ram: rockchip: Add initial Kconfig
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
Right now sdram drivers in rockchip SoC are built based
on the SoC configs which may not be an adequate solutions
while adding common or debug driver.
So, add meaningful Kconfig options start with rk3399.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
drivers/ram/Kconfig | 1 +
drivers/ram/rockchip/Kconfig | 17 +++++++++++++++++
drivers/ram/rockchip/Makefile | 2 +-
3 files changed, 19 insertions(+), 1 deletion(-)
create mode 100644 drivers/ram/rockchip/Kconfig
diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index fbf7d7b20f..568d8f2c6a 100644
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -54,4 +54,5 @@ config K3_AM654_DDRSS
config add support for the initialization of the external
SDRAM devices connected to DDR subsystem.
+source "drivers/ram/rockchip/Kconfig"
source "drivers/ram/stm32mp1/Kconfig"
diff --git a/drivers/ram/rockchip/Kconfig b/drivers/ram/rockchip/Kconfig
new file mode 100644
index 0000000000..995cb487b8
--- /dev/null
+++ b/drivers/ram/rockchip/Kconfig
@@ -0,0 +1,17 @@
+config RAM_ROCKCHIP
+ bool "Ram drivers support for Rockchip SoCs"
+ depends on RAM && ARCH_ROCKCHIP
+ default y
+ help
+ This enables support for ram drivers Rockchip SoCs.
+
+if RAM_ROCKCHIP
+
+config RAM_RK3399
+ bool "Ram driver for Rockchip RK3399"
+ default ROCKCHIP_RK3399
+ help
+ This enables ram drivers support for the platforms based on
+ Rockchip RK3399 SoC.
+
+endif # RAM_ROCKCHIP
diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile
index 5df196066d..07d4b62a9d 100644
--- a/drivers/ram/rockchip/Makefile
+++ b/drivers/ram/rockchip/Makefile
@@ -9,4 +9,4 @@ obj-$(CONFIG_ROCKCHIP_RK3188) = sdram_rk3188.o
obj-$(CONFIG_ROCKCHIP_RK322X) = sdram_rk322x.o
obj-$(CONFIG_ROCKCHIP_RK3288) = sdram_rk3288.o
obj-$(CONFIG_ROCKCHIP_RK3328) = sdram_rk3328.o
-obj-$(CONFIG_ROCKCHIP_RK3399) = sdram_rk3399.o
+obj-$(CONFIG_RAM_RK3399) += sdram_rk3399.o
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 43/92] debug_uart: Add printdec
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Add printdec, this would help to print an
output a decimalism value.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
include/debug_uart.h | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/include/debug_uart.h b/include/debug_uart.h
index 34e8b2fc81..cd70ae1a04 100644
--- a/include/debug_uart.h
+++ b/include/debug_uart.h
@@ -104,6 +104,13 @@ void printhex4(uint value);
*/
void printhex8(uint value);
+/**
+ * printdec() - Output a decimalism value
+ *
+ * @value: Value to output
+ */
+void printdec(uint value);
+
#ifdef CONFIG_DEBUG_UART_ANNOUNCE
#define _DEBUG_UART_ANNOUNCE printascii("<debug_uart> ");
#else
@@ -170,6 +177,18 @@ void printhex8(uint value);
{ \
printhex(value, 8); \
} \
+\
+ void printdec(uint value) \
+ { \
+ if (value > 10) { \
+ printdec(value / 10); \
+ value %= 10; \
+ } else if (value == 10) { \
+ _debug_uart_putc('1'); \
+ value = 0; \
+ } \
+ _debug_uart_putc('0' + value); \
+ } \
\
void debug_uart_init(void) \
{ \
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 43/92] debug_uart: Add printdec
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
Add printdec, this would help to print an
output a decimalism value.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
include/debug_uart.h | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/include/debug_uart.h b/include/debug_uart.h
index 34e8b2fc81..cd70ae1a04 100644
--- a/include/debug_uart.h
+++ b/include/debug_uart.h
@@ -104,6 +104,13 @@ void printhex4(uint value);
*/
void printhex8(uint value);
+/**
+ * printdec() - Output a decimalism value
+ *
+ * @value: Value to output
+ */
+void printdec(uint value);
+
#ifdef CONFIG_DEBUG_UART_ANNOUNCE
#define _DEBUG_UART_ANNOUNCE printascii("<debug_uart> ");
#else
@@ -170,6 +177,18 @@ void printhex8(uint value);
{ \
printhex(value, 8); \
} \
+\
+ void printdec(uint value) \
+ { \
+ if (value > 10) { \
+ printdec(value / 10); \
+ value %= 10; \
+ } else if (value == 10) { \
+ _debug_uart_putc('1'); \
+ value = 0; \
+ } \
+ _debug_uart_putc('0' + value); \
+ } \
\
void debug_uart_init(void) \
{ \
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 44/92] ram: rockchip: Add debug sdram driver
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Add sdram driver to handle debug across rockchip SoCs.
This would help to improve code debugging feature for
sdram drivers in rockchip family, whoever wants to
debug the driver should call these core debug code on
their respective platform sdram drivers.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
.../include/asm/arch-rockchip/sdram_common.h | 9 +++++
drivers/ram/rockchip/Kconfig | 9 +++++
drivers/ram/rockchip/Makefile | 1 +
drivers/ram/rockchip/sdram_debug.c | 34 +++++++++++++++++++
4 files changed, 53 insertions(+)
create mode 100644 drivers/ram/rockchip/sdram_debug.c
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index d723e6dacc..ebf4148b4d 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -122,4 +122,13 @@ size_t rockchip_sdram_size(phys_addr_t reg);
/* Called by U-Boot board_init_r for Rockchip SoCs */
int dram_init(void);
+
+#if !defined(CONFIG_RAM_ROCKCHIP_DEBUG)
+inline void sdram_print_dram_type(unsigned char dramtype)
+{
+}
+#else
+void sdram_print_dram_type(unsigned char dramtype);
+#endif /* CONFIG_RAM_ROCKCHIP_DEBUG */
+
#endif
diff --git a/drivers/ram/rockchip/Kconfig b/drivers/ram/rockchip/Kconfig
index 995cb487b8..151ffb684d 100644
--- a/drivers/ram/rockchip/Kconfig
+++ b/drivers/ram/rockchip/Kconfig
@@ -7,6 +7,15 @@ config RAM_ROCKCHIP
if RAM_ROCKCHIP
+config RAM_ROCKCHIP_DEBUG
+ bool "Rockchip ram drivers debugging"
+ help
+ This enables debugging ram driver API's for the platforms
+ based on Rockchip SoCs.
+
+ This is an option for developers to understand the ram drivers
+ initialization, configurations and etc.
+
config RAM_RK3399
bool "Ram driver for Rockchip RK3399"
default ROCKCHIP_RK3399
diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile
index 07d4b62a9d..feb1f82d00 100644
--- a/drivers/ram/rockchip/Makefile
+++ b/drivers/ram/rockchip/Makefile
@@ -3,6 +3,7 @@
# Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
#
+obj-$(CONFIG_RAM_ROCKCHIP_DEBUG) += sdram_debug.o
obj-$(CONFIG_ROCKCHIP_RK3368) = dmc-rk3368.o
obj-$(CONFIG_ROCKCHIP_RK3128) = sdram_rk3128.o
obj-$(CONFIG_ROCKCHIP_RK3188) = sdram_rk3188.o
diff --git a/drivers/ram/rockchip/sdram_debug.c b/drivers/ram/rockchip/sdram_debug.c
new file mode 100644
index 0000000000..c13e140fa5
--- /dev/null
+++ b/drivers/ram/rockchip/sdram_debug.c
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ * (C) Copyright 2019 Amarula Solutions.
+ * Author: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <asm/arch-rockchip/sdram_common.h>
+
+void sdram_print_dram_type(unsigned char dramtype)
+{
+ switch (dramtype) {
+ case DDR3:
+ printascii("DDR3");
+ break;
+ case DDR4:
+ printascii("DDR4");
+ break;
+ case LPDDR2:
+ printascii("LPDDR2");
+ break;
+ case LPDDR3:
+ printascii("LPDDR3");
+ break;
+ case LPDDR4:
+ printascii("LPDDR4");
+ break;
+ default:
+ printascii("Unknown Device");
+ break;
+ }
+}
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 44/92] ram: rockchip: Add debug sdram driver
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
Add sdram driver to handle debug across rockchip SoCs.
This would help to improve code debugging feature for
sdram drivers in rockchip family, whoever wants to
debug the driver should call these core debug code on
their respective platform sdram drivers.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
.../include/asm/arch-rockchip/sdram_common.h | 9 +++++
drivers/ram/rockchip/Kconfig | 9 +++++
drivers/ram/rockchip/Makefile | 1 +
drivers/ram/rockchip/sdram_debug.c | 34 +++++++++++++++++++
4 files changed, 53 insertions(+)
create mode 100644 drivers/ram/rockchip/sdram_debug.c
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index d723e6dacc..ebf4148b4d 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -122,4 +122,13 @@ size_t rockchip_sdram_size(phys_addr_t reg);
/* Called by U-Boot board_init_r for Rockchip SoCs */
int dram_init(void);
+
+#if !defined(CONFIG_RAM_ROCKCHIP_DEBUG)
+inline void sdram_print_dram_type(unsigned char dramtype)
+{
+}
+#else
+void sdram_print_dram_type(unsigned char dramtype);
+#endif /* CONFIG_RAM_ROCKCHIP_DEBUG */
+
#endif
diff --git a/drivers/ram/rockchip/Kconfig b/drivers/ram/rockchip/Kconfig
index 995cb487b8..151ffb684d 100644
--- a/drivers/ram/rockchip/Kconfig
+++ b/drivers/ram/rockchip/Kconfig
@@ -7,6 +7,15 @@ config RAM_ROCKCHIP
if RAM_ROCKCHIP
+config RAM_ROCKCHIP_DEBUG
+ bool "Rockchip ram drivers debugging"
+ help
+ This enables debugging ram driver API's for the platforms
+ based on Rockchip SoCs.
+
+ This is an option for developers to understand the ram drivers
+ initialization, configurations and etc.
+
config RAM_RK3399
bool "Ram driver for Rockchip RK3399"
default ROCKCHIP_RK3399
diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile
index 07d4b62a9d..feb1f82d00 100644
--- a/drivers/ram/rockchip/Makefile
+++ b/drivers/ram/rockchip/Makefile
@@ -3,6 +3,7 @@
# Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
#
+obj-$(CONFIG_RAM_ROCKCHIP_DEBUG) += sdram_debug.o
obj-$(CONFIG_ROCKCHIP_RK3368) = dmc-rk3368.o
obj-$(CONFIG_ROCKCHIP_RK3128) = sdram_rk3128.o
obj-$(CONFIG_ROCKCHIP_RK3188) = sdram_rk3188.o
diff --git a/drivers/ram/rockchip/sdram_debug.c b/drivers/ram/rockchip/sdram_debug.c
new file mode 100644
index 0000000000..c13e140fa5
--- /dev/null
+++ b/drivers/ram/rockchip/sdram_debug.c
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ * (C) Copyright 2019 Amarula Solutions.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <asm/arch-rockchip/sdram_common.h>
+
+void sdram_print_dram_type(unsigned char dramtype)
+{
+ switch (dramtype) {
+ case DDR3:
+ printascii("DDR3");
+ break;
+ case DDR4:
+ printascii("DDR4");
+ break;
+ case LPDDR2:
+ printascii("LPDDR2");
+ break;
+ case LPDDR3:
+ printascii("LPDDR3");
+ break;
+ case LPDDR4:
+ printascii("LPDDR4");
+ break;
+ default:
+ printascii("Unknown Device");
+ break;
+ }
+}
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 45/92] ram: rockchip: debug: Add sdram_print_ddr_info
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Add sdram ddr info print support, this would help to
observe the sdram base parameters.
Here is sample print on LPDDR4, 50MHz channel 0
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
.../include/asm/arch-rockchip/sdram_common.h | 7 ++++
drivers/ram/rockchip/sdram_debug.c | 40 +++++++++++++++++++
2 files changed, 47 insertions(+)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index ebf4148b4d..3935733871 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -127,8 +127,15 @@ int dram_init(void);
inline void sdram_print_dram_type(unsigned char dramtype)
{
}
+
+inline void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
+ struct sdram_base_params *base)
+{
+}
#else
void sdram_print_dram_type(unsigned char dramtype);
+void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
+ struct sdram_base_params *base);
#endif /* CONFIG_RAM_ROCKCHIP_DEBUG */
#endif
diff --git a/drivers/ram/rockchip/sdram_debug.c b/drivers/ram/rockchip/sdram_debug.c
index c13e140fa5..69a6f94a73 100644
--- a/drivers/ram/rockchip/sdram_debug.c
+++ b/drivers/ram/rockchip/sdram_debug.c
@@ -32,3 +32,43 @@ void sdram_print_dram_type(unsigned char dramtype)
break;
}
}
+
+void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
+ struct sdram_base_params *base)
+{
+ u32 bg;
+
+ bg = (cap_info->dbw == 0) ? 2 : 1;
+
+ sdram_print_dram_type(base->dramtype);
+
+ printascii(", ");
+ printdec(base->ddr_freq);
+ printascii("MHz\n");
+
+ printascii("BW=");
+ printdec(8 << cap_info->bw);
+
+ printascii(" Col=");
+ printdec(cap_info->col);
+
+ printascii(" Bk=");
+ printdec(0x1 << cap_info->bk);
+ if (base->dramtype == DDR4) {
+ printascii(" BG=");
+ printdec(1 << bg);
+ }
+
+ printascii(" CS0 Row=");
+ printdec(cap_info->cs0_row);
+ if (cap_info->rank > 1) {
+ printascii(" CS1 Row=");
+ printdec(cap_info->cs1_row);
+ }
+
+ printascii(" CS=");
+ printdec(cap_info->rank);
+
+ printascii(" Die BW=");
+ printdec(8 << cap_info->dbw);
+}
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 45/92] ram: rockchip: debug: Add sdram_print_ddr_info
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
Add sdram ddr info print support, this would help to
observe the sdram base parameters.
Here is sample print on LPDDR4, 50MHz channel 0
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
.../include/asm/arch-rockchip/sdram_common.h | 7 ++++
drivers/ram/rockchip/sdram_debug.c | 40 +++++++++++++++++++
2 files changed, 47 insertions(+)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index ebf4148b4d..3935733871 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -127,8 +127,15 @@ int dram_init(void);
inline void sdram_print_dram_type(unsigned char dramtype)
{
}
+
+inline void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
+ struct sdram_base_params *base)
+{
+}
#else
void sdram_print_dram_type(unsigned char dramtype);
+void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
+ struct sdram_base_params *base);
#endif /* CONFIG_RAM_ROCKCHIP_DEBUG */
#endif
diff --git a/drivers/ram/rockchip/sdram_debug.c b/drivers/ram/rockchip/sdram_debug.c
index c13e140fa5..69a6f94a73 100644
--- a/drivers/ram/rockchip/sdram_debug.c
+++ b/drivers/ram/rockchip/sdram_debug.c
@@ -32,3 +32,43 @@ void sdram_print_dram_type(unsigned char dramtype)
break;
}
}
+
+void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
+ struct sdram_base_params *base)
+{
+ u32 bg;
+
+ bg = (cap_info->dbw == 0) ? 2 : 1;
+
+ sdram_print_dram_type(base->dramtype);
+
+ printascii(", ");
+ printdec(base->ddr_freq);
+ printascii("MHz\n");
+
+ printascii("BW=");
+ printdec(8 << cap_info->bw);
+
+ printascii(" Col=");
+ printdec(cap_info->col);
+
+ printascii(" Bk=");
+ printdec(0x1 << cap_info->bk);
+ if (base->dramtype == DDR4) {
+ printascii(" BG=");
+ printdec(1 << bg);
+ }
+
+ printascii(" CS0 Row=");
+ printdec(cap_info->cs0_row);
+ if (cap_info->rank > 1) {
+ printascii(" CS1 Row=");
+ printdec(cap_info->cs1_row);
+ }
+
+ printascii(" CS=");
+ printdec(cap_info->rank);
+
+ printascii(" Die BW=");
+ printdec(8 << cap_info->dbw);
+}
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 46/92] ram: rockchip: debug: Get the cs capacity
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Add code to get the channel capacity, this would help to
print the capacity of specific channel.
Here is sample print on LPDDR4, 50MHz channel 0
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
drivers/ram/rockchip/sdram_debug.c | 46 +++++++++++++++++++++++++++++-
1 file changed, 45 insertions(+), 1 deletion(-)
diff --git a/drivers/ram/rockchip/sdram_debug.c b/drivers/ram/rockchip/sdram_debug.c
index 69a6f94a73..19e9225c12 100644
--- a/drivers/ram/rockchip/sdram_debug.c
+++ b/drivers/ram/rockchip/sdram_debug.c
@@ -33,10 +33,46 @@ void sdram_print_dram_type(unsigned char dramtype)
}
}
+/**
+ * cs = 0, cs0
+ * cs = 1, cs1
+ * cs => 2, cs0+cs1
+ * note: it didn't consider about row_3_4
+ */
+u64 sdram_get_cs_cap(struct sdram_cap_info *cap_info, u32 cs, u32 dram_type)
+{
+ u32 bg;
+ u64 cap[2];
+
+ if (dram_type == DDR4)
+ /* DDR4 8bit dram BG = 2(4bank groups),
+ * 16bit dram BG = 1 (2 bank groups)
+ */
+ bg = (cap_info->dbw == 0) ? 2 : 1;
+ else
+ bg = 0;
+
+ cap[0] = 1llu << (cap_info->bw + cap_info->col +
+ bg + cap_info->bk + cap_info->cs0_row);
+
+ if (cap_info->rank == 2)
+ cap[1] = 1llu << (cap_info->bw + cap_info->col +
+ bg + cap_info->bk + cap_info->cs1_row);
+ else
+ cap[1] = 0;
+
+ if (cs == 0)
+ return cap[0];
+ else if (cs == 1)
+ return cap[1];
+ else
+ return (cap[0] + cap[1]);
+}
+
void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
struct sdram_base_params *base)
{
- u32 bg;
+ u32 bg, cap;
bg = (cap_info->dbw == 0) ? 2 : 1;
@@ -71,4 +107,12 @@ void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
printascii(" Die BW=");
printdec(8 << cap_info->dbw);
+
+ cap = sdram_get_cs_cap(cap_info, 3, base->dramtype);
+ if (cap_info->row_3_4)
+ cap = cap * 3 / 4;
+
+ printascii(" Size=");
+ printdec(cap >> 20);
+ printascii("MB\n");
}
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 46/92] ram: rockchip: debug: Get the cs capacity
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
Add code to get the channel capacity, this would help to
print the capacity of specific channel.
Here is sample print on LPDDR4, 50MHz channel 0
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
drivers/ram/rockchip/sdram_debug.c | 46 +++++++++++++++++++++++++++++-
1 file changed, 45 insertions(+), 1 deletion(-)
diff --git a/drivers/ram/rockchip/sdram_debug.c b/drivers/ram/rockchip/sdram_debug.c
index 69a6f94a73..19e9225c12 100644
--- a/drivers/ram/rockchip/sdram_debug.c
+++ b/drivers/ram/rockchip/sdram_debug.c
@@ -33,10 +33,46 @@ void sdram_print_dram_type(unsigned char dramtype)
}
}
+/**
+ * cs = 0, cs0
+ * cs = 1, cs1
+ * cs => 2, cs0+cs1
+ * note: it didn't consider about row_3_4
+ */
+u64 sdram_get_cs_cap(struct sdram_cap_info *cap_info, u32 cs, u32 dram_type)
+{
+ u32 bg;
+ u64 cap[2];
+
+ if (dram_type == DDR4)
+ /* DDR4 8bit dram BG = 2(4bank groups),
+ * 16bit dram BG = 1 (2 bank groups)
+ */
+ bg = (cap_info->dbw == 0) ? 2 : 1;
+ else
+ bg = 0;
+
+ cap[0] = 1llu << (cap_info->bw + cap_info->col +
+ bg + cap_info->bk + cap_info->cs0_row);
+
+ if (cap_info->rank == 2)
+ cap[1] = 1llu << (cap_info->bw + cap_info->col +
+ bg + cap_info->bk + cap_info->cs1_row);
+ else
+ cap[1] = 0;
+
+ if (cs == 0)
+ return cap[0];
+ else if (cs == 1)
+ return cap[1];
+ else
+ return (cap[0] + cap[1]);
+}
+
void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
struct sdram_base_params *base)
{
- u32 bg;
+ u32 bg, cap;
bg = (cap_info->dbw == 0) ? 2 : 1;
@@ -71,4 +107,12 @@ void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
printascii(" Die BW=");
printdec(8 << cap_info->dbw);
+
+ cap = sdram_get_cs_cap(cap_info, 3, base->dramtype);
+ if (cap_info->row_3_4)
+ cap = cap * 3 / 4;
+
+ printascii(" Size=");
+ printdec(cap >> 20);
+ printascii("MB\n");
}
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 47/92] ram: rk3399: debug: Add sdram_print_stride
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Add code to print the channel stride, this would help to
print the stride of associated channel.
Here is sample print on LPDDR4, 50MHz.
256B stride
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
.../include/asm/arch-rockchip/sdram_common.h | 5 ++++
drivers/ram/rockchip/sdram_debug.c | 29 +++++++++++++++++++
2 files changed, 34 insertions(+)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index 3935733871..69cafda904 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -132,10 +132,15 @@ inline void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
struct sdram_base_params *base)
{
}
+
+inline void sdram_print_stride(unsigned int stride)
+{
+}
#else
void sdram_print_dram_type(unsigned char dramtype);
void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
struct sdram_base_params *base);
+void sdram_print_stride(unsigned int stride);
#endif /* CONFIG_RAM_ROCKCHIP_DEBUG */
#endif
diff --git a/drivers/ram/rockchip/sdram_debug.c b/drivers/ram/rockchip/sdram_debug.c
index 19e9225c12..9cf662675b 100644
--- a/drivers/ram/rockchip/sdram_debug.c
+++ b/drivers/ram/rockchip/sdram_debug.c
@@ -116,3 +116,32 @@ void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
printdec(cap >> 20);
printascii("MB\n");
}
+
+void sdram_print_stride(unsigned int stride)
+{
+ switch (stride) {
+ case 0xc:
+ printf("128B stride\n");
+ break;
+ case 5:
+ case 9:
+ case 0xd:
+ case 0x11:
+ case 0x19:
+ printf("256B stride\n");
+ break;
+ case 0xa:
+ case 0xe:
+ case 0x12:
+ printf("512B stride\n");
+ break;
+ case 0xf:
+ printf("4K stride\n");
+ break;
+ case 0x1f:
+ printf("32MB + 256B stride\n");
+ break;
+ default:
+ printf("no stride\n");
+ }
+}
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 47/92] ram: rk3399: debug: Add sdram_print_stride
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
Add code to print the channel stride, this would help to
print the stride of associated channel.
Here is sample print on LPDDR4, 50MHz.
256B stride
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
.../include/asm/arch-rockchip/sdram_common.h | 5 ++++
drivers/ram/rockchip/sdram_debug.c | 29 +++++++++++++++++++
2 files changed, 34 insertions(+)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index 3935733871..69cafda904 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -132,10 +132,15 @@ inline void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
struct sdram_base_params *base)
{
}
+
+inline void sdram_print_stride(unsigned int stride)
+{
+}
#else
void sdram_print_dram_type(unsigned char dramtype);
void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
struct sdram_base_params *base);
+void sdram_print_stride(unsigned int stride);
#endif /* CONFIG_RAM_ROCKCHIP_DEBUG */
#endif
diff --git a/drivers/ram/rockchip/sdram_debug.c b/drivers/ram/rockchip/sdram_debug.c
index 19e9225c12..9cf662675b 100644
--- a/drivers/ram/rockchip/sdram_debug.c
+++ b/drivers/ram/rockchip/sdram_debug.c
@@ -116,3 +116,32 @@ void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
printdec(cap >> 20);
printascii("MB\n");
}
+
+void sdram_print_stride(unsigned int stride)
+{
+ switch (stride) {
+ case 0xc:
+ printf("128B stride\n");
+ break;
+ case 5:
+ case 9:
+ case 0xd:
+ case 0x11:
+ case 0x19:
+ printf("256B stride\n");
+ break;
+ case 0xa:
+ case 0xe:
+ case 0x12:
+ printf("512B stride\n");
+ break;
+ case 0xf:
+ printf("4K stride\n");
+ break;
+ case 0x1f:
+ printf("32MB + 256B stride\n");
+ break;
+ default:
+ printf("no stride\n");
+ }
+}
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 48/92] ram: rk3399: Compute stride for 2 channels
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
stride value from sdram timings can be computed dynamically
based on the determined capacity for the given channel.
Right now these stride values are taken as part of sdram timings
via dtsi, but it possible to use same timings dtsi for given
frequency even though the configured board sdram do support
single channel with different size by dynamically detect the
stride value.
Example, NanoPi NEO4 do have DDR3-1866, but with single channel
and 1GB size with dynamic stride detection it is possible to
use existing rk3399-sdram-ddr3-1866.dtsi whose stride,
number of channels and capacity it support is d efferent.
So, add initial support to calculate the stride value for
2 channels sdram, which is available by default on existing
boards.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 72 ++++++++++++++++++++++++++++-
1 file changed, 71 insertions(+), 1 deletion(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 1acf9efe9c..5985c37f08 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1185,8 +1185,76 @@ static int switch_to_phy_index1(struct dram_info *dram,
return 0;
}
+static unsigned char calculate_stride(struct rk3399_sdram_params *sdram_params)
+{
+ unsigned int stride = sdram_params->base.stride;
+ unsigned int channel, chinfo = 0;
+ unsigned int ch_cap[2] = {0, 0};
+ u64 cap;
+
+ for (channel = 0; channel < 2; channel++) {
+ unsigned int cs0_cap = 0;
+ unsigned int cs1_cap = 0;
+ struct sdram_cap_info *cap_info =
+ &sdram_params->ch[channel].cap_info;
+
+ if (cap_info->col == 0)
+ continue;
+
+ cs0_cap = (1 << (cap_info->cs0_row + cap_info->col +
+ cap_info->bk + cap_info->bw - 20));
+ if (cap_info->rank > 1)
+ cs1_cap = cs0_cap >> (cap_info->cs0_row
+ - cap_info->cs1_row);
+ if (cap_info->row_3_4) {
+ cs0_cap = cs0_cap * 3 / 4;
+ cs1_cap = cs1_cap * 3 / 4;
+ }
+ ch_cap[channel] = cs0_cap + cs1_cap;
+ chinfo |= 1 << channel;
+ }
+
+ /* stride calculation for 2 channels, default gstride type is 256B */
+ if (ch_cap[0] == ch_cap[1]) {
+ cap = ch_cap[0] + ch_cap[1];
+ switch (cap) {
+ /* 512MB */
+ case 512:
+ stride = 0;
+ break;
+ /* 1GB */
+ case 1024:
+ stride = 0x5;
+ break;
+ /*
+ * 768MB + 768MB same as total 2GB memory
+ * useful space: 0-768MB 1GB-1792MB
+ */
+ case 1536:
+ /* 2GB */
+ case 2048:
+ stride = 0x9;
+ break;
+ /* 1536MB + 1536MB */
+ case 3072:
+ stride = 0x11;
+ break;
+ /* 4GB */
+ case 4096:
+ stride = 0xD;
+ break;
+ default:
+ printf("%s: Unable to calculate stride for ", __func__);
+ print_size((cap * (1 << 20)), " capacity\n");
+ break;
+ }
+ }
+
+ return stride;
+}
+
static int sdram_init(struct dram_info *dram,
- const struct rk3399_sdram_params *sdram_params)
+ struct rk3399_sdram_params *sdram_params)
{
unsigned char dramtype = sdram_params->base.dramtype;
unsigned int ddr_freq = sdram_params->base.ddr_freq;
@@ -1235,6 +1303,8 @@ static int sdram_init(struct dram_info *dram,
set_ddrconfig(chan, sdram_params, channel,
sdram_params->ch[channel].cap_info.ddrconfig);
}
+
+ sdram_params->base.stride = calculate_stride(sdram_params);
dram_all_config(dram, sdram_params);
switch_to_phy_index1(dram, sdram_params);
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 48/92] ram: rk3399: Compute stride for 2 channels
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
stride value from sdram timings can be computed dynamically
based on the determined capacity for the given channel.
Right now these stride values are taken as part of sdram timings
via dtsi, but it possible to use same timings dtsi for given
frequency even though the configured board sdram do support
single channel with different size by dynamically detect the
stride value.
Example, NanoPi NEO4 do have DDR3-1866, but with single channel
and 1GB size with dynamic stride detection it is possible to
use existing rk3399-sdram-ddr3-1866.dtsi whose stride,
number of channels and capacity it support is d efferent.
So, add initial support to calculate the stride value for
2 channels sdram, which is available by default on existing
boards.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 72 ++++++++++++++++++++++++++++-
1 file changed, 71 insertions(+), 1 deletion(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 1acf9efe9c..5985c37f08 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1185,8 +1185,76 @@ static int switch_to_phy_index1(struct dram_info *dram,
return 0;
}
+static unsigned char calculate_stride(struct rk3399_sdram_params *sdram_params)
+{
+ unsigned int stride = sdram_params->base.stride;
+ unsigned int channel, chinfo = 0;
+ unsigned int ch_cap[2] = {0, 0};
+ u64 cap;
+
+ for (channel = 0; channel < 2; channel++) {
+ unsigned int cs0_cap = 0;
+ unsigned int cs1_cap = 0;
+ struct sdram_cap_info *cap_info =
+ &sdram_params->ch[channel].cap_info;
+
+ if (cap_info->col == 0)
+ continue;
+
+ cs0_cap = (1 << (cap_info->cs0_row + cap_info->col +
+ cap_info->bk + cap_info->bw - 20));
+ if (cap_info->rank > 1)
+ cs1_cap = cs0_cap >> (cap_info->cs0_row
+ - cap_info->cs1_row);
+ if (cap_info->row_3_4) {
+ cs0_cap = cs0_cap * 3 / 4;
+ cs1_cap = cs1_cap * 3 / 4;
+ }
+ ch_cap[channel] = cs0_cap + cs1_cap;
+ chinfo |= 1 << channel;
+ }
+
+ /* stride calculation for 2 channels, default gstride type is 256B */
+ if (ch_cap[0] == ch_cap[1]) {
+ cap = ch_cap[0] + ch_cap[1];
+ switch (cap) {
+ /* 512MB */
+ case 512:
+ stride = 0;
+ break;
+ /* 1GB */
+ case 1024:
+ stride = 0x5;
+ break;
+ /*
+ * 768MB + 768MB same as total 2GB memory
+ * useful space: 0-768MB 1GB-1792MB
+ */
+ case 1536:
+ /* 2GB */
+ case 2048:
+ stride = 0x9;
+ break;
+ /* 1536MB + 1536MB */
+ case 3072:
+ stride = 0x11;
+ break;
+ /* 4GB */
+ case 4096:
+ stride = 0xD;
+ break;
+ default:
+ printf("%s: Unable to calculate stride for ", __func__);
+ print_size((cap * (1 << 20)), " capacity\n");
+ break;
+ }
+ }
+
+ return stride;
+}
+
static int sdram_init(struct dram_info *dram,
- const struct rk3399_sdram_params *sdram_params)
+ struct rk3399_sdram_params *sdram_params)
{
unsigned char dramtype = sdram_params->base.dramtype;
unsigned int ddr_freq = sdram_params->base.ddr_freq;
@@ -1235,6 +1303,8 @@ static int sdram_init(struct dram_info *dram,
set_ddrconfig(chan, sdram_params, channel,
sdram_params->ch[channel].cap_info.ddrconfig);
}
+
+ sdram_params->base.stride = calculate_stride(sdram_params);
dram_all_config(dram, sdram_params);
switch_to_phy_index1(dram, sdram_params);
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 49/92] ram: rk3399: Compute stride for 1 channel a
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Add stride computation for the sdram which support
single channel a
This configuration available in NanoPi NEO4 and the
same can work with existing rk3399-sdram-ddr3-1866.dtsi
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 5985c37f08..033b2730a6 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1214,6 +1214,10 @@ static unsigned char calculate_stride(struct rk3399_sdram_params *sdram_params)
chinfo |= 1 << channel;
}
+ /* stride calculation for 1 channel */
+ if (sdram_params->base.num_channels == 1 && chinfo & 1)
+ return 0x17; /* channel a */
+
/* stride calculation for 2 channels, default gstride type is 256B */
if (ch_cap[0] == ch_cap[1]) {
cap = ch_cap[0] + ch_cap[1];
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 49/92] ram: rk3399: Compute stride for 1 channel a
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
Add stride computation for the sdram which support
single channel a
This configuration available in NanoPi NEO4 and the
same can work with existing rk3399-sdram-ddr3-1866.dtsi
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 5985c37f08..033b2730a6 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1214,6 +1214,10 @@ static unsigned char calculate_stride(struct rk3399_sdram_params *sdram_params)
chinfo |= 1 << channel;
}
+ /* stride calculation for 1 channel */
+ if (sdram_params->base.num_channels == 1 && chinfo & 1)
+ return 0x17; /* channel a */
+
/* stride calculation for 2 channels, default gstride type is 256B */
if (ch_cap[0] == ch_cap[1]) {
cap = ch_cap[0] + ch_cap[1];
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 50/92] ram: rk3399: Add rank detection support
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Right now the rk3399 sdram driver assume that the board
has configured with 2 channels, so any possibility to
enable single channel on the same driver will encounter
channel #1 data training failure.
Log:
U-Boot TPL board init
sdram_init: data training failed
rk3399_dmc_init DRAM init failed -5
So, add an algorithm that can capable to compute the active
or configured rank with associated channel like
a) do rank loop to compute the active rank, with associated
channel numbers
b) then, succeed the data training only for configured channel
c) preserve the rank for given channel
d) do channel loop for setting the active channel
e) if given rank is zero or inactive on the specific channel,
clear the timings for the associated channel
f) finally, return error if number of channels is zero
Tested in NanoPI-NEO4 since it support single channel sdram
configuration.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 112 +++++++++++++++++++++-------
1 file changed, 87 insertions(+), 25 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 033b2730a6..b658d7d1ab 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1257,13 +1257,52 @@ static unsigned char calculate_stride(struct rk3399_sdram_params *sdram_params)
return stride;
}
+static void clear_channel_params(struct rk3399_sdram_params *params, u8 channel)
+{
+ params->ch[channel].cap_info.rank = 0;
+ params->ch[channel].cap_info.col = 0;
+ params->ch[channel].cap_info.bk = 0;
+ params->ch[channel].cap_info.bw = 32;
+ params->ch[channel].cap_info.dbw = 32;
+ params->ch[channel].cap_info.row_3_4 = 0;
+ params->ch[channel].cap_info.cs0_row = 0;
+ params->ch[channel].cap_info.cs1_row = 0;
+ params->ch[channel].cap_info.ddrconfig = 0;
+}
+
+static int pctl_init(struct dram_info *dram, struct rk3399_sdram_params *params)
+{
+ int channel;
+ int ret;
+
+ for (channel = 0; channel < 2; channel++) {
+ const struct chan_info *chan = &dram->chan[channel];
+ struct rk3399_cru *cru = dram->cru;
+ struct rk3399_ddr_publ_regs *publ = chan->publ;
+
+ phy_pctrl_reset(cru, channel);
+ phy_dll_bypass_set(publ, params->base.ddr_freq);
+
+ ret = pctl_cfg(dram, chan, channel, params);
+ if (ret < 0) {
+ printf("%s: pctl config failed\n", __func__);
+ return ret;
+ }
+
+ /* start to trigger initialization */
+ pctl_start(dram, params, channel);
+ }
+
+ return 0;
+}
+
static int sdram_init(struct dram_info *dram,
struct rk3399_sdram_params *sdram_params)
{
unsigned char dramtype = sdram_params->base.dramtype;
unsigned int ddr_freq = sdram_params->base.ddr_freq;
- struct rk3399_cru *cru = dram->cru;
- int channel;
+ u32 training_flag = PI_READ_GATE_TRAINING;
+ int channel, ch, rank;
int ret;
debug("Starting SDRAM initialization...\n");
@@ -1275,37 +1314,60 @@ static int sdram_init(struct dram_info *dram,
return -E2BIG;
}
- for (channel = 0; channel < 2; channel++) {
- const struct chan_info *chan = &dram->chan[channel];
- struct rk3399_ddr_publ_regs *publ = chan->publ;
+ for (ch = 0; ch < 2; ch++) {
+ sdram_params->ch[ch].cap_info.rank = 2;
+ for (rank = 2; rank != 0; rank--) {
+ ret = pctl_init(dram, sdram_params);
+ if (ret < 0) {
+ printf("%s: pctl init failed\n", __func__);
+ return ret;
+ }
- phy_pctrl_reset(cru, channel);
- phy_dll_bypass_set(publ, ddr_freq);
+ /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */
+ if (dramtype == LPDDR3)
+ udelay(10);
- if (channel >= sdram_params->base.num_channels)
- continue;
+ sdram_params->ch[ch].cap_info.rank = rank;
- ret = pctl_cfg(dram, chan, channel, sdram_params);
- if (ret < 0) {
- printf("%s: pctl config failed\n", __func__);
- return ret;
- }
+ /*
+ * LPDDR3 CA training msut be trigger before
+ * other training.
+ * DDR3 is not have CA training.
+ */
+ if (sdram_params->base.dramtype == LPDDR3)
+ training_flag |= PI_CA_TRAINING;
- /* start to trigger initialization */
- pctl_start(dram, sdram_params, channel);
+ if (!(data_training(&dram->chan[ch], ch,
+ sdram_params, training_flag)))
+ break;
+ }
+ /* Computed rank with associated channel number */
+ sdram_params->ch[ch].cap_info.rank = rank;
+ }
- /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */
- if (dramtype == LPDDR3)
- udelay(10);
+ sdram_params->base.num_channels = 0;
+ for (channel = 0; channel < 2; channel++) {
+ const struct chan_info *chan = &dram->chan[channel];
+ struct sdram_cap_info *cap_info =
+ &sdram_params->ch[channel].cap_info;
- if (data_training(chan, channel,
- sdram_params, PI_FULL_TRAINING)) {
- printf("%s: data training failed\n", __func__);
- return -EIO;
+ if (cap_info->rank == 0) {
+ clear_channel_params(sdram_params, channel);
+ continue;
+ } else {
+ sdram_params->base.num_channels++;
}
- set_ddrconfig(chan, sdram_params, channel,
- sdram_params->ch[channel].cap_info.ddrconfig);
+ debug("Channel ");
+ debug(channel ? "1: " : "0: ");
+
+ set_ddrconfig(chan, sdram_params, channel, cap_info->ddrconfig);
+ }
+
+ if (sdram_params->base.num_channels == 0) {
+ printf("%s: ", __func__);
+ printf(" - %dMHz failed!\n", sdram_params->base.ddr_freq);
+ return -EINVAL;
}
sdram_params->base.stride = calculate_stride(sdram_params);
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 50/92] ram: rk3399: Add rank detection support
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
Right now the rk3399 sdram driver assume that the board
has configured with 2 channels, so any possibility to
enable single channel on the same driver will encounter
channel #1 data training failure.
Log:
U-Boot TPL board init
sdram_init: data training failed
rk3399_dmc_init DRAM init failed -5
So, add an algorithm that can capable to compute the active
or configured rank with associated channel like
a) do rank loop to compute the active rank, with associated
channel numbers
b) then, succeed the data training only for configured channel
c) preserve the rank for given channel
d) do channel loop for setting the active channel
e) if given rank is zero or inactive on the specific channel,
clear the timings for the associated channel
f) finally, return error if number of channels is zero
Tested in NanoPI-NEO4 since it support single channel sdram
configuration.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 112 +++++++++++++++++++++-------
1 file changed, 87 insertions(+), 25 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 033b2730a6..b658d7d1ab 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1257,13 +1257,52 @@ static unsigned char calculate_stride(struct rk3399_sdram_params *sdram_params)
return stride;
}
+static void clear_channel_params(struct rk3399_sdram_params *params, u8 channel)
+{
+ params->ch[channel].cap_info.rank = 0;
+ params->ch[channel].cap_info.col = 0;
+ params->ch[channel].cap_info.bk = 0;
+ params->ch[channel].cap_info.bw = 32;
+ params->ch[channel].cap_info.dbw = 32;
+ params->ch[channel].cap_info.row_3_4 = 0;
+ params->ch[channel].cap_info.cs0_row = 0;
+ params->ch[channel].cap_info.cs1_row = 0;
+ params->ch[channel].cap_info.ddrconfig = 0;
+}
+
+static int pctl_init(struct dram_info *dram, struct rk3399_sdram_params *params)
+{
+ int channel;
+ int ret;
+
+ for (channel = 0; channel < 2; channel++) {
+ const struct chan_info *chan = &dram->chan[channel];
+ struct rk3399_cru *cru = dram->cru;
+ struct rk3399_ddr_publ_regs *publ = chan->publ;
+
+ phy_pctrl_reset(cru, channel);
+ phy_dll_bypass_set(publ, params->base.ddr_freq);
+
+ ret = pctl_cfg(dram, chan, channel, params);
+ if (ret < 0) {
+ printf("%s: pctl config failed\n", __func__);
+ return ret;
+ }
+
+ /* start to trigger initialization */
+ pctl_start(dram, params, channel);
+ }
+
+ return 0;
+}
+
static int sdram_init(struct dram_info *dram,
struct rk3399_sdram_params *sdram_params)
{
unsigned char dramtype = sdram_params->base.dramtype;
unsigned int ddr_freq = sdram_params->base.ddr_freq;
- struct rk3399_cru *cru = dram->cru;
- int channel;
+ u32 training_flag = PI_READ_GATE_TRAINING;
+ int channel, ch, rank;
int ret;
debug("Starting SDRAM initialization...\n");
@@ -1275,37 +1314,60 @@ static int sdram_init(struct dram_info *dram,
return -E2BIG;
}
- for (channel = 0; channel < 2; channel++) {
- const struct chan_info *chan = &dram->chan[channel];
- struct rk3399_ddr_publ_regs *publ = chan->publ;
+ for (ch = 0; ch < 2; ch++) {
+ sdram_params->ch[ch].cap_info.rank = 2;
+ for (rank = 2; rank != 0; rank--) {
+ ret = pctl_init(dram, sdram_params);
+ if (ret < 0) {
+ printf("%s: pctl init failed\n", __func__);
+ return ret;
+ }
- phy_pctrl_reset(cru, channel);
- phy_dll_bypass_set(publ, ddr_freq);
+ /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */
+ if (dramtype == LPDDR3)
+ udelay(10);
- if (channel >= sdram_params->base.num_channels)
- continue;
+ sdram_params->ch[ch].cap_info.rank = rank;
- ret = pctl_cfg(dram, chan, channel, sdram_params);
- if (ret < 0) {
- printf("%s: pctl config failed\n", __func__);
- return ret;
- }
+ /*
+ * LPDDR3 CA training msut be trigger before
+ * other training.
+ * DDR3 is not have CA training.
+ */
+ if (sdram_params->base.dramtype == LPDDR3)
+ training_flag |= PI_CA_TRAINING;
- /* start to trigger initialization */
- pctl_start(dram, sdram_params, channel);
+ if (!(data_training(&dram->chan[ch], ch,
+ sdram_params, training_flag)))
+ break;
+ }
+ /* Computed rank with associated channel number */
+ sdram_params->ch[ch].cap_info.rank = rank;
+ }
- /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */
- if (dramtype == LPDDR3)
- udelay(10);
+ sdram_params->base.num_channels = 0;
+ for (channel = 0; channel < 2; channel++) {
+ const struct chan_info *chan = &dram->chan[channel];
+ struct sdram_cap_info *cap_info =
+ &sdram_params->ch[channel].cap_info;
- if (data_training(chan, channel,
- sdram_params, PI_FULL_TRAINING)) {
- printf("%s: data training failed\n", __func__);
- return -EIO;
+ if (cap_info->rank == 0) {
+ clear_channel_params(sdram_params, channel);
+ continue;
+ } else {
+ sdram_params->base.num_channels++;
}
- set_ddrconfig(chan, sdram_params, channel,
- sdram_params->ch[channel].cap_info.ddrconfig);
+ debug("Channel ");
+ debug(channel ? "1: " : "0: ");
+
+ set_ddrconfig(chan, sdram_params, channel, cap_info->ddrconfig);
+ }
+
+ if (sdram_params->base.num_channels == 0) {
+ printf("%s: ", __func__);
+ printf(" - %dMHz failed!\n", sdram_params->base.ddr_freq);
+ return -EINVAL;
}
sdram_params->base.stride = calculate_stride(sdram_params);
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 51/92] ram: rk3399: Enable sdram debug functions
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
This would help to debug the sdram base parameters while
debugging existing chip or while supporting new sdram type.
It require explicit enablement of CONFIG_RAM_ROCKCHIP_DEBUG
for showing the debug prints.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index b658d7d1ab..ce38f72374 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1254,6 +1254,8 @@ static unsigned char calculate_stride(struct rk3399_sdram_params *sdram_params)
}
}
+ sdram_print_stride(stride);
+
return stride;
}
@@ -1361,11 +1363,14 @@ static int sdram_init(struct dram_info *dram,
debug("Channel ");
debug(channel ? "1: " : "0: ");
+ sdram_print_ddr_info(cap_info, &sdram_params->base);
+
set_ddrconfig(chan, sdram_params, channel, cap_info->ddrconfig);
}
if (sdram_params->base.num_channels == 0) {
printf("%s: ", __func__);
+ sdram_print_dram_type(sdram_params->base.dramtype);
printf(" - %dMHz failed!\n", sdram_params->base.ddr_freq);
return -EINVAL;
}
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 51/92] ram: rk3399: Enable sdram debug functions
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
This would help to debug the sdram base parameters while
debugging existing chip or while supporting new sdram type.
It require explicit enablement of CONFIG_RAM_ROCKCHIP_DEBUG
for showing the debug prints.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index b658d7d1ab..ce38f72374 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1254,6 +1254,8 @@ static unsigned char calculate_stride(struct rk3399_sdram_params *sdram_params)
}
}
+ sdram_print_stride(stride);
+
return stride;
}
@@ -1361,11 +1363,14 @@ static int sdram_init(struct dram_info *dram,
debug("Channel ");
debug(channel ? "1: " : "0: ");
+ sdram_print_ddr_info(cap_info, &sdram_params->base);
+
set_ddrconfig(chan, sdram_params, channel, cap_info->ddrconfig);
}
if (sdram_params->base.num_channels == 0) {
printf("%s: ", __func__);
+ sdram_print_dram_type(sdram_params->base.dramtype);
printf(" - %dMHz failed!\n", sdram_params->base.ddr_freq);
return -EINVAL;
}
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 52/92] rockchip: dts: rk3399: nanopi-neo4: Use DDR3-1866 dtsi
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Use DDR3-1866 2GB ddr timings dtsi for 1GB NanoPi Neo4 board.
Since sdram rk3399 support dynamic stride and rank detection it
can able to detect 1GB ddr eventough the timings are meant for
dual channel, 2GB size.
Bootchain after and before this change are:
TPL -> SPL -> U-Boot proper
rkbin -> SPL -> U-Boot proper
This certainly fix the second channel data training initialization
since we have dynamic rank, stride where second channel capabilities
are clear or memset to 0.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi b/arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi
index 7d22528f49..eb0aca4758 100644
--- a/arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi
@@ -4,3 +4,4 @@
*/
#include "rk3399-nanopi4-u-boot.dtsi"
+#include "rk3399-sdram-ddr3-1866.dtsi"
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 52/92] rockchip: dts: rk3399: nanopi-neo4: Use DDR3-1866 dtsi
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
Use DDR3-1866 2GB ddr timings dtsi for 1GB NanoPi Neo4 board.
Since sdram rk3399 support dynamic stride and rank detection it
can able to detect 1GB ddr eventough the timings are meant for
dual channel, 2GB size.
Bootchain after and before this change are:
TPL -> SPL -> U-Boot proper
rkbin -> SPL -> U-Boot proper
This certainly fix the second channel data training initialization
since we have dynamic rank, stride where second channel capabilities
are clear or memset to 0.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi b/arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi
index 7d22528f49..eb0aca4758 100644
--- a/arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi
@@ -4,3 +4,4 @@
*/
#include "rk3399-nanopi4-u-boot.dtsi"
+#include "rk3399-sdram-ddr3-1866.dtsi"
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 53/92] clk: rockchip: rk3399: Fix check patch warnings and checks
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
- CHECK: spaces preferred around that '*'
- CHECK: spaces preferred around that '/'
- CHECK: space preferred before that '|'
- WARNING: macros should not use a trailing semicolon
- CHECK: Unnecessary parentheses around 'fbdiv <= min_fbdiv'
- CHECK: Unnecessary parentheses around 'parent->id == SCLK_MAC'
- CHECK: Unnecessary parentheses around 'parent->dev == clk->dev'
- WARNING: line over 80 characters
- CHECK: Prefer kernel type 'u8' over 'uint8_t'
- Add proper macro definitions arrangements
Note: there are still line over 80 characters and other warnings but
fixing those making code look unreadable, so I kept it as it is.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
drivers/clk/rockchip/clk_rk3399.c | 68 ++++++++++++++-----------------
1 file changed, 31 insertions(+), 37 deletions(-)
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index aa6a8ad1c9..5d1ad94e85 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -38,8 +38,8 @@ struct pll_div {
};
#define RATE_TO_DIV(input_rate, output_rate) \
- ((input_rate) / (output_rate) - 1);
-#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
+ ((input_rate) / (output_rate) - 1)
+#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
.refdiv = _refdiv,\
@@ -53,15 +53,15 @@ static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2);
static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1);
#endif
-static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600*MHz, 3, 1, 1);
-static const struct pll_div apll_l_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1);
+static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600 * MHz, 3, 1, 1);
+static const struct pll_div apll_l_600_cfg = PLL_DIVISORS(600 * MHz, 1, 2, 1);
static const struct pll_div *apll_l_cfgs[] = {
[APLL_L_1600_MHZ] = &apll_l_1600_cfg,
[APLL_L_600_MHZ] = &apll_l_600_cfg,
};
-static const struct pll_div apll_b_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1);
+static const struct pll_div apll_b_600_cfg = PLL_DIVISORS(600 * MHz, 1, 2, 1);
static const struct pll_div *apll_b_cfgs[] = {
[APLL_B_600_MHZ] = &apll_b_600_cfg,
};
@@ -393,7 +393,7 @@ static int pll_para_config(u32 freq_hz, struct pll_div *div)
fref_khz = ref_khz / refdiv;
fbdiv = vco_khz / fref_khz;
- if ((fbdiv >= max_fbdiv) || (fbdiv <= min_fbdiv))
+ if (fbdiv >= max_fbdiv || fbdiv <= min_fbdiv)
continue;
diff_khz = vco_khz - fbdiv * fref_khz;
if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) {
@@ -409,7 +409,7 @@ static int pll_para_config(u32 freq_hz, struct pll_div *div)
div->fbdiv = fbdiv;
}
- if (best_diff_khz > 4 * (MHz/KHz)) {
+ if (best_diff_khz > 4 * (MHz / KHz)) {
printf("%s: Failed to match output frequency %u, "
"difference is %u Hz,exceed 4MHZ\n", __func__, freq_hz,
best_diff_khz * KHz);
@@ -489,28 +489,21 @@ void rk3399_configure_cpu_b(struct rk3399_cru *cru,
}
#define I2C_CLK_REG_MASK(bus) \
- (I2C_DIV_CON_MASK << \
- CLK_I2C ##bus## _DIV_CON_SHIFT | \
- CLK_I2C_PLL_SEL_MASK << \
- CLK_I2C ##bus## _PLL_SEL_SHIFT)
+ (I2C_DIV_CON_MASK << CLK_I2C ##bus## _DIV_CON_SHIFT | \
+ CLK_I2C_PLL_SEL_MASK << CLK_I2C ##bus## _PLL_SEL_SHIFT)
#define I2C_CLK_REG_VALUE(bus, clk_div) \
- ((clk_div - 1) << \
- CLK_I2C ##bus## _DIV_CON_SHIFT | \
- CLK_I2C_PLL_SEL_GPLL << \
- CLK_I2C ##bus## _PLL_SEL_SHIFT)
+ ((clk_div - 1) << CLK_I2C ##bus## _DIV_CON_SHIFT | \
+ CLK_I2C_PLL_SEL_GPLL << CLK_I2C ##bus## _PLL_SEL_SHIFT)
#define I2C_CLK_DIV_VALUE(con, bus) \
- (con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & \
- I2C_DIV_CON_MASK;
+ ((con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & I2C_DIV_CON_MASK)
#define I2C_PMUCLK_REG_MASK(bus) \
- (I2C_DIV_CON_MASK << \
- CLK_I2C ##bus## _DIV_CON_SHIFT)
+ (I2C_DIV_CON_MASK << CLK_I2C ##bus## _DIV_CON_SHIFT)
#define I2C_PMUCLK_REG_VALUE(bus, clk_div) \
- ((clk_div - 1) << \
- CLK_I2C ##bus## _DIV_CON_SHIFT)
+ ((clk_div - 1) << CLK_I2C ##bus## _DIV_CON_SHIFT)
static ulong rk3399_i2c_get_clk(struct rk3399_cru *cru, ulong clk_id)
{
@@ -597,9 +590,9 @@ static ulong rk3399_i2c_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)
*/
struct spi_clkreg {
- uint8_t reg; /* CLKSEL_CON[reg] register in CRU */
- uint8_t div_shift;
- uint8_t sel_shift;
+ u8 reg; /* CLKSEL_CON[reg] register in CRU */
+ u8 div_shift;
+ u8 sel_shift;
};
/*
@@ -678,7 +671,7 @@ static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)
static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz)
{
struct pll_div vpll_config = {0};
- int aclk_vop = 198*MHz;
+ int aclk_vop = 198 * MHz;
void *aclkreg_addr, *dclkreg_addr;
u32 div;
@@ -710,7 +703,7 @@ static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz)
rkclk_set_pll(&cru->vpll_con[0], &vpll_config);
rk_clrsetreg(dclkreg_addr,
- DCLK_VOP_DCLK_SEL_MASK | DCLK_VOP_PLL_SEL_MASK|
+ DCLK_VOP_DCLK_SEL_MASK | DCLK_VOP_PLL_SEL_MASK |
DCLK_VOP_DIV_CON_MASK,
DCLK_VOP_DCLK_SEL_DIVOUT << DCLK_VOP_DCLK_SEL_SHIFT |
DCLK_VOP_PLL_SEL_VPLL << DCLK_VOP_PLL_SEL_SHIFT |
@@ -750,7 +743,7 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,
ulong clk_id, ulong set_rate)
{
int src_clk_div;
- int aclk_emmc = 198*MHz;
+ int aclk_emmc = 198 * MHz;
switch (clk_id) {
case HCLK_SDMMC:
@@ -776,7 +769,7 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,
break;
case SCLK_EMMC:
/* Select aclk_emmc source from GPLL */
- src_clk_div = DIV_ROUND_UP(GPLL_HZ , aclk_emmc);
+ src_clk_div = DIV_ROUND_UP(GPLL_HZ, aclk_emmc);
assert(src_clk_div - 1 < 32);
rk_clrsetreg(&cru->clksel_con[21],
@@ -834,23 +827,23 @@ static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru,
/* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
switch (set_rate) {
- case 200*MHz:
+ case 200 * MHz:
dpll_cfg = (struct pll_div)
{.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1};
break;
- case 300*MHz:
+ case 300 * MHz:
dpll_cfg = (struct pll_div)
{.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1};
break;
- case 666*MHz:
+ case 666 * MHz:
dpll_cfg = (struct pll_div)
{.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1};
break;
- case 800*MHz:
+ case 800 * MHz:
dpll_cfg = (struct pll_div)
{.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1};
break;
- case 933*MHz:
+ case 933 * MHz:
dpll_cfg = (struct pll_div)
{.refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1};
break;
@@ -916,7 +909,6 @@ static ulong rk3399_clk_get_rate(struct clk *clk)
case SCLK_UART2:
case SCLK_UART3:
return 24000000;
- break;
case PCLK_HDMI_CTRL:
break;
case DCLK_VOP0:
@@ -1014,7 +1006,8 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
return ret;
}
-static int __maybe_unused rk3399_gmac_set_parent(struct clk *clk, struct clk *parent)
+static int __maybe_unused rk3399_gmac_set_parent(struct clk *clk,
+ struct clk *parent)
{
struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
const char *clock_output_name;
@@ -1024,7 +1017,7 @@ static int __maybe_unused rk3399_gmac_set_parent(struct clk *clk, struct clk *pa
* If the requested parent is in the same clock-controller and
* the id is SCLK_MAC ("clk_gmac"), switch to the internal clock.
*/
- if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC)) {
+ if (parent->dev == clk->dev && parent->id == SCLK_MAC) {
debug("%s: switching RGMII to SCLK_MAC\n", __func__);
rk_clrreg(&priv->cru->clksel_con[19], BIT(4));
return 0;
@@ -1049,7 +1042,8 @@ static int __maybe_unused rk3399_gmac_set_parent(struct clk *clk, struct clk *pa
return -EINVAL;
}
-static int __maybe_unused rk3399_clk_set_parent(struct clk *clk, struct clk *parent)
+static int __maybe_unused rk3399_clk_set_parent(struct clk *clk,
+ struct clk *parent)
{
switch (clk->id) {
case SCLK_RMII_SRC:
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 53/92] clk: rockchip: rk3399: Fix check patch warnings and checks
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
- CHECK: spaces preferred around that '*'
- CHECK: spaces preferred around that '/'
- CHECK: space preferred before that '|'
- WARNING: macros should not use a trailing semicolon
- CHECK: Unnecessary parentheses around 'fbdiv <= min_fbdiv'
- CHECK: Unnecessary parentheses around 'parent->id == SCLK_MAC'
- CHECK: Unnecessary parentheses around 'parent->dev == clk->dev'
- WARNING: line over 80 characters
- CHECK: Prefer kernel type 'u8' over 'uint8_t'
- Add proper macro definitions arrangements
Note: there are still line over 80 characters and other warnings but
fixing those making code look unreadable, so I kept it as it is.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
drivers/clk/rockchip/clk_rk3399.c | 68 ++++++++++++++-----------------
1 file changed, 31 insertions(+), 37 deletions(-)
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index aa6a8ad1c9..5d1ad94e85 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -38,8 +38,8 @@ struct pll_div {
};
#define RATE_TO_DIV(input_rate, output_rate) \
- ((input_rate) / (output_rate) - 1);
-#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
+ ((input_rate) / (output_rate) - 1)
+#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
.refdiv = _refdiv,\
@@ -53,15 +53,15 @@ static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2);
static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1);
#endif
-static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600*MHz, 3, 1, 1);
-static const struct pll_div apll_l_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1);
+static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600 * MHz, 3, 1, 1);
+static const struct pll_div apll_l_600_cfg = PLL_DIVISORS(600 * MHz, 1, 2, 1);
static const struct pll_div *apll_l_cfgs[] = {
[APLL_L_1600_MHZ] = &apll_l_1600_cfg,
[APLL_L_600_MHZ] = &apll_l_600_cfg,
};
-static const struct pll_div apll_b_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1);
+static const struct pll_div apll_b_600_cfg = PLL_DIVISORS(600 * MHz, 1, 2, 1);
static const struct pll_div *apll_b_cfgs[] = {
[APLL_B_600_MHZ] = &apll_b_600_cfg,
};
@@ -393,7 +393,7 @@ static int pll_para_config(u32 freq_hz, struct pll_div *div)
fref_khz = ref_khz / refdiv;
fbdiv = vco_khz / fref_khz;
- if ((fbdiv >= max_fbdiv) || (fbdiv <= min_fbdiv))
+ if (fbdiv >= max_fbdiv || fbdiv <= min_fbdiv)
continue;
diff_khz = vco_khz - fbdiv * fref_khz;
if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) {
@@ -409,7 +409,7 @@ static int pll_para_config(u32 freq_hz, struct pll_div *div)
div->fbdiv = fbdiv;
}
- if (best_diff_khz > 4 * (MHz/KHz)) {
+ if (best_diff_khz > 4 * (MHz / KHz)) {
printf("%s: Failed to match output frequency %u, "
"difference is %u Hz,exceed 4MHZ\n", __func__, freq_hz,
best_diff_khz * KHz);
@@ -489,28 +489,21 @@ void rk3399_configure_cpu_b(struct rk3399_cru *cru,
}
#define I2C_CLK_REG_MASK(bus) \
- (I2C_DIV_CON_MASK << \
- CLK_I2C ##bus## _DIV_CON_SHIFT | \
- CLK_I2C_PLL_SEL_MASK << \
- CLK_I2C ##bus## _PLL_SEL_SHIFT)
+ (I2C_DIV_CON_MASK << CLK_I2C ##bus## _DIV_CON_SHIFT | \
+ CLK_I2C_PLL_SEL_MASK << CLK_I2C ##bus## _PLL_SEL_SHIFT)
#define I2C_CLK_REG_VALUE(bus, clk_div) \
- ((clk_div - 1) << \
- CLK_I2C ##bus## _DIV_CON_SHIFT | \
- CLK_I2C_PLL_SEL_GPLL << \
- CLK_I2C ##bus## _PLL_SEL_SHIFT)
+ ((clk_div - 1) << CLK_I2C ##bus## _DIV_CON_SHIFT | \
+ CLK_I2C_PLL_SEL_GPLL << CLK_I2C ##bus## _PLL_SEL_SHIFT)
#define I2C_CLK_DIV_VALUE(con, bus) \
- (con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & \
- I2C_DIV_CON_MASK;
+ ((con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & I2C_DIV_CON_MASK)
#define I2C_PMUCLK_REG_MASK(bus) \
- (I2C_DIV_CON_MASK << \
- CLK_I2C ##bus## _DIV_CON_SHIFT)
+ (I2C_DIV_CON_MASK << CLK_I2C ##bus## _DIV_CON_SHIFT)
#define I2C_PMUCLK_REG_VALUE(bus, clk_div) \
- ((clk_div - 1) << \
- CLK_I2C ##bus## _DIV_CON_SHIFT)
+ ((clk_div - 1) << CLK_I2C ##bus## _DIV_CON_SHIFT)
static ulong rk3399_i2c_get_clk(struct rk3399_cru *cru, ulong clk_id)
{
@@ -597,9 +590,9 @@ static ulong rk3399_i2c_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)
*/
struct spi_clkreg {
- uint8_t reg; /* CLKSEL_CON[reg] register in CRU */
- uint8_t div_shift;
- uint8_t sel_shift;
+ u8 reg; /* CLKSEL_CON[reg] register in CRU */
+ u8 div_shift;
+ u8 sel_shift;
};
/*
@@ -678,7 +671,7 @@ static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)
static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz)
{
struct pll_div vpll_config = {0};
- int aclk_vop = 198*MHz;
+ int aclk_vop = 198 * MHz;
void *aclkreg_addr, *dclkreg_addr;
u32 div;
@@ -710,7 +703,7 @@ static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz)
rkclk_set_pll(&cru->vpll_con[0], &vpll_config);
rk_clrsetreg(dclkreg_addr,
- DCLK_VOP_DCLK_SEL_MASK | DCLK_VOP_PLL_SEL_MASK|
+ DCLK_VOP_DCLK_SEL_MASK | DCLK_VOP_PLL_SEL_MASK |
DCLK_VOP_DIV_CON_MASK,
DCLK_VOP_DCLK_SEL_DIVOUT << DCLK_VOP_DCLK_SEL_SHIFT |
DCLK_VOP_PLL_SEL_VPLL << DCLK_VOP_PLL_SEL_SHIFT |
@@ -750,7 +743,7 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,
ulong clk_id, ulong set_rate)
{
int src_clk_div;
- int aclk_emmc = 198*MHz;
+ int aclk_emmc = 198 * MHz;
switch (clk_id) {
case HCLK_SDMMC:
@@ -776,7 +769,7 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,
break;
case SCLK_EMMC:
/* Select aclk_emmc source from GPLL */
- src_clk_div = DIV_ROUND_UP(GPLL_HZ , aclk_emmc);
+ src_clk_div = DIV_ROUND_UP(GPLL_HZ, aclk_emmc);
assert(src_clk_div - 1 < 32);
rk_clrsetreg(&cru->clksel_con[21],
@@ -834,23 +827,23 @@ static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru,
/* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
switch (set_rate) {
- case 200*MHz:
+ case 200 * MHz:
dpll_cfg = (struct pll_div)
{.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1};
break;
- case 300*MHz:
+ case 300 * MHz:
dpll_cfg = (struct pll_div)
{.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1};
break;
- case 666*MHz:
+ case 666 * MHz:
dpll_cfg = (struct pll_div)
{.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1};
break;
- case 800*MHz:
+ case 800 * MHz:
dpll_cfg = (struct pll_div)
{.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1};
break;
- case 933*MHz:
+ case 933 * MHz:
dpll_cfg = (struct pll_div)
{.refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1};
break;
@@ -916,7 +909,6 @@ static ulong rk3399_clk_get_rate(struct clk *clk)
case SCLK_UART2:
case SCLK_UART3:
return 24000000;
- break;
case PCLK_HDMI_CTRL:
break;
case DCLK_VOP0:
@@ -1014,7 +1006,8 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
return ret;
}
-static int __maybe_unused rk3399_gmac_set_parent(struct clk *clk, struct clk *parent)
+static int __maybe_unused rk3399_gmac_set_parent(struct clk *clk,
+ struct clk *parent)
{
struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
const char *clock_output_name;
@@ -1024,7 +1017,7 @@ static int __maybe_unused rk3399_gmac_set_parent(struct clk *clk, struct clk *pa
* If the requested parent is in the same clock-controller and
* the id is SCLK_MAC ("clk_gmac"), switch to the internal clock.
*/
- if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC)) {
+ if (parent->dev == clk->dev && parent->id == SCLK_MAC) {
debug("%s: switching RGMII to SCLK_MAC\n", __func__);
rk_clrreg(&priv->cru->clksel_con[19], BIT(4));
return 0;
@@ -1049,7 +1042,8 @@ static int __maybe_unused rk3399_gmac_set_parent(struct clk *clk, struct clk *pa
return -EINVAL;
}
-static int __maybe_unused rk3399_clk_set_parent(struct clk *clk, struct clk *parent)
+static int __maybe_unused rk3399_clk_set_parent(struct clk *clk,
+ struct clk *parent)
{
switch (clk->id) {
case SCLK_RMII_SRC:
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 54/92] clk: rockchip: rk3399: Set 50MHz ddr clock
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Add support for setting 50MHz ddr clock.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
drivers/clk/rockchip/clk_rk3399.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 5d1ad94e85..1de21c9f3e 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -827,6 +827,10 @@ static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru,
/* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
switch (set_rate) {
+ case 50 * MHz:
+ dpll_cfg = (struct pll_div)
+ {.refdiv = 1, .fbdiv = 12, .postdiv1 = 3, .postdiv2 = 2};
+ break;
case 200 * MHz:
dpll_cfg = (struct pll_div)
{.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1};
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 54/92] clk: rockchip: rk3399: Set 50MHz ddr clock
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
Add support for setting 50MHz ddr clock.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
drivers/clk/rockchip/clk_rk3399.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 5d1ad94e85..1de21c9f3e 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -827,6 +827,10 @@ static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru,
/* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
switch (set_rate) {
+ case 50 * MHz:
+ dpll_cfg = (struct pll_div)
+ {.refdiv = 1, .fbdiv = 12, .postdiv1 = 3, .postdiv2 = 2};
+ break;
case 200 * MHz:
dpll_cfg = (struct pll_div)
{.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1};
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 55/92] clk: rockchip: rk3399: Set 400MHz ddr clock
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Add support for setting 400MHz ddr clock.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
drivers/clk/rockchip/clk_rk3399.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 1de21c9f3e..79007b8682 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -839,6 +839,10 @@ static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru,
dpll_cfg = (struct pll_div)
{.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1};
break;
+ case 400 * MHz:
+ dpll_cfg = (struct pll_div)
+ {.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1};
+ break;
case 666 * MHz:
dpll_cfg = (struct pll_div)
{.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1};
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 55/92] clk: rockchip: rk3399: Set 400MHz ddr clock
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
Add support for setting 400MHz ddr clock.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
drivers/clk/rockchip/clk_rk3399.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 1de21c9f3e..79007b8682 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -839,6 +839,10 @@ static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru,
dpll_cfg = (struct pll_div)
{.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1};
break;
+ case 400 * MHz:
+ dpll_cfg = (struct pll_div)
+ {.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1};
+ break;
case 666 * MHz:
dpll_cfg = (struct pll_div)
{.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1};
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 56/92] ram: rk3399: Add spaces in pctl_cfg
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:50 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Trivial patch, add proper spaces in pctl_cfg.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index ce38f72374..7251532ad0 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -559,8 +559,10 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
copy_to_reg(&denali_ctl[1], ¶ms_ctl[1],
sizeof(struct rk3399_ddr_pctl_regs) - 4);
writel(params_ctl[0], &denali_ctl[0]);
+
copy_to_reg(denali_pi, &sdram_params->pi_regs.denali_pi[0],
sizeof(struct rk3399_ddr_pi_regs));
+
/* rank count need to set for init */
set_memory_map(chan, channel, sdram_params);
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 56/92] ram: rk3399: Add spaces in pctl_cfg
@ 2019-06-11 14:50 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:50 UTC (permalink / raw)
To: u-boot
Trivial patch, add proper spaces in pctl_cfg.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index ce38f72374..7251532ad0 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -559,8 +559,10 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
copy_to_reg(&denali_ctl[1], ¶ms_ctl[1],
sizeof(struct rk3399_ddr_pctl_regs) - 4);
writel(params_ctl[0], &denali_ctl[0]);
+
copy_to_reg(denali_pi, &sdram_params->pi_regs.denali_pi[0],
sizeof(struct rk3399_ddr_pi_regs));
+
/* rank count need to set for init */
set_memory_map(chan, channel, sdram_params);
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 57/92] ram: rk3399: Configure phy IO in ds odt
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:51 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Some dramtypes like lpddr4 initialization would required to
configure phy IO even after pctl_cfg and after set_ds_odt.
For those cases the set_ds_odt would be an initial call to
setup the phy.
To satisfy all the cases, trigger phy IO from set_ds_odt.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 327 ++++++++++++++--------------
1 file changed, 162 insertions(+), 165 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 7251532ad0..a5fa41e498 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -189,6 +189,166 @@ static void set_memory_map(const struct chan_info *chan, u32 channel,
writel(0x2EC7FFFF, &denali_pi[34]);
}
+static int phy_io_config(const struct chan_info *chan,
+ const struct rk3399_sdram_params *sdram_params)
+{
+ u32 *denali_phy = chan->publ->denali_phy;
+ u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac;
+ u32 mode_sel;
+ u32 reg_value;
+ u32 drv_value, odt_value;
+ u32 speed;
+
+ /* vref setting */
+ if (sdram_params->base.dramtype == LPDDR4) {
+ /* LPDDR4 */
+ vref_mode_dq = 0x6;
+ vref_value_dq = 0x1f;
+ vref_mode_ac = 0x6;
+ vref_value_ac = 0x1f;
+ } else if (sdram_params->base.dramtype == LPDDR3) {
+ if (sdram_params->base.odt == 1) {
+ vref_mode_dq = 0x5; /* LPDDR3 ODT */
+ drv_value = (readl(&denali_phy[6]) >> 12) & 0xf;
+ odt_value = (readl(&denali_phy[6]) >> 4) & 0xf;
+ if (drv_value == PHY_DRV_ODT_48) {
+ switch (odt_value) {
+ case PHY_DRV_ODT_240:
+ vref_value_dq = 0x16;
+ break;
+ case PHY_DRV_ODT_120:
+ vref_value_dq = 0x26;
+ break;
+ case PHY_DRV_ODT_60:
+ vref_value_dq = 0x36;
+ break;
+ default:
+ debug("Invalid ODT value.\n");
+ return -EINVAL;
+ }
+ } else if (drv_value == PHY_DRV_ODT_40) {
+ switch (odt_value) {
+ case PHY_DRV_ODT_240:
+ vref_value_dq = 0x19;
+ break;
+ case PHY_DRV_ODT_120:
+ vref_value_dq = 0x23;
+ break;
+ case PHY_DRV_ODT_60:
+ vref_value_dq = 0x31;
+ break;
+ default:
+ debug("Invalid ODT value.\n");
+ return -EINVAL;
+ }
+ } else if (drv_value == PHY_DRV_ODT_34_3) {
+ switch (odt_value) {
+ case PHY_DRV_ODT_240:
+ vref_value_dq = 0x17;
+ break;
+ case PHY_DRV_ODT_120:
+ vref_value_dq = 0x20;
+ break;
+ case PHY_DRV_ODT_60:
+ vref_value_dq = 0x2e;
+ break;
+ default:
+ debug("Invalid ODT value.\n");
+ return -EINVAL;
+ }
+ } else {
+ debug("Invalid DRV value.\n");
+ return -EINVAL;
+ }
+ } else {
+ vref_mode_dq = 0x2; /* LPDDR3 */
+ vref_value_dq = 0x1f;
+ }
+ vref_mode_ac = 0x2;
+ vref_value_ac = 0x1f;
+ } else if (sdram_params->base.dramtype == DDR3) {
+ /* DDR3L */
+ vref_mode_dq = 0x1;
+ vref_value_dq = 0x1f;
+ vref_mode_ac = 0x1;
+ vref_value_ac = 0x1f;
+ } else {
+ debug("Unknown DRAM type.\n");
+ return -EINVAL;
+ }
+
+ reg_value = (vref_mode_dq << 9) | (0x1 << 8) | vref_value_dq;
+
+ /* PHY_913 PHY_PAD_VREF_CTRL_DQ_0 12bits offset_8 */
+ clrsetbits_le32(&denali_phy[913], 0xfff << 8, reg_value << 8);
+ /* PHY_914 PHY_PAD_VREF_CTRL_DQ_1 12bits offset_0 */
+ clrsetbits_le32(&denali_phy[914], 0xfff, reg_value);
+ /* PHY_914 PHY_PAD_VREF_CTRL_DQ_2 12bits offset_16 */
+ clrsetbits_le32(&denali_phy[914], 0xfff << 16, reg_value << 16);
+ /* PHY_915 PHY_PAD_VREF_CTRL_DQ_3 12bits offset_0 */
+ clrsetbits_le32(&denali_phy[915], 0xfff, reg_value);
+
+ reg_value = (vref_mode_ac << 9) | (0x1 << 8) | vref_value_ac;
+
+ /* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */
+ clrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16);
+
+ if (sdram_params->base.dramtype == LPDDR4)
+ mode_sel = 0x6;
+ else if (sdram_params->base.dramtype == LPDDR3)
+ mode_sel = 0x0;
+ else if (sdram_params->base.dramtype == DDR3)
+ mode_sel = 0x1;
+ else
+ return -EINVAL;
+
+ /* PHY_924 PHY_PAD_FDBK_DRIVE */
+ clrsetbits_le32(&denali_phy[924], 0x7 << 15, mode_sel << 15);
+ /* PHY_926 PHY_PAD_DATA_DRIVE */
+ clrsetbits_le32(&denali_phy[926], 0x7 << 6, mode_sel << 6);
+ /* PHY_927 PHY_PAD_DQS_DRIVE */
+ clrsetbits_le32(&denali_phy[927], 0x7 << 6, mode_sel << 6);
+ /* PHY_928 PHY_PAD_ADDR_DRIVE */
+ clrsetbits_le32(&denali_phy[928], 0x7 << 14, mode_sel << 14);
+ /* PHY_929 PHY_PAD_CLK_DRIVE */
+ clrsetbits_le32(&denali_phy[929], 0x7 << 14, mode_sel << 14);
+ /* PHY_935 PHY_PAD_CKE_DRIVE */
+ clrsetbits_le32(&denali_phy[935], 0x7 << 14, mode_sel << 14);
+ /* PHY_937 PHY_PAD_RST_DRIVE */
+ clrsetbits_le32(&denali_phy[937], 0x7 << 14, mode_sel << 14);
+ /* PHY_939 PHY_PAD_CS_DRIVE */
+ clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14);
+
+ /* speed setting */
+ if (sdram_params->base.ddr_freq < 400)
+ speed = 0x0;
+ else if (sdram_params->base.ddr_freq < 800)
+ speed = 0x1;
+ else if (sdram_params->base.ddr_freq < 1200)
+ speed = 0x2;
+ else
+ speed = 0x3;
+
+ /* PHY_924 PHY_PAD_FDBK_DRIVE */
+ clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21);
+ /* PHY_926 PHY_PAD_DATA_DRIVE */
+ clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9);
+ /* PHY_927 PHY_PAD_DQS_DRIVE */
+ clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9);
+ /* PHY_928 PHY_PAD_ADDR_DRIVE */
+ clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17);
+ /* PHY_929 PHY_PAD_CLK_DRIVE */
+ clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17);
+ /* PHY_935 PHY_PAD_CKE_DRIVE */
+ clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17);
+ /* PHY_937 PHY_PAD_RST_DRIVE */
+ clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17);
+ /* PHY_939 PHY_PAD_CS_DRIVE */
+ clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17);
+
+ return 0;
+}
+
static void set_ds_odt(const struct chan_info *chan,
const struct rk3399_sdram_params *sdram_params)
{
@@ -333,6 +493,8 @@ static void set_ds_odt(const struct chan_info *chan,
/* phy_pad_fdbk_term 1bit DENALI_PHY_930 offset_17 */
clrsetbits_le32(&denali_phy[930], 0x1 << 17, reg_value);
+
+ phy_io_config(chan, sdram_params);
}
static void pctl_start(struct dram_info *dram,
@@ -381,166 +543,6 @@ static void pctl_start(struct dram_info *dram,
dram->pwrup_srefresh_exit[channel]);
}
-static int phy_io_config(const struct chan_info *chan,
- const struct rk3399_sdram_params *sdram_params)
-{
- u32 *denali_phy = chan->publ->denali_phy;
- u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac;
- u32 mode_sel;
- u32 reg_value;
- u32 drv_value, odt_value;
- u32 speed;
-
- /* vref setting */
- if (sdram_params->base.dramtype == LPDDR4) {
- /* LPDDR4 */
- vref_mode_dq = 0x6;
- vref_value_dq = 0x1f;
- vref_mode_ac = 0x6;
- vref_value_ac = 0x1f;
- } else if (sdram_params->base.dramtype == LPDDR3) {
- if (sdram_params->base.odt == 1) {
- vref_mode_dq = 0x5; /* LPDDR3 ODT */
- drv_value = (readl(&denali_phy[6]) >> 12) & 0xf;
- odt_value = (readl(&denali_phy[6]) >> 4) & 0xf;
- if (drv_value == PHY_DRV_ODT_48) {
- switch (odt_value) {
- case PHY_DRV_ODT_240:
- vref_value_dq = 0x16;
- break;
- case PHY_DRV_ODT_120:
- vref_value_dq = 0x26;
- break;
- case PHY_DRV_ODT_60:
- vref_value_dq = 0x36;
- break;
- default:
- debug("Invalid ODT value.\n");
- return -EINVAL;
- }
- } else if (drv_value == PHY_DRV_ODT_40) {
- switch (odt_value) {
- case PHY_DRV_ODT_240:
- vref_value_dq = 0x19;
- break;
- case PHY_DRV_ODT_120:
- vref_value_dq = 0x23;
- break;
- case PHY_DRV_ODT_60:
- vref_value_dq = 0x31;
- break;
- default:
- debug("Invalid ODT value.\n");
- return -EINVAL;
- }
- } else if (drv_value == PHY_DRV_ODT_34_3) {
- switch (odt_value) {
- case PHY_DRV_ODT_240:
- vref_value_dq = 0x17;
- break;
- case PHY_DRV_ODT_120:
- vref_value_dq = 0x20;
- break;
- case PHY_DRV_ODT_60:
- vref_value_dq = 0x2e;
- break;
- default:
- debug("Invalid ODT value.\n");
- return -EINVAL;
- }
- } else {
- debug("Invalid DRV value.\n");
- return -EINVAL;
- }
- } else {
- vref_mode_dq = 0x2; /* LPDDR3 */
- vref_value_dq = 0x1f;
- }
- vref_mode_ac = 0x2;
- vref_value_ac = 0x1f;
- } else if (sdram_params->base.dramtype == DDR3) {
- /* DDR3L */
- vref_mode_dq = 0x1;
- vref_value_dq = 0x1f;
- vref_mode_ac = 0x1;
- vref_value_ac = 0x1f;
- } else {
- debug("Unknown DRAM type.\n");
- return -EINVAL;
- }
-
- reg_value = (vref_mode_dq << 9) | (0x1 << 8) | vref_value_dq;
-
- /* PHY_913 PHY_PAD_VREF_CTRL_DQ_0 12bits offset_8 */
- clrsetbits_le32(&denali_phy[913], 0xfff << 8, reg_value << 8);
- /* PHY_914 PHY_PAD_VREF_CTRL_DQ_1 12bits offset_0 */
- clrsetbits_le32(&denali_phy[914], 0xfff, reg_value);
- /* PHY_914 PHY_PAD_VREF_CTRL_DQ_2 12bits offset_16 */
- clrsetbits_le32(&denali_phy[914], 0xfff << 16, reg_value << 16);
- /* PHY_915 PHY_PAD_VREF_CTRL_DQ_3 12bits offset_0 */
- clrsetbits_le32(&denali_phy[915], 0xfff, reg_value);
-
- reg_value = (vref_mode_ac << 9) | (0x1 << 8) | vref_value_ac;
-
- /* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */
- clrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16);
-
- if (sdram_params->base.dramtype == LPDDR4)
- mode_sel = 0x6;
- else if (sdram_params->base.dramtype == LPDDR3)
- mode_sel = 0x0;
- else if (sdram_params->base.dramtype == DDR3)
- mode_sel = 0x1;
- else
- return -EINVAL;
-
- /* PHY_924 PHY_PAD_FDBK_DRIVE */
- clrsetbits_le32(&denali_phy[924], 0x7 << 15, mode_sel << 15);
- /* PHY_926 PHY_PAD_DATA_DRIVE */
- clrsetbits_le32(&denali_phy[926], 0x7 << 6, mode_sel << 6);
- /* PHY_927 PHY_PAD_DQS_DRIVE */
- clrsetbits_le32(&denali_phy[927], 0x7 << 6, mode_sel << 6);
- /* PHY_928 PHY_PAD_ADDR_DRIVE */
- clrsetbits_le32(&denali_phy[928], 0x7 << 14, mode_sel << 14);
- /* PHY_929 PHY_PAD_CLK_DRIVE */
- clrsetbits_le32(&denali_phy[929], 0x7 << 14, mode_sel << 14);
- /* PHY_935 PHY_PAD_CKE_DRIVE */
- clrsetbits_le32(&denali_phy[935], 0x7 << 14, mode_sel << 14);
- /* PHY_937 PHY_PAD_RST_DRIVE */
- clrsetbits_le32(&denali_phy[937], 0x7 << 14, mode_sel << 14);
- /* PHY_939 PHY_PAD_CS_DRIVE */
- clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14);
-
- /* speed setting */
- if (sdram_params->base.ddr_freq < 400)
- speed = 0x0;
- else if (sdram_params->base.ddr_freq < 800)
- speed = 0x1;
- else if (sdram_params->base.ddr_freq < 1200)
- speed = 0x2;
- else
- speed = 0x3;
-
- /* PHY_924 PHY_PAD_FDBK_DRIVE */
- clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21);
- /* PHY_926 PHY_PAD_DATA_DRIVE */
- clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9);
- /* PHY_927 PHY_PAD_DQS_DRIVE */
- clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9);
- /* PHY_928 PHY_PAD_ADDR_DRIVE */
- clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17);
- /* PHY_929 PHY_PAD_CLK_DRIVE */
- clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17);
- /* PHY_935 PHY_PAD_CKE_DRIVE */
- clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17);
- /* PHY_937 PHY_PAD_RST_DRIVE */
- clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17);
- /* PHY_939 PHY_PAD_CS_DRIVE */
- clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17);
-
- return 0;
-}
-
static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
u32 channel, const struct rk3399_sdram_params *sdram_params)
{
@@ -550,7 +552,6 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
const u32 *params_ctl = sdram_params->pctl_regs.denali_ctl;
const u32 *params_phy = sdram_params->phy_regs.denali_phy;
u32 tmp, tmp1, tmp2;
- int ret;
/*
* work around controller bug:
@@ -628,10 +629,6 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
tmp = (readl(&denali_phy[467]) >> 16) & 0xff;
clrsetbits_le32(&denali_phy[467], 0xff << 16, (tmp + 0x10) << 16);
- ret = phy_io_config(chan, sdram_params);
- if (ret)
- return ret;
-
return 0;
}
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 57/92] ram: rk3399: Configure phy IO in ds odt
@ 2019-06-11 14:51 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: u-boot
Some dramtypes like lpddr4 initialization would required to
configure phy IO even after pctl_cfg and after set_ds_odt.
For those cases the set_ds_odt would be an initial call to
setup the phy.
To satisfy all the cases, trigger phy IO from set_ds_odt.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 327 ++++++++++++++--------------
1 file changed, 162 insertions(+), 165 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 7251532ad0..a5fa41e498 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -189,6 +189,166 @@ static void set_memory_map(const struct chan_info *chan, u32 channel,
writel(0x2EC7FFFF, &denali_pi[34]);
}
+static int phy_io_config(const struct chan_info *chan,
+ const struct rk3399_sdram_params *sdram_params)
+{
+ u32 *denali_phy = chan->publ->denali_phy;
+ u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac;
+ u32 mode_sel;
+ u32 reg_value;
+ u32 drv_value, odt_value;
+ u32 speed;
+
+ /* vref setting */
+ if (sdram_params->base.dramtype == LPDDR4) {
+ /* LPDDR4 */
+ vref_mode_dq = 0x6;
+ vref_value_dq = 0x1f;
+ vref_mode_ac = 0x6;
+ vref_value_ac = 0x1f;
+ } else if (sdram_params->base.dramtype == LPDDR3) {
+ if (sdram_params->base.odt == 1) {
+ vref_mode_dq = 0x5; /* LPDDR3 ODT */
+ drv_value = (readl(&denali_phy[6]) >> 12) & 0xf;
+ odt_value = (readl(&denali_phy[6]) >> 4) & 0xf;
+ if (drv_value == PHY_DRV_ODT_48) {
+ switch (odt_value) {
+ case PHY_DRV_ODT_240:
+ vref_value_dq = 0x16;
+ break;
+ case PHY_DRV_ODT_120:
+ vref_value_dq = 0x26;
+ break;
+ case PHY_DRV_ODT_60:
+ vref_value_dq = 0x36;
+ break;
+ default:
+ debug("Invalid ODT value.\n");
+ return -EINVAL;
+ }
+ } else if (drv_value == PHY_DRV_ODT_40) {
+ switch (odt_value) {
+ case PHY_DRV_ODT_240:
+ vref_value_dq = 0x19;
+ break;
+ case PHY_DRV_ODT_120:
+ vref_value_dq = 0x23;
+ break;
+ case PHY_DRV_ODT_60:
+ vref_value_dq = 0x31;
+ break;
+ default:
+ debug("Invalid ODT value.\n");
+ return -EINVAL;
+ }
+ } else if (drv_value == PHY_DRV_ODT_34_3) {
+ switch (odt_value) {
+ case PHY_DRV_ODT_240:
+ vref_value_dq = 0x17;
+ break;
+ case PHY_DRV_ODT_120:
+ vref_value_dq = 0x20;
+ break;
+ case PHY_DRV_ODT_60:
+ vref_value_dq = 0x2e;
+ break;
+ default:
+ debug("Invalid ODT value.\n");
+ return -EINVAL;
+ }
+ } else {
+ debug("Invalid DRV value.\n");
+ return -EINVAL;
+ }
+ } else {
+ vref_mode_dq = 0x2; /* LPDDR3 */
+ vref_value_dq = 0x1f;
+ }
+ vref_mode_ac = 0x2;
+ vref_value_ac = 0x1f;
+ } else if (sdram_params->base.dramtype == DDR3) {
+ /* DDR3L */
+ vref_mode_dq = 0x1;
+ vref_value_dq = 0x1f;
+ vref_mode_ac = 0x1;
+ vref_value_ac = 0x1f;
+ } else {
+ debug("Unknown DRAM type.\n");
+ return -EINVAL;
+ }
+
+ reg_value = (vref_mode_dq << 9) | (0x1 << 8) | vref_value_dq;
+
+ /* PHY_913 PHY_PAD_VREF_CTRL_DQ_0 12bits offset_8 */
+ clrsetbits_le32(&denali_phy[913], 0xfff << 8, reg_value << 8);
+ /* PHY_914 PHY_PAD_VREF_CTRL_DQ_1 12bits offset_0 */
+ clrsetbits_le32(&denali_phy[914], 0xfff, reg_value);
+ /* PHY_914 PHY_PAD_VREF_CTRL_DQ_2 12bits offset_16 */
+ clrsetbits_le32(&denali_phy[914], 0xfff << 16, reg_value << 16);
+ /* PHY_915 PHY_PAD_VREF_CTRL_DQ_3 12bits offset_0 */
+ clrsetbits_le32(&denali_phy[915], 0xfff, reg_value);
+
+ reg_value = (vref_mode_ac << 9) | (0x1 << 8) | vref_value_ac;
+
+ /* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */
+ clrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16);
+
+ if (sdram_params->base.dramtype == LPDDR4)
+ mode_sel = 0x6;
+ else if (sdram_params->base.dramtype == LPDDR3)
+ mode_sel = 0x0;
+ else if (sdram_params->base.dramtype == DDR3)
+ mode_sel = 0x1;
+ else
+ return -EINVAL;
+
+ /* PHY_924 PHY_PAD_FDBK_DRIVE */
+ clrsetbits_le32(&denali_phy[924], 0x7 << 15, mode_sel << 15);
+ /* PHY_926 PHY_PAD_DATA_DRIVE */
+ clrsetbits_le32(&denali_phy[926], 0x7 << 6, mode_sel << 6);
+ /* PHY_927 PHY_PAD_DQS_DRIVE */
+ clrsetbits_le32(&denali_phy[927], 0x7 << 6, mode_sel << 6);
+ /* PHY_928 PHY_PAD_ADDR_DRIVE */
+ clrsetbits_le32(&denali_phy[928], 0x7 << 14, mode_sel << 14);
+ /* PHY_929 PHY_PAD_CLK_DRIVE */
+ clrsetbits_le32(&denali_phy[929], 0x7 << 14, mode_sel << 14);
+ /* PHY_935 PHY_PAD_CKE_DRIVE */
+ clrsetbits_le32(&denali_phy[935], 0x7 << 14, mode_sel << 14);
+ /* PHY_937 PHY_PAD_RST_DRIVE */
+ clrsetbits_le32(&denali_phy[937], 0x7 << 14, mode_sel << 14);
+ /* PHY_939 PHY_PAD_CS_DRIVE */
+ clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14);
+
+ /* speed setting */
+ if (sdram_params->base.ddr_freq < 400)
+ speed = 0x0;
+ else if (sdram_params->base.ddr_freq < 800)
+ speed = 0x1;
+ else if (sdram_params->base.ddr_freq < 1200)
+ speed = 0x2;
+ else
+ speed = 0x3;
+
+ /* PHY_924 PHY_PAD_FDBK_DRIVE */
+ clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21);
+ /* PHY_926 PHY_PAD_DATA_DRIVE */
+ clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9);
+ /* PHY_927 PHY_PAD_DQS_DRIVE */
+ clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9);
+ /* PHY_928 PHY_PAD_ADDR_DRIVE */
+ clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17);
+ /* PHY_929 PHY_PAD_CLK_DRIVE */
+ clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17);
+ /* PHY_935 PHY_PAD_CKE_DRIVE */
+ clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17);
+ /* PHY_937 PHY_PAD_RST_DRIVE */
+ clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17);
+ /* PHY_939 PHY_PAD_CS_DRIVE */
+ clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17);
+
+ return 0;
+}
+
static void set_ds_odt(const struct chan_info *chan,
const struct rk3399_sdram_params *sdram_params)
{
@@ -333,6 +493,8 @@ static void set_ds_odt(const struct chan_info *chan,
/* phy_pad_fdbk_term 1bit DENALI_PHY_930 offset_17 */
clrsetbits_le32(&denali_phy[930], 0x1 << 17, reg_value);
+
+ phy_io_config(chan, sdram_params);
}
static void pctl_start(struct dram_info *dram,
@@ -381,166 +543,6 @@ static void pctl_start(struct dram_info *dram,
dram->pwrup_srefresh_exit[channel]);
}
-static int phy_io_config(const struct chan_info *chan,
- const struct rk3399_sdram_params *sdram_params)
-{
- u32 *denali_phy = chan->publ->denali_phy;
- u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac;
- u32 mode_sel;
- u32 reg_value;
- u32 drv_value, odt_value;
- u32 speed;
-
- /* vref setting */
- if (sdram_params->base.dramtype == LPDDR4) {
- /* LPDDR4 */
- vref_mode_dq = 0x6;
- vref_value_dq = 0x1f;
- vref_mode_ac = 0x6;
- vref_value_ac = 0x1f;
- } else if (sdram_params->base.dramtype == LPDDR3) {
- if (sdram_params->base.odt == 1) {
- vref_mode_dq = 0x5; /* LPDDR3 ODT */
- drv_value = (readl(&denali_phy[6]) >> 12) & 0xf;
- odt_value = (readl(&denali_phy[6]) >> 4) & 0xf;
- if (drv_value == PHY_DRV_ODT_48) {
- switch (odt_value) {
- case PHY_DRV_ODT_240:
- vref_value_dq = 0x16;
- break;
- case PHY_DRV_ODT_120:
- vref_value_dq = 0x26;
- break;
- case PHY_DRV_ODT_60:
- vref_value_dq = 0x36;
- break;
- default:
- debug("Invalid ODT value.\n");
- return -EINVAL;
- }
- } else if (drv_value == PHY_DRV_ODT_40) {
- switch (odt_value) {
- case PHY_DRV_ODT_240:
- vref_value_dq = 0x19;
- break;
- case PHY_DRV_ODT_120:
- vref_value_dq = 0x23;
- break;
- case PHY_DRV_ODT_60:
- vref_value_dq = 0x31;
- break;
- default:
- debug("Invalid ODT value.\n");
- return -EINVAL;
- }
- } else if (drv_value == PHY_DRV_ODT_34_3) {
- switch (odt_value) {
- case PHY_DRV_ODT_240:
- vref_value_dq = 0x17;
- break;
- case PHY_DRV_ODT_120:
- vref_value_dq = 0x20;
- break;
- case PHY_DRV_ODT_60:
- vref_value_dq = 0x2e;
- break;
- default:
- debug("Invalid ODT value.\n");
- return -EINVAL;
- }
- } else {
- debug("Invalid DRV value.\n");
- return -EINVAL;
- }
- } else {
- vref_mode_dq = 0x2; /* LPDDR3 */
- vref_value_dq = 0x1f;
- }
- vref_mode_ac = 0x2;
- vref_value_ac = 0x1f;
- } else if (sdram_params->base.dramtype == DDR3) {
- /* DDR3L */
- vref_mode_dq = 0x1;
- vref_value_dq = 0x1f;
- vref_mode_ac = 0x1;
- vref_value_ac = 0x1f;
- } else {
- debug("Unknown DRAM type.\n");
- return -EINVAL;
- }
-
- reg_value = (vref_mode_dq << 9) | (0x1 << 8) | vref_value_dq;
-
- /* PHY_913 PHY_PAD_VREF_CTRL_DQ_0 12bits offset_8 */
- clrsetbits_le32(&denali_phy[913], 0xfff << 8, reg_value << 8);
- /* PHY_914 PHY_PAD_VREF_CTRL_DQ_1 12bits offset_0 */
- clrsetbits_le32(&denali_phy[914], 0xfff, reg_value);
- /* PHY_914 PHY_PAD_VREF_CTRL_DQ_2 12bits offset_16 */
- clrsetbits_le32(&denali_phy[914], 0xfff << 16, reg_value << 16);
- /* PHY_915 PHY_PAD_VREF_CTRL_DQ_3 12bits offset_0 */
- clrsetbits_le32(&denali_phy[915], 0xfff, reg_value);
-
- reg_value = (vref_mode_ac << 9) | (0x1 << 8) | vref_value_ac;
-
- /* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */
- clrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16);
-
- if (sdram_params->base.dramtype == LPDDR4)
- mode_sel = 0x6;
- else if (sdram_params->base.dramtype == LPDDR3)
- mode_sel = 0x0;
- else if (sdram_params->base.dramtype == DDR3)
- mode_sel = 0x1;
- else
- return -EINVAL;
-
- /* PHY_924 PHY_PAD_FDBK_DRIVE */
- clrsetbits_le32(&denali_phy[924], 0x7 << 15, mode_sel << 15);
- /* PHY_926 PHY_PAD_DATA_DRIVE */
- clrsetbits_le32(&denali_phy[926], 0x7 << 6, mode_sel << 6);
- /* PHY_927 PHY_PAD_DQS_DRIVE */
- clrsetbits_le32(&denali_phy[927], 0x7 << 6, mode_sel << 6);
- /* PHY_928 PHY_PAD_ADDR_DRIVE */
- clrsetbits_le32(&denali_phy[928], 0x7 << 14, mode_sel << 14);
- /* PHY_929 PHY_PAD_CLK_DRIVE */
- clrsetbits_le32(&denali_phy[929], 0x7 << 14, mode_sel << 14);
- /* PHY_935 PHY_PAD_CKE_DRIVE */
- clrsetbits_le32(&denali_phy[935], 0x7 << 14, mode_sel << 14);
- /* PHY_937 PHY_PAD_RST_DRIVE */
- clrsetbits_le32(&denali_phy[937], 0x7 << 14, mode_sel << 14);
- /* PHY_939 PHY_PAD_CS_DRIVE */
- clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14);
-
- /* speed setting */
- if (sdram_params->base.ddr_freq < 400)
- speed = 0x0;
- else if (sdram_params->base.ddr_freq < 800)
- speed = 0x1;
- else if (sdram_params->base.ddr_freq < 1200)
- speed = 0x2;
- else
- speed = 0x3;
-
- /* PHY_924 PHY_PAD_FDBK_DRIVE */
- clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21);
- /* PHY_926 PHY_PAD_DATA_DRIVE */
- clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9);
- /* PHY_927 PHY_PAD_DQS_DRIVE */
- clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9);
- /* PHY_928 PHY_PAD_ADDR_DRIVE */
- clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17);
- /* PHY_929 PHY_PAD_CLK_DRIVE */
- clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17);
- /* PHY_935 PHY_PAD_CKE_DRIVE */
- clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17);
- /* PHY_937 PHY_PAD_RST_DRIVE */
- clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17);
- /* PHY_939 PHY_PAD_CS_DRIVE */
- clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17);
-
- return 0;
-}
-
static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
u32 channel, const struct rk3399_sdram_params *sdram_params)
{
@@ -550,7 +552,6 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
const u32 *params_ctl = sdram_params->pctl_regs.denali_ctl;
const u32 *params_phy = sdram_params->phy_regs.denali_phy;
u32 tmp, tmp1, tmp2;
- int ret;
/*
* work around controller bug:
@@ -628,10 +629,6 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
tmp = (readl(&denali_phy[467]) >> 16) & 0xff;
clrsetbits_le32(&denali_phy[467], 0xff << 16, (tmp + 0x10) << 16);
- ret = phy_io_config(chan, sdram_params);
- if (ret)
- return ret;
-
return 0;
}
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 58/92] ram: rk3399: Add lpddr4 rank mask for cs training
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:51 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Add rank_mask based on the rank number for lpddr4.
This would keep the ca data training loop based on the
desired rank mask value instead of looping for all values.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index a5fa41e498..004a4819ff 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -692,7 +692,10 @@ static int data_training_ca(const struct chan_info *chan, u32 channel,
/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
writel(0x00003f7c, (&denali_pi[175]));
- rank_mask = (rank == 1) ? 0x1 : 0x3;
+ if (sdram_params->base.dramtype == LPDDR4)
+ rank_mask = (rank == 1) ? 0x5 : 0xf;
+ else
+ rank_mask = (rank == 1) ? 0x1 : 0x3;
for (i = 0; i < 4; i++) {
if (!(rank_mask & (1 << i)))
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 58/92] ram: rk3399: Add lpddr4 rank mask for cs training
@ 2019-06-11 14:51 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: u-boot
Add rank_mask based on the rank number for lpddr4.
This would keep the ca data training loop based on the
desired rank mask value instead of looping for all values.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index a5fa41e498..004a4819ff 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -692,7 +692,10 @@ static int data_training_ca(const struct chan_info *chan, u32 channel,
/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
writel(0x00003f7c, (&denali_pi[175]));
- rank_mask = (rank == 1) ? 0x1 : 0x3;
+ if (sdram_params->base.dramtype == LPDDR4)
+ rank_mask = (rank == 1) ? 0x5 : 0xf;
+ else
+ rank_mask = (rank == 1) ? 0x1 : 0x3;
for (i = 0; i < 4; i++) {
if (!(rank_mask & (1 << i)))
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 59/92] ram: rk3399: Add lpddr4 rank mask for wdql training
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:51 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Add rank_mask based on the rank number for lpddr4.
This would keep the wdql data training loop based on the
desired rank mask value instead of looping for all values.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 004a4819ff..f80c8a424c 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -930,7 +930,10 @@ static int data_training_wdql(const struct chan_info *chan, u32 channel,
/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
writel(0x00003f7c, (&denali_pi[175]));
- rank_mask = (rank == 1) ? 0x1 : 0x3;
+ if (sdram_params->base.dramtype == LPDDR4)
+ rank_mask = (rank == 1) ? 0x5 : 0xf;
+ else
+ rank_mask = (rank == 1) ? 0x1 : 0x3;
for (i = 0; i < 4; i++) {
if (!(rank_mask & (1 << i)))
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 59/92] ram: rk3399: Add lpddr4 rank mask for wdql training
@ 2019-06-11 14:51 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: u-boot
Add rank_mask based on the rank number for lpddr4.
This would keep the wdql data training loop based on the
desired rank mask value instead of looping for all values.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 004a4819ff..f80c8a424c 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -930,7 +930,10 @@ static int data_training_wdql(const struct chan_info *chan, u32 channel,
/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
writel(0x00003f7c, (&denali_pi[175]));
- rank_mask = (rank == 1) ? 0x1 : 0x3;
+ if (sdram_params->base.dramtype == LPDDR4)
+ rank_mask = (rank == 1) ? 0x5 : 0xf;
+ else
+ rank_mask = (rank == 1) ? 0x1 : 0x3;
for (i = 0; i < 4; i++) {
if (!(rank_mask & (1 << i)))
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 60/92] ram: rk3399: Move mode_sel assignment
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:51 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
mode_sel assignment is based on dram type.
In phy_io_config, already have vref setting based
on the dram type, so move this mode_sel assignment
on vref setting area.
No functionality change.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 12 +++---------
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index f80c8a424c..d399ec8e38 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -206,6 +206,7 @@ static int phy_io_config(const struct chan_info *chan,
vref_value_dq = 0x1f;
vref_mode_ac = 0x6;
vref_value_ac = 0x1f;
+ mode_sel = 0x6;
} else if (sdram_params->base.dramtype == LPDDR3) {
if (sdram_params->base.odt == 1) {
vref_mode_dq = 0x5; /* LPDDR3 ODT */
@@ -266,12 +267,14 @@ static int phy_io_config(const struct chan_info *chan,
}
vref_mode_ac = 0x2;
vref_value_ac = 0x1f;
+ mode_sel = 0x0;
} else if (sdram_params->base.dramtype == DDR3) {
/* DDR3L */
vref_mode_dq = 0x1;
vref_value_dq = 0x1f;
vref_mode_ac = 0x1;
vref_value_ac = 0x1f;
+ mode_sel = 0x1;
} else {
debug("Unknown DRAM type.\n");
return -EINVAL;
@@ -293,15 +296,6 @@ static int phy_io_config(const struct chan_info *chan,
/* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */
clrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16);
- if (sdram_params->base.dramtype == LPDDR4)
- mode_sel = 0x6;
- else if (sdram_params->base.dramtype == LPDDR3)
- mode_sel = 0x0;
- else if (sdram_params->base.dramtype == DDR3)
- mode_sel = 0x1;
- else
- return -EINVAL;
-
/* PHY_924 PHY_PAD_FDBK_DRIVE */
clrsetbits_le32(&denali_phy[924], 0x7 << 15, mode_sel << 15);
/* PHY_926 PHY_PAD_DATA_DRIVE */
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 60/92] ram: rk3399: Move mode_sel assignment
@ 2019-06-11 14:51 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: u-boot
mode_sel assignment is based on dram type.
In phy_io_config, already have vref setting based
on the dram type, so move this mode_sel assignment
on vref setting area.
No functionality change.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 12 +++---------
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index f80c8a424c..d399ec8e38 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -206,6 +206,7 @@ static int phy_io_config(const struct chan_info *chan,
vref_value_dq = 0x1f;
vref_mode_ac = 0x6;
vref_value_ac = 0x1f;
+ mode_sel = 0x6;
} else if (sdram_params->base.dramtype == LPDDR3) {
if (sdram_params->base.odt == 1) {
vref_mode_dq = 0x5; /* LPDDR3 ODT */
@@ -266,12 +267,14 @@ static int phy_io_config(const struct chan_info *chan,
}
vref_mode_ac = 0x2;
vref_value_ac = 0x1f;
+ mode_sel = 0x0;
} else if (sdram_params->base.dramtype == DDR3) {
/* DDR3L */
vref_mode_dq = 0x1;
vref_value_dq = 0x1f;
vref_mode_ac = 0x1;
vref_value_ac = 0x1f;
+ mode_sel = 0x1;
} else {
debug("Unknown DRAM type.\n");
return -EINVAL;
@@ -293,15 +296,6 @@ static int phy_io_config(const struct chan_info *chan,
/* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */
clrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16);
- if (sdram_params->base.dramtype == LPDDR4)
- mode_sel = 0x6;
- else if (sdram_params->base.dramtype == LPDDR3)
- mode_sel = 0x0;
- else if (sdram_params->base.dramtype == DDR3)
- mode_sel = 0x1;
- else
- return -EINVAL;
-
/* PHY_924 PHY_PAD_FDBK_DRIVE */
clrsetbits_le32(&denali_phy[924], 0x7 << 15, mode_sel << 15);
/* PHY_926 PHY_PAD_DATA_DRIVE */
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 61/92] ram: rk3399: Don't wait for PLL lock in lpddr4
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:51 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
lpddr4 has PLL bypass mode during phy initialization phase,
which does all pll configurations.
So need to wait explicitly during pctl config.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 26 ++++++++++++++++----------
1 file changed, 16 insertions(+), 10 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index d399ec8e38..3d26cede77 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -575,16 +575,22 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
setbits_le32(&denali_pi[0], START);
setbits_le32(&denali_ctl[0], START);
- /* Waiting for phy DLL lock */
- while (1) {
- tmp = readl(&denali_phy[920]);
- tmp1 = readl(&denali_phy[921]);
- tmp2 = readl(&denali_phy[922]);
- if ((((tmp >> 16) & 0x1) == 0x1) &&
- (((tmp1 >> 16) & 0x1) == 0x1) &&
- (((tmp1 >> 0) & 0x1) == 0x1) &&
- (((tmp2 >> 0) & 0x1) == 0x1))
- break;
+ /**
+ * LPDDR4 use PLL bypass mode for init
+ * not need to wait for the PLL to lock
+ */
+ if (sdram_params->base.dramtype != LPDDR4) {
+ /* Waiting for phy DLL lock */
+ while (1) {
+ tmp = readl(&denali_phy[920]);
+ tmp1 = readl(&denali_phy[921]);
+ tmp2 = readl(&denali_phy[922]);
+ if ((((tmp >> 16) & 0x1) == 0x1) &&
+ (((tmp1 >> 16) & 0x1) == 0x1) &&
+ (((tmp1 >> 0) & 0x1) == 0x1) &&
+ (((tmp2 >> 0) & 0x1) == 0x1))
+ break;
+ }
}
copy_to_reg(&denali_phy[896], ¶ms_phy[896], (958 - 895) * 4);
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 61/92] ram: rk3399: Don't wait for PLL lock in lpddr4
@ 2019-06-11 14:51 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: u-boot
lpddr4 has PLL bypass mode during phy initialization phase,
which does all pll configurations.
So need to wait explicitly during pctl config.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 26 ++++++++++++++++----------
1 file changed, 16 insertions(+), 10 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index d399ec8e38..3d26cede77 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -575,16 +575,22 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
setbits_le32(&denali_pi[0], START);
setbits_le32(&denali_ctl[0], START);
- /* Waiting for phy DLL lock */
- while (1) {
- tmp = readl(&denali_phy[920]);
- tmp1 = readl(&denali_phy[921]);
- tmp2 = readl(&denali_phy[922]);
- if ((((tmp >> 16) & 0x1) == 0x1) &&
- (((tmp1 >> 16) & 0x1) == 0x1) &&
- (((tmp1 >> 0) & 0x1) == 0x1) &&
- (((tmp2 >> 0) & 0x1) == 0x1))
- break;
+ /**
+ * LPDDR4 use PLL bypass mode for init
+ * not need to wait for the PLL to lock
+ */
+ if (sdram_params->base.dramtype != LPDDR4) {
+ /* Waiting for phy DLL lock */
+ while (1) {
+ tmp = readl(&denali_phy[920]);
+ tmp1 = readl(&denali_phy[921]);
+ tmp2 = readl(&denali_phy[922]);
+ if ((((tmp >> 16) & 0x1) == 0x1) &&
+ (((tmp1 >> 16) & 0x1) == 0x1) &&
+ (((tmp1 >> 0) & 0x1) == 0x1) &&
+ (((tmp2 >> 0) & 0x1) == 0x1))
+ break;
+ }
}
copy_to_reg(&denali_phy[896], ¶ms_phy[896], (958 - 895) * 4);
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 62/92] ram: rk3399: Avoid two channel ZQ Cal Start at the same time
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:51 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
It is possible in lpddr4 dram, where both the channels would
start at same time with ZQ Cal Start. If it uses ZQ Call start
then it will use RZQ.
For example LPDDR4 366 Dual-Die, Quad-Channel Package, RZQ maybe
connect to both channel. If ZQ Cal Start at the same time,
it will use the same RZQ.
It is not a problem of using RZQ in both the channels, but can not
use at the same time.
So, to avoid this, we have an option of dram tINIT3 value for
increasing the frequency for channel 1.
This patch increase the available tINIT3 with existing running
dram frequency.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 3d26cede77..1abeee7198 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -555,6 +555,20 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
sizeof(struct rk3399_ddr_pctl_regs) - 4);
writel(params_ctl[0], &denali_ctl[0]);
+ /*
+ * two channel init at the same time, then ZQ Cal Start
+ * at the same time, it will use the same RZQ, but cannot
+ * start at the same time.
+ *
+ * So, increase tINIT3 for channel 1, will avoid two
+ * channel ZQ Cal Start at the same time
+ */
+ if (sdram_params->base.dramtype == LPDDR4 && channel == 1) {
+ tmp = ((sdram_params->base.ddr_freq * MHz + 999) / 1000);
+ tmp1 = readl(&denali_ctl[14]);
+ writel(tmp + tmp1, &denali_ctl[14]);
+ }
+
copy_to_reg(denali_pi, &sdram_params->pi_regs.denali_pi[0],
sizeof(struct rk3399_ddr_pi_regs));
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 62/92] ram: rk3399: Avoid two channel ZQ Cal Start at the same time
@ 2019-06-11 14:51 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: u-boot
It is possible in lpddr4 dram, where both the channels would
start at same time with ZQ Cal Start. If it uses ZQ Call start
then it will use RZQ.
For example LPDDR4 366 Dual-Die, Quad-Channel Package, RZQ maybe
connect to both channel. If ZQ Cal Start at the same time,
it will use the same RZQ.
It is not a problem of using RZQ in both the channels, but can not
use at the same time.
So, to avoid this, we have an option of dram tINIT3 value for
increasing the frequency for channel 1.
This patch increase the available tINIT3 with existing running
dram frequency.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 3d26cede77..1abeee7198 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -555,6 +555,20 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
sizeof(struct rk3399_ddr_pctl_regs) - 4);
writel(params_ctl[0], &denali_ctl[0]);
+ /*
+ * two channel init at the same time, then ZQ Cal Start
+ * at the same time, it will use the same RZQ, but cannot
+ * start at the same time.
+ *
+ * So, increase tINIT3 for channel 1, will avoid two
+ * channel ZQ Cal Start at the same time
+ */
+ if (sdram_params->base.dramtype == LPDDR4 && channel == 1) {
+ tmp = ((sdram_params->base.ddr_freq * MHz + 999) / 1000);
+ tmp1 = readl(&denali_ctl[14]);
+ writel(tmp + tmp1, &denali_ctl[14]);
+ }
+
copy_to_reg(denali_pi, &sdram_params->pi_regs.denali_pi[0],
sizeof(struct rk3399_ddr_pi_regs));
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 63/92] ram: rk3399: Configure PHY_898, PHY_919 for lpddr4
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:51 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
PHY_898, PHY_919 would require to configure PHY LP4 boot
pll control and ca for lpddr4.
So, configure the same in pctl_cfg for LPDDR4.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 1abeee7198..7d2359740c 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -579,6 +579,13 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
writel(sdram_params->phy_regs.denali_phy[911], &denali_phy[911]);
writel(sdram_params->phy_regs.denali_phy[912], &denali_phy[912]);
+ if (sdram_params->base.dramtype == LPDDR4) {
+ writel(sdram_params->phy_regs.denali_phy[898],
+ &denali_phy[898]);
+ writel(sdram_params->phy_regs.denali_phy[919],
+ &denali_phy[919]);
+ }
+
dram->pwrup_srefresh_exit[channel] = readl(&denali_ctl[68]) &
PWRUP_SREFRESH_EXIT;
clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT);
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 63/92] ram: rk3399: Configure PHY_898, PHY_919 for lpddr4
@ 2019-06-11 14:51 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: u-boot
PHY_898, PHY_919 would require to configure PHY LP4 boot
pll control and ca for lpddr4.
So, configure the same in pctl_cfg for LPDDR4.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 1abeee7198..7d2359740c 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -579,6 +579,13 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
writel(sdram_params->phy_regs.denali_phy[911], &denali_phy[911]);
writel(sdram_params->phy_regs.denali_phy[912], &denali_phy[912]);
+ if (sdram_params->base.dramtype == LPDDR4) {
+ writel(sdram_params->phy_regs.denali_phy[898],
+ &denali_phy[898]);
+ writel(sdram_params->phy_regs.denali_phy[919],
+ &denali_phy[919]);
+ }
+
dram->pwrup_srefresh_exit[channel] = readl(&denali_ctl[68]) &
PWRUP_SREFRESH_EXIT;
clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT);
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 64/92] ram: rk3399: Configure BOOSTP_EN, BOOSTN_EN for lpddr4
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:51 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Configure BOOSTP_EN, BOOSTN_EN for lpddr4 during phy IO config.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 7d2359740c..4328790a4f 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -35,6 +35,9 @@
#define PHY_DRV_ODT_40 0xe
#define PHY_DRV_ODT_34_3 0xf
+#define PHY_BOOSTP_EN 0x1
+#define PHY_BOOSTN_EN 0x1
+
#define CRU_SFTRST_DDR_CTRL(ch, n) ((0x1 << (8 + 16 + (ch) * 4)) | \
((n) << (8 + (ch) * 4)))
#define CRU_SFTRST_DDR_PHY(ch, n) ((0x1 << (9 + 16 + (ch) * 4)) | \
@@ -313,6 +316,27 @@ static int phy_io_config(const struct chan_info *chan,
/* PHY_939 PHY_PAD_CS_DRIVE */
clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14);
+ if (sdram_params->base.dramtype == LPDDR4) {
+ /* BOOSTP_EN & BOOSTN_EN */
+ reg_value = ((PHY_BOOSTP_EN << 4) | PHY_BOOSTN_EN);
+ /* PHY_925 PHY_PAD_FDBK_DRIVE2 */
+ clrsetbits_le32(&denali_phy[925], 0xff << 8, reg_value << 8);
+ /* PHY_926 PHY_PAD_DATA_DRIVE */
+ clrsetbits_le32(&denali_phy[926], 0xff << 12, reg_value << 12);
+ /* PHY_927 PHY_PAD_DQS_DRIVE */
+ clrsetbits_le32(&denali_phy[927], 0xff << 14, reg_value << 14);
+ /* PHY_928 PHY_PAD_ADDR_DRIVE */
+ clrsetbits_le32(&denali_phy[928], 0xff << 20, reg_value << 20);
+ /* PHY_929 PHY_PAD_CLK_DRIVE */
+ clrsetbits_le32(&denali_phy[929], 0xff << 22, reg_value << 22);
+ /* PHY_935 PHY_PAD_CKE_DRIVE */
+ clrsetbits_le32(&denali_phy[935], 0xff << 20, reg_value << 20);
+ /* PHY_937 PHY_PAD_RST_DRIVE */
+ clrsetbits_le32(&denali_phy[937], 0xff << 20, reg_value << 20);
+ /* PHY_939 PHY_PAD_CS_DRIVE */
+ clrsetbits_le32(&denali_phy[939], 0xff << 20, reg_value << 20);
+ }
+
/* speed setting */
if (sdram_params->base.ddr_freq < 400)
speed = 0x0;
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 64/92] ram: rk3399: Configure BOOSTP_EN, BOOSTN_EN for lpddr4
@ 2019-06-11 14:51 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: u-boot
Configure BOOSTP_EN, BOOSTN_EN for lpddr4 during phy IO config.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 7d2359740c..4328790a4f 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -35,6 +35,9 @@
#define PHY_DRV_ODT_40 0xe
#define PHY_DRV_ODT_34_3 0xf
+#define PHY_BOOSTP_EN 0x1
+#define PHY_BOOSTN_EN 0x1
+
#define CRU_SFTRST_DDR_CTRL(ch, n) ((0x1 << (8 + 16 + (ch) * 4)) | \
((n) << (8 + (ch) * 4)))
#define CRU_SFTRST_DDR_PHY(ch, n) ((0x1 << (9 + 16 + (ch) * 4)) | \
@@ -313,6 +316,27 @@ static int phy_io_config(const struct chan_info *chan,
/* PHY_939 PHY_PAD_CS_DRIVE */
clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14);
+ if (sdram_params->base.dramtype == LPDDR4) {
+ /* BOOSTP_EN & BOOSTN_EN */
+ reg_value = ((PHY_BOOSTP_EN << 4) | PHY_BOOSTN_EN);
+ /* PHY_925 PHY_PAD_FDBK_DRIVE2 */
+ clrsetbits_le32(&denali_phy[925], 0xff << 8, reg_value << 8);
+ /* PHY_926 PHY_PAD_DATA_DRIVE */
+ clrsetbits_le32(&denali_phy[926], 0xff << 12, reg_value << 12);
+ /* PHY_927 PHY_PAD_DQS_DRIVE */
+ clrsetbits_le32(&denali_phy[927], 0xff << 14, reg_value << 14);
+ /* PHY_928 PHY_PAD_ADDR_DRIVE */
+ clrsetbits_le32(&denali_phy[928], 0xff << 20, reg_value << 20);
+ /* PHY_929 PHY_PAD_CLK_DRIVE */
+ clrsetbits_le32(&denali_phy[929], 0xff << 22, reg_value << 22);
+ /* PHY_935 PHY_PAD_CKE_DRIVE */
+ clrsetbits_le32(&denali_phy[935], 0xff << 20, reg_value << 20);
+ /* PHY_937 PHY_PAD_RST_DRIVE */
+ clrsetbits_le32(&denali_phy[937], 0xff << 20, reg_value << 20);
+ /* PHY_939 PHY_PAD_CS_DRIVE */
+ clrsetbits_le32(&denali_phy[939], 0xff << 20, reg_value << 20);
+ }
+
/* speed setting */
if (sdram_params->base.ddr_freq < 400)
speed = 0x0;
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 65/92] ram: rk3399: Configure SLEWP_EN, SLEWN_EN for lpddr4
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:51 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Configure SLEWP_EN, SLEWN_EN for lpddr4 during phy IO config.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 4328790a4f..78e249e164 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -37,6 +37,8 @@
#define PHY_BOOSTP_EN 0x1
#define PHY_BOOSTN_EN 0x1
+#define PHY_SLEWP_EN 0x1
+#define PHY_SLEWN_EN 0x1
#define CRU_SFTRST_DDR_CTRL(ch, n) ((0x1 << (8 + 16 + (ch) * 4)) | \
((n) << (8 + (ch) * 4)))
@@ -335,6 +337,25 @@ static int phy_io_config(const struct chan_info *chan,
clrsetbits_le32(&denali_phy[937], 0xff << 20, reg_value << 20);
/* PHY_939 PHY_PAD_CS_DRIVE */
clrsetbits_le32(&denali_phy[939], 0xff << 20, reg_value << 20);
+
+ /* SLEWP_EN & SLEWN_EN */
+ reg_value = ((PHY_SLEWP_EN << 3) | PHY_SLEWN_EN);
+ /* PHY_924 PHY_PAD_FDBK_DRIVE */
+ clrsetbits_le32(&denali_phy[924], 0x3f << 8, reg_value << 8);
+ /* PHY_926 PHY_PAD_DATA_DRIVE */
+ clrsetbits_le32(&denali_phy[926], 0x3f, reg_value);
+ /* PHY_927 PHY_PAD_DQS_DRIVE */
+ clrsetbits_le32(&denali_phy[927], 0x3f, reg_value);
+ /* PHY_928 PHY_PAD_ADDR_DRIVE */
+ clrsetbits_le32(&denali_phy[928], 0x3f << 8, reg_value << 8);
+ /* PHY_929 PHY_PAD_CLK_DRIVE */
+ clrsetbits_le32(&denali_phy[929], 0x3f << 8, reg_value << 8);
+ /* PHY_935 PHY_PAD_CKE_DRIVE */
+ clrsetbits_le32(&denali_phy[935], 0x3f << 8, reg_value << 8);
+ /* PHY_937 PHY_PAD_RST_DRIVE */
+ clrsetbits_le32(&denali_phy[937], 0x3f << 8, reg_value << 8);
+ /* PHY_939 PHY_PAD_CS_DRIVE */
+ clrsetbits_le32(&denali_phy[939], 0x3f << 8, reg_value << 8);
}
/* speed setting */
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 65/92] ram: rk3399: Configure SLEWP_EN, SLEWN_EN for lpddr4
@ 2019-06-11 14:51 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: u-boot
Configure SLEWP_EN, SLEWN_EN for lpddr4 during phy IO config.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 4328790a4f..78e249e164 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -37,6 +37,8 @@
#define PHY_BOOSTP_EN 0x1
#define PHY_BOOSTN_EN 0x1
+#define PHY_SLEWP_EN 0x1
+#define PHY_SLEWN_EN 0x1
#define CRU_SFTRST_DDR_CTRL(ch, n) ((0x1 << (8 + 16 + (ch) * 4)) | \
((n) << (8 + (ch) * 4)))
@@ -335,6 +337,25 @@ static int phy_io_config(const struct chan_info *chan,
clrsetbits_le32(&denali_phy[937], 0xff << 20, reg_value << 20);
/* PHY_939 PHY_PAD_CS_DRIVE */
clrsetbits_le32(&denali_phy[939], 0xff << 20, reg_value << 20);
+
+ /* SLEWP_EN & SLEWN_EN */
+ reg_value = ((PHY_SLEWP_EN << 3) | PHY_SLEWN_EN);
+ /* PHY_924 PHY_PAD_FDBK_DRIVE */
+ clrsetbits_le32(&denali_phy[924], 0x3f << 8, reg_value << 8);
+ /* PHY_926 PHY_PAD_DATA_DRIVE */
+ clrsetbits_le32(&denali_phy[926], 0x3f, reg_value);
+ /* PHY_927 PHY_PAD_DQS_DRIVE */
+ clrsetbits_le32(&denali_phy[927], 0x3f, reg_value);
+ /* PHY_928 PHY_PAD_ADDR_DRIVE */
+ clrsetbits_le32(&denali_phy[928], 0x3f << 8, reg_value << 8);
+ /* PHY_929 PHY_PAD_CLK_DRIVE */
+ clrsetbits_le32(&denali_phy[929], 0x3f << 8, reg_value << 8);
+ /* PHY_935 PHY_PAD_CKE_DRIVE */
+ clrsetbits_le32(&denali_phy[935], 0x3f << 8, reg_value << 8);
+ /* PHY_937 PHY_PAD_RST_DRIVE */
+ clrsetbits_le32(&denali_phy[937], 0x3f << 8, reg_value << 8);
+ /* PHY_939 PHY_PAD_CS_DRIVE */
+ clrsetbits_le32(&denali_phy[939], 0x3f << 8, reg_value << 8);
}
/* speed setting */
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 66/92] ram: rk3399: Configure PHY RX_CM_INPUT for lpddr4
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:51 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Configure PHY RX_CM_INPUT for lpddr4 during phy IO config.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 78e249e164..13c552649c 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -39,6 +39,7 @@
#define PHY_BOOSTN_EN 0x1
#define PHY_SLEWP_EN 0x1
#define PHY_SLEWN_EN 0x1
+#define PHY_RX_CM_INPUT 0x1
#define CRU_SFTRST_DDR_CTRL(ch, n) ((0x1 << (8 + 16 + (ch) * 4)) | \
((n) << (8 + (ch) * 4)))
@@ -385,6 +386,27 @@ static int phy_io_config(const struct chan_info *chan,
/* PHY_939 PHY_PAD_CS_DRIVE */
clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17);
+ if (sdram_params->base.dramtype == LPDDR4) {
+ /* RX_CM_INPUT */
+ reg_value = PHY_RX_CM_INPUT;
+ /* PHY_924 PHY_PAD_FDBK_DRIVE */
+ clrsetbits_le32(&denali_phy[924], 0x1 << 14, reg_value << 14);
+ /* PHY_926 PHY_PAD_DATA_DRIVE */
+ clrsetbits_le32(&denali_phy[926], 0x1 << 11, reg_value << 11);
+ /* PHY_927 PHY_PAD_DQS_DRIVE */
+ clrsetbits_le32(&denali_phy[927], 0x1 << 13, reg_value << 13);
+ /* PHY_928 PHY_PAD_ADDR_DRIVE */
+ clrsetbits_le32(&denali_phy[928], 0x1 << 19, reg_value << 19);
+ /* PHY_929 PHY_PAD_CLK_DRIVE */
+ clrsetbits_le32(&denali_phy[929], 0x1 << 21, reg_value << 21);
+ /* PHY_935 PHY_PAD_CKE_DRIVE */
+ clrsetbits_le32(&denali_phy[935], 0x1 << 19, reg_value << 19);
+ /* PHY_937 PHY_PAD_RST_DRIVE */
+ clrsetbits_le32(&denali_phy[937], 0x1 << 19, reg_value << 19);
+ /* PHY_939 PHY_PAD_CS_DRIVE */
+ clrsetbits_le32(&denali_phy[939], 0x1 << 19, reg_value << 19);
+ }
+
return 0;
}
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 66/92] ram: rk3399: Configure PHY RX_CM_INPUT for lpddr4
@ 2019-06-11 14:51 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: u-boot
Configure PHY RX_CM_INPUT for lpddr4 during phy IO config.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 78e249e164..13c552649c 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -39,6 +39,7 @@
#define PHY_BOOSTN_EN 0x1
#define PHY_SLEWP_EN 0x1
#define PHY_SLEWN_EN 0x1
+#define PHY_RX_CM_INPUT 0x1
#define CRU_SFTRST_DDR_CTRL(ch, n) ((0x1 << (8 + 16 + (ch) * 4)) | \
((n) << (8 + (ch) * 4)))
@@ -385,6 +386,27 @@ static int phy_io_config(const struct chan_info *chan,
/* PHY_939 PHY_PAD_CS_DRIVE */
clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17);
+ if (sdram_params->base.dramtype == LPDDR4) {
+ /* RX_CM_INPUT */
+ reg_value = PHY_RX_CM_INPUT;
+ /* PHY_924 PHY_PAD_FDBK_DRIVE */
+ clrsetbits_le32(&denali_phy[924], 0x1 << 14, reg_value << 14);
+ /* PHY_926 PHY_PAD_DATA_DRIVE */
+ clrsetbits_le32(&denali_phy[926], 0x1 << 11, reg_value << 11);
+ /* PHY_927 PHY_PAD_DQS_DRIVE */
+ clrsetbits_le32(&denali_phy[927], 0x1 << 13, reg_value << 13);
+ /* PHY_928 PHY_PAD_ADDR_DRIVE */
+ clrsetbits_le32(&denali_phy[928], 0x1 << 19, reg_value << 19);
+ /* PHY_929 PHY_PAD_CLK_DRIVE */
+ clrsetbits_le32(&denali_phy[929], 0x1 << 21, reg_value << 21);
+ /* PHY_935 PHY_PAD_CKE_DRIVE */
+ clrsetbits_le32(&denali_phy[935], 0x1 << 19, reg_value << 19);
+ /* PHY_937 PHY_PAD_RST_DRIVE */
+ clrsetbits_le32(&denali_phy[937], 0x1 << 19, reg_value << 19);
+ /* PHY_939 PHY_PAD_CS_DRIVE */
+ clrsetbits_le32(&denali_phy[939], 0x1 << 19, reg_value << 19);
+ }
+
return 0;
}
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 67/92] ram: rk3399: Map chipselect for lpddr4
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:51 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Assign desired cs_map values for lpddr4 during set memory map.
Initial cs_map values is based on the sdram parameters, so
the same will adjusted based dramtype as LPDDR4.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 13c552649c..ecc215b9c7 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -189,6 +189,16 @@ static void set_memory_map(const struct chan_info *chan, u32 channel,
clrsetbits_le32(&denali_pi[155], (0x3 << 16) | (0x7 << 24),
((3 - sdram_ch->cap_info.bk) << 16) |
((16 - row) << 24));
+
+ if (sdram_params->base.dramtype == LPDDR4) {
+ if (cs_map == 1)
+ cs_map = 0x5;
+ else if (cs_map == 2)
+ cs_map = 0xa;
+ else
+ cs_map = 0xF;
+ }
+
/* PI_41 PI_CS_MAP:RW:24:4 */
clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24);
if (sdram_ch->cap_info.rank == 1 && sdram_params->base.dramtype == DDR3)
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 67/92] ram: rk3399: Map chipselect for lpddr4
@ 2019-06-11 14:51 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: u-boot
Assign desired cs_map values for lpddr4 during set memory map.
Initial cs_map values is based on the sdram parameters, so
the same will adjusted based dramtype as LPDDR4.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 13c552649c..ecc215b9c7 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -189,6 +189,16 @@ static void set_memory_map(const struct chan_info *chan, u32 channel,
clrsetbits_le32(&denali_pi[155], (0x3 << 16) | (0x7 << 24),
((3 - sdram_ch->cap_info.bk) << 16) |
((16 - row) << 24));
+
+ if (sdram_params->base.dramtype == LPDDR4) {
+ if (cs_map == 1)
+ cs_map = 0x5;
+ else if (cs_map == 2)
+ cs_map = 0xa;
+ else
+ cs_map = 0xF;
+ }
+
/* PI_41 PI_CS_MAP:RW:24:4 */
clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24);
if (sdram_ch->cap_info.rank == 1 && sdram_params->base.dramtype == DDR3)
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 68/92] ram: rk3399: Configure tsel write ca for lpddr4
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:51 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
tsel write ca_p and ca_n values need to write on PHY 544, 672
and 800 to configure ds odt.
Configure the same PHY register for lpddr4 would require a mask
value of (300 << 8).
Add support for it.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 15 ++++++++++++---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index ecc215b9c7..a251fc6045 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -503,9 +503,18 @@ static void set_ds_odt(const struct chan_info *chan,
/* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */
reg_value = tsel_wr_select_ca_n | (tsel_wr_select_ca_p << 0x4);
- clrsetbits_le32(&denali_phy[544], 0xff, reg_value);
- clrsetbits_le32(&denali_phy[672], 0xff, reg_value);
- clrsetbits_le32(&denali_phy[800], 0xff, reg_value);
+ if (sdram_params->base.dramtype == LPDDR4) {
+ /* LPDDR4 these register read always return 0, so
+ * can not use clrsetbits_le32(), need to write32
+ */
+ writel((0x300 << 8) | reg_value, &denali_phy[544]);
+ writel((0x300 << 8) | reg_value, &denali_phy[672]);
+ writel((0x300 << 8) | reg_value, &denali_phy[800]);
+ } else {
+ clrsetbits_le32(&denali_phy[544], 0xff, reg_value);
+ clrsetbits_le32(&denali_phy[672], 0xff, reg_value);
+ clrsetbits_le32(&denali_phy[800], 0xff, reg_value);
+ }
/* phy_pad_addr_drive 8bits DENALI_PHY_928 offset_0 */
clrsetbits_le32(&denali_phy[928], 0xff, reg_value);
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 68/92] ram: rk3399: Configure tsel write ca for lpddr4
@ 2019-06-11 14:51 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: u-boot
tsel write ca_p and ca_n values need to write on PHY 544, 672
and 800 to configure ds odt.
Configure the same PHY register for lpddr4 would require a mask
value of (300 << 8).
Add support for it.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 15 ++++++++++++---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index ecc215b9c7..a251fc6045 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -503,9 +503,18 @@ static void set_ds_odt(const struct chan_info *chan,
/* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */
reg_value = tsel_wr_select_ca_n | (tsel_wr_select_ca_p << 0x4);
- clrsetbits_le32(&denali_phy[544], 0xff, reg_value);
- clrsetbits_le32(&denali_phy[672], 0xff, reg_value);
- clrsetbits_le32(&denali_phy[800], 0xff, reg_value);
+ if (sdram_params->base.dramtype == LPDDR4) {
+ /* LPDDR4 these register read always return 0, so
+ * can not use clrsetbits_le32(), need to write32
+ */
+ writel((0x300 << 8) | reg_value, &denali_phy[544]);
+ writel((0x300 << 8) | reg_value, &denali_phy[672]);
+ writel((0x300 << 8) | reg_value, &denali_phy[800]);
+ } else {
+ clrsetbits_le32(&denali_phy[544], 0xff, reg_value);
+ clrsetbits_le32(&denali_phy[672], 0xff, reg_value);
+ clrsetbits_le32(&denali_phy[800], 0xff, reg_value);
+ }
/* phy_pad_addr_drive 8bits DENALI_PHY_928 offset_0 */
clrsetbits_le32(&denali_phy[928], 0xff, reg_value);
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 69/92] ram: rk3399: Don't disable dfi dram clk for lpddr4, rank 1
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:51 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
The hardware for LPDDR4 with
- CLK0P/N connect to lower 16-bits
- CLK1P/N connect to higher 16-bits
and usually dfi dram clk is configured via CLK1P/N, so
disabling dfi dram clk will disable the CLK1P/N as well.
So, add patch to not to disable dfi dram clk for lpddr4,
with rank 1.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 14 ++++++++++++--
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index a251fc6045..9151b023e2 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1233,8 +1233,18 @@ static void dram_all_config(struct dram_info *dram,
writel(noc_timing->ddrmode.d32,
&ddr_msch_regs->ddrmode);
- /* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */
- if (sdram_params->ch[channel].cap_info.rank == 1)
+ /**
+ * rank 1 memory clock disable (dfi_dram_clk_disable = 1)
+ *
+ * The hardware for LPDDR4 with
+ * - CLK0P/N connect to lower 16-bits
+ * - CLK1P/N connect to higher 16-bits
+ *
+ * dfi dram clk is configured via CLK1P/N, so disabling
+ * dfi dram clk will disable the CLK1P/N as well for lpddr4.
+ */
+ if (sdram_params->ch[channel].cap_info.rank == 1 &&
+ sdram_params->base.dramtype != LPDDR4)
setbits_le32(&dram->chan[channel].pctl->denali_ctl[276],
1 << 17);
}
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 69/92] ram: rk3399: Don't disable dfi dram clk for lpddr4, rank 1
@ 2019-06-11 14:51 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: u-boot
The hardware for LPDDR4 with
- CLK0P/N connect to lower 16-bits
- CLK1P/N connect to higher 16-bits
and usually dfi dram clk is configured via CLK1P/N, so
disabling dfi dram clk will disable the CLK1P/N as well.
So, add patch to not to disable dfi dram clk for lpddr4,
with rank 1.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 14 ++++++++++++--
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index a251fc6045..9151b023e2 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1233,8 +1233,18 @@ static void dram_all_config(struct dram_info *dram,
writel(noc_timing->ddrmode.d32,
&ddr_msch_regs->ddrmode);
- /* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */
- if (sdram_params->ch[channel].cap_info.rank == 1)
+ /**
+ * rank 1 memory clock disable (dfi_dram_clk_disable = 1)
+ *
+ * The hardware for LPDDR4 with
+ * - CLK0P/N connect to lower 16-bits
+ * - CLK1P/N connect to higher 16-bits
+ *
+ * dfi dram clk is configured via CLK1P/N, so disabling
+ * dfi dram clk will disable the CLK1P/N as well for lpddr4.
+ */
+ if (sdram_params->ch[channel].cap_info.rank == 1 &&
+ sdram_params->base.dramtype != LPDDR4)
setbits_le32(&dram->chan[channel].pctl->denali_ctl[276],
1 << 17);
}
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 70/92] ram: rk3399: Add IO settings
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:51 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Add IO settings for dram ctl and phy.
IO settings are useful for configuring ctl, phy odt, vref,
mr5, mode select and other needed input output operations
for lpddr4 or any other dramtype sdram.
Right now, this patch added IO setting for all supported
sdram frequencies.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 104 ++++++++++++++++++++++++++++
1 file changed, 104 insertions(+)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 9151b023e2..5db7cbe116 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -80,6 +80,110 @@ struct rockchip_dmc_plat {
struct regmap *map;
};
+struct io_setting {
+ u32 mhz;
+ u32 mr5;
+ /* dram side */
+ u32 dq_odt;
+ u32 ca_odt;
+ u32 pdds;
+ u32 dq_vref;
+ u32 ca_vref;
+ /* phy side */
+ u32 rd_odt;
+ u32 wr_dq_drv;
+ u32 wr_ca_drv;
+ u32 wr_ckcs_drv;
+ u32 rd_odt_en;
+ u32 rd_vref;
+} lpddr4_io_setting[] = {
+ {
+ 50 * MHz,
+ 0,
+ /* dram side */
+ 0, /* dq_odt; */
+ 0, /* ca_odt; */
+ 6, /* pdds; */
+ 0x72, /* dq_vref; */
+ 0x72, /* ca_vref; */
+ /* phy side */
+ PHY_DRV_ODT_HI_Z, /* rd_odt; */
+ PHY_DRV_ODT_40, /* wr_dq_drv; */
+ PHY_DRV_ODT_40, /* wr_ca_drv; */
+ PHY_DRV_ODT_40, /* wr_ckcs_drv; */
+ 0, /* rd_odt_en;*/
+ 41, /* rd_vref; (unit %, range 3.3% - 48.7%) */
+ },
+ {
+ 600 * MHz,
+ 0,
+ /* dram side */
+ 1, /* dq_odt; */
+ 0, /* ca_odt; */
+ 6, /* pdds; */
+ 0x72, /* dq_vref; */
+ 0x72, /* ca_vref; */
+ /* phy side */
+ PHY_DRV_ODT_HI_Z, /* rd_odt; */
+ PHY_DRV_ODT_48, /* wr_dq_drv; */
+ PHY_DRV_ODT_40, /* wr_ca_drv; */
+ PHY_DRV_ODT_40, /* wr_ckcs_drv; */
+ 0, /* rd_odt_en; */
+ 32, /* rd_vref; (unit %, range 3.3% - 48.7%) */
+ },
+ {
+ 800 * MHz,
+ 0,
+ /* dram side */
+ 1, /* dq_odt; */
+ 0, /* ca_odt; */
+ 1, /* pdds; */
+ 0x72, /* dq_vref; */
+ 0x72, /* ca_vref; */
+ /* phy side */
+ PHY_DRV_ODT_40, /* rd_odt; */
+ PHY_DRV_ODT_48, /* wr_dq_drv; */
+ PHY_DRV_ODT_40, /* wr_ca_drv; */
+ PHY_DRV_ODT_40, /* wr_ckcs_drv; */
+ 1, /* rd_odt_en; */
+ 17, /* rd_vref; (unit %, range 3.3% - 48.7%) */
+ },
+ {
+ 933 * MHz,
+ 0,
+ /* dram side */
+ 3, /* dq_odt; */
+ 0, /* ca_odt; */
+ 6, /* pdds; */
+ 0x59, /* dq_vref; 32% */
+ 0x72, /* ca_vref; */
+ /* phy side */
+ PHY_DRV_ODT_HI_Z, /* rd_odt; */
+ PHY_DRV_ODT_48, /* wr_dq_drv; */
+ PHY_DRV_ODT_40, /* wr_ca_drv; */
+ PHY_DRV_ODT_40, /* wr_ckcs_drv; */
+ 0, /* rd_odt_en; */
+ 32, /* rd_vref; (unit %, range 3.3% - 48.7%) */
+ },
+ {
+ 1066 * MHz,
+ 0,
+ /* dram side */
+ 6, /* dq_odt; */
+ 0, /* ca_odt; */
+ 1, /* pdds; */
+ 0x10, /* dq_vref; */
+ 0x72, /* ca_vref; */
+ /* phy side */
+ PHY_DRV_ODT_40, /* rd_odt; */
+ PHY_DRV_ODT_60, /* wr_dq_drv; */
+ PHY_DRV_ODT_40, /* wr_ca_drv; */
+ PHY_DRV_ODT_40, /* wr_ckcs_drv; */
+ 1, /* rd_odt_en; */
+ 17, /* rd_vref; (unit %, range 3.3% - 48.7%) */
+ },
+};
+
static void *get_ddrc0_con(struct dram_info *dram, u8 channel)
{
return (channel == 0) ? &dram->grf->ddrc0_con0 : &dram->grf->ddrc0_con1;
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 70/92] ram: rk3399: Add IO settings
@ 2019-06-11 14:51 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: u-boot
Add IO settings for dram ctl and phy.
IO settings are useful for configuring ctl, phy odt, vref,
mr5, mode select and other needed input output operations
for lpddr4 or any other dramtype sdram.
Right now, this patch added IO setting for all supported
sdram frequencies.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 104 ++++++++++++++++++++++++++++
1 file changed, 104 insertions(+)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 9151b023e2..5db7cbe116 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -80,6 +80,110 @@ struct rockchip_dmc_plat {
struct regmap *map;
};
+struct io_setting {
+ u32 mhz;
+ u32 mr5;
+ /* dram side */
+ u32 dq_odt;
+ u32 ca_odt;
+ u32 pdds;
+ u32 dq_vref;
+ u32 ca_vref;
+ /* phy side */
+ u32 rd_odt;
+ u32 wr_dq_drv;
+ u32 wr_ca_drv;
+ u32 wr_ckcs_drv;
+ u32 rd_odt_en;
+ u32 rd_vref;
+} lpddr4_io_setting[] = {
+ {
+ 50 * MHz,
+ 0,
+ /* dram side */
+ 0, /* dq_odt; */
+ 0, /* ca_odt; */
+ 6, /* pdds; */
+ 0x72, /* dq_vref; */
+ 0x72, /* ca_vref; */
+ /* phy side */
+ PHY_DRV_ODT_HI_Z, /* rd_odt; */
+ PHY_DRV_ODT_40, /* wr_dq_drv; */
+ PHY_DRV_ODT_40, /* wr_ca_drv; */
+ PHY_DRV_ODT_40, /* wr_ckcs_drv; */
+ 0, /* rd_odt_en;*/
+ 41, /* rd_vref; (unit %, range 3.3% - 48.7%) */
+ },
+ {
+ 600 * MHz,
+ 0,
+ /* dram side */
+ 1, /* dq_odt; */
+ 0, /* ca_odt; */
+ 6, /* pdds; */
+ 0x72, /* dq_vref; */
+ 0x72, /* ca_vref; */
+ /* phy side */
+ PHY_DRV_ODT_HI_Z, /* rd_odt; */
+ PHY_DRV_ODT_48, /* wr_dq_drv; */
+ PHY_DRV_ODT_40, /* wr_ca_drv; */
+ PHY_DRV_ODT_40, /* wr_ckcs_drv; */
+ 0, /* rd_odt_en; */
+ 32, /* rd_vref; (unit %, range 3.3% - 48.7%) */
+ },
+ {
+ 800 * MHz,
+ 0,
+ /* dram side */
+ 1, /* dq_odt; */
+ 0, /* ca_odt; */
+ 1, /* pdds; */
+ 0x72, /* dq_vref; */
+ 0x72, /* ca_vref; */
+ /* phy side */
+ PHY_DRV_ODT_40, /* rd_odt; */
+ PHY_DRV_ODT_48, /* wr_dq_drv; */
+ PHY_DRV_ODT_40, /* wr_ca_drv; */
+ PHY_DRV_ODT_40, /* wr_ckcs_drv; */
+ 1, /* rd_odt_en; */
+ 17, /* rd_vref; (unit %, range 3.3% - 48.7%) */
+ },
+ {
+ 933 * MHz,
+ 0,
+ /* dram side */
+ 3, /* dq_odt; */
+ 0, /* ca_odt; */
+ 6, /* pdds; */
+ 0x59, /* dq_vref; 32% */
+ 0x72, /* ca_vref; */
+ /* phy side */
+ PHY_DRV_ODT_HI_Z, /* rd_odt; */
+ PHY_DRV_ODT_48, /* wr_dq_drv; */
+ PHY_DRV_ODT_40, /* wr_ca_drv; */
+ PHY_DRV_ODT_40, /* wr_ckcs_drv; */
+ 0, /* rd_odt_en; */
+ 32, /* rd_vref; (unit %, range 3.3% - 48.7%) */
+ },
+ {
+ 1066 * MHz,
+ 0,
+ /* dram side */
+ 6, /* dq_odt; */
+ 0, /* ca_odt; */
+ 1, /* pdds; */
+ 0x10, /* dq_vref; */
+ 0x72, /* ca_vref; */
+ /* phy side */
+ PHY_DRV_ODT_40, /* rd_odt; */
+ PHY_DRV_ODT_60, /* wr_dq_drv; */
+ PHY_DRV_ODT_40, /* wr_ca_drv; */
+ PHY_DRV_ODT_40, /* wr_ckcs_drv; */
+ 1, /* rd_odt_en; */
+ 17, /* rd_vref; (unit %, range 3.3% - 48.7%) */
+ },
+};
+
static void *get_ddrc0_con(struct dram_info *dram, u8 channel)
{
return (channel == 0) ? &dram->grf->ddrc0_con0 : &dram->grf->ddrc0_con1;
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 71/92] ram: sdram: Configure lpddr4 tsel rd, wr based on IO settings
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:51 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Now we have IO settings available for all supported sdram
frequencies, so retrieve these IO settings and make used
for LPDDR4 ds odt configuration.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 42 ++++++++++++++++++++++++-----
1 file changed, 36 insertions(+), 6 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 5db7cbe116..6385df5600 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -184,6 +184,33 @@ struct io_setting {
},
};
+/**
+ * phy = 0, PHY boot freq
+ * phy = 1, PHY index 0
+ * phy = 2, PHY index 1
+ */
+static struct io_setting *
+lpddr4_get_io_settings(const struct rk3399_sdram_params *params, u32 mr5)
+{
+ struct io_setting *io = NULL;
+ u32 n;
+
+ for (n = 0; n < ARRAY_SIZE(lpddr4_io_setting); n++) {
+ io = &lpddr4_io_setting[n];
+
+ if (io->mr5 != 0) {
+ if (io->mhz >= params->base.ddr_freq &&
+ io->mr5 == mr5)
+ break;
+ } else {
+ if (io->mhz >= params->base.ddr_freq)
+ break;
+ }
+ }
+
+ return io;
+}
+
static void *get_ddrc0_con(struct dram_info *dram, u8 channel)
{
return (channel == 0) ? &dram->grf->ddrc0_con0 : &dram->grf->ddrc0_con1;
@@ -525,7 +552,7 @@ static int phy_io_config(const struct chan_info *chan,
}
static void set_ds_odt(const struct chan_info *chan,
- const struct rk3399_sdram_params *sdram_params)
+ const struct rk3399_sdram_params *sdram_params, u32 mr5)
{
u32 *denali_phy = chan->publ->denali_phy;
@@ -534,19 +561,22 @@ static void set_ds_odt(const struct chan_info *chan,
u32 tsel_idle_select_n, tsel_rd_select_n;
u32 tsel_wr_select_dq_p, tsel_wr_select_ca_p;
u32 tsel_wr_select_dq_n, tsel_wr_select_ca_n;
+ struct io_setting *io = NULL;
u32 reg_value;
if (sdram_params->base.dramtype == LPDDR4) {
+ io = lpddr4_get_io_settings(sdram_params, mr5);
+
tsel_rd_select_p = PHY_DRV_ODT_HI_Z;
- tsel_rd_select_n = PHY_DRV_ODT_240;
+ tsel_rd_select_n = io->rd_odt;
tsel_idle_select_p = PHY_DRV_ODT_HI_Z;
tsel_idle_select_n = PHY_DRV_ODT_240;
- tsel_wr_select_dq_p = PHY_DRV_ODT_40;
+ tsel_wr_select_dq_p = io->wr_dq_drv;
tsel_wr_select_dq_n = PHY_DRV_ODT_40;
- tsel_wr_select_ca_p = PHY_DRV_ODT_40;
+ tsel_wr_select_ca_p = io->wr_ca_drv;
tsel_wr_select_ca_n = PHY_DRV_ODT_40;
} else if (sdram_params->base.dramtype == LPDDR3) {
tsel_rd_select_p = PHY_DRV_ODT_240;
@@ -728,7 +758,7 @@ static void pctl_start(struct dram_info *dram,
}
static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
- u32 channel, const struct rk3399_sdram_params *sdram_params)
+ u32 channel, struct rk3399_sdram_params *sdram_params)
{
u32 *denali_ctl = chan->pctl->denali_ctl;
u32 *denali_pi = chan->pi->denali_pi;
@@ -812,7 +842,7 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
copy_to_reg(&denali_phy[512], ¶ms_phy[512], (549 - 512 + 1) * 4);
copy_to_reg(&denali_phy[640], ¶ms_phy[640], (677 - 640 + 1) * 4);
copy_to_reg(&denali_phy[768], ¶ms_phy[768], (805 - 768 + 1) * 4);
- set_ds_odt(chan, sdram_params);
+ set_ds_odt(chan, sdram_params, 0);
/*
* phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_84/212/340/468 offset_8
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 71/92] ram: sdram: Configure lpddr4 tsel rd, wr based on IO settings
@ 2019-06-11 14:51 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: u-boot
Now we have IO settings available for all supported sdram
frequencies, so retrieve these IO settings and make used
for LPDDR4 ds odt configuration.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 42 ++++++++++++++++++++++++-----
1 file changed, 36 insertions(+), 6 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 5db7cbe116..6385df5600 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -184,6 +184,33 @@ struct io_setting {
},
};
+/**
+ * phy = 0, PHY boot freq
+ * phy = 1, PHY index 0
+ * phy = 2, PHY index 1
+ */
+static struct io_setting *
+lpddr4_get_io_settings(const struct rk3399_sdram_params *params, u32 mr5)
+{
+ struct io_setting *io = NULL;
+ u32 n;
+
+ for (n = 0; n < ARRAY_SIZE(lpddr4_io_setting); n++) {
+ io = &lpddr4_io_setting[n];
+
+ if (io->mr5 != 0) {
+ if (io->mhz >= params->base.ddr_freq &&
+ io->mr5 == mr5)
+ break;
+ } else {
+ if (io->mhz >= params->base.ddr_freq)
+ break;
+ }
+ }
+
+ return io;
+}
+
static void *get_ddrc0_con(struct dram_info *dram, u8 channel)
{
return (channel == 0) ? &dram->grf->ddrc0_con0 : &dram->grf->ddrc0_con1;
@@ -525,7 +552,7 @@ static int phy_io_config(const struct chan_info *chan,
}
static void set_ds_odt(const struct chan_info *chan,
- const struct rk3399_sdram_params *sdram_params)
+ const struct rk3399_sdram_params *sdram_params, u32 mr5)
{
u32 *denali_phy = chan->publ->denali_phy;
@@ -534,19 +561,22 @@ static void set_ds_odt(const struct chan_info *chan,
u32 tsel_idle_select_n, tsel_rd_select_n;
u32 tsel_wr_select_dq_p, tsel_wr_select_ca_p;
u32 tsel_wr_select_dq_n, tsel_wr_select_ca_n;
+ struct io_setting *io = NULL;
u32 reg_value;
if (sdram_params->base.dramtype == LPDDR4) {
+ io = lpddr4_get_io_settings(sdram_params, mr5);
+
tsel_rd_select_p = PHY_DRV_ODT_HI_Z;
- tsel_rd_select_n = PHY_DRV_ODT_240;
+ tsel_rd_select_n = io->rd_odt;
tsel_idle_select_p = PHY_DRV_ODT_HI_Z;
tsel_idle_select_n = PHY_DRV_ODT_240;
- tsel_wr_select_dq_p = PHY_DRV_ODT_40;
+ tsel_wr_select_dq_p = io->wr_dq_drv;
tsel_wr_select_dq_n = PHY_DRV_ODT_40;
- tsel_wr_select_ca_p = PHY_DRV_ODT_40;
+ tsel_wr_select_ca_p = io->wr_ca_drv;
tsel_wr_select_ca_n = PHY_DRV_ODT_40;
} else if (sdram_params->base.dramtype == LPDDR3) {
tsel_rd_select_p = PHY_DRV_ODT_240;
@@ -728,7 +758,7 @@ static void pctl_start(struct dram_info *dram,
}
static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
- u32 channel, const struct rk3399_sdram_params *sdram_params)
+ u32 channel, struct rk3399_sdram_params *sdram_params)
{
u32 *denali_ctl = chan->pctl->denali_ctl;
u32 *denali_pi = chan->pi->denali_pi;
@@ -812,7 +842,7 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
copy_to_reg(&denali_phy[512], ¶ms_phy[512], (549 - 512 + 1) * 4);
copy_to_reg(&denali_phy[640], ¶ms_phy[640], (677 - 640 + 1) * 4);
copy_to_reg(&denali_phy[768], ¶ms_phy[768], (805 - 768 + 1) * 4);
- set_ds_odt(chan, sdram_params);
+ set_ds_odt(chan, sdram_params, 0);
/*
* phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_84/212/340/468 offset_8
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 72/92] ram: rk3399: Add tsel control clock drive
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:51 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
tsel contrl clock drives are required to configure PHY
929, 939 controls drive settings.
Add support for these control clock for all dramtype
sdrams.
Thse control clock drives are configure via tsel_ckcs_select_p
and tsel_ckcs_select_n variables.
tsel_ckcs_select_n is PHY_DRV_ODT_34_3 value where as
tsel_ckcs_select_p is retrived from IO settings for lpddr4
and rest uses PHY_DRV_ODT_34_3.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 6385df5600..8eaa304e95 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -561,6 +561,7 @@ static void set_ds_odt(const struct chan_info *chan,
u32 tsel_idle_select_n, tsel_rd_select_n;
u32 tsel_wr_select_dq_p, tsel_wr_select_ca_p;
u32 tsel_wr_select_dq_n, tsel_wr_select_ca_n;
+ u32 tsel_ckcs_select_p, tsel_ckcs_select_n;
struct io_setting *io = NULL;
u32 reg_value;
@@ -578,6 +579,9 @@ static void set_ds_odt(const struct chan_info *chan,
tsel_wr_select_ca_p = io->wr_ca_drv;
tsel_wr_select_ca_n = PHY_DRV_ODT_40;
+
+ tsel_ckcs_select_p = io->wr_ckcs_drv;
+ tsel_ckcs_select_n = PHY_DRV_ODT_34_3;
} else if (sdram_params->base.dramtype == LPDDR3) {
tsel_rd_select_p = PHY_DRV_ODT_240;
tsel_rd_select_n = PHY_DRV_ODT_HI_Z;
@@ -590,6 +594,9 @@ static void set_ds_odt(const struct chan_info *chan,
tsel_wr_select_ca_p = PHY_DRV_ODT_48;
tsel_wr_select_ca_n = PHY_DRV_ODT_48;
+
+ tsel_ckcs_select_p = PHY_DRV_ODT_34_3;
+ tsel_ckcs_select_n = PHY_DRV_ODT_34_3;
} else {
tsel_rd_select_p = PHY_DRV_ODT_240;
tsel_rd_select_n = PHY_DRV_ODT_240;
@@ -602,6 +609,9 @@ static void set_ds_odt(const struct chan_info *chan,
tsel_wr_select_ca_p = PHY_DRV_ODT_34_3;
tsel_wr_select_ca_n = PHY_DRV_ODT_34_3;
+
+ tsel_ckcs_select_p = PHY_DRV_ODT_34_3;
+ tsel_ckcs_select_n = PHY_DRV_ODT_34_3;
}
if (sdram_params->base.odt == 1)
@@ -660,10 +670,12 @@ static void set_ds_odt(const struct chan_info *chan,
clrsetbits_le32(&denali_phy[935], 0xff, reg_value);
/* phy_pad_cs_drive 8bits DENALI_PHY_939 offset_0 */
- clrsetbits_le32(&denali_phy[939], 0xff, reg_value);
+ clrsetbits_le32(&denali_phy[939], 0xff,
+ tsel_ckcs_select_n | (tsel_ckcs_select_p << 0x4));
/* phy_pad_clk_drive 8bits DENALI_PHY_929 offset_0 */
- clrsetbits_le32(&denali_phy[929], 0xff, reg_value);
+ clrsetbits_le32(&denali_phy[929], 0xff,
+ tsel_ckcs_select_n | (tsel_ckcs_select_p << 0x4));
/* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */
clrsetbits_le32(&denali_phy[924], 0xff,
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 72/92] ram: rk3399: Add tsel control clock drive
@ 2019-06-11 14:51 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: u-boot
tsel contrl clock drives are required to configure PHY
929, 939 controls drive settings.
Add support for these control clock for all dramtype
sdrams.
Thse control clock drives are configure via tsel_ckcs_select_p
and tsel_ckcs_select_n variables.
tsel_ckcs_select_n is PHY_DRV_ODT_34_3 value where as
tsel_ckcs_select_p is retrived from IO settings for lpddr4
and rest uses PHY_DRV_ODT_34_3.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 6385df5600..8eaa304e95 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -561,6 +561,7 @@ static void set_ds_odt(const struct chan_info *chan,
u32 tsel_idle_select_n, tsel_rd_select_n;
u32 tsel_wr_select_dq_p, tsel_wr_select_ca_p;
u32 tsel_wr_select_dq_n, tsel_wr_select_ca_n;
+ u32 tsel_ckcs_select_p, tsel_ckcs_select_n;
struct io_setting *io = NULL;
u32 reg_value;
@@ -578,6 +579,9 @@ static void set_ds_odt(const struct chan_info *chan,
tsel_wr_select_ca_p = io->wr_ca_drv;
tsel_wr_select_ca_n = PHY_DRV_ODT_40;
+
+ tsel_ckcs_select_p = io->wr_ckcs_drv;
+ tsel_ckcs_select_n = PHY_DRV_ODT_34_3;
} else if (sdram_params->base.dramtype == LPDDR3) {
tsel_rd_select_p = PHY_DRV_ODT_240;
tsel_rd_select_n = PHY_DRV_ODT_HI_Z;
@@ -590,6 +594,9 @@ static void set_ds_odt(const struct chan_info *chan,
tsel_wr_select_ca_p = PHY_DRV_ODT_48;
tsel_wr_select_ca_n = PHY_DRV_ODT_48;
+
+ tsel_ckcs_select_p = PHY_DRV_ODT_34_3;
+ tsel_ckcs_select_n = PHY_DRV_ODT_34_3;
} else {
tsel_rd_select_p = PHY_DRV_ODT_240;
tsel_rd_select_n = PHY_DRV_ODT_240;
@@ -602,6 +609,9 @@ static void set_ds_odt(const struct chan_info *chan,
tsel_wr_select_ca_p = PHY_DRV_ODT_34_3;
tsel_wr_select_ca_n = PHY_DRV_ODT_34_3;
+
+ tsel_ckcs_select_p = PHY_DRV_ODT_34_3;
+ tsel_ckcs_select_n = PHY_DRV_ODT_34_3;
}
if (sdram_params->base.odt == 1)
@@ -660,10 +670,12 @@ static void set_ds_odt(const struct chan_info *chan,
clrsetbits_le32(&denali_phy[935], 0xff, reg_value);
/* phy_pad_cs_drive 8bits DENALI_PHY_939 offset_0 */
- clrsetbits_le32(&denali_phy[939], 0xff, reg_value);
+ clrsetbits_le32(&denali_phy[939], 0xff,
+ tsel_ckcs_select_n | (tsel_ckcs_select_p << 0x4));
/* phy_pad_clk_drive 8bits DENALI_PHY_929 offset_0 */
- clrsetbits_le32(&denali_phy[929], 0xff, reg_value);
+ clrsetbits_le32(&denali_phy[929], 0xff,
+ tsel_ckcs_select_n | (tsel_ckcs_select_p << 0x4));
/* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */
clrsetbits_le32(&denali_phy[924], 0xff,
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 73/92] ram: rk3399: Configure soc odt support
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:51 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
CTL 145, 146, 159, 160 registers are used to configure
soc odt on rk3399.
These soc odt values are updated from CS0_MR22_VAL and
CS1_MR22_VAL and for lpddr4 these values ORed with
tsel_rd_select_n.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 49 ++++++++++++++++++++++++++++-
1 file changed, 48 insertions(+), 1 deletion(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 8eaa304e95..2ce9066d53 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -40,6 +40,8 @@
#define PHY_SLEWP_EN 0x1
#define PHY_SLEWN_EN 0x1
#define PHY_RX_CM_INPUT 0x1
+#define CS0_MR22_VAL 0
+#define CS1_MR22_VAL 3
#define CRU_SFTRST_DDR_CTRL(ch, n) ((0x1 << (8 + 16 + (ch) * 4)) | \
((n) << (8 + (ch) * 4)))
@@ -555,7 +557,7 @@ static void set_ds_odt(const struct chan_info *chan,
const struct rk3399_sdram_params *sdram_params, u32 mr5)
{
u32 *denali_phy = chan->publ->denali_phy;
-
+ u32 *denali_ctl = chan->pctl->denali_ctl;
u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
u32 tsel_idle_select_p, tsel_rd_select_p;
u32 tsel_idle_select_n, tsel_rd_select_n;
@@ -563,6 +565,7 @@ static void set_ds_odt(const struct chan_info *chan,
u32 tsel_wr_select_dq_n, tsel_wr_select_ca_n;
u32 tsel_ckcs_select_p, tsel_ckcs_select_n;
struct io_setting *io = NULL;
+ u32 soc_odt = 0;
u32 reg_value;
if (sdram_params->base.dramtype == LPDDR4) {
@@ -582,6 +585,35 @@ static void set_ds_odt(const struct chan_info *chan,
tsel_ckcs_select_p = io->wr_ckcs_drv;
tsel_ckcs_select_n = PHY_DRV_ODT_34_3;
+ switch (tsel_rd_select_n) {
+ case PHY_DRV_ODT_240:
+ soc_odt = 1;
+ break;
+ case PHY_DRV_ODT_120:
+ soc_odt = 2;
+ break;
+ case PHY_DRV_ODT_80:
+ soc_odt = 3;
+ break;
+ case PHY_DRV_ODT_60:
+ soc_odt = 4;
+ break;
+ case PHY_DRV_ODT_48:
+ soc_odt = 5;
+ break;
+ case PHY_DRV_ODT_40:
+ soc_odt = 6;
+ break;
+ case PHY_DRV_ODT_34_3:
+ soc_odt = 6;
+ printf("%s: Unable to support LPDDR4 MR22 Soc ODT\n",
+ __func__);
+ break;
+ case PHY_DRV_ODT_HI_Z:
+ default:
+ soc_odt = 0;
+ break;
+ }
} else if (sdram_params->base.dramtype == LPDDR3) {
tsel_rd_select_p = PHY_DRV_ODT_240;
tsel_rd_select_n = PHY_DRV_ODT_HI_Z;
@@ -622,6 +654,21 @@ static void set_ds_odt(const struct chan_info *chan,
tsel_wr_en = 0;
tsel_idle_en = 0;
+ /* F0_0 */
+ clrsetbits_le32(&denali_ctl[145], 0xFF << 16,
+ (soc_odt | (CS0_MR22_VAL << 3)) << 16);
+ /* F2_0, F1_0 */
+ clrsetbits_le32(&denali_ctl[146], 0xFF00FF,
+ ((soc_odt | (CS0_MR22_VAL << 3)) << 16) |
+ (soc_odt | (CS0_MR22_VAL << 3)));
+ /* F0_1 */
+ clrsetbits_le32(&denali_ctl[159], 0xFF << 16,
+ (soc_odt | (CS1_MR22_VAL << 3)) << 16);
+ /* F2_1, F1_1 */
+ clrsetbits_le32(&denali_ctl[160], 0xFF00FF,
+ ((soc_odt | (CS1_MR22_VAL << 3)) << 16) |
+ (soc_odt | (CS1_MR22_VAL << 3)));
+
/*
* phy_dq_tsel_select_X 24bits DENALI_PHY_6/134/262/390 offset_0
* sets termination values for read/idle cycles and drive strength
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 73/92] ram: rk3399: Configure soc odt support
@ 2019-06-11 14:51 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: u-boot
CTL 145, 146, 159, 160 registers are used to configure
soc odt on rk3399.
These soc odt values are updated from CS0_MR22_VAL and
CS1_MR22_VAL and for lpddr4 these values ORed with
tsel_rd_select_n.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 49 ++++++++++++++++++++++++++++-
1 file changed, 48 insertions(+), 1 deletion(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 8eaa304e95..2ce9066d53 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -40,6 +40,8 @@
#define PHY_SLEWP_EN 0x1
#define PHY_SLEWN_EN 0x1
#define PHY_RX_CM_INPUT 0x1
+#define CS0_MR22_VAL 0
+#define CS1_MR22_VAL 3
#define CRU_SFTRST_DDR_CTRL(ch, n) ((0x1 << (8 + 16 + (ch) * 4)) | \
((n) << (8 + (ch) * 4)))
@@ -555,7 +557,7 @@ static void set_ds_odt(const struct chan_info *chan,
const struct rk3399_sdram_params *sdram_params, u32 mr5)
{
u32 *denali_phy = chan->publ->denali_phy;
-
+ u32 *denali_ctl = chan->pctl->denali_ctl;
u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
u32 tsel_idle_select_p, tsel_rd_select_p;
u32 tsel_idle_select_n, tsel_rd_select_n;
@@ -563,6 +565,7 @@ static void set_ds_odt(const struct chan_info *chan,
u32 tsel_wr_select_dq_n, tsel_wr_select_ca_n;
u32 tsel_ckcs_select_p, tsel_ckcs_select_n;
struct io_setting *io = NULL;
+ u32 soc_odt = 0;
u32 reg_value;
if (sdram_params->base.dramtype == LPDDR4) {
@@ -582,6 +585,35 @@ static void set_ds_odt(const struct chan_info *chan,
tsel_ckcs_select_p = io->wr_ckcs_drv;
tsel_ckcs_select_n = PHY_DRV_ODT_34_3;
+ switch (tsel_rd_select_n) {
+ case PHY_DRV_ODT_240:
+ soc_odt = 1;
+ break;
+ case PHY_DRV_ODT_120:
+ soc_odt = 2;
+ break;
+ case PHY_DRV_ODT_80:
+ soc_odt = 3;
+ break;
+ case PHY_DRV_ODT_60:
+ soc_odt = 4;
+ break;
+ case PHY_DRV_ODT_48:
+ soc_odt = 5;
+ break;
+ case PHY_DRV_ODT_40:
+ soc_odt = 6;
+ break;
+ case PHY_DRV_ODT_34_3:
+ soc_odt = 6;
+ printf("%s: Unable to support LPDDR4 MR22 Soc ODT\n",
+ __func__);
+ break;
+ case PHY_DRV_ODT_HI_Z:
+ default:
+ soc_odt = 0;
+ break;
+ }
} else if (sdram_params->base.dramtype == LPDDR3) {
tsel_rd_select_p = PHY_DRV_ODT_240;
tsel_rd_select_n = PHY_DRV_ODT_HI_Z;
@@ -622,6 +654,21 @@ static void set_ds_odt(const struct chan_info *chan,
tsel_wr_en = 0;
tsel_idle_en = 0;
+ /* F0_0 */
+ clrsetbits_le32(&denali_ctl[145], 0xFF << 16,
+ (soc_odt | (CS0_MR22_VAL << 3)) << 16);
+ /* F2_0, F1_0 */
+ clrsetbits_le32(&denali_ctl[146], 0xFF00FF,
+ ((soc_odt | (CS0_MR22_VAL << 3)) << 16) |
+ (soc_odt | (CS0_MR22_VAL << 3)));
+ /* F0_1 */
+ clrsetbits_le32(&denali_ctl[159], 0xFF << 16,
+ (soc_odt | (CS1_MR22_VAL << 3)) << 16);
+ /* F2_1, F1_1 */
+ clrsetbits_le32(&denali_ctl[160], 0xFF00FF,
+ ((soc_odt | (CS1_MR22_VAL << 3)) << 16) |
+ (soc_odt | (CS1_MR22_VAL << 3)));
+
/*
* phy_dq_tsel_select_X 24bits DENALI_PHY_6/134/262/390 offset_0
* sets termination values for read/idle cycles and drive strength
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 74/92] ram: rk3399: Get lpddr4 tsel_rd_en from io settings
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:51 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
For base.odt 1 the lpddr4 tsel_rd_en value is depending
on IO settings of rd_odt_en.
Add support for it.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 2ce9066d53..c0e9a4e7c8 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -646,10 +646,14 @@ static void set_ds_odt(const struct chan_info *chan,
tsel_ckcs_select_n = PHY_DRV_ODT_34_3;
}
- if (sdram_params->base.odt == 1)
+ if (sdram_params->base.odt == 1) {
tsel_rd_en = 1;
- else
+
+ if (sdram_params->base.dramtype == LPDDR4)
+ tsel_rd_en = io->rd_odt_en;
+ } else {
tsel_rd_en = 0;
+ }
tsel_wr_en = 0;
tsel_idle_en = 0;
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 74/92] ram: rk3399: Get lpddr4 tsel_rd_en from io settings
@ 2019-06-11 14:51 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: u-boot
For base.odt 1 the lpddr4 tsel_rd_en value is depending
on IO settings of rd_odt_en.
Add support for it.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 2ce9066d53..c0e9a4e7c8 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -646,10 +646,14 @@ static void set_ds_odt(const struct chan_info *chan,
tsel_ckcs_select_n = PHY_DRV_ODT_34_3;
}
- if (sdram_params->base.odt == 1)
+ if (sdram_params->base.odt == 1) {
tsel_rd_en = 1;
- else
+
+ if (sdram_params->base.dramtype == LPDDR4)
+ tsel_rd_en = io->rd_odt_en;
+ } else {
tsel_rd_en = 0;
+ }
tsel_wr_en = 0;
tsel_idle_en = 0;
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 75/92] ram: rk3399: Update lpddr4 vref based on io settings
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:51 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
The vref_mode_dq, vref_value_dq on lpddr4 value is depending
on IO settings of rd_vref.
Add support for it.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 21 ++++++++++++++++-----
1 file changed, 16 insertions(+), 5 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index c0e9a4e7c8..413469f4cc 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -339,7 +339,8 @@ static void set_memory_map(const struct chan_info *chan, u32 channel,
}
static int phy_io_config(const struct chan_info *chan,
- const struct rk3399_sdram_params *sdram_params)
+ const struct rk3399_sdram_params *sdram_params,
+ u32 mr5)
{
u32 *denali_phy = chan->publ->denali_phy;
u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac;
@@ -350,9 +351,19 @@ static int phy_io_config(const struct chan_info *chan,
/* vref setting */
if (sdram_params->base.dramtype == LPDDR4) {
- /* LPDDR4 */
- vref_mode_dq = 0x6;
- vref_value_dq = 0x1f;
+ struct io_setting *io = lpddr4_get_io_settings(sdram_params,
+ mr5);
+ u32 rd_vref = io->rd_vref * 1000;
+
+ if (rd_vref < 36700) {
+ /* MODE_LV[2:0] = LPDDR4 (Range 2)*/
+ vref_mode_dq = 0x7;
+ vref_value_dq = (rd_vref - 3300) / 521;
+ } else {
+ /* MODE_LV[2:0] = LPDDR4 (Range 1)*/
+ vref_mode_dq = 0x6;
+ vref_value_dq = (rd_vref - 15300) / 521;
+ }
vref_mode_ac = 0x6;
vref_value_ac = 0x1f;
mode_sel = 0x6;
@@ -771,7 +782,7 @@ static void set_ds_odt(const struct chan_info *chan,
/* phy_pad_fdbk_term 1bit DENALI_PHY_930 offset_17 */
clrsetbits_le32(&denali_phy[930], 0x1 << 17, reg_value);
- phy_io_config(chan, sdram_params);
+ phy_io_config(chan, sdram_params, mr5);
}
static void pctl_start(struct dram_info *dram,
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 75/92] ram: rk3399: Update lpddr4 vref based on io settings
@ 2019-06-11 14:51 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: u-boot
The vref_mode_dq, vref_value_dq on lpddr4 value is depending
on IO settings of rd_vref.
Add support for it.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 21 ++++++++++++++++-----
1 file changed, 16 insertions(+), 5 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index c0e9a4e7c8..413469f4cc 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -339,7 +339,8 @@ static void set_memory_map(const struct chan_info *chan, u32 channel,
}
static int phy_io_config(const struct chan_info *chan,
- const struct rk3399_sdram_params *sdram_params)
+ const struct rk3399_sdram_params *sdram_params,
+ u32 mr5)
{
u32 *denali_phy = chan->publ->denali_phy;
u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac;
@@ -350,9 +351,19 @@ static int phy_io_config(const struct chan_info *chan,
/* vref setting */
if (sdram_params->base.dramtype == LPDDR4) {
- /* LPDDR4 */
- vref_mode_dq = 0x6;
- vref_value_dq = 0x1f;
+ struct io_setting *io = lpddr4_get_io_settings(sdram_params,
+ mr5);
+ u32 rd_vref = io->rd_vref * 1000;
+
+ if (rd_vref < 36700) {
+ /* MODE_LV[2:0] = LPDDR4 (Range 2)*/
+ vref_mode_dq = 0x7;
+ vref_value_dq = (rd_vref - 3300) / 521;
+ } else {
+ /* MODE_LV[2:0] = LPDDR4 (Range 1)*/
+ vref_mode_dq = 0x6;
+ vref_value_dq = (rd_vref - 15300) / 521;
+ }
vref_mode_ac = 0x6;
vref_value_ac = 0x1f;
mode_sel = 0x6;
@@ -771,7 +782,7 @@ static void set_ds_odt(const struct chan_info *chan,
/* phy_pad_fdbk_term 1bit DENALI_PHY_930 offset_17 */
clrsetbits_le32(&denali_phy[930], 0x1 << 17, reg_value);
- phy_io_config(chan, sdram_params);
+ phy_io_config(chan, sdram_params, mr5);
}
static void pctl_start(struct dram_info *dram,
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 76/92] ram: rk3399: Update lpddr4 mode_sel based on io settings
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:51 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
The mode_sel on lpddr4 value is depending on IO settings
of rd_vref.
Add support for it.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 413469f4cc..618327983a 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -349,7 +349,7 @@ static int phy_io_config(const struct chan_info *chan,
u32 drv_value, odt_value;
u32 speed;
- /* vref setting */
+ /* vref setting & mode setting */
if (sdram_params->base.dramtype == LPDDR4) {
struct io_setting *io = lpddr4_get_io_settings(sdram_params,
mr5);
@@ -358,15 +358,18 @@ static int phy_io_config(const struct chan_info *chan,
if (rd_vref < 36700) {
/* MODE_LV[2:0] = LPDDR4 (Range 2)*/
vref_mode_dq = 0x7;
+ /* MODE[2:0]= LPDDR4 Range 2(0.4*VDDQ) */
+ mode_sel = 0x5;
vref_value_dq = (rd_vref - 3300) / 521;
} else {
/* MODE_LV[2:0] = LPDDR4 (Range 1)*/
vref_mode_dq = 0x6;
+ /* MODE[2:0]= LPDDR4 Range 1(0.33*VDDQ) */
+ mode_sel = 0x4;
vref_value_dq = (rd_vref - 15300) / 521;
}
vref_mode_ac = 0x6;
vref_value_ac = 0x1f;
- mode_sel = 0x6;
} else if (sdram_params->base.dramtype == LPDDR3) {
if (sdram_params->base.odt == 1) {
vref_mode_dq = 0x5; /* LPDDR3 ODT */
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 76/92] ram: rk3399: Update lpddr4 mode_sel based on io settings
@ 2019-06-11 14:51 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: u-boot
The mode_sel on lpddr4 value is depending on IO settings
of rd_vref.
Add support for it.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 413469f4cc..618327983a 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -349,7 +349,7 @@ static int phy_io_config(const struct chan_info *chan,
u32 drv_value, odt_value;
u32 speed;
- /* vref setting */
+ /* vref setting & mode setting */
if (sdram_params->base.dramtype == LPDDR4) {
struct io_setting *io = lpddr4_get_io_settings(sdram_params,
mr5);
@@ -358,15 +358,18 @@ static int phy_io_config(const struct chan_info *chan,
if (rd_vref < 36700) {
/* MODE_LV[2:0] = LPDDR4 (Range 2)*/
vref_mode_dq = 0x7;
+ /* MODE[2:0]= LPDDR4 Range 2(0.4*VDDQ) */
+ mode_sel = 0x5;
vref_value_dq = (rd_vref - 3300) / 521;
} else {
/* MODE_LV[2:0] = LPDDR4 (Range 1)*/
vref_mode_dq = 0x6;
+ /* MODE[2:0]= LPDDR4 Range 1(0.33*VDDQ) */
+ mode_sel = 0x4;
vref_value_dq = (rd_vref - 15300) / 521;
}
vref_mode_ac = 0x6;
vref_value_ac = 0x1f;
- mode_sel = 0x6;
} else if (sdram_params->base.dramtype == LPDDR3) {
if (sdram_params->base.odt == 1) {
vref_mode_dq = 0x5; /* LPDDR3 ODT */
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 77/92] ram: rk3399: Update lpddr4 vref_mode_ac
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:51 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Update vref_mode_ac for lpddr4 based on VDDQ/3/2=16.8%
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 618327983a..89348cf296 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -369,7 +369,8 @@ static int phy_io_config(const struct chan_info *chan,
vref_value_dq = (rd_vref - 15300) / 521;
}
vref_mode_ac = 0x6;
- vref_value_ac = 0x1f;
+ /* VDDQ/3/2=16.8% */
+ vref_value_ac = 0x3;
} else if (sdram_params->base.dramtype == LPDDR3) {
if (sdram_params->base.odt == 1) {
vref_mode_dq = 0x5; /* LPDDR3 ODT */
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 77/92] ram: rk3399: Update lpddr4 vref_mode_ac
@ 2019-06-11 14:51 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: u-boot
Update vref_mode_ac for lpddr4 based on VDDQ/3/2=16.8%
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 618327983a..89348cf296 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -369,7 +369,8 @@ static int phy_io_config(const struct chan_info *chan,
vref_value_dq = (rd_vref - 15300) / 521;
}
vref_mode_ac = 0x6;
- vref_value_ac = 0x1f;
+ /* VDDQ/3/2=16.8% */
+ vref_value_ac = 0x3;
} else if (sdram_params->base.dramtype == LPDDR3) {
if (sdram_params->base.odt == 1) {
vref_mode_dq = 0x5; /* LPDDR3 ODT */
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 78/92] ram: rk3399: Add LPPDR4 mr detection
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:51 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Like data training in other sdram types, mr detection need
to taken care for lpddr4 with looped rank and associated
channel to make sure the proper configuration held.
Once the mr detection successful for active and configured
rank with channel number, the same can later reused during
actual LPDDR4 initialization.
So, add code to support for it.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 254 ++++++++++++++++++++++++++--
1 file changed, 243 insertions(+), 11 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 89348cf296..5a0872c23f 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -218,6 +218,16 @@ static void *get_ddrc0_con(struct dram_info *dram, u8 channel)
return (channel == 0) ? &dram->grf->ddrc0_con0 : &dram->grf->ddrc0_con1;
}
+static u32 get_ddr_stride(struct rk3399_pmusgrf_regs *pmusgrf)
+{
+ return ((readl(&pmusgrf->soc_con4) >> 10) & 0x1F);
+}
+
+static void set_ddr_stride(struct rk3399_pmusgrf_regs *pmusgrf, u32 stride)
+{
+ rk_clrsetreg(&pmusgrf->soc_con4, 0x1f << 10, stride << 10);
+}
+
static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
{
int i;
@@ -1593,6 +1603,215 @@ static unsigned char calculate_stride(struct rk3399_sdram_params *sdram_params)
return stride;
}
+static void set_cap_relate_config(const struct chan_info *chan,
+ struct rk3399_sdram_params *sdram_params,
+ unsigned int channel)
+{
+ u32 *denali_ctl = chan->pctl->denali_ctl;
+ u32 tmp;
+ struct rk3399_msch_timings *noc_timing;
+
+ if (sdram_params->base.dramtype == LPDDR3) {
+ tmp = (8 << sdram_params->ch[channel].cap_info.bw) /
+ (8 << sdram_params->ch[channel].cap_info.dbw);
+
+ /**
+ * memdata_ratio
+ * 1 -> 0, 2 -> 1, 4 -> 2
+ */
+ clrsetbits_le32(&denali_ctl[197], 0x7,
+ (tmp >> 1));
+ clrsetbits_le32(&denali_ctl[198], 0x7 << 8,
+ (tmp >> 1) << 8);
+ }
+
+ noc_timing = &sdram_params->ch[channel].noc_timings;
+
+ /*
+ * noc timing bw relate timing is 32 bit, and real bw is 16bit
+ * actually noc reg is setting at function dram_all_config
+ */
+ if (sdram_params->ch[channel].cap_info.bw == 16 &&
+ noc_timing->ddrmode.b.mwrsize == 2) {
+ if (noc_timing->ddrmode.b.burstsize)
+ noc_timing->ddrmode.b.burstsize -= 1;
+ noc_timing->ddrmode.b.mwrsize -= 1;
+ noc_timing->ddrtimingc0.b.burstpenalty *= 2;
+ noc_timing->ddrtimingc0.b.wrtomwr *= 2;
+ }
+}
+
+static u32 calculate_ddrconfig(struct rk3399_sdram_params *sdram_params,
+ u32 channel)
+{
+ unsigned int cs0_row = sdram_params->ch[channel].cap_info.cs0_row;
+ unsigned int col = sdram_params->ch[channel].cap_info.col;
+ unsigned int bw = sdram_params->ch[channel].cap_info.bw;
+ u16 ddr_cfg_2_rbc[] = {
+ /*
+ * [6] highest bit col
+ * [5:3] max row(14+n)
+ * [2] insertion row
+ * [1:0] col(9+n),col, data bus 32bit
+ *
+ * highbitcol, max_row, insertion_row, col
+ */
+ ((0 << 6) | (2 << 3) | (0 << 2) | 0), /* 0 */
+ ((0 << 6) | (2 << 3) | (0 << 2) | 1), /* 1 */
+ ((0 << 6) | (1 << 3) | (0 << 2) | 2), /* 2 */
+ ((0 << 6) | (0 << 3) | (0 << 2) | 3), /* 3 */
+ ((0 << 6) | (2 << 3) | (1 << 2) | 1), /* 4 */
+ ((0 << 6) | (1 << 3) | (1 << 2) | 2), /* 5 */
+ ((1 << 6) | (0 << 3) | (0 << 2) | 2), /* 6 */
+ ((1 << 6) | (1 << 3) | (0 << 2) | 2), /* 7 */
+ };
+ u32 i;
+
+ col -= (bw == 2) ? 0 : 1;
+ col -= 9;
+
+ for (i = 0; i < 4; i++) {
+ if ((col == (ddr_cfg_2_rbc[i] & 0x3)) &&
+ (cs0_row <= (((ddr_cfg_2_rbc[i] >> 3) & 0x7) + 14)))
+ break;
+ }
+
+ if (i >= 4)
+ i = -EINVAL;
+
+ return i;
+}
+
+/**
+ * read mr_num mode register
+ * rank = 1: cs0
+ * rank = 2: cs1
+ */
+static int read_mr(struct rk3399_ddr_pctl_regs *ddr_pctl_regs, u32 rank,
+ u32 mr_num, u32 *buf)
+{
+ s32 timeout = 100;
+
+ writel(((1 << 16) | (((rank == 2) ? 1 : 0) << 8) | mr_num) << 8,
+ &ddr_pctl_regs->denali_ctl[118]);
+
+ while (0 == (readl(&ddr_pctl_regs->denali_ctl[203]) &
+ ((1 << 21) | (1 << 12)))) {
+ udelay(1);
+
+ if (timeout <= 0) {
+ printf("%s: pctl timeout!\n", __func__);
+ return -ETIMEDOUT;
+ }
+
+ timeout--;
+ }
+
+ if (!(readl(&ddr_pctl_regs->denali_ctl[203]) & (1 << 12))) {
+ *buf = readl(&ddr_pctl_regs->denali_ctl[119]) & 0xFF;
+ } else {
+ printf("%s: read mr failed with 0x%x status\n", __func__,
+ readl(&ddr_pctl_regs->denali_ctl[17]) & 0x3);
+ *buf = 0;
+ }
+
+ setbits_le32(&ddr_pctl_regs->denali_ctl[205], (1 << 21) | (1 << 12));
+
+ return 0;
+}
+
+static int lpddr4_mr_detect(struct dram_info *dram, u32 channel, u32 rank,
+ struct rk3399_sdram_params *sdram_params)
+{
+ u64 cs0_cap;
+ u32 stride;
+ u32 cs = 0, col = 0, bk = 0, bw = 0, row_3_4 = 0;
+ u32 cs0_row = 0, cs1_row = 0, ddrconfig = 0;
+ u32 mr5, mr12, mr14;
+ struct chan_info *chan = &dram->chan[channel];
+ struct rk3399_ddr_pctl_regs *ddr_pctl_regs = chan->pctl;
+ void __iomem *addr = NULL;
+ int ret = 0;
+ u32 val;
+
+ stride = get_ddr_stride(dram->pmusgrf);
+
+ if (sdram_params->ch[channel].cap_info.col == 0) {
+ ret = -EPERM;
+ goto end;
+ }
+
+ cs = sdram_params->ch[channel].cap_info.rank;
+ col = sdram_params->ch[channel].cap_info.col;
+ bk = sdram_params->ch[channel].cap_info.bk;
+ bw = sdram_params->ch[channel].cap_info.bw;
+ row_3_4 = sdram_params->ch[channel].cap_info.row_3_4;
+ cs0_row = sdram_params->ch[channel].cap_info.cs0_row;
+ cs1_row = sdram_params->ch[channel].cap_info.cs1_row;
+ ddrconfig = sdram_params->ch[channel].cap_info.ddrconfig;
+
+ /* 2GB */
+ sdram_params->ch[channel].cap_info.rank = 2;
+ sdram_params->ch[channel].cap_info.col = 10;
+ sdram_params->ch[channel].cap_info.bk = 3;
+ sdram_params->ch[channel].cap_info.bw = 2;
+ sdram_params->ch[channel].cap_info.row_3_4 = 0;
+ sdram_params->ch[channel].cap_info.cs0_row = 15;
+ sdram_params->ch[channel].cap_info.cs1_row = 15;
+ sdram_params->ch[channel].cap_info.ddrconfig = 1;
+
+ set_memory_map(chan, channel, sdram_params);
+ sdram_params->ch[channel].cap_info.ddrconfig =
+ calculate_ddrconfig(sdram_params, channel);
+ set_ddrconfig(chan, sdram_params, channel,
+ sdram_params->ch[channel].cap_info.ddrconfig);
+ set_cap_relate_config(chan, sdram_params, channel);
+
+ cs0_cap = (1 << (sdram_params->ch[channel].cap_info.bw
+ + sdram_params->ch[channel].cap_info.col
+ + sdram_params->ch[channel].cap_info.bk
+ + sdram_params->ch[channel].cap_info.cs0_row));
+
+ if (sdram_params->ch[channel].cap_info.row_3_4)
+ cs0_cap = cs0_cap * 3 / 4;
+
+ if (channel == 0)
+ set_ddr_stride(dram->pmusgrf, 0x17);
+ else
+ set_ddr_stride(dram->pmusgrf, 0x18);
+
+ /* read and write data to DRAM, avoid be optimized by compiler. */
+ if (rank == 1)
+ addr = (void __iomem *)0x100;
+ else if (rank == 2)
+ addr = (void __iomem *)(cs0_cap + 0x100);
+
+ val = readl(addr);
+ writel(val + 1, addr);
+
+ read_mr(ddr_pctl_regs, rank, 5, &mr5);
+ read_mr(ddr_pctl_regs, rank, 12, &mr12);
+ read_mr(ddr_pctl_regs, rank, 14, &mr14);
+
+ if (mr5 == 0 || mr12 != 0x4d || mr14 != 0x4d) {
+ ret = -EINVAL;
+ goto end;
+ }
+end:
+ sdram_params->ch[channel].cap_info.rank = cs;
+ sdram_params->ch[channel].cap_info.col = col;
+ sdram_params->ch[channel].cap_info.bk = bk;
+ sdram_params->ch[channel].cap_info.bw = bw;
+ sdram_params->ch[channel].cap_info.row_3_4 = row_3_4;
+ sdram_params->ch[channel].cap_info.cs0_row = cs0_row;
+ sdram_params->ch[channel].cap_info.cs1_row = cs1_row;
+ sdram_params->ch[channel].cap_info.ddrconfig = ddrconfig;
+
+ set_ddr_stride(dram->pmusgrf, stride);
+
+ return ret;
+}
+
static void clear_channel_params(struct rk3399_sdram_params *params, u8 channel)
{
params->ch[channel].cap_info.rank = 0;
@@ -1665,17 +1884,30 @@ static int sdram_init(struct dram_info *dram,
sdram_params->ch[ch].cap_info.rank = rank;
- /*
- * LPDDR3 CA training msut be trigger before
- * other training.
- * DDR3 is not have CA training.
- */
- if (sdram_params->base.dramtype == LPDDR3)
- training_flag |= PI_CA_TRAINING;
-
- if (!(data_training(&dram->chan[ch], ch,
- sdram_params, training_flag)))
- break;
+ if (sdram_params->base.dramtype == LPDDR4) {
+ if (!lpddr4_mr_detect(dram, ch, rank,
+ sdram_params)) {
+ debug("%s: lpddr4 mr detected for rank %d, ch %d\n",
+ __func__, rank, ch);
+ break;
+ }
+ } else {
+ /*
+ * LPDDR3 CA training msut be trigger before
+ * other training.
+ * DDR3 is not have CA training.
+ */
+ if (sdram_params->base.dramtype == LPDDR3)
+ training_flag |= PI_CA_TRAINING;
+
+ if (!(data_training(&dram->chan[ch], ch,
+ sdram_params,
+ training_flag))) {
+ debug("%s: data trained for rank %d, ch %d\n",
+ __func__, rank, ch);
+ break;
+ }
+ }
}
/* Computed rank with associated channel number */
sdram_params->ch[ch].cap_info.rank = rank;
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 78/92] ram: rk3399: Add LPPDR4 mr detection
@ 2019-06-11 14:51 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: u-boot
Like data training in other sdram types, mr detection need
to taken care for lpddr4 with looped rank and associated
channel to make sure the proper configuration held.
Once the mr detection successful for active and configured
rank with channel number, the same can later reused during
actual LPDDR4 initialization.
So, add code to support for it.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 254 ++++++++++++++++++++++++++--
1 file changed, 243 insertions(+), 11 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 89348cf296..5a0872c23f 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -218,6 +218,16 @@ static void *get_ddrc0_con(struct dram_info *dram, u8 channel)
return (channel == 0) ? &dram->grf->ddrc0_con0 : &dram->grf->ddrc0_con1;
}
+static u32 get_ddr_stride(struct rk3399_pmusgrf_regs *pmusgrf)
+{
+ return ((readl(&pmusgrf->soc_con4) >> 10) & 0x1F);
+}
+
+static void set_ddr_stride(struct rk3399_pmusgrf_regs *pmusgrf, u32 stride)
+{
+ rk_clrsetreg(&pmusgrf->soc_con4, 0x1f << 10, stride << 10);
+}
+
static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
{
int i;
@@ -1593,6 +1603,215 @@ static unsigned char calculate_stride(struct rk3399_sdram_params *sdram_params)
return stride;
}
+static void set_cap_relate_config(const struct chan_info *chan,
+ struct rk3399_sdram_params *sdram_params,
+ unsigned int channel)
+{
+ u32 *denali_ctl = chan->pctl->denali_ctl;
+ u32 tmp;
+ struct rk3399_msch_timings *noc_timing;
+
+ if (sdram_params->base.dramtype == LPDDR3) {
+ tmp = (8 << sdram_params->ch[channel].cap_info.bw) /
+ (8 << sdram_params->ch[channel].cap_info.dbw);
+
+ /**
+ * memdata_ratio
+ * 1 -> 0, 2 -> 1, 4 -> 2
+ */
+ clrsetbits_le32(&denali_ctl[197], 0x7,
+ (tmp >> 1));
+ clrsetbits_le32(&denali_ctl[198], 0x7 << 8,
+ (tmp >> 1) << 8);
+ }
+
+ noc_timing = &sdram_params->ch[channel].noc_timings;
+
+ /*
+ * noc timing bw relate timing is 32 bit, and real bw is 16bit
+ * actually noc reg is setting at function dram_all_config
+ */
+ if (sdram_params->ch[channel].cap_info.bw == 16 &&
+ noc_timing->ddrmode.b.mwrsize == 2) {
+ if (noc_timing->ddrmode.b.burstsize)
+ noc_timing->ddrmode.b.burstsize -= 1;
+ noc_timing->ddrmode.b.mwrsize -= 1;
+ noc_timing->ddrtimingc0.b.burstpenalty *= 2;
+ noc_timing->ddrtimingc0.b.wrtomwr *= 2;
+ }
+}
+
+static u32 calculate_ddrconfig(struct rk3399_sdram_params *sdram_params,
+ u32 channel)
+{
+ unsigned int cs0_row = sdram_params->ch[channel].cap_info.cs0_row;
+ unsigned int col = sdram_params->ch[channel].cap_info.col;
+ unsigned int bw = sdram_params->ch[channel].cap_info.bw;
+ u16 ddr_cfg_2_rbc[] = {
+ /*
+ * [6] highest bit col
+ * [5:3] max row(14+n)
+ * [2] insertion row
+ * [1:0] col(9+n),col, data bus 32bit
+ *
+ * highbitcol, max_row, insertion_row, col
+ */
+ ((0 << 6) | (2 << 3) | (0 << 2) | 0), /* 0 */
+ ((0 << 6) | (2 << 3) | (0 << 2) | 1), /* 1 */
+ ((0 << 6) | (1 << 3) | (0 << 2) | 2), /* 2 */
+ ((0 << 6) | (0 << 3) | (0 << 2) | 3), /* 3 */
+ ((0 << 6) | (2 << 3) | (1 << 2) | 1), /* 4 */
+ ((0 << 6) | (1 << 3) | (1 << 2) | 2), /* 5 */
+ ((1 << 6) | (0 << 3) | (0 << 2) | 2), /* 6 */
+ ((1 << 6) | (1 << 3) | (0 << 2) | 2), /* 7 */
+ };
+ u32 i;
+
+ col -= (bw == 2) ? 0 : 1;
+ col -= 9;
+
+ for (i = 0; i < 4; i++) {
+ if ((col == (ddr_cfg_2_rbc[i] & 0x3)) &&
+ (cs0_row <= (((ddr_cfg_2_rbc[i] >> 3) & 0x7) + 14)))
+ break;
+ }
+
+ if (i >= 4)
+ i = -EINVAL;
+
+ return i;
+}
+
+/**
+ * read mr_num mode register
+ * rank = 1: cs0
+ * rank = 2: cs1
+ */
+static int read_mr(struct rk3399_ddr_pctl_regs *ddr_pctl_regs, u32 rank,
+ u32 mr_num, u32 *buf)
+{
+ s32 timeout = 100;
+
+ writel(((1 << 16) | (((rank == 2) ? 1 : 0) << 8) | mr_num) << 8,
+ &ddr_pctl_regs->denali_ctl[118]);
+
+ while (0 == (readl(&ddr_pctl_regs->denali_ctl[203]) &
+ ((1 << 21) | (1 << 12)))) {
+ udelay(1);
+
+ if (timeout <= 0) {
+ printf("%s: pctl timeout!\n", __func__);
+ return -ETIMEDOUT;
+ }
+
+ timeout--;
+ }
+
+ if (!(readl(&ddr_pctl_regs->denali_ctl[203]) & (1 << 12))) {
+ *buf = readl(&ddr_pctl_regs->denali_ctl[119]) & 0xFF;
+ } else {
+ printf("%s: read mr failed with 0x%x status\n", __func__,
+ readl(&ddr_pctl_regs->denali_ctl[17]) & 0x3);
+ *buf = 0;
+ }
+
+ setbits_le32(&ddr_pctl_regs->denali_ctl[205], (1 << 21) | (1 << 12));
+
+ return 0;
+}
+
+static int lpddr4_mr_detect(struct dram_info *dram, u32 channel, u32 rank,
+ struct rk3399_sdram_params *sdram_params)
+{
+ u64 cs0_cap;
+ u32 stride;
+ u32 cs = 0, col = 0, bk = 0, bw = 0, row_3_4 = 0;
+ u32 cs0_row = 0, cs1_row = 0, ddrconfig = 0;
+ u32 mr5, mr12, mr14;
+ struct chan_info *chan = &dram->chan[channel];
+ struct rk3399_ddr_pctl_regs *ddr_pctl_regs = chan->pctl;
+ void __iomem *addr = NULL;
+ int ret = 0;
+ u32 val;
+
+ stride = get_ddr_stride(dram->pmusgrf);
+
+ if (sdram_params->ch[channel].cap_info.col == 0) {
+ ret = -EPERM;
+ goto end;
+ }
+
+ cs = sdram_params->ch[channel].cap_info.rank;
+ col = sdram_params->ch[channel].cap_info.col;
+ bk = sdram_params->ch[channel].cap_info.bk;
+ bw = sdram_params->ch[channel].cap_info.bw;
+ row_3_4 = sdram_params->ch[channel].cap_info.row_3_4;
+ cs0_row = sdram_params->ch[channel].cap_info.cs0_row;
+ cs1_row = sdram_params->ch[channel].cap_info.cs1_row;
+ ddrconfig = sdram_params->ch[channel].cap_info.ddrconfig;
+
+ /* 2GB */
+ sdram_params->ch[channel].cap_info.rank = 2;
+ sdram_params->ch[channel].cap_info.col = 10;
+ sdram_params->ch[channel].cap_info.bk = 3;
+ sdram_params->ch[channel].cap_info.bw = 2;
+ sdram_params->ch[channel].cap_info.row_3_4 = 0;
+ sdram_params->ch[channel].cap_info.cs0_row = 15;
+ sdram_params->ch[channel].cap_info.cs1_row = 15;
+ sdram_params->ch[channel].cap_info.ddrconfig = 1;
+
+ set_memory_map(chan, channel, sdram_params);
+ sdram_params->ch[channel].cap_info.ddrconfig =
+ calculate_ddrconfig(sdram_params, channel);
+ set_ddrconfig(chan, sdram_params, channel,
+ sdram_params->ch[channel].cap_info.ddrconfig);
+ set_cap_relate_config(chan, sdram_params, channel);
+
+ cs0_cap = (1 << (sdram_params->ch[channel].cap_info.bw
+ + sdram_params->ch[channel].cap_info.col
+ + sdram_params->ch[channel].cap_info.bk
+ + sdram_params->ch[channel].cap_info.cs0_row));
+
+ if (sdram_params->ch[channel].cap_info.row_3_4)
+ cs0_cap = cs0_cap * 3 / 4;
+
+ if (channel == 0)
+ set_ddr_stride(dram->pmusgrf, 0x17);
+ else
+ set_ddr_stride(dram->pmusgrf, 0x18);
+
+ /* read and write data to DRAM, avoid be optimized by compiler. */
+ if (rank == 1)
+ addr = (void __iomem *)0x100;
+ else if (rank == 2)
+ addr = (void __iomem *)(cs0_cap + 0x100);
+
+ val = readl(addr);
+ writel(val + 1, addr);
+
+ read_mr(ddr_pctl_regs, rank, 5, &mr5);
+ read_mr(ddr_pctl_regs, rank, 12, &mr12);
+ read_mr(ddr_pctl_regs, rank, 14, &mr14);
+
+ if (mr5 == 0 || mr12 != 0x4d || mr14 != 0x4d) {
+ ret = -EINVAL;
+ goto end;
+ }
+end:
+ sdram_params->ch[channel].cap_info.rank = cs;
+ sdram_params->ch[channel].cap_info.col = col;
+ sdram_params->ch[channel].cap_info.bk = bk;
+ sdram_params->ch[channel].cap_info.bw = bw;
+ sdram_params->ch[channel].cap_info.row_3_4 = row_3_4;
+ sdram_params->ch[channel].cap_info.cs0_row = cs0_row;
+ sdram_params->ch[channel].cap_info.cs1_row = cs1_row;
+ sdram_params->ch[channel].cap_info.ddrconfig = ddrconfig;
+
+ set_ddr_stride(dram->pmusgrf, stride);
+
+ return ret;
+}
+
static void clear_channel_params(struct rk3399_sdram_params *params, u8 channel)
{
params->ch[channel].cap_info.rank = 0;
@@ -1665,17 +1884,30 @@ static int sdram_init(struct dram_info *dram,
sdram_params->ch[ch].cap_info.rank = rank;
- /*
- * LPDDR3 CA training msut be trigger before
- * other training.
- * DDR3 is not have CA training.
- */
- if (sdram_params->base.dramtype == LPDDR3)
- training_flag |= PI_CA_TRAINING;
-
- if (!(data_training(&dram->chan[ch], ch,
- sdram_params, training_flag)))
- break;
+ if (sdram_params->base.dramtype == LPDDR4) {
+ if (!lpddr4_mr_detect(dram, ch, rank,
+ sdram_params)) {
+ debug("%s: lpddr4 mr detected for rank %d, ch %d\n",
+ __func__, rank, ch);
+ break;
+ }
+ } else {
+ /*
+ * LPDDR3 CA training msut be trigger before
+ * other training.
+ * DDR3 is not have CA training.
+ */
+ if (sdram_params->base.dramtype == LPDDR3)
+ training_flag |= PI_CA_TRAINING;
+
+ if (!(data_training(&dram->chan[ch], ch,
+ sdram_params,
+ training_flag))) {
+ debug("%s: data trained for rank %d, ch %d\n",
+ __func__, rank, ch);
+ break;
+ }
+ }
}
/* Computed rank with associated channel number */
sdram_params->ch[ch].cap_info.rank = rank;
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 79/92] arm: include: rockchip: Add rk3399 pmu file
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:51 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Add pmu header file for rk3399 SoC, this will help
to configure pmu in sdram driver.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
.../include/asm/arch-rockchip/pmu_rk3399.h | 72 +++++++++++++++++++
1 file changed, 72 insertions(+)
create mode 100644 arch/arm/include/asm/arch-rockchip/pmu_rk3399.h
diff --git a/arch/arm/include/asm/arch-rockchip/pmu_rk3399.h b/arch/arm/include/asm/arch-rockchip/pmu_rk3399.h
new file mode 100644
index 0000000000..f1096dccce
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/pmu_rk3399.h
@@ -0,0 +1,72 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2018 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+#ifndef __SOC_ROCKCHIP_RK3399_PMU_H__
+#define __SOC_ROCKCHIP_RK3399_PMU_H__
+
+struct rk3399_pmu_regs {
+ u32 pmu_wakeup_cfg[5];
+ u32 pmu_pwrdn_con;
+ u32 pmu_pwrdn_st;
+ u32 pmu_pll_con;
+ u32 pmu_pwrmode_con;
+ u32 pmu_sft_con;
+ u32 pmu_int_con;
+ u32 pmu_int_st;
+ u32 pmu_gpio0_pos_int_con;
+ u32 pmu_gpio0_net_int_con;
+ u32 pmu_gpio1_pos_int_con;
+ u32 pmu_gpio1_net_int_con;
+ u32 pmu_gpio0_pos_int_st;
+ u32 pmu_gpio0_net_int_st;
+ u32 pmu_gpio1_pos_int_st;
+ u32 pmu_gpio1_net_int_st;
+ u32 pmu_pwrdn_inten;
+ u32 pmu_pwrdn_status;
+ u32 pmu_wakeup_status;
+ u32 pmu_bus_clr;
+ u32 pmu_bus_idle_req;
+ u32 pmu_bus_idle_st;
+ u32 pmu_bus_idle_ack;
+ u32 pmu_cci500_con;
+ u32 pmu_adb400_con;
+ u32 pmu_adb400_st;
+ u32 pmu_power_st;
+ u32 pmu_core_pwr_st;
+ u32 pmu_osc_cnt;
+ u32 pmu_plllock_cnt;
+ u32 pmu_pllrst_cnt;
+ u32 pmu_stable_cnt;
+ u32 pmu_ddrio_pwron_cnt;
+ u32 pmu_wakeup_rst_clr_cnt;
+ u32 pmu_ddr_sref_st;
+ u32 pmu_scu_l_pwrdn_cnt;
+ u32 pmu_scu_l_pwrup_cnt;
+ u32 pmu_scu_b_pwrdn_cnt;
+ u32 pmu_scu_b_pwrup_cnt;
+ u32 pmu_gpu_pwrdn_cnt;
+ u32 pmu_gpu_pwrup_cnt;
+ u32 pmu_center_pwrdn_cnt;
+ u32 pmu_center_pwrup_cnt;
+ u32 pmu_timeout_cnt;
+ u32 pmu_cpu0apm_con;
+ u32 pmu_cpu1apm_con;
+ u32 pmu_cpu2apm_con;
+ u32 pmu_cpu3apm_con;
+ u32 pmu_cpu0bpm_con;
+ u32 pmu_cpu1bpm_con;
+ u32 pmu_noc_auto_ena;
+ u32 pmu_pwrdn_con1;
+ u32 reserved0[0x4];
+ u32 pmu_sys_reg_reg0;
+ u32 pmu_sys_reg_reg1;
+ u32 pmu_sys_reg_reg2;
+ u32 pmu_sys_reg_reg3;
+};
+
+check_member(rk3399_pmu_regs, pmu_sys_reg_reg3, 0xfc);
+
+#endif /* __SOC_ROCKCHIP_RK3399_PMU_H__ */
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 79/92] arm: include: rockchip: Add rk3399 pmu file
@ 2019-06-11 14:51 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: u-boot
Add pmu header file for rk3399 SoC, this will help
to configure pmu in sdram driver.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
.../include/asm/arch-rockchip/pmu_rk3399.h | 72 +++++++++++++++++++
1 file changed, 72 insertions(+)
create mode 100644 arch/arm/include/asm/arch-rockchip/pmu_rk3399.h
diff --git a/arch/arm/include/asm/arch-rockchip/pmu_rk3399.h b/arch/arm/include/asm/arch-rockchip/pmu_rk3399.h
new file mode 100644
index 0000000000..f1096dccce
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/pmu_rk3399.h
@@ -0,0 +1,72 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2018 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+#ifndef __SOC_ROCKCHIP_RK3399_PMU_H__
+#define __SOC_ROCKCHIP_RK3399_PMU_H__
+
+struct rk3399_pmu_regs {
+ u32 pmu_wakeup_cfg[5];
+ u32 pmu_pwrdn_con;
+ u32 pmu_pwrdn_st;
+ u32 pmu_pll_con;
+ u32 pmu_pwrmode_con;
+ u32 pmu_sft_con;
+ u32 pmu_int_con;
+ u32 pmu_int_st;
+ u32 pmu_gpio0_pos_int_con;
+ u32 pmu_gpio0_net_int_con;
+ u32 pmu_gpio1_pos_int_con;
+ u32 pmu_gpio1_net_int_con;
+ u32 pmu_gpio0_pos_int_st;
+ u32 pmu_gpio0_net_int_st;
+ u32 pmu_gpio1_pos_int_st;
+ u32 pmu_gpio1_net_int_st;
+ u32 pmu_pwrdn_inten;
+ u32 pmu_pwrdn_status;
+ u32 pmu_wakeup_status;
+ u32 pmu_bus_clr;
+ u32 pmu_bus_idle_req;
+ u32 pmu_bus_idle_st;
+ u32 pmu_bus_idle_ack;
+ u32 pmu_cci500_con;
+ u32 pmu_adb400_con;
+ u32 pmu_adb400_st;
+ u32 pmu_power_st;
+ u32 pmu_core_pwr_st;
+ u32 pmu_osc_cnt;
+ u32 pmu_plllock_cnt;
+ u32 pmu_pllrst_cnt;
+ u32 pmu_stable_cnt;
+ u32 pmu_ddrio_pwron_cnt;
+ u32 pmu_wakeup_rst_clr_cnt;
+ u32 pmu_ddr_sref_st;
+ u32 pmu_scu_l_pwrdn_cnt;
+ u32 pmu_scu_l_pwrup_cnt;
+ u32 pmu_scu_b_pwrdn_cnt;
+ u32 pmu_scu_b_pwrup_cnt;
+ u32 pmu_gpu_pwrdn_cnt;
+ u32 pmu_gpu_pwrup_cnt;
+ u32 pmu_center_pwrdn_cnt;
+ u32 pmu_center_pwrup_cnt;
+ u32 pmu_timeout_cnt;
+ u32 pmu_cpu0apm_con;
+ u32 pmu_cpu1apm_con;
+ u32 pmu_cpu2apm_con;
+ u32 pmu_cpu3apm_con;
+ u32 pmu_cpu0bpm_con;
+ u32 pmu_cpu1bpm_con;
+ u32 pmu_noc_auto_ena;
+ u32 pmu_pwrdn_con1;
+ u32 reserved0[0x4];
+ u32 pmu_sys_reg_reg0;
+ u32 pmu_sys_reg_reg1;
+ u32 pmu_sys_reg_reg2;
+ u32 pmu_sys_reg_reg3;
+};
+
+check_member(rk3399_pmu_regs, pmu_sys_reg_reg3, 0xfc);
+
+#endif /* __SOC_ROCKCHIP_RK3399_PMU_H__ */
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 80/92] rockchip: rk3399: syscon: Add pmu support
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:51 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Add pmu compatible with relevant U_BOOT_DRIVER for rk3399
via syscon rk3399 driver.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
arch/arm/mach-rockchip/rk3399/syscon_rk3399.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c b/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c
index a8bb5b11e5..259ca44d68 100644
--- a/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c
+++ b/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c
@@ -13,6 +13,7 @@ static const struct udevice_id rk3399_syscon_ids[] = {
{ .compatible = "rockchip,rk3399-pmugrf", .data = ROCKCHIP_SYSCON_PMUGRF },
{ .compatible = "rockchip,rk3399-pmusgrf", .data = ROCKCHIP_SYSCON_PMUSGRF },
{ .compatible = "rockchip,rk3399-cic", .data = ROCKCHIP_SYSCON_CIC },
+ { .compatible = "rockchip,rk3399-pmu", .data = ROCKCHIP_SYSCON_PMU },
{ }
};
@@ -58,4 +59,11 @@ U_BOOT_DRIVER(rockchip_rk3399_cic) = {
.of_match = rk3399_syscon_ids + 3,
.bind = rk3399_syscon_bind_of_platdata,
};
+
+U_BOOT_DRIVER(rockchip_rk3399_pmu) = {
+ .name = "rockchip_rk3399_pmu",
+ .id = UCLASS_SYSCON,
+ .of_match = rk3399_syscon_ids + 4,
+ .bind = rk3399_syscon_bind_of_platdata,
+};
#endif
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 80/92] rockchip: rk3399: syscon: Add pmu support
@ 2019-06-11 14:51 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: u-boot
Add pmu compatible with relevant U_BOOT_DRIVER for rk3399
via syscon rk3399 driver.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
arch/arm/mach-rockchip/rk3399/syscon_rk3399.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c b/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c
index a8bb5b11e5..259ca44d68 100644
--- a/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c
+++ b/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c
@@ -13,6 +13,7 @@ static const struct udevice_id rk3399_syscon_ids[] = {
{ .compatible = "rockchip,rk3399-pmugrf", .data = ROCKCHIP_SYSCON_PMUGRF },
{ .compatible = "rockchip,rk3399-pmusgrf", .data = ROCKCHIP_SYSCON_PMUSGRF },
{ .compatible = "rockchip,rk3399-cic", .data = ROCKCHIP_SYSCON_CIC },
+ { .compatible = "rockchip,rk3399-pmu", .data = ROCKCHIP_SYSCON_PMU },
{ }
};
@@ -58,4 +59,11 @@ U_BOOT_DRIVER(rockchip_rk3399_cic) = {
.of_match = rk3399_syscon_ids + 3,
.bind = rk3399_syscon_bind_of_platdata,
};
+
+U_BOOT_DRIVER(rockchip_rk3399_pmu) = {
+ .name = "rockchip_rk3399_pmu",
+ .id = UCLASS_SYSCON,
+ .of_match = rk3399_syscon_ids + 4,
+ .bind = rk3399_syscon_bind_of_platdata,
+};
#endif
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 81/92] rockchip: dts: rk3399: Add u-boot,dm-pre-reloc for pmu
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:51 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Add u-boot,dm-pre-reloc property for pmu in rk3399-u-boot.dtsi
so-that SPL can access pmu.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
arch/arm/dts/rk3399-u-boot.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi
index 0786c1193a..31942899f6 100644
--- a/arch/arm/dts/rk3399-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-u-boot.dtsi
@@ -3,6 +3,10 @@
* Copyright (C) 2019 Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
*/
+&pmu {
+ u-boot,dm-pre-reloc;
+};
+
&sdmmc {
u-boot,dm-pre-reloc;
};
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 81/92] rockchip: dts: rk3399: Add u-boot, dm-pre-reloc for pmu
@ 2019-06-11 14:51 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: u-boot
Add u-boot,dm-pre-reloc property for pmu in rk3399-u-boot.dtsi
so-that SPL can access pmu.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
arch/arm/dts/rk3399-u-boot.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi
index 0786c1193a..31942899f6 100644
--- a/arch/arm/dts/rk3399-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-u-boot.dtsi
@@ -3,6 +3,10 @@
* Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
*/
+&pmu {
+ u-boot,dm-pre-reloc;
+};
+
&sdmmc {
u-boot,dm-pre-reloc;
};
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 82/92] ram: rk3399: Add LPPDDR4-400 timings inc
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:51 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
LPDDR4 initialization start with at board selected frequency
and then it switches into 400MHz and 800MHz simultaneously to
make the proper sequence work on each channel with associated
training.
So, add LPDDR4-400 timings inc file in driver area so-that
these timings will take during LPDDR4 initialization phase.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
.../ram/rockchip/sdram-rk3399-lpddr4-400.inc | 1570 +++++++++++++++++
1 file changed, 1570 insertions(+)
create mode 100644 drivers/ram/rockchip/sdram-rk3399-lpddr4-400.inc
diff --git a/drivers/ram/rockchip/sdram-rk3399-lpddr4-400.inc b/drivers/ram/rockchip/sdram-rk3399-lpddr4-400.inc
new file mode 100644
index 0000000000..c50a03d9dd
--- /dev/null
+++ b/drivers/ram/rockchip/sdram-rk3399-lpddr4-400.inc
@@ -0,0 +1,1570 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd.
+ * (C) Copyright 2019 Amarula Solutions
+ */
+
+{
+ {
+ {
+ {
+ .rank = 0x2,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF,
+ .ddrconfig = 1,
+ },
+ {
+ .ddrtiminga0 = 0x80241d22,
+ .ddrtimingb0 = 0x15050f08,
+ .ddrtimingc0 = {
+ 0x00000602,
+ },
+ .devtodev0 = 0x00002122,
+ .ddrmode = {
+ 0x0000004c,
+ },
+ .agingx0 = 0x00000000,
+ }
+ },
+ {
+ {
+ .rank = 0x2,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF,
+ .ddrconfig = 1,
+ },
+ {
+ .ddrtiminga0 = 0x80241d22,
+ .ddrtimingb0 = 0x15050f08,
+ .ddrtimingc0 = {
+ 0x00000602,
+ },
+ .devtodev0 = 0x00002122,
+ .ddrmode = {
+ 0x0000004c,
+ },
+ .agingx0 = 0x00000000,
+ }
+ }
+ },
+ {
+ .ddr_freq = 400 * MHz,
+ .dramtype = LPDDR4,
+ .num_channels = 2,
+ .stride = 13,
+ .odt = 1,
+ },
+ {
+ {
+ 0x00000b00, /* DENALI_CTL_00_DATA */
+ 0x00000000, /* DENALI_CTL_01_DATA */
+ 0x00000000, /* DENALI_CTL_02_DATA */
+ 0x00000000, /* DENALI_CTL_03_DATA */
+ 0x00000000, /* DENALI_CTL_04_DATA */
+ 0x00013880, /* DENALI_CTL_05_DATA */
+ 0x000c3500, /* DENALI_CTL_06_DATA */
+ 0x00000005, /* DENALI_CTL_07_DATA */
+ 0x00000320, /* DENALI_CTL_08_DATA */
+ 0x00027100, /* DENALI_CTL_09_DATA */
+ 0x00186a00, /* DENALI_CTL_10_DATA */
+ 0x00000005, /* DENALI_CTL_11_DATA */
+ 0x00000640, /* DENALI_CTL_12_DATA */
+ 0x00002710, /* DENALI_CTL_13_DATA */
+ 0x000186a0, /* DENALI_CTL_14_DATA */
+ 0x00000005, /* DENALI_CTL_15_DATA */
+ 0x01000064, /* DENALI_CTL_16_DATA */
+ 0x00000000, /* DENALI_CTL_17_DATA */
+ 0x02020101, /* DENALI_CTL_18_DATA */
+ 0x00000102, /* DENALI_CTL_19_DATA */
+ 0x00000050, /* DENALI_CTL_20_DATA */
+ 0x000000c8, /* DENALI_CTL_21_DATA */
+ 0x00000000, /* DENALI_CTL_22_DATA */
+ 0x06140000, /* DENALI_CTL_23_DATA */
+ 0x00081c00, /* DENALI_CTL_24_DATA */
+ 0x0400040c, /* DENALI_CTL_25_DATA */
+ 0x19042008, /* DENALI_CTL_26_DATA */
+ 0x10080a11, /* DENALI_CTL_27_DATA */
+ 0x22310800, /* DENALI_CTL_28_DATA */
+ 0x00200f0a, /* DENALI_CTL_29_DATA */
+ 0x0a030704, /* DENALI_CTL_30_DATA */
+ 0x08000204, /* DENALI_CTL_31_DATA */
+ 0x00000a0a, /* DENALI_CTL_32_DATA */
+ 0x04006db0, /* DENALI_CTL_33_DATA */
+ 0x0a0a0804, /* DENALI_CTL_34_DATA */
+ 0x0600db60, /* DENALI_CTL_35_DATA */
+ 0x0a0a0806, /* DENALI_CTL_36_DATA */
+ 0x04000db6, /* DENALI_CTL_37_DATA */
+ 0x02030404, /* DENALI_CTL_38_DATA */
+ 0x0f0a0800, /* DENALI_CTL_39_DATA */
+ 0x08040411, /* DENALI_CTL_40_DATA */
+ 0x1400640a, /* DENALI_CTL_41_DATA */
+ 0x02010a0a, /* DENALI_CTL_42_DATA */
+ 0x00010001, /* DENALI_CTL_43_DATA */
+ 0x04082012, /* DENALI_CTL_44_DATA */
+ 0x00041109, /* DENALI_CTL_45_DATA */
+ 0x00000000, /* DENALI_CTL_46_DATA */
+ 0x03010000, /* DENALI_CTL_47_DATA */
+ 0x06100034, /* DENALI_CTL_48_DATA */
+ 0x0c280068, /* DENALI_CTL_49_DATA */
+ 0x00bb0007, /* DENALI_CTL_50_DATA */
+ 0x00000000, /* DENALI_CTL_51_DATA */
+ 0x00060003, /* DENALI_CTL_52_DATA */
+ 0x000a0003, /* DENALI_CTL_53_DATA */
+ 0x000a0014, /* DENALI_CTL_54_DATA */
+ 0x01000000, /* DENALI_CTL_55_DATA */
+ 0x030a0000, /* DENALI_CTL_56_DATA */
+ 0x0c000002, /* DENALI_CTL_57_DATA */
+ 0x00000103, /* DENALI_CTL_58_DATA */
+ 0x0003030a, /* DENALI_CTL_59_DATA */
+ 0x00060037, /* DENALI_CTL_60_DATA */
+ 0x0003006e, /* DENALI_CTL_61_DATA */
+ 0x05050007, /* DENALI_CTL_62_DATA */
+ 0x03020605, /* DENALI_CTL_63_DATA */
+ 0x06050301, /* DENALI_CTL_64_DATA */
+ 0x06020c05, /* DENALI_CTL_65_DATA */
+ 0x05050302, /* DENALI_CTL_66_DATA */
+ 0x03020305, /* DENALI_CTL_67_DATA */
+ 0x00000301, /* DENALI_CTL_68_DATA */
+ 0x00000301, /* DENALI_CTL_69_DATA */
+ 0x00000001, /* DENALI_CTL_70_DATA */
+ 0x00000000, /* DENALI_CTL_71_DATA */
+ 0x00000000, /* DENALI_CTL_72_DATA */
+ 0x01000000, /* DENALI_CTL_73_DATA */
+ 0x80104002, /* DENALI_CTL_74_DATA */
+ 0x00040003, /* DENALI_CTL_75_DATA */
+ 0x00040005, /* DENALI_CTL_76_DATA */
+ 0x00030000, /* DENALI_CTL_77_DATA */
+ 0x00050004, /* DENALI_CTL_78_DATA */
+ 0x00000004, /* DENALI_CTL_79_DATA */
+ 0x00040003, /* DENALI_CTL_80_DATA */
+ 0x00040005, /* DENALI_CTL_81_DATA */
+ 0x18400000, /* DENALI_CTL_82_DATA */
+ 0x00000c20, /* DENALI_CTL_83_DATA */
+ 0x185030a0, /* DENALI_CTL_84_DATA */
+ 0x02ec0000, /* DENALI_CTL_85_DATA */
+ 0x00000176, /* DENALI_CTL_86_DATA */
+ 0x00000000, /* DENALI_CTL_87_DATA */
+ 0x00000000, /* DENALI_CTL_88_DATA */
+ 0x00000000, /* DENALI_CTL_89_DATA */
+ 0x00000000, /* DENALI_CTL_90_DATA */
+ 0x00000000, /* DENALI_CTL_91_DATA */
+ 0x06030300, /* DENALI_CTL_92_DATA */
+ 0x00030303, /* DENALI_CTL_93_DATA */
+ 0x02030200, /* DENALI_CTL_94_DATA */
+ 0x00040703, /* DENALI_CTL_95_DATA */
+ 0x03020302, /* DENALI_CTL_96_DATA */
+ 0x02000407, /* DENALI_CTL_97_DATA */
+ 0x07030203, /* DENALI_CTL_98_DATA */
+ 0x00030f04, /* DENALI_CTL_99_DATA */
+ 0x00070004, /* DENALI_CTL_100_DATA */
+ 0x00000000, /* DENALI_CTL_101_DATA */
+ 0x00000000, /* DENALI_CTL_102_DATA */
+ 0x00000000, /* DENALI_CTL_103_DATA */
+ 0x00000000, /* DENALI_CTL_104_DATA */
+ 0x00000000, /* DENALI_CTL_105_DATA */
+ 0x00000000, /* DENALI_CTL_106_DATA */
+ 0x00000000, /* DENALI_CTL_107_DATA */
+ 0x00010000, /* DENALI_CTL_108_DATA */
+ 0x20040020, /* DENALI_CTL_109_DATA */
+ 0x00200400, /* DENALI_CTL_110_DATA */
+ 0x01000400, /* DENALI_CTL_111_DATA */
+ 0x00000b80, /* DENALI_CTL_112_DATA */
+ 0x00000000, /* DENALI_CTL_113_DATA */
+ 0x00000001, /* DENALI_CTL_114_DATA */
+ 0x00000002, /* DENALI_CTL_115_DATA */
+ 0x0000000e, /* DENALI_CTL_116_DATA */
+ 0x00000000, /* DENALI_CTL_117_DATA */
+ 0x00000000, /* DENALI_CTL_118_DATA */
+ 0x00000000, /* DENALI_CTL_119_DATA */
+ 0x00000000, /* DENALI_CTL_120_DATA */
+ 0x00000000, /* DENALI_CTL_121_DATA */
+ 0x00500000, /* DENALI_CTL_122_DATA */
+ 0x00640028, /* DENALI_CTL_123_DATA */
+ 0x00640404, /* DENALI_CTL_124_DATA */
+ 0x005000a0, /* DENALI_CTL_125_DATA */
+ 0x060600c8, /* DENALI_CTL_126_DATA */
+ 0x000a00c8, /* DENALI_CTL_127_DATA */
+ 0x000d0005, /* DENALI_CTL_128_DATA */
+ 0x000d0404, /* DENALI_CTL_129_DATA */
+ 0x00000000, /* DENALI_CTL_130_DATA */
+ 0x00000000, /* DENALI_CTL_131_DATA */
+ 0x00000000, /* DENALI_CTL_132_DATA */
+ 0x001400a3, /* DENALI_CTL_133_DATA */
+ 0x00e30009, /* DENALI_CTL_134_DATA */
+ 0x00120024, /* DENALI_CTL_135_DATA */
+ 0x00040063, /* DENALI_CTL_136_DATA */
+ 0x00000000, /* DENALI_CTL_137_DATA */
+ 0x00310031, /* DENALI_CTL_138_DATA */
+ 0x00000031, /* DENALI_CTL_139_DATA */
+ 0x004d0000, /* DENALI_CTL_140_DATA */
+ 0x004d004d, /* DENALI_CTL_141_DATA */
+ 0x004d0000, /* DENALI_CTL_142_DATA */
+ 0x004d004d, /* DENALI_CTL_143_DATA */
+ 0x00010101, /* DENALI_CTL_144_DATA */
+ 0x00000000, /* DENALI_CTL_145_DATA */
+ 0x00000000, /* DENALI_CTL_146_DATA */
+ 0x001400a3, /* DENALI_CTL_147_DATA */
+ 0x00e30009, /* DENALI_CTL_148_DATA */
+ 0x00120024, /* DENALI_CTL_149_DATA */
+ 0x00040063, /* DENALI_CTL_150_DATA */
+ 0x00000000, /* DENALI_CTL_151_DATA */
+ 0x00310031, /* DENALI_CTL_152_DATA */
+ 0x00000031, /* DENALI_CTL_153_DATA */
+ 0x004d0000, /* DENALI_CTL_154_DATA */
+ 0x004d004d, /* DENALI_CTL_155_DATA */
+ 0x004d0000, /* DENALI_CTL_156_DATA */
+ 0x004d004d, /* DENALI_CTL_157_DATA */
+ 0x00010101, /* DENALI_CTL_158_DATA */
+ 0x00000000, /* DENALI_CTL_159_DATA */
+ 0x00000000, /* DENALI_CTL_160_DATA */
+ 0x00000000, /* DENALI_CTL_161_DATA */
+ 0x00000001, /* DENALI_CTL_162_DATA */
+ 0x00000000, /* DENALI_CTL_163_DATA */
+ 0x18151100, /* DENALI_CTL_164_DATA */
+ 0x0000000c, /* DENALI_CTL_165_DATA */
+ 0x00000000, /* DENALI_CTL_166_DATA */
+ 0x00000000, /* DENALI_CTL_167_DATA */
+ 0x00000000, /* DENALI_CTL_168_DATA */
+ 0x00000000, /* DENALI_CTL_169_DATA */
+ 0x00000000, /* DENALI_CTL_170_DATA */
+ 0x00000000, /* DENALI_CTL_171_DATA */
+ 0x00000000, /* DENALI_CTL_172_DATA */
+ 0x00000000, /* DENALI_CTL_173_DATA */
+ 0x00000000, /* DENALI_CTL_174_DATA */
+ 0x00000000, /* DENALI_CTL_175_DATA */
+ 0x00000000, /* DENALI_CTL_176_DATA */
+ 0x00000000, /* DENALI_CTL_177_DATA */
+ 0x00000000, /* DENALI_CTL_178_DATA */
+ 0x00020003, /* DENALI_CTL_179_DATA */
+ 0x00400100, /* DENALI_CTL_180_DATA */
+ 0x000c0190, /* DENALI_CTL_181_DATA */
+ 0x01000200, /* DENALI_CTL_182_DATA */
+ 0x03200040, /* DENALI_CTL_183_DATA */
+ 0x00020018, /* DENALI_CTL_184_DATA */
+ 0x00400100, /* DENALI_CTL_185_DATA */
+ 0x00080032, /* DENALI_CTL_186_DATA */
+ 0x00140000, /* DENALI_CTL_187_DATA */
+ 0x00030028, /* DENALI_CTL_188_DATA */
+ 0x01010100, /* DENALI_CTL_189_DATA */
+ 0x02000202, /* DENALI_CTL_190_DATA */
+ 0x0b000002, /* DENALI_CTL_191_DATA */
+ 0x01000f0f, /* DENALI_CTL_192_DATA */
+ 0x00000000, /* DENALI_CTL_193_DATA */
+ 0x00000000, /* DENALI_CTL_194_DATA */
+ 0x00010003, /* DENALI_CTL_195_DATA */
+ 0x00000c03, /* DENALI_CTL_196_DATA */
+ 0x00040101, /* DENALI_CTL_197_DATA */
+ 0x04010100, /* DENALI_CTL_198_DATA */
+ 0x01000000, /* DENALI_CTL_199_DATA */
+ 0x02010000, /* DENALI_CTL_200_DATA */
+ 0x00000001, /* DENALI_CTL_201_DATA */
+ 0x00000000, /* DENALI_CTL_202_DATA */
+ 0x00000000, /* DENALI_CTL_203_DATA */
+ 0x00000000, /* DENALI_CTL_204_DATA */
+ 0x00000000, /* DENALI_CTL_205_DATA */
+ 0x00000000, /* DENALI_CTL_206_DATA */
+ 0x00000000, /* DENALI_CTL_207_DATA */
+ 0x00000000, /* DENALI_CTL_208_DATA */
+ 0x00000000, /* DENALI_CTL_209_DATA */
+ 0x00000000, /* DENALI_CTL_210_DATA */
+ 0x00010000, /* DENALI_CTL_211_DATA */
+ 0x00000001, /* DENALI_CTL_212_DATA */
+ 0x01010001, /* DENALI_CTL_213_DATA */
+ 0x05040001, /* DENALI_CTL_214_DATA */
+ 0x040a0703, /* DENALI_CTL_215_DATA */
+ 0x02080808, /* DENALI_CTL_216_DATA */
+ 0x020e000a, /* DENALI_CTL_217_DATA */
+ 0x020f010b, /* DENALI_CTL_218_DATA */
+ 0x000d0008, /* DENALI_CTL_219_DATA */
+ 0x00080b0a, /* DENALI_CTL_220_DATA */
+ 0x03000200, /* DENALI_CTL_221_DATA */
+ 0x00000100, /* DENALI_CTL_222_DATA */
+ 0x00000000, /* DENALI_CTL_223_DATA */
+ 0x00000000, /* DENALI_CTL_224_DATA */
+ 0x0d000001, /* DENALI_CTL_225_DATA */
+ 0x00000028, /* DENALI_CTL_226_DATA */
+ 0x00010000, /* DENALI_CTL_227_DATA */
+ 0x00000003, /* DENALI_CTL_228_DATA */
+ 0x00000000, /* DENALI_CTL_229_DATA */
+ 0x00000000, /* DENALI_CTL_230_DATA */
+ 0x00000000, /* DENALI_CTL_231_DATA */
+ 0x00000000, /* DENALI_CTL_232_DATA */
+ 0x00000000, /* DENALI_CTL_233_DATA */
+ 0x00000000, /* DENALI_CTL_234_DATA */
+ 0x00000000, /* DENALI_CTL_235_DATA */
+ 0x00000000, /* DENALI_CTL_236_DATA */
+ 0x00010100, /* DENALI_CTL_237_DATA */
+ 0x01000000, /* DENALI_CTL_238_DATA */
+ 0x00000001, /* DENALI_CTL_239_DATA */
+ 0x00000303, /* DENALI_CTL_240_DATA */
+ 0x00000000, /* DENALI_CTL_241_DATA */
+ 0x00000000, /* DENALI_CTL_242_DATA */
+ 0x00000000, /* DENALI_CTL_243_DATA */
+ 0x00000000, /* DENALI_CTL_244_DATA */
+ 0x00000000, /* DENALI_CTL_245_DATA */
+ 0x00000000, /* DENALI_CTL_246_DATA */
+ 0x00000000, /* DENALI_CTL_247_DATA */
+ 0x00000000, /* DENALI_CTL_248_DATA */
+ 0x00000000, /* DENALI_CTL_249_DATA */
+ 0x00000000, /* DENALI_CTL_250_DATA */
+ 0x00000000, /* DENALI_CTL_251_DATA */
+ 0x00000000, /* DENALI_CTL_252_DATA */
+ 0x00000000, /* DENALI_CTL_253_DATA */
+ 0x00000000, /* DENALI_CTL_254_DATA */
+ 0x00000000, /* DENALI_CTL_255_DATA */
+ 0x000556aa, /* DENALI_CTL_256_DATA */
+ 0x000aaaaa, /* DENALI_CTL_257_DATA */
+ 0x000aa955, /* DENALI_CTL_258_DATA */
+ 0x00055555, /* DENALI_CTL_259_DATA */
+ 0x000b3133, /* DENALI_CTL_260_DATA */
+ 0x0004cd33, /* DENALI_CTL_261_DATA */
+ 0x0004cecc, /* DENALI_CTL_262_DATA */
+ 0x000b32cc, /* DENALI_CTL_263_DATA */
+ 0x00010300, /* DENALI_CTL_264_DATA */
+ 0x03000100, /* DENALI_CTL_265_DATA */
+ 0x00000000, /* DENALI_CTL_266_DATA */
+ 0x00000000, /* DENALI_CTL_267_DATA */
+ 0x00000000, /* DENALI_CTL_268_DATA */
+ 0x00000000, /* DENALI_CTL_269_DATA */
+ 0x00000000, /* DENALI_CTL_270_DATA */
+ 0x00000000, /* DENALI_CTL_271_DATA */
+ 0x00000000, /* DENALI_CTL_272_DATA */
+ 0x00000000, /* DENALI_CTL_273_DATA */
+ 0x00ffff00, /* DENALI_CTL_274_DATA */
+ 0x1a160000, /* DENALI_CTL_275_DATA */
+ 0x08000012, /* DENALI_CTL_276_DATA */
+ 0x00000c20, /* DENALI_CTL_277_DATA */
+ 0x00000200, /* DENALI_CTL_278_DATA */
+ 0x00000200, /* DENALI_CTL_279_DATA */
+ 0x00000200, /* DENALI_CTL_280_DATA */
+ 0x00000200, /* DENALI_CTL_281_DATA */
+ 0x00000c20, /* DENALI_CTL_282_DATA */
+ 0x00007940, /* DENALI_CTL_283_DATA */
+ 0x18500409, /* DENALI_CTL_284_DATA */
+ 0x00000200, /* DENALI_CTL_285_DATA */
+ 0x00000200, /* DENALI_CTL_286_DATA */
+ 0x00000200, /* DENALI_CTL_287_DATA */
+ 0x00000200, /* DENALI_CTL_288_DATA */
+ 0x00001850, /* DENALI_CTL_289_DATA */
+ 0x0000f320, /* DENALI_CTL_290_DATA */
+ 0x0176060c, /* DENALI_CTL_291_DATA */
+ 0x00000200, /* DENALI_CTL_292_DATA */
+ 0x00000200, /* DENALI_CTL_293_DATA */
+ 0x00000200, /* DENALI_CTL_294_DATA */
+ 0x00000200, /* DENALI_CTL_295_DATA */
+ 0x00000176, /* DENALI_CTL_296_DATA */
+ 0x00000e9c, /* DENALI_CTL_297_DATA */
+ 0x02020205, /* DENALI_CTL_298_DATA */
+ 0x03030202, /* DENALI_CTL_299_DATA */
+ 0x00000018, /* DENALI_CTL_300_DATA */
+ 0x00000000, /* DENALI_CTL_301_DATA */
+ 0x00000000, /* DENALI_CTL_302_DATA */
+ 0x00001403, /* DENALI_CTL_303_DATA */
+ 0x00000000, /* DENALI_CTL_304_DATA */
+ 0x00000000, /* DENALI_CTL_305_DATA */
+ 0x00000000, /* DENALI_CTL_306_DATA */
+ 0x00030000, /* DENALI_CTL_307_DATA */
+ 0x000a001c, /* DENALI_CTL_308_DATA */
+ 0x000e0020, /* DENALI_CTL_309_DATA */
+ 0x00060018, /* DENALI_CTL_310_DATA */
+ 0x00000000, /* DENALI_CTL_311_DATA */
+ 0x00000000, /* DENALI_CTL_312_DATA */
+ 0x02000000, /* DENALI_CTL_313_DATA */
+ 0x00090305, /* DENALI_CTL_314_DATA */
+ 0x00050101, /* DENALI_CTL_315_DATA */
+ 0x00000000, /* DENALI_CTL_316_DATA */
+ 0x00000000, /* DENALI_CTL_317_DATA */
+ 0x00000000, /* DENALI_CTL_318_DATA */
+ 0x00000000, /* DENALI_CTL_319_DATA */
+ 0x00000000, /* DENALI_CTL_320_DATA */
+ 0x00000000, /* DENALI_CTL_321_DATA */
+ 0x00000000, /* DENALI_CTL_322_DATA */
+ 0x00000000, /* DENALI_CTL_323_DATA */
+ 0x01000001, /* DENALI_CTL_324_DATA */
+ 0x01010101, /* DENALI_CTL_325_DATA */
+ 0x01000101, /* DENALI_CTL_326_DATA */
+ 0x01000100, /* DENALI_CTL_327_DATA */
+ 0x00010001, /* DENALI_CTL_328_DATA */
+ 0x00010002, /* DENALI_CTL_329_DATA */
+ 0x00020100, /* DENALI_CTL_330_DATA */
+ 0x00000002 /* DENALI_CTL_331_DATA */
+ }
+ },
+ {
+ {
+ 0x00000b00, /* DENALI_PI_00_DATA */
+ 0x00000000, /* DENALI_PI_01_DATA */
+ 0x000002ec, /* DENALI_PI_02_DATA */
+ 0x00000176, /* DENALI_PI_03_DATA */
+ 0x000030a0, /* DENALI_PI_04_DATA */
+ 0x00001850, /* DENALI_PI_05_DATA */
+ 0x00001840, /* DENALI_PI_06_DATA */
+ 0x01760c20, /* DENALI_PI_07_DATA */
+ 0x00000200, /* DENALI_PI_08_DATA */
+ 0x00000200, /* DENALI_PI_09_DATA */
+ 0x00000200, /* DENALI_PI_10_DATA */
+ 0x00000200, /* DENALI_PI_11_DATA */
+ 0x00001850, /* DENALI_PI_12_DATA */
+ 0x00000200, /* DENALI_PI_13_DATA */
+ 0x00000200, /* DENALI_PI_14_DATA */
+ 0x00000200, /* DENALI_PI_15_DATA */
+ 0x00000200, /* DENALI_PI_16_DATA */
+ 0x00000c20, /* DENALI_PI_17_DATA */
+ 0x00000200, /* DENALI_PI_18_DATA */
+ 0x00000200, /* DENALI_PI_19_DATA */
+ 0x00000200, /* DENALI_PI_20_DATA */
+ 0x00000200, /* DENALI_PI_21_DATA */
+ 0x00010000, /* DENALI_PI_22_DATA */
+ 0x00000007, /* DENALI_PI_23_DATA */
+ 0x01000001, /* DENALI_PI_24_DATA */
+ 0x00000000, /* DENALI_PI_25_DATA */
+ 0x3fffffff, /* DENALI_PI_26_DATA */
+ 0x00000000, /* DENALI_PI_27_DATA */
+ 0x00000000, /* DENALI_PI_28_DATA */
+ 0x00000000, /* DENALI_PI_29_DATA */
+ 0x00000000, /* DENALI_PI_30_DATA */
+ 0x00000000, /* DENALI_PI_31_DATA */
+ 0x00000000, /* DENALI_PI_32_DATA */
+ 0x00000000, /* DENALI_PI_33_DATA */
+ 0x00000000, /* DENALI_PI_34_DATA */
+ 0x00000000, /* DENALI_PI_35_DATA */
+ 0x00000000, /* DENALI_PI_36_DATA */
+ 0x00000000, /* DENALI_PI_37_DATA */
+ 0x00000000, /* DENALI_PI_38_DATA */
+ 0x00000000, /* DENALI_PI_39_DATA */
+ 0x00000000, /* DENALI_PI_40_DATA */
+ 0x0f000101, /* DENALI_PI_41_DATA */
+ 0x082b3223, /* DENALI_PI_42_DATA */
+ 0x080c0004, /* DENALI_PI_43_DATA */
+ 0x00061c00, /* DENALI_PI_44_DATA */
+ 0x00000214, /* DENALI_PI_45_DATA */
+ 0x00bb0007, /* DENALI_PI_46_DATA */
+ 0x0c280068, /* DENALI_PI_47_DATA */
+ 0x06100034, /* DENALI_PI_48_DATA */
+ 0x00000500, /* DENALI_PI_49_DATA */
+ 0x00000000, /* DENALI_PI_50_DATA */
+ 0x00000000, /* DENALI_PI_51_DATA */
+ 0x00000000, /* DENALI_PI_52_DATA */
+ 0x00000000, /* DENALI_PI_53_DATA */
+ 0x00000000, /* DENALI_PI_54_DATA */
+ 0x00000000, /* DENALI_PI_55_DATA */
+ 0x00000000, /* DENALI_PI_56_DATA */
+ 0x00000000, /* DENALI_PI_57_DATA */
+ 0x04040100, /* DENALI_PI_58_DATA */
+ 0x0a000004, /* DENALI_PI_59_DATA */
+ 0x00000128, /* DENALI_PI_60_DATA */
+ 0x00000000, /* DENALI_PI_61_DATA */
+ 0x0003000f, /* DENALI_PI_62_DATA */
+ 0x00000018, /* DENALI_PI_63_DATA */
+ 0x00000000, /* DENALI_PI_64_DATA */
+ 0x00000000, /* DENALI_PI_65_DATA */
+ 0x00060002, /* DENALI_PI_66_DATA */
+ 0x00010001, /* DENALI_PI_67_DATA */
+ 0x00000101, /* DENALI_PI_68_DATA */
+ 0x00020001, /* DENALI_PI_69_DATA */
+ 0x00080004, /* DENALI_PI_70_DATA */
+ 0x00000000, /* DENALI_PI_71_DATA */
+ 0x05030000, /* DENALI_PI_72_DATA */
+ 0x070a0404, /* DENALI_PI_73_DATA */
+ 0x00000000, /* DENALI_PI_74_DATA */
+ 0x00000000, /* DENALI_PI_75_DATA */
+ 0x00000000, /* DENALI_PI_76_DATA */
+ 0x000f0f00, /* DENALI_PI_77_DATA */
+ 0x0000001e, /* DENALI_PI_78_DATA */
+ 0x00000000, /* DENALI_PI_79_DATA */
+ 0x01010300, /* DENALI_PI_80_DATA */
+ 0x00000000, /* DENALI_PI_81_DATA */
+ 0x00000000, /* DENALI_PI_82_DATA */
+ 0x01000000, /* DENALI_PI_83_DATA */
+ 0x00000101, /* DENALI_PI_84_DATA */
+ 0x55555a5a, /* DENALI_PI_85_DATA */
+ 0x55555a5a, /* DENALI_PI_86_DATA */
+ 0x55555a5a, /* DENALI_PI_87_DATA */
+ 0x55555a5a, /* DENALI_PI_88_DATA */
+ 0x0c050001, /* DENALI_PI_89_DATA */
+ 0x06020009, /* DENALI_PI_90_DATA */
+ 0x00010004, /* DENALI_PI_91_DATA */
+ 0x00000203, /* DENALI_PI_92_DATA */
+ 0x00030000, /* DENALI_PI_93_DATA */
+ 0x170f0000, /* DENALI_PI_94_DATA */
+ 0x00060018, /* DENALI_PI_95_DATA */
+ 0x000e0020, /* DENALI_PI_96_DATA */
+ 0x000a001c, /* DENALI_PI_97_DATA */
+ 0x00000000, /* DENALI_PI_98_DATA */
+ 0x00000000, /* DENALI_PI_99_DATA */
+ 0x00000100, /* DENALI_PI_100_DATA */
+ 0x140a0000, /* DENALI_PI_101_DATA */
+ 0x000d010a, /* DENALI_PI_102_DATA */
+ 0x0100c802, /* DENALI_PI_103_DATA */
+ 0x010a0064, /* DENALI_PI_104_DATA */
+ 0x000e0100, /* DENALI_PI_105_DATA */
+ 0x0100000e, /* DENALI_PI_106_DATA */
+ 0x00c900c9, /* DENALI_PI_107_DATA */
+ 0x00650100, /* DENALI_PI_108_DATA */
+ 0x1e1a0065, /* DENALI_PI_109_DATA */
+ 0x10010204, /* DENALI_PI_110_DATA */
+ 0x06070605, /* DENALI_PI_111_DATA */
+ 0x20000202, /* DENALI_PI_112_DATA */
+ 0x00201000, /* DENALI_PI_113_DATA */
+ 0x00201000, /* DENALI_PI_114_DATA */
+ 0x04041000, /* DENALI_PI_115_DATA */
+ 0x10020100, /* DENALI_PI_116_DATA */
+ 0x0003010c, /* DENALI_PI_117_DATA */
+ 0x004b004a, /* DENALI_PI_118_DATA */
+ 0x1a0f0000, /* DENALI_PI_119_DATA */
+ 0x0102041e, /* DENALI_PI_120_DATA */
+ 0x34000000, /* DENALI_PI_121_DATA */
+ 0x00000000, /* DENALI_PI_122_DATA */
+ 0x00000000, /* DENALI_PI_123_DATA */
+ 0x00010000, /* DENALI_PI_124_DATA */
+ 0x00000400, /* DENALI_PI_125_DATA */
+ 0x00310000, /* DENALI_PI_126_DATA */
+ 0x004d4d00, /* DENALI_PI_127_DATA */
+ 0x00120024, /* DENALI_PI_128_DATA */
+ 0x4d000031, /* DENALI_PI_129_DATA */
+ 0x0000144d, /* DENALI_PI_130_DATA */
+ 0x00310009, /* DENALI_PI_131_DATA */
+ 0x004d4d00, /* DENALI_PI_132_DATA */
+ 0x00000004, /* DENALI_PI_133_DATA */
+ 0x4d000031, /* DENALI_PI_134_DATA */
+ 0x0000244d, /* DENALI_PI_135_DATA */
+ 0x00310012, /* DENALI_PI_136_DATA */
+ 0x004d4d00, /* DENALI_PI_137_DATA */
+ 0x00090014, /* DENALI_PI_138_DATA */
+ 0x4d000031, /* DENALI_PI_139_DATA */
+ 0x0004004d, /* DENALI_PI_140_DATA */
+ 0x00310000, /* DENALI_PI_141_DATA */
+ 0x004d4d00, /* DENALI_PI_142_DATA */
+ 0x00120024, /* DENALI_PI_143_DATA */
+ 0x4d000031, /* DENALI_PI_144_DATA */
+ 0x0000144d, /* DENALI_PI_145_DATA */
+ 0x00310009, /* DENALI_PI_146_DATA */
+ 0x004d4d00, /* DENALI_PI_147_DATA */
+ 0x00000004, /* DENALI_PI_148_DATA */
+ 0x4d000031, /* DENALI_PI_149_DATA */
+ 0x0000244d, /* DENALI_PI_150_DATA */
+ 0x00310012, /* DENALI_PI_151_DATA */
+ 0x004d4d00, /* DENALI_PI_152_DATA */
+ 0x00090014, /* DENALI_PI_153_DATA */
+ 0x4d000031, /* DENALI_PI_154_DATA */
+ 0x0200004d, /* DENALI_PI_155_DATA */
+ 0x00c8000d, /* DENALI_PI_156_DATA */
+ 0x08080064, /* DENALI_PI_157_DATA */
+ 0x040a0404, /* DENALI_PI_158_DATA */
+ 0x03000d92, /* DENALI_PI_159_DATA */
+ 0x010a2001, /* DENALI_PI_160_DATA */
+ 0x0f11080a, /* DENALI_PI_161_DATA */
+ 0x0000110a, /* DENALI_PI_162_DATA */
+ 0x2200d92e, /* DENALI_PI_163_DATA */
+ 0x080c2003, /* DENALI_PI_164_DATA */
+ 0x0809080a, /* DENALI_PI_165_DATA */
+ 0x00000a0a, /* DENALI_PI_166_DATA */
+ 0x11006c97, /* DENALI_PI_167_DATA */
+ 0x040a2002, /* DENALI_PI_168_DATA */
+ 0x0200020a, /* DENALI_PI_169_DATA */
+ 0x02000200, /* DENALI_PI_170_DATA */
+ 0x02000200, /* DENALI_PI_171_DATA */
+ 0x02000200, /* DENALI_PI_172_DATA */
+ 0x02000200, /* DENALI_PI_173_DATA */
+ 0x00000000, /* DENALI_PI_174_DATA */
+ 0x00000000, /* DENALI_PI_175_DATA */
+ 0x00000000, /* DENALI_PI_176_DATA */
+ 0x00000000, /* DENALI_PI_177_DATA */
+ 0x00000000, /* DENALI_PI_178_DATA */
+ 0x00000000, /* DENALI_PI_179_DATA */
+ 0x00000000, /* DENALI_PI_180_DATA */
+ 0x00000000, /* DENALI_PI_181_DATA */
+ 0x00000000, /* DENALI_PI_182_DATA */
+ 0x00000000, /* DENALI_PI_183_DATA */
+ 0x00000000, /* DENALI_PI_184_DATA */
+ 0x00000000, /* DENALI_PI_185_DATA */
+ 0x01000400, /* DENALI_PI_186_DATA */
+ 0x00017600, /* DENALI_PI_187_DATA */
+ 0x00000e9c, /* DENALI_PI_188_DATA */
+ 0x00001850, /* DENALI_PI_189_DATA */
+ 0x0000f320, /* DENALI_PI_190_DATA */
+ 0x00000c20, /* DENALI_PI_191_DATA */
+ 0x00007940, /* DENALI_PI_192_DATA */
+ 0x08000000, /* DENALI_PI_193_DATA */
+ 0x00000100, /* DENALI_PI_194_DATA */
+ 0x00000000, /* DENALI_PI_195_DATA */
+ 0x00000000, /* DENALI_PI_196_DATA */
+ 0x00000000, /* DENALI_PI_197_DATA */
+ 0x00000000, /* DENALI_PI_198_DATA */
+ 0x00000002 /* DENALI_PI_199_DATA */
+ }
+ },
+ {
+ {
+ 0x76543210, /* DENALI_PHY_00_DATA */
+ 0x0004f008, /* DENALI_PHY_01_DATA */
+ 0x00020119, /* DENALI_PHY_02_DATA */
+ 0x00000000, /* DENALI_PHY_03_DATA */
+ 0x00000000, /* DENALI_PHY_04_DATA */
+ 0x00010000, /* DENALI_PHY_05_DATA */
+ 0x01665555, /* DENALI_PHY_06_DATA */
+ 0x03665555, /* DENALI_PHY_07_DATA */
+ 0x00010f00, /* DENALI_PHY_08_DATA */
+ 0x04000100, /* DENALI_PHY_09_DATA */
+ 0x00000001, /* DENALI_PHY_10_DATA */
+ 0x00170180, /* DENALI_PHY_11_DATA */
+ 0x00cc0201, /* DENALI_PHY_12_DATA */
+ 0x00030066, /* DENALI_PHY_13_DATA */
+ 0x00000000, /* DENALI_PHY_14_DATA */
+ 0x00000000, /* DENALI_PHY_15_DATA */
+ 0x00000000, /* DENALI_PHY_16_DATA */
+ 0x00000000, /* DENALI_PHY_17_DATA */
+ 0x00000000, /* DENALI_PHY_18_DATA */
+ 0x00000000, /* DENALI_PHY_19_DATA */
+ 0x00000000, /* DENALI_PHY_20_DATA */
+ 0x00000000, /* DENALI_PHY_21_DATA */
+ 0x04080000, /* DENALI_PHY_22_DATA */
+ 0x04080400, /* DENALI_PHY_23_DATA */
+ 0x30000000, /* DENALI_PHY_24_DATA */
+ 0x0c00c007, /* DENALI_PHY_25_DATA */
+ 0x00000100, /* DENALI_PHY_26_DATA */
+ 0x00000000, /* DENALI_PHY_27_DATA */
+ 0xfd02fe01, /* DENALI_PHY_28_DATA */
+ 0xf708fb04, /* DENALI_PHY_29_DATA */
+ 0xdf20ef10, /* DENALI_PHY_30_DATA */
+ 0x7f80bf40, /* DENALI_PHY_31_DATA */
+ 0x0001aaaa, /* DENALI_PHY_32_DATA */
+ 0x00000000, /* DENALI_PHY_33_DATA */
+ 0x00000000, /* DENALI_PHY_34_DATA */
+ 0x00000000, /* DENALI_PHY_35_DATA */
+ 0x00000000, /* DENALI_PHY_36_DATA */
+ 0x00000000, /* DENALI_PHY_37_DATA */
+ 0x00000000, /* DENALI_PHY_38_DATA */
+ 0x00000000, /* DENALI_PHY_39_DATA */
+ 0x00000000, /* DENALI_PHY_40_DATA */
+ 0x00000000, /* DENALI_PHY_41_DATA */
+ 0x00000000, /* DENALI_PHY_42_DATA */
+ 0x00000000, /* DENALI_PHY_43_DATA */
+ 0x00000000, /* DENALI_PHY_44_DATA */
+ 0x00000000, /* DENALI_PHY_45_DATA */
+ 0x00000000, /* DENALI_PHY_46_DATA */
+ 0x00000000, /* DENALI_PHY_47_DATA */
+ 0x00000000, /* DENALI_PHY_48_DATA */
+ 0x00000000, /* DENALI_PHY_49_DATA */
+ 0x00000000, /* DENALI_PHY_50_DATA */
+ 0x00000000, /* DENALI_PHY_51_DATA */
+ 0x00200000, /* DENALI_PHY_52_DATA */
+ 0x00000000, /* DENALI_PHY_53_DATA */
+ 0x00000000, /* DENALI_PHY_54_DATA */
+ 0x00000000, /* DENALI_PHY_55_DATA */
+ 0x00000000, /* DENALI_PHY_56_DATA */
+ 0x00000000, /* DENALI_PHY_57_DATA */
+ 0x00000000, /* DENALI_PHY_58_DATA */
+ 0x02800280, /* DENALI_PHY_59_DATA */
+ 0x02800280, /* DENALI_PHY_60_DATA */
+ 0x02800280, /* DENALI_PHY_61_DATA */
+ 0x02800280, /* DENALI_PHY_62_DATA */
+ 0x00000280, /* DENALI_PHY_63_DATA */
+ 0x00000000, /* DENALI_PHY_64_DATA */
+ 0x00000000, /* DENALI_PHY_65_DATA */
+ 0x00000000, /* DENALI_PHY_66_DATA */
+ 0x00000000, /* DENALI_PHY_67_DATA */
+ 0x00800000, /* DENALI_PHY_68_DATA */
+ 0x00800080, /* DENALI_PHY_69_DATA */
+ 0x00800080, /* DENALI_PHY_70_DATA */
+ 0x00800080, /* DENALI_PHY_71_DATA */
+ 0x00800080, /* DENALI_PHY_72_DATA */
+ 0x00800080, /* DENALI_PHY_73_DATA */
+ 0x00800080, /* DENALI_PHY_74_DATA */
+ 0x00800080, /* DENALI_PHY_75_DATA */
+ 0x00800080, /* DENALI_PHY_76_DATA */
+ 0x01190080, /* DENALI_PHY_77_DATA */
+ 0x00000001, /* DENALI_PHY_78_DATA */
+ 0x00000000, /* DENALI_PHY_79_DATA */
+ 0x00000000, /* DENALI_PHY_80_DATA */
+ 0x00000200, /* DENALI_PHY_81_DATA */
+ 0x00000000, /* DENALI_PHY_82_DATA */
+ 0x51315152, /* DENALI_PHY_83_DATA */
+ 0xc0003150, /* DENALI_PHY_84_DATA */
+ 0x010000c0, /* DENALI_PHY_85_DATA */
+ 0x00100000, /* DENALI_PHY_86_DATA */
+ 0x07044204, /* DENALI_PHY_87_DATA */
+ 0x000f0c18, /* DENALI_PHY_88_DATA */
+ 0x01000140, /* DENALI_PHY_89_DATA */
+ 0x00000c10, /* DENALI_PHY_90_DATA */
+ 0x00000000, /* DENALI_PHY_91_DATA */
+ 0x00000000, /* DENALI_PHY_92_DATA */
+ 0x00000000, /* DENALI_PHY_93_DATA */
+ 0x00000000, /* DENALI_PHY_94_DATA */
+ 0x00000000, /* DENALI_PHY_95_DATA */
+ 0x00000000, /* DENALI_PHY_96_DATA */
+ 0x00000000, /* DENALI_PHY_97_DATA */
+ 0x00000000, /* DENALI_PHY_98_DATA */
+ 0x00000000, /* DENALI_PHY_99_DATA */
+ 0x00000000, /* DENALI_PHY_100_DATA */
+ 0x00000000, /* DENALI_PHY_101_DATA */
+ 0x00000000, /* DENALI_PHY_102_DATA */
+ 0x00000000, /* DENALI_PHY_103_DATA */
+ 0x00000000, /* DENALI_PHY_104_DATA */
+ 0x00000000, /* DENALI_PHY_105_DATA */
+ 0x00000000, /* DENALI_PHY_106_DATA */
+ 0x00000000, /* DENALI_PHY_107_DATA */
+ 0x00000000, /* DENALI_PHY_108_DATA */
+ 0x00000000, /* DENALI_PHY_109_DATA */
+ 0x00000000, /* DENALI_PHY_110_DATA */
+ 0x00000000, /* DENALI_PHY_111_DATA */
+ 0x00000000, /* DENALI_PHY_112_DATA */
+ 0x00000000, /* DENALI_PHY_113_DATA */
+ 0x00000000, /* DENALI_PHY_114_DATA */
+ 0x00000000, /* DENALI_PHY_115_DATA */
+ 0x00000000, /* DENALI_PHY_116_DATA */
+ 0x00000000, /* DENALI_PHY_117_DATA */
+ 0x00000000, /* DENALI_PHY_118_DATA */
+ 0x00000000, /* DENALI_PHY_119_DATA */
+ 0x00000000, /* DENALI_PHY_120_DATA */
+ 0x00000000, /* DENALI_PHY_121_DATA */
+ 0x00000000, /* DENALI_PHY_122_DATA */
+ 0x00000000, /* DENALI_PHY_123_DATA */
+ 0x00000000, /* DENALI_PHY_124_DATA */
+ 0x00000000, /* DENALI_PHY_125_DATA */
+ 0x00000000, /* DENALI_PHY_126_DATA */
+ 0x00000000, /* DENALI_PHY_127_DATA */
+ 0x76543210, /* DENALI_PHY_128_DATA */
+ 0x0004f008, /* DENALI_PHY_129_DATA */
+ 0x00020119, /* DENALI_PHY_130_DATA */
+ 0x00000000, /* DENALI_PHY_131_DATA */
+ 0x00000000, /* DENALI_PHY_132_DATA */
+ 0x00010000, /* DENALI_PHY_133_DATA */
+ 0x01665555, /* DENALI_PHY_134_DATA */
+ 0x03665555, /* DENALI_PHY_135_DATA */
+ 0x00010f00, /* DENALI_PHY_136_DATA */
+ 0x04000100, /* DENALI_PHY_137_DATA */
+ 0x00000001, /* DENALI_PHY_138_DATA */
+ 0x00170180, /* DENALI_PHY_139_DATA */
+ 0x00cc0201, /* DENALI_PHY_140_DATA */
+ 0x00030066, /* DENALI_PHY_141_DATA */
+ 0x00000000, /* DENALI_PHY_142_DATA */
+ 0x00000000, /* DENALI_PHY_143_DATA */
+ 0x00000000, /* DENALI_PHY_144_DATA */
+ 0x00000000, /* DENALI_PHY_145_DATA */
+ 0x00000000, /* DENALI_PHY_146_DATA */
+ 0x00000000, /* DENALI_PHY_147_DATA */
+ 0x00000000, /* DENALI_PHY_148_DATA */
+ 0x00000000, /* DENALI_PHY_149_DATA */
+ 0x04080000, /* DENALI_PHY_150_DATA */
+ 0x04080400, /* DENALI_PHY_151_DATA */
+ 0x30000000, /* DENALI_PHY_152_DATA */
+ 0x0c00c007, /* DENALI_PHY_153_DATA */
+ 0x00000100, /* DENALI_PHY_154_DATA */
+ 0x00000000, /* DENALI_PHY_155_DATA */
+ 0xfd02fe01, /* DENALI_PHY_156_DATA */
+ 0xf708fb04, /* DENALI_PHY_157_DATA */
+ 0xdf20ef10, /* DENALI_PHY_158_DATA */
+ 0x7f80bf40, /* DENALI_PHY_159_DATA */
+ 0x0000aaaa, /* DENALI_PHY_160_DATA */
+ 0x00000000, /* DENALI_PHY_161_DATA */
+ 0x00000000, /* DENALI_PHY_162_DATA */
+ 0x00000000, /* DENALI_PHY_163_DATA */
+ 0x00000000, /* DENALI_PHY_164_DATA */
+ 0x00000000, /* DENALI_PHY_165_DATA */
+ 0x00000000, /* DENALI_PHY_166_DATA */
+ 0x00000000, /* DENALI_PHY_167_DATA */
+ 0x00000000, /* DENALI_PHY_168_DATA */
+ 0x00000000, /* DENALI_PHY_169_DATA */
+ 0x00000000, /* DENALI_PHY_170_DATA */
+ 0x00000000, /* DENALI_PHY_171_DATA */
+ 0x00000000, /* DENALI_PHY_172_DATA */
+ 0x00000000, /* DENALI_PHY_173_DATA */
+ 0x00000000, /* DENALI_PHY_174_DATA */
+ 0x00000000, /* DENALI_PHY_175_DATA */
+ 0x00000000, /* DENALI_PHY_176_DATA */
+ 0x00000000, /* DENALI_PHY_177_DATA */
+ 0x00000000, /* DENALI_PHY_178_DATA */
+ 0x00000000, /* DENALI_PHY_179_DATA */
+ 0x00200000, /* DENALI_PHY_180_DATA */
+ 0x00000000, /* DENALI_PHY_181_DATA */
+ 0x00000000, /* DENALI_PHY_182_DATA */
+ 0x00000000, /* DENALI_PHY_183_DATA */
+ 0x00000000, /* DENALI_PHY_184_DATA */
+ 0x00000000, /* DENALI_PHY_185_DATA */
+ 0x00000000, /* DENALI_PHY_186_DATA */
+ 0x02800280, /* DENALI_PHY_187_DATA */
+ 0x02800280, /* DENALI_PHY_188_DATA */
+ 0x02800280, /* DENALI_PHY_189_DATA */
+ 0x02800280, /* DENALI_PHY_190_DATA */
+ 0x00000280, /* DENALI_PHY_191_DATA */
+ 0x00000000, /* DENALI_PHY_192_DATA */
+ 0x00000000, /* DENALI_PHY_193_DATA */
+ 0x00000000, /* DENALI_PHY_194_DATA */
+ 0x00000000, /* DENALI_PHY_195_DATA */
+ 0x00800000, /* DENALI_PHY_196_DATA */
+ 0x00800080, /* DENALI_PHY_197_DATA */
+ 0x00800080, /* DENALI_PHY_198_DATA */
+ 0x00800080, /* DENALI_PHY_199_DATA */
+ 0x00800080, /* DENALI_PHY_200_DATA */
+ 0x00800080, /* DENALI_PHY_201_DATA */
+ 0x00800080, /* DENALI_PHY_202_DATA */
+ 0x00800080, /* DENALI_PHY_203_DATA */
+ 0x00800080, /* DENALI_PHY_204_DATA */
+ 0x01190080, /* DENALI_PHY_205_DATA */
+ 0x00000001, /* DENALI_PHY_206_DATA */
+ 0x00000000, /* DENALI_PHY_207_DATA */
+ 0x00000000, /* DENALI_PHY_208_DATA */
+ 0x00000200, /* DENALI_PHY_209_DATA */
+ 0x00000000, /* DENALI_PHY_210_DATA */
+ 0x51315152, /* DENALI_PHY_211_DATA */
+ 0xc0003150, /* DENALI_PHY_212_DATA */
+ 0x010000c0, /* DENALI_PHY_213_DATA */
+ 0x00100000, /* DENALI_PHY_214_DATA */
+ 0x07044204, /* DENALI_PHY_215_DATA */
+ 0x000f0c18, /* DENALI_PHY_216_DATA */
+ 0x01000140, /* DENALI_PHY_217_DATA */
+ 0x00000c10, /* DENALI_PHY_218_DATA */
+ 0x00000000, /* DENALI_PHY_219_DATA */
+ 0x00000000, /* DENALI_PHY_220_DATA */
+ 0x00000000, /* DENALI_PHY_221_DATA */
+ 0x00000000, /* DENALI_PHY_222_DATA */
+ 0x00000000, /* DENALI_PHY_223_DATA */
+ 0x00000000, /* DENALI_PHY_224_DATA */
+ 0x00000000, /* DENALI_PHY_225_DATA */
+ 0x00000000, /* DENALI_PHY_226_DATA */
+ 0x00000000, /* DENALI_PHY_227_DATA */
+ 0x00000000, /* DENALI_PHY_228_DATA */
+ 0x00000000, /* DENALI_PHY_229_DATA */
+ 0x00000000, /* DENALI_PHY_230_DATA */
+ 0x00000000, /* DENALI_PHY_231_DATA */
+ 0x00000000, /* DENALI_PHY_232_DATA */
+ 0x00000000, /* DENALI_PHY_233_DATA */
+ 0x00000000, /* DENALI_PHY_234_DATA */
+ 0x00000000, /* DENALI_PHY_235_DATA */
+ 0x00000000, /* DENALI_PHY_236_DATA */
+ 0x00000000, /* DENALI_PHY_237_DATA */
+ 0x00000000, /* DENALI_PHY_238_DATA */
+ 0x00000000, /* DENALI_PHY_239_DATA */
+ 0x00000000, /* DENALI_PHY_240_DATA */
+ 0x00000000, /* DENALI_PHY_241_DATA */
+ 0x00000000, /* DENALI_PHY_242_DATA */
+ 0x00000000, /* DENALI_PHY_243_DATA */
+ 0x00000000, /* DENALI_PHY_244_DATA */
+ 0x00000000, /* DENALI_PHY_245_DATA */
+ 0x00000000, /* DENALI_PHY_246_DATA */
+ 0x00000000, /* DENALI_PHY_247_DATA */
+ 0x00000000, /* DENALI_PHY_248_DATA */
+ 0x00000000, /* DENALI_PHY_249_DATA */
+ 0x00000000, /* DENALI_PHY_250_DATA */
+ 0x00000000, /* DENALI_PHY_251_DATA */
+ 0x00000000, /* DENALI_PHY_252_DATA */
+ 0x00000000, /* DENALI_PHY_253_DATA */
+ 0x00000000, /* DENALI_PHY_254_DATA */
+ 0x00000000, /* DENALI_PHY_255_DATA */
+ 0x76543210, /* DENALI_PHY_256_DATA */
+ 0x0004f008, /* DENALI_PHY_257_DATA */
+ 0x00020119, /* DENALI_PHY_258_DATA */
+ 0x00000000, /* DENALI_PHY_259_DATA */
+ 0x00000000, /* DENALI_PHY_260_DATA */
+ 0x00010000, /* DENALI_PHY_261_DATA */
+ 0x01665555, /* DENALI_PHY_262_DATA */
+ 0x03665555, /* DENALI_PHY_263_DATA */
+ 0x00010f00, /* DENALI_PHY_264_DATA */
+ 0x04000100, /* DENALI_PHY_265_DATA */
+ 0x00000001, /* DENALI_PHY_266_DATA */
+ 0x00170180, /* DENALI_PHY_267_DATA */
+ 0x00cc0201, /* DENALI_PHY_268_DATA */
+ 0x00030066, /* DENALI_PHY_269_DATA */
+ 0x00000000, /* DENALI_PHY_270_DATA */
+ 0x00000000, /* DENALI_PHY_271_DATA */
+ 0x00000000, /* DENALI_PHY_272_DATA */
+ 0x00000000, /* DENALI_PHY_273_DATA */
+ 0x00000000, /* DENALI_PHY_274_DATA */
+ 0x00000000, /* DENALI_PHY_275_DATA */
+ 0x00000000, /* DENALI_PHY_276_DATA */
+ 0x00000000, /* DENALI_PHY_277_DATA */
+ 0x04080000, /* DENALI_PHY_278_DATA */
+ 0x04080400, /* DENALI_PHY_279_DATA */
+ 0x30000000, /* DENALI_PHY_280_DATA */
+ 0x0c00c007, /* DENALI_PHY_281_DATA */
+ 0x00000100, /* DENALI_PHY_282_DATA */
+ 0x00000000, /* DENALI_PHY_283_DATA */
+ 0xfd02fe01, /* DENALI_PHY_284_DATA */
+ 0xf708fb04, /* DENALI_PHY_285_DATA */
+ 0xdf20ef10, /* DENALI_PHY_286_DATA */
+ 0x7f80bf40, /* DENALI_PHY_287_DATA */
+ 0x0001aaaa, /* DENALI_PHY_288_DATA */
+ 0x00000000, /* DENALI_PHY_289_DATA */
+ 0x00000000, /* DENALI_PHY_290_DATA */
+ 0x00000000, /* DENALI_PHY_291_DATA */
+ 0x00000000, /* DENALI_PHY_292_DATA */
+ 0x00000000, /* DENALI_PHY_293_DATA */
+ 0x00000000, /* DENALI_PHY_294_DATA */
+ 0x00000000, /* DENALI_PHY_295_DATA */
+ 0x00000000, /* DENALI_PHY_296_DATA */
+ 0x00000000, /* DENALI_PHY_297_DATA */
+ 0x00000000, /* DENALI_PHY_298_DATA */
+ 0x00000000, /* DENALI_PHY_299_DATA */
+ 0x00000000, /* DENALI_PHY_300_DATA */
+ 0x00000000, /* DENALI_PHY_301_DATA */
+ 0x00000000, /* DENALI_PHY_302_DATA */
+ 0x00000000, /* DENALI_PHY_303_DATA */
+ 0x00000000, /* DENALI_PHY_304_DATA */
+ 0x00000000, /* DENALI_PHY_305_DATA */
+ 0x00000000, /* DENALI_PHY_306_DATA */
+ 0x00000000, /* DENALI_PHY_307_DATA */
+ 0x00200000, /* DENALI_PHY_308_DATA */
+ 0x00000000, /* DENALI_PHY_309_DATA */
+ 0x00000000, /* DENALI_PHY_310_DATA */
+ 0x00000000, /* DENALI_PHY_311_DATA */
+ 0x00000000, /* DENALI_PHY_312_DATA */
+ 0x00000000, /* DENALI_PHY_313_DATA */
+ 0x00000000, /* DENALI_PHY_314_DATA */
+ 0x02800280, /* DENALI_PHY_315_DATA */
+ 0x02800280, /* DENALI_PHY_316_DATA */
+ 0x02800280, /* DENALI_PHY_317_DATA */
+ 0x02800280, /* DENALI_PHY_318_DATA */
+ 0x00000280, /* DENALI_PHY_319_DATA */
+ 0x00000000, /* DENALI_PHY_320_DATA */
+ 0x00000000, /* DENALI_PHY_321_DATA */
+ 0x00000000, /* DENALI_PHY_322_DATA */
+ 0x00000000, /* DENALI_PHY_323_DATA */
+ 0x00800000, /* DENALI_PHY_324_DATA */
+ 0x00800080, /* DENALI_PHY_325_DATA */
+ 0x00800080, /* DENALI_PHY_326_DATA */
+ 0x00800080, /* DENALI_PHY_327_DATA */
+ 0x00800080, /* DENALI_PHY_328_DATA */
+ 0x00800080, /* DENALI_PHY_329_DATA */
+ 0x00800080, /* DENALI_PHY_330_DATA */
+ 0x00800080, /* DENALI_PHY_331_DATA */
+ 0x00800080, /* DENALI_PHY_332_DATA */
+ 0x01190080, /* DENALI_PHY_333_DATA */
+ 0x00000001, /* DENALI_PHY_334_DATA */
+ 0x00000000, /* DENALI_PHY_335_DATA */
+ 0x00000000, /* DENALI_PHY_336_DATA */
+ 0x00000200, /* DENALI_PHY_337_DATA */
+ 0x00000000, /* DENALI_PHY_338_DATA */
+ 0x51315152, /* DENALI_PHY_339_DATA */
+ 0xc0003150, /* DENALI_PHY_340_DATA */
+ 0x010000c0, /* DENALI_PHY_341_DATA */
+ 0x00100000, /* DENALI_PHY_342_DATA */
+ 0x07044204, /* DENALI_PHY_343_DATA */
+ 0x000f0c18, /* DENALI_PHY_344_DATA */
+ 0x01000140, /* DENALI_PHY_345_DATA */
+ 0x00000c10, /* DENALI_PHY_346_DATA */
+ 0x00000000, /* DENALI_PHY_347_DATA */
+ 0x00000000, /* DENALI_PHY_348_DATA */
+ 0x00000000, /* DENALI_PHY_349_DATA */
+ 0x00000000, /* DENALI_PHY_350_DATA */
+ 0x00000000, /* DENALI_PHY_351_DATA */
+ 0x00000000, /* DENALI_PHY_352_DATA */
+ 0x00000000, /* DENALI_PHY_353_DATA */
+ 0x00000000, /* DENALI_PHY_354_DATA */
+ 0x00000000, /* DENALI_PHY_355_DATA */
+ 0x00000000, /* DENALI_PHY_356_DATA */
+ 0x00000000, /* DENALI_PHY_357_DATA */
+ 0x00000000, /* DENALI_PHY_358_DATA */
+ 0x00000000, /* DENALI_PHY_359_DATA */
+ 0x00000000, /* DENALI_PHY_360_DATA */
+ 0x00000000, /* DENALI_PHY_361_DATA */
+ 0x00000000, /* DENALI_PHY_362_DATA */
+ 0x00000000, /* DENALI_PHY_363_DATA */
+ 0x00000000, /* DENALI_PHY_364_DATA */
+ 0x00000000, /* DENALI_PHY_365_DATA */
+ 0x00000000, /* DENALI_PHY_366_DATA */
+ 0x00000000, /* DENALI_PHY_367_DATA */
+ 0x00000000, /* DENALI_PHY_368_DATA */
+ 0x00000000, /* DENALI_PHY_369_DATA */
+ 0x00000000, /* DENALI_PHY_370_DATA */
+ 0x00000000, /* DENALI_PHY_371_DATA */
+ 0x00000000, /* DENALI_PHY_372_DATA */
+ 0x00000000, /* DENALI_PHY_373_DATA */
+ 0x00000000, /* DENALI_PHY_374_DATA */
+ 0x00000000, /* DENALI_PHY_375_DATA */
+ 0x00000000, /* DENALI_PHY_376_DATA */
+ 0x00000000, /* DENALI_PHY_377_DATA */
+ 0x00000000, /* DENALI_PHY_378_DATA */
+ 0x00000000, /* DENALI_PHY_379_DATA */
+ 0x00000000, /* DENALI_PHY_380_DATA */
+ 0x00000000, /* DENALI_PHY_381_DATA */
+ 0x00000000, /* DENALI_PHY_382_DATA */
+ 0x00000000, /* DENALI_PHY_383_DATA */
+ 0x76543210, /* DENALI_PHY_384_DATA */
+ 0x0004f008, /* DENALI_PHY_385_DATA */
+ 0x00020119, /* DENALI_PHY_386_DATA */
+ 0x00000000, /* DENALI_PHY_387_DATA */
+ 0x00000000, /* DENALI_PHY_388_DATA */
+ 0x00010000, /* DENALI_PHY_389_DATA */
+ 0x01665555, /* DENALI_PHY_390_DATA */
+ 0x03665555, /* DENALI_PHY_391_DATA */
+ 0x00010f00, /* DENALI_PHY_392_DATA */
+ 0x04000100, /* DENALI_PHY_393_DATA */
+ 0x00000001, /* DENALI_PHY_394_DATA */
+ 0x00170180, /* DENALI_PHY_395_DATA */
+ 0x00cc0201, /* DENALI_PHY_396_DATA */
+ 0x00030066, /* DENALI_PHY_397_DATA */
+ 0x00000000, /* DENALI_PHY_398_DATA */
+ 0x00000000, /* DENALI_PHY_399_DATA */
+ 0x00000000, /* DENALI_PHY_400_DATA */
+ 0x00000000, /* DENALI_PHY_401_DATA */
+ 0x00000000, /* DENALI_PHY_402_DATA */
+ 0x00000000, /* DENALI_PHY_403_DATA */
+ 0x00000000, /* DENALI_PHY_404_DATA */
+ 0x00000000, /* DENALI_PHY_405_DATA */
+ 0x04080000, /* DENALI_PHY_406_DATA */
+ 0x04080400, /* DENALI_PHY_407_DATA */
+ 0x30000000, /* DENALI_PHY_408_DATA */
+ 0x0c00c007, /* DENALI_PHY_409_DATA */
+ 0x00000100, /* DENALI_PHY_410_DATA */
+ 0x00000000, /* DENALI_PHY_411_DATA */
+ 0xfd02fe01, /* DENALI_PHY_412_DATA */
+ 0xf708fb04, /* DENALI_PHY_413_DATA */
+ 0xdf20ef10, /* DENALI_PHY_414_DATA */
+ 0x7f80bf40, /* DENALI_PHY_415_DATA */
+ 0x0000aaaa, /* DENALI_PHY_416_DATA */
+ 0x00000000, /* DENALI_PHY_417_DATA */
+ 0x00000000, /* DENALI_PHY_418_DATA */
+ 0x00000000, /* DENALI_PHY_419_DATA */
+ 0x00000000, /* DENALI_PHY_420_DATA */
+ 0x00000000, /* DENALI_PHY_421_DATA */
+ 0x00000000, /* DENALI_PHY_422_DATA */
+ 0x00000000, /* DENALI_PHY_423_DATA */
+ 0x00000000, /* DENALI_PHY_424_DATA */
+ 0x00000000, /* DENALI_PHY_425_DATA */
+ 0x00000000, /* DENALI_PHY_426_DATA */
+ 0x00000000, /* DENALI_PHY_427_DATA */
+ 0x00000000, /* DENALI_PHY_428_DATA */
+ 0x00000000, /* DENALI_PHY_429_DATA */
+ 0x00000000, /* DENALI_PHY_430_DATA */
+ 0x00000000, /* DENALI_PHY_431_DATA */
+ 0x00000000, /* DENALI_PHY_432_DATA */
+ 0x00000000, /* DENALI_PHY_433_DATA */
+ 0x00000000, /* DENALI_PHY_434_DATA */
+ 0x00000000, /* DENALI_PHY_435_DATA */
+ 0x00200000, /* DENALI_PHY_436_DATA */
+ 0x00000000, /* DENALI_PHY_437_DATA */
+ 0x00000000, /* DENALI_PHY_438_DATA */
+ 0x00000000, /* DENALI_PHY_439_DATA */
+ 0x00000000, /* DENALI_PHY_440_DATA */
+ 0x00000000, /* DENALI_PHY_441_DATA */
+ 0x00000000, /* DENALI_PHY_442_DATA */
+ 0x02800280, /* DENALI_PHY_443_DATA */
+ 0x02800280, /* DENALI_PHY_444_DATA */
+ 0x02800280, /* DENALI_PHY_445_DATA */
+ 0x02800280, /* DENALI_PHY_446_DATA */
+ 0x00000280, /* DENALI_PHY_447_DATA */
+ 0x00000000, /* DENALI_PHY_448_DATA */
+ 0x00000000, /* DENALI_PHY_449_DATA */
+ 0x00000000, /* DENALI_PHY_450_DATA */
+ 0x00000000, /* DENALI_PHY_451_DATA */
+ 0x00800000, /* DENALI_PHY_452_DATA */
+ 0x00800080, /* DENALI_PHY_453_DATA */
+ 0x00800080, /* DENALI_PHY_454_DATA */
+ 0x00800080, /* DENALI_PHY_455_DATA */
+ 0x00800080, /* DENALI_PHY_456_DATA */
+ 0x00800080, /* DENALI_PHY_457_DATA */
+ 0x00800080, /* DENALI_PHY_458_DATA */
+ 0x00800080, /* DENALI_PHY_459_DATA */
+ 0x00800080, /* DENALI_PHY_460_DATA */
+ 0x01190080, /* DENALI_PHY_461_DATA */
+ 0x00000001, /* DENALI_PHY_462_DATA */
+ 0x00000000, /* DENALI_PHY_463_DATA */
+ 0x00000000, /* DENALI_PHY_464_DATA */
+ 0x00000200, /* DENALI_PHY_465_DATA */
+ 0x00000000, /* DENALI_PHY_466_DATA */
+ 0x51315152, /* DENALI_PHY_467_DATA */
+ 0xc0003150, /* DENALI_PHY_468_DATA */
+ 0x010000c0, /* DENALI_PHY_469_DATA */
+ 0x00100000, /* DENALI_PHY_470_DATA */
+ 0x07044204, /* DENALI_PHY_471_DATA */
+ 0x000f0c18, /* DENALI_PHY_472_DATA */
+ 0x01000140, /* DENALI_PHY_473_DATA */
+ 0x00000c10, /* DENALI_PHY_474_DATA */
+ 0x00000000, /* DENALI_PHY_475_DATA */
+ 0x00000000, /* DENALI_PHY_476_DATA */
+ 0x00000000, /* DENALI_PHY_477_DATA */
+ 0x00000000, /* DENALI_PHY_478_DATA */
+ 0x00000000, /* DENALI_PHY_479_DATA */
+ 0x00000000, /* DENALI_PHY_480_DATA */
+ 0x00000000, /* DENALI_PHY_481_DATA */
+ 0x00000000, /* DENALI_PHY_482_DATA */
+ 0x00000000, /* DENALI_PHY_483_DATA */
+ 0x00000000, /* DENALI_PHY_484_DATA */
+ 0x00000000, /* DENALI_PHY_485_DATA */
+ 0x00000000, /* DENALI_PHY_486_DATA */
+ 0x00000000, /* DENALI_PHY_487_DATA */
+ 0x00000000, /* DENALI_PHY_488_DATA */
+ 0x00000000, /* DENALI_PHY_489_DATA */
+ 0x00000000, /* DENALI_PHY_490_DATA */
+ 0x00000000, /* DENALI_PHY_491_DATA */
+ 0x00000000, /* DENALI_PHY_492_DATA */
+ 0x00000000, /* DENALI_PHY_493_DATA */
+ 0x00000000, /* DENALI_PHY_494_DATA */
+ 0x00000000, /* DENALI_PHY_495_DATA */
+ 0x00000000, /* DENALI_PHY_496_DATA */
+ 0x00000000, /* DENALI_PHY_497_DATA */
+ 0x00000000, /* DENALI_PHY_498_DATA */
+ 0x00000000, /* DENALI_PHY_499_DATA */
+ 0x00000000, /* DENALI_PHY_500_DATA */
+ 0x00000000, /* DENALI_PHY_501_DATA */
+ 0x00000000, /* DENALI_PHY_502_DATA */
+ 0x00000000, /* DENALI_PHY_503_DATA */
+ 0x00000000, /* DENALI_PHY_504_DATA */
+ 0x00000000, /* DENALI_PHY_505_DATA */
+ 0x00000000, /* DENALI_PHY_506_DATA */
+ 0x00000000, /* DENALI_PHY_507_DATA */
+ 0x00000000, /* DENALI_PHY_508_DATA */
+ 0x00000000, /* DENALI_PHY_509_DATA */
+ 0x00000000, /* DENALI_PHY_510_DATA */
+ 0x00000000, /* DENALI_PHY_511_DATA */
+ 0x00000000, /* DENALI_PHY_512_DATA */
+ 0x00000000, /* DENALI_PHY_513_DATA */
+ 0x00000000, /* DENALI_PHY_514_DATA */
+ 0x00000000, /* DENALI_PHY_515_DATA */
+ 0x00000000, /* DENALI_PHY_516_DATA */
+ 0x00000000, /* DENALI_PHY_517_DATA */
+ 0x00000000, /* DENALI_PHY_518_DATA */
+ 0x00000002, /* DENALI_PHY_519_DATA */
+ 0x00000000, /* DENALI_PHY_520_DATA */
+ 0x00000000, /* DENALI_PHY_521_DATA */
+ 0x00000000, /* DENALI_PHY_522_DATA */
+ 0x00400320, /* DENALI_PHY_523_DATA */
+ 0x00000040, /* DENALI_PHY_524_DATA */
+ 0x00dcba98, /* DENALI_PHY_525_DATA */
+ 0x00000000, /* DENALI_PHY_526_DATA */
+ 0x00dcba98, /* DENALI_PHY_527_DATA */
+ 0x01000000, /* DENALI_PHY_528_DATA */
+ 0x00020003, /* DENALI_PHY_529_DATA */
+ 0x00000000, /* DENALI_PHY_530_DATA */
+ 0x00000000, /* DENALI_PHY_531_DATA */
+ 0x00000000, /* DENALI_PHY_532_DATA */
+ 0x0000002a, /* DENALI_PHY_533_DATA */
+ 0x00000015, /* DENALI_PHY_534_DATA */
+ 0x00000015, /* DENALI_PHY_535_DATA */
+ 0x0000002a, /* DENALI_PHY_536_DATA */
+ 0x00000033, /* DENALI_PHY_537_DATA */
+ 0x0000000c, /* DENALI_PHY_538_DATA */
+ 0x0000000c, /* DENALI_PHY_539_DATA */
+ 0x00000033, /* DENALI_PHY_540_DATA */
+ 0x0a418820, /* DENALI_PHY_541_DATA */
+ 0x003f0000, /* DENALI_PHY_542_DATA */
+ 0x0000003f, /* DENALI_PHY_543_DATA */
+ 0x00030055, /* DENALI_PHY_544_DATA */
+ 0x03000300, /* DENALI_PHY_545_DATA */
+ 0x03000300, /* DENALI_PHY_546_DATA */
+ 0x00000300, /* DENALI_PHY_547_DATA */
+ 0x42080010, /* DENALI_PHY_548_DATA */
+ 0x00000003, /* DENALI_PHY_549_DATA */
+ 0x00000000, /* DENALI_PHY_550_DATA */
+ 0x00000000, /* DENALI_PHY_551_DATA */
+ 0x00000000, /* DENALI_PHY_552_DATA */
+ 0x00000000, /* DENALI_PHY_553_DATA */
+ 0x00000000, /* DENALI_PHY_554_DATA */
+ 0x00000000, /* DENALI_PHY_555_DATA */
+ 0x00000000, /* DENALI_PHY_556_DATA */
+ 0x00000000, /* DENALI_PHY_557_DATA */
+ 0x00000000, /* DENALI_PHY_558_DATA */
+ 0x00000000, /* DENALI_PHY_559_DATA */
+ 0x00000000, /* DENALI_PHY_560_DATA */
+ 0x00000000, /* DENALI_PHY_561_DATA */
+ 0x00000000, /* DENALI_PHY_562_DATA */
+ 0x00000000, /* DENALI_PHY_563_DATA */
+ 0x00000000, /* DENALI_PHY_564_DATA */
+ 0x00000000, /* DENALI_PHY_565_DATA */
+ 0x00000000, /* DENALI_PHY_566_DATA */
+ 0x00000000, /* DENALI_PHY_567_DATA */
+ 0x00000000, /* DENALI_PHY_568_DATA */
+ 0x00000000, /* DENALI_PHY_569_DATA */
+ 0x00000000, /* DENALI_PHY_570_DATA */
+ 0x00000000, /* DENALI_PHY_571_DATA */
+ 0x00000000, /* DENALI_PHY_572_DATA */
+ 0x00000000, /* DENALI_PHY_573_DATA */
+ 0x00000000, /* DENALI_PHY_574_DATA */
+ 0x00000000, /* DENALI_PHY_575_DATA */
+ 0x00000000, /* DENALI_PHY_576_DATA */
+ 0x00000000, /* DENALI_PHY_577_DATA */
+ 0x00000000, /* DENALI_PHY_578_DATA */
+ 0x00000000, /* DENALI_PHY_579_DATA */
+ 0x00000000, /* DENALI_PHY_580_DATA */
+ 0x00000000, /* DENALI_PHY_581_DATA */
+ 0x00000000, /* DENALI_PHY_582_DATA */
+ 0x00000000, /* DENALI_PHY_583_DATA */
+ 0x00000000, /* DENALI_PHY_584_DATA */
+ 0x00000000, /* DENALI_PHY_585_DATA */
+ 0x00000000, /* DENALI_PHY_586_DATA */
+ 0x00000000, /* DENALI_PHY_587_DATA */
+ 0x00000000, /* DENALI_PHY_588_DATA */
+ 0x00000000, /* DENALI_PHY_589_DATA */
+ 0x00000000, /* DENALI_PHY_590_DATA */
+ 0x00000000, /* DENALI_PHY_591_DATA */
+ 0x00000000, /* DENALI_PHY_592_DATA */
+ 0x00000000, /* DENALI_PHY_593_DATA */
+ 0x00000000, /* DENALI_PHY_594_DATA */
+ 0x00000000, /* DENALI_PHY_595_DATA */
+ 0x00000000, /* DENALI_PHY_596_DATA */
+ 0x00000000, /* DENALI_PHY_597_DATA */
+ 0x00000000, /* DENALI_PHY_598_DATA */
+ 0x00000000, /* DENALI_PHY_599_DATA */
+ 0x00000000, /* DENALI_PHY_600_DATA */
+ 0x00000000, /* DENALI_PHY_601_DATA */
+ 0x00000000, /* DENALI_PHY_602_DATA */
+ 0x00000000, /* DENALI_PHY_603_DATA */
+ 0x00000000, /* DENALI_PHY_604_DATA */
+ 0x00000000, /* DENALI_PHY_605_DATA */
+ 0x00000000, /* DENALI_PHY_606_DATA */
+ 0x00000000, /* DENALI_PHY_607_DATA */
+ 0x00000000, /* DENALI_PHY_608_DATA */
+ 0x00000000, /* DENALI_PHY_609_DATA */
+ 0x00000000, /* DENALI_PHY_610_DATA */
+ 0x00000000, /* DENALI_PHY_611_DATA */
+ 0x00000000, /* DENALI_PHY_612_DATA */
+ 0x00000000, /* DENALI_PHY_613_DATA */
+ 0x00000000, /* DENALI_PHY_614_DATA */
+ 0x00000000, /* DENALI_PHY_615_DATA */
+ 0x00000000, /* DENALI_PHY_616_DATA */
+ 0x00000000, /* DENALI_PHY_617_DATA */
+ 0x00000000, /* DENALI_PHY_618_DATA */
+ 0x00000000, /* DENALI_PHY_619_DATA */
+ 0x00000000, /* DENALI_PHY_620_DATA */
+ 0x00000000, /* DENALI_PHY_621_DATA */
+ 0x00000000, /* DENALI_PHY_622_DATA */
+ 0x00000000, /* DENALI_PHY_623_DATA */
+ 0x00000000, /* DENALI_PHY_624_DATA */
+ 0x00000000, /* DENALI_PHY_625_DATA */
+ 0x00000000, /* DENALI_PHY_626_DATA */
+ 0x00000000, /* DENALI_PHY_627_DATA */
+ 0x00000000, /* DENALI_PHY_628_DATA */
+ 0x00000000, /* DENALI_PHY_629_DATA */
+ 0x00000000, /* DENALI_PHY_630_DATA */
+ 0x00000000, /* DENALI_PHY_631_DATA */
+ 0x00000000, /* DENALI_PHY_632_DATA */
+ 0x00000000, /* DENALI_PHY_633_DATA */
+ 0x00000000, /* DENALI_PHY_634_DATA */
+ 0x00000000, /* DENALI_PHY_635_DATA */
+ 0x00000000, /* DENALI_PHY_636_DATA */
+ 0x00000000, /* DENALI_PHY_637_DATA */
+ 0x00000000, /* DENALI_PHY_638_DATA */
+ 0x00000000, /* DENALI_PHY_639_DATA */
+ 0x00000000, /* DENALI_PHY_640_DATA */
+ 0x00000000, /* DENALI_PHY_641_DATA */
+ 0x00000000, /* DENALI_PHY_642_DATA */
+ 0x00000000, /* DENALI_PHY_643_DATA */
+ 0x00000000, /* DENALI_PHY_644_DATA */
+ 0x00000000, /* DENALI_PHY_645_DATA */
+ 0x00000000, /* DENALI_PHY_646_DATA */
+ 0x00000002, /* DENALI_PHY_647_DATA */
+ 0x00000000, /* DENALI_PHY_648_DATA */
+ 0x00000000, /* DENALI_PHY_649_DATA */
+ 0x00000000, /* DENALI_PHY_650_DATA */
+ 0x00400320, /* DENALI_PHY_651_DATA */
+ 0x00000040, /* DENALI_PHY_652_DATA */
+ 0x00000000, /* DENALI_PHY_653_DATA */
+ 0x00000000, /* DENALI_PHY_654_DATA */
+ 0x00000000, /* DENALI_PHY_655_DATA */
+ 0x01000000, /* DENALI_PHY_656_DATA */
+ 0x00020003, /* DENALI_PHY_657_DATA */
+ 0x00000000, /* DENALI_PHY_658_DATA */
+ 0x00000000, /* DENALI_PHY_659_DATA */
+ 0x00000000, /* DENALI_PHY_660_DATA */
+ 0x0000002a, /* DENALI_PHY_661_DATA */
+ 0x00000015, /* DENALI_PHY_662_DATA */
+ 0x00000015, /* DENALI_PHY_663_DATA */
+ 0x0000002a, /* DENALI_PHY_664_DATA */
+ 0x00000033, /* DENALI_PHY_665_DATA */
+ 0x0000000c, /* DENALI_PHY_666_DATA */
+ 0x0000000c, /* DENALI_PHY_667_DATA */
+ 0x00000033, /* DENALI_PHY_668_DATA */
+ 0x00000000, /* DENALI_PHY_669_DATA */
+ 0x00000000, /* DENALI_PHY_670_DATA */
+ 0x00000000, /* DENALI_PHY_671_DATA */
+ 0x00030055, /* DENALI_PHY_672_DATA */
+ 0x03000300, /* DENALI_PHY_673_DATA */
+ 0x03000300, /* DENALI_PHY_674_DATA */
+ 0x00000300, /* DENALI_PHY_675_DATA */
+ 0x42080010, /* DENALI_PHY_676_DATA */
+ 0x00000003, /* DENALI_PHY_677_DATA */
+ 0x00000000, /* DENALI_PHY_678_DATA */
+ 0x00000000, /* DENALI_PHY_679_DATA */
+ 0x00000000, /* DENALI_PHY_680_DATA */
+ 0x00000000, /* DENALI_PHY_681_DATA */
+ 0x00000000, /* DENALI_PHY_682_DATA */
+ 0x00000000, /* DENALI_PHY_683_DATA */
+ 0x00000000, /* DENALI_PHY_684_DATA */
+ 0x00000000, /* DENALI_PHY_685_DATA */
+ 0x00000000, /* DENALI_PHY_686_DATA */
+ 0x00000000, /* DENALI_PHY_687_DATA */
+ 0x00000000, /* DENALI_PHY_688_DATA */
+ 0x00000000, /* DENALI_PHY_689_DATA */
+ 0x00000000, /* DENALI_PHY_690_DATA */
+ 0x00000000, /* DENALI_PHY_691_DATA */
+ 0x00000000, /* DENALI_PHY_692_DATA */
+ 0x00000000, /* DENALI_PHY_693_DATA */
+ 0x00000000, /* DENALI_PHY_694_DATA */
+ 0x00000000, /* DENALI_PHY_695_DATA */
+ 0x00000000, /* DENALI_PHY_696_DATA */
+ 0x00000000, /* DENALI_PHY_697_DATA */
+ 0x00000000, /* DENALI_PHY_698_DATA */
+ 0x00000000, /* DENALI_PHY_699_DATA */
+ 0x00000000, /* DENALI_PHY_700_DATA */
+ 0x00000000, /* DENALI_PHY_701_DATA */
+ 0x00000000, /* DENALI_PHY_702_DATA */
+ 0x00000000, /* DENALI_PHY_703_DATA */
+ 0x00000000, /* DENALI_PHY_704_DATA */
+ 0x00000000, /* DENALI_PHY_705_DATA */
+ 0x00000000, /* DENALI_PHY_706_DATA */
+ 0x00000000, /* DENALI_PHY_707_DATA */
+ 0x00000000, /* DENALI_PHY_708_DATA */
+ 0x00000000, /* DENALI_PHY_709_DATA */
+ 0x00000000, /* DENALI_PHY_710_DATA */
+ 0x00000000, /* DENALI_PHY_711_DATA */
+ 0x00000000, /* DENALI_PHY_712_DATA */
+ 0x00000000, /* DENALI_PHY_713_DATA */
+ 0x00000000, /* DENALI_PHY_714_DATA */
+ 0x00000000, /* DENALI_PHY_715_DATA */
+ 0x00000000, /* DENALI_PHY_716_DATA */
+ 0x00000000, /* DENALI_PHY_717_DATA */
+ 0x00000000, /* DENALI_PHY_718_DATA */
+ 0x00000000, /* DENALI_PHY_719_DATA */
+ 0x00000000, /* DENALI_PHY_720_DATA */
+ 0x00000000, /* DENALI_PHY_721_DATA */
+ 0x00000000, /* DENALI_PHY_722_DATA */
+ 0x00000000, /* DENALI_PHY_723_DATA */
+ 0x00000000, /* DENALI_PHY_724_DATA */
+ 0x00000000, /* DENALI_PHY_725_DATA */
+ 0x00000000, /* DENALI_PHY_726_DATA */
+ 0x00000000, /* DENALI_PHY_727_DATA */
+ 0x00000000, /* DENALI_PHY_728_DATA */
+ 0x00000000, /* DENALI_PHY_729_DATA */
+ 0x00000000, /* DENALI_PHY_730_DATA */
+ 0x00000000, /* DENALI_PHY_731_DATA */
+ 0x00000000, /* DENALI_PHY_732_DATA */
+ 0x00000000, /* DENALI_PHY_733_DATA */
+ 0x00000000, /* DENALI_PHY_734_DATA */
+ 0x00000000, /* DENALI_PHY_735_DATA */
+ 0x00000000, /* DENALI_PHY_736_DATA */
+ 0x00000000, /* DENALI_PHY_737_DATA */
+ 0x00000000, /* DENALI_PHY_738_DATA */
+ 0x00000000, /* DENALI_PHY_739_DATA */
+ 0x00000000, /* DENALI_PHY_740_DATA */
+ 0x00000000, /* DENALI_PHY_741_DATA */
+ 0x00000000, /* DENALI_PHY_742_DATA */
+ 0x00000000, /* DENALI_PHY_743_DATA */
+ 0x00000000, /* DENALI_PHY_744_DATA */
+ 0x00000000, /* DENALI_PHY_745_DATA */
+ 0x00000000, /* DENALI_PHY_746_DATA */
+ 0x00000000, /* DENALI_PHY_747_DATA */
+ 0x00000000, /* DENALI_PHY_748_DATA */
+ 0x00000000, /* DENALI_PHY_749_DATA */
+ 0x00000000, /* DENALI_PHY_750_DATA */
+ 0x00000000, /* DENALI_PHY_751_DATA */
+ 0x00000000, /* DENALI_PHY_752_DATA */
+ 0x00000000, /* DENALI_PHY_753_DATA */
+ 0x00000000, /* DENALI_PHY_754_DATA */
+ 0x00000000, /* DENALI_PHY_755_DATA */
+ 0x00000000, /* DENALI_PHY_756_DATA */
+ 0x00000000, /* DENALI_PHY_757_DATA */
+ 0x00000000, /* DENALI_PHY_758_DATA */
+ 0x00000000, /* DENALI_PHY_759_DATA */
+ 0x00000000, /* DENALI_PHY_760_DATA */
+ 0x00000000, /* DENALI_PHY_761_DATA */
+ 0x00000000, /* DENALI_PHY_762_DATA */
+ 0x00000000, /* DENALI_PHY_763_DATA */
+ 0x00000000, /* DENALI_PHY_764_DATA */
+ 0x00000000, /* DENALI_PHY_765_DATA */
+ 0x00000000, /* DENALI_PHY_766_DATA */
+ 0x00000000, /* DENALI_PHY_767_DATA */
+ 0x00000000, /* DENALI_PHY_768_DATA */
+ 0x00000000, /* DENALI_PHY_769_DATA */
+ 0x00000000, /* DENALI_PHY_770_DATA */
+ 0x00000000, /* DENALI_PHY_771_DATA */
+ 0x00000000, /* DENALI_PHY_772_DATA */
+ 0x00000000, /* DENALI_PHY_773_DATA */
+ 0x00000000, /* DENALI_PHY_774_DATA */
+ 0x00000002, /* DENALI_PHY_775_DATA */
+ 0x00000000, /* DENALI_PHY_776_DATA */
+ 0x00000000, /* DENALI_PHY_777_DATA */
+ 0x00000000, /* DENALI_PHY_778_DATA */
+ 0x00400320, /* DENALI_PHY_779_DATA */
+ 0x00000040, /* DENALI_PHY_780_DATA */
+ 0x00000000, /* DENALI_PHY_781_DATA */
+ 0x00000000, /* DENALI_PHY_782_DATA */
+ 0x00000000, /* DENALI_PHY_783_DATA */
+ 0x01000000, /* DENALI_PHY_784_DATA */
+ 0x00020003, /* DENALI_PHY_785_DATA */
+ 0x00000000, /* DENALI_PHY_786_DATA */
+ 0x00000000, /* DENALI_PHY_787_DATA */
+ 0x00000000, /* DENALI_PHY_788_DATA */
+ 0x0000002a, /* DENALI_PHY_789_DATA */
+ 0x00000015, /* DENALI_PHY_790_DATA */
+ 0x00000015, /* DENALI_PHY_791_DATA */
+ 0x0000002a, /* DENALI_PHY_792_DATA */
+ 0x00000033, /* DENALI_PHY_793_DATA */
+ 0x0000000c, /* DENALI_PHY_794_DATA */
+ 0x0000000c, /* DENALI_PHY_795_DATA */
+ 0x00000033, /* DENALI_PHY_796_DATA */
+ 0x1ee6b16a, /* DENALI_PHY_797_DATA */
+ 0x10000000, /* DENALI_PHY_798_DATA */
+ 0x00000000, /* DENALI_PHY_799_DATA */
+ 0x00030055, /* DENALI_PHY_800_DATA */
+ 0x03000300, /* DENALI_PHY_801_DATA */
+ 0x03000300, /* DENALI_PHY_802_DATA */
+ 0x00000300, /* DENALI_PHY_803_DATA */
+ 0x42080010, /* DENALI_PHY_804_DATA */
+ 0x00000003, /* DENALI_PHY_805_DATA */
+ 0x00000000, /* DENALI_PHY_806_DATA */
+ 0x00000000, /* DENALI_PHY_807_DATA */
+ 0x00000000, /* DENALI_PHY_808_DATA */
+ 0x00000000, /* DENALI_PHY_809_DATA */
+ 0x00000000, /* DENALI_PHY_810_DATA */
+ 0x00000000, /* DENALI_PHY_811_DATA */
+ 0x00000000, /* DENALI_PHY_812_DATA */
+ 0x00000000, /* DENALI_PHY_813_DATA */
+ 0x00000000, /* DENALI_PHY_814_DATA */
+ 0x00000000, /* DENALI_PHY_815_DATA */
+ 0x00000000, /* DENALI_PHY_816_DATA */
+ 0x00000000, /* DENALI_PHY_817_DATA */
+ 0x00000000, /* DENALI_PHY_818_DATA */
+ 0x00000000, /* DENALI_PHY_819_DATA */
+ 0x00000000, /* DENALI_PHY_820_DATA */
+ 0x00000000, /* DENALI_PHY_821_DATA */
+ 0x00000000, /* DENALI_PHY_822_DATA */
+ 0x00000000, /* DENALI_PHY_823_DATA */
+ 0x00000000, /* DENALI_PHY_824_DATA */
+ 0x00000000, /* DENALI_PHY_825_DATA */
+ 0x00000000, /* DENALI_PHY_826_DATA */
+ 0x00000000, /* DENALI_PHY_827_DATA */
+ 0x00000000, /* DENALI_PHY_828_DATA */
+ 0x00000000, /* DENALI_PHY_829_DATA */
+ 0x00000000, /* DENALI_PHY_830_DATA */
+ 0x00000000, /* DENALI_PHY_831_DATA */
+ 0x00000000, /* DENALI_PHY_832_DATA */
+ 0x00000000, /* DENALI_PHY_833_DATA */
+ 0x00000000, /* DENALI_PHY_834_DATA */
+ 0x00000000, /* DENALI_PHY_835_DATA */
+ 0x00000000, /* DENALI_PHY_836_DATA */
+ 0x00000000, /* DENALI_PHY_837_DATA */
+ 0x00000000, /* DENALI_PHY_838_DATA */
+ 0x00000000, /* DENALI_PHY_839_DATA */
+ 0x00000000, /* DENALI_PHY_840_DATA */
+ 0x00000000, /* DENALI_PHY_841_DATA */
+ 0x00000000, /* DENALI_PHY_842_DATA */
+ 0x00000000, /* DENALI_PHY_843_DATA */
+ 0x00000000, /* DENALI_PHY_844_DATA */
+ 0x00000000, /* DENALI_PHY_845_DATA */
+ 0x00000000, /* DENALI_PHY_846_DATA */
+ 0x00000000, /* DENALI_PHY_847_DATA */
+ 0x00000000, /* DENALI_PHY_848_DATA */
+ 0x00000000, /* DENALI_PHY_849_DATA */
+ 0x00000000, /* DENALI_PHY_850_DATA */
+ 0x00000000, /* DENALI_PHY_851_DATA */
+ 0x00000000, /* DENALI_PHY_852_DATA */
+ 0x00000000, /* DENALI_PHY_853_DATA */
+ 0x00000000, /* DENALI_PHY_854_DATA */
+ 0x00000000, /* DENALI_PHY_855_DATA */
+ 0x00000000, /* DENALI_PHY_856_DATA */
+ 0x00000000, /* DENALI_PHY_857_DATA */
+ 0x00000000, /* DENALI_PHY_858_DATA */
+ 0x00000000, /* DENALI_PHY_859_DATA */
+ 0x00000000, /* DENALI_PHY_860_DATA */
+ 0x00000000, /* DENALI_PHY_861_DATA */
+ 0x00000000, /* DENALI_PHY_862_DATA */
+ 0x00000000, /* DENALI_PHY_863_DATA */
+ 0x00000000, /* DENALI_PHY_864_DATA */
+ 0x00000000, /* DENALI_PHY_865_DATA */
+ 0x00000000, /* DENALI_PHY_866_DATA */
+ 0x00000000, /* DENALI_PHY_867_DATA */
+ 0x00000000, /* DENALI_PHY_868_DATA */
+ 0x00000000, /* DENALI_PHY_869_DATA */
+ 0x00000000, /* DENALI_PHY_870_DATA */
+ 0x00000000, /* DENALI_PHY_871_DATA */
+ 0x00000000, /* DENALI_PHY_872_DATA */
+ 0x00000000, /* DENALI_PHY_873_DATA */
+ 0x00000000, /* DENALI_PHY_874_DATA */
+ 0x00000000, /* DENALI_PHY_875_DATA */
+ 0x00000000, /* DENALI_PHY_876_DATA */
+ 0x00000000, /* DENALI_PHY_877_DATA */
+ 0x00000000, /* DENALI_PHY_878_DATA */
+ 0x00000000, /* DENALI_PHY_879_DATA */
+ 0x00000000, /* DENALI_PHY_880_DATA */
+ 0x00000000, /* DENALI_PHY_881_DATA */
+ 0x00000000, /* DENALI_PHY_882_DATA */
+ 0x00000000, /* DENALI_PHY_883_DATA */
+ 0x00000000, /* DENALI_PHY_884_DATA */
+ 0x00000000, /* DENALI_PHY_885_DATA */
+ 0x00000000, /* DENALI_PHY_886_DATA */
+ 0x00000000, /* DENALI_PHY_887_DATA */
+ 0x00000000, /* DENALI_PHY_888_DATA */
+ 0x00000000, /* DENALI_PHY_889_DATA */
+ 0x00000000, /* DENALI_PHY_890_DATA */
+ 0x00000000, /* DENALI_PHY_891_DATA */
+ 0x00000000, /* DENALI_PHY_892_DATA */
+ 0x00000000, /* DENALI_PHY_893_DATA */
+ 0x00000000, /* DENALI_PHY_894_DATA */
+ 0x00000000, /* DENALI_PHY_895_DATA */
+ 0x00000000, /* DENALI_PHY_896_DATA */
+ 0x00000000, /* DENALI_PHY_897_DATA */
+ 0x00000005, /* DENALI_PHY_898_DATA */
+ 0x04000f01, /* DENALI_PHY_899_DATA */
+ 0x00020040, /* DENALI_PHY_900_DATA */
+ 0x00020055, /* DENALI_PHY_901_DATA */
+ 0x00000000, /* DENALI_PHY_902_DATA */
+ 0x00000000, /* DENALI_PHY_903_DATA */
+ 0x00000000, /* DENALI_PHY_904_DATA */
+ 0x00000050, /* DENALI_PHY_905_DATA */
+ 0x00000000, /* DENALI_PHY_906_DATA */
+ 0x01010100, /* DENALI_PHY_907_DATA */
+ 0x00000600, /* DENALI_PHY_908_DATA */
+ 0x00000000, /* DENALI_PHY_909_DATA */
+ 0x00006400, /* DENALI_PHY_910_DATA */
+ 0x03221302, /* DENALI_PHY_911_DATA */
+ 0x00000000, /* DENALI_PHY_912_DATA */
+ 0x000d1f01, /* DENALI_PHY_913_DATA */
+ 0x0d1f0d1f, /* DENALI_PHY_914_DATA */
+ 0x0d1f0d1f, /* DENALI_PHY_915_DATA */
+ 0x00030003, /* DENALI_PHY_916_DATA */
+ 0x03000300, /* DENALI_PHY_917_DATA */
+ 0x00000300, /* DENALI_PHY_918_DATA */
+ 0x03221302, /* DENALI_PHY_919_DATA */
+ 0x00000000, /* DENALI_PHY_920_DATA */
+ 0x00000000, /* DENALI_PHY_921_DATA */
+ 0x01020000, /* DENALI_PHY_922_DATA */
+ 0x00000001, /* DENALI_PHY_923_DATA */
+ 0x00000411, /* DENALI_PHY_924_DATA */
+ 0x00000411, /* DENALI_PHY_925_DATA */
+ 0x00000040, /* DENALI_PHY_926_DATA */
+ 0x00000040, /* DENALI_PHY_927_DATA */
+ 0x00000411, /* DENALI_PHY_928_DATA */
+ 0x00000411, /* DENALI_PHY_929_DATA */
+ 0x00004410, /* DENALI_PHY_930_DATA */
+ 0x00004410, /* DENALI_PHY_931_DATA */
+ 0x00004410, /* DENALI_PHY_932_DATA */
+ 0x00004410, /* DENALI_PHY_933_DATA */
+ 0x00004410, /* DENALI_PHY_934_DATA */
+ 0x00000411, /* DENALI_PHY_935_DATA */
+ 0x00004410, /* DENALI_PHY_936_DATA */
+ 0x00000411, /* DENALI_PHY_937_DATA */
+ 0x00004410, /* DENALI_PHY_938_DATA */
+ 0x00000411, /* DENALI_PHY_939_DATA */
+ 0x00004410, /* DENALI_PHY_940_DATA */
+ 0x00000000, /* DENALI_PHY_941_DATA */
+ 0x00000000, /* DENALI_PHY_942_DATA */
+ 0x00000000, /* DENALI_PHY_943_DATA */
+ 0x64000000, /* DENALI_PHY_944_DATA */
+ 0x00000000, /* DENALI_PHY_945_DATA */
+ 0x00000000, /* DENALI_PHY_946_DATA */
+ 0x00000408, /* DENALI_PHY_947_DATA */
+ 0x00000000, /* DENALI_PHY_948_DATA */
+ 0x00000000, /* DENALI_PHY_949_DATA */
+ 0x00000000, /* DENALI_PHY_950_DATA */
+ 0x00000000, /* DENALI_PHY_951_DATA */
+ 0x00000000, /* DENALI_PHY_952_DATA */
+ 0x00000000, /* DENALI_PHY_953_DATA */
+ 0xe4000000, /* DENALI_PHY_954_DATA */
+ 0x00000000, /* DENALI_PHY_955_DATA */
+ 0x00000000, /* DENALI_PHY_956_DATA */
+ 0x01010000, /* DENALI_PHY_957_DATA */
+ 0x00000000 /* DENALI_PHY_958_DATA */
+ }
+ },
+},
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 82/92] ram: rk3399: Add LPPDDR4-400 timings inc
@ 2019-06-11 14:51 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: u-boot
LPDDR4 initialization start with at board selected frequency
and then it switches into 400MHz and 800MHz simultaneously to
make the proper sequence work on each channel with associated
training.
So, add LPDDR4-400 timings inc file in driver area so-that
these timings will take during LPDDR4 initialization phase.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
.../ram/rockchip/sdram-rk3399-lpddr4-400.inc | 1570 +++++++++++++++++
1 file changed, 1570 insertions(+)
create mode 100644 drivers/ram/rockchip/sdram-rk3399-lpddr4-400.inc
diff --git a/drivers/ram/rockchip/sdram-rk3399-lpddr4-400.inc b/drivers/ram/rockchip/sdram-rk3399-lpddr4-400.inc
new file mode 100644
index 0000000000..c50a03d9dd
--- /dev/null
+++ b/drivers/ram/rockchip/sdram-rk3399-lpddr4-400.inc
@@ -0,0 +1,1570 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd.
+ * (C) Copyright 2019 Amarula Solutions
+ */
+
+{
+ {
+ {
+ {
+ .rank = 0x2,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF,
+ .ddrconfig = 1,
+ },
+ {
+ .ddrtiminga0 = 0x80241d22,
+ .ddrtimingb0 = 0x15050f08,
+ .ddrtimingc0 = {
+ 0x00000602,
+ },
+ .devtodev0 = 0x00002122,
+ .ddrmode = {
+ 0x0000004c,
+ },
+ .agingx0 = 0x00000000,
+ }
+ },
+ {
+ {
+ .rank = 0x2,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF,
+ .ddrconfig = 1,
+ },
+ {
+ .ddrtiminga0 = 0x80241d22,
+ .ddrtimingb0 = 0x15050f08,
+ .ddrtimingc0 = {
+ 0x00000602,
+ },
+ .devtodev0 = 0x00002122,
+ .ddrmode = {
+ 0x0000004c,
+ },
+ .agingx0 = 0x00000000,
+ }
+ }
+ },
+ {
+ .ddr_freq = 400 * MHz,
+ .dramtype = LPDDR4,
+ .num_channels = 2,
+ .stride = 13,
+ .odt = 1,
+ },
+ {
+ {
+ 0x00000b00, /* DENALI_CTL_00_DATA */
+ 0x00000000, /* DENALI_CTL_01_DATA */
+ 0x00000000, /* DENALI_CTL_02_DATA */
+ 0x00000000, /* DENALI_CTL_03_DATA */
+ 0x00000000, /* DENALI_CTL_04_DATA */
+ 0x00013880, /* DENALI_CTL_05_DATA */
+ 0x000c3500, /* DENALI_CTL_06_DATA */
+ 0x00000005, /* DENALI_CTL_07_DATA */
+ 0x00000320, /* DENALI_CTL_08_DATA */
+ 0x00027100, /* DENALI_CTL_09_DATA */
+ 0x00186a00, /* DENALI_CTL_10_DATA */
+ 0x00000005, /* DENALI_CTL_11_DATA */
+ 0x00000640, /* DENALI_CTL_12_DATA */
+ 0x00002710, /* DENALI_CTL_13_DATA */
+ 0x000186a0, /* DENALI_CTL_14_DATA */
+ 0x00000005, /* DENALI_CTL_15_DATA */
+ 0x01000064, /* DENALI_CTL_16_DATA */
+ 0x00000000, /* DENALI_CTL_17_DATA */
+ 0x02020101, /* DENALI_CTL_18_DATA */
+ 0x00000102, /* DENALI_CTL_19_DATA */
+ 0x00000050, /* DENALI_CTL_20_DATA */
+ 0x000000c8, /* DENALI_CTL_21_DATA */
+ 0x00000000, /* DENALI_CTL_22_DATA */
+ 0x06140000, /* DENALI_CTL_23_DATA */
+ 0x00081c00, /* DENALI_CTL_24_DATA */
+ 0x0400040c, /* DENALI_CTL_25_DATA */
+ 0x19042008, /* DENALI_CTL_26_DATA */
+ 0x10080a11, /* DENALI_CTL_27_DATA */
+ 0x22310800, /* DENALI_CTL_28_DATA */
+ 0x00200f0a, /* DENALI_CTL_29_DATA */
+ 0x0a030704, /* DENALI_CTL_30_DATA */
+ 0x08000204, /* DENALI_CTL_31_DATA */
+ 0x00000a0a, /* DENALI_CTL_32_DATA */
+ 0x04006db0, /* DENALI_CTL_33_DATA */
+ 0x0a0a0804, /* DENALI_CTL_34_DATA */
+ 0x0600db60, /* DENALI_CTL_35_DATA */
+ 0x0a0a0806, /* DENALI_CTL_36_DATA */
+ 0x04000db6, /* DENALI_CTL_37_DATA */
+ 0x02030404, /* DENALI_CTL_38_DATA */
+ 0x0f0a0800, /* DENALI_CTL_39_DATA */
+ 0x08040411, /* DENALI_CTL_40_DATA */
+ 0x1400640a, /* DENALI_CTL_41_DATA */
+ 0x02010a0a, /* DENALI_CTL_42_DATA */
+ 0x00010001, /* DENALI_CTL_43_DATA */
+ 0x04082012, /* DENALI_CTL_44_DATA */
+ 0x00041109, /* DENALI_CTL_45_DATA */
+ 0x00000000, /* DENALI_CTL_46_DATA */
+ 0x03010000, /* DENALI_CTL_47_DATA */
+ 0x06100034, /* DENALI_CTL_48_DATA */
+ 0x0c280068, /* DENALI_CTL_49_DATA */
+ 0x00bb0007, /* DENALI_CTL_50_DATA */
+ 0x00000000, /* DENALI_CTL_51_DATA */
+ 0x00060003, /* DENALI_CTL_52_DATA */
+ 0x000a0003, /* DENALI_CTL_53_DATA */
+ 0x000a0014, /* DENALI_CTL_54_DATA */
+ 0x01000000, /* DENALI_CTL_55_DATA */
+ 0x030a0000, /* DENALI_CTL_56_DATA */
+ 0x0c000002, /* DENALI_CTL_57_DATA */
+ 0x00000103, /* DENALI_CTL_58_DATA */
+ 0x0003030a, /* DENALI_CTL_59_DATA */
+ 0x00060037, /* DENALI_CTL_60_DATA */
+ 0x0003006e, /* DENALI_CTL_61_DATA */
+ 0x05050007, /* DENALI_CTL_62_DATA */
+ 0x03020605, /* DENALI_CTL_63_DATA */
+ 0x06050301, /* DENALI_CTL_64_DATA */
+ 0x06020c05, /* DENALI_CTL_65_DATA */
+ 0x05050302, /* DENALI_CTL_66_DATA */
+ 0x03020305, /* DENALI_CTL_67_DATA */
+ 0x00000301, /* DENALI_CTL_68_DATA */
+ 0x00000301, /* DENALI_CTL_69_DATA */
+ 0x00000001, /* DENALI_CTL_70_DATA */
+ 0x00000000, /* DENALI_CTL_71_DATA */
+ 0x00000000, /* DENALI_CTL_72_DATA */
+ 0x01000000, /* DENALI_CTL_73_DATA */
+ 0x80104002, /* DENALI_CTL_74_DATA */
+ 0x00040003, /* DENALI_CTL_75_DATA */
+ 0x00040005, /* DENALI_CTL_76_DATA */
+ 0x00030000, /* DENALI_CTL_77_DATA */
+ 0x00050004, /* DENALI_CTL_78_DATA */
+ 0x00000004, /* DENALI_CTL_79_DATA */
+ 0x00040003, /* DENALI_CTL_80_DATA */
+ 0x00040005, /* DENALI_CTL_81_DATA */
+ 0x18400000, /* DENALI_CTL_82_DATA */
+ 0x00000c20, /* DENALI_CTL_83_DATA */
+ 0x185030a0, /* DENALI_CTL_84_DATA */
+ 0x02ec0000, /* DENALI_CTL_85_DATA */
+ 0x00000176, /* DENALI_CTL_86_DATA */
+ 0x00000000, /* DENALI_CTL_87_DATA */
+ 0x00000000, /* DENALI_CTL_88_DATA */
+ 0x00000000, /* DENALI_CTL_89_DATA */
+ 0x00000000, /* DENALI_CTL_90_DATA */
+ 0x00000000, /* DENALI_CTL_91_DATA */
+ 0x06030300, /* DENALI_CTL_92_DATA */
+ 0x00030303, /* DENALI_CTL_93_DATA */
+ 0x02030200, /* DENALI_CTL_94_DATA */
+ 0x00040703, /* DENALI_CTL_95_DATA */
+ 0x03020302, /* DENALI_CTL_96_DATA */
+ 0x02000407, /* DENALI_CTL_97_DATA */
+ 0x07030203, /* DENALI_CTL_98_DATA */
+ 0x00030f04, /* DENALI_CTL_99_DATA */
+ 0x00070004, /* DENALI_CTL_100_DATA */
+ 0x00000000, /* DENALI_CTL_101_DATA */
+ 0x00000000, /* DENALI_CTL_102_DATA */
+ 0x00000000, /* DENALI_CTL_103_DATA */
+ 0x00000000, /* DENALI_CTL_104_DATA */
+ 0x00000000, /* DENALI_CTL_105_DATA */
+ 0x00000000, /* DENALI_CTL_106_DATA */
+ 0x00000000, /* DENALI_CTL_107_DATA */
+ 0x00010000, /* DENALI_CTL_108_DATA */
+ 0x20040020, /* DENALI_CTL_109_DATA */
+ 0x00200400, /* DENALI_CTL_110_DATA */
+ 0x01000400, /* DENALI_CTL_111_DATA */
+ 0x00000b80, /* DENALI_CTL_112_DATA */
+ 0x00000000, /* DENALI_CTL_113_DATA */
+ 0x00000001, /* DENALI_CTL_114_DATA */
+ 0x00000002, /* DENALI_CTL_115_DATA */
+ 0x0000000e, /* DENALI_CTL_116_DATA */
+ 0x00000000, /* DENALI_CTL_117_DATA */
+ 0x00000000, /* DENALI_CTL_118_DATA */
+ 0x00000000, /* DENALI_CTL_119_DATA */
+ 0x00000000, /* DENALI_CTL_120_DATA */
+ 0x00000000, /* DENALI_CTL_121_DATA */
+ 0x00500000, /* DENALI_CTL_122_DATA */
+ 0x00640028, /* DENALI_CTL_123_DATA */
+ 0x00640404, /* DENALI_CTL_124_DATA */
+ 0x005000a0, /* DENALI_CTL_125_DATA */
+ 0x060600c8, /* DENALI_CTL_126_DATA */
+ 0x000a00c8, /* DENALI_CTL_127_DATA */
+ 0x000d0005, /* DENALI_CTL_128_DATA */
+ 0x000d0404, /* DENALI_CTL_129_DATA */
+ 0x00000000, /* DENALI_CTL_130_DATA */
+ 0x00000000, /* DENALI_CTL_131_DATA */
+ 0x00000000, /* DENALI_CTL_132_DATA */
+ 0x001400a3, /* DENALI_CTL_133_DATA */
+ 0x00e30009, /* DENALI_CTL_134_DATA */
+ 0x00120024, /* DENALI_CTL_135_DATA */
+ 0x00040063, /* DENALI_CTL_136_DATA */
+ 0x00000000, /* DENALI_CTL_137_DATA */
+ 0x00310031, /* DENALI_CTL_138_DATA */
+ 0x00000031, /* DENALI_CTL_139_DATA */
+ 0x004d0000, /* DENALI_CTL_140_DATA */
+ 0x004d004d, /* DENALI_CTL_141_DATA */
+ 0x004d0000, /* DENALI_CTL_142_DATA */
+ 0x004d004d, /* DENALI_CTL_143_DATA */
+ 0x00010101, /* DENALI_CTL_144_DATA */
+ 0x00000000, /* DENALI_CTL_145_DATA */
+ 0x00000000, /* DENALI_CTL_146_DATA */
+ 0x001400a3, /* DENALI_CTL_147_DATA */
+ 0x00e30009, /* DENALI_CTL_148_DATA */
+ 0x00120024, /* DENALI_CTL_149_DATA */
+ 0x00040063, /* DENALI_CTL_150_DATA */
+ 0x00000000, /* DENALI_CTL_151_DATA */
+ 0x00310031, /* DENALI_CTL_152_DATA */
+ 0x00000031, /* DENALI_CTL_153_DATA */
+ 0x004d0000, /* DENALI_CTL_154_DATA */
+ 0x004d004d, /* DENALI_CTL_155_DATA */
+ 0x004d0000, /* DENALI_CTL_156_DATA */
+ 0x004d004d, /* DENALI_CTL_157_DATA */
+ 0x00010101, /* DENALI_CTL_158_DATA */
+ 0x00000000, /* DENALI_CTL_159_DATA */
+ 0x00000000, /* DENALI_CTL_160_DATA */
+ 0x00000000, /* DENALI_CTL_161_DATA */
+ 0x00000001, /* DENALI_CTL_162_DATA */
+ 0x00000000, /* DENALI_CTL_163_DATA */
+ 0x18151100, /* DENALI_CTL_164_DATA */
+ 0x0000000c, /* DENALI_CTL_165_DATA */
+ 0x00000000, /* DENALI_CTL_166_DATA */
+ 0x00000000, /* DENALI_CTL_167_DATA */
+ 0x00000000, /* DENALI_CTL_168_DATA */
+ 0x00000000, /* DENALI_CTL_169_DATA */
+ 0x00000000, /* DENALI_CTL_170_DATA */
+ 0x00000000, /* DENALI_CTL_171_DATA */
+ 0x00000000, /* DENALI_CTL_172_DATA */
+ 0x00000000, /* DENALI_CTL_173_DATA */
+ 0x00000000, /* DENALI_CTL_174_DATA */
+ 0x00000000, /* DENALI_CTL_175_DATA */
+ 0x00000000, /* DENALI_CTL_176_DATA */
+ 0x00000000, /* DENALI_CTL_177_DATA */
+ 0x00000000, /* DENALI_CTL_178_DATA */
+ 0x00020003, /* DENALI_CTL_179_DATA */
+ 0x00400100, /* DENALI_CTL_180_DATA */
+ 0x000c0190, /* DENALI_CTL_181_DATA */
+ 0x01000200, /* DENALI_CTL_182_DATA */
+ 0x03200040, /* DENALI_CTL_183_DATA */
+ 0x00020018, /* DENALI_CTL_184_DATA */
+ 0x00400100, /* DENALI_CTL_185_DATA */
+ 0x00080032, /* DENALI_CTL_186_DATA */
+ 0x00140000, /* DENALI_CTL_187_DATA */
+ 0x00030028, /* DENALI_CTL_188_DATA */
+ 0x01010100, /* DENALI_CTL_189_DATA */
+ 0x02000202, /* DENALI_CTL_190_DATA */
+ 0x0b000002, /* DENALI_CTL_191_DATA */
+ 0x01000f0f, /* DENALI_CTL_192_DATA */
+ 0x00000000, /* DENALI_CTL_193_DATA */
+ 0x00000000, /* DENALI_CTL_194_DATA */
+ 0x00010003, /* DENALI_CTL_195_DATA */
+ 0x00000c03, /* DENALI_CTL_196_DATA */
+ 0x00040101, /* DENALI_CTL_197_DATA */
+ 0x04010100, /* DENALI_CTL_198_DATA */
+ 0x01000000, /* DENALI_CTL_199_DATA */
+ 0x02010000, /* DENALI_CTL_200_DATA */
+ 0x00000001, /* DENALI_CTL_201_DATA */
+ 0x00000000, /* DENALI_CTL_202_DATA */
+ 0x00000000, /* DENALI_CTL_203_DATA */
+ 0x00000000, /* DENALI_CTL_204_DATA */
+ 0x00000000, /* DENALI_CTL_205_DATA */
+ 0x00000000, /* DENALI_CTL_206_DATA */
+ 0x00000000, /* DENALI_CTL_207_DATA */
+ 0x00000000, /* DENALI_CTL_208_DATA */
+ 0x00000000, /* DENALI_CTL_209_DATA */
+ 0x00000000, /* DENALI_CTL_210_DATA */
+ 0x00010000, /* DENALI_CTL_211_DATA */
+ 0x00000001, /* DENALI_CTL_212_DATA */
+ 0x01010001, /* DENALI_CTL_213_DATA */
+ 0x05040001, /* DENALI_CTL_214_DATA */
+ 0x040a0703, /* DENALI_CTL_215_DATA */
+ 0x02080808, /* DENALI_CTL_216_DATA */
+ 0x020e000a, /* DENALI_CTL_217_DATA */
+ 0x020f010b, /* DENALI_CTL_218_DATA */
+ 0x000d0008, /* DENALI_CTL_219_DATA */
+ 0x00080b0a, /* DENALI_CTL_220_DATA */
+ 0x03000200, /* DENALI_CTL_221_DATA */
+ 0x00000100, /* DENALI_CTL_222_DATA */
+ 0x00000000, /* DENALI_CTL_223_DATA */
+ 0x00000000, /* DENALI_CTL_224_DATA */
+ 0x0d000001, /* DENALI_CTL_225_DATA */
+ 0x00000028, /* DENALI_CTL_226_DATA */
+ 0x00010000, /* DENALI_CTL_227_DATA */
+ 0x00000003, /* DENALI_CTL_228_DATA */
+ 0x00000000, /* DENALI_CTL_229_DATA */
+ 0x00000000, /* DENALI_CTL_230_DATA */
+ 0x00000000, /* DENALI_CTL_231_DATA */
+ 0x00000000, /* DENALI_CTL_232_DATA */
+ 0x00000000, /* DENALI_CTL_233_DATA */
+ 0x00000000, /* DENALI_CTL_234_DATA */
+ 0x00000000, /* DENALI_CTL_235_DATA */
+ 0x00000000, /* DENALI_CTL_236_DATA */
+ 0x00010100, /* DENALI_CTL_237_DATA */
+ 0x01000000, /* DENALI_CTL_238_DATA */
+ 0x00000001, /* DENALI_CTL_239_DATA */
+ 0x00000303, /* DENALI_CTL_240_DATA */
+ 0x00000000, /* DENALI_CTL_241_DATA */
+ 0x00000000, /* DENALI_CTL_242_DATA */
+ 0x00000000, /* DENALI_CTL_243_DATA */
+ 0x00000000, /* DENALI_CTL_244_DATA */
+ 0x00000000, /* DENALI_CTL_245_DATA */
+ 0x00000000, /* DENALI_CTL_246_DATA */
+ 0x00000000, /* DENALI_CTL_247_DATA */
+ 0x00000000, /* DENALI_CTL_248_DATA */
+ 0x00000000, /* DENALI_CTL_249_DATA */
+ 0x00000000, /* DENALI_CTL_250_DATA */
+ 0x00000000, /* DENALI_CTL_251_DATA */
+ 0x00000000, /* DENALI_CTL_252_DATA */
+ 0x00000000, /* DENALI_CTL_253_DATA */
+ 0x00000000, /* DENALI_CTL_254_DATA */
+ 0x00000000, /* DENALI_CTL_255_DATA */
+ 0x000556aa, /* DENALI_CTL_256_DATA */
+ 0x000aaaaa, /* DENALI_CTL_257_DATA */
+ 0x000aa955, /* DENALI_CTL_258_DATA */
+ 0x00055555, /* DENALI_CTL_259_DATA */
+ 0x000b3133, /* DENALI_CTL_260_DATA */
+ 0x0004cd33, /* DENALI_CTL_261_DATA */
+ 0x0004cecc, /* DENALI_CTL_262_DATA */
+ 0x000b32cc, /* DENALI_CTL_263_DATA */
+ 0x00010300, /* DENALI_CTL_264_DATA */
+ 0x03000100, /* DENALI_CTL_265_DATA */
+ 0x00000000, /* DENALI_CTL_266_DATA */
+ 0x00000000, /* DENALI_CTL_267_DATA */
+ 0x00000000, /* DENALI_CTL_268_DATA */
+ 0x00000000, /* DENALI_CTL_269_DATA */
+ 0x00000000, /* DENALI_CTL_270_DATA */
+ 0x00000000, /* DENALI_CTL_271_DATA */
+ 0x00000000, /* DENALI_CTL_272_DATA */
+ 0x00000000, /* DENALI_CTL_273_DATA */
+ 0x00ffff00, /* DENALI_CTL_274_DATA */
+ 0x1a160000, /* DENALI_CTL_275_DATA */
+ 0x08000012, /* DENALI_CTL_276_DATA */
+ 0x00000c20, /* DENALI_CTL_277_DATA */
+ 0x00000200, /* DENALI_CTL_278_DATA */
+ 0x00000200, /* DENALI_CTL_279_DATA */
+ 0x00000200, /* DENALI_CTL_280_DATA */
+ 0x00000200, /* DENALI_CTL_281_DATA */
+ 0x00000c20, /* DENALI_CTL_282_DATA */
+ 0x00007940, /* DENALI_CTL_283_DATA */
+ 0x18500409, /* DENALI_CTL_284_DATA */
+ 0x00000200, /* DENALI_CTL_285_DATA */
+ 0x00000200, /* DENALI_CTL_286_DATA */
+ 0x00000200, /* DENALI_CTL_287_DATA */
+ 0x00000200, /* DENALI_CTL_288_DATA */
+ 0x00001850, /* DENALI_CTL_289_DATA */
+ 0x0000f320, /* DENALI_CTL_290_DATA */
+ 0x0176060c, /* DENALI_CTL_291_DATA */
+ 0x00000200, /* DENALI_CTL_292_DATA */
+ 0x00000200, /* DENALI_CTL_293_DATA */
+ 0x00000200, /* DENALI_CTL_294_DATA */
+ 0x00000200, /* DENALI_CTL_295_DATA */
+ 0x00000176, /* DENALI_CTL_296_DATA */
+ 0x00000e9c, /* DENALI_CTL_297_DATA */
+ 0x02020205, /* DENALI_CTL_298_DATA */
+ 0x03030202, /* DENALI_CTL_299_DATA */
+ 0x00000018, /* DENALI_CTL_300_DATA */
+ 0x00000000, /* DENALI_CTL_301_DATA */
+ 0x00000000, /* DENALI_CTL_302_DATA */
+ 0x00001403, /* DENALI_CTL_303_DATA */
+ 0x00000000, /* DENALI_CTL_304_DATA */
+ 0x00000000, /* DENALI_CTL_305_DATA */
+ 0x00000000, /* DENALI_CTL_306_DATA */
+ 0x00030000, /* DENALI_CTL_307_DATA */
+ 0x000a001c, /* DENALI_CTL_308_DATA */
+ 0x000e0020, /* DENALI_CTL_309_DATA */
+ 0x00060018, /* DENALI_CTL_310_DATA */
+ 0x00000000, /* DENALI_CTL_311_DATA */
+ 0x00000000, /* DENALI_CTL_312_DATA */
+ 0x02000000, /* DENALI_CTL_313_DATA */
+ 0x00090305, /* DENALI_CTL_314_DATA */
+ 0x00050101, /* DENALI_CTL_315_DATA */
+ 0x00000000, /* DENALI_CTL_316_DATA */
+ 0x00000000, /* DENALI_CTL_317_DATA */
+ 0x00000000, /* DENALI_CTL_318_DATA */
+ 0x00000000, /* DENALI_CTL_319_DATA */
+ 0x00000000, /* DENALI_CTL_320_DATA */
+ 0x00000000, /* DENALI_CTL_321_DATA */
+ 0x00000000, /* DENALI_CTL_322_DATA */
+ 0x00000000, /* DENALI_CTL_323_DATA */
+ 0x01000001, /* DENALI_CTL_324_DATA */
+ 0x01010101, /* DENALI_CTL_325_DATA */
+ 0x01000101, /* DENALI_CTL_326_DATA */
+ 0x01000100, /* DENALI_CTL_327_DATA */
+ 0x00010001, /* DENALI_CTL_328_DATA */
+ 0x00010002, /* DENALI_CTL_329_DATA */
+ 0x00020100, /* DENALI_CTL_330_DATA */
+ 0x00000002 /* DENALI_CTL_331_DATA */
+ }
+ },
+ {
+ {
+ 0x00000b00, /* DENALI_PI_00_DATA */
+ 0x00000000, /* DENALI_PI_01_DATA */
+ 0x000002ec, /* DENALI_PI_02_DATA */
+ 0x00000176, /* DENALI_PI_03_DATA */
+ 0x000030a0, /* DENALI_PI_04_DATA */
+ 0x00001850, /* DENALI_PI_05_DATA */
+ 0x00001840, /* DENALI_PI_06_DATA */
+ 0x01760c20, /* DENALI_PI_07_DATA */
+ 0x00000200, /* DENALI_PI_08_DATA */
+ 0x00000200, /* DENALI_PI_09_DATA */
+ 0x00000200, /* DENALI_PI_10_DATA */
+ 0x00000200, /* DENALI_PI_11_DATA */
+ 0x00001850, /* DENALI_PI_12_DATA */
+ 0x00000200, /* DENALI_PI_13_DATA */
+ 0x00000200, /* DENALI_PI_14_DATA */
+ 0x00000200, /* DENALI_PI_15_DATA */
+ 0x00000200, /* DENALI_PI_16_DATA */
+ 0x00000c20, /* DENALI_PI_17_DATA */
+ 0x00000200, /* DENALI_PI_18_DATA */
+ 0x00000200, /* DENALI_PI_19_DATA */
+ 0x00000200, /* DENALI_PI_20_DATA */
+ 0x00000200, /* DENALI_PI_21_DATA */
+ 0x00010000, /* DENALI_PI_22_DATA */
+ 0x00000007, /* DENALI_PI_23_DATA */
+ 0x01000001, /* DENALI_PI_24_DATA */
+ 0x00000000, /* DENALI_PI_25_DATA */
+ 0x3fffffff, /* DENALI_PI_26_DATA */
+ 0x00000000, /* DENALI_PI_27_DATA */
+ 0x00000000, /* DENALI_PI_28_DATA */
+ 0x00000000, /* DENALI_PI_29_DATA */
+ 0x00000000, /* DENALI_PI_30_DATA */
+ 0x00000000, /* DENALI_PI_31_DATA */
+ 0x00000000, /* DENALI_PI_32_DATA */
+ 0x00000000, /* DENALI_PI_33_DATA */
+ 0x00000000, /* DENALI_PI_34_DATA */
+ 0x00000000, /* DENALI_PI_35_DATA */
+ 0x00000000, /* DENALI_PI_36_DATA */
+ 0x00000000, /* DENALI_PI_37_DATA */
+ 0x00000000, /* DENALI_PI_38_DATA */
+ 0x00000000, /* DENALI_PI_39_DATA */
+ 0x00000000, /* DENALI_PI_40_DATA */
+ 0x0f000101, /* DENALI_PI_41_DATA */
+ 0x082b3223, /* DENALI_PI_42_DATA */
+ 0x080c0004, /* DENALI_PI_43_DATA */
+ 0x00061c00, /* DENALI_PI_44_DATA */
+ 0x00000214, /* DENALI_PI_45_DATA */
+ 0x00bb0007, /* DENALI_PI_46_DATA */
+ 0x0c280068, /* DENALI_PI_47_DATA */
+ 0x06100034, /* DENALI_PI_48_DATA */
+ 0x00000500, /* DENALI_PI_49_DATA */
+ 0x00000000, /* DENALI_PI_50_DATA */
+ 0x00000000, /* DENALI_PI_51_DATA */
+ 0x00000000, /* DENALI_PI_52_DATA */
+ 0x00000000, /* DENALI_PI_53_DATA */
+ 0x00000000, /* DENALI_PI_54_DATA */
+ 0x00000000, /* DENALI_PI_55_DATA */
+ 0x00000000, /* DENALI_PI_56_DATA */
+ 0x00000000, /* DENALI_PI_57_DATA */
+ 0x04040100, /* DENALI_PI_58_DATA */
+ 0x0a000004, /* DENALI_PI_59_DATA */
+ 0x00000128, /* DENALI_PI_60_DATA */
+ 0x00000000, /* DENALI_PI_61_DATA */
+ 0x0003000f, /* DENALI_PI_62_DATA */
+ 0x00000018, /* DENALI_PI_63_DATA */
+ 0x00000000, /* DENALI_PI_64_DATA */
+ 0x00000000, /* DENALI_PI_65_DATA */
+ 0x00060002, /* DENALI_PI_66_DATA */
+ 0x00010001, /* DENALI_PI_67_DATA */
+ 0x00000101, /* DENALI_PI_68_DATA */
+ 0x00020001, /* DENALI_PI_69_DATA */
+ 0x00080004, /* DENALI_PI_70_DATA */
+ 0x00000000, /* DENALI_PI_71_DATA */
+ 0x05030000, /* DENALI_PI_72_DATA */
+ 0x070a0404, /* DENALI_PI_73_DATA */
+ 0x00000000, /* DENALI_PI_74_DATA */
+ 0x00000000, /* DENALI_PI_75_DATA */
+ 0x00000000, /* DENALI_PI_76_DATA */
+ 0x000f0f00, /* DENALI_PI_77_DATA */
+ 0x0000001e, /* DENALI_PI_78_DATA */
+ 0x00000000, /* DENALI_PI_79_DATA */
+ 0x01010300, /* DENALI_PI_80_DATA */
+ 0x00000000, /* DENALI_PI_81_DATA */
+ 0x00000000, /* DENALI_PI_82_DATA */
+ 0x01000000, /* DENALI_PI_83_DATA */
+ 0x00000101, /* DENALI_PI_84_DATA */
+ 0x55555a5a, /* DENALI_PI_85_DATA */
+ 0x55555a5a, /* DENALI_PI_86_DATA */
+ 0x55555a5a, /* DENALI_PI_87_DATA */
+ 0x55555a5a, /* DENALI_PI_88_DATA */
+ 0x0c050001, /* DENALI_PI_89_DATA */
+ 0x06020009, /* DENALI_PI_90_DATA */
+ 0x00010004, /* DENALI_PI_91_DATA */
+ 0x00000203, /* DENALI_PI_92_DATA */
+ 0x00030000, /* DENALI_PI_93_DATA */
+ 0x170f0000, /* DENALI_PI_94_DATA */
+ 0x00060018, /* DENALI_PI_95_DATA */
+ 0x000e0020, /* DENALI_PI_96_DATA */
+ 0x000a001c, /* DENALI_PI_97_DATA */
+ 0x00000000, /* DENALI_PI_98_DATA */
+ 0x00000000, /* DENALI_PI_99_DATA */
+ 0x00000100, /* DENALI_PI_100_DATA */
+ 0x140a0000, /* DENALI_PI_101_DATA */
+ 0x000d010a, /* DENALI_PI_102_DATA */
+ 0x0100c802, /* DENALI_PI_103_DATA */
+ 0x010a0064, /* DENALI_PI_104_DATA */
+ 0x000e0100, /* DENALI_PI_105_DATA */
+ 0x0100000e, /* DENALI_PI_106_DATA */
+ 0x00c900c9, /* DENALI_PI_107_DATA */
+ 0x00650100, /* DENALI_PI_108_DATA */
+ 0x1e1a0065, /* DENALI_PI_109_DATA */
+ 0x10010204, /* DENALI_PI_110_DATA */
+ 0x06070605, /* DENALI_PI_111_DATA */
+ 0x20000202, /* DENALI_PI_112_DATA */
+ 0x00201000, /* DENALI_PI_113_DATA */
+ 0x00201000, /* DENALI_PI_114_DATA */
+ 0x04041000, /* DENALI_PI_115_DATA */
+ 0x10020100, /* DENALI_PI_116_DATA */
+ 0x0003010c, /* DENALI_PI_117_DATA */
+ 0x004b004a, /* DENALI_PI_118_DATA */
+ 0x1a0f0000, /* DENALI_PI_119_DATA */
+ 0x0102041e, /* DENALI_PI_120_DATA */
+ 0x34000000, /* DENALI_PI_121_DATA */
+ 0x00000000, /* DENALI_PI_122_DATA */
+ 0x00000000, /* DENALI_PI_123_DATA */
+ 0x00010000, /* DENALI_PI_124_DATA */
+ 0x00000400, /* DENALI_PI_125_DATA */
+ 0x00310000, /* DENALI_PI_126_DATA */
+ 0x004d4d00, /* DENALI_PI_127_DATA */
+ 0x00120024, /* DENALI_PI_128_DATA */
+ 0x4d000031, /* DENALI_PI_129_DATA */
+ 0x0000144d, /* DENALI_PI_130_DATA */
+ 0x00310009, /* DENALI_PI_131_DATA */
+ 0x004d4d00, /* DENALI_PI_132_DATA */
+ 0x00000004, /* DENALI_PI_133_DATA */
+ 0x4d000031, /* DENALI_PI_134_DATA */
+ 0x0000244d, /* DENALI_PI_135_DATA */
+ 0x00310012, /* DENALI_PI_136_DATA */
+ 0x004d4d00, /* DENALI_PI_137_DATA */
+ 0x00090014, /* DENALI_PI_138_DATA */
+ 0x4d000031, /* DENALI_PI_139_DATA */
+ 0x0004004d, /* DENALI_PI_140_DATA */
+ 0x00310000, /* DENALI_PI_141_DATA */
+ 0x004d4d00, /* DENALI_PI_142_DATA */
+ 0x00120024, /* DENALI_PI_143_DATA */
+ 0x4d000031, /* DENALI_PI_144_DATA */
+ 0x0000144d, /* DENALI_PI_145_DATA */
+ 0x00310009, /* DENALI_PI_146_DATA */
+ 0x004d4d00, /* DENALI_PI_147_DATA */
+ 0x00000004, /* DENALI_PI_148_DATA */
+ 0x4d000031, /* DENALI_PI_149_DATA */
+ 0x0000244d, /* DENALI_PI_150_DATA */
+ 0x00310012, /* DENALI_PI_151_DATA */
+ 0x004d4d00, /* DENALI_PI_152_DATA */
+ 0x00090014, /* DENALI_PI_153_DATA */
+ 0x4d000031, /* DENALI_PI_154_DATA */
+ 0x0200004d, /* DENALI_PI_155_DATA */
+ 0x00c8000d, /* DENALI_PI_156_DATA */
+ 0x08080064, /* DENALI_PI_157_DATA */
+ 0x040a0404, /* DENALI_PI_158_DATA */
+ 0x03000d92, /* DENALI_PI_159_DATA */
+ 0x010a2001, /* DENALI_PI_160_DATA */
+ 0x0f11080a, /* DENALI_PI_161_DATA */
+ 0x0000110a, /* DENALI_PI_162_DATA */
+ 0x2200d92e, /* DENALI_PI_163_DATA */
+ 0x080c2003, /* DENALI_PI_164_DATA */
+ 0x0809080a, /* DENALI_PI_165_DATA */
+ 0x00000a0a, /* DENALI_PI_166_DATA */
+ 0x11006c97, /* DENALI_PI_167_DATA */
+ 0x040a2002, /* DENALI_PI_168_DATA */
+ 0x0200020a, /* DENALI_PI_169_DATA */
+ 0x02000200, /* DENALI_PI_170_DATA */
+ 0x02000200, /* DENALI_PI_171_DATA */
+ 0x02000200, /* DENALI_PI_172_DATA */
+ 0x02000200, /* DENALI_PI_173_DATA */
+ 0x00000000, /* DENALI_PI_174_DATA */
+ 0x00000000, /* DENALI_PI_175_DATA */
+ 0x00000000, /* DENALI_PI_176_DATA */
+ 0x00000000, /* DENALI_PI_177_DATA */
+ 0x00000000, /* DENALI_PI_178_DATA */
+ 0x00000000, /* DENALI_PI_179_DATA */
+ 0x00000000, /* DENALI_PI_180_DATA */
+ 0x00000000, /* DENALI_PI_181_DATA */
+ 0x00000000, /* DENALI_PI_182_DATA */
+ 0x00000000, /* DENALI_PI_183_DATA */
+ 0x00000000, /* DENALI_PI_184_DATA */
+ 0x00000000, /* DENALI_PI_185_DATA */
+ 0x01000400, /* DENALI_PI_186_DATA */
+ 0x00017600, /* DENALI_PI_187_DATA */
+ 0x00000e9c, /* DENALI_PI_188_DATA */
+ 0x00001850, /* DENALI_PI_189_DATA */
+ 0x0000f320, /* DENALI_PI_190_DATA */
+ 0x00000c20, /* DENALI_PI_191_DATA */
+ 0x00007940, /* DENALI_PI_192_DATA */
+ 0x08000000, /* DENALI_PI_193_DATA */
+ 0x00000100, /* DENALI_PI_194_DATA */
+ 0x00000000, /* DENALI_PI_195_DATA */
+ 0x00000000, /* DENALI_PI_196_DATA */
+ 0x00000000, /* DENALI_PI_197_DATA */
+ 0x00000000, /* DENALI_PI_198_DATA */
+ 0x00000002 /* DENALI_PI_199_DATA */
+ }
+ },
+ {
+ {
+ 0x76543210, /* DENALI_PHY_00_DATA */
+ 0x0004f008, /* DENALI_PHY_01_DATA */
+ 0x00020119, /* DENALI_PHY_02_DATA */
+ 0x00000000, /* DENALI_PHY_03_DATA */
+ 0x00000000, /* DENALI_PHY_04_DATA */
+ 0x00010000, /* DENALI_PHY_05_DATA */
+ 0x01665555, /* DENALI_PHY_06_DATA */
+ 0x03665555, /* DENALI_PHY_07_DATA */
+ 0x00010f00, /* DENALI_PHY_08_DATA */
+ 0x04000100, /* DENALI_PHY_09_DATA */
+ 0x00000001, /* DENALI_PHY_10_DATA */
+ 0x00170180, /* DENALI_PHY_11_DATA */
+ 0x00cc0201, /* DENALI_PHY_12_DATA */
+ 0x00030066, /* DENALI_PHY_13_DATA */
+ 0x00000000, /* DENALI_PHY_14_DATA */
+ 0x00000000, /* DENALI_PHY_15_DATA */
+ 0x00000000, /* DENALI_PHY_16_DATA */
+ 0x00000000, /* DENALI_PHY_17_DATA */
+ 0x00000000, /* DENALI_PHY_18_DATA */
+ 0x00000000, /* DENALI_PHY_19_DATA */
+ 0x00000000, /* DENALI_PHY_20_DATA */
+ 0x00000000, /* DENALI_PHY_21_DATA */
+ 0x04080000, /* DENALI_PHY_22_DATA */
+ 0x04080400, /* DENALI_PHY_23_DATA */
+ 0x30000000, /* DENALI_PHY_24_DATA */
+ 0x0c00c007, /* DENALI_PHY_25_DATA */
+ 0x00000100, /* DENALI_PHY_26_DATA */
+ 0x00000000, /* DENALI_PHY_27_DATA */
+ 0xfd02fe01, /* DENALI_PHY_28_DATA */
+ 0xf708fb04, /* DENALI_PHY_29_DATA */
+ 0xdf20ef10, /* DENALI_PHY_30_DATA */
+ 0x7f80bf40, /* DENALI_PHY_31_DATA */
+ 0x0001aaaa, /* DENALI_PHY_32_DATA */
+ 0x00000000, /* DENALI_PHY_33_DATA */
+ 0x00000000, /* DENALI_PHY_34_DATA */
+ 0x00000000, /* DENALI_PHY_35_DATA */
+ 0x00000000, /* DENALI_PHY_36_DATA */
+ 0x00000000, /* DENALI_PHY_37_DATA */
+ 0x00000000, /* DENALI_PHY_38_DATA */
+ 0x00000000, /* DENALI_PHY_39_DATA */
+ 0x00000000, /* DENALI_PHY_40_DATA */
+ 0x00000000, /* DENALI_PHY_41_DATA */
+ 0x00000000, /* DENALI_PHY_42_DATA */
+ 0x00000000, /* DENALI_PHY_43_DATA */
+ 0x00000000, /* DENALI_PHY_44_DATA */
+ 0x00000000, /* DENALI_PHY_45_DATA */
+ 0x00000000, /* DENALI_PHY_46_DATA */
+ 0x00000000, /* DENALI_PHY_47_DATA */
+ 0x00000000, /* DENALI_PHY_48_DATA */
+ 0x00000000, /* DENALI_PHY_49_DATA */
+ 0x00000000, /* DENALI_PHY_50_DATA */
+ 0x00000000, /* DENALI_PHY_51_DATA */
+ 0x00200000, /* DENALI_PHY_52_DATA */
+ 0x00000000, /* DENALI_PHY_53_DATA */
+ 0x00000000, /* DENALI_PHY_54_DATA */
+ 0x00000000, /* DENALI_PHY_55_DATA */
+ 0x00000000, /* DENALI_PHY_56_DATA */
+ 0x00000000, /* DENALI_PHY_57_DATA */
+ 0x00000000, /* DENALI_PHY_58_DATA */
+ 0x02800280, /* DENALI_PHY_59_DATA */
+ 0x02800280, /* DENALI_PHY_60_DATA */
+ 0x02800280, /* DENALI_PHY_61_DATA */
+ 0x02800280, /* DENALI_PHY_62_DATA */
+ 0x00000280, /* DENALI_PHY_63_DATA */
+ 0x00000000, /* DENALI_PHY_64_DATA */
+ 0x00000000, /* DENALI_PHY_65_DATA */
+ 0x00000000, /* DENALI_PHY_66_DATA */
+ 0x00000000, /* DENALI_PHY_67_DATA */
+ 0x00800000, /* DENALI_PHY_68_DATA */
+ 0x00800080, /* DENALI_PHY_69_DATA */
+ 0x00800080, /* DENALI_PHY_70_DATA */
+ 0x00800080, /* DENALI_PHY_71_DATA */
+ 0x00800080, /* DENALI_PHY_72_DATA */
+ 0x00800080, /* DENALI_PHY_73_DATA */
+ 0x00800080, /* DENALI_PHY_74_DATA */
+ 0x00800080, /* DENALI_PHY_75_DATA */
+ 0x00800080, /* DENALI_PHY_76_DATA */
+ 0x01190080, /* DENALI_PHY_77_DATA */
+ 0x00000001, /* DENALI_PHY_78_DATA */
+ 0x00000000, /* DENALI_PHY_79_DATA */
+ 0x00000000, /* DENALI_PHY_80_DATA */
+ 0x00000200, /* DENALI_PHY_81_DATA */
+ 0x00000000, /* DENALI_PHY_82_DATA */
+ 0x51315152, /* DENALI_PHY_83_DATA */
+ 0xc0003150, /* DENALI_PHY_84_DATA */
+ 0x010000c0, /* DENALI_PHY_85_DATA */
+ 0x00100000, /* DENALI_PHY_86_DATA */
+ 0x07044204, /* DENALI_PHY_87_DATA */
+ 0x000f0c18, /* DENALI_PHY_88_DATA */
+ 0x01000140, /* DENALI_PHY_89_DATA */
+ 0x00000c10, /* DENALI_PHY_90_DATA */
+ 0x00000000, /* DENALI_PHY_91_DATA */
+ 0x00000000, /* DENALI_PHY_92_DATA */
+ 0x00000000, /* DENALI_PHY_93_DATA */
+ 0x00000000, /* DENALI_PHY_94_DATA */
+ 0x00000000, /* DENALI_PHY_95_DATA */
+ 0x00000000, /* DENALI_PHY_96_DATA */
+ 0x00000000, /* DENALI_PHY_97_DATA */
+ 0x00000000, /* DENALI_PHY_98_DATA */
+ 0x00000000, /* DENALI_PHY_99_DATA */
+ 0x00000000, /* DENALI_PHY_100_DATA */
+ 0x00000000, /* DENALI_PHY_101_DATA */
+ 0x00000000, /* DENALI_PHY_102_DATA */
+ 0x00000000, /* DENALI_PHY_103_DATA */
+ 0x00000000, /* DENALI_PHY_104_DATA */
+ 0x00000000, /* DENALI_PHY_105_DATA */
+ 0x00000000, /* DENALI_PHY_106_DATA */
+ 0x00000000, /* DENALI_PHY_107_DATA */
+ 0x00000000, /* DENALI_PHY_108_DATA */
+ 0x00000000, /* DENALI_PHY_109_DATA */
+ 0x00000000, /* DENALI_PHY_110_DATA */
+ 0x00000000, /* DENALI_PHY_111_DATA */
+ 0x00000000, /* DENALI_PHY_112_DATA */
+ 0x00000000, /* DENALI_PHY_113_DATA */
+ 0x00000000, /* DENALI_PHY_114_DATA */
+ 0x00000000, /* DENALI_PHY_115_DATA */
+ 0x00000000, /* DENALI_PHY_116_DATA */
+ 0x00000000, /* DENALI_PHY_117_DATA */
+ 0x00000000, /* DENALI_PHY_118_DATA */
+ 0x00000000, /* DENALI_PHY_119_DATA */
+ 0x00000000, /* DENALI_PHY_120_DATA */
+ 0x00000000, /* DENALI_PHY_121_DATA */
+ 0x00000000, /* DENALI_PHY_122_DATA */
+ 0x00000000, /* DENALI_PHY_123_DATA */
+ 0x00000000, /* DENALI_PHY_124_DATA */
+ 0x00000000, /* DENALI_PHY_125_DATA */
+ 0x00000000, /* DENALI_PHY_126_DATA */
+ 0x00000000, /* DENALI_PHY_127_DATA */
+ 0x76543210, /* DENALI_PHY_128_DATA */
+ 0x0004f008, /* DENALI_PHY_129_DATA */
+ 0x00020119, /* DENALI_PHY_130_DATA */
+ 0x00000000, /* DENALI_PHY_131_DATA */
+ 0x00000000, /* DENALI_PHY_132_DATA */
+ 0x00010000, /* DENALI_PHY_133_DATA */
+ 0x01665555, /* DENALI_PHY_134_DATA */
+ 0x03665555, /* DENALI_PHY_135_DATA */
+ 0x00010f00, /* DENALI_PHY_136_DATA */
+ 0x04000100, /* DENALI_PHY_137_DATA */
+ 0x00000001, /* DENALI_PHY_138_DATA */
+ 0x00170180, /* DENALI_PHY_139_DATA */
+ 0x00cc0201, /* DENALI_PHY_140_DATA */
+ 0x00030066, /* DENALI_PHY_141_DATA */
+ 0x00000000, /* DENALI_PHY_142_DATA */
+ 0x00000000, /* DENALI_PHY_143_DATA */
+ 0x00000000, /* DENALI_PHY_144_DATA */
+ 0x00000000, /* DENALI_PHY_145_DATA */
+ 0x00000000, /* DENALI_PHY_146_DATA */
+ 0x00000000, /* DENALI_PHY_147_DATA */
+ 0x00000000, /* DENALI_PHY_148_DATA */
+ 0x00000000, /* DENALI_PHY_149_DATA */
+ 0x04080000, /* DENALI_PHY_150_DATA */
+ 0x04080400, /* DENALI_PHY_151_DATA */
+ 0x30000000, /* DENALI_PHY_152_DATA */
+ 0x0c00c007, /* DENALI_PHY_153_DATA */
+ 0x00000100, /* DENALI_PHY_154_DATA */
+ 0x00000000, /* DENALI_PHY_155_DATA */
+ 0xfd02fe01, /* DENALI_PHY_156_DATA */
+ 0xf708fb04, /* DENALI_PHY_157_DATA */
+ 0xdf20ef10, /* DENALI_PHY_158_DATA */
+ 0x7f80bf40, /* DENALI_PHY_159_DATA */
+ 0x0000aaaa, /* DENALI_PHY_160_DATA */
+ 0x00000000, /* DENALI_PHY_161_DATA */
+ 0x00000000, /* DENALI_PHY_162_DATA */
+ 0x00000000, /* DENALI_PHY_163_DATA */
+ 0x00000000, /* DENALI_PHY_164_DATA */
+ 0x00000000, /* DENALI_PHY_165_DATA */
+ 0x00000000, /* DENALI_PHY_166_DATA */
+ 0x00000000, /* DENALI_PHY_167_DATA */
+ 0x00000000, /* DENALI_PHY_168_DATA */
+ 0x00000000, /* DENALI_PHY_169_DATA */
+ 0x00000000, /* DENALI_PHY_170_DATA */
+ 0x00000000, /* DENALI_PHY_171_DATA */
+ 0x00000000, /* DENALI_PHY_172_DATA */
+ 0x00000000, /* DENALI_PHY_173_DATA */
+ 0x00000000, /* DENALI_PHY_174_DATA */
+ 0x00000000, /* DENALI_PHY_175_DATA */
+ 0x00000000, /* DENALI_PHY_176_DATA */
+ 0x00000000, /* DENALI_PHY_177_DATA */
+ 0x00000000, /* DENALI_PHY_178_DATA */
+ 0x00000000, /* DENALI_PHY_179_DATA */
+ 0x00200000, /* DENALI_PHY_180_DATA */
+ 0x00000000, /* DENALI_PHY_181_DATA */
+ 0x00000000, /* DENALI_PHY_182_DATA */
+ 0x00000000, /* DENALI_PHY_183_DATA */
+ 0x00000000, /* DENALI_PHY_184_DATA */
+ 0x00000000, /* DENALI_PHY_185_DATA */
+ 0x00000000, /* DENALI_PHY_186_DATA */
+ 0x02800280, /* DENALI_PHY_187_DATA */
+ 0x02800280, /* DENALI_PHY_188_DATA */
+ 0x02800280, /* DENALI_PHY_189_DATA */
+ 0x02800280, /* DENALI_PHY_190_DATA */
+ 0x00000280, /* DENALI_PHY_191_DATA */
+ 0x00000000, /* DENALI_PHY_192_DATA */
+ 0x00000000, /* DENALI_PHY_193_DATA */
+ 0x00000000, /* DENALI_PHY_194_DATA */
+ 0x00000000, /* DENALI_PHY_195_DATA */
+ 0x00800000, /* DENALI_PHY_196_DATA */
+ 0x00800080, /* DENALI_PHY_197_DATA */
+ 0x00800080, /* DENALI_PHY_198_DATA */
+ 0x00800080, /* DENALI_PHY_199_DATA */
+ 0x00800080, /* DENALI_PHY_200_DATA */
+ 0x00800080, /* DENALI_PHY_201_DATA */
+ 0x00800080, /* DENALI_PHY_202_DATA */
+ 0x00800080, /* DENALI_PHY_203_DATA */
+ 0x00800080, /* DENALI_PHY_204_DATA */
+ 0x01190080, /* DENALI_PHY_205_DATA */
+ 0x00000001, /* DENALI_PHY_206_DATA */
+ 0x00000000, /* DENALI_PHY_207_DATA */
+ 0x00000000, /* DENALI_PHY_208_DATA */
+ 0x00000200, /* DENALI_PHY_209_DATA */
+ 0x00000000, /* DENALI_PHY_210_DATA */
+ 0x51315152, /* DENALI_PHY_211_DATA */
+ 0xc0003150, /* DENALI_PHY_212_DATA */
+ 0x010000c0, /* DENALI_PHY_213_DATA */
+ 0x00100000, /* DENALI_PHY_214_DATA */
+ 0x07044204, /* DENALI_PHY_215_DATA */
+ 0x000f0c18, /* DENALI_PHY_216_DATA */
+ 0x01000140, /* DENALI_PHY_217_DATA */
+ 0x00000c10, /* DENALI_PHY_218_DATA */
+ 0x00000000, /* DENALI_PHY_219_DATA */
+ 0x00000000, /* DENALI_PHY_220_DATA */
+ 0x00000000, /* DENALI_PHY_221_DATA */
+ 0x00000000, /* DENALI_PHY_222_DATA */
+ 0x00000000, /* DENALI_PHY_223_DATA */
+ 0x00000000, /* DENALI_PHY_224_DATA */
+ 0x00000000, /* DENALI_PHY_225_DATA */
+ 0x00000000, /* DENALI_PHY_226_DATA */
+ 0x00000000, /* DENALI_PHY_227_DATA */
+ 0x00000000, /* DENALI_PHY_228_DATA */
+ 0x00000000, /* DENALI_PHY_229_DATA */
+ 0x00000000, /* DENALI_PHY_230_DATA */
+ 0x00000000, /* DENALI_PHY_231_DATA */
+ 0x00000000, /* DENALI_PHY_232_DATA */
+ 0x00000000, /* DENALI_PHY_233_DATA */
+ 0x00000000, /* DENALI_PHY_234_DATA */
+ 0x00000000, /* DENALI_PHY_235_DATA */
+ 0x00000000, /* DENALI_PHY_236_DATA */
+ 0x00000000, /* DENALI_PHY_237_DATA */
+ 0x00000000, /* DENALI_PHY_238_DATA */
+ 0x00000000, /* DENALI_PHY_239_DATA */
+ 0x00000000, /* DENALI_PHY_240_DATA */
+ 0x00000000, /* DENALI_PHY_241_DATA */
+ 0x00000000, /* DENALI_PHY_242_DATA */
+ 0x00000000, /* DENALI_PHY_243_DATA */
+ 0x00000000, /* DENALI_PHY_244_DATA */
+ 0x00000000, /* DENALI_PHY_245_DATA */
+ 0x00000000, /* DENALI_PHY_246_DATA */
+ 0x00000000, /* DENALI_PHY_247_DATA */
+ 0x00000000, /* DENALI_PHY_248_DATA */
+ 0x00000000, /* DENALI_PHY_249_DATA */
+ 0x00000000, /* DENALI_PHY_250_DATA */
+ 0x00000000, /* DENALI_PHY_251_DATA */
+ 0x00000000, /* DENALI_PHY_252_DATA */
+ 0x00000000, /* DENALI_PHY_253_DATA */
+ 0x00000000, /* DENALI_PHY_254_DATA */
+ 0x00000000, /* DENALI_PHY_255_DATA */
+ 0x76543210, /* DENALI_PHY_256_DATA */
+ 0x0004f008, /* DENALI_PHY_257_DATA */
+ 0x00020119, /* DENALI_PHY_258_DATA */
+ 0x00000000, /* DENALI_PHY_259_DATA */
+ 0x00000000, /* DENALI_PHY_260_DATA */
+ 0x00010000, /* DENALI_PHY_261_DATA */
+ 0x01665555, /* DENALI_PHY_262_DATA */
+ 0x03665555, /* DENALI_PHY_263_DATA */
+ 0x00010f00, /* DENALI_PHY_264_DATA */
+ 0x04000100, /* DENALI_PHY_265_DATA */
+ 0x00000001, /* DENALI_PHY_266_DATA */
+ 0x00170180, /* DENALI_PHY_267_DATA */
+ 0x00cc0201, /* DENALI_PHY_268_DATA */
+ 0x00030066, /* DENALI_PHY_269_DATA */
+ 0x00000000, /* DENALI_PHY_270_DATA */
+ 0x00000000, /* DENALI_PHY_271_DATA */
+ 0x00000000, /* DENALI_PHY_272_DATA */
+ 0x00000000, /* DENALI_PHY_273_DATA */
+ 0x00000000, /* DENALI_PHY_274_DATA */
+ 0x00000000, /* DENALI_PHY_275_DATA */
+ 0x00000000, /* DENALI_PHY_276_DATA */
+ 0x00000000, /* DENALI_PHY_277_DATA */
+ 0x04080000, /* DENALI_PHY_278_DATA */
+ 0x04080400, /* DENALI_PHY_279_DATA */
+ 0x30000000, /* DENALI_PHY_280_DATA */
+ 0x0c00c007, /* DENALI_PHY_281_DATA */
+ 0x00000100, /* DENALI_PHY_282_DATA */
+ 0x00000000, /* DENALI_PHY_283_DATA */
+ 0xfd02fe01, /* DENALI_PHY_284_DATA */
+ 0xf708fb04, /* DENALI_PHY_285_DATA */
+ 0xdf20ef10, /* DENALI_PHY_286_DATA */
+ 0x7f80bf40, /* DENALI_PHY_287_DATA */
+ 0x0001aaaa, /* DENALI_PHY_288_DATA */
+ 0x00000000, /* DENALI_PHY_289_DATA */
+ 0x00000000, /* DENALI_PHY_290_DATA */
+ 0x00000000, /* DENALI_PHY_291_DATA */
+ 0x00000000, /* DENALI_PHY_292_DATA */
+ 0x00000000, /* DENALI_PHY_293_DATA */
+ 0x00000000, /* DENALI_PHY_294_DATA */
+ 0x00000000, /* DENALI_PHY_295_DATA */
+ 0x00000000, /* DENALI_PHY_296_DATA */
+ 0x00000000, /* DENALI_PHY_297_DATA */
+ 0x00000000, /* DENALI_PHY_298_DATA */
+ 0x00000000, /* DENALI_PHY_299_DATA */
+ 0x00000000, /* DENALI_PHY_300_DATA */
+ 0x00000000, /* DENALI_PHY_301_DATA */
+ 0x00000000, /* DENALI_PHY_302_DATA */
+ 0x00000000, /* DENALI_PHY_303_DATA */
+ 0x00000000, /* DENALI_PHY_304_DATA */
+ 0x00000000, /* DENALI_PHY_305_DATA */
+ 0x00000000, /* DENALI_PHY_306_DATA */
+ 0x00000000, /* DENALI_PHY_307_DATA */
+ 0x00200000, /* DENALI_PHY_308_DATA */
+ 0x00000000, /* DENALI_PHY_309_DATA */
+ 0x00000000, /* DENALI_PHY_310_DATA */
+ 0x00000000, /* DENALI_PHY_311_DATA */
+ 0x00000000, /* DENALI_PHY_312_DATA */
+ 0x00000000, /* DENALI_PHY_313_DATA */
+ 0x00000000, /* DENALI_PHY_314_DATA */
+ 0x02800280, /* DENALI_PHY_315_DATA */
+ 0x02800280, /* DENALI_PHY_316_DATA */
+ 0x02800280, /* DENALI_PHY_317_DATA */
+ 0x02800280, /* DENALI_PHY_318_DATA */
+ 0x00000280, /* DENALI_PHY_319_DATA */
+ 0x00000000, /* DENALI_PHY_320_DATA */
+ 0x00000000, /* DENALI_PHY_321_DATA */
+ 0x00000000, /* DENALI_PHY_322_DATA */
+ 0x00000000, /* DENALI_PHY_323_DATA */
+ 0x00800000, /* DENALI_PHY_324_DATA */
+ 0x00800080, /* DENALI_PHY_325_DATA */
+ 0x00800080, /* DENALI_PHY_326_DATA */
+ 0x00800080, /* DENALI_PHY_327_DATA */
+ 0x00800080, /* DENALI_PHY_328_DATA */
+ 0x00800080, /* DENALI_PHY_329_DATA */
+ 0x00800080, /* DENALI_PHY_330_DATA */
+ 0x00800080, /* DENALI_PHY_331_DATA */
+ 0x00800080, /* DENALI_PHY_332_DATA */
+ 0x01190080, /* DENALI_PHY_333_DATA */
+ 0x00000001, /* DENALI_PHY_334_DATA */
+ 0x00000000, /* DENALI_PHY_335_DATA */
+ 0x00000000, /* DENALI_PHY_336_DATA */
+ 0x00000200, /* DENALI_PHY_337_DATA */
+ 0x00000000, /* DENALI_PHY_338_DATA */
+ 0x51315152, /* DENALI_PHY_339_DATA */
+ 0xc0003150, /* DENALI_PHY_340_DATA */
+ 0x010000c0, /* DENALI_PHY_341_DATA */
+ 0x00100000, /* DENALI_PHY_342_DATA */
+ 0x07044204, /* DENALI_PHY_343_DATA */
+ 0x000f0c18, /* DENALI_PHY_344_DATA */
+ 0x01000140, /* DENALI_PHY_345_DATA */
+ 0x00000c10, /* DENALI_PHY_346_DATA */
+ 0x00000000, /* DENALI_PHY_347_DATA */
+ 0x00000000, /* DENALI_PHY_348_DATA */
+ 0x00000000, /* DENALI_PHY_349_DATA */
+ 0x00000000, /* DENALI_PHY_350_DATA */
+ 0x00000000, /* DENALI_PHY_351_DATA */
+ 0x00000000, /* DENALI_PHY_352_DATA */
+ 0x00000000, /* DENALI_PHY_353_DATA */
+ 0x00000000, /* DENALI_PHY_354_DATA */
+ 0x00000000, /* DENALI_PHY_355_DATA */
+ 0x00000000, /* DENALI_PHY_356_DATA */
+ 0x00000000, /* DENALI_PHY_357_DATA */
+ 0x00000000, /* DENALI_PHY_358_DATA */
+ 0x00000000, /* DENALI_PHY_359_DATA */
+ 0x00000000, /* DENALI_PHY_360_DATA */
+ 0x00000000, /* DENALI_PHY_361_DATA */
+ 0x00000000, /* DENALI_PHY_362_DATA */
+ 0x00000000, /* DENALI_PHY_363_DATA */
+ 0x00000000, /* DENALI_PHY_364_DATA */
+ 0x00000000, /* DENALI_PHY_365_DATA */
+ 0x00000000, /* DENALI_PHY_366_DATA */
+ 0x00000000, /* DENALI_PHY_367_DATA */
+ 0x00000000, /* DENALI_PHY_368_DATA */
+ 0x00000000, /* DENALI_PHY_369_DATA */
+ 0x00000000, /* DENALI_PHY_370_DATA */
+ 0x00000000, /* DENALI_PHY_371_DATA */
+ 0x00000000, /* DENALI_PHY_372_DATA */
+ 0x00000000, /* DENALI_PHY_373_DATA */
+ 0x00000000, /* DENALI_PHY_374_DATA */
+ 0x00000000, /* DENALI_PHY_375_DATA */
+ 0x00000000, /* DENALI_PHY_376_DATA */
+ 0x00000000, /* DENALI_PHY_377_DATA */
+ 0x00000000, /* DENALI_PHY_378_DATA */
+ 0x00000000, /* DENALI_PHY_379_DATA */
+ 0x00000000, /* DENALI_PHY_380_DATA */
+ 0x00000000, /* DENALI_PHY_381_DATA */
+ 0x00000000, /* DENALI_PHY_382_DATA */
+ 0x00000000, /* DENALI_PHY_383_DATA */
+ 0x76543210, /* DENALI_PHY_384_DATA */
+ 0x0004f008, /* DENALI_PHY_385_DATA */
+ 0x00020119, /* DENALI_PHY_386_DATA */
+ 0x00000000, /* DENALI_PHY_387_DATA */
+ 0x00000000, /* DENALI_PHY_388_DATA */
+ 0x00010000, /* DENALI_PHY_389_DATA */
+ 0x01665555, /* DENALI_PHY_390_DATA */
+ 0x03665555, /* DENALI_PHY_391_DATA */
+ 0x00010f00, /* DENALI_PHY_392_DATA */
+ 0x04000100, /* DENALI_PHY_393_DATA */
+ 0x00000001, /* DENALI_PHY_394_DATA */
+ 0x00170180, /* DENALI_PHY_395_DATA */
+ 0x00cc0201, /* DENALI_PHY_396_DATA */
+ 0x00030066, /* DENALI_PHY_397_DATA */
+ 0x00000000, /* DENALI_PHY_398_DATA */
+ 0x00000000, /* DENALI_PHY_399_DATA */
+ 0x00000000, /* DENALI_PHY_400_DATA */
+ 0x00000000, /* DENALI_PHY_401_DATA */
+ 0x00000000, /* DENALI_PHY_402_DATA */
+ 0x00000000, /* DENALI_PHY_403_DATA */
+ 0x00000000, /* DENALI_PHY_404_DATA */
+ 0x00000000, /* DENALI_PHY_405_DATA */
+ 0x04080000, /* DENALI_PHY_406_DATA */
+ 0x04080400, /* DENALI_PHY_407_DATA */
+ 0x30000000, /* DENALI_PHY_408_DATA */
+ 0x0c00c007, /* DENALI_PHY_409_DATA */
+ 0x00000100, /* DENALI_PHY_410_DATA */
+ 0x00000000, /* DENALI_PHY_411_DATA */
+ 0xfd02fe01, /* DENALI_PHY_412_DATA */
+ 0xf708fb04, /* DENALI_PHY_413_DATA */
+ 0xdf20ef10, /* DENALI_PHY_414_DATA */
+ 0x7f80bf40, /* DENALI_PHY_415_DATA */
+ 0x0000aaaa, /* DENALI_PHY_416_DATA */
+ 0x00000000, /* DENALI_PHY_417_DATA */
+ 0x00000000, /* DENALI_PHY_418_DATA */
+ 0x00000000, /* DENALI_PHY_419_DATA */
+ 0x00000000, /* DENALI_PHY_420_DATA */
+ 0x00000000, /* DENALI_PHY_421_DATA */
+ 0x00000000, /* DENALI_PHY_422_DATA */
+ 0x00000000, /* DENALI_PHY_423_DATA */
+ 0x00000000, /* DENALI_PHY_424_DATA */
+ 0x00000000, /* DENALI_PHY_425_DATA */
+ 0x00000000, /* DENALI_PHY_426_DATA */
+ 0x00000000, /* DENALI_PHY_427_DATA */
+ 0x00000000, /* DENALI_PHY_428_DATA */
+ 0x00000000, /* DENALI_PHY_429_DATA */
+ 0x00000000, /* DENALI_PHY_430_DATA */
+ 0x00000000, /* DENALI_PHY_431_DATA */
+ 0x00000000, /* DENALI_PHY_432_DATA */
+ 0x00000000, /* DENALI_PHY_433_DATA */
+ 0x00000000, /* DENALI_PHY_434_DATA */
+ 0x00000000, /* DENALI_PHY_435_DATA */
+ 0x00200000, /* DENALI_PHY_436_DATA */
+ 0x00000000, /* DENALI_PHY_437_DATA */
+ 0x00000000, /* DENALI_PHY_438_DATA */
+ 0x00000000, /* DENALI_PHY_439_DATA */
+ 0x00000000, /* DENALI_PHY_440_DATA */
+ 0x00000000, /* DENALI_PHY_441_DATA */
+ 0x00000000, /* DENALI_PHY_442_DATA */
+ 0x02800280, /* DENALI_PHY_443_DATA */
+ 0x02800280, /* DENALI_PHY_444_DATA */
+ 0x02800280, /* DENALI_PHY_445_DATA */
+ 0x02800280, /* DENALI_PHY_446_DATA */
+ 0x00000280, /* DENALI_PHY_447_DATA */
+ 0x00000000, /* DENALI_PHY_448_DATA */
+ 0x00000000, /* DENALI_PHY_449_DATA */
+ 0x00000000, /* DENALI_PHY_450_DATA */
+ 0x00000000, /* DENALI_PHY_451_DATA */
+ 0x00800000, /* DENALI_PHY_452_DATA */
+ 0x00800080, /* DENALI_PHY_453_DATA */
+ 0x00800080, /* DENALI_PHY_454_DATA */
+ 0x00800080, /* DENALI_PHY_455_DATA */
+ 0x00800080, /* DENALI_PHY_456_DATA */
+ 0x00800080, /* DENALI_PHY_457_DATA */
+ 0x00800080, /* DENALI_PHY_458_DATA */
+ 0x00800080, /* DENALI_PHY_459_DATA */
+ 0x00800080, /* DENALI_PHY_460_DATA */
+ 0x01190080, /* DENALI_PHY_461_DATA */
+ 0x00000001, /* DENALI_PHY_462_DATA */
+ 0x00000000, /* DENALI_PHY_463_DATA */
+ 0x00000000, /* DENALI_PHY_464_DATA */
+ 0x00000200, /* DENALI_PHY_465_DATA */
+ 0x00000000, /* DENALI_PHY_466_DATA */
+ 0x51315152, /* DENALI_PHY_467_DATA */
+ 0xc0003150, /* DENALI_PHY_468_DATA */
+ 0x010000c0, /* DENALI_PHY_469_DATA */
+ 0x00100000, /* DENALI_PHY_470_DATA */
+ 0x07044204, /* DENALI_PHY_471_DATA */
+ 0x000f0c18, /* DENALI_PHY_472_DATA */
+ 0x01000140, /* DENALI_PHY_473_DATA */
+ 0x00000c10, /* DENALI_PHY_474_DATA */
+ 0x00000000, /* DENALI_PHY_475_DATA */
+ 0x00000000, /* DENALI_PHY_476_DATA */
+ 0x00000000, /* DENALI_PHY_477_DATA */
+ 0x00000000, /* DENALI_PHY_478_DATA */
+ 0x00000000, /* DENALI_PHY_479_DATA */
+ 0x00000000, /* DENALI_PHY_480_DATA */
+ 0x00000000, /* DENALI_PHY_481_DATA */
+ 0x00000000, /* DENALI_PHY_482_DATA */
+ 0x00000000, /* DENALI_PHY_483_DATA */
+ 0x00000000, /* DENALI_PHY_484_DATA */
+ 0x00000000, /* DENALI_PHY_485_DATA */
+ 0x00000000, /* DENALI_PHY_486_DATA */
+ 0x00000000, /* DENALI_PHY_487_DATA */
+ 0x00000000, /* DENALI_PHY_488_DATA */
+ 0x00000000, /* DENALI_PHY_489_DATA */
+ 0x00000000, /* DENALI_PHY_490_DATA */
+ 0x00000000, /* DENALI_PHY_491_DATA */
+ 0x00000000, /* DENALI_PHY_492_DATA */
+ 0x00000000, /* DENALI_PHY_493_DATA */
+ 0x00000000, /* DENALI_PHY_494_DATA */
+ 0x00000000, /* DENALI_PHY_495_DATA */
+ 0x00000000, /* DENALI_PHY_496_DATA */
+ 0x00000000, /* DENALI_PHY_497_DATA */
+ 0x00000000, /* DENALI_PHY_498_DATA */
+ 0x00000000, /* DENALI_PHY_499_DATA */
+ 0x00000000, /* DENALI_PHY_500_DATA */
+ 0x00000000, /* DENALI_PHY_501_DATA */
+ 0x00000000, /* DENALI_PHY_502_DATA */
+ 0x00000000, /* DENALI_PHY_503_DATA */
+ 0x00000000, /* DENALI_PHY_504_DATA */
+ 0x00000000, /* DENALI_PHY_505_DATA */
+ 0x00000000, /* DENALI_PHY_506_DATA */
+ 0x00000000, /* DENALI_PHY_507_DATA */
+ 0x00000000, /* DENALI_PHY_508_DATA */
+ 0x00000000, /* DENALI_PHY_509_DATA */
+ 0x00000000, /* DENALI_PHY_510_DATA */
+ 0x00000000, /* DENALI_PHY_511_DATA */
+ 0x00000000, /* DENALI_PHY_512_DATA */
+ 0x00000000, /* DENALI_PHY_513_DATA */
+ 0x00000000, /* DENALI_PHY_514_DATA */
+ 0x00000000, /* DENALI_PHY_515_DATA */
+ 0x00000000, /* DENALI_PHY_516_DATA */
+ 0x00000000, /* DENALI_PHY_517_DATA */
+ 0x00000000, /* DENALI_PHY_518_DATA */
+ 0x00000002, /* DENALI_PHY_519_DATA */
+ 0x00000000, /* DENALI_PHY_520_DATA */
+ 0x00000000, /* DENALI_PHY_521_DATA */
+ 0x00000000, /* DENALI_PHY_522_DATA */
+ 0x00400320, /* DENALI_PHY_523_DATA */
+ 0x00000040, /* DENALI_PHY_524_DATA */
+ 0x00dcba98, /* DENALI_PHY_525_DATA */
+ 0x00000000, /* DENALI_PHY_526_DATA */
+ 0x00dcba98, /* DENALI_PHY_527_DATA */
+ 0x01000000, /* DENALI_PHY_528_DATA */
+ 0x00020003, /* DENALI_PHY_529_DATA */
+ 0x00000000, /* DENALI_PHY_530_DATA */
+ 0x00000000, /* DENALI_PHY_531_DATA */
+ 0x00000000, /* DENALI_PHY_532_DATA */
+ 0x0000002a, /* DENALI_PHY_533_DATA */
+ 0x00000015, /* DENALI_PHY_534_DATA */
+ 0x00000015, /* DENALI_PHY_535_DATA */
+ 0x0000002a, /* DENALI_PHY_536_DATA */
+ 0x00000033, /* DENALI_PHY_537_DATA */
+ 0x0000000c, /* DENALI_PHY_538_DATA */
+ 0x0000000c, /* DENALI_PHY_539_DATA */
+ 0x00000033, /* DENALI_PHY_540_DATA */
+ 0x0a418820, /* DENALI_PHY_541_DATA */
+ 0x003f0000, /* DENALI_PHY_542_DATA */
+ 0x0000003f, /* DENALI_PHY_543_DATA */
+ 0x00030055, /* DENALI_PHY_544_DATA */
+ 0x03000300, /* DENALI_PHY_545_DATA */
+ 0x03000300, /* DENALI_PHY_546_DATA */
+ 0x00000300, /* DENALI_PHY_547_DATA */
+ 0x42080010, /* DENALI_PHY_548_DATA */
+ 0x00000003, /* DENALI_PHY_549_DATA */
+ 0x00000000, /* DENALI_PHY_550_DATA */
+ 0x00000000, /* DENALI_PHY_551_DATA */
+ 0x00000000, /* DENALI_PHY_552_DATA */
+ 0x00000000, /* DENALI_PHY_553_DATA */
+ 0x00000000, /* DENALI_PHY_554_DATA */
+ 0x00000000, /* DENALI_PHY_555_DATA */
+ 0x00000000, /* DENALI_PHY_556_DATA */
+ 0x00000000, /* DENALI_PHY_557_DATA */
+ 0x00000000, /* DENALI_PHY_558_DATA */
+ 0x00000000, /* DENALI_PHY_559_DATA */
+ 0x00000000, /* DENALI_PHY_560_DATA */
+ 0x00000000, /* DENALI_PHY_561_DATA */
+ 0x00000000, /* DENALI_PHY_562_DATA */
+ 0x00000000, /* DENALI_PHY_563_DATA */
+ 0x00000000, /* DENALI_PHY_564_DATA */
+ 0x00000000, /* DENALI_PHY_565_DATA */
+ 0x00000000, /* DENALI_PHY_566_DATA */
+ 0x00000000, /* DENALI_PHY_567_DATA */
+ 0x00000000, /* DENALI_PHY_568_DATA */
+ 0x00000000, /* DENALI_PHY_569_DATA */
+ 0x00000000, /* DENALI_PHY_570_DATA */
+ 0x00000000, /* DENALI_PHY_571_DATA */
+ 0x00000000, /* DENALI_PHY_572_DATA */
+ 0x00000000, /* DENALI_PHY_573_DATA */
+ 0x00000000, /* DENALI_PHY_574_DATA */
+ 0x00000000, /* DENALI_PHY_575_DATA */
+ 0x00000000, /* DENALI_PHY_576_DATA */
+ 0x00000000, /* DENALI_PHY_577_DATA */
+ 0x00000000, /* DENALI_PHY_578_DATA */
+ 0x00000000, /* DENALI_PHY_579_DATA */
+ 0x00000000, /* DENALI_PHY_580_DATA */
+ 0x00000000, /* DENALI_PHY_581_DATA */
+ 0x00000000, /* DENALI_PHY_582_DATA */
+ 0x00000000, /* DENALI_PHY_583_DATA */
+ 0x00000000, /* DENALI_PHY_584_DATA */
+ 0x00000000, /* DENALI_PHY_585_DATA */
+ 0x00000000, /* DENALI_PHY_586_DATA */
+ 0x00000000, /* DENALI_PHY_587_DATA */
+ 0x00000000, /* DENALI_PHY_588_DATA */
+ 0x00000000, /* DENALI_PHY_589_DATA */
+ 0x00000000, /* DENALI_PHY_590_DATA */
+ 0x00000000, /* DENALI_PHY_591_DATA */
+ 0x00000000, /* DENALI_PHY_592_DATA */
+ 0x00000000, /* DENALI_PHY_593_DATA */
+ 0x00000000, /* DENALI_PHY_594_DATA */
+ 0x00000000, /* DENALI_PHY_595_DATA */
+ 0x00000000, /* DENALI_PHY_596_DATA */
+ 0x00000000, /* DENALI_PHY_597_DATA */
+ 0x00000000, /* DENALI_PHY_598_DATA */
+ 0x00000000, /* DENALI_PHY_599_DATA */
+ 0x00000000, /* DENALI_PHY_600_DATA */
+ 0x00000000, /* DENALI_PHY_601_DATA */
+ 0x00000000, /* DENALI_PHY_602_DATA */
+ 0x00000000, /* DENALI_PHY_603_DATA */
+ 0x00000000, /* DENALI_PHY_604_DATA */
+ 0x00000000, /* DENALI_PHY_605_DATA */
+ 0x00000000, /* DENALI_PHY_606_DATA */
+ 0x00000000, /* DENALI_PHY_607_DATA */
+ 0x00000000, /* DENALI_PHY_608_DATA */
+ 0x00000000, /* DENALI_PHY_609_DATA */
+ 0x00000000, /* DENALI_PHY_610_DATA */
+ 0x00000000, /* DENALI_PHY_611_DATA */
+ 0x00000000, /* DENALI_PHY_612_DATA */
+ 0x00000000, /* DENALI_PHY_613_DATA */
+ 0x00000000, /* DENALI_PHY_614_DATA */
+ 0x00000000, /* DENALI_PHY_615_DATA */
+ 0x00000000, /* DENALI_PHY_616_DATA */
+ 0x00000000, /* DENALI_PHY_617_DATA */
+ 0x00000000, /* DENALI_PHY_618_DATA */
+ 0x00000000, /* DENALI_PHY_619_DATA */
+ 0x00000000, /* DENALI_PHY_620_DATA */
+ 0x00000000, /* DENALI_PHY_621_DATA */
+ 0x00000000, /* DENALI_PHY_622_DATA */
+ 0x00000000, /* DENALI_PHY_623_DATA */
+ 0x00000000, /* DENALI_PHY_624_DATA */
+ 0x00000000, /* DENALI_PHY_625_DATA */
+ 0x00000000, /* DENALI_PHY_626_DATA */
+ 0x00000000, /* DENALI_PHY_627_DATA */
+ 0x00000000, /* DENALI_PHY_628_DATA */
+ 0x00000000, /* DENALI_PHY_629_DATA */
+ 0x00000000, /* DENALI_PHY_630_DATA */
+ 0x00000000, /* DENALI_PHY_631_DATA */
+ 0x00000000, /* DENALI_PHY_632_DATA */
+ 0x00000000, /* DENALI_PHY_633_DATA */
+ 0x00000000, /* DENALI_PHY_634_DATA */
+ 0x00000000, /* DENALI_PHY_635_DATA */
+ 0x00000000, /* DENALI_PHY_636_DATA */
+ 0x00000000, /* DENALI_PHY_637_DATA */
+ 0x00000000, /* DENALI_PHY_638_DATA */
+ 0x00000000, /* DENALI_PHY_639_DATA */
+ 0x00000000, /* DENALI_PHY_640_DATA */
+ 0x00000000, /* DENALI_PHY_641_DATA */
+ 0x00000000, /* DENALI_PHY_642_DATA */
+ 0x00000000, /* DENALI_PHY_643_DATA */
+ 0x00000000, /* DENALI_PHY_644_DATA */
+ 0x00000000, /* DENALI_PHY_645_DATA */
+ 0x00000000, /* DENALI_PHY_646_DATA */
+ 0x00000002, /* DENALI_PHY_647_DATA */
+ 0x00000000, /* DENALI_PHY_648_DATA */
+ 0x00000000, /* DENALI_PHY_649_DATA */
+ 0x00000000, /* DENALI_PHY_650_DATA */
+ 0x00400320, /* DENALI_PHY_651_DATA */
+ 0x00000040, /* DENALI_PHY_652_DATA */
+ 0x00000000, /* DENALI_PHY_653_DATA */
+ 0x00000000, /* DENALI_PHY_654_DATA */
+ 0x00000000, /* DENALI_PHY_655_DATA */
+ 0x01000000, /* DENALI_PHY_656_DATA */
+ 0x00020003, /* DENALI_PHY_657_DATA */
+ 0x00000000, /* DENALI_PHY_658_DATA */
+ 0x00000000, /* DENALI_PHY_659_DATA */
+ 0x00000000, /* DENALI_PHY_660_DATA */
+ 0x0000002a, /* DENALI_PHY_661_DATA */
+ 0x00000015, /* DENALI_PHY_662_DATA */
+ 0x00000015, /* DENALI_PHY_663_DATA */
+ 0x0000002a, /* DENALI_PHY_664_DATA */
+ 0x00000033, /* DENALI_PHY_665_DATA */
+ 0x0000000c, /* DENALI_PHY_666_DATA */
+ 0x0000000c, /* DENALI_PHY_667_DATA */
+ 0x00000033, /* DENALI_PHY_668_DATA */
+ 0x00000000, /* DENALI_PHY_669_DATA */
+ 0x00000000, /* DENALI_PHY_670_DATA */
+ 0x00000000, /* DENALI_PHY_671_DATA */
+ 0x00030055, /* DENALI_PHY_672_DATA */
+ 0x03000300, /* DENALI_PHY_673_DATA */
+ 0x03000300, /* DENALI_PHY_674_DATA */
+ 0x00000300, /* DENALI_PHY_675_DATA */
+ 0x42080010, /* DENALI_PHY_676_DATA */
+ 0x00000003, /* DENALI_PHY_677_DATA */
+ 0x00000000, /* DENALI_PHY_678_DATA */
+ 0x00000000, /* DENALI_PHY_679_DATA */
+ 0x00000000, /* DENALI_PHY_680_DATA */
+ 0x00000000, /* DENALI_PHY_681_DATA */
+ 0x00000000, /* DENALI_PHY_682_DATA */
+ 0x00000000, /* DENALI_PHY_683_DATA */
+ 0x00000000, /* DENALI_PHY_684_DATA */
+ 0x00000000, /* DENALI_PHY_685_DATA */
+ 0x00000000, /* DENALI_PHY_686_DATA */
+ 0x00000000, /* DENALI_PHY_687_DATA */
+ 0x00000000, /* DENALI_PHY_688_DATA */
+ 0x00000000, /* DENALI_PHY_689_DATA */
+ 0x00000000, /* DENALI_PHY_690_DATA */
+ 0x00000000, /* DENALI_PHY_691_DATA */
+ 0x00000000, /* DENALI_PHY_692_DATA */
+ 0x00000000, /* DENALI_PHY_693_DATA */
+ 0x00000000, /* DENALI_PHY_694_DATA */
+ 0x00000000, /* DENALI_PHY_695_DATA */
+ 0x00000000, /* DENALI_PHY_696_DATA */
+ 0x00000000, /* DENALI_PHY_697_DATA */
+ 0x00000000, /* DENALI_PHY_698_DATA */
+ 0x00000000, /* DENALI_PHY_699_DATA */
+ 0x00000000, /* DENALI_PHY_700_DATA */
+ 0x00000000, /* DENALI_PHY_701_DATA */
+ 0x00000000, /* DENALI_PHY_702_DATA */
+ 0x00000000, /* DENALI_PHY_703_DATA */
+ 0x00000000, /* DENALI_PHY_704_DATA */
+ 0x00000000, /* DENALI_PHY_705_DATA */
+ 0x00000000, /* DENALI_PHY_706_DATA */
+ 0x00000000, /* DENALI_PHY_707_DATA */
+ 0x00000000, /* DENALI_PHY_708_DATA */
+ 0x00000000, /* DENALI_PHY_709_DATA */
+ 0x00000000, /* DENALI_PHY_710_DATA */
+ 0x00000000, /* DENALI_PHY_711_DATA */
+ 0x00000000, /* DENALI_PHY_712_DATA */
+ 0x00000000, /* DENALI_PHY_713_DATA */
+ 0x00000000, /* DENALI_PHY_714_DATA */
+ 0x00000000, /* DENALI_PHY_715_DATA */
+ 0x00000000, /* DENALI_PHY_716_DATA */
+ 0x00000000, /* DENALI_PHY_717_DATA */
+ 0x00000000, /* DENALI_PHY_718_DATA */
+ 0x00000000, /* DENALI_PHY_719_DATA */
+ 0x00000000, /* DENALI_PHY_720_DATA */
+ 0x00000000, /* DENALI_PHY_721_DATA */
+ 0x00000000, /* DENALI_PHY_722_DATA */
+ 0x00000000, /* DENALI_PHY_723_DATA */
+ 0x00000000, /* DENALI_PHY_724_DATA */
+ 0x00000000, /* DENALI_PHY_725_DATA */
+ 0x00000000, /* DENALI_PHY_726_DATA */
+ 0x00000000, /* DENALI_PHY_727_DATA */
+ 0x00000000, /* DENALI_PHY_728_DATA */
+ 0x00000000, /* DENALI_PHY_729_DATA */
+ 0x00000000, /* DENALI_PHY_730_DATA */
+ 0x00000000, /* DENALI_PHY_731_DATA */
+ 0x00000000, /* DENALI_PHY_732_DATA */
+ 0x00000000, /* DENALI_PHY_733_DATA */
+ 0x00000000, /* DENALI_PHY_734_DATA */
+ 0x00000000, /* DENALI_PHY_735_DATA */
+ 0x00000000, /* DENALI_PHY_736_DATA */
+ 0x00000000, /* DENALI_PHY_737_DATA */
+ 0x00000000, /* DENALI_PHY_738_DATA */
+ 0x00000000, /* DENALI_PHY_739_DATA */
+ 0x00000000, /* DENALI_PHY_740_DATA */
+ 0x00000000, /* DENALI_PHY_741_DATA */
+ 0x00000000, /* DENALI_PHY_742_DATA */
+ 0x00000000, /* DENALI_PHY_743_DATA */
+ 0x00000000, /* DENALI_PHY_744_DATA */
+ 0x00000000, /* DENALI_PHY_745_DATA */
+ 0x00000000, /* DENALI_PHY_746_DATA */
+ 0x00000000, /* DENALI_PHY_747_DATA */
+ 0x00000000, /* DENALI_PHY_748_DATA */
+ 0x00000000, /* DENALI_PHY_749_DATA */
+ 0x00000000, /* DENALI_PHY_750_DATA */
+ 0x00000000, /* DENALI_PHY_751_DATA */
+ 0x00000000, /* DENALI_PHY_752_DATA */
+ 0x00000000, /* DENALI_PHY_753_DATA */
+ 0x00000000, /* DENALI_PHY_754_DATA */
+ 0x00000000, /* DENALI_PHY_755_DATA */
+ 0x00000000, /* DENALI_PHY_756_DATA */
+ 0x00000000, /* DENALI_PHY_757_DATA */
+ 0x00000000, /* DENALI_PHY_758_DATA */
+ 0x00000000, /* DENALI_PHY_759_DATA */
+ 0x00000000, /* DENALI_PHY_760_DATA */
+ 0x00000000, /* DENALI_PHY_761_DATA */
+ 0x00000000, /* DENALI_PHY_762_DATA */
+ 0x00000000, /* DENALI_PHY_763_DATA */
+ 0x00000000, /* DENALI_PHY_764_DATA */
+ 0x00000000, /* DENALI_PHY_765_DATA */
+ 0x00000000, /* DENALI_PHY_766_DATA */
+ 0x00000000, /* DENALI_PHY_767_DATA */
+ 0x00000000, /* DENALI_PHY_768_DATA */
+ 0x00000000, /* DENALI_PHY_769_DATA */
+ 0x00000000, /* DENALI_PHY_770_DATA */
+ 0x00000000, /* DENALI_PHY_771_DATA */
+ 0x00000000, /* DENALI_PHY_772_DATA */
+ 0x00000000, /* DENALI_PHY_773_DATA */
+ 0x00000000, /* DENALI_PHY_774_DATA */
+ 0x00000002, /* DENALI_PHY_775_DATA */
+ 0x00000000, /* DENALI_PHY_776_DATA */
+ 0x00000000, /* DENALI_PHY_777_DATA */
+ 0x00000000, /* DENALI_PHY_778_DATA */
+ 0x00400320, /* DENALI_PHY_779_DATA */
+ 0x00000040, /* DENALI_PHY_780_DATA */
+ 0x00000000, /* DENALI_PHY_781_DATA */
+ 0x00000000, /* DENALI_PHY_782_DATA */
+ 0x00000000, /* DENALI_PHY_783_DATA */
+ 0x01000000, /* DENALI_PHY_784_DATA */
+ 0x00020003, /* DENALI_PHY_785_DATA */
+ 0x00000000, /* DENALI_PHY_786_DATA */
+ 0x00000000, /* DENALI_PHY_787_DATA */
+ 0x00000000, /* DENALI_PHY_788_DATA */
+ 0x0000002a, /* DENALI_PHY_789_DATA */
+ 0x00000015, /* DENALI_PHY_790_DATA */
+ 0x00000015, /* DENALI_PHY_791_DATA */
+ 0x0000002a, /* DENALI_PHY_792_DATA */
+ 0x00000033, /* DENALI_PHY_793_DATA */
+ 0x0000000c, /* DENALI_PHY_794_DATA */
+ 0x0000000c, /* DENALI_PHY_795_DATA */
+ 0x00000033, /* DENALI_PHY_796_DATA */
+ 0x1ee6b16a, /* DENALI_PHY_797_DATA */
+ 0x10000000, /* DENALI_PHY_798_DATA */
+ 0x00000000, /* DENALI_PHY_799_DATA */
+ 0x00030055, /* DENALI_PHY_800_DATA */
+ 0x03000300, /* DENALI_PHY_801_DATA */
+ 0x03000300, /* DENALI_PHY_802_DATA */
+ 0x00000300, /* DENALI_PHY_803_DATA */
+ 0x42080010, /* DENALI_PHY_804_DATA */
+ 0x00000003, /* DENALI_PHY_805_DATA */
+ 0x00000000, /* DENALI_PHY_806_DATA */
+ 0x00000000, /* DENALI_PHY_807_DATA */
+ 0x00000000, /* DENALI_PHY_808_DATA */
+ 0x00000000, /* DENALI_PHY_809_DATA */
+ 0x00000000, /* DENALI_PHY_810_DATA */
+ 0x00000000, /* DENALI_PHY_811_DATA */
+ 0x00000000, /* DENALI_PHY_812_DATA */
+ 0x00000000, /* DENALI_PHY_813_DATA */
+ 0x00000000, /* DENALI_PHY_814_DATA */
+ 0x00000000, /* DENALI_PHY_815_DATA */
+ 0x00000000, /* DENALI_PHY_816_DATA */
+ 0x00000000, /* DENALI_PHY_817_DATA */
+ 0x00000000, /* DENALI_PHY_818_DATA */
+ 0x00000000, /* DENALI_PHY_819_DATA */
+ 0x00000000, /* DENALI_PHY_820_DATA */
+ 0x00000000, /* DENALI_PHY_821_DATA */
+ 0x00000000, /* DENALI_PHY_822_DATA */
+ 0x00000000, /* DENALI_PHY_823_DATA */
+ 0x00000000, /* DENALI_PHY_824_DATA */
+ 0x00000000, /* DENALI_PHY_825_DATA */
+ 0x00000000, /* DENALI_PHY_826_DATA */
+ 0x00000000, /* DENALI_PHY_827_DATA */
+ 0x00000000, /* DENALI_PHY_828_DATA */
+ 0x00000000, /* DENALI_PHY_829_DATA */
+ 0x00000000, /* DENALI_PHY_830_DATA */
+ 0x00000000, /* DENALI_PHY_831_DATA */
+ 0x00000000, /* DENALI_PHY_832_DATA */
+ 0x00000000, /* DENALI_PHY_833_DATA */
+ 0x00000000, /* DENALI_PHY_834_DATA */
+ 0x00000000, /* DENALI_PHY_835_DATA */
+ 0x00000000, /* DENALI_PHY_836_DATA */
+ 0x00000000, /* DENALI_PHY_837_DATA */
+ 0x00000000, /* DENALI_PHY_838_DATA */
+ 0x00000000, /* DENALI_PHY_839_DATA */
+ 0x00000000, /* DENALI_PHY_840_DATA */
+ 0x00000000, /* DENALI_PHY_841_DATA */
+ 0x00000000, /* DENALI_PHY_842_DATA */
+ 0x00000000, /* DENALI_PHY_843_DATA */
+ 0x00000000, /* DENALI_PHY_844_DATA */
+ 0x00000000, /* DENALI_PHY_845_DATA */
+ 0x00000000, /* DENALI_PHY_846_DATA */
+ 0x00000000, /* DENALI_PHY_847_DATA */
+ 0x00000000, /* DENALI_PHY_848_DATA */
+ 0x00000000, /* DENALI_PHY_849_DATA */
+ 0x00000000, /* DENALI_PHY_850_DATA */
+ 0x00000000, /* DENALI_PHY_851_DATA */
+ 0x00000000, /* DENALI_PHY_852_DATA */
+ 0x00000000, /* DENALI_PHY_853_DATA */
+ 0x00000000, /* DENALI_PHY_854_DATA */
+ 0x00000000, /* DENALI_PHY_855_DATA */
+ 0x00000000, /* DENALI_PHY_856_DATA */
+ 0x00000000, /* DENALI_PHY_857_DATA */
+ 0x00000000, /* DENALI_PHY_858_DATA */
+ 0x00000000, /* DENALI_PHY_859_DATA */
+ 0x00000000, /* DENALI_PHY_860_DATA */
+ 0x00000000, /* DENALI_PHY_861_DATA */
+ 0x00000000, /* DENALI_PHY_862_DATA */
+ 0x00000000, /* DENALI_PHY_863_DATA */
+ 0x00000000, /* DENALI_PHY_864_DATA */
+ 0x00000000, /* DENALI_PHY_865_DATA */
+ 0x00000000, /* DENALI_PHY_866_DATA */
+ 0x00000000, /* DENALI_PHY_867_DATA */
+ 0x00000000, /* DENALI_PHY_868_DATA */
+ 0x00000000, /* DENALI_PHY_869_DATA */
+ 0x00000000, /* DENALI_PHY_870_DATA */
+ 0x00000000, /* DENALI_PHY_871_DATA */
+ 0x00000000, /* DENALI_PHY_872_DATA */
+ 0x00000000, /* DENALI_PHY_873_DATA */
+ 0x00000000, /* DENALI_PHY_874_DATA */
+ 0x00000000, /* DENALI_PHY_875_DATA */
+ 0x00000000, /* DENALI_PHY_876_DATA */
+ 0x00000000, /* DENALI_PHY_877_DATA */
+ 0x00000000, /* DENALI_PHY_878_DATA */
+ 0x00000000, /* DENALI_PHY_879_DATA */
+ 0x00000000, /* DENALI_PHY_880_DATA */
+ 0x00000000, /* DENALI_PHY_881_DATA */
+ 0x00000000, /* DENALI_PHY_882_DATA */
+ 0x00000000, /* DENALI_PHY_883_DATA */
+ 0x00000000, /* DENALI_PHY_884_DATA */
+ 0x00000000, /* DENALI_PHY_885_DATA */
+ 0x00000000, /* DENALI_PHY_886_DATA */
+ 0x00000000, /* DENALI_PHY_887_DATA */
+ 0x00000000, /* DENALI_PHY_888_DATA */
+ 0x00000000, /* DENALI_PHY_889_DATA */
+ 0x00000000, /* DENALI_PHY_890_DATA */
+ 0x00000000, /* DENALI_PHY_891_DATA */
+ 0x00000000, /* DENALI_PHY_892_DATA */
+ 0x00000000, /* DENALI_PHY_893_DATA */
+ 0x00000000, /* DENALI_PHY_894_DATA */
+ 0x00000000, /* DENALI_PHY_895_DATA */
+ 0x00000000, /* DENALI_PHY_896_DATA */
+ 0x00000000, /* DENALI_PHY_897_DATA */
+ 0x00000005, /* DENALI_PHY_898_DATA */
+ 0x04000f01, /* DENALI_PHY_899_DATA */
+ 0x00020040, /* DENALI_PHY_900_DATA */
+ 0x00020055, /* DENALI_PHY_901_DATA */
+ 0x00000000, /* DENALI_PHY_902_DATA */
+ 0x00000000, /* DENALI_PHY_903_DATA */
+ 0x00000000, /* DENALI_PHY_904_DATA */
+ 0x00000050, /* DENALI_PHY_905_DATA */
+ 0x00000000, /* DENALI_PHY_906_DATA */
+ 0x01010100, /* DENALI_PHY_907_DATA */
+ 0x00000600, /* DENALI_PHY_908_DATA */
+ 0x00000000, /* DENALI_PHY_909_DATA */
+ 0x00006400, /* DENALI_PHY_910_DATA */
+ 0x03221302, /* DENALI_PHY_911_DATA */
+ 0x00000000, /* DENALI_PHY_912_DATA */
+ 0x000d1f01, /* DENALI_PHY_913_DATA */
+ 0x0d1f0d1f, /* DENALI_PHY_914_DATA */
+ 0x0d1f0d1f, /* DENALI_PHY_915_DATA */
+ 0x00030003, /* DENALI_PHY_916_DATA */
+ 0x03000300, /* DENALI_PHY_917_DATA */
+ 0x00000300, /* DENALI_PHY_918_DATA */
+ 0x03221302, /* DENALI_PHY_919_DATA */
+ 0x00000000, /* DENALI_PHY_920_DATA */
+ 0x00000000, /* DENALI_PHY_921_DATA */
+ 0x01020000, /* DENALI_PHY_922_DATA */
+ 0x00000001, /* DENALI_PHY_923_DATA */
+ 0x00000411, /* DENALI_PHY_924_DATA */
+ 0x00000411, /* DENALI_PHY_925_DATA */
+ 0x00000040, /* DENALI_PHY_926_DATA */
+ 0x00000040, /* DENALI_PHY_927_DATA */
+ 0x00000411, /* DENALI_PHY_928_DATA */
+ 0x00000411, /* DENALI_PHY_929_DATA */
+ 0x00004410, /* DENALI_PHY_930_DATA */
+ 0x00004410, /* DENALI_PHY_931_DATA */
+ 0x00004410, /* DENALI_PHY_932_DATA */
+ 0x00004410, /* DENALI_PHY_933_DATA */
+ 0x00004410, /* DENALI_PHY_934_DATA */
+ 0x00000411, /* DENALI_PHY_935_DATA */
+ 0x00004410, /* DENALI_PHY_936_DATA */
+ 0x00000411, /* DENALI_PHY_937_DATA */
+ 0x00004410, /* DENALI_PHY_938_DATA */
+ 0x00000411, /* DENALI_PHY_939_DATA */
+ 0x00004410, /* DENALI_PHY_940_DATA */
+ 0x00000000, /* DENALI_PHY_941_DATA */
+ 0x00000000, /* DENALI_PHY_942_DATA */
+ 0x00000000, /* DENALI_PHY_943_DATA */
+ 0x64000000, /* DENALI_PHY_944_DATA */
+ 0x00000000, /* DENALI_PHY_945_DATA */
+ 0x00000000, /* DENALI_PHY_946_DATA */
+ 0x00000408, /* DENALI_PHY_947_DATA */
+ 0x00000000, /* DENALI_PHY_948_DATA */
+ 0x00000000, /* DENALI_PHY_949_DATA */
+ 0x00000000, /* DENALI_PHY_950_DATA */
+ 0x00000000, /* DENALI_PHY_951_DATA */
+ 0x00000000, /* DENALI_PHY_952_DATA */
+ 0x00000000, /* DENALI_PHY_953_DATA */
+ 0xe4000000, /* DENALI_PHY_954_DATA */
+ 0x00000000, /* DENALI_PHY_955_DATA */
+ 0x00000000, /* DENALI_PHY_956_DATA */
+ 0x01010000, /* DENALI_PHY_957_DATA */
+ 0x00000000 /* DENALI_PHY_958_DATA */
+ }
+ },
+},
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 83/92] ram: rk3399: Add LPPDDR4-800 timings inc
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:51 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
LPDDR4 initialization start with at board selected frequency
and then it switches into 400MHz and 800MHz simultaneously to
make the proper sequence work on each channel with associated
training.
So, add LPDDR4-800 timings inc file in driver area so-that
these timings will take during LPDDR4 initialization phase.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
.../ram/rockchip/sdram-rk3399-lpddr4-800.inc | 1570 +++++++++++++++++
1 file changed, 1570 insertions(+)
create mode 100644 drivers/ram/rockchip/sdram-rk3399-lpddr4-800.inc
diff --git a/drivers/ram/rockchip/sdram-rk3399-lpddr4-800.inc b/drivers/ram/rockchip/sdram-rk3399-lpddr4-800.inc
new file mode 100644
index 0000000000..d8ae3359a3
--- /dev/null
+++ b/drivers/ram/rockchip/sdram-rk3399-lpddr4-800.inc
@@ -0,0 +1,1570 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd.
+ * (C) Copyright 2019 Amarula Solutions
+ */
+
+{
+ {
+ {
+ {
+ .rank = 0x2,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF,
+ .ddrconfig = 1,
+ },
+ {
+ .ddrtiminga0 = 0x80241d22,
+ .ddrtimingb0 = 0x15050f08,
+ .ddrtimingc0 = {
+ 0x00000602,
+ },
+ .devtodev0 = 0x00002122,
+ .ddrmode = {
+ 0x0000004c,
+ },
+ .agingx0 = 0x00000000,
+ }
+ },
+ {
+ {
+ .rank = 0x2,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF,
+ .ddrconfig = 1,
+ },
+ {
+ .ddrtiminga0 = 0x80241d22,
+ .ddrtimingb0 = 0x15050f08,
+ .ddrtimingc0 = {
+ 0x00000602,
+ },
+ .devtodev0 = 0x00002122,
+ .ddrmode = {
+ 0x0000004c,
+ },
+ .agingx0 = 0x00000000,
+ }
+ }
+ },
+ {
+ .ddr_freq = 800 * MHz,
+ .dramtype = LPDDR4,
+ .num_channels = 2,
+ .stride = 13,
+ .odt = 1,
+ },
+ {
+ {
+ 0x00000b00, /* DENALI_CTL_00_DATA */
+ 0x00000000, /* DENALI_CTL_01_DATA */
+ 0x00000000, /* DENALI_CTL_02_DATA */
+ 0x00000000, /* DENALI_CTL_03_DATA */
+ 0x00000000, /* DENALI_CTL_04_DATA */
+ 0x00013880, /* DENALI_CTL_05_DATA */
+ 0x000c3500, /* DENALI_CTL_06_DATA */
+ 0x00000005, /* DENALI_CTL_07_DATA */
+ 0x00000320, /* DENALI_CTL_08_DATA */
+ 0x00027100, /* DENALI_CTL_09_DATA */
+ 0x00186a00, /* DENALI_CTL_10_DATA */
+ 0x00000005, /* DENALI_CTL_11_DATA */
+ 0x00000640, /* DENALI_CTL_12_DATA */
+ 0x00002710, /* DENALI_CTL_13_DATA */
+ 0x000186a0, /* DENALI_CTL_14_DATA */
+ 0x00000005, /* DENALI_CTL_15_DATA */
+ 0x01000064, /* DENALI_CTL_16_DATA */
+ 0x00000000, /* DENALI_CTL_17_DATA */
+ 0x02020101, /* DENALI_CTL_18_DATA */
+ 0x00000102, /* DENALI_CTL_19_DATA */
+ 0x00000050, /* DENALI_CTL_20_DATA */
+ 0x000000c8, /* DENALI_CTL_21_DATA */
+ 0x00000000, /* DENALI_CTL_22_DATA */
+ 0x06140000, /* DENALI_CTL_23_DATA */
+ 0x00081c00, /* DENALI_CTL_24_DATA */
+ 0x0400040c, /* DENALI_CTL_25_DATA */
+ 0x19042008, /* DENALI_CTL_26_DATA */
+ 0x10080a11, /* DENALI_CTL_27_DATA */
+ 0x22310800, /* DENALI_CTL_28_DATA */
+ 0x00200f0a, /* DENALI_CTL_29_DATA */
+ 0x0a030704, /* DENALI_CTL_30_DATA */
+ 0x08000204, /* DENALI_CTL_31_DATA */
+ 0x00000a0a, /* DENALI_CTL_32_DATA */
+ 0x04006db0, /* DENALI_CTL_33_DATA */
+ 0x0a0a0804, /* DENALI_CTL_34_DATA */
+ 0x0600db60, /* DENALI_CTL_35_DATA */
+ 0x0a0a0806, /* DENALI_CTL_36_DATA */
+ 0x04000db6, /* DENALI_CTL_37_DATA */
+ 0x02030404, /* DENALI_CTL_38_DATA */
+ 0x0f0a0800, /* DENALI_CTL_39_DATA */
+ 0x08040411, /* DENALI_CTL_40_DATA */
+ 0x1400640a, /* DENALI_CTL_41_DATA */
+ 0x02010a0a, /* DENALI_CTL_42_DATA */
+ 0x00010001, /* DENALI_CTL_43_DATA */
+ 0x04082012, /* DENALI_CTL_44_DATA */
+ 0x00041109, /* DENALI_CTL_45_DATA */
+ 0x00000000, /* DENALI_CTL_46_DATA */
+ 0x03010000, /* DENALI_CTL_47_DATA */
+ 0x06100034, /* DENALI_CTL_48_DATA */
+ 0x0c280068, /* DENALI_CTL_49_DATA */
+ 0x00bb0007, /* DENALI_CTL_50_DATA */
+ 0x00000000, /* DENALI_CTL_51_DATA */
+ 0x00060003, /* DENALI_CTL_52_DATA */
+ 0x000a0003, /* DENALI_CTL_53_DATA */
+ 0x000a0014, /* DENALI_CTL_54_DATA */
+ 0x01000000, /* DENALI_CTL_55_DATA */
+ 0x030a0000, /* DENALI_CTL_56_DATA */
+ 0x0c000002, /* DENALI_CTL_57_DATA */
+ 0x00000103, /* DENALI_CTL_58_DATA */
+ 0x0003030a, /* DENALI_CTL_59_DATA */
+ 0x00060037, /* DENALI_CTL_60_DATA */
+ 0x0003006e, /* DENALI_CTL_61_DATA */
+ 0x05050007, /* DENALI_CTL_62_DATA */
+ 0x03020605, /* DENALI_CTL_63_DATA */
+ 0x06050301, /* DENALI_CTL_64_DATA */
+ 0x06020c05, /* DENALI_CTL_65_DATA */
+ 0x05050302, /* DENALI_CTL_66_DATA */
+ 0x03020305, /* DENALI_CTL_67_DATA */
+ 0x00000301, /* DENALI_CTL_68_DATA */
+ 0x00000301, /* DENALI_CTL_69_DATA */
+ 0x00000001, /* DENALI_CTL_70_DATA */
+ 0x00000000, /* DENALI_CTL_71_DATA */
+ 0x00000000, /* DENALI_CTL_72_DATA */
+ 0x01000000, /* DENALI_CTL_73_DATA */
+ 0x80104002, /* DENALI_CTL_74_DATA */
+ 0x00040003, /* DENALI_CTL_75_DATA */
+ 0x00040005, /* DENALI_CTL_76_DATA */
+ 0x00030000, /* DENALI_CTL_77_DATA */
+ 0x00050004, /* DENALI_CTL_78_DATA */
+ 0x00000004, /* DENALI_CTL_79_DATA */
+ 0x00040003, /* DENALI_CTL_80_DATA */
+ 0x00040005, /* DENALI_CTL_81_DATA */
+ 0x18400000, /* DENALI_CTL_82_DATA */
+ 0x00000c20, /* DENALI_CTL_83_DATA */
+ 0x185030a0, /* DENALI_CTL_84_DATA */
+ 0x02ec0000, /* DENALI_CTL_85_DATA */
+ 0x00000176, /* DENALI_CTL_86_DATA */
+ 0x00000000, /* DENALI_CTL_87_DATA */
+ 0x00000000, /* DENALI_CTL_88_DATA */
+ 0x00000000, /* DENALI_CTL_89_DATA */
+ 0x00000000, /* DENALI_CTL_90_DATA */
+ 0x00000000, /* DENALI_CTL_91_DATA */
+ 0x06030300, /* DENALI_CTL_92_DATA */
+ 0x00030303, /* DENALI_CTL_93_DATA */
+ 0x02030200, /* DENALI_CTL_94_DATA */
+ 0x00040703, /* DENALI_CTL_95_DATA */
+ 0x03020302, /* DENALI_CTL_96_DATA */
+ 0x02000407, /* DENALI_CTL_97_DATA */
+ 0x07030203, /* DENALI_CTL_98_DATA */
+ 0x00030f04, /* DENALI_CTL_99_DATA */
+ 0x00070004, /* DENALI_CTL_100_DATA */
+ 0x00000000, /* DENALI_CTL_101_DATA */
+ 0x00000000, /* DENALI_CTL_102_DATA */
+ 0x00000000, /* DENALI_CTL_103_DATA */
+ 0x00000000, /* DENALI_CTL_104_DATA */
+ 0x00000000, /* DENALI_CTL_105_DATA */
+ 0x00000000, /* DENALI_CTL_106_DATA */
+ 0x00000000, /* DENALI_CTL_107_DATA */
+ 0x00010000, /* DENALI_CTL_108_DATA */
+ 0x20040020, /* DENALI_CTL_109_DATA */
+ 0x00200400, /* DENALI_CTL_110_DATA */
+ 0x01000400, /* DENALI_CTL_111_DATA */
+ 0x00000b80, /* DENALI_CTL_112_DATA */
+ 0x00000000, /* DENALI_CTL_113_DATA */
+ 0x00000001, /* DENALI_CTL_114_DATA */
+ 0x00000002, /* DENALI_CTL_115_DATA */
+ 0x0000000e, /* DENALI_CTL_116_DATA */
+ 0x00000000, /* DENALI_CTL_117_DATA */
+ 0x00000000, /* DENALI_CTL_118_DATA */
+ 0x00000000, /* DENALI_CTL_119_DATA */
+ 0x00000000, /* DENALI_CTL_120_DATA */
+ 0x00000000, /* DENALI_CTL_121_DATA */
+ 0x00500000, /* DENALI_CTL_122_DATA */
+ 0x00640028, /* DENALI_CTL_123_DATA */
+ 0x00640404, /* DENALI_CTL_124_DATA */
+ 0x005000a0, /* DENALI_CTL_125_DATA */
+ 0x060600c8, /* DENALI_CTL_126_DATA */
+ 0x000a00c8, /* DENALI_CTL_127_DATA */
+ 0x000d0005, /* DENALI_CTL_128_DATA */
+ 0x000d0404, /* DENALI_CTL_129_DATA */
+ 0x00000000, /* DENALI_CTL_130_DATA */
+ 0x00000000, /* DENALI_CTL_131_DATA */
+ 0x00000000, /* DENALI_CTL_132_DATA */
+ 0x001400a3, /* DENALI_CTL_133_DATA */
+ 0x00e30009, /* DENALI_CTL_134_DATA */
+ 0x00120024, /* DENALI_CTL_135_DATA */
+ 0x00040063, /* DENALI_CTL_136_DATA */
+ 0x00000000, /* DENALI_CTL_137_DATA */
+ 0x00310031, /* DENALI_CTL_138_DATA */
+ 0x00000031, /* DENALI_CTL_139_DATA */
+ 0x004d0000, /* DENALI_CTL_140_DATA */
+ 0x004d004d, /* DENALI_CTL_141_DATA */
+ 0x004d0000, /* DENALI_CTL_142_DATA */
+ 0x004d004d, /* DENALI_CTL_143_DATA */
+ 0x00010101, /* DENALI_CTL_144_DATA */
+ 0x00000000, /* DENALI_CTL_145_DATA */
+ 0x00000000, /* DENALI_CTL_146_DATA */
+ 0x001400a3, /* DENALI_CTL_147_DATA */
+ 0x00e30009, /* DENALI_CTL_148_DATA */
+ 0x00120024, /* DENALI_CTL_149_DATA */
+ 0x00040063, /* DENALI_CTL_150_DATA */
+ 0x00000000, /* DENALI_CTL_151_DATA */
+ 0x00310031, /* DENALI_CTL_152_DATA */
+ 0x00000031, /* DENALI_CTL_153_DATA */
+ 0x004d0000, /* DENALI_CTL_154_DATA */
+ 0x004d004d, /* DENALI_CTL_155_DATA */
+ 0x004d0000, /* DENALI_CTL_156_DATA */
+ 0x004d004d, /* DENALI_CTL_157_DATA */
+ 0x00010101, /* DENALI_CTL_158_DATA */
+ 0x00000000, /* DENALI_CTL_159_DATA */
+ 0x00000000, /* DENALI_CTL_160_DATA */
+ 0x00000000, /* DENALI_CTL_161_DATA */
+ 0x00000001, /* DENALI_CTL_162_DATA */
+ 0x00000000, /* DENALI_CTL_163_DATA */
+ 0x18151100, /* DENALI_CTL_164_DATA */
+ 0x0000000c, /* DENALI_CTL_165_DATA */
+ 0x00000000, /* DENALI_CTL_166_DATA */
+ 0x00000000, /* DENALI_CTL_167_DATA */
+ 0x00000000, /* DENALI_CTL_168_DATA */
+ 0x00000000, /* DENALI_CTL_169_DATA */
+ 0x00000000, /* DENALI_CTL_170_DATA */
+ 0x00000000, /* DENALI_CTL_171_DATA */
+ 0x00000000, /* DENALI_CTL_172_DATA */
+ 0x00000000, /* DENALI_CTL_173_DATA */
+ 0x00000000, /* DENALI_CTL_174_DATA */
+ 0x00000000, /* DENALI_CTL_175_DATA */
+ 0x00000000, /* DENALI_CTL_176_DATA */
+ 0x00000000, /* DENALI_CTL_177_DATA */
+ 0x00000000, /* DENALI_CTL_178_DATA */
+ 0x00020003, /* DENALI_CTL_179_DATA */
+ 0x00400100, /* DENALI_CTL_180_DATA */
+ 0x000c0190, /* DENALI_CTL_181_DATA */
+ 0x01000200, /* DENALI_CTL_182_DATA */
+ 0x03200040, /* DENALI_CTL_183_DATA */
+ 0x00020018, /* DENALI_CTL_184_DATA */
+ 0x00400100, /* DENALI_CTL_185_DATA */
+ 0x00080032, /* DENALI_CTL_186_DATA */
+ 0x00140000, /* DENALI_CTL_187_DATA */
+ 0x00030028, /* DENALI_CTL_188_DATA */
+ 0x01010100, /* DENALI_CTL_189_DATA */
+ 0x02000202, /* DENALI_CTL_190_DATA */
+ 0x0b000002, /* DENALI_CTL_191_DATA */
+ 0x01000f0f, /* DENALI_CTL_192_DATA */
+ 0x00000000, /* DENALI_CTL_193_DATA */
+ 0x00000000, /* DENALI_CTL_194_DATA */
+ 0x00010003, /* DENALI_CTL_195_DATA */
+ 0x00000c03, /* DENALI_CTL_196_DATA */
+ 0x00040101, /* DENALI_CTL_197_DATA */
+ 0x04010100, /* DENALI_CTL_198_DATA */
+ 0x01000000, /* DENALI_CTL_199_DATA */
+ 0x02010000, /* DENALI_CTL_200_DATA */
+ 0x00000001, /* DENALI_CTL_201_DATA */
+ 0x00000000, /* DENALI_CTL_202_DATA */
+ 0x00000000, /* DENALI_CTL_203_DATA */
+ 0x00000000, /* DENALI_CTL_204_DATA */
+ 0x00000000, /* DENALI_CTL_205_DATA */
+ 0x00000000, /* DENALI_CTL_206_DATA */
+ 0x00000000, /* DENALI_CTL_207_DATA */
+ 0x00000000, /* DENALI_CTL_208_DATA */
+ 0x00000000, /* DENALI_CTL_209_DATA */
+ 0x00000000, /* DENALI_CTL_210_DATA */
+ 0x00010000, /* DENALI_CTL_211_DATA */
+ 0x00000001, /* DENALI_CTL_212_DATA */
+ 0x01010001, /* DENALI_CTL_213_DATA */
+ 0x05040001, /* DENALI_CTL_214_DATA */
+ 0x040a0703, /* DENALI_CTL_215_DATA */
+ 0x02080808, /* DENALI_CTL_216_DATA */
+ 0x020e000a, /* DENALI_CTL_217_DATA */
+ 0x020f010b, /* DENALI_CTL_218_DATA */
+ 0x000d0008, /* DENALI_CTL_219_DATA */
+ 0x00080b0a, /* DENALI_CTL_220_DATA */
+ 0x03000200, /* DENALI_CTL_221_DATA */
+ 0x00000100, /* DENALI_CTL_222_DATA */
+ 0x00000000, /* DENALI_CTL_223_DATA */
+ 0x00000000, /* DENALI_CTL_224_DATA */
+ 0x0d000001, /* DENALI_CTL_225_DATA */
+ 0x00000028, /* DENALI_CTL_226_DATA */
+ 0x00010000, /* DENALI_CTL_227_DATA */
+ 0x00000003, /* DENALI_CTL_228_DATA */
+ 0x00000000, /* DENALI_CTL_229_DATA */
+ 0x00000000, /* DENALI_CTL_230_DATA */
+ 0x00000000, /* DENALI_CTL_231_DATA */
+ 0x00000000, /* DENALI_CTL_232_DATA */
+ 0x00000000, /* DENALI_CTL_233_DATA */
+ 0x00000000, /* DENALI_CTL_234_DATA */
+ 0x00000000, /* DENALI_CTL_235_DATA */
+ 0x00000000, /* DENALI_CTL_236_DATA */
+ 0x00010100, /* DENALI_CTL_237_DATA */
+ 0x01000000, /* DENALI_CTL_238_DATA */
+ 0x00000001, /* DENALI_CTL_239_DATA */
+ 0x00000303, /* DENALI_CTL_240_DATA */
+ 0x00000000, /* DENALI_CTL_241_DATA */
+ 0x00000000, /* DENALI_CTL_242_DATA */
+ 0x00000000, /* DENALI_CTL_243_DATA */
+ 0x00000000, /* DENALI_CTL_244_DATA */
+ 0x00000000, /* DENALI_CTL_245_DATA */
+ 0x00000000, /* DENALI_CTL_246_DATA */
+ 0x00000000, /* DENALI_CTL_247_DATA */
+ 0x00000000, /* DENALI_CTL_248_DATA */
+ 0x00000000, /* DENALI_CTL_249_DATA */
+ 0x00000000, /* DENALI_CTL_250_DATA */
+ 0x00000000, /* DENALI_CTL_251_DATA */
+ 0x00000000, /* DENALI_CTL_252_DATA */
+ 0x00000000, /* DENALI_CTL_253_DATA */
+ 0x00000000, /* DENALI_CTL_254_DATA */
+ 0x00000000, /* DENALI_CTL_255_DATA */
+ 0x000556aa, /* DENALI_CTL_256_DATA */
+ 0x000aaaaa, /* DENALI_CTL_257_DATA */
+ 0x000aa955, /* DENALI_CTL_258_DATA */
+ 0x00055555, /* DENALI_CTL_259_DATA */
+ 0x000b3133, /* DENALI_CTL_260_DATA */
+ 0x0004cd33, /* DENALI_CTL_261_DATA */
+ 0x0004cecc, /* DENALI_CTL_262_DATA */
+ 0x000b32cc, /* DENALI_CTL_263_DATA */
+ 0x00010300, /* DENALI_CTL_264_DATA */
+ 0x03000100, /* DENALI_CTL_265_DATA */
+ 0x00000000, /* DENALI_CTL_266_DATA */
+ 0x00000000, /* DENALI_CTL_267_DATA */
+ 0x00000000, /* DENALI_CTL_268_DATA */
+ 0x00000000, /* DENALI_CTL_269_DATA */
+ 0x00000000, /* DENALI_CTL_270_DATA */
+ 0x00000000, /* DENALI_CTL_271_DATA */
+ 0x00000000, /* DENALI_CTL_272_DATA */
+ 0x00000000, /* DENALI_CTL_273_DATA */
+ 0x00ffff00, /* DENALI_CTL_274_DATA */
+ 0x1a160000, /* DENALI_CTL_275_DATA */
+ 0x08000012, /* DENALI_CTL_276_DATA */
+ 0x00000c20, /* DENALI_CTL_277_DATA */
+ 0x00000200, /* DENALI_CTL_278_DATA */
+ 0x00000200, /* DENALI_CTL_279_DATA */
+ 0x00000200, /* DENALI_CTL_280_DATA */
+ 0x00000200, /* DENALI_CTL_281_DATA */
+ 0x00000c20, /* DENALI_CTL_282_DATA */
+ 0x00007940, /* DENALI_CTL_283_DATA */
+ 0x18500409, /* DENALI_CTL_284_DATA */
+ 0x00000200, /* DENALI_CTL_285_DATA */
+ 0x00000200, /* DENALI_CTL_286_DATA */
+ 0x00000200, /* DENALI_CTL_287_DATA */
+ 0x00000200, /* DENALI_CTL_288_DATA */
+ 0x00001850, /* DENALI_CTL_289_DATA */
+ 0x0000f320, /* DENALI_CTL_290_DATA */
+ 0x0176060c, /* DENALI_CTL_291_DATA */
+ 0x00000200, /* DENALI_CTL_292_DATA */
+ 0x00000200, /* DENALI_CTL_293_DATA */
+ 0x00000200, /* DENALI_CTL_294_DATA */
+ 0x00000200, /* DENALI_CTL_295_DATA */
+ 0x00000176, /* DENALI_CTL_296_DATA */
+ 0x00000e9c, /* DENALI_CTL_297_DATA */
+ 0x02020205, /* DENALI_CTL_298_DATA */
+ 0x03030202, /* DENALI_CTL_299_DATA */
+ 0x00000018, /* DENALI_CTL_300_DATA */
+ 0x00000000, /* DENALI_CTL_301_DATA */
+ 0x00000000, /* DENALI_CTL_302_DATA */
+ 0x00001403, /* DENALI_CTL_303_DATA */
+ 0x00000000, /* DENALI_CTL_304_DATA */
+ 0x00000000, /* DENALI_CTL_305_DATA */
+ 0x00000000, /* DENALI_CTL_306_DATA */
+ 0x00030000, /* DENALI_CTL_307_DATA */
+ 0x000a001c, /* DENALI_CTL_308_DATA */
+ 0x000e0020, /* DENALI_CTL_309_DATA */
+ 0x00060018, /* DENALI_CTL_310_DATA */
+ 0x00000000, /* DENALI_CTL_311_DATA */
+ 0x00000000, /* DENALI_CTL_312_DATA */
+ 0x02000000, /* DENALI_CTL_313_DATA */
+ 0x00090305, /* DENALI_CTL_314_DATA */
+ 0x00050101, /* DENALI_CTL_315_DATA */
+ 0x00000000, /* DENALI_CTL_316_DATA */
+ 0x00000000, /* DENALI_CTL_317_DATA */
+ 0x00000000, /* DENALI_CTL_318_DATA */
+ 0x00000000, /* DENALI_CTL_319_DATA */
+ 0x00000000, /* DENALI_CTL_320_DATA */
+ 0x00000000, /* DENALI_CTL_321_DATA */
+ 0x00000000, /* DENALI_CTL_322_DATA */
+ 0x00000000, /* DENALI_CTL_323_DATA */
+ 0x01000001, /* DENALI_CTL_324_DATA */
+ 0x01010101, /* DENALI_CTL_325_DATA */
+ 0x01000101, /* DENALI_CTL_326_DATA */
+ 0x01000100, /* DENALI_CTL_327_DATA */
+ 0x00010001, /* DENALI_CTL_328_DATA */
+ 0x00010002, /* DENALI_CTL_329_DATA */
+ 0x00020100, /* DENALI_CTL_330_DATA */
+ 0x00000002 /* DENALI_CTL_331_DATA */
+ }
+ },
+ {
+ {
+ 0x00000b00, /* DENALI_PI_00_DATA */
+ 0x00000000, /* DENALI_PI_01_DATA */
+ 0x000002ec, /* DENALI_PI_02_DATA */
+ 0x00000176, /* DENALI_PI_03_DATA */
+ 0x000030a0, /* DENALI_PI_04_DATA */
+ 0x00001850, /* DENALI_PI_05_DATA */
+ 0x00001840, /* DENALI_PI_06_DATA */
+ 0x01760c20, /* DENALI_PI_07_DATA */
+ 0x00000200, /* DENALI_PI_08_DATA */
+ 0x00000200, /* DENALI_PI_09_DATA */
+ 0x00000200, /* DENALI_PI_10_DATA */
+ 0x00000200, /* DENALI_PI_11_DATA */
+ 0x00001850, /* DENALI_PI_12_DATA */
+ 0x00000200, /* DENALI_PI_13_DATA */
+ 0x00000200, /* DENALI_PI_14_DATA */
+ 0x00000200, /* DENALI_PI_15_DATA */
+ 0x00000200, /* DENALI_PI_16_DATA */
+ 0x00000c20, /* DENALI_PI_17_DATA */
+ 0x00000200, /* DENALI_PI_18_DATA */
+ 0x00000200, /* DENALI_PI_19_DATA */
+ 0x00000200, /* DENALI_PI_20_DATA */
+ 0x00000200, /* DENALI_PI_21_DATA */
+ 0x00010000, /* DENALI_PI_22_DATA */
+ 0x00000007, /* DENALI_PI_23_DATA */
+ 0x01000001, /* DENALI_PI_24_DATA */
+ 0x00000000, /* DENALI_PI_25_DATA */
+ 0x3fffffff, /* DENALI_PI_26_DATA */
+ 0x00000000, /* DENALI_PI_27_DATA */
+ 0x00000000, /* DENALI_PI_28_DATA */
+ 0x00000000, /* DENALI_PI_29_DATA */
+ 0x00000000, /* DENALI_PI_30_DATA */
+ 0x00000000, /* DENALI_PI_31_DATA */
+ 0x00000000, /* DENALI_PI_32_DATA */
+ 0x00000000, /* DENALI_PI_33_DATA */
+ 0x00000000, /* DENALI_PI_34_DATA */
+ 0x00000000, /* DENALI_PI_35_DATA */
+ 0x00000000, /* DENALI_PI_36_DATA */
+ 0x00000000, /* DENALI_PI_37_DATA */
+ 0x00000000, /* DENALI_PI_38_DATA */
+ 0x00000000, /* DENALI_PI_39_DATA */
+ 0x00000000, /* DENALI_PI_40_DATA */
+ 0x0f000101, /* DENALI_PI_41_DATA */
+ 0x082b3223, /* DENALI_PI_42_DATA */
+ 0x080c0004, /* DENALI_PI_43_DATA */
+ 0x00061c00, /* DENALI_PI_44_DATA */
+ 0x00000214, /* DENALI_PI_45_DATA */
+ 0x00bb0007, /* DENALI_PI_46_DATA */
+ 0x0c280068, /* DENALI_PI_47_DATA */
+ 0x06100034, /* DENALI_PI_48_DATA */
+ 0x00000500, /* DENALI_PI_49_DATA */
+ 0x00000000, /* DENALI_PI_50_DATA */
+ 0x00000000, /* DENALI_PI_51_DATA */
+ 0x00000000, /* DENALI_PI_52_DATA */
+ 0x00000000, /* DENALI_PI_53_DATA */
+ 0x00000000, /* DENALI_PI_54_DATA */
+ 0x00000000, /* DENALI_PI_55_DATA */
+ 0x00000000, /* DENALI_PI_56_DATA */
+ 0x00000000, /* DENALI_PI_57_DATA */
+ 0x04040100, /* DENALI_PI_58_DATA */
+ 0x0a000004, /* DENALI_PI_59_DATA */
+ 0x00000128, /* DENALI_PI_60_DATA */
+ 0x00000000, /* DENALI_PI_61_DATA */
+ 0x0003000f, /* DENALI_PI_62_DATA */
+ 0x00000018, /* DENALI_PI_63_DATA */
+ 0x00000000, /* DENALI_PI_64_DATA */
+ 0x00000000, /* DENALI_PI_65_DATA */
+ 0x00060002, /* DENALI_PI_66_DATA */
+ 0x00010001, /* DENALI_PI_67_DATA */
+ 0x00000101, /* DENALI_PI_68_DATA */
+ 0x00020001, /* DENALI_PI_69_DATA */
+ 0x00080004, /* DENALI_PI_70_DATA */
+ 0x00000000, /* DENALI_PI_71_DATA */
+ 0x05030000, /* DENALI_PI_72_DATA */
+ 0x070a0404, /* DENALI_PI_73_DATA */
+ 0x00000000, /* DENALI_PI_74_DATA */
+ 0x00000000, /* DENALI_PI_75_DATA */
+ 0x00000000, /* DENALI_PI_76_DATA */
+ 0x000f0f00, /* DENALI_PI_77_DATA */
+ 0x0000001e, /* DENALI_PI_78_DATA */
+ 0x00000000, /* DENALI_PI_79_DATA */
+ 0x01010300, /* DENALI_PI_80_DATA */
+ 0x00000000, /* DENALI_PI_81_DATA */
+ 0x00000000, /* DENALI_PI_82_DATA */
+ 0x01000000, /* DENALI_PI_83_DATA */
+ 0x00000101, /* DENALI_PI_84_DATA */
+ 0x55555a5a, /* DENALI_PI_85_DATA */
+ 0x55555a5a, /* DENALI_PI_86_DATA */
+ 0x55555a5a, /* DENALI_PI_87_DATA */
+ 0x55555a5a, /* DENALI_PI_88_DATA */
+ 0x0c050001, /* DENALI_PI_89_DATA */
+ 0x06020009, /* DENALI_PI_90_DATA */
+ 0x00010004, /* DENALI_PI_91_DATA */
+ 0x00000203, /* DENALI_PI_92_DATA */
+ 0x00030000, /* DENALI_PI_93_DATA */
+ 0x170f0000, /* DENALI_PI_94_DATA */
+ 0x00060018, /* DENALI_PI_95_DATA */
+ 0x000e0020, /* DENALI_PI_96_DATA */
+ 0x000a001c, /* DENALI_PI_97_DATA */
+ 0x00000000, /* DENALI_PI_98_DATA */
+ 0x00000000, /* DENALI_PI_99_DATA */
+ 0x00000100, /* DENALI_PI_100_DATA */
+ 0x140a0000, /* DENALI_PI_101_DATA */
+ 0x000d010a, /* DENALI_PI_102_DATA */
+ 0x0100c802, /* DENALI_PI_103_DATA */
+ 0x010a0064, /* DENALI_PI_104_DATA */
+ 0x000e0100, /* DENALI_PI_105_DATA */
+ 0x0100000e, /* DENALI_PI_106_DATA */
+ 0x00c900c9, /* DENALI_PI_107_DATA */
+ 0x00650100, /* DENALI_PI_108_DATA */
+ 0x1e1a0065, /* DENALI_PI_109_DATA */
+ 0x10010204, /* DENALI_PI_110_DATA */
+ 0x06070605, /* DENALI_PI_111_DATA */
+ 0x20000202, /* DENALI_PI_112_DATA */
+ 0x00201000, /* DENALI_PI_113_DATA */
+ 0x00201000, /* DENALI_PI_114_DATA */
+ 0x04041000, /* DENALI_PI_115_DATA */
+ 0x10020100, /* DENALI_PI_116_DATA */
+ 0x0003010c, /* DENALI_PI_117_DATA */
+ 0x004b004a, /* DENALI_PI_118_DATA */
+ 0x1a0f0000, /* DENALI_PI_119_DATA */
+ 0x0102041e, /* DENALI_PI_120_DATA */
+ 0x34000000, /* DENALI_PI_121_DATA */
+ 0x00000000, /* DENALI_PI_122_DATA */
+ 0x00000000, /* DENALI_PI_123_DATA */
+ 0x00010000, /* DENALI_PI_124_DATA */
+ 0x00000400, /* DENALI_PI_125_DATA */
+ 0x00310000, /* DENALI_PI_126_DATA */
+ 0x004d4d00, /* DENALI_PI_127_DATA */
+ 0x00120024, /* DENALI_PI_128_DATA */
+ 0x4d000031, /* DENALI_PI_129_DATA */
+ 0x0000144d, /* DENALI_PI_130_DATA */
+ 0x00310009, /* DENALI_PI_131_DATA */
+ 0x004d4d00, /* DENALI_PI_132_DATA */
+ 0x00000004, /* DENALI_PI_133_DATA */
+ 0x4d000031, /* DENALI_PI_134_DATA */
+ 0x0000244d, /* DENALI_PI_135_DATA */
+ 0x00310012, /* DENALI_PI_136_DATA */
+ 0x004d4d00, /* DENALI_PI_137_DATA */
+ 0x00090014, /* DENALI_PI_138_DATA */
+ 0x4d000031, /* DENALI_PI_139_DATA */
+ 0x0004004d, /* DENALI_PI_140_DATA */
+ 0x00310000, /* DENALI_PI_141_DATA */
+ 0x004d4d00, /* DENALI_PI_142_DATA */
+ 0x00120024, /* DENALI_PI_143_DATA */
+ 0x4d000031, /* DENALI_PI_144_DATA */
+ 0x0000144d, /* DENALI_PI_145_DATA */
+ 0x00310009, /* DENALI_PI_146_DATA */
+ 0x004d4d00, /* DENALI_PI_147_DATA */
+ 0x00000004, /* DENALI_PI_148_DATA */
+ 0x4d000031, /* DENALI_PI_149_DATA */
+ 0x0000244d, /* DENALI_PI_150_DATA */
+ 0x00310012, /* DENALI_PI_151_DATA */
+ 0x004d4d00, /* DENALI_PI_152_DATA */
+ 0x00090014, /* DENALI_PI_153_DATA */
+ 0x4d000031, /* DENALI_PI_154_DATA */
+ 0x0200004d, /* DENALI_PI_155_DATA */
+ 0x00c8000d, /* DENALI_PI_156_DATA */
+ 0x08080064, /* DENALI_PI_157_DATA */
+ 0x040a0404, /* DENALI_PI_158_DATA */
+ 0x03000d92, /* DENALI_PI_159_DATA */
+ 0x010a2001, /* DENALI_PI_160_DATA */
+ 0x0f11080a, /* DENALI_PI_161_DATA */
+ 0x0000110a, /* DENALI_PI_162_DATA */
+ 0x2200d92e, /* DENALI_PI_163_DATA */
+ 0x080c2003, /* DENALI_PI_164_DATA */
+ 0x0809080a, /* DENALI_PI_165_DATA */
+ 0x00000a0a, /* DENALI_PI_166_DATA */
+ 0x11006c97, /* DENALI_PI_167_DATA */
+ 0x040a2002, /* DENALI_PI_168_DATA */
+ 0x0200020a, /* DENALI_PI_169_DATA */
+ 0x02000200, /* DENALI_PI_170_DATA */
+ 0x02000200, /* DENALI_PI_171_DATA */
+ 0x02000200, /* DENALI_PI_172_DATA */
+ 0x02000200, /* DENALI_PI_173_DATA */
+ 0x00000000, /* DENALI_PI_174_DATA */
+ 0x00000000, /* DENALI_PI_175_DATA */
+ 0x00000000, /* DENALI_PI_176_DATA */
+ 0x00000000, /* DENALI_PI_177_DATA */
+ 0x00000000, /* DENALI_PI_178_DATA */
+ 0x00000000, /* DENALI_PI_179_DATA */
+ 0x00000000, /* DENALI_PI_180_DATA */
+ 0x00000000, /* DENALI_PI_181_DATA */
+ 0x00000000, /* DENALI_PI_182_DATA */
+ 0x00000000, /* DENALI_PI_183_DATA */
+ 0x00000000, /* DENALI_PI_184_DATA */
+ 0x00000000, /* DENALI_PI_185_DATA */
+ 0x01000400, /* DENALI_PI_186_DATA */
+ 0x00017600, /* DENALI_PI_187_DATA */
+ 0x00000e9c, /* DENALI_PI_188_DATA */
+ 0x00001850, /* DENALI_PI_189_DATA */
+ 0x0000f320, /* DENALI_PI_190_DATA */
+ 0x00000c20, /* DENALI_PI_191_DATA */
+ 0x00007940, /* DENALI_PI_192_DATA */
+ 0x08000000, /* DENALI_PI_193_DATA */
+ 0x00000100, /* DENALI_PI_194_DATA */
+ 0x00000000, /* DENALI_PI_195_DATA */
+ 0x00000000, /* DENALI_PI_196_DATA */
+ 0x00000000, /* DENALI_PI_197_DATA */
+ 0x00000000, /* DENALI_PI_198_DATA */
+ 0x00000002 /* DENALI_PI_199_DATA */
+ }
+ },
+ {
+ {
+ 0x76543210, /* DENALI_PHY_00_DATA */
+ 0x0004f008, /* DENALI_PHY_01_DATA */
+ 0x00020119, /* DENALI_PHY_02_DATA */
+ 0x00000000, /* DENALI_PHY_03_DATA */
+ 0x00000000, /* DENALI_PHY_04_DATA */
+ 0x00010000, /* DENALI_PHY_05_DATA */
+ 0x01665555, /* DENALI_PHY_06_DATA */
+ 0x03665555, /* DENALI_PHY_07_DATA */
+ 0x00010f00, /* DENALI_PHY_08_DATA */
+ 0x05010200, /* DENALI_PHY_09_DATA */
+ 0x00000002, /* DENALI_PHY_10_DATA */
+ 0x00170180, /* DENALI_PHY_11_DATA */
+ 0x00cc0201, /* DENALI_PHY_12_DATA */
+ 0x00030066, /* DENALI_PHY_13_DATA */
+ 0x00000000, /* DENALI_PHY_14_DATA */
+ 0x00000000, /* DENALI_PHY_15_DATA */
+ 0x00000000, /* DENALI_PHY_16_DATA */
+ 0x00000000, /* DENALI_PHY_17_DATA */
+ 0x00000000, /* DENALI_PHY_18_DATA */
+ 0x00000000, /* DENALI_PHY_19_DATA */
+ 0x00000000, /* DENALI_PHY_20_DATA */
+ 0x00000000, /* DENALI_PHY_21_DATA */
+ 0x04080000, /* DENALI_PHY_22_DATA */
+ 0x04080400, /* DENALI_PHY_23_DATA */
+ 0x30000000, /* DENALI_PHY_24_DATA */
+ 0x0c00c007, /* DENALI_PHY_25_DATA */
+ 0x00000100, /* DENALI_PHY_26_DATA */
+ 0x00000000, /* DENALI_PHY_27_DATA */
+ 0xfd02fe01, /* DENALI_PHY_28_DATA */
+ 0xf708fb04, /* DENALI_PHY_29_DATA */
+ 0xdf20ef10, /* DENALI_PHY_30_DATA */
+ 0x7f80bf40, /* DENALI_PHY_31_DATA */
+ 0x0001aaaa, /* DENALI_PHY_32_DATA */
+ 0x00000000, /* DENALI_PHY_33_DATA */
+ 0x00000000, /* DENALI_PHY_34_DATA */
+ 0x00000000, /* DENALI_PHY_35_DATA */
+ 0x00000000, /* DENALI_PHY_36_DATA */
+ 0x00000000, /* DENALI_PHY_37_DATA */
+ 0x00000000, /* DENALI_PHY_38_DATA */
+ 0x00000000, /* DENALI_PHY_39_DATA */
+ 0x00000000, /* DENALI_PHY_40_DATA */
+ 0x00000000, /* DENALI_PHY_41_DATA */
+ 0x00000000, /* DENALI_PHY_42_DATA */
+ 0x00000000, /* DENALI_PHY_43_DATA */
+ 0x00000000, /* DENALI_PHY_44_DATA */
+ 0x00000000, /* DENALI_PHY_45_DATA */
+ 0x00000000, /* DENALI_PHY_46_DATA */
+ 0x00000000, /* DENALI_PHY_47_DATA */
+ 0x00000000, /* DENALI_PHY_48_DATA */
+ 0x00000000, /* DENALI_PHY_49_DATA */
+ 0x00000000, /* DENALI_PHY_50_DATA */
+ 0x00000000, /* DENALI_PHY_51_DATA */
+ 0x00200000, /* DENALI_PHY_52_DATA */
+ 0x00000000, /* DENALI_PHY_53_DATA */
+ 0x00000000, /* DENALI_PHY_54_DATA */
+ 0x00000000, /* DENALI_PHY_55_DATA */
+ 0x00000000, /* DENALI_PHY_56_DATA */
+ 0x00000000, /* DENALI_PHY_57_DATA */
+ 0x00000000, /* DENALI_PHY_58_DATA */
+ 0x02800280, /* DENALI_PHY_59_DATA */
+ 0x02800280, /* DENALI_PHY_60_DATA */
+ 0x02800280, /* DENALI_PHY_61_DATA */
+ 0x02800280, /* DENALI_PHY_62_DATA */
+ 0x00000280, /* DENALI_PHY_63_DATA */
+ 0x00000000, /* DENALI_PHY_64_DATA */
+ 0x00000000, /* DENALI_PHY_65_DATA */
+ 0x00000000, /* DENALI_PHY_66_DATA */
+ 0x00000000, /* DENALI_PHY_67_DATA */
+ 0x00800000, /* DENALI_PHY_68_DATA */
+ 0x00800080, /* DENALI_PHY_69_DATA */
+ 0x00800080, /* DENALI_PHY_70_DATA */
+ 0x00800080, /* DENALI_PHY_71_DATA */
+ 0x00800080, /* DENALI_PHY_72_DATA */
+ 0x00800080, /* DENALI_PHY_73_DATA */
+ 0x00800080, /* DENALI_PHY_74_DATA */
+ 0x00800080, /* DENALI_PHY_75_DATA */
+ 0x00800080, /* DENALI_PHY_76_DATA */
+ 0x01190080, /* DENALI_PHY_77_DATA */
+ 0x00000002, /* DENALI_PHY_78_DATA */
+ 0x00000000, /* DENALI_PHY_79_DATA */
+ 0x00000000, /* DENALI_PHY_80_DATA */
+ 0x00000200, /* DENALI_PHY_81_DATA */
+ 0x00000000, /* DENALI_PHY_82_DATA */
+ 0x51315152, /* DENALI_PHY_83_DATA */
+ 0xc0013150, /* DENALI_PHY_84_DATA */
+ 0x020000c0, /* DENALI_PHY_85_DATA */
+ 0x00100001, /* DENALI_PHY_86_DATA */
+ 0x07054204, /* DENALI_PHY_87_DATA */
+ 0x000f0c18, /* DENALI_PHY_88_DATA */
+ 0x01000140, /* DENALI_PHY_89_DATA */
+ 0x00000c10, /* DENALI_PHY_90_DATA */
+ 0x00000000, /* DENALI_PHY_91_DATA */
+ 0x00000000, /* DENALI_PHY_92_DATA */
+ 0x00000000, /* DENALI_PHY_93_DATA */
+ 0x00000000, /* DENALI_PHY_94_DATA */
+ 0x00000000, /* DENALI_PHY_95_DATA */
+ 0x00000000, /* DENALI_PHY_96_DATA */
+ 0x00000000, /* DENALI_PHY_97_DATA */
+ 0x00000000, /* DENALI_PHY_98_DATA */
+ 0x00000000, /* DENALI_PHY_99_DATA */
+ 0x00000000, /* DENALI_PHY_100_DATA */
+ 0x00000000, /* DENALI_PHY_101_DATA */
+ 0x00000000, /* DENALI_PHY_102_DATA */
+ 0x00000000, /* DENALI_PHY_103_DATA */
+ 0x00000000, /* DENALI_PHY_104_DATA */
+ 0x00000000, /* DENALI_PHY_105_DATA */
+ 0x00000000, /* DENALI_PHY_106_DATA */
+ 0x00000000, /* DENALI_PHY_107_DATA */
+ 0x00000000, /* DENALI_PHY_108_DATA */
+ 0x00000000, /* DENALI_PHY_109_DATA */
+ 0x00000000, /* DENALI_PHY_110_DATA */
+ 0x00000000, /* DENALI_PHY_111_DATA */
+ 0x00000000, /* DENALI_PHY_112_DATA */
+ 0x00000000, /* DENALI_PHY_113_DATA */
+ 0x00000000, /* DENALI_PHY_114_DATA */
+ 0x00000000, /* DENALI_PHY_115_DATA */
+ 0x00000000, /* DENALI_PHY_116_DATA */
+ 0x00000000, /* DENALI_PHY_117_DATA */
+ 0x00000000, /* DENALI_PHY_118_DATA */
+ 0x00000000, /* DENALI_PHY_119_DATA */
+ 0x00000000, /* DENALI_PHY_120_DATA */
+ 0x00000000, /* DENALI_PHY_121_DATA */
+ 0x00000000, /* DENALI_PHY_122_DATA */
+ 0x00000000, /* DENALI_PHY_123_DATA */
+ 0x00000000, /* DENALI_PHY_124_DATA */
+ 0x00000000, /* DENALI_PHY_125_DATA */
+ 0x00000000, /* DENALI_PHY_126_DATA */
+ 0x00000000, /* DENALI_PHY_127_DATA */
+ 0x76543210, /* DENALI_PHY_128_DATA */
+ 0x0004f008, /* DENALI_PHY_129_DATA */
+ 0x00020119, /* DENALI_PHY_130_DATA */
+ 0x00000000, /* DENALI_PHY_131_DATA */
+ 0x00000000, /* DENALI_PHY_132_DATA */
+ 0x00010000, /* DENALI_PHY_133_DATA */
+ 0x01665555, /* DENALI_PHY_134_DATA */
+ 0x03665555, /* DENALI_PHY_135_DATA */
+ 0x00010f00, /* DENALI_PHY_136_DATA */
+ 0x05010200, /* DENALI_PHY_137_DATA */
+ 0x00000002, /* DENALI_PHY_138_DATA */
+ 0x00170180, /* DENALI_PHY_139_DATA */
+ 0x00cc0201, /* DENALI_PHY_140_DATA */
+ 0x00030066, /* DENALI_PHY_141_DATA */
+ 0x00000000, /* DENALI_PHY_142_DATA */
+ 0x00000000, /* DENALI_PHY_143_DATA */
+ 0x00000000, /* DENALI_PHY_144_DATA */
+ 0x00000000, /* DENALI_PHY_145_DATA */
+ 0x00000000, /* DENALI_PHY_146_DATA */
+ 0x00000000, /* DENALI_PHY_147_DATA */
+ 0x00000000, /* DENALI_PHY_148_DATA */
+ 0x00000000, /* DENALI_PHY_149_DATA */
+ 0x04080000, /* DENALI_PHY_150_DATA */
+ 0x04080400, /* DENALI_PHY_151_DATA */
+ 0x30000000, /* DENALI_PHY_152_DATA */
+ 0x0c00c007, /* DENALI_PHY_153_DATA */
+ 0x00000100, /* DENALI_PHY_154_DATA */
+ 0x00000000, /* DENALI_PHY_155_DATA */
+ 0xfd02fe01, /* DENALI_PHY_156_DATA */
+ 0xf708fb04, /* DENALI_PHY_157_DATA */
+ 0xdf20ef10, /* DENALI_PHY_158_DATA */
+ 0x7f80bf40, /* DENALI_PHY_159_DATA */
+ 0x0000aaaa, /* DENALI_PHY_160_DATA */
+ 0x00000000, /* DENALI_PHY_161_DATA */
+ 0x00000000, /* DENALI_PHY_162_DATA */
+ 0x00000000, /* DENALI_PHY_163_DATA */
+ 0x00000000, /* DENALI_PHY_164_DATA */
+ 0x00000000, /* DENALI_PHY_165_DATA */
+ 0x00000000, /* DENALI_PHY_166_DATA */
+ 0x00000000, /* DENALI_PHY_167_DATA */
+ 0x00000000, /* DENALI_PHY_168_DATA */
+ 0x00000000, /* DENALI_PHY_169_DATA */
+ 0x00000000, /* DENALI_PHY_170_DATA */
+ 0x00000000, /* DENALI_PHY_171_DATA */
+ 0x00000000, /* DENALI_PHY_172_DATA */
+ 0x00000000, /* DENALI_PHY_173_DATA */
+ 0x00000000, /* DENALI_PHY_174_DATA */
+ 0x00000000, /* DENALI_PHY_175_DATA */
+ 0x00000000, /* DENALI_PHY_176_DATA */
+ 0x00000000, /* DENALI_PHY_177_DATA */
+ 0x00000000, /* DENALI_PHY_178_DATA */
+ 0x00000000, /* DENALI_PHY_179_DATA */
+ 0x00200000, /* DENALI_PHY_180_DATA */
+ 0x00000000, /* DENALI_PHY_181_DATA */
+ 0x00000000, /* DENALI_PHY_182_DATA */
+ 0x00000000, /* DENALI_PHY_183_DATA */
+ 0x00000000, /* DENALI_PHY_184_DATA */
+ 0x00000000, /* DENALI_PHY_185_DATA */
+ 0x00000000, /* DENALI_PHY_186_DATA */
+ 0x02800280, /* DENALI_PHY_187_DATA */
+ 0x02800280, /* DENALI_PHY_188_DATA */
+ 0x02800280, /* DENALI_PHY_189_DATA */
+ 0x02800280, /* DENALI_PHY_190_DATA */
+ 0x00000280, /* DENALI_PHY_191_DATA */
+ 0x00000000, /* DENALI_PHY_192_DATA */
+ 0x00000000, /* DENALI_PHY_193_DATA */
+ 0x00000000, /* DENALI_PHY_194_DATA */
+ 0x00000000, /* DENALI_PHY_195_DATA */
+ 0x00800000, /* DENALI_PHY_196_DATA */
+ 0x00800080, /* DENALI_PHY_197_DATA */
+ 0x00800080, /* DENALI_PHY_198_DATA */
+ 0x00800080, /* DENALI_PHY_199_DATA */
+ 0x00800080, /* DENALI_PHY_200_DATA */
+ 0x00800080, /* DENALI_PHY_201_DATA */
+ 0x00800080, /* DENALI_PHY_202_DATA */
+ 0x00800080, /* DENALI_PHY_203_DATA */
+ 0x00800080, /* DENALI_PHY_204_DATA */
+ 0x01190080, /* DENALI_PHY_205_DATA */
+ 0x00000002, /* DENALI_PHY_206_DATA */
+ 0x00000000, /* DENALI_PHY_207_DATA */
+ 0x00000000, /* DENALI_PHY_208_DATA */
+ 0x00000200, /* DENALI_PHY_209_DATA */
+ 0x00000000, /* DENALI_PHY_210_DATA */
+ 0x51315152, /* DENALI_PHY_211_DATA */
+ 0xc0013150, /* DENALI_PHY_212_DATA */
+ 0x020000c0, /* DENALI_PHY_213_DATA */
+ 0x00100001, /* DENALI_PHY_214_DATA */
+ 0x07054204, /* DENALI_PHY_215_DATA */
+ 0x000f0c18, /* DENALI_PHY_216_DATA */
+ 0x01000140, /* DENALI_PHY_217_DATA */
+ 0x00000c10, /* DENALI_PHY_218_DATA */
+ 0x00000000, /* DENALI_PHY_219_DATA */
+ 0x00000000, /* DENALI_PHY_220_DATA */
+ 0x00000000, /* DENALI_PHY_221_DATA */
+ 0x00000000, /* DENALI_PHY_222_DATA */
+ 0x00000000, /* DENALI_PHY_223_DATA */
+ 0x00000000, /* DENALI_PHY_224_DATA */
+ 0x00000000, /* DENALI_PHY_225_DATA */
+ 0x00000000, /* DENALI_PHY_226_DATA */
+ 0x00000000, /* DENALI_PHY_227_DATA */
+ 0x00000000, /* DENALI_PHY_228_DATA */
+ 0x00000000, /* DENALI_PHY_229_DATA */
+ 0x00000000, /* DENALI_PHY_230_DATA */
+ 0x00000000, /* DENALI_PHY_231_DATA */
+ 0x00000000, /* DENALI_PHY_232_DATA */
+ 0x00000000, /* DENALI_PHY_233_DATA */
+ 0x00000000, /* DENALI_PHY_234_DATA */
+ 0x00000000, /* DENALI_PHY_235_DATA */
+ 0x00000000, /* DENALI_PHY_236_DATA */
+ 0x00000000, /* DENALI_PHY_237_DATA */
+ 0x00000000, /* DENALI_PHY_238_DATA */
+ 0x00000000, /* DENALI_PHY_239_DATA */
+ 0x00000000, /* DENALI_PHY_240_DATA */
+ 0x00000000, /* DENALI_PHY_241_DATA */
+ 0x00000000, /* DENALI_PHY_242_DATA */
+ 0x00000000, /* DENALI_PHY_243_DATA */
+ 0x00000000, /* DENALI_PHY_244_DATA */
+ 0x00000000, /* DENALI_PHY_245_DATA */
+ 0x00000000, /* DENALI_PHY_246_DATA */
+ 0x00000000, /* DENALI_PHY_247_DATA */
+ 0x00000000, /* DENALI_PHY_248_DATA */
+ 0x00000000, /* DENALI_PHY_249_DATA */
+ 0x00000000, /* DENALI_PHY_250_DATA */
+ 0x00000000, /* DENALI_PHY_251_DATA */
+ 0x00000000, /* DENALI_PHY_252_DATA */
+ 0x00000000, /* DENALI_PHY_253_DATA */
+ 0x00000000, /* DENALI_PHY_254_DATA */
+ 0x00000000, /* DENALI_PHY_255_DATA */
+ 0x76543210, /* DENALI_PHY_256_DATA */
+ 0x0004f008, /* DENALI_PHY_257_DATA */
+ 0x00020119, /* DENALI_PHY_258_DATA */
+ 0x00000000, /* DENALI_PHY_259_DATA */
+ 0x00000000, /* DENALI_PHY_260_DATA */
+ 0x00010000, /* DENALI_PHY_261_DATA */
+ 0x01665555, /* DENALI_PHY_262_DATA */
+ 0x03665555, /* DENALI_PHY_263_DATA */
+ 0x00010f00, /* DENALI_PHY_264_DATA */
+ 0x05010200, /* DENALI_PHY_265_DATA */
+ 0x00000002, /* DENALI_PHY_266_DATA */
+ 0x00170180, /* DENALI_PHY_267_DATA */
+ 0x00cc0201, /* DENALI_PHY_268_DATA */
+ 0x00030066, /* DENALI_PHY_269_DATA */
+ 0x00000000, /* DENALI_PHY_270_DATA */
+ 0x00000000, /* DENALI_PHY_271_DATA */
+ 0x00000000, /* DENALI_PHY_272_DATA */
+ 0x00000000, /* DENALI_PHY_273_DATA */
+ 0x00000000, /* DENALI_PHY_274_DATA */
+ 0x00000000, /* DENALI_PHY_275_DATA */
+ 0x00000000, /* DENALI_PHY_276_DATA */
+ 0x00000000, /* DENALI_PHY_277_DATA */
+ 0x04080000, /* DENALI_PHY_278_DATA */
+ 0x04080400, /* DENALI_PHY_279_DATA */
+ 0x30000000, /* DENALI_PHY_280_DATA */
+ 0x0c00c007, /* DENALI_PHY_281_DATA */
+ 0x00000100, /* DENALI_PHY_282_DATA */
+ 0x00000000, /* DENALI_PHY_283_DATA */
+ 0xfd02fe01, /* DENALI_PHY_284_DATA */
+ 0xf708fb04, /* DENALI_PHY_285_DATA */
+ 0xdf20ef10, /* DENALI_PHY_286_DATA */
+ 0x7f80bf40, /* DENALI_PHY_287_DATA */
+ 0x0001aaaa, /* DENALI_PHY_288_DATA */
+ 0x00000000, /* DENALI_PHY_289_DATA */
+ 0x00000000, /* DENALI_PHY_290_DATA */
+ 0x00000000, /* DENALI_PHY_291_DATA */
+ 0x00000000, /* DENALI_PHY_292_DATA */
+ 0x00000000, /* DENALI_PHY_293_DATA */
+ 0x00000000, /* DENALI_PHY_294_DATA */
+ 0x00000000, /* DENALI_PHY_295_DATA */
+ 0x00000000, /* DENALI_PHY_296_DATA */
+ 0x00000000, /* DENALI_PHY_297_DATA */
+ 0x00000000, /* DENALI_PHY_298_DATA */
+ 0x00000000, /* DENALI_PHY_299_DATA */
+ 0x00000000, /* DENALI_PHY_300_DATA */
+ 0x00000000, /* DENALI_PHY_301_DATA */
+ 0x00000000, /* DENALI_PHY_302_DATA */
+ 0x00000000, /* DENALI_PHY_303_DATA */
+ 0x00000000, /* DENALI_PHY_304_DATA */
+ 0x00000000, /* DENALI_PHY_305_DATA */
+ 0x00000000, /* DENALI_PHY_306_DATA */
+ 0x00000000, /* DENALI_PHY_307_DATA */
+ 0x00200000, /* DENALI_PHY_308_DATA */
+ 0x00000000, /* DENALI_PHY_309_DATA */
+ 0x00000000, /* DENALI_PHY_310_DATA */
+ 0x00000000, /* DENALI_PHY_311_DATA */
+ 0x00000000, /* DENALI_PHY_312_DATA */
+ 0x00000000, /* DENALI_PHY_313_DATA */
+ 0x00000000, /* DENALI_PHY_314_DATA */
+ 0x02800280, /* DENALI_PHY_315_DATA */
+ 0x02800280, /* DENALI_PHY_316_DATA */
+ 0x02800280, /* DENALI_PHY_317_DATA */
+ 0x02800280, /* DENALI_PHY_318_DATA */
+ 0x00000280, /* DENALI_PHY_319_DATA */
+ 0x00000000, /* DENALI_PHY_320_DATA */
+ 0x00000000, /* DENALI_PHY_321_DATA */
+ 0x00000000, /* DENALI_PHY_322_DATA */
+ 0x00000000, /* DENALI_PHY_323_DATA */
+ 0x00800000, /* DENALI_PHY_324_DATA */
+ 0x00800080, /* DENALI_PHY_325_DATA */
+ 0x00800080, /* DENALI_PHY_326_DATA */
+ 0x00800080, /* DENALI_PHY_327_DATA */
+ 0x00800080, /* DENALI_PHY_328_DATA */
+ 0x00800080, /* DENALI_PHY_329_DATA */
+ 0x00800080, /* DENALI_PHY_330_DATA */
+ 0x00800080, /* DENALI_PHY_331_DATA */
+ 0x00800080, /* DENALI_PHY_332_DATA */
+ 0x01190080, /* DENALI_PHY_333_DATA */
+ 0x00000002, /* DENALI_PHY_334_DATA */
+ 0x00000000, /* DENALI_PHY_335_DATA */
+ 0x00000000, /* DENALI_PHY_336_DATA */
+ 0x00000200, /* DENALI_PHY_337_DATA */
+ 0x00000000, /* DENALI_PHY_338_DATA */
+ 0x51315152, /* DENALI_PHY_339_DATA */
+ 0xc0013150, /* DENALI_PHY_340_DATA */
+ 0x020000c0, /* DENALI_PHY_341_DATA */
+ 0x00100001, /* DENALI_PHY_342_DATA */
+ 0x07054204, /* DENALI_PHY_343_DATA */
+ 0x000f0c18, /* DENALI_PHY_344_DATA */
+ 0x01000140, /* DENALI_PHY_345_DATA */
+ 0x00000c10, /* DENALI_PHY_346_DATA */
+ 0x00000000, /* DENALI_PHY_347_DATA */
+ 0x00000000, /* DENALI_PHY_348_DATA */
+ 0x00000000, /* DENALI_PHY_349_DATA */
+ 0x00000000, /* DENALI_PHY_350_DATA */
+ 0x00000000, /* DENALI_PHY_351_DATA */
+ 0x00000000, /* DENALI_PHY_352_DATA */
+ 0x00000000, /* DENALI_PHY_353_DATA */
+ 0x00000000, /* DENALI_PHY_354_DATA */
+ 0x00000000, /* DENALI_PHY_355_DATA */
+ 0x00000000, /* DENALI_PHY_356_DATA */
+ 0x00000000, /* DENALI_PHY_357_DATA */
+ 0x00000000, /* DENALI_PHY_358_DATA */
+ 0x00000000, /* DENALI_PHY_359_DATA */
+ 0x00000000, /* DENALI_PHY_360_DATA */
+ 0x00000000, /* DENALI_PHY_361_DATA */
+ 0x00000000, /* DENALI_PHY_362_DATA */
+ 0x00000000, /* DENALI_PHY_363_DATA */
+ 0x00000000, /* DENALI_PHY_364_DATA */
+ 0x00000000, /* DENALI_PHY_365_DATA */
+ 0x00000000, /* DENALI_PHY_366_DATA */
+ 0x00000000, /* DENALI_PHY_367_DATA */
+ 0x00000000, /* DENALI_PHY_368_DATA */
+ 0x00000000, /* DENALI_PHY_369_DATA */
+ 0x00000000, /* DENALI_PHY_370_DATA */
+ 0x00000000, /* DENALI_PHY_371_DATA */
+ 0x00000000, /* DENALI_PHY_372_DATA */
+ 0x00000000, /* DENALI_PHY_373_DATA */
+ 0x00000000, /* DENALI_PHY_374_DATA */
+ 0x00000000, /* DENALI_PHY_375_DATA */
+ 0x00000000, /* DENALI_PHY_376_DATA */
+ 0x00000000, /* DENALI_PHY_377_DATA */
+ 0x00000000, /* DENALI_PHY_378_DATA */
+ 0x00000000, /* DENALI_PHY_379_DATA */
+ 0x00000000, /* DENALI_PHY_380_DATA */
+ 0x00000000, /* DENALI_PHY_381_DATA */
+ 0x00000000, /* DENALI_PHY_382_DATA */
+ 0x00000000, /* DENALI_PHY_383_DATA */
+ 0x76543210, /* DENALI_PHY_384_DATA */
+ 0x0004f008, /* DENALI_PHY_385_DATA */
+ 0x00020119, /* DENALI_PHY_386_DATA */
+ 0x00000000, /* DENALI_PHY_387_DATA */
+ 0x00000000, /* DENALI_PHY_388_DATA */
+ 0x00010000, /* DENALI_PHY_389_DATA */
+ 0x01665555, /* DENALI_PHY_390_DATA */
+ 0x03665555, /* DENALI_PHY_391_DATA */
+ 0x00010f00, /* DENALI_PHY_392_DATA */
+ 0x05010200, /* DENALI_PHY_393_DATA */
+ 0x00000002, /* DENALI_PHY_394_DATA */
+ 0x00170180, /* DENALI_PHY_395_DATA */
+ 0x00cc0201, /* DENALI_PHY_396_DATA */
+ 0x00030066, /* DENALI_PHY_397_DATA */
+ 0x00000000, /* DENALI_PHY_398_DATA */
+ 0x00000000, /* DENALI_PHY_399_DATA */
+ 0x00000000, /* DENALI_PHY_400_DATA */
+ 0x00000000, /* DENALI_PHY_401_DATA */
+ 0x00000000, /* DENALI_PHY_402_DATA */
+ 0x00000000, /* DENALI_PHY_403_DATA */
+ 0x00000000, /* DENALI_PHY_404_DATA */
+ 0x00000000, /* DENALI_PHY_405_DATA */
+ 0x04080000, /* DENALI_PHY_406_DATA */
+ 0x04080400, /* DENALI_PHY_407_DATA */
+ 0x30000000, /* DENALI_PHY_408_DATA */
+ 0x0c00c007, /* DENALI_PHY_409_DATA */
+ 0x00000100, /* DENALI_PHY_410_DATA */
+ 0x00000000, /* DENALI_PHY_411_DATA */
+ 0xfd02fe01, /* DENALI_PHY_412_DATA */
+ 0xf708fb04, /* DENALI_PHY_413_DATA */
+ 0xdf20ef10, /* DENALI_PHY_414_DATA */
+ 0x7f80bf40, /* DENALI_PHY_415_DATA */
+ 0x0000aaaa, /* DENALI_PHY_416_DATA */
+ 0x00000000, /* DENALI_PHY_417_DATA */
+ 0x00000000, /* DENALI_PHY_418_DATA */
+ 0x00000000, /* DENALI_PHY_419_DATA */
+ 0x00000000, /* DENALI_PHY_420_DATA */
+ 0x00000000, /* DENALI_PHY_421_DATA */
+ 0x00000000, /* DENALI_PHY_422_DATA */
+ 0x00000000, /* DENALI_PHY_423_DATA */
+ 0x00000000, /* DENALI_PHY_424_DATA */
+ 0x00000000, /* DENALI_PHY_425_DATA */
+ 0x00000000, /* DENALI_PHY_426_DATA */
+ 0x00000000, /* DENALI_PHY_427_DATA */
+ 0x00000000, /* DENALI_PHY_428_DATA */
+ 0x00000000, /* DENALI_PHY_429_DATA */
+ 0x00000000, /* DENALI_PHY_430_DATA */
+ 0x00000000, /* DENALI_PHY_431_DATA */
+ 0x00000000, /* DENALI_PHY_432_DATA */
+ 0x00000000, /* DENALI_PHY_433_DATA */
+ 0x00000000, /* DENALI_PHY_434_DATA */
+ 0x00000000, /* DENALI_PHY_435_DATA */
+ 0x00200000, /* DENALI_PHY_436_DATA */
+ 0x00000000, /* DENALI_PHY_437_DATA */
+ 0x00000000, /* DENALI_PHY_438_DATA */
+ 0x00000000, /* DENALI_PHY_439_DATA */
+ 0x00000000, /* DENALI_PHY_440_DATA */
+ 0x00000000, /* DENALI_PHY_441_DATA */
+ 0x00000000, /* DENALI_PHY_442_DATA */
+ 0x02800280, /* DENALI_PHY_443_DATA */
+ 0x02800280, /* DENALI_PHY_444_DATA */
+ 0x02800280, /* DENALI_PHY_445_DATA */
+ 0x02800280, /* DENALI_PHY_446_DATA */
+ 0x00000280, /* DENALI_PHY_447_DATA */
+ 0x00000000, /* DENALI_PHY_448_DATA */
+ 0x00000000, /* DENALI_PHY_449_DATA */
+ 0x00000000, /* DENALI_PHY_450_DATA */
+ 0x00000000, /* DENALI_PHY_451_DATA */
+ 0x00800000, /* DENALI_PHY_452_DATA */
+ 0x00800080, /* DENALI_PHY_453_DATA */
+ 0x00800080, /* DENALI_PHY_454_DATA */
+ 0x00800080, /* DENALI_PHY_455_DATA */
+ 0x00800080, /* DENALI_PHY_456_DATA */
+ 0x00800080, /* DENALI_PHY_457_DATA */
+ 0x00800080, /* DENALI_PHY_458_DATA */
+ 0x00800080, /* DENALI_PHY_459_DATA */
+ 0x00800080, /* DENALI_PHY_460_DATA */
+ 0x01190080, /* DENALI_PHY_461_DATA */
+ 0x00000002, /* DENALI_PHY_462_DATA */
+ 0x00000000, /* DENALI_PHY_463_DATA */
+ 0x00000000, /* DENALI_PHY_464_DATA */
+ 0x00000200, /* DENALI_PHY_465_DATA */
+ 0x00000000, /* DENALI_PHY_466_DATA */
+ 0x51315152, /* DENALI_PHY_467_DATA */
+ 0xc0013150, /* DENALI_PHY_468_DATA */
+ 0x020000c0, /* DENALI_PHY_469_DATA */
+ 0x00100001, /* DENALI_PHY_470_DATA */
+ 0x07054204, /* DENALI_PHY_471_DATA */
+ 0x000f0c18, /* DENALI_PHY_472_DATA */
+ 0x01000140, /* DENALI_PHY_473_DATA */
+ 0x00000c10, /* DENALI_PHY_474_DATA */
+ 0x00000000, /* DENALI_PHY_475_DATA */
+ 0x00000000, /* DENALI_PHY_476_DATA */
+ 0x00000000, /* DENALI_PHY_477_DATA */
+ 0x00000000, /* DENALI_PHY_478_DATA */
+ 0x00000000, /* DENALI_PHY_479_DATA */
+ 0x00000000, /* DENALI_PHY_480_DATA */
+ 0x00000000, /* DENALI_PHY_481_DATA */
+ 0x00000000, /* DENALI_PHY_482_DATA */
+ 0x00000000, /* DENALI_PHY_483_DATA */
+ 0x00000000, /* DENALI_PHY_484_DATA */
+ 0x00000000, /* DENALI_PHY_485_DATA */
+ 0x00000000, /* DENALI_PHY_486_DATA */
+ 0x00000000, /* DENALI_PHY_487_DATA */
+ 0x00000000, /* DENALI_PHY_488_DATA */
+ 0x00000000, /* DENALI_PHY_489_DATA */
+ 0x00000000, /* DENALI_PHY_490_DATA */
+ 0x00000000, /* DENALI_PHY_491_DATA */
+ 0x00000000, /* DENALI_PHY_492_DATA */
+ 0x00000000, /* DENALI_PHY_493_DATA */
+ 0x00000000, /* DENALI_PHY_494_DATA */
+ 0x00000000, /* DENALI_PHY_495_DATA */
+ 0x00000000, /* DENALI_PHY_496_DATA */
+ 0x00000000, /* DENALI_PHY_497_DATA */
+ 0x00000000, /* DENALI_PHY_498_DATA */
+ 0x00000000, /* DENALI_PHY_499_DATA */
+ 0x00000000, /* DENALI_PHY_500_DATA */
+ 0x00000000, /* DENALI_PHY_501_DATA */
+ 0x00000000, /* DENALI_PHY_502_DATA */
+ 0x00000000, /* DENALI_PHY_503_DATA */
+ 0x00000000, /* DENALI_PHY_504_DATA */
+ 0x00000000, /* DENALI_PHY_505_DATA */
+ 0x00000000, /* DENALI_PHY_506_DATA */
+ 0x00000000, /* DENALI_PHY_507_DATA */
+ 0x00000000, /* DENALI_PHY_508_DATA */
+ 0x00000000, /* DENALI_PHY_509_DATA */
+ 0x00000000, /* DENALI_PHY_510_DATA */
+ 0x00000000, /* DENALI_PHY_511_DATA */
+ 0x00000000, /* DENALI_PHY_512_DATA */
+ 0x00000000, /* DENALI_PHY_513_DATA */
+ 0x00000000, /* DENALI_PHY_514_DATA */
+ 0x00000000, /* DENALI_PHY_515_DATA */
+ 0x00000000, /* DENALI_PHY_516_DATA */
+ 0x00000000, /* DENALI_PHY_517_DATA */
+ 0x00000000, /* DENALI_PHY_518_DATA */
+ 0x00000002, /* DENALI_PHY_519_DATA */
+ 0x00000000, /* DENALI_PHY_520_DATA */
+ 0x00000000, /* DENALI_PHY_521_DATA */
+ 0x00000000, /* DENALI_PHY_522_DATA */
+ 0x00400320, /* DENALI_PHY_523_DATA */
+ 0x00000040, /* DENALI_PHY_524_DATA */
+ 0x00dcba98, /* DENALI_PHY_525_DATA */
+ 0x00000000, /* DENALI_PHY_526_DATA */
+ 0x00dcba98, /* DENALI_PHY_527_DATA */
+ 0x01000000, /* DENALI_PHY_528_DATA */
+ 0x00020003, /* DENALI_PHY_529_DATA */
+ 0x00000000, /* DENALI_PHY_530_DATA */
+ 0x00000000, /* DENALI_PHY_531_DATA */
+ 0x00000000, /* DENALI_PHY_532_DATA */
+ 0x0000002a, /* DENALI_PHY_533_DATA */
+ 0x00000015, /* DENALI_PHY_534_DATA */
+ 0x00000015, /* DENALI_PHY_535_DATA */
+ 0x0000002a, /* DENALI_PHY_536_DATA */
+ 0x00000033, /* DENALI_PHY_537_DATA */
+ 0x0000000c, /* DENALI_PHY_538_DATA */
+ 0x0000000c, /* DENALI_PHY_539_DATA */
+ 0x00000033, /* DENALI_PHY_540_DATA */
+ 0x0a418820, /* DENALI_PHY_541_DATA */
+ 0x003f0000, /* DENALI_PHY_542_DATA */
+ 0x0000003f, /* DENALI_PHY_543_DATA */
+ 0x00030055, /* DENALI_PHY_544_DATA */
+ 0x03000300, /* DENALI_PHY_545_DATA */
+ 0x03000300, /* DENALI_PHY_546_DATA */
+ 0x00000300, /* DENALI_PHY_547_DATA */
+ 0x42080010, /* DENALI_PHY_548_DATA */
+ 0x00000003, /* DENALI_PHY_549_DATA */
+ 0x00000000, /* DENALI_PHY_550_DATA */
+ 0x00000000, /* DENALI_PHY_551_DATA */
+ 0x00000000, /* DENALI_PHY_552_DATA */
+ 0x00000000, /* DENALI_PHY_553_DATA */
+ 0x00000000, /* DENALI_PHY_554_DATA */
+ 0x00000000, /* DENALI_PHY_555_DATA */
+ 0x00000000, /* DENALI_PHY_556_DATA */
+ 0x00000000, /* DENALI_PHY_557_DATA */
+ 0x00000000, /* DENALI_PHY_558_DATA */
+ 0x00000000, /* DENALI_PHY_559_DATA */
+ 0x00000000, /* DENALI_PHY_560_DATA */
+ 0x00000000, /* DENALI_PHY_561_DATA */
+ 0x00000000, /* DENALI_PHY_562_DATA */
+ 0x00000000, /* DENALI_PHY_563_DATA */
+ 0x00000000, /* DENALI_PHY_564_DATA */
+ 0x00000000, /* DENALI_PHY_565_DATA */
+ 0x00000000, /* DENALI_PHY_566_DATA */
+ 0x00000000, /* DENALI_PHY_567_DATA */
+ 0x00000000, /* DENALI_PHY_568_DATA */
+ 0x00000000, /* DENALI_PHY_569_DATA */
+ 0x00000000, /* DENALI_PHY_570_DATA */
+ 0x00000000, /* DENALI_PHY_571_DATA */
+ 0x00000000, /* DENALI_PHY_572_DATA */
+ 0x00000000, /* DENALI_PHY_573_DATA */
+ 0x00000000, /* DENALI_PHY_574_DATA */
+ 0x00000000, /* DENALI_PHY_575_DATA */
+ 0x00000000, /* DENALI_PHY_576_DATA */
+ 0x00000000, /* DENALI_PHY_577_DATA */
+ 0x00000000, /* DENALI_PHY_578_DATA */
+ 0x00000000, /* DENALI_PHY_579_DATA */
+ 0x00000000, /* DENALI_PHY_580_DATA */
+ 0x00000000, /* DENALI_PHY_581_DATA */
+ 0x00000000, /* DENALI_PHY_582_DATA */
+ 0x00000000, /* DENALI_PHY_583_DATA */
+ 0x00000000, /* DENALI_PHY_584_DATA */
+ 0x00000000, /* DENALI_PHY_585_DATA */
+ 0x00000000, /* DENALI_PHY_586_DATA */
+ 0x00000000, /* DENALI_PHY_587_DATA */
+ 0x00000000, /* DENALI_PHY_588_DATA */
+ 0x00000000, /* DENALI_PHY_589_DATA */
+ 0x00000000, /* DENALI_PHY_590_DATA */
+ 0x00000000, /* DENALI_PHY_591_DATA */
+ 0x00000000, /* DENALI_PHY_592_DATA */
+ 0x00000000, /* DENALI_PHY_593_DATA */
+ 0x00000000, /* DENALI_PHY_594_DATA */
+ 0x00000000, /* DENALI_PHY_595_DATA */
+ 0x00000000, /* DENALI_PHY_596_DATA */
+ 0x00000000, /* DENALI_PHY_597_DATA */
+ 0x00000000, /* DENALI_PHY_598_DATA */
+ 0x00000000, /* DENALI_PHY_599_DATA */
+ 0x00000000, /* DENALI_PHY_600_DATA */
+ 0x00000000, /* DENALI_PHY_601_DATA */
+ 0x00000000, /* DENALI_PHY_602_DATA */
+ 0x00000000, /* DENALI_PHY_603_DATA */
+ 0x00000000, /* DENALI_PHY_604_DATA */
+ 0x00000000, /* DENALI_PHY_605_DATA */
+ 0x00000000, /* DENALI_PHY_606_DATA */
+ 0x00000000, /* DENALI_PHY_607_DATA */
+ 0x00000000, /* DENALI_PHY_608_DATA */
+ 0x00000000, /* DENALI_PHY_609_DATA */
+ 0x00000000, /* DENALI_PHY_610_DATA */
+ 0x00000000, /* DENALI_PHY_611_DATA */
+ 0x00000000, /* DENALI_PHY_612_DATA */
+ 0x00000000, /* DENALI_PHY_613_DATA */
+ 0x00000000, /* DENALI_PHY_614_DATA */
+ 0x00000000, /* DENALI_PHY_615_DATA */
+ 0x00000000, /* DENALI_PHY_616_DATA */
+ 0x00000000, /* DENALI_PHY_617_DATA */
+ 0x00000000, /* DENALI_PHY_618_DATA */
+ 0x00000000, /* DENALI_PHY_619_DATA */
+ 0x00000000, /* DENALI_PHY_620_DATA */
+ 0x00000000, /* DENALI_PHY_621_DATA */
+ 0x00000000, /* DENALI_PHY_622_DATA */
+ 0x00000000, /* DENALI_PHY_623_DATA */
+ 0x00000000, /* DENALI_PHY_624_DATA */
+ 0x00000000, /* DENALI_PHY_625_DATA */
+ 0x00000000, /* DENALI_PHY_626_DATA */
+ 0x00000000, /* DENALI_PHY_627_DATA */
+ 0x00000000, /* DENALI_PHY_628_DATA */
+ 0x00000000, /* DENALI_PHY_629_DATA */
+ 0x00000000, /* DENALI_PHY_630_DATA */
+ 0x00000000, /* DENALI_PHY_631_DATA */
+ 0x00000000, /* DENALI_PHY_632_DATA */
+ 0x00000000, /* DENALI_PHY_633_DATA */
+ 0x00000000, /* DENALI_PHY_634_DATA */
+ 0x00000000, /* DENALI_PHY_635_DATA */
+ 0x00000000, /* DENALI_PHY_636_DATA */
+ 0x00000000, /* DENALI_PHY_637_DATA */
+ 0x00000000, /* DENALI_PHY_638_DATA */
+ 0x00000000, /* DENALI_PHY_639_DATA */
+ 0x00000000, /* DENALI_PHY_640_DATA */
+ 0x00000000, /* DENALI_PHY_641_DATA */
+ 0x00000000, /* DENALI_PHY_642_DATA */
+ 0x00000000, /* DENALI_PHY_643_DATA */
+ 0x00000000, /* DENALI_PHY_644_DATA */
+ 0x00000000, /* DENALI_PHY_645_DATA */
+ 0x00000000, /* DENALI_PHY_646_DATA */
+ 0x00000002, /* DENALI_PHY_647_DATA */
+ 0x00000000, /* DENALI_PHY_648_DATA */
+ 0x00000000, /* DENALI_PHY_649_DATA */
+ 0x00000000, /* DENALI_PHY_650_DATA */
+ 0x00400320, /* DENALI_PHY_651_DATA */
+ 0x00000040, /* DENALI_PHY_652_DATA */
+ 0x00000000, /* DENALI_PHY_653_DATA */
+ 0x00000000, /* DENALI_PHY_654_DATA */
+ 0x00000000, /* DENALI_PHY_655_DATA */
+ 0x01000000, /* DENALI_PHY_656_DATA */
+ 0x00020003, /* DENALI_PHY_657_DATA */
+ 0x00000000, /* DENALI_PHY_658_DATA */
+ 0x00000000, /* DENALI_PHY_659_DATA */
+ 0x00000000, /* DENALI_PHY_660_DATA */
+ 0x0000002a, /* DENALI_PHY_661_DATA */
+ 0x00000015, /* DENALI_PHY_662_DATA */
+ 0x00000015, /* DENALI_PHY_663_DATA */
+ 0x0000002a, /* DENALI_PHY_664_DATA */
+ 0x00000033, /* DENALI_PHY_665_DATA */
+ 0x0000000c, /* DENALI_PHY_666_DATA */
+ 0x0000000c, /* DENALI_PHY_667_DATA */
+ 0x00000033, /* DENALI_PHY_668_DATA */
+ 0x00000000, /* DENALI_PHY_669_DATA */
+ 0x00000000, /* DENALI_PHY_670_DATA */
+ 0x00000000, /* DENALI_PHY_671_DATA */
+ 0x00030055, /* DENALI_PHY_672_DATA */
+ 0x03000300, /* DENALI_PHY_673_DATA */
+ 0x03000300, /* DENALI_PHY_674_DATA */
+ 0x00000300, /* DENALI_PHY_675_DATA */
+ 0x42080010, /* DENALI_PHY_676_DATA */
+ 0x00000003, /* DENALI_PHY_677_DATA */
+ 0x00000000, /* DENALI_PHY_678_DATA */
+ 0x00000000, /* DENALI_PHY_679_DATA */
+ 0x00000000, /* DENALI_PHY_680_DATA */
+ 0x00000000, /* DENALI_PHY_681_DATA */
+ 0x00000000, /* DENALI_PHY_682_DATA */
+ 0x00000000, /* DENALI_PHY_683_DATA */
+ 0x00000000, /* DENALI_PHY_684_DATA */
+ 0x00000000, /* DENALI_PHY_685_DATA */
+ 0x00000000, /* DENALI_PHY_686_DATA */
+ 0x00000000, /* DENALI_PHY_687_DATA */
+ 0x00000000, /* DENALI_PHY_688_DATA */
+ 0x00000000, /* DENALI_PHY_689_DATA */
+ 0x00000000, /* DENALI_PHY_690_DATA */
+ 0x00000000, /* DENALI_PHY_691_DATA */
+ 0x00000000, /* DENALI_PHY_692_DATA */
+ 0x00000000, /* DENALI_PHY_693_DATA */
+ 0x00000000, /* DENALI_PHY_694_DATA */
+ 0x00000000, /* DENALI_PHY_695_DATA */
+ 0x00000000, /* DENALI_PHY_696_DATA */
+ 0x00000000, /* DENALI_PHY_697_DATA */
+ 0x00000000, /* DENALI_PHY_698_DATA */
+ 0x00000000, /* DENALI_PHY_699_DATA */
+ 0x00000000, /* DENALI_PHY_700_DATA */
+ 0x00000000, /* DENALI_PHY_701_DATA */
+ 0x00000000, /* DENALI_PHY_702_DATA */
+ 0x00000000, /* DENALI_PHY_703_DATA */
+ 0x00000000, /* DENALI_PHY_704_DATA */
+ 0x00000000, /* DENALI_PHY_705_DATA */
+ 0x00000000, /* DENALI_PHY_706_DATA */
+ 0x00000000, /* DENALI_PHY_707_DATA */
+ 0x00000000, /* DENALI_PHY_708_DATA */
+ 0x00000000, /* DENALI_PHY_709_DATA */
+ 0x00000000, /* DENALI_PHY_710_DATA */
+ 0x00000000, /* DENALI_PHY_711_DATA */
+ 0x00000000, /* DENALI_PHY_712_DATA */
+ 0x00000000, /* DENALI_PHY_713_DATA */
+ 0x00000000, /* DENALI_PHY_714_DATA */
+ 0x00000000, /* DENALI_PHY_715_DATA */
+ 0x00000000, /* DENALI_PHY_716_DATA */
+ 0x00000000, /* DENALI_PHY_717_DATA */
+ 0x00000000, /* DENALI_PHY_718_DATA */
+ 0x00000000, /* DENALI_PHY_719_DATA */
+ 0x00000000, /* DENALI_PHY_720_DATA */
+ 0x00000000, /* DENALI_PHY_721_DATA */
+ 0x00000000, /* DENALI_PHY_722_DATA */
+ 0x00000000, /* DENALI_PHY_723_DATA */
+ 0x00000000, /* DENALI_PHY_724_DATA */
+ 0x00000000, /* DENALI_PHY_725_DATA */
+ 0x00000000, /* DENALI_PHY_726_DATA */
+ 0x00000000, /* DENALI_PHY_727_DATA */
+ 0x00000000, /* DENALI_PHY_728_DATA */
+ 0x00000000, /* DENALI_PHY_729_DATA */
+ 0x00000000, /* DENALI_PHY_730_DATA */
+ 0x00000000, /* DENALI_PHY_731_DATA */
+ 0x00000000, /* DENALI_PHY_732_DATA */
+ 0x00000000, /* DENALI_PHY_733_DATA */
+ 0x00000000, /* DENALI_PHY_734_DATA */
+ 0x00000000, /* DENALI_PHY_735_DATA */
+ 0x00000000, /* DENALI_PHY_736_DATA */
+ 0x00000000, /* DENALI_PHY_737_DATA */
+ 0x00000000, /* DENALI_PHY_738_DATA */
+ 0x00000000, /* DENALI_PHY_739_DATA */
+ 0x00000000, /* DENALI_PHY_740_DATA */
+ 0x00000000, /* DENALI_PHY_741_DATA */
+ 0x00000000, /* DENALI_PHY_742_DATA */
+ 0x00000000, /* DENALI_PHY_743_DATA */
+ 0x00000000, /* DENALI_PHY_744_DATA */
+ 0x00000000, /* DENALI_PHY_745_DATA */
+ 0x00000000, /* DENALI_PHY_746_DATA */
+ 0x00000000, /* DENALI_PHY_747_DATA */
+ 0x00000000, /* DENALI_PHY_748_DATA */
+ 0x00000000, /* DENALI_PHY_749_DATA */
+ 0x00000000, /* DENALI_PHY_750_DATA */
+ 0x00000000, /* DENALI_PHY_751_DATA */
+ 0x00000000, /* DENALI_PHY_752_DATA */
+ 0x00000000, /* DENALI_PHY_753_DATA */
+ 0x00000000, /* DENALI_PHY_754_DATA */
+ 0x00000000, /* DENALI_PHY_755_DATA */
+ 0x00000000, /* DENALI_PHY_756_DATA */
+ 0x00000000, /* DENALI_PHY_757_DATA */
+ 0x00000000, /* DENALI_PHY_758_DATA */
+ 0x00000000, /* DENALI_PHY_759_DATA */
+ 0x00000000, /* DENALI_PHY_760_DATA */
+ 0x00000000, /* DENALI_PHY_761_DATA */
+ 0x00000000, /* DENALI_PHY_762_DATA */
+ 0x00000000, /* DENALI_PHY_763_DATA */
+ 0x00000000, /* DENALI_PHY_764_DATA */
+ 0x00000000, /* DENALI_PHY_765_DATA */
+ 0x00000000, /* DENALI_PHY_766_DATA */
+ 0x00000000, /* DENALI_PHY_767_DATA */
+ 0x00000000, /* DENALI_PHY_768_DATA */
+ 0x00000000, /* DENALI_PHY_769_DATA */
+ 0x00000000, /* DENALI_PHY_770_DATA */
+ 0x00000000, /* DENALI_PHY_771_DATA */
+ 0x00000000, /* DENALI_PHY_772_DATA */
+ 0x00000000, /* DENALI_PHY_773_DATA */
+ 0x00000000, /* DENALI_PHY_774_DATA */
+ 0x00000002, /* DENALI_PHY_775_DATA */
+ 0x00000000, /* DENALI_PHY_776_DATA */
+ 0x00000000, /* DENALI_PHY_777_DATA */
+ 0x00000000, /* DENALI_PHY_778_DATA */
+ 0x00400320, /* DENALI_PHY_779_DATA */
+ 0x00000040, /* DENALI_PHY_780_DATA */
+ 0x00000000, /* DENALI_PHY_781_DATA */
+ 0x00000000, /* DENALI_PHY_782_DATA */
+ 0x00000000, /* DENALI_PHY_783_DATA */
+ 0x01000000, /* DENALI_PHY_784_DATA */
+ 0x00020003, /* DENALI_PHY_785_DATA */
+ 0x00000000, /* DENALI_PHY_786_DATA */
+ 0x00000000, /* DENALI_PHY_787_DATA */
+ 0x00000000, /* DENALI_PHY_788_DATA */
+ 0x0000002a, /* DENALI_PHY_789_DATA */
+ 0x00000015, /* DENALI_PHY_790_DATA */
+ 0x00000015, /* DENALI_PHY_791_DATA */
+ 0x0000002a, /* DENALI_PHY_792_DATA */
+ 0x00000033, /* DENALI_PHY_793_DATA */
+ 0x0000000c, /* DENALI_PHY_794_DATA */
+ 0x0000000c, /* DENALI_PHY_795_DATA */
+ 0x00000033, /* DENALI_PHY_796_DATA */
+ 0x1ee6b16a, /* DENALI_PHY_797_DATA */
+ 0x10000000, /* DENALI_PHY_798_DATA */
+ 0x00000000, /* DENALI_PHY_799_DATA */
+ 0x00030055, /* DENALI_PHY_800_DATA */
+ 0x03000300, /* DENALI_PHY_801_DATA */
+ 0x03000300, /* DENALI_PHY_802_DATA */
+ 0x00000300, /* DENALI_PHY_803_DATA */
+ 0x42080010, /* DENALI_PHY_804_DATA */
+ 0x00000003, /* DENALI_PHY_805_DATA */
+ 0x00000000, /* DENALI_PHY_806_DATA */
+ 0x00000000, /* DENALI_PHY_807_DATA */
+ 0x00000000, /* DENALI_PHY_808_DATA */
+ 0x00000000, /* DENALI_PHY_809_DATA */
+ 0x00000000, /* DENALI_PHY_810_DATA */
+ 0x00000000, /* DENALI_PHY_811_DATA */
+ 0x00000000, /* DENALI_PHY_812_DATA */
+ 0x00000000, /* DENALI_PHY_813_DATA */
+ 0x00000000, /* DENALI_PHY_814_DATA */
+ 0x00000000, /* DENALI_PHY_815_DATA */
+ 0x00000000, /* DENALI_PHY_816_DATA */
+ 0x00000000, /* DENALI_PHY_817_DATA */
+ 0x00000000, /* DENALI_PHY_818_DATA */
+ 0x00000000, /* DENALI_PHY_819_DATA */
+ 0x00000000, /* DENALI_PHY_820_DATA */
+ 0x00000000, /* DENALI_PHY_821_DATA */
+ 0x00000000, /* DENALI_PHY_822_DATA */
+ 0x00000000, /* DENALI_PHY_823_DATA */
+ 0x00000000, /* DENALI_PHY_824_DATA */
+ 0x00000000, /* DENALI_PHY_825_DATA */
+ 0x00000000, /* DENALI_PHY_826_DATA */
+ 0x00000000, /* DENALI_PHY_827_DATA */
+ 0x00000000, /* DENALI_PHY_828_DATA */
+ 0x00000000, /* DENALI_PHY_829_DATA */
+ 0x00000000, /* DENALI_PHY_830_DATA */
+ 0x00000000, /* DENALI_PHY_831_DATA */
+ 0x00000000, /* DENALI_PHY_832_DATA */
+ 0x00000000, /* DENALI_PHY_833_DATA */
+ 0x00000000, /* DENALI_PHY_834_DATA */
+ 0x00000000, /* DENALI_PHY_835_DATA */
+ 0x00000000, /* DENALI_PHY_836_DATA */
+ 0x00000000, /* DENALI_PHY_837_DATA */
+ 0x00000000, /* DENALI_PHY_838_DATA */
+ 0x00000000, /* DENALI_PHY_839_DATA */
+ 0x00000000, /* DENALI_PHY_840_DATA */
+ 0x00000000, /* DENALI_PHY_841_DATA */
+ 0x00000000, /* DENALI_PHY_842_DATA */
+ 0x00000000, /* DENALI_PHY_843_DATA */
+ 0x00000000, /* DENALI_PHY_844_DATA */
+ 0x00000000, /* DENALI_PHY_845_DATA */
+ 0x00000000, /* DENALI_PHY_846_DATA */
+ 0x00000000, /* DENALI_PHY_847_DATA */
+ 0x00000000, /* DENALI_PHY_848_DATA */
+ 0x00000000, /* DENALI_PHY_849_DATA */
+ 0x00000000, /* DENALI_PHY_850_DATA */
+ 0x00000000, /* DENALI_PHY_851_DATA */
+ 0x00000000, /* DENALI_PHY_852_DATA */
+ 0x00000000, /* DENALI_PHY_853_DATA */
+ 0x00000000, /* DENALI_PHY_854_DATA */
+ 0x00000000, /* DENALI_PHY_855_DATA */
+ 0x00000000, /* DENALI_PHY_856_DATA */
+ 0x00000000, /* DENALI_PHY_857_DATA */
+ 0x00000000, /* DENALI_PHY_858_DATA */
+ 0x00000000, /* DENALI_PHY_859_DATA */
+ 0x00000000, /* DENALI_PHY_860_DATA */
+ 0x00000000, /* DENALI_PHY_861_DATA */
+ 0x00000000, /* DENALI_PHY_862_DATA */
+ 0x00000000, /* DENALI_PHY_863_DATA */
+ 0x00000000, /* DENALI_PHY_864_DATA */
+ 0x00000000, /* DENALI_PHY_865_DATA */
+ 0x00000000, /* DENALI_PHY_866_DATA */
+ 0x00000000, /* DENALI_PHY_867_DATA */
+ 0x00000000, /* DENALI_PHY_868_DATA */
+ 0x00000000, /* DENALI_PHY_869_DATA */
+ 0x00000000, /* DENALI_PHY_870_DATA */
+ 0x00000000, /* DENALI_PHY_871_DATA */
+ 0x00000000, /* DENALI_PHY_872_DATA */
+ 0x00000000, /* DENALI_PHY_873_DATA */
+ 0x00000000, /* DENALI_PHY_874_DATA */
+ 0x00000000, /* DENALI_PHY_875_DATA */
+ 0x00000000, /* DENALI_PHY_876_DATA */
+ 0x00000000, /* DENALI_PHY_877_DATA */
+ 0x00000000, /* DENALI_PHY_878_DATA */
+ 0x00000000, /* DENALI_PHY_879_DATA */
+ 0x00000000, /* DENALI_PHY_880_DATA */
+ 0x00000000, /* DENALI_PHY_881_DATA */
+ 0x00000000, /* DENALI_PHY_882_DATA */
+ 0x00000000, /* DENALI_PHY_883_DATA */
+ 0x00000000, /* DENALI_PHY_884_DATA */
+ 0x00000000, /* DENALI_PHY_885_DATA */
+ 0x00000000, /* DENALI_PHY_886_DATA */
+ 0x00000000, /* DENALI_PHY_887_DATA */
+ 0x00000000, /* DENALI_PHY_888_DATA */
+ 0x00000000, /* DENALI_PHY_889_DATA */
+ 0x00000000, /* DENALI_PHY_890_DATA */
+ 0x00000000, /* DENALI_PHY_891_DATA */
+ 0x00000000, /* DENALI_PHY_892_DATA */
+ 0x00000000, /* DENALI_PHY_893_DATA */
+ 0x00000000, /* DENALI_PHY_894_DATA */
+ 0x00000000, /* DENALI_PHY_895_DATA */
+ 0x00000000, /* DENALI_PHY_896_DATA */
+ 0x00000000, /* DENALI_PHY_897_DATA */
+ 0x00000005, /* DENALI_PHY_898_DATA */
+ 0x04000f01, /* DENALI_PHY_899_DATA */
+ 0x00020040, /* DENALI_PHY_900_DATA */
+ 0x00020055, /* DENALI_PHY_901_DATA */
+ 0x00000000, /* DENALI_PHY_902_DATA */
+ 0x00000000, /* DENALI_PHY_903_DATA */
+ 0x00000000, /* DENALI_PHY_904_DATA */
+ 0x00000050, /* DENALI_PHY_905_DATA */
+ 0x00000000, /* DENALI_PHY_906_DATA */
+ 0x01010100, /* DENALI_PHY_907_DATA */
+ 0x00000600, /* DENALI_PHY_908_DATA */
+ 0x00000000, /* DENALI_PHY_909_DATA */
+ 0x00006400, /* DENALI_PHY_910_DATA */
+ 0x01221102, /* DENALI_PHY_911_DATA */
+ 0x00000000, /* DENALI_PHY_912_DATA */
+ 0x000d1f00, /* DENALI_PHY_913_DATA */
+ 0x0d1f0d1f, /* DENALI_PHY_914_DATA */
+ 0x0d1f0d1f, /* DENALI_PHY_915_DATA */
+ 0x00030003, /* DENALI_PHY_916_DATA */
+ 0x03000300, /* DENALI_PHY_917_DATA */
+ 0x00000300, /* DENALI_PHY_918_DATA */
+ 0x01221102, /* DENALI_PHY_919_DATA */
+ 0x00000000, /* DENALI_PHY_920_DATA */
+ 0x00000000, /* DENALI_PHY_921_DATA */
+ 0x03020000, /* DENALI_PHY_922_DATA */
+ 0x00000001, /* DENALI_PHY_923_DATA */
+ 0x00000411, /* DENALI_PHY_924_DATA */
+ 0x00000411, /* DENALI_PHY_925_DATA */
+ 0x00000040, /* DENALI_PHY_926_DATA */
+ 0x00000040, /* DENALI_PHY_927_DATA */
+ 0x00000411, /* DENALI_PHY_928_DATA */
+ 0x00000411, /* DENALI_PHY_929_DATA */
+ 0x00004410, /* DENALI_PHY_930_DATA */
+ 0x00004410, /* DENALI_PHY_931_DATA */
+ 0x00004410, /* DENALI_PHY_932_DATA */
+ 0x00004410, /* DENALI_PHY_933_DATA */
+ 0x00004410, /* DENALI_PHY_934_DATA */
+ 0x00000411, /* DENALI_PHY_935_DATA */
+ 0x00004410, /* DENALI_PHY_936_DATA */
+ 0x00000411, /* DENALI_PHY_937_DATA */
+ 0x00004410, /* DENALI_PHY_938_DATA */
+ 0x00000411, /* DENALI_PHY_939_DATA */
+ 0x00004410, /* DENALI_PHY_940_DATA */
+ 0x00000000, /* DENALI_PHY_941_DATA */
+ 0x00000000, /* DENALI_PHY_942_DATA */
+ 0x00000000, /* DENALI_PHY_943_DATA */
+ 0x64000000, /* DENALI_PHY_944_DATA */
+ 0x00000000, /* DENALI_PHY_945_DATA */
+ 0x00000000, /* DENALI_PHY_946_DATA */
+ 0x00000508, /* DENALI_PHY_947_DATA */
+ 0x00000000, /* DENALI_PHY_948_DATA */
+ 0x00000000, /* DENALI_PHY_949_DATA */
+ 0x00000000, /* DENALI_PHY_950_DATA */
+ 0x00000000, /* DENALI_PHY_951_DATA */
+ 0x00000000, /* DENALI_PHY_952_DATA */
+ 0x00000000, /* DENALI_PHY_953_DATA */
+ 0xe4000000, /* DENALI_PHY_954_DATA */
+ 0x00000000, /* DENALI_PHY_955_DATA */
+ 0x00000000, /* DENALI_PHY_956_DATA */
+ 0x01010000, /* DENALI_PHY_957_DATA */
+ 0x00000000 /* DENALI_PHY_958_DATA */
+ }
+ },
+},
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 83/92] ram: rk3399: Add LPPDDR4-800 timings inc
@ 2019-06-11 14:51 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: u-boot
LPDDR4 initialization start with at board selected frequency
and then it switches into 400MHz and 800MHz simultaneously to
make the proper sequence work on each channel with associated
training.
So, add LPDDR4-800 timings inc file in driver area so-that
these timings will take during LPDDR4 initialization phase.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
.../ram/rockchip/sdram-rk3399-lpddr4-800.inc | 1570 +++++++++++++++++
1 file changed, 1570 insertions(+)
create mode 100644 drivers/ram/rockchip/sdram-rk3399-lpddr4-800.inc
diff --git a/drivers/ram/rockchip/sdram-rk3399-lpddr4-800.inc b/drivers/ram/rockchip/sdram-rk3399-lpddr4-800.inc
new file mode 100644
index 0000000000..d8ae3359a3
--- /dev/null
+++ b/drivers/ram/rockchip/sdram-rk3399-lpddr4-800.inc
@@ -0,0 +1,1570 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd.
+ * (C) Copyright 2019 Amarula Solutions
+ */
+
+{
+ {
+ {
+ {
+ .rank = 0x2,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF,
+ .ddrconfig = 1,
+ },
+ {
+ .ddrtiminga0 = 0x80241d22,
+ .ddrtimingb0 = 0x15050f08,
+ .ddrtimingc0 = {
+ 0x00000602,
+ },
+ .devtodev0 = 0x00002122,
+ .ddrmode = {
+ 0x0000004c,
+ },
+ .agingx0 = 0x00000000,
+ }
+ },
+ {
+ {
+ .rank = 0x2,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF,
+ .ddrconfig = 1,
+ },
+ {
+ .ddrtiminga0 = 0x80241d22,
+ .ddrtimingb0 = 0x15050f08,
+ .ddrtimingc0 = {
+ 0x00000602,
+ },
+ .devtodev0 = 0x00002122,
+ .ddrmode = {
+ 0x0000004c,
+ },
+ .agingx0 = 0x00000000,
+ }
+ }
+ },
+ {
+ .ddr_freq = 800 * MHz,
+ .dramtype = LPDDR4,
+ .num_channels = 2,
+ .stride = 13,
+ .odt = 1,
+ },
+ {
+ {
+ 0x00000b00, /* DENALI_CTL_00_DATA */
+ 0x00000000, /* DENALI_CTL_01_DATA */
+ 0x00000000, /* DENALI_CTL_02_DATA */
+ 0x00000000, /* DENALI_CTL_03_DATA */
+ 0x00000000, /* DENALI_CTL_04_DATA */
+ 0x00013880, /* DENALI_CTL_05_DATA */
+ 0x000c3500, /* DENALI_CTL_06_DATA */
+ 0x00000005, /* DENALI_CTL_07_DATA */
+ 0x00000320, /* DENALI_CTL_08_DATA */
+ 0x00027100, /* DENALI_CTL_09_DATA */
+ 0x00186a00, /* DENALI_CTL_10_DATA */
+ 0x00000005, /* DENALI_CTL_11_DATA */
+ 0x00000640, /* DENALI_CTL_12_DATA */
+ 0x00002710, /* DENALI_CTL_13_DATA */
+ 0x000186a0, /* DENALI_CTL_14_DATA */
+ 0x00000005, /* DENALI_CTL_15_DATA */
+ 0x01000064, /* DENALI_CTL_16_DATA */
+ 0x00000000, /* DENALI_CTL_17_DATA */
+ 0x02020101, /* DENALI_CTL_18_DATA */
+ 0x00000102, /* DENALI_CTL_19_DATA */
+ 0x00000050, /* DENALI_CTL_20_DATA */
+ 0x000000c8, /* DENALI_CTL_21_DATA */
+ 0x00000000, /* DENALI_CTL_22_DATA */
+ 0x06140000, /* DENALI_CTL_23_DATA */
+ 0x00081c00, /* DENALI_CTL_24_DATA */
+ 0x0400040c, /* DENALI_CTL_25_DATA */
+ 0x19042008, /* DENALI_CTL_26_DATA */
+ 0x10080a11, /* DENALI_CTL_27_DATA */
+ 0x22310800, /* DENALI_CTL_28_DATA */
+ 0x00200f0a, /* DENALI_CTL_29_DATA */
+ 0x0a030704, /* DENALI_CTL_30_DATA */
+ 0x08000204, /* DENALI_CTL_31_DATA */
+ 0x00000a0a, /* DENALI_CTL_32_DATA */
+ 0x04006db0, /* DENALI_CTL_33_DATA */
+ 0x0a0a0804, /* DENALI_CTL_34_DATA */
+ 0x0600db60, /* DENALI_CTL_35_DATA */
+ 0x0a0a0806, /* DENALI_CTL_36_DATA */
+ 0x04000db6, /* DENALI_CTL_37_DATA */
+ 0x02030404, /* DENALI_CTL_38_DATA */
+ 0x0f0a0800, /* DENALI_CTL_39_DATA */
+ 0x08040411, /* DENALI_CTL_40_DATA */
+ 0x1400640a, /* DENALI_CTL_41_DATA */
+ 0x02010a0a, /* DENALI_CTL_42_DATA */
+ 0x00010001, /* DENALI_CTL_43_DATA */
+ 0x04082012, /* DENALI_CTL_44_DATA */
+ 0x00041109, /* DENALI_CTL_45_DATA */
+ 0x00000000, /* DENALI_CTL_46_DATA */
+ 0x03010000, /* DENALI_CTL_47_DATA */
+ 0x06100034, /* DENALI_CTL_48_DATA */
+ 0x0c280068, /* DENALI_CTL_49_DATA */
+ 0x00bb0007, /* DENALI_CTL_50_DATA */
+ 0x00000000, /* DENALI_CTL_51_DATA */
+ 0x00060003, /* DENALI_CTL_52_DATA */
+ 0x000a0003, /* DENALI_CTL_53_DATA */
+ 0x000a0014, /* DENALI_CTL_54_DATA */
+ 0x01000000, /* DENALI_CTL_55_DATA */
+ 0x030a0000, /* DENALI_CTL_56_DATA */
+ 0x0c000002, /* DENALI_CTL_57_DATA */
+ 0x00000103, /* DENALI_CTL_58_DATA */
+ 0x0003030a, /* DENALI_CTL_59_DATA */
+ 0x00060037, /* DENALI_CTL_60_DATA */
+ 0x0003006e, /* DENALI_CTL_61_DATA */
+ 0x05050007, /* DENALI_CTL_62_DATA */
+ 0x03020605, /* DENALI_CTL_63_DATA */
+ 0x06050301, /* DENALI_CTL_64_DATA */
+ 0x06020c05, /* DENALI_CTL_65_DATA */
+ 0x05050302, /* DENALI_CTL_66_DATA */
+ 0x03020305, /* DENALI_CTL_67_DATA */
+ 0x00000301, /* DENALI_CTL_68_DATA */
+ 0x00000301, /* DENALI_CTL_69_DATA */
+ 0x00000001, /* DENALI_CTL_70_DATA */
+ 0x00000000, /* DENALI_CTL_71_DATA */
+ 0x00000000, /* DENALI_CTL_72_DATA */
+ 0x01000000, /* DENALI_CTL_73_DATA */
+ 0x80104002, /* DENALI_CTL_74_DATA */
+ 0x00040003, /* DENALI_CTL_75_DATA */
+ 0x00040005, /* DENALI_CTL_76_DATA */
+ 0x00030000, /* DENALI_CTL_77_DATA */
+ 0x00050004, /* DENALI_CTL_78_DATA */
+ 0x00000004, /* DENALI_CTL_79_DATA */
+ 0x00040003, /* DENALI_CTL_80_DATA */
+ 0x00040005, /* DENALI_CTL_81_DATA */
+ 0x18400000, /* DENALI_CTL_82_DATA */
+ 0x00000c20, /* DENALI_CTL_83_DATA */
+ 0x185030a0, /* DENALI_CTL_84_DATA */
+ 0x02ec0000, /* DENALI_CTL_85_DATA */
+ 0x00000176, /* DENALI_CTL_86_DATA */
+ 0x00000000, /* DENALI_CTL_87_DATA */
+ 0x00000000, /* DENALI_CTL_88_DATA */
+ 0x00000000, /* DENALI_CTL_89_DATA */
+ 0x00000000, /* DENALI_CTL_90_DATA */
+ 0x00000000, /* DENALI_CTL_91_DATA */
+ 0x06030300, /* DENALI_CTL_92_DATA */
+ 0x00030303, /* DENALI_CTL_93_DATA */
+ 0x02030200, /* DENALI_CTL_94_DATA */
+ 0x00040703, /* DENALI_CTL_95_DATA */
+ 0x03020302, /* DENALI_CTL_96_DATA */
+ 0x02000407, /* DENALI_CTL_97_DATA */
+ 0x07030203, /* DENALI_CTL_98_DATA */
+ 0x00030f04, /* DENALI_CTL_99_DATA */
+ 0x00070004, /* DENALI_CTL_100_DATA */
+ 0x00000000, /* DENALI_CTL_101_DATA */
+ 0x00000000, /* DENALI_CTL_102_DATA */
+ 0x00000000, /* DENALI_CTL_103_DATA */
+ 0x00000000, /* DENALI_CTL_104_DATA */
+ 0x00000000, /* DENALI_CTL_105_DATA */
+ 0x00000000, /* DENALI_CTL_106_DATA */
+ 0x00000000, /* DENALI_CTL_107_DATA */
+ 0x00010000, /* DENALI_CTL_108_DATA */
+ 0x20040020, /* DENALI_CTL_109_DATA */
+ 0x00200400, /* DENALI_CTL_110_DATA */
+ 0x01000400, /* DENALI_CTL_111_DATA */
+ 0x00000b80, /* DENALI_CTL_112_DATA */
+ 0x00000000, /* DENALI_CTL_113_DATA */
+ 0x00000001, /* DENALI_CTL_114_DATA */
+ 0x00000002, /* DENALI_CTL_115_DATA */
+ 0x0000000e, /* DENALI_CTL_116_DATA */
+ 0x00000000, /* DENALI_CTL_117_DATA */
+ 0x00000000, /* DENALI_CTL_118_DATA */
+ 0x00000000, /* DENALI_CTL_119_DATA */
+ 0x00000000, /* DENALI_CTL_120_DATA */
+ 0x00000000, /* DENALI_CTL_121_DATA */
+ 0x00500000, /* DENALI_CTL_122_DATA */
+ 0x00640028, /* DENALI_CTL_123_DATA */
+ 0x00640404, /* DENALI_CTL_124_DATA */
+ 0x005000a0, /* DENALI_CTL_125_DATA */
+ 0x060600c8, /* DENALI_CTL_126_DATA */
+ 0x000a00c8, /* DENALI_CTL_127_DATA */
+ 0x000d0005, /* DENALI_CTL_128_DATA */
+ 0x000d0404, /* DENALI_CTL_129_DATA */
+ 0x00000000, /* DENALI_CTL_130_DATA */
+ 0x00000000, /* DENALI_CTL_131_DATA */
+ 0x00000000, /* DENALI_CTL_132_DATA */
+ 0x001400a3, /* DENALI_CTL_133_DATA */
+ 0x00e30009, /* DENALI_CTL_134_DATA */
+ 0x00120024, /* DENALI_CTL_135_DATA */
+ 0x00040063, /* DENALI_CTL_136_DATA */
+ 0x00000000, /* DENALI_CTL_137_DATA */
+ 0x00310031, /* DENALI_CTL_138_DATA */
+ 0x00000031, /* DENALI_CTL_139_DATA */
+ 0x004d0000, /* DENALI_CTL_140_DATA */
+ 0x004d004d, /* DENALI_CTL_141_DATA */
+ 0x004d0000, /* DENALI_CTL_142_DATA */
+ 0x004d004d, /* DENALI_CTL_143_DATA */
+ 0x00010101, /* DENALI_CTL_144_DATA */
+ 0x00000000, /* DENALI_CTL_145_DATA */
+ 0x00000000, /* DENALI_CTL_146_DATA */
+ 0x001400a3, /* DENALI_CTL_147_DATA */
+ 0x00e30009, /* DENALI_CTL_148_DATA */
+ 0x00120024, /* DENALI_CTL_149_DATA */
+ 0x00040063, /* DENALI_CTL_150_DATA */
+ 0x00000000, /* DENALI_CTL_151_DATA */
+ 0x00310031, /* DENALI_CTL_152_DATA */
+ 0x00000031, /* DENALI_CTL_153_DATA */
+ 0x004d0000, /* DENALI_CTL_154_DATA */
+ 0x004d004d, /* DENALI_CTL_155_DATA */
+ 0x004d0000, /* DENALI_CTL_156_DATA */
+ 0x004d004d, /* DENALI_CTL_157_DATA */
+ 0x00010101, /* DENALI_CTL_158_DATA */
+ 0x00000000, /* DENALI_CTL_159_DATA */
+ 0x00000000, /* DENALI_CTL_160_DATA */
+ 0x00000000, /* DENALI_CTL_161_DATA */
+ 0x00000001, /* DENALI_CTL_162_DATA */
+ 0x00000000, /* DENALI_CTL_163_DATA */
+ 0x18151100, /* DENALI_CTL_164_DATA */
+ 0x0000000c, /* DENALI_CTL_165_DATA */
+ 0x00000000, /* DENALI_CTL_166_DATA */
+ 0x00000000, /* DENALI_CTL_167_DATA */
+ 0x00000000, /* DENALI_CTL_168_DATA */
+ 0x00000000, /* DENALI_CTL_169_DATA */
+ 0x00000000, /* DENALI_CTL_170_DATA */
+ 0x00000000, /* DENALI_CTL_171_DATA */
+ 0x00000000, /* DENALI_CTL_172_DATA */
+ 0x00000000, /* DENALI_CTL_173_DATA */
+ 0x00000000, /* DENALI_CTL_174_DATA */
+ 0x00000000, /* DENALI_CTL_175_DATA */
+ 0x00000000, /* DENALI_CTL_176_DATA */
+ 0x00000000, /* DENALI_CTL_177_DATA */
+ 0x00000000, /* DENALI_CTL_178_DATA */
+ 0x00020003, /* DENALI_CTL_179_DATA */
+ 0x00400100, /* DENALI_CTL_180_DATA */
+ 0x000c0190, /* DENALI_CTL_181_DATA */
+ 0x01000200, /* DENALI_CTL_182_DATA */
+ 0x03200040, /* DENALI_CTL_183_DATA */
+ 0x00020018, /* DENALI_CTL_184_DATA */
+ 0x00400100, /* DENALI_CTL_185_DATA */
+ 0x00080032, /* DENALI_CTL_186_DATA */
+ 0x00140000, /* DENALI_CTL_187_DATA */
+ 0x00030028, /* DENALI_CTL_188_DATA */
+ 0x01010100, /* DENALI_CTL_189_DATA */
+ 0x02000202, /* DENALI_CTL_190_DATA */
+ 0x0b000002, /* DENALI_CTL_191_DATA */
+ 0x01000f0f, /* DENALI_CTL_192_DATA */
+ 0x00000000, /* DENALI_CTL_193_DATA */
+ 0x00000000, /* DENALI_CTL_194_DATA */
+ 0x00010003, /* DENALI_CTL_195_DATA */
+ 0x00000c03, /* DENALI_CTL_196_DATA */
+ 0x00040101, /* DENALI_CTL_197_DATA */
+ 0x04010100, /* DENALI_CTL_198_DATA */
+ 0x01000000, /* DENALI_CTL_199_DATA */
+ 0x02010000, /* DENALI_CTL_200_DATA */
+ 0x00000001, /* DENALI_CTL_201_DATA */
+ 0x00000000, /* DENALI_CTL_202_DATA */
+ 0x00000000, /* DENALI_CTL_203_DATA */
+ 0x00000000, /* DENALI_CTL_204_DATA */
+ 0x00000000, /* DENALI_CTL_205_DATA */
+ 0x00000000, /* DENALI_CTL_206_DATA */
+ 0x00000000, /* DENALI_CTL_207_DATA */
+ 0x00000000, /* DENALI_CTL_208_DATA */
+ 0x00000000, /* DENALI_CTL_209_DATA */
+ 0x00000000, /* DENALI_CTL_210_DATA */
+ 0x00010000, /* DENALI_CTL_211_DATA */
+ 0x00000001, /* DENALI_CTL_212_DATA */
+ 0x01010001, /* DENALI_CTL_213_DATA */
+ 0x05040001, /* DENALI_CTL_214_DATA */
+ 0x040a0703, /* DENALI_CTL_215_DATA */
+ 0x02080808, /* DENALI_CTL_216_DATA */
+ 0x020e000a, /* DENALI_CTL_217_DATA */
+ 0x020f010b, /* DENALI_CTL_218_DATA */
+ 0x000d0008, /* DENALI_CTL_219_DATA */
+ 0x00080b0a, /* DENALI_CTL_220_DATA */
+ 0x03000200, /* DENALI_CTL_221_DATA */
+ 0x00000100, /* DENALI_CTL_222_DATA */
+ 0x00000000, /* DENALI_CTL_223_DATA */
+ 0x00000000, /* DENALI_CTL_224_DATA */
+ 0x0d000001, /* DENALI_CTL_225_DATA */
+ 0x00000028, /* DENALI_CTL_226_DATA */
+ 0x00010000, /* DENALI_CTL_227_DATA */
+ 0x00000003, /* DENALI_CTL_228_DATA */
+ 0x00000000, /* DENALI_CTL_229_DATA */
+ 0x00000000, /* DENALI_CTL_230_DATA */
+ 0x00000000, /* DENALI_CTL_231_DATA */
+ 0x00000000, /* DENALI_CTL_232_DATA */
+ 0x00000000, /* DENALI_CTL_233_DATA */
+ 0x00000000, /* DENALI_CTL_234_DATA */
+ 0x00000000, /* DENALI_CTL_235_DATA */
+ 0x00000000, /* DENALI_CTL_236_DATA */
+ 0x00010100, /* DENALI_CTL_237_DATA */
+ 0x01000000, /* DENALI_CTL_238_DATA */
+ 0x00000001, /* DENALI_CTL_239_DATA */
+ 0x00000303, /* DENALI_CTL_240_DATA */
+ 0x00000000, /* DENALI_CTL_241_DATA */
+ 0x00000000, /* DENALI_CTL_242_DATA */
+ 0x00000000, /* DENALI_CTL_243_DATA */
+ 0x00000000, /* DENALI_CTL_244_DATA */
+ 0x00000000, /* DENALI_CTL_245_DATA */
+ 0x00000000, /* DENALI_CTL_246_DATA */
+ 0x00000000, /* DENALI_CTL_247_DATA */
+ 0x00000000, /* DENALI_CTL_248_DATA */
+ 0x00000000, /* DENALI_CTL_249_DATA */
+ 0x00000000, /* DENALI_CTL_250_DATA */
+ 0x00000000, /* DENALI_CTL_251_DATA */
+ 0x00000000, /* DENALI_CTL_252_DATA */
+ 0x00000000, /* DENALI_CTL_253_DATA */
+ 0x00000000, /* DENALI_CTL_254_DATA */
+ 0x00000000, /* DENALI_CTL_255_DATA */
+ 0x000556aa, /* DENALI_CTL_256_DATA */
+ 0x000aaaaa, /* DENALI_CTL_257_DATA */
+ 0x000aa955, /* DENALI_CTL_258_DATA */
+ 0x00055555, /* DENALI_CTL_259_DATA */
+ 0x000b3133, /* DENALI_CTL_260_DATA */
+ 0x0004cd33, /* DENALI_CTL_261_DATA */
+ 0x0004cecc, /* DENALI_CTL_262_DATA */
+ 0x000b32cc, /* DENALI_CTL_263_DATA */
+ 0x00010300, /* DENALI_CTL_264_DATA */
+ 0x03000100, /* DENALI_CTL_265_DATA */
+ 0x00000000, /* DENALI_CTL_266_DATA */
+ 0x00000000, /* DENALI_CTL_267_DATA */
+ 0x00000000, /* DENALI_CTL_268_DATA */
+ 0x00000000, /* DENALI_CTL_269_DATA */
+ 0x00000000, /* DENALI_CTL_270_DATA */
+ 0x00000000, /* DENALI_CTL_271_DATA */
+ 0x00000000, /* DENALI_CTL_272_DATA */
+ 0x00000000, /* DENALI_CTL_273_DATA */
+ 0x00ffff00, /* DENALI_CTL_274_DATA */
+ 0x1a160000, /* DENALI_CTL_275_DATA */
+ 0x08000012, /* DENALI_CTL_276_DATA */
+ 0x00000c20, /* DENALI_CTL_277_DATA */
+ 0x00000200, /* DENALI_CTL_278_DATA */
+ 0x00000200, /* DENALI_CTL_279_DATA */
+ 0x00000200, /* DENALI_CTL_280_DATA */
+ 0x00000200, /* DENALI_CTL_281_DATA */
+ 0x00000c20, /* DENALI_CTL_282_DATA */
+ 0x00007940, /* DENALI_CTL_283_DATA */
+ 0x18500409, /* DENALI_CTL_284_DATA */
+ 0x00000200, /* DENALI_CTL_285_DATA */
+ 0x00000200, /* DENALI_CTL_286_DATA */
+ 0x00000200, /* DENALI_CTL_287_DATA */
+ 0x00000200, /* DENALI_CTL_288_DATA */
+ 0x00001850, /* DENALI_CTL_289_DATA */
+ 0x0000f320, /* DENALI_CTL_290_DATA */
+ 0x0176060c, /* DENALI_CTL_291_DATA */
+ 0x00000200, /* DENALI_CTL_292_DATA */
+ 0x00000200, /* DENALI_CTL_293_DATA */
+ 0x00000200, /* DENALI_CTL_294_DATA */
+ 0x00000200, /* DENALI_CTL_295_DATA */
+ 0x00000176, /* DENALI_CTL_296_DATA */
+ 0x00000e9c, /* DENALI_CTL_297_DATA */
+ 0x02020205, /* DENALI_CTL_298_DATA */
+ 0x03030202, /* DENALI_CTL_299_DATA */
+ 0x00000018, /* DENALI_CTL_300_DATA */
+ 0x00000000, /* DENALI_CTL_301_DATA */
+ 0x00000000, /* DENALI_CTL_302_DATA */
+ 0x00001403, /* DENALI_CTL_303_DATA */
+ 0x00000000, /* DENALI_CTL_304_DATA */
+ 0x00000000, /* DENALI_CTL_305_DATA */
+ 0x00000000, /* DENALI_CTL_306_DATA */
+ 0x00030000, /* DENALI_CTL_307_DATA */
+ 0x000a001c, /* DENALI_CTL_308_DATA */
+ 0x000e0020, /* DENALI_CTL_309_DATA */
+ 0x00060018, /* DENALI_CTL_310_DATA */
+ 0x00000000, /* DENALI_CTL_311_DATA */
+ 0x00000000, /* DENALI_CTL_312_DATA */
+ 0x02000000, /* DENALI_CTL_313_DATA */
+ 0x00090305, /* DENALI_CTL_314_DATA */
+ 0x00050101, /* DENALI_CTL_315_DATA */
+ 0x00000000, /* DENALI_CTL_316_DATA */
+ 0x00000000, /* DENALI_CTL_317_DATA */
+ 0x00000000, /* DENALI_CTL_318_DATA */
+ 0x00000000, /* DENALI_CTL_319_DATA */
+ 0x00000000, /* DENALI_CTL_320_DATA */
+ 0x00000000, /* DENALI_CTL_321_DATA */
+ 0x00000000, /* DENALI_CTL_322_DATA */
+ 0x00000000, /* DENALI_CTL_323_DATA */
+ 0x01000001, /* DENALI_CTL_324_DATA */
+ 0x01010101, /* DENALI_CTL_325_DATA */
+ 0x01000101, /* DENALI_CTL_326_DATA */
+ 0x01000100, /* DENALI_CTL_327_DATA */
+ 0x00010001, /* DENALI_CTL_328_DATA */
+ 0x00010002, /* DENALI_CTL_329_DATA */
+ 0x00020100, /* DENALI_CTL_330_DATA */
+ 0x00000002 /* DENALI_CTL_331_DATA */
+ }
+ },
+ {
+ {
+ 0x00000b00, /* DENALI_PI_00_DATA */
+ 0x00000000, /* DENALI_PI_01_DATA */
+ 0x000002ec, /* DENALI_PI_02_DATA */
+ 0x00000176, /* DENALI_PI_03_DATA */
+ 0x000030a0, /* DENALI_PI_04_DATA */
+ 0x00001850, /* DENALI_PI_05_DATA */
+ 0x00001840, /* DENALI_PI_06_DATA */
+ 0x01760c20, /* DENALI_PI_07_DATA */
+ 0x00000200, /* DENALI_PI_08_DATA */
+ 0x00000200, /* DENALI_PI_09_DATA */
+ 0x00000200, /* DENALI_PI_10_DATA */
+ 0x00000200, /* DENALI_PI_11_DATA */
+ 0x00001850, /* DENALI_PI_12_DATA */
+ 0x00000200, /* DENALI_PI_13_DATA */
+ 0x00000200, /* DENALI_PI_14_DATA */
+ 0x00000200, /* DENALI_PI_15_DATA */
+ 0x00000200, /* DENALI_PI_16_DATA */
+ 0x00000c20, /* DENALI_PI_17_DATA */
+ 0x00000200, /* DENALI_PI_18_DATA */
+ 0x00000200, /* DENALI_PI_19_DATA */
+ 0x00000200, /* DENALI_PI_20_DATA */
+ 0x00000200, /* DENALI_PI_21_DATA */
+ 0x00010000, /* DENALI_PI_22_DATA */
+ 0x00000007, /* DENALI_PI_23_DATA */
+ 0x01000001, /* DENALI_PI_24_DATA */
+ 0x00000000, /* DENALI_PI_25_DATA */
+ 0x3fffffff, /* DENALI_PI_26_DATA */
+ 0x00000000, /* DENALI_PI_27_DATA */
+ 0x00000000, /* DENALI_PI_28_DATA */
+ 0x00000000, /* DENALI_PI_29_DATA */
+ 0x00000000, /* DENALI_PI_30_DATA */
+ 0x00000000, /* DENALI_PI_31_DATA */
+ 0x00000000, /* DENALI_PI_32_DATA */
+ 0x00000000, /* DENALI_PI_33_DATA */
+ 0x00000000, /* DENALI_PI_34_DATA */
+ 0x00000000, /* DENALI_PI_35_DATA */
+ 0x00000000, /* DENALI_PI_36_DATA */
+ 0x00000000, /* DENALI_PI_37_DATA */
+ 0x00000000, /* DENALI_PI_38_DATA */
+ 0x00000000, /* DENALI_PI_39_DATA */
+ 0x00000000, /* DENALI_PI_40_DATA */
+ 0x0f000101, /* DENALI_PI_41_DATA */
+ 0x082b3223, /* DENALI_PI_42_DATA */
+ 0x080c0004, /* DENALI_PI_43_DATA */
+ 0x00061c00, /* DENALI_PI_44_DATA */
+ 0x00000214, /* DENALI_PI_45_DATA */
+ 0x00bb0007, /* DENALI_PI_46_DATA */
+ 0x0c280068, /* DENALI_PI_47_DATA */
+ 0x06100034, /* DENALI_PI_48_DATA */
+ 0x00000500, /* DENALI_PI_49_DATA */
+ 0x00000000, /* DENALI_PI_50_DATA */
+ 0x00000000, /* DENALI_PI_51_DATA */
+ 0x00000000, /* DENALI_PI_52_DATA */
+ 0x00000000, /* DENALI_PI_53_DATA */
+ 0x00000000, /* DENALI_PI_54_DATA */
+ 0x00000000, /* DENALI_PI_55_DATA */
+ 0x00000000, /* DENALI_PI_56_DATA */
+ 0x00000000, /* DENALI_PI_57_DATA */
+ 0x04040100, /* DENALI_PI_58_DATA */
+ 0x0a000004, /* DENALI_PI_59_DATA */
+ 0x00000128, /* DENALI_PI_60_DATA */
+ 0x00000000, /* DENALI_PI_61_DATA */
+ 0x0003000f, /* DENALI_PI_62_DATA */
+ 0x00000018, /* DENALI_PI_63_DATA */
+ 0x00000000, /* DENALI_PI_64_DATA */
+ 0x00000000, /* DENALI_PI_65_DATA */
+ 0x00060002, /* DENALI_PI_66_DATA */
+ 0x00010001, /* DENALI_PI_67_DATA */
+ 0x00000101, /* DENALI_PI_68_DATA */
+ 0x00020001, /* DENALI_PI_69_DATA */
+ 0x00080004, /* DENALI_PI_70_DATA */
+ 0x00000000, /* DENALI_PI_71_DATA */
+ 0x05030000, /* DENALI_PI_72_DATA */
+ 0x070a0404, /* DENALI_PI_73_DATA */
+ 0x00000000, /* DENALI_PI_74_DATA */
+ 0x00000000, /* DENALI_PI_75_DATA */
+ 0x00000000, /* DENALI_PI_76_DATA */
+ 0x000f0f00, /* DENALI_PI_77_DATA */
+ 0x0000001e, /* DENALI_PI_78_DATA */
+ 0x00000000, /* DENALI_PI_79_DATA */
+ 0x01010300, /* DENALI_PI_80_DATA */
+ 0x00000000, /* DENALI_PI_81_DATA */
+ 0x00000000, /* DENALI_PI_82_DATA */
+ 0x01000000, /* DENALI_PI_83_DATA */
+ 0x00000101, /* DENALI_PI_84_DATA */
+ 0x55555a5a, /* DENALI_PI_85_DATA */
+ 0x55555a5a, /* DENALI_PI_86_DATA */
+ 0x55555a5a, /* DENALI_PI_87_DATA */
+ 0x55555a5a, /* DENALI_PI_88_DATA */
+ 0x0c050001, /* DENALI_PI_89_DATA */
+ 0x06020009, /* DENALI_PI_90_DATA */
+ 0x00010004, /* DENALI_PI_91_DATA */
+ 0x00000203, /* DENALI_PI_92_DATA */
+ 0x00030000, /* DENALI_PI_93_DATA */
+ 0x170f0000, /* DENALI_PI_94_DATA */
+ 0x00060018, /* DENALI_PI_95_DATA */
+ 0x000e0020, /* DENALI_PI_96_DATA */
+ 0x000a001c, /* DENALI_PI_97_DATA */
+ 0x00000000, /* DENALI_PI_98_DATA */
+ 0x00000000, /* DENALI_PI_99_DATA */
+ 0x00000100, /* DENALI_PI_100_DATA */
+ 0x140a0000, /* DENALI_PI_101_DATA */
+ 0x000d010a, /* DENALI_PI_102_DATA */
+ 0x0100c802, /* DENALI_PI_103_DATA */
+ 0x010a0064, /* DENALI_PI_104_DATA */
+ 0x000e0100, /* DENALI_PI_105_DATA */
+ 0x0100000e, /* DENALI_PI_106_DATA */
+ 0x00c900c9, /* DENALI_PI_107_DATA */
+ 0x00650100, /* DENALI_PI_108_DATA */
+ 0x1e1a0065, /* DENALI_PI_109_DATA */
+ 0x10010204, /* DENALI_PI_110_DATA */
+ 0x06070605, /* DENALI_PI_111_DATA */
+ 0x20000202, /* DENALI_PI_112_DATA */
+ 0x00201000, /* DENALI_PI_113_DATA */
+ 0x00201000, /* DENALI_PI_114_DATA */
+ 0x04041000, /* DENALI_PI_115_DATA */
+ 0x10020100, /* DENALI_PI_116_DATA */
+ 0x0003010c, /* DENALI_PI_117_DATA */
+ 0x004b004a, /* DENALI_PI_118_DATA */
+ 0x1a0f0000, /* DENALI_PI_119_DATA */
+ 0x0102041e, /* DENALI_PI_120_DATA */
+ 0x34000000, /* DENALI_PI_121_DATA */
+ 0x00000000, /* DENALI_PI_122_DATA */
+ 0x00000000, /* DENALI_PI_123_DATA */
+ 0x00010000, /* DENALI_PI_124_DATA */
+ 0x00000400, /* DENALI_PI_125_DATA */
+ 0x00310000, /* DENALI_PI_126_DATA */
+ 0x004d4d00, /* DENALI_PI_127_DATA */
+ 0x00120024, /* DENALI_PI_128_DATA */
+ 0x4d000031, /* DENALI_PI_129_DATA */
+ 0x0000144d, /* DENALI_PI_130_DATA */
+ 0x00310009, /* DENALI_PI_131_DATA */
+ 0x004d4d00, /* DENALI_PI_132_DATA */
+ 0x00000004, /* DENALI_PI_133_DATA */
+ 0x4d000031, /* DENALI_PI_134_DATA */
+ 0x0000244d, /* DENALI_PI_135_DATA */
+ 0x00310012, /* DENALI_PI_136_DATA */
+ 0x004d4d00, /* DENALI_PI_137_DATA */
+ 0x00090014, /* DENALI_PI_138_DATA */
+ 0x4d000031, /* DENALI_PI_139_DATA */
+ 0x0004004d, /* DENALI_PI_140_DATA */
+ 0x00310000, /* DENALI_PI_141_DATA */
+ 0x004d4d00, /* DENALI_PI_142_DATA */
+ 0x00120024, /* DENALI_PI_143_DATA */
+ 0x4d000031, /* DENALI_PI_144_DATA */
+ 0x0000144d, /* DENALI_PI_145_DATA */
+ 0x00310009, /* DENALI_PI_146_DATA */
+ 0x004d4d00, /* DENALI_PI_147_DATA */
+ 0x00000004, /* DENALI_PI_148_DATA */
+ 0x4d000031, /* DENALI_PI_149_DATA */
+ 0x0000244d, /* DENALI_PI_150_DATA */
+ 0x00310012, /* DENALI_PI_151_DATA */
+ 0x004d4d00, /* DENALI_PI_152_DATA */
+ 0x00090014, /* DENALI_PI_153_DATA */
+ 0x4d000031, /* DENALI_PI_154_DATA */
+ 0x0200004d, /* DENALI_PI_155_DATA */
+ 0x00c8000d, /* DENALI_PI_156_DATA */
+ 0x08080064, /* DENALI_PI_157_DATA */
+ 0x040a0404, /* DENALI_PI_158_DATA */
+ 0x03000d92, /* DENALI_PI_159_DATA */
+ 0x010a2001, /* DENALI_PI_160_DATA */
+ 0x0f11080a, /* DENALI_PI_161_DATA */
+ 0x0000110a, /* DENALI_PI_162_DATA */
+ 0x2200d92e, /* DENALI_PI_163_DATA */
+ 0x080c2003, /* DENALI_PI_164_DATA */
+ 0x0809080a, /* DENALI_PI_165_DATA */
+ 0x00000a0a, /* DENALI_PI_166_DATA */
+ 0x11006c97, /* DENALI_PI_167_DATA */
+ 0x040a2002, /* DENALI_PI_168_DATA */
+ 0x0200020a, /* DENALI_PI_169_DATA */
+ 0x02000200, /* DENALI_PI_170_DATA */
+ 0x02000200, /* DENALI_PI_171_DATA */
+ 0x02000200, /* DENALI_PI_172_DATA */
+ 0x02000200, /* DENALI_PI_173_DATA */
+ 0x00000000, /* DENALI_PI_174_DATA */
+ 0x00000000, /* DENALI_PI_175_DATA */
+ 0x00000000, /* DENALI_PI_176_DATA */
+ 0x00000000, /* DENALI_PI_177_DATA */
+ 0x00000000, /* DENALI_PI_178_DATA */
+ 0x00000000, /* DENALI_PI_179_DATA */
+ 0x00000000, /* DENALI_PI_180_DATA */
+ 0x00000000, /* DENALI_PI_181_DATA */
+ 0x00000000, /* DENALI_PI_182_DATA */
+ 0x00000000, /* DENALI_PI_183_DATA */
+ 0x00000000, /* DENALI_PI_184_DATA */
+ 0x00000000, /* DENALI_PI_185_DATA */
+ 0x01000400, /* DENALI_PI_186_DATA */
+ 0x00017600, /* DENALI_PI_187_DATA */
+ 0x00000e9c, /* DENALI_PI_188_DATA */
+ 0x00001850, /* DENALI_PI_189_DATA */
+ 0x0000f320, /* DENALI_PI_190_DATA */
+ 0x00000c20, /* DENALI_PI_191_DATA */
+ 0x00007940, /* DENALI_PI_192_DATA */
+ 0x08000000, /* DENALI_PI_193_DATA */
+ 0x00000100, /* DENALI_PI_194_DATA */
+ 0x00000000, /* DENALI_PI_195_DATA */
+ 0x00000000, /* DENALI_PI_196_DATA */
+ 0x00000000, /* DENALI_PI_197_DATA */
+ 0x00000000, /* DENALI_PI_198_DATA */
+ 0x00000002 /* DENALI_PI_199_DATA */
+ }
+ },
+ {
+ {
+ 0x76543210, /* DENALI_PHY_00_DATA */
+ 0x0004f008, /* DENALI_PHY_01_DATA */
+ 0x00020119, /* DENALI_PHY_02_DATA */
+ 0x00000000, /* DENALI_PHY_03_DATA */
+ 0x00000000, /* DENALI_PHY_04_DATA */
+ 0x00010000, /* DENALI_PHY_05_DATA */
+ 0x01665555, /* DENALI_PHY_06_DATA */
+ 0x03665555, /* DENALI_PHY_07_DATA */
+ 0x00010f00, /* DENALI_PHY_08_DATA */
+ 0x05010200, /* DENALI_PHY_09_DATA */
+ 0x00000002, /* DENALI_PHY_10_DATA */
+ 0x00170180, /* DENALI_PHY_11_DATA */
+ 0x00cc0201, /* DENALI_PHY_12_DATA */
+ 0x00030066, /* DENALI_PHY_13_DATA */
+ 0x00000000, /* DENALI_PHY_14_DATA */
+ 0x00000000, /* DENALI_PHY_15_DATA */
+ 0x00000000, /* DENALI_PHY_16_DATA */
+ 0x00000000, /* DENALI_PHY_17_DATA */
+ 0x00000000, /* DENALI_PHY_18_DATA */
+ 0x00000000, /* DENALI_PHY_19_DATA */
+ 0x00000000, /* DENALI_PHY_20_DATA */
+ 0x00000000, /* DENALI_PHY_21_DATA */
+ 0x04080000, /* DENALI_PHY_22_DATA */
+ 0x04080400, /* DENALI_PHY_23_DATA */
+ 0x30000000, /* DENALI_PHY_24_DATA */
+ 0x0c00c007, /* DENALI_PHY_25_DATA */
+ 0x00000100, /* DENALI_PHY_26_DATA */
+ 0x00000000, /* DENALI_PHY_27_DATA */
+ 0xfd02fe01, /* DENALI_PHY_28_DATA */
+ 0xf708fb04, /* DENALI_PHY_29_DATA */
+ 0xdf20ef10, /* DENALI_PHY_30_DATA */
+ 0x7f80bf40, /* DENALI_PHY_31_DATA */
+ 0x0001aaaa, /* DENALI_PHY_32_DATA */
+ 0x00000000, /* DENALI_PHY_33_DATA */
+ 0x00000000, /* DENALI_PHY_34_DATA */
+ 0x00000000, /* DENALI_PHY_35_DATA */
+ 0x00000000, /* DENALI_PHY_36_DATA */
+ 0x00000000, /* DENALI_PHY_37_DATA */
+ 0x00000000, /* DENALI_PHY_38_DATA */
+ 0x00000000, /* DENALI_PHY_39_DATA */
+ 0x00000000, /* DENALI_PHY_40_DATA */
+ 0x00000000, /* DENALI_PHY_41_DATA */
+ 0x00000000, /* DENALI_PHY_42_DATA */
+ 0x00000000, /* DENALI_PHY_43_DATA */
+ 0x00000000, /* DENALI_PHY_44_DATA */
+ 0x00000000, /* DENALI_PHY_45_DATA */
+ 0x00000000, /* DENALI_PHY_46_DATA */
+ 0x00000000, /* DENALI_PHY_47_DATA */
+ 0x00000000, /* DENALI_PHY_48_DATA */
+ 0x00000000, /* DENALI_PHY_49_DATA */
+ 0x00000000, /* DENALI_PHY_50_DATA */
+ 0x00000000, /* DENALI_PHY_51_DATA */
+ 0x00200000, /* DENALI_PHY_52_DATA */
+ 0x00000000, /* DENALI_PHY_53_DATA */
+ 0x00000000, /* DENALI_PHY_54_DATA */
+ 0x00000000, /* DENALI_PHY_55_DATA */
+ 0x00000000, /* DENALI_PHY_56_DATA */
+ 0x00000000, /* DENALI_PHY_57_DATA */
+ 0x00000000, /* DENALI_PHY_58_DATA */
+ 0x02800280, /* DENALI_PHY_59_DATA */
+ 0x02800280, /* DENALI_PHY_60_DATA */
+ 0x02800280, /* DENALI_PHY_61_DATA */
+ 0x02800280, /* DENALI_PHY_62_DATA */
+ 0x00000280, /* DENALI_PHY_63_DATA */
+ 0x00000000, /* DENALI_PHY_64_DATA */
+ 0x00000000, /* DENALI_PHY_65_DATA */
+ 0x00000000, /* DENALI_PHY_66_DATA */
+ 0x00000000, /* DENALI_PHY_67_DATA */
+ 0x00800000, /* DENALI_PHY_68_DATA */
+ 0x00800080, /* DENALI_PHY_69_DATA */
+ 0x00800080, /* DENALI_PHY_70_DATA */
+ 0x00800080, /* DENALI_PHY_71_DATA */
+ 0x00800080, /* DENALI_PHY_72_DATA */
+ 0x00800080, /* DENALI_PHY_73_DATA */
+ 0x00800080, /* DENALI_PHY_74_DATA */
+ 0x00800080, /* DENALI_PHY_75_DATA */
+ 0x00800080, /* DENALI_PHY_76_DATA */
+ 0x01190080, /* DENALI_PHY_77_DATA */
+ 0x00000002, /* DENALI_PHY_78_DATA */
+ 0x00000000, /* DENALI_PHY_79_DATA */
+ 0x00000000, /* DENALI_PHY_80_DATA */
+ 0x00000200, /* DENALI_PHY_81_DATA */
+ 0x00000000, /* DENALI_PHY_82_DATA */
+ 0x51315152, /* DENALI_PHY_83_DATA */
+ 0xc0013150, /* DENALI_PHY_84_DATA */
+ 0x020000c0, /* DENALI_PHY_85_DATA */
+ 0x00100001, /* DENALI_PHY_86_DATA */
+ 0x07054204, /* DENALI_PHY_87_DATA */
+ 0x000f0c18, /* DENALI_PHY_88_DATA */
+ 0x01000140, /* DENALI_PHY_89_DATA */
+ 0x00000c10, /* DENALI_PHY_90_DATA */
+ 0x00000000, /* DENALI_PHY_91_DATA */
+ 0x00000000, /* DENALI_PHY_92_DATA */
+ 0x00000000, /* DENALI_PHY_93_DATA */
+ 0x00000000, /* DENALI_PHY_94_DATA */
+ 0x00000000, /* DENALI_PHY_95_DATA */
+ 0x00000000, /* DENALI_PHY_96_DATA */
+ 0x00000000, /* DENALI_PHY_97_DATA */
+ 0x00000000, /* DENALI_PHY_98_DATA */
+ 0x00000000, /* DENALI_PHY_99_DATA */
+ 0x00000000, /* DENALI_PHY_100_DATA */
+ 0x00000000, /* DENALI_PHY_101_DATA */
+ 0x00000000, /* DENALI_PHY_102_DATA */
+ 0x00000000, /* DENALI_PHY_103_DATA */
+ 0x00000000, /* DENALI_PHY_104_DATA */
+ 0x00000000, /* DENALI_PHY_105_DATA */
+ 0x00000000, /* DENALI_PHY_106_DATA */
+ 0x00000000, /* DENALI_PHY_107_DATA */
+ 0x00000000, /* DENALI_PHY_108_DATA */
+ 0x00000000, /* DENALI_PHY_109_DATA */
+ 0x00000000, /* DENALI_PHY_110_DATA */
+ 0x00000000, /* DENALI_PHY_111_DATA */
+ 0x00000000, /* DENALI_PHY_112_DATA */
+ 0x00000000, /* DENALI_PHY_113_DATA */
+ 0x00000000, /* DENALI_PHY_114_DATA */
+ 0x00000000, /* DENALI_PHY_115_DATA */
+ 0x00000000, /* DENALI_PHY_116_DATA */
+ 0x00000000, /* DENALI_PHY_117_DATA */
+ 0x00000000, /* DENALI_PHY_118_DATA */
+ 0x00000000, /* DENALI_PHY_119_DATA */
+ 0x00000000, /* DENALI_PHY_120_DATA */
+ 0x00000000, /* DENALI_PHY_121_DATA */
+ 0x00000000, /* DENALI_PHY_122_DATA */
+ 0x00000000, /* DENALI_PHY_123_DATA */
+ 0x00000000, /* DENALI_PHY_124_DATA */
+ 0x00000000, /* DENALI_PHY_125_DATA */
+ 0x00000000, /* DENALI_PHY_126_DATA */
+ 0x00000000, /* DENALI_PHY_127_DATA */
+ 0x76543210, /* DENALI_PHY_128_DATA */
+ 0x0004f008, /* DENALI_PHY_129_DATA */
+ 0x00020119, /* DENALI_PHY_130_DATA */
+ 0x00000000, /* DENALI_PHY_131_DATA */
+ 0x00000000, /* DENALI_PHY_132_DATA */
+ 0x00010000, /* DENALI_PHY_133_DATA */
+ 0x01665555, /* DENALI_PHY_134_DATA */
+ 0x03665555, /* DENALI_PHY_135_DATA */
+ 0x00010f00, /* DENALI_PHY_136_DATA */
+ 0x05010200, /* DENALI_PHY_137_DATA */
+ 0x00000002, /* DENALI_PHY_138_DATA */
+ 0x00170180, /* DENALI_PHY_139_DATA */
+ 0x00cc0201, /* DENALI_PHY_140_DATA */
+ 0x00030066, /* DENALI_PHY_141_DATA */
+ 0x00000000, /* DENALI_PHY_142_DATA */
+ 0x00000000, /* DENALI_PHY_143_DATA */
+ 0x00000000, /* DENALI_PHY_144_DATA */
+ 0x00000000, /* DENALI_PHY_145_DATA */
+ 0x00000000, /* DENALI_PHY_146_DATA */
+ 0x00000000, /* DENALI_PHY_147_DATA */
+ 0x00000000, /* DENALI_PHY_148_DATA */
+ 0x00000000, /* DENALI_PHY_149_DATA */
+ 0x04080000, /* DENALI_PHY_150_DATA */
+ 0x04080400, /* DENALI_PHY_151_DATA */
+ 0x30000000, /* DENALI_PHY_152_DATA */
+ 0x0c00c007, /* DENALI_PHY_153_DATA */
+ 0x00000100, /* DENALI_PHY_154_DATA */
+ 0x00000000, /* DENALI_PHY_155_DATA */
+ 0xfd02fe01, /* DENALI_PHY_156_DATA */
+ 0xf708fb04, /* DENALI_PHY_157_DATA */
+ 0xdf20ef10, /* DENALI_PHY_158_DATA */
+ 0x7f80bf40, /* DENALI_PHY_159_DATA */
+ 0x0000aaaa, /* DENALI_PHY_160_DATA */
+ 0x00000000, /* DENALI_PHY_161_DATA */
+ 0x00000000, /* DENALI_PHY_162_DATA */
+ 0x00000000, /* DENALI_PHY_163_DATA */
+ 0x00000000, /* DENALI_PHY_164_DATA */
+ 0x00000000, /* DENALI_PHY_165_DATA */
+ 0x00000000, /* DENALI_PHY_166_DATA */
+ 0x00000000, /* DENALI_PHY_167_DATA */
+ 0x00000000, /* DENALI_PHY_168_DATA */
+ 0x00000000, /* DENALI_PHY_169_DATA */
+ 0x00000000, /* DENALI_PHY_170_DATA */
+ 0x00000000, /* DENALI_PHY_171_DATA */
+ 0x00000000, /* DENALI_PHY_172_DATA */
+ 0x00000000, /* DENALI_PHY_173_DATA */
+ 0x00000000, /* DENALI_PHY_174_DATA */
+ 0x00000000, /* DENALI_PHY_175_DATA */
+ 0x00000000, /* DENALI_PHY_176_DATA */
+ 0x00000000, /* DENALI_PHY_177_DATA */
+ 0x00000000, /* DENALI_PHY_178_DATA */
+ 0x00000000, /* DENALI_PHY_179_DATA */
+ 0x00200000, /* DENALI_PHY_180_DATA */
+ 0x00000000, /* DENALI_PHY_181_DATA */
+ 0x00000000, /* DENALI_PHY_182_DATA */
+ 0x00000000, /* DENALI_PHY_183_DATA */
+ 0x00000000, /* DENALI_PHY_184_DATA */
+ 0x00000000, /* DENALI_PHY_185_DATA */
+ 0x00000000, /* DENALI_PHY_186_DATA */
+ 0x02800280, /* DENALI_PHY_187_DATA */
+ 0x02800280, /* DENALI_PHY_188_DATA */
+ 0x02800280, /* DENALI_PHY_189_DATA */
+ 0x02800280, /* DENALI_PHY_190_DATA */
+ 0x00000280, /* DENALI_PHY_191_DATA */
+ 0x00000000, /* DENALI_PHY_192_DATA */
+ 0x00000000, /* DENALI_PHY_193_DATA */
+ 0x00000000, /* DENALI_PHY_194_DATA */
+ 0x00000000, /* DENALI_PHY_195_DATA */
+ 0x00800000, /* DENALI_PHY_196_DATA */
+ 0x00800080, /* DENALI_PHY_197_DATA */
+ 0x00800080, /* DENALI_PHY_198_DATA */
+ 0x00800080, /* DENALI_PHY_199_DATA */
+ 0x00800080, /* DENALI_PHY_200_DATA */
+ 0x00800080, /* DENALI_PHY_201_DATA */
+ 0x00800080, /* DENALI_PHY_202_DATA */
+ 0x00800080, /* DENALI_PHY_203_DATA */
+ 0x00800080, /* DENALI_PHY_204_DATA */
+ 0x01190080, /* DENALI_PHY_205_DATA */
+ 0x00000002, /* DENALI_PHY_206_DATA */
+ 0x00000000, /* DENALI_PHY_207_DATA */
+ 0x00000000, /* DENALI_PHY_208_DATA */
+ 0x00000200, /* DENALI_PHY_209_DATA */
+ 0x00000000, /* DENALI_PHY_210_DATA */
+ 0x51315152, /* DENALI_PHY_211_DATA */
+ 0xc0013150, /* DENALI_PHY_212_DATA */
+ 0x020000c0, /* DENALI_PHY_213_DATA */
+ 0x00100001, /* DENALI_PHY_214_DATA */
+ 0x07054204, /* DENALI_PHY_215_DATA */
+ 0x000f0c18, /* DENALI_PHY_216_DATA */
+ 0x01000140, /* DENALI_PHY_217_DATA */
+ 0x00000c10, /* DENALI_PHY_218_DATA */
+ 0x00000000, /* DENALI_PHY_219_DATA */
+ 0x00000000, /* DENALI_PHY_220_DATA */
+ 0x00000000, /* DENALI_PHY_221_DATA */
+ 0x00000000, /* DENALI_PHY_222_DATA */
+ 0x00000000, /* DENALI_PHY_223_DATA */
+ 0x00000000, /* DENALI_PHY_224_DATA */
+ 0x00000000, /* DENALI_PHY_225_DATA */
+ 0x00000000, /* DENALI_PHY_226_DATA */
+ 0x00000000, /* DENALI_PHY_227_DATA */
+ 0x00000000, /* DENALI_PHY_228_DATA */
+ 0x00000000, /* DENALI_PHY_229_DATA */
+ 0x00000000, /* DENALI_PHY_230_DATA */
+ 0x00000000, /* DENALI_PHY_231_DATA */
+ 0x00000000, /* DENALI_PHY_232_DATA */
+ 0x00000000, /* DENALI_PHY_233_DATA */
+ 0x00000000, /* DENALI_PHY_234_DATA */
+ 0x00000000, /* DENALI_PHY_235_DATA */
+ 0x00000000, /* DENALI_PHY_236_DATA */
+ 0x00000000, /* DENALI_PHY_237_DATA */
+ 0x00000000, /* DENALI_PHY_238_DATA */
+ 0x00000000, /* DENALI_PHY_239_DATA */
+ 0x00000000, /* DENALI_PHY_240_DATA */
+ 0x00000000, /* DENALI_PHY_241_DATA */
+ 0x00000000, /* DENALI_PHY_242_DATA */
+ 0x00000000, /* DENALI_PHY_243_DATA */
+ 0x00000000, /* DENALI_PHY_244_DATA */
+ 0x00000000, /* DENALI_PHY_245_DATA */
+ 0x00000000, /* DENALI_PHY_246_DATA */
+ 0x00000000, /* DENALI_PHY_247_DATA */
+ 0x00000000, /* DENALI_PHY_248_DATA */
+ 0x00000000, /* DENALI_PHY_249_DATA */
+ 0x00000000, /* DENALI_PHY_250_DATA */
+ 0x00000000, /* DENALI_PHY_251_DATA */
+ 0x00000000, /* DENALI_PHY_252_DATA */
+ 0x00000000, /* DENALI_PHY_253_DATA */
+ 0x00000000, /* DENALI_PHY_254_DATA */
+ 0x00000000, /* DENALI_PHY_255_DATA */
+ 0x76543210, /* DENALI_PHY_256_DATA */
+ 0x0004f008, /* DENALI_PHY_257_DATA */
+ 0x00020119, /* DENALI_PHY_258_DATA */
+ 0x00000000, /* DENALI_PHY_259_DATA */
+ 0x00000000, /* DENALI_PHY_260_DATA */
+ 0x00010000, /* DENALI_PHY_261_DATA */
+ 0x01665555, /* DENALI_PHY_262_DATA */
+ 0x03665555, /* DENALI_PHY_263_DATA */
+ 0x00010f00, /* DENALI_PHY_264_DATA */
+ 0x05010200, /* DENALI_PHY_265_DATA */
+ 0x00000002, /* DENALI_PHY_266_DATA */
+ 0x00170180, /* DENALI_PHY_267_DATA */
+ 0x00cc0201, /* DENALI_PHY_268_DATA */
+ 0x00030066, /* DENALI_PHY_269_DATA */
+ 0x00000000, /* DENALI_PHY_270_DATA */
+ 0x00000000, /* DENALI_PHY_271_DATA */
+ 0x00000000, /* DENALI_PHY_272_DATA */
+ 0x00000000, /* DENALI_PHY_273_DATA */
+ 0x00000000, /* DENALI_PHY_274_DATA */
+ 0x00000000, /* DENALI_PHY_275_DATA */
+ 0x00000000, /* DENALI_PHY_276_DATA */
+ 0x00000000, /* DENALI_PHY_277_DATA */
+ 0x04080000, /* DENALI_PHY_278_DATA */
+ 0x04080400, /* DENALI_PHY_279_DATA */
+ 0x30000000, /* DENALI_PHY_280_DATA */
+ 0x0c00c007, /* DENALI_PHY_281_DATA */
+ 0x00000100, /* DENALI_PHY_282_DATA */
+ 0x00000000, /* DENALI_PHY_283_DATA */
+ 0xfd02fe01, /* DENALI_PHY_284_DATA */
+ 0xf708fb04, /* DENALI_PHY_285_DATA */
+ 0xdf20ef10, /* DENALI_PHY_286_DATA */
+ 0x7f80bf40, /* DENALI_PHY_287_DATA */
+ 0x0001aaaa, /* DENALI_PHY_288_DATA */
+ 0x00000000, /* DENALI_PHY_289_DATA */
+ 0x00000000, /* DENALI_PHY_290_DATA */
+ 0x00000000, /* DENALI_PHY_291_DATA */
+ 0x00000000, /* DENALI_PHY_292_DATA */
+ 0x00000000, /* DENALI_PHY_293_DATA */
+ 0x00000000, /* DENALI_PHY_294_DATA */
+ 0x00000000, /* DENALI_PHY_295_DATA */
+ 0x00000000, /* DENALI_PHY_296_DATA */
+ 0x00000000, /* DENALI_PHY_297_DATA */
+ 0x00000000, /* DENALI_PHY_298_DATA */
+ 0x00000000, /* DENALI_PHY_299_DATA */
+ 0x00000000, /* DENALI_PHY_300_DATA */
+ 0x00000000, /* DENALI_PHY_301_DATA */
+ 0x00000000, /* DENALI_PHY_302_DATA */
+ 0x00000000, /* DENALI_PHY_303_DATA */
+ 0x00000000, /* DENALI_PHY_304_DATA */
+ 0x00000000, /* DENALI_PHY_305_DATA */
+ 0x00000000, /* DENALI_PHY_306_DATA */
+ 0x00000000, /* DENALI_PHY_307_DATA */
+ 0x00200000, /* DENALI_PHY_308_DATA */
+ 0x00000000, /* DENALI_PHY_309_DATA */
+ 0x00000000, /* DENALI_PHY_310_DATA */
+ 0x00000000, /* DENALI_PHY_311_DATA */
+ 0x00000000, /* DENALI_PHY_312_DATA */
+ 0x00000000, /* DENALI_PHY_313_DATA */
+ 0x00000000, /* DENALI_PHY_314_DATA */
+ 0x02800280, /* DENALI_PHY_315_DATA */
+ 0x02800280, /* DENALI_PHY_316_DATA */
+ 0x02800280, /* DENALI_PHY_317_DATA */
+ 0x02800280, /* DENALI_PHY_318_DATA */
+ 0x00000280, /* DENALI_PHY_319_DATA */
+ 0x00000000, /* DENALI_PHY_320_DATA */
+ 0x00000000, /* DENALI_PHY_321_DATA */
+ 0x00000000, /* DENALI_PHY_322_DATA */
+ 0x00000000, /* DENALI_PHY_323_DATA */
+ 0x00800000, /* DENALI_PHY_324_DATA */
+ 0x00800080, /* DENALI_PHY_325_DATA */
+ 0x00800080, /* DENALI_PHY_326_DATA */
+ 0x00800080, /* DENALI_PHY_327_DATA */
+ 0x00800080, /* DENALI_PHY_328_DATA */
+ 0x00800080, /* DENALI_PHY_329_DATA */
+ 0x00800080, /* DENALI_PHY_330_DATA */
+ 0x00800080, /* DENALI_PHY_331_DATA */
+ 0x00800080, /* DENALI_PHY_332_DATA */
+ 0x01190080, /* DENALI_PHY_333_DATA */
+ 0x00000002, /* DENALI_PHY_334_DATA */
+ 0x00000000, /* DENALI_PHY_335_DATA */
+ 0x00000000, /* DENALI_PHY_336_DATA */
+ 0x00000200, /* DENALI_PHY_337_DATA */
+ 0x00000000, /* DENALI_PHY_338_DATA */
+ 0x51315152, /* DENALI_PHY_339_DATA */
+ 0xc0013150, /* DENALI_PHY_340_DATA */
+ 0x020000c0, /* DENALI_PHY_341_DATA */
+ 0x00100001, /* DENALI_PHY_342_DATA */
+ 0x07054204, /* DENALI_PHY_343_DATA */
+ 0x000f0c18, /* DENALI_PHY_344_DATA */
+ 0x01000140, /* DENALI_PHY_345_DATA */
+ 0x00000c10, /* DENALI_PHY_346_DATA */
+ 0x00000000, /* DENALI_PHY_347_DATA */
+ 0x00000000, /* DENALI_PHY_348_DATA */
+ 0x00000000, /* DENALI_PHY_349_DATA */
+ 0x00000000, /* DENALI_PHY_350_DATA */
+ 0x00000000, /* DENALI_PHY_351_DATA */
+ 0x00000000, /* DENALI_PHY_352_DATA */
+ 0x00000000, /* DENALI_PHY_353_DATA */
+ 0x00000000, /* DENALI_PHY_354_DATA */
+ 0x00000000, /* DENALI_PHY_355_DATA */
+ 0x00000000, /* DENALI_PHY_356_DATA */
+ 0x00000000, /* DENALI_PHY_357_DATA */
+ 0x00000000, /* DENALI_PHY_358_DATA */
+ 0x00000000, /* DENALI_PHY_359_DATA */
+ 0x00000000, /* DENALI_PHY_360_DATA */
+ 0x00000000, /* DENALI_PHY_361_DATA */
+ 0x00000000, /* DENALI_PHY_362_DATA */
+ 0x00000000, /* DENALI_PHY_363_DATA */
+ 0x00000000, /* DENALI_PHY_364_DATA */
+ 0x00000000, /* DENALI_PHY_365_DATA */
+ 0x00000000, /* DENALI_PHY_366_DATA */
+ 0x00000000, /* DENALI_PHY_367_DATA */
+ 0x00000000, /* DENALI_PHY_368_DATA */
+ 0x00000000, /* DENALI_PHY_369_DATA */
+ 0x00000000, /* DENALI_PHY_370_DATA */
+ 0x00000000, /* DENALI_PHY_371_DATA */
+ 0x00000000, /* DENALI_PHY_372_DATA */
+ 0x00000000, /* DENALI_PHY_373_DATA */
+ 0x00000000, /* DENALI_PHY_374_DATA */
+ 0x00000000, /* DENALI_PHY_375_DATA */
+ 0x00000000, /* DENALI_PHY_376_DATA */
+ 0x00000000, /* DENALI_PHY_377_DATA */
+ 0x00000000, /* DENALI_PHY_378_DATA */
+ 0x00000000, /* DENALI_PHY_379_DATA */
+ 0x00000000, /* DENALI_PHY_380_DATA */
+ 0x00000000, /* DENALI_PHY_381_DATA */
+ 0x00000000, /* DENALI_PHY_382_DATA */
+ 0x00000000, /* DENALI_PHY_383_DATA */
+ 0x76543210, /* DENALI_PHY_384_DATA */
+ 0x0004f008, /* DENALI_PHY_385_DATA */
+ 0x00020119, /* DENALI_PHY_386_DATA */
+ 0x00000000, /* DENALI_PHY_387_DATA */
+ 0x00000000, /* DENALI_PHY_388_DATA */
+ 0x00010000, /* DENALI_PHY_389_DATA */
+ 0x01665555, /* DENALI_PHY_390_DATA */
+ 0x03665555, /* DENALI_PHY_391_DATA */
+ 0x00010f00, /* DENALI_PHY_392_DATA */
+ 0x05010200, /* DENALI_PHY_393_DATA */
+ 0x00000002, /* DENALI_PHY_394_DATA */
+ 0x00170180, /* DENALI_PHY_395_DATA */
+ 0x00cc0201, /* DENALI_PHY_396_DATA */
+ 0x00030066, /* DENALI_PHY_397_DATA */
+ 0x00000000, /* DENALI_PHY_398_DATA */
+ 0x00000000, /* DENALI_PHY_399_DATA */
+ 0x00000000, /* DENALI_PHY_400_DATA */
+ 0x00000000, /* DENALI_PHY_401_DATA */
+ 0x00000000, /* DENALI_PHY_402_DATA */
+ 0x00000000, /* DENALI_PHY_403_DATA */
+ 0x00000000, /* DENALI_PHY_404_DATA */
+ 0x00000000, /* DENALI_PHY_405_DATA */
+ 0x04080000, /* DENALI_PHY_406_DATA */
+ 0x04080400, /* DENALI_PHY_407_DATA */
+ 0x30000000, /* DENALI_PHY_408_DATA */
+ 0x0c00c007, /* DENALI_PHY_409_DATA */
+ 0x00000100, /* DENALI_PHY_410_DATA */
+ 0x00000000, /* DENALI_PHY_411_DATA */
+ 0xfd02fe01, /* DENALI_PHY_412_DATA */
+ 0xf708fb04, /* DENALI_PHY_413_DATA */
+ 0xdf20ef10, /* DENALI_PHY_414_DATA */
+ 0x7f80bf40, /* DENALI_PHY_415_DATA */
+ 0x0000aaaa, /* DENALI_PHY_416_DATA */
+ 0x00000000, /* DENALI_PHY_417_DATA */
+ 0x00000000, /* DENALI_PHY_418_DATA */
+ 0x00000000, /* DENALI_PHY_419_DATA */
+ 0x00000000, /* DENALI_PHY_420_DATA */
+ 0x00000000, /* DENALI_PHY_421_DATA */
+ 0x00000000, /* DENALI_PHY_422_DATA */
+ 0x00000000, /* DENALI_PHY_423_DATA */
+ 0x00000000, /* DENALI_PHY_424_DATA */
+ 0x00000000, /* DENALI_PHY_425_DATA */
+ 0x00000000, /* DENALI_PHY_426_DATA */
+ 0x00000000, /* DENALI_PHY_427_DATA */
+ 0x00000000, /* DENALI_PHY_428_DATA */
+ 0x00000000, /* DENALI_PHY_429_DATA */
+ 0x00000000, /* DENALI_PHY_430_DATA */
+ 0x00000000, /* DENALI_PHY_431_DATA */
+ 0x00000000, /* DENALI_PHY_432_DATA */
+ 0x00000000, /* DENALI_PHY_433_DATA */
+ 0x00000000, /* DENALI_PHY_434_DATA */
+ 0x00000000, /* DENALI_PHY_435_DATA */
+ 0x00200000, /* DENALI_PHY_436_DATA */
+ 0x00000000, /* DENALI_PHY_437_DATA */
+ 0x00000000, /* DENALI_PHY_438_DATA */
+ 0x00000000, /* DENALI_PHY_439_DATA */
+ 0x00000000, /* DENALI_PHY_440_DATA */
+ 0x00000000, /* DENALI_PHY_441_DATA */
+ 0x00000000, /* DENALI_PHY_442_DATA */
+ 0x02800280, /* DENALI_PHY_443_DATA */
+ 0x02800280, /* DENALI_PHY_444_DATA */
+ 0x02800280, /* DENALI_PHY_445_DATA */
+ 0x02800280, /* DENALI_PHY_446_DATA */
+ 0x00000280, /* DENALI_PHY_447_DATA */
+ 0x00000000, /* DENALI_PHY_448_DATA */
+ 0x00000000, /* DENALI_PHY_449_DATA */
+ 0x00000000, /* DENALI_PHY_450_DATA */
+ 0x00000000, /* DENALI_PHY_451_DATA */
+ 0x00800000, /* DENALI_PHY_452_DATA */
+ 0x00800080, /* DENALI_PHY_453_DATA */
+ 0x00800080, /* DENALI_PHY_454_DATA */
+ 0x00800080, /* DENALI_PHY_455_DATA */
+ 0x00800080, /* DENALI_PHY_456_DATA */
+ 0x00800080, /* DENALI_PHY_457_DATA */
+ 0x00800080, /* DENALI_PHY_458_DATA */
+ 0x00800080, /* DENALI_PHY_459_DATA */
+ 0x00800080, /* DENALI_PHY_460_DATA */
+ 0x01190080, /* DENALI_PHY_461_DATA */
+ 0x00000002, /* DENALI_PHY_462_DATA */
+ 0x00000000, /* DENALI_PHY_463_DATA */
+ 0x00000000, /* DENALI_PHY_464_DATA */
+ 0x00000200, /* DENALI_PHY_465_DATA */
+ 0x00000000, /* DENALI_PHY_466_DATA */
+ 0x51315152, /* DENALI_PHY_467_DATA */
+ 0xc0013150, /* DENALI_PHY_468_DATA */
+ 0x020000c0, /* DENALI_PHY_469_DATA */
+ 0x00100001, /* DENALI_PHY_470_DATA */
+ 0x07054204, /* DENALI_PHY_471_DATA */
+ 0x000f0c18, /* DENALI_PHY_472_DATA */
+ 0x01000140, /* DENALI_PHY_473_DATA */
+ 0x00000c10, /* DENALI_PHY_474_DATA */
+ 0x00000000, /* DENALI_PHY_475_DATA */
+ 0x00000000, /* DENALI_PHY_476_DATA */
+ 0x00000000, /* DENALI_PHY_477_DATA */
+ 0x00000000, /* DENALI_PHY_478_DATA */
+ 0x00000000, /* DENALI_PHY_479_DATA */
+ 0x00000000, /* DENALI_PHY_480_DATA */
+ 0x00000000, /* DENALI_PHY_481_DATA */
+ 0x00000000, /* DENALI_PHY_482_DATA */
+ 0x00000000, /* DENALI_PHY_483_DATA */
+ 0x00000000, /* DENALI_PHY_484_DATA */
+ 0x00000000, /* DENALI_PHY_485_DATA */
+ 0x00000000, /* DENALI_PHY_486_DATA */
+ 0x00000000, /* DENALI_PHY_487_DATA */
+ 0x00000000, /* DENALI_PHY_488_DATA */
+ 0x00000000, /* DENALI_PHY_489_DATA */
+ 0x00000000, /* DENALI_PHY_490_DATA */
+ 0x00000000, /* DENALI_PHY_491_DATA */
+ 0x00000000, /* DENALI_PHY_492_DATA */
+ 0x00000000, /* DENALI_PHY_493_DATA */
+ 0x00000000, /* DENALI_PHY_494_DATA */
+ 0x00000000, /* DENALI_PHY_495_DATA */
+ 0x00000000, /* DENALI_PHY_496_DATA */
+ 0x00000000, /* DENALI_PHY_497_DATA */
+ 0x00000000, /* DENALI_PHY_498_DATA */
+ 0x00000000, /* DENALI_PHY_499_DATA */
+ 0x00000000, /* DENALI_PHY_500_DATA */
+ 0x00000000, /* DENALI_PHY_501_DATA */
+ 0x00000000, /* DENALI_PHY_502_DATA */
+ 0x00000000, /* DENALI_PHY_503_DATA */
+ 0x00000000, /* DENALI_PHY_504_DATA */
+ 0x00000000, /* DENALI_PHY_505_DATA */
+ 0x00000000, /* DENALI_PHY_506_DATA */
+ 0x00000000, /* DENALI_PHY_507_DATA */
+ 0x00000000, /* DENALI_PHY_508_DATA */
+ 0x00000000, /* DENALI_PHY_509_DATA */
+ 0x00000000, /* DENALI_PHY_510_DATA */
+ 0x00000000, /* DENALI_PHY_511_DATA */
+ 0x00000000, /* DENALI_PHY_512_DATA */
+ 0x00000000, /* DENALI_PHY_513_DATA */
+ 0x00000000, /* DENALI_PHY_514_DATA */
+ 0x00000000, /* DENALI_PHY_515_DATA */
+ 0x00000000, /* DENALI_PHY_516_DATA */
+ 0x00000000, /* DENALI_PHY_517_DATA */
+ 0x00000000, /* DENALI_PHY_518_DATA */
+ 0x00000002, /* DENALI_PHY_519_DATA */
+ 0x00000000, /* DENALI_PHY_520_DATA */
+ 0x00000000, /* DENALI_PHY_521_DATA */
+ 0x00000000, /* DENALI_PHY_522_DATA */
+ 0x00400320, /* DENALI_PHY_523_DATA */
+ 0x00000040, /* DENALI_PHY_524_DATA */
+ 0x00dcba98, /* DENALI_PHY_525_DATA */
+ 0x00000000, /* DENALI_PHY_526_DATA */
+ 0x00dcba98, /* DENALI_PHY_527_DATA */
+ 0x01000000, /* DENALI_PHY_528_DATA */
+ 0x00020003, /* DENALI_PHY_529_DATA */
+ 0x00000000, /* DENALI_PHY_530_DATA */
+ 0x00000000, /* DENALI_PHY_531_DATA */
+ 0x00000000, /* DENALI_PHY_532_DATA */
+ 0x0000002a, /* DENALI_PHY_533_DATA */
+ 0x00000015, /* DENALI_PHY_534_DATA */
+ 0x00000015, /* DENALI_PHY_535_DATA */
+ 0x0000002a, /* DENALI_PHY_536_DATA */
+ 0x00000033, /* DENALI_PHY_537_DATA */
+ 0x0000000c, /* DENALI_PHY_538_DATA */
+ 0x0000000c, /* DENALI_PHY_539_DATA */
+ 0x00000033, /* DENALI_PHY_540_DATA */
+ 0x0a418820, /* DENALI_PHY_541_DATA */
+ 0x003f0000, /* DENALI_PHY_542_DATA */
+ 0x0000003f, /* DENALI_PHY_543_DATA */
+ 0x00030055, /* DENALI_PHY_544_DATA */
+ 0x03000300, /* DENALI_PHY_545_DATA */
+ 0x03000300, /* DENALI_PHY_546_DATA */
+ 0x00000300, /* DENALI_PHY_547_DATA */
+ 0x42080010, /* DENALI_PHY_548_DATA */
+ 0x00000003, /* DENALI_PHY_549_DATA */
+ 0x00000000, /* DENALI_PHY_550_DATA */
+ 0x00000000, /* DENALI_PHY_551_DATA */
+ 0x00000000, /* DENALI_PHY_552_DATA */
+ 0x00000000, /* DENALI_PHY_553_DATA */
+ 0x00000000, /* DENALI_PHY_554_DATA */
+ 0x00000000, /* DENALI_PHY_555_DATA */
+ 0x00000000, /* DENALI_PHY_556_DATA */
+ 0x00000000, /* DENALI_PHY_557_DATA */
+ 0x00000000, /* DENALI_PHY_558_DATA */
+ 0x00000000, /* DENALI_PHY_559_DATA */
+ 0x00000000, /* DENALI_PHY_560_DATA */
+ 0x00000000, /* DENALI_PHY_561_DATA */
+ 0x00000000, /* DENALI_PHY_562_DATA */
+ 0x00000000, /* DENALI_PHY_563_DATA */
+ 0x00000000, /* DENALI_PHY_564_DATA */
+ 0x00000000, /* DENALI_PHY_565_DATA */
+ 0x00000000, /* DENALI_PHY_566_DATA */
+ 0x00000000, /* DENALI_PHY_567_DATA */
+ 0x00000000, /* DENALI_PHY_568_DATA */
+ 0x00000000, /* DENALI_PHY_569_DATA */
+ 0x00000000, /* DENALI_PHY_570_DATA */
+ 0x00000000, /* DENALI_PHY_571_DATA */
+ 0x00000000, /* DENALI_PHY_572_DATA */
+ 0x00000000, /* DENALI_PHY_573_DATA */
+ 0x00000000, /* DENALI_PHY_574_DATA */
+ 0x00000000, /* DENALI_PHY_575_DATA */
+ 0x00000000, /* DENALI_PHY_576_DATA */
+ 0x00000000, /* DENALI_PHY_577_DATA */
+ 0x00000000, /* DENALI_PHY_578_DATA */
+ 0x00000000, /* DENALI_PHY_579_DATA */
+ 0x00000000, /* DENALI_PHY_580_DATA */
+ 0x00000000, /* DENALI_PHY_581_DATA */
+ 0x00000000, /* DENALI_PHY_582_DATA */
+ 0x00000000, /* DENALI_PHY_583_DATA */
+ 0x00000000, /* DENALI_PHY_584_DATA */
+ 0x00000000, /* DENALI_PHY_585_DATA */
+ 0x00000000, /* DENALI_PHY_586_DATA */
+ 0x00000000, /* DENALI_PHY_587_DATA */
+ 0x00000000, /* DENALI_PHY_588_DATA */
+ 0x00000000, /* DENALI_PHY_589_DATA */
+ 0x00000000, /* DENALI_PHY_590_DATA */
+ 0x00000000, /* DENALI_PHY_591_DATA */
+ 0x00000000, /* DENALI_PHY_592_DATA */
+ 0x00000000, /* DENALI_PHY_593_DATA */
+ 0x00000000, /* DENALI_PHY_594_DATA */
+ 0x00000000, /* DENALI_PHY_595_DATA */
+ 0x00000000, /* DENALI_PHY_596_DATA */
+ 0x00000000, /* DENALI_PHY_597_DATA */
+ 0x00000000, /* DENALI_PHY_598_DATA */
+ 0x00000000, /* DENALI_PHY_599_DATA */
+ 0x00000000, /* DENALI_PHY_600_DATA */
+ 0x00000000, /* DENALI_PHY_601_DATA */
+ 0x00000000, /* DENALI_PHY_602_DATA */
+ 0x00000000, /* DENALI_PHY_603_DATA */
+ 0x00000000, /* DENALI_PHY_604_DATA */
+ 0x00000000, /* DENALI_PHY_605_DATA */
+ 0x00000000, /* DENALI_PHY_606_DATA */
+ 0x00000000, /* DENALI_PHY_607_DATA */
+ 0x00000000, /* DENALI_PHY_608_DATA */
+ 0x00000000, /* DENALI_PHY_609_DATA */
+ 0x00000000, /* DENALI_PHY_610_DATA */
+ 0x00000000, /* DENALI_PHY_611_DATA */
+ 0x00000000, /* DENALI_PHY_612_DATA */
+ 0x00000000, /* DENALI_PHY_613_DATA */
+ 0x00000000, /* DENALI_PHY_614_DATA */
+ 0x00000000, /* DENALI_PHY_615_DATA */
+ 0x00000000, /* DENALI_PHY_616_DATA */
+ 0x00000000, /* DENALI_PHY_617_DATA */
+ 0x00000000, /* DENALI_PHY_618_DATA */
+ 0x00000000, /* DENALI_PHY_619_DATA */
+ 0x00000000, /* DENALI_PHY_620_DATA */
+ 0x00000000, /* DENALI_PHY_621_DATA */
+ 0x00000000, /* DENALI_PHY_622_DATA */
+ 0x00000000, /* DENALI_PHY_623_DATA */
+ 0x00000000, /* DENALI_PHY_624_DATA */
+ 0x00000000, /* DENALI_PHY_625_DATA */
+ 0x00000000, /* DENALI_PHY_626_DATA */
+ 0x00000000, /* DENALI_PHY_627_DATA */
+ 0x00000000, /* DENALI_PHY_628_DATA */
+ 0x00000000, /* DENALI_PHY_629_DATA */
+ 0x00000000, /* DENALI_PHY_630_DATA */
+ 0x00000000, /* DENALI_PHY_631_DATA */
+ 0x00000000, /* DENALI_PHY_632_DATA */
+ 0x00000000, /* DENALI_PHY_633_DATA */
+ 0x00000000, /* DENALI_PHY_634_DATA */
+ 0x00000000, /* DENALI_PHY_635_DATA */
+ 0x00000000, /* DENALI_PHY_636_DATA */
+ 0x00000000, /* DENALI_PHY_637_DATA */
+ 0x00000000, /* DENALI_PHY_638_DATA */
+ 0x00000000, /* DENALI_PHY_639_DATA */
+ 0x00000000, /* DENALI_PHY_640_DATA */
+ 0x00000000, /* DENALI_PHY_641_DATA */
+ 0x00000000, /* DENALI_PHY_642_DATA */
+ 0x00000000, /* DENALI_PHY_643_DATA */
+ 0x00000000, /* DENALI_PHY_644_DATA */
+ 0x00000000, /* DENALI_PHY_645_DATA */
+ 0x00000000, /* DENALI_PHY_646_DATA */
+ 0x00000002, /* DENALI_PHY_647_DATA */
+ 0x00000000, /* DENALI_PHY_648_DATA */
+ 0x00000000, /* DENALI_PHY_649_DATA */
+ 0x00000000, /* DENALI_PHY_650_DATA */
+ 0x00400320, /* DENALI_PHY_651_DATA */
+ 0x00000040, /* DENALI_PHY_652_DATA */
+ 0x00000000, /* DENALI_PHY_653_DATA */
+ 0x00000000, /* DENALI_PHY_654_DATA */
+ 0x00000000, /* DENALI_PHY_655_DATA */
+ 0x01000000, /* DENALI_PHY_656_DATA */
+ 0x00020003, /* DENALI_PHY_657_DATA */
+ 0x00000000, /* DENALI_PHY_658_DATA */
+ 0x00000000, /* DENALI_PHY_659_DATA */
+ 0x00000000, /* DENALI_PHY_660_DATA */
+ 0x0000002a, /* DENALI_PHY_661_DATA */
+ 0x00000015, /* DENALI_PHY_662_DATA */
+ 0x00000015, /* DENALI_PHY_663_DATA */
+ 0x0000002a, /* DENALI_PHY_664_DATA */
+ 0x00000033, /* DENALI_PHY_665_DATA */
+ 0x0000000c, /* DENALI_PHY_666_DATA */
+ 0x0000000c, /* DENALI_PHY_667_DATA */
+ 0x00000033, /* DENALI_PHY_668_DATA */
+ 0x00000000, /* DENALI_PHY_669_DATA */
+ 0x00000000, /* DENALI_PHY_670_DATA */
+ 0x00000000, /* DENALI_PHY_671_DATA */
+ 0x00030055, /* DENALI_PHY_672_DATA */
+ 0x03000300, /* DENALI_PHY_673_DATA */
+ 0x03000300, /* DENALI_PHY_674_DATA */
+ 0x00000300, /* DENALI_PHY_675_DATA */
+ 0x42080010, /* DENALI_PHY_676_DATA */
+ 0x00000003, /* DENALI_PHY_677_DATA */
+ 0x00000000, /* DENALI_PHY_678_DATA */
+ 0x00000000, /* DENALI_PHY_679_DATA */
+ 0x00000000, /* DENALI_PHY_680_DATA */
+ 0x00000000, /* DENALI_PHY_681_DATA */
+ 0x00000000, /* DENALI_PHY_682_DATA */
+ 0x00000000, /* DENALI_PHY_683_DATA */
+ 0x00000000, /* DENALI_PHY_684_DATA */
+ 0x00000000, /* DENALI_PHY_685_DATA */
+ 0x00000000, /* DENALI_PHY_686_DATA */
+ 0x00000000, /* DENALI_PHY_687_DATA */
+ 0x00000000, /* DENALI_PHY_688_DATA */
+ 0x00000000, /* DENALI_PHY_689_DATA */
+ 0x00000000, /* DENALI_PHY_690_DATA */
+ 0x00000000, /* DENALI_PHY_691_DATA */
+ 0x00000000, /* DENALI_PHY_692_DATA */
+ 0x00000000, /* DENALI_PHY_693_DATA */
+ 0x00000000, /* DENALI_PHY_694_DATA */
+ 0x00000000, /* DENALI_PHY_695_DATA */
+ 0x00000000, /* DENALI_PHY_696_DATA */
+ 0x00000000, /* DENALI_PHY_697_DATA */
+ 0x00000000, /* DENALI_PHY_698_DATA */
+ 0x00000000, /* DENALI_PHY_699_DATA */
+ 0x00000000, /* DENALI_PHY_700_DATA */
+ 0x00000000, /* DENALI_PHY_701_DATA */
+ 0x00000000, /* DENALI_PHY_702_DATA */
+ 0x00000000, /* DENALI_PHY_703_DATA */
+ 0x00000000, /* DENALI_PHY_704_DATA */
+ 0x00000000, /* DENALI_PHY_705_DATA */
+ 0x00000000, /* DENALI_PHY_706_DATA */
+ 0x00000000, /* DENALI_PHY_707_DATA */
+ 0x00000000, /* DENALI_PHY_708_DATA */
+ 0x00000000, /* DENALI_PHY_709_DATA */
+ 0x00000000, /* DENALI_PHY_710_DATA */
+ 0x00000000, /* DENALI_PHY_711_DATA */
+ 0x00000000, /* DENALI_PHY_712_DATA */
+ 0x00000000, /* DENALI_PHY_713_DATA */
+ 0x00000000, /* DENALI_PHY_714_DATA */
+ 0x00000000, /* DENALI_PHY_715_DATA */
+ 0x00000000, /* DENALI_PHY_716_DATA */
+ 0x00000000, /* DENALI_PHY_717_DATA */
+ 0x00000000, /* DENALI_PHY_718_DATA */
+ 0x00000000, /* DENALI_PHY_719_DATA */
+ 0x00000000, /* DENALI_PHY_720_DATA */
+ 0x00000000, /* DENALI_PHY_721_DATA */
+ 0x00000000, /* DENALI_PHY_722_DATA */
+ 0x00000000, /* DENALI_PHY_723_DATA */
+ 0x00000000, /* DENALI_PHY_724_DATA */
+ 0x00000000, /* DENALI_PHY_725_DATA */
+ 0x00000000, /* DENALI_PHY_726_DATA */
+ 0x00000000, /* DENALI_PHY_727_DATA */
+ 0x00000000, /* DENALI_PHY_728_DATA */
+ 0x00000000, /* DENALI_PHY_729_DATA */
+ 0x00000000, /* DENALI_PHY_730_DATA */
+ 0x00000000, /* DENALI_PHY_731_DATA */
+ 0x00000000, /* DENALI_PHY_732_DATA */
+ 0x00000000, /* DENALI_PHY_733_DATA */
+ 0x00000000, /* DENALI_PHY_734_DATA */
+ 0x00000000, /* DENALI_PHY_735_DATA */
+ 0x00000000, /* DENALI_PHY_736_DATA */
+ 0x00000000, /* DENALI_PHY_737_DATA */
+ 0x00000000, /* DENALI_PHY_738_DATA */
+ 0x00000000, /* DENALI_PHY_739_DATA */
+ 0x00000000, /* DENALI_PHY_740_DATA */
+ 0x00000000, /* DENALI_PHY_741_DATA */
+ 0x00000000, /* DENALI_PHY_742_DATA */
+ 0x00000000, /* DENALI_PHY_743_DATA */
+ 0x00000000, /* DENALI_PHY_744_DATA */
+ 0x00000000, /* DENALI_PHY_745_DATA */
+ 0x00000000, /* DENALI_PHY_746_DATA */
+ 0x00000000, /* DENALI_PHY_747_DATA */
+ 0x00000000, /* DENALI_PHY_748_DATA */
+ 0x00000000, /* DENALI_PHY_749_DATA */
+ 0x00000000, /* DENALI_PHY_750_DATA */
+ 0x00000000, /* DENALI_PHY_751_DATA */
+ 0x00000000, /* DENALI_PHY_752_DATA */
+ 0x00000000, /* DENALI_PHY_753_DATA */
+ 0x00000000, /* DENALI_PHY_754_DATA */
+ 0x00000000, /* DENALI_PHY_755_DATA */
+ 0x00000000, /* DENALI_PHY_756_DATA */
+ 0x00000000, /* DENALI_PHY_757_DATA */
+ 0x00000000, /* DENALI_PHY_758_DATA */
+ 0x00000000, /* DENALI_PHY_759_DATA */
+ 0x00000000, /* DENALI_PHY_760_DATA */
+ 0x00000000, /* DENALI_PHY_761_DATA */
+ 0x00000000, /* DENALI_PHY_762_DATA */
+ 0x00000000, /* DENALI_PHY_763_DATA */
+ 0x00000000, /* DENALI_PHY_764_DATA */
+ 0x00000000, /* DENALI_PHY_765_DATA */
+ 0x00000000, /* DENALI_PHY_766_DATA */
+ 0x00000000, /* DENALI_PHY_767_DATA */
+ 0x00000000, /* DENALI_PHY_768_DATA */
+ 0x00000000, /* DENALI_PHY_769_DATA */
+ 0x00000000, /* DENALI_PHY_770_DATA */
+ 0x00000000, /* DENALI_PHY_771_DATA */
+ 0x00000000, /* DENALI_PHY_772_DATA */
+ 0x00000000, /* DENALI_PHY_773_DATA */
+ 0x00000000, /* DENALI_PHY_774_DATA */
+ 0x00000002, /* DENALI_PHY_775_DATA */
+ 0x00000000, /* DENALI_PHY_776_DATA */
+ 0x00000000, /* DENALI_PHY_777_DATA */
+ 0x00000000, /* DENALI_PHY_778_DATA */
+ 0x00400320, /* DENALI_PHY_779_DATA */
+ 0x00000040, /* DENALI_PHY_780_DATA */
+ 0x00000000, /* DENALI_PHY_781_DATA */
+ 0x00000000, /* DENALI_PHY_782_DATA */
+ 0x00000000, /* DENALI_PHY_783_DATA */
+ 0x01000000, /* DENALI_PHY_784_DATA */
+ 0x00020003, /* DENALI_PHY_785_DATA */
+ 0x00000000, /* DENALI_PHY_786_DATA */
+ 0x00000000, /* DENALI_PHY_787_DATA */
+ 0x00000000, /* DENALI_PHY_788_DATA */
+ 0x0000002a, /* DENALI_PHY_789_DATA */
+ 0x00000015, /* DENALI_PHY_790_DATA */
+ 0x00000015, /* DENALI_PHY_791_DATA */
+ 0x0000002a, /* DENALI_PHY_792_DATA */
+ 0x00000033, /* DENALI_PHY_793_DATA */
+ 0x0000000c, /* DENALI_PHY_794_DATA */
+ 0x0000000c, /* DENALI_PHY_795_DATA */
+ 0x00000033, /* DENALI_PHY_796_DATA */
+ 0x1ee6b16a, /* DENALI_PHY_797_DATA */
+ 0x10000000, /* DENALI_PHY_798_DATA */
+ 0x00000000, /* DENALI_PHY_799_DATA */
+ 0x00030055, /* DENALI_PHY_800_DATA */
+ 0x03000300, /* DENALI_PHY_801_DATA */
+ 0x03000300, /* DENALI_PHY_802_DATA */
+ 0x00000300, /* DENALI_PHY_803_DATA */
+ 0x42080010, /* DENALI_PHY_804_DATA */
+ 0x00000003, /* DENALI_PHY_805_DATA */
+ 0x00000000, /* DENALI_PHY_806_DATA */
+ 0x00000000, /* DENALI_PHY_807_DATA */
+ 0x00000000, /* DENALI_PHY_808_DATA */
+ 0x00000000, /* DENALI_PHY_809_DATA */
+ 0x00000000, /* DENALI_PHY_810_DATA */
+ 0x00000000, /* DENALI_PHY_811_DATA */
+ 0x00000000, /* DENALI_PHY_812_DATA */
+ 0x00000000, /* DENALI_PHY_813_DATA */
+ 0x00000000, /* DENALI_PHY_814_DATA */
+ 0x00000000, /* DENALI_PHY_815_DATA */
+ 0x00000000, /* DENALI_PHY_816_DATA */
+ 0x00000000, /* DENALI_PHY_817_DATA */
+ 0x00000000, /* DENALI_PHY_818_DATA */
+ 0x00000000, /* DENALI_PHY_819_DATA */
+ 0x00000000, /* DENALI_PHY_820_DATA */
+ 0x00000000, /* DENALI_PHY_821_DATA */
+ 0x00000000, /* DENALI_PHY_822_DATA */
+ 0x00000000, /* DENALI_PHY_823_DATA */
+ 0x00000000, /* DENALI_PHY_824_DATA */
+ 0x00000000, /* DENALI_PHY_825_DATA */
+ 0x00000000, /* DENALI_PHY_826_DATA */
+ 0x00000000, /* DENALI_PHY_827_DATA */
+ 0x00000000, /* DENALI_PHY_828_DATA */
+ 0x00000000, /* DENALI_PHY_829_DATA */
+ 0x00000000, /* DENALI_PHY_830_DATA */
+ 0x00000000, /* DENALI_PHY_831_DATA */
+ 0x00000000, /* DENALI_PHY_832_DATA */
+ 0x00000000, /* DENALI_PHY_833_DATA */
+ 0x00000000, /* DENALI_PHY_834_DATA */
+ 0x00000000, /* DENALI_PHY_835_DATA */
+ 0x00000000, /* DENALI_PHY_836_DATA */
+ 0x00000000, /* DENALI_PHY_837_DATA */
+ 0x00000000, /* DENALI_PHY_838_DATA */
+ 0x00000000, /* DENALI_PHY_839_DATA */
+ 0x00000000, /* DENALI_PHY_840_DATA */
+ 0x00000000, /* DENALI_PHY_841_DATA */
+ 0x00000000, /* DENALI_PHY_842_DATA */
+ 0x00000000, /* DENALI_PHY_843_DATA */
+ 0x00000000, /* DENALI_PHY_844_DATA */
+ 0x00000000, /* DENALI_PHY_845_DATA */
+ 0x00000000, /* DENALI_PHY_846_DATA */
+ 0x00000000, /* DENALI_PHY_847_DATA */
+ 0x00000000, /* DENALI_PHY_848_DATA */
+ 0x00000000, /* DENALI_PHY_849_DATA */
+ 0x00000000, /* DENALI_PHY_850_DATA */
+ 0x00000000, /* DENALI_PHY_851_DATA */
+ 0x00000000, /* DENALI_PHY_852_DATA */
+ 0x00000000, /* DENALI_PHY_853_DATA */
+ 0x00000000, /* DENALI_PHY_854_DATA */
+ 0x00000000, /* DENALI_PHY_855_DATA */
+ 0x00000000, /* DENALI_PHY_856_DATA */
+ 0x00000000, /* DENALI_PHY_857_DATA */
+ 0x00000000, /* DENALI_PHY_858_DATA */
+ 0x00000000, /* DENALI_PHY_859_DATA */
+ 0x00000000, /* DENALI_PHY_860_DATA */
+ 0x00000000, /* DENALI_PHY_861_DATA */
+ 0x00000000, /* DENALI_PHY_862_DATA */
+ 0x00000000, /* DENALI_PHY_863_DATA */
+ 0x00000000, /* DENALI_PHY_864_DATA */
+ 0x00000000, /* DENALI_PHY_865_DATA */
+ 0x00000000, /* DENALI_PHY_866_DATA */
+ 0x00000000, /* DENALI_PHY_867_DATA */
+ 0x00000000, /* DENALI_PHY_868_DATA */
+ 0x00000000, /* DENALI_PHY_869_DATA */
+ 0x00000000, /* DENALI_PHY_870_DATA */
+ 0x00000000, /* DENALI_PHY_871_DATA */
+ 0x00000000, /* DENALI_PHY_872_DATA */
+ 0x00000000, /* DENALI_PHY_873_DATA */
+ 0x00000000, /* DENALI_PHY_874_DATA */
+ 0x00000000, /* DENALI_PHY_875_DATA */
+ 0x00000000, /* DENALI_PHY_876_DATA */
+ 0x00000000, /* DENALI_PHY_877_DATA */
+ 0x00000000, /* DENALI_PHY_878_DATA */
+ 0x00000000, /* DENALI_PHY_879_DATA */
+ 0x00000000, /* DENALI_PHY_880_DATA */
+ 0x00000000, /* DENALI_PHY_881_DATA */
+ 0x00000000, /* DENALI_PHY_882_DATA */
+ 0x00000000, /* DENALI_PHY_883_DATA */
+ 0x00000000, /* DENALI_PHY_884_DATA */
+ 0x00000000, /* DENALI_PHY_885_DATA */
+ 0x00000000, /* DENALI_PHY_886_DATA */
+ 0x00000000, /* DENALI_PHY_887_DATA */
+ 0x00000000, /* DENALI_PHY_888_DATA */
+ 0x00000000, /* DENALI_PHY_889_DATA */
+ 0x00000000, /* DENALI_PHY_890_DATA */
+ 0x00000000, /* DENALI_PHY_891_DATA */
+ 0x00000000, /* DENALI_PHY_892_DATA */
+ 0x00000000, /* DENALI_PHY_893_DATA */
+ 0x00000000, /* DENALI_PHY_894_DATA */
+ 0x00000000, /* DENALI_PHY_895_DATA */
+ 0x00000000, /* DENALI_PHY_896_DATA */
+ 0x00000000, /* DENALI_PHY_897_DATA */
+ 0x00000005, /* DENALI_PHY_898_DATA */
+ 0x04000f01, /* DENALI_PHY_899_DATA */
+ 0x00020040, /* DENALI_PHY_900_DATA */
+ 0x00020055, /* DENALI_PHY_901_DATA */
+ 0x00000000, /* DENALI_PHY_902_DATA */
+ 0x00000000, /* DENALI_PHY_903_DATA */
+ 0x00000000, /* DENALI_PHY_904_DATA */
+ 0x00000050, /* DENALI_PHY_905_DATA */
+ 0x00000000, /* DENALI_PHY_906_DATA */
+ 0x01010100, /* DENALI_PHY_907_DATA */
+ 0x00000600, /* DENALI_PHY_908_DATA */
+ 0x00000000, /* DENALI_PHY_909_DATA */
+ 0x00006400, /* DENALI_PHY_910_DATA */
+ 0x01221102, /* DENALI_PHY_911_DATA */
+ 0x00000000, /* DENALI_PHY_912_DATA */
+ 0x000d1f00, /* DENALI_PHY_913_DATA */
+ 0x0d1f0d1f, /* DENALI_PHY_914_DATA */
+ 0x0d1f0d1f, /* DENALI_PHY_915_DATA */
+ 0x00030003, /* DENALI_PHY_916_DATA */
+ 0x03000300, /* DENALI_PHY_917_DATA */
+ 0x00000300, /* DENALI_PHY_918_DATA */
+ 0x01221102, /* DENALI_PHY_919_DATA */
+ 0x00000000, /* DENALI_PHY_920_DATA */
+ 0x00000000, /* DENALI_PHY_921_DATA */
+ 0x03020000, /* DENALI_PHY_922_DATA */
+ 0x00000001, /* DENALI_PHY_923_DATA */
+ 0x00000411, /* DENALI_PHY_924_DATA */
+ 0x00000411, /* DENALI_PHY_925_DATA */
+ 0x00000040, /* DENALI_PHY_926_DATA */
+ 0x00000040, /* DENALI_PHY_927_DATA */
+ 0x00000411, /* DENALI_PHY_928_DATA */
+ 0x00000411, /* DENALI_PHY_929_DATA */
+ 0x00004410, /* DENALI_PHY_930_DATA */
+ 0x00004410, /* DENALI_PHY_931_DATA */
+ 0x00004410, /* DENALI_PHY_932_DATA */
+ 0x00004410, /* DENALI_PHY_933_DATA */
+ 0x00004410, /* DENALI_PHY_934_DATA */
+ 0x00000411, /* DENALI_PHY_935_DATA */
+ 0x00004410, /* DENALI_PHY_936_DATA */
+ 0x00000411, /* DENALI_PHY_937_DATA */
+ 0x00004410, /* DENALI_PHY_938_DATA */
+ 0x00000411, /* DENALI_PHY_939_DATA */
+ 0x00004410, /* DENALI_PHY_940_DATA */
+ 0x00000000, /* DENALI_PHY_941_DATA */
+ 0x00000000, /* DENALI_PHY_942_DATA */
+ 0x00000000, /* DENALI_PHY_943_DATA */
+ 0x64000000, /* DENALI_PHY_944_DATA */
+ 0x00000000, /* DENALI_PHY_945_DATA */
+ 0x00000000, /* DENALI_PHY_946_DATA */
+ 0x00000508, /* DENALI_PHY_947_DATA */
+ 0x00000000, /* DENALI_PHY_948_DATA */
+ 0x00000000, /* DENALI_PHY_949_DATA */
+ 0x00000000, /* DENALI_PHY_950_DATA */
+ 0x00000000, /* DENALI_PHY_951_DATA */
+ 0x00000000, /* DENALI_PHY_952_DATA */
+ 0x00000000, /* DENALI_PHY_953_DATA */
+ 0xe4000000, /* DENALI_PHY_954_DATA */
+ 0x00000000, /* DENALI_PHY_955_DATA */
+ 0x00000000, /* DENALI_PHY_956_DATA */
+ 0x01010000, /* DENALI_PHY_957_DATA */
+ 0x00000000 /* DENALI_PHY_958_DATA */
+ }
+ },
+},
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 84/92] ram: rk3399: Add lpddr4 set rate support
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:51 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Unlike rest of dram type chips, LPDDR4 initialization start
with at board selected frequency (say 50MHz) and then it
switches into 400MHz and 800MHz simultaneously to make the
proper sequence work on each channel with associated training.
Here is sameple log about LPDDR4-100 init sequence in Rockpro64:
Channel 0: LPDDR4, 50MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
Channel 1: LPDDR4, 50MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
256B stride
channel 0 training pass
channel 1 training pass
change freq to 400 MHz 0, 1
channel 0 training pass
channel 1 training pass
change freq to 800 MHz 1, 0
This patch add support to this init sequence via lpddr4 set rate
by taking sdram timing parameters from 400, 800 .inc files.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 402 +++++++++++++++++++++++++++-
1 file changed, 393 insertions(+), 9 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 5a0872c23f..170743b88c 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -16,6 +16,7 @@
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru_rk3399.h>
#include <asm/arch-rockchip/grf_rk3399.h>
+#include <asm/arch-rockchip/pmu_rk3399.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/sdram_common.h>
#include <asm/arch-rockchip/sdram_rk3399.h>
@@ -62,6 +63,7 @@ struct dram_info {
struct clk ddr_clk;
struct rk3399_cru *cru;
struct rk3399_grf_regs *grf;
+ struct rk3399_pmu_regs *pmu;
struct rk3399_pmucru *pmucru;
struct rk3399_pmusgrf_regs *pmusgrf;
struct rk3399_ddr_cic_regs *cic;
@@ -186,6 +188,11 @@ struct io_setting {
},
};
+struct rk3399_sdram_params lpddr4_timings[] = {
+ #include "sdram-rk3399-lpddr4-400.inc"
+ #include "sdram-rk3399-lpddr4-800.inc"
+};
+
/**
* phy = 0, PHY boot freq
* phy = 1, PHY index 0
@@ -213,11 +220,30 @@ lpddr4_get_io_settings(const struct rk3399_sdram_params *params, u32 mr5)
return io;
}
+static void *get_denali_phy(const struct chan_info *chan,
+ struct rk3399_sdram_params *params, bool reg)
+{
+ return reg ? &chan->publ->denali_phy : ¶ms->phy_regs.denali_phy;
+}
+
+static void *get_denali_ctl(const struct chan_info *chan,
+ struct rk3399_sdram_params *params, bool reg)
+{
+ return reg ? &chan->pctl->denali_ctl : ¶ms->pctl_regs.denali_ctl;
+}
+
static void *get_ddrc0_con(struct dram_info *dram, u8 channel)
{
return (channel == 0) ? &dram->grf->ddrc0_con0 : &dram->grf->ddrc0_con1;
}
+static u32 lpddr4_get_phy(struct rk3399_sdram_params *params, u32 ctl)
+{
+ u32 lpddr4_phy[] = {1, 0, 0xb};
+
+ return lpddr4_phy[ctl];
+}
+
static u32 get_ddr_stride(struct rk3399_pmusgrf_regs *pmusgrf)
{
return ((readl(&pmusgrf->soc_con4) >> 10) & 0x1F);
@@ -579,10 +605,11 @@ static int phy_io_config(const struct chan_info *chan,
}
static void set_ds_odt(const struct chan_info *chan,
- const struct rk3399_sdram_params *sdram_params, u32 mr5)
+ struct rk3399_sdram_params *sdram_params,
+ bool ctl_phy_reg, u32 mr5)
{
- u32 *denali_phy = chan->publ->denali_phy;
- u32 *denali_ctl = chan->pctl->denali_ctl;
+ u32 *denali_phy = get_denali_phy(chan, sdram_params, ctl_phy_reg);
+ u32 *denali_ctl = get_denali_ctl(chan, sdram_params, ctl_phy_reg);
u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
u32 tsel_idle_select_p, tsel_rd_select_p;
u32 tsel_idle_select_n, tsel_rd_select_n;
@@ -740,7 +767,8 @@ static void set_ds_odt(const struct chan_info *chan,
clrsetbits_le32(&denali_phy[928], 0xff, reg_value);
/* phy_pad_rst_drive 8bits DENALI_PHY_937 offset_0 */
- clrsetbits_le32(&denali_phy[937], 0xff, reg_value);
+ if (!ctl_phy_reg)
+ clrsetbits_le32(&denali_phy[937], 0xff, reg_value);
/* phy_pad_cke_drive 8bits DENALI_PHY_935 offset_0 */
clrsetbits_le32(&denali_phy[935], 0xff, reg_value);
@@ -930,7 +958,7 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
copy_to_reg(&denali_phy[512], ¶ms_phy[512], (549 - 512 + 1) * 4);
copy_to_reg(&denali_phy[640], ¶ms_phy[640], (677 - 640 + 1) * 4);
copy_to_reg(&denali_phy[768], ¶ms_phy[768], (805 - 768 + 1) * 4);
- set_ds_odt(chan, sdram_params, 0);
+ set_ds_odt(chan, sdram_params, true, 0);
/*
* phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_84/212/340/468 offset_8
@@ -1317,7 +1345,7 @@ static int data_training(const struct chan_info *chan, u32 channel,
if (training_flag == PI_FULL_TRAINING) {
if (sdram_params->base.dramtype == LPDDR4) {
- training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING |
+ training_flag = PI_WRITE_LEVELING |
PI_READ_GATE_TRAINING |
PI_READ_LEVELING | PI_WDQ_LEVELING;
} else if (sdram_params->base.dramtype == LPDDR3) {
@@ -1812,6 +1840,357 @@ end:
return ret;
}
+static void lpddr4_copy_phy(struct dram_info *dram,
+ struct rk3399_sdram_params *params, u32 phy,
+ struct rk3399_sdram_params *timings,
+ u32 channel)
+{
+ u32 *denali_phy;
+ u32 *denali_phy_params;
+ u32 speed = 0;
+ u32 mr5;
+
+ denali_phy = dram->chan[channel].publ->denali_phy;
+ denali_phy_params = timings->phy_regs.denali_phy;
+
+ /* switch index */
+ clrsetbits_le32(&denali_phy_params[896], 0x3 << 8, phy << 8);
+ writel(denali_phy_params[896], &denali_phy[896]);
+
+ /* phy_pll_ctrl_ca, phy_pll_ctrl */
+ writel(denali_phy_params[911], &denali_phy[911]);
+
+ /* phy_low_freq_sel */
+ clrsetbits_le32(&denali_phy[913], 0x1,
+ denali_phy_params[913] & 0x1);
+
+ /* PHY_GRP_SLAVE_DELAY_X, phy_cslvl_dly_step */
+ writel(denali_phy_params[916], &denali_phy[916]);
+ writel(denali_phy_params[917], &denali_phy[917]);
+ writel(denali_phy_params[918], &denali_phy[918]);
+
+ /* phy_adrZ_sw_wraddr_shift_X */
+ writel(denali_phy_params[512], &denali_phy[512]);
+ clrsetbits_le32(&denali_phy[513], 0xFFFF,
+ denali_phy_params[513] & 0xFFFF);
+ writel(denali_phy_params[640], &denali_phy[640]);
+ clrsetbits_le32(&denali_phy[641], 0xFFFF,
+ denali_phy_params[641] & 0xFFFF);
+ writel(denali_phy_params[768], &denali_phy[768]);
+ clrsetbits_le32(&denali_phy[769], 0xFFFF,
+ denali_phy_params[769] & 0xFFFF);
+
+ writel(denali_phy_params[544], &denali_phy[544]);
+ writel(denali_phy_params[545], &denali_phy[545]);
+ writel(denali_phy_params[546], &denali_phy[546]);
+ writel(denali_phy_params[547], &denali_phy[547]);
+
+ writel(denali_phy_params[672], &denali_phy[672]);
+ writel(denali_phy_params[673], &denali_phy[673]);
+ writel(denali_phy_params[674], &denali_phy[674]);
+ writel(denali_phy_params[675], &denali_phy[675]);
+
+ writel(denali_phy_params[800], &denali_phy[800]);
+ writel(denali_phy_params[801], &denali_phy[801]);
+ writel(denali_phy_params[802], &denali_phy[802]);
+ writel(denali_phy_params[803], &denali_phy[803]);
+
+ /*
+ * phy_adr_master_delay_start_X
+ * phy_adr_master_delay_step_X
+ * phy_adr_master_delay_wait_X
+ */
+ writel(denali_phy_params[548], &denali_phy[548]);
+ writel(denali_phy_params[676], &denali_phy[676]);
+ writel(denali_phy_params[804], &denali_phy[804]);
+
+ /* phy_adr_calvl_dly_step_X */
+ writel(denali_phy_params[549], &denali_phy[549]);
+ writel(denali_phy_params[677], &denali_phy[677]);
+ writel(denali_phy_params[805], &denali_phy[805]);
+
+ /*
+ * phy_clk_wrdm_slave_delay_X
+ * phy_clk_wrdqZ_slave_delay_X
+ * phy_clk_wrdqs_slave_delay_X
+ */
+ copy_to_reg((u32 *)&denali_phy[59], (u32 *)&denali_phy_params[59],
+ (63 - 58) * 4);
+ copy_to_reg((u32 *)&denali_phy[187], (u32 *)&denali_phy_params[187],
+ (191 - 186) * 4);
+ copy_to_reg((u32 *)&denali_phy[315], (u32 *)&denali_phy_params[315],
+ (319 - 314) * 4);
+ copy_to_reg((u32 *)&denali_phy[443], (u32 *)&denali_phy_params[443],
+ (447 - 442) * 4);
+
+ /*
+ * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_84/212/340/468 offset_8
+ * dqs_tsel_wr_end[7:4] add Half cycle
+ * phy_dq_tsel_wr_timing_X 8bits DENALI_PHY_83/211/339/467 offset_8
+ * dq_tsel_wr_end[7:4] add Half cycle
+ */
+ writel(denali_phy_params[83] + (0x10 << 16), &denali_phy[83]);
+ writel(denali_phy_params[84] + (0x10 << 8), &denali_phy[84]);
+ writel(denali_phy_params[85], &denali_phy[85]);
+
+ writel(denali_phy_params[211] + (0x10 << 16), &denali_phy[211]);
+ writel(denali_phy_params[212] + (0x10 << 8), &denali_phy[212]);
+ writel(denali_phy_params[213], &denali_phy[213]);
+
+ writel(denali_phy_params[339] + (0x10 << 16), &denali_phy[339]);
+ writel(denali_phy_params[340] + (0x10 << 8), &denali_phy[340]);
+ writel(denali_phy_params[341], &denali_phy[341]);
+
+ writel(denali_phy_params[467] + (0x10 << 16), &denali_phy[467]);
+ writel(denali_phy_params[468] + (0x10 << 8), &denali_phy[468]);
+ writel(denali_phy_params[469], &denali_phy[469]);
+
+ /*
+ * phy_gtlvl_resp_wait_cnt_X
+ * phy_gtlvl_dly_step_X
+ * phy_wrlvl_resp_wait_cnt_X
+ * phy_gtlvl_final_step_X
+ * phy_gtlvl_back_step_X
+ * phy_rdlvl_dly_step_X
+ *
+ * phy_master_delay_step_X
+ * phy_master_delay_wait_X
+ * phy_wrlvl_dly_step_X
+ * phy_rptr_update_X
+ * phy_wdqlvl_dly_step_X
+ */
+ writel(denali_phy_params[87], &denali_phy[87]);
+ writel(denali_phy_params[88], &denali_phy[88]);
+ writel(denali_phy_params[89], &denali_phy[89]);
+ writel(denali_phy_params[90], &denali_phy[90]);
+
+ writel(denali_phy_params[215], &denali_phy[215]);
+ writel(denali_phy_params[216], &denali_phy[216]);
+ writel(denali_phy_params[217], &denali_phy[217]);
+ writel(denali_phy_params[218], &denali_phy[218]);
+
+ writel(denali_phy_params[343], &denali_phy[343]);
+ writel(denali_phy_params[344], &denali_phy[344]);
+ writel(denali_phy_params[345], &denali_phy[345]);
+ writel(denali_phy_params[346], &denali_phy[346]);
+
+ writel(denali_phy_params[471], &denali_phy[471]);
+ writel(denali_phy_params[472], &denali_phy[472]);
+ writel(denali_phy_params[473], &denali_phy[473]);
+ writel(denali_phy_params[474], &denali_phy[474]);
+
+ /*
+ * phy_gtlvl_lat_adj_start_X
+ * phy_gtlvl_rddqs_slv_dly_start_X
+ * phy_rdlvl_rddqs_dq_slv_dly_start_X
+ * phy_wdqlvl_dqdm_slv_dly_start_X
+ */
+ writel(denali_phy_params[80], &denali_phy[80]);
+ writel(denali_phy_params[81], &denali_phy[81]);
+
+ writel(denali_phy_params[208], &denali_phy[208]);
+ writel(denali_phy_params[209], &denali_phy[209]);
+
+ writel(denali_phy_params[336], &denali_phy[336]);
+ writel(denali_phy_params[337], &denali_phy[337]);
+
+ writel(denali_phy_params[464], &denali_phy[464]);
+ writel(denali_phy_params[465], &denali_phy[465]);
+
+ /*
+ * phy_master_delay_start_X
+ * phy_sw_master_mode_X
+ * phy_rddata_en_tsel_dly_X
+ */
+ writel(denali_phy_params[86], &denali_phy[86]);
+ writel(denali_phy_params[214], &denali_phy[214]);
+ writel(denali_phy_params[342], &denali_phy[342]);
+ writel(denali_phy_params[470], &denali_phy[470]);
+
+ /*
+ * phy_rddqZ_slave_delay_X
+ * phy_rddqs_dqZ_fall_slave_delay_X
+ * phy_rddqs_dqZ_rise_slave_delay_X
+ * phy_rddqs_dm_fall_slave_delay_X
+ * phy_rddqs_dm_rise_slave_delay_X
+ * phy_rddqs_gate_slave_delay_X
+ * phy_wrlvl_delay_early_threshold_X
+ * phy_write_path_lat_add_X
+ * phy_rddqs_latency_adjust_X
+ * phy_wrlvl_delay_period_threshold_X
+ * phy_wrlvl_early_force_zero_X
+ */
+ copy_to_reg((u32 *)&denali_phy[64], (u32 *)&denali_phy_params[64],
+ (67 - 63) * 4);
+ clrsetbits_le32(&denali_phy[68], 0xFFFFFC00,
+ denali_phy_params[68] & 0xFFFFFC00);
+ copy_to_reg((u32 *)&denali_phy[69], (u32 *)&denali_phy_params[69],
+ (79 - 68) * 4);
+ copy_to_reg((u32 *)&denali_phy[192], (u32 *)&denali_phy_params[192],
+ (195 - 191) * 4);
+ clrsetbits_le32(&denali_phy[196], 0xFFFFFC00,
+ denali_phy_params[196] & 0xFFFFFC00);
+ copy_to_reg((u32 *)&denali_phy[197], (u32 *)&denali_phy_params[197],
+ (207 - 196) * 4);
+ copy_to_reg((u32 *)&denali_phy[320], (u32 *)&denali_phy_params[320],
+ (323 - 319) * 4);
+ clrsetbits_le32(&denali_phy[324], 0xFFFFFC00,
+ denali_phy_params[324] & 0xFFFFFC00);
+ copy_to_reg((u32 *)&denali_phy[325], (u32 *)&denali_phy_params[325],
+ (335 - 324) * 4);
+
+ copy_to_reg((u32 *)&denali_phy[448], (u32 *)&denali_phy_params[448],
+ (451 - 447) * 4);
+ clrsetbits_le32(&denali_phy[452], 0xFFFFFC00,
+ denali_phy_params[452] & 0xFFFFFC00);
+ copy_to_reg((u32 *)&denali_phy[453], (u32 *)&denali_phy_params[453],
+ (463 - 452) * 4);
+
+ /* phy_two_cyc_preamble_X */
+ clrsetbits_le32(&denali_phy[7], 0x3 << 24,
+ denali_phy_params[7] & (0x3 << 24));
+ clrsetbits_le32(&denali_phy[135], 0x3 << 24,
+ denali_phy_params[135] & (0x3 << 24));
+ clrsetbits_le32(&denali_phy[263], 0x3 << 24,
+ denali_phy_params[263] & (0x3 << 24));
+ clrsetbits_le32(&denali_phy[391], 0x3 << 24,
+ denali_phy_params[391] & (0x3 << 24));
+
+ /* speed */
+ if (timings->base.ddr_freq < 400 * MHz)
+ speed = 0x0;
+ else if (timings->base.ddr_freq < 800 * MHz)
+ speed = 0x1;
+ else if (timings->base.ddr_freq < 1200 * MHz)
+ speed = 0x2;
+
+ /* PHY_924 PHY_PAD_FDBK_DRIVE */
+ clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21);
+ /* PHY_926 PHY_PAD_DATA_DRIVE */
+ clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9);
+ /* PHY_927 PHY_PAD_DQS_DRIVE */
+ clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9);
+ /* PHY_928 PHY_PAD_ADDR_DRIVE */
+ clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17);
+ /* PHY_929 PHY_PAD_CLK_DRIVE */
+ clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17);
+ /* PHY_935 PHY_PAD_CKE_DRIVE */
+ clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17);
+ /* PHY_937 PHY_PAD_RST_DRIVE */
+ clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17);
+ /* PHY_939 PHY_PAD_CS_DRIVE */
+ clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17);
+
+ read_mr(dram->chan[channel].pctl, 1, 5, &mr5);
+ set_ds_odt(&dram->chan[channel], timings, true, mr5);
+
+ /*
+ * if phy_sw_master_mode_X not bypass mode,
+ * clear PHY_SLICE_PWR_RDC_DISABLE.
+ * NOTE: need use timings, not ddr_publ_regs
+ */
+ if (!((denali_phy_params[86] >> 8) & (1 << 2))) {
+ clrbits_le32(&denali_phy[10], 1 << 16);
+ clrbits_le32(&denali_phy[138], 1 << 16);
+ clrbits_le32(&denali_phy[266], 1 << 16);
+ clrbits_le32(&denali_phy[394], 1 << 16);
+ }
+}
+
+static void lpddr4_set_phy(struct dram_info *dram,
+ struct rk3399_sdram_params *params, u32 phy,
+ struct rk3399_sdram_params *timings)
+{
+ u32 channel;
+
+ for (channel = 0; channel < 2; channel++)
+ lpddr4_copy_phy(dram, params, phy, timings, channel);
+}
+
+static int lpddr4_set_ctl(struct dram_info *dram,
+ struct rk3399_sdram_params *params, u32 ctl, u32 hz)
+{
+ u32 channel;
+ int ret_clk, ret[2];
+
+ /* cci idle req stall */
+ writel(0x70007, &dram->grf->soc_con0);
+
+ /* enable all clk */
+ setbits_le32(&dram->pmu->pmu_noc_auto_ena, (0x3 << 7));
+
+ /* idle */
+ setbits_le32(&dram->pmu->pmu_bus_idle_req, (0x3 << 18));
+ while ((readl(&dram->pmu->pmu_bus_idle_st) & (0x3 << 18))
+ != (0x3 << 18))
+ ;
+
+ /* change freq */
+ writel((((0x3 << 4) | (1 << 2) | 1) << 16) |
+ (ctl << 4) | (1 << 2) | 1, &dram->cic->cic_ctrl0);
+ while (!(readl(&dram->cic->cic_status0) & (1 << 2)))
+ ;
+
+ ret_clk = clk_set_rate(&dram->ddr_clk, hz);
+ if (ret_clk < 0) {
+ printf("%s clk set failed %d\n", __func__, ret_clk);
+ return ret_clk;
+ }
+
+ writel(0x20002, &dram->cic->cic_ctrl0);
+ while (!(readl(&dram->cic->cic_status0) & (1 << 0)))
+ ;
+
+ /* deidle */
+ clrbits_le32(&dram->pmu->pmu_bus_idle_req, (0x3 << 18));
+ while (readl(&dram->pmu->pmu_bus_idle_st) & (0x3 << 18))
+ ;
+
+ /* clear enable all clk */
+ clrbits_le32(&dram->pmu->pmu_noc_auto_ena, (0x3 << 7));
+
+ /* LPDDR4 ctl2 can not do training, all training will fail */
+ if (!(params->base.dramtype == LPDDR4 && ctl == 2)) {
+ for (channel = 0; channel < 2; channel++) {
+ if (!(params->ch[channel].cap_info.col))
+ continue;
+ ret[channel] = data_training(&dram->chan[channel],
+ channel, params,
+ PI_FULL_TRAINING);
+ }
+ for (channel = 0; channel < 2; channel++) {
+ if (!(params->ch[channel].cap_info.col))
+ continue;
+ if (ret[channel])
+ printf("%s: channel %d training failed!\n",
+ __func__, channel);
+ else
+ debug("%s: channel %d training pass\n",
+ __func__, channel);
+ }
+ }
+
+ return 0;
+}
+
+static void lpddr4_set_rate(struct dram_info *dram,
+ struct rk3399_sdram_params *params)
+{
+ u32 ctl;
+ u32 phy;
+
+ for (ctl = 0; ctl < 2; ctl++) {
+ phy = lpddr4_get_phy(params, ctl);
+
+ lpddr4_set_phy(dram, params, phy, &lpddr4_timings[ctl]);
+ lpddr4_set_ctl(dram, params, ctl,
+ lpddr4_timings[ctl].base.ddr_freq);
+
+ debug("%s: change freq to %d MHz %d, %d\n", __func__,
+ lpddr4_timings[ctl].base.ddr_freq / MHz, ctl, phy);
+ }
+}
+
static void clear_channel_params(struct rk3399_sdram_params *params, u8 channel)
{
params->ch[channel].cap_info.rank = 0;
@@ -1943,7 +2322,11 @@ static int sdram_init(struct dram_info *dram,
sdram_params->base.stride = calculate_stride(sdram_params);
dram_all_config(dram, sdram_params);
- switch_to_phy_index1(dram, sdram_params);
+
+ if (sdram_params->base.dramtype == LPDDR4)
+ lpddr4_set_rate(dram, sdram_params);
+ else
+ switch_to_phy_index1(dram, sdram_params);
debug("Finish SDRAM initialization...\n");
return 0;
@@ -2007,6 +2390,7 @@ static int rk3399_dmc_init(struct udevice *dev)
priv->cic = syscon_get_first_range(ROCKCHIP_SYSCON_CIC);
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
priv->pmusgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
priv->pmucru = rockchip_get_pmucru();
@@ -2025,8 +2409,8 @@ static int rk3399_dmc_init(struct udevice *dev)
priv->chan[0].publ, priv->chan[0].msch,
priv->chan[1].pctl, priv->chan[1].pi,
priv->chan[1].publ, priv->chan[1].msch);
- debug("cru %p, cic %p, grf %p, sgrf %p, pmucru %p\n", priv->cru,
- priv->cic, priv->pmugrf, priv->pmusgrf, priv->pmucru);
+ debug("cru %p, cic %p, grf %p, sgrf %p, pmucru %p, pmu %p\n", priv->cru,
+ priv->cic, priv->pmugrf, priv->pmusgrf, priv->pmucru, priv->pmu);
#if CONFIG_IS_ENABLED(OF_PLATDATA)
ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->ddr_clk);
#else
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 84/92] ram: rk3399: Add lpddr4 set rate support
@ 2019-06-11 14:51 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: u-boot
Unlike rest of dram type chips, LPDDR4 initialization start
with at board selected frequency (say 50MHz) and then it
switches into 400MHz and 800MHz simultaneously to make the
proper sequence work on each channel with associated training.
Here is sameple log about LPDDR4-100 init sequence in Rockpro64:
Channel 0: LPDDR4, 50MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
Channel 1: LPDDR4, 50MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
256B stride
channel 0 training pass
channel 1 training pass
change freq to 400 MHz 0, 1
channel 0 training pass
channel 1 training pass
change freq to 800 MHz 1, 0
This patch add support to this init sequence via lpddr4 set rate
by taking sdram timing parameters from 400, 800 .inc files.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 402 +++++++++++++++++++++++++++-
1 file changed, 393 insertions(+), 9 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 5a0872c23f..170743b88c 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -16,6 +16,7 @@
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru_rk3399.h>
#include <asm/arch-rockchip/grf_rk3399.h>
+#include <asm/arch-rockchip/pmu_rk3399.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/sdram_common.h>
#include <asm/arch-rockchip/sdram_rk3399.h>
@@ -62,6 +63,7 @@ struct dram_info {
struct clk ddr_clk;
struct rk3399_cru *cru;
struct rk3399_grf_regs *grf;
+ struct rk3399_pmu_regs *pmu;
struct rk3399_pmucru *pmucru;
struct rk3399_pmusgrf_regs *pmusgrf;
struct rk3399_ddr_cic_regs *cic;
@@ -186,6 +188,11 @@ struct io_setting {
},
};
+struct rk3399_sdram_params lpddr4_timings[] = {
+ #include "sdram-rk3399-lpddr4-400.inc"
+ #include "sdram-rk3399-lpddr4-800.inc"
+};
+
/**
* phy = 0, PHY boot freq
* phy = 1, PHY index 0
@@ -213,11 +220,30 @@ lpddr4_get_io_settings(const struct rk3399_sdram_params *params, u32 mr5)
return io;
}
+static void *get_denali_phy(const struct chan_info *chan,
+ struct rk3399_sdram_params *params, bool reg)
+{
+ return reg ? &chan->publ->denali_phy : ¶ms->phy_regs.denali_phy;
+}
+
+static void *get_denali_ctl(const struct chan_info *chan,
+ struct rk3399_sdram_params *params, bool reg)
+{
+ return reg ? &chan->pctl->denali_ctl : ¶ms->pctl_regs.denali_ctl;
+}
+
static void *get_ddrc0_con(struct dram_info *dram, u8 channel)
{
return (channel == 0) ? &dram->grf->ddrc0_con0 : &dram->grf->ddrc0_con1;
}
+static u32 lpddr4_get_phy(struct rk3399_sdram_params *params, u32 ctl)
+{
+ u32 lpddr4_phy[] = {1, 0, 0xb};
+
+ return lpddr4_phy[ctl];
+}
+
static u32 get_ddr_stride(struct rk3399_pmusgrf_regs *pmusgrf)
{
return ((readl(&pmusgrf->soc_con4) >> 10) & 0x1F);
@@ -579,10 +605,11 @@ static int phy_io_config(const struct chan_info *chan,
}
static void set_ds_odt(const struct chan_info *chan,
- const struct rk3399_sdram_params *sdram_params, u32 mr5)
+ struct rk3399_sdram_params *sdram_params,
+ bool ctl_phy_reg, u32 mr5)
{
- u32 *denali_phy = chan->publ->denali_phy;
- u32 *denali_ctl = chan->pctl->denali_ctl;
+ u32 *denali_phy = get_denali_phy(chan, sdram_params, ctl_phy_reg);
+ u32 *denali_ctl = get_denali_ctl(chan, sdram_params, ctl_phy_reg);
u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
u32 tsel_idle_select_p, tsel_rd_select_p;
u32 tsel_idle_select_n, tsel_rd_select_n;
@@ -740,7 +767,8 @@ static void set_ds_odt(const struct chan_info *chan,
clrsetbits_le32(&denali_phy[928], 0xff, reg_value);
/* phy_pad_rst_drive 8bits DENALI_PHY_937 offset_0 */
- clrsetbits_le32(&denali_phy[937], 0xff, reg_value);
+ if (!ctl_phy_reg)
+ clrsetbits_le32(&denali_phy[937], 0xff, reg_value);
/* phy_pad_cke_drive 8bits DENALI_PHY_935 offset_0 */
clrsetbits_le32(&denali_phy[935], 0xff, reg_value);
@@ -930,7 +958,7 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
copy_to_reg(&denali_phy[512], ¶ms_phy[512], (549 - 512 + 1) * 4);
copy_to_reg(&denali_phy[640], ¶ms_phy[640], (677 - 640 + 1) * 4);
copy_to_reg(&denali_phy[768], ¶ms_phy[768], (805 - 768 + 1) * 4);
- set_ds_odt(chan, sdram_params, 0);
+ set_ds_odt(chan, sdram_params, true, 0);
/*
* phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_84/212/340/468 offset_8
@@ -1317,7 +1345,7 @@ static int data_training(const struct chan_info *chan, u32 channel,
if (training_flag == PI_FULL_TRAINING) {
if (sdram_params->base.dramtype == LPDDR4) {
- training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING |
+ training_flag = PI_WRITE_LEVELING |
PI_READ_GATE_TRAINING |
PI_READ_LEVELING | PI_WDQ_LEVELING;
} else if (sdram_params->base.dramtype == LPDDR3) {
@@ -1812,6 +1840,357 @@ end:
return ret;
}
+static void lpddr4_copy_phy(struct dram_info *dram,
+ struct rk3399_sdram_params *params, u32 phy,
+ struct rk3399_sdram_params *timings,
+ u32 channel)
+{
+ u32 *denali_phy;
+ u32 *denali_phy_params;
+ u32 speed = 0;
+ u32 mr5;
+
+ denali_phy = dram->chan[channel].publ->denali_phy;
+ denali_phy_params = timings->phy_regs.denali_phy;
+
+ /* switch index */
+ clrsetbits_le32(&denali_phy_params[896], 0x3 << 8, phy << 8);
+ writel(denali_phy_params[896], &denali_phy[896]);
+
+ /* phy_pll_ctrl_ca, phy_pll_ctrl */
+ writel(denali_phy_params[911], &denali_phy[911]);
+
+ /* phy_low_freq_sel */
+ clrsetbits_le32(&denali_phy[913], 0x1,
+ denali_phy_params[913] & 0x1);
+
+ /* PHY_GRP_SLAVE_DELAY_X, phy_cslvl_dly_step */
+ writel(denali_phy_params[916], &denali_phy[916]);
+ writel(denali_phy_params[917], &denali_phy[917]);
+ writel(denali_phy_params[918], &denali_phy[918]);
+
+ /* phy_adrZ_sw_wraddr_shift_X */
+ writel(denali_phy_params[512], &denali_phy[512]);
+ clrsetbits_le32(&denali_phy[513], 0xFFFF,
+ denali_phy_params[513] & 0xFFFF);
+ writel(denali_phy_params[640], &denali_phy[640]);
+ clrsetbits_le32(&denali_phy[641], 0xFFFF,
+ denali_phy_params[641] & 0xFFFF);
+ writel(denali_phy_params[768], &denali_phy[768]);
+ clrsetbits_le32(&denali_phy[769], 0xFFFF,
+ denali_phy_params[769] & 0xFFFF);
+
+ writel(denali_phy_params[544], &denali_phy[544]);
+ writel(denali_phy_params[545], &denali_phy[545]);
+ writel(denali_phy_params[546], &denali_phy[546]);
+ writel(denali_phy_params[547], &denali_phy[547]);
+
+ writel(denali_phy_params[672], &denali_phy[672]);
+ writel(denali_phy_params[673], &denali_phy[673]);
+ writel(denali_phy_params[674], &denali_phy[674]);
+ writel(denali_phy_params[675], &denali_phy[675]);
+
+ writel(denali_phy_params[800], &denali_phy[800]);
+ writel(denali_phy_params[801], &denali_phy[801]);
+ writel(denali_phy_params[802], &denali_phy[802]);
+ writel(denali_phy_params[803], &denali_phy[803]);
+
+ /*
+ * phy_adr_master_delay_start_X
+ * phy_adr_master_delay_step_X
+ * phy_adr_master_delay_wait_X
+ */
+ writel(denali_phy_params[548], &denali_phy[548]);
+ writel(denali_phy_params[676], &denali_phy[676]);
+ writel(denali_phy_params[804], &denali_phy[804]);
+
+ /* phy_adr_calvl_dly_step_X */
+ writel(denali_phy_params[549], &denali_phy[549]);
+ writel(denali_phy_params[677], &denali_phy[677]);
+ writel(denali_phy_params[805], &denali_phy[805]);
+
+ /*
+ * phy_clk_wrdm_slave_delay_X
+ * phy_clk_wrdqZ_slave_delay_X
+ * phy_clk_wrdqs_slave_delay_X
+ */
+ copy_to_reg((u32 *)&denali_phy[59], (u32 *)&denali_phy_params[59],
+ (63 - 58) * 4);
+ copy_to_reg((u32 *)&denali_phy[187], (u32 *)&denali_phy_params[187],
+ (191 - 186) * 4);
+ copy_to_reg((u32 *)&denali_phy[315], (u32 *)&denali_phy_params[315],
+ (319 - 314) * 4);
+ copy_to_reg((u32 *)&denali_phy[443], (u32 *)&denali_phy_params[443],
+ (447 - 442) * 4);
+
+ /*
+ * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_84/212/340/468 offset_8
+ * dqs_tsel_wr_end[7:4] add Half cycle
+ * phy_dq_tsel_wr_timing_X 8bits DENALI_PHY_83/211/339/467 offset_8
+ * dq_tsel_wr_end[7:4] add Half cycle
+ */
+ writel(denali_phy_params[83] + (0x10 << 16), &denali_phy[83]);
+ writel(denali_phy_params[84] + (0x10 << 8), &denali_phy[84]);
+ writel(denali_phy_params[85], &denali_phy[85]);
+
+ writel(denali_phy_params[211] + (0x10 << 16), &denali_phy[211]);
+ writel(denali_phy_params[212] + (0x10 << 8), &denali_phy[212]);
+ writel(denali_phy_params[213], &denali_phy[213]);
+
+ writel(denali_phy_params[339] + (0x10 << 16), &denali_phy[339]);
+ writel(denali_phy_params[340] + (0x10 << 8), &denali_phy[340]);
+ writel(denali_phy_params[341], &denali_phy[341]);
+
+ writel(denali_phy_params[467] + (0x10 << 16), &denali_phy[467]);
+ writel(denali_phy_params[468] + (0x10 << 8), &denali_phy[468]);
+ writel(denali_phy_params[469], &denali_phy[469]);
+
+ /*
+ * phy_gtlvl_resp_wait_cnt_X
+ * phy_gtlvl_dly_step_X
+ * phy_wrlvl_resp_wait_cnt_X
+ * phy_gtlvl_final_step_X
+ * phy_gtlvl_back_step_X
+ * phy_rdlvl_dly_step_X
+ *
+ * phy_master_delay_step_X
+ * phy_master_delay_wait_X
+ * phy_wrlvl_dly_step_X
+ * phy_rptr_update_X
+ * phy_wdqlvl_dly_step_X
+ */
+ writel(denali_phy_params[87], &denali_phy[87]);
+ writel(denali_phy_params[88], &denali_phy[88]);
+ writel(denali_phy_params[89], &denali_phy[89]);
+ writel(denali_phy_params[90], &denali_phy[90]);
+
+ writel(denali_phy_params[215], &denali_phy[215]);
+ writel(denali_phy_params[216], &denali_phy[216]);
+ writel(denali_phy_params[217], &denali_phy[217]);
+ writel(denali_phy_params[218], &denali_phy[218]);
+
+ writel(denali_phy_params[343], &denali_phy[343]);
+ writel(denali_phy_params[344], &denali_phy[344]);
+ writel(denali_phy_params[345], &denali_phy[345]);
+ writel(denali_phy_params[346], &denali_phy[346]);
+
+ writel(denali_phy_params[471], &denali_phy[471]);
+ writel(denali_phy_params[472], &denali_phy[472]);
+ writel(denali_phy_params[473], &denali_phy[473]);
+ writel(denali_phy_params[474], &denali_phy[474]);
+
+ /*
+ * phy_gtlvl_lat_adj_start_X
+ * phy_gtlvl_rddqs_slv_dly_start_X
+ * phy_rdlvl_rddqs_dq_slv_dly_start_X
+ * phy_wdqlvl_dqdm_slv_dly_start_X
+ */
+ writel(denali_phy_params[80], &denali_phy[80]);
+ writel(denali_phy_params[81], &denali_phy[81]);
+
+ writel(denali_phy_params[208], &denali_phy[208]);
+ writel(denali_phy_params[209], &denali_phy[209]);
+
+ writel(denali_phy_params[336], &denali_phy[336]);
+ writel(denali_phy_params[337], &denali_phy[337]);
+
+ writel(denali_phy_params[464], &denali_phy[464]);
+ writel(denali_phy_params[465], &denali_phy[465]);
+
+ /*
+ * phy_master_delay_start_X
+ * phy_sw_master_mode_X
+ * phy_rddata_en_tsel_dly_X
+ */
+ writel(denali_phy_params[86], &denali_phy[86]);
+ writel(denali_phy_params[214], &denali_phy[214]);
+ writel(denali_phy_params[342], &denali_phy[342]);
+ writel(denali_phy_params[470], &denali_phy[470]);
+
+ /*
+ * phy_rddqZ_slave_delay_X
+ * phy_rddqs_dqZ_fall_slave_delay_X
+ * phy_rddqs_dqZ_rise_slave_delay_X
+ * phy_rddqs_dm_fall_slave_delay_X
+ * phy_rddqs_dm_rise_slave_delay_X
+ * phy_rddqs_gate_slave_delay_X
+ * phy_wrlvl_delay_early_threshold_X
+ * phy_write_path_lat_add_X
+ * phy_rddqs_latency_adjust_X
+ * phy_wrlvl_delay_period_threshold_X
+ * phy_wrlvl_early_force_zero_X
+ */
+ copy_to_reg((u32 *)&denali_phy[64], (u32 *)&denali_phy_params[64],
+ (67 - 63) * 4);
+ clrsetbits_le32(&denali_phy[68], 0xFFFFFC00,
+ denali_phy_params[68] & 0xFFFFFC00);
+ copy_to_reg((u32 *)&denali_phy[69], (u32 *)&denali_phy_params[69],
+ (79 - 68) * 4);
+ copy_to_reg((u32 *)&denali_phy[192], (u32 *)&denali_phy_params[192],
+ (195 - 191) * 4);
+ clrsetbits_le32(&denali_phy[196], 0xFFFFFC00,
+ denali_phy_params[196] & 0xFFFFFC00);
+ copy_to_reg((u32 *)&denali_phy[197], (u32 *)&denali_phy_params[197],
+ (207 - 196) * 4);
+ copy_to_reg((u32 *)&denali_phy[320], (u32 *)&denali_phy_params[320],
+ (323 - 319) * 4);
+ clrsetbits_le32(&denali_phy[324], 0xFFFFFC00,
+ denali_phy_params[324] & 0xFFFFFC00);
+ copy_to_reg((u32 *)&denali_phy[325], (u32 *)&denali_phy_params[325],
+ (335 - 324) * 4);
+
+ copy_to_reg((u32 *)&denali_phy[448], (u32 *)&denali_phy_params[448],
+ (451 - 447) * 4);
+ clrsetbits_le32(&denali_phy[452], 0xFFFFFC00,
+ denali_phy_params[452] & 0xFFFFFC00);
+ copy_to_reg((u32 *)&denali_phy[453], (u32 *)&denali_phy_params[453],
+ (463 - 452) * 4);
+
+ /* phy_two_cyc_preamble_X */
+ clrsetbits_le32(&denali_phy[7], 0x3 << 24,
+ denali_phy_params[7] & (0x3 << 24));
+ clrsetbits_le32(&denali_phy[135], 0x3 << 24,
+ denali_phy_params[135] & (0x3 << 24));
+ clrsetbits_le32(&denali_phy[263], 0x3 << 24,
+ denali_phy_params[263] & (0x3 << 24));
+ clrsetbits_le32(&denali_phy[391], 0x3 << 24,
+ denali_phy_params[391] & (0x3 << 24));
+
+ /* speed */
+ if (timings->base.ddr_freq < 400 * MHz)
+ speed = 0x0;
+ else if (timings->base.ddr_freq < 800 * MHz)
+ speed = 0x1;
+ else if (timings->base.ddr_freq < 1200 * MHz)
+ speed = 0x2;
+
+ /* PHY_924 PHY_PAD_FDBK_DRIVE */
+ clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21);
+ /* PHY_926 PHY_PAD_DATA_DRIVE */
+ clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9);
+ /* PHY_927 PHY_PAD_DQS_DRIVE */
+ clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9);
+ /* PHY_928 PHY_PAD_ADDR_DRIVE */
+ clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17);
+ /* PHY_929 PHY_PAD_CLK_DRIVE */
+ clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17);
+ /* PHY_935 PHY_PAD_CKE_DRIVE */
+ clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17);
+ /* PHY_937 PHY_PAD_RST_DRIVE */
+ clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17);
+ /* PHY_939 PHY_PAD_CS_DRIVE */
+ clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17);
+
+ read_mr(dram->chan[channel].pctl, 1, 5, &mr5);
+ set_ds_odt(&dram->chan[channel], timings, true, mr5);
+
+ /*
+ * if phy_sw_master_mode_X not bypass mode,
+ * clear PHY_SLICE_PWR_RDC_DISABLE.
+ * NOTE: need use timings, not ddr_publ_regs
+ */
+ if (!((denali_phy_params[86] >> 8) & (1 << 2))) {
+ clrbits_le32(&denali_phy[10], 1 << 16);
+ clrbits_le32(&denali_phy[138], 1 << 16);
+ clrbits_le32(&denali_phy[266], 1 << 16);
+ clrbits_le32(&denali_phy[394], 1 << 16);
+ }
+}
+
+static void lpddr4_set_phy(struct dram_info *dram,
+ struct rk3399_sdram_params *params, u32 phy,
+ struct rk3399_sdram_params *timings)
+{
+ u32 channel;
+
+ for (channel = 0; channel < 2; channel++)
+ lpddr4_copy_phy(dram, params, phy, timings, channel);
+}
+
+static int lpddr4_set_ctl(struct dram_info *dram,
+ struct rk3399_sdram_params *params, u32 ctl, u32 hz)
+{
+ u32 channel;
+ int ret_clk, ret[2];
+
+ /* cci idle req stall */
+ writel(0x70007, &dram->grf->soc_con0);
+
+ /* enable all clk */
+ setbits_le32(&dram->pmu->pmu_noc_auto_ena, (0x3 << 7));
+
+ /* idle */
+ setbits_le32(&dram->pmu->pmu_bus_idle_req, (0x3 << 18));
+ while ((readl(&dram->pmu->pmu_bus_idle_st) & (0x3 << 18))
+ != (0x3 << 18))
+ ;
+
+ /* change freq */
+ writel((((0x3 << 4) | (1 << 2) | 1) << 16) |
+ (ctl << 4) | (1 << 2) | 1, &dram->cic->cic_ctrl0);
+ while (!(readl(&dram->cic->cic_status0) & (1 << 2)))
+ ;
+
+ ret_clk = clk_set_rate(&dram->ddr_clk, hz);
+ if (ret_clk < 0) {
+ printf("%s clk set failed %d\n", __func__, ret_clk);
+ return ret_clk;
+ }
+
+ writel(0x20002, &dram->cic->cic_ctrl0);
+ while (!(readl(&dram->cic->cic_status0) & (1 << 0)))
+ ;
+
+ /* deidle */
+ clrbits_le32(&dram->pmu->pmu_bus_idle_req, (0x3 << 18));
+ while (readl(&dram->pmu->pmu_bus_idle_st) & (0x3 << 18))
+ ;
+
+ /* clear enable all clk */
+ clrbits_le32(&dram->pmu->pmu_noc_auto_ena, (0x3 << 7));
+
+ /* LPDDR4 ctl2 can not do training, all training will fail */
+ if (!(params->base.dramtype == LPDDR4 && ctl == 2)) {
+ for (channel = 0; channel < 2; channel++) {
+ if (!(params->ch[channel].cap_info.col))
+ continue;
+ ret[channel] = data_training(&dram->chan[channel],
+ channel, params,
+ PI_FULL_TRAINING);
+ }
+ for (channel = 0; channel < 2; channel++) {
+ if (!(params->ch[channel].cap_info.col))
+ continue;
+ if (ret[channel])
+ printf("%s: channel %d training failed!\n",
+ __func__, channel);
+ else
+ debug("%s: channel %d training pass\n",
+ __func__, channel);
+ }
+ }
+
+ return 0;
+}
+
+static void lpddr4_set_rate(struct dram_info *dram,
+ struct rk3399_sdram_params *params)
+{
+ u32 ctl;
+ u32 phy;
+
+ for (ctl = 0; ctl < 2; ctl++) {
+ phy = lpddr4_get_phy(params, ctl);
+
+ lpddr4_set_phy(dram, params, phy, &lpddr4_timings[ctl]);
+ lpddr4_set_ctl(dram, params, ctl,
+ lpddr4_timings[ctl].base.ddr_freq);
+
+ debug("%s: change freq to %d MHz %d, %d\n", __func__,
+ lpddr4_timings[ctl].base.ddr_freq / MHz, ctl, phy);
+ }
+}
+
static void clear_channel_params(struct rk3399_sdram_params *params, u8 channel)
{
params->ch[channel].cap_info.rank = 0;
@@ -1943,7 +2322,11 @@ static int sdram_init(struct dram_info *dram,
sdram_params->base.stride = calculate_stride(sdram_params);
dram_all_config(dram, sdram_params);
- switch_to_phy_index1(dram, sdram_params);
+
+ if (sdram_params->base.dramtype == LPDDR4)
+ lpddr4_set_rate(dram, sdram_params);
+ else
+ switch_to_phy_index1(dram, sdram_params);
debug("Finish SDRAM initialization...\n");
return 0;
@@ -2007,6 +2390,7 @@ static int rk3399_dmc_init(struct udevice *dev)
priv->cic = syscon_get_first_range(ROCKCHIP_SYSCON_CIC);
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
priv->pmusgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
priv->pmucru = rockchip_get_pmucru();
@@ -2025,8 +2409,8 @@ static int rk3399_dmc_init(struct udevice *dev)
priv->chan[0].publ, priv->chan[0].msch,
priv->chan[1].pctl, priv->chan[1].pi,
priv->chan[1].publ, priv->chan[1].msch);
- debug("cru %p, cic %p, grf %p, sgrf %p, pmucru %p\n", priv->cru,
- priv->cic, priv->pmugrf, priv->pmusgrf, priv->pmucru);
+ debug("cru %p, cic %p, grf %p, sgrf %p, pmucru %p, pmu %p\n", priv->cru,
+ priv->cic, priv->pmugrf, priv->pmusgrf, priv->pmucru, priv->pmu);
#if CONFIG_IS_ENABLED(OF_PLATDATA)
ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->ddr_clk);
#else
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 85/92] ram: rk3399: Set lpddr4 dq odt
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:51 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Set DQ ODT based identified controller in lpddr4
as part of LPDDR set rate initialization phase.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 80 ++++++++++++++++++++++++++++-
1 file changed, 78 insertions(+), 2 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 170743b88c..fc9958de17 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -220,6 +220,12 @@ lpddr4_get_io_settings(const struct rk3399_sdram_params *params, u32 mr5)
return io;
}
+static void *get_denali_pi(const struct chan_info *chan,
+ struct rk3399_sdram_params *params, bool reg)
+{
+ return reg ? &chan->pi->denali_pi : ¶ms->pi_regs.denali_pi;
+}
+
static void *get_denali_phy(const struct chan_info *chan,
struct rk3399_sdram_params *params, bool reg)
{
@@ -244,6 +250,13 @@ static u32 lpddr4_get_phy(struct rk3399_sdram_params *params, u32 ctl)
return lpddr4_phy[ctl];
}
+static u32 lpddr4_get_ctl(struct rk3399_sdram_params *params, u32 phy)
+{
+ u32 lpddr4_ctl[] = {1, 0, 2};
+
+ return lpddr4_ctl[phy];
+}
+
static u32 get_ddr_stride(struct rk3399_pmusgrf_regs *pmusgrf)
{
return ((readl(&pmusgrf->soc_con4) >> 10) & 0x1F);
@@ -1840,16 +1853,65 @@ end:
return ret;
}
+static void set_lpddr4_dq_odt(const struct chan_info *chan,
+ struct rk3399_sdram_params *params, u32 ctl,
+ bool en, bool ctl_phy_reg, u32 mr5)
+{
+ u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg);
+ u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg);
+ struct io_setting *io;
+ u32 reg_value;
+
+ if (!en)
+ return;
+
+ io = lpddr4_get_io_settings(params, mr5);
+
+ reg_value = io->dq_odt;
+
+ switch (ctl) {
+ case 0:
+ clrsetbits_le32(&denali_ctl[139], 0x7 << 24, reg_value << 24);
+ clrsetbits_le32(&denali_ctl[153], 0x7 << 24, reg_value << 24);
+
+ clrsetbits_le32(&denali_pi[132], 0x7 << 0, (reg_value << 0));
+ clrsetbits_le32(&denali_pi[139], 0x7 << 16, (reg_value << 16));
+ clrsetbits_le32(&denali_pi[147], 0x7 << 0, (reg_value << 0));
+ clrsetbits_le32(&denali_pi[154], 0x7 << 16, (reg_value << 16));
+ break;
+ case 1:
+ clrsetbits_le32(&denali_ctl[140], 0x7 << 0, reg_value << 0);
+ clrsetbits_le32(&denali_ctl[154], 0x7 << 0, reg_value << 0);
+
+ clrsetbits_le32(&denali_pi[129], 0x7 << 16, (reg_value << 16));
+ clrsetbits_le32(&denali_pi[137], 0x7 << 0, (reg_value << 0));
+ clrsetbits_le32(&denali_pi[144], 0x7 << 16, (reg_value << 16));
+ clrsetbits_le32(&denali_pi[152], 0x7 << 0, (reg_value << 0));
+ break;
+ case 2:
+ default:
+ clrsetbits_le32(&denali_ctl[140], 0x7 << 8, (reg_value << 8));
+ clrsetbits_le32(&denali_ctl[154], 0x7 << 8, (reg_value << 8));
+
+ clrsetbits_le32(&denali_pi[127], 0x7 << 0, (reg_value << 0));
+ clrsetbits_le32(&denali_pi[134], 0x7 << 16, (reg_value << 16));
+ clrsetbits_le32(&denali_pi[142], 0x7 << 0, (reg_value << 0));
+ clrsetbits_le32(&denali_pi[149], 0x7 << 16, (reg_value << 16));
+ break;
+ }
+}
+
static void lpddr4_copy_phy(struct dram_info *dram,
struct rk3399_sdram_params *params, u32 phy,
struct rk3399_sdram_params *timings,
u32 channel)
{
- u32 *denali_phy;
+ u32 *denali_ctl, *denali_phy;
u32 *denali_phy_params;
u32 speed = 0;
- u32 mr5;
+ u32 ctl, mr5;
+ denali_ctl = dram->chan[channel].pctl->denali_ctl;
denali_phy = dram->chan[channel].publ->denali_phy;
denali_phy_params = timings->phy_regs.denali_phy;
@@ -2084,6 +2146,9 @@ static void lpddr4_copy_phy(struct dram_info *dram,
read_mr(dram->chan[channel].pctl, 1, 5, &mr5);
set_ds_odt(&dram->chan[channel], timings, true, mr5);
+ ctl = lpddr4_get_ctl(timings, phy);
+ set_lpddr4_dq_odt(&dram->chan[channel], timings, ctl, true, true, mr5);
+
/*
* if phy_sw_master_mode_X not bypass mode,
* clear PHY_SLICE_PWR_RDC_DISABLE.
@@ -2095,6 +2160,17 @@ static void lpddr4_copy_phy(struct dram_info *dram,
clrbits_le32(&denali_phy[266], 1 << 16);
clrbits_le32(&denali_phy[394], 1 << 16);
}
+
+ /*
+ * when PHY_PER_CS_TRAINING_EN=1, W2W_DIFFCS_DLY_Fx can't
+ * smaller than 8
+ * NOTE: need use timings, not ddr_publ_regs
+ */
+ if ((denali_phy_params[84] >> 16) & 1) {
+ if (((readl(&denali_ctl[217 + ctl]) >> 16) & 0x1f) < 8)
+ clrsetbits_le32(&denali_ctl[217 + ctl],
+ 0x1f << 16, 8 << 16);
+ }
}
static void lpddr4_set_phy(struct dram_info *dram,
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 85/92] ram: rk3399: Set lpddr4 dq odt
@ 2019-06-11 14:51 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: u-boot
Set DQ ODT based identified controller in lpddr4
as part of LPDDR set rate initialization phase.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 80 ++++++++++++++++++++++++++++-
1 file changed, 78 insertions(+), 2 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 170743b88c..fc9958de17 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -220,6 +220,12 @@ lpddr4_get_io_settings(const struct rk3399_sdram_params *params, u32 mr5)
return io;
}
+static void *get_denali_pi(const struct chan_info *chan,
+ struct rk3399_sdram_params *params, bool reg)
+{
+ return reg ? &chan->pi->denali_pi : ¶ms->pi_regs.denali_pi;
+}
+
static void *get_denali_phy(const struct chan_info *chan,
struct rk3399_sdram_params *params, bool reg)
{
@@ -244,6 +250,13 @@ static u32 lpddr4_get_phy(struct rk3399_sdram_params *params, u32 ctl)
return lpddr4_phy[ctl];
}
+static u32 lpddr4_get_ctl(struct rk3399_sdram_params *params, u32 phy)
+{
+ u32 lpddr4_ctl[] = {1, 0, 2};
+
+ return lpddr4_ctl[phy];
+}
+
static u32 get_ddr_stride(struct rk3399_pmusgrf_regs *pmusgrf)
{
return ((readl(&pmusgrf->soc_con4) >> 10) & 0x1F);
@@ -1840,16 +1853,65 @@ end:
return ret;
}
+static void set_lpddr4_dq_odt(const struct chan_info *chan,
+ struct rk3399_sdram_params *params, u32 ctl,
+ bool en, bool ctl_phy_reg, u32 mr5)
+{
+ u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg);
+ u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg);
+ struct io_setting *io;
+ u32 reg_value;
+
+ if (!en)
+ return;
+
+ io = lpddr4_get_io_settings(params, mr5);
+
+ reg_value = io->dq_odt;
+
+ switch (ctl) {
+ case 0:
+ clrsetbits_le32(&denali_ctl[139], 0x7 << 24, reg_value << 24);
+ clrsetbits_le32(&denali_ctl[153], 0x7 << 24, reg_value << 24);
+
+ clrsetbits_le32(&denali_pi[132], 0x7 << 0, (reg_value << 0));
+ clrsetbits_le32(&denali_pi[139], 0x7 << 16, (reg_value << 16));
+ clrsetbits_le32(&denali_pi[147], 0x7 << 0, (reg_value << 0));
+ clrsetbits_le32(&denali_pi[154], 0x7 << 16, (reg_value << 16));
+ break;
+ case 1:
+ clrsetbits_le32(&denali_ctl[140], 0x7 << 0, reg_value << 0);
+ clrsetbits_le32(&denali_ctl[154], 0x7 << 0, reg_value << 0);
+
+ clrsetbits_le32(&denali_pi[129], 0x7 << 16, (reg_value << 16));
+ clrsetbits_le32(&denali_pi[137], 0x7 << 0, (reg_value << 0));
+ clrsetbits_le32(&denali_pi[144], 0x7 << 16, (reg_value << 16));
+ clrsetbits_le32(&denali_pi[152], 0x7 << 0, (reg_value << 0));
+ break;
+ case 2:
+ default:
+ clrsetbits_le32(&denali_ctl[140], 0x7 << 8, (reg_value << 8));
+ clrsetbits_le32(&denali_ctl[154], 0x7 << 8, (reg_value << 8));
+
+ clrsetbits_le32(&denali_pi[127], 0x7 << 0, (reg_value << 0));
+ clrsetbits_le32(&denali_pi[134], 0x7 << 16, (reg_value << 16));
+ clrsetbits_le32(&denali_pi[142], 0x7 << 0, (reg_value << 0));
+ clrsetbits_le32(&denali_pi[149], 0x7 << 16, (reg_value << 16));
+ break;
+ }
+}
+
static void lpddr4_copy_phy(struct dram_info *dram,
struct rk3399_sdram_params *params, u32 phy,
struct rk3399_sdram_params *timings,
u32 channel)
{
- u32 *denali_phy;
+ u32 *denali_ctl, *denali_phy;
u32 *denali_phy_params;
u32 speed = 0;
- u32 mr5;
+ u32 ctl, mr5;
+ denali_ctl = dram->chan[channel].pctl->denali_ctl;
denali_phy = dram->chan[channel].publ->denali_phy;
denali_phy_params = timings->phy_regs.denali_phy;
@@ -2084,6 +2146,9 @@ static void lpddr4_copy_phy(struct dram_info *dram,
read_mr(dram->chan[channel].pctl, 1, 5, &mr5);
set_ds_odt(&dram->chan[channel], timings, true, mr5);
+ ctl = lpddr4_get_ctl(timings, phy);
+ set_lpddr4_dq_odt(&dram->chan[channel], timings, ctl, true, true, mr5);
+
/*
* if phy_sw_master_mode_X not bypass mode,
* clear PHY_SLICE_PWR_RDC_DISABLE.
@@ -2095,6 +2160,17 @@ static void lpddr4_copy_phy(struct dram_info *dram,
clrbits_le32(&denali_phy[266], 1 << 16);
clrbits_le32(&denali_phy[394], 1 << 16);
}
+
+ /*
+ * when PHY_PER_CS_TRAINING_EN=1, W2W_DIFFCS_DLY_Fx can't
+ * smaller than 8
+ * NOTE: need use timings, not ddr_publ_regs
+ */
+ if ((denali_phy_params[84] >> 16) & 1) {
+ if (((readl(&denali_ctl[217 + ctl]) >> 16) & 0x1f) < 8)
+ clrsetbits_le32(&denali_ctl[217 + ctl],
+ 0x1f << 16, 8 << 16);
+ }
}
static void lpddr4_set_phy(struct dram_info *dram,
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 86/92] ram: rk3399: Set lpddr4 ca odt
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:51 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Set CA ODT based identified controller in lpddr4
as part of LPDDR set rate initialization phase.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 49 +++++++++++++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index fc9958de17..2c02c51fdf 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1901,6 +1901,54 @@ static void set_lpddr4_dq_odt(const struct chan_info *chan,
}
}
+static void set_lpddr4_ca_odt(const struct chan_info *chan,
+ struct rk3399_sdram_params *params, u32 ctl,
+ bool en, bool ctl_phy_reg, u32 mr5)
+{
+ u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg);
+ u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg);
+ struct io_setting *io;
+ u32 reg_value;
+
+ if (!en)
+ return;
+
+ io = lpddr4_get_io_settings(params, mr5);
+
+ reg_value = io->ca_odt;
+
+ switch (ctl) {
+ case 0:
+ clrsetbits_le32(&denali_ctl[139], 0x7 << 28, reg_value << 28);
+ clrsetbits_le32(&denali_ctl[153], 0x7 << 28, reg_value << 28);
+
+ clrsetbits_le32(&denali_pi[132], 0x7 << 4, reg_value << 4);
+ clrsetbits_le32(&denali_pi[139], 0x7 << 20, reg_value << 20);
+ clrsetbits_le32(&denali_pi[147], 0x7 << 4, reg_value << 4);
+ clrsetbits_le32(&denali_pi[154], 0x7 << 20, reg_value << 20);
+ break;
+ case 1:
+ clrsetbits_le32(&denali_ctl[140], 0x7 << 4, reg_value << 4);
+ clrsetbits_le32(&denali_ctl[154], 0x7 << 4, reg_value << 4);
+
+ clrsetbits_le32(&denali_pi[129], 0x7 << 20, reg_value << 20);
+ clrsetbits_le32(&denali_pi[137], 0x7 << 4, reg_value << 4);
+ clrsetbits_le32(&denali_pi[144], 0x7 << 20, reg_value << 20);
+ clrsetbits_le32(&denali_pi[152], 0x7 << 4, reg_value << 4);
+ break;
+ case 2:
+ default:
+ clrsetbits_le32(&denali_ctl[140], 0x7 << 12, (reg_value << 12));
+ clrsetbits_le32(&denali_ctl[154], 0x7 << 12, (reg_value << 12));
+
+ clrsetbits_le32(&denali_pi[127], 0x7 << 4, reg_value << 4);
+ clrsetbits_le32(&denali_pi[134], 0x7 << 20, reg_value << 20);
+ clrsetbits_le32(&denali_pi[142], 0x7 << 4, reg_value << 4);
+ clrsetbits_le32(&denali_pi[149], 0x7 << 20, reg_value << 20);
+ break;
+ }
+}
+
static void lpddr4_copy_phy(struct dram_info *dram,
struct rk3399_sdram_params *params, u32 phy,
struct rk3399_sdram_params *timings,
@@ -2148,6 +2196,7 @@ static void lpddr4_copy_phy(struct dram_info *dram,
ctl = lpddr4_get_ctl(timings, phy);
set_lpddr4_dq_odt(&dram->chan[channel], timings, ctl, true, true, mr5);
+ set_lpddr4_ca_odt(&dram->chan[channel], timings, ctl, true, true, mr5);
/*
* if phy_sw_master_mode_X not bypass mode,
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 86/92] ram: rk3399: Set lpddr4 ca odt
@ 2019-06-11 14:51 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: u-boot
Set CA ODT based identified controller in lpddr4
as part of LPDDR set rate initialization phase.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 49 +++++++++++++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index fc9958de17..2c02c51fdf 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1901,6 +1901,54 @@ static void set_lpddr4_dq_odt(const struct chan_info *chan,
}
}
+static void set_lpddr4_ca_odt(const struct chan_info *chan,
+ struct rk3399_sdram_params *params, u32 ctl,
+ bool en, bool ctl_phy_reg, u32 mr5)
+{
+ u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg);
+ u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg);
+ struct io_setting *io;
+ u32 reg_value;
+
+ if (!en)
+ return;
+
+ io = lpddr4_get_io_settings(params, mr5);
+
+ reg_value = io->ca_odt;
+
+ switch (ctl) {
+ case 0:
+ clrsetbits_le32(&denali_ctl[139], 0x7 << 28, reg_value << 28);
+ clrsetbits_le32(&denali_ctl[153], 0x7 << 28, reg_value << 28);
+
+ clrsetbits_le32(&denali_pi[132], 0x7 << 4, reg_value << 4);
+ clrsetbits_le32(&denali_pi[139], 0x7 << 20, reg_value << 20);
+ clrsetbits_le32(&denali_pi[147], 0x7 << 4, reg_value << 4);
+ clrsetbits_le32(&denali_pi[154], 0x7 << 20, reg_value << 20);
+ break;
+ case 1:
+ clrsetbits_le32(&denali_ctl[140], 0x7 << 4, reg_value << 4);
+ clrsetbits_le32(&denali_ctl[154], 0x7 << 4, reg_value << 4);
+
+ clrsetbits_le32(&denali_pi[129], 0x7 << 20, reg_value << 20);
+ clrsetbits_le32(&denali_pi[137], 0x7 << 4, reg_value << 4);
+ clrsetbits_le32(&denali_pi[144], 0x7 << 20, reg_value << 20);
+ clrsetbits_le32(&denali_pi[152], 0x7 << 4, reg_value << 4);
+ break;
+ case 2:
+ default:
+ clrsetbits_le32(&denali_ctl[140], 0x7 << 12, (reg_value << 12));
+ clrsetbits_le32(&denali_ctl[154], 0x7 << 12, (reg_value << 12));
+
+ clrsetbits_le32(&denali_pi[127], 0x7 << 4, reg_value << 4);
+ clrsetbits_le32(&denali_pi[134], 0x7 << 20, reg_value << 20);
+ clrsetbits_le32(&denali_pi[142], 0x7 << 4, reg_value << 4);
+ clrsetbits_le32(&denali_pi[149], 0x7 << 20, reg_value << 20);
+ break;
+ }
+}
+
static void lpddr4_copy_phy(struct dram_info *dram,
struct rk3399_sdram_params *params, u32 phy,
struct rk3399_sdram_params *timings,
@@ -2148,6 +2196,7 @@ static void lpddr4_copy_phy(struct dram_info *dram,
ctl = lpddr4_get_ctl(timings, phy);
set_lpddr4_dq_odt(&dram->chan[channel], timings, ctl, true, true, mr5);
+ set_lpddr4_ca_odt(&dram->chan[channel], timings, ctl, true, true, mr5);
/*
* if phy_sw_master_mode_X not bypass mode,
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 87/92] ram: rk3399: Set lpddr4 MR3
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:51 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Set MR3 based identified controller in lpddr4
as part of LPDDR set rate initialization phase.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 48 +++++++++++++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 2c02c51fdf..f1fb16c130 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1949,6 +1949,53 @@ static void set_lpddr4_ca_odt(const struct chan_info *chan,
}
}
+static void set_lpddr4_MR3(const struct chan_info *chan,
+ struct rk3399_sdram_params *params, u32 ctl,
+ bool ctl_phy_reg, u32 mr5)
+{
+ u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg);
+ u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg);
+ struct io_setting *io;
+ u32 reg_value;
+
+ io = lpddr4_get_io_settings(params, mr5);
+
+ reg_value = ((io->pdds << 3) | 1);
+
+ switch (ctl) {
+ case 0:
+ clrsetbits_le32(&denali_ctl[138], 0xFFFF, reg_value);
+ clrsetbits_le32(&denali_ctl[152], 0xFFFF, reg_value);
+
+ clrsetbits_le32(&denali_pi[131], 0xFFFF << 16, reg_value << 16);
+ clrsetbits_le32(&denali_pi[139], 0xFFFF, reg_value);
+ clrsetbits_le32(&denali_pi[146], 0xFFFF << 16, reg_value << 16);
+ clrsetbits_le32(&denali_pi[154], 0xFFFF, reg_value);
+ break;
+ case 1:
+ clrsetbits_le32(&denali_ctl[138], 0xFFFF << 16,
+ reg_value << 16);
+ clrsetbits_le32(&denali_ctl[152], 0xFFFF << 16,
+ reg_value << 16);
+
+ clrsetbits_le32(&denali_pi[129], 0xFFFF, reg_value);
+ clrsetbits_le32(&denali_pi[136], 0xFFFF << 16, reg_value << 16);
+ clrsetbits_le32(&denali_pi[144], 0xFFFF, reg_value);
+ clrsetbits_le32(&denali_pi[151], 0xFFFF << 16, reg_value << 16);
+ break;
+ case 2:
+ default:
+ clrsetbits_le32(&denali_ctl[139], 0xFFFF, reg_value);
+ clrsetbits_le32(&denali_ctl[153], 0xFFFF, reg_value);
+
+ clrsetbits_le32(&denali_pi[126], 0xFFFF << 16, reg_value << 16);
+ clrsetbits_le32(&denali_pi[134], 0xFFFF, reg_value);
+ clrsetbits_le32(&denali_pi[141], 0xFFFF << 16, reg_value << 16);
+ clrsetbits_le32(&denali_pi[149], 0xFFFF, reg_value);
+ break;
+ }
+}
+
static void lpddr4_copy_phy(struct dram_info *dram,
struct rk3399_sdram_params *params, u32 phy,
struct rk3399_sdram_params *timings,
@@ -2197,6 +2244,7 @@ static void lpddr4_copy_phy(struct dram_info *dram,
ctl = lpddr4_get_ctl(timings, phy);
set_lpddr4_dq_odt(&dram->chan[channel], timings, ctl, true, true, mr5);
set_lpddr4_ca_odt(&dram->chan[channel], timings, ctl, true, true, mr5);
+ set_lpddr4_MR3(&dram->chan[channel], timings, ctl, true, mr5);
/*
* if phy_sw_master_mode_X not bypass mode,
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 87/92] ram: rk3399: Set lpddr4 MR3
@ 2019-06-11 14:51 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: u-boot
Set MR3 based identified controller in lpddr4
as part of LPDDR set rate initialization phase.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 48 +++++++++++++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 2c02c51fdf..f1fb16c130 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1949,6 +1949,53 @@ static void set_lpddr4_ca_odt(const struct chan_info *chan,
}
}
+static void set_lpddr4_MR3(const struct chan_info *chan,
+ struct rk3399_sdram_params *params, u32 ctl,
+ bool ctl_phy_reg, u32 mr5)
+{
+ u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg);
+ u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg);
+ struct io_setting *io;
+ u32 reg_value;
+
+ io = lpddr4_get_io_settings(params, mr5);
+
+ reg_value = ((io->pdds << 3) | 1);
+
+ switch (ctl) {
+ case 0:
+ clrsetbits_le32(&denali_ctl[138], 0xFFFF, reg_value);
+ clrsetbits_le32(&denali_ctl[152], 0xFFFF, reg_value);
+
+ clrsetbits_le32(&denali_pi[131], 0xFFFF << 16, reg_value << 16);
+ clrsetbits_le32(&denali_pi[139], 0xFFFF, reg_value);
+ clrsetbits_le32(&denali_pi[146], 0xFFFF << 16, reg_value << 16);
+ clrsetbits_le32(&denali_pi[154], 0xFFFF, reg_value);
+ break;
+ case 1:
+ clrsetbits_le32(&denali_ctl[138], 0xFFFF << 16,
+ reg_value << 16);
+ clrsetbits_le32(&denali_ctl[152], 0xFFFF << 16,
+ reg_value << 16);
+
+ clrsetbits_le32(&denali_pi[129], 0xFFFF, reg_value);
+ clrsetbits_le32(&denali_pi[136], 0xFFFF << 16, reg_value << 16);
+ clrsetbits_le32(&denali_pi[144], 0xFFFF, reg_value);
+ clrsetbits_le32(&denali_pi[151], 0xFFFF << 16, reg_value << 16);
+ break;
+ case 2:
+ default:
+ clrsetbits_le32(&denali_ctl[139], 0xFFFF, reg_value);
+ clrsetbits_le32(&denali_ctl[153], 0xFFFF, reg_value);
+
+ clrsetbits_le32(&denali_pi[126], 0xFFFF << 16, reg_value << 16);
+ clrsetbits_le32(&denali_pi[134], 0xFFFF, reg_value);
+ clrsetbits_le32(&denali_pi[141], 0xFFFF << 16, reg_value << 16);
+ clrsetbits_le32(&denali_pi[149], 0xFFFF, reg_value);
+ break;
+ }
+}
+
static void lpddr4_copy_phy(struct dram_info *dram,
struct rk3399_sdram_params *params, u32 phy,
struct rk3399_sdram_params *timings,
@@ -2197,6 +2244,7 @@ static void lpddr4_copy_phy(struct dram_info *dram,
ctl = lpddr4_get_ctl(timings, phy);
set_lpddr4_dq_odt(&dram->chan[channel], timings, ctl, true, true, mr5);
set_lpddr4_ca_odt(&dram->chan[channel], timings, ctl, true, true, mr5);
+ set_lpddr4_MR3(&dram->chan[channel], timings, ctl, true, mr5);
/*
* if phy_sw_master_mode_X not bypass mode,
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 88/92] ram: rk3399: Set lpddr4 MR12
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:51 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Set MR12 based identified controller in lpddr4
as part of LPDDR set rate initialization phase.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 50 +++++++++++++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index f1fb16c130..38fc8ffe63 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1996,6 +1996,55 @@ static void set_lpddr4_MR3(const struct chan_info *chan,
}
}
+static void set_lpddr4_MR12(const struct chan_info *chan,
+ struct rk3399_sdram_params *params, u32 ctl,
+ bool ctl_phy_reg, u32 mr5)
+{
+ u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg);
+ u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg);
+ struct io_setting *io;
+ u32 reg_value;
+
+ io = lpddr4_get_io_settings(params, mr5);
+
+ reg_value = io->ca_vref;
+
+ switch (ctl) {
+ case 0:
+ clrsetbits_le32(&denali_ctl[140], 0xFFFF << 16,
+ reg_value << 16);
+ clrsetbits_le32(&denali_ctl[154], 0xFFFF << 16,
+ reg_value << 16);
+
+ clrsetbits_le32(&denali_pi[132], 0xFF << 8, reg_value << 8);
+ clrsetbits_le32(&denali_pi[139], 0xFF << 24, reg_value << 24);
+ clrsetbits_le32(&denali_pi[147], 0xFF << 8, reg_value << 8);
+ clrsetbits_le32(&denali_pi[154], 0xFF << 24, reg_value << 24);
+ break;
+ case 1:
+ clrsetbits_le32(&denali_ctl[141], 0xFFFF, reg_value);
+ clrsetbits_le32(&denali_ctl[155], 0xFFFF, reg_value);
+
+ clrsetbits_le32(&denali_pi[129], 0xFF << 24, reg_value << 24);
+ clrsetbits_le32(&denali_pi[137], 0xFF << 8, reg_value << 8);
+ clrsetbits_le32(&denali_pi[144], 0xFF << 24, reg_value << 24);
+ clrsetbits_le32(&denali_pi[152], 0xFF << 8, reg_value << 8);
+ break;
+ case 2:
+ default:
+ clrsetbits_le32(&denali_ctl[141], 0xFFFF << 16,
+ reg_value << 16);
+ clrsetbits_le32(&denali_ctl[155], 0xFFFF << 16,
+ reg_value << 16);
+
+ clrsetbits_le32(&denali_pi[127], 0xFF << 8, reg_value << 8);
+ clrsetbits_le32(&denali_pi[134], 0xFF << 24, reg_value << 24);
+ clrsetbits_le32(&denali_pi[142], 0xFF << 8, reg_value << 8);
+ clrsetbits_le32(&denali_pi[149], 0xFF << 24, reg_value << 24);
+ break;
+ }
+}
+
static void lpddr4_copy_phy(struct dram_info *dram,
struct rk3399_sdram_params *params, u32 phy,
struct rk3399_sdram_params *timings,
@@ -2245,6 +2294,7 @@ static void lpddr4_copy_phy(struct dram_info *dram,
set_lpddr4_dq_odt(&dram->chan[channel], timings, ctl, true, true, mr5);
set_lpddr4_ca_odt(&dram->chan[channel], timings, ctl, true, true, mr5);
set_lpddr4_MR3(&dram->chan[channel], timings, ctl, true, mr5);
+ set_lpddr4_MR12(&dram->chan[channel], timings, ctl, true, mr5);
/*
* if phy_sw_master_mode_X not bypass mode,
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 88/92] ram: rk3399: Set lpddr4 MR12
@ 2019-06-11 14:51 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: u-boot
Set MR12 based identified controller in lpddr4
as part of LPDDR set rate initialization phase.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 50 +++++++++++++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index f1fb16c130..38fc8ffe63 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1996,6 +1996,55 @@ static void set_lpddr4_MR3(const struct chan_info *chan,
}
}
+static void set_lpddr4_MR12(const struct chan_info *chan,
+ struct rk3399_sdram_params *params, u32 ctl,
+ bool ctl_phy_reg, u32 mr5)
+{
+ u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg);
+ u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg);
+ struct io_setting *io;
+ u32 reg_value;
+
+ io = lpddr4_get_io_settings(params, mr5);
+
+ reg_value = io->ca_vref;
+
+ switch (ctl) {
+ case 0:
+ clrsetbits_le32(&denali_ctl[140], 0xFFFF << 16,
+ reg_value << 16);
+ clrsetbits_le32(&denali_ctl[154], 0xFFFF << 16,
+ reg_value << 16);
+
+ clrsetbits_le32(&denali_pi[132], 0xFF << 8, reg_value << 8);
+ clrsetbits_le32(&denali_pi[139], 0xFF << 24, reg_value << 24);
+ clrsetbits_le32(&denali_pi[147], 0xFF << 8, reg_value << 8);
+ clrsetbits_le32(&denali_pi[154], 0xFF << 24, reg_value << 24);
+ break;
+ case 1:
+ clrsetbits_le32(&denali_ctl[141], 0xFFFF, reg_value);
+ clrsetbits_le32(&denali_ctl[155], 0xFFFF, reg_value);
+
+ clrsetbits_le32(&denali_pi[129], 0xFF << 24, reg_value << 24);
+ clrsetbits_le32(&denali_pi[137], 0xFF << 8, reg_value << 8);
+ clrsetbits_le32(&denali_pi[144], 0xFF << 24, reg_value << 24);
+ clrsetbits_le32(&denali_pi[152], 0xFF << 8, reg_value << 8);
+ break;
+ case 2:
+ default:
+ clrsetbits_le32(&denali_ctl[141], 0xFFFF << 16,
+ reg_value << 16);
+ clrsetbits_le32(&denali_ctl[155], 0xFFFF << 16,
+ reg_value << 16);
+
+ clrsetbits_le32(&denali_pi[127], 0xFF << 8, reg_value << 8);
+ clrsetbits_le32(&denali_pi[134], 0xFF << 24, reg_value << 24);
+ clrsetbits_le32(&denali_pi[142], 0xFF << 8, reg_value << 8);
+ clrsetbits_le32(&denali_pi[149], 0xFF << 24, reg_value << 24);
+ break;
+ }
+}
+
static void lpddr4_copy_phy(struct dram_info *dram,
struct rk3399_sdram_params *params, u32 phy,
struct rk3399_sdram_params *timings,
@@ -2245,6 +2294,7 @@ static void lpddr4_copy_phy(struct dram_info *dram,
set_lpddr4_dq_odt(&dram->chan[channel], timings, ctl, true, true, mr5);
set_lpddr4_ca_odt(&dram->chan[channel], timings, ctl, true, true, mr5);
set_lpddr4_MR3(&dram->chan[channel], timings, ctl, true, mr5);
+ set_lpddr4_MR12(&dram->chan[channel], timings, ctl, true, mr5);
/*
* if phy_sw_master_mode_X not bypass mode,
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 89/92] ram: rk3399: Set lpddr4 MR14
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:51 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Set MR14 based identified controller in lpddr4
as part of LPDDR set rate initialization phase.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 50 +++++++++++++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 38fc8ffe63..859f26462d 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -2045,6 +2045,55 @@ static void set_lpddr4_MR12(const struct chan_info *chan,
}
}
+static void set_lpddr4_MR14(const struct chan_info *chan,
+ struct rk3399_sdram_params *params, u32 ctl,
+ bool ctl_phy_reg, u32 mr5)
+{
+ u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg);
+ u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg);
+ struct io_setting *io;
+ u32 reg_value;
+
+ io = lpddr4_get_io_settings(params, mr5);
+
+ reg_value = io->dq_vref;
+
+ switch (ctl) {
+ case 0:
+ clrsetbits_le32(&denali_ctl[142], 0xFFFF << 16,
+ reg_value << 16);
+ clrsetbits_le32(&denali_ctl[156], 0xFFFF << 16,
+ reg_value << 16);
+
+ clrsetbits_le32(&denali_pi[132], 0xFF << 16, reg_value << 16);
+ clrsetbits_le32(&denali_pi[140], 0xFF << 0, reg_value << 0);
+ clrsetbits_le32(&denali_pi[147], 0xFF << 16, reg_value << 16);
+ clrsetbits_le32(&denali_pi[155], 0xFF << 0, reg_value << 0);
+ break;
+ case 1:
+ clrsetbits_le32(&denali_ctl[143], 0xFFFF, reg_value);
+ clrsetbits_le32(&denali_ctl[157], 0xFFFF, reg_value);
+
+ clrsetbits_le32(&denali_pi[130], 0xFF << 0, reg_value << 0);
+ clrsetbits_le32(&denali_pi[137], 0xFF << 16, reg_value << 16);
+ clrsetbits_le32(&denali_pi[145], 0xFF << 0, reg_value << 0);
+ clrsetbits_le32(&denali_pi[152], 0xFF << 16, reg_value << 16);
+ break;
+ case 2:
+ default:
+ clrsetbits_le32(&denali_ctl[143], 0xFFFF << 16,
+ reg_value << 16);
+ clrsetbits_le32(&denali_ctl[157], 0xFFFF << 16,
+ reg_value << 16);
+
+ clrsetbits_le32(&denali_pi[127], 0xFF << 16, reg_value << 16);
+ clrsetbits_le32(&denali_pi[135], 0xFF << 0, reg_value << 0);
+ clrsetbits_le32(&denali_pi[142], 0xFF << 16, reg_value << 16);
+ clrsetbits_le32(&denali_pi[150], 0xFF << 0, reg_value << 0);
+ break;
+ }
+}
+
static void lpddr4_copy_phy(struct dram_info *dram,
struct rk3399_sdram_params *params, u32 phy,
struct rk3399_sdram_params *timings,
@@ -2295,6 +2344,7 @@ static void lpddr4_copy_phy(struct dram_info *dram,
set_lpddr4_ca_odt(&dram->chan[channel], timings, ctl, true, true, mr5);
set_lpddr4_MR3(&dram->chan[channel], timings, ctl, true, mr5);
set_lpddr4_MR12(&dram->chan[channel], timings, ctl, true, mr5);
+ set_lpddr4_MR14(&dram->chan[channel], timings, ctl, true, mr5);
/*
* if phy_sw_master_mode_X not bypass mode,
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 89/92] ram: rk3399: Set lpddr4 MR14
@ 2019-06-11 14:51 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: u-boot
Set MR14 based identified controller in lpddr4
as part of LPDDR set rate initialization phase.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 50 +++++++++++++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 38fc8ffe63..859f26462d 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -2045,6 +2045,55 @@ static void set_lpddr4_MR12(const struct chan_info *chan,
}
}
+static void set_lpddr4_MR14(const struct chan_info *chan,
+ struct rk3399_sdram_params *params, u32 ctl,
+ bool ctl_phy_reg, u32 mr5)
+{
+ u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg);
+ u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg);
+ struct io_setting *io;
+ u32 reg_value;
+
+ io = lpddr4_get_io_settings(params, mr5);
+
+ reg_value = io->dq_vref;
+
+ switch (ctl) {
+ case 0:
+ clrsetbits_le32(&denali_ctl[142], 0xFFFF << 16,
+ reg_value << 16);
+ clrsetbits_le32(&denali_ctl[156], 0xFFFF << 16,
+ reg_value << 16);
+
+ clrsetbits_le32(&denali_pi[132], 0xFF << 16, reg_value << 16);
+ clrsetbits_le32(&denali_pi[140], 0xFF << 0, reg_value << 0);
+ clrsetbits_le32(&denali_pi[147], 0xFF << 16, reg_value << 16);
+ clrsetbits_le32(&denali_pi[155], 0xFF << 0, reg_value << 0);
+ break;
+ case 1:
+ clrsetbits_le32(&denali_ctl[143], 0xFFFF, reg_value);
+ clrsetbits_le32(&denali_ctl[157], 0xFFFF, reg_value);
+
+ clrsetbits_le32(&denali_pi[130], 0xFF << 0, reg_value << 0);
+ clrsetbits_le32(&denali_pi[137], 0xFF << 16, reg_value << 16);
+ clrsetbits_le32(&denali_pi[145], 0xFF << 0, reg_value << 0);
+ clrsetbits_le32(&denali_pi[152], 0xFF << 16, reg_value << 16);
+ break;
+ case 2:
+ default:
+ clrsetbits_le32(&denali_ctl[143], 0xFFFF << 16,
+ reg_value << 16);
+ clrsetbits_le32(&denali_ctl[157], 0xFFFF << 16,
+ reg_value << 16);
+
+ clrsetbits_le32(&denali_pi[127], 0xFF << 16, reg_value << 16);
+ clrsetbits_le32(&denali_pi[135], 0xFF << 0, reg_value << 0);
+ clrsetbits_le32(&denali_pi[142], 0xFF << 16, reg_value << 16);
+ clrsetbits_le32(&denali_pi[150], 0xFF << 0, reg_value << 0);
+ break;
+ }
+}
+
static void lpddr4_copy_phy(struct dram_info *dram,
struct rk3399_sdram_params *params, u32 phy,
struct rk3399_sdram_params *timings,
@@ -2295,6 +2344,7 @@ static void lpddr4_copy_phy(struct dram_info *dram,
set_lpddr4_ca_odt(&dram->chan[channel], timings, ctl, true, true, mr5);
set_lpddr4_MR3(&dram->chan[channel], timings, ctl, true, mr5);
set_lpddr4_MR12(&dram->chan[channel], timings, ctl, true, mr5);
+ set_lpddr4_MR14(&dram->chan[channel], timings, ctl, true, mr5);
/*
* if phy_sw_master_mode_X not bypass mode,
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 90/92] rockchip: dts: rk3399: Add LPDDR4-100 timings
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:51 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Add sdram timings for LPDDR4-100 via rk3399-sdram-lpddr4-100.dtsi file.
all timings are dumped from rkbin/bin/rk33/rk3399_ddr_800MHz_v1.20.bin
Associated LPDDR4 board -u-boot.dtsi can include this to make these
timings available during SPL or TPL stages.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi | 1537 +++++++++++++++++++++
1 file changed, 1537 insertions(+)
create mode 100644 arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi
diff --git a/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi b/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi
new file mode 100644
index 0000000000..4a4414a960
--- /dev/null
+++ b/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi
@@ -0,0 +1,1537 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ * (C) Copyright 2019 Amarula Solutions.
+ * Author: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
+ */
+
+&dmc {
+ rockchip,sdram-params = <
+ 0x2
+ 0xa
+ 0x3
+ 0x2
+ 0x1
+ 0x0
+ 0xf
+ 0xf
+ 1
+ 0x80241d22
+ 0x15050f08
+ 0x00000602
+ 0x00002122
+ 0x0000004c
+ 0x00000000
+ 0x2
+ 0xa
+ 0x3
+ 0x2
+ 0x1
+ 0x0
+ 0xf
+ 0xf
+ 1
+ 0x80241d22
+ 0x15050f08
+ 0x00000602
+ 0x00002122
+ 0x0000004c
+ 0x00000000
+ 50
+ 7
+ 2
+ 13
+ 1
+ 0x00000b00
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00013880
+ 0x000c3500
+ 0x00000005
+ 0x00000320
+ 0x00027100
+ 0x00186a00
+ 0x00000005
+ 0x00000640
+ 0x00002710
+ 0x000186a0
+ 0x00000005
+ 0x01000064
+ 0x00000000
+ 0x02020101
+ 0x00000102
+ 0x00000050
+ 0x000000c8
+ 0x00000000
+ 0x06140000
+ 0x00081c00
+ 0x0400040c
+ 0x19042008
+ 0x10080a11
+ 0x22310800
+ 0x00200f0a
+ 0x0a030704
+ 0x08000204
+ 0x00000a0a
+ 0x04006db0
+ 0x0a0a0804
+ 0x0600db60
+ 0x0a0a0806
+ 0x04000db6
+ 0x02030404
+ 0x0f0a0800
+ 0x08040411
+ 0x1400640a
+ 0x02010a0a
+ 0x00010001
+ 0x04082012
+ 0x00041109
+ 0x00000000
+ 0x03010000
+ 0x06100048
+ 0x0c280090
+ 0x00bb0009
+ 0x00000000
+ 0x00060005
+ 0x000a0005
+ 0x000a0014
+ 0x01000000
+ 0x030a0000
+ 0x0c000002
+ 0x00000103
+ 0x0005030a
+ 0x00060037
+ 0x0005006e
+ 0x05050007
+ 0x03030605
+ 0x06050301
+ 0x06030c05
+ 0x05050302
+ 0x03030305
+ 0x00000301
+ 0x00000301
+ 0x00000001
+ 0x00000000
+ 0x00000000
+ 0x01000000
+ 0x80104002
+ 0x00040003
+ 0x00040005
+ 0x00030000
+ 0x00050004
+ 0x00000004
+ 0x00040003
+ 0x00040005
+ 0x18400000
+ 0x00000c20
+ 0x185030a0
+ 0x02ec0000
+ 0x00000176
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x06030300
+ 0x00030303
+ 0x02030200
+ 0x00040703
+ 0x03020302
+ 0x02000407
+ 0x07030203
+ 0x00030f04
+ 0x00070004
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00010000
+ 0x20040020
+ 0x00200400
+ 0x01000400
+ 0x00000b80
+ 0x00000000
+ 0x00000001
+ 0x00000002
+ 0x0000000e
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00500000
+ 0x00640028
+ 0x00640404
+ 0x005000a0
+ 0x060600c8
+ 0x000a00c8
+ 0x000d0005
+ 0x000d0404
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x001400a3
+ 0x00e30009
+ 0x00120024
+ 0x00040063
+ 0x00000000
+ 0x00310031
+ 0x00000031
+ 0x004d0000
+ 0x004d004d
+ 0x004d0000
+ 0x004d004d
+ 0x00010101
+ 0x00000000
+ 0x00000000
+ 0x001400a3
+ 0x00e30009
+ 0x00120024
+ 0x00040063
+ 0x00000000
+ 0x00310031
+ 0x00000031
+ 0x004d0000
+ 0x004d004d
+ 0x004d0000
+ 0x004d004d
+ 0x00010101
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000001
+ 0x00000000
+ 0x18151100
+ 0x0000000c
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00020003
+ 0x00400100
+ 0x000c0190
+ 0x01000200
+ 0x03200040
+ 0x00020018
+ 0x00400100
+ 0x00080032
+ 0x00140000
+ 0x00030028
+ 0x01010100
+ 0x02000202
+ 0x0b000002
+ 0x01000f0f
+ 0x00000000
+ 0x00000000
+ 0x00010003
+ 0x00000c03
+ 0x00040101
+ 0x04010100
+ 0x01000000
+ 0x02010000
+ 0x00000001
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00010000
+ 0x00000001
+ 0x01010001
+ 0x05040001
+ 0x040a0703
+ 0x02080808
+ 0x020e000a
+ 0x020f010b
+ 0x000d0008
+ 0x00080b0a
+ 0x03000200
+ 0x00000100
+ 0x00000000
+ 0x00000000
+ 0x0d000001
+ 0x00000028
+ 0x00010000
+ 0x00000003
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
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+ 0xe4000000
+ 0x00000000
+ 0x00000000
+ 0x01010000
+ 0x00000000
+ >;
+};
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 90/92] rockchip: dts: rk3399: Add LPDDR4-100 timings
@ 2019-06-11 14:51 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: u-boot
Add sdram timings for LPDDR4-100 via rk3399-sdram-lpddr4-100.dtsi file.
all timings are dumped from rkbin/bin/rk33/rk3399_ddr_800MHz_v1.20.bin
Associated LPDDR4 board -u-boot.dtsi can include this to make these
timings available during SPL or TPL stages.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi | 1537 +++++++++++++++++++++
1 file changed, 1537 insertions(+)
create mode 100644 arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi
diff --git a/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi b/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi
new file mode 100644
index 0000000000..4a4414a960
--- /dev/null
+++ b/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi
@@ -0,0 +1,1537 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ * (C) Copyright 2019 Amarula Solutions.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+&dmc {
+ rockchip,sdram-params = <
+ 0x2
+ 0xa
+ 0x3
+ 0x2
+ 0x1
+ 0x0
+ 0xf
+ 0xf
+ 1
+ 0x80241d22
+ 0x15050f08
+ 0x00000602
+ 0x00002122
+ 0x0000004c
+ 0x00000000
+ 0x2
+ 0xa
+ 0x3
+ 0x2
+ 0x1
+ 0x0
+ 0xf
+ 0xf
+ 1
+ 0x80241d22
+ 0x15050f08
+ 0x00000602
+ 0x00002122
+ 0x0000004c
+ 0x00000000
+ 50
+ 7
+ 2
+ 13
+ 1
+ 0x00000b00
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00013880
+ 0x000c3500
+ 0x00000005
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+ 0x00027100
+ 0x00186a00
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+ 0x00002710
+ 0x000186a0
+ 0x00000005
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+ 0x00000102
+ 0x00000050
+ 0x000000c8
+ 0x00000000
+ 0x06140000
+ 0x00081c00
+ 0x0400040c
+ 0x19042008
+ 0x10080a11
+ 0x22310800
+ 0x00200f0a
+ 0x0a030704
+ 0x08000204
+ 0x00000a0a
+ 0x04006db0
+ 0x0a0a0804
+ 0x0600db60
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+ 0xe4000000
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+ 0x01010000
+ 0x00000000
+ >;
+};
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 91/92] rockchip: dts: rk3399: rockpro64: Use LPDDR4-100 dtsi
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:51 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Use LPDDR4-100 sdram timings dtsi for Rockpro64 board.
All these timings are processed during TPL stage of rockpro64 board,
bootchain. This make TPL would replace rockchip in house rkbin in
current bootchain.
Bootchain after and before this change:
TPL -> SPL -> U-Boot proper
rkbin -> SPL -> U-Boot proper
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
index 7bddc3acdb..dbfa4ba9f8 100644
--- a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
@@ -4,3 +4,4 @@
*/
#include "rk3399-u-boot.dtsi"
+#include "rk3399-sdram-lpddr4-100.dtsi"
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 91/92] rockchip: dts: rk3399: rockpro64: Use LPDDR4-100 dtsi
@ 2019-06-11 14:51 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: u-boot
Use LPDDR4-100 sdram timings dtsi for Rockpro64 board.
All these timings are processed during TPL stage of rockpro64 board,
bootchain. This make TPL would replace rockchip in house rkbin in
current bootchain.
Bootchain after and before this change:
TPL -> SPL -> U-Boot proper
rkbin -> SPL -> U-Boot proper
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
index 7bddc3acdb..dbfa4ba9f8 100644
--- a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
@@ -4,3 +4,4 @@
*/
#include "rk3399-u-boot.dtsi"
+#include "rk3399-sdram-lpddr4-100.dtsi"
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [PATCH 92/92] rockchip: dts: rk3399: rock-pi-4: Use LPDDR4-100 dtsi
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:51 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang, YouMin Chen,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w
Use LPDDR4-100 sdram timings dtsi for RockPI-4 board.
All these timings are processed during TPL stage of rock-pi-4 board,
bootchain. This make TPL would replace rockchip in house rkbin in
current bootchain.
Bootchain after and before this change:
TPL -> SPL -> U-Boot proper
rkbin -> SPL -> U-Boot proper
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi b/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
index 7bddc3acdb..dbfa4ba9f8 100644
--- a/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
@@ -4,3 +4,4 @@
*/
#include "rk3399-u-boot.dtsi"
+#include "rk3399-sdram-lpddr4-100.dtsi"
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 92/92] rockchip: dts: rk3399: rock-pi-4: Use LPDDR4-100 dtsi
@ 2019-06-11 14:51 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 14:51 UTC (permalink / raw)
To: u-boot
Use LPDDR4-100 sdram timings dtsi for RockPI-4 board.
All these timings are processed during TPL stage of rock-pi-4 board,
bootchain. This make TPL would replace rockchip in house rkbin in
current bootchain.
Bootchain after and before this change:
TPL -> SPL -> U-Boot proper
rkbin -> SPL -> U-Boot proper
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi b/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
index 7bddc3acdb..dbfa4ba9f8 100644
--- a/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
@@ -4,3 +4,4 @@
*/
#include "rk3399-u-boot.dtsi"
+#include "rk3399-sdram-lpddr4-100.dtsi"
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 204+ messages in thread
* Re: [PATCH 00/92] ram: rk3399: Add LPDDR4 support
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-11 14:53 ` Philipp Tomsich
-1 siblings, 0 replies; 204+ messages in thread
From: Philipp Tomsich @ 2019-06-11 14:53 UTC (permalink / raw)
To: Jagan Teki
Cc: YouMin Chen, u-boot-0aAXYlwwYIKGBzrmiIFOJg, Simon Glass,
gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w, Kever Yang,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/
> On 11.06.2019, at 16:50, Jagan Teki <jagan@amarulasolutions.com> wrote:
>
> Yes, it can be possible to break this series into multiple sub series
> but idea here is to mark all the required changes to support LPDDR4
> in rk3399 in one set. if required we can break it from next versions.
>
> This is the initial set for supporting LPDDR4 with associated
> features.
>
> Thanks to
> - YouMin Chen
> - Akash Gajjar
> - Kever Yang
> for supporting all the help on this work.
>
> On summary this series support
> - Code warning and fixes
> - rank detection, this would required to probe single channel
> sdram configured in NanoPI-NEO4
> - LPDDR4 support, tested in Rockpro64 and Rock-PI-4
>
> patch 0001 - 0033: fix code warnings, prints, new macros
>
> patch 0034 - 0051: rank detection, sdram debug code
>
> patch 0052: Use DDR3-1800 on NanoPI-NEO4
>
> patch 0053 - 0089: lpddr4 support
>
> patch 0090: LPDDR4-100 timings
>
> patch 0091: Use LPDDR4-100 on Rockpro64
>
> patch 0092: Use LPDDR4-100 on Rock-PI 4
>
> Note: Puma rk3399 has SPL size overflow, better to enable TPL
> for this board.
We need to keep Puma on a SPL-only configuration for the time being.
Please make sure that the LPDDR4 code is an optional feature that does not
increase the DRAM-driver size for boards that don’t need/want it.
Thanks,
Philipp.
>
> Any inputs?
> Jagan.
>
> Jagan Teki (92):
> ram: rk3399: Fix code warnings
> ram: rk3399: Add space between string with format specifier
> ram: rk3399: Add proper spaces in data training
> ram: rk3399: Handle data training return types
> ram: rk3399: Order include files
> ram: rk3399: Move macro after include files
> ram: rk3399: Clear PI_175 interrupts in data training
> ram: rk3399: Use rank mask in ca data training
> ram: rk3399: Use rank mask in wdql data training
> ram: rk3399: Add ddrtype enc macro
> ram: rk3399: Add channel number encoder macro
> ram: rk3399: Add row_3_4 enc macro
> ram: rk3399: Add chipinfo macro
> ram: rk3399: Add rank enc macro
> ram: rk3399: Add column enc macro
> ram: rk3399: Add bk enc macro
> ram: rk3399: Add dbw enc macro
> ram: rk3399: Add cs0_rw macro
> ram: rk3399: Add cs1_rw macro
> ram: rk3399: Add bw enc macro
> ram: rk3399: Rename sys_reg with sys_reg2
> ram: rk3399: Update cs0_row to use sys_reg3
> ram: rk3399: Update cs1_row to use sys_reg3
> ram: rk3399: Add cs1_col enc macro
> ram: rk3399: Add ddr version enc macro
> ram: rk3399: Add ddrtimingC0
> ram: rk3399: Add DdrMode
> ram: rk3399: Handle pctl_cfg return type
> ram: rk3399: s/tsel_wr_select_n/tsel_wr_select_dq_n
> ram: rk3399: s/tsel_wr_select_p/tsel_wr_select_dq_p
> ram: rk3399: s/ca_tsel_wr_select_n/tsel_wr_select_ca_n
> ram: rk3399: s/ca_tsel_wr_select_p/tsel_wr_select_ca_p
> ram: rk3399: Order tsel variables
> ram: rk3399: Add phy pctrl reset support
> ram: rk3399: Move pwrup_srefresh_exit to dram_info
> ram: rk3399: Add pctl start support
> ram: rockchip: rk3399: Add cap_info structure
> ram: rk3399: s/rk3399_base_params/sdram_base_params
> ram: rk3399: Move common sdram structures in common header
> arm: include: rockchip: Move dramtypes to common header
> arm: include: rockchip: Add DDR4 enum
> ram: rockchip: Add initial Kconfig
> debug_uart: Add printdec
> ram: rockchip: Add debug sdram driver
> ram: rockchip: debug: Add sdram_print_ddr_info
> ram: rockchip: debug: Get the cs capacity
> ram: rk3399: debug: Add sdram_print_stride
> ram: rk3399: Compute stride for 2 channels
> ram: rk3399: Compute stride for 1 channel a
> ram: rk3399: Add rank detection support
> ram: rk3399: Enable sdram debug functions
> rockchip: dts: rk3399: nanopi-neo4: Use DDR3-1866 dtsi
> clk: rockchip: rk3399: Fix check patch warnings and checks
> clk: rockchip: rk3399: Set 50MHz ddr clock
> clk: rockchip: rk3399: Set 400MHz ddr clock
> ram: rk3399: Add spaces in pctl_cfg
> ram: rk3399: Configure phy IO in ds odt
> ram: rk3399: Add lpddr4 rank mask for cs training
> ram: rk3399: Add lpddr4 rank mask for wdql training
> ram: rk3399: Move mode_sel assignment
> ram: rk3399: Don't wait for PLL lock in lpddr4
> ram: rk3399: Avoid two channel ZQ Cal Start at the same time
> ram: rk3399: Configure PHY_898, PHY_919 for lpddr4
> ram: rk3399: Configure BOOSTP_EN, BOOSTN_EN for lpddr4
> ram: rk3399: Configure SLEWP_EN, SLEWN_EN for lpddr4
> ram: rk3399: Configure PHY RX_CM_INPUT for lpddr4
> ram: rk3399: Map chipselect for lpddr4
> ram: rk3399: Configure tsel write ca for lpddr4
> ram: rk3399: Don't disable dfi dram clk for lpddr4, rank 1
> ram: rk3399: Add IO settings
> ram: sdram: Configure lpddr4 tsel rd, wr based on IO settings
> ram: rk3399: Add tsel control clock drive
> ram: rk3399: Configure soc odt support
> ram: rk3399: Get lpddr4 tsel_rd_en from io settings
> ram: rk3399: Update lpddr4 vref based on io settings
> ram: rk3399: Update lpddr4 mode_sel based on io settings
> ram: rk3399: Update lpddr4 vref_mode_ac
> ram: rk3399: Add LPPDR4 mr detection
> arm: include: rockchip: Add rk3399 pmu file
> rockchip: rk3399: syscon: Add pmu support
> rockchip: dts: rk3399: Add u-boot,dm-pre-reloc for pmu
> ram: rk3399: Add LPPDDR4-400 timings inc
> ram: rk3399: Add LPPDDR4-800 timings inc
> ram: rk3399: Add lpddr4 set rate support
> ram: rk3399: Set lpddr4 dq odt
> ram: rk3399: Set lpddr4 ca odt
> ram: rk3399: Set lpddr4 MR3
> ram: rk3399: Set lpddr4 MR12
> ram: rk3399: Set lpddr4 MR14
> rockchip: dts: rk3399: Add LPDDR4-100 timings
> rockchip: dts: rk3399: rockpro64: Use LPDDR4-100 dtsi
> rockchip: dts: rk3399: rock-pi-4: Use LPDDR4-100 dtsi
>
> arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi | 1 +
> arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi | 1 +
> arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 1 +
> arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi | 1537 ++++++++++++
> arch/arm/dts/rk3399-u-boot.dtsi | 4 +
> .../include/asm/arch-rockchip/pmu_rk3399.h | 72 +
> arch/arm/include/asm/arch-rockchip/sdram.h | 6 -
> .../include/asm/arch-rockchip/sdram_common.h | 89 +
> .../include/asm/arch-rockchip/sdram_rk322x.h | 7 -
> .../include/asm/arch-rockchip/sdram_rk3399.h | 65 +-
> arch/arm/mach-rockchip/rk3399/syscon_rk3399.c | 8 +
> drivers/clk/rockchip/clk_rk3399.c | 76 +-
> drivers/ram/Kconfig | 1 +
> drivers/ram/rockchip/Kconfig | 26 +
> drivers/ram/rockchip/Makefile | 3 +-
> .../ram/rockchip/sdram-rk3399-lpddr4-400.inc | 1570 ++++++++++++
> .../ram/rockchip/sdram-rk3399-lpddr4-800.inc | 1570 ++++++++++++
> drivers/ram/rockchip/sdram_debug.c | 147 ++
> drivers/ram/rockchip/sdram_rk3399.c | 2176 ++++++++++++++---
> include/debug_uart.h | 19 +
> 20 files changed, 6964 insertions(+), 415 deletions(-)
> create mode 100644 arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi
> create mode 100644 arch/arm/include/asm/arch-rockchip/pmu_rk3399.h
> create mode 100644 drivers/ram/rockchip/Kconfig
> create mode 100644 drivers/ram/rockchip/sdram-rk3399-lpddr4-400.inc
> create mode 100644 drivers/ram/rockchip/sdram-rk3399-lpddr4-800.inc
> create mode 100644 drivers/ram/rockchip/sdram_debug.c
>
> --
> 2.18.0.321.gffc6fa0e3
>
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 00/92] ram: rk3399: Add LPDDR4 support
@ 2019-06-11 14:53 ` Philipp Tomsich
0 siblings, 0 replies; 204+ messages in thread
From: Philipp Tomsich @ 2019-06-11 14:53 UTC (permalink / raw)
To: u-boot
> On 11.06.2019, at 16:50, Jagan Teki <jagan@amarulasolutions.com> wrote:
>
> Yes, it can be possible to break this series into multiple sub series
> but idea here is to mark all the required changes to support LPDDR4
> in rk3399 in one set. if required we can break it from next versions.
>
> This is the initial set for supporting LPDDR4 with associated
> features.
>
> Thanks to
> - YouMin Chen
> - Akash Gajjar
> - Kever Yang
> for supporting all the help on this work.
>
> On summary this series support
> - Code warning and fixes
> - rank detection, this would required to probe single channel
> sdram configured in NanoPI-NEO4
> - LPDDR4 support, tested in Rockpro64 and Rock-PI-4
>
> patch 0001 - 0033: fix code warnings, prints, new macros
>
> patch 0034 - 0051: rank detection, sdram debug code
>
> patch 0052: Use DDR3-1800 on NanoPI-NEO4
>
> patch 0053 - 0089: lpddr4 support
>
> patch 0090: LPDDR4-100 timings
>
> patch 0091: Use LPDDR4-100 on Rockpro64
>
> patch 0092: Use LPDDR4-100 on Rock-PI 4
>
> Note: Puma rk3399 has SPL size overflow, better to enable TPL
> for this board.
We need to keep Puma on a SPL-only configuration for the time being.
Please make sure that the LPDDR4 code is an optional feature that does not
increase the DRAM-driver size for boards that don’t need/want it.
Thanks,
Philipp.
>
> Any inputs?
> Jagan.
>
> Jagan Teki (92):
> ram: rk3399: Fix code warnings
> ram: rk3399: Add space between string with format specifier
> ram: rk3399: Add proper spaces in data training
> ram: rk3399: Handle data training return types
> ram: rk3399: Order include files
> ram: rk3399: Move macro after include files
> ram: rk3399: Clear PI_175 interrupts in data training
> ram: rk3399: Use rank mask in ca data training
> ram: rk3399: Use rank mask in wdql data training
> ram: rk3399: Add ddrtype enc macro
> ram: rk3399: Add channel number encoder macro
> ram: rk3399: Add row_3_4 enc macro
> ram: rk3399: Add chipinfo macro
> ram: rk3399: Add rank enc macro
> ram: rk3399: Add column enc macro
> ram: rk3399: Add bk enc macro
> ram: rk3399: Add dbw enc macro
> ram: rk3399: Add cs0_rw macro
> ram: rk3399: Add cs1_rw macro
> ram: rk3399: Add bw enc macro
> ram: rk3399: Rename sys_reg with sys_reg2
> ram: rk3399: Update cs0_row to use sys_reg3
> ram: rk3399: Update cs1_row to use sys_reg3
> ram: rk3399: Add cs1_col enc macro
> ram: rk3399: Add ddr version enc macro
> ram: rk3399: Add ddrtimingC0
> ram: rk3399: Add DdrMode
> ram: rk3399: Handle pctl_cfg return type
> ram: rk3399: s/tsel_wr_select_n/tsel_wr_select_dq_n
> ram: rk3399: s/tsel_wr_select_p/tsel_wr_select_dq_p
> ram: rk3399: s/ca_tsel_wr_select_n/tsel_wr_select_ca_n
> ram: rk3399: s/ca_tsel_wr_select_p/tsel_wr_select_ca_p
> ram: rk3399: Order tsel variables
> ram: rk3399: Add phy pctrl reset support
> ram: rk3399: Move pwrup_srefresh_exit to dram_info
> ram: rk3399: Add pctl start support
> ram: rockchip: rk3399: Add cap_info structure
> ram: rk3399: s/rk3399_base_params/sdram_base_params
> ram: rk3399: Move common sdram structures in common header
> arm: include: rockchip: Move dramtypes to common header
> arm: include: rockchip: Add DDR4 enum
> ram: rockchip: Add initial Kconfig
> debug_uart: Add printdec
> ram: rockchip: Add debug sdram driver
> ram: rockchip: debug: Add sdram_print_ddr_info
> ram: rockchip: debug: Get the cs capacity
> ram: rk3399: debug: Add sdram_print_stride
> ram: rk3399: Compute stride for 2 channels
> ram: rk3399: Compute stride for 1 channel a
> ram: rk3399: Add rank detection support
> ram: rk3399: Enable sdram debug functions
> rockchip: dts: rk3399: nanopi-neo4: Use DDR3-1866 dtsi
> clk: rockchip: rk3399: Fix check patch warnings and checks
> clk: rockchip: rk3399: Set 50MHz ddr clock
> clk: rockchip: rk3399: Set 400MHz ddr clock
> ram: rk3399: Add spaces in pctl_cfg
> ram: rk3399: Configure phy IO in ds odt
> ram: rk3399: Add lpddr4 rank mask for cs training
> ram: rk3399: Add lpddr4 rank mask for wdql training
> ram: rk3399: Move mode_sel assignment
> ram: rk3399: Don't wait for PLL lock in lpddr4
> ram: rk3399: Avoid two channel ZQ Cal Start at the same time
> ram: rk3399: Configure PHY_898, PHY_919 for lpddr4
> ram: rk3399: Configure BOOSTP_EN, BOOSTN_EN for lpddr4
> ram: rk3399: Configure SLEWP_EN, SLEWN_EN for lpddr4
> ram: rk3399: Configure PHY RX_CM_INPUT for lpddr4
> ram: rk3399: Map chipselect for lpddr4
> ram: rk3399: Configure tsel write ca for lpddr4
> ram: rk3399: Don't disable dfi dram clk for lpddr4, rank 1
> ram: rk3399: Add IO settings
> ram: sdram: Configure lpddr4 tsel rd, wr based on IO settings
> ram: rk3399: Add tsel control clock drive
> ram: rk3399: Configure soc odt support
> ram: rk3399: Get lpddr4 tsel_rd_en from io settings
> ram: rk3399: Update lpddr4 vref based on io settings
> ram: rk3399: Update lpddr4 mode_sel based on io settings
> ram: rk3399: Update lpddr4 vref_mode_ac
> ram: rk3399: Add LPPDR4 mr detection
> arm: include: rockchip: Add rk3399 pmu file
> rockchip: rk3399: syscon: Add pmu support
> rockchip: dts: rk3399: Add u-boot,dm-pre-reloc for pmu
> ram: rk3399: Add LPPDDR4-400 timings inc
> ram: rk3399: Add LPPDDR4-800 timings inc
> ram: rk3399: Add lpddr4 set rate support
> ram: rk3399: Set lpddr4 dq odt
> ram: rk3399: Set lpddr4 ca odt
> ram: rk3399: Set lpddr4 MR3
> ram: rk3399: Set lpddr4 MR12
> ram: rk3399: Set lpddr4 MR14
> rockchip: dts: rk3399: Add LPDDR4-100 timings
> rockchip: dts: rk3399: rockpro64: Use LPDDR4-100 dtsi
> rockchip: dts: rk3399: rock-pi-4: Use LPDDR4-100 dtsi
>
> arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi | 1 +
> arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi | 1 +
> arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 1 +
> arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi | 1537 ++++++++++++
> arch/arm/dts/rk3399-u-boot.dtsi | 4 +
> .../include/asm/arch-rockchip/pmu_rk3399.h | 72 +
> arch/arm/include/asm/arch-rockchip/sdram.h | 6 -
> .../include/asm/arch-rockchip/sdram_common.h | 89 +
> .../include/asm/arch-rockchip/sdram_rk322x.h | 7 -
> .../include/asm/arch-rockchip/sdram_rk3399.h | 65 +-
> arch/arm/mach-rockchip/rk3399/syscon_rk3399.c | 8 +
> drivers/clk/rockchip/clk_rk3399.c | 76 +-
> drivers/ram/Kconfig | 1 +
> drivers/ram/rockchip/Kconfig | 26 +
> drivers/ram/rockchip/Makefile | 3 +-
> .../ram/rockchip/sdram-rk3399-lpddr4-400.inc | 1570 ++++++++++++
> .../ram/rockchip/sdram-rk3399-lpddr4-800.inc | 1570 ++++++++++++
> drivers/ram/rockchip/sdram_debug.c | 147 ++
> drivers/ram/rockchip/sdram_rk3399.c | 2176 ++++++++++++++---
> include/debug_uart.h | 19 +
> 20 files changed, 6964 insertions(+), 415 deletions(-)
> create mode 100644 arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi
> create mode 100644 arch/arm/include/asm/arch-rockchip/pmu_rk3399.h
> create mode 100644 drivers/ram/rockchip/Kconfig
> create mode 100644 drivers/ram/rockchip/sdram-rk3399-lpddr4-400.inc
> create mode 100644 drivers/ram/rockchip/sdram-rk3399-lpddr4-800.inc
> create mode 100644 drivers/ram/rockchip/sdram_debug.c
>
> --
> 2.18.0.321.gffc6fa0e3
>
^ permalink raw reply [flat|nested] 204+ messages in thread
* Re: [PATCH 00/92] ram: rk3399: Add LPDDR4 support
2019-06-11 14:53 ` [U-Boot] " Philipp Tomsich
@ 2019-06-11 15:03 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 15:03 UTC (permalink / raw)
To: Philipp Tomsich
Cc: YouMin Chen, U-Boot-Denx, Simon Glass, Akash Gajjar, Kever Yang,
open list:ARM/Rockchip SoC...,
linux-amarula
On Tue, Jun 11, 2019 at 8:23 PM Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
>
>
>
> > On 11.06.2019, at 16:50, Jagan Teki <jagan@amarulasolutions.com> wrote:
> >
> > Yes, it can be possible to break this series into multiple sub series
> > but idea here is to mark all the required changes to support LPDDR4
> > in rk3399 in one set. if required we can break it from next versions.
> >
> > This is the initial set for supporting LPDDR4 with associated
> > features.
> >
> > Thanks to
> > - YouMin Chen
> > - Akash Gajjar
> > - Kever Yang
> > for supporting all the help on this work.
> >
> > On summary this series support
> > - Code warning and fixes
> > - rank detection, this would required to probe single channel
> > sdram configured in NanoPI-NEO4
> > - LPDDR4 support, tested in Rockpro64 and Rock-PI-4
> >
> > patch 0001 - 0033: fix code warnings, prints, new macros
> >
> > patch 0034 - 0051: rank detection, sdram debug code
> >
> > patch 0052: Use DDR3-1800 on NanoPI-NEO4
> >
> > patch 0053 - 0089: lpddr4 support
> >
> > patch 0090: LPDDR4-100 timings
> >
> > patch 0091: Use LPDDR4-100 on Rockpro64
> >
> > patch 0092: Use LPDDR4-100 on Rock-PI 4
> >
> > Note: Puma rk3399 has SPL size overflow, better to enable TPL
> > for this board.
>
> We need to keep Puma on a SPL-only configuration for the time being.
> Please make sure that the LPDDR4 code is an optional feature that does not
> increase the DRAM-driver size for boards that don’t need/want it.
We have few boards do have TPL-runnable, would be any technical issue
to switch puma to TPL? because we have lpddr4 code part of existing
driver itself and it require extra ifdef to consider which indeed look
awful from code point-of-view.
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 00/92] ram: rk3399: Add LPDDR4 support
@ 2019-06-11 15:03 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-11 15:03 UTC (permalink / raw)
To: u-boot
On Tue, Jun 11, 2019 at 8:23 PM Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
>
>
>
> > On 11.06.2019, at 16:50, Jagan Teki <jagan@amarulasolutions.com> wrote:
> >
> > Yes, it can be possible to break this series into multiple sub series
> > but idea here is to mark all the required changes to support LPDDR4
> > in rk3399 in one set. if required we can break it from next versions.
> >
> > This is the initial set for supporting LPDDR4 with associated
> > features.
> >
> > Thanks to
> > - YouMin Chen
> > - Akash Gajjar
> > - Kever Yang
> > for supporting all the help on this work.
> >
> > On summary this series support
> > - Code warning and fixes
> > - rank detection, this would required to probe single channel
> > sdram configured in NanoPI-NEO4
> > - LPDDR4 support, tested in Rockpro64 and Rock-PI-4
> >
> > patch 0001 - 0033: fix code warnings, prints, new macros
> >
> > patch 0034 - 0051: rank detection, sdram debug code
> >
> > patch 0052: Use DDR3-1800 on NanoPI-NEO4
> >
> > patch 0053 - 0089: lpddr4 support
> >
> > patch 0090: LPDDR4-100 timings
> >
> > patch 0091: Use LPDDR4-100 on Rockpro64
> >
> > patch 0092: Use LPDDR4-100 on Rock-PI 4
> >
> > Note: Puma rk3399 has SPL size overflow, better to enable TPL
> > for this board.
>
> We need to keep Puma on a SPL-only configuration for the time being.
> Please make sure that the LPDDR4 code is an optional feature that does not
> increase the DRAM-driver size for boards that don’t need/want it.
We have few boards do have TPL-runnable, would be any technical issue
to switch puma to TPL? because we have lpddr4 code part of existing
driver itself and it require extra ifdef to consider which indeed look
awful from code point-of-view.
^ permalink raw reply [flat|nested] 204+ messages in thread
* Re: [PATCH 00/92] ram: rk3399: Add LPDDR4 support
2019-06-11 15:03 ` [U-Boot] " Jagan Teki
@ 2019-06-11 15:06 ` Philipp Tomsich
-1 siblings, 0 replies; 204+ messages in thread
From: Philipp Tomsich @ 2019-06-11 15:06 UTC (permalink / raw)
To: Jagan Teki
Cc: YouMin Chen, U-Boot-Denx, Simon Glass, Akash Gajjar, Kever Yang,
open list:ARM/Rockchip SoC...,
linux-amarula
> On 11.06.2019, at 17:03, Jagan Teki <jagan@amarulasolutions.com> wrote:
>
> On Tue, Jun 11, 2019 at 8:23 PM Philipp Tomsich
> <philipp.tomsich@theobroma-systems.com> wrote:
>>
>>
>>
>>> On 11.06.2019, at 16:50, Jagan Teki <jagan@amarulasolutions.com> wrote:
>>>
>>> Yes, it can be possible to break this series into multiple sub series
>>> but idea here is to mark all the required changes to support LPDDR4
>>> in rk3399 in one set. if required we can break it from next versions.
>>>
>>> This is the initial set for supporting LPDDR4 with associated
>>> features.
>>>
>>> Thanks to
>>> - YouMin Chen
>>> - Akash Gajjar
>>> - Kever Yang
>>> for supporting all the help on this work.
>>>
>>> On summary this series support
>>> - Code warning and fixes
>>> - rank detection, this would required to probe single channel
>>> sdram configured in NanoPI-NEO4
>>> - LPDDR4 support, tested in Rockpro64 and Rock-PI-4
>>>
>>> patch 0001 - 0033: fix code warnings, prints, new macros
>>>
>>> patch 0034 - 0051: rank detection, sdram debug code
>>>
>>> patch 0052: Use DDR3-1800 on NanoPI-NEO4
>>>
>>> patch 0053 - 0089: lpddr4 support
>>>
>>> patch 0090: LPDDR4-100 timings
>>>
>>> patch 0091: Use LPDDR4-100 on Rockpro64
>>>
>>> patch 0092: Use LPDDR4-100 on Rock-PI 4
>>>
>>> Note: Puma rk3399 has SPL size overflow, better to enable TPL
>>> for this board.
>>
>> We need to keep Puma on a SPL-only configuration for the time being.
>> Please make sure that the LPDDR4 code is an optional feature that does not
>> increase the DRAM-driver size for boards that don’t need/want it.
>
> We have few boards do have TPL-runnable, would be any technical issue
> to switch puma to TPL? because we have lpddr4 code part of existing
> driver itself and it require extra ifdef to consider which indeed look
> awful from code point-of-view.
Our secure boot process (i.e. signing tools) currently depends on this and
the changeover won’t be quick…
Thanks,
Philipp.
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 00/92] ram: rk3399: Add LPDDR4 support
@ 2019-06-11 15:06 ` Philipp Tomsich
0 siblings, 0 replies; 204+ messages in thread
From: Philipp Tomsich @ 2019-06-11 15:06 UTC (permalink / raw)
To: u-boot
> On 11.06.2019, at 17:03, Jagan Teki <jagan@amarulasolutions.com> wrote:
>
> On Tue, Jun 11, 2019 at 8:23 PM Philipp Tomsich
> <philipp.tomsich@theobroma-systems.com> wrote:
>>
>>
>>
>>> On 11.06.2019, at 16:50, Jagan Teki <jagan@amarulasolutions.com> wrote:
>>>
>>> Yes, it can be possible to break this series into multiple sub series
>>> but idea here is to mark all the required changes to support LPDDR4
>>> in rk3399 in one set. if required we can break it from next versions.
>>>
>>> This is the initial set for supporting LPDDR4 with associated
>>> features.
>>>
>>> Thanks to
>>> - YouMin Chen
>>> - Akash Gajjar
>>> - Kever Yang
>>> for supporting all the help on this work.
>>>
>>> On summary this series support
>>> - Code warning and fixes
>>> - rank detection, this would required to probe single channel
>>> sdram configured in NanoPI-NEO4
>>> - LPDDR4 support, tested in Rockpro64 and Rock-PI-4
>>>
>>> patch 0001 - 0033: fix code warnings, prints, new macros
>>>
>>> patch 0034 - 0051: rank detection, sdram debug code
>>>
>>> patch 0052: Use DDR3-1800 on NanoPI-NEO4
>>>
>>> patch 0053 - 0089: lpddr4 support
>>>
>>> patch 0090: LPDDR4-100 timings
>>>
>>> patch 0091: Use LPDDR4-100 on Rockpro64
>>>
>>> patch 0092: Use LPDDR4-100 on Rock-PI 4
>>>
>>> Note: Puma rk3399 has SPL size overflow, better to enable TPL
>>> for this board.
>>
>> We need to keep Puma on a SPL-only configuration for the time being.
>> Please make sure that the LPDDR4 code is an optional feature that does not
>> increase the DRAM-driver size for boards that don’t need/want it.
>
> We have few boards do have TPL-runnable, would be any technical issue
> to switch puma to TPL? because we have lpddr4 code part of existing
> driver itself and it require extra ifdef to consider which indeed look
> awful from code point-of-view.
Our secure boot process (i.e. signing tools) currently depends on this and
the changeover won’t be quick…
Thanks,
Philipp.
^ permalink raw reply [flat|nested] 204+ messages in thread
* Re: [PATCH 00/92] ram: rk3399: Add LPDDR4 support
2019-06-11 15:06 ` [U-Boot] " Philipp Tomsich
@ 2019-06-12 15:30 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-12 15:30 UTC (permalink / raw)
To: Philipp Tomsich
Cc: YouMin Chen, U-Boot-Denx, Akash Gajjar,
open list:ARM/Rockchip SoC...,
linux-amarula
On Tue, Jun 11, 2019 at 8:36 PM Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
>
>
>
> > On 11.06.2019, at 17:03, Jagan Teki <jagan@amarulasolutions.com> wrote:
> >
> > On Tue, Jun 11, 2019 at 8:23 PM Philipp Tomsich
> > <philipp.tomsich@theobroma-systems.com> wrote:
> >>
> >>
> >>
> >>> On 11.06.2019, at 16:50, Jagan Teki <jagan@amarulasolutions.com> wrote:
> >>>
> >>> Yes, it can be possible to break this series into multiple sub series
> >>> but idea here is to mark all the required changes to support LPDDR4
> >>> in rk3399 in one set. if required we can break it from next versions.
> >>>
> >>> This is the initial set for supporting LPDDR4 with associated
> >>> features.
> >>>
> >>> Thanks to
> >>> - YouMin Chen
> >>> - Akash Gajjar
> >>> - Kever Yang
> >>> for supporting all the help on this work.
> >>>
> >>> On summary this series support
> >>> - Code warning and fixes
> >>> - rank detection, this would required to probe single channel
> >>> sdram configured in NanoPI-NEO4
> >>> - LPDDR4 support, tested in Rockpro64 and Rock-PI-4
> >>>
> >>> patch 0001 - 0033: fix code warnings, prints, new macros
> >>>
> >>> patch 0034 - 0051: rank detection, sdram debug code
> >>>
> >>> patch 0052: Use DDR3-1800 on NanoPI-NEO4
> >>>
> >>> patch 0053 - 0089: lpddr4 support
> >>>
> >>> patch 0090: LPDDR4-100 timings
> >>>
> >>> patch 0091: Use LPDDR4-100 on Rockpro64
> >>>
> >>> patch 0092: Use LPDDR4-100 on Rock-PI 4
> >>>
> >>> Note: Puma rk3399 has SPL size overflow, better to enable TPL
> >>> for this board.
> >>
> >> We need to keep Puma on a SPL-only configuration for the time being.
> >> Please make sure that the LPDDR4 code is an optional feature that does not
> >> increase the DRAM-driver size for boards that don’t need/want it.
> >
> > We have few boards do have TPL-runnable, would be any technical issue
> > to switch puma to TPL? because we have lpddr4 code part of existing
> > driver itself and it require extra ifdef to consider which indeed look
> > awful from code point-of-view.
>
> Our secure boot process (i.e. signing tools) currently depends on this and
> the changeover won’t be quick…
Not so quick, we have time till MW. isn't it possible? enabling secure
tools in both TPL and SPL or TPL-alone would be meaningful trail. what
do you think?
_______________________________________________
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
^ permalink raw reply [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 00/92] ram: rk3399: Add LPDDR4 support
@ 2019-06-12 15:30 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-12 15:30 UTC (permalink / raw)
To: u-boot
On Tue, Jun 11, 2019 at 8:36 PM Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
>
>
>
> > On 11.06.2019, at 17:03, Jagan Teki <jagan@amarulasolutions.com> wrote:
> >
> > On Tue, Jun 11, 2019 at 8:23 PM Philipp Tomsich
> > <philipp.tomsich@theobroma-systems.com> wrote:
> >>
> >>
> >>
> >>> On 11.06.2019, at 16:50, Jagan Teki <jagan@amarulasolutions.com> wrote:
> >>>
> >>> Yes, it can be possible to break this series into multiple sub series
> >>> but idea here is to mark all the required changes to support LPDDR4
> >>> in rk3399 in one set. if required we can break it from next versions.
> >>>
> >>> This is the initial set for supporting LPDDR4 with associated
> >>> features.
> >>>
> >>> Thanks to
> >>> - YouMin Chen
> >>> - Akash Gajjar
> >>> - Kever Yang
> >>> for supporting all the help on this work.
> >>>
> >>> On summary this series support
> >>> - Code warning and fixes
> >>> - rank detection, this would required to probe single channel
> >>> sdram configured in NanoPI-NEO4
> >>> - LPDDR4 support, tested in Rockpro64 and Rock-PI-4
> >>>
> >>> patch 0001 - 0033: fix code warnings, prints, new macros
> >>>
> >>> patch 0034 - 0051: rank detection, sdram debug code
> >>>
> >>> patch 0052: Use DDR3-1800 on NanoPI-NEO4
> >>>
> >>> patch 0053 - 0089: lpddr4 support
> >>>
> >>> patch 0090: LPDDR4-100 timings
> >>>
> >>> patch 0091: Use LPDDR4-100 on Rockpro64
> >>>
> >>> patch 0092: Use LPDDR4-100 on Rock-PI 4
> >>>
> >>> Note: Puma rk3399 has SPL size overflow, better to enable TPL
> >>> for this board.
> >>
> >> We need to keep Puma on a SPL-only configuration for the time being.
> >> Please make sure that the LPDDR4 code is an optional feature that does not
> >> increase the DRAM-driver size for boards that don’t need/want it.
> >
> > We have few boards do have TPL-runnable, would be any technical issue
> > to switch puma to TPL? because we have lpddr4 code part of existing
> > driver itself and it require extra ifdef to consider which indeed look
> > awful from code point-of-view.
>
> Our secure boot process (i.e. signing tools) currently depends on this and
> the changeover won’t be quick…
Not so quick, we have time till MW. isn't it possible? enabling secure
tools in both TPL and SPL or TPL-alone would be meaningful trail. what
do you think?
^ permalink raw reply [flat|nested] 204+ messages in thread
* Re: [PATCH 00/92] ram: rk3399: Add LPDDR4 support
2019-06-12 15:30 ` [U-Boot] " Jagan Teki
@ 2019-06-12 15:40 ` Philipp Tomsich
-1 siblings, 0 replies; 204+ messages in thread
From: Philipp Tomsich @ 2019-06-12 15:40 UTC (permalink / raw)
To: Jagan Teki
Cc: YouMin Chen, U-Boot-Denx, Akash Gajjar,
open list:ARM/Rockchip SoC...,
linux-amarula
> On 12.06.2019, at 17:30, Jagan Teki <jagan@amarulasolutions.com> wrote:
>
> On Tue, Jun 11, 2019 at 8:36 PM Philipp Tomsich
> <philipp.tomsich@theobroma-systems.com <mailto:philipp.tomsich@theobroma-systems.com>> wrote:
>>
>>
>>
>>> On 11.06.2019, at 17:03, Jagan Teki <jagan@amarulasolutions.com> wrote:
>>>
>>> On Tue, Jun 11, 2019 at 8:23 PM Philipp Tomsich
>>> <philipp.tomsich@theobroma-systems.com> wrote:
>>>>
>>>>
>>>>
>>>>> On 11.06.2019, at 16:50, Jagan Teki <jagan@amarulasolutions.com> wrote:
>>>>>
>>>>> Yes, it can be possible to break this series into multiple sub series
>>>>> but idea here is to mark all the required changes to support LPDDR4
>>>>> in rk3399 in one set. if required we can break it from next versions.
>>>>>
>>>>> This is the initial set for supporting LPDDR4 with associated
>>>>> features.
>>>>>
>>>>> Thanks to
>>>>> - YouMin Chen
>>>>> - Akash Gajjar
>>>>> - Kever Yang
>>>>> for supporting all the help on this work.
>>>>>
>>>>> On summary this series support
>>>>> - Code warning and fixes
>>>>> - rank detection, this would required to probe single channel
>>>>> sdram configured in NanoPI-NEO4
>>>>> - LPDDR4 support, tested in Rockpro64 and Rock-PI-4
>>>>>
>>>>> patch 0001 - 0033: fix code warnings, prints, new macros
>>>>>
>>>>> patch 0034 - 0051: rank detection, sdram debug code
>>>>>
>>>>> patch 0052: Use DDR3-1800 on NanoPI-NEO4
>>>>>
>>>>> patch 0053 - 0089: lpddr4 support
>>>>>
>>>>> patch 0090: LPDDR4-100 timings
>>>>>
>>>>> patch 0091: Use LPDDR4-100 on Rockpro64
>>>>>
>>>>> patch 0092: Use LPDDR4-100 on Rock-PI 4
>>>>>
>>>>> Note: Puma rk3399 has SPL size overflow, better to enable TPL
>>>>> for this board.
>>>>
>>>> We need to keep Puma on a SPL-only configuration for the time being.
>>>> Please make sure that the LPDDR4 code is an optional feature that does not
>>>> increase the DRAM-driver size for boards that don’t need/want it.
>>>
>>> We have few boards do have TPL-runnable, would be any technical issue
>>> to switch puma to TPL? because we have lpddr4 code part of existing
>>> driver itself and it require extra ifdef to consider which indeed look
>>> awful from code point-of-view.
>>
>> Our secure boot process (i.e. signing tools) currently depends on this and
>> the changeover won’t be quick…
>
> Not so quick, we have time till MW. isn't it possible? enabling secure
> tools in both TPL and SPL or TPL-alone would be meaningful trail. what
> do you think?
We aren’t talking about a single MW here, given that summer is starting to eat
up some of my resources…
Thanks,
Phil.
_______________________________________________
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
^ permalink raw reply [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 00/92] ram: rk3399: Add LPDDR4 support
@ 2019-06-12 15:40 ` Philipp Tomsich
0 siblings, 0 replies; 204+ messages in thread
From: Philipp Tomsich @ 2019-06-12 15:40 UTC (permalink / raw)
To: u-boot
> On 12.06.2019, at 17:30, Jagan Teki <jagan@amarulasolutions.com> wrote:
>
> On Tue, Jun 11, 2019 at 8:36 PM Philipp Tomsich
> <philipp.tomsich at theobroma-systems.com <mailto:philipp.tomsich@theobroma-systems.com>> wrote:
>>
>>
>>
>>> On 11.06.2019, at 17:03, Jagan Teki <jagan@amarulasolutions.com> wrote:
>>>
>>> On Tue, Jun 11, 2019 at 8:23 PM Philipp Tomsich
>>> <philipp.tomsich@theobroma-systems.com> wrote:
>>>>
>>>>
>>>>
>>>>> On 11.06.2019, at 16:50, Jagan Teki <jagan@amarulasolutions.com> wrote:
>>>>>
>>>>> Yes, it can be possible to break this series into multiple sub series
>>>>> but idea here is to mark all the required changes to support LPDDR4
>>>>> in rk3399 in one set. if required we can break it from next versions.
>>>>>
>>>>> This is the initial set for supporting LPDDR4 with associated
>>>>> features.
>>>>>
>>>>> Thanks to
>>>>> - YouMin Chen
>>>>> - Akash Gajjar
>>>>> - Kever Yang
>>>>> for supporting all the help on this work.
>>>>>
>>>>> On summary this series support
>>>>> - Code warning and fixes
>>>>> - rank detection, this would required to probe single channel
>>>>> sdram configured in NanoPI-NEO4
>>>>> - LPDDR4 support, tested in Rockpro64 and Rock-PI-4
>>>>>
>>>>> patch 0001 - 0033: fix code warnings, prints, new macros
>>>>>
>>>>> patch 0034 - 0051: rank detection, sdram debug code
>>>>>
>>>>> patch 0052: Use DDR3-1800 on NanoPI-NEO4
>>>>>
>>>>> patch 0053 - 0089: lpddr4 support
>>>>>
>>>>> patch 0090: LPDDR4-100 timings
>>>>>
>>>>> patch 0091: Use LPDDR4-100 on Rockpro64
>>>>>
>>>>> patch 0092: Use LPDDR4-100 on Rock-PI 4
>>>>>
>>>>> Note: Puma rk3399 has SPL size overflow, better to enable TPL
>>>>> for this board.
>>>>
>>>> We need to keep Puma on a SPL-only configuration for the time being.
>>>> Please make sure that the LPDDR4 code is an optional feature that does not
>>>> increase the DRAM-driver size for boards that don’t need/want it.
>>>
>>> We have few boards do have TPL-runnable, would be any technical issue
>>> to switch puma to TPL? because we have lpddr4 code part of existing
>>> driver itself and it require extra ifdef to consider which indeed look
>>> awful from code point-of-view.
>>
>> Our secure boot process (i.e. signing tools) currently depends on this and
>> the changeover won’t be quick…
>
> Not so quick, we have time till MW. isn't it possible? enabling secure
> tools in both TPL and SPL or TPL-alone would be meaningful trail. what
> do you think?
We aren’t talking about a single MW here, given that summer is starting to eat
up some of my resources…
Thanks,
Phil.
^ permalink raw reply [flat|nested] 204+ messages in thread
* Re: [PATCH 00/92] ram: rk3399: Add LPDDR4 support
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
@ 2019-06-13 1:44 ` Kever Yang
-1 siblings, 0 replies; 204+ messages in thread
From: Kever Yang @ 2019-06-13 1:44 UTC (permalink / raw)
To: Jagan Teki, Simon Glass, Philipp Tomsich, YouMin Chen, u-boot
Cc: linux-rockchip, linux-amarula, gajjar04akash
Hi Jagan,
Very grateful for you to send this patch set for LPDDR4 support.
But, 92 patches, a little bit too much for merge them one by one,
is it possible for U-Boot to merge this from somewhere after we review
all these patches?
Thanks,
- Kever
On 06/11/2019 10:50 PM, Jagan Teki wrote:
> Yes, it can be possible to break this series into multiple sub series
> but idea here is to mark all the required changes to support LPDDR4
> in rk3399 in one set. if required we can break it from next versions.
>
> This is the initial set for supporting LPDDR4 with associated
> features.
>
> Thanks to
> - YouMin Chen
> - Akash Gajjar
> - Kever Yang
> for supporting all the help on this work.
>
> On summary this series support
> - Code warning and fixes
> - rank detection, this would required to probe single channel
> sdram configured in NanoPI-NEO4
> - LPDDR4 support, tested in Rockpro64 and Rock-PI-4
>
> patch 0001 - 0033: fix code warnings, prints, new macros
>
> patch 0034 - 0051: rank detection, sdram debug code
>
> patch 0052: Use DDR3-1800 on NanoPI-NEO4
>
> patch 0053 - 0089: lpddr4 support
>
> patch 0090: LPDDR4-100 timings
>
> patch 0091: Use LPDDR4-100 on Rockpro64
>
> patch 0092: Use LPDDR4-100 on Rock-PI 4
>
> Note: Puma rk3399 has SPL size overflow, better to enable TPL
> for this board.
>
> Any inputs?
> Jagan.
>
> Jagan Teki (92):
> ram: rk3399: Fix code warnings
> ram: rk3399: Add space between string with format specifier
> ram: rk3399: Add proper spaces in data training
> ram: rk3399: Handle data training return types
> ram: rk3399: Order include files
> ram: rk3399: Move macro after include files
> ram: rk3399: Clear PI_175 interrupts in data training
> ram: rk3399: Use rank mask in ca data training
> ram: rk3399: Use rank mask in wdql data training
> ram: rk3399: Add ddrtype enc macro
> ram: rk3399: Add channel number encoder macro
> ram: rk3399: Add row_3_4 enc macro
> ram: rk3399: Add chipinfo macro
> ram: rk3399: Add rank enc macro
> ram: rk3399: Add column enc macro
> ram: rk3399: Add bk enc macro
> ram: rk3399: Add dbw enc macro
> ram: rk3399: Add cs0_rw macro
> ram: rk3399: Add cs1_rw macro
> ram: rk3399: Add bw enc macro
> ram: rk3399: Rename sys_reg with sys_reg2
> ram: rk3399: Update cs0_row to use sys_reg3
> ram: rk3399: Update cs1_row to use sys_reg3
> ram: rk3399: Add cs1_col enc macro
> ram: rk3399: Add ddr version enc macro
> ram: rk3399: Add ddrtimingC0
> ram: rk3399: Add DdrMode
> ram: rk3399: Handle pctl_cfg return type
> ram: rk3399: s/tsel_wr_select_n/tsel_wr_select_dq_n
> ram: rk3399: s/tsel_wr_select_p/tsel_wr_select_dq_p
> ram: rk3399: s/ca_tsel_wr_select_n/tsel_wr_select_ca_n
> ram: rk3399: s/ca_tsel_wr_select_p/tsel_wr_select_ca_p
> ram: rk3399: Order tsel variables
> ram: rk3399: Add phy pctrl reset support
> ram: rk3399: Move pwrup_srefresh_exit to dram_info
> ram: rk3399: Add pctl start support
> ram: rockchip: rk3399: Add cap_info structure
> ram: rk3399: s/rk3399_base_params/sdram_base_params
> ram: rk3399: Move common sdram structures in common header
> arm: include: rockchip: Move dramtypes to common header
> arm: include: rockchip: Add DDR4 enum
> ram: rockchip: Add initial Kconfig
> debug_uart: Add printdec
> ram: rockchip: Add debug sdram driver
> ram: rockchip: debug: Add sdram_print_ddr_info
> ram: rockchip: debug: Get the cs capacity
> ram: rk3399: debug: Add sdram_print_stride
> ram: rk3399: Compute stride for 2 channels
> ram: rk3399: Compute stride for 1 channel a
> ram: rk3399: Add rank detection support
> ram: rk3399: Enable sdram debug functions
> rockchip: dts: rk3399: nanopi-neo4: Use DDR3-1866 dtsi
> clk: rockchip: rk3399: Fix check patch warnings and checks
> clk: rockchip: rk3399: Set 50MHz ddr clock
> clk: rockchip: rk3399: Set 400MHz ddr clock
> ram: rk3399: Add spaces in pctl_cfg
> ram: rk3399: Configure phy IO in ds odt
> ram: rk3399: Add lpddr4 rank mask for cs training
> ram: rk3399: Add lpddr4 rank mask for wdql training
> ram: rk3399: Move mode_sel assignment
> ram: rk3399: Don't wait for PLL lock in lpddr4
> ram: rk3399: Avoid two channel ZQ Cal Start at the same time
> ram: rk3399: Configure PHY_898, PHY_919 for lpddr4
> ram: rk3399: Configure BOOSTP_EN, BOOSTN_EN for lpddr4
> ram: rk3399: Configure SLEWP_EN, SLEWN_EN for lpddr4
> ram: rk3399: Configure PHY RX_CM_INPUT for lpddr4
> ram: rk3399: Map chipselect for lpddr4
> ram: rk3399: Configure tsel write ca for lpddr4
> ram: rk3399: Don't disable dfi dram clk for lpddr4, rank 1
> ram: rk3399: Add IO settings
> ram: sdram: Configure lpddr4 tsel rd, wr based on IO settings
> ram: rk3399: Add tsel control clock drive
> ram: rk3399: Configure soc odt support
> ram: rk3399: Get lpddr4 tsel_rd_en from io settings
> ram: rk3399: Update lpddr4 vref based on io settings
> ram: rk3399: Update lpddr4 mode_sel based on io settings
> ram: rk3399: Update lpddr4 vref_mode_ac
> ram: rk3399: Add LPPDR4 mr detection
> arm: include: rockchip: Add rk3399 pmu file
> rockchip: rk3399: syscon: Add pmu support
> rockchip: dts: rk3399: Add u-boot,dm-pre-reloc for pmu
> ram: rk3399: Add LPPDDR4-400 timings inc
> ram: rk3399: Add LPPDDR4-800 timings inc
> ram: rk3399: Add lpddr4 set rate support
> ram: rk3399: Set lpddr4 dq odt
> ram: rk3399: Set lpddr4 ca odt
> ram: rk3399: Set lpddr4 MR3
> ram: rk3399: Set lpddr4 MR12
> ram: rk3399: Set lpddr4 MR14
> rockchip: dts: rk3399: Add LPDDR4-100 timings
> rockchip: dts: rk3399: rockpro64: Use LPDDR4-100 dtsi
> rockchip: dts: rk3399: rock-pi-4: Use LPDDR4-100 dtsi
>
> arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi | 1 +
> arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi | 1 +
> arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 1 +
> arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi | 1537 ++++++++++++
> arch/arm/dts/rk3399-u-boot.dtsi | 4 +
> .../include/asm/arch-rockchip/pmu_rk3399.h | 72 +
> arch/arm/include/asm/arch-rockchip/sdram.h | 6 -
> .../include/asm/arch-rockchip/sdram_common.h | 89 +
> .../include/asm/arch-rockchip/sdram_rk322x.h | 7 -
> .../include/asm/arch-rockchip/sdram_rk3399.h | 65 +-
> arch/arm/mach-rockchip/rk3399/syscon_rk3399.c | 8 +
> drivers/clk/rockchip/clk_rk3399.c | 76 +-
> drivers/ram/Kconfig | 1 +
> drivers/ram/rockchip/Kconfig | 26 +
> drivers/ram/rockchip/Makefile | 3 +-
> .../ram/rockchip/sdram-rk3399-lpddr4-400.inc | 1570 ++++++++++++
> .../ram/rockchip/sdram-rk3399-lpddr4-800.inc | 1570 ++++++++++++
> drivers/ram/rockchip/sdram_debug.c | 147 ++
> drivers/ram/rockchip/sdram_rk3399.c | 2176 ++++++++++++++---
> include/debug_uart.h | 19 +
> 20 files changed, 6964 insertions(+), 415 deletions(-)
> create mode 100644 arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi
> create mode 100644 arch/arm/include/asm/arch-rockchip/pmu_rk3399.h
> create mode 100644 drivers/ram/rockchip/Kconfig
> create mode 100644 drivers/ram/rockchip/sdram-rk3399-lpddr4-400.inc
> create mode 100644 drivers/ram/rockchip/sdram-rk3399-lpddr4-800.inc
> create mode 100644 drivers/ram/rockchip/sdram_debug.c
>
_______________________________________________
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
^ permalink raw reply [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 00/92] ram: rk3399: Add LPDDR4 support
@ 2019-06-13 1:44 ` Kever Yang
0 siblings, 0 replies; 204+ messages in thread
From: Kever Yang @ 2019-06-13 1:44 UTC (permalink / raw)
To: u-boot
Hi Jagan,
Very grateful for you to send this patch set for LPDDR4 support.
But, 92 patches, a little bit too much for merge them one by one,
is it possible for U-Boot to merge this from somewhere after we review
all these patches?
Thanks,
- Kever
On 06/11/2019 10:50 PM, Jagan Teki wrote:
> Yes, it can be possible to break this series into multiple sub series
> but idea here is to mark all the required changes to support LPDDR4
> in rk3399 in one set. if required we can break it from next versions.
>
> This is the initial set for supporting LPDDR4 with associated
> features.
>
> Thanks to
> - YouMin Chen
> - Akash Gajjar
> - Kever Yang
> for supporting all the help on this work.
>
> On summary this series support
> - Code warning and fixes
> - rank detection, this would required to probe single channel
> sdram configured in NanoPI-NEO4
> - LPDDR4 support, tested in Rockpro64 and Rock-PI-4
>
> patch 0001 - 0033: fix code warnings, prints, new macros
>
> patch 0034 - 0051: rank detection, sdram debug code
>
> patch 0052: Use DDR3-1800 on NanoPI-NEO4
>
> patch 0053 - 0089: lpddr4 support
>
> patch 0090: LPDDR4-100 timings
>
> patch 0091: Use LPDDR4-100 on Rockpro64
>
> patch 0092: Use LPDDR4-100 on Rock-PI 4
>
> Note: Puma rk3399 has SPL size overflow, better to enable TPL
> for this board.
>
> Any inputs?
> Jagan.
>
> Jagan Teki (92):
> ram: rk3399: Fix code warnings
> ram: rk3399: Add space between string with format specifier
> ram: rk3399: Add proper spaces in data training
> ram: rk3399: Handle data training return types
> ram: rk3399: Order include files
> ram: rk3399: Move macro after include files
> ram: rk3399: Clear PI_175 interrupts in data training
> ram: rk3399: Use rank mask in ca data training
> ram: rk3399: Use rank mask in wdql data training
> ram: rk3399: Add ddrtype enc macro
> ram: rk3399: Add channel number encoder macro
> ram: rk3399: Add row_3_4 enc macro
> ram: rk3399: Add chipinfo macro
> ram: rk3399: Add rank enc macro
> ram: rk3399: Add column enc macro
> ram: rk3399: Add bk enc macro
> ram: rk3399: Add dbw enc macro
> ram: rk3399: Add cs0_rw macro
> ram: rk3399: Add cs1_rw macro
> ram: rk3399: Add bw enc macro
> ram: rk3399: Rename sys_reg with sys_reg2
> ram: rk3399: Update cs0_row to use sys_reg3
> ram: rk3399: Update cs1_row to use sys_reg3
> ram: rk3399: Add cs1_col enc macro
> ram: rk3399: Add ddr version enc macro
> ram: rk3399: Add ddrtimingC0
> ram: rk3399: Add DdrMode
> ram: rk3399: Handle pctl_cfg return type
> ram: rk3399: s/tsel_wr_select_n/tsel_wr_select_dq_n
> ram: rk3399: s/tsel_wr_select_p/tsel_wr_select_dq_p
> ram: rk3399: s/ca_tsel_wr_select_n/tsel_wr_select_ca_n
> ram: rk3399: s/ca_tsel_wr_select_p/tsel_wr_select_ca_p
> ram: rk3399: Order tsel variables
> ram: rk3399: Add phy pctrl reset support
> ram: rk3399: Move pwrup_srefresh_exit to dram_info
> ram: rk3399: Add pctl start support
> ram: rockchip: rk3399: Add cap_info structure
> ram: rk3399: s/rk3399_base_params/sdram_base_params
> ram: rk3399: Move common sdram structures in common header
> arm: include: rockchip: Move dramtypes to common header
> arm: include: rockchip: Add DDR4 enum
> ram: rockchip: Add initial Kconfig
> debug_uart: Add printdec
> ram: rockchip: Add debug sdram driver
> ram: rockchip: debug: Add sdram_print_ddr_info
> ram: rockchip: debug: Get the cs capacity
> ram: rk3399: debug: Add sdram_print_stride
> ram: rk3399: Compute stride for 2 channels
> ram: rk3399: Compute stride for 1 channel a
> ram: rk3399: Add rank detection support
> ram: rk3399: Enable sdram debug functions
> rockchip: dts: rk3399: nanopi-neo4: Use DDR3-1866 dtsi
> clk: rockchip: rk3399: Fix check patch warnings and checks
> clk: rockchip: rk3399: Set 50MHz ddr clock
> clk: rockchip: rk3399: Set 400MHz ddr clock
> ram: rk3399: Add spaces in pctl_cfg
> ram: rk3399: Configure phy IO in ds odt
> ram: rk3399: Add lpddr4 rank mask for cs training
> ram: rk3399: Add lpddr4 rank mask for wdql training
> ram: rk3399: Move mode_sel assignment
> ram: rk3399: Don't wait for PLL lock in lpddr4
> ram: rk3399: Avoid two channel ZQ Cal Start at the same time
> ram: rk3399: Configure PHY_898, PHY_919 for lpddr4
> ram: rk3399: Configure BOOSTP_EN, BOOSTN_EN for lpddr4
> ram: rk3399: Configure SLEWP_EN, SLEWN_EN for lpddr4
> ram: rk3399: Configure PHY RX_CM_INPUT for lpddr4
> ram: rk3399: Map chipselect for lpddr4
> ram: rk3399: Configure tsel write ca for lpddr4
> ram: rk3399: Don't disable dfi dram clk for lpddr4, rank 1
> ram: rk3399: Add IO settings
> ram: sdram: Configure lpddr4 tsel rd, wr based on IO settings
> ram: rk3399: Add tsel control clock drive
> ram: rk3399: Configure soc odt support
> ram: rk3399: Get lpddr4 tsel_rd_en from io settings
> ram: rk3399: Update lpddr4 vref based on io settings
> ram: rk3399: Update lpddr4 mode_sel based on io settings
> ram: rk3399: Update lpddr4 vref_mode_ac
> ram: rk3399: Add LPPDR4 mr detection
> arm: include: rockchip: Add rk3399 pmu file
> rockchip: rk3399: syscon: Add pmu support
> rockchip: dts: rk3399: Add u-boot,dm-pre-reloc for pmu
> ram: rk3399: Add LPPDDR4-400 timings inc
> ram: rk3399: Add LPPDDR4-800 timings inc
> ram: rk3399: Add lpddr4 set rate support
> ram: rk3399: Set lpddr4 dq odt
> ram: rk3399: Set lpddr4 ca odt
> ram: rk3399: Set lpddr4 MR3
> ram: rk3399: Set lpddr4 MR12
> ram: rk3399: Set lpddr4 MR14
> rockchip: dts: rk3399: Add LPDDR4-100 timings
> rockchip: dts: rk3399: rockpro64: Use LPDDR4-100 dtsi
> rockchip: dts: rk3399: rock-pi-4: Use LPDDR4-100 dtsi
>
> arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi | 1 +
> arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi | 1 +
> arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 1 +
> arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi | 1537 ++++++++++++
> arch/arm/dts/rk3399-u-boot.dtsi | 4 +
> .../include/asm/arch-rockchip/pmu_rk3399.h | 72 +
> arch/arm/include/asm/arch-rockchip/sdram.h | 6 -
> .../include/asm/arch-rockchip/sdram_common.h | 89 +
> .../include/asm/arch-rockchip/sdram_rk322x.h | 7 -
> .../include/asm/arch-rockchip/sdram_rk3399.h | 65 +-
> arch/arm/mach-rockchip/rk3399/syscon_rk3399.c | 8 +
> drivers/clk/rockchip/clk_rk3399.c | 76 +-
> drivers/ram/Kconfig | 1 +
> drivers/ram/rockchip/Kconfig | 26 +
> drivers/ram/rockchip/Makefile | 3 +-
> .../ram/rockchip/sdram-rk3399-lpddr4-400.inc | 1570 ++++++++++++
> .../ram/rockchip/sdram-rk3399-lpddr4-800.inc | 1570 ++++++++++++
> drivers/ram/rockchip/sdram_debug.c | 147 ++
> drivers/ram/rockchip/sdram_rk3399.c | 2176 ++++++++++++++---
> include/debug_uart.h | 19 +
> 20 files changed, 6964 insertions(+), 415 deletions(-)
> create mode 100644 arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi
> create mode 100644 arch/arm/include/asm/arch-rockchip/pmu_rk3399.h
> create mode 100644 drivers/ram/rockchip/Kconfig
> create mode 100644 drivers/ram/rockchip/sdram-rk3399-lpddr4-400.inc
> create mode 100644 drivers/ram/rockchip/sdram-rk3399-lpddr4-800.inc
> create mode 100644 drivers/ram/rockchip/sdram_debug.c
>
^ permalink raw reply [flat|nested] 204+ messages in thread
* Re: [PATCH 00/92] ram: rk3399: Add LPDDR4 support
2019-06-11 15:03 ` [U-Boot] " Jagan Teki
@ 2019-06-13 1:50 ` Kever Yang
-1 siblings, 0 replies; 204+ messages in thread
From: Kever Yang @ 2019-06-13 1:50 UTC (permalink / raw)
To: Jagan Teki, Philipp Tomsich
Cc: YouMin Chen, U-Boot-Denx, Akash Gajjar,
open list:ARM/Rockchip SoC...,
linux-amarula
Hi Jagan,
On 06/11/2019 11:03 PM, Jagan Teki wrote:
>>> Note: Puma rk3399 has SPL size overflow, better to enable TPL
>>> for this board.
>> We need to keep Puma on a SPL-only configuration for the time being.
>> Please make sure that the LPDDR4 code is an optional feature that does not
>> increase the DRAM-driver size for boards that don’t need/want it.
> We have few boards do have TPL-runnable, would be any technical issue
> to switch puma to TPL? because we have lpddr4 code part of existing
> driver itself and it require extra ifdef to consider which indeed look
> awful from code point-of-view.
>
Dose the driver size increase too much for Puma because of the lpddr4
init logic or because of the two extra timing data? The two timing data
are pretty big, maybe we do not need them if the board is not lpddr4?
Thanks,
- Kever
_______________________________________________
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
^ permalink raw reply [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 00/92] ram: rk3399: Add LPDDR4 support
@ 2019-06-13 1:50 ` Kever Yang
0 siblings, 0 replies; 204+ messages in thread
From: Kever Yang @ 2019-06-13 1:50 UTC (permalink / raw)
To: u-boot
Hi Jagan,
On 06/11/2019 11:03 PM, Jagan Teki wrote:
>>> Note: Puma rk3399 has SPL size overflow, better to enable TPL
>>> for this board.
>> We need to keep Puma on a SPL-only configuration for the time being.
>> Please make sure that the LPDDR4 code is an optional feature that does not
>> increase the DRAM-driver size for boards that don’t need/want it.
> We have few boards do have TPL-runnable, would be any technical issue
> to switch puma to TPL? because we have lpddr4 code part of existing
> driver itself and it require extra ifdef to consider which indeed look
> awful from code point-of-view.
>
Dose the driver size increase too much for Puma because of the lpddr4
init logic or because of the two extra timing data? The two timing data
are pretty big, maybe we do not need them if the board is not lpddr4?
Thanks,
- Kever
^ permalink raw reply [flat|nested] 204+ messages in thread
* Re: [PATCH 00/92] ram: rk3399: Add LPDDR4 support
2019-06-13 1:44 ` [U-Boot] " Kever Yang
@ 2019-06-13 6:23 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-13 6:23 UTC (permalink / raw)
To: Kever Yang
Cc: YouMin Chen, U-Boot-Denx, Akash Gajjar,
open list:ARM/Rockchip SoC...,
linux-amarula
On Thu, Jun 13, 2019 at 7:14 AM Kever Yang <kever.yang@rock-chips.com> wrote:
>
> Hi Jagan,
>
> Very grateful for you to send this patch set for LPDDR4 support.
>
> But, 92 patches, a little bit too much for merge them one by one,
>
> is it possible for U-Boot to merge this from somewhere after we review
>
> all these patches?
Applying entire series still not working for me via pwclient or
git-pw, but I usually create a bundle and apply them in single instant
like as below
₹ git config pw.server https://patchwork.ozlabs.org/
₹ git config pw.project uboot
₹ git config pw.username
₹ git config pw.password
₹ git-pw bundle list
₹ git-pw bundle apply <id>
_______________________________________________
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
^ permalink raw reply [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 00/92] ram: rk3399: Add LPDDR4 support
@ 2019-06-13 6:23 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-13 6:23 UTC (permalink / raw)
To: u-boot
On Thu, Jun 13, 2019 at 7:14 AM Kever Yang <kever.yang@rock-chips.com> wrote:
>
> Hi Jagan,
>
> Very grateful for you to send this patch set for LPDDR4 support.
>
> But, 92 patches, a little bit too much for merge them one by one,
>
> is it possible for U-Boot to merge this from somewhere after we review
>
> all these patches?
Applying entire series still not working for me via pwclient or
git-pw, but I usually create a bundle and apply them in single instant
like as below
₹ git config pw.server https://patchwork.ozlabs.org/
₹ git config pw.project uboot
₹ git config pw.username
₹ git config pw.password
₹ git-pw bundle list
₹ git-pw bundle apply <id>
^ permalink raw reply [flat|nested] 204+ messages in thread
* Re: [PATCH 00/92] ram: rk3399: Add LPDDR4 support
2019-06-13 1:50 ` [U-Boot] " Kever Yang
@ 2019-06-13 6:26 ` Jagan Teki
-1 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-13 6:26 UTC (permalink / raw)
To: Kever Yang
Cc: YouMin Chen, U-Boot-Denx, Simon Glass, Akash Gajjar,
open list:ARM/Rockchip SoC...,
Philipp Tomsich, linux-amarula
On Thu, Jun 13, 2019 at 7:21 AM Kever Yang <kever.yang@rock-chips.com> wrote:
>
> Hi Jagan,
>
>
> On 06/11/2019 11:03 PM, Jagan Teki wrote:
>
> Note: Puma rk3399 has SPL size overflow, better to enable TPL
> for this board.
>
> We need to keep Puma on a SPL-only configuration for the time being.
> Please make sure that the LPDDR4 code is an optional feature that does not
> increase the DRAM-driver size for boards that don’t need/want it.
>
> We have few boards do have TPL-runnable, would be any technical issue
> to switch puma to TPL? because we have lpddr4 code part of existing
> driver itself and it require extra ifdef to consider which indeed look
> awful from code point-of-view.
>
> Dose the driver size increase too much for Puma because of the lpddr4
> init logic or because of the two extra timing data? The two timing data
> are pretty big, maybe we do not need them if the board is not lpddr4?
Yes, along with the code that support set rate for lpddr4. Still
thinking how we can manage to mark the lpddr4 changes independent,
marking ifdef in all the code look awful. let me know if you have any
inputs?
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 204+ messages in thread
* [U-Boot] [PATCH 00/92] ram: rk3399: Add LPDDR4 support
@ 2019-06-13 6:26 ` Jagan Teki
0 siblings, 0 replies; 204+ messages in thread
From: Jagan Teki @ 2019-06-13 6:26 UTC (permalink / raw)
To: u-boot
On Thu, Jun 13, 2019 at 7:21 AM Kever Yang <kever.yang@rock-chips.com> wrote:
>
> Hi Jagan,
>
>
> On 06/11/2019 11:03 PM, Jagan Teki wrote:
>
> Note: Puma rk3399 has SPL size overflow, better to enable TPL
> for this board.
>
> We need to keep Puma on a SPL-only configuration for the time being.
> Please make sure that the LPDDR4 code is an optional feature that does not
> increase the DRAM-driver size for boards that don’t need/want it.
>
> We have few boards do have TPL-runnable, would be any technical issue
> to switch puma to TPL? because we have lpddr4 code part of existing
> driver itself and it require extra ifdef to consider which indeed look
> awful from code point-of-view.
>
> Dose the driver size increase too much for Puma because of the lpddr4
> init logic or because of the two extra timing data? The two timing data
> are pretty big, maybe we do not need them if the board is not lpddr4?
Yes, along with the code that support set rate for lpddr4. Still
thinking how we can manage to mark the lpddr4 changes independent,
marking ifdef in all the code look awful. let me know if you have any
inputs?
^ permalink raw reply [flat|nested] 204+ messages in thread
end of thread, other threads:[~2019-06-13 6:26 UTC | newest]
Thread overview: 204+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-06-11 14:50 [PATCH 00/92] ram: rk3399: Add LPDDR4 support Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
[not found] ` <20190611145135.21399-1-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
2019-06-11 14:50 ` [PATCH 01/92] ram: rk3399: Fix code warnings Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 02/92] ram: rk3399: Add space between string with format specifier Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 03/92] ram: rk3399: Add proper spaces in data training Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 04/92] ram: rk3399: Handle data training return types Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 05/92] ram: rk3399: Order include files Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 06/92] ram: rk3399: Move macro after " Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 07/92] ram: rk3399: Clear PI_175 interrupts in data training Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 08/92] ram: rk3399: Use rank mask in ca " Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 09/92] ram: rk3399: Use rank mask in wdql " Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 10/92] ram: rk3399: Add ddrtype enc macro Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 11/92] ram: rk3399: Add channel number encoder macro Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 12/92] ram: rk3399: Add row_3_4 enc macro Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 13/92] ram: rk3399: Add chipinfo macro Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 14/92] ram: rk3399: Add rank enc macro Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 15/92] ram: rk3399: Add column " Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 16/92] ram: rk3399: Add bk " Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 17/92] ram: rk3399: Add dbw " Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 18/92] ram: rk3399: Add cs0_rw macro Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 19/92] ram: rk3399: Add cs1_rw macro Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 20/92] ram: rk3399: Add bw enc macro Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 21/92] ram: rk3399: Rename sys_reg with sys_reg2 Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 22/92] ram: rk3399: Update cs0_row to use sys_reg3 Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 23/92] ram: rk3399: Update cs1_row " Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 24/92] ram: rk3399: Add cs1_col enc macro Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 25/92] ram: rk3399: Add ddr version " Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 26/92] ram: rk3399: Add ddrtimingC0 Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 27/92] ram: rk3399: Add DdrMode Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 28/92] ram: rk3399: Handle pctl_cfg return type Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 29/92] ram: rk3399: s/tsel_wr_select_n/tsel_wr_select_dq_n Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 30/92] ram: rk3399: s/tsel_wr_select_p/tsel_wr_select_dq_p Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 31/92] ram: rk3399: s/ca_tsel_wr_select_n/tsel_wr_select_ca_n Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 32/92] ram: rk3399: s/ca_tsel_wr_select_p/tsel_wr_select_ca_p Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 33/92] ram: rk3399: Order tsel variables Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 34/92] ram: rk3399: Add phy pctrl reset support Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 35/92] ram: rk3399: Move pwrup_srefresh_exit to dram_info Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 36/92] ram: rk3399: Add pctl start support Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 37/92] ram: rockchip: rk3399: Add cap_info structure Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 38/92] ram: rk3399: s/rk3399_base_params/sdram_base_params Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 39/92] ram: rk3399: Move common sdram structures in common header Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 40/92] arm: include: rockchip: Move dramtypes to " Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 41/92] arm: include: rockchip: Add DDR4 enum Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 42/92] ram: rockchip: Add initial Kconfig Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 43/92] debug_uart: Add printdec Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 44/92] ram: rockchip: Add debug sdram driver Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 45/92] ram: rockchip: debug: Add sdram_print_ddr_info Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 46/92] ram: rockchip: debug: Get the cs capacity Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 47/92] ram: rk3399: debug: Add sdram_print_stride Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 48/92] ram: rk3399: Compute stride for 2 channels Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 49/92] ram: rk3399: Compute stride for 1 channel a Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 50/92] ram: rk3399: Add rank detection support Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 51/92] ram: rk3399: Enable sdram debug functions Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 52/92] rockchip: dts: rk3399: nanopi-neo4: Use DDR3-1866 dtsi Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 53/92] clk: rockchip: rk3399: Fix check patch warnings and checks Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 54/92] clk: rockchip: rk3399: Set 50MHz ddr clock Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 55/92] clk: rockchip: rk3399: Set 400MHz " Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:50 ` [PATCH 56/92] ram: rk3399: Add spaces in pctl_cfg Jagan Teki
2019-06-11 14:50 ` [U-Boot] " Jagan Teki
2019-06-11 14:51 ` [PATCH 57/92] ram: rk3399: Configure phy IO in ds odt Jagan Teki
2019-06-11 14:51 ` [U-Boot] " Jagan Teki
2019-06-11 14:51 ` [PATCH 58/92] ram: rk3399: Add lpddr4 rank mask for cs training Jagan Teki
2019-06-11 14:51 ` [U-Boot] " Jagan Teki
2019-06-11 14:51 ` [PATCH 59/92] ram: rk3399: Add lpddr4 rank mask for wdql training Jagan Teki
2019-06-11 14:51 ` [U-Boot] " Jagan Teki
2019-06-11 14:51 ` [PATCH 60/92] ram: rk3399: Move mode_sel assignment Jagan Teki
2019-06-11 14:51 ` [U-Boot] " Jagan Teki
2019-06-11 14:51 ` [PATCH 61/92] ram: rk3399: Don't wait for PLL lock in lpddr4 Jagan Teki
2019-06-11 14:51 ` [U-Boot] " Jagan Teki
2019-06-11 14:51 ` [PATCH 62/92] ram: rk3399: Avoid two channel ZQ Cal Start at the same time Jagan Teki
2019-06-11 14:51 ` [U-Boot] " Jagan Teki
2019-06-11 14:51 ` [PATCH 63/92] ram: rk3399: Configure PHY_898, PHY_919 for lpddr4 Jagan Teki
2019-06-11 14:51 ` [U-Boot] " Jagan Teki
2019-06-11 14:51 ` [PATCH 64/92] ram: rk3399: Configure BOOSTP_EN, BOOSTN_EN " Jagan Teki
2019-06-11 14:51 ` [U-Boot] " Jagan Teki
2019-06-11 14:51 ` [PATCH 65/92] ram: rk3399: Configure SLEWP_EN, SLEWN_EN " Jagan Teki
2019-06-11 14:51 ` [U-Boot] " Jagan Teki
2019-06-11 14:51 ` [PATCH 66/92] ram: rk3399: Configure PHY RX_CM_INPUT " Jagan Teki
2019-06-11 14:51 ` [U-Boot] " Jagan Teki
2019-06-11 14:51 ` [PATCH 67/92] ram: rk3399: Map chipselect " Jagan Teki
2019-06-11 14:51 ` [U-Boot] " Jagan Teki
2019-06-11 14:51 ` [PATCH 68/92] ram: rk3399: Configure tsel write ca " Jagan Teki
2019-06-11 14:51 ` [U-Boot] " Jagan Teki
2019-06-11 14:51 ` [PATCH 69/92] ram: rk3399: Don't disable dfi dram clk for lpddr4, rank 1 Jagan Teki
2019-06-11 14:51 ` [U-Boot] " Jagan Teki
2019-06-11 14:51 ` [PATCH 70/92] ram: rk3399: Add IO settings Jagan Teki
2019-06-11 14:51 ` [U-Boot] " Jagan Teki
2019-06-11 14:51 ` [PATCH 71/92] ram: sdram: Configure lpddr4 tsel rd, wr based on " Jagan Teki
2019-06-11 14:51 ` [U-Boot] " Jagan Teki
2019-06-11 14:51 ` [PATCH 72/92] ram: rk3399: Add tsel control clock drive Jagan Teki
2019-06-11 14:51 ` [U-Boot] " Jagan Teki
2019-06-11 14:51 ` [PATCH 73/92] ram: rk3399: Configure soc odt support Jagan Teki
2019-06-11 14:51 ` [U-Boot] " Jagan Teki
2019-06-11 14:51 ` [PATCH 74/92] ram: rk3399: Get lpddr4 tsel_rd_en from io settings Jagan Teki
2019-06-11 14:51 ` [U-Boot] " Jagan Teki
2019-06-11 14:51 ` [PATCH 75/92] ram: rk3399: Update lpddr4 vref based on " Jagan Teki
2019-06-11 14:51 ` [U-Boot] " Jagan Teki
2019-06-11 14:51 ` [PATCH 76/92] ram: rk3399: Update lpddr4 mode_sel " Jagan Teki
2019-06-11 14:51 ` [U-Boot] " Jagan Teki
2019-06-11 14:51 ` [PATCH 77/92] ram: rk3399: Update lpddr4 vref_mode_ac Jagan Teki
2019-06-11 14:51 ` [U-Boot] " Jagan Teki
2019-06-11 14:51 ` [PATCH 78/92] ram: rk3399: Add LPPDR4 mr detection Jagan Teki
2019-06-11 14:51 ` [U-Boot] " Jagan Teki
2019-06-11 14:51 ` [PATCH 79/92] arm: include: rockchip: Add rk3399 pmu file Jagan Teki
2019-06-11 14:51 ` [U-Boot] " Jagan Teki
2019-06-11 14:51 ` [PATCH 80/92] rockchip: rk3399: syscon: Add pmu support Jagan Teki
2019-06-11 14:51 ` [U-Boot] " Jagan Teki
2019-06-11 14:51 ` [PATCH 81/92] rockchip: dts: rk3399: Add u-boot,dm-pre-reloc for pmu Jagan Teki
2019-06-11 14:51 ` [U-Boot] [PATCH 81/92] rockchip: dts: rk3399: Add u-boot, dm-pre-reloc " Jagan Teki
2019-06-11 14:51 ` [PATCH 82/92] ram: rk3399: Add LPPDDR4-400 timings inc Jagan Teki
2019-06-11 14:51 ` [U-Boot] " Jagan Teki
2019-06-11 14:51 ` [PATCH 83/92] ram: rk3399: Add LPPDDR4-800 " Jagan Teki
2019-06-11 14:51 ` [U-Boot] " Jagan Teki
2019-06-11 14:51 ` [PATCH 84/92] ram: rk3399: Add lpddr4 set rate support Jagan Teki
2019-06-11 14:51 ` [U-Boot] " Jagan Teki
2019-06-11 14:51 ` [PATCH 85/92] ram: rk3399: Set lpddr4 dq odt Jagan Teki
2019-06-11 14:51 ` [U-Boot] " Jagan Teki
2019-06-11 14:51 ` [PATCH 86/92] ram: rk3399: Set lpddr4 ca odt Jagan Teki
2019-06-11 14:51 ` [U-Boot] " Jagan Teki
2019-06-11 14:51 ` [PATCH 87/92] ram: rk3399: Set lpddr4 MR3 Jagan Teki
2019-06-11 14:51 ` [U-Boot] " Jagan Teki
2019-06-11 14:51 ` [PATCH 88/92] ram: rk3399: Set lpddr4 MR12 Jagan Teki
2019-06-11 14:51 ` [U-Boot] " Jagan Teki
2019-06-11 14:51 ` [PATCH 89/92] ram: rk3399: Set lpddr4 MR14 Jagan Teki
2019-06-11 14:51 ` [U-Boot] " Jagan Teki
2019-06-11 14:51 ` [PATCH 90/92] rockchip: dts: rk3399: Add LPDDR4-100 timings Jagan Teki
2019-06-11 14:51 ` [U-Boot] " Jagan Teki
2019-06-11 14:51 ` [PATCH 91/92] rockchip: dts: rk3399: rockpro64: Use LPDDR4-100 dtsi Jagan Teki
2019-06-11 14:51 ` [U-Boot] " Jagan Teki
2019-06-11 14:51 ` [PATCH 92/92] rockchip: dts: rk3399: rock-pi-4: " Jagan Teki
2019-06-11 14:51 ` [U-Boot] " Jagan Teki
2019-06-11 14:53 ` [PATCH 00/92] ram: rk3399: Add LPDDR4 support Philipp Tomsich
2019-06-11 14:53 ` [U-Boot] " Philipp Tomsich
[not found] ` <349AB0AF-4DEE-4BC8-8FEF-B3DBD34564E4-SN7IsUiht6C/RdPyistoZJqQE7yCjDx5@public.gmane.org>
2019-06-11 15:03 ` Jagan Teki
2019-06-11 15:03 ` [U-Boot] " Jagan Teki
[not found] ` <CAMty3ZDxop1nKHOxGYC0O7b8HL_ybmBSZr1P8gbDpz7eKyOyDw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2019-06-11 15:06 ` Philipp Tomsich
2019-06-11 15:06 ` [U-Boot] " Philipp Tomsich
2019-06-12 15:30 ` Jagan Teki
2019-06-12 15:30 ` [U-Boot] " Jagan Teki
2019-06-12 15:40 ` Philipp Tomsich
2019-06-12 15:40 ` [U-Boot] " Philipp Tomsich
2019-06-13 1:50 ` Kever Yang
2019-06-13 1:50 ` [U-Boot] " Kever Yang
[not found] ` <b4c1bc19-70b5-d6c4-6764-1c1356b47b38-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2019-06-13 6:26 ` Jagan Teki
2019-06-13 6:26 ` [U-Boot] " Jagan Teki
2019-06-13 1:44 ` Kever Yang
2019-06-13 1:44 ` [U-Boot] " Kever Yang
2019-06-13 6:23 ` Jagan Teki
2019-06-13 6:23 ` [U-Boot] " Jagan Teki
This is an external index of several public inboxes,
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