From: Prabhakar <prabhakar.csengg@gmail.com>
To: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Magnus Damm <magnus.damm@gmail.com>,
Heiko Stuebner <heiko@sntech.de>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor.dooley@microchip.com>,
Guo Ren <guoren@kernel.org>
Cc: Jisheng Zhang <jszhang@kernel.org>,
Atish Patra <atishp@rivosinc.com>,
Anup Patel <apatel@ventanamicro.com>,
Andrew Jones <ajones@ventanamicro.com>,
Nathan Chancellor <nathan@kernel.org>,
Philipp Tomsich <philipp.tomsich@vrull.eu>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org,
linux-renesas-soc@vger.kernel.org,
Prabhakar <prabhakar.csengg@gmail.com>,
Biju Das <biju.das.jz@bp.renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [PATCH v4 1/7] riscv: asm: alternative-macros: Introduce ALTERNATIVE_3() macro
Date: Thu, 24 Nov 2022 17:22:01 +0000 [thread overview]
Message-ID: <20221124172207.153718-2-prabhakar.mahadev-lad.rj@bp.renesas.com> (raw)
In-Reply-To: <20221124172207.153718-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Introduce ALTERNATIVE_3() macro.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
RFC v3 -> v4
* New patch
---
arch/riscv/include/asm/alternative-macros.h | 94 +++++++++++++++++++++
1 file changed, 94 insertions(+)
diff --git a/arch/riscv/include/asm/alternative-macros.h b/arch/riscv/include/asm/alternative-macros.h
index ec2f3f1b836f..1caf4306b3d6 100644
--- a/arch/riscv/include/asm/alternative-macros.h
+++ b/arch/riscv/include/asm/alternative-macros.h
@@ -69,6 +69,34 @@
new_c_2, vendor_id_2, errata_id_2, \
IS_ENABLED(CONFIG_k_2)
+.macro __ALTERNATIVE_CFG_3 old_c, new_c_1, vendor_id_1, errata_id_1, enable_1, \
+ new_c_2, vendor_id_2, errata_id_2, enable_2, \
+ new_c_3, vendor_id_3, errata_id_3, enable_3
+886 :
+ .option push
+ .option norvc
+ .option norelax
+ \old_c
+ .option pop
+887 :
+ ALT_NEW_CONTENT \vendor_id_1, \errata_id_1, \enable_1, \new_c_1
+ ALT_NEW_CONTENT \vendor_id_2, \errata_id_2, \enable_2, \new_c_2
+ ALT_NEW_CONTENT \vendor_id_3, \errata_id_3, \enable_3, \new_c_3
+.endm
+
+#define _ALTERNATIVE_CFG_3(old_c, new_c_1, vendor_id_1, errata_id_1, \
+ CONFIG_k_1, \
+ new_c_2, vendor_id_2, errata_id_2, \
+ CONFIG_k_2, \
+ new_c_3, vendor_id_3, errata_id_3, \
+ CONFIG_k_3) \
+ __ALTERNATIVE_CFG_3 old_c, new_c_1, vendor_id_1, errata_id_1, \
+ IS_ENABLED(CONFIG_k_1), \
+ new_c_2, vendor_id_2, errata_id_2, \
+ IS_ENABLED(CONFIG_k_2), \
+ new_c_3, vendor_id_3, errata_id_3, \
+ IS_ENABLED(CONFIG_k_3)
+
#else /* !__ASSEMBLY__ */
#include <asm/asm.h>
@@ -135,6 +163,36 @@
new_c_2, vendor_id_2, errata_id_2, \
IS_ENABLED(CONFIG_k_2))
+#define __ALTERNATIVE_CFG_3(old_c, new_c_1, vendor_id_1, errata_id_1, \
+ enable_1, \
+ new_c_2, vendor_id_2, errata_id_2, \
+ enable_2, \
+ new_c_3, vendor_id_3, errata_id_3, \
+ enable_3) \
+ "886 :\n" \
+ ".option push\n" \
+ ".option norvc\n" \
+ ".option norelax\n" \
+ old_c "\n" \
+ ".option pop\n" \
+ "887 :\n" \
+ ALT_NEW_CONTENT(vendor_id_1, errata_id_1, enable_1, new_c_1) \
+ ALT_NEW_CONTENT(vendor_id_2, errata_id_2, enable_2, new_c_2) \
+ ALT_NEW_CONTENT(vendor_id_3, errata_id_3, enable_3, new_c_3)
+
+#define _ALTERNATIVE_CFG_3(old_c, new_c_1, vendor_id_1, errata_id_1, \
+ CONFIG_k_1, \
+ new_c_2, vendor_id_2, errata_id_2, \
+ CONFIG_k_2, \
+ new_c_3, vendor_id_3, errata_id_3, \
+ CONFIG_k_3) \
+ __ALTERNATIVE_CFG_3(old_c, new_c_1, vendor_id_1, errata_id_1, \
+ IS_ENABLED(CONFIG_k_1), \
+ new_c_2, vendor_id_2, errata_id_2, \
+ IS_ENABLED(CONFIG_k_2), \
+ new_c_3, vendor_id_3, errata_id_3, \
+ IS_ENABLED(CONFIG_k_3))
+
#endif /* __ASSEMBLY__ */
#else /* CONFIG_RISCV_ALTERNATIVE */
@@ -153,6 +211,14 @@
CONFIG_k_2) \
__ALTERNATIVE_CFG old_c
+#define _ALTERNATIVE_CFG_3(old_c, new_c_1, vendor_id_1, errata_id_1, \
+ CONFIG_k_1, \
+ new_c_2, vendor_id_2, errata_id_2, \
+ CONFIG_k_2, \
+ new_c_3, vendor_id_3, errata_id_3, \
+ CONFIG_k_3) \
+ __ALTERNATIVE_CFG old_c
+
#else /* !__ASSEMBLY__ */
#define __ALTERNATIVE_CFG(old_c) \
@@ -167,6 +233,14 @@
CONFIG_k_2) \
__ALTERNATIVE_CFG(old_c)
+#define _ALTERNATIVE_CFG_3(old_c, new_c_1, vendor_id_1, errata_id_1, \
+ CONFIG_k_1, \
+ new_c_2, vendor_id_2, errata_id_2, \
+ CONFIG_k_2, \
+ new_c_3, vendor_id_3, errata_id_3, \
+ CONFIG_k_3) \
+ __ALTERNATIVE_CFG(old_c)
+
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_RISCV_ALTERNATIVE */
@@ -202,4 +276,24 @@
new_content_2, vendor_id_2, \
errata_id_2, CONFIG_k_2)
+/*
+ * A vendor wants to replace an old_content, but another vendor has used
+ * ALTERNATIVE_2() to patch its customized content at the same location. In
+ * this case, this vendor can create a new macro ALTERNATIVE_3() based
+ * on the following sample code and then replace ALTERNATIVE_2() with
+ * ALTERNATIVE_3() to append its customized content.
+ */
+#define ALTERNATIVE_3(old_content, new_content_1, vendor_id_1, \
+ errata_id_1, CONFIG_k_1, \
+ new_content_2, vendor_id_2, \
+ errata_id_2, CONFIG_k_2, \
+ new_content_3, vendor_id_3, \
+ errata_id_3, CONFIG_k_3) \
+ _ALTERNATIVE_CFG_3(old_content, new_content_1, vendor_id_1, \
+ errata_id_1, CONFIG_k_1, \
+ new_content_2, vendor_id_2, \
+ errata_id_2, CONFIG_k_2, \
+ new_content_3, vendor_id_3, \
+ errata_id_3, CONFIG_k_3)
+
#endif
--
2.25.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-11-24 17:23 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-24 17:22 [PATCH v4 0/7] AX45MP: Add support to non-coherent DMA Prabhakar
2022-11-24 17:22 ` Prabhakar [this message]
2022-11-24 18:06 ` [PATCH v4 1/7] riscv: asm: alternative-macros: Introduce ALTERNATIVE_3() macro Heiko Stübner
2022-11-24 19:52 ` Conor Dooley
2022-11-24 19:58 ` Heiko Stübner
2022-11-24 20:05 ` Conor Dooley
2022-11-24 20:08 ` Conor Dooley
2022-11-24 20:44 ` Heiko Stübner
2022-11-25 11:44 ` Andrew Jones
2022-11-25 10:02 ` Lad, Prabhakar
2022-11-25 10:20 ` Heiko Stübner
2022-11-25 10:36 ` Lad, Prabhakar
2022-11-24 17:22 ` [PATCH v4 2/7] riscv: asm: vendorid_list: Add Andes Technology to the vendors list Prabhakar
2022-11-24 18:06 ` Heiko Stübner
2022-11-24 20:09 ` Conor Dooley
2022-11-24 17:22 ` [PATCH v4 3/7] riscv: errata: Add Andes alternative ports Prabhakar
2022-11-24 18:24 ` Heiko Stübner
2022-11-24 19:14 ` Lad, Prabhakar
2022-11-24 20:21 ` Conor Dooley
2022-11-25 10:08 ` Lad, Prabhakar
2022-11-24 17:22 ` [PATCH DO NOT REVIEW v4 4/7] riscv: errata: andes: Fix auipc-jalr addresses in patched alternatives Prabhakar
2022-11-25 1:08 ` Guo Ren
2022-11-25 10:10 ` Lad, Prabhakar
2022-11-24 17:22 ` [PATCH v4 5/7] riscv: mm: dma-noncoherent: Pass direction and operation to ALT_CMO_OP() Prabhakar
2022-11-24 18:29 ` Heiko Stübner
2022-11-24 19:18 ` Lad, Prabhakar
2022-11-25 18:49 ` Samuel Holland
2022-11-25 20:53 ` Lad, Prabhakar
2022-11-24 17:22 ` [PATCH v4 6/7] dt-bindings: cache: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller Prabhakar
2022-11-25 8:16 ` Krzysztof Kozlowski
2022-11-25 10:34 ` Lad, Prabhakar
2022-11-25 11:17 ` Geert Uytterhoeven
2022-11-25 11:45 ` Lad, Prabhakar
2022-11-25 12:12 ` Krzysztof Kozlowski
2022-11-25 12:25 ` Conor Dooley
2022-11-25 12:51 ` Lad, Prabhakar
2022-11-25 13:24 ` Conor Dooley
2022-11-25 15:55 ` Krzysztof Kozlowski
2022-11-25 16:50 ` Conor Dooley
2022-11-25 18:18 ` Lad, Prabhakar
2022-11-24 17:22 ` [PATCH v4 7/7] soc: renesas: Add L2 cache management for RZ/Five SoC Prabhakar
2022-11-24 18:30 ` Heiko Stübner
2022-11-24 19:56 ` Lad, Prabhakar
2022-11-24 20:47 ` Heiko Stübner
2022-11-24 21:31 ` Conor Dooley
2022-11-24 21:34 ` Conor Dooley
2022-11-25 10:50 ` Lad, Prabhakar
2022-11-25 12:16 ` Conor Dooley
2022-11-25 19:43 ` Samuel Holland
2022-11-26 21:09 ` Lad, Prabhakar
2022-11-27 9:55 ` Geert Uytterhoeven
2022-11-28 12:08 ` Lad, Prabhakar
2022-11-29 5:48 ` Samuel Holland
2022-11-29 5:58 ` Samuel Holland
2022-12-01 11:30 ` Lad, Prabhakar
2022-11-24 19:41 ` [PATCH v4 0/7] AX45MP: Add support to non-coherent DMA Conor Dooley
2022-11-24 19:52 ` Lad, Prabhakar
2022-11-24 19:59 ` Conor Dooley
2022-11-25 9:04 ` Geert Uytterhoeven
2022-11-25 10:51 ` Lad, Prabhakar
2022-12-01 23:36 ` Conor Dooley
2022-12-02 9:38 ` Lad, Prabhakar
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20221124172207.153718-2-prabhakar.mahadev-lad.rj@bp.renesas.com \
--to=prabhakar.csengg@gmail.com \
--cc=ajones@ventanamicro.com \
--cc=aou@eecs.berkeley.edu \
--cc=apatel@ventanamicro.com \
--cc=atishp@rivosinc.com \
--cc=biju.das.jz@bp.renesas.com \
--cc=conor.dooley@microchip.com \
--cc=devicetree@vger.kernel.org \
--cc=geert+renesas@glider.be \
--cc=guoren@kernel.org \
--cc=heiko@sntech.de \
--cc=jszhang@kernel.org \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-renesas-soc@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=magnus.damm@gmail.com \
--cc=nathan@kernel.org \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=philipp.tomsich@vrull.eu \
--cc=prabhakar.mahadev-lad.rj@bp.renesas.com \
--cc=robh+dt@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).