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From: Conor Dooley <conor.dooley@microchip.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Cc: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Geert Uytterhoeven <geert+renesas@glider.be>,
	Magnus Damm <magnus.damm@gmail.com>,
	Heiko Stuebner <heiko@sntech.de>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Guo Ren <guoren@kernel.org>, Jisheng Zhang <jszhang@kernel.org>,
	Atish Patra <atishp@rivosinc.com>,
	Anup Patel <apatel@ventanamicro.com>,
	Andrew Jones <ajones@ventanamicro.com>,
	Nathan Chancellor <nathan@kernel.org>,
	Philipp Tomsich <philipp.tomsich@vrull.eu>,
	<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-riscv@lists.infradead.org>,
	<linux-renesas-soc@vger.kernel.org>,
	Biju Das <biju.das.jz@bp.renesas.com>,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH v4 6/7] dt-bindings: cache: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller
Date: Fri, 25 Nov 2022 12:25:10 +0000	[thread overview]
Message-ID: <Y4C0Jn1hl81ZCxOt@wendy> (raw)
In-Reply-To: <9b0f8312-2caa-b9f3-edf3-1b720532f559@linaro.org>

On Fri, Nov 25, 2022 at 01:12:18PM +0100, Krzysztof Kozlowski wrote:
> On 25/11/2022 11:34, Lad, Prabhakar wrote:
> >>> +/* Device, Non-bufferable */
> >>> +#define AX45MP_PMACFG_MTYP_DEV_NON_BUF                       (0 << 2)
> >>> +/* Device, bufferable */
> >>> +#define AX45MP_PMACFG_MTYP_DEV_BUF                   (1 << 2)
> >>> +/* Memory, Non-cacheable, Non-bufferable */
> >>> +#define AX45MP_PMACFG_MTYP_MEM_NON_CACHE_NON_BUF     (2 << 2)
> >>> +/* Memory, Non-cacheable, Bufferable */
> >>> +#define AX45MP_PMACFG_MTYP_MEM_NON_CACHE_BUF         (3 << 2)
> >>
> >> What are all these? They don't look like flags, because 3 = 1 | 2...
> >> they don't look like constants, because we do not use shifts in
> >> constants. Are these some register values? I also do not see the header
> >> being used in the code, so why having a bindings header if it is not
> >> used (DTS is not usage...)?
> >>
> > These are register bit values for the MTYP[5:2] field. The DTS example
> > in the binding doc (above) uses these macros. I haven't included the
> > DTS/I patches with this patchset yet do think I should?
> 
> Then why storing it as bindings? Bindings headers describe the interface
> implemented by drivers and used by DTS, but this is not implemented by
> drivers.

IIUC, some of these properties are non-discoverable attributes of the
cache controller. I see two things that could be done here that are
"better" than #defining bits:
- add an RZ/Five specific compatible and use match data to set the
  attributes which is only possible if the pma-regions are set on a
  per SoC basis
- make pma-regions into a child node, in which andestech,non-cacheable
  andestech,non-bufferable etc are properties of the child node

Prabhakar, does that make sense or am I off with my understanding of the
attributes?

Thanks,
Conor.


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  reply	other threads:[~2022-11-25 12:25 UTC|newest]

Thread overview: 62+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-24 17:22 [PATCH v4 0/7] AX45MP: Add support to non-coherent DMA Prabhakar
2022-11-24 17:22 ` [PATCH v4 1/7] riscv: asm: alternative-macros: Introduce ALTERNATIVE_3() macro Prabhakar
2022-11-24 18:06   ` Heiko Stübner
2022-11-24 19:52   ` Conor Dooley
2022-11-24 19:58     ` Heiko Stübner
2022-11-24 20:05       ` Conor Dooley
2022-11-24 20:08         ` Conor Dooley
2022-11-24 20:44           ` Heiko Stübner
2022-11-25 11:44         ` Andrew Jones
2022-11-25 10:02       ` Lad, Prabhakar
2022-11-25 10:20         ` Heiko Stübner
2022-11-25 10:36           ` Lad, Prabhakar
2022-11-24 17:22 ` [PATCH v4 2/7] riscv: asm: vendorid_list: Add Andes Technology to the vendors list Prabhakar
2022-11-24 18:06   ` Heiko Stübner
2022-11-24 20:09   ` Conor Dooley
2022-11-24 17:22 ` [PATCH v4 3/7] riscv: errata: Add Andes alternative ports Prabhakar
2022-11-24 18:24   ` Heiko Stübner
2022-11-24 19:14     ` Lad, Prabhakar
2022-11-24 20:21   ` Conor Dooley
2022-11-25 10:08     ` Lad, Prabhakar
2022-11-24 17:22 ` [PATCH DO NOT REVIEW v4 4/7] riscv: errata: andes: Fix auipc-jalr addresses in patched alternatives Prabhakar
2022-11-25  1:08   ` Guo Ren
2022-11-25 10:10     ` Lad, Prabhakar
2022-11-24 17:22 ` [PATCH v4 5/7] riscv: mm: dma-noncoherent: Pass direction and operation to ALT_CMO_OP() Prabhakar
2022-11-24 18:29   ` Heiko Stübner
2022-11-24 19:18     ` Lad, Prabhakar
2022-11-25 18:49       ` Samuel Holland
2022-11-25 20:53         ` Lad, Prabhakar
2022-11-24 17:22 ` [PATCH v4 6/7] dt-bindings: cache: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller Prabhakar
2022-11-25  8:16   ` Krzysztof Kozlowski
2022-11-25 10:34     ` Lad, Prabhakar
2022-11-25 11:17       ` Geert Uytterhoeven
2022-11-25 11:45         ` Lad, Prabhakar
2022-11-25 12:12       ` Krzysztof Kozlowski
2022-11-25 12:25         ` Conor Dooley [this message]
2022-11-25 12:51           ` Lad, Prabhakar
2022-11-25 13:24             ` Conor Dooley
2022-11-25 15:55           ` Krzysztof Kozlowski
2022-11-25 16:50             ` Conor Dooley
2022-11-25 18:18         ` Lad, Prabhakar
2022-11-24 17:22 ` [PATCH v4 7/7] soc: renesas: Add L2 cache management for RZ/Five SoC Prabhakar
2022-11-24 18:30   ` Heiko Stübner
2022-11-24 19:56     ` Lad, Prabhakar
2022-11-24 20:47       ` Heiko Stübner
2022-11-24 21:31   ` Conor Dooley
2022-11-24 21:34     ` Conor Dooley
2022-11-25 10:50     ` Lad, Prabhakar
2022-11-25 12:16       ` Conor Dooley
2022-11-25 19:43   ` Samuel Holland
2022-11-26 21:09     ` Lad, Prabhakar
2022-11-27  9:55       ` Geert Uytterhoeven
2022-11-28 12:08         ` Lad, Prabhakar
2022-11-29  5:48           ` Samuel Holland
2022-11-29  5:58       ` Samuel Holland
2022-12-01 11:30         ` Lad, Prabhakar
2022-11-24 19:41 ` [PATCH v4 0/7] AX45MP: Add support to non-coherent DMA Conor Dooley
2022-11-24 19:52   ` Lad, Prabhakar
2022-11-24 19:59     ` Conor Dooley
2022-11-25  9:04 ` Geert Uytterhoeven
2022-11-25 10:51   ` Lad, Prabhakar
2022-12-01 23:36 ` Conor Dooley
2022-12-02  9:38   ` Lad, Prabhakar

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