From: "Heiko Stübner" <heiko@sntech.de>
To: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Magnus Damm <magnus.damm@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor.dooley@microchip.com>,
Guo Ren <guoren@kernel.org>,
Prabhakar <prabhakar.csengg@gmail.com>
Cc: Jisheng Zhang <jszhang@kernel.org>,
Atish Patra <atishp@rivosinc.com>,
Anup Patel <apatel@ventanamicro.com>,
Andrew Jones <ajones@ventanamicro.com>,
Nathan Chancellor <nathan@kernel.org>,
Philipp Tomsich <philipp.tomsich@vrull.eu>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org,
linux-renesas-soc@vger.kernel.org,
Prabhakar <prabhakar.csengg@gmail.com>,
Biju Das <biju.das.jz@bp.renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH v4 5/7] riscv: mm: dma-noncoherent: Pass direction and operation to ALT_CMO_OP()
Date: Thu, 24 Nov 2022 19:29:35 +0100 [thread overview]
Message-ID: <3689906.Lt9SDvczpP@diego> (raw)
In-Reply-To: <20221124172207.153718-6-prabhakar.mahadev-lad.rj@bp.renesas.com>
Am Donnerstag, 24. November 2022, 18:22:05 CET schrieb Prabhakar:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Pass direction and operation to ALT_CMO_OP() macro.
>
> This is in preparation for adding errata for the Andes CPU core.
can you provide more explanation why that is necessary please?
I guess you want to use different cache operations for some cases?
Thanks
Heiko
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> RFC v3 -> v4
> * New patch
> ---
> arch/riscv/include/asm/cacheflush.h | 4 ++++
> arch/riscv/include/asm/errata_list.h | 8 ++++++--
> arch/riscv/mm/dma-noncoherent.c | 15 ++++++++++-----
> 3 files changed, 20 insertions(+), 7 deletions(-)
>
> diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h
> index f6fbe7042f1c..4a04d1be7c67 100644
> --- a/arch/riscv/include/asm/cacheflush.h
> +++ b/arch/riscv/include/asm/cacheflush.h
> @@ -8,6 +8,10 @@
>
> #include <linux/mm.h>
>
> +#define NON_COHERENT_SYNC_DMA_FOR_DEVICE 0
> +#define NON_COHERENT_SYNC_DMA_FOR_CPU 1
> +#define NON_COHERENT_DMA_PREP 2
> +
> static inline void local_flush_icache_all(void)
> {
> asm volatile ("fence.i" ::: "memory");
> diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
> index 2ba7e6e74540..48e899a8e7a9 100644
> --- a/arch/riscv/include/asm/errata_list.h
> +++ b/arch/riscv/include/asm/errata_list.h
> @@ -124,7 +124,7 @@ asm volatile(ALTERNATIVE( \
> #define THEAD_flush_A0 ".long 0x0275000b"
> #define THEAD_SYNC_S ".long 0x0190000b"
>
> -#define ALT_CMO_OP(_op, _start, _size, _cachesize) \
> +#define ALT_CMO_OP(_op, _start, _size, _cachesize, _dir, _ops) \
> asm volatile(ALTERNATIVE_2( \
> __nops(6), \
> "mv a0, %1\n\t" \
> @@ -146,7 +146,11 @@ asm volatile(ALTERNATIVE_2( \
> ERRATA_THEAD_CMO, CONFIG_ERRATA_THEAD_CMO) \
> : : "r"(_cachesize), \
> "r"((unsigned long)(_start) & ~((_cachesize) - 1UL)), \
> - "r"((unsigned long)(_start) + (_size)) \
> + "r"((unsigned long)(_start) + (_size)), \
> + "r"((unsigned long)(_start)), \
> + "r"((unsigned long)(_size)), \
> + "r"((unsigned long)(_dir)), \
> + "r"((unsigned long)(_ops)) \
> : "a0")
>
> #define THEAD_C9XX_RV_IRQ_PMU 17
> diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c
> index d919efab6eba..e2b82034f504 100644
> --- a/arch/riscv/mm/dma-noncoherent.c
> +++ b/arch/riscv/mm/dma-noncoherent.c
> @@ -19,13 +19,16 @@ void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
>
> switch (dir) {
> case DMA_TO_DEVICE:
> - ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size);
> + ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size,
> + dir, NON_COHERENT_SYNC_DMA_FOR_DEVICE);
> break;
> case DMA_FROM_DEVICE:
> - ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size);
> + ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size,
> + dir, NON_COHERENT_SYNC_DMA_FOR_DEVICE);
> break;
> case DMA_BIDIRECTIONAL:
> - ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size);
> + ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size,
> + dir, NON_COHERENT_SYNC_DMA_FOR_DEVICE);
> break;
> default:
> break;
> @@ -42,7 +45,8 @@ void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
> break;
> case DMA_FROM_DEVICE:
> case DMA_BIDIRECTIONAL:
> - ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size);
> + ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size,
> + dir, NON_COHERENT_SYNC_DMA_FOR_CPU);
> break;
> default:
> break;
> @@ -53,7 +57,8 @@ void arch_dma_prep_coherent(struct page *page, size_t size)
> {
> void *flush_addr = page_address(page);
>
> - ALT_CMO_OP(flush, flush_addr, size, riscv_cbom_block_size);
> + ALT_CMO_OP(flush, flush_addr, size, riscv_cbom_block_size,
> + 0, NON_COHERENT_DMA_PREP);
> }
>
> void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
>
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next prev parent reply other threads:[~2022-11-24 18:30 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-24 17:22 [PATCH v4 0/7] AX45MP: Add support to non-coherent DMA Prabhakar
2022-11-24 17:22 ` [PATCH v4 1/7] riscv: asm: alternative-macros: Introduce ALTERNATIVE_3() macro Prabhakar
2022-11-24 18:06 ` Heiko Stübner
2022-11-24 19:52 ` Conor Dooley
2022-11-24 19:58 ` Heiko Stübner
2022-11-24 20:05 ` Conor Dooley
2022-11-24 20:08 ` Conor Dooley
2022-11-24 20:44 ` Heiko Stübner
2022-11-25 11:44 ` Andrew Jones
2022-11-25 10:02 ` Lad, Prabhakar
2022-11-25 10:20 ` Heiko Stübner
2022-11-25 10:36 ` Lad, Prabhakar
2022-11-24 17:22 ` [PATCH v4 2/7] riscv: asm: vendorid_list: Add Andes Technology to the vendors list Prabhakar
2022-11-24 18:06 ` Heiko Stübner
2022-11-24 20:09 ` Conor Dooley
2022-11-24 17:22 ` [PATCH v4 3/7] riscv: errata: Add Andes alternative ports Prabhakar
2022-11-24 18:24 ` Heiko Stübner
2022-11-24 19:14 ` Lad, Prabhakar
2022-11-24 20:21 ` Conor Dooley
2022-11-25 10:08 ` Lad, Prabhakar
2022-11-24 17:22 ` [PATCH DO NOT REVIEW v4 4/7] riscv: errata: andes: Fix auipc-jalr addresses in patched alternatives Prabhakar
2022-11-25 1:08 ` Guo Ren
2022-11-25 10:10 ` Lad, Prabhakar
2022-11-24 17:22 ` [PATCH v4 5/7] riscv: mm: dma-noncoherent: Pass direction and operation to ALT_CMO_OP() Prabhakar
2022-11-24 18:29 ` Heiko Stübner [this message]
2022-11-24 19:18 ` Lad, Prabhakar
2022-11-25 18:49 ` Samuel Holland
2022-11-25 20:53 ` Lad, Prabhakar
2022-11-24 17:22 ` [PATCH v4 6/7] dt-bindings: cache: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller Prabhakar
2022-11-25 8:16 ` Krzysztof Kozlowski
2022-11-25 10:34 ` Lad, Prabhakar
2022-11-25 11:17 ` Geert Uytterhoeven
2022-11-25 11:45 ` Lad, Prabhakar
2022-11-25 12:12 ` Krzysztof Kozlowski
2022-11-25 12:25 ` Conor Dooley
2022-11-25 12:51 ` Lad, Prabhakar
2022-11-25 13:24 ` Conor Dooley
2022-11-25 15:55 ` Krzysztof Kozlowski
2022-11-25 16:50 ` Conor Dooley
2022-11-25 18:18 ` Lad, Prabhakar
2022-11-24 17:22 ` [PATCH v4 7/7] soc: renesas: Add L2 cache management for RZ/Five SoC Prabhakar
2022-11-24 18:30 ` Heiko Stübner
2022-11-24 19:56 ` Lad, Prabhakar
2022-11-24 20:47 ` Heiko Stübner
2022-11-24 21:31 ` Conor Dooley
2022-11-24 21:34 ` Conor Dooley
2022-11-25 10:50 ` Lad, Prabhakar
2022-11-25 12:16 ` Conor Dooley
2022-11-25 19:43 ` Samuel Holland
2022-11-26 21:09 ` Lad, Prabhakar
2022-11-27 9:55 ` Geert Uytterhoeven
2022-11-28 12:08 ` Lad, Prabhakar
2022-11-29 5:48 ` Samuel Holland
2022-11-29 5:58 ` Samuel Holland
2022-12-01 11:30 ` Lad, Prabhakar
2022-11-24 19:41 ` [PATCH v4 0/7] AX45MP: Add support to non-coherent DMA Conor Dooley
2022-11-24 19:52 ` Lad, Prabhakar
2022-11-24 19:59 ` Conor Dooley
2022-11-25 9:04 ` Geert Uytterhoeven
2022-11-25 10:51 ` Lad, Prabhakar
2022-12-01 23:36 ` Conor Dooley
2022-12-02 9:38 ` Lad, Prabhakar
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