From: Samuel Holland <samuel@sholland.org>
To: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>,
Geert Uytterhoeven <geert@linux-m68k.org>
Cc: opensbi@lists.infradead.org, Anup Patel <apatel@ventanamicro.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Magnus Damm <magnus.damm@gmail.com>,
Heiko Stuebner <heiko@sntech.de>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor.dooley@microchip.com>,
Guo Ren <guoren@kernel.org>, Jisheng Zhang <jszhang@kernel.org>,
Atish Patra <atishp@rivosinc.com>,
Andrew Jones <ajones@ventanamicro.com>,
Nathan Chancellor <nathan@kernel.org>,
Philipp Tomsich <philipp.tomsich@vrull.eu>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org,
linux-renesas-soc@vger.kernel.org,
Biju Das <biju.das.jz@bp.renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH v4 7/7] soc: renesas: Add L2 cache management for RZ/Five SoC
Date: Mon, 28 Nov 2022 23:48:32 -0600 [thread overview]
Message-ID: <df0fed9d-6d0a-3e76-1ebf-920e4d19d624@sholland.org> (raw)
In-Reply-To: <CA+V-a8s5mZoLMhjjpo_89taaBx+M_EwXMZUu-TUpZc8Q3bw4ug@mail.gmail.com>
On 11/28/22 06:08, Lad, Prabhakar wrote:
> Hi Geert,
>
> On Sun, Nov 27, 2022 at 9:55 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>>
>> Hi Prabhakar,
>>
>> On Sat, Nov 26, 2022 at 10:10 PM Lad, Prabhakar
>> <prabhakar.csengg@gmail.com> wrote:
>>> On Fri, Nov 25, 2022 at 7:43 PM Samuel Holland <samuel@sholland.org> wrote:
>>>> On 11/24/22 11:22, Prabhakar wrote:
>>>>> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>>>>>
>>>>> On the AX45MP core, cache coherency is a specification option so it may
>>>>> not be supported. In this case DMA will fail. As a workaround, firstly we
>>>>> allocate a global dma coherent pool from which DMA allocations are taken
>>>>> and marked as non-cacheable + bufferable using the PMA region as specified
>>>>> in the device tree. Synchronization callbacks are implemented to
>>>>> synchronize when doing DMA transactions.
>>>>>
>>>>> The Andes AX45MP core has a Programmable Physical Memory Attributes (PMA)
>>>>> block that allows dynamic adjustment of memory attributes in the runtime.
>>>>> It contains a configurable amount of PMA entries implemented as CSR
>>>>> registers to control the attributes of memory locations in interest.
>>>>>
>>>>> Below are the memory attributes supported:
>>>>> * Device, Non-bufferable
>>>>> * Device, bufferable
>>>>> * Memory, Non-cacheable, Non-bufferable
>>>>> * Memory, Non-cacheable, Bufferable
>>>>> * Memory, Write-back, No-allocate
>>>>> * Memory, Write-back, Read-allocate
>>>>> * Memory, Write-back, Write-allocate
>>>>> * Memory, Write-back, Read and Write-allocate
>>>>>
>>>>> This patch adds support to configure the memory attributes of the memory
>>>>> regions as passed from the l2 cache node and exposes the cache management
>>>>> ops.
>>>>
>>>> Forgive my ignorance, but why do you need both a DMA pool and explicit
>>>> cache maintenance? Wouldn't the purpose of marking a memory region as
>>>> permanently non-cacheable be to avoid cache maintenance? And likewise,
>>>> if you are doing cache maintenance anyway, why does it matter if/how the
>>>> memory is cacheable?
>>>>
>>> "Memory, Non-cacheable, Bufferable" raises an AXI signal for
>>> transactions hence needing SW implementation for cache maintenance.
>>>
>>>>> More info about PMA (section 10.3):
>>>>> Link: http://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
>>>>>
>>>>> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>>
>>>>> +static int ax45mp_configure_pma_regions(struct device_node *np)
>>>>> +{
>>>>> + const char *propname = "andestech,pma-regions";
>>>>> + u32 start, size, flags;
>>>>> + unsigned int entry_id;
>>>>> + unsigned int i;
>>>>> + int count;
>>>>> + int ret;
>>>>> +
>>>>> + count = of_property_count_elems_of_size(np, propname, sizeof(u32) * 3);
>>>>> + if (count < 0)
>>>>> + return count;
>>>>> +
>>>>> + if (count > AX45MP_MAX_PMA_REGIONS)
>>>>> + return -EINVAL;
>>>>> +
>>>>> + for (i = 0, entry_id = 0 ; entry_id < count ; i += 3, entry_id++) {
>>>>> + of_property_read_u32_index(np, propname, i, &start);
>>>>> + of_property_read_u32_index(np, propname, i + 1, &size);
>>>>> + of_property_read_u32_index(np, propname, i + 2, &flags);
>>>>> + ret = ax45mp_sbi_set_pma(start, size, flags, entry_id);
>>>>> + if (!ret)
>>>>> + pr_err("Failed to setup PMA region 0x%x - 0x%x flags: 0x%x",
>>>>> + start, start + size, flags);
>>>>> + }
>>>>> +
>>>>> + return 0;
>>>>> +}
>>>>
>>>> If firmware support is required to set up these PMA regions, why is
>>>> Linux doing this at all? The firmware has access to the devicetree as
>>>> well. It can set this up before entering S-mode, and then you don't need
>>>> to expose this capability via an SBI extension. In fact, firmware could
>>>> generate the reserved-memory node based on these regions at runtime (or
>>>> vice versa).
>>>>
>>> That's a good point. I'll do some research on this and get back.
>>>
>>> Btw are there any existing examples where the firmware adds DT nodes?
>>
>> /memory, reserved-memory, optee on ARM, RPC status on R-Car Gen3/4, ...
>>
> On the TF-A we pass the FDT blob to u-boot and this does the magic.
>
> On the RISC-V what would be the correct approach?
> - We setup the PMA regions in OpenSBI
> - We provide a vendor specific EXT to check if the PMA is setup
> - In u-boot ft_board_setup() callback add the reserved-memory node
>
> Does the above approach sound good or is there a better approach I'm missing?
My suggestion was to fix up the DT in OpenSBI itself. See
lib/utils/fdt/fdt_fixup.c in the OpenSBI source tree. There is also a
platform hook for this. Then OpenSBI passes the FDT to U-Boot, and
U-Boot passes it on to Linux. No SBI extension is needed in that case.
If you optionally want your U-Boot to support loading a replacement FDT
from disk, then ft_board_setup() would need to copy the reserved-memory
nodes from U-Boot's control FDT to the loaded FDT. But this logic is the
same for all reserved-memory nodes, including the one OpenSBI adds
already. U-Boot has some code for this copying which you could reuse.
Regards,
Samuel
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next prev parent reply other threads:[~2022-11-29 5:48 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-24 17:22 [PATCH v4 0/7] AX45MP: Add support to non-coherent DMA Prabhakar
2022-11-24 17:22 ` [PATCH v4 1/7] riscv: asm: alternative-macros: Introduce ALTERNATIVE_3() macro Prabhakar
2022-11-24 18:06 ` Heiko Stübner
2022-11-24 19:52 ` Conor Dooley
2022-11-24 19:58 ` Heiko Stübner
2022-11-24 20:05 ` Conor Dooley
2022-11-24 20:08 ` Conor Dooley
2022-11-24 20:44 ` Heiko Stübner
2022-11-25 11:44 ` Andrew Jones
2022-11-25 10:02 ` Lad, Prabhakar
2022-11-25 10:20 ` Heiko Stübner
2022-11-25 10:36 ` Lad, Prabhakar
2022-11-24 17:22 ` [PATCH v4 2/7] riscv: asm: vendorid_list: Add Andes Technology to the vendors list Prabhakar
2022-11-24 18:06 ` Heiko Stübner
2022-11-24 20:09 ` Conor Dooley
2022-11-24 17:22 ` [PATCH v4 3/7] riscv: errata: Add Andes alternative ports Prabhakar
2022-11-24 18:24 ` Heiko Stübner
2022-11-24 19:14 ` Lad, Prabhakar
2022-11-24 20:21 ` Conor Dooley
2022-11-25 10:08 ` Lad, Prabhakar
2022-11-24 17:22 ` [PATCH DO NOT REVIEW v4 4/7] riscv: errata: andes: Fix auipc-jalr addresses in patched alternatives Prabhakar
2022-11-25 1:08 ` Guo Ren
2022-11-25 10:10 ` Lad, Prabhakar
2022-11-24 17:22 ` [PATCH v4 5/7] riscv: mm: dma-noncoherent: Pass direction and operation to ALT_CMO_OP() Prabhakar
2022-11-24 18:29 ` Heiko Stübner
2022-11-24 19:18 ` Lad, Prabhakar
2022-11-25 18:49 ` Samuel Holland
2022-11-25 20:53 ` Lad, Prabhakar
2022-11-24 17:22 ` [PATCH v4 6/7] dt-bindings: cache: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller Prabhakar
2022-11-25 8:16 ` Krzysztof Kozlowski
2022-11-25 10:34 ` Lad, Prabhakar
2022-11-25 11:17 ` Geert Uytterhoeven
2022-11-25 11:45 ` Lad, Prabhakar
2022-11-25 12:12 ` Krzysztof Kozlowski
2022-11-25 12:25 ` Conor Dooley
2022-11-25 12:51 ` Lad, Prabhakar
2022-11-25 13:24 ` Conor Dooley
2022-11-25 15:55 ` Krzysztof Kozlowski
2022-11-25 16:50 ` Conor Dooley
2022-11-25 18:18 ` Lad, Prabhakar
2022-11-24 17:22 ` [PATCH v4 7/7] soc: renesas: Add L2 cache management for RZ/Five SoC Prabhakar
2022-11-24 18:30 ` Heiko Stübner
2022-11-24 19:56 ` Lad, Prabhakar
2022-11-24 20:47 ` Heiko Stübner
2022-11-24 21:31 ` Conor Dooley
2022-11-24 21:34 ` Conor Dooley
2022-11-25 10:50 ` Lad, Prabhakar
2022-11-25 12:16 ` Conor Dooley
2022-11-25 19:43 ` Samuel Holland
2022-11-26 21:09 ` Lad, Prabhakar
2022-11-27 9:55 ` Geert Uytterhoeven
2022-11-28 12:08 ` Lad, Prabhakar
2022-11-29 5:48 ` Samuel Holland [this message]
2022-11-29 5:58 ` Samuel Holland
2022-12-01 11:30 ` Lad, Prabhakar
2022-11-24 19:41 ` [PATCH v4 0/7] AX45MP: Add support to non-coherent DMA Conor Dooley
2022-11-24 19:52 ` Lad, Prabhakar
2022-11-24 19:59 ` Conor Dooley
2022-11-25 9:04 ` Geert Uytterhoeven
2022-11-25 10:51 ` Lad, Prabhakar
2022-12-01 23:36 ` Conor Dooley
2022-12-02 9:38 ` Lad, Prabhakar
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