From: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
To: Conor Dooley <conor.dooley@microchip.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Magnus Damm <magnus.damm@gmail.com>,
Heiko Stuebner <heiko@sntech.de>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Guo Ren <guoren@kernel.org>, Jisheng Zhang <jszhang@kernel.org>,
Atish Patra <atishp@rivosinc.com>,
Anup Patel <apatel@ventanamicro.com>,
Andrew Jones <ajones@ventanamicro.com>,
Nathan Chancellor <nathan@kernel.org>,
Philipp Tomsich <philipp.tomsich@vrull.eu>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org,
linux-renesas-soc@vger.kernel.org,
Biju Das <biju.das.jz@bp.renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH v4 6/7] dt-bindings: cache: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller
Date: Fri, 25 Nov 2022 12:51:34 +0000 [thread overview]
Message-ID: <CA+V-a8u_R9X10AQ2dV9ieDGx7OJPhLRW3ENAoRP2fqVQTVodPw@mail.gmail.com> (raw)
In-Reply-To: <Y4C0Jn1hl81ZCxOt@wendy>
Hi Conor,
On Fri, Nov 25, 2022 at 12:25 PM Conor Dooley
<conor.dooley@microchip.com> wrote:
>
> On Fri, Nov 25, 2022 at 01:12:18PM +0100, Krzysztof Kozlowski wrote:
> > On 25/11/2022 11:34, Lad, Prabhakar wrote:
> > >>> +/* Device, Non-bufferable */
> > >>> +#define AX45MP_PMACFG_MTYP_DEV_NON_BUF (0 << 2)
> > >>> +/* Device, bufferable */
> > >>> +#define AX45MP_PMACFG_MTYP_DEV_BUF (1 << 2)
> > >>> +/* Memory, Non-cacheable, Non-bufferable */
> > >>> +#define AX45MP_PMACFG_MTYP_MEM_NON_CACHE_NON_BUF (2 << 2)
> > >>> +/* Memory, Non-cacheable, Bufferable */
> > >>> +#define AX45MP_PMACFG_MTYP_MEM_NON_CACHE_BUF (3 << 2)
> > >>
> > >> What are all these? They don't look like flags, because 3 = 1 | 2...
> > >> they don't look like constants, because we do not use shifts in
> > >> constants. Are these some register values? I also do not see the header
> > >> being used in the code, so why having a bindings header if it is not
> > >> used (DTS is not usage...)?
> > >>
> > > These are register bit values for the MTYP[5:2] field. The DTS example
> > > in the binding doc (above) uses these macros. I haven't included the
> > > DTS/I patches with this patchset yet do think I should?
> >
> > Then why storing it as bindings? Bindings headers describe the interface
> > implemented by drivers and used by DTS, but this is not implemented by
> > drivers.
>
> IIUC, some of these properties are non-discoverable attributes of the
> cache controller. I see two things that could be done here that are
> "better" than #defining bits:
> - add an RZ/Five specific compatible and use match data to set the
> attributes which is only possible if the pma-regions are set on a
> per SoC basis
> - make pma-regions into a child node, in which andestech,non-cacheable
> andestech,non-bufferable etc are properties of the child node
>
For now the only way to get DMA working without IOCP is to have
AX45MP_PMACFG_MTYP_MEM_NON_CACHE_BUF. But for future purposes I have
introduced the other available flags.
So maybe for now we could just have this flag
andestech,mem-non-cacheable-bufferable in the binding doc.
cache-controller@2010000 {
reg = <0x13400000 0x100000>;
compatible = "andestech,ax45mp-cache", "cache";
interrupts = <508 IRQ_TYPE_LEVEL_HIGH>;
cache-line-size = <64>;
cache-level = <2>;
cache-sets = <1024>;
cache-size = <262144>;
cache-unified;
andestech,pma-region@0x58000000 {
reg = <0x58000000 0x08000000>;
andestech,mem-non-cacheable-bufferable;
};
andestech,pma-region@0xdeadbeef {
reg = <0xdeadbeef 0x08000000>;
andestech,mem-non-cacheable-bufferable;
};
....
};
Did I chime in this time?
Cheers,
Prabhakar
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-11-25 12:52 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-24 17:22 [PATCH v4 0/7] AX45MP: Add support to non-coherent DMA Prabhakar
2022-11-24 17:22 ` [PATCH v4 1/7] riscv: asm: alternative-macros: Introduce ALTERNATIVE_3() macro Prabhakar
2022-11-24 18:06 ` Heiko Stübner
2022-11-24 19:52 ` Conor Dooley
2022-11-24 19:58 ` Heiko Stübner
2022-11-24 20:05 ` Conor Dooley
2022-11-24 20:08 ` Conor Dooley
2022-11-24 20:44 ` Heiko Stübner
2022-11-25 11:44 ` Andrew Jones
2022-11-25 10:02 ` Lad, Prabhakar
2022-11-25 10:20 ` Heiko Stübner
2022-11-25 10:36 ` Lad, Prabhakar
2022-11-24 17:22 ` [PATCH v4 2/7] riscv: asm: vendorid_list: Add Andes Technology to the vendors list Prabhakar
2022-11-24 18:06 ` Heiko Stübner
2022-11-24 20:09 ` Conor Dooley
2022-11-24 17:22 ` [PATCH v4 3/7] riscv: errata: Add Andes alternative ports Prabhakar
2022-11-24 18:24 ` Heiko Stübner
2022-11-24 19:14 ` Lad, Prabhakar
2022-11-24 20:21 ` Conor Dooley
2022-11-25 10:08 ` Lad, Prabhakar
2022-11-24 17:22 ` [PATCH DO NOT REVIEW v4 4/7] riscv: errata: andes: Fix auipc-jalr addresses in patched alternatives Prabhakar
2022-11-25 1:08 ` Guo Ren
2022-11-25 10:10 ` Lad, Prabhakar
2022-11-24 17:22 ` [PATCH v4 5/7] riscv: mm: dma-noncoherent: Pass direction and operation to ALT_CMO_OP() Prabhakar
2022-11-24 18:29 ` Heiko Stübner
2022-11-24 19:18 ` Lad, Prabhakar
2022-11-25 18:49 ` Samuel Holland
2022-11-25 20:53 ` Lad, Prabhakar
2022-11-24 17:22 ` [PATCH v4 6/7] dt-bindings: cache: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller Prabhakar
2022-11-25 8:16 ` Krzysztof Kozlowski
2022-11-25 10:34 ` Lad, Prabhakar
2022-11-25 11:17 ` Geert Uytterhoeven
2022-11-25 11:45 ` Lad, Prabhakar
2022-11-25 12:12 ` Krzysztof Kozlowski
2022-11-25 12:25 ` Conor Dooley
2022-11-25 12:51 ` Lad, Prabhakar [this message]
2022-11-25 13:24 ` Conor Dooley
2022-11-25 15:55 ` Krzysztof Kozlowski
2022-11-25 16:50 ` Conor Dooley
2022-11-25 18:18 ` Lad, Prabhakar
2022-11-24 17:22 ` [PATCH v4 7/7] soc: renesas: Add L2 cache management for RZ/Five SoC Prabhakar
2022-11-24 18:30 ` Heiko Stübner
2022-11-24 19:56 ` Lad, Prabhakar
2022-11-24 20:47 ` Heiko Stübner
2022-11-24 21:31 ` Conor Dooley
2022-11-24 21:34 ` Conor Dooley
2022-11-25 10:50 ` Lad, Prabhakar
2022-11-25 12:16 ` Conor Dooley
2022-11-25 19:43 ` Samuel Holland
2022-11-26 21:09 ` Lad, Prabhakar
2022-11-27 9:55 ` Geert Uytterhoeven
2022-11-28 12:08 ` Lad, Prabhakar
2022-11-29 5:48 ` Samuel Holland
2022-11-29 5:58 ` Samuel Holland
2022-12-01 11:30 ` Lad, Prabhakar
2022-11-24 19:41 ` [PATCH v4 0/7] AX45MP: Add support to non-coherent DMA Conor Dooley
2022-11-24 19:52 ` Lad, Prabhakar
2022-11-24 19:59 ` Conor Dooley
2022-11-25 9:04 ` Geert Uytterhoeven
2022-11-25 10:51 ` Lad, Prabhakar
2022-12-01 23:36 ` Conor Dooley
2022-12-02 9:38 ` Lad, Prabhakar
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=CA+V-a8u_R9X10AQ2dV9ieDGx7OJPhLRW3ENAoRP2fqVQTVodPw@mail.gmail.com \
--to=prabhakar.csengg@gmail.com \
--cc=ajones@ventanamicro.com \
--cc=aou@eecs.berkeley.edu \
--cc=apatel@ventanamicro.com \
--cc=atishp@rivosinc.com \
--cc=biju.das.jz@bp.renesas.com \
--cc=conor.dooley@microchip.com \
--cc=devicetree@vger.kernel.org \
--cc=geert+renesas@glider.be \
--cc=guoren@kernel.org \
--cc=heiko@sntech.de \
--cc=jszhang@kernel.org \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=krzysztof.kozlowski@linaro.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-renesas-soc@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=magnus.damm@gmail.com \
--cc=nathan@kernel.org \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=philipp.tomsich@vrull.eu \
--cc=prabhakar.mahadev-lad.rj@bp.renesas.com \
--cc=robh+dt@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).