From: Guo Ren <guoren@kernel.org>
To: Prabhakar <prabhakar.csengg@gmail.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Magnus Damm <magnus.damm@gmail.com>,
Heiko Stuebner <heiko@sntech.de>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor.dooley@microchip.com>,
Jisheng Zhang <jszhang@kernel.org>,
Atish Patra <atishp@rivosinc.com>,
Anup Patel <apatel@ventanamicro.com>,
Andrew Jones <ajones@ventanamicro.com>,
Nathan Chancellor <nathan@kernel.org>,
Philipp Tomsich <philipp.tomsich@vrull.eu>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org,
linux-renesas-soc@vger.kernel.org,
Biju Das <biju.das.jz@bp.renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH DO NOT REVIEW v4 4/7] riscv: errata: andes: Fix auipc-jalr addresses in patched alternatives
Date: Fri, 25 Nov 2022 09:08:48 +0800 [thread overview]
Message-ID: <CAJF2gTT7XEXmLWpP6nnSNRms9kj2NQR2dOA5N+V2UmnsurJogQ@mail.gmail.com> (raw)
In-Reply-To: <20221124172207.153718-5-prabhakar.mahadev-lad.rj@bp.renesas.com>
On Fri, Nov 25, 2022 at 1:22 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
>
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> This patch is added just for building purpose, as patch [0] will export
> this in its next version.
>
> https://patchwork.kernel.org/project/linux-riscv/patch/20221110164924.529386-6-heiko@sntech.de/
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> Note, as Heiko will be exporting riscv_alternative_fix_auipc_jalr() function
> so that it can be used other erratas Ive just included for compilation.
> ---
> arch/riscv/errata/andes/errata.c | 71 ++++++++++++++++++++++++++++++++
> 1 file changed, 71 insertions(+)
>
> diff --git a/arch/riscv/errata/andes/errata.c b/arch/riscv/errata/andes/errata.c
> index ec3e052ca8c7..4061ad4983bc 100644
> --- a/arch/riscv/errata/andes/errata.c
> +++ b/arch/riscv/errata/andes/errata.c
> @@ -13,9 +13,80 @@
> #include <asm/alternative.h>
> #include <asm/cacheflush.h>
> #include <asm/errata_list.h>
> +#include <asm/parse_asm.h>
> #include <asm/patch.h>
> +#include <asm/sbi.h>
> #include <asm/vendorid_list.h>
>
> +/* Copy of Heiko's code from patch [0]
> + * [0] https://patchwork.kernel.org/project/linux-riscv/patch/20221110164924.529386-6-heiko@sntech.de/
Move it to commit-msg. No link in the code.
> + */
> +DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR)
> +DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC)
> +
> +static inline bool is_auipc_jalr_pair(long insn1, long insn2)
> +{
> + return is_auipc_insn(insn1) && is_jalr_insn(insn2);
> +}
> +
> +#define JALR_SIGN_MASK BIT(I_IMM_SIGN_OPOFF - I_IMM_11_0_OPOFF)
> +#define JALR_OFFSET_MASK I_IMM_11_0_MASK
> +#define AUIPC_OFFSET_MASK U_IMM_31_12_MASK
> +#define AUIPC_PAD (0x00001000)
> +#define JALR_SHIFT I_IMM_11_0_OPOFF
> +
> +#define to_jalr_imm(offset) \
> + ((offset & I_IMM_11_0_MASK) << I_IMM_11_0_OPOFF)
> +
> +#define to_auipc_imm(offset) \
> + ((offset & JALR_SIGN_MASK) ? \
> + ((offset & AUIPC_OFFSET_MASK) + AUIPC_PAD) : \
> + (offset & AUIPC_OFFSET_MASK))
> +
> +static void riscv_alternative_fix_auipc_jalr(unsigned int *alt_ptr,
> + unsigned int len, int patch_offset)
> +{
> + int num_instr = len / sizeof(u32);
> + unsigned int call[2];
> + int i;
> + int imm1;
> + u32 rd1;
> +
> + for (i = 0; i < num_instr; i++) {
> + /* is there a further instruction? */
> + if (i + 1 >= num_instr)
> + continue;
> +
> + if (!is_auipc_jalr_pair(*(alt_ptr + i), *(alt_ptr + i + 1)))
> + continue;
> +
> + /* call will use ra register */
> + rd1 = EXTRACT_RD_REG(*(alt_ptr + i));
> + if (rd1 != 1)
> + continue;
> +
> + /* get and adjust new target address */
> + imm1 = EXTRACT_UTYPE_IMM(*(alt_ptr + i));
> + imm1 += EXTRACT_ITYPE_IMM(*(alt_ptr + i + 1));
> + imm1 -= patch_offset;
> +
> + /* pick the original auipc + jalr */
> + call[0] = *(alt_ptr + i);
> + call[1] = *(alt_ptr + i + 1);
> +
> + /* drop the old IMMs */
> + call[0] &= ~(U_IMM_31_12_MASK);
> + call[1] &= ~(I_IMM_11_0_MASK << I_IMM_11_0_OPOFF);
> +
> + /* add the adapted IMMs */
> + call[0] |= to_auipc_imm(imm1);
> + call[1] |= to_jalr_imm(imm1);
> +
> + /* patch the call place again */
> + patch_text_nosync(alt_ptr + i, call, 8);
> + }
> +}
> +
> static bool errata_probe_iocp(unsigned int stage, unsigned long arch_id, unsigned long impid)
> {
> if (!IS_ENABLED(CONFIG_ERRATA_ANDES_CMO))
> --
> 2.25.1
>
--
Best Regards
Guo Ren
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-11-25 1:09 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-24 17:22 [PATCH v4 0/7] AX45MP: Add support to non-coherent DMA Prabhakar
2022-11-24 17:22 ` [PATCH v4 1/7] riscv: asm: alternative-macros: Introduce ALTERNATIVE_3() macro Prabhakar
2022-11-24 18:06 ` Heiko Stübner
2022-11-24 19:52 ` Conor Dooley
2022-11-24 19:58 ` Heiko Stübner
2022-11-24 20:05 ` Conor Dooley
2022-11-24 20:08 ` Conor Dooley
2022-11-24 20:44 ` Heiko Stübner
2022-11-25 11:44 ` Andrew Jones
2022-11-25 10:02 ` Lad, Prabhakar
2022-11-25 10:20 ` Heiko Stübner
2022-11-25 10:36 ` Lad, Prabhakar
2022-11-24 17:22 ` [PATCH v4 2/7] riscv: asm: vendorid_list: Add Andes Technology to the vendors list Prabhakar
2022-11-24 18:06 ` Heiko Stübner
2022-11-24 20:09 ` Conor Dooley
2022-11-24 17:22 ` [PATCH v4 3/7] riscv: errata: Add Andes alternative ports Prabhakar
2022-11-24 18:24 ` Heiko Stübner
2022-11-24 19:14 ` Lad, Prabhakar
2022-11-24 20:21 ` Conor Dooley
2022-11-25 10:08 ` Lad, Prabhakar
2022-11-24 17:22 ` [PATCH DO NOT REVIEW v4 4/7] riscv: errata: andes: Fix auipc-jalr addresses in patched alternatives Prabhakar
2022-11-25 1:08 ` Guo Ren [this message]
2022-11-25 10:10 ` Lad, Prabhakar
2022-11-24 17:22 ` [PATCH v4 5/7] riscv: mm: dma-noncoherent: Pass direction and operation to ALT_CMO_OP() Prabhakar
2022-11-24 18:29 ` Heiko Stübner
2022-11-24 19:18 ` Lad, Prabhakar
2022-11-25 18:49 ` Samuel Holland
2022-11-25 20:53 ` Lad, Prabhakar
2022-11-24 17:22 ` [PATCH v4 6/7] dt-bindings: cache: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller Prabhakar
2022-11-25 8:16 ` Krzysztof Kozlowski
2022-11-25 10:34 ` Lad, Prabhakar
2022-11-25 11:17 ` Geert Uytterhoeven
2022-11-25 11:45 ` Lad, Prabhakar
2022-11-25 12:12 ` Krzysztof Kozlowski
2022-11-25 12:25 ` Conor Dooley
2022-11-25 12:51 ` Lad, Prabhakar
2022-11-25 13:24 ` Conor Dooley
2022-11-25 15:55 ` Krzysztof Kozlowski
2022-11-25 16:50 ` Conor Dooley
2022-11-25 18:18 ` Lad, Prabhakar
2022-11-24 17:22 ` [PATCH v4 7/7] soc: renesas: Add L2 cache management for RZ/Five SoC Prabhakar
2022-11-24 18:30 ` Heiko Stübner
2022-11-24 19:56 ` Lad, Prabhakar
2022-11-24 20:47 ` Heiko Stübner
2022-11-24 21:31 ` Conor Dooley
2022-11-24 21:34 ` Conor Dooley
2022-11-25 10:50 ` Lad, Prabhakar
2022-11-25 12:16 ` Conor Dooley
2022-11-25 19:43 ` Samuel Holland
2022-11-26 21:09 ` Lad, Prabhakar
2022-11-27 9:55 ` Geert Uytterhoeven
2022-11-28 12:08 ` Lad, Prabhakar
2022-11-29 5:48 ` Samuel Holland
2022-11-29 5:58 ` Samuel Holland
2022-12-01 11:30 ` Lad, Prabhakar
2022-11-24 19:41 ` [PATCH v4 0/7] AX45MP: Add support to non-coherent DMA Conor Dooley
2022-11-24 19:52 ` Lad, Prabhakar
2022-11-24 19:59 ` Conor Dooley
2022-11-25 9:04 ` Geert Uytterhoeven
2022-11-25 10:51 ` Lad, Prabhakar
2022-12-01 23:36 ` Conor Dooley
2022-12-02 9:38 ` Lad, Prabhakar
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