From: "Heiko Stübner" <heiko@sntech.de>
To: Prabhakar <prabhakar.csengg@gmail.com>, Conor Dooley <conor@kernel.org>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Magnus Damm <magnus.damm@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor.dooley@microchip.com>,
Guo Ren <guoren@kernel.org>, Jisheng Zhang <jszhang@kernel.org>,
Atish Patra <atishp@rivosinc.com>,
Anup Patel <apatel@ventanamicro.com>,
Andrew Jones <ajones@ventanamicro.com>,
Nathan Chancellor <nathan@kernel.org>,
Philipp Tomsich <philipp.tomsich@vrull.eu>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org,
linux-renesas-soc@vger.kernel.org,
Biju Das <biju.das.jz@bp.renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH v4 1/7] riscv: asm: alternative-macros: Introduce ALTERNATIVE_3() macro
Date: Thu, 24 Nov 2022 20:58:41 +0100 [thread overview]
Message-ID: <4801607.MHq7AAxBmi@diego> (raw)
In-Reply-To: <Y3/LgZkR1hkblJ8D@spud>
Am Donnerstag, 24. November 2022, 20:52:33 CET schrieb Conor Dooley:
> On Thu, Nov 24, 2022 at 05:22:01PM +0000, Prabhakar wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Introduce ALTERNATIVE_3() macro.
>
> Bit perfunctory I think! There's a lovely comment down below that would
> make for a better commit message if you were to yoink it.
> Content looks about what I'd expect to see though.
Also both the comment on the original ALTERNATIVE_2 and the new ALTERNATIVE_3
should probably be merged into a single comment explaining this once for all
ALTERNATIVE_x variants.
Especially with the dma stuff, I'm pretty sure we'll get at least an ALTERNATIVE_4
if not even more ;-) . So we defnitly don't want to repeat this multiple times.
Heiko
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > RFC v3 -> v4
> > * New patch
> > ---
> > arch/riscv/include/asm/alternative-macros.h | 94 +++++++++++++++++++++
> > 1 file changed, 94 insertions(+)
> >
> > diff --git a/arch/riscv/include/asm/alternative-macros.h b/arch/riscv/include/asm/alternative-macros.h
> > index ec2f3f1b836f..1caf4306b3d6 100644
> > --- a/arch/riscv/include/asm/alternative-macros.h
> > +++ b/arch/riscv/include/asm/alternative-macros.h
> > @@ -69,6 +69,34 @@
> > new_c_2, vendor_id_2, errata_id_2, \
> > IS_ENABLED(CONFIG_k_2)
> >
> > +.macro __ALTERNATIVE_CFG_3 old_c, new_c_1, vendor_id_1, errata_id_1, enable_1, \
> > + new_c_2, vendor_id_2, errata_id_2, enable_2, \
> > + new_c_3, vendor_id_3, errata_id_3, enable_3
> > +886 :
> > + .option push
> > + .option norvc
> > + .option norelax
> > + \old_c
> > + .option pop
> > +887 :
> > + ALT_NEW_CONTENT \vendor_id_1, \errata_id_1, \enable_1, \new_c_1
> > + ALT_NEW_CONTENT \vendor_id_2, \errata_id_2, \enable_2, \new_c_2
> > + ALT_NEW_CONTENT \vendor_id_3, \errata_id_3, \enable_3, \new_c_3
> > +.endm
> > +
> > +#define _ALTERNATIVE_CFG_3(old_c, new_c_1, vendor_id_1, errata_id_1, \
> > + CONFIG_k_1, \
> > + new_c_2, vendor_id_2, errata_id_2, \
> > + CONFIG_k_2, \
> > + new_c_3, vendor_id_3, errata_id_3, \
> > + CONFIG_k_3) \
> > + __ALTERNATIVE_CFG_3 old_c, new_c_1, vendor_id_1, errata_id_1, \
> > + IS_ENABLED(CONFIG_k_1), \
> > + new_c_2, vendor_id_2, errata_id_2, \
> > + IS_ENABLED(CONFIG_k_2), \
> > + new_c_3, vendor_id_3, errata_id_3, \
> > + IS_ENABLED(CONFIG_k_3)
> > +
> > #else /* !__ASSEMBLY__ */
> >
> > #include <asm/asm.h>
> > @@ -135,6 +163,36 @@
> > new_c_2, vendor_id_2, errata_id_2, \
> > IS_ENABLED(CONFIG_k_2))
> >
> > +#define __ALTERNATIVE_CFG_3(old_c, new_c_1, vendor_id_1, errata_id_1, \
> > + enable_1, \
> > + new_c_2, vendor_id_2, errata_id_2, \
> > + enable_2, \
> > + new_c_3, vendor_id_3, errata_id_3, \
> > + enable_3) \
> > + "886 :\n" \
> > + ".option push\n" \
> > + ".option norvc\n" \
> > + ".option norelax\n" \
> > + old_c "\n" \
> > + ".option pop\n" \
> > + "887 :\n" \
> > + ALT_NEW_CONTENT(vendor_id_1, errata_id_1, enable_1, new_c_1) \
> > + ALT_NEW_CONTENT(vendor_id_2, errata_id_2, enable_2, new_c_2) \
> > + ALT_NEW_CONTENT(vendor_id_3, errata_id_3, enable_3, new_c_3)
> > +
> > +#define _ALTERNATIVE_CFG_3(old_c, new_c_1, vendor_id_1, errata_id_1, \
> > + CONFIG_k_1, \
> > + new_c_2, vendor_id_2, errata_id_2, \
> > + CONFIG_k_2, \
> > + new_c_3, vendor_id_3, errata_id_3, \
> > + CONFIG_k_3) \
> > + __ALTERNATIVE_CFG_3(old_c, new_c_1, vendor_id_1, errata_id_1, \
> > + IS_ENABLED(CONFIG_k_1), \
> > + new_c_2, vendor_id_2, errata_id_2, \
> > + IS_ENABLED(CONFIG_k_2), \
> > + new_c_3, vendor_id_3, errata_id_3, \
> > + IS_ENABLED(CONFIG_k_3))
> > +
> > #endif /* __ASSEMBLY__ */
> >
> > #else /* CONFIG_RISCV_ALTERNATIVE */
> > @@ -153,6 +211,14 @@
> > CONFIG_k_2) \
> > __ALTERNATIVE_CFG old_c
> >
> > +#define _ALTERNATIVE_CFG_3(old_c, new_c_1, vendor_id_1, errata_id_1, \
> > + CONFIG_k_1, \
> > + new_c_2, vendor_id_2, errata_id_2, \
> > + CONFIG_k_2, \
> > + new_c_3, vendor_id_3, errata_id_3, \
> > + CONFIG_k_3) \
> > + __ALTERNATIVE_CFG old_c
> > +
> > #else /* !__ASSEMBLY__ */
> >
> > #define __ALTERNATIVE_CFG(old_c) \
> > @@ -167,6 +233,14 @@
> > CONFIG_k_2) \
> > __ALTERNATIVE_CFG(old_c)
> >
> > +#define _ALTERNATIVE_CFG_3(old_c, new_c_1, vendor_id_1, errata_id_1, \
> > + CONFIG_k_1, \
> > + new_c_2, vendor_id_2, errata_id_2, \
> > + CONFIG_k_2, \
> > + new_c_3, vendor_id_3, errata_id_3, \
> > + CONFIG_k_3) \
> > + __ALTERNATIVE_CFG(old_c)
> > +
> > #endif /* __ASSEMBLY__ */
> > #endif /* CONFIG_RISCV_ALTERNATIVE */
> >
> > @@ -202,4 +276,24 @@
> > new_content_2, vendor_id_2, \
> > errata_id_2, CONFIG_k_2)
> >
> > +/*
> > + * A vendor wants to replace an old_content, but another vendor has used
> > + * ALTERNATIVE_2() to patch its customized content at the same location. In
> > + * this case, this vendor can create a new macro ALTERNATIVE_3() based
> > + * on the following sample code and then replace ALTERNATIVE_2() with
> > + * ALTERNATIVE_3() to append its customized content.
> > + */
> > +#define ALTERNATIVE_3(old_content, new_content_1, vendor_id_1, \
> > + errata_id_1, CONFIG_k_1, \
> > + new_content_2, vendor_id_2, \
> > + errata_id_2, CONFIG_k_2, \
> > + new_content_3, vendor_id_3, \
> > + errata_id_3, CONFIG_k_3) \
> > + _ALTERNATIVE_CFG_3(old_content, new_content_1, vendor_id_1, \
> > + errata_id_1, CONFIG_k_1, \
> > + new_content_2, vendor_id_2, \
> > + errata_id_2, CONFIG_k_2, \
> > + new_content_3, vendor_id_3, \
> > + errata_id_3, CONFIG_k_3)
> > +
> > #endif
>
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next prev parent reply other threads:[~2022-11-24 19:59 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-24 17:22 [PATCH v4 0/7] AX45MP: Add support to non-coherent DMA Prabhakar
2022-11-24 17:22 ` [PATCH v4 1/7] riscv: asm: alternative-macros: Introduce ALTERNATIVE_3() macro Prabhakar
2022-11-24 18:06 ` Heiko Stübner
2022-11-24 19:52 ` Conor Dooley
2022-11-24 19:58 ` Heiko Stübner [this message]
2022-11-24 20:05 ` Conor Dooley
2022-11-24 20:08 ` Conor Dooley
2022-11-24 20:44 ` Heiko Stübner
2022-11-25 11:44 ` Andrew Jones
2022-11-25 10:02 ` Lad, Prabhakar
2022-11-25 10:20 ` Heiko Stübner
2022-11-25 10:36 ` Lad, Prabhakar
2022-11-24 17:22 ` [PATCH v4 2/7] riscv: asm: vendorid_list: Add Andes Technology to the vendors list Prabhakar
2022-11-24 18:06 ` Heiko Stübner
2022-11-24 20:09 ` Conor Dooley
2022-11-24 17:22 ` [PATCH v4 3/7] riscv: errata: Add Andes alternative ports Prabhakar
2022-11-24 18:24 ` Heiko Stübner
2022-11-24 19:14 ` Lad, Prabhakar
2022-11-24 20:21 ` Conor Dooley
2022-11-25 10:08 ` Lad, Prabhakar
2022-11-24 17:22 ` [PATCH DO NOT REVIEW v4 4/7] riscv: errata: andes: Fix auipc-jalr addresses in patched alternatives Prabhakar
2022-11-25 1:08 ` Guo Ren
2022-11-25 10:10 ` Lad, Prabhakar
2022-11-24 17:22 ` [PATCH v4 5/7] riscv: mm: dma-noncoherent: Pass direction and operation to ALT_CMO_OP() Prabhakar
2022-11-24 18:29 ` Heiko Stübner
2022-11-24 19:18 ` Lad, Prabhakar
2022-11-25 18:49 ` Samuel Holland
2022-11-25 20:53 ` Lad, Prabhakar
2022-11-24 17:22 ` [PATCH v4 6/7] dt-bindings: cache: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller Prabhakar
2022-11-25 8:16 ` Krzysztof Kozlowski
2022-11-25 10:34 ` Lad, Prabhakar
2022-11-25 11:17 ` Geert Uytterhoeven
2022-11-25 11:45 ` Lad, Prabhakar
2022-11-25 12:12 ` Krzysztof Kozlowski
2022-11-25 12:25 ` Conor Dooley
2022-11-25 12:51 ` Lad, Prabhakar
2022-11-25 13:24 ` Conor Dooley
2022-11-25 15:55 ` Krzysztof Kozlowski
2022-11-25 16:50 ` Conor Dooley
2022-11-25 18:18 ` Lad, Prabhakar
2022-11-24 17:22 ` [PATCH v4 7/7] soc: renesas: Add L2 cache management for RZ/Five SoC Prabhakar
2022-11-24 18:30 ` Heiko Stübner
2022-11-24 19:56 ` Lad, Prabhakar
2022-11-24 20:47 ` Heiko Stübner
2022-11-24 21:31 ` Conor Dooley
2022-11-24 21:34 ` Conor Dooley
2022-11-25 10:50 ` Lad, Prabhakar
2022-11-25 12:16 ` Conor Dooley
2022-11-25 19:43 ` Samuel Holland
2022-11-26 21:09 ` Lad, Prabhakar
2022-11-27 9:55 ` Geert Uytterhoeven
2022-11-28 12:08 ` Lad, Prabhakar
2022-11-29 5:48 ` Samuel Holland
2022-11-29 5:58 ` Samuel Holland
2022-12-01 11:30 ` Lad, Prabhakar
2022-11-24 19:41 ` [PATCH v4 0/7] AX45MP: Add support to non-coherent DMA Conor Dooley
2022-11-24 19:52 ` Lad, Prabhakar
2022-11-24 19:59 ` Conor Dooley
2022-11-25 9:04 ` Geert Uytterhoeven
2022-11-25 10:51 ` Lad, Prabhakar
2022-12-01 23:36 ` Conor Dooley
2022-12-02 9:38 ` Lad, Prabhakar
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