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From: Apurva Nandan <a-nandan@ti.com>
To: Miquel Raynal <miquel.raynal@bootlin.com>
Cc: Richard Weinberger <richard@nod.at>,
	Vignesh Raghavendra <vigneshr@ti.com>,
	Mark Brown <broonie@kernel.org>,
	Patrice Chotard <patrice.chotard@foss.st.com>,
	Boris Brezillon <boris.brezillon@collabora.com>,
	<linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
	<linux-spi@vger.kernel.org>, Pratyush Yadav <p.yadav@ti.com>
Subject: Re: [PATCH 10/13] mtd: spinand: Add octal_dtr_enable() for Winbond manufacturer_ops
Date: Fri, 20 Aug 2021 17:01:40 +0530	[thread overview]
Message-ID: <0ac67f14-b25c-2e3b-fdd9-f5f101d9caad@ti.com> (raw)
In-Reply-To: <20210806210609.0fd94b9e@xps13>

Hi Miquèl,

On 07/08/21 12:36 am, Miquel Raynal wrote:
> Hi Apurva,
> 
> Apurva Nandan <a-nandan@ti.com> wrote on Tue, 13 Jul 2021 13:05:35
> +0000:
> 
>> Add implementation of octal_dtr_enable() manufacturer_ops for Winbond.
>> To switch to Ocatl DTR mode, setting programmable dummy cycles and
>> SPI IO mode using the volatile configuration register is required. To
>> function at max 120MHz SPI clock in Octal DTR mode, 12 programmable
>> dummy clock cycle setting is required. (Default number of dummy cycle
>> are 8 clocks)
>>
>> Set the programmable dummy cycle to 12 clocks, and SPI IO mode to
>> Octal DTR with Data Strobe in the VCR. Also, perform a READ ID
>> operation in Octal DTR SPI mode to ensure the switch was successful.
> 
> Commit title should contain "winbond:" (same for the previous patch and
> possibly next ones as well).
> 

Okay, got it!

>> Datasheet: https://www.winbond.com/export/sites/winbond/datasheet/W35N01JW_Datasheet_Brief.pdf
>>
>> Signed-off-by: Apurva Nandan <a-nandan@ti.com>
>> ---
>>   drivers/mtd/nand/spi/winbond.c | 42 ++++++++++++++++++++++++++++++++++
>>   1 file changed, 42 insertions(+)
>>
>> diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c
>> index a7052a9ca171..58cda07c15a0 100644
>> --- a/drivers/mtd/nand/spi/winbond.c
>> +++ b/drivers/mtd/nand/spi/winbond.c
>> @@ -16,6 +16,14 @@
>>   
>>   #define WINBOND_CFG_BUF_READ		BIT(3)
>>   
>> +/* Octal DTR SPI mode (8D-8D-8D) with Data Strobe output*/
>> +#define WINBOND_IO_MODE_VCR_OCTAL_DTR	0xE7
>> +#define WINBOND_IO_MODE_VCR_ADDR	0x00
>> +
>> +/* Use 12 dummy clk cycles for using Octal DTR SPI at max 120MHZ */
>> +#define WINBOND_DUMMY_CLK_COUNT		12
>> +#define WINBOND_DUMMY_CLK_VCR_ADDR	0x01
>> +
>>   static SPINAND_OP_VARIANTS(read_cache_variants,
>>   		SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
>>   		SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
>> @@ -142,8 +150,42 @@ static int winbond_write_vcr_op(struct spinand_device *spinand, u8 reg, u8 val)
>>   	return 0;
>>   }
>>   
>> +static int winbond_spinand_octal_dtr_enable(struct spinand_device *spinand)
>> +{
>> +	int ret;
>> +	struct spi_mem_op op;
>> +
>> +	ret = winbond_write_vcr_op(spinand, WINBOND_DUMMY_CLK_VCR_ADDR,
>> +				   WINBOND_DUMMY_CLK_COUNT);
>> +	if (ret)
>> +		return ret;
>> +
>> +	ret = winbond_write_vcr_op(spinand, WINBOND_IO_MODE_VCR_ADDR,
>> +				   WINBOND_IO_MODE_VCR_OCTAL_DTR);
>> +	if (ret)
>> +		return ret;
>> +
>> +	/* Read flash ID to make sure the switch was successful. */
>> +	op = (struct spi_mem_op)
>> +		SPI_MEM_OP(SPI_MEM_OP_CMD_DTR(2, 0x9f9f, 8),
>> +			   SPI_MEM_OP_NO_ADDR,
>> +			   SPI_MEM_OP_DUMMY_DTR(16, 8),
>> +			   SPI_MEM_OP_DATA_IN_DTR(SPINAND_MAX_ID_LEN,
>> +						  spinand->scratchbuf, 8));
>> +
>> +	ret = spi_mem_exec_op(spinand->spimem, &op);
>> +	if (ret)
>> +		return ret;
>> +
>> +	if (memcmp(spinand->scratchbuf, spinand->id.data, SPINAND_MAX_ID_LEN))
>> +		return -EINVAL;
>> +
>> +	return 0;
>> +}
>> +
>>   static const struct spinand_manufacturer_ops winbond_spinand_manuf_ops = {
>>   	.init = winbond_spinand_init,
>> +	.octal_dtr_enable = winbond_spinand_octal_dtr_enable,
>>   };
>>   
>>   const struct spinand_manufacturer winbond_spinand_manufacturer = {
> 
> 
> 
> 
> Thanks,
> Miquèl
> 
> ______________________________________________________
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/
> 

Thanks,
Apurva Nandan

  reply	other threads:[~2021-08-20 11:32 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-13 13:05 [PATCH 00/13] mtd: spinand: Add Octal DTR SPI (8D-8D-8D) mode support Apurva Nandan
2021-07-13 13:05 ` [PATCH 01/13] spi: spi-mem: Add DTR templates for cmd, address, dummy and data phase Apurva Nandan
2021-07-14 17:06   ` Mark Brown
2021-08-23  7:57   ` Boris Brezillon
2021-07-13 13:05 ` [PATCH 02/13] mtd: spinand: Add enum spinand_proto to indicate current SPI IO mode Apurva Nandan
2021-07-13 13:05 ` [PATCH 03/13] mtd: spinand: Setup spi_mem_op for the SPI IO protocol using reg_proto Apurva Nandan
2021-08-06 18:30   ` Miquel Raynal
2021-08-20  9:52     ` Apurva Nandan
2021-08-20 12:08       ` Miquel Raynal
2021-08-23  7:11         ` Boris Brezillon
2021-08-23  7:24           ` Miquel Raynal
2021-07-13 13:05 ` [PATCH 04/13] mtd: spinand: Fix odd byte addr and data phase in read/write reg op and write VCR op for Octal DTR mode Apurva Nandan
2021-08-06 18:43   ` Miquel Raynal
2021-08-20 10:27     ` Apurva Nandan
2021-08-20 12:06       ` Miquel Raynal
2021-07-13 13:05 ` [PATCH 05/13] mtd: spinand: Add adjust_op() in manufacturer_ops to modify the ops for manufacturer specific changes Apurva Nandan
2021-07-13 13:05 ` [PATCH 06/13] mtd: spinand: Add macros for Octal DTR page read and write operations Apurva Nandan
2021-08-06 18:54   ` Miquel Raynal
2021-08-20 10:35     ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 07/13] mtd: spinand: Allow enabling Octal DTR mode in the core Apurva Nandan
2021-08-06 18:58   ` Miquel Raynal
2021-08-20 10:41     ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 08/13] mtd: spinand: Reject 8D-8D-8D op_templates if octal_dtr_enale() is missing in manufacturer_op Apurva Nandan
2021-08-06 19:01   ` Miquel Raynal
2021-08-20 11:26     ` Apurva Nandan
2021-08-20 12:14       ` Miquel Raynal
2021-08-20 13:54         ` Apurva Nandan
2021-08-20 14:38           ` Miquel Raynal
2021-08-20 15:53             ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 09/13] mtd: spinand: Add support for write volatile configuration register op Apurva Nandan
2021-08-06 19:05   ` Miquel Raynal
2021-08-20 11:30     ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 10/13] mtd: spinand: Add octal_dtr_enable() for Winbond manufacturer_ops Apurva Nandan
2021-08-06 19:06   ` Miquel Raynal
2021-08-20 11:31     ` Apurva Nandan [this message]
2021-07-13 13:05 ` [PATCH 11/13] mtd: spinand: Add support for Power-on-Reset (PoR) instruction Apurva Nandan
2021-08-06 19:08   ` Miquel Raynal
2021-08-20 11:39     ` Apurva Nandan
2021-08-20 12:18       ` Miquel Raynal
2021-08-20 13:41         ` Apurva Nandan
2021-08-20 14:17           ` Miquel Raynal
2021-08-20 15:56             ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 12/13] mtd: spinand: Perform Power-on-Reset when runtime_pm suspend is issued Apurva Nandan
2021-08-06 19:12   ` Miquel Raynal
2021-08-20 11:45     ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 13/13] mtd: spinand: Add support for Winbond W35N01JW SPI NAND flash Apurva Nandan
2021-08-06 19:14   ` Miquel Raynal
2021-08-20 11:51     ` Apurva Nandan
2021-08-20 12:02       ` Miquel Raynal
2021-08-20 13:14         ` Apurva Nandan
2021-07-20 16:53 ` [PATCH 00/13] mtd: spinand: Add Octal DTR SPI (8D-8D-8D) mode support Nandan, Apurva

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