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From: Apurva Nandan <a-nandan@ti.com>
To: Miquel Raynal <miquel.raynal@bootlin.com>,
	Richard Weinberger <richard@nod.at>,
	Vignesh Raghavendra <vigneshr@ti.com>,
	Mark Brown <broonie@kernel.org>,
	Patrice Chotard <patrice.chotard@foss.st.com>,
	Boris Brezillon <boris.brezillon@collabora.com>,
	<linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
	<linux-spi@vger.kernel.org>
Cc: Apurva Nandan <a-nandan@ti.com>, Pratyush Yadav <p.yadav@ti.com>
Subject: [PATCH 02/13] mtd: spinand: Add enum spinand_proto to indicate current SPI IO mode
Date: Tue, 13 Jul 2021 13:05:27 +0000	[thread overview]
Message-ID: <20210713130538.646-3-a-nandan@ti.com> (raw)
In-Reply-To: <20210713130538.646-1-a-nandan@ti.com>

Unlike Dual and Quad SPI modes flashes, Octal DTR SPI NAND flashes
require all instructions to be made in 8D-8D-8D protocol when the
flash is in Octal DTR mode. Hence, storing the current SPI IO mode
becomes necessary for correctly generating non-array access operations.

Store the current SPI IO mode in the spinand struct using a reg_proto
enum. This would act as a flag, denoting that the core should use
the given SPI protocol for non-page access operations.

Also provide basic macros for extracting buswidth and dtr mode
information from the spinand_proto enum.

Signed-off-by: Apurva Nandan <a-nandan@ti.com>
---
 drivers/mtd/nand/spi/core.c |  2 ++
 include/linux/mtd/spinand.h | 30 ++++++++++++++++++++++++++++++
 2 files changed, 32 insertions(+)

diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c
index 446ba8d43fbc..a4f25649e293 100644
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
@@ -1153,6 +1153,7 @@ static void spinand_mtd_resume(struct mtd_info *mtd)
 	struct spinand_device *spinand = mtd_to_spinand(mtd);
 	int ret;
 
+	spinand->reg_proto = SPINAND_SINGLE_STR;
 	ret = spinand_reset_op(spinand);
 	if (ret)
 		return;
@@ -1179,6 +1180,7 @@ static int spinand_init(struct spinand_device *spinand)
 	if (!spinand->scratchbuf)
 		return -ENOMEM;
 
+	spinand->reg_proto = SPINAND_SINGLE_STR;
 	ret = spinand_detect(spinand);
 	if (ret)
 		goto err_free_bufs;
diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h
index 6988956b8492..f6093cd98d7b 100644
--- a/include/linux/mtd/spinand.h
+++ b/include/linux/mtd/spinand.h
@@ -140,6 +140,31 @@
 		   SPI_MEM_OP_NO_DUMMY,					\
 		   SPI_MEM_OP_DATA_OUT(len, buf, 4))
 
+#define SPINAND_PROTO_BUSWIDTH_MASK	GENMASK(6, 0)
+#define SPINAND_PROTO_DTR_BIT		BIT(7)
+
+#define SPINAND_PROTO_STR(__buswidth)	\
+	((u8)(((__buswidth) - 1) & SPINAND_PROTO_BUSWIDTH_MASK))
+#define SPINAND_PROTO_DTR(__buswidth)	\
+	(SPINAND_PROTO_DTR_BIT | SPINAND_PROTO_STR(__buswidth))
+
+#define SPINAND_PROTO_BUSWIDTH(__proto)	\
+	((u8)(((__proto) & SPINAND_PROTO_BUSWIDTH_MASK) + 1))
+#define SPINAND_PROTO_IS_DTR(__proto)	(!!((__proto) & SPINAND_PROTO_DTR_BIT))
+
+/**
+ * enum spinand_proto - List allowable SPI protocol variants for read reg,
+ *			write reg, blk erase, write enable/disable, page read
+ *			and program exec operations.
+ */
+enum spinand_proto {
+	SPINAND_SINGLE_STR = SPINAND_PROTO_STR(1),
+	SPINAND_DUAL_STR = SPINAND_PROTO_STR(2),
+	SPINAND_QUAD_STR = SPINAND_PROTO_STR(4),
+	SPINAND_OCTAL_STR = SPINAND_PROTO_STR(8),
+	SPINAND_OCTAL_DTR = SPINAND_PROTO_DTR(8),
+};
+
 /**
  * Standard SPI NAND flash commands
  */
@@ -407,6 +432,9 @@ struct spinand_dirmap {
  *		   this die. Only required if your chip exposes several dies
  * @cur_target: currently selected target/die
  * @eccinfo: on-die ECC information
+ * @reg_proto: select a variant of SPI IO protocol (single, quad, octal or
+ *	       octal DTR) for read_reg/write_reg/erase operations. Update on
+ *	       successful transition into a different SPI IO protocol.
  * @cfg_cache: config register cache. One entry per die
  * @databuf: bounce buffer for data
  * @oobbuf: bounce buffer for OOB data
@@ -438,6 +466,8 @@ struct spinand_device {
 
 	struct spinand_ecc_info eccinfo;
 
+	enum spinand_proto reg_proto;
+
 	u8 *cfg_cache;
 	u8 *databuf;
 	u8 *oobbuf;
-- 
2.17.1


  parent reply	other threads:[~2021-07-13 13:06 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-13 13:05 [PATCH 00/13] mtd: spinand: Add Octal DTR SPI (8D-8D-8D) mode support Apurva Nandan
2021-07-13 13:05 ` [PATCH 01/13] spi: spi-mem: Add DTR templates for cmd, address, dummy and data phase Apurva Nandan
2021-07-14 17:06   ` Mark Brown
2021-08-23  7:57   ` Boris Brezillon
2021-07-13 13:05 ` Apurva Nandan [this message]
2021-07-13 13:05 ` [PATCH 03/13] mtd: spinand: Setup spi_mem_op for the SPI IO protocol using reg_proto Apurva Nandan
2021-08-06 18:30   ` Miquel Raynal
2021-08-20  9:52     ` Apurva Nandan
2021-08-20 12:08       ` Miquel Raynal
2021-08-23  7:11         ` Boris Brezillon
2021-08-23  7:24           ` Miquel Raynal
2021-07-13 13:05 ` [PATCH 04/13] mtd: spinand: Fix odd byte addr and data phase in read/write reg op and write VCR op for Octal DTR mode Apurva Nandan
2021-08-06 18:43   ` Miquel Raynal
2021-08-20 10:27     ` Apurva Nandan
2021-08-20 12:06       ` Miquel Raynal
2021-07-13 13:05 ` [PATCH 05/13] mtd: spinand: Add adjust_op() in manufacturer_ops to modify the ops for manufacturer specific changes Apurva Nandan
2021-07-13 13:05 ` [PATCH 06/13] mtd: spinand: Add macros for Octal DTR page read and write operations Apurva Nandan
2021-08-06 18:54   ` Miquel Raynal
2021-08-20 10:35     ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 07/13] mtd: spinand: Allow enabling Octal DTR mode in the core Apurva Nandan
2021-08-06 18:58   ` Miquel Raynal
2021-08-20 10:41     ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 08/13] mtd: spinand: Reject 8D-8D-8D op_templates if octal_dtr_enale() is missing in manufacturer_op Apurva Nandan
2021-08-06 19:01   ` Miquel Raynal
2021-08-20 11:26     ` Apurva Nandan
2021-08-20 12:14       ` Miquel Raynal
2021-08-20 13:54         ` Apurva Nandan
2021-08-20 14:38           ` Miquel Raynal
2021-08-20 15:53             ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 09/13] mtd: spinand: Add support for write volatile configuration register op Apurva Nandan
2021-08-06 19:05   ` Miquel Raynal
2021-08-20 11:30     ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 10/13] mtd: spinand: Add octal_dtr_enable() for Winbond manufacturer_ops Apurva Nandan
2021-08-06 19:06   ` Miquel Raynal
2021-08-20 11:31     ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 11/13] mtd: spinand: Add support for Power-on-Reset (PoR) instruction Apurva Nandan
2021-08-06 19:08   ` Miquel Raynal
2021-08-20 11:39     ` Apurva Nandan
2021-08-20 12:18       ` Miquel Raynal
2021-08-20 13:41         ` Apurva Nandan
2021-08-20 14:17           ` Miquel Raynal
2021-08-20 15:56             ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 12/13] mtd: spinand: Perform Power-on-Reset when runtime_pm suspend is issued Apurva Nandan
2021-08-06 19:12   ` Miquel Raynal
2021-08-20 11:45     ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 13/13] mtd: spinand: Add support for Winbond W35N01JW SPI NAND flash Apurva Nandan
2021-08-06 19:14   ` Miquel Raynal
2021-08-20 11:51     ` Apurva Nandan
2021-08-20 12:02       ` Miquel Raynal
2021-08-20 13:14         ` Apurva Nandan
2021-07-20 16:53 ` [PATCH 00/13] mtd: spinand: Add Octal DTR SPI (8D-8D-8D) mode support Nandan, Apurva

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