From: Miquel Raynal <firstname.lastname@example.org> To: Apurva Nandan <email@example.com> Cc: Richard Weinberger <firstname.lastname@example.org>, Vignesh Raghavendra <email@example.com>, Mark Brown <firstname.lastname@example.org>, Patrice Chotard <email@example.com>, Boris Brezillon <firstname.lastname@example.org>, <email@example.com>, <firstname.lastname@example.org>, <email@example.com>, Pratyush Yadav <firstname.lastname@example.org> Subject: Re: [PATCH 08/13] mtd: spinand: Reject 8D-8D-8D op_templates if octal_dtr_enale() is missing in manufacturer_op Date: Fri, 20 Aug 2021 16:38:02 +0200 [thread overview] Message-ID: <20210820163802.529482dd@xps13> (raw) In-Reply-To: <email@example.com> Hi Apurva, Apurva Nandan <firstname.lastname@example.org> wrote on Fri, 20 Aug 2021 19:24:34 +0530: > Hi Miquèl, > > On 20/08/21 5:44 pm, Miquel Raynal wrote: > > Hi Apurva, > > > > Apurva Nandan <email@example.com> wrote on Fri, 20 Aug 2021 16:56:50 > > +0530: > > > >> On 07/08/21 12:31 am, Miquel Raynal wrote: > >>> Hi Apurva, > >>> > >>> Apurva Nandan <firstname.lastname@example.org> wrote on Tue, 13 Jul 2021 13:05:33 > >>> +0000: > >>> >>>> The SPI NAND core doesn't know how to switch the flash to Octal DTR > >>>> mode (i.e. which operations to perform). If the manufacturer hasn't > >>>> implemented the octal_dtr_enable() manufacturer_op, the SPI NAND core > >>>> wouldn't be able to switch to 8D-8D-8D mode and will also not be able > >>>> to run in 1S-1S-1S mode due to already selected 8D-8D-8D read/write > >>>> cache op_templates. > >>>> > >>>> So, avoid choosing a Octal DTR SPI op_template for read_cache, > >>>> write_cache and update_cache operations, if the manufacturer_op > >>>> octal_dtr_enable() is missing. > >>> > >>> After looking at your previous commit I don't see why this patch would > >>> be needed. octal_dtr_enable() only updates the mode when it succeeds so > >>> I don't think this patch is really needed. > >>> >> > >> I added it to prevent any errors happening dues to a missing implementation of octal_dtr_enable() from manufacturer driver side. > >> So, if the manufacturers skips the octal_dtr_enable() implementation, we want the spinand core to run in 1s-1s-1s mode. > > > > I still don't get the point: you fail the probe if the octal bit is > > enabled but the manufacturer did not implement octal_dtr_enable(), so > > how could we have issues? Maybe I am overlooking something though, but > > this seemed completely redundant to my eyes so far. > > > > Okay, I feel this may be redundant. This is for the case when the manufacturer has added Octal DTR read/write/update cache variants but hasn't implemented the octal_dtr_enable() method. > > Without this patch, the probe would fail, if the manufacturer did not implement octal_dtr_enable(). But after using this patch, spinand can still use the chip in 1s-1s-1s mode in that case and just skip the Octal DTR op variants during the selection. And also the probe would succeed. Unless I am overlooking something with this series applied (with or without this patch) the possibilities are: - no octal bit -> continue as before - octal bit and vendor callback -> uses octal mode - octal bit and no vendor callback -> will return an error from spinand_init_octal_dtr_enable() which will fail the probe (patch 7) Anyway we have a choice: - Either we consider the tables describing chips as pure descriptions and we can support these chips in mode 1-1-1 (will require changes in your series as this is not what you support as far as I understand the code) - Or we consider these tables as "what is currently supported" and in this case we just fail if one adds the octal bit without any callback implementation. I think the latter is better for now. We can update this choice later if needed anyway. > > >> > >> Read/write/update op variant selection happens in select_op_variant(), much before octal_dtr_enable(). So just check if there is a definition of octal_dtr_enable in manufacturer ops and then only use 8D op variants. > >> > >> Removing this wouldn't break anything in the current implementation. > >> Do you think we should drop this? > >> > >>>> > >>>> Signed-off-by: Apurva Nandan <email@example.com> > >>>> --- > >>>> drivers/mtd/nand/spi/core.c | 7 ++++++- > >>>> 1 file changed, 6 insertions(+), 1 deletion(-) > >>>> > >>>> diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c > >>>> index 19d8affac058..8711e887b795 100644 > >>>> --- a/drivers/mtd/nand/spi/core.c > >>>> +++ b/drivers/mtd/nand/spi/core.c > >>>> @@ -1028,6 +1028,8 @@ static int spinand_manufacturer_match(struct spinand_device *spinand, > >>>> if (id != manufacturer->id) > >>>> continue; > >>>> >> + spinand->manufacturer = manufacturer; > >>>> + > >>>> ret = spinand_match_and_init(spinand, > >>>> manufacturer->chips, > >>>> manufacturer->nchips, > >>>> @@ -1035,7 +1037,6 @@ static int spinand_manufacturer_match(struct spinand_device *spinand, > >>>> if (ret < 0) > >>>> continue; > >>>> >> - spinand->manufacturer = manufacturer; > >>>> return 0; > >>>> } > >>>> return -ENOTSUPP; > >>>> @@ -1097,6 +1098,10 @@ spinand_select_op_variant(struct spinand_device *spinand, > >>>> unsigned int nbytes; > >>>> int ret; > >>>> >> + if (spinand_op_is_octal_dtr(&op) && > >>>> + !spinand->manufacturer->ops->octal_dtr_enable) > >>>> + continue; > >>>> + > >>>> nbytes = nanddev_per_page_oobsize(nand) + > >>>> nanddev_page_size(nand); > >>>> > > Thanks, > >>> Miquèl > >>> > >>> ______________________________________________________ > >>> Linux MTD discussion mailing list > >>> http://lists.infradead.org/mailman/listinfo/linux-mtd/ > >>> >> > >> Thanks, > >> Apurva Nandan > > > > > > > > > > Thanks, > > Miquèl > > > > Thanks, > Apurva Nandan Thanks, Miquèl
next prev parent reply other threads:[~2021-08-20 14:38 UTC|newest] Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-07-13 13:05 [PATCH 00/13] mtd: spinand: Add Octal DTR SPI (8D-8D-8D) mode support Apurva Nandan 2021-07-13 13:05 ` [PATCH 01/13] spi: spi-mem: Add DTR templates for cmd, address, dummy and data phase Apurva Nandan 2021-07-14 17:06 ` Mark Brown 2021-08-23 7:57 ` Boris Brezillon 2021-07-13 13:05 ` [PATCH 02/13] mtd: spinand: Add enum spinand_proto to indicate current SPI IO mode Apurva Nandan 2021-07-13 13:05 ` [PATCH 03/13] mtd: spinand: Setup spi_mem_op for the SPI IO protocol using reg_proto Apurva Nandan 2021-08-06 18:30 ` Miquel Raynal 2021-08-20 9:52 ` Apurva Nandan 2021-08-20 12:08 ` Miquel Raynal 2021-08-23 7:11 ` Boris Brezillon 2021-08-23 7:24 ` Miquel Raynal 2021-07-13 13:05 ` [PATCH 04/13] mtd: spinand: Fix odd byte addr and data phase in read/write reg op and write VCR op for Octal DTR mode Apurva Nandan 2021-08-06 18:43 ` Miquel Raynal 2021-08-20 10:27 ` Apurva Nandan 2021-08-20 12:06 ` Miquel Raynal 2021-07-13 13:05 ` [PATCH 05/13] mtd: spinand: Add adjust_op() in manufacturer_ops to modify the ops for manufacturer specific changes Apurva Nandan 2021-07-13 13:05 ` [PATCH 06/13] mtd: spinand: Add macros for Octal DTR page read and write operations Apurva Nandan 2021-08-06 18:54 ` Miquel Raynal 2021-08-20 10:35 ` Apurva Nandan 2021-07-13 13:05 ` [PATCH 07/13] mtd: spinand: Allow enabling Octal DTR mode in the core Apurva Nandan 2021-08-06 18:58 ` Miquel Raynal 2021-08-20 10:41 ` Apurva Nandan 2021-07-13 13:05 ` [PATCH 08/13] mtd: spinand: Reject 8D-8D-8D op_templates if octal_dtr_enale() is missing in manufacturer_op Apurva Nandan 2021-08-06 19:01 ` Miquel Raynal 2021-08-20 11:26 ` Apurva Nandan 2021-08-20 12:14 ` Miquel Raynal 2021-08-20 13:54 ` Apurva Nandan 2021-08-20 14:38 ` Miquel Raynal [this message] 2021-08-20 15:53 ` Apurva Nandan 2021-07-13 13:05 ` [PATCH 09/13] mtd: spinand: Add support for write volatile configuration register op Apurva Nandan 2021-08-06 19:05 ` Miquel Raynal 2021-08-20 11:30 ` Apurva Nandan 2021-07-13 13:05 ` [PATCH 10/13] mtd: spinand: Add octal_dtr_enable() for Winbond manufacturer_ops Apurva Nandan 2021-08-06 19:06 ` Miquel Raynal 2021-08-20 11:31 ` Apurva Nandan 2021-07-13 13:05 ` [PATCH 11/13] mtd: spinand: Add support for Power-on-Reset (PoR) instruction Apurva Nandan 2021-08-06 19:08 ` Miquel Raynal 2021-08-20 11:39 ` Apurva Nandan 2021-08-20 12:18 ` Miquel Raynal 2021-08-20 13:41 ` Apurva Nandan 2021-08-20 14:17 ` Miquel Raynal 2021-08-20 15:56 ` Apurva Nandan 2021-07-13 13:05 ` [PATCH 12/13] mtd: spinand: Perform Power-on-Reset when runtime_pm suspend is issued Apurva Nandan 2021-08-06 19:12 ` Miquel Raynal 2021-08-20 11:45 ` Apurva Nandan 2021-07-13 13:05 ` [PATCH 13/13] mtd: spinand: Add support for Winbond W35N01JW SPI NAND flash Apurva Nandan 2021-08-06 19:14 ` Miquel Raynal 2021-08-20 11:51 ` Apurva Nandan 2021-08-20 12:02 ` Miquel Raynal 2021-08-20 13:14 ` Apurva Nandan 2021-07-20 16:53 ` [PATCH 00/13] mtd: spinand: Add Octal DTR SPI (8D-8D-8D) mode support Nandan, Apurva
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20210820163802.529482dd@xps13 \ --firstname.lastname@example.org \ --email@example.com \ --firstname.lastname@example.org \ --email@example.com \ --firstname.lastname@example.org \ --email@example.com \ --firstname.lastname@example.org \ --email@example.com \ --firstname.lastname@example.org \ --email@example.com \ --firstname.lastname@example.org \ --subject='Re: [PATCH 08/13] mtd: spinand: Reject 8D-8D-8D op_templates if octal_dtr_enale() is missing in manufacturer_op' \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: link
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).