From: Apurva Nandan <a-nandan@ti.com>
To: Miquel Raynal <miquel.raynal@bootlin.com>
Cc: Richard Weinberger <richard@nod.at>,
Vignesh Raghavendra <vigneshr@ti.com>,
Mark Brown <broonie@kernel.org>,
Patrice Chotard <patrice.chotard@foss.st.com>,
Boris Brezillon <boris.brezillon@collabora.com>,
<linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
<linux-spi@vger.kernel.org>, Pratyush Yadav <p.yadav@ti.com>
Subject: Re: [PATCH 09/13] mtd: spinand: Add support for write volatile configuration register op
Date: Fri, 20 Aug 2021 17:00:03 +0530 [thread overview]
Message-ID: <24b79a08-96fd-34eb-13d3-f707970aae95@ti.com> (raw)
In-Reply-To: <20210806210500.3ead1600@xps13>
Hi Miquèl,
On 07/08/21 12:35 am, Miquel Raynal wrote:
> Hi Apurva,
>
> Apurva Nandan <a-nandan@ti.com> wrote on Tue, 13 Jul 2021 13:05:34
> +0000:
>
>> Volatile configuration register are a different set of configuration
>> registers, i.e. they differ from the status registers. A different
>> SPI instruction is required to write to these registers. Any changes
>> to the Volatile Configuration Register get transferred directly to
>> the Internal Configuration Register and instantly reflect on the
>> device operation.
>>
>> In Winbond W35N01JW, these volatile configuration register must be
>> configured in order to switch to Octal DTR SPI mode.
>>
>> Add support for writing to volatile configuration registers using a
>> new WRITE_VCR_OP template.
>>
>> Datasheet: https://www.winbond.com/export/sites/winbond/datasheet/W35N01JW_Datasheet_Brief.pdf
>>
>> Signed-off-by: Apurva Nandan <a-nandan@ti.com>
>> ---
>> drivers/mtd/nand/spi/core.c | 2 +-
>> drivers/mtd/nand/spi/winbond.c | 28 ++++++++++++++++++++++++++++
>> include/linux/mtd/spinand.h | 1 +
>> 3 files changed, 30 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c
>> index 8711e887b795..f577e72da2c4 100644
>> --- a/drivers/mtd/nand/spi/core.c
>> +++ b/drivers/mtd/nand/spi/core.c
>> @@ -442,7 +442,7 @@ static void spinand_ondie_ecc_save_status(struct nand_device *nand, u8 status)
>> engine_conf->status = status;
>> }
>>
>> -static int spinand_write_enable_op(struct spinand_device *spinand)
>> +int spinand_write_enable_op(struct spinand_device *spinand)
>> {
>> struct spi_mem_op op = SPINAND_WR_EN_DIS_OP(true);
>>
>> diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c
>> index 76684428354e..a7052a9ca171 100644
>> --- a/drivers/mtd/nand/spi/winbond.c
>> +++ b/drivers/mtd/nand/spi/winbond.c
>> @@ -7,6 +7,7 @@
>> * Boris Brezillon <boris.brezillon@bootlin.com>
>> */
>>
>> +#include <linux/delay.h>
>> #include <linux/device.h>
>> #include <linux/kernel.h>
>> #include <linux/mtd/spinand.h>
>> @@ -114,6 +115,33 @@ static int winbond_spinand_init(struct spinand_device *spinand)
>> return 0;
>> }
>>
>> +static int winbond_write_vcr_op(struct spinand_device *spinand, u8 reg, u8 val)
>
> Maybe a comment to tell people what vcr is?
>
Okay sure!
>> +{
>> + int ret;
>> + struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(0x81, 1),
>> + SPI_MEM_OP_ADDR(3, reg, 1),
>> + SPI_MEM_OP_NO_DUMMY,
>> + SPI_MEM_OP_DATA_OUT(1, spinand->scratchbuf, 1));
>> +
>> + *spinand->scratchbuf = val;
>> +
>> + ret = spinand_write_enable_op(spinand);
>> + if (ret)
>> + return ret;
>> +
>> + ret = spi_mem_exec_op(spinand->spimem, &op);
>> + if (ret)
>> + return ret;
>> +
>> + /*
>> + * Write VCR operation doesn't set the busy bit in SR, so can't perform
>> + * a status poll. Minimum time of 50ns is needed to complete the write.
>> + * So, give thrice the minimum required delay.
>
> Isn't there an official maximum time?
>
No, there is only an official minimum time. No maximum time..
>> + */
>> + ndelay(150);
>> + return 0;
>> +}
>> +
>> static const struct spinand_manufacturer_ops winbond_spinand_manuf_ops = {
>> .init = winbond_spinand_init,
>> };
>> diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h
>> index daa2ac5c3110..21a4e5adcd59 100644
>> --- a/include/linux/mtd/spinand.h
>> +++ b/include/linux/mtd/spinand.h
>> @@ -560,5 +560,6 @@ int spinand_match_and_init(struct spinand_device *spinand,
>>
>> int spinand_upd_cfg(struct spinand_device *spinand, u8 mask, u8 val);
>> int spinand_select_target(struct spinand_device *spinand, unsigned int target);
>> +int spinand_write_enable_op(struct spinand_device *spinand);
>>
>> #endif /* __LINUX_MTD_SPINAND_H */
>
>
>
>
> Thanks,
> Miquèl
>
> ______________________________________________________
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/
>
Thanks,
Apurva Nandan
next prev parent reply other threads:[~2021-08-20 11:30 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-13 13:05 [PATCH 00/13] mtd: spinand: Add Octal DTR SPI (8D-8D-8D) mode support Apurva Nandan
2021-07-13 13:05 ` [PATCH 01/13] spi: spi-mem: Add DTR templates for cmd, address, dummy and data phase Apurva Nandan
2021-07-14 17:06 ` Mark Brown
2021-08-23 7:57 ` Boris Brezillon
2021-07-13 13:05 ` [PATCH 02/13] mtd: spinand: Add enum spinand_proto to indicate current SPI IO mode Apurva Nandan
2021-07-13 13:05 ` [PATCH 03/13] mtd: spinand: Setup spi_mem_op for the SPI IO protocol using reg_proto Apurva Nandan
2021-08-06 18:30 ` Miquel Raynal
2021-08-20 9:52 ` Apurva Nandan
2021-08-20 12:08 ` Miquel Raynal
2021-08-23 7:11 ` Boris Brezillon
2021-08-23 7:24 ` Miquel Raynal
2021-07-13 13:05 ` [PATCH 04/13] mtd: spinand: Fix odd byte addr and data phase in read/write reg op and write VCR op for Octal DTR mode Apurva Nandan
2021-08-06 18:43 ` Miquel Raynal
2021-08-20 10:27 ` Apurva Nandan
2021-08-20 12:06 ` Miquel Raynal
2021-07-13 13:05 ` [PATCH 05/13] mtd: spinand: Add adjust_op() in manufacturer_ops to modify the ops for manufacturer specific changes Apurva Nandan
2021-07-13 13:05 ` [PATCH 06/13] mtd: spinand: Add macros for Octal DTR page read and write operations Apurva Nandan
2021-08-06 18:54 ` Miquel Raynal
2021-08-20 10:35 ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 07/13] mtd: spinand: Allow enabling Octal DTR mode in the core Apurva Nandan
2021-08-06 18:58 ` Miquel Raynal
2021-08-20 10:41 ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 08/13] mtd: spinand: Reject 8D-8D-8D op_templates if octal_dtr_enale() is missing in manufacturer_op Apurva Nandan
2021-08-06 19:01 ` Miquel Raynal
2021-08-20 11:26 ` Apurva Nandan
2021-08-20 12:14 ` Miquel Raynal
2021-08-20 13:54 ` Apurva Nandan
2021-08-20 14:38 ` Miquel Raynal
2021-08-20 15:53 ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 09/13] mtd: spinand: Add support for write volatile configuration register op Apurva Nandan
2021-08-06 19:05 ` Miquel Raynal
2021-08-20 11:30 ` Apurva Nandan [this message]
2021-07-13 13:05 ` [PATCH 10/13] mtd: spinand: Add octal_dtr_enable() for Winbond manufacturer_ops Apurva Nandan
2021-08-06 19:06 ` Miquel Raynal
2021-08-20 11:31 ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 11/13] mtd: spinand: Add support for Power-on-Reset (PoR) instruction Apurva Nandan
2021-08-06 19:08 ` Miquel Raynal
2021-08-20 11:39 ` Apurva Nandan
2021-08-20 12:18 ` Miquel Raynal
2021-08-20 13:41 ` Apurva Nandan
2021-08-20 14:17 ` Miquel Raynal
2021-08-20 15:56 ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 12/13] mtd: spinand: Perform Power-on-Reset when runtime_pm suspend is issued Apurva Nandan
2021-08-06 19:12 ` Miquel Raynal
2021-08-20 11:45 ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 13/13] mtd: spinand: Add support for Winbond W35N01JW SPI NAND flash Apurva Nandan
2021-08-06 19:14 ` Miquel Raynal
2021-08-20 11:51 ` Apurva Nandan
2021-08-20 12:02 ` Miquel Raynal
2021-08-20 13:14 ` Apurva Nandan
2021-07-20 16:53 ` [PATCH 00/13] mtd: spinand: Add Octal DTR SPI (8D-8D-8D) mode support Nandan, Apurva
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