From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Apurva Nandan <a-nandan@ti.com>
Cc: Richard Weinberger <richard@nod.at>,
Vignesh Raghavendra <vigneshr@ti.com>,
Mark Brown <broonie@kernel.org>,
Patrice Chotard <patrice.chotard@foss.st.com>,
Boris Brezillon <boris.brezillon@collabora.com>,
<linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
<linux-spi@vger.kernel.org>, Pratyush Yadav <p.yadav@ti.com>
Subject: Re: [PATCH 07/13] mtd: spinand: Allow enabling Octal DTR mode in the core
Date: Fri, 6 Aug 2021 20:58:45 +0200 [thread overview]
Message-ID: <20210806205845.03dd97c9@xps13> (raw)
In-Reply-To: <20210713130538.646-8-a-nandan@ti.com>
Hi Apurva,
Apurva Nandan <a-nandan@ti.com> wrote on Tue, 13 Jul 2021 13:05:32
+0000:
> Enable Octal DTR SPI mode, i.e. 8D-8D-8D mode, if the SPI NAND flash
> device supports it. Mixed OSPI (1S-1S-8S & 1S-8S-8S), mixed DTR modes
> (1S-1D-8D), etc. aren't supported yet.
>
> The method to switch to Octal DTR SPI mode may vary across
> manufacturers. For example, for Winbond, it is enabled by writing
> values to the volatile configuration register. So, let the
> manufacturer's code have their own implementation for switching to
> Octal DTR SPI mode. Mixed OSPI (1S-1S-8S & 1S-8S-8S), mixed DTR modes
> (1S-1D-8D), etc. aren't supported yet.
You can drop the final sentence which is a repetition of the previous
paragraph.
> Check for the SPI NAND device's support for Octal DTR mode using
> spinand flags, and if the op_templates allow 8D-8D-8D, call
allows
> octal_dtr_enable() manufacturer op. If the SPI controller doesn't
> supports these modes, the selected op_templates would prevent switching
will
> to the Octal DTR mode. And finally update the spinand reg_proto
> if success.
on
>
> Signed-off-by: Apurva Nandan <a-nandan@ti.com>
> ---
> drivers/mtd/nand/spi/core.c | 46 +++++++++++++++++++++++++++++++++++++
> include/linux/mtd/spinand.h | 3 +++
> 2 files changed, 49 insertions(+)
>
> diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c
> index 1e619b6d777f..19d8affac058 100644
> --- a/drivers/mtd/nand/spi/core.c
> +++ b/drivers/mtd/nand/spi/core.c
> @@ -256,6 +256,48 @@ static int spinand_init_quad_enable(struct spinand_device *spinand)
> enable ? CFG_QUAD_ENABLE : 0);
> }
>
> +static bool spinand_op_is_octal_dtr(const struct spi_mem_op *op)
> +{
> + return op->cmd.buswidth == 8 && op->cmd.dtr &&
> + op->addr.buswidth == 8 && op->addr.dtr &&
> + op->data.buswidth == 8 && op->data.dtr;
> +}
> +
> +static int spinand_init_octal_dtr_enable(struct spinand_device *spinand)
> +{
> + struct device *dev = &spinand->spimem->spi->dev;
> + int ret;
> +
> + if (!(spinand->flags & SPINAND_HAS_OCTAL_DTR_BIT))
> + return 0;
> +
> + if (!(spinand_op_is_octal_dtr(spinand->op_templates.read_cache) &&
> + spinand_op_is_octal_dtr(spinand->op_templates.write_cache) &&
> + spinand_op_is_octal_dtr(spinand->op_templates.update_cache)))
> + return 0;
> +
> + if (!spinand->manufacturer->ops->octal_dtr_enable) {
> + dev_err(dev,
> + "Missing ->octal_dtr_enable(), unable to switch mode\n");
I don't think we want an error here. Perhaps a debug or info call, but
no more.
> + return -EINVAL;
> + }
> +
> + ret = spinand->manufacturer->ops->octal_dtr_enable(spinand);
> + if (ret) {
> + dev_err(dev,
> + "Failed to enable Octal DTR SPI mode (err = %d)\n",
> + ret);
> + return ret;
> + }
> +
> + spinand->reg_proto = SPINAND_OCTAL_DTR;
> +
> + dev_dbg(dev,
> + "%s SPI NAND switched to Octal DTR SPI (8D-8D-8D) mode\n",
> + spinand->manufacturer->name);
> + return 0;
> +}
> +
> static int spinand_ecc_enable(struct spinand_device *spinand,
> bool enable)
> {
> @@ -1189,6 +1231,10 @@ static int spinand_init_flash(struct spinand_device *spinand)
> if (ret)
> return ret;
>
> + ret = spinand_init_octal_dtr_enable(spinand);
> + if (ret)
> + return ret;
> +
> ret = spinand_upd_cfg(spinand, CFG_OTP_ENABLE, 0);
> if (ret)
> return ret;
> diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h
> index 35816b8cfe81..daa2ac5c3110 100644
> --- a/include/linux/mtd/spinand.h
> +++ b/include/linux/mtd/spinand.h
> @@ -271,6 +271,7 @@ struct spinand_devid {
> * @init: initialize a SPI NAND device
> * @adjust_op: modify the ops for any variation in their cmd, address, dummy or
> * data phase by the manufacturer
> + * @octal_dtr_enable: switch the SPI NAND flash into Octal DTR SPI mode
> * @cleanup: cleanup a SPI NAND device
> *
> * Each SPI NAND manufacturer driver should implement this interface so that
> @@ -280,6 +281,7 @@ struct spinand_manufacturer_ops {
> int (*init)(struct spinand_device *spinand);
> void (*adjust_op)(struct spi_mem_op *op,
> const enum spinand_proto reg_proto);
> + int (*octal_dtr_enable)(struct spinand_device *spinand);
> void (*cleanup)(struct spinand_device *spinand);
> };
>
> @@ -348,6 +350,7 @@ struct spinand_ecc_info {
>
> #define SPINAND_HAS_QE_BIT BIT(0)
> #define SPINAND_HAS_CR_FEAT_BIT BIT(1)
> +#define SPINAND_HAS_OCTAL_DTR_BIT BIT(2)
>
> /**
> * struct spinand_ondie_ecc_conf - private SPI-NAND on-die ECC engine structure
Thanks,
Miquèl
next prev parent reply other threads:[~2021-08-06 18:58 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-13 13:05 [PATCH 00/13] mtd: spinand: Add Octal DTR SPI (8D-8D-8D) mode support Apurva Nandan
2021-07-13 13:05 ` [PATCH 01/13] spi: spi-mem: Add DTR templates for cmd, address, dummy and data phase Apurva Nandan
2021-07-14 17:06 ` Mark Brown
2021-08-23 7:57 ` Boris Brezillon
2021-07-13 13:05 ` [PATCH 02/13] mtd: spinand: Add enum spinand_proto to indicate current SPI IO mode Apurva Nandan
2021-07-13 13:05 ` [PATCH 03/13] mtd: spinand: Setup spi_mem_op for the SPI IO protocol using reg_proto Apurva Nandan
2021-08-06 18:30 ` Miquel Raynal
2021-08-20 9:52 ` Apurva Nandan
2021-08-20 12:08 ` Miquel Raynal
2021-08-23 7:11 ` Boris Brezillon
2021-08-23 7:24 ` Miquel Raynal
2021-07-13 13:05 ` [PATCH 04/13] mtd: spinand: Fix odd byte addr and data phase in read/write reg op and write VCR op for Octal DTR mode Apurva Nandan
2021-08-06 18:43 ` Miquel Raynal
2021-08-20 10:27 ` Apurva Nandan
2021-08-20 12:06 ` Miquel Raynal
2021-07-13 13:05 ` [PATCH 05/13] mtd: spinand: Add adjust_op() in manufacturer_ops to modify the ops for manufacturer specific changes Apurva Nandan
2021-07-13 13:05 ` [PATCH 06/13] mtd: spinand: Add macros for Octal DTR page read and write operations Apurva Nandan
2021-08-06 18:54 ` Miquel Raynal
2021-08-20 10:35 ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 07/13] mtd: spinand: Allow enabling Octal DTR mode in the core Apurva Nandan
2021-08-06 18:58 ` Miquel Raynal [this message]
2021-08-20 10:41 ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 08/13] mtd: spinand: Reject 8D-8D-8D op_templates if octal_dtr_enale() is missing in manufacturer_op Apurva Nandan
2021-08-06 19:01 ` Miquel Raynal
2021-08-20 11:26 ` Apurva Nandan
2021-08-20 12:14 ` Miquel Raynal
2021-08-20 13:54 ` Apurva Nandan
2021-08-20 14:38 ` Miquel Raynal
2021-08-20 15:53 ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 09/13] mtd: spinand: Add support for write volatile configuration register op Apurva Nandan
2021-08-06 19:05 ` Miquel Raynal
2021-08-20 11:30 ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 10/13] mtd: spinand: Add octal_dtr_enable() for Winbond manufacturer_ops Apurva Nandan
2021-08-06 19:06 ` Miquel Raynal
2021-08-20 11:31 ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 11/13] mtd: spinand: Add support for Power-on-Reset (PoR) instruction Apurva Nandan
2021-08-06 19:08 ` Miquel Raynal
2021-08-20 11:39 ` Apurva Nandan
2021-08-20 12:18 ` Miquel Raynal
2021-08-20 13:41 ` Apurva Nandan
2021-08-20 14:17 ` Miquel Raynal
2021-08-20 15:56 ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 12/13] mtd: spinand: Perform Power-on-Reset when runtime_pm suspend is issued Apurva Nandan
2021-08-06 19:12 ` Miquel Raynal
2021-08-20 11:45 ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 13/13] mtd: spinand: Add support for Winbond W35N01JW SPI NAND flash Apurva Nandan
2021-08-06 19:14 ` Miquel Raynal
2021-08-20 11:51 ` Apurva Nandan
2021-08-20 12:02 ` Miquel Raynal
2021-08-20 13:14 ` Apurva Nandan
2021-07-20 16:53 ` [PATCH 00/13] mtd: spinand: Add Octal DTR SPI (8D-8D-8D) mode support Nandan, Apurva
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210806205845.03dd97c9@xps13 \
--to=miquel.raynal@bootlin.com \
--cc=a-nandan@ti.com \
--cc=boris.brezillon@collabora.com \
--cc=broonie@kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mtd@lists.infradead.org \
--cc=linux-spi@vger.kernel.org \
--cc=p.yadav@ti.com \
--cc=patrice.chotard@foss.st.com \
--cc=richard@nod.at \
--cc=vigneshr@ti.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).