* [PATCH] mailmap: Update remaining active codeaurora.org email addresses
@ 2023-07-20 21:02 8% Bjorn Andersson
0 siblings, 0 replies; 200+ results
From: Bjorn Andersson @ 2023-07-20 21:02 UTC (permalink / raw)
To: Andrew Morton, Bjorn Andersson, Arnd Bergmann
Cc: Konrad Dybcio, linux-kernel, linux-arm-msm
The lack of mailmap updates for @codeaurora.org addresses reduces the
usefulness of tools such as get_maintainer.pl. Some recent (and
welcome!) additions has been made to improve the situation, this
concludes the effort.
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
---
.mailmap | 97 +++++++++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 96 insertions(+), 1 deletion(-)
diff --git a/.mailmap b/.mailmap
index 89b7f33cd330..9f067df9c306 100644
--- a/.mailmap
+++ b/.mailmap
@@ -13,7 +13,9 @@
Aaron Durbin <adurbin@google.com>
Abel Vesa <abelvesa@kernel.org> <abel.vesa@nxp.com>
Abel Vesa <abelvesa@kernel.org> <abelvesa@gmail.com>
+Abhijeet Dharmapurikar <quic_adharmap@quicinc.com> <adharmap@codeaurora.org>
Abhinav Kumar <quic_abhinavk@quicinc.com> <abhinavk@codeaurora.org>
+Ahmad Masri <quic_amasri@quicinc.com> <amasri@codeaurora.org>
Adam Oldham <oldhamca@gmail.com>
Adam Radford <aradford@gmail.com>
Adriana Reus <adi.reus@gmail.com> <adriana.reus@intel.com>
@@ -30,6 +32,7 @@ Alexander Mikhalitsyn <alexander@mihalicyn.com> <alexander.mikhalitsyn@virtuozzo
Alexander Mikhalitsyn <alexander@mihalicyn.com> <aleksandr.mikhalitsyn@canonical.com>
Alexandre Belloni <alexandre.belloni@bootlin.com> <alexandre.belloni@free-electrons.com>
Alexandre Ghiti <alex@ghiti.fr> <alexandre.ghiti@canonical.com>
+Alexei Avshalom Lazar <quic_ailizaro@quicinc.com> <ailizaro@codeaurora.org>
Alexei Starovoitov <ast@kernel.org> <alexei.starovoitov@gmail.com>
Alexei Starovoitov <ast@kernel.org> <ast@fb.com>
Alexei Starovoitov <ast@kernel.org> <ast@plumgrid.com>
@@ -37,8 +40,11 @@ Alex Hung <alexhung@gmail.com> <alex.hung@canonical.com>
Alex Shi <alexs@kernel.org> <alex.shi@intel.com>
Alex Shi <alexs@kernel.org> <alex.shi@linaro.org>
Alex Shi <alexs@kernel.org> <alex.shi@linux.alibaba.com>
+Aloka Dixit <quic_alokad@quicinc.com> <alokad@codeaurora.org>
Al Viro <viro@ftp.linux.org.uk>
Al Viro <viro@zenIV.linux.org.uk>
+Amit Blay <quic_ablay@quicinc.com> <ablay@codeaurora.org>
+Amit Nischal <quic_anischal@quicinc.com> <anischal@codeaurora.org>
Andi Kleen <ak@linux.intel.com> <ak@suse.de>
Andi Shyti <andi@etezian.org> <andi.shyti@samsung.com>
Andreas Herrmann <aherrman@de.ibm.com>
@@ -54,6 +60,8 @@ Andrey Ryabinin <ryabinin.a.a@gmail.com> <aryabinin@virtuozzo.com>
Andrzej Hajda <andrzej.hajda@intel.com> <a.hajda@samsung.com>
André Almeida <andrealmeid@igalia.com> <andrealmeid@collabora.com>
Andy Adamson <andros@citi.umich.edu>
+Anilkumar Kolli <quic_akolli@quicinc.com> <akolli@codeaurora.org>
+Anirudh Ghayal <quic_aghayal@quicinc.com> <aghayal@codeaurora.org>
Antoine Tenart <atenart@kernel.org> <antoine.tenart@bootlin.com>
Antoine Tenart <atenart@kernel.org> <antoine.tenart@free-electrons.com>
Antonio Ospite <ao2@ao2.it> <ao2@amarulasolutions.com>
@@ -62,9 +70,17 @@ Archit Taneja <archit@ti.com>
Ard Biesheuvel <ardb@kernel.org> <ard.biesheuvel@linaro.org>
Arnaud Patard <arnaud.patard@rtp-net.org>
Arnd Bergmann <arnd@arndb.de>
+Arun Kumar Neelakantam <quic_aneela@quicinc.com> <aneela@codeaurora.org>
+Ashok Raj Nagarajan <quic_arnagara@quicinc.com> <arnagara@codeaurora.org>
+Ashwin Chaugule <quic_ashwinc@quicinc.com> <ashwinc@codeaurora.org>
+Asutosh Das <quic_asutoshd@quicinc.com> <asutoshd@codeaurora.org>
Atish Patra <atishp@atishpatra.org> <atish.patra@wdc.com>
+Avaneesh Kumar Dwivedi <quic_akdwived@quicinc.com> <akdwived@codeaurora.org>
Axel Dyks <xl@xlsigned.net>
Axel Lin <axel.lin@gmail.com>
+Balakrishna Godavarthi <quic_bgodavar@quicinc.com> <bgodavar@codeaurora.org>
+Banajit Goswami <quic_bgoswami@quicinc.com> <bgoswami@codeaurora.org>
+Baochen Qiang <quic_bqiang@quicinc.com> <bqiang@codeaurora.org>
Baolin Wang <baolin.wang@linux.alibaba.com> <baolin.wang@linaro.org>
Baolin Wang <baolin.wang@linux.alibaba.com> <baolin.wang@spreadtrum.com>
Baolin Wang <baolin.wang@linux.alibaba.com> <baolin.wang@unisoc.com>
@@ -93,12 +109,15 @@ Brian Avery <b.avery@hp.com>
Brian King <brking@us.ibm.com>
Brian Silverman <bsilver16384@gmail.com> <brian.silverman@bluerivertech.com>
Cai Huoqing <cai.huoqing@linux.dev> <caihuoqing@baidu.com>
+Can Guo <quic_cang@quicinc.com> <cang@codeaurora.org>
+Carl Huang <quic_cjhuang@quicinc.com> <cjhuang@codeaurora.org>
Changbin Du <changbin.du@intel.com> <changbin.du@gmail.com>
Changbin Du <changbin.du@intel.com> <changbin.du@intel.com>
Chao Yu <chao@kernel.org> <chao2.yu@samsung.com>
Chao Yu <chao@kernel.org> <yuchao0@huawei.com>
Chris Chiu <chris.chiu@canonical.com> <chiu@endlessm.com>
Chris Chiu <chris.chiu@canonical.com> <chiu@endlessos.org>
+Chris Lew <quic_clew@quicinc.com> <clew@codeaurora.org>
Christian Borntraeger <borntraeger@linux.ibm.com> <borntraeger@de.ibm.com>
Christian Borntraeger <borntraeger@linux.ibm.com> <cborntra@de.ibm.com>
Christian Borntraeger <borntraeger@linux.ibm.com> <borntrae@de.ibm.com>
@@ -119,7 +138,10 @@ Daniel Borkmann <daniel@iogearbox.net> <dborkmann@redhat.com>
Daniel Borkmann <daniel@iogearbox.net> <dborkman@redhat.com>
Daniel Borkmann <daniel@iogearbox.net> <dxchgb@gmail.com>
David Brownell <david-b@pacbell.net>
+David Collins <quic_collinsd@quicinc.com> <collinsd@codeaurora.org>
David Woodhouse <dwmw2@shinybook.infradead.org>
+Dedy Lansky <quic_dlansky@quicinc.com> <dlansky@codeaurora.org>
+Deepak Kumar Singh <quic_deesin@quicinc.com> <deesin@codeaurora.org>
Dengcheng Zhu <dzhu@wavecomp.com> <dczhu@mips.com>
Dengcheng Zhu <dzhu@wavecomp.com> <dengcheng.zhu@gmail.com>
Dengcheng Zhu <dzhu@wavecomp.com> <dengcheng.zhu@imgtec.com>
@@ -136,6 +158,7 @@ Dmitry Safonov <0x7f454c46@gmail.com> <dsafonov@virtuozzo.com>
Domen Puncer <domen@coderock.org>
Douglas Gilbert <dougg@torque.net>
Ed L. Cashin <ecashin@coraid.com>
+Elliot Berman <quic_eberman@quicinc.com> <eberman@codeaurora.org>
Enric Balletbo i Serra <eballetbo@kernel.org> <enric.balletbo@collabora.com>
Enric Balletbo i Serra <eballetbo@kernel.org> <eballetbo@iseebcn.com>
Erik Kaneda <erik.kaneda@intel.com> <erik.schmauss@intel.com>
@@ -148,6 +171,7 @@ Faith Ekstrand <faith.ekstrand@collabora.com> <jason.ekstrand@collabora.com>
Felipe W Damasio <felipewd@terra.com.br>
Felix Kuhling <fxkuehl@gmx.de>
Felix Moeller <felix@derklecks.de>
+Fenglin Wu <quic_fenglinw@quicinc.com> <fenglinw@codeaurora.org>
Filipe Lautert <filipe@icewall.org>
Finn Thain <fthain@linux-m68k.org> <fthain@telegraphics.com.au>
Franck Bui-Huu <vagabon.xyz@gmail.com>
@@ -171,8 +195,11 @@ Greg Kurz <groug@kaod.org> <gkurz@linux.vnet.ibm.com>
Gregory CLEMENT <gregory.clement@bootlin.com> <gregory.clement@free-electrons.com>
Guilherme G. Piccoli <kernel@gpiccoli.net> <gpiccoli@linux.vnet.ibm.com>
Guilherme G. Piccoli <kernel@gpiccoli.net> <gpiccoli@canonical.com>
+Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com> <gokulsri@codeaurora.org>
+Govindaraj Saminathan <quic_gsamin@quicinc.com> <gsamin@codeaurora.org>
Guo Ren <guoren@kernel.org> <guoren@linux.alibaba.com>
Guo Ren <guoren@kernel.org> <ren_guo@c-sky.com>
+Guru Das Srinagesh <quic_gurus@quicinc.com> <gurus@codeaurora.org>
Gustavo Padovan <gustavo@las.ic.unicamp.br>
Gustavo Padovan <padovan@profusion.mobi>
Hanjun Guo <guohanjun@huawei.com> <hanjun.guo@linaro.org>
@@ -190,6 +217,7 @@ Huacai Chen <chenhuacai@kernel.org> <chenhuacai@loongson.cn>
J. Bruce Fields <bfields@fieldses.org> <bfields@redhat.com>
J. Bruce Fields <bfields@fieldses.org> <bfields@citi.umich.edu>
Jacob Shin <Jacob.Shin@amd.com>
+Jack Pham <quic_jackp@quicinc.com> <jackp@codeaurora.org>
Jaegeuk Kim <jaegeuk@kernel.org> <jaegeuk@google.com>
Jaegeuk Kim <jaegeuk@kernel.org> <jaegeuk.kim@samsung.com>
Jaegeuk Kim <jaegeuk@kernel.org> <jaegeuk@motorola.com>
@@ -217,10 +245,12 @@ Jayachandran C <c.jayachandran@gmail.com> <jchandra@digeo.com>
Jayachandran C <c.jayachandran@gmail.com> <jnair@caviumnetworks.com>
<jean-philippe@linaro.org> <jean-philippe.brucker@arm.com>
Jean Tourrilhes <jt@hpl.hp.com>
+Jeevan Shriram <quic_jshriram@quicinc.com> <jshriram@codeaurora.org>
Jeff Garzik <jgarzik@pretzel.yyz.us>
Jeff Layton <jlayton@kernel.org> <jlayton@poochiereds.net>
Jeff Layton <jlayton@kernel.org> <jlayton@primarydata.com>
Jeff Layton <jlayton@kernel.org> <jlayton@redhat.com>
+Jeffrey Hugo <quic_jhugo@quicinc.com> <jhugo@codeaurora.org>
Jens Axboe <axboe@kernel.dk> <axboe@suse.de>
Jens Axboe <axboe@kernel.dk> <jens.axboe@oracle.com>
Jens Axboe <axboe@kernel.dk> <axboe@fb.com>
@@ -228,6 +258,7 @@ Jens Axboe <axboe@kernel.dk> <axboe@meta.com>
Jens Osterkamp <Jens.Osterkamp@de.ibm.com>
Jernej Skrabec <jernej.skrabec@gmail.com> <jernej.skrabec@siol.net>
Jessica Zhang <quic_jesszhan@quicinc.com> <jesszhan@codeaurora.org>
+Jilai Wang <quic_jilaiw@quicinc.com> <jilaiw@codeaurora.org>
Jiri Pirko <jiri@resnulli.us> <jiri@nvidia.com>
Jiri Pirko <jiri@resnulli.us> <jiri@mellanox.com>
Jiri Pirko <jiri@resnulli.us> <jpirko@redhat.com>
@@ -238,6 +269,7 @@ Jiri Slaby <jirislaby@kernel.org> <jslaby@suse.cz>
Jiri Slaby <jirislaby@kernel.org> <xslaby@fi.muni.cz>
Jisheng Zhang <jszhang@kernel.org> <jszhang@marvell.com>
Jisheng Zhang <jszhang@kernel.org> <Jisheng.Zhang@synaptics.com>
+Jishnu Prakash <quic_jprakash@quicinc.com> <jprakash@codeaurora.org>
Johan Hovold <johan@kernel.org> <jhovold@gmail.com>
Johan Hovold <johan@kernel.org> <johan@hovoldconsulting.com>
John Crispin <john@phrozen.org> <blogic@openwrt.org>
@@ -255,6 +287,7 @@ Jordan Crouse <jordan@cosmicpenguin.net> <jcrouse@codeaurora.org>
<josh@joshtriplett.org> <josht@vnet.ibm.com>
Josh Poimboeuf <jpoimboe@kernel.org> <jpoimboe@redhat.com>
Josh Poimboeuf <jpoimboe@kernel.org> <jpoimboe@us.ibm.com>
+Jouni Malinen <quic_jouni@quicinc.com> <jouni@codeaurora.org>
Juha Yrjola <at solidboot.com>
Juha Yrjola <juha.yrjola@nokia.com>
Juha Yrjola <juha.yrjola@solidboot.com>
@@ -262,6 +295,8 @@ Julien Thierry <julien.thierry.kdev@gmail.com> <julien.thierry@arm.com>
Iskren Chernev <me@iskren.info> <iskren.chernev@gmail.com>
Kalle Valo <kvalo@kernel.org> <kvalo@codeaurora.org>
Kalyan Thota <quic_kalyant@quicinc.com> <kalyan_t@codeaurora.org>
+Karthikeyan Periyasamy <quic_periyasa@quicinc.com> <periyasa@codeaurora.org>
+Kathiravan T <quic_kathirav@quicinc.com> <kathirav@codeaurora.org>
Kay Sievers <kay.sievers@vrfy.org>
Kees Cook <keescook@chromium.org> <kees.cook@canonical.com>
Kees Cook <keescook@chromium.org> <keescook@google.com>
@@ -270,6 +305,8 @@ Kees Cook <keescook@chromium.org> <kees@ubuntu.com>
Keith Busch <kbusch@kernel.org> <keith.busch@intel.com>
Keith Busch <kbusch@kernel.org> <keith.busch@linux.intel.com>
Kenneth W Chen <kenneth.w.chen@intel.com>
+Kenneth Westfield <quic_kwestfie@quicinc.com> <kwestfie@codeaurora.org>
+Kiran Gunda <quic_kgunda@quicinc.com> <kgunda@codeaurora.org>
Kirill Tkhai <tkhai@ya.ru> <ktkhai@virtuozzo.com>
Konstantin Khlebnikov <koct9i@gmail.com> <khlebnikov@yandex-team.ru>
Konstantin Khlebnikov <koct9i@gmail.com> <k.khlebnikov@samsung.com>
@@ -278,6 +315,7 @@ Krishna Manikandan <quic_mkrishn@quicinc.com> <mkrishn@codeaurora.org>
Krzysztof Kozlowski <krzk@kernel.org> <k.kozlowski.k@gmail.com>
Krzysztof Kozlowski <krzk@kernel.org> <k.kozlowski@samsung.com>
Krzysztof Kozlowski <krzk@kernel.org> <krzysztof.kozlowski@canonical.com>
+Kshitiz Godara <quic_kgodara@quicinc.com> <kgodara@codeaurora.org>
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Kuogee Hsieh <quic_khsieh@quicinc.com> <khsieh@codeaurora.org>
Lee Jones <lee@kernel.org> <joneslee@google.com>
@@ -291,19 +329,27 @@ Leonid I Ananiev <leonid.i.ananiev@intel.com>
Leon Romanovsky <leon@kernel.org> <leon@leon.nu>
Leon Romanovsky <leon@kernel.org> <leonro@mellanox.com>
Leon Romanovsky <leon@kernel.org> <leonro@nvidia.com>
+Liam Mark <quic_lmark@quicinc.com> <lmark@codeaurora.org>
Linas Vepstas <linas@austin.ibm.com>
Linus Lüssing <linus.luessing@c0d3.blue> <linus.luessing@ascom.ch>
Linus Lüssing <linus.luessing@c0d3.blue> <linus.luessing@web.de>
<linux-hardening@vger.kernel.org> <kernel-hardening@lists.openwall.com>
Li Yang <leoyang.li@nxp.com> <leoli@freescale.com>
Li Yang <leoyang.li@nxp.com> <leo@zh-kernel.org>
+Lior David <quic_liord@quicinc.com> <liord@codeaurora.org>
Lorenzo Pieralisi <lpieralisi@kernel.org> <lorenzo.pieralisi@arm.com>
Luca Ceresoli <luca.ceresoli@bootlin.com> <luca@lucaceresoli.net>
Lukasz Luba <lukasz.luba@arm.com> <l.luba@partner.samsung.com>
+Luo Jie <quic_luoj@quicinc.com> <luoj@codeaurora.org>
Maciej W. Rozycki <macro@mips.com> <macro@imgtec.com>
Maciej W. Rozycki <macro@orcam.me.uk> <macro@linux-mips.org>
+Maharaja Kennadyrajan <quic_mkenna@quicinc.com> <mkenna@codeaurora.org>
+Maheshwar Ajja <quic_majja@quicinc.com> <majja@codeaurora.org>
+Malathi Gottam <quic_mgottam@quicinc.com> <mgottam@codeaurora.org>
+Manikanta Pubbisetty <quic_mpubbise@quicinc.com> <mpubbise@codeaurora.org>
Manivannan Sadhasivam <mani@kernel.org> <manivannanece23@gmail.com>
Manivannan Sadhasivam <mani@kernel.org> <manivannan.sadhasivam@linaro.org>
+Manoj Basapathi <quic_manojbm@quicinc.com> <manojbm@codeaurora.org>
Marcin Nowakowski <marcin.nowakowski@mips.com> <marcin.nowakowski@imgtec.com>
Marc Zyngier <maz@kernel.org> <marc.zyngier@arm.com>
Marek Behún <kabel@kernel.org> <marek.behun@nic.cz>
@@ -333,6 +379,7 @@ Matt Ranostay <matt.ranostay@konsulko.com> <matt@ranostay.consulting>
Matt Ranostay <mranostay@gmail.com> Matthew Ranostay <mranostay@embeddedalley.com>
Matt Ranostay <mranostay@gmail.com> <matt.ranostay@intel.com>
Matt Redfearn <matt.redfearn@mips.com> <matt.redfearn@imgtec.com>
+Maulik Shah <quic_mkshah@quicinc.com> <mkshah@codeaurora.org>
Mauro Carvalho Chehab <mchehab@kernel.org> <maurochehab@gmail.com>
Mauro Carvalho Chehab <mchehab@kernel.org> <mchehab@brturbo.com.br>
Mauro Carvalho Chehab <mchehab@kernel.org> <mchehab@infradead.org>
@@ -345,7 +392,10 @@ Maxim Mikityanskiy <maxtram95@gmail.com> <maximmi@nvidia.com>
Maxime Ripard <mripard@kernel.org> <maxime@cerno.tech>
Maxime Ripard <mripard@kernel.org> <maxime.ripard@bootlin.com>
Maxime Ripard <mripard@kernel.org> <maxime.ripard@free-electrons.com>
+Maya Erez <quic_merez@quicinc.com> <merez@codeaurora.org>
Mayuresh Janorkar <mayur@ti.com>
+Md Sadre Alam <quic_mdalam@quicinc.com> <mdalam@codeaurora.org>
+Miaoqing Pan <quic_miaoqing@quicinc.com> <miaoqing@codeaurora.org>
Michael Buesch <m@bues.ch>
Michal Simek <michal.simek@amd.com> <michal.simek@xilinx.com>
Michel Dänzer <michel@tungstengraphics.com>
@@ -356,6 +406,7 @@ Miguel Ojeda <ojeda@kernel.org> <miguel.ojeda.sandonis@gmail.com>
Mike Rapoport <rppt@kernel.org> <mike@compulab.co.il>
Mike Rapoport <rppt@kernel.org> <mike.rapoport@gmail.com>
Mike Rapoport <rppt@kernel.org> <rppt@linux.ibm.com>
+Mike Tipton <quic_mdtipton@quicinc.com> <mdtipton@codeaurora.org>
Miodrag Dinic <miodrag.dinic@mips.com> <miodrag.dinic@imgtec.com>
Miquel Raynal <miquel.raynal@bootlin.com> <miquel.raynal@free-electrons.com>
Mitesh shah <mshah@teja.com>
@@ -364,9 +415,13 @@ Morten Welinder <terra@gnome.org>
Morten Welinder <welinder@anemone.rentec.com>
Morten Welinder <welinder@darter.rentec.com>
Morten Welinder <welinder@troll.com>
+Mukesh Ojha <quic_mojha@quicinc.com> <mojha@codeaurora.org>
+Muna Sinada <quic_msinada@quicinc.com> <msinada@codeaurora.org>
+Murali Nalajala <quic_mnalajal@quicinc.com> <mnalajal@codeaurora.org>
Mythri P K <mythripk@ti.com>
Nadia Yvette Chambers <nyc@holomorphy.com> William Lee Irwin III <wli@holomorphy.com>
Nathan Chancellor <nathan@kernel.org> <natechancellor@gmail.com>
+Neeraj Upadhyay <quic_neeraju@quicinc.com> <neeraju@codeaurora.org>
Neil Armstrong <neil.armstrong@linaro.org> <narmstrong@baylibre.com>
Nguyen Anh Quynh <aquynh@gmail.com>
Nicholas Piggin <npiggin@gmail.com> <npiggen@suse.de>
@@ -385,6 +440,7 @@ Nikolay Aleksandrov <razor@blackwall.org> <nikolay@redhat.com>
Nikolay Aleksandrov <razor@blackwall.org> <nikolay@cumulusnetworks.com>
Nikolay Aleksandrov <razor@blackwall.org> <nikolay@nvidia.com>
Nikolay Aleksandrov <razor@blackwall.org> <nikolay@isovalent.com>
+Odelu Kukatla <quic_okukatla@quicinc.com> <okukatla@codeaurora.org>
Oleksandr Natalenko <oleksandr@natalenko.name> <oleksandr@redhat.com>
Oleksij Rempel <linux@rempel-privat.de> <bug-track@fisher-privat.net>
Oleksij Rempel <linux@rempel-privat.de> <external.Oleksij.Rempel@de.bosch.com>
@@ -392,6 +448,7 @@ Oleksij Rempel <linux@rempel-privat.de> <fixed-term.Oleksij.Rempel@de.bosch.com>
Oleksij Rempel <linux@rempel-privat.de> <o.rempel@pengutronix.de>
Oleksij Rempel <linux@rempel-privat.de> <ore@pengutronix.de>
Oliver Upton <oliver.upton@linux.dev> <oupton@google.com>
+Oza Pawandeep <quic_poza@quicinc.com> <poza@codeaurora.org>
Pali Rohár <pali@kernel.org> <pali.rohar@gmail.com>
Paolo 'Blaisorblade' Giarrusso <blaisorblade@yahoo.it>
Patrick Mochel <mochel@digitalimplant.org>
@@ -403,11 +460,14 @@ Paul E. McKenney <paulmck@kernel.org> <paulmck@linux.vnet.ibm.com>
Paul E. McKenney <paulmck@kernel.org> <paulmck@us.ibm.com>
Paul Mackerras <paulus@ozlabs.org> <paulus@samba.org>
Paul Mackerras <paulus@ozlabs.org> <paulus@au1.ibm.com>
+Pavankumar Kondeti <quic_pkondeti@quicinc.com> <pkondeti@codeaurora.org>
Peter A Jonsson <pj@ludd.ltu.se>
Peter Oruba <peter.oruba@amd.com>
Peter Oruba <peter@oruba.de>
Pratyush Anand <pratyush.anand@gmail.com> <pratyush.anand@st.com>
Praveen BP <praveenbp@ti.com>
+Pradeep Kumar Chitrapu <quic_pradeepc@quicinc.com> <pradeepc@codeaurora.org>
+Prasad Sodagudi <quic_psodagud@quicinc.com> <psodagud@codeaurora.org>
Punit Agrawal <punitagrawal@gmail.com> <punit.agrawal@arm.com>
Qais Yousef <qyousef@layalina.io> <qais.yousef@imgtec.com>
Qais Yousef <qyousef@layalina.io> <qais.yousef@arm.com>
@@ -416,10 +476,16 @@ Quentin Perret <qperret@qperret.net> <quentin.perret@arm.com>
Rafael J. Wysocki <rjw@rjwysocki.net> <rjw@sisk.pl>
Rajeev Nandan <quic_rajeevny@quicinc.com> <rajeevny@codeaurora.org>
Rajendra Nayak <quic_rjendra@quicinc.com> <rnayak@codeaurora.org>
+Rajeshwari Ravindra Kamble <quic_rkambl@quicinc.com> <rkambl@codeaurora.org>
+Raju P.L.S.S.S.N <quic_rplsssn@quicinc.com> <rplsssn@codeaurora.org>
Rajesh Shah <rajesh.shah@intel.com>
+Rakesh Pillai <quic_pillair@quicinc.com> <pillair@codeaurora.org>
Ralf Baechle <ralf@linux-mips.org>
Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
+Ram Chandra Jangir <quic_rjangir@quicinc.com> <rjangir@codeaurora.org>
Randy Dunlap <rdunlap@infradead.org> <rdunlap@xenotime.net>
+Ravi Kumar Bokka <quic_rbokka@quicinc.com> <rbokka@codeaurora.org>
+Ravi Kumar Siddojigari <quic_rsiddoji@quicinc.com> <rsiddoji@codeaurora.org>
Rémi Denis-Courmont <rdenis@simphalempin.com>
Ricardo Ribalda <ribalda@kernel.org> <ricardo@ribalda.com>
Ricardo Ribalda <ribalda@kernel.org> Ricardo Ribalda Delgado <ribalda@kernel.org>
@@ -428,6 +494,7 @@ Richard Leitner <richard.leitner@linux.dev> <dev@g0hl1n.net>
Richard Leitner <richard.leitner@linux.dev> <me@g0hl1n.net>
Richard Leitner <richard.leitner@linux.dev> <richard.leitner@skidata.com>
Robert Foss <rfoss@kernel.org> <robert.foss@linaro.org>
+Rocky Liao <quic_rjliao@quicinc.com> <rjliao@codeaurora.org>
Roman Gushchin <roman.gushchin@linux.dev> <guro@fb.com>
Roman Gushchin <roman.gushchin@linux.dev> <guroan@gmail.com>
Roman Gushchin <roman.gushchin@linux.dev> <klamm@yandex-team.ru>
@@ -445,22 +512,33 @@ Santosh Shilimkar <santosh.shilimkar@oracle.org>
Santosh Shilimkar <ssantosh@kernel.org>
Sarangdhar Joshi <spjoshi@codeaurora.org>
Sascha Hauer <s.hauer@pengutronix.de>
+Sahitya Tummala <quic_stummala@quicinc.com> <stummala@codeaurora.org>
+Sathishkumar Muruganandam <quic_murugana@quicinc.com> <murugana@codeaurora.org>
Satya Priya <quic_c_skakit@quicinc.com> <skakit@codeaurora.org>
S.Çağlar Onur <caglar@pardus.org.tr>
+Sayali Lokhande <quic_sayalil@quicinc.com> <sayalil@codeaurora.org>
Sean Christopherson <seanjc@google.com> <sean.j.christopherson@intel.com>
Sean Nyekjaer <sean@geanix.com> <sean.nyekjaer@prevas.dk>
+Sean Tranchetti <quic_stranche@quicinc.com> <stranche@codeaurora.org>
Sebastian Reichel <sre@kernel.org> <sebastian.reichel@collabora.co.uk>
Sebastian Reichel <sre@kernel.org> <sre@debian.org>
Sedat Dilek <sedat.dilek@gmail.com> <sedat.dilek@credativ.de>
+Senthilkumar N L <quic_snlakshm@quicinc.com> <snlakshm@codeaurora.org>
Seth Forshee <sforshee@kernel.org> <seth.forshee@canonical.com>
Shannon Nelson <shannon.nelson@amd.com> <snelson@pensando.io>
+Sharath Chandra Vurukala <quic_sharathv@quicinc.com> <sharathv@codeaurora.org>
Shiraz Hashim <shiraz.linux.kernel@gmail.com> <shiraz.hashim@st.com>
Shuah Khan <shuah@kernel.org> <shuahkhan@gmail.com>
Shuah Khan <shuah@kernel.org> <shuah.khan@hp.com>
Shuah Khan <shuah@kernel.org> <shuahkh@osg.samsung.com>
Shuah Khan <shuah@kernel.org> <shuah.kh@samsung.com>
+Sibi Sankar <quic_sibis@quicinc.com> <sibis@codeaurora.org>
+Sid Manning <quic_sidneym@quicinc.com> <sidneym@codeaurora.org>
Simon Arlott <simon@octiron.net> <simon@fire.lp0.eu>
Simon Kelley <simon@thekelleys.org.uk>
+Sricharan Ramabadhran <quic_srichara@quicinc.com> <sricharan@codeaurora.org>
+Srinivas Ramana <quic_sramana@quicinc.com> <sramana@codeaurora.org>
+Sriram R <quic_srirrama@quicinc.com> <srirrama@codeaurora.org>
Stéphane Witzmann <stephane.witzmann@ubpmes.univ-bpclermont.fr>
Stephen Hemminger <stephen@networkplumber.org> <shemminger@linux-foundation.org>
Stephen Hemminger <stephen@networkplumber.org> <shemminger@osdl.org>
@@ -468,22 +546,30 @@ Stephen Hemminger <stephen@networkplumber.org> <sthemmin@microsoft.com>
Stephen Hemminger <stephen@networkplumber.org> <sthemmin@vyatta.com>
Steve Wise <larrystevenwise@gmail.com> <swise@chelsio.com>
Steve Wise <larrystevenwise@gmail.com> <swise@opengridcomputing.com>
-Subash Abhinov Kasiviswanathan <subashab@codeaurora.org>
+Subash Abhinov Kasiviswanathan <quic_subashab@quicinc.com> <subashab@codeaurora.org>
+Subbaraman Narayanamurthy <quic_subbaram@quicinc.com> <subbaram@codeaurora.org>
Subhash Jadavani <subhashj@codeaurora.org>
+Sudarshan Rajagopalan <quic_sudaraja@quicinc.com> <sudaraja@codeaurora.org>
Sudeep Holla <sudeep.holla@arm.com> Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
Sumit Semwal <sumit.semwal@ti.com>
+Surabhi Vishnoi <quic_svishnoi@quicinc.com> <svishnoi@codeaurora.org>
Takashi YOSHII <takashi.yoshii.zj@renesas.com>
+Tamizh Chelvam Raja <quic_tamizhr@quicinc.com> <tamizhr@codeaurora.org>
+Taniya Das <quic_tdas@quicinc.com> <tdas@codeaurora.org>
Tejun Heo <htejun@gmail.com>
Thomas Graf <tgraf@suug.ch>
Thomas Körper <socketcan@esd.eu> <thomas.koerper@esd.eu>
Thomas Pedersen <twp@codeaurora.org>
Tiezhu Yang <yangtiezhu@loongson.cn> <kernelpatch@126.com>
+Tingwei Zhang <quic_tingwei@quicinc.com> <tingwei@codeaurora.org>
+Tirupathi Reddy <quic_tirupath@quicinc.com> <tirupath@codeaurora.org>
Tobias Klauser <tklauser@distanz.ch> <tobias.klauser@gmail.com>
Tobias Klauser <tklauser@distanz.ch> <klto@zhaw.ch>
Tobias Klauser <tklauser@distanz.ch> <tklauser@nuerscht.ch>
Tobias Klauser <tklauser@distanz.ch> <tklauser@xenon.tklauser.home>
Todor Tomov <todor.too@gmail.com> <todor.tomov@linaro.org>
Tony Luck <tony.luck@intel.com>
+Trilok Soni <quic_tsoni@quicinc.com> <tsoni@codeaurora.org>
TripleX Chung <xxx.phy@gmail.com> <triplex@zh-kernel.org>
TripleX Chung <xxx.phy@gmail.com> <zhongyu@18mail.cn>
Tsuneo Yoshioka <Tsuneo.Yoshioka@f-secure.com>
@@ -496,11 +582,17 @@ Uwe Kleine-König <ukleinek@strlen.de>
Uwe Kleine-König <ukl@pengutronix.de>
Uwe Kleine-König <Uwe.Kleine-Koenig@digi.com>
Valdis Kletnieks <Valdis.Kletnieks@vt.edu>
+Vara Reddy <quic_varar@quicinc.com> <varar@codeaurora.org>
+Varadarajan Narayanan <quic_varada@quicinc.com> <varada@codeaurora.org>
+Vasanthakumar Thiagarajan <quic_vthiagar@quicinc.com> <vthiagar@codeaurora.org>
Vasily Averin <vasily.averin@linux.dev> <vvs@virtuozzo.com>
Vasily Averin <vasily.averin@linux.dev> <vvs@openvz.org>
Vasily Averin <vasily.averin@linux.dev> <vvs@parallels.com>
Vasily Averin <vasily.averin@linux.dev> <vvs@sw.ru>
Valentin Schneider <vschneid@redhat.com> <valentin.schneider@arm.com>
+Veera Sundaram Sankaran <quic_veeras@quicinc.com> <veeras@codeaurora.org>
+Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com> <vbadigan@codeaurora.org>
+Venkateswara Naralasetty <quic_vnaralas@quicinc.com> <vnaralas@codeaurora.org>
Vikash Garodia <quic_vgarodia@quicinc.com> <vgarodia@codeaurora.org>
Vinod Koul <vkoul@kernel.org> <vinod.koul@intel.com>
Vinod Koul <vkoul@kernel.org> <vinod.koul@linux.intel.com>
@@ -510,11 +602,14 @@ Viresh Kumar <vireshk@kernel.org> <viresh.kumar@st.com>
Viresh Kumar <vireshk@kernel.org> <viresh.linux@gmail.com>
Viresh Kumar <viresh.kumar@linaro.org> <viresh.kumar@linaro.org>
Viresh Kumar <viresh.kumar@linaro.org> <viresh.kumar@linaro.com>
+Vivek Aknurwar <quic_viveka@quicinc.com> <viveka@codeaurora.org>
Vivien Didelot <vivien.didelot@gmail.com> <vivien.didelot@savoirfairelinux.com>
Vlad Dogaru <ddvlad@gmail.com> <vlad.dogaru@intel.com>
Vladimir Davydov <vdavydov.dev@gmail.com> <vdavydov@parallels.com>
Vladimir Davydov <vdavydov.dev@gmail.com> <vdavydov@virtuozzo.com>
WeiXiong Liao <gmpy.liaowx@gmail.com> <liaoweixiong@allwinnertech.com>
+Wen Gong <quic_wgong@quicinc.com> <wgong@codeaurora.org>
+Wesley Cheng <quic_wcheng@quicinc.com> <wcheng@codeaurora.org>
Will Deacon <will@kernel.org> <will.deacon@arm.com>
Wolfram Sang <wsa@kernel.org> <w.sang@pengutronix.de>
Wolfram Sang <wsa@kernel.org> <wsa@the-dreams.de>
--
2.25.1
^ permalink raw reply related [relevance 8%]
* Re: [PATCH v2 14/18] arm64: dts: qcom: sc7280: Add compat qcom,mdss-dsi-ctrl-sc7280
2022-11-07 23:56 6% ` [PATCH v2 14/18] arm64: dts: qcom: sc7280: Add compat qcom,mdss-dsi-ctrl-sc7280 Bryan O'Donoghue
@ 2022-11-08 16:41 0% ` Doug Anderson
0 siblings, 0 replies; 200+ results
From: Doug Anderson @ 2022-11-08 16:41 UTC (permalink / raw)
To: Bryan O'Donoghue
Cc: robdclark, quic_abhinavk, dmitry.baryshkov,
krzysztof.kozlowski+dt, robh+dt, quic_mkrishn, linux-arm-msm,
Andy Gross, Bjorn Andersson, Konrad Dybcio, devicetree,
linux-kernel, Sibi Sankar, Sai Prakash Ranjan
Hi,
On Mon, Nov 7, 2022 at 3:57 PM Bryan O'Donoghue
<bryan.odonoghue@linaro.org> wrote:
>
> Add silicon specific compatible qcom,mdss-dsi-ctrl-sc7280 to the
> mdss-dsi-ctrl block. This allows us to differentiate the specific bindings
> for sc7280 against the yaml documentation.
>
> Cc: Andy Gross <agross@kernel.org>
> Cc: Bjorn Andersson <andersson@kernel.org>
> Cc: Konrad Dybcio <konrad.dybcio@somainline.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
> Cc: linux-arm-msm@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> Cc: Douglas Anderson <dianders@chromium.org>
> Cc: Sibi Sankar <sibis@codeaurora.org>
> Cc: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
Reviewed-by: Douglas Anderson <dianders@chromium.org>
^ permalink raw reply [relevance 0%]
* [PATCH v2 14/18] arm64: dts: qcom: sc7280: Add compat qcom,mdss-dsi-ctrl-sc7280
[not found] <20221107235654.1769462-1-bryan.odonoghue@linaro.org>
@ 2022-11-07 23:56 6% ` Bryan O'Donoghue
2022-11-08 16:41 0% ` Doug Anderson
0 siblings, 1 reply; 200+ results
From: Bryan O'Donoghue @ 2022-11-07 23:56 UTC (permalink / raw)
To: robdclark, quic_abhinavk, dmitry.baryshkov,
krzysztof.kozlowski+dt, robh+dt, quic_mkrishn, linux-arm-msm
Cc: Bryan O'Donoghue, Andy Gross, Bjorn Andersson, Konrad Dybcio,
devicetree, linux-kernel, Douglas Anderson, Sibi Sankar,
Sai Prakash Ranjan
Add silicon specific compatible qcom,mdss-dsi-ctrl-sc7280 to the
mdss-dsi-ctrl block. This allows us to differentiate the specific bindings
for sc7280 against the yaml documentation.
Cc: Andy Gross <agross@kernel.org>
Cc: Bjorn Andersson <andersson@kernel.org>
Cc: Konrad Dybcio <konrad.dybcio@somainline.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: linux-arm-msm@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: Douglas Anderson <dianders@chromium.org>
Cc: Sibi Sankar <sibis@codeaurora.org>
Cc: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index a4d6e866b5999..7d4df38348e4f 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -3903,7 +3903,8 @@ opp-506666667 {
};
mdss_dsi: dsi@ae94000 {
- compatible = "qcom,mdss-dsi-ctrl";
+ compatible = "qcom,mdss-dsi-ctrl-sc7280",
+ "qcom,mdss-dsi-ctrl";
reg = <0 0x0ae94000 0 0x400>;
reg-names = "dsi_ctrl";
--
2.38.1
^ permalink raw reply related [relevance 6%]
* [PATCH 5.10 00/73] 5.10.152-rc1 review
@ 2022-10-28 12:02 3% Greg Kroah-Hartman
0 siblings, 0 replies; 200+ results
From: Greg Kroah-Hartman @ 2022-10-28 12:02 UTC (permalink / raw)
To: stable
Cc: Greg Kroah-Hartman, patches, linux-kernel, torvalds, akpm, linux,
shuah, patches, lkft-triage, pavel, jonathanh, f.fainelli,
sudipm.mukherjee, srw
This is the start of the stable review cycle for the 5.10.152 release.
There are 73 patches in this series, all will be posted as a response
to this one. If anyone has any issues with these being applied, please
let me know.
Responses should be made by Sun, 30 Oct 2022 12:02:13 +0000.
Anything received after that time might be too late.
The whole patch series can be found in one patch at:
https://www.kernel.org/pub/linux/kernel/v5.x/stable-review/patch-5.10.152-rc1.gz
or in the git tree and branch at:
git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git linux-5.10.y
and the diffstat can be found below.
thanks,
greg k-h
-------------
Pseudo-Shortlog of commits:
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Linux 5.10.152-rc1
Seth Jenkins <sethjenkins@google.com>
mm: /proc/pid/smaps_rollup: fix no vma's null-deref
Yu Kuai <yukuai3@huawei.com>
blk-wbt: fix that 'rwb->wc' is always set to 1 in wbt_init()
Avri Altman <avri.altman@wdc.com>
mmc: core: Add SD card quirk for broken discard
Nick Desaulniers <ndesaulniers@google.com>
Makefile.debug: re-enable debug info for .S files
Nathan Chancellor <nathan@kernel.org>
x86/Kconfig: Drop check for -mabi=ms for CONFIG_EFI_STUB
Werner Sembach <wse@tuxedocomputers.com>
ACPI: video: Force backlight native for more TongFang devices
Gaurav Kohli <gauravkohli@linux.microsoft.com>
hv_netvsc: Fix race between VF offering and VF association message from host
Adrian Hunter <adrian.hunter@intel.com>
perf/x86/intel/pt: Relax address filter validation
Conor Dooley <conor.dooley@microchip.com>
riscv: topology: fix default topology reporting
Conor Dooley <conor.dooley@microchip.com>
arm64: topology: move store_cpu_topology() to shared code
Sibi Sankar <sibis@codeaurora.org>
arm64: dts: qcom: sc7180-trogdor: Fixup modem memory region
Desmond Cheong Zhi Xi <desmondcheongzx@gmail.com>
fcntl: fix potential deadlocks for &fown_struct.lock
Pavel Tikhomirov <ptikhomirov@virtuozzo.com>
fcntl: make F_GETOWN(EX) return 0 on dead owner task
Rob Herring <robh@kernel.org>
perf: Skip and warn on unknown format 'configN' attrs
Jin Yao <yao.jin@linux.intel.com>
perf pmu: Validate raw event with sysfs exported format bits
Wenting Zhang <zephray@outlook.com>
riscv: always honor the CONFIG_CMDLINE_FORCE when parsing dtb
Kefeng Wang <wangkefeng.wang@huawei.com>
riscv: Add machine name to kernel boot log and stack dump output
Prathamesh Shete <pshete@nvidia.com>
mmc: sdhci-tegra: Use actual clock rate for SW tuning correction
M. Vefa Bicakci <m.v.b@runbox.com>
xen/gntdev: Accommodate VMA splitting
Juergen Gross <jgross@suse.com>
xen: assume XENFEAT_gnttab_map_avail_bits being set for pv guests
Steven Rostedt (Google) <rostedt@goodmis.org>
tracing: Do not free snapshot if tracer is on cmdline
sunliming <sunliming@kylinos.cn>
tracing: Simplify conditional compilation code in tracing_set_tracer()
Dario Binacchi <dario.binacchi@amarulasolutions.com>
dmaengine: mxs: use platform_driver_register
Fabio Estevam <festevam@gmail.com>
dmaengine: mxs-dma: Remove the unused .id_table
Dmitry Osipenko <dmitry.osipenko@collabora.com>
drm/virtio: Use appropriate atomic state in virtio_gpu_plane_cleanup_fb()
Jerry Snitselaar <jsnitsel@redhat.com>
iommu/vt-d: Clean up si_domain in the init_dmars() error path
Charlotte Tan <charlotte@extrahop.com>
iommu/vt-d: Allow NVS regions in arch_rmrr_sanity_check()
Felix Riemann <felix.riemann@sma.de>
net: phy: dp83822: disable MDI crossover status change interrupt
Eric Dumazet <edumazet@google.com>
net: sched: fix race condition in qdisc_graft()
Yang Yingliang <yangyingliang@huawei.com>
net: hns: fix possible memory leak in hnae_ae_register()
Pieter Jansen van Vuuren <pieter.jansen-van-vuuren@amd.com>
sfc: include vport_id in filter spec hash and equal()
Zhengchao Shao <shaozhengchao@huawei.com>
net: sched: sfb: fix null pointer access issue when sfb_init() fails
Zhengchao Shao <shaozhengchao@huawei.com>
net: sched: delete duplicate cleanup of backlog and qlen
Zhengchao Shao <shaozhengchao@huawei.com>
net: sched: cake: fix null pointer access issue when cake_init() fails
Serge Semin <Sergey.Semin@baikalelectronics.ru>
nvme-hwmon: kmalloc the NVME SMART log buffer
Christoph Hellwig <hch@lst.de>
nvme-hwmon: consistently ignore errors from nvme_hwmon_init
Daniel Wagner <dwagner@suse.de>
nvme-hwmon: Return error code when registration fails
Hannes Reinecke <hare@suse.de>
nvme-hwmon: rework to avoid devm allocation
Brett Creeley <brett@pensando.io>
ionic: catch NULL pointer issue on reconfig
Eric Dumazet <edumazet@google.com>
net: hsr: avoid possible NULL deref in skb_clone()
Zhang Xiaoxu <zhangxiaoxu5@huawei.com>
cifs: Fix xid leak in cifs_ses_add_channel()
Zhang Xiaoxu <zhangxiaoxu5@huawei.com>
cifs: Fix xid leak in cifs_flock()
Zhang Xiaoxu <zhangxiaoxu5@huawei.com>
cifs: Fix xid leak in cifs_copy_file_range()
Kuniyuki Iwashima <kuniyu@amazon.com>
udp: Update reuse->has_conns under reuseport_lock.
Kuniyuki Iwashima <kuniyu@amazon.co.jp>
tcp: Add num_closed_socks to struct sock_reuseport.
Harini Katakam <harini.katakam@amd.com>
net: phy: dp83867: Extend RX strap quirk for SGMII mode
Xiaobo Liu <cppcoffee@gmail.com>
net/atm: fix proc_mpc_write incorrect return value
Jonathan Cooper <jonathan.s.cooper@amd.com>
sfc: Change VF mac via PF as first preference if available.
José Expósito <jose.exposito89@gmail.com>
HID: magicmouse: Do not set BTN_MOUSE on double report
Jan Sokolowski <jan.sokolowski@intel.com>
i40e: Fix DMA mappings leak
Alexander Potapenko <glider@google.com>
tipc: fix an information leak in tipc_topsrv_kern_subscr
Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
tipc: Fix recognition of trial period
Tony Luck <tony.luck@intel.com>
ACPI: extlog: Handle multiple records
Filipe Manana <fdmanana@suse.com>
btrfs: fix processing of delayed tree block refs during backref walking
Filipe Manana <fdmanana@suse.com>
btrfs: fix processing of delayed data refs during backref walking
Jean-Francois Le Fillatre <jflf_kernel@gmx.com>
r8152: add PID for the Lenovo OneLink+ Dock
James Morse <james.morse@arm.com>
arm64: errata: Remove AES hwcap for COMPAT tasks
Yu Kuai <yukuai3@huawei.com>
blk-wbt: call rq_qos_add() after wb_normal is initialized
Lei Chen <lennychen@tencent.com>
block: wbt: Remove unnecessary invoking of wbt_update_limits in wbt_init
Bryan O'Donoghue <bryan.odonoghue@linaro.org>
media: venus: dec: Handle the case where find_format fails
Sean Young <sean@mess.org>
media: mceusb: set timeout to at least timeout provided
Eric Ren <renzhengeek@gmail.com>
KVM: arm64: vgic: Fix exit condition in scan_its_table()
Alexander Graf <graf@amazon.com>
kvm: Add support for arch compat vm ioctls
Fabien Parent <fabien.parent@linaro.org>
cpufreq: qcom: fix memory leak in error path
Kai-Heng Feng <kai.heng.feng@canonical.com>
ata: ahci: Match EM_MAX_SLOTS with SATA_PMP_MAX_PORTS
Alexander Stein <alexander.stein@ew.tq-group.com>
ata: ahci-imx: Fix MODULE_ALIAS
Zhang Rui <rui.zhang@intel.com>
hwmon/coretemp: Handle large core ID value
Borislav Petkov <bp@suse.de>
x86/microcode/AMD: Apply the patch early on every logical thread
Bryan O'Donoghue <bryan.odonoghue@linaro.org>
i2c: qcom-cci: Fix ordering of pm_runtime_xx and i2c_add_adapter
Fabien Parent <fabien.parent@linaro.org>
cpufreq: qcom: fix writes in read-only memory region
GONG, Ruiqi <gongruiqi1@huawei.com>
selinux: enable use of both GFP_KERNEL and GFP_ATOMIC in convert_context()
Joseph Qi <joseph.qi@linux.alibaba.com>
ocfs2: fix BUG when iput after ocfs2_mknod fails
Joseph Qi <joseph.qi@linux.alibaba.com>
ocfs2: clear dinode links count in case of error
-------------
Diffstat:
Documentation/arm64/silicon-errata.rst | 4 +
Makefile | 8 +-
arch/arm64/Kconfig | 16 ++++
.../boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi | 4 +
arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 2 +-
arch/arm64/include/asm/cpucaps.h | 3 +-
arch/arm64/kernel/cpu_errata.c | 16 ++++
arch/arm64/kernel/cpufeature.c | 13 ++-
arch/arm64/kernel/topology.c | 40 ---------
arch/arm64/kvm/vgic/vgic-its.c | 5 +-
arch/riscv/Kconfig | 2 +-
arch/riscv/kernel/setup.c | 13 ++-
arch/riscv/kernel/smpboot.c | 4 +-
arch/x86/Kconfig | 1 -
arch/x86/events/intel/pt.c | 63 ++++++++++++---
arch/x86/include/asm/iommu.h | 4 +-
arch/x86/kernel/cpu/microcode/amd.c | 16 +++-
block/blk-wbt.c | 11 +--
drivers/acpi/acpi_extlog.c | 33 +++++---
drivers/acpi/video_detect.c | 64 +++++++++++++++
drivers/ata/ahci.h | 2 +-
drivers/ata/ahci_imx.c | 2 +-
drivers/base/arch_topology.c | 19 +++++
drivers/cpufreq/qcom-cpufreq-nvmem.c | 10 ++-
drivers/dma/mxs-dma.c | 48 +++--------
drivers/gpu/drm/virtio/virtgpu_plane.c | 6 +-
drivers/hid/hid-magicmouse.c | 2 +-
drivers/hwmon/coretemp.c | 56 +++++++++----
drivers/i2c/busses/i2c-qcom-cci.c | 13 +--
drivers/iommu/intel/iommu.c | 5 ++
drivers/media/platform/qcom/venus/vdec.c | 2 +
drivers/media/rc/mceusb.c | 2 +-
drivers/mmc/core/block.c | 7 +-
drivers/mmc/core/card.h | 6 ++
drivers/mmc/core/quirks.h | 6 ++
drivers/mmc/host/sdhci-tegra.c | 2 +-
drivers/net/ethernet/hisilicon/hns/hnae.c | 4 +-
drivers/net/ethernet/intel/i40e/i40e_ethtool.c | 3 -
drivers/net/ethernet/intel/i40e/i40e_main.c | 16 ++--
drivers/net/ethernet/intel/i40e/i40e_txrx.c | 13 ++-
drivers/net/ethernet/intel/i40e/i40e_txrx.h | 1 -
drivers/net/ethernet/intel/i40e/i40e_xsk.c | 67 +++++++++++++--
drivers/net/ethernet/intel/i40e/i40e_xsk.h | 2 +-
drivers/net/ethernet/pensando/ionic/ionic_lif.c | 12 ++-
drivers/net/ethernet/sfc/ef10.c | 58 ++++++-------
drivers/net/ethernet/sfc/filter.h | 3 +-
drivers/net/ethernet/sfc/rx_common.c | 10 +--
drivers/net/hyperv/hyperv_net.h | 3 +-
drivers/net/hyperv/netvsc.c | 4 +
drivers/net/hyperv/netvsc_drv.c | 20 +++++
drivers/net/phy/dp83822.c | 3 +-
drivers/net/phy/dp83867.c | 8 ++
drivers/net/usb/cdc_ether.c | 7 ++
drivers/net/usb/r8152.c | 1 +
drivers/nvme/host/core.c | 7 +-
drivers/nvme/host/hwmon.c | 58 +++++++++----
drivers/nvme/host/nvme.h | 8 ++
drivers/xen/gntdev-common.h | 3 +-
drivers/xen/gntdev.c | 94 +++++++---------------
fs/btrfs/backref.c | 46 +++++++----
fs/cifs/cifsfs.c | 7 +-
fs/cifs/file.c | 11 ++-
fs/cifs/sess.c | 1 +
fs/fcntl.c | 32 +++++---
fs/ocfs2/namei.c | 23 +++---
fs/proc/task_mmu.c | 2 +-
include/linux/kvm_host.h | 2 +
include/linux/mmc/card.h | 1 +
include/net/sch_generic.h | 1 -
include/net/sock_reuseport.h | 16 ++--
kernel/trace/trace.c | 12 +--
net/atm/mpoa_proc.c | 3 +-
net/core/sock_reuseport.c | 91 ++++++++++++++++-----
net/hsr/hsr_forward.c | 12 +--
net/ipv4/datagram.c | 2 +-
net/ipv4/udp.c | 2 +-
net/ipv6/datagram.c | 2 +-
net/ipv6/udp.c | 2 +-
net/sched/sch_api.c | 5 +-
net/sched/sch_atm.c | 1 -
net/sched/sch_cake.c | 4 +
net/sched/sch_cbq.c | 1 -
net/sched/sch_choke.c | 2 -
net/sched/sch_drr.c | 2 -
net/sched/sch_dsmark.c | 2 -
net/sched/sch_etf.c | 3 -
net/sched/sch_ets.c | 2 -
net/sched/sch_fq_codel.c | 2 -
net/sched/sch_fq_pie.c | 3 -
net/sched/sch_hfsc.c | 2 -
net/sched/sch_htb.c | 2 -
net/sched/sch_multiq.c | 1 -
net/sched/sch_prio.c | 2 -
net/sched/sch_qfq.c | 2 -
net/sched/sch_red.c | 2 -
net/sched/sch_sfb.c | 5 +-
net/sched/sch_skbprio.c | 3 -
net/sched/sch_taprio.c | 2 -
net/sched/sch_tbf.c | 2 -
net/sched/sch_teql.c | 1 -
net/tipc/discover.c | 2 +-
net/tipc/topsrv.c | 2 +-
security/selinux/ss/services.c | 5 +-
security/selinux/ss/sidtab.c | 4 +-
security/selinux/ss/sidtab.h | 2 +-
tools/perf/util/parse-events.c | 6 ++
tools/perf/util/pmu.c | 50 ++++++++++++
tools/perf/util/pmu.h | 5 ++
tools/perf/util/pmu.l | 2 -
tools/perf/util/pmu.y | 15 +---
virt/kvm/kvm_main.c | 11 +++
111 files changed, 863 insertions(+), 475 deletions(-)
^ permalink raw reply [relevance 3%]
* [PATCH 5.10 00/79] 5.10.151-rc1 review
@ 2022-10-27 16:55 3% Greg Kroah-Hartman
0 siblings, 0 replies; 200+ results
From: Greg Kroah-Hartman @ 2022-10-27 16:55 UTC (permalink / raw)
To: stable
Cc: Greg Kroah-Hartman, patches, linux-kernel, torvalds, akpm, linux,
shuah, patches, lkft-triage, pavel, jonathanh, f.fainelli,
sudipm.mukherjee, srw
This is the start of the stable review cycle for the 5.10.151 release.
There are 79 patches in this series, all will be posted as a response
to this one. If anyone has any issues with these being applied, please
let me know.
Responses should be made by Sat, 29 Oct 2022 16:50:35 +0000.
Anything received after that time might be too late.
The whole patch series can be found in one patch at:
https://www.kernel.org/pub/linux/kernel/v5.x/stable-review/patch-5.10.151-rc1.gz
or in the git tree and branch at:
git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git linux-5.10.y
and the diffstat can be found below.
thanks,
greg k-h
-------------
Pseudo-Shortlog of commits:
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Linux 5.10.151-rc1
Seth Jenkins <sethjenkins@google.com>
mm: /proc/pid/smaps_rollup: fix no vma's null-deref
Yu Kuai <yukuai3@huawei.com>
blk-wbt: fix that 'rwb->wc' is always set to 1 in wbt_init()
Avri Altman <avri.altman@wdc.com>
mmc: core: Add SD card quirk for broken discard
Nick Desaulniers <ndesaulniers@google.com>
Makefile.debug: re-enable debug info for .S files
Nathan Chancellor <nathan@kernel.org>
x86/Kconfig: Drop check for -mabi=ms for CONFIG_EFI_STUB
Werner Sembach <wse@tuxedocomputers.com>
ACPI: video: Force backlight native for more TongFang devices
Gaurav Kohli <gauravkohli@linux.microsoft.com>
hv_netvsc: Fix race between VF offering and VF association message from host
Adrian Hunter <adrian.hunter@intel.com>
perf/x86/intel/pt: Relax address filter validation
Conor Dooley <conor.dooley@microchip.com>
riscv: topology: fix default topology reporting
Conor Dooley <conor.dooley@microchip.com>
arm64: topology: move store_cpu_topology() to shared code
Sibi Sankar <sibis@codeaurora.org>
arm64: dts: qcom: sc7180-trogdor: Fixup modem memory region
Desmond Cheong Zhi Xi <desmondcheongzx@gmail.com>
fcntl: fix potential deadlocks for &fown_struct.lock
Pavel Tikhomirov <ptikhomirov@virtuozzo.com>
fcntl: make F_GETOWN(EX) return 0 on dead owner task
Rob Herring <robh@kernel.org>
perf: Skip and warn on unknown format 'configN' attrs
Jin Yao <yao.jin@linux.intel.com>
perf pmu: Validate raw event with sysfs exported format bits
Wenting Zhang <zephray@outlook.com>
riscv: always honor the CONFIG_CMDLINE_FORCE when parsing dtb
Kefeng Wang <wangkefeng.wang@huawei.com>
riscv: Add machine name to kernel boot log and stack dump output
Prathamesh Shete <pshete@nvidia.com>
mmc: sdhci-tegra: Use actual clock rate for SW tuning correction
M. Vefa Bicakci <m.v.b@runbox.com>
xen/gntdev: Accommodate VMA splitting
Juergen Gross <jgross@suse.com>
xen: assume XENFEAT_gnttab_map_avail_bits being set for pv guests
Steven Rostedt (Google) <rostedt@goodmis.org>
tracing: Do not free snapshot if tracer is on cmdline
sunliming <sunliming@kylinos.cn>
tracing: Simplify conditional compilation code in tracing_set_tracer()
Dario Binacchi <dario.binacchi@amarulasolutions.com>
dmaengine: mxs: use platform_driver_register
Fabio Estevam <festevam@gmail.com>
dmaengine: mxs-dma: Remove the unused .id_table
Dmitry Osipenko <dmitry.osipenko@collabora.com>
drm/virtio: Use appropriate atomic state in virtio_gpu_plane_cleanup_fb()
Jerry Snitselaar <jsnitsel@redhat.com>
iommu/vt-d: Clean up si_domain in the init_dmars() error path
Charlotte Tan <charlotte@extrahop.com>
iommu/vt-d: Allow NVS regions in arch_rmrr_sanity_check()
Felix Riemann <felix.riemann@sma.de>
net: phy: dp83822: disable MDI crossover status change interrupt
Eric Dumazet <edumazet@google.com>
net: sched: fix race condition in qdisc_graft()
Yang Yingliang <yangyingliang@huawei.com>
net: hns: fix possible memory leak in hnae_ae_register()
Pieter Jansen van Vuuren <pieter.jansen-van-vuuren@amd.com>
sfc: include vport_id in filter spec hash and equal()
Zhengchao Shao <shaozhengchao@huawei.com>
net: sched: sfb: fix null pointer access issue when sfb_init() fails
Zhengchao Shao <shaozhengchao@huawei.com>
net: sched: delete duplicate cleanup of backlog and qlen
Zhengchao Shao <shaozhengchao@huawei.com>
net: sched: cake: fix null pointer access issue when cake_init() fails
Serge Semin <Sergey.Semin@baikalelectronics.ru>
nvme-hwmon: kmalloc the NVME SMART log buffer
Christoph Hellwig <hch@lst.de>
nvme-hwmon: consistently ignore errors from nvme_hwmon_init
Daniel Wagner <dwagner@suse.de>
nvme-hwmon: Return error code when registration fails
Hannes Reinecke <hare@suse.de>
nvme-hwmon: rework to avoid devm allocation
Brett Creeley <brett@pensando.io>
ionic: catch NULL pointer issue on reconfig
Eric Dumazet <edumazet@google.com>
net: hsr: avoid possible NULL deref in skb_clone()
Zhang Xiaoxu <zhangxiaoxu5@huawei.com>
cifs: Fix xid leak in cifs_ses_add_channel()
Zhang Xiaoxu <zhangxiaoxu5@huawei.com>
cifs: Fix xid leak in cifs_flock()
Zhang Xiaoxu <zhangxiaoxu5@huawei.com>
cifs: Fix xid leak in cifs_copy_file_range()
Kuniyuki Iwashima <kuniyu@amazon.com>
udp: Update reuse->has_conns under reuseport_lock.
Kuniyuki Iwashima <kuniyu@amazon.co.jp>
tcp: Add num_closed_socks to struct sock_reuseport.
Harini Katakam <harini.katakam@amd.com>
net: phy: dp83867: Extend RX strap quirk for SGMII mode
Xiaobo Liu <cppcoffee@gmail.com>
net/atm: fix proc_mpc_write incorrect return value
Jonathan Cooper <jonathan.s.cooper@amd.com>
sfc: Change VF mac via PF as first preference if available.
José Expósito <jose.exposito89@gmail.com>
HID: magicmouse: Do not set BTN_MOUSE on double report
Jan Sokolowski <jan.sokolowski@intel.com>
i40e: Fix DMA mappings leak
Alexander Potapenko <glider@google.com>
tipc: fix an information leak in tipc_topsrv_kern_subscr
Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
tipc: Fix recognition of trial period
Tony Luck <tony.luck@intel.com>
ACPI: extlog: Handle multiple records
Filipe Manana <fdmanana@suse.com>
btrfs: fix processing of delayed tree block refs during backref walking
Filipe Manana <fdmanana@suse.com>
btrfs: fix processing of delayed data refs during backref walking
Jean-Francois Le Fillatre <jflf_kernel@gmx.com>
r8152: add PID for the Lenovo OneLink+ Dock
James Morse <james.morse@arm.com>
arm64: errata: Remove AES hwcap for COMPAT tasks
Yu Kuai <yukuai3@huawei.com>
blk-wbt: call rq_qos_add() after wb_normal is initialized
Lei Chen <lennychen@tencent.com>
block: wbt: Remove unnecessary invoking of wbt_update_limits in wbt_init
Martin Rodriguez Reboredo <yakoyoku@gmail.com>
kbuild: Add skip_encoding_btf_enum64 option to pahole
Jiri Olsa <jolsa@redhat.com>
kbuild: Unify options for BTF generation for vmlinux and modules
Andrii Nakryiko <andrii@kernel.org>
kbuild: skip per-CPU BTF generation for pahole v1.18-v1.21
Javier Martinez Canillas <javierm@redhat.com>
kbuild: Quote OBJCOPY var to avoid a pahole call break the build
Ilya Leoshkevich <iii@linux.ibm.com>
bpf: Generate BTF_KIND_FLOAT when linking vmlinux
Bryan O'Donoghue <bryan.odonoghue@linaro.org>
media: venus: dec: Handle the case where find_format fails
Sean Young <sean@mess.org>
media: mceusb: set timeout to at least timeout provided
Eric Ren <renzhengeek@gmail.com>
KVM: arm64: vgic: Fix exit condition in scan_its_table()
Alexander Graf <graf@amazon.com>
kvm: Add support for arch compat vm ioctls
Fabien Parent <fabien.parent@linaro.org>
cpufreq: qcom: fix memory leak in error path
Kai-Heng Feng <kai.heng.feng@canonical.com>
ata: ahci: Match EM_MAX_SLOTS with SATA_PMP_MAX_PORTS
Alexander Stein <alexander.stein@ew.tq-group.com>
ata: ahci-imx: Fix MODULE_ALIAS
Zhang Rui <rui.zhang@intel.com>
hwmon/coretemp: Handle large core ID value
Borislav Petkov <bp@suse.de>
x86/microcode/AMD: Apply the patch early on every logical thread
Jon Hunter <jonathanh@nvidia.com>
cpufreq: tegra194: Fix module loading
Bryan O'Donoghue <bryan.odonoghue@linaro.org>
i2c: qcom-cci: Fix ordering of pm_runtime_xx and i2c_add_adapter
Fabien Parent <fabien.parent@linaro.org>
cpufreq: qcom: fix writes in read-only memory region
GONG, Ruiqi <gongruiqi1@huawei.com>
selinux: enable use of both GFP_KERNEL and GFP_ATOMIC in convert_context()
Joseph Qi <joseph.qi@linux.alibaba.com>
ocfs2: fix BUG when iput after ocfs2_mknod fails
Joseph Qi <joseph.qi@linux.alibaba.com>
ocfs2: clear dinode links count in case of error
-------------
Diffstat:
Documentation/arm64/silicon-errata.rst | 4 +
Makefile | 11 ++-
arch/arm64/Kconfig | 16 ++++
.../boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi | 4 +
arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 2 +-
arch/arm64/include/asm/cpucaps.h | 3 +-
arch/arm64/kernel/cpu_errata.c | 16 ++++
arch/arm64/kernel/cpufeature.c | 13 ++-
arch/arm64/kernel/topology.c | 40 ---------
arch/arm64/kvm/vgic/vgic-its.c | 5 +-
arch/riscv/Kconfig | 2 +-
arch/riscv/kernel/setup.c | 13 ++-
arch/riscv/kernel/smpboot.c | 4 +-
arch/x86/Kconfig | 1 -
arch/x86/events/intel/pt.c | 63 ++++++++++++---
arch/x86/include/asm/iommu.h | 4 +-
arch/x86/kernel/cpu/microcode/amd.c | 16 +++-
block/blk-wbt.c | 11 +--
drivers/acpi/acpi_extlog.c | 33 +++++---
drivers/acpi/video_detect.c | 64 +++++++++++++++
drivers/ata/ahci.h | 2 +-
drivers/ata/ahci_imx.c | 2 +-
drivers/base/arch_topology.c | 19 +++++
drivers/cpufreq/qcom-cpufreq-nvmem.c | 10 ++-
drivers/cpufreq/tegra194-cpufreq.c | 1 +
drivers/dma/mxs-dma.c | 48 +++--------
drivers/gpu/drm/virtio/virtgpu_plane.c | 6 +-
drivers/hid/hid-magicmouse.c | 2 +-
drivers/hwmon/coretemp.c | 56 +++++++++----
drivers/i2c/busses/i2c-qcom-cci.c | 13 +--
drivers/iommu/intel/iommu.c | 5 ++
drivers/media/platform/qcom/venus/vdec.c | 2 +
drivers/media/rc/mceusb.c | 2 +-
drivers/mmc/core/block.c | 7 +-
drivers/mmc/core/card.h | 6 ++
drivers/mmc/core/quirks.h | 6 ++
drivers/mmc/host/sdhci-tegra.c | 2 +-
drivers/net/ethernet/hisilicon/hns/hnae.c | 4 +-
drivers/net/ethernet/intel/i40e/i40e_ethtool.c | 3 -
drivers/net/ethernet/intel/i40e/i40e_main.c | 16 ++--
drivers/net/ethernet/intel/i40e/i40e_txrx.c | 13 ++-
drivers/net/ethernet/intel/i40e/i40e_txrx.h | 1 -
drivers/net/ethernet/intel/i40e/i40e_xsk.c | 67 +++++++++++++--
drivers/net/ethernet/intel/i40e/i40e_xsk.h | 2 +-
drivers/net/ethernet/pensando/ionic/ionic_lif.c | 12 ++-
drivers/net/ethernet/sfc/ef10.c | 58 ++++++-------
drivers/net/ethernet/sfc/filter.h | 3 +-
drivers/net/ethernet/sfc/rx_common.c | 10 +--
drivers/net/hyperv/hyperv_net.h | 3 +-
drivers/net/hyperv/netvsc.c | 4 +
drivers/net/hyperv/netvsc_drv.c | 20 +++++
drivers/net/phy/dp83822.c | 3 +-
drivers/net/phy/dp83867.c | 8 ++
drivers/net/usb/cdc_ether.c | 7 ++
drivers/net/usb/r8152.c | 1 +
drivers/nvme/host/core.c | 7 +-
drivers/nvme/host/hwmon.c | 58 +++++++++----
drivers/nvme/host/nvme.h | 8 ++
drivers/xen/gntdev-common.h | 3 +-
drivers/xen/gntdev.c | 94 +++++++---------------
fs/btrfs/backref.c | 46 +++++++----
fs/cifs/cifsfs.c | 7 +-
fs/cifs/file.c | 11 ++-
fs/cifs/sess.c | 1 +
fs/fcntl.c | 32 +++++---
fs/ocfs2/namei.c | 23 +++---
fs/proc/task_mmu.c | 2 +-
include/linux/kvm_host.h | 2 +
include/linux/mmc/card.h | 1 +
include/net/sch_generic.h | 1 -
include/net/sock_reuseport.h | 16 ++--
kernel/trace/trace.c | 12 +--
net/atm/mpoa_proc.c | 3 +-
net/core/sock_reuseport.c | 91 ++++++++++++++++-----
net/hsr/hsr_forward.c | 12 +--
net/ipv4/datagram.c | 2 +-
net/ipv4/udp.c | 2 +-
net/ipv6/datagram.c | 2 +-
net/ipv6/udp.c | 2 +-
net/sched/sch_api.c | 5 +-
net/sched/sch_atm.c | 1 -
net/sched/sch_cake.c | 4 +
net/sched/sch_cbq.c | 1 -
net/sched/sch_choke.c | 2 -
net/sched/sch_drr.c | 2 -
net/sched/sch_dsmark.c | 2 -
net/sched/sch_etf.c | 3 -
net/sched/sch_ets.c | 2 -
net/sched/sch_fq_codel.c | 2 -
net/sched/sch_fq_pie.c | 3 -
net/sched/sch_hfsc.c | 2 -
net/sched/sch_htb.c | 2 -
net/sched/sch_multiq.c | 1 -
net/sched/sch_prio.c | 2 -
net/sched/sch_qfq.c | 2 -
net/sched/sch_red.c | 2 -
net/sched/sch_sfb.c | 5 +-
net/sched/sch_skbprio.c | 3 -
net/sched/sch_taprio.c | 2 -
net/sched/sch_tbf.c | 2 -
net/sched/sch_teql.c | 1 -
net/tipc/discover.c | 2 +-
net/tipc/topsrv.c | 2 +-
scripts/link-vmlinux.sh | 2 +-
scripts/pahole-flags.sh | 21 +++++
security/selinux/ss/services.c | 5 +-
security/selinux/ss/sidtab.c | 4 +-
security/selinux/ss/sidtab.h | 2 +-
tools/perf/util/parse-events.c | 6 ++
tools/perf/util/pmu.c | 50 ++++++++++++
tools/perf/util/pmu.h | 5 ++
tools/perf/util/pmu.l | 2 -
tools/perf/util/pmu.y | 15 +---
virt/kvm/kvm_main.c | 11 +++
114 files changed, 889 insertions(+), 476 deletions(-)
^ permalink raw reply [relevance 3%]
* Re: [PATCH] arm64: dts: qcom: sc7180-trogdor: Fixup modem memory region
2022-10-17 18:22 8% [PATCH] " Stephen Boyd
@ 2022-10-27 10:14 0% ` Greg KH
0 siblings, 0 replies; 200+ results
From: Greg KH @ 2022-10-27 10:14 UTC (permalink / raw)
To: Stephen Boyd
Cc: stable, Sibi Sankar, linux-kernel, patches, Evan Green,
Bjorn Andersson, Alex Elder
On Mon, Oct 17, 2022 at 11:22:41AM -0700, Stephen Boyd wrote:
> From: Sibi Sankar <sibis@codeaurora.org>
>
> commit ef9a5d188d663753e73a3c8e8910ceab8e9305c4 upstream.
>
> The modem firmware memory requirements vary between 32M/140M on
> no-lte/lte skus respectively, so fixup the modem memory region
> to reflect the requirements.
>
> Reviewed-by: Evan Green <evgreen@chromium.org>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> Link: https://lore.kernel.org/r/1602786476-27833-1-git-send-email-sibis@codeaurora.org
> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> Acked-by: Alex Elder <elder@linaro.org>
> Signed-off-by: Stephen Boyd <swboyd@chromium.org>
> ---
>
> This fixes boot of the modem on trogdor boards with the DTS from 5.10.y
> stable tree. Without this patch I run into memory assignment errors and
> then the modem fails to boot.
Now queued up, thanks.
greg k-h
^ permalink raw reply [relevance 0%]
* [PATCH] arm64: dts: qcom: sc7180-trogdor: Fixup modem memory region
@ 2022-10-17 18:22 8% Stephen Boyd
2022-10-27 10:14 0% ` Greg KH
0 siblings, 1 reply; 200+ results
From: Stephen Boyd @ 2022-10-17 18:22 UTC (permalink / raw)
To: stable
Cc: Sibi Sankar, linux-kernel, patches, Evan Green, Bjorn Andersson,
Alex Elder
From: Sibi Sankar <sibis@codeaurora.org>
commit ef9a5d188d663753e73a3c8e8910ceab8e9305c4 upstream.
The modem firmware memory requirements vary between 32M/140M on
no-lte/lte skus respectively, so fixup the modem memory region
to reflect the requirements.
Reviewed-by: Evan Green <evgreen@chromium.org>
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Link: https://lore.kernel.org/r/1602786476-27833-1-git-send-email-sibis@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Alex Elder <elder@linaro.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
---
This fixes boot of the modem on trogdor boards with the DTS from 5.10.y
stable tree. Without this patch I run into memory assignment errors and
then the modem fails to boot.
arch/arm64/boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi | 4 ++++
arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 2 +-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi
index 44956e3165a1..469aad4e5948 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi
@@ -9,6 +9,10 @@ &ap_sar_sensor {
label = "proximity-wifi-lte";
};
+&mpss_mem {
+ reg = <0x0 0x86000000 0x0 0x8c00000>;
+};
+
&remoteproc_mpss {
firmware-name = "qcom/sc7180-trogdor/modem/mba.mbn",
"qcom/sc7180-trogdor/modem/qdsp6sw.mbn";
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
index 5b2a616c6257..cb2c47f13a8a 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
@@ -39,7 +39,7 @@ atf_mem: memory@80b00000 {
};
mpss_mem: memory@86000000 {
- reg = <0x0 0x86000000 0x0 0x8c00000>;
+ reg = <0x0 0x86000000 0x0 0x2000000>;
no-map;
};
base-commit: 014862eecf03f58066a957027dde73cbecdf4395
--
https://chromeos.dev
^ permalink raw reply related [relevance 8%]
* Re: [PATCH 5.10] arm64: dts: qcom: sc7180-trogdor: Fixup modem memory region
2022-10-14 21:53 8% [PATCH 5.10] arm64: dts: qcom: sc7180-trogdor: Fixup modem memory region Stephen Boyd
2022-10-16 10:50 0% ` Greg KH
@ 2022-10-16 12:47 0% ` Alex Elder
1 sibling, 0 replies; 200+ results
From: Alex Elder @ 2022-10-16 12:47 UTC (permalink / raw)
To: Stephen Boyd, stable
Cc: Sibi Sankar, linux-kernel, patches, Evan Green, Bjorn Andersson
On 10/14/22 4:53 PM, Stephen Boyd wrote:
> From: Sibi Sankar <sibis@codeaurora.org>
>
> commit ef9a5d188d663753e73a3c8e8910ceab8e9305c4 upstream.
When you re-send you can add this if you like:
Acked-by: Alex Elder <elder@linaro.org>
> The modem firmware memory requirements vary between 32M/140M on
> no-lte/lte skus respectively, so fixup the modem memory region
> to reflect the requirements.
>
> Reviewed-by: Evan Green <evgreen@chromium.org>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> Link: https://lore.kernel.org/r/1602786476-27833-1-git-send-email-sibis@codeaurora.org
> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> ---
>
> This fixes boot of the modem on trogdor boards with the DTS from 5.10.y
> stable tree. Without this patch I run into memory assignment errors and
> then the modem fails to boot.
>
> arch/arm64/boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi | 4 ++++
> arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 2 +-
> 2 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi
> index 44956e3165a1..469aad4e5948 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi
> @@ -9,6 +9,10 @@ &ap_sar_sensor {
> label = "proximity-wifi-lte";
> };
>
> +&mpss_mem {
> + reg = <0x0 0x86000000 0x0 0x8c00000>;
> +};
> +
> &remoteproc_mpss {
> firmware-name = "qcom/sc7180-trogdor/modem/mba.mbn",
> "qcom/sc7180-trogdor/modem/qdsp6sw.mbn";
> diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
> index 5b2a616c6257..cb2c47f13a8a 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
> @@ -39,7 +39,7 @@ atf_mem: memory@80b00000 {
> };
>
> mpss_mem: memory@86000000 {
> - reg = <0x0 0x86000000 0x0 0x8c00000>;
> + reg = <0x0 0x86000000 0x0 0x2000000>;
> no-map;
> };
>
>
> base-commit: 014862eecf03f58066a957027dde73cbecdf4395
^ permalink raw reply [relevance 0%]
* Re: [PATCH 5.10] arm64: dts: qcom: sc7180-trogdor: Fixup modem memory region
2022-10-14 21:53 8% [PATCH 5.10] arm64: dts: qcom: sc7180-trogdor: Fixup modem memory region Stephen Boyd
@ 2022-10-16 10:50 0% ` Greg KH
2022-10-16 12:47 0% ` Alex Elder
1 sibling, 0 replies; 200+ results
From: Greg KH @ 2022-10-16 10:50 UTC (permalink / raw)
To: Stephen Boyd
Cc: stable, Sibi Sankar, linux-kernel, patches, Alex Elder,
Evan Green, Bjorn Andersson
On Fri, Oct 14, 2022 at 02:53:02PM -0700, Stephen Boyd wrote:
> From: Sibi Sankar <sibis@codeaurora.org>
>
> commit ef9a5d188d663753e73a3c8e8910ceab8e9305c4 upstream.
>
> The modem firmware memory requirements vary between 32M/140M on
> no-lte/lte skus respectively, so fixup the modem memory region
> to reflect the requirements.
>
> Reviewed-by: Evan Green <evgreen@chromium.org>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> Link: https://lore.kernel.org/r/1602786476-27833-1-git-send-email-sibis@codeaurora.org
> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> ---
>
> This fixes boot of the modem on trogdor boards with the DTS from 5.10.y
> stable tree. Without this patch I run into memory assignment errors and
> then the modem fails to boot.
You forgot to sign off on this patch you forwarded on for stable
inclusion :(
Please fix up and resend if you wish to see it applied.
thanks,
greg k-h
^ permalink raw reply [relevance 0%]
* [PATCH 5.10] arm64: dts: qcom: sc7180-trogdor: Fixup modem memory region
@ 2022-10-14 21:53 8% Stephen Boyd
2022-10-16 10:50 0% ` Greg KH
2022-10-16 12:47 0% ` Alex Elder
0 siblings, 2 replies; 200+ results
From: Stephen Boyd @ 2022-10-14 21:53 UTC (permalink / raw)
To: stable
Cc: Sibi Sankar, linux-kernel, patches, Alex Elder, Evan Green,
Bjorn Andersson
From: Sibi Sankar <sibis@codeaurora.org>
commit ef9a5d188d663753e73a3c8e8910ceab8e9305c4 upstream.
The modem firmware memory requirements vary between 32M/140M on
no-lte/lte skus respectively, so fixup the modem memory region
to reflect the requirements.
Reviewed-by: Evan Green <evgreen@chromium.org>
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Link: https://lore.kernel.org/r/1602786476-27833-1-git-send-email-sibis@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
This fixes boot of the modem on trogdor boards with the DTS from 5.10.y
stable tree. Without this patch I run into memory assignment errors and
then the modem fails to boot.
arch/arm64/boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi | 4 ++++
arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 2 +-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi
index 44956e3165a1..469aad4e5948 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi
@@ -9,6 +9,10 @@ &ap_sar_sensor {
label = "proximity-wifi-lte";
};
+&mpss_mem {
+ reg = <0x0 0x86000000 0x0 0x8c00000>;
+};
+
&remoteproc_mpss {
firmware-name = "qcom/sc7180-trogdor/modem/mba.mbn",
"qcom/sc7180-trogdor/modem/qdsp6sw.mbn";
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
index 5b2a616c6257..cb2c47f13a8a 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
@@ -39,7 +39,7 @@ atf_mem: memory@80b00000 {
};
mpss_mem: memory@86000000 {
- reg = <0x0 0x86000000 0x0 0x8c00000>;
+ reg = <0x0 0x86000000 0x0 0x2000000>;
no-map;
};
base-commit: 014862eecf03f58066a957027dde73cbecdf4395
--
https://chromeos.dev
^ permalink raw reply related [relevance 8%]
* [PATCH 3/3] dt-bindings: reset: pdc: Update email address
2022-06-02 0:48 11% [PATCH 1/3] dt-bindings: interconnect: Update email address Sibi Sankar
2022-06-02 0:48 11% ` [PATCH 2/3] dt-bindings: reset: aoss: Update e-mail address Sibi Sankar
@ 2022-06-02 0:48 11% ` Sibi Sankar
1 sibling, 0 replies; 200+ results
From: Sibi Sankar @ 2022-06-02 0:48 UTC (permalink / raw)
To: bjorn.andersson
Cc: agross, djakov, robh+dt, krzysztof.kozlowski+dt, p.zabel,
linux-arm-msm, linux-kernel, linux-pm, devicetree, Sibi Sankar
Update email address to the quicinc.com domain.
Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
---
Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml b/Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml
index 831ea8d5d83f..ca5d79332189 100644
--- a/Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml
+++ b/Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm PDC Global
maintainers:
- - Sibi Sankar <sibis@codeaurora.org>
+ - Sibi Sankar <quic_sibis@quicinc.com>
description:
The bindings describes the reset-controller found on PDC-Global (Power Domain
--
2.7.4
^ permalink raw reply related [relevance 11%]
* [PATCH 2/3] dt-bindings: reset: aoss: Update e-mail address
2022-06-02 0:48 11% [PATCH 1/3] dt-bindings: interconnect: Update email address Sibi Sankar
@ 2022-06-02 0:48 11% ` Sibi Sankar
2022-06-02 0:48 11% ` [PATCH 3/3] dt-bindings: reset: pdc: Update email address Sibi Sankar
1 sibling, 0 replies; 200+ results
From: Sibi Sankar @ 2022-06-02 0:48 UTC (permalink / raw)
To: bjorn.andersson
Cc: agross, djakov, robh+dt, krzysztof.kozlowski+dt, p.zabel,
linux-arm-msm, linux-kernel, linux-pm, devicetree, Sibi Sankar
Update email address to the quicinc.com domain.
Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
---
Documentation/devicetree/bindings/reset/qcom,aoss-reset.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/reset/qcom,aoss-reset.yaml b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.yaml
index a054757f4d9f..d92e2b3cc83f 100644
--- a/Documentation/devicetree/bindings/reset/qcom,aoss-reset.yaml
+++ b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.yaml
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm AOSS Reset Controller
maintainers:
- - Sibi Sankar <sibis@codeaurora.org>
+ - Sibi Sankar <quic_sibis@quicinc.com>
description:
The bindings describe the reset-controller found on AOSS-CC (always on
--
2.7.4
^ permalink raw reply related [relevance 11%]
* [PATCH 1/3] dt-bindings: interconnect: Update email address
@ 2022-06-02 0:48 11% Sibi Sankar
2022-06-02 0:48 11% ` [PATCH 2/3] dt-bindings: reset: aoss: Update e-mail address Sibi Sankar
2022-06-02 0:48 11% ` [PATCH 3/3] dt-bindings: reset: pdc: Update email address Sibi Sankar
0 siblings, 2 replies; 200+ results
From: Sibi Sankar @ 2022-06-02 0:48 UTC (permalink / raw)
To: bjorn.andersson
Cc: agross, djakov, robh+dt, krzysztof.kozlowski+dt, p.zabel,
linux-arm-msm, linux-kernel, linux-pm, devicetree, Sibi Sankar
Update email address to the quicinc.com domain.
Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
---
Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
index 116e434d0daa..bf538c0c5a81 100644
--- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
+++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Operating State Manager (OSM) L3 Interconnect Provider
maintainers:
- - Sibi Sankar <sibis@codeaurora.org>
+ - Sibi Sankar <quic_sibis@quicinc.com>
description:
L3 cache bandwidth requirements on Qualcomm SoCs is serviced by the OSM.
--
2.7.4
^ permalink raw reply related [relevance 11%]
* [PATCH v5 2/4] PM / devfreq: Add cpu based scaling support to passive governor
[not found] ` <CGME20220517085448epcas1p46423db24a3211003238b6c5947228923@epcas1p4.samsung.com>
@ 2022-05-17 9:21 4% ` Chanwoo Choi
0 siblings, 0 replies; 200+ results
From: Chanwoo Choi @ 2022-05-17 9:21 UTC (permalink / raw)
To: linux-pm, linux-kernel
Cc: johnson.wang, mka, wenst, jia-wei.chang, andrew-sh.cheng, hsinyi,
m.szyprowski, saravanak, cw00.choi, myungjoo.ham, kyungmin.park,
Saravana Kannan, Sibi Sankar
From: Saravana Kannan <skannan@codeaurora.org>
Many CPU architectures have caches that can scale independent of the
CPUs. Frequency scaling of the caches is necessary to make sure that the
cache is not a performance bottleneck that leads to poor performance and
power. The same idea applies for RAM/DDR.
To achieve this, this patch adds support for cpu based scaling to the
passive governor. This is accomplished by taking the current frequency
of each CPU frequency domain and then adjust the frequency of the cache
(or any devfreq device) based on the frequency of the CPUs. It listens
to CPU frequency transition notifiers to keep itself up to date on the
current CPU frequency.
To decide the frequency of the device, the governor does one of the
following:
* Derives the optimal devfreq device opp from required-opps property of
the parent cpu opp_table.
* Scales the device frequency in proportion to the CPU frequency. So, if
the CPUs are running at their max frequency, the device runs at its
max frequency. If the CPUs are running at their min frequency, the
device runs at its min frequency. It is interpolated for frequencies
in between.
Tested-by: Chen-Yu Tsai <wenst@chromium.org>
Tested-by: Johnson Wang <johnson.wang@mediatek.com>
Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
[Sibi: Integrated cpu-freqmap governor into passive_governor]
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
[Chanwoo: Fix conflict with latest code and cleanup code]
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
drivers/devfreq/governor.h | 22 +++
drivers/devfreq/governor_passive.c | 298 +++++++++++++++++++++++++++--
include/linux/devfreq.h | 17 +-
3 files changed, 323 insertions(+), 14 deletions(-)
diff --git a/drivers/devfreq/governor.h b/drivers/devfreq/governor.h
index b0dbfee8bbf2..335c4a491254 100644
--- a/drivers/devfreq/governor.h
+++ b/drivers/devfreq/governor.h
@@ -47,6 +47,28 @@
#define DEVFREQ_GOV_ATTR_POLLING_INTERVAL BIT(0)
#define DEVFREQ_GOV_ATTR_TIMER BIT(1)
+/**
+ * struct devfreq_cpu_data - Hold the per-cpu data
+ * @dev: reference to cpu device.
+ * @first_cpu: the cpumask of the first cpu of a policy.
+ * @opp_table: reference to cpu opp table.
+ * @cur_freq: the current frequency of the cpu.
+ * @min_freq: the min frequency of the cpu.
+ * @max_freq: the max frequency of the cpu.
+ *
+ * This structure stores the required cpu_data of a cpu.
+ * This is auto-populated by the governor.
+ */
+struct devfreq_cpu_data {
+ struct device *dev;
+ unsigned int first_cpu;
+
+ struct opp_table *opp_table;
+ unsigned int cur_freq;
+ unsigned int min_freq;
+ unsigned int max_freq;
+};
+
/**
* struct devfreq_governor - Devfreq policy governor
* @node: list node - contains registered devfreq governors
diff --git a/drivers/devfreq/governor_passive.c b/drivers/devfreq/governor_passive.c
index fc09324a03e0..7f30088b500b 100644
--- a/drivers/devfreq/governor_passive.c
+++ b/drivers/devfreq/governor_passive.c
@@ -8,11 +8,85 @@
*/
#include <linux/module.h>
+#include <linux/cpu.h>
+#include <linux/cpufreq.h>
+#include <linux/cpumask.h>
+#include <linux/slab.h>
#include <linux/device.h>
#include <linux/devfreq.h>
#include "governor.h"
-static int devfreq_passive_get_target_freq(struct devfreq *devfreq,
+#define HZ_PER_KHZ 1000
+
+static unsigned long get_target_freq_by_required_opp(struct device *p_dev,
+ struct opp_table *p_opp_table,
+ struct opp_table *opp_table,
+ unsigned long *freq)
+{
+ struct dev_pm_opp *opp = NULL, *p_opp = NULL;
+ unsigned long target_freq;
+
+ if (!p_dev || !p_opp_table || !opp_table || !freq)
+ return 0;
+
+ p_opp = devfreq_recommended_opp(p_dev, freq, 0);
+ if (IS_ERR(p_opp))
+ return 0;
+
+ opp = dev_pm_opp_xlate_required_opp(p_opp_table, opp_table, p_opp);
+ dev_pm_opp_put(p_opp);
+
+ if (IS_ERR(opp))
+ return 0;
+
+ target_freq = dev_pm_opp_get_freq(opp);
+ dev_pm_opp_put(opp);
+
+ return target_freq;
+}
+
+static int get_target_freq_with_cpufreq(struct devfreq *devfreq,
+ unsigned long *target_freq)
+{
+ struct devfreq_passive_data *p_data =
+ (struct devfreq_passive_data *)devfreq->data;
+ struct devfreq_cpu_data *parent_cpu_data;
+ unsigned long cpu, cpu_cur, cpu_min, cpu_max, cpu_percent;
+ unsigned long dev_min, dev_max;
+ unsigned long freq = 0;
+
+ for_each_online_cpu(cpu) {
+ parent_cpu_data = p_data->parent_cpu_data[cpu];
+ if (!parent_cpu_data || parent_cpu_data->first_cpu != cpu)
+ continue;
+
+ /* Get target freq via required opps */
+ cpu_cur = parent_cpu_data->cur_freq * HZ_PER_KHZ;
+ freq = get_target_freq_by_required_opp(parent_cpu_data->dev,
+ parent_cpu_data->opp_table,
+ devfreq->opp_table, &cpu_cur);
+ if (freq) {
+ *target_freq = max(freq, *target_freq);
+ continue;
+ }
+
+ /* Use interpolation if required opps is not available */
+ devfreq_get_freq_range(devfreq, &dev_min, &dev_max);
+
+ cpu_min = parent_cpu_data->min_freq;
+ cpu_max = parent_cpu_data->max_freq;
+ cpu_cur = parent_cpu_data->cur_freq;
+
+ cpu_percent = ((cpu_cur - cpu_min) * 100) / (cpu_max - cpu_min);
+ freq = dev_min + mult_frac(dev_max - dev_min, cpu_percent, 100);
+
+ *target_freq = max(freq, *target_freq);
+ }
+
+ return 0;
+}
+
+static int get_target_freq_with_devfreq(struct devfreq *devfreq,
unsigned long *freq)
{
struct devfreq_passive_data *p_data
@@ -99,6 +173,181 @@ static int devfreq_passive_get_target_freq(struct devfreq *devfreq,
return 0;
}
+static int devfreq_passive_get_target_freq(struct devfreq *devfreq,
+ unsigned long *freq)
+{
+ struct devfreq_passive_data *p_data =
+ (struct devfreq_passive_data *)devfreq->data;
+ int ret;
+
+ if (!p_data)
+ return -EINVAL;
+
+ /*
+ * If the devfreq device with passive governor has the specific method
+ * to determine the next frequency, should use the get_target_freq()
+ * of struct devfreq_passive_data.
+ */
+ if (p_data->get_target_freq)
+ return p_data->get_target_freq(devfreq, freq);
+
+ switch (p_data->parent_type) {
+ case DEVFREQ_PARENT_DEV:
+ ret = get_target_freq_with_devfreq(devfreq, freq);
+ break;
+ case CPUFREQ_PARENT_DEV:
+ ret = get_target_freq_with_cpufreq(devfreq, freq);
+ break;
+ default:
+ ret = -EINVAL;
+ dev_err(&devfreq->dev, "Invalid parent type\n");
+ break;
+ }
+
+ return ret;
+}
+
+static int cpufreq_passive_notifier_call(struct notifier_block *nb,
+ unsigned long event, void *ptr)
+{
+ struct devfreq_passive_data *p_data =
+ container_of(nb, struct devfreq_passive_data, nb);
+ struct devfreq *devfreq = (struct devfreq *)p_data->this;
+ struct devfreq_cpu_data *parent_cpu_data;
+ struct cpufreq_freqs *freqs = ptr;
+ unsigned int cur_freq;
+ int ret;
+
+ if (event != CPUFREQ_POSTCHANGE || !freqs ||
+ !p_data->parent_cpu_data[freqs->policy->cpu])
+ return 0;
+
+ parent_cpu_data = p_data->parent_cpu_data[freqs->policy->cpu];
+ if (parent_cpu_data->cur_freq == freqs->new)
+ return 0;
+
+ cur_freq = parent_cpu_data->cur_freq;
+ parent_cpu_data->cur_freq = freqs->new;
+
+ mutex_lock(&devfreq->lock);
+ ret = devfreq_update_target(devfreq, freqs->new);
+ mutex_unlock(&devfreq->lock);
+ if (ret) {
+ parent_cpu_data->cur_freq = cur_freq;
+ dev_err(&devfreq->dev, "failed to update the frequency.\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int cpufreq_passive_unregister_notifier(struct devfreq *devfreq)
+{
+ struct devfreq_passive_data *p_data
+ = (struct devfreq_passive_data *)devfreq->data;
+ struct devfreq_cpu_data *parent_cpu_data;
+ int cpu, ret;
+
+ if (p_data->nb.notifier_call) {
+ ret = cpufreq_unregister_notifier(&p_data->nb,
+ CPUFREQ_TRANSITION_NOTIFIER);
+ if (ret < 0)
+ return ret;
+ }
+
+ for_each_possible_cpu(cpu) {
+ parent_cpu_data = p_data->parent_cpu_data[cpu];
+ if (!parent_cpu_data)
+ continue;
+
+ if (parent_cpu_data->opp_table)
+ dev_pm_opp_put_opp_table(parent_cpu_data->opp_table);
+ kfree(parent_cpu_data);
+ }
+
+ return 0;
+}
+
+static int cpufreq_passive_register_notifier(struct devfreq *devfreq)
+{
+ struct devfreq_passive_data *p_data
+ = (struct devfreq_passive_data *)devfreq->data;
+ struct device *dev = devfreq->dev.parent;
+ struct opp_table *opp_table = NULL;
+ struct devfreq_cpu_data *parent_cpu_data;
+ struct cpufreq_policy *policy;
+ struct device *cpu_dev;
+ unsigned int cpu;
+ int ret;
+
+ p_data->nb.notifier_call = cpufreq_passive_notifier_call;
+ ret = cpufreq_register_notifier(&p_data->nb, CPUFREQ_TRANSITION_NOTIFIER);
+ if (ret) {
+ dev_err(dev, "failed to register cpufreq notifier\n");
+ p_data->nb.notifier_call = NULL;
+ goto err;
+ }
+
+ for_each_possible_cpu(cpu) {
+ if (p_data->parent_cpu_data[cpu])
+ continue;
+
+ policy = cpufreq_cpu_get(cpu);
+ if (!policy) {
+ ret = -EPROBE_DEFER;
+ goto err;
+ }
+
+ parent_cpu_data = kzalloc(sizeof(*parent_cpu_data),
+ GFP_KERNEL);
+ if (!parent_cpu_data) {
+ ret = -ENOMEM;
+ goto err_put_policy;
+ }
+
+ cpu_dev = get_cpu_device(cpu);
+ if (!cpu_dev) {
+ dev_err(dev, "failed to get cpu device\n");
+ ret = -ENODEV;
+ goto err_free_cpu_data;
+ }
+
+ opp_table = dev_pm_opp_get_opp_table(cpu_dev);
+ if (IS_ERR(opp_table)) {
+ dev_err(dev, "failed to get opp_table of cpu%d\n", cpu);
+ ret = PTR_ERR(opp_table);
+ goto err_free_cpu_data;
+ }
+
+ parent_cpu_data->dev = cpu_dev;
+ parent_cpu_data->opp_table = opp_table;
+ parent_cpu_data->first_cpu = cpumask_first(policy->related_cpus);
+ parent_cpu_data->cur_freq = policy->cur;
+ parent_cpu_data->min_freq = policy->cpuinfo.min_freq;
+ parent_cpu_data->max_freq = policy->cpuinfo.max_freq;
+
+ p_data->parent_cpu_data[cpu] = parent_cpu_data;
+ cpufreq_cpu_put(policy);
+ }
+
+ mutex_lock(&devfreq->lock);
+ ret = devfreq_update_target(devfreq, 0L);
+ mutex_unlock(&devfreq->lock);
+ if (ret)
+ dev_err(dev, "failed to update the frequency\n");
+
+ return ret;
+
+err_free_cpu_data:
+ kfree(parent_cpu_data);
+err_put_policy:
+ cpufreq_cpu_put(policy);
+err:
+ WARN_ON(cpufreq_passive_unregister_notifier(devfreq));
+
+ return ret;
+}
+
static int devfreq_passive_notifier_call(struct notifier_block *nb,
unsigned long event, void *ptr)
{
@@ -131,30 +380,55 @@ static int devfreq_passive_notifier_call(struct notifier_block *nb,
return NOTIFY_DONE;
}
-static int devfreq_passive_event_handler(struct devfreq *devfreq,
- unsigned int event, void *data)
+static int devfreq_passive_unregister_notifier(struct devfreq *devfreq)
+{
+ struct devfreq_passive_data *p_data
+ = (struct devfreq_passive_data *)devfreq->data;
+ struct devfreq *parent = (struct devfreq *)p_data->parent;
+ struct notifier_block *nb = &p_data->nb;
+
+ return devfreq_unregister_notifier(parent, nb, DEVFREQ_TRANSITION_NOTIFIER);
+}
+
+static int devfreq_passive_register_notifier(struct devfreq *devfreq)
{
struct devfreq_passive_data *p_data
= (struct devfreq_passive_data *)devfreq->data;
struct devfreq *parent = (struct devfreq *)p_data->parent;
struct notifier_block *nb = &p_data->nb;
- int ret = 0;
if (!parent)
return -EPROBE_DEFER;
+ nb->notifier_call = devfreq_passive_notifier_call;
+ return devfreq_register_notifier(parent, nb, DEVFREQ_TRANSITION_NOTIFIER);
+}
+
+static int devfreq_passive_event_handler(struct devfreq *devfreq,
+ unsigned int event, void *data)
+{
+ struct devfreq_passive_data *p_data
+ = (struct devfreq_passive_data *)devfreq->data;
+ int ret = -EINVAL;
+
+ if (!p_data)
+ return -EINVAL;
+
+ if (!p_data->this)
+ p_data->this = devfreq;
+
switch (event) {
case DEVFREQ_GOV_START:
- if (!p_data->this)
- p_data->this = devfreq;
-
- nb->notifier_call = devfreq_passive_notifier_call;
- ret = devfreq_register_notifier(parent, nb,
- DEVFREQ_TRANSITION_NOTIFIER);
+ if (p_data->parent_type == DEVFREQ_PARENT_DEV)
+ ret = devfreq_passive_register_notifier(devfreq);
+ else if (p_data->parent_type == CPUFREQ_PARENT_DEV)
+ ret = cpufreq_passive_register_notifier(devfreq);
break;
case DEVFREQ_GOV_STOP:
- WARN_ON(devfreq_unregister_notifier(parent, nb,
- DEVFREQ_TRANSITION_NOTIFIER));
+ if (p_data->parent_type == DEVFREQ_PARENT_DEV)
+ WARN_ON(devfreq_passive_unregister_notifier(devfreq));
+ else if (p_data->parent_type == CPUFREQ_PARENT_DEV)
+ WARN_ON(cpufreq_passive_unregister_notifier(devfreq));
break;
default:
break;
diff --git a/include/linux/devfreq.h b/include/linux/devfreq.h
index 142474b4af96..b1e4a6f796ce 100644
--- a/include/linux/devfreq.h
+++ b/include/linux/devfreq.h
@@ -38,6 +38,7 @@ enum devfreq_timer {
struct devfreq;
struct devfreq_governor;
+struct devfreq_cpu_data;
struct thermal_cooling_device;
/**
@@ -288,6 +289,11 @@ struct devfreq_simple_ondemand_data {
#endif
#if IS_ENABLED(CONFIG_DEVFREQ_GOV_PASSIVE)
+enum devfreq_parent_dev_type {
+ DEVFREQ_PARENT_DEV,
+ CPUFREQ_PARENT_DEV,
+};
+
/**
* struct devfreq_passive_data - ``void *data`` fed to struct devfreq
* and devfreq_add_device
@@ -299,8 +305,11 @@ struct devfreq_simple_ondemand_data {
* using governors except for passive governor.
* If the devfreq device has the specific method to decide
* the next frequency, should use this callback.
- * @this: the devfreq instance of own device.
- * @nb: the notifier block for DEVFREQ_TRANSITION_NOTIFIER list
+ * @parent_type: the parent type of the device.
+ * @this: the devfreq instance of own device.
+ * @nb: the notifier block for DEVFREQ_TRANSITION_NOTIFIER or
+ * CPUFREQ_TRANSITION_NOTIFIER list.
+ * @parent_cpu_data: the state min/max/current frequency of all online cpu's.
*
* The devfreq_passive_data have to set the devfreq instance of parent
* device with governors except for the passive governor. But, don't need to
@@ -314,9 +323,13 @@ struct devfreq_passive_data {
/* Optional callback to decide the next frequency of passvice device */
int (*get_target_freq)(struct devfreq *this, unsigned long *freq);
+ /* Should set the type of parent device */
+ enum devfreq_parent_dev_type parent_type;
+
/* For passive governor's internal use. Don't need to set them */
struct devfreq *this;
struct notifier_block nb;
+ struct devfreq_cpu_data *parent_cpu_data[NR_CPUS];
};
#endif
--
2.17.1
^ permalink raw reply related [relevance 4%]
* Re: [PATCH v4 2/4] PM / devfreq: Add cpu based scaling support to passive governor
2022-05-12 22:34 0% ` Marek Szyprowski
@ 2022-05-13 4:46 0% ` Chanwoo Choi
0 siblings, 0 replies; 200+ results
From: Chanwoo Choi @ 2022-05-13 4:46 UTC (permalink / raw)
To: Marek Szyprowski, linux-pm, linux-kernel
Cc: johnson.wang, mka, wenst, jia-wei.chang, andrew-sh.cheng, hsinyi,
saravanak, cw00.choi, myungjoo.ham, kyungmin.park,
Saravana Kannan, Sibi Sankar, Krzysztof Kozlowski,
'Linux Samsung SOC'
On 22. 5. 13. 07:34, Marek Szyprowski wrote:
> Hi Chanwoo,
>
> On 11.05.2022 11:35, Chanwoo Choi wrote:
>> From: Saravana Kannan <skannan@codeaurora.org>
>>
>> Many CPU architectures have caches that can scale independent of the
>> CPUs. Frequency scaling of the caches is necessary to make sure that the
>> cache is not a performance bottleneck that leads to poor performance and
>> power. The same idea applies for RAM/DDR.
>>
>> To achieve this, this patch adds support for cpu based scaling to the
>> passive governor. This is accomplished by taking the current frequency
>> of each CPU frequency domain and then adjust the frequency of the cache
>> (or any devfreq device) based on the frequency of the CPUs. It listens
>> to CPU frequency transition notifiers to keep itself up to date on the
>> current CPU frequency.
>>
>> To decide the frequency of the device, the governor does one of the
>> following:
>> * Derives the optimal devfreq device opp from required-opps property of
>> the parent cpu opp_table.
>>
>> * Scales the device frequency in proportion to the CPU frequency. So, if
>> the CPUs are running at their max frequency, the device runs at its
>> max frequency. If the CPUs are running at their min frequency, the
>> device runs at its min frequency. It is interpolated for frequencies
>> in between.
>>
>> Tested-by: Chen-Yu Tsai <wenst@chromium.org>
>> Tested-by: Johnson Wang <johnson.wang@mediatek.com>
>> Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
>> [Sibi: Integrated cpu-freqmap governor into passive_governor]
>> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
>> [Chanwoo: Fix conflict with latest code and cleanup code]
>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>
> This patch landed in today's linux next-20220512 as commit 2ab415d4e4e6
> ("PM / devfreq: Add cpu based scaling support to passive governor").
>
> It triggers the following NULL pointer dereference on Exynos based boards:
>
> exynos-bus: new bus device registered: soc:bus-leftbus (100000 KHz ~
> 200000 KHz)
> exynos-bus: new bus device registered: soc:bus-rightbus (100000 KHz ~
> 200000 KHz)
> exynos-bus: new bus device registered: soc:bus-display (160000 KHz ~
> 200000 KHz)
> exynos-bus: new bus device registered: soc:bus-fsys (100000 KHz ~ 134000
> KHz)
> exynos-bus: new bus device registered: soc:bus-peri ( 50000 KHz ~ 100000
> KHz)
> exynos-bus: new bus device registered: soc:bus-mfc (100000 KHz ~ 200000 KHz)
> 8<--- cut here ---
> Unable to handle kernel NULL pointer dereference at virtual address 0000003c
> [0000003c] *pgd=00000000
> Internal error: Oops: 5 [#1] PREEMPT SMP ARM
> Modules linked in:
> CPU: 3 PID: 8 Comm: kworker/u8:0 Not tainted 5.18.0-rc6-next-20220512 #5014
> Hardware name: Samsung Exynos (Flattened Device Tree)
> Workqueue: devfreq_wq devfreq_monitor
> PC is at __mutex_lock+0x48/0x948
> LR is at lock_is_held_type+0x104/0x1a4
> pc : [<c0b93098>] lr : [<c0b8f2ec>] psr: 60000053
> sp : f0889dc0 ip : 600000d3 fp : c1dca624
> r10: c1dca44c r9 : 00000000 r8 : c1984104
> r7 : c1d7f000 r6 : 00000000 r5 : 00000001 r4 : 00000008
> r3 : 00000000 r2 : 00000000 r1 : 2de44000 r0 : 00000000
> Flags: nZCv IRQs on FIQs off Mode SVC_32 ISA ARM Segment none
> Control: 10c5387d Table: 4000404a DAC: 00000051
> Register r0 information: NULL pointer
> Register r1 information: non-paged memory
> Register r2 information: NULL pointer
> Register r3 information: NULL pointer
> Register r4 information: non-paged memory
> Register r5 information: non-paged memory
> Register r6 information: NULL pointer
> Register r7 information: slab task_struct start c1d7f000 pointer offset 0
> Register r8 information: non-slab/vmalloc memory
> Register r9 information: NULL pointer
> Register r10 information: slab kmalloc-2k start c1dca000 pointer offset
> 1100 size 2048
> Register r11 information: slab kmalloc-2k start c1dca000 pointer offset
> 1572 size 2048
> Register r12 information: non-paged memory
> Process kworker/u8:0 (pid: 8, stack limit = 0x(ptrval))
> Stack: (0xf0889dc0 to 0xf088a000)
> ...
> __mutex_lock from mutex_lock_nested+0x1c/0x24
> mutex_lock_nested from devfreq_passive_notifier_call+0x24/0x90
> devfreq_passive_notifier_call from srcu_notifier_call_chain+0x98/0x114
> srcu_notifier_call_chain from devfreq_set_target+0x6c/0x304
> devfreq_set_target from devfreq_update_target+0x98/0xe8
> devfreq_update_target from devfreq_monitor+0x28/0x1c0
> devfreq_monitor from process_one_work+0x288/0x774
> process_one_work from worker_thread+0x44/0x504
> worker_thread from kthread+0xf4/0x128
> kthread from ret_from_fork+0x14/0x2c
> Exception stack(0xf0889fb0 to 0xf0889ff8)
> ...
> ---[ end trace 0000000000000000 ]---
>
> The issue is caused by the lack of setting devfreq_passive_data->this
> pointer in devfreq_passive_register_notifier. However, after adding:
>
> @@ -395,6 +395,9 @@ static int devfreq_passive_register_notifier(struct
> devfreq *devfreq)
> if (!parent)
> return -EPROBE_DEFER;
>
> + if (!p_data->this)
> + p_data->this = devfreq;
> +
> nb->notifier_call = devfreq_passive_notifier_call;
> return devfreq_register_notifier(parent, nb,
> DEVFREQ_TRANSITION_NOTIFIER);
> }
>
> the NULL pointer dereference is gone, but I see the following warnings
> on Odroid U3 board, which were not present before this patch:
>
> devfreq soc:bus-acp: failed to update devfreq using passive governor
> devfreq soc:bus-c2c: failed to update devfreq using passive governor
> devfreq soc:bus-acp: failed to update devfreq using passive governor
> devfreq soc:bus-c2c: failed to update devfreq using passive governor
Hi Marek,
Thanks for the report. I'll fix it.
--
Best Regards,
Samsung Electronics
Chanwoo Choi
^ permalink raw reply [relevance 0%]
* Re: [PATCH v4 2/4] PM / devfreq: Add cpu based scaling support to passive governor
[not found] ` <CGME20220512223450eucas1p203b702e114dd2cd1bafcfd7d4c80b638@eucas1p2.samsung.com>
@ 2022-05-12 22:34 0% ` Marek Szyprowski
2022-05-13 4:46 0% ` Chanwoo Choi
0 siblings, 1 reply; 200+ results
From: Marek Szyprowski @ 2022-05-12 22:34 UTC (permalink / raw)
To: Chanwoo Choi, linux-pm, linux-kernel
Cc: johnson.wang, mka, wenst, jia-wei.chang, andrew-sh.cheng, hsinyi,
saravanak, cw00.choi, myungjoo.ham, kyungmin.park,
Saravana Kannan, Sibi Sankar, Krzysztof Kozlowski,
'Linux Samsung SOC'
Hi Chanwoo,
On 11.05.2022 11:35, Chanwoo Choi wrote:
> From: Saravana Kannan <skannan@codeaurora.org>
>
> Many CPU architectures have caches that can scale independent of the
> CPUs. Frequency scaling of the caches is necessary to make sure that the
> cache is not a performance bottleneck that leads to poor performance and
> power. The same idea applies for RAM/DDR.
>
> To achieve this, this patch adds support for cpu based scaling to the
> passive governor. This is accomplished by taking the current frequency
> of each CPU frequency domain and then adjust the frequency of the cache
> (or any devfreq device) based on the frequency of the CPUs. It listens
> to CPU frequency transition notifiers to keep itself up to date on the
> current CPU frequency.
>
> To decide the frequency of the device, the governor does one of the
> following:
> * Derives the optimal devfreq device opp from required-opps property of
> the parent cpu opp_table.
>
> * Scales the device frequency in proportion to the CPU frequency. So, if
> the CPUs are running at their max frequency, the device runs at its
> max frequency. If the CPUs are running at their min frequency, the
> device runs at its min frequency. It is interpolated for frequencies
> in between.
>
> Tested-by: Chen-Yu Tsai <wenst@chromium.org>
> Tested-by: Johnson Wang <johnson.wang@mediatek.com>
> Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
> [Sibi: Integrated cpu-freqmap governor into passive_governor]
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> [Chanwoo: Fix conflict with latest code and cleanup code]
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
This patch landed in today's linux next-20220512 as commit 2ab415d4e4e6
("PM / devfreq: Add cpu based scaling support to passive governor").
It triggers the following NULL pointer dereference on Exynos based boards:
exynos-bus: new bus device registered: soc:bus-leftbus (100000 KHz ~
200000 KHz)
exynos-bus: new bus device registered: soc:bus-rightbus (100000 KHz ~
200000 KHz)
exynos-bus: new bus device registered: soc:bus-display (160000 KHz ~
200000 KHz)
exynos-bus: new bus device registered: soc:bus-fsys (100000 KHz ~ 134000
KHz)
exynos-bus: new bus device registered: soc:bus-peri ( 50000 KHz ~ 100000
KHz)
exynos-bus: new bus device registered: soc:bus-mfc (100000 KHz ~ 200000 KHz)
8<--- cut here ---
Unable to handle kernel NULL pointer dereference at virtual address 0000003c
[0000003c] *pgd=00000000
Internal error: Oops: 5 [#1] PREEMPT SMP ARM
Modules linked in:
CPU: 3 PID: 8 Comm: kworker/u8:0 Not tainted 5.18.0-rc6-next-20220512 #5014
Hardware name: Samsung Exynos (Flattened Device Tree)
Workqueue: devfreq_wq devfreq_monitor
PC is at __mutex_lock+0x48/0x948
LR is at lock_is_held_type+0x104/0x1a4
pc : [<c0b93098>] lr : [<c0b8f2ec>] psr: 60000053
sp : f0889dc0 ip : 600000d3 fp : c1dca624
r10: c1dca44c r9 : 00000000 r8 : c1984104
r7 : c1d7f000 r6 : 00000000 r5 : 00000001 r4 : 00000008
r3 : 00000000 r2 : 00000000 r1 : 2de44000 r0 : 00000000
Flags: nZCv IRQs on FIQs off Mode SVC_32 ISA ARM Segment none
Control: 10c5387d Table: 4000404a DAC: 00000051
Register r0 information: NULL pointer
Register r1 information: non-paged memory
Register r2 information: NULL pointer
Register r3 information: NULL pointer
Register r4 information: non-paged memory
Register r5 information: non-paged memory
Register r6 information: NULL pointer
Register r7 information: slab task_struct start c1d7f000 pointer offset 0
Register r8 information: non-slab/vmalloc memory
Register r9 information: NULL pointer
Register r10 information: slab kmalloc-2k start c1dca000 pointer offset
1100 size 2048
Register r11 information: slab kmalloc-2k start c1dca000 pointer offset
1572 size 2048
Register r12 information: non-paged memory
Process kworker/u8:0 (pid: 8, stack limit = 0x(ptrval))
Stack: (0xf0889dc0 to 0xf088a000)
...
__mutex_lock from mutex_lock_nested+0x1c/0x24
mutex_lock_nested from devfreq_passive_notifier_call+0x24/0x90
devfreq_passive_notifier_call from srcu_notifier_call_chain+0x98/0x114
srcu_notifier_call_chain from devfreq_set_target+0x6c/0x304
devfreq_set_target from devfreq_update_target+0x98/0xe8
devfreq_update_target from devfreq_monitor+0x28/0x1c0
devfreq_monitor from process_one_work+0x288/0x774
process_one_work from worker_thread+0x44/0x504
worker_thread from kthread+0xf4/0x128
kthread from ret_from_fork+0x14/0x2c
Exception stack(0xf0889fb0 to 0xf0889ff8)
...
---[ end trace 0000000000000000 ]---
The issue is caused by the lack of setting devfreq_passive_data->this
pointer in devfreq_passive_register_notifier. However, after adding:
@@ -395,6 +395,9 @@ static int devfreq_passive_register_notifier(struct
devfreq *devfreq)
if (!parent)
return -EPROBE_DEFER;
+ if (!p_data->this)
+ p_data->this = devfreq;
+
nb->notifier_call = devfreq_passive_notifier_call;
return devfreq_register_notifier(parent, nb,
DEVFREQ_TRANSITION_NOTIFIER);
}
the NULL pointer dereference is gone, but I see the following warnings
on Odroid U3 board, which were not present before this patch:
devfreq soc:bus-acp: failed to update devfreq using passive governor
devfreq soc:bus-c2c: failed to update devfreq using passive governor
devfreq soc:bus-acp: failed to update devfreq using passive governor
devfreq soc:bus-c2c: failed to update devfreq using passive governor
> ---
> drivers/devfreq/governor.h | 22 +++
> drivers/devfreq/governor_passive.c | 297 +++++++++++++++++++++++++++--
> include/linux/devfreq.h | 17 +-
> 3 files changed, 322 insertions(+), 14 deletions(-)
> ...
Best regards
--
Marek Szyprowski, PhD
Samsung R&D Institute Poland
^ permalink raw reply [relevance 0%]
* [PATCH v4 2/4] PM / devfreq: Add cpu based scaling support to passive governor
@ 2022-05-11 9:35 4% ` Chanwoo Choi
[not found] ` <CGME20220512223450eucas1p203b702e114dd2cd1bafcfd7d4c80b638@eucas1p2.samsung.com>
0 siblings, 1 reply; 200+ results
From: Chanwoo Choi @ 2022-05-11 9:35 UTC (permalink / raw)
To: linux-pm, linux-kernel
Cc: johnson.wang, mka, wenst, jia-wei.chang, andrew-sh.cheng, hsinyi,
saravanak, cw00.choi, myungjoo.ham, kyungmin.park,
Saravana Kannan, Sibi Sankar
From: Saravana Kannan <skannan@codeaurora.org>
Many CPU architectures have caches that can scale independent of the
CPUs. Frequency scaling of the caches is necessary to make sure that the
cache is not a performance bottleneck that leads to poor performance and
power. The same idea applies for RAM/DDR.
To achieve this, this patch adds support for cpu based scaling to the
passive governor. This is accomplished by taking the current frequency
of each CPU frequency domain and then adjust the frequency of the cache
(or any devfreq device) based on the frequency of the CPUs. It listens
to CPU frequency transition notifiers to keep itself up to date on the
current CPU frequency.
To decide the frequency of the device, the governor does one of the
following:
* Derives the optimal devfreq device opp from required-opps property of
the parent cpu opp_table.
* Scales the device frequency in proportion to the CPU frequency. So, if
the CPUs are running at their max frequency, the device runs at its
max frequency. If the CPUs are running at their min frequency, the
device runs at its min frequency. It is interpolated for frequencies
in between.
Tested-by: Chen-Yu Tsai <wenst@chromium.org>
Tested-by: Johnson Wang <johnson.wang@mediatek.com>
Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
[Sibi: Integrated cpu-freqmap governor into passive_governor]
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
[Chanwoo: Fix conflict with latest code and cleanup code]
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
drivers/devfreq/governor.h | 22 +++
drivers/devfreq/governor_passive.c | 297 +++++++++++++++++++++++++++--
include/linux/devfreq.h | 17 +-
3 files changed, 322 insertions(+), 14 deletions(-)
diff --git a/drivers/devfreq/governor.h b/drivers/devfreq/governor.h
index b0dbfee8bbf2..335c4a491254 100644
--- a/drivers/devfreq/governor.h
+++ b/drivers/devfreq/governor.h
@@ -47,6 +47,28 @@
#define DEVFREQ_GOV_ATTR_POLLING_INTERVAL BIT(0)
#define DEVFREQ_GOV_ATTR_TIMER BIT(1)
+/**
+ * struct devfreq_cpu_data - Hold the per-cpu data
+ * @dev: reference to cpu device.
+ * @first_cpu: the cpumask of the first cpu of a policy.
+ * @opp_table: reference to cpu opp table.
+ * @cur_freq: the current frequency of the cpu.
+ * @min_freq: the min frequency of the cpu.
+ * @max_freq: the max frequency of the cpu.
+ *
+ * This structure stores the required cpu_data of a cpu.
+ * This is auto-populated by the governor.
+ */
+struct devfreq_cpu_data {
+ struct device *dev;
+ unsigned int first_cpu;
+
+ struct opp_table *opp_table;
+ unsigned int cur_freq;
+ unsigned int min_freq;
+ unsigned int max_freq;
+};
+
/**
* struct devfreq_governor - Devfreq policy governor
* @node: list node - contains registered devfreq governors
diff --git a/drivers/devfreq/governor_passive.c b/drivers/devfreq/governor_passive.c
index fc09324a03e0..3fba05beaf24 100644
--- a/drivers/devfreq/governor_passive.c
+++ b/drivers/devfreq/governor_passive.c
@@ -8,11 +8,84 @@
*/
#include <linux/module.h>
+#include <linux/cpu.h>
+#include <linux/cpufreq.h>
+#include <linux/cpumask.h>
+#include <linux/slab.h>
#include <linux/device.h>
#include <linux/devfreq.h>
#include "governor.h"
-static int devfreq_passive_get_target_freq(struct devfreq *devfreq,
+#define HZ_PER_KHZ 1000
+
+static unsigned long get_target_freq_by_required_opp(struct device *p_dev,
+ struct opp_table *p_opp_table,
+ struct opp_table *opp_table,
+ unsigned long freq)
+{
+ struct dev_pm_opp *opp = NULL, *p_opp = NULL;
+
+ if (!p_dev || !p_opp_table || !opp_table || !freq)
+ return 0;
+
+ p_opp = devfreq_recommended_opp(p_dev, &freq, 0);
+ if (IS_ERR(p_opp))
+ return 0;
+
+ opp = dev_pm_opp_xlate_required_opp(p_opp_table, opp_table, p_opp);
+ dev_pm_opp_put(p_opp);
+
+ if (IS_ERR(opp))
+ return 0;
+
+ freq = dev_pm_opp_get_freq(opp);
+ dev_pm_opp_put(opp);
+
+ return freq;
+}
+
+static int get_target_freq_with_cpufreq(struct devfreq *devfreq,
+ unsigned long *target_freq)
+{
+ struct devfreq_passive_data *p_data =
+ (struct devfreq_passive_data *)devfreq->data;
+ struct devfreq_cpu_data *parent_cpu_data;
+ unsigned long cpu, cpu_cur, cpu_min, cpu_max, cpu_percent;
+ unsigned long dev_min, dev_max;
+ unsigned long freq = 0;
+
+ for_each_online_cpu(cpu) {
+ parent_cpu_data = p_data->parent_cpu_data[cpu];
+ if (!parent_cpu_data || parent_cpu_data->first_cpu != cpu)
+ continue;
+
+ /* Get target freq via required opps */
+ cpu_cur = parent_cpu_data->cur_freq * HZ_PER_KHZ;
+ freq = get_target_freq_by_required_opp(parent_cpu_data->dev,
+ parent_cpu_data->opp_table,
+ devfreq->opp_table, cpu_cur);
+ if (freq) {
+ *target_freq = max(freq, *target_freq);
+ continue;
+ }
+
+ /* Use interpolation if required opps is not available */
+ devfreq_get_freq_range(devfreq, &dev_min, &dev_max);
+
+ cpu_min = parent_cpu_data->min_freq;
+ cpu_max = parent_cpu_data->max_freq;
+ cpu_cur = parent_cpu_data->cur_freq;
+
+ cpu_percent = ((cpu_cur - cpu_min) * 100) / (cpu_max - cpu_min);
+ freq = dev_min + mult_frac(dev_max - dev_min, cpu_percent, 100);
+
+ *target_freq = max(freq, *target_freq);
+ }
+
+ return 0;
+}
+
+static int get_target_freq_with_devfreq(struct devfreq *devfreq,
unsigned long *freq)
{
struct devfreq_passive_data *p_data
@@ -99,6 +172,184 @@ static int devfreq_passive_get_target_freq(struct devfreq *devfreq,
return 0;
}
+static int devfreq_passive_get_target_freq(struct devfreq *devfreq,
+ unsigned long *freq)
+{
+ struct devfreq_passive_data *p_data =
+ (struct devfreq_passive_data *)devfreq->data;
+ int ret;
+
+ if (!p_data)
+ return -EINVAL;
+
+ /*
+ * If the devfreq device with passive governor has the specific method
+ * to determine the next frequency, should use the get_target_freq()
+ * of struct devfreq_passive_data.
+ */
+ if (p_data->get_target_freq)
+ return p_data->get_target_freq(devfreq, freq);
+
+ switch (p_data->parent_type) {
+ case DEVFREQ_PARENT_DEV:
+ ret = get_target_freq_with_devfreq(devfreq, freq);
+ break;
+ case CPUFREQ_PARENT_DEV:
+ ret = get_target_freq_with_cpufreq(devfreq, freq);
+ break;
+ default:
+ ret = -EINVAL;
+ dev_err(&devfreq->dev, "Invalid parent type\n");
+ break;
+ }
+
+ return ret;
+}
+
+static int cpufreq_passive_notifier_call(struct notifier_block *nb,
+ unsigned long event, void *ptr)
+{
+ struct devfreq_passive_data *p_data =
+ container_of(nb, struct devfreq_passive_data, nb);
+ struct devfreq *devfreq = (struct devfreq *)p_data->this;
+ struct devfreq_cpu_data *parent_cpu_data;
+ struct cpufreq_freqs *freqs = ptr;
+ unsigned int cur_freq;
+ int ret;
+
+ if (event != CPUFREQ_POSTCHANGE || !freqs ||
+ !p_data->parent_cpu_data[freqs->policy->cpu])
+ return 0;
+
+ parent_cpu_data = p_data->parent_cpu_data[freqs->policy->cpu];
+ if (parent_cpu_data->cur_freq == freqs->new)
+ return 0;
+
+ cur_freq = parent_cpu_data->cur_freq;
+ parent_cpu_data->cur_freq = freqs->new;
+
+ mutex_lock(&devfreq->lock);
+ ret = devfreq_update_target(devfreq, freqs->new);
+ mutex_unlock(&devfreq->lock);
+ if (ret) {
+ parent_cpu_data->cur_freq = cur_freq;
+ dev_err(&devfreq->dev, "failed to update the frequency.\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int cpufreq_passive_unregister_notifier(struct devfreq *devfreq)
+{
+ struct devfreq_passive_data *p_data
+ = (struct devfreq_passive_data *)devfreq->data;
+ struct devfreq_cpu_data *parent_cpu_data;
+ int cpu, ret;
+
+ if (p_data->nb.notifier_call) {
+ ret = cpufreq_unregister_notifier(&p_data->nb,
+ CPUFREQ_TRANSITION_NOTIFIER);
+ if (ret < 0)
+ return ret;
+ }
+
+ for_each_possible_cpu(cpu) {
+ parent_cpu_data = p_data->parent_cpu_data[cpu];
+ if (!parent_cpu_data)
+ continue;
+
+ if (parent_cpu_data->opp_table)
+ dev_pm_opp_put_opp_table(parent_cpu_data->opp_table);
+ kfree(parent_cpu_data);
+ }
+
+ return 0;
+}
+
+static int cpufreq_passive_register_notifier(struct devfreq *devfreq)
+{
+ struct devfreq_passive_data *p_data
+ = (struct devfreq_passive_data *)devfreq->data;
+ struct device *dev = devfreq->dev.parent;
+ struct opp_table *opp_table = NULL;
+ struct devfreq_cpu_data *parent_cpu_data;
+ struct cpufreq_policy *policy;
+ struct device *cpu_dev;
+ unsigned int cpu;
+ int ret;
+
+ if (!p_data->this)
+ p_data->this = devfreq;
+
+ p_data->nb.notifier_call = cpufreq_passive_notifier_call;
+ ret = cpufreq_register_notifier(&p_data->nb, CPUFREQ_TRANSITION_NOTIFIER);
+ if (ret) {
+ dev_err(dev, "failed to register cpufreq notifier\n");
+ p_data->nb.notifier_call = NULL;
+ goto err;
+ }
+
+ for_each_possible_cpu(cpu) {
+ if (p_data->parent_cpu_data[cpu])
+ continue;
+
+ policy = cpufreq_cpu_get(cpu);
+ if (!policy) {
+ ret = -EPROBE_DEFER;
+ goto err;
+ }
+
+ parent_cpu_data = kzalloc(sizeof(*parent_cpu_data),
+ GFP_KERNEL);
+ if (!parent_cpu_data) {
+ ret = -ENOMEM;
+ goto err_put_policy;
+ }
+
+ cpu_dev = get_cpu_device(cpu);
+ if (!cpu_dev) {
+ dev_err(dev, "failed to get cpu device\n");
+ ret = -ENODEV;
+ goto err_free_cpu_data;
+ }
+
+ opp_table = dev_pm_opp_get_opp_table(cpu_dev);
+ if (IS_ERR(opp_table)) {
+ dev_err(dev, "failed to get opp_table of cpu%d\n", cpu);
+ ret = PTR_ERR(opp_table);
+ goto err_free_cpu_data;
+ }
+
+ parent_cpu_data->dev = cpu_dev;
+ parent_cpu_data->opp_table = opp_table;
+ parent_cpu_data->first_cpu = cpumask_first(policy->related_cpus);
+ parent_cpu_data->cur_freq = policy->cur;
+ parent_cpu_data->min_freq = policy->cpuinfo.min_freq;
+ parent_cpu_data->max_freq = policy->cpuinfo.max_freq;
+
+ p_data->parent_cpu_data[cpu] = parent_cpu_data;
+ cpufreq_cpu_put(policy);
+ }
+
+ mutex_lock(&devfreq->lock);
+ ret = devfreq_update_target(devfreq, 0L);
+ mutex_unlock(&devfreq->lock);
+ if (ret)
+ dev_err(dev, "failed to update the frequency\n");
+
+ return ret;
+
+err_free_cpu_data:
+ kfree(parent_cpu_data);
+err_put_policy:
+ cpufreq_cpu_put(policy);
+err:
+ WARN_ON(cpufreq_passive_unregister_notifier(devfreq));
+
+ return ret;
+}
+
static int devfreq_passive_notifier_call(struct notifier_block *nb,
unsigned long event, void *ptr)
{
@@ -131,30 +382,52 @@ static int devfreq_passive_notifier_call(struct notifier_block *nb,
return NOTIFY_DONE;
}
-static int devfreq_passive_event_handler(struct devfreq *devfreq,
- unsigned int event, void *data)
+static int devfreq_passive_unregister_notifier(struct devfreq *devfreq)
+{
+ struct devfreq_passive_data *p_data
+ = (struct devfreq_passive_data *)devfreq->data;
+ struct devfreq *parent = (struct devfreq *)p_data->parent;
+ struct notifier_block *nb = &p_data->nb;
+
+ return devfreq_unregister_notifier(parent, nb, DEVFREQ_TRANSITION_NOTIFIER);
+}
+
+static int devfreq_passive_register_notifier(struct devfreq *devfreq)
{
struct devfreq_passive_data *p_data
= (struct devfreq_passive_data *)devfreq->data;
struct devfreq *parent = (struct devfreq *)p_data->parent;
struct notifier_block *nb = &p_data->nb;
- int ret = 0;
if (!parent)
return -EPROBE_DEFER;
+ nb->notifier_call = devfreq_passive_notifier_call;
+ return devfreq_register_notifier(parent, nb, DEVFREQ_TRANSITION_NOTIFIER);
+}
+
+static int devfreq_passive_event_handler(struct devfreq *devfreq,
+ unsigned int event, void *data)
+{
+ struct devfreq_passive_data *p_data
+ = (struct devfreq_passive_data *)devfreq->data;
+ int ret = -EINVAL;
+
+ if (!p_data)
+ return -EINVAL;
+
switch (event) {
case DEVFREQ_GOV_START:
- if (!p_data->this)
- p_data->this = devfreq;
-
- nb->notifier_call = devfreq_passive_notifier_call;
- ret = devfreq_register_notifier(parent, nb,
- DEVFREQ_TRANSITION_NOTIFIER);
+ if (p_data->parent_type == DEVFREQ_PARENT_DEV)
+ ret = devfreq_passive_register_notifier(devfreq);
+ else if (p_data->parent_type == CPUFREQ_PARENT_DEV)
+ ret = cpufreq_passive_register_notifier(devfreq);
break;
case DEVFREQ_GOV_STOP:
- WARN_ON(devfreq_unregister_notifier(parent, nb,
- DEVFREQ_TRANSITION_NOTIFIER));
+ if (p_data->parent_type == DEVFREQ_PARENT_DEV)
+ WARN_ON(devfreq_passive_unregister_notifier(devfreq));
+ else if (p_data->parent_type == CPUFREQ_PARENT_DEV)
+ WARN_ON(cpufreq_passive_unregister_notifier(devfreq));
break;
default:
break;
diff --git a/include/linux/devfreq.h b/include/linux/devfreq.h
index 142474b4af96..b1e4a6f796ce 100644
--- a/include/linux/devfreq.h
+++ b/include/linux/devfreq.h
@@ -38,6 +38,7 @@ enum devfreq_timer {
struct devfreq;
struct devfreq_governor;
+struct devfreq_cpu_data;
struct thermal_cooling_device;
/**
@@ -288,6 +289,11 @@ struct devfreq_simple_ondemand_data {
#endif
#if IS_ENABLED(CONFIG_DEVFREQ_GOV_PASSIVE)
+enum devfreq_parent_dev_type {
+ DEVFREQ_PARENT_DEV,
+ CPUFREQ_PARENT_DEV,
+};
+
/**
* struct devfreq_passive_data - ``void *data`` fed to struct devfreq
* and devfreq_add_device
@@ -299,8 +305,11 @@ struct devfreq_simple_ondemand_data {
* using governors except for passive governor.
* If the devfreq device has the specific method to decide
* the next frequency, should use this callback.
- * @this: the devfreq instance of own device.
- * @nb: the notifier block for DEVFREQ_TRANSITION_NOTIFIER list
+ * @parent_type: the parent type of the device.
+ * @this: the devfreq instance of own device.
+ * @nb: the notifier block for DEVFREQ_TRANSITION_NOTIFIER or
+ * CPUFREQ_TRANSITION_NOTIFIER list.
+ * @parent_cpu_data: the state min/max/current frequency of all online cpu's.
*
* The devfreq_passive_data have to set the devfreq instance of parent
* device with governors except for the passive governor. But, don't need to
@@ -314,9 +323,13 @@ struct devfreq_passive_data {
/* Optional callback to decide the next frequency of passvice device */
int (*get_target_freq)(struct devfreq *this, unsigned long *freq);
+ /* Should set the type of parent device */
+ enum devfreq_parent_dev_type parent_type;
+
/* For passive governor's internal use. Don't need to set them */
struct devfreq *this;
struct notifier_block nb;
+ struct devfreq_cpu_data *parent_cpu_data[NR_CPUS];
};
#endif
--
2.25.1
^ permalink raw reply related [relevance 4%]
* [PATCH v3 2/4] PM / devfreq: Add cpu based scaling support to passive governor
@ 2022-05-09 12:03 4% ` Chanwoo Choi
0 siblings, 0 replies; 200+ results
From: Chanwoo Choi @ 2022-05-09 12:03 UTC (permalink / raw)
To: linux-pm, linux-kernel
Cc: johnson.wang, mka, wenst, jia-wei.chang, andrew-sh.cheng, hsinyi,
saravanak, cw00.choi, myungjoo.ham, kyungmin.park,
Saravana Kannan, Sibi Sankar
From: Saravana Kannan <skannan@codeaurora.org>
Many CPU architectures have caches that can scale independent of the
CPUs. Frequency scaling of the caches is necessary to make sure that the
cache is not a performance bottleneck that leads to poor performance and
power. The same idea applies for RAM/DDR.
To achieve this, this patch adds support for cpu based scaling to the
passive governor. This is accomplished by taking the current frequency
of each CPU frequency domain and then adjust the frequency of the cache
(or any devfreq device) based on the frequency of the CPUs. It listens
to CPU frequency transition notifiers to keep itself up to date on the
current CPU frequency.
To decide the frequency of the device, the governor does one of the
following:
* Derives the optimal devfreq device opp from required-opps property of
the parent cpu opp_table.
* Scales the device frequency in proportion to the CPU frequency. So, if
the CPUs are running at their max frequency, the device runs at its
max frequency. If the CPUs are running at their min frequency, the
device runs at its min frequency. It is interpolated for frequencies
in between.
Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
[Sibi: Integrated cpu-freqmap governor into passive_governor]
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
[Chanwoo: Fix conflict with latest code and cleanup code]
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
drivers/devfreq/governor.h | 22 +++
drivers/devfreq/governor_passive.c | 297 +++++++++++++++++++++++++++--
include/linux/devfreq.h | 17 +-
3 files changed, 322 insertions(+), 14 deletions(-)
diff --git a/drivers/devfreq/governor.h b/drivers/devfreq/governor.h
index b0dbfee8bbf2..335c4a491254 100644
--- a/drivers/devfreq/governor.h
+++ b/drivers/devfreq/governor.h
@@ -47,6 +47,28 @@
#define DEVFREQ_GOV_ATTR_POLLING_INTERVAL BIT(0)
#define DEVFREQ_GOV_ATTR_TIMER BIT(1)
+/**
+ * struct devfreq_cpu_data - Hold the per-cpu data
+ * @dev: reference to cpu device.
+ * @first_cpu: the cpumask of the first cpu of a policy.
+ * @opp_table: reference to cpu opp table.
+ * @cur_freq: the current frequency of the cpu.
+ * @min_freq: the min frequency of the cpu.
+ * @max_freq: the max frequency of the cpu.
+ *
+ * This structure stores the required cpu_data of a cpu.
+ * This is auto-populated by the governor.
+ */
+struct devfreq_cpu_data {
+ struct device *dev;
+ unsigned int first_cpu;
+
+ struct opp_table *opp_table;
+ unsigned int cur_freq;
+ unsigned int min_freq;
+ unsigned int max_freq;
+};
+
/**
* struct devfreq_governor - Devfreq policy governor
* @node: list node - contains registered devfreq governors
diff --git a/drivers/devfreq/governor_passive.c b/drivers/devfreq/governor_passive.c
index fc09324a03e0..3fba05beaf24 100644
--- a/drivers/devfreq/governor_passive.c
+++ b/drivers/devfreq/governor_passive.c
@@ -8,11 +8,84 @@
*/
#include <linux/module.h>
+#include <linux/cpu.h>
+#include <linux/cpufreq.h>
+#include <linux/cpumask.h>
+#include <linux/slab.h>
#include <linux/device.h>
#include <linux/devfreq.h>
#include "governor.h"
-static int devfreq_passive_get_target_freq(struct devfreq *devfreq,
+#define HZ_PER_KHZ 1000
+
+static unsigned long get_target_freq_by_required_opp(struct device *p_dev,
+ struct opp_table *p_opp_table,
+ struct opp_table *opp_table,
+ unsigned long freq)
+{
+ struct dev_pm_opp *opp = NULL, *p_opp = NULL;
+
+ if (!p_dev || !p_opp_table || !opp_table || !freq)
+ return 0;
+
+ p_opp = devfreq_recommended_opp(p_dev, &freq, 0);
+ if (IS_ERR(p_opp))
+ return 0;
+
+ opp = dev_pm_opp_xlate_required_opp(p_opp_table, opp_table, p_opp);
+ dev_pm_opp_put(p_opp);
+
+ if (IS_ERR(opp))
+ return 0;
+
+ freq = dev_pm_opp_get_freq(opp);
+ dev_pm_opp_put(opp);
+
+ return freq;
+}
+
+static int get_target_freq_with_cpufreq(struct devfreq *devfreq,
+ unsigned long *target_freq)
+{
+ struct devfreq_passive_data *p_data =
+ (struct devfreq_passive_data *)devfreq->data;
+ struct devfreq_cpu_data *parent_cpu_data;
+ unsigned long cpu, cpu_cur, cpu_min, cpu_max, cpu_percent;
+ unsigned long dev_min, dev_max;
+ unsigned long freq = 0;
+
+ for_each_online_cpu(cpu) {
+ parent_cpu_data = p_data->parent_cpu_data[cpu];
+ if (!parent_cpu_data || parent_cpu_data->first_cpu != cpu)
+ continue;
+
+ /* Get target freq via required opps */
+ cpu_cur = parent_cpu_data->cur_freq * HZ_PER_KHZ;
+ freq = get_target_freq_by_required_opp(parent_cpu_data->dev,
+ parent_cpu_data->opp_table,
+ devfreq->opp_table, cpu_cur);
+ if (freq) {
+ *target_freq = max(freq, *target_freq);
+ continue;
+ }
+
+ /* Use interpolation if required opps is not available */
+ devfreq_get_freq_range(devfreq, &dev_min, &dev_max);
+
+ cpu_min = parent_cpu_data->min_freq;
+ cpu_max = parent_cpu_data->max_freq;
+ cpu_cur = parent_cpu_data->cur_freq;
+
+ cpu_percent = ((cpu_cur - cpu_min) * 100) / (cpu_max - cpu_min);
+ freq = dev_min + mult_frac(dev_max - dev_min, cpu_percent, 100);
+
+ *target_freq = max(freq, *target_freq);
+ }
+
+ return 0;
+}
+
+static int get_target_freq_with_devfreq(struct devfreq *devfreq,
unsigned long *freq)
{
struct devfreq_passive_data *p_data
@@ -99,6 +172,184 @@ static int devfreq_passive_get_target_freq(struct devfreq *devfreq,
return 0;
}
+static int devfreq_passive_get_target_freq(struct devfreq *devfreq,
+ unsigned long *freq)
+{
+ struct devfreq_passive_data *p_data =
+ (struct devfreq_passive_data *)devfreq->data;
+ int ret;
+
+ if (!p_data)
+ return -EINVAL;
+
+ /*
+ * If the devfreq device with passive governor has the specific method
+ * to determine the next frequency, should use the get_target_freq()
+ * of struct devfreq_passive_data.
+ */
+ if (p_data->get_target_freq)
+ return p_data->get_target_freq(devfreq, freq);
+
+ switch (p_data->parent_type) {
+ case DEVFREQ_PARENT_DEV:
+ ret = get_target_freq_with_devfreq(devfreq, freq);
+ break;
+ case CPUFREQ_PARENT_DEV:
+ ret = get_target_freq_with_cpufreq(devfreq, freq);
+ break;
+ default:
+ ret = -EINVAL;
+ dev_err(&devfreq->dev, "Invalid parent type\n");
+ break;
+ }
+
+ return ret;
+}
+
+static int cpufreq_passive_notifier_call(struct notifier_block *nb,
+ unsigned long event, void *ptr)
+{
+ struct devfreq_passive_data *p_data =
+ container_of(nb, struct devfreq_passive_data, nb);
+ struct devfreq *devfreq = (struct devfreq *)p_data->this;
+ struct devfreq_cpu_data *parent_cpu_data;
+ struct cpufreq_freqs *freqs = ptr;
+ unsigned int cur_freq;
+ int ret;
+
+ if (event != CPUFREQ_POSTCHANGE || !freqs ||
+ !p_data->parent_cpu_data[freqs->policy->cpu])
+ return 0;
+
+ parent_cpu_data = p_data->parent_cpu_data[freqs->policy->cpu];
+ if (parent_cpu_data->cur_freq == freqs->new)
+ return 0;
+
+ cur_freq = parent_cpu_data->cur_freq;
+ parent_cpu_data->cur_freq = freqs->new;
+
+ mutex_lock(&devfreq->lock);
+ ret = devfreq_update_target(devfreq, freqs->new);
+ mutex_unlock(&devfreq->lock);
+ if (ret) {
+ parent_cpu_data->cur_freq = cur_freq;
+ dev_err(&devfreq->dev, "failed to update the frequency.\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int cpufreq_passive_unregister_notifier(struct devfreq *devfreq)
+{
+ struct devfreq_passive_data *p_data
+ = (struct devfreq_passive_data *)devfreq->data;
+ struct devfreq_cpu_data *parent_cpu_data;
+ int cpu, ret;
+
+ if (p_data->nb.notifier_call) {
+ ret = cpufreq_unregister_notifier(&p_data->nb,
+ CPUFREQ_TRANSITION_NOTIFIER);
+ if (ret < 0)
+ return ret;
+ }
+
+ for_each_possible_cpu(cpu) {
+ parent_cpu_data = p_data->parent_cpu_data[cpu];
+ if (!parent_cpu_data)
+ continue;
+
+ if (parent_cpu_data->opp_table)
+ dev_pm_opp_put_opp_table(parent_cpu_data->opp_table);
+ kfree(parent_cpu_data);
+ }
+
+ return 0;
+}
+
+static int cpufreq_passive_register_notifier(struct devfreq *devfreq)
+{
+ struct devfreq_passive_data *p_data
+ = (struct devfreq_passive_data *)devfreq->data;
+ struct device *dev = devfreq->dev.parent;
+ struct opp_table *opp_table = NULL;
+ struct devfreq_cpu_data *parent_cpu_data;
+ struct cpufreq_policy *policy;
+ struct device *cpu_dev;
+ unsigned int cpu;
+ int ret;
+
+ if (!p_data->this)
+ p_data->this = devfreq;
+
+ p_data->nb.notifier_call = cpufreq_passive_notifier_call;
+ ret = cpufreq_register_notifier(&p_data->nb, CPUFREQ_TRANSITION_NOTIFIER);
+ if (ret) {
+ dev_err(dev, "failed to register cpufreq notifier\n");
+ p_data->nb.notifier_call = NULL;
+ goto err;
+ }
+
+ for_each_possible_cpu(cpu) {
+ if (p_data->parent_cpu_data[cpu])
+ continue;
+
+ policy = cpufreq_cpu_get(cpu);
+ if (!policy) {
+ ret = -EPROBE_DEFER;
+ goto err;
+ }
+
+ parent_cpu_data = kzalloc(sizeof(*parent_cpu_data),
+ GFP_KERNEL);
+ if (!parent_cpu_data) {
+ ret = -ENOMEM;
+ goto err_put_policy;
+ }
+
+ cpu_dev = get_cpu_device(cpu);
+ if (!cpu_dev) {
+ dev_err(dev, "failed to get cpu device\n");
+ ret = -ENODEV;
+ goto err_free_cpu_data;
+ }
+
+ opp_table = dev_pm_opp_get_opp_table(cpu_dev);
+ if (IS_ERR(opp_table)) {
+ dev_err(dev, "failed to get opp_table of cpu%d\n", cpu);
+ ret = PTR_ERR(opp_table);
+ goto err_free_cpu_data;
+ }
+
+ parent_cpu_data->dev = cpu_dev;
+ parent_cpu_data->opp_table = opp_table;
+ parent_cpu_data->first_cpu = cpumask_first(policy->related_cpus);
+ parent_cpu_data->cur_freq = policy->cur;
+ parent_cpu_data->min_freq = policy->cpuinfo.min_freq;
+ parent_cpu_data->max_freq = policy->cpuinfo.max_freq;
+
+ p_data->parent_cpu_data[cpu] = parent_cpu_data;
+ cpufreq_cpu_put(policy);
+ }
+
+ mutex_lock(&devfreq->lock);
+ ret = devfreq_update_target(devfreq, 0L);
+ mutex_unlock(&devfreq->lock);
+ if (ret)
+ dev_err(dev, "failed to update the frequency\n");
+
+ return ret;
+
+err_free_cpu_data:
+ kfree(parent_cpu_data);
+err_put_policy:
+ cpufreq_cpu_put(policy);
+err:
+ WARN_ON(cpufreq_passive_unregister_notifier(devfreq));
+
+ return ret;
+}
+
static int devfreq_passive_notifier_call(struct notifier_block *nb,
unsigned long event, void *ptr)
{
@@ -131,30 +382,52 @@ static int devfreq_passive_notifier_call(struct notifier_block *nb,
return NOTIFY_DONE;
}
-static int devfreq_passive_event_handler(struct devfreq *devfreq,
- unsigned int event, void *data)
+static int devfreq_passive_unregister_notifier(struct devfreq *devfreq)
+{
+ struct devfreq_passive_data *p_data
+ = (struct devfreq_passive_data *)devfreq->data;
+ struct devfreq *parent = (struct devfreq *)p_data->parent;
+ struct notifier_block *nb = &p_data->nb;
+
+ return devfreq_unregister_notifier(parent, nb, DEVFREQ_TRANSITION_NOTIFIER);
+}
+
+static int devfreq_passive_register_notifier(struct devfreq *devfreq)
{
struct devfreq_passive_data *p_data
= (struct devfreq_passive_data *)devfreq->data;
struct devfreq *parent = (struct devfreq *)p_data->parent;
struct notifier_block *nb = &p_data->nb;
- int ret = 0;
if (!parent)
return -EPROBE_DEFER;
+ nb->notifier_call = devfreq_passive_notifier_call;
+ return devfreq_register_notifier(parent, nb, DEVFREQ_TRANSITION_NOTIFIER);
+}
+
+static int devfreq_passive_event_handler(struct devfreq *devfreq,
+ unsigned int event, void *data)
+{
+ struct devfreq_passive_data *p_data
+ = (struct devfreq_passive_data *)devfreq->data;
+ int ret = -EINVAL;
+
+ if (!p_data)
+ return -EINVAL;
+
switch (event) {
case DEVFREQ_GOV_START:
- if (!p_data->this)
- p_data->this = devfreq;
-
- nb->notifier_call = devfreq_passive_notifier_call;
- ret = devfreq_register_notifier(parent, nb,
- DEVFREQ_TRANSITION_NOTIFIER);
+ if (p_data->parent_type == DEVFREQ_PARENT_DEV)
+ ret = devfreq_passive_register_notifier(devfreq);
+ else if (p_data->parent_type == CPUFREQ_PARENT_DEV)
+ ret = cpufreq_passive_register_notifier(devfreq);
break;
case DEVFREQ_GOV_STOP:
- WARN_ON(devfreq_unregister_notifier(parent, nb,
- DEVFREQ_TRANSITION_NOTIFIER));
+ if (p_data->parent_type == DEVFREQ_PARENT_DEV)
+ WARN_ON(devfreq_passive_unregister_notifier(devfreq));
+ else if (p_data->parent_type == CPUFREQ_PARENT_DEV)
+ WARN_ON(cpufreq_passive_unregister_notifier(devfreq));
break;
default:
break;
diff --git a/include/linux/devfreq.h b/include/linux/devfreq.h
index 142474b4af96..ccebb5c84d62 100644
--- a/include/linux/devfreq.h
+++ b/include/linux/devfreq.h
@@ -38,6 +38,7 @@ enum devfreq_timer {
struct devfreq;
struct devfreq_governor;
+struct devfreq_cpu_data;
struct thermal_cooling_device;
/**
@@ -288,6 +289,11 @@ struct devfreq_simple_ondemand_data {
#endif
#if IS_ENABLED(CONFIG_DEVFREQ_GOV_PASSIVE)
+enum devfreq_parent_dev_type {
+ DEVFREQ_PARENT_DEV,
+ CPUFREQ_PARENT_DEV,
+};
+
/**
* struct devfreq_passive_data - ``void *data`` fed to struct devfreq
* and devfreq_add_device
@@ -299,8 +305,11 @@ struct devfreq_simple_ondemand_data {
* using governors except for passive governor.
* If the devfreq device has the specific method to decide
* the next frequency, should use this callback.
- * @this: the devfreq instance of own device.
- * @nb: the notifier block for DEVFREQ_TRANSITION_NOTIFIER list
+ + * @parent_type parent type of the device.
+ + * @this: the devfreq instance of own device.
+ + * @nb: the notifier block for DEVFREQ_TRANSITION_NOTIFIER or
+ * CPUFREQ_TRANSITION_NOTIFIER list.
+ + * @cpu_data: the state min/max/current frequency of all online cpu's
*
* The devfreq_passive_data have to set the devfreq instance of parent
* device with governors except for the passive governor. But, don't need to
@@ -314,9 +323,13 @@ struct devfreq_passive_data {
/* Optional callback to decide the next frequency of passvice device */
int (*get_target_freq)(struct devfreq *this, unsigned long *freq);
+ /* Should set the type of parent device */
+ enum devfreq_parent_dev_type parent_type;
+
/* For passive governor's internal use. Don't need to set them */
struct devfreq *this;
struct notifier_block nb;
+ struct devfreq_cpu_data *parent_cpu_data[NR_CPUS];
};
#endif
--
2.25.1
^ permalink raw reply related [relevance 4%]
* [PATCH v2 2/5] PM / devfreq: Add cpu based scaling support to passive governor
@ 2022-05-07 15:01 4% ` Chanwoo Choi
0 siblings, 0 replies; 200+ results
From: Chanwoo Choi @ 2022-05-07 15:01 UTC (permalink / raw)
To: linux-pm, linux-kernel
Cc: cw00.choi, myungjoo.ham, kyungmin.park, johnson.wang, mka,
jia-wei.chang, andrew-sh.cheng, hsinyi, sibis, saravanak,
Saravana Kannan
From: Saravana Kannan <skannan@codeaurora.org>
Many CPU architectures have caches that can scale independent of the
CPUs. Frequency scaling of the caches is necessary to make sure that the
cache is not a performance bottleneck that leads to poor performance and
power. The same idea applies for RAM/DDR.
To achieve this, this patch adds support for cpu based scaling to the
passive governor. This is accomplished by taking the current frequency
of each CPU frequency domain and then adjust the frequency of the cache
(or any devfreq device) based on the frequency of the CPUs. It listens
to CPU frequency transition notifiers to keep itself up to date on the
current CPU frequency.
To decide the frequency of the device, the governor does one of the
following:
* Derives the optimal devfreq device opp from required-opps property of
the parent cpu opp_table.
* Scales the device frequency in proportion to the CPU frequency. So, if
the CPUs are running at their max frequency, the device runs at its
max frequency. If the CPUs are running at their min frequency, the
device runs at its min frequency. It is interpolated for frequencies
in between.
Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
[Sibi: Integrated cpu-freqmap governor into passive_governor]
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
[Chanwoo: Fix conflict with latest code and cleanup code]
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
drivers/devfreq/governor.h | 22 +++
drivers/devfreq/governor_passive.c | 292 ++++++++++++++++++++++++++++-
include/linux/devfreq.h | 17 +-
3 files changed, 320 insertions(+), 11 deletions(-)
diff --git a/drivers/devfreq/governor.h b/drivers/devfreq/governor.h
index b0dbfee8bbf2..335c4a491254 100644
--- a/drivers/devfreq/governor.h
+++ b/drivers/devfreq/governor.h
@@ -47,6 +47,28 @@
#define DEVFREQ_GOV_ATTR_POLLING_INTERVAL BIT(0)
#define DEVFREQ_GOV_ATTR_TIMER BIT(1)
+/**
+ * struct devfreq_cpu_data - Hold the per-cpu data
+ * @dev: reference to cpu device.
+ * @first_cpu: the cpumask of the first cpu of a policy.
+ * @opp_table: reference to cpu opp table.
+ * @cur_freq: the current frequency of the cpu.
+ * @min_freq: the min frequency of the cpu.
+ * @max_freq: the max frequency of the cpu.
+ *
+ * This structure stores the required cpu_data of a cpu.
+ * This is auto-populated by the governor.
+ */
+struct devfreq_cpu_data {
+ struct device *dev;
+ unsigned int first_cpu;
+
+ struct opp_table *opp_table;
+ unsigned int cur_freq;
+ unsigned int min_freq;
+ unsigned int max_freq;
+};
+
/**
* struct devfreq_governor - Devfreq policy governor
* @node: list node - contains registered devfreq governors
diff --git a/drivers/devfreq/governor_passive.c b/drivers/devfreq/governor_passive.c
index fc09324a03e0..bfbe5604538d 100644
--- a/drivers/devfreq/governor_passive.c
+++ b/drivers/devfreq/governor_passive.c
@@ -8,11 +8,84 @@
*/
#include <linux/module.h>
+#include <linux/cpu.h>
+#include <linux/cpufreq.h>
+#include <linux/cpumask.h>
+#include <linux/slab.h>
#include <linux/device.h>
#include <linux/devfreq.h>
#include "governor.h"
-static int devfreq_passive_get_target_freq(struct devfreq *devfreq,
+#define HZ_PER_KHZ 1000
+
+static unsigned long get_target_freq_by_required_opp(struct device *p_dev,
+ struct opp_table *p_opp_table,
+ struct opp_table *opp_table,
+ unsigned long freq)
+{
+ struct dev_pm_opp *opp = NULL, *p_opp = NULL;
+
+ if (!p_dev || !p_opp_table || !opp_table || !freq)
+ return 0;
+
+ p_opp = devfreq_recommended_opp(p_dev, &freq, 0);
+ if (IS_ERR(p_opp))
+ return 0;
+
+ opp = dev_pm_opp_xlate_required_opp(p_opp_table, opp_table, p_opp);
+ dev_pm_opp_put(p_opp);
+
+ if (IS_ERR(opp))
+ return 0;
+
+ freq = dev_pm_opp_get_freq(opp);
+ dev_pm_opp_put(opp);
+
+ return freq;
+}
+
+static int get_target_freq_with_cpufreq(struct devfreq *devfreq,
+ unsigned long *target_freq)
+{
+ struct devfreq_passive_data *p_data =
+ (struct devfreq_passive_data *)devfreq->data;
+ struct devfreq_cpu_data *parent_cpu_data;
+ unsigned long cpu, cpu_cur, cpu_min, cpu_max, cpu_percent;
+ unsigned long dev_min, dev_max;
+ unsigned long freq = 0;
+
+ for_each_online_cpu(cpu) {
+ parent_cpu_data = p_data->parent_cpu_data[cpu];
+ if (!parent_cpu_data || parent_cpu_data->first_cpu != cpu)
+ continue;
+
+ /* Get target freq via required opps */
+ cpu_cur = parent_cpu_data->cur_freq * HZ_PER_KHZ;
+ freq = get_target_freq_by_required_opp(parent_cpu_data->dev,
+ parent_cpu_data->opp_table,
+ devfreq->opp_table, cpu_cur);
+ if (freq) {
+ *target_freq = max(freq, *target_freq);
+ continue;
+ }
+
+ /* Use interpolation if required opps is not available */
+ devfreq_get_freq_range(devfreq, &dev_min, &dev_max);
+
+ cpu_min = parent_cpu_data->min_freq;
+ cpu_max = parent_cpu_data->max_freq;
+ cpu_cur = parent_cpu_data->cur_freq;
+
+ cpu_percent = ((cpu_cur - cpu_min) * 100) / (cpu_max - cpu_min);
+ freq = dev_min + mult_frac(dev_max - dev_min, cpu_percent, 100);
+
+ *target_freq = max(freq, *target_freq);
+ }
+
+ return 0;
+}
+
+static int get_target_freq_with_devfreq(struct devfreq *devfreq,
unsigned long *freq)
{
struct devfreq_passive_data *p_data
@@ -99,6 +172,181 @@ static int devfreq_passive_get_target_freq(struct devfreq *devfreq,
return 0;
}
+static int devfreq_passive_get_target_freq(struct devfreq *devfreq,
+ unsigned long *freq)
+{
+ struct devfreq_passive_data *p_data =
+ (struct devfreq_passive_data *)devfreq->data;
+ int ret;
+
+ if (!p_data)
+ return -EINVAL;
+
+ /*
+ * If the devfreq device with passive governor has the specific method
+ * to determine the next frequency, should use the get_target_freq()
+ * of struct devfreq_passive_data.
+ */
+ if (p_data->get_target_freq)
+ return p_data->get_target_freq(devfreq, freq);
+
+ switch (p_data->parent_type) {
+ case DEVFREQ_PARENT_DEV:
+ ret = get_target_freq_with_devfreq(devfreq, freq);
+ break;
+ case CPUFREQ_PARENT_DEV:
+ ret = get_target_freq_with_cpufreq(devfreq, freq);
+ break;
+ default:
+ ret = -EINVAL;
+ dev_err(&devfreq->dev, "Invalid parent type\n");
+ break;
+ }
+
+ return ret;
+}
+
+static int cpufreq_passive_notifier_call(struct notifier_block *nb,
+ unsigned long event, void *ptr)
+{
+ struct devfreq_passive_data *p_data =
+ container_of(nb, struct devfreq_passive_data, nb);
+ struct devfreq *devfreq = (struct devfreq *)p_data->this;
+ struct devfreq_cpu_data *parent_cpu_data;
+ struct cpufreq_freqs *freqs = ptr;
+ unsigned int cur_freq;
+ int ret;
+
+ if (event != CPUFREQ_POSTCHANGE || !freqs ||
+ !p_data->parent_cpu_data[freqs->policy->cpu])
+ return 0;
+
+ parent_cpu_data = p_data->parent_cpu_data[freqs->policy->cpu];
+ if (parent_cpu_data->cur_freq == freqs->new)
+ return 0;
+
+ cur_freq = parent_cpu_data->cur_freq;
+ parent_cpu_data->cur_freq = freqs->new;
+
+ mutex_lock(&devfreq->lock);
+ ret = devfreq_update_target(devfreq, freqs->new);
+ mutex_unlock(&devfreq->lock);
+ if (ret) {
+ parent_cpu_data->cur_freq = cur_freq;
+ dev_err(&devfreq->dev, "failed to update the frequency.\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int cpufreq_passive_unregister_notifier(struct devfreq *devfreq)
+{
+ struct devfreq_passive_data *p_data
+ = (struct devfreq_passive_data *)devfreq->data;
+ struct devfreq_cpu_data *parent_cpu_data;
+ int cpu, ret;
+
+ if (p_data->nb.notifier_call) {
+ ret = cpufreq_unregister_notifier(&p_data->nb,
+ CPUFREQ_TRANSITION_NOTIFIER);
+ if (ret < 0)
+ return ret;
+ }
+
+ for_each_possible_cpu(cpu) {
+ parent_cpu_data = p_data->parent_cpu_data[cpu];
+ if (!parent_cpu_data)
+ continue;
+
+ if (parent_cpu_data->opp_table)
+ dev_pm_opp_put_opp_table(parent_cpu_data->opp_table);
+ kfree(parent_cpu_data);
+ }
+
+ return 0;
+}
+
+static int cpufreq_passive_register_notifier(struct devfreq *devfreq)
+{
+ struct devfreq_passive_data *p_data
+ = (struct devfreq_passive_data *)devfreq->data;
+ struct device *dev = devfreq->dev.parent;
+ struct opp_table *opp_table = NULL;
+ struct devfreq_cpu_data *parent_cpu_data;
+ struct cpufreq_policy *policy;
+ struct device *cpu_dev;
+ unsigned int cpu;
+ int ret;
+
+ p_data->nb.notifier_call = cpufreq_passive_notifier_call;
+ ret = cpufreq_register_notifier(&p_data->nb, CPUFREQ_TRANSITION_NOTIFIER);
+ if (ret) {
+ dev_err(dev, "failed to register cpufreq notifier\n");
+ p_data->nb.notifier_call = NULL;
+ goto err;
+ }
+
+ for_each_possible_cpu(cpu) {
+ if (p_data->parent_cpu_data[cpu])
+ continue;
+
+ policy = cpufreq_cpu_get(cpu);
+ if (!policy) {
+ ret = -EPROBE_DEFER;
+ goto err;
+ }
+
+ parent_cpu_data = kzalloc(sizeof(*parent_cpu_data),
+ GFP_KERNEL);
+ if (!parent_cpu_data) {
+ ret = -ENOMEM;
+ goto err_put_policy;
+ }
+
+ cpu_dev = get_cpu_device(cpu);
+ if (!cpu_dev) {
+ dev_err(dev, "failed to get cpu device\n");
+ ret = -ENODEV;
+ goto err_free_cpu_data;
+ }
+
+ opp_table = dev_pm_opp_get_opp_table(cpu_dev);
+ if (IS_ERR(opp_table)) {
+ dev_err(dev, "failed to get opp_table of cpu%d\n", cpu);
+ ret = PTR_ERR(opp_table);
+ goto err_free_cpu_data;
+ }
+
+ parent_cpu_data->dev = cpu_dev;
+ parent_cpu_data->opp_table = opp_table;
+ parent_cpu_data->first_cpu = cpumask_first(policy->related_cpus);
+ parent_cpu_data->cur_freq = policy->cur;
+ parent_cpu_data->min_freq = policy->cpuinfo.min_freq;
+ parent_cpu_data->max_freq = policy->cpuinfo.max_freq;
+
+ p_data->parent_cpu_data[cpu] = parent_cpu_data;
+ cpufreq_cpu_put(policy);
+ }
+
+ mutex_lock(&devfreq->lock);
+ ret = devfreq_update_target(devfreq, 0L);
+ mutex_unlock(&devfreq->lock);
+ if (ret)
+ dev_err(dev, "failed to update the frequency\n");
+
+ return ret;
+
+err_free_cpu_data:
+ kfree(parent_cpu_data);
+err_put_policy:
+ cpufreq_cpu_put(policy);
+err:
+ WARN_ON(cpufreq_passive_unregister_notifier(devfreq));
+
+ return ret;
+}
+
static int devfreq_passive_notifier_call(struct notifier_block *nb,
unsigned long event, void *ptr)
{
@@ -131,16 +379,39 @@ static int devfreq_passive_notifier_call(struct notifier_block *nb,
return NOTIFY_DONE;
}
+static int devfreq_passive_unregister_notifier(struct devfreq *devfreq)
+{
+ struct devfreq_passive_data *p_data
+ = (struct devfreq_passive_data *)devfreq->data;
+ struct devfreq *parent = (struct devfreq *)p_data->parent;
+ struct notifier_block *nb = &p_data->nb;
+
+ return devfreq_unregister_notifier(parent, nb, DEVFREQ_TRANSITION_NOTIFIER);
+}
+
+static int devfreq_passive_register_notifier(struct devfreq *devfreq)
+{
+ struct devfreq_passive_data *p_data
+ = (struct devfreq_passive_data *)devfreq->data;
+ struct devfreq *parent = (struct devfreq *)p_data->parent;
+ struct notifier_block *nb = &p_data->nb;
+
+ nb->notifier_call = devfreq_passive_notifier_call;
+ return devfreq_register_notifier(parent, nb, DEVFREQ_TRANSITION_NOTIFIER);
+}
+
static int devfreq_passive_event_handler(struct devfreq *devfreq,
unsigned int event, void *data)
{
struct devfreq_passive_data *p_data
= (struct devfreq_passive_data *)devfreq->data;
struct devfreq *parent = (struct devfreq *)p_data->parent;
- struct notifier_block *nb = &p_data->nb;
- int ret = 0;
+ int ret = -EINVAL;
+
+ if (!p_data)
+ return -EINVAL;
- if (!parent)
+ if (p_data->parent_type == DEVFREQ_PARENT_DEV && !parent)
return -EPROBE_DEFER;
switch (event) {
@@ -148,13 +419,16 @@ static int devfreq_passive_event_handler(struct devfreq *devfreq,
if (!p_data->this)
p_data->this = devfreq;
- nb->notifier_call = devfreq_passive_notifier_call;
- ret = devfreq_register_notifier(parent, nb,
- DEVFREQ_TRANSITION_NOTIFIER);
+ if (p_data->parent_type == DEVFREQ_PARENT_DEV)
+ ret = devfreq_passive_register_notifier(devfreq);
+ else if (p_data->parent_type == CPUFREQ_PARENT_DEV)
+ ret = cpufreq_passive_register_notifier(devfreq);
break;
case DEVFREQ_GOV_STOP:
- WARN_ON(devfreq_unregister_notifier(parent, nb,
- DEVFREQ_TRANSITION_NOTIFIER));
+ if (p_data->parent_type == DEVFREQ_PARENT_DEV)
+ WARN_ON(devfreq_passive_unregister_notifier(devfreq));
+ else if (p_data->parent_type == CPUFREQ_PARENT_DEV)
+ WARN_ON(cpufreq_passive_unregister_notifier(devfreq));
break;
default:
break;
diff --git a/include/linux/devfreq.h b/include/linux/devfreq.h
index 142474b4af96..ccebb5c84d62 100644
--- a/include/linux/devfreq.h
+++ b/include/linux/devfreq.h
@@ -38,6 +38,7 @@ enum devfreq_timer {
struct devfreq;
struct devfreq_governor;
+struct devfreq_cpu_data;
struct thermal_cooling_device;
/**
@@ -288,6 +289,11 @@ struct devfreq_simple_ondemand_data {
#endif
#if IS_ENABLED(CONFIG_DEVFREQ_GOV_PASSIVE)
+enum devfreq_parent_dev_type {
+ DEVFREQ_PARENT_DEV,
+ CPUFREQ_PARENT_DEV,
+};
+
/**
* struct devfreq_passive_data - ``void *data`` fed to struct devfreq
* and devfreq_add_device
@@ -299,8 +305,11 @@ struct devfreq_simple_ondemand_data {
* using governors except for passive governor.
* If the devfreq device has the specific method to decide
* the next frequency, should use this callback.
- * @this: the devfreq instance of own device.
- * @nb: the notifier block for DEVFREQ_TRANSITION_NOTIFIER list
+ + * @parent_type parent type of the device.
+ + * @this: the devfreq instance of own device.
+ + * @nb: the notifier block for DEVFREQ_TRANSITION_NOTIFIER or
+ * CPUFREQ_TRANSITION_NOTIFIER list.
+ + * @cpu_data: the state min/max/current frequency of all online cpu's
*
* The devfreq_passive_data have to set the devfreq instance of parent
* device with governors except for the passive governor. But, don't need to
@@ -314,9 +323,13 @@ struct devfreq_passive_data {
/* Optional callback to decide the next frequency of passvice device */
int (*get_target_freq)(struct devfreq *this, unsigned long *freq);
+ /* Should set the type of parent device */
+ enum devfreq_parent_dev_type parent_type;
+
/* For passive governor's internal use. Don't need to set them */
struct devfreq *this;
struct notifier_block nb;
+ struct devfreq_cpu_data *parent_cpu_data[NR_CPUS];
};
#endif
--
2.25.1
^ permalink raw reply related [relevance 4%]
* [PATCH 5.10 051/599] remoteproc: Fix count check in rproc_coredump_write()
@ 2022-04-05 7:25 6% ` Greg Kroah-Hartman
0 siblings, 0 replies; 200+ results
From: Greg Kroah-Hartman @ 2022-04-05 7:25 UTC (permalink / raw)
To: linux-kernel
Cc: Greg Kroah-Hartman, stable, Alistair Delva, Rishabh Bhatnagar,
Ohad Ben-Cohen, Bjorn Andersson, Mathieu Poirier, Sibi Sankar,
linux-remoteproc, kernel-team
From: Alistair Delva <adelva@google.com>
commit f89672cc3681952f2d06314981a6b45f8b0045d1 upstream.
Check count for 0, to avoid a potential underflow. Make the check the
same as the one in rproc_recovery_write().
Fixes: 3afdc59e4390 ("remoteproc: Add coredump debugfs entry")
Signed-off-by: Alistair Delva <adelva@google.com>
Cc: Rishabh Bhatnagar <rishabhb@codeaurora.org>
Cc: stable@vger.kernel.org
Cc: Ohad Ben-Cohen <ohad@wizery.com>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Sibi Sankar <sibis@codeaurora.org>
Cc: linux-remoteproc@vger.kernel.org
Cc: kernel-team@android.com
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220119232139.1125908-1-adelva@google.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
drivers/remoteproc/remoteproc_debugfs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/remoteproc/remoteproc_debugfs.c
+++ b/drivers/remoteproc/remoteproc_debugfs.c
@@ -76,7 +76,7 @@ static ssize_t rproc_coredump_write(stru
int ret, err = 0;
char buf[20];
- if (count > sizeof(buf))
+ if (count < 1 || count > sizeof(buf))
return -EINVAL;
ret = copy_from_user(buf, user_buf, count);
^ permalink raw reply [relevance 6%]
* [PATCH 5.15 070/913] remoteproc: Fix count check in rproc_coredump_write()
@ 2022-04-05 7:18 6% ` Greg Kroah-Hartman
0 siblings, 0 replies; 200+ results
From: Greg Kroah-Hartman @ 2022-04-05 7:18 UTC (permalink / raw)
To: linux-kernel
Cc: Greg Kroah-Hartman, stable, Alistair Delva, Rishabh Bhatnagar,
Ohad Ben-Cohen, Bjorn Andersson, Mathieu Poirier, Sibi Sankar,
linux-remoteproc, kernel-team
From: Alistair Delva <adelva@google.com>
commit f89672cc3681952f2d06314981a6b45f8b0045d1 upstream.
Check count for 0, to avoid a potential underflow. Make the check the
same as the one in rproc_recovery_write().
Fixes: 3afdc59e4390 ("remoteproc: Add coredump debugfs entry")
Signed-off-by: Alistair Delva <adelva@google.com>
Cc: Rishabh Bhatnagar <rishabhb@codeaurora.org>
Cc: stable@vger.kernel.org
Cc: Ohad Ben-Cohen <ohad@wizery.com>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Sibi Sankar <sibis@codeaurora.org>
Cc: linux-remoteproc@vger.kernel.org
Cc: kernel-team@android.com
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220119232139.1125908-1-adelva@google.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
drivers/remoteproc/remoteproc_debugfs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/remoteproc/remoteproc_debugfs.c
+++ b/drivers/remoteproc/remoteproc_debugfs.c
@@ -76,7 +76,7 @@ static ssize_t rproc_coredump_write(stru
int ret, err = 0;
char buf[20];
- if (count > sizeof(buf))
+ if (count < 1 || count > sizeof(buf))
return -EINVAL;
ret = copy_from_user(buf, user_buf, count);
^ permalink raw reply [relevance 6%]
* [PATCH 5.16 0073/1017] remoteproc: Fix count check in rproc_coredump_write()
@ 2022-04-05 7:16 6% ` Greg Kroah-Hartman
0 siblings, 0 replies; 200+ results
From: Greg Kroah-Hartman @ 2022-04-05 7:16 UTC (permalink / raw)
To: linux-kernel
Cc: Greg Kroah-Hartman, stable, Alistair Delva, Rishabh Bhatnagar,
Ohad Ben-Cohen, Bjorn Andersson, Mathieu Poirier, Sibi Sankar,
linux-remoteproc, kernel-team
From: Alistair Delva <adelva@google.com>
commit f89672cc3681952f2d06314981a6b45f8b0045d1 upstream.
Check count for 0, to avoid a potential underflow. Make the check the
same as the one in rproc_recovery_write().
Fixes: 3afdc59e4390 ("remoteproc: Add coredump debugfs entry")
Signed-off-by: Alistair Delva <adelva@google.com>
Cc: Rishabh Bhatnagar <rishabhb@codeaurora.org>
Cc: stable@vger.kernel.org
Cc: Ohad Ben-Cohen <ohad@wizery.com>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Sibi Sankar <sibis@codeaurora.org>
Cc: linux-remoteproc@vger.kernel.org
Cc: kernel-team@android.com
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220119232139.1125908-1-adelva@google.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
drivers/remoteproc/remoteproc_debugfs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/remoteproc/remoteproc_debugfs.c
+++ b/drivers/remoteproc/remoteproc_debugfs.c
@@ -76,7 +76,7 @@ static ssize_t rproc_coredump_write(stru
int ret, err = 0;
char buf[20];
- if (count > sizeof(buf))
+ if (count < 1 || count > sizeof(buf))
return -EINVAL;
ret = copy_from_user(buf, user_buf, count);
^ permalink raw reply [relevance 6%]
* [PATCH 5.17 0062/1126] remoteproc: Fix count check in rproc_coredump_write()
@ 2022-04-05 7:13 6% ` Greg Kroah-Hartman
0 siblings, 0 replies; 200+ results
From: Greg Kroah-Hartman @ 2022-04-05 7:13 UTC (permalink / raw)
To: linux-kernel
Cc: Greg Kroah-Hartman, stable, Alistair Delva, Rishabh Bhatnagar,
Ohad Ben-Cohen, Bjorn Andersson, Mathieu Poirier, Sibi Sankar,
linux-remoteproc, kernel-team
From: Alistair Delva <adelva@google.com>
commit f89672cc3681952f2d06314981a6b45f8b0045d1 upstream.
Check count for 0, to avoid a potential underflow. Make the check the
same as the one in rproc_recovery_write().
Fixes: 3afdc59e4390 ("remoteproc: Add coredump debugfs entry")
Signed-off-by: Alistair Delva <adelva@google.com>
Cc: Rishabh Bhatnagar <rishabhb@codeaurora.org>
Cc: stable@vger.kernel.org
Cc: Ohad Ben-Cohen <ohad@wizery.com>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Sibi Sankar <sibis@codeaurora.org>
Cc: linux-remoteproc@vger.kernel.org
Cc: kernel-team@android.com
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220119232139.1125908-1-adelva@google.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
drivers/remoteproc/remoteproc_debugfs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/remoteproc/remoteproc_debugfs.c
+++ b/drivers/remoteproc/remoteproc_debugfs.c
@@ -76,7 +76,7 @@ static ssize_t rproc_coredump_write(stru
int ret, err = 0;
char buf[20];
- if (count > sizeof(buf))
+ if (count < 1 || count > sizeof(buf))
return -EINVAL;
ret = copy_from_user(buf, user_buf, count);
^ permalink raw reply [relevance 6%]
* [PATCH 5.16 127/200] remoteproc: qcom: q6v5: fix service routines build errors
@ 2022-01-31 10:56 5% ` Greg Kroah-Hartman
0 siblings, 0 replies; 200+ results
From: Greg Kroah-Hartman @ 2022-01-31 10:56 UTC (permalink / raw)
To: linux-kernel
Cc: Greg Kroah-Hartman, stable, Randy Dunlap, kernel test robot,
Bjorn Andersson, Mathieu Poirier, linux-remoteproc, Sibi Sankar,
Stephen Boyd, Sasha Levin
From: Randy Dunlap <rdunlap@infradead.org>
[ Upstream commit eee412e968f7b950564880bc6a7a9f00f49034da ]
When CONFIG_QCOM_AOSS_QMP=m and CONFIG_QCOM_Q6V5_MSS=y, the builtin
driver cannot call into the loadable module's low-level service
functions. Trying to build with that config combo causes linker errors.
There are two problems here. First, drivers/remoteproc/qcom_q6v5.c
should #include <linux/soc/qcom/qcom_aoss.h> for the definitions of
the service functions, depending on whether CONFIG_QCOM_AOSS_QMP is
set/enabled or not. Second, the qcom remoteproc drivers should depend
on QCOM_AOSS_QMP iff it is enabled (=y or =m) so that the qcom
remoteproc drivers can be built properly.
This prevents these build errors:
aarch64-linux-ld: drivers/remoteproc/qcom_q6v5.o: in function `q6v5_load_state_toggle':
qcom_q6v5.c:(.text+0xc4): undefined reference to `qmp_send'
aarch64-linux-ld: drivers/remoteproc/qcom_q6v5.o: in function `qcom_q6v5_deinit':
(.text+0x2e4): undefined reference to `qmp_put'
aarch64-linux-ld: drivers/remoteproc/qcom_q6v5.o: in function `qcom_q6v5_init':
(.text+0x778): undefined reference to `qmp_get'
aarch64-linux-ld: (.text+0x7d8): undefined reference to `qmp_put'
Fixes: c1fe10d238c0 ("remoteproc: qcom: q6v5: Use qmp_send to update co-processor load state")
Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Reported-by: kernel test robot <lkp@intel.com>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: linux-remoteproc@vger.kernel.org
Cc: Sibi Sankar <sibis@codeaurora.org>
Cc: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220115011338.2973-1-rdunlap@infradead.org
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
drivers/remoteproc/Kconfig | 4 ++++
drivers/remoteproc/qcom_q6v5.c | 1 +
2 files changed, 5 insertions(+)
diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig
index f2e961f998ca2..341156e2a29b9 100644
--- a/drivers/remoteproc/Kconfig
+++ b/drivers/remoteproc/Kconfig
@@ -180,6 +180,7 @@ config QCOM_Q6V5_ADSP
depends on RPMSG_QCOM_GLINK_SMEM || RPMSG_QCOM_GLINK_SMEM=n
depends on QCOM_SYSMON || QCOM_SYSMON=n
depends on RPMSG_QCOM_GLINK || RPMSG_QCOM_GLINK=n
+ depends on QCOM_AOSS_QMP || QCOM_AOSS_QMP=n
select MFD_SYSCON
select QCOM_PIL_INFO
select QCOM_MDT_LOADER
@@ -199,6 +200,7 @@ config QCOM_Q6V5_MSS
depends on RPMSG_QCOM_GLINK_SMEM || RPMSG_QCOM_GLINK_SMEM=n
depends on QCOM_SYSMON || QCOM_SYSMON=n
depends on RPMSG_QCOM_GLINK || RPMSG_QCOM_GLINK=n
+ depends on QCOM_AOSS_QMP || QCOM_AOSS_QMP=n
select MFD_SYSCON
select QCOM_MDT_LOADER
select QCOM_PIL_INFO
@@ -218,6 +220,7 @@ config QCOM_Q6V5_PAS
depends on RPMSG_QCOM_GLINK_SMEM || RPMSG_QCOM_GLINK_SMEM=n
depends on QCOM_SYSMON || QCOM_SYSMON=n
depends on RPMSG_QCOM_GLINK || RPMSG_QCOM_GLINK=n
+ depends on QCOM_AOSS_QMP || QCOM_AOSS_QMP=n
select MFD_SYSCON
select QCOM_PIL_INFO
select QCOM_MDT_LOADER
@@ -239,6 +242,7 @@ config QCOM_Q6V5_WCSS
depends on RPMSG_QCOM_GLINK_SMEM || RPMSG_QCOM_GLINK_SMEM=n
depends on QCOM_SYSMON || QCOM_SYSMON=n
depends on RPMSG_QCOM_GLINK || RPMSG_QCOM_GLINK=n
+ depends on QCOM_AOSS_QMP || QCOM_AOSS_QMP=n
select MFD_SYSCON
select QCOM_MDT_LOADER
select QCOM_PIL_INFO
diff --git a/drivers/remoteproc/qcom_q6v5.c b/drivers/remoteproc/qcom_q6v5.c
index eada7e34f3af5..442a388f81028 100644
--- a/drivers/remoteproc/qcom_q6v5.c
+++ b/drivers/remoteproc/qcom_q6v5.c
@@ -10,6 +10,7 @@
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/module.h>
+#include <linux/soc/qcom/qcom_aoss.h>
#include <linux/soc/qcom/smem.h>
#include <linux/soc/qcom/smem_state.h>
#include <linux/remoteproc.h>
--
2.34.1
^ permalink raw reply related [relevance 5%]
* Re: [PATCH 5.15 00/28] 5.15.16-rc1 review
2022-01-18 16:05 4% [PATCH 5.15 00/28] 5.15.16-rc1 review Greg Kroah-Hartman
2022-01-18 16:05 9% ` [PATCH 5.15 11/28] remoteproc: qcom: pas: Add missing power-domain "mxc" for CDSP Greg Kroah-Hartman
@ 2022-01-22 0:29 0% ` Allen
1 sibling, 0 replies; 200+ results
From: Allen @ 2022-01-22 0:29 UTC (permalink / raw)
To: Greg Kroah-Hartman
Cc: Linux Kernel Mailing List, Linus Torvalds, Andrew Morton, linux,
shuah, patches, lkft-triage, pavel, jonathanh, Florian Fainelli,
stable
> This is the start of the stable review cycle for the 5.15.16 release.
> There are 28 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
>
> Responses should be made by Thu, 20 Jan 2022 16:04:42 +0000.
> Anything received after that time might be too late.
>
> The whole patch series can be found in one patch at:
> https://www.kernel.org/pub/linux/kernel/v5.x/stable-review/patch-5.15.16-rc1.gz
> or in the git tree and branch at:
> git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git linux-5.15.y
> and the diffstat can be found below.
>
> thanks,
>
> greg k-h
>
Build and boot tested. No dmesg regressions.
Tested-by: Allen Pais <apais@linux.microsoft.com>
Thanks,
- Allen
> -------------
> Pseudo-Shortlog of commits:
>
> Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Linux 5.15.16-rc1
>
> Arnd Bergmann <arnd@arndb.de>
> mtd: fixup CFI on ixp4xx
>
> Takashi Iwai <tiwai@suse.de>
> ALSA: hda/realtek: Re-order quirk entries for Lenovo
>
> Baole Fang <fbl718@163.com>
> ALSA: hda/realtek: Add quirk for Legion Y9000X 2020
>
> Sameer Pujar <spujar@nvidia.com>
> ALSA: hda/tegra: Fix Tegra194 HDA reset failure
>
> Bart Kroon <bart@tarmack.eu>
> ALSA: hda: ALC287: Add Lenovo IdeaPad Slim 9i 14ITL5 speaker quirk
>
> Christian Lachner <gladiac@gmail.com>
> ALSA: hda/realtek - Fix silent output on Gigabyte X570 Aorus Master after reboot from Windows
>
> Kai-Heng Feng <kai.heng.feng@canonical.com>
> ALSA: hda/realtek: Use ALC285_FIXUP_HP_GPIO_LED on another HP laptop
>
> Arie Geiger <arsgeiger@gmail.com>
> ALSA: hda/realtek: Add speaker fixup for some Yoga 15ITL5 devices
>
> Wei Wang <wei.w.wang@intel.com>
> KVM: x86: remove PMU FIXED_CTR3 from msrs_to_save_all
>
> Dario Petrillo <dario.pk1@gmail.com>
> perf annotate: Avoid TUI crash when navigating in the annotation of recursive functions
>
> Johan Hovold <johan@kernel.org>
> firmware: qemu_fw_cfg: fix kobject leak in probe error path
>
> Johan Hovold <johan@kernel.org>
> firmware: qemu_fw_cfg: fix NULL-pointer deref on duplicate entries
>
> Johan Hovold <johan@kernel.org>
> firmware: qemu_fw_cfg: fix sysfs information leak
>
> Larry Finger <Larry.Finger@lwfinger.net>
> rtlwifi: rtl8192cu: Fix WARNING when calling local_irq_restore() with interrupts enabled
>
> Johan Hovold <johan@kernel.org>
> media: uvcvideo: fix division by zero at stream start
>
> Javier Martinez Canillas <javierm@redhat.com>
> video: vga16fb: Only probe for EGA and VGA 16 color graphic cards
>
> Christian Brauner <christian.brauner@ubuntu.com>
> 9p: only copy valid iattrs in 9P2000.L setattr implementation
>
> Sibi Sankar <sibis@codeaurora.org>
> remoteproc: qcom: pas: Add missing power-domain "mxc" for CDSP
>
> Eric Farman <farman@linux.ibm.com>
> KVM: s390: Clarify SIGP orders versus STOP/RESTART
>
> Li RongQing <lirongqing@baidu.com>
> KVM: x86: don't print when fail to read/write pv eoi memory
>
> Sean Christopherson <seanjc@google.com>
> KVM: x86: Register Processor Trace interrupt hook iff PT enabled in guest
>
> Sean Christopherson <seanjc@google.com>
> KVM: x86: Register perf callbacks after calling vendor's hardware_setup()
>
> Sean Christopherson <seanjc@google.com>
> perf: Protect perf_guest_cbs with RCU
>
> Jamie Hill-Daniel <jamie@hill-daniel.co.uk>
> vfs: fs_context: fix up param length parsing in legacy_parse_param
>
> Stephen Boyd <swboyd@chromium.org>
> remoteproc: qcom: pil_info: Don't memcpy_toio more than is provided
>
> Christophe JAILLET <christophe.jaillet@wanadoo.fr>
> orangefs: Fix the size of a memory allocation in orangefs_bufmap_alloc()
>
> Mario Limonciello <mario.limonciello@amd.com>
> drm/amd/display: explicitly set is_dsc_supported to false before use
>
> NeilBrown <neilb@suse.de>
> devtmpfs regression fix: reconfigure on each mount
>
>
> -------------
>
> Diffstat:
>
> Makefile | 4 +-
> arch/arm/kernel/perf_callchain.c | 17 ++++---
> arch/arm64/kernel/perf_callchain.c | 18 +++++---
> arch/csky/kernel/perf_callchain.c | 6 ++-
> arch/nds32/kernel/perf_event_cpu.c | 17 ++++---
> arch/riscv/kernel/perf_callchain.c | 7 ++-
> arch/s390/kvm/interrupt.c | 7 +++
> arch/s390/kvm/kvm-s390.c | 9 +++-
> arch/s390/kvm/kvm-s390.h | 1 +
> arch/s390/kvm/sigp.c | 28 ++++++++++++
> arch/x86/events/core.c | 17 ++++---
> arch/x86/events/intel/core.c | 9 ++--
> arch/x86/include/asm/kvm_host.h | 1 +
> arch/x86/kvm/lapic.c | 18 +++-----
> arch/x86/kvm/vmx/vmx.c | 1 +
> arch/x86/kvm/x86.c | 14 +++---
> drivers/base/devtmpfs.c | 7 +++
> drivers/firmware/qemu_fw_cfg.c | 20 ++++-----
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
> drivers/media/usb/uvc/uvc_video.c | 4 ++
> drivers/mtd/chips/Kconfig | 2 +
> drivers/mtd/maps/Kconfig | 2 +-
> .../net/wireless/realtek/rtlwifi/rtl8192cu/hw.c | 1 +
> drivers/remoteproc/qcom_pil_info.c | 2 +-
> drivers/remoteproc/qcom_q6v5_pas.c | 1 +
> drivers/video/fbdev/vga16fb.c | 24 ++++++++++
> fs/9p/vfs_inode_dotl.c | 29 ++++++++----
> fs/fs_context.c | 2 +-
> fs/orangefs/orangefs-bufmap.c | 7 ++-
> fs/super.c | 4 +-
> include/linux/fs_context.h | 2 +
> include/linux/perf_event.h | 13 +++++-
> kernel/events/core.c | 13 ++++--
> sound/pci/hda/hda_tegra.c | 43 ++++++++++++++----
> sound/pci/hda/patch_realtek.c | 52 ++++++++++++++++++++--
> tools/perf/ui/browsers/annotate.c | 23 ++++++----
> 36 files changed, 319 insertions(+), 107 deletions(-)
>
>
--
- Allen
^ permalink raw reply [relevance 0%]
* Re: [PATCH] remoteproc: Fix count check in rproc_coredump_write()
2022-01-19 23:21 7% [PATCH] remoteproc: Fix count check in rproc_coredump_write() Alistair Delva
@ 2022-01-20 0:24 0% ` Bjorn Andersson
0 siblings, 0 replies; 200+ results
From: Bjorn Andersson @ 2022-01-20 0:24 UTC (permalink / raw)
To: Alistair Delva
Cc: linux-kernel, Rishabh Bhatnagar, stable, Ohad Ben-Cohen,
Mathieu Poirier, Sibi Sankar, linux-remoteproc, kernel-team
On Wed 19 Jan 15:21 PST 2022, Alistair Delva wrote:
> Check count for 0, to avoid a potential underflow. Make the check the
> same as the one in rproc_recovery_write().
>
> Fixes: 3afdc59e4390 ("remoteproc: Add coredump debugfs entry")
> Signed-off-by: Alistair Delva <adelva@google.com>
> Cc: Rishabh Bhatnagar <rishabhb@codeaurora.org>
> Cc: stable@vger.kernel.org
> Cc: Ohad Ben-Cohen <ohad@wizery.com>
> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Sibi Sankar <sibis@codeaurora.org>
> Cc: linux-remoteproc@vger.kernel.org
> Cc: kernel-team@android.com
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Regards,
Bjorn
> ---
> drivers/remoteproc/remoteproc_debugfs.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/remoteproc/remoteproc_debugfs.c b/drivers/remoteproc/remoteproc_debugfs.c
> index b5a1e3b697d9..581930483ef8 100644
> --- a/drivers/remoteproc/remoteproc_debugfs.c
> +++ b/drivers/remoteproc/remoteproc_debugfs.c
> @@ -76,7 +76,7 @@ static ssize_t rproc_coredump_write(struct file *filp,
> int ret, err = 0;
> char buf[20];
>
> - if (count > sizeof(buf))
> + if (count < 1 || count > sizeof(buf))
> return -EINVAL;
>
> ret = copy_from_user(buf, user_buf, count);
> --
> 2.30.2
>
^ permalink raw reply [relevance 0%]
* [PATCH] remoteproc: Fix count check in rproc_coredump_write()
@ 2022-01-19 23:21 7% Alistair Delva
2022-01-20 0:24 0% ` Bjorn Andersson
0 siblings, 1 reply; 200+ results
From: Alistair Delva @ 2022-01-19 23:21 UTC (permalink / raw)
To: linux-kernel
Cc: Rishabh Bhatnagar, stable, Ohad Ben-Cohen, Bjorn Andersson,
Mathieu Poirier, Sibi Sankar, linux-remoteproc, kernel-team
Check count for 0, to avoid a potential underflow. Make the check the
same as the one in rproc_recovery_write().
Fixes: 3afdc59e4390 ("remoteproc: Add coredump debugfs entry")
Signed-off-by: Alistair Delva <adelva@google.com>
Cc: Rishabh Bhatnagar <rishabhb@codeaurora.org>
Cc: stable@vger.kernel.org
Cc: Ohad Ben-Cohen <ohad@wizery.com>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Sibi Sankar <sibis@codeaurora.org>
Cc: linux-remoteproc@vger.kernel.org
Cc: kernel-team@android.com
---
drivers/remoteproc/remoteproc_debugfs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/remoteproc/remoteproc_debugfs.c b/drivers/remoteproc/remoteproc_debugfs.c
index b5a1e3b697d9..581930483ef8 100644
--- a/drivers/remoteproc/remoteproc_debugfs.c
+++ b/drivers/remoteproc/remoteproc_debugfs.c
@@ -76,7 +76,7 @@ static ssize_t rproc_coredump_write(struct file *filp,
int ret, err = 0;
char buf[20];
- if (count > sizeof(buf))
+ if (count < 1 || count > sizeof(buf))
return -EINVAL;
ret = copy_from_user(buf, user_buf, count);
--
2.30.2
^ permalink raw reply related [relevance 7%]
* [PATCH 5.16 00/28] 5.16.2-rc1 review
@ 2022-01-18 16:05 4% Greg Kroah-Hartman
2022-01-18 16:06 9% ` [PATCH 5.16 11/28] remoteproc: qcom: pas: Add missing power-domain "mxc" for CDSP Greg Kroah-Hartman
0 siblings, 1 reply; 200+ results
From: Greg Kroah-Hartman @ 2022-01-18 16:05 UTC (permalink / raw)
To: linux-kernel
Cc: Greg Kroah-Hartman, torvalds, akpm, linux, shuah, patches,
lkft-triage, pavel, jonathanh, f.fainelli, stable
This is the start of the stable review cycle for the 5.16.2 release.
There are 28 patches in this series, all will be posted as a response
to this one. If anyone has any issues with these being applied, please
let me know.
Responses should be made by Thu, 20 Jan 2022 16:04:42 +0000.
Anything received after that time might be too late.
The whole patch series can be found in one patch at:
https://www.kernel.org/pub/linux/kernel/v5.x/stable-review/patch-5.16.2-rc1.gz
or in the git tree and branch at:
git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git linux-5.16.y
and the diffstat can be found below.
thanks,
greg k-h
-------------
Pseudo-Shortlog of commits:
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Linux 5.16.2-rc1
Takashi Iwai <tiwai@suse.de>
ALSA: hda/realtek: Re-order quirk entries for Lenovo
Baole Fang <fbl718@163.com>
ALSA: hda/realtek: Add quirk for Legion Y9000X 2020
Sameer Pujar <spujar@nvidia.com>
ALSA: hda/tegra: Fix Tegra194 HDA reset failure
Bart Kroon <bart@tarmack.eu>
ALSA: hda: ALC287: Add Lenovo IdeaPad Slim 9i 14ITL5 speaker quirk
Christian Lachner <gladiac@gmail.com>
ALSA: hda/realtek - Fix silent output on Gigabyte X570 Aorus Master after reboot from Windows
Kai-Heng Feng <kai.heng.feng@canonical.com>
ALSA: hda/realtek: Use ALC285_FIXUP_HP_GPIO_LED on another HP laptop
Arie Geiger <arsgeiger@gmail.com>
ALSA: hda/realtek: Add speaker fixup for some Yoga 15ITL5 devices
Dario Petrillo <dario.pk1@gmail.com>
perf annotate: Avoid TUI crash when navigating in the annotation of recursive functions
Johan Hovold <johan@kernel.org>
firmware: qemu_fw_cfg: fix kobject leak in probe error path
Johan Hovold <johan@kernel.org>
firmware: qemu_fw_cfg: fix NULL-pointer deref on duplicate entries
Johan Hovold <johan@kernel.org>
firmware: qemu_fw_cfg: fix sysfs information leak
Larry Finger <Larry.Finger@lwfinger.net>
rtlwifi: rtl8192cu: Fix WARNING when calling local_irq_restore() with interrupts enabled
Johan Hovold <johan@kernel.org>
media: uvcvideo: fix division by zero at stream start
Javier Martinez Canillas <javierm@redhat.com>
video: vga16fb: Only probe for EGA and VGA 16 color graphic cards
Dominique Martinet <asmadeus@codewreck.org>
9p: fix enodata when reading growing file
Christian Brauner <christian.brauner@ubuntu.com>
9p: only copy valid iattrs in 9P2000.L setattr implementation
Chuck Lever <chuck.lever@oracle.com>
NFSD: Fix zero-length NFSv3 WRITEs
Sibi Sankar <sibis@codeaurora.org>
remoteproc: qcom: pas: Add missing power-domain "mxc" for CDSP
Eric Farman <farman@linux.ibm.com>
KVM: s390: Clarify SIGP orders versus STOP/RESTART
Li RongQing <lirongqing@baidu.com>
KVM: x86: don't print when fail to read/write pv eoi memory
Sean Christopherson <seanjc@google.com>
KVM: x86: Register Processor Trace interrupt hook iff PT enabled in guest
Sean Christopherson <seanjc@google.com>
KVM: x86: Register perf callbacks after calling vendor's hardware_setup()
Sean Christopherson <seanjc@google.com>
perf: Protect perf_guest_cbs with RCU
Jamie Hill-Daniel <jamie@hill-daniel.co.uk>
vfs: fs_context: fix up param length parsing in legacy_parse_param
Stephen Boyd <swboyd@chromium.org>
remoteproc: qcom: pil_info: Don't memcpy_toio more than is provided
Christophe JAILLET <christophe.jaillet@wanadoo.fr>
orangefs: Fix the size of a memory allocation in orangefs_bufmap_alloc()
Mario Limonciello <mario.limonciello@amd.com>
drm/amd/display: explicitly set is_dsc_supported to false before use
NeilBrown <neilb@suse.de>
devtmpfs regression fix: reconfigure on each mount
-------------
Diffstat:
Makefile | 4 +-
arch/arm/kernel/perf_callchain.c | 17 ++++---
arch/arm64/kernel/perf_callchain.c | 18 +++++---
arch/csky/kernel/perf_callchain.c | 6 ++-
arch/nds32/kernel/perf_event_cpu.c | 17 ++++---
arch/riscv/kernel/perf_callchain.c | 7 ++-
arch/s390/kvm/interrupt.c | 7 +++
arch/s390/kvm/kvm-s390.c | 9 +++-
arch/s390/kvm/kvm-s390.h | 1 +
arch/s390/kvm/sigp.c | 28 ++++++++++++
arch/x86/events/core.c | 17 ++++---
arch/x86/events/intel/core.c | 9 ++--
arch/x86/include/asm/kvm_host.h | 1 +
arch/x86/kvm/lapic.c | 18 +++-----
arch/x86/kvm/vmx/vmx.c | 1 +
arch/x86/kvm/x86.c | 12 +++--
drivers/base/devtmpfs.c | 7 +++
drivers/firmware/qemu_fw_cfg.c | 20 ++++-----
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
drivers/media/usb/uvc/uvc_video.c | 4 ++
.../net/wireless/realtek/rtlwifi/rtl8192cu/hw.c | 1 +
drivers/remoteproc/qcom_pil_info.c | 2 +-
drivers/remoteproc/qcom_q6v5_pas.c | 1 +
drivers/video/fbdev/vga16fb.c | 24 ++++++++++
fs/9p/vfs_addr.c | 5 +++
fs/9p/vfs_inode_dotl.c | 29 ++++++++----
fs/fs_context.c | 2 +-
fs/nfsd/nfs3proc.c | 6 +--
fs/nfsd/nfsproc.c | 5 ---
fs/orangefs/orangefs-bufmap.c | 7 ++-
fs/super.c | 4 +-
include/linux/fs_context.h | 2 +
include/linux/perf_event.h | 13 +++++-
kernel/events/core.c | 13 ++++--
sound/pci/hda/hda_tegra.c | 43 ++++++++++++++----
sound/pci/hda/patch_realtek.c | 52 ++++++++++++++++++++--
tools/perf/ui/browsers/annotate.c | 23 ++++++----
37 files changed, 321 insertions(+), 115 deletions(-)
^ permalink raw reply [relevance 4%]
* [PATCH 5.16 11/28] remoteproc: qcom: pas: Add missing power-domain "mxc" for CDSP
2022-01-18 16:05 4% [PATCH 5.16 00/28] 5.16.2-rc1 review Greg Kroah-Hartman
@ 2022-01-18 16:06 9% ` Greg Kroah-Hartman
0 siblings, 0 replies; 200+ results
From: Greg Kroah-Hartman @ 2022-01-18 16:06 UTC (permalink / raw)
To: linux-kernel; +Cc: Greg Kroah-Hartman, stable, Sibi Sankar, Bjorn Andersson
From: Sibi Sankar <sibis@codeaurora.org>
commit dd585d9bfbf06fd08a6326c82978be1f06e7d1bd upstream.
Add missing power-domain "mxc" required by CDSP PAS remoteproc on SM8350
SoC.
Fixes: e8b4e9a21af7 ("remoteproc: qcom: pas: Add SM8350 PAS remoteprocs")
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Cc: stable@vger.kernel.org
Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1624559605-29847-1-git-send-email-sibis@codeaurora.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
drivers/remoteproc/qcom_q6v5_pas.c | 1 +
1 file changed, 1 insertion(+)
--- a/drivers/remoteproc/qcom_q6v5_pas.c
+++ b/drivers/remoteproc/qcom_q6v5_pas.c
@@ -652,6 +652,7 @@ static const struct adsp_data sm8350_cds
.auto_boot = true,
.proxy_pd_names = (char*[]){
"cx",
+ "mxc",
NULL
},
.load_state = "cdsp",
^ permalink raw reply [relevance 9%]
* [PATCH 5.15 11/28] remoteproc: qcom: pas: Add missing power-domain "mxc" for CDSP
2022-01-18 16:05 4% [PATCH 5.15 00/28] 5.15.16-rc1 review Greg Kroah-Hartman
@ 2022-01-18 16:05 9% ` Greg Kroah-Hartman
2022-01-22 0:29 0% ` [PATCH 5.15 00/28] 5.15.16-rc1 review Allen
1 sibling, 0 replies; 200+ results
From: Greg Kroah-Hartman @ 2022-01-18 16:05 UTC (permalink / raw)
To: linux-kernel; +Cc: Greg Kroah-Hartman, stable, Sibi Sankar, Bjorn Andersson
From: Sibi Sankar <sibis@codeaurora.org>
commit dd585d9bfbf06fd08a6326c82978be1f06e7d1bd upstream.
Add missing power-domain "mxc" required by CDSP PAS remoteproc on SM8350
SoC.
Fixes: e8b4e9a21af7 ("remoteproc: qcom: pas: Add SM8350 PAS remoteprocs")
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Cc: stable@vger.kernel.org
Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1624559605-29847-1-git-send-email-sibis@codeaurora.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
drivers/remoteproc/qcom_q6v5_pas.c | 1 +
1 file changed, 1 insertion(+)
--- a/drivers/remoteproc/qcom_q6v5_pas.c
+++ b/drivers/remoteproc/qcom_q6v5_pas.c
@@ -661,6 +661,7 @@ static const struct adsp_data sm8350_cds
},
.proxy_pd_names = (char*[]){
"cx",
+ "mxc",
NULL
},
.ssr_name = "cdsp",
^ permalink raw reply [relevance 9%]
* [PATCH 5.15 00/28] 5.15.16-rc1 review
@ 2022-01-18 16:05 4% Greg Kroah-Hartman
2022-01-18 16:05 9% ` [PATCH 5.15 11/28] remoteproc: qcom: pas: Add missing power-domain "mxc" for CDSP Greg Kroah-Hartman
2022-01-22 0:29 0% ` [PATCH 5.15 00/28] 5.15.16-rc1 review Allen
0 siblings, 2 replies; 200+ results
From: Greg Kroah-Hartman @ 2022-01-18 16:05 UTC (permalink / raw)
To: linux-kernel
Cc: Greg Kroah-Hartman, torvalds, akpm, linux, shuah, patches,
lkft-triage, pavel, jonathanh, f.fainelli, stable
This is the start of the stable review cycle for the 5.15.16 release.
There are 28 patches in this series, all will be posted as a response
to this one. If anyone has any issues with these being applied, please
let me know.
Responses should be made by Thu, 20 Jan 2022 16:04:42 +0000.
Anything received after that time might be too late.
The whole patch series can be found in one patch at:
https://www.kernel.org/pub/linux/kernel/v5.x/stable-review/patch-5.15.16-rc1.gz
or in the git tree and branch at:
git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git linux-5.15.y
and the diffstat can be found below.
thanks,
greg k-h
-------------
Pseudo-Shortlog of commits:
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Linux 5.15.16-rc1
Arnd Bergmann <arnd@arndb.de>
mtd: fixup CFI on ixp4xx
Takashi Iwai <tiwai@suse.de>
ALSA: hda/realtek: Re-order quirk entries for Lenovo
Baole Fang <fbl718@163.com>
ALSA: hda/realtek: Add quirk for Legion Y9000X 2020
Sameer Pujar <spujar@nvidia.com>
ALSA: hda/tegra: Fix Tegra194 HDA reset failure
Bart Kroon <bart@tarmack.eu>
ALSA: hda: ALC287: Add Lenovo IdeaPad Slim 9i 14ITL5 speaker quirk
Christian Lachner <gladiac@gmail.com>
ALSA: hda/realtek - Fix silent output on Gigabyte X570 Aorus Master after reboot from Windows
Kai-Heng Feng <kai.heng.feng@canonical.com>
ALSA: hda/realtek: Use ALC285_FIXUP_HP_GPIO_LED on another HP laptop
Arie Geiger <arsgeiger@gmail.com>
ALSA: hda/realtek: Add speaker fixup for some Yoga 15ITL5 devices
Wei Wang <wei.w.wang@intel.com>
KVM: x86: remove PMU FIXED_CTR3 from msrs_to_save_all
Dario Petrillo <dario.pk1@gmail.com>
perf annotate: Avoid TUI crash when navigating in the annotation of recursive functions
Johan Hovold <johan@kernel.org>
firmware: qemu_fw_cfg: fix kobject leak in probe error path
Johan Hovold <johan@kernel.org>
firmware: qemu_fw_cfg: fix NULL-pointer deref on duplicate entries
Johan Hovold <johan@kernel.org>
firmware: qemu_fw_cfg: fix sysfs information leak
Larry Finger <Larry.Finger@lwfinger.net>
rtlwifi: rtl8192cu: Fix WARNING when calling local_irq_restore() with interrupts enabled
Johan Hovold <johan@kernel.org>
media: uvcvideo: fix division by zero at stream start
Javier Martinez Canillas <javierm@redhat.com>
video: vga16fb: Only probe for EGA and VGA 16 color graphic cards
Christian Brauner <christian.brauner@ubuntu.com>
9p: only copy valid iattrs in 9P2000.L setattr implementation
Sibi Sankar <sibis@codeaurora.org>
remoteproc: qcom: pas: Add missing power-domain "mxc" for CDSP
Eric Farman <farman@linux.ibm.com>
KVM: s390: Clarify SIGP orders versus STOP/RESTART
Li RongQing <lirongqing@baidu.com>
KVM: x86: don't print when fail to read/write pv eoi memory
Sean Christopherson <seanjc@google.com>
KVM: x86: Register Processor Trace interrupt hook iff PT enabled in guest
Sean Christopherson <seanjc@google.com>
KVM: x86: Register perf callbacks after calling vendor's hardware_setup()
Sean Christopherson <seanjc@google.com>
perf: Protect perf_guest_cbs with RCU
Jamie Hill-Daniel <jamie@hill-daniel.co.uk>
vfs: fs_context: fix up param length parsing in legacy_parse_param
Stephen Boyd <swboyd@chromium.org>
remoteproc: qcom: pil_info: Don't memcpy_toio more than is provided
Christophe JAILLET <christophe.jaillet@wanadoo.fr>
orangefs: Fix the size of a memory allocation in orangefs_bufmap_alloc()
Mario Limonciello <mario.limonciello@amd.com>
drm/amd/display: explicitly set is_dsc_supported to false before use
NeilBrown <neilb@suse.de>
devtmpfs regression fix: reconfigure on each mount
-------------
Diffstat:
Makefile | 4 +-
arch/arm/kernel/perf_callchain.c | 17 ++++---
arch/arm64/kernel/perf_callchain.c | 18 +++++---
arch/csky/kernel/perf_callchain.c | 6 ++-
arch/nds32/kernel/perf_event_cpu.c | 17 ++++---
arch/riscv/kernel/perf_callchain.c | 7 ++-
arch/s390/kvm/interrupt.c | 7 +++
arch/s390/kvm/kvm-s390.c | 9 +++-
arch/s390/kvm/kvm-s390.h | 1 +
arch/s390/kvm/sigp.c | 28 ++++++++++++
arch/x86/events/core.c | 17 ++++---
arch/x86/events/intel/core.c | 9 ++--
arch/x86/include/asm/kvm_host.h | 1 +
arch/x86/kvm/lapic.c | 18 +++-----
arch/x86/kvm/vmx/vmx.c | 1 +
arch/x86/kvm/x86.c | 14 +++---
drivers/base/devtmpfs.c | 7 +++
drivers/firmware/qemu_fw_cfg.c | 20 ++++-----
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
drivers/media/usb/uvc/uvc_video.c | 4 ++
drivers/mtd/chips/Kconfig | 2 +
drivers/mtd/maps/Kconfig | 2 +-
.../net/wireless/realtek/rtlwifi/rtl8192cu/hw.c | 1 +
drivers/remoteproc/qcom_pil_info.c | 2 +-
drivers/remoteproc/qcom_q6v5_pas.c | 1 +
drivers/video/fbdev/vga16fb.c | 24 ++++++++++
fs/9p/vfs_inode_dotl.c | 29 ++++++++----
fs/fs_context.c | 2 +-
fs/orangefs/orangefs-bufmap.c | 7 ++-
fs/super.c | 4 +-
include/linux/fs_context.h | 2 +
include/linux/perf_event.h | 13 +++++-
kernel/events/core.c | 13 ++++--
sound/pci/hda/hda_tegra.c | 43 ++++++++++++++----
sound/pci/hda/patch_realtek.c | 52 ++++++++++++++++++++--
tools/perf/ui/browsers/annotate.c | 23 ++++++----
36 files changed, 319 insertions(+), 107 deletions(-)
^ permalink raw reply [relevance 4%]
* Re: [PATCH] remoteproc: qcom: q6v5: fix service routines build errors
2022-01-15 1:13 5% [PATCH] remoteproc: qcom: q6v5: fix service routines build errors Randy Dunlap
2022-01-15 8:09 0% ` Stephen Boyd
@ 2022-01-17 22:43 0% ` Bjorn Andersson
1 sibling, 0 replies; 200+ results
From: Bjorn Andersson @ 2022-01-17 22:43 UTC (permalink / raw)
To: Randy Dunlap
Cc: linux-kernel, kernel test robot, Mathieu Poirier,
linux-remoteproc, Sibi Sankar, Stephen Boyd
On Fri 14 Jan 19:13 CST 2022, Randy Dunlap wrote:
> When CONFIG_QCOM_AOSS_QMP=m and CONFIG_QCOM_Q6V5_MSS=y, the builtin
> driver cannot call into the loadable module's low-level service
> functions. Trying to build with that config combo causes linker errors.
>
> There are two problems here. First, drivers/remoteproc/qcom_q6v5.c
> should #include <linux/soc/qcom/qcom_aoss.h> for the definitions of
> the service functions, depending on whether CONFIG_QCOM_AOSS_QMP is
> set/enabled or not. Second, the qcom remoteproc drivers should depend
> on QCOM_AOSS_QMP iff it is enabled (=y or =m) so that the qcom
> remoteproc drivers can be built properly.
>
> This prevents these build errors:
>
> aarch64-linux-ld: drivers/remoteproc/qcom_q6v5.o: in function `q6v5_load_state_toggle':
> qcom_q6v5.c:(.text+0xc4): undefined reference to `qmp_send'
> aarch64-linux-ld: drivers/remoteproc/qcom_q6v5.o: in function `qcom_q6v5_deinit':
> (.text+0x2e4): undefined reference to `qmp_put'
> aarch64-linux-ld: drivers/remoteproc/qcom_q6v5.o: in function `qcom_q6v5_init':
> (.text+0x778): undefined reference to `qmp_get'
> aarch64-linux-ld: (.text+0x7d8): undefined reference to `qmp_put'
>
> Fixes: c1fe10d238c0 ("remoteproc: qcom: q6v5: Use qmp_send to update co-processor load state")
> Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
> Reported-by: kernel test robot <lkp@intel.com>
> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: linux-remoteproc@vger.kernel.org
> Cc: Sibi Sankar <sibis@codeaurora.org>
> Cc: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Regards,
Bjorn
> ---
> drivers/remoteproc/Kconfig | 4 ++++
> drivers/remoteproc/qcom_q6v5.c | 1 +
> 2 files changed, 5 insertions(+)
>
> --- linux-next-20220114.orig/drivers/remoteproc/qcom_q6v5.c
> +++ linux-next-20220114/drivers/remoteproc/qcom_q6v5.c
> @@ -10,6 +10,7 @@
> #include <linux/platform_device.h>
> #include <linux/interrupt.h>
> #include <linux/module.h>
> +#include <linux/soc/qcom/qcom_aoss.h>
> #include <linux/soc/qcom/smem.h>
> #include <linux/soc/qcom/smem_state.h>
> #include <linux/remoteproc.h>
> --- linux-next-20220114.orig/drivers/remoteproc/Kconfig
> +++ linux-next-20220114/drivers/remoteproc/Kconfig
> @@ -180,6 +180,7 @@ config QCOM_Q6V5_ADSP
> depends on RPMSG_QCOM_GLINK_SMEM || RPMSG_QCOM_GLINK_SMEM=n
> depends on QCOM_SYSMON || QCOM_SYSMON=n
> depends on RPMSG_QCOM_GLINK || RPMSG_QCOM_GLINK=n
> + depends on QCOM_AOSS_QMP || QCOM_AOSS_QMP=n
> select MFD_SYSCON
> select QCOM_PIL_INFO
> select QCOM_MDT_LOADER
> @@ -199,6 +200,7 @@ config QCOM_Q6V5_MSS
> depends on RPMSG_QCOM_GLINK_SMEM || RPMSG_QCOM_GLINK_SMEM=n
> depends on QCOM_SYSMON || QCOM_SYSMON=n
> depends on RPMSG_QCOM_GLINK || RPMSG_QCOM_GLINK=n
> + depends on QCOM_AOSS_QMP || QCOM_AOSS_QMP=n
> select MFD_SYSCON
> select QCOM_MDT_LOADER
> select QCOM_PIL_INFO
> @@ -218,6 +220,7 @@ config QCOM_Q6V5_PAS
> depends on RPMSG_QCOM_GLINK_SMEM || RPMSG_QCOM_GLINK_SMEM=n
> depends on QCOM_SYSMON || QCOM_SYSMON=n
> depends on RPMSG_QCOM_GLINK || RPMSG_QCOM_GLINK=n
> + depends on QCOM_AOSS_QMP || QCOM_AOSS_QMP=n
> select MFD_SYSCON
> select QCOM_PIL_INFO
> select QCOM_MDT_LOADER
> @@ -239,6 +242,7 @@ config QCOM_Q6V5_WCSS
> depends on RPMSG_QCOM_GLINK_SMEM || RPMSG_QCOM_GLINK_SMEM=n
> depends on QCOM_SYSMON || QCOM_SYSMON=n
> depends on RPMSG_QCOM_GLINK || RPMSG_QCOM_GLINK=n
> + depends on QCOM_AOSS_QMP || QCOM_AOSS_QMP=n
> select MFD_SYSCON
> select QCOM_MDT_LOADER
> select QCOM_PIL_INFO
^ permalink raw reply [relevance 0%]
* Re: [PATCH] remoteproc: qcom: q6v5: fix service routines build errors
2022-01-15 1:13 5% [PATCH] remoteproc: qcom: q6v5: fix service routines build errors Randy Dunlap
@ 2022-01-15 8:09 0% ` Stephen Boyd
2022-01-17 22:43 0% ` Bjorn Andersson
1 sibling, 0 replies; 200+ results
From: Stephen Boyd @ 2022-01-15 8:09 UTC (permalink / raw)
To: Randy Dunlap, linux-kernel
Cc: kernel test robot, Bjorn Andersson, Mathieu Poirier,
linux-remoteproc, Sibi Sankar
Quoting Randy Dunlap (2022-01-14 17:13:38)
> When CONFIG_QCOM_AOSS_QMP=m and CONFIG_QCOM_Q6V5_MSS=y, the builtin
> driver cannot call into the loadable module's low-level service
> functions. Trying to build with that config combo causes linker errors.
>
> There are two problems here. First, drivers/remoteproc/qcom_q6v5.c
> should #include <linux/soc/qcom/qcom_aoss.h> for the definitions of
> the service functions, depending on whether CONFIG_QCOM_AOSS_QMP is
> set/enabled or not. Second, the qcom remoteproc drivers should depend
> on QCOM_AOSS_QMP iff it is enabled (=y or =m) so that the qcom
> remoteproc drivers can be built properly.
>
> This prevents these build errors:
>
> aarch64-linux-ld: drivers/remoteproc/qcom_q6v5.o: in function `q6v5_load_state_toggle':
> qcom_q6v5.c:(.text+0xc4): undefined reference to `qmp_send'
> aarch64-linux-ld: drivers/remoteproc/qcom_q6v5.o: in function `qcom_q6v5_deinit':
> (.text+0x2e4): undefined reference to `qmp_put'
> aarch64-linux-ld: drivers/remoteproc/qcom_q6v5.o: in function `qcom_q6v5_init':
> (.text+0x778): undefined reference to `qmp_get'
> aarch64-linux-ld: (.text+0x7d8): undefined reference to `qmp_put'
>
> Fixes: c1fe10d238c0 ("remoteproc: qcom: q6v5: Use qmp_send to update co-processor load state")
> Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
> Reported-by: kernel test robot <lkp@intel.com>
> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: linux-remoteproc@vger.kernel.org
> Cc: Sibi Sankar <sibis@codeaurora.org>
> Cc: Stephen Boyd <swboyd@chromium.org>
> ---
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
^ permalink raw reply [relevance 0%]
* [PATCH] remoteproc: qcom: q6v5: fix service routines build errors
@ 2022-01-15 1:13 5% Randy Dunlap
2022-01-15 8:09 0% ` Stephen Boyd
2022-01-17 22:43 0% ` Bjorn Andersson
0 siblings, 2 replies; 200+ results
From: Randy Dunlap @ 2022-01-15 1:13 UTC (permalink / raw)
To: linux-kernel
Cc: Randy Dunlap, kernel test robot, Bjorn Andersson,
Mathieu Poirier, linux-remoteproc, Sibi Sankar, Stephen Boyd
When CONFIG_QCOM_AOSS_QMP=m and CONFIG_QCOM_Q6V5_MSS=y, the builtin
driver cannot call into the loadable module's low-level service
functions. Trying to build with that config combo causes linker errors.
There are two problems here. First, drivers/remoteproc/qcom_q6v5.c
should #include <linux/soc/qcom/qcom_aoss.h> for the definitions of
the service functions, depending on whether CONFIG_QCOM_AOSS_QMP is
set/enabled or not. Second, the qcom remoteproc drivers should depend
on QCOM_AOSS_QMP iff it is enabled (=y or =m) so that the qcom
remoteproc drivers can be built properly.
This prevents these build errors:
aarch64-linux-ld: drivers/remoteproc/qcom_q6v5.o: in function `q6v5_load_state_toggle':
qcom_q6v5.c:(.text+0xc4): undefined reference to `qmp_send'
aarch64-linux-ld: drivers/remoteproc/qcom_q6v5.o: in function `qcom_q6v5_deinit':
(.text+0x2e4): undefined reference to `qmp_put'
aarch64-linux-ld: drivers/remoteproc/qcom_q6v5.o: in function `qcom_q6v5_init':
(.text+0x778): undefined reference to `qmp_get'
aarch64-linux-ld: (.text+0x7d8): undefined reference to `qmp_put'
Fixes: c1fe10d238c0 ("remoteproc: qcom: q6v5: Use qmp_send to update co-processor load state")
Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Reported-by: kernel test robot <lkp@intel.com>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: linux-remoteproc@vger.kernel.org
Cc: Sibi Sankar <sibis@codeaurora.org>
Cc: Stephen Boyd <swboyd@chromium.org>
---
drivers/remoteproc/Kconfig | 4 ++++
drivers/remoteproc/qcom_q6v5.c | 1 +
2 files changed, 5 insertions(+)
--- linux-next-20220114.orig/drivers/remoteproc/qcom_q6v5.c
+++ linux-next-20220114/drivers/remoteproc/qcom_q6v5.c
@@ -10,6 +10,7 @@
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/module.h>
+#include <linux/soc/qcom/qcom_aoss.h>
#include <linux/soc/qcom/smem.h>
#include <linux/soc/qcom/smem_state.h>
#include <linux/remoteproc.h>
--- linux-next-20220114.orig/drivers/remoteproc/Kconfig
+++ linux-next-20220114/drivers/remoteproc/Kconfig
@@ -180,6 +180,7 @@ config QCOM_Q6V5_ADSP
depends on RPMSG_QCOM_GLINK_SMEM || RPMSG_QCOM_GLINK_SMEM=n
depends on QCOM_SYSMON || QCOM_SYSMON=n
depends on RPMSG_QCOM_GLINK || RPMSG_QCOM_GLINK=n
+ depends on QCOM_AOSS_QMP || QCOM_AOSS_QMP=n
select MFD_SYSCON
select QCOM_PIL_INFO
select QCOM_MDT_LOADER
@@ -199,6 +200,7 @@ config QCOM_Q6V5_MSS
depends on RPMSG_QCOM_GLINK_SMEM || RPMSG_QCOM_GLINK_SMEM=n
depends on QCOM_SYSMON || QCOM_SYSMON=n
depends on RPMSG_QCOM_GLINK || RPMSG_QCOM_GLINK=n
+ depends on QCOM_AOSS_QMP || QCOM_AOSS_QMP=n
select MFD_SYSCON
select QCOM_MDT_LOADER
select QCOM_PIL_INFO
@@ -218,6 +220,7 @@ config QCOM_Q6V5_PAS
depends on RPMSG_QCOM_GLINK_SMEM || RPMSG_QCOM_GLINK_SMEM=n
depends on QCOM_SYSMON || QCOM_SYSMON=n
depends on RPMSG_QCOM_GLINK || RPMSG_QCOM_GLINK=n
+ depends on QCOM_AOSS_QMP || QCOM_AOSS_QMP=n
select MFD_SYSCON
select QCOM_PIL_INFO
select QCOM_MDT_LOADER
@@ -239,6 +242,7 @@ config QCOM_Q6V5_WCSS
depends on RPMSG_QCOM_GLINK_SMEM || RPMSG_QCOM_GLINK_SMEM=n
depends on QCOM_SYSMON || QCOM_SYSMON=n
depends on RPMSG_QCOM_GLINK || RPMSG_QCOM_GLINK=n
+ depends on QCOM_AOSS_QMP || QCOM_AOSS_QMP=n
select MFD_SYSCON
select QCOM_MDT_LOADER
select QCOM_PIL_INFO
^ permalink raw reply [relevance 5%]
* [PATCH] remoteproc: qcom: q6v5: make symbols modular when QCOM_AOSS_QMP=m
@ 2021-12-11 6:46 5% Randy Dunlap
0 siblings, 0 replies; 200+ results
From: Randy Dunlap @ 2021-12-11 6:46 UTC (permalink / raw)
To: linux-kernel
Cc: Randy Dunlap, Sibi Sankar, Bjorn Andersson, Stephen Boyd,
Mathieu Poirier, Ohad Ben-Cohen, linux-remoteproc
When CONFIG_QCOM_Q6V5_COMMON=y and CONFIG_QCOM_AOSS_QMP=m,
there are linker errors:
aarch64-linux-ld: drivers/remoteproc/qcom_q6v5.o: in function `q6v5_load_state_toggle':
qcom_q6v5.c:(.text+0xac): undefined reference to `qmp_send'
qcom_q6v5.c:(.text+0xac): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `qmp_send'
aarch64-linux-ld: drivers/remoteproc/qcom_q6v5.o: in function `qcom_q6v5_deinit':
(.text+0x204): undefined reference to `qmp_put'
(.text+0x204): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `qmp_put'
Fix these by requiring QCOM_Q6V5 symbols to be modular (=m) when
QCOM_AOSS_QMP=m.
Fixes: c1fe10d238c0 ("remoteproc: qcom: q6v5: Use qmp_send to update co-processor load state")
Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Cc: Sibi Sankar <sibis@codeaurora.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Stephen Boyd <swboyd@chromium.org>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Ohad Ben-Cohen <ohad@wizery.com>
Cc: linux-remoteproc@vger.kernel.org
---
drivers/remoteproc/Kconfig | 4 ++++
1 file changed, 4 insertions(+)
--- next-2021-1210.orig/drivers/remoteproc/Kconfig
+++ next-2021-1210/drivers/remoteproc/Kconfig
@@ -176,6 +176,7 @@ config QCOM_Q6V5_ADSP
tristate "Qualcomm Technology Inc ADSP Peripheral Image Loader"
depends on OF && ARCH_QCOM
depends on QCOM_SMEM
+ depends on QCOM_AOSS_QMP
depends on RPMSG_QCOM_SMD || RPMSG_QCOM_SMD=n
depends on RPMSG_QCOM_GLINK_SMEM || RPMSG_QCOM_GLINK_SMEM=n
depends on QCOM_SYSMON || QCOM_SYSMON=n
@@ -195,6 +196,7 @@ config QCOM_Q6V5_MSS
tristate "Qualcomm Hexagon V5 self-authenticating modem subsystem support"
depends on OF && ARCH_QCOM
depends on QCOM_SMEM
+ depends on QCOM_AOSS_QMP
depends on RPMSG_QCOM_SMD || RPMSG_QCOM_SMD=n
depends on RPMSG_QCOM_GLINK_SMEM || RPMSG_QCOM_GLINK_SMEM=n
depends on QCOM_SYSMON || QCOM_SYSMON=n
@@ -214,6 +216,7 @@ config QCOM_Q6V5_PAS
tristate "Qualcomm Hexagon v5 Peripheral Authentication Service support"
depends on OF && ARCH_QCOM
depends on QCOM_SMEM
+ depends on QCOM_AOSS_QMP
depends on RPMSG_QCOM_SMD || RPMSG_QCOM_SMD=n
depends on RPMSG_QCOM_GLINK_SMEM || RPMSG_QCOM_GLINK_SMEM=n
depends on QCOM_SYSMON || QCOM_SYSMON=n
@@ -235,6 +238,7 @@ config QCOM_Q6V5_WCSS
tristate "Qualcomm Hexagon based WCSS Peripheral Image Loader"
depends on OF && ARCH_QCOM
depends on QCOM_SMEM
+ depends on QCOM_AOSS_QMP
depends on RPMSG_QCOM_SMD || RPMSG_QCOM_SMD=n
depends on RPMSG_QCOM_GLINK_SMEM || RPMSG_QCOM_GLINK_SMEM=n
depends on QCOM_SYSMON || QCOM_SYSMON=n
^ permalink raw reply [relevance 5%]
* Re: [PATCH v7] arm64: dts: qcom: sc7280: Add WPSS remoteproc node
@ 2021-11-29 9:55 6% ` Sibi Sankar
0 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-11-29 9:55 UTC (permalink / raw)
To: Rakesh Pillai
Cc: agross, bjorn.andersson, robh+dt, swboyd, linux-arm-msm,
devicetree, linux-kernel, mpubbise, kuabhs,
pillair=codeaurora.org
Hey Rakesh,
On 2021-11-19 10:54, Rakesh Pillai wrote:
> Add the WPSS remoteproc node in dts for
> PIL loading.
>
> Reviewed-by: Stephen Boyd <swboyd@chromium.org>
> Signed-off-by: Rakesh Pillai <pillair@codeaurora.org>
> ---
> Changes from v6:
> - Swap the oder of two properties in wpss_mem reserved memory
>
> Changes from v5:
> - Update the clock names
> ---
> arch/arm64/boot/dts/qcom/sc7280-idp.dts | 4 +++
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 56
> +++++++++++++++++++++++++++++++++
> 2 files changed, 60 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> index 9b991ba..ddab150 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> @@ -80,3 +80,7 @@
> qcom,pre-scaling = <1 1>;
> };
> };
> +
> +&remoteproc_wpss {
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 365a2e0..dd93f13 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -134,6 +134,11 @@
> no-map;
> };
>
> + wpss_mem: memory@9ae00000 {
> + reg = <0x0 0x9ae00000 0x0 0x1900000>;
> + no-map;
> + };
> +
wpss_mem is already part of idp
board dts. We no longer include
PIL reserved memory regions in
the base SoC dtsi since the size
varies across boards.
> rmtfs_mem: memory@9c900000 {
> compatible = "qcom,rmtfs-mem";
> reg = <0x0 0x9c900000 0x0 0x280000>;
> @@ -2598,6 +2603,57 @@
> status = "disabled";
> };
>
> + remoteproc_wpss: remoteproc@8a00000 {
> + compatible = "qcom,sc7280-wpss-pil";
> + reg = <0 0x08a00000 0 0x10000>;
> +
> + interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>,
> + <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
> + <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
> + <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
> + <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
> + <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "wdog", "fatal", "ready", "handover",
> + "stop-ack", "shutdown-ack";
> +
> + clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>,
> + <&gcc GCC_WPSS_AHB_CLK>,
> + <&gcc GCC_WPSS_RSCP_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "ahb_bdg", "ahb",
> + "rscp", "xo";
> +
> + power-domains = <&rpmhpd SC7280_CX>,
> + <&rpmhpd SC7280_MX>;
> + power-domain-names = "cx", "mx";
> +
> + memory-region = <&wpss_mem>;
> +
> + qcom,qmp = <&aoss_qmp>;
> +
> + qcom,smem-states = <&wpss_smp2p_out 0>;
> + qcom,smem-state-names = "stop";
> +
> + resets = <&aoss_reset AOSS_CC_WCSS_RESTART>,
> + <&pdc_reset PDC_WPSS_SYNC_RESET>;
> + reset-names = "restart", "pdc_sync";
> +
> + qcom,halt-regs = <&tcsr_mutex 0x37000>;
> +
> + status = "disabled";
> +
> + glink-edge {
> + interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
> + IPCC_MPROC_SIGNAL_GLINK_QMP
> + IRQ_TYPE_EDGE_RISING>;
> + mboxes = <&ipcc IPCC_CLIENT_WPSS
> + IPCC_MPROC_SIGNAL_GLINK_QMP>;
> +
> + label = "wpss";
> + qcom,remote-pid = <13>;
> + };
> + };
> +
> dc_noc: interconnect@90e0000 {
> reg = <0 0x090e0000 0 0x5080>;
> compatible = "qcom,sc7280-dc-noc";
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply [relevance 6%]
* RE: [PATCH v6] arm64: dts: qcom: sc7280: Add WPSS remoteproc node
@ 2021-11-19 5:25 0% ` Rakesh Pillai
0 siblings, 0 replies; 200+ results
From: Rakesh Pillai @ 2021-11-19 5:25 UTC (permalink / raw)
To: 'Stephen Boyd', agross, bjorn.andersson, robh+dt
Cc: linux-arm-msm, devicetree, linux-kernel, sibis, mpubbise, kuabhs
> -----Original Message-----
> From: Stephen Boyd <swboyd@chromium.org>
> Sent: Friday, November 19, 2021 6:22 AM
> To: Rakesh Pillai <pillair@codeaurora.org>; agross@kernel.org;
> bjorn.andersson@linaro.org; robh+dt@kernel.org
> Cc: linux-arm-msm@vger.kernel.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; sibis@codeaurora.org; mpubbise@codeaurora.org;
> kuabhs@chromium.org
> Subject: Re: [PATCH v6] arm64: dts: qcom: sc7280: Add WPSS remoteproc
> node
>
> Quoting Rakesh Pillai (2021-11-18 07:56:56)
> > Add the WPSS remoteproc node in dts for PIL loading.
> >
> > Signed-off-by: Rakesh Pillai <pillair@codeaurora.org>
> > ---
> > Changes from v5:
> > - Update the clock names
> > ---
> > arch/arm64/boot/dts/qcom/sc7280-idp.dts | 4 +++
> > arch/arm64/boot/dts/qcom/sc7280.dtsi | 56
> +++++++++++++++++++++++++++++++++
> > 2 files changed, 60 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> > b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> > index 9b991ba..ddab150 100644
> > --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> > +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> > @@ -80,3 +80,7 @@
> > qcom,pre-scaling = <1 1>;
> > };
> > };
> > +
> > +&remoteproc_wpss {
> > + status = "okay";
> > +};
> > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > index 365a2e0..76c2a90 100644
> > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > @@ -134,6 +134,11 @@
> > no-map;
> > };
> >
> > + wpss_mem: memory@9ae00000 {
> > + no-map;
> > + reg = <0x0 0x9ae00000 0x0 0x1900000>;
>
> Almost always reg comes first. Please swap the order of these two
> properties.
Hi Stephen,
I have fixed this and sent v7 for the DTSI change.
Thanks,
Rakesh Pillai
>
> > + };
> > +
> > rmtfs_mem: memory@9c900000 {
> > compatible = "qcom,rmtfs-mem";
> > reg = <0x0 0x9c900000 0x0 0x280000>;
>
> Otherwise
>
> Reviewed-by: Stephen Boyd <swboyd@chromium.org>
^ permalink raw reply [relevance 0%]
* Re: [PATCH] remoteproc: qcom: pas: Add missing power-domain "mxc" for CDSP
@ 2021-11-17 18:57 0% ` Bjorn Andersson
0 siblings, 0 replies; 200+ results
From: Bjorn Andersson @ 2021-11-17 18:57 UTC (permalink / raw)
To: Sibi Sankar
Cc: vkoul, agross, ohad, mathieu.poirier, linux-remoteproc,
linux-kernel, linux-arm-msm, stable
On Thu 24 Jun 13:33 CDT 2021, Sibi Sankar wrote:
> Add missing power-domain "mxc" required by CDSP PAS remoteproc on SM8350
> SoC.
>
> Fixes: e8b4e9a21af7 ("remoteproc: qcom: pas: Add SM8350 PAS remoteprocs")
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> Cc: stable@vger.kernel.org
> ---
>
> The device tree and pas documentation lists mcx as a required pd for cdsp.
> Looks like it was missed while adding the proxy pds in the pas driver.
> Bjorn/Vinod you'll need to test this patch before picking it up.
>
At least on the HDK mxc seems to be optional given the current system
state, but I don't see any regressions so let's land this before we put
the system in a state where it would matter.
Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Regards,
Bjorn
> drivers/remoteproc/qcom_q6v5_pas.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q6v5_pas.c
> index b921fc26cd04..ad20065dbdea 100644
> --- a/drivers/remoteproc/qcom_q6v5_pas.c
> +++ b/drivers/remoteproc/qcom_q6v5_pas.c
> @@ -661,6 +661,7 @@ static const struct adsp_data sm8350_cdsp_resource = {
> },
> .proxy_pd_names = (char*[]){
> "cx",
> + "mxc",
> NULL
> },
> .ssr_name = "cdsp",
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
^ permalink raw reply [relevance 0%]
* RE: [PATCH v8 3/3] remoteproc: qcom: q6v5_wpss: Add support for sc7280 WPSS
2021-11-17 6:31 0% ` Rakesh Pillai
@ 2021-11-17 6:39 0% ` Stephen Boyd
0 siblings, 0 replies; 200+ results
From: Stephen Boyd @ 2021-11-17 6:39 UTC (permalink / raw)
To: Rakesh Pillai, agross, bjorn.andersson, mathieu.poirier, ohad,
p.zabel, robh+dt
Cc: linux-arm-msm, linux-remoteproc, devicetree, linux-kernel, sibis,
mpubbise, kuabhs
Quoting Rakesh Pillai (2021-11-16 22:31:51)
>
>
> > -----Original Message-----
> > From: Stephen Boyd <swboyd@chromium.org>
> > Sent: Wednesday, November 17, 2021 4:25 AM
> > To: Rakesh Pillai <pillair@codeaurora.org>; agross@kernel.org;
> > bjorn.andersson@linaro.org; mathieu.poirier@linaro.org; ohad@wizery.com;
> > p.zabel@pengutronix.de; robh+dt@kernel.org
> > Cc: linux-arm-msm@vger.kernel.org; linux-remoteproc@vger.kernel.org;
> > devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> > sibis@codeaurora.org; mpubbise@codeaurora.org; kuabhs@chromium.org
> > Subject: Re: [PATCH v8 3/3] remoteproc: qcom: q6v5_wpss: Add support for
> > sc7280 WPSS
> >
> > Quoting Rakesh Pillai (2021-11-02 06:44:33)
> > > @@ -457,7 +608,13 @@ static int adsp_probe(struct platform_device
> > *pdev)
> > > if (ret)
> > > goto free_rproc;
> > >
> > > - pm_runtime_enable(adsp->dev);
> > > + ret = qcom_rproc_pds_attach(adsp->dev, adsp->proxy_pds,
> > > + desc->proxy_pd_names);
> > > + if (ret < 0) {
> > > + dev_err(&pdev->dev, "Failed to attach proxy power domains\n");
> > > + goto free_rproc;
> > > + }
> > > + adsp->proxy_pd_count = ret;
> >
> > Can we check this against the define so that we don't have more than the
> > fixed number of power domains and try to access elements beyond the
> > length of the array?
>
> The number of entries populated in the "proxy_pds" array depends on the "desc->proxy_pd_names", which is statically
> initialized for each remoteproc. Hence there will not be any out of bound access for this array.
>
Sure nothing is wrong today but it's a potential problem in the future
if someone adds more elements to proxy_pd_names than proxy_pds can hold.
Please prevent that from happening by writing stricter code.
^ permalink raw reply [relevance 0%]
* RE: [PATCH v8 3/3] remoteproc: qcom: q6v5_wpss: Add support for sc7280 WPSS
@ 2021-11-17 6:31 0% ` Rakesh Pillai
2021-11-17 6:39 0% ` Stephen Boyd
0 siblings, 1 reply; 200+ results
From: Rakesh Pillai @ 2021-11-17 6:31 UTC (permalink / raw)
To: 'Stephen Boyd',
agross, bjorn.andersson, mathieu.poirier, ohad, p.zabel, robh+dt
Cc: linux-arm-msm, linux-remoteproc, devicetree, linux-kernel, sibis,
mpubbise, kuabhs
> -----Original Message-----
> From: Stephen Boyd <swboyd@chromium.org>
> Sent: Wednesday, November 17, 2021 4:25 AM
> To: Rakesh Pillai <pillair@codeaurora.org>; agross@kernel.org;
> bjorn.andersson@linaro.org; mathieu.poirier@linaro.org; ohad@wizery.com;
> p.zabel@pengutronix.de; robh+dt@kernel.org
> Cc: linux-arm-msm@vger.kernel.org; linux-remoteproc@vger.kernel.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> sibis@codeaurora.org; mpubbise@codeaurora.org; kuabhs@chromium.org
> Subject: Re: [PATCH v8 3/3] remoteproc: qcom: q6v5_wpss: Add support for
> sc7280 WPSS
>
> Quoting Rakesh Pillai (2021-11-02 06:44:33)
> > @@ -457,7 +608,13 @@ static int adsp_probe(struct platform_device
> *pdev)
> > if (ret)
> > goto free_rproc;
> >
> > - pm_runtime_enable(adsp->dev);
> > + ret = qcom_rproc_pds_attach(adsp->dev, adsp->proxy_pds,
> > + desc->proxy_pd_names);
> > + if (ret < 0) {
> > + dev_err(&pdev->dev, "Failed to attach proxy power domains\n");
> > + goto free_rproc;
> > + }
> > + adsp->proxy_pd_count = ret;
>
> Can we check this against the define so that we don't have more than the
> fixed number of power domains and try to access elements beyond the
> length of the array?
The number of entries populated in the "proxy_pds" array depends on the "desc->proxy_pd_names", which is statically
initialized for each remoteproc. Hence there will not be any out of bound access for this array.
Thanks,
Rakesh Pillai.
^ permalink raw reply [relevance 0%]
* RE: [PATCH v8 3/3] remoteproc: qcom: q6v5_wpss: Add support for sc7280 WPSS
@ 2021-11-16 17:49 0% ` pillair
0 siblings, 0 replies; 200+ results
From: pillair @ 2021-11-16 17:49 UTC (permalink / raw)
To: 'Stephen Boyd',
agross, bjorn.andersson, mathieu.poirier, ohad, p.zabel, robh+dt
Cc: linux-arm-msm, linux-remoteproc, devicetree, linux-kernel, sibis,
mpubbise, kuabhs
> -----Original Message-----
> From: Stephen Boyd <swboyd@chromium.org>
> Sent: Tuesday, November 16, 2021 5:13 AM
> To: Rakesh Pillai <pillair@codeaurora.org>; agross@kernel.org;
> bjorn.andersson@linaro.org; mathieu.poirier@linaro.org; ohad@wizery.com;
> p.zabel@pengutronix.de; robh+dt@kernel.org
> Cc: linux-arm-msm@vger.kernel.org; linux-remoteproc@vger.kernel.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> sibis@codeaurora.org; mpubbise@codeaurora.org; kuabhs@chromium.org
> Subject: Re: [PATCH v8 3/3] remoteproc: qcom: q6v5_wpss: Add support for
> sc7280 WPSS
>
> Quoting Rakesh Pillai (2021-11-02 06:44:33)
> > diff --git a/drivers/remoteproc/qcom_q6v5_adsp.c
> b/drivers/remoteproc/qcom_q6v5_adsp.c
> > index 098362e6..e2e8d33 100644
> > --- a/drivers/remoteproc/qcom_q6v5_adsp.c
> > +++ b/drivers/remoteproc/qcom_q6v5_adsp.c
> > @@ -435,12 +571,22 @@ static int adsp_probe(struct platform_device
> *pdev)
> > if (!desc)
> > return -EINVAL;
> >
> > + firmware_name = desc->firmware_name;
> > + ret = of_property_read_string(pdev->dev.of_node, "firmware-
> name",
>
> Is this documented in the binding? If not, please add it.
Hi Stephen,
"firmware-name" is already documented in the bindings.
Thanks,
Rakesh Pillai.
^ permalink raw reply [relevance 0%]
* RE: [PATCH v7 2/3] dt-bindings: remoteproc: qcom: Add SC7280 WPSS support
@ 2021-11-02 13:45 0% ` pillair
0 siblings, 0 replies; 200+ results
From: pillair @ 2021-11-02 13:45 UTC (permalink / raw)
To: 'Stephen Boyd',
agross, bjorn.andersson, mathieu.poirier, ohad, p.zabel, robh+dt
Cc: linux-arm-msm, linux-remoteproc, devicetree, linux-kernel, sibis,
mpubbise, kuabhs
> -----Original Message-----
> From: Stephen Boyd <swboyd@chromium.org>
> Sent: Saturday, October 30, 2021 12:34 AM
> To: agross@kernel.org; bjorn.andersson@linaro.org;
> mathieu.poirier@linaro.org; ohad@wizery.com; p.zabel@pengutronix.de;
> pillair@codeaurora.org; robh+dt@kernel.org
> Cc: linux-arm-msm@vger.kernel.org; linux-remoteproc@vger.kernel.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> sibis@codeaurora.org; mpubbise@codeaurora.org; kuabhs@chromium.org
> Subject: RE: [PATCH v7 2/3] dt-bindings: remoteproc: qcom: Add SC7280
> WPSS support
>
> Quoting pillair@codeaurora.org (2021-10-29 03:46:03)
> >
> > > > +
> > > > + glink-edge {
> > > > + interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
> > > > + IPCC_MPROC_SIGNAL_GLINK_QMP
> > > > + IRQ_TYPE_EDGE_RISING>;
> > > > + mboxes = <&ipcc IPCC_CLIENT_WPSS
> > > > + IPCC_MPROC_SIGNAL_GLINK_QMP>;
> > > > +
> > > > + label = "wpss";
> > > > + qcom,remote-pid = <13>;
> > >
> > > There are a few properties here that don't seem to be required. Is
> > > that intentional?
> >
> > Hi Stephen,
> > All the properties in the example are listed as required (except for status,
> which will be removed in the subsequent patchset).
> > Do you mean the glink-edge node properties ?
>
> Yes I mean all the properties in the glink-edge node. Are they required?
> If so then we need to list them in the schema.
Hi Stephen,
I have sent v8 with glink-edge properties also included in the dt-bindings.
Thanks,
Rakesh Pillai.
^ permalink raw reply [relevance 0%]
* Re: [v8 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider
2021-10-28 23:27 6% ` Bjorn Andersson
@ 2021-11-01 13:39 6% ` okukatla
0 siblings, 0 replies; 200+ results
From: okukatla @ 2021-11-01 13:39 UTC (permalink / raw)
To: Bjorn Andersson
Cc: georgi.djakov, evgreen, Andy Gross, Rob Herring, linux-arm-msm,
devicetree, linux-kernel, sboyd, mdtipton, sibis, saravanak,
seansw, elder, linux-pm, linux-arm-msm-owner
On 2021-10-29 04:57, Bjorn Andersson wrote:
> On Thu 21 Oct 03:40 PDT 2021, Odelu Kukatla wrote:
>
>> Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280
>> SoCs.
>>
>> Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
>> ---
>> arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 ++++++++
>> 1 file changed, 8 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> index d74a4c8..0b55742 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> @@ -3687,6 +3687,14 @@
>> };
>> };
>>
>> + epss_l3: interconnect@18590000 {
>> + compatible = "qcom,sc7280-epss-l3";
>> + reg = <0 0x18590000 0 0x1000>;
>
> This series looks like I would expect, with and without per-core dcvs.
> But can you please explain why this contradict what Sibi says here:
> https://lore.kernel.org/all/1627581885-32165-3-git-send-email-sibis@codeaurora.org/
>
> Regards,
> Bjorn
>
Thanks for Review!
Sibi's patch will be dropped, it is not required with my updated patch
series:
https://lore.kernel.org/all/1627581885-32165-3-git-send-email-sibis@codeaurora.org/
>> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
>> + clock-names = "xo", "alternate";
>> + #interconnect-cells = <1>;
>> + };
>> +
>> cpufreq_hw: cpufreq@18591000 {
>> compatible = "qcom,cpufreq-epss";
>> reg = <0 0x18591000 0 0x1000>,
>> --
>> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
>> Forum,
>> a Linux Foundation Collaborative Project
>>
^ permalink raw reply [relevance 6%]
* RE: [PATCH v7 2/3] dt-bindings: remoteproc: qcom: Add SC7280 WPSS support
@ 2021-10-29 10:46 0% ` pillair
0 siblings, 1 reply; 200+ results
From: pillair @ 2021-10-29 10:46 UTC (permalink / raw)
To: 'Stephen Boyd',
agross, bjorn.andersson, mathieu.poirier, ohad, p.zabel, robh+dt
Cc: linux-arm-msm, linux-remoteproc, devicetree, linux-kernel, sibis,
mpubbise, kuabhs
> -----Original Message-----
> From: Stephen Boyd <swboyd@chromium.org>
> Sent: Friday, October 29, 2021 3:38 AM
> To: Rakesh Pillai <pillair@codeaurora.org>; agross@kernel.org;
> bjorn.andersson@linaro.org; mathieu.poirier@linaro.org; ohad@wizery.com;
> p.zabel@pengutronix.de; robh+dt@kernel.org
> Cc: linux-arm-msm@vger.kernel.org; linux-remoteproc@vger.kernel.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> sibis@codeaurora.org; mpubbise@codeaurora.org; kuabhs@chromium.org
> Subject: Re: [PATCH v7 2/3] dt-bindings: remoteproc: qcom: Add SC7280
> WPSS support
>
> > +
> > + glink-edge {
> > + interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
> > + IPCC_MPROC_SIGNAL_GLINK_QMP
> > + IRQ_TYPE_EDGE_RISING>;
> > + mboxes = <&ipcc IPCC_CLIENT_WPSS
> > + IPCC_MPROC_SIGNAL_GLINK_QMP>;
> > +
> > + label = "wpss";
> > + qcom,remote-pid = <13>;
>
> There are a few properties here that don't seem to be required. Is that
> intentional?
Hi Stephen,
All the properties in the example are listed as required (except for status, which will be removed in the subsequent patchset).
Do you mean the glink-edge node properties ?
Thanks,
Rakesh Pillai.
^ permalink raw reply [relevance 0%]
* RE: [PATCH v6 0/3] Add support for sc7280 WPSS PIL loading
2021-10-28 22:01 0% ` Stephen Boyd
@ 2021-10-29 6:21 0% ` pillair
0 siblings, 0 replies; 200+ results
From: pillair @ 2021-10-29 6:21 UTC (permalink / raw)
To: 'Stephen Boyd',
agross, bjorn.andersson, mathieu.poirier, ohad, p.zabel, robh+dt
Cc: linux-arm-msm, devicetree, linux-kernel, sibis, mpubbise, kuabhs
> -----Original Message-----
> From: Stephen Boyd <swboyd@chromium.org>
> Sent: Friday, October 29, 2021 3:32 AM
> To: agross@kernel.org; bjorn.andersson@linaro.org;
> mathieu.poirier@linaro.org; ohad@wizery.com; p.zabel@pengutronix.de;
> pillair@codeaurora.org; robh+dt@kernel.org
> Cc: linux-arm-msm@vger.kernel.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; sibis@codeaurora.org; mpubbise@codeaurora.org;
> kuabhs@chromium.org
> Subject: RE: [PATCH v6 0/3] Add support for sc7280 WPSS PIL loading
>
> Quoting pillair@codeaurora.org (2021-10-28 06:08:39)
> >
> >
> > > -----Original Message-----
> > > From: Stephen Boyd <swboyd@chromium.org>
> > > Sent: Friday, October 8, 2021 12:05 AM
> > > To: Rakesh Pillai <pillair@codeaurora.org>; agross@kernel.org;
> > > bjorn.andersson@linaro.org; mathieu.poirier@linaro.org;
> > > ohad@wizery.com; p.zabel@pengutronix.de; robh+dt@kernel.org
> > > Cc: linux-arm-msm@vger.kernel.org; devicetree@vger.kernel.org;
> > > linux- kernel@vger.kernel.org; sibis@codeaurora.org;
> > > mpubbise@codeaurora.org; kuabhs@chromium.org
> > > Subject: Re: [PATCH v6 0/3] Add support for sc7280 WPSS PIL loading
> > >
> > > Quoting Rakesh Pillai (2021-10-03 23:48:50)
> > > > Add support for PIL loading of WPSS co-processor for SC7280 SOCs.
> > > >
> > > > Changes from v4/v5:
> > > > - Add yaml conversion for adsp/cdsp dt-bindings
> > > > - Change clock names in wpss dt-bindings
> > > > - Correct mistake in signed-off enail ID
> > >
> > > Can you keep a running tally here of the full progression of the series?
> > > That helps to look back and make sure we don't make a comment that
> > > has already been made before.
> > >
> > > One more request. Can you add support for 'firmware-name' like there
> > > is in Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt so
> > > that we can install firmware into some namespaced/versioned place
> > > instead of having to put wpss files into /lib/firmware?
> >
> > Hi Stephen,
> > I have posted v7 with the support for firmware-name to be provided in the
> DT entry.
>
> Thanks. I didn't see it in my inbox. No Cc for me?
>
> >
> > > It would also be nice to load a
> > > single firmware file instead of having to split the file into many pieces.
> >
> > This would require lot of changes and lot of code duplication from request
> firmware.
> > Also the base ath11k firmware files have been posted as split files.
> >
>
> Other firmwares have done it so it seems technically possible. So nothing is
> preventing it?
Yes it should be possible.
I can probably add that support and post it as a different patch series, so as to
not club it with the current patch series. Does that sound okay ?
Thanks,
Rakesh Pillai.
^ permalink raw reply [relevance 0%]
* Re: [v8 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider
@ 2021-10-28 23:27 6% ` Bjorn Andersson
2021-11-01 13:39 6% ` okukatla
0 siblings, 1 reply; 200+ results
From: Bjorn Andersson @ 2021-10-28 23:27 UTC (permalink / raw)
To: Odelu Kukatla
Cc: georgi.djakov, evgreen, Andy Gross, Rob Herring, linux-arm-msm,
devicetree, linux-kernel, sboyd, mdtipton, sibis, saravanak,
seansw, elder, linux-pm, linux-arm-msm-owner
On Thu 21 Oct 03:40 PDT 2021, Odelu Kukatla wrote:
> Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280
> SoCs.
>
> Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
> ---
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index d74a4c8..0b55742 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -3687,6 +3687,14 @@
> };
> };
>
> + epss_l3: interconnect@18590000 {
> + compatible = "qcom,sc7280-epss-l3";
> + reg = <0 0x18590000 0 0x1000>;
This series looks like I would expect, with and without per-core dcvs.
But can you please explain why this contradict what Sibi says here:
https://lore.kernel.org/all/1627581885-32165-3-git-send-email-sibis@codeaurora.org/
Regards,
Bjorn
> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
> + clock-names = "xo", "alternate";
> + #interconnect-cells = <1>;
> + };
> +
> cpufreq_hw: cpufreq@18591000 {
> compatible = "qcom,cpufreq-epss";
> reg = <0 0x18591000 0 0x1000>,
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
^ permalink raw reply [relevance 6%]
* RE: [PATCH v6 0/3] Add support for sc7280 WPSS PIL loading
2021-10-28 13:08 0% ` pillair
@ 2021-10-28 22:01 0% ` Stephen Boyd
2021-10-29 6:21 0% ` pillair
0 siblings, 1 reply; 200+ results
From: Stephen Boyd @ 2021-10-28 22:01 UTC (permalink / raw)
To: agross, bjorn.andersson, mathieu.poirier, ohad, p.zabel, pillair,
robh+dt
Cc: linux-arm-msm, devicetree, linux-kernel, sibis, mpubbise, kuabhs
Quoting pillair@codeaurora.org (2021-10-28 06:08:39)
>
>
> > -----Original Message-----
> > From: Stephen Boyd <swboyd@chromium.org>
> > Sent: Friday, October 8, 2021 12:05 AM
> > To: Rakesh Pillai <pillair@codeaurora.org>; agross@kernel.org;
> > bjorn.andersson@linaro.org; mathieu.poirier@linaro.org; ohad@wizery.com;
> > p.zabel@pengutronix.de; robh+dt@kernel.org
> > Cc: linux-arm-msm@vger.kernel.org; devicetree@vger.kernel.org; linux-
> > kernel@vger.kernel.org; sibis@codeaurora.org; mpubbise@codeaurora.org;
> > kuabhs@chromium.org
> > Subject: Re: [PATCH v6 0/3] Add support for sc7280 WPSS PIL loading
> >
> > Quoting Rakesh Pillai (2021-10-03 23:48:50)
> > > Add support for PIL loading of WPSS co-processor for SC7280 SOCs.
> > >
> > > Changes from v4/v5:
> > > - Add yaml conversion for adsp/cdsp dt-bindings
> > > - Change clock names in wpss dt-bindings
> > > - Correct mistake in signed-off enail ID
> >
> > Can you keep a running tally here of the full progression of the series?
> > That helps to look back and make sure we don't make a comment that has
> > already been made before.
> >
> > One more request. Can you add support for 'firmware-name' like there is in
> > Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt so that we
> > can install firmware into some namespaced/versioned place instead of
> > having to put wpss files into /lib/firmware?
>
> Hi Stephen,
> I have posted v7 with the support for firmware-name to be provided in the DT entry.
Thanks. I didn't see it in my inbox. No Cc for me?
>
> > It would also be nice to load a
> > single firmware file instead of having to split the file into many pieces.
>
> This would require lot of changes and lot of code duplication from request firmware.
> Also the base ath11k firmware files have been posted as split files.
>
Other firmwares have done it so it seems technically possible. So
nothing is preventing it?
^ permalink raw reply [relevance 0%]
* RE: [PATCH v6 1/3] dt-bindings: remoteproc: qcom: adsp: Convert binding to YAML
@ 2021-10-28 13:09 0% ` pillair
0 siblings, 0 replies; 200+ results
From: pillair @ 2021-10-28 13:09 UTC (permalink / raw)
To: 'Rob Herring'
Cc: agross, bjorn.andersson, ohad, mathieu.poirier, p.zabel, swboyd,
linux-arm-msm, devicetree, linux-kernel, sibis, mpubbise, kuabhs
> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: Tuesday, October 12, 2021 6:49 AM
> To: Rakesh Pillai <pillair@codeaurora.org>
> Cc: agross@kernel.org; bjorn.andersson@linaro.org; ohad@wizery.com;
> mathieu.poirier@linaro.org; p.zabel@pengutronix.de;
> swboyd@chromium.org; linux-arm-msm@vger.kernel.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> sibis@codeaurora.org; mpubbise@codeaurora.org; kuabhs@chromium.org
> Subject: Re: [PATCH v6 1/3] dt-bindings: remoteproc: qcom: adsp: Convert
> binding to YAML
>
> On Mon, Oct 04, 2021 at 12:18:51PM +0530, Rakesh Pillai wrote:
> > Convert Qualcomm ADSP/CDSP Remoteproc devicetree binding to YAML.
> >
> > Signed-off-by: Rakesh Pillai <pillair@codeaurora.org>
> > ---
> > .../bindings/remoteproc/qcom,hexagon-v56.txt | 140
-----------------
> > .../bindings/remoteproc/qcom,qcs404-cdsp-pil.yaml | 167
> > +++++++++++++++++++++
> > .../bindings/remoteproc/qcom,sdm845-adsp-pil.yaml | 160
> > ++++++++++++++++++++
> > 3 files changed, 327 insertions(+), 140 deletions(-) delete mode
> > 100644
> > Documentation/devicetree/bindings/remoteproc/qcom,hexagon-v56.txt
> > create mode 100644
> > Documentation/devicetree/bindings/remoteproc/qcom,qcs404-cdsp-
> pil.yaml
> > create mode 100644
> > Documentation/devicetree/bindings/remoteproc/qcom,sdm845-adsp-
> pil.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/remoteproc/qcom,hexagon-
> v56.txt
> > b/Documentation/devicetree/bindings/remoteproc/qcom,hexagon-
> v56.txt
> > deleted file mode 100644
> > index 1337a3d..0000000
> > ---
> > a/Documentation/devicetree/bindings/remoteproc/qcom,hexagon-
> v56.txt
> > +++ /dev/null
> > @@ -1,140 +0,0 @@
> > -Qualcomm Technology Inc. Hexagon v56 Peripheral Image Loader
> > -
> > -This document defines the binding for a component that loads and
> > boots firmware -on the Qualcomm Technology Inc. Hexagon v56 core.
> > -
> > -- compatible:
> > - Usage: required
> > - Value type: <string>
> > - Definition: must be one of:
> > - "qcom,qcs404-cdsp-pil",
> > - "qcom,sdm845-adsp-pil"
> > -
> > -- reg:
> > - Usage: required
> > - Value type: <prop-encoded-array>
> > - Definition: must specify the base address and size of the qdsp6ss
> register
> > -
> > -- interrupts-extended:
> > - Usage: required
> > - Value type: <prop-encoded-array>
> > - Definition: must list the watchdog, fatal IRQs ready, handover and
> > - stop-ack IRQs
> > -
> > -- interrupt-names:
> > - Usage: required
> > - Value type: <stringlist>
> > - Definition: must be "wdog", "fatal", "ready", "handover", "stop-ack"
> > -
> > -- clocks:
> > - Usage: required
> > - Value type: <prop-encoded-array>
> > - Definition: List of phandles and clock specifier pairs for the
Hexagon,
> > - per clock-names below.
> > -
> > -- clock-names:
> > - Usage: required for SDM845 ADSP
> > - Value type: <stringlist>
> > - Definition: List of clock input name strings sorted in the same
> > - order as the clocks property. Definition must have
> > - "xo", "sway_cbcr", "lpass_ahbs_aon_cbcr",
> > - "lpass_ahbm_aon_cbcr", "qdsp6ss_xo", "qdsp6ss_sleep"
> > - and "qdsp6ss_core".
> > -
> > -- clock-names:
> > - Usage: required for QCS404 CDSP
> > - Value type: <stringlist>
> > - Definition: List of clock input name strings sorted in the same
> > - order as the clocks property. Definition must have
> > - "xo", "sway", "tbu", "bimc", "ahb_aon", "q6ss_slave",
> > - "q6ss_master", "q6_axim".
> > -
> > -- power-domains:
> > - Usage: required
> > - Value type: <phandle>
> > - Definition: reference to cx power domain node.
> > -
> > -- resets:
> > - Usage: required
> > - Value type: <phandle>
> > - Definition: reference to the list of resets for the Hexagon.
> > -
> > -- reset-names:
> > - Usage: required for SDM845 ADSP
> > - Value type: <stringlist>
> > - Definition: must be "pdc_sync" and "cc_lpass"
> > -
> > -- reset-names:
> > - Usage: required for QCS404 CDSP
> > - Value type: <stringlist>
> > - Definition: must be "restart"
> > -
> > -- qcom,halt-regs:
> > - Usage: required
> > - Value type: <prop-encoded-array>
> > - Definition: a phandle reference to a syscon representing TCSR
> followed
> > - by the offset within syscon for Hexagon halt register.
> > -
> > -- memory-region:
> > - Usage: required
> > - Value type: <phandle>
> > - Definition: reference to the reserved-memory for the firmware
> > -
> > -- qcom,smem-states:
> > - Usage: required
> > - Value type: <phandle>
> > - Definition: reference to the smem state for requesting the Hexagon
> to
> > - shut down
> > -
> > -- qcom,smem-state-names:
> > - Usage: required
> > - Value type: <stringlist>
> > - Definition: must be "stop"
> > -
> > -
> > -= SUBNODES
> > -The adsp node may have an subnode named "glink-edge" that describes
> > the -communication edge, channels and devices related to the Hexagon.
> > -See ../soc/qcom/qcom,glink.txt for details on how to describe these.
> > -
> > -= EXAMPLE
> > -The following example describes the resources needed to boot control
> > the -ADSP, as it is found on SDM845 boards.
> > -
> > - remoteproc@17300000 {
> > - compatible = "qcom,sdm845-adsp-pil";
> > - reg = <0x17300000 0x40c>;
> > -
> > - interrupts-extended = <&intc GIC_SPI 162
> IRQ_TYPE_EDGE_RISING>,
> > - <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
> > - <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
> > - <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
> > - <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
> > - interrupt-names = "wdog", "fatal", "ready",
> > - "handover", "stop-ack";
> > -
> > - clocks = <&rpmhcc RPMH_CXO_CLK>,
> > - <&gcc GCC_LPASS_SWAY_CLK>,
> > - <&lpasscc LPASS_Q6SS_AHBS_AON_CLK>,
> > - <&lpasscc LPASS_Q6SS_AHBM_AON_CLK>,
> > - <&lpasscc LPASS_QDSP6SS_XO_CLK>,
> > - <&lpasscc LPASS_QDSP6SS_SLEEP_CLK>,
> > - <&lpasscc LPASS_QDSP6SS_CORE_CLK>;
> > - clock-names = "xo", "sway_cbcr",
> > - "lpass_ahbs_aon_cbcr",
> > - "lpass_ahbm_aon_cbcr", "qdsp6ss_xo",
> > - "qdsp6ss_sleep", "qdsp6ss_core";
> > -
> > - power-domains = <&rpmhpd SDM845_CX>;
> > -
> > - resets = <&pdc_reset PDC_AUDIO_SYNC_RESET>,
> > - <&aoss_reset AOSS_CC_LPASS_RESTART>;
> > - reset-names = "pdc_sync", "cc_lpass";
> > -
> > - qcom,halt-regs = <&tcsr_mutex_regs 0x22000>;
> > -
> > - memory-region = <&pil_adsp_mem>;
> > -
> > - qcom,smem-states = <&adsp_smp2p_out 0>;
> > - qcom,smem-state-names = "stop";
> > - };
> > diff --git
> > a/Documentation/devicetree/bindings/remoteproc/qcom,qcs404-cdsp-
> pil.ya
> > ml
> > b/Documentation/devicetree/bindings/remoteproc/qcom,qcs404-cdsp-
> pil.ya
> > ml
> > new file mode 100644
> > index 0000000..b698bb7
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/remoteproc/qcom,qcs404-
> cdsp-pi
> > +++ l.yaml
> > @@ -0,0 +1,167 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id:
> > +http://devicetree.org/schemas/remoteproc/qcom,qcs404-cdsp-pil.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Qualcomm QCS404 CDSP Peripheral Image Loader
> > +
> > +maintainers:
> > + - Bjorn Andersson <bjorn.andersson@linaro.org>
> > +
> > +description:
> > + This document defines the binding for a component that loads and
> > +boots firmware
> > + on the Qualcomm Technology Inc. CDSP.
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - qcom,qcs404-cdsp-pil
> > +
> > + reg:
> > + maxItems: 1
> > + description:
> > + The base address and size of the qdsp6ss register
> > +
> > + interrupts-extended:
> > + items:
> > + - description: Watchdog interrupt
> > + - description: Fatal interrupt
> > + - description: Ready interrupt
> > + - description: Handover interrupt
> > + - description: Stop acknowledge interrupt
> > +
> > + interrupt-names:
> > + items:
> > + - const: wdog
> > + - const: fatal
> > + - const: ready
> > + - const: handover
> > + - const: stop-ack
> > +
> > + clocks:
> > + items:
> > + - description: XO clock
> > + - description: SWAY clock
> > + - description: TBU clock
> > + - description: BIMC clock
> > + - description: AHB AON clock
> > + - description: Q6SS SLAVE clock
> > + - description: Q6SS MASTER clock
> > + - description: Q6 AXIM clock
> > +
> > + clock-names:
> > + items:
> > + - const: xo
> > + - const: sway
> > + - const: tbu
> > + - const: bimc
> > + - const: ahb_aon
> > + - const: q6ss_slave
> > + - const: q6ss_master
> > + - const: q6_axim
> > +
> > + power-domains:
> > + items:
> > + - description: CX power domain
> > +
> > + resets:
> > + items:
> > + - description: AOSS restart
> > +
> > + reset-names:
> > + items:
> > + - const: restart
> > +
> > + memory-region:
> > + maxItems: 1
> > + description: Reference to the reserved-memory for the Hexagon
> > + core
> > +
> > + qcom,halt-regs:
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + description:
> > + Phandle reference to a syscon representing TCSR followed by the
> > + three offsets within syscon for q6, modem and nc halt registers.
> > +
> > + qcom,smem-states:
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + description: States used by the AP to signal the Hexagon core
> > + items:
> > + - description: Stop the modem
> > +
> > + qcom,smem-state-names:
> > + $ref: /schemas/types.yaml#/definitions/string
> > + description: The names of the state bits used for SMP2P output
> > + items:
> > + - const: stop
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - interrupts-extended
> > + - interrupt-names
> > + - clocks
> > + - clock-names
> > + - power-domains
> > + - reset
> > + - reset-names
> > + - qcom,halt-regs
> > + - memory-region
> > + - qcom,smem-states
> > + - qcom,smem-state-names
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > + #include <dt-bindings/clock/qcom,gcc-qcs404.h>
> > + #include <dt-bindings/clock/qcom,turingcc-qcs404.h>
> > + remoteproc@b00000 {
> > + compatible = "qcom,qcs404-cdsp-pas";
>
> Doesn't match the schema.
Hi Rob,
I have fixed this and posted v7.
Thanks,
Rakesh Pillai
^ permalink raw reply [relevance 0%]
* RE: [PATCH v6 0/3] Add support for sc7280 WPSS PIL loading
@ 2021-10-28 13:08 0% ` pillair
2021-10-28 22:01 0% ` Stephen Boyd
0 siblings, 1 reply; 200+ results
From: pillair @ 2021-10-28 13:08 UTC (permalink / raw)
To: 'Stephen Boyd',
agross, bjorn.andersson, mathieu.poirier, ohad, p.zabel, robh+dt
Cc: linux-arm-msm, devicetree, linux-kernel, sibis, mpubbise, kuabhs
> -----Original Message-----
> From: Stephen Boyd <swboyd@chromium.org>
> Sent: Friday, October 8, 2021 12:05 AM
> To: Rakesh Pillai <pillair@codeaurora.org>; agross@kernel.org;
> bjorn.andersson@linaro.org; mathieu.poirier@linaro.org; ohad@wizery.com;
> p.zabel@pengutronix.de; robh+dt@kernel.org
> Cc: linux-arm-msm@vger.kernel.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; sibis@codeaurora.org; mpubbise@codeaurora.org;
> kuabhs@chromium.org
> Subject: Re: [PATCH v6 0/3] Add support for sc7280 WPSS PIL loading
>
> Quoting Rakesh Pillai (2021-10-03 23:48:50)
> > Add support for PIL loading of WPSS co-processor for SC7280 SOCs.
> >
> > Changes from v4/v5:
> > - Add yaml conversion for adsp/cdsp dt-bindings
> > - Change clock names in wpss dt-bindings
> > - Correct mistake in signed-off enail ID
>
> Can you keep a running tally here of the full progression of the series?
> That helps to look back and make sure we don't make a comment that has
> already been made before.
>
> One more request. Can you add support for 'firmware-name' like there is in
> Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt so that we
> can install firmware into some namespaced/versioned place instead of
> having to put wpss files into /lib/firmware?
Hi Stephen,
I have posted v7 with the support for firmware-name to be provided in the DT entry.
> It would also be nice to load a
> single firmware file instead of having to split the file into many pieces.
This would require lot of changes and lot of code duplication from request firmware.
Also the base ath11k firmware files have been posted as split files.
Thanks,
Rakesh Pillai
^ permalink raw reply [relevance 0%]
* RE: [PATCH 2/2] remoteproc: qcom: q6v5_wpss: Add support for sc7280 WPSS
2021-10-04 15:29 0% ` Bjorn Andersson
@ 2021-10-28 7:43 0% ` pillair
0 siblings, 0 replies; 200+ results
From: pillair @ 2021-10-28 7:43 UTC (permalink / raw)
To: 'Bjorn Andersson'
Cc: agross, ohad, mathieu.poirier, robh+dt, p.zabel, sibis,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel
> -----Original Message-----
> From: Bjorn Andersson <bjorn.andersson@linaro.org>
> Sent: Monday, October 4, 2021 8:59 PM
> To: Rakesh Pillai <pillair@codeaurora.org>
> Cc: agross@kernel.org; ohad@wizery.com; mathieu.poirier@linaro.org;
> robh+dt@kernel.org; p.zabel@pengutronix.de; sibis@codeaurora.org; linux-
> arm-msm@vger.kernel.org; linux-remoteproc@vger.kernel.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH 2/2] remoteproc: qcom: q6v5_wpss: Add support for
> sc7280 WPSS
>
> On Mon 15 Mar 07:08 CDT 2021, Rakesh Pillai wrote:
>
> >
> >
> > > -----Original Message-----
> > > From: Bjorn Andersson <bjorn.andersson@linaro.org>
> > > Sent: Wednesday, March 10, 2021 10:15 PM
> > > To: Rakesh Pillai <pillair@codeaurora.org>
> > > Cc: agross@kernel.org; ohad@wizery.com; mathieu.poirier@linaro.org;
> > > robh+dt@kernel.org; p.zabel@pengutronix.de; sibis@codeaurora.org;
> > > robh+linux-
> > > arm-msm@vger.kernel.org; linux-remoteproc@vger.kernel.org;
> > > devicetree@vger.kernel.org; linux-kernel@vger.kernel.org
> > > Subject: Re: [PATCH 2/2] remoteproc: qcom: q6v5_wpss: Add support
> > > for
> > > sc7280 WPSS
> > >
> > > On Wed 10 Mar 01:28 CST 2021, Rakesh Pillai wrote:
> > >
> > > > Add support for PIL loading of WPSS processor for SC7280 WPSS boot
> > > > will be requested by the wifi driver and hence disable auto-boot
> > > > for WPSS. Also add a separate shutdown sequence handler for WPSS.
> > > >
> > > > Signed-off-by: Rakesh Pillai <pillair@codeaurora.org>
> > > > ---
> > > > drivers/remoteproc/qcom_q6v5_adsp.c | 77
> > > ++++++++++++++++++++++++++++++++++++-
> > > > 1 file changed, 76 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/remoteproc/qcom_q6v5_adsp.c
> > > b/drivers/remoteproc/qcom_q6v5_adsp.c
> > > > index e024502..dc6b91d 100644
> > > > --- a/drivers/remoteproc/qcom_q6v5_adsp.c
> > > > +++ b/drivers/remoteproc/qcom_q6v5_adsp.c
> > > > @@ -58,6 +58,8 @@ struct adsp_pil_data {
> > > > const char *ssr_name;
> > > > const char *sysmon_name;
> > > > int ssctl_id;
> > > > + bool is_wpss;
> > > > + bool auto_boot;
> > > >
> > > > const char **clk_ids;
> > > > int num_clks;
> > > > @@ -96,8 +98,54 @@ struct qcom_adsp {
> > > > struct qcom_rproc_glink glink_subdev;
> > > > struct qcom_rproc_ssr ssr_subdev;
> > > > struct qcom_sysmon *sysmon;
> > > > +
> > > > + int (*shutdown)(struct qcom_adsp *adsp);
> > > > };
> > > >
> > > > +static int qcom_wpss_shutdown(struct qcom_adsp *adsp) {
> > > > + unsigned long timeout;
> > > > + unsigned int val;
> > > > + int ret;
> > > > +
> > > > + regmap_write(adsp->halt_map, adsp->halt_lpass +
> > > LPASS_HALTREQ_REG, 1);
> > > > +
> > > > + /* Wait for halt ACK from QDSP6 */
> > > > + timeout = jiffies + msecs_to_jiffies(ACK_TIMEOUT);
> > > > + for (;;) {
> > > > + ret = regmap_read(adsp->halt_map,
> > > > + adsp->halt_lpass +
LPASS_HALTACK_REG,
> > > &val);
> > > > + if (ret || val || time_after(jiffies, timeout))
> > > > + break;
> > > > +
> > > > + usleep_range(1000, 1100);
> > > > + }
> > > > +
> > > > + /* Place the WPSS processor into reset */
> > > > + reset_control_assert(adsp->restart);
> > > > + /* wait after asserting subsystem restart from AOSS */
> > > > + usleep_range(100, 105);
> > > > + /* Remove the WPSS reset */
> > > > + reset_control_deassert(adsp->restart);
> > > > +
> > > > + usleep_range(100, 105);
> > > > +
> > > > + regmap_write(adsp->halt_map, adsp->halt_lpass +
> > > LPASS_HALTREQ_REG, 0);
> > > > +
> > > > + /* Wait for halt ACK from QDSP6 */
> > > > + timeout = jiffies + msecs_to_jiffies(ACK_TIMEOUT);
> > > > + for (;;) {
> > > > + ret = regmap_read(adsp->halt_map,
> > > > + adsp->halt_lpass +
LPASS_HALTACK_REG,
> > > &val);
> > > > + if (ret || !val || time_after(jiffies, timeout))
> > > > + break;
> > > > +
> > > > + usleep_range(1000, 1100);
> > > > + }
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > static int qcom_adsp_shutdown(struct qcom_adsp *adsp) {
> > > > unsigned long timeout;
> > > > @@ -270,7 +318,7 @@ static int adsp_stop(struct rproc *rproc)
> > > > if (ret == -ETIMEDOUT)
> > > > dev_err(adsp->dev, "timed out on wait\n");
> > > >
> > > > - ret = qcom_adsp_shutdown(adsp);
> > > > + ret = adsp->shutdown(adsp);
> > > > if (ret)
> > > > dev_err(adsp->dev, "failed to shutdown: %d\n", ret);
> > > >
> > > > @@ -439,6 +487,8 @@ static int adsp_probe(struct platform_device
> > > *pdev)
> > > > dev_err(&pdev->dev, "unable to allocate
remoteproc\n");
> > > > return -ENOMEM;
> > > > }
> > > > +
> > > > + rproc->auto_boot = desc->auto_boot;
> > > > rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);
> > > >
> > > > adsp = (struct qcom_adsp *)rproc->priv; @@ -447,6 +497,11 @@
> > > > static int adsp_probe(struct platform_device
> > > *pdev)
> > > > adsp->info_name = desc->sysmon_name;
> > > > platform_set_drvdata(pdev, adsp);
> > > >
> > > > + if (desc->is_wpss)
> > > > + adsp->shutdown = qcom_wpss_shutdown;
> > > > + else
> > > > + adsp->shutdown = qcom_adsp_shutdown;
> > > > +
> > > > ret = adsp_alloc_memory_region(adsp);
> > > > if (ret)
> > > > goto free_rproc;
> > > > @@ -515,6 +570,8 @@ static const struct adsp_pil_data
> > > > adsp_resource_init
> > > = {
> > > > .ssr_name = "lpass",
> > > > .sysmon_name = "adsp",
> > > > .ssctl_id = 0x14,
> > > > + .is_wpss = false,
> > > > + .auto_boot = true;
> > > > .clk_ids = (const char*[]) {
> > > > "sway_cbcr", "lpass_ahbs_aon_cbcr",
> > > "lpass_ahbm_aon_cbcr",
> > > > "qdsp6ss_xo", "qdsp6ss_sleep", "qdsp6ss_core", NULL
@@ -
> 528,6
> > > > +585,8 @@ static const struct adsp_pil_data cdsp_resource_init
> > > = {
> > > > .ssr_name = "cdsp",
> > > > .sysmon_name = "cdsp",
> > > > .ssctl_id = 0x17,
> > > > + .is_wpss = false,
> > > > + .auto_boot = true;
> > > > .clk_ids = (const char*[]) {
> > > > "sway", "tbu", "bimc", "ahb_aon", "q6ss_slave",
> > > "q6ss_master",
> > > > "q6_axim", NULL
> > > > @@ -535,7 +594,23 @@ static const struct adsp_pil_data
> > > cdsp_resource_init = {
> > > > .num_clks = 7,
> > > > };
> > > >
> > > > +static const struct adsp_pil_data wpss_resource_init = {
> > > > + .crash_reason_smem = 626,
> > > > + .firmware_name = "wpss.mdt",
> > > > + .ssr_name = "wpss",
> > > > + .sysmon_name = "wpss",
> > > > + .ssctl_id = 0x19,
> > > > + .is_wpss = true,
> > > > + .auto_boot = false;
> > >
> > > Why is auto_boot false for the WPSS?
> >
> > Wifi driver will start the remote processor when it comes up. We do
> > not want to load it at the start.
> >
>
> Can you please explain this further?
>
> We've had several cases in the past where functional drivers controls a
> remoteproc instance and makes assumptions about when the remoteproc is
> up or not. I would like to ensure that we don't design ourselves into such
> corner (even though I see that the ath11k code for this was merged a long
> time ago)
>
> Regards,
> Bjorn
>
Hi Bjorn,
Yes, the wpss remoteproc is used by ath11k, where it takes care of starting
the rproc during init.
Ideally the wpss is not supposed to be started until the wifi driver comes
up.
If wifi is started/enabled, the wifi driver can take care of starting the
wpss.
This is the reason behind keeping auto_boot as false for wpss.
Thanks,
Rakesh Pillai
> > > > 2.7.4
> > > >
> >
^ permalink raw reply [relevance 0%]
* [PATCH 5.14 039/151] Revert "arm64: dts: qcom: sc7280: Fixup the cpufreq node"
@ 2021-10-11 13:45 6% ` Greg Kroah-Hartman
0 siblings, 0 replies; 200+ results
From: Greg Kroah-Hartman @ 2021-10-11 13:45 UTC (permalink / raw)
To: linux-kernel
Cc: Greg Kroah-Hartman, stable, Matthias Kaehlcke, Sibi Sankar,
Stephen Boyd, Douglas Anderson, Bjorn Andersson, Sasha Levin
From: Douglas Anderson <dianders@chromium.org>
[ Upstream commit a48c730a4e0bf480bcde12d795a9cd6f9ef14d1e ]
This reverts commit 11e03d692101e484df9322f892a8b6e111a82bfd.
As per discussion [1] the patch shouldn't have landed. Let's revert.
[1] https://lore.kernel.org/r/fde7bac239f796b039b9be58b391fb77@codeaurora.org/
Fixes: 11e03d692101 ("arm64: dts: qcom: sc7280: Fixup the cpufreq node")
Reported-by: Matthias Kaehlcke <mka@chromium.org>
Cc: Sibi Sankar <sibis@codeaurora.org>
Cc: Matthias Kaehlcke <mka@chromium.org>
Cc: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210907121220.1.I08460f490473b70de0d768db45f030a4d5c17828@changeid
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index c08f07410699..188c5768a55a 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -1437,9 +1437,9 @@
cpufreq_hw: cpufreq@18591000 {
compatible = "qcom,cpufreq-epss";
- reg = <0 0x18591100 0 0x900>,
- <0 0x18592100 0 0x900>,
- <0 0x18593100 0 0x900>;
+ reg = <0 0x18591000 0 0x1000>,
+ <0 0x18592000 0 0x1000>,
+ <0 0x18593000 0 0x1000>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
clock-names = "xo", "alternate";
#freq-domain-cells = <1>;
--
2.33.0
^ permalink raw reply related [relevance 6%]
* Re: [PATCH v5 00/10] Add Modem support on SC7280 SoCs
2021-09-17 13:55 17% [PATCH v5 00/10] Add Modem support on SC7280 SoCs Sibi Sankar
` (10 preceding siblings ...)
2021-09-27 22:56 0% ` (subset) [PATCH v5 00/10] Add Modem support on SC7280 SoCs Bjorn Andersson
@ 2021-10-08 12:53 0% ` Will Deacon
11 siblings, 0 replies; 200+ results
From: Will Deacon @ 2021-10-08 12:53 UTC (permalink / raw)
To: bjorn.andersson, Sibi Sankar, swboyd, mka, saiprakash.ranjan, robh+dt
Cc: catalin.marinas, kernel-team, Will Deacon, dianders,
robin.murphy, joro, linux-arm-kernel, devicetree, linux-arm-msm,
linux-kernel, ohad, evgreen, p.zabel, agross, linux-remoteproc,
mathieu.poirier
On Fri, 17 Sep 2021 19:25:25 +0530, Sibi Sankar wrote:
> This patch series adds support for booting the Modem Q6 DSP found on
> Qualcomm's SC7280 SoCs.
>
> Depends on:
> qmp_send: https://patchwork.kernel.org/project/linux-arm-msm/cover/1630420228-31075-1-git-send-email-deesin@codeaurora.org/
> rproc qmp: https://patchwork.kernel.org/project/linux-arm-msm/cover/1631800770-371-1-git-send-email-sibis@codeaurora.org/
>
> [...]
Applied SMMU patch to will (for-joerg/arm-smmu/updates), thanks!
[04/10] iommu/arm-smmu-qcom: Request direct mapping for modem device
https://git.kernel.org/will/c/e37f1fe43324
Cheers,
--
Will
https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev
^ permalink raw reply [relevance 0%]
* Re: [PATCH v5 04/10] iommu/arm-smmu-qcom: Request direct mapping for modem device
2021-09-17 13:55 19% ` [PATCH v5 04/10] iommu/arm-smmu-qcom: Request direct mapping for modem device Sibi Sankar
@ 2021-10-07 20:08 6% ` Sibi Sankar
0 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-10-07 20:08 UTC (permalink / raw)
To: will
Cc: bjorn.andersson, robh+dt, saiprakash.ranjan, swboyd, mka, ohad,
agross, mathieu.poirier, robin.murphy, joro, p.zabel,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
linux-arm-kernel, evgreen, dianders, sibis=codeaurora.org
Hey Will,
Can you pick this patch up, the rest of
the series is now in linux-next.
On 2021-09-17 19:25, Sibi Sankar wrote:
> The SID configuration requirement for Modem on SC7280 is similar to the
> ones found on SC7180/SDM845 SoCs. So, add the SC7280 modem compatible
> to
> the list to defer the programming of the modem SIDs to the kernel.
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> Reviewed-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> Reviewed-by: Stephen Boyd <swboyd@chromium.org>
> ---
> drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> index 55690af1b25d..3b9b46fca0b3 100644
> --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> @@ -231,6 +231,7 @@ static const struct of_device_id
> qcom_smmu_client_of_match[] __maybe_unused = {
> { .compatible = "qcom,sc7180-mdss" },
> { .compatible = "qcom,sc7180-mss-pil" },
> { .compatible = "qcom,sc7280-mdss" },
> + { .compatible = "qcom,sc7280-mss-pil" },
> { .compatible = "qcom,sc8180x-mdss" },
> { .compatible = "qcom,sdm845-mdss" },
> { .compatible = "qcom,sdm845-mss-pil" },
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply [relevance 6%]
* RE: [PATCH v6 2/3] dt-bindings: remoteproc: qcom: Add SC7280 WPSS support
@ 2021-10-06 16:56 0% ` pillair
0 siblings, 0 replies; 200+ results
From: pillair @ 2021-10-06 16:56 UTC (permalink / raw)
To: 'Stephen Boyd', 'Rob Herring'
Cc: mathieu.poirier, p.zabel, devicetree, bjorn.andersson,
linux-kernel, robh+dt, sibis, kuabhs, agross, ohad,
linux-arm-msm, mpubbise
> -----Original Message-----
> From: Stephen Boyd <swboyd@chromium.org>
> Sent: Wednesday, October 6, 2021 12:40 PM
> To: Rob Herring <robh@kernel.org>; pillair@codeaurora.org
> Cc: mathieu.poirier@linaro.org; p.zabel@pengutronix.de;
> devicetree@vger.kernel.org; bjorn.andersson@linaro.org; linux-
> kernel@vger.kernel.org; robh+dt@kernel.org; sibis@codeaurora.org;
> kuabhs@chromium.org; agross@kernel.org; ohad@wizery.com; linux-arm-
> msm@vger.kernel.org; mpubbise@codeaurora.org
> Subject: RE: [PATCH v6 2/3] dt-bindings: remoteproc: qcom: Add SC7280
> WPSS support
>
> Quoting pillair@codeaurora.org (2021-10-05 22:09:18)
> >
> > >
> > > If you already ran 'make dt_binding_check' and didn't see the above
> > error(s),
> > > then make sure 'yamllint' is installed and dt-schema is up to
> > > date:
> > >
> > > pip3 install dtschema --upgrade
> > >
> > > Please check and re-submit.
> >
> >
> > I have updated the dtschema (2021.7) and still not seeing these
> > errors. I will fix the errors mentioned in this log though.
> > Is there any other flag/setting, which is to be enabled ?
> >
>
> I have dtschema-2021.10 installed.
Thanks Stephen. Yes, my dtschema, for some reason, was not getting updated.
After upgrading it to 2021.10, I was able to see the same errors.
I will send out the next patchset with these errors fixed.
Thanks,
Rakesh Pillai.
^ permalink raw reply [relevance 0%]
* RE: [PATCH v6 2/3] dt-bindings: remoteproc: qcom: Add SC7280 WPSS support
@ 2021-10-06 5:09 0% ` pillair
0 siblings, 1 reply; 200+ results
From: pillair @ 2021-10-06 5:09 UTC (permalink / raw)
To: 'Rob Herring'
Cc: mathieu.poirier, swboyd, p.zabel, devicetree, bjorn.andersson,
linux-kernel, robh+dt, sibis, kuabhs, agross, ohad,
linux-arm-msm, mpubbise
> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: Monday, October 4, 2021 5:51 PM
> To: Rakesh Pillai <pillair@codeaurora.org>
> Cc: mathieu.poirier@linaro.org; swboyd@chromium.org;
> p.zabel@pengutronix.de; devicetree@vger.kernel.org;
> bjorn.andersson@linaro.org; linux-kernel@vger.kernel.org;
> robh+dt@kernel.org; sibis@codeaurora.org; kuabhs@chromium.org;
> agross@kernel.org; ohad@wizery.com; linux-arm-msm@vger.kernel.org;
> mpubbise@codeaurora.org
> Subject: Re: [PATCH v6 2/3] dt-bindings: remoteproc: qcom: Add SC7280
> WPSS support
>
> On Mon, 04 Oct 2021 12:18:52 +0530, Rakesh Pillai wrote:
> > Add WPSS PIL loading support for SC7280 SoCs.
> >
> > Signed-off-by: Rakesh Pillai <pillair@codeaurora.org>
> > ---
> > .../bindings/remoteproc/qcom,sc7280-wpss-pil.yaml | 196
> > +++++++++++++++++++++
> > 1 file changed, 196 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/remoteproc/qcom,sc7280-wpss-
> pil.yaml
> >
>
> My bot found errors running 'make DT_CHECKER_FLAGS=-m
> dt_binding_check'
> on your patch (DT_CHECKER_FLAGS is new in v5.13):
>
> yamllint warnings/errors:
>
> dtschema/dtc warnings/errors:
> /builds/robherring/linux-dt-
> review/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-
> wpss-pil.yaml: properties:interrupts: 'oneOf' conditional failed, one must
be
> fixed:
> [{'description': 'Watchdog interrupt'}, {'description': 'Fatal
interrupt'},
> {'description': 'Ready interrupt'}, {'description': 'Handover interrupt'},
> {'description': 'Stop acknowledge interrupt'}, {'description': 'Shutdown
> acknowledge interrupt'}] is too long
> [{'description': 'Watchdog interrupt'}, {'description': 'Fatal
interrupt'},
> {'description': 'Ready interrupt'}, {'description': 'Handover interrupt'},
> {'description': 'Stop acknowledge interrupt'}, {'description': 'Shutdown
> acknowledge interrupt'}] is too short
> False schema does not allow 6
> 1 was expected
> 6 is greater than the maximum of 2
> 6 is greater than the maximum of 3
> 6 is greater than the maximum of 4
> 6 is greater than the maximum of 5
> hint: "minItems" is only needed if less than the "items" list length
> from schema $id: http://devicetree.org/meta-schemas/items.yaml#
> /builds/robherring/linux-dt-
> review/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-
> wpss-pil.yaml: properties:interrupt-names: 'oneOf' conditional failed, one
> must be fixed:
> [{'const': 'wdog'}, {'const': 'fatal'}, {'const': 'ready'},
{'const':
> 'handover'}, {'const': 'stop-ack'}, {'const': 'shutdown-ack'}] is too long
> [{'const': 'wdog'}, {'const': 'fatal'}, {'const': 'ready'},
{'const':
> 'handover'}, {'const': 'stop-ack'}, {'const': 'shutdown-ack'}] is too
short
> False schema does not allow 6
> 1 was expected
> 6 is greater than the maximum of 2
> 6 is greater than the maximum of 3
> 6 is greater than the maximum of 4
> 6 is greater than the maximum of 5
> hint: "minItems" is only needed if less than the "items" list length
> from schema $id: http://devicetree.org/meta-schemas/items.yaml#
> /builds/robherring/linux-dt-
> review/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-
> wpss-pil.yaml: properties:clocks: 'oneOf' conditional failed, one must be
> fixed:
> [{'description': 'GCC WPSS AHB BDG Master clock'}, {'description':
> 'GCC WPSS AHB clock'}, {'description': 'GCC WPSS RSCP clock'},
{'description':
> 'XO clock'}] is too long
> [{'description': 'GCC WPSS AHB BDG Master clock'}, {'description':
> 'GCC WPSS AHB clock'}, {'description': 'GCC WPSS RSCP clock'},
{'description':
> 'XO clock'}] is too short
> False schema does not allow 4
> 1 was expected
> 4 is greater than the maximum of 2
> 4 is greater than the maximum of 3
> hint: "minItems" is only needed if less than the "items" list length
> from schema $id: http://devicetree.org/meta-schemas/items.yaml#
> /builds/robherring/linux-dt-
> review/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-
> wpss-pil.yaml: properties:clock-names: 'oneOf' conditional failed, one
must
> be fixed:
> [{'const': 'ahb_bdg'}, {'const': 'ahb'}, {'const': 'rscp'},
{'const': 'xo'}] is
> too long
> [{'const': 'ahb_bdg'}, {'const': 'ahb'}, {'const': 'rscp'},
{'const': 'xo'}] is
> too short
> False schema does not allow 4
> 1 was expected
> 4 is greater than the maximum of 2
> 4 is greater than the maximum of 3
> hint: "minItems" is only needed if less than the "items" list length
> from schema $id: http://devicetree.org/meta-schemas/items.yaml#
> /builds/robherring/linux-dt-
> review/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-
> wpss-pil.yaml: properties:power-domains: 'oneOf' conditional failed, one
> must be fixed:
> [{'description': 'CX power domain'}, {'description': 'MX power
> domain'}] is too long
> [{'description': 'CX power domain'}, {'description': 'MX power
> domain'}] is too short
> False schema does not allow 2
> 1 was expected
> hint: "minItems" is only needed if less than the "items" list length
> from schema $id: http://devicetree.org/meta-schemas/items.yaml#
> /builds/robherring/linux-dt-
> review/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-
> wpss-pil.yaml: properties:power-domain-names: 'oneOf' conditional failed,
> one must be fixed:
> [{'const': 'cx'}, {'const': 'mx'}] is too long
> [{'const': 'cx'}, {'const': 'mx'}] is too short
> False schema does not allow 2
> 1 was expected
> hint: "minItems" is only needed if less than the "items" list length
> from schema $id: http://devicetree.org/meta-schemas/items.yaml#
> /builds/robherring/linux-dt-
> review/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-
> wpss-pil.yaml: properties:resets: 'oneOf' conditional failed, one must be
> fixed:
> [{'description': 'AOSS restart'}, {'description': 'PDC SYNC'}] is
too long
> [{'description': 'AOSS restart'}, {'description': 'PDC SYNC'}] is
too short
> False schema does not allow 2
> 1 was expected
> hint: "minItems" is only needed if less than the "items" list length
> from schema $id: http://devicetree.org/meta-schemas/items.yaml#
> /builds/robherring/linux-dt-
> review/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-
> wpss-pil.yaml: properties:reset-names: 'oneOf' conditional failed, one
must
> be fixed:
> [{'const': 'restart'}, {'const': 'pdc_sync'}] is too long
> [{'const': 'restart'}, {'const': 'pdc_sync'}] is too short
> False schema does not allow 2
> 1 was expected
> hint: "minItems" is only needed if less than the "items" list length
> from schema $id: http://devicetree.org/meta-schemas/items.yaml#
> /builds/robherring/linux-dt-
> review/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-
> wpss-pil.yaml: ignoring, error in schema: properties: interrupts
> warning: no schema found in file:
> ./Documentation/devicetree/bindings/remoteproc/qcom,sc7280-wpss-
> pil.yaml
> Documentation/devicetree/bindings/remoteproc/qcom,sc7280-wpss-
> pil.example.dt.yaml:0:0: /example-0/remoteproc@8a00000: failed to match
> any schema with compatible: ['qcom,sc7280-wpss-pil']
>
> doc reference errors (make refcheckdocs):
>
> See https://patchwork.ozlabs.org/patch/1535950
>
> This check can fail if there are any dependencies. The base for a patch
series
> is generally the most recent rc1.
>
> If you already ran 'make dt_binding_check' and didn't see the above
error(s),
> then make sure 'yamllint' is installed and dt-schema is up to
> date:
>
> pip3 install dtschema --upgrade
>
> Please check and re-submit.
I have updated the dtschema (2021.7) and still not seeing these errors. I
will fix the errors mentioned in this log though.
Is there any other flag/setting, which is to be enabled ?
Thanks,
Rakesh Pillai.
^ permalink raw reply [relevance 0%]
* Re: [PATCH 2/2] remoteproc: qcom: q6v5_wpss: Add support for sc7280 WPSS
@ 2021-10-04 15:29 0% ` Bjorn Andersson
2021-10-28 7:43 0% ` pillair
0 siblings, 1 reply; 200+ results
From: Bjorn Andersson @ 2021-10-04 15:29 UTC (permalink / raw)
To: Rakesh Pillai
Cc: agross, ohad, mathieu.poirier, robh+dt, p.zabel, sibis,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel
On Mon 15 Mar 07:08 CDT 2021, Rakesh Pillai wrote:
>
>
> > -----Original Message-----
> > From: Bjorn Andersson <bjorn.andersson@linaro.org>
> > Sent: Wednesday, March 10, 2021 10:15 PM
> > To: Rakesh Pillai <pillair@codeaurora.org>
> > Cc: agross@kernel.org; ohad@wizery.com; mathieu.poirier@linaro.org;
> > robh+dt@kernel.org; p.zabel@pengutronix.de; sibis@codeaurora.org; linux-
> > arm-msm@vger.kernel.org; linux-remoteproc@vger.kernel.org;
> > devicetree@vger.kernel.org; linux-kernel@vger.kernel.org
> > Subject: Re: [PATCH 2/2] remoteproc: qcom: q6v5_wpss: Add support for
> > sc7280 WPSS
> >
> > On Wed 10 Mar 01:28 CST 2021, Rakesh Pillai wrote:
> >
> > > Add support for PIL loading of WPSS processor for SC7280
> > > WPSS boot will be requested by the wifi driver and hence
> > > disable auto-boot for WPSS. Also add a separate shutdown
> > > sequence handler for WPSS.
> > >
> > > Signed-off-by: Rakesh Pillai <pillair@codeaurora.org>
> > > ---
> > > drivers/remoteproc/qcom_q6v5_adsp.c | 77
> > ++++++++++++++++++++++++++++++++++++-
> > > 1 file changed, 76 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/remoteproc/qcom_q6v5_adsp.c
> > b/drivers/remoteproc/qcom_q6v5_adsp.c
> > > index e024502..dc6b91d 100644
> > > --- a/drivers/remoteproc/qcom_q6v5_adsp.c
> > > +++ b/drivers/remoteproc/qcom_q6v5_adsp.c
> > > @@ -58,6 +58,8 @@ struct adsp_pil_data {
> > > const char *ssr_name;
> > > const char *sysmon_name;
> > > int ssctl_id;
> > > + bool is_wpss;
> > > + bool auto_boot;
> > >
> > > const char **clk_ids;
> > > int num_clks;
> > > @@ -96,8 +98,54 @@ struct qcom_adsp {
> > > struct qcom_rproc_glink glink_subdev;
> > > struct qcom_rproc_ssr ssr_subdev;
> > > struct qcom_sysmon *sysmon;
> > > +
> > > + int (*shutdown)(struct qcom_adsp *adsp);
> > > };
> > >
> > > +static int qcom_wpss_shutdown(struct qcom_adsp *adsp)
> > > +{
> > > + unsigned long timeout;
> > > + unsigned int val;
> > > + int ret;
> > > +
> > > + regmap_write(adsp->halt_map, adsp->halt_lpass +
> > LPASS_HALTREQ_REG, 1);
> > > +
> > > + /* Wait for halt ACK from QDSP6 */
> > > + timeout = jiffies + msecs_to_jiffies(ACK_TIMEOUT);
> > > + for (;;) {
> > > + ret = regmap_read(adsp->halt_map,
> > > + adsp->halt_lpass + LPASS_HALTACK_REG,
> > &val);
> > > + if (ret || val || time_after(jiffies, timeout))
> > > + break;
> > > +
> > > + usleep_range(1000, 1100);
> > > + }
> > > +
> > > + /* Place the WPSS processor into reset */
> > > + reset_control_assert(adsp->restart);
> > > + /* wait after asserting subsystem restart from AOSS */
> > > + usleep_range(100, 105);
> > > + /* Remove the WPSS reset */
> > > + reset_control_deassert(adsp->restart);
> > > +
> > > + usleep_range(100, 105);
> > > +
> > > + regmap_write(adsp->halt_map, adsp->halt_lpass +
> > LPASS_HALTREQ_REG, 0);
> > > +
> > > + /* Wait for halt ACK from QDSP6 */
> > > + timeout = jiffies + msecs_to_jiffies(ACK_TIMEOUT);
> > > + for (;;) {
> > > + ret = regmap_read(adsp->halt_map,
> > > + adsp->halt_lpass + LPASS_HALTACK_REG,
> > &val);
> > > + if (ret || !val || time_after(jiffies, timeout))
> > > + break;
> > > +
> > > + usleep_range(1000, 1100);
> > > + }
> > > +
> > > + return 0;
> > > +}
> > > +
> > > static int qcom_adsp_shutdown(struct qcom_adsp *adsp)
> > > {
> > > unsigned long timeout;
> > > @@ -270,7 +318,7 @@ static int adsp_stop(struct rproc *rproc)
> > > if (ret == -ETIMEDOUT)
> > > dev_err(adsp->dev, "timed out on wait\n");
> > >
> > > - ret = qcom_adsp_shutdown(adsp);
> > > + ret = adsp->shutdown(adsp);
> > > if (ret)
> > > dev_err(adsp->dev, "failed to shutdown: %d\n", ret);
> > >
> > > @@ -439,6 +487,8 @@ static int adsp_probe(struct platform_device
> > *pdev)
> > > dev_err(&pdev->dev, "unable to allocate remoteproc\n");
> > > return -ENOMEM;
> > > }
> > > +
> > > + rproc->auto_boot = desc->auto_boot;
> > > rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);
> > >
> > > adsp = (struct qcom_adsp *)rproc->priv;
> > > @@ -447,6 +497,11 @@ static int adsp_probe(struct platform_device
> > *pdev)
> > > adsp->info_name = desc->sysmon_name;
> > > platform_set_drvdata(pdev, adsp);
> > >
> > > + if (desc->is_wpss)
> > > + adsp->shutdown = qcom_wpss_shutdown;
> > > + else
> > > + adsp->shutdown = qcom_adsp_shutdown;
> > > +
> > > ret = adsp_alloc_memory_region(adsp);
> > > if (ret)
> > > goto free_rproc;
> > > @@ -515,6 +570,8 @@ static const struct adsp_pil_data adsp_resource_init
> > = {
> > > .ssr_name = "lpass",
> > > .sysmon_name = "adsp",
> > > .ssctl_id = 0x14,
> > > + .is_wpss = false,
> > > + .auto_boot = true;
> > > .clk_ids = (const char*[]) {
> > > "sway_cbcr", "lpass_ahbs_aon_cbcr",
> > "lpass_ahbm_aon_cbcr",
> > > "qdsp6ss_xo", "qdsp6ss_sleep", "qdsp6ss_core", NULL
> > > @@ -528,6 +585,8 @@ static const struct adsp_pil_data cdsp_resource_init
> > = {
> > > .ssr_name = "cdsp",
> > > .sysmon_name = "cdsp",
> > > .ssctl_id = 0x17,
> > > + .is_wpss = false,
> > > + .auto_boot = true;
> > > .clk_ids = (const char*[]) {
> > > "sway", "tbu", "bimc", "ahb_aon", "q6ss_slave",
> > "q6ss_master",
> > > "q6_axim", NULL
> > > @@ -535,7 +594,23 @@ static const struct adsp_pil_data
> > cdsp_resource_init = {
> > > .num_clks = 7,
> > > };
> > >
> > > +static const struct adsp_pil_data wpss_resource_init = {
> > > + .crash_reason_smem = 626,
> > > + .firmware_name = "wpss.mdt",
> > > + .ssr_name = "wpss",
> > > + .sysmon_name = "wpss",
> > > + .ssctl_id = 0x19,
> > > + .is_wpss = true,
> > > + .auto_boot = false;
> >
> > Why is auto_boot false for the WPSS?
>
> Wifi driver will start the remote processor when it comes up. We do not want
> to load it at the start.
>
Can you please explain this further?
We've had several cases in the past where functional drivers controls
a remoteproc instance and makes assumptions about when the remoteproc is
up or not. I would like to ensure that we don't design ourselves into
such corner (even though I see that the ath11k code for this was merged
a long time ago)
Regards,
Bjorn
> >
> > > + .clk_ids = (const char*[]) {
> > > + "gcc_wpss_ahb_bdg_mst_clk", "gcc_wpss_ahb_clk",
> > > + "gcc_wpss_rscp_clk", NULL
> > > + },
> > > + .num_clks = 3,
> > > +};
> > > +
> > > static const struct of_device_id adsp_of_match[] = {
> > > + { .compatible = "qcom,sc7280-wpss-pil", .data = &wpss_resource_init
> > },
> >
> > Nit. Please keep things like this sorted alphabetically.
>
> Will fix this in the next patchset.
>
> Thanks,
> Rakesh
>
> >
> > Regards,
> > Bjorn
> >
> > > { .compatible = "qcom,qcs404-cdsp-pil", .data = &cdsp_resource_init
> > },
> > > { .compatible = "qcom,sdm845-adsp-pil", .data =
> > &adsp_resource_init },
> > > { },
> > > --
> > > 2.7.4
> > >
>
^ permalink raw reply [relevance 0%]
* RE: [PATCH v4] arm64: dts: qcom: sc7280: Add WPSS remoteproc node
@ 2021-10-04 9:33 0% ` pillair
0 siblings, 0 replies; 200+ results
From: pillair @ 2021-10-04 9:33 UTC (permalink / raw)
To: agross, bjorn.andersson, robh+dt, swboyd
Cc: linux-arm-msm, devicetree, linux-kernel, sibis, mpubbise, kuabhs
> -----Original Message-----
> From: Rakesh Pillai <pillair@codeaurora.org>
> Sent: Friday, September 17, 2021 4:05 PM
> To: agross@kernel.org; bjorn.andersson@linaro.org; robh+dt@kernel.org;
> swboyd@chromium.org
> Cc: linux-arm-msm@vger.kernel.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; sibis@codeaurora.org; mpubbise@codeaurora.org;
> kuabhs@chromium.org; Rakesh Pillai <pillair@codeaurora.org>
> Subject: [PATCH v4] arm64: dts: qcom: sc7280: Add WPSS remoteproc node
>
> Add the WPSS remoteproc node in dts for
> PIL loading.
>
> Signed-off-by: Rakesh Pillai <pillair@codeaurora.org>
> ---
> Changes from v3:
> - Fix the qcom,halt-regs
> ---
> arch/arm64/boot/dts/qcom/sc7280-idp.dts | 4 +++
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 63
> +++++++++++++++++++++++++++++++++
> 2 files changed, 67 insertions(+)
>
I have sent v5 after rebasing to latest linux-next.
Thanks,
Rakesh Pillai
^ permalink raw reply [relevance 0%]
* RE: [PATCH v5 0/3] Add support for sc7280 WPSS PIL loading
@ 2021-10-03 3:07 0% ` pillair
0 siblings, 0 replies; 200+ results
From: pillair @ 2021-10-03 3:07 UTC (permalink / raw)
To: agross, bjorn.andersson, ohad, mathieu.poirier, robh+dt, p.zabel
Cc: swboyd, linux-arm-msm, devicetree, linux-kernel, sibis, mpubbise, kuabhs
Please ignore v5 due to a mistake in signed-off.
I will send v6 after correcting it.
Thanks,
Rakesh Pillai
> -----Original Message-----
> From: Rakesh Pillai <pillair@codeaurora.org>
> Sent: Sunday, October 3, 2021 8:34 AM
> To: agross@kernel.org; bjorn.andersson@linaro.org; ohad@wizery.com;
> mathieu.poirier@linaro.org; robh+dt@kernel.org; p.zabel@pengutronix.de
> Cc: swboyd@chromium.org; linux-arm-msm@vger.kernel.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> sibis@codeaurora.org; mpubbise@codeaurora.org; kuabhs@chromium.org;
> Rakesh Pillai <pillair@codeaurora.org>
> Subject: [PATCH v5 0/3] Add support for sc7280 WPSS PIL loading
>
> Add support for PIL loading of WPSS co-processor for SC7280 SOCs.
>
> Changes from v4:
> - Add yaml conversion for adsp/cdsp dt-bindings
> - Change clock names in wpss dt-bindings
>
> Rakesh Pillai (3):
> dt-bindings: remoteproc: qcom: adsp: Convert binding to YAML
> dt-bindings: remoteproc: qcom: Add SC7280 WPSS support
> remoteproc: qcom: q6v5_wpss: Add support for sc7280 WPSS
>
> .../bindings/remoteproc/qcom,hexagon-v56.txt | 140 --------------
> .../bindings/remoteproc/qcom,qcs404-cdsp-pil.yaml | 167
> ++++++++++++++++ .../bindings/remoteproc/qcom,sc7280-wpss-pil.yaml |
> 196 +++++++++++++++++++ .../bindings/remoteproc/qcom,sdm845-adsp-
> pil.yaml | 160 ++++++++++++++++
> drivers/remoteproc/qcom_q6v5_adsp.c | 209
> +++++++++++++++++++--
> 5 files changed, 717 insertions(+), 155 deletions(-) delete mode 100644
> Documentation/devicetree/bindings/remoteproc/qcom,hexagon-v56.txt
> create mode 100644
> Documentation/devicetree/bindings/remoteproc/qcom,qcs404-cdsp-
> pil.yaml
> create mode 100644
> Documentation/devicetree/bindings/remoteproc/qcom,sc7280-wpss-
> pil.yaml
> create mode 100644
> Documentation/devicetree/bindings/remoteproc/qcom,sdm845-adsp-
> pil.yaml
>
> --
> 2.7.4
^ permalink raw reply [relevance 0%]
* Re: (subset) [PATCH v5 00/10] Add Modem support on SC7280 SoCs
2021-09-17 13:55 17% [PATCH v5 00/10] Add Modem support on SC7280 SoCs Sibi Sankar
` (9 preceding siblings ...)
2021-09-17 13:55 17% ` [PATCH v5 10/10] arm64: dts: qcom: sc7280: Update " Sibi Sankar
@ 2021-09-27 22:56 0% ` Bjorn Andersson
2021-10-08 12:53 0% ` Will Deacon
11 siblings, 0 replies; 200+ results
From: Bjorn Andersson @ 2021-09-27 22:56 UTC (permalink / raw)
To: robh+dt, mka, Sibi Sankar, saiprakash.ranjan, will, swboyd
Cc: robin.murphy, linux-kernel, joro, linux-arm-kernel,
linux-remoteproc, linux-arm-msm, evgreen, dianders, p.zabel,
mathieu.poirier, ohad, devicetree, agross
On Fri, 17 Sep 2021 19:25:25 +0530, Sibi Sankar wrote:
> This patch series adds support for booting the Modem Q6 DSP found on
> Qualcomm's SC7280 SoCs.
>
> Depends on:
> qmp_send: https://patchwork.kernel.org/project/linux-arm-msm/cover/1630420228-31075-1-git-send-email-deesin@codeaurora.org/
> rproc qmp: https://patchwork.kernel.org/project/linux-arm-msm/cover/1631800770-371-1-git-send-email-sibis@codeaurora.org/
>
> [...]
Applied, thanks!
[06/10] arm64: dts: qcom: sc7280: Update reserved memory map
commit: eca7d3a366b3ab9f31e142c13a43c5b0f94a920d
[07/10] arm64: dts: qcom: sc7280: Add/Delete/Update reserved memory nodes
commit: f83146890172da67443c7b80e529fd1781046c65
[08/10] arm64: dts: qcom: sc7280: Add nodes to boot modem
commit: dddf4b0621d61b8203d500ef85a853626ff42432
[09/10] arm64: dts: qcom: sc7280: Add Q6V5 MSS node
commit: 4882cafb99c2b004b9773631fb00ca6d96dc0124
[10/10] arm64: dts: qcom: sc7280: Update Q6V5 MSS node
commit: 0025fac17b313cca5c640dd57cbf38d01ce10b27
Best regards,
--
Bjorn Andersson <bjorn.andersson@linaro.org>
^ permalink raw reply [relevance 0%]
* RE: [PATCH v4 1/2] dt-bindings: remoteproc: qcom: Add SC7280 WPSS support
@ 2021-09-23 17:12 0% ` pillair
0 siblings, 0 replies; 200+ results
From: pillair @ 2021-09-23 17:12 UTC (permalink / raw)
To: 'Rob Herring'
Cc: 'Gross, Andy', 'Bjorn Andersson',
'Ohad Ben-Cohen', 'Mathieu Poirier',
'Philipp Zabel', 'Stephen Boyd',
'linux-arm-msm',
devicetree, linux-kernel, 'sibis',
mpubbise, kuabhs
> -----Original Message-----
> From: Rob Herring <robh+dt@kernel.org>
> Sent: Wednesday, September 22, 2021 10:59 PM
> To: Rakesh Pillai <pillair@codeaurora.org>
> Cc: Gross, Andy <agross@kernel.org>; Bjorn Andersson
> <bjorn.andersson@linaro.org>; Ohad Ben-Cohen <ohad@wizery.com>;
> Mathieu Poirier <mathieu.poirier@linaro.org>; Philipp Zabel
> <p.zabel@pengutronix.de>; Stephen Boyd <swboyd@chromium.org>; linux-
> arm-msm <linux-arm-msm@vger.kernel.org>; devicetree@vger.kernel.org;
> linux-kernel@vger.kernel.org; sibis <sibis@codeaurora.org>;
> mpubbise@codeaurora.org; kuabhs@chromium.org
> Subject: Re: [PATCH v4 1/2] dt-bindings: remoteproc: qcom: Add SC7280
> WPSS support
>
> On Fri, Sep 17, 2021 at 5:36 AM Rakesh Pillai <pillair@codeaurora.org> wrote:
> >
> > Add WPSS PIL loading support for SC7280 SoCs.
> >
> > Signed-off-by: Rakesh Pillai <pillair@codeaurora.org>
> > ---
> > .../bindings/remoteproc/qcom,sc7280-wpss-pil.yaml | 198
> > +++++++++++++++++++++
> > 1 file changed, 198 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/remoteproc/qcom,sc7280-wpss-
> pil.yaml
>
> What happened to converting the existing binding? Given you already did
> that, please don't drop it.
Hi Rob,
Thanks for the review.
Sure, let me post v5 with other comments on this patch-series addressed.
I will also include the yaml conversion for existing dt-bindings.
Thanks,
Rakesh Pillai.
>
> >
> > diff --git
> > a/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-wpss-
> pil.ya
> > ml
> > b/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-wpss-
> pil.ya
> > ml
> > new file mode 100644
> > index 0000000..896d5f47
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-
> wpss-pi
> > +++ l.yaml
> > @@ -0,0 +1,198 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id:
> > +http://devicetree.org/schemas/remoteproc/qcom,sc7280-wpss-pil.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Qualcomm SC7280 WPSS Peripheral Image Loader
> > +
> > +maintainers:
> > + - Bjorn Andersson <bjorn.andersson@linaro.org>
> > +
> > +description:
> > + This document defines the binding for a component that loads and
> > +boots firmware
> > + on the Qualcomm Technology Inc. WPSS.
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - qcom,sc7280-wpss-pil
> > +
> > + reg:
> > + maxItems: 1
> > + description:
> > + The base address and size of the qdsp6ss register
> > +
> > + interrupts-extended:
>
> Use 'interrupts'. The tooling supports either.
>
> > + minItems: 6
>
> Don't need minItems unless it is less than 'items' length.
>
> > + items:
> > + - description: Watchdog interrupt
> > + - description: Fatal interrupt
> > + - description: Ready interrupt
> > + - description: Handover interrupt
> > + - description: Stop acknowledge interrupt
> > + - description: Shutdown acknowledge interrupt
> > +
> > + interrupt-names:
> > + minItems: 6
> > + items:
> > + - const: wdog
> > + - const: fatal
> > + - const: ready
> > + - const: handover
> > + - const: stop-ack
> > + - const: shutdown-ack
> > +
> > + clocks:
> > + minItems: 4
> > + items:
> > + - description: GCC WPSS AHB BDG Master clock
> > + - description: GCC WPSS AHB clock
> > + - description: GCC WPSS RSCP clock
> > + - description: XO clock
> > +
> > + clock-names:
> > + minItems: 4
> > + items:
> > + - const: gcc_wpss_ahb_bdg_mst_clk
> > + - const: gcc_wpss_ahb_clk
> > + - const: gcc_wpss_rscp_clk
>
> ahb_bdg, ahb, rscp is sufficient. Or use the same names as prior versions (did
> the h/w clocks change?).
>
> > + - const: xo
> > +
> > + power-domains:
> > + minItems: 2
> > + items:
> > + - description: CX power domain
> > + - description: MX power domain
> > +
> > + power-domain-names:
> > + minItems: 2
> > + items:
> > + - const: cx
> > + - const: mx
> > +
> > + resets:
> > + minItems: 2
> > + items:
> > + - description: AOSS restart
> > + - description: PDC SYNC
> > +
> > + reset-names:
> > + minItems: 2
> > + items:
> > + - const: restart
> > + - const: pdc_sync
> > +
> > + memory-region:
> > + maxItems: 1
> > + description: Reference to the reserved-memory for the Hexagon
> > + core
> > +
> > + qcom,halt-regs:
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + description:
> > + Phandle reference to a syscon representing TCSR followed by the
> > + three offsets within syscon for q6, modem and nc halt registers.
> > +
> > + qcom,qmp:
> > + $ref: /schemas/types.yaml#/definitions/phandle
> > + description: Reference to the AOSS side-channel message RAM.
> > +
> > + qcom,smem-states:
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + description: States used by the AP to signal the Hexagon core
> > + items:
> > + - description: Stop the modem
> > +
> > + qcom,smem-state-names:
> > + $ref: /schemas/types.yaml#/definitions/string-array
>
> string or string-array?
>
> > + description: The names of the state bits used for SMP2P output
> > + items:
> > + - const: stop
>
> This says only 1 entry, so 'string'.
>
> > +
> > + glink-edge:
> > + type: object
> > + description:
> > + Qualcomm G-Link subnode which represents communication edge,
> channels
> > + and devices related to the ADSP.
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - interrupts-extended
> > + - interrupt-names
> > + - clocks
> > + - clock-names
> > + - power-domains
> > + - power-domain-names
> > + - reset
> > + - reset-names
> > + - qcom,halt-regs
> > + - memory-region
> > + - qcom,qmp
> > + - qcom,smem-states
> > + - qcom,smem-state-names
> > + - glink-edge
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > + #include <dt-bindings/clock/qcom,gcc-sc7280.h>
> > + #include <dt-bindings/clock/qcom,rpmh.h>
> > + #include <dt-bindings/power/qcom-rpmpd.h>
> > + #include <dt-bindings/reset/qcom,sdm845-aoss.h>
> > + #include <dt-bindings/reset/qcom,sdm845-pdc.h>
> > + #include <dt-bindings/mailbox/qcom-ipcc.h>
> > + remoteproc@8a00000 {
> > + compatible = "qcom,sc7280-wpss-pil";
> > + reg = <0x08a00000 0x10000>;
> > +
> > + interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>,
> > + <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
> > + <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
> > + <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
> > + <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
> > + <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
> > + interrupt-names = "wdog", "fatal", "ready", "handover",
> > + "stop-ack", "shutdown-ack";
> > +
> > + clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>,
> > + <&gcc GCC_WPSS_AHB_CLK>,
> > + <&gcc GCC_WPSS_RSCP_CLK>,
> > + <&rpmhcc RPMH_CXO_CLK>;
> > + clock-names = "gcc_wpss_ahb_bdg_mst_clk",
> > + "gcc_wpss_ahb_clk",
> > + "gcc_wpss_rscp_clk",
> > + "xo";
> > +
> > + power-domains = <&rpmhpd SC7280_CX>,
> > + <&rpmhpd SC7280_MX>;
> > + power-domain-names = "cx", "mx";
> > +
> > + memory-region = <&wpss_mem>;
> > +
> > + qcom,qmp = <&aoss_qmp>;
> > +
> > + qcom,smem-states = <&wpss_smp2p_out 0>;
> > + qcom,smem-state-names = "stop";
> > +
> > + resets = <&aoss_reset AOSS_CC_WCSS_RESTART>,
> > + <&pdc_reset PDC_WPSS_SYNC_RESET>;
> > + reset-names = "restart", "pdc_sync";
> > +
> > + qcom,halt-regs = <&tcsr_mutex 0x37000>;
> > +
> > + status = "disabled";
> > +
> > + glink-edge {
> > + interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
> > + IPCC_MPROC_SIGNAL_GLINK_QMP
> > + IRQ_TYPE_EDGE_RISING>;
> > + mboxes = <&ipcc IPCC_CLIENT_WPSS
> > + IPCC_MPROC_SIGNAL_GLINK_QMP>;
> > +
> > + label = "wpss";
> > + qcom,remote-pid = <13>;
> > + };
> > + };
> > --
> > 2.7.4
> >
^ permalink raw reply [relevance 0%]
* RE: [PATCH v3 2/3] dt-bindings: remoteproc: qcom: Add SC7280 WPSS support
@ 2021-09-22 5:03 0% ` pillair
0 siblings, 0 replies; 200+ results
From: pillair @ 2021-09-22 5:03 UTC (permalink / raw)
To: 'Bjorn Andersson', 'Stephen Boyd'
Cc: agross, mathieu.poirier, ohad, p.zabel, robh+dt, linux-arm-msm,
devicetree, linux-kernel, sibis, mpubbise, kuabhs
> -----Original Message-----
> From: Bjorn Andersson <bjorn.andersson@linaro.org>
> Sent: Wednesday, September 22, 2021 5:08 AM
> To: Stephen Boyd <swboyd@chromium.org>
> Cc: Rakesh Pillai <pillair@codeaurora.org>; agross@kernel.org;
> mathieu.poirier@linaro.org; ohad@wizery.com; p.zabel@pengutronix.de;
> robh+dt@kernel.org; linux-arm-msm@vger.kernel.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> sibis@codeaurora.org; mpubbise@codeaurora.org; kuabhs@chromium.org
> Subject: Re: [PATCH v3 2/3] dt-bindings: remoteproc: qcom: Add SC7280
> WPSS support
>
> On Thu 16 Sep 23:25 PDT 2021, Stephen Boyd wrote:
>
> > Quoting Rakesh Pillai (2021-09-16 09:55:52)
> > > @@ -78,6 +84,10 @@ properties:
> > > Phandle reference to a syscon representing TCSR followed by the
> > > three offsets within syscon for q6, modem and nc halt
registers.
> > >
> > > + qcom,qmp:
> > > + $ref: /schemas/types.yaml#/definitions/phandle
> > > + description: Reference to the AOSS side-channel message RAM.
> > > +
> > > qcom,smem-states:
> > > $ref: /schemas/types.yaml#/definitions/phandle-array
> > > description: States used by the AP to signal the Hexagon core
> > > @@ -117,6 +127,33 @@ allOf:
> > > compatible:
> > > contains:
> > > enum:
> > > + - qcom,sc7280-wpss-pil
> > > + then:
> >
> > Honestly I find this if/else to be a huge tangle. Why not split the
> > binding so that each compatible is a different file? Then it is easier
> > to read and see what properties to set.
> >
>
> Further more, the way we express the non-PAS properties in the PAS node
> in the dtsi and then switch the compatible in the non-PAS devices means
that
> we're causing validation errors.
>
> So we should explode this binding to get rid of the conditionals and to
> describe the "superset" of the PAS and non-PAS compatibles, for platforms
> where this is applicable.
>
> Regards,
> Bjorn
Hi Bjorn,
I have posted v4 for this patchseries with wpss dt-bindings added as a
separate file.
Can you please check v4 ?
Thanks,
Rakesh Pillai.
>
> > > + properties:
> > > + interrupts-extended:
> > > + maxItems: 6
> > > + items:
> > > + - description: Watchdog interrupt
> > > + - description: Fatal interrupt
> > > + - description: Ready interrupt
^ permalink raw reply [relevance 0%]
* RE: [PATCH v3 1/3] dt-bindings: remoteproc: qcom: adsp: Convert binding to YAML
@ 2021-09-22 5:01 0% ` pillair
0 siblings, 0 replies; 200+ results
From: pillair @ 2021-09-22 5:01 UTC (permalink / raw)
To: 'Rob Herring', 'Stephen Boyd'
Cc: agross, bjorn.andersson, mathieu.poirier, ohad, p.zabel,
linux-arm-msm, devicetree, linux-kernel, sibis, mpubbise, kuabhs,
'Rakesh Pillai'
> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: Wednesday, September 22, 2021 4:59 AM
> To: Stephen Boyd <swboyd@chromium.org>
> Cc: Rakesh Pillai <pillair@codeaurora.org>; agross@kernel.org;
> bjorn.andersson@linaro.org; mathieu.poirier@linaro.org; ohad@wizery.com;
> p.zabel@pengutronix.de; linux-arm-msm@vger.kernel.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> sibis@codeaurora.org; mpubbise@codeaurora.org; kuabhs@chromium.org;
> Rakesh Pillai <pillair@qti.qualcomm.com>
> Subject: Re: [PATCH v3 1/3] dt-bindings: remoteproc: qcom: adsp: Convert
> binding to YAML
>
> On Thu, Sep 16, 2021 at 11:24:10PM -0700, Stephen Boyd wrote:
> > Quoting Rakesh Pillai (2021-09-16 09:55:51)
> > > diff --git
> > > a/Documentation/devicetree/bindings/remoteproc/qcom,hexagon-
> v56.yaml
> > > b/Documentation/devicetree/bindings/remoteproc/qcom,hexagon-
> v56.yaml
> > > new file mode 100644
> > > index 0000000..051da43
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/remoteproc/qcom,hexagon-
> v56.
> > > +++ yaml
> > > @@ -0,0 +1,267 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > > +---
> > > +$id:
> > > +http://devicetree.org/schemas/remoteproc/qcom,hexagon-v56.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: Qualcomm Hexagon v56 Peripheral Image Loader
> > > +
> > > +maintainers:
> > > + - Bjorn Andersson <bjorn.andersson@linaro.org>
> > > +
> > > +description:
> > > + This document defines the binding for a component that loads and
> > > +boots firmware
> > > + on the Qualcomm Technology Inc. Hexagon v56 core.
> > > +
> > > +properties:
> > > + compatible:
> > > + enum:
> > > + - qcom,qcs404-cdsp-pil
> > > + - qcom,sdm845-adsp-pil
> > > +
> > > + reg:
> > > + maxItems: 1
> > > + description:
> > > + The base address and size of the qdsp6ss register
> > > +
> > > + interrupts-extended:
> > > + minItems: 5
> > > + items:
> > > + - description: Watchdog interrupt
> > > + - description: Fatal interrupt
> > > + - description: Ready interrupt
> > > + - description: Handover interrupt
> > > + - description: Stop acknowledge interrupt
> > > +
> > > + interrupt-names:
> > > + minItems: 5
> > > + items:
> > > + - const: wdog
> > > + - const: fatal
> > > + - const: ready
> > > + - const: handover
> > > + - const: stop-ack
> > > +
> > > + clocks:
> > > + minItems: 7
> > > + maxItems: 8
> > > + description:
> > > + List of phandles and clock specifier pairs for the Hexagon,
> > > + per clock-names below.
> > > +
> > > + clock-names:
> > > + minItems: 7
> > > + maxItems: 8
> > > +
> > > + power-domains:
> > > + minItems: 1
> > > + items:
> > > + - description: CX power domain
> > > +
> > > + resets:
> > > + minItems: 1
> > > + maxItems: 2
> > > + description:
> > > + reference to the list of resets for the Hexagon.
> > > +
> > > + reset-names:
> > > + minItems: 1
> > > + maxItems: 2
> > > +
> > > + memory-region:
> > > + maxItems: 1
> > > + description: Reference to the reserved-memory for the Hexagon
> > > + core
> > > +
> > > + qcom,halt-regs:
> > > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > > + description:
> > > + Phandle reference to a syscon representing TCSR followed by the
> > > + three offsets within syscon for q6, modem and nc halt
registers.
> > > +
> > > + qcom,smem-states:
> > > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > > + description: States used by the AP to signal the Hexagon core
> > > + items:
> > > + - description: Stop the modem
> > > +
> > > + qcom,smem-state-names:
> > > + $ref: /schemas/types.yaml#/definitions/string-array
> > > + description: The names of the state bits used for SMP2P output
> > > + items:
> > > + - const: stop
> > > +
> > > + glink-edge:
> > > + type: object
> > > + description:
> > > + Qualcomm G-Link subnode which represents communication edge,
> channels
> > > + and devices related to the ADSP.
> > > +
> > > +required:
> > > + - compatible
> > > + - reg
> > > + - interrupts-extended
> > > + - interrupt-names
> > > + - clocks
> > > + - clock-names
> > > + - power-domains
> > > + - qcom,halt-regs
> > > + - memory-region
> > > + - qcom,smem-states
> > > + - qcom,smem-state-names
> >
> > Is there some way to make sure that 'resets' and 'reset-names' is
> > present when the compatible that defines them is used and not required
> > otherwise?
>
> Yes, plenty of examples of that.
>
> >
> > > +
> > > +additionalProperties: false
> > > +
> > > +allOf:
> > > + - if:
> > > + properties:
> > > + compatible:
> > > + contains:
> > > + enum:
> > > + - qcom,sdm845-adsp-pil
> > > + then:
> > > + properties:
> > > + clocks:
> > > + items:
> > > + - description: XO clock
> > > + - description: SWAY clock
> > > + - description: LPASS AHBS AON clock
> > > + - description: LPASS AHBM AON clock
> > > + - description: QDSP6SS XO clock
> > > + - description: QDSP6SS SLEEP clock
> > > + - description: QDSP6SS CORE clock
> > > + clock-names:
> > > + items:
> > > + - const: xo
> > > + - const: sway_cbcr
> > > + - const: lpass_ahbs_aon_cbcr
> > > + - const: lpass_ahbm_aon_cbcr
> > > + - const: qdsp6ss_xo
> > > + - const: qdsp6ss_sleep
> > > + - const: qdsp6ss_core
> > > +
> > > + - if:
> > > + properties:
> > > + compatible:
> > > + contains:
> > > + enum:
> > > + - qcom,qcs404-cdsp-pil
> > > + then:
> > > + properties:
> > > + clocks:
> > > + items:
> > > + - description: XO clock
> > > + - description: SWAY clock
> > > + - description: TBU clock
> > > + - description: BIMC clock
> > > + - description: AHB AON clock
> > > + - description: Q6SS SLAVE clock
> > > + - description: Q6SS MASTER clock
> > > + - description: Q6 AXIM clock
> > > + clock-names:
> > > + items:
> > > + - const: xo
> > > + - const: sway
> > > + - const: tbu
> > > + - const: bimc
> > > + - const: ahb_aon
> > > + - const: q6ss_slave
> > > + - const: q6ss_master
> > > + - const: q6_axim
> > > +
> > > + - if:
> > > + properties:
> > > + compatible:
> > > + contains:
> > > + enum:
> > > + - qcom,sc7280-wpss-pil
> >
> > This should be documented above in the compatible list?
> >
> > > + then:
> > > + properties:
> > > + clocks:
> > > + items:
> > > + - description: GCC WPSS AHB BDG Master clock
> > > + - description: GCC WPSS AHB clock
> > > + - description: GCC WPSS RSCP clock
> > > + clock-names:
> > > + items:
> > > + - const: gcc_wpss_ahb_bdg_mst_clk
> > > + - const: gcc_wpss_ahb_clk
> > > + - const: gcc_wpss_rscp_clk
> >
> > Is the 'gcc_wpss' prefix important? It would be shorter if it wasn't
> > there.
>
> Yes, and adding this new platform should be a separate patch.
>
> Rob
Hi Rob,
I have posted v4 for this patch series, where the dt-bindings for wpss has
been moved to a separate file.
Can you please review v4 ?
Thanks,
Rakesh Pillai
^ permalink raw reply [relevance 0%]
* Re: [PATCH v7 02/13] dt-bindings: remoteproc: qcom: pas: Add QMP property
2021-09-16 13:59 15% ` [PATCH v7 02/13] dt-bindings: remoteproc: qcom: pas: Add QMP property Sibi Sankar
@ 2021-09-21 22:06 0% ` Rob Herring
0 siblings, 0 replies; 200+ results
From: Rob Herring @ 2021-09-21 22:06 UTC (permalink / raw)
To: Sibi Sankar
Cc: rjw, sidgup, ohad, agross, linux-kernel, bjorn.andersson,
mathieu.poirier, mka, swboyd, devicetree, dianders, robh+dt,
linux-remoteproc, rishabhb, linux-arm-msm, ulf.hansson
On Thu, 16 Sep 2021 19:29:19 +0530, Sibi Sankar wrote:
> The load state power-domain, used by the co-processors to notify the
> Always on Subsystem (AOSS) that a particular co-processor is up/down,
> suffers from the side-effect of changing states during suspend/resume.
> However the co-processors enter low-power modes independent to that of
> the application processor and their states are expected to remain
> unaltered across system suspend/resume cycles. To achieve this behavior
> let's drop the load state power-domain and replace them with the qmp
> property for all SoCs supporting low power mode signalling.
>
> Due to the current broken load state implementation, we can afford the
> binding breakage that ensues and the remoteproc functionality will remain
> the same when using newer kernels with older dtbs.
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> Reviewed-by: Stephen Boyd <swboyd@chromium.org>
> ---
>
> v7:
> * Set "qcom,qmp" property to false for unsupported devices. [Rob]
>
> .../devicetree/bindings/remoteproc/qcom,adsp.yaml | 54 ++++++++++------------
> 1 file changed, 24 insertions(+), 30 deletions(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [relevance 0%]
* [PATCH v5 08/10] arm64: dts: qcom: sc7280: Add nodes to boot modem
2021-09-17 13:55 17% [PATCH v5 00/10] Add Modem support on SC7280 SoCs Sibi Sankar
` (6 preceding siblings ...)
2021-09-17 13:55 18% ` [PATCH v5 07/10] arm64: dts: qcom: sc7280: Add/Delete/Update reserved memory nodes Sibi Sankar
@ 2021-09-17 13:55 18% ` Sibi Sankar
2021-09-17 13:55 18% ` [PATCH v5 09/10] arm64: dts: qcom: sc7280: Add Q6V5 MSS node Sibi Sankar
` (3 subsequent siblings)
11 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-09-17 13:55 UTC (permalink / raw)
To: bjorn.andersson, robh+dt, will, saiprakash.ranjan, swboyd, mka
Cc: ohad, agross, mathieu.poirier, robin.murphy, joro, p.zabel,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
linux-arm-kernel, evgreen, dianders, Sibi Sankar
Add miscellaneous nodes to boot the modem and support post-mortem debug
on SC7280 SoCs.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 386c559351d5..84f56dae241b 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -662,6 +662,11 @@
#hwlock-cells = <1>;
};
+ tcsr: syscon@1fc0000 {
+ compatible = "qcom,sc7280-tcsr", "syscon";
+ reg = <0 0x01fc0000 0 0x30000>;
+ };
+
lpasscc: lpasscc@3000000 {
compatible = "qcom,sc7280-lpasscc";
reg = <0 0x03000000 0 0x40>,
@@ -1632,6 +1637,21 @@
};
};
+ imem@146a5000 {
+ compatible = "qcom,sc7280-imem", "syscon";
+ reg = <0 0x146a5000 0 0x6000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ranges = <0 0 0x146a5000 0x6000>;
+
+ pil-reloc@594c {
+ compatible = "qcom,pil-reloc-info";
+ reg = <0x594c 0xc8>;
+ };
+ };
+
apps_smmu: iommu@15000000 {
compatible = "qcom,sc7280-smmu-500", "arm,mmu-500";
reg = <0 0x15000000 0 0x100000>;
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 18%]
* [PATCH v5 10/10] arm64: dts: qcom: sc7280: Update Q6V5 MSS node
2021-09-17 13:55 17% [PATCH v5 00/10] Add Modem support on SC7280 SoCs Sibi Sankar
` (8 preceding siblings ...)
2021-09-17 13:55 18% ` [PATCH v5 09/10] arm64: dts: qcom: sc7280: Add Q6V5 MSS node Sibi Sankar
@ 2021-09-17 13:55 17% ` Sibi Sankar
2021-09-27 22:56 0% ` (subset) [PATCH v5 00/10] Add Modem support on SC7280 SoCs Bjorn Andersson
2021-10-08 12:53 0% ` Will Deacon
11 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-09-17 13:55 UTC (permalink / raw)
To: bjorn.andersson, robh+dt, will, saiprakash.ranjan, swboyd, mka
Cc: ohad, agross, mathieu.poirier, robin.murphy, joro, p.zabel,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
linux-arm-kernel, evgreen, dianders, Sibi Sankar
Update MSS node to support MSA based modem boot on SC7280 SoCs.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
v5:
* Add pka to the clock list to boot secure modem devices.
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 7 +++++++
arch/arm64/boot/dts/qcom/sc7280.dtsi | 19 ++++++++++++++++---
2 files changed, 23 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
index 21f29645d648..a50217722f1d 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
@@ -267,6 +267,13 @@
status = "okay";
};
+&remoteproc_mpss {
+ status = "okay";
+ compatible = "qcom,sc7280-mss-pil";
+ iommus = <&apps_smmu 0x124 0x0>, <&apps_smmu 0x488 0x7>;
+ memory-region = <&mba_mem &mpss_mem>;
+};
+
&sdhc_1 {
status = "okay";
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 2b9c28329f1e..85622c64774d 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -701,7 +701,8 @@
remoteproc_mpss: remoteproc@4080000 {
compatible = "qcom,sc7280-mpss-pas";
- reg = <0 0x04080000 0 0x10000>;
+ reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>;
+ reg-names = "qdsp6", "rmb";
interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
@@ -712,8 +713,12 @@
interrupt-names = "wdog", "fatal", "ready", "handover",
"stop-ack", "shutdown-ack";
- clocks = <&rpmhcc RPMH_CXO_CLK>;
- clock-names = "xo";
+ clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
+ <&gcc GCC_MSS_OFFLINE_AXI_CLK>,
+ <&gcc GCC_MSS_SNOC_AXI_CLK>,
+ <&rpmhcc RPMH_PKA_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "offline", "snoc_axi", "pka", "xo";
power-domains = <&rpmhpd SC7280_CX>,
<&rpmhpd SC7280_MSS>;
@@ -726,6 +731,14 @@
qcom,smem-states = <&modem_smp2p_out 0>;
qcom,smem-state-names = "stop";
+ resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
+ <&pdc_reset PDC_MODEM_SYNC_RESET>;
+ reset-names = "mss_restart", "pdc_reset";
+
+ qcom,halt-regs = <&tcsr_mutex 0x23000 0x25000 0x28000 0x33000>;
+ qcom,ext-regs = <&tcsr 0x10000 0x10004 &tcsr_mutex 0x26004 0x26008>;
+ qcom,qaccept-regs = <&tcsr_mutex 0x23030 0x23040 0x23020>;
+
status = "disabled";
glink-edge {
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 17%]
* [PATCH v5 09/10] arm64: dts: qcom: sc7280: Add Q6V5 MSS node
2021-09-17 13:55 17% [PATCH v5 00/10] Add Modem support on SC7280 SoCs Sibi Sankar
` (7 preceding siblings ...)
2021-09-17 13:55 18% ` [PATCH v5 08/10] arm64: dts: qcom: sc7280: Add nodes to boot modem Sibi Sankar
@ 2021-09-17 13:55 18% ` Sibi Sankar
2021-09-17 13:55 17% ` [PATCH v5 10/10] arm64: dts: qcom: sc7280: Update " Sibi Sankar
` (2 subsequent siblings)
11 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-09-17 13:55 UTC (permalink / raw)
To: bjorn.andersson, robh+dt, will, saiprakash.ranjan, swboyd, mka
Cc: ohad, agross, mathieu.poirier, robin.murphy, joro, p.zabel,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
linux-arm-kernel, evgreen, dianders, Sibi Sankar
This patch adds Q6V5 MSS PAS remoteproc node for SC7280 SoCs.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 40 ++++++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 84f56dae241b..2b9c28329f1e 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -699,6 +699,46 @@
#power-domain-cells = <1>;
};
+ remoteproc_mpss: remoteproc@4080000 {
+ compatible = "qcom,sc7280-mpss-pas";
+ reg = <0 0x04080000 0 0x10000>;
+
+ interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog", "fatal", "ready", "handover",
+ "stop-ack", "shutdown-ack";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ power-domains = <&rpmhpd SC7280_CX>,
+ <&rpmhpd SC7280_MSS>;
+ power-domain-names = "cx", "mss";
+
+ memory-region = <&mpss_mem>;
+
+ qcom,qmp = <&aoss_qmp>;
+
+ qcom,smem-states = <&modem_smp2p_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_MPSS
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+ label = "modem";
+ qcom,remote-pid = <1>;
+ };
+ };
+
stm@6002000 {
compatible = "arm,coresight-stm", "arm,primecell";
reg = <0 0x06002000 0 0x1000>,
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 18%]
* [PATCH v5 07/10] arm64: dts: qcom: sc7280: Add/Delete/Update reserved memory nodes
2021-09-17 13:55 17% [PATCH v5 00/10] Add Modem support on SC7280 SoCs Sibi Sankar
` (5 preceding siblings ...)
2021-09-17 13:55 18% ` [PATCH v5 06/10] arm64: dts: qcom: sc7280: Update reserved memory map Sibi Sankar
@ 2021-09-17 13:55 18% ` Sibi Sankar
2021-09-17 13:55 18% ` [PATCH v5 08/10] arm64: dts: qcom: sc7280: Add nodes to boot modem Sibi Sankar
` (4 subsequent siblings)
11 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-09-17 13:55 UTC (permalink / raw)
To: bjorn.andersson, robh+dt, will, saiprakash.ranjan, swboyd, mka
Cc: ohad, agross, mathieu.poirier, robin.murphy, joro, p.zabel,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
linux-arm-kernel, evgreen, dianders, Sibi Sankar
Add, delete and update platform specific reserved memory nodes.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 52 ++++++++++++++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
index 99f9ee5d13f5..21f29645d648 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
@@ -12,6 +12,58 @@
#include "pm8350c.dtsi"
#include "pmk8350.dtsi"
+/*
+ * Reserved memory changes
+ *
+ * Delete all unused memory nodes and define the peripheral memory regions
+ * required by the board dts.
+ *
+ */
+
+/delete-node/ &hyp_mem;
+/delete-node/ &xbl_mem;
+/delete-node/ &reserved_xbl_uefi_log;
+/delete-node/ &sec_apps_mem;
+
+/* Increase the size from 2.5MB to 8MB */
+&rmtfs_mem {
+ reg = <0x0 0x9c900000 0x0 0x800000>;
+};
+
+/ {
+ reserved-memory {
+ adsp_mem: memory@86700000 {
+ reg = <0x0 0x86700000 0x0 0x2800000>;
+ no-map;
+ };
+
+ camera_mem: memory@8ad00000 {
+ reg = <0x0 0x8ad00000 0x0 0x500000>;
+ no-map;
+ };
+
+ venus_mem: memory@8b200000 {
+ reg = <0x0 0x8b200000 0x0 0x500000>;
+ no-map;
+ };
+
+ mpss_mem: memory@8b800000 {
+ reg = <0x0 0x8b800000 0x0 0xf600000>;
+ no-map;
+ };
+
+ wpss_mem: memory@9ae00000 {
+ reg = <0x0 0x9ae00000 0x0 0x1900000>;
+ no-map;
+ };
+
+ mba_mem: memory@9c700000 {
+ reg = <0x0 0x9c700000 0x0 0x200000>;
+ no-map;
+ };
+ };
+};
+
&apps_rsc {
pm7325-regulators {
compatible = "qcom,pm7325-rpmh-regulators";
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 18%]
* [PATCH v5 05/10] remoteproc: mss: q6v5-mss: Add modem support on SC7280
2021-09-17 13:55 17% [PATCH v5 00/10] Add Modem support on SC7280 SoCs Sibi Sankar
` (3 preceding siblings ...)
2021-09-17 13:55 19% ` [PATCH v5 04/10] iommu/arm-smmu-qcom: Request direct mapping for modem device Sibi Sankar
@ 2021-09-17 13:55 10% ` Sibi Sankar
2021-09-17 13:55 18% ` [PATCH v5 06/10] arm64: dts: qcom: sc7280: Update reserved memory map Sibi Sankar
` (6 subsequent siblings)
11 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-09-17 13:55 UTC (permalink / raw)
To: bjorn.andersson, robh+dt, will, saiprakash.ranjan, swboyd, mka
Cc: ohad, agross, mathieu.poirier, robin.murphy, joro, p.zabel,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
linux-arm-kernel, evgreen, dianders, Sibi Sankar
Add out of reset sequence support for modem sub-system on SC7280 SoCs.
It requires access to an additional set of qaccept registers, external
power/clk control registers and halt vq6 register to put the modem back
into reset.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
v5:
* Add pka to the clock list to boot secure modem devices.
drivers/remoteproc/qcom_q6v5_mss.c | 253 ++++++++++++++++++++++++++++++++++++-
1 file changed, 249 insertions(+), 4 deletions(-)
diff --git a/drivers/remoteproc/qcom_q6v5_mss.c b/drivers/remoteproc/qcom_q6v5_mss.c
index 7a1422bd7925..ec0701126ab3 100644
--- a/drivers/remoteproc/qcom_q6v5_mss.c
+++ b/drivers/remoteproc/qcom_q6v5_mss.c
@@ -77,6 +77,14 @@
#define HALT_ACK_TIMEOUT_US 100000
+/* QACCEPT Register Offsets */
+#define QACCEPT_ACCEPT_REG 0x0
+#define QACCEPT_ACTIVE_REG 0x4
+#define QACCEPT_DENY_REG 0x8
+#define QACCEPT_REQ_REG 0xC
+
+#define QACCEPT_TIMEOUT_US 50
+
/* QDSP6SS_RESET */
#define Q6SS_STOP_CORE BIT(0)
#define Q6SS_CORE_ARES BIT(1)
@@ -143,6 +151,9 @@ struct rproc_hexagon_res {
bool has_alt_reset;
bool has_mba_logs;
bool has_spare_reg;
+ bool has_qaccept_regs;
+ bool has_ext_cntl_regs;
+ bool has_vq6;
};
struct q6v5 {
@@ -158,8 +169,18 @@ struct q6v5 {
u32 halt_q6;
u32 halt_modem;
u32 halt_nc;
+ u32 halt_vq6;
u32 conn_box;
+ u32 qaccept_mdm;
+ u32 qaccept_cx;
+ u32 qaccept_axi;
+
+ u32 axim1_clk_off;
+ u32 crypto_clk_off;
+ u32 force_clk_on;
+ u32 rscc_disable;
+
struct reset_control *mss_restart;
struct reset_control *pdc_reset;
@@ -201,6 +222,9 @@ struct q6v5 {
bool has_alt_reset;
bool has_mba_logs;
bool has_spare_reg;
+ bool has_qaccept_regs;
+ bool has_ext_cntl_regs;
+ bool has_vq6;
int mpss_perm;
int mba_perm;
const char *hexagon_mdt_image;
@@ -213,6 +237,7 @@ enum {
MSS_MSM8996,
MSS_MSM8998,
MSS_SC7180,
+ MSS_SC7280,
MSS_SDM845,
};
@@ -473,6 +498,12 @@ static int q6v5_reset_assert(struct q6v5 *qproc)
regmap_update_bits(qproc->conn_map, qproc->conn_box,
AXI_GATING_VALID_OVERRIDE, 0);
ret = reset_control_deassert(qproc->mss_restart);
+ } else if (qproc->has_ext_cntl_regs) {
+ regmap_write(qproc->conn_map, qproc->rscc_disable, 0);
+ reset_control_assert(qproc->pdc_reset);
+ reset_control_assert(qproc->mss_restart);
+ reset_control_deassert(qproc->pdc_reset);
+ ret = reset_control_deassert(qproc->mss_restart);
} else {
ret = reset_control_assert(qproc->mss_restart);
}
@@ -490,7 +521,7 @@ static int q6v5_reset_deassert(struct q6v5 *qproc)
ret = reset_control_reset(qproc->mss_restart);
writel(0, qproc->rmb_base + RMB_MBA_ALT_RESET);
reset_control_deassert(qproc->pdc_reset);
- } else if (qproc->has_spare_reg) {
+ } else if (qproc->has_spare_reg || qproc->has_ext_cntl_regs) {
ret = reset_control_reset(qproc->mss_restart);
} else {
ret = reset_control_deassert(qproc->mss_restart);
@@ -604,7 +635,7 @@ static int q6v5proc_reset(struct q6v5 *qproc)
}
goto pbl_wait;
- } else if (qproc->version == MSS_SC7180) {
+ } else if (qproc->version == MSS_SC7180 || qproc->version == MSS_SC7280) {
val = readl(qproc->reg_base + QDSP6SS_SLEEP);
val |= Q6SS_CBCR_CLKEN;
writel(val, qproc->reg_base + QDSP6SS_SLEEP);
@@ -787,6 +818,89 @@ static int q6v5proc_reset(struct q6v5 *qproc)
return ret;
}
+static int q6v5proc_enable_qchannel(struct q6v5 *qproc, struct regmap *map, u32 offset)
+{
+ unsigned int val;
+ int ret;
+
+ if (!qproc->has_qaccept_regs)
+ return 0;
+
+ if (qproc->has_ext_cntl_regs) {
+ regmap_write(qproc->conn_map, qproc->rscc_disable, 0);
+ regmap_write(qproc->conn_map, qproc->force_clk_on, 1);
+
+ ret = regmap_read_poll_timeout(qproc->halt_map, qproc->axim1_clk_off, val,
+ !val, 1, Q6SS_CBCR_TIMEOUT_US);
+ if (ret) {
+ dev_err(qproc->dev, "failed to enable axim1 clock\n");
+ return -ETIMEDOUT;
+ }
+ }
+
+ regmap_write(map, offset + QACCEPT_REQ_REG, 1);
+
+ /* Wait for accept */
+ ret = regmap_read_poll_timeout(map, offset + QACCEPT_ACCEPT_REG, val, val, 5,
+ QACCEPT_TIMEOUT_US);
+ if (ret) {
+ dev_err(qproc->dev, "qchannel enable failed\n");
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+static void q6v5proc_disable_qchannel(struct q6v5 *qproc, struct regmap *map, u32 offset)
+{
+ int ret;
+ unsigned int val, retry;
+ unsigned int nretry = 10;
+ bool takedown_complete = false;
+
+ if (!qproc->has_qaccept_regs)
+ return;
+
+ while (!takedown_complete && nretry) {
+ nretry--;
+
+ /* Wait for active transactions to complete */
+ regmap_read_poll_timeout(map, offset + QACCEPT_ACTIVE_REG, val, !val, 5,
+ QACCEPT_TIMEOUT_US);
+
+ /* Request Q-channel transaction takedown */
+ regmap_write(map, offset + QACCEPT_REQ_REG, 0);
+
+ /*
+ * If the request is denied, reset the Q-channel takedown request,
+ * wait for active transactions to complete and retry takedown.
+ */
+ retry = 10;
+ while (retry) {
+ usleep_range(5, 10);
+ retry--;
+ ret = regmap_read(map, offset + QACCEPT_DENY_REG, &val);
+ if (!ret && val) {
+ regmap_write(map, offset + QACCEPT_REQ_REG, 1);
+ break;
+ }
+
+ ret = regmap_read(map, offset + QACCEPT_ACCEPT_REG, &val);
+ if (!ret && !val) {
+ takedown_complete = true;
+ break;
+ }
+ }
+
+ if (!retry)
+ break;
+ }
+
+ /* Rely on mss_restart to clear out pending transactions on takedown failure */
+ if (!takedown_complete)
+ dev_err(qproc->dev, "qchannel takedown failed\n");
+}
+
static void q6v5proc_halt_axi_port(struct q6v5 *qproc,
struct regmap *halt_map,
u32 offset)
@@ -950,6 +1064,12 @@ static int q6v5_mba_load(struct q6v5 *qproc)
goto assert_reset;
}
+ ret = q6v5proc_enable_qchannel(qproc, qproc->halt_map, qproc->qaccept_axi);
+ if (ret) {
+ dev_err(qproc->dev, "failed to enable axi bridge\n");
+ goto disable_active_clks;
+ }
+
/*
* Some versions of the MBA firmware will upon boot wipe the MPSS region as well, so provide
* the Q6 access to this region.
@@ -996,8 +1116,13 @@ static int q6v5_mba_load(struct q6v5 *qproc)
halt_axi_ports:
q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
+ if (qproc->has_vq6)
+ q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_vq6);
q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
+ q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_mdm);
+ q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_cx);
+ q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_axi);
mba_load_err = true;
reclaim_mba:
xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true,
@@ -1047,6 +1172,8 @@ static void q6v5_mba_reclaim(struct q6v5 *qproc)
qproc->dp_size = 0;
q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
+ if (qproc->has_vq6)
+ q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_vq6);
q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
if (qproc->version == MSS_MSM8996) {
@@ -1059,6 +1186,24 @@ static void q6v5_mba_reclaim(struct q6v5 *qproc)
writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
}
+ if (qproc->has_ext_cntl_regs) {
+ regmap_write(qproc->conn_map, qproc->rscc_disable, 1);
+
+ ret = regmap_read_poll_timeout(qproc->halt_map, qproc->axim1_clk_off, val,
+ !val, 1, Q6SS_CBCR_TIMEOUT_US);
+ if (ret)
+ dev_err(qproc->dev, "failed to enable axim1 clock\n");
+
+ ret = regmap_read_poll_timeout(qproc->halt_map, qproc->crypto_clk_off, val,
+ !val, 1, Q6SS_CBCR_TIMEOUT_US);
+ if (ret)
+ dev_err(qproc->dev, "failed to enable crypto clock\n");
+ }
+
+ q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_mdm);
+ q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_cx);
+ q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_axi);
+
q6v5_reset_assert(qproc);
q6v5_clk_disable(qproc->dev, qproc->reset_clks,
@@ -1471,6 +1616,7 @@ static int q6v5_init_mem(struct q6v5 *qproc, struct platform_device *pdev)
{
struct of_phandle_args args;
struct resource *res;
+ int halt_cell_cnt = 3;
int ret;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qdsp6");
@@ -1483,8 +1629,11 @@ static int q6v5_init_mem(struct q6v5 *qproc, struct platform_device *pdev)
if (IS_ERR(qproc->rmb_base))
return PTR_ERR(qproc->rmb_base);
+ if (qproc->has_vq6)
+ halt_cell_cnt++;
+
ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
- "qcom,halt-regs", 3, 0, &args);
+ "qcom,halt-regs", halt_cell_cnt, 0, &args);
if (ret < 0) {
dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n");
return -EINVAL;
@@ -1499,6 +1648,52 @@ static int q6v5_init_mem(struct q6v5 *qproc, struct platform_device *pdev)
qproc->halt_modem = args.args[1];
qproc->halt_nc = args.args[2];
+ if (qproc->has_vq6)
+ qproc->halt_vq6 = args.args[3];
+
+ if (qproc->has_qaccept_regs) {
+ ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
+ "qcom,qaccept-regs",
+ 3, 0, &args);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "failed to parse qaccept-regs\n");
+ return -EINVAL;
+ }
+
+ qproc->qaccept_mdm = args.args[0];
+ qproc->qaccept_cx = args.args[1];
+ qproc->qaccept_axi = args.args[2];
+ }
+
+ if (qproc->has_ext_cntl_regs) {
+ ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
+ "qcom,ext-regs",
+ 2, 0, &args);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "failed to parse ext-regs index 0\n");
+ return -EINVAL;
+ }
+
+ qproc->conn_map = syscon_node_to_regmap(args.np);
+ of_node_put(args.np);
+ if (IS_ERR(qproc->conn_map))
+ return PTR_ERR(qproc->conn_map);
+
+ qproc->force_clk_on = args.args[0];
+ qproc->rscc_disable = args.args[1];
+
+ ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
+ "qcom,ext-regs",
+ 2, 1, &args);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "failed to parse ext-regs index 1\n");
+ return -EINVAL;
+ }
+
+ qproc->axim1_clk_off = args.args[0];
+ qproc->crypto_clk_off = args.args[1];
+ }
+
if (qproc->has_spare_reg) {
ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
"qcom,spare-regs",
@@ -1590,7 +1785,7 @@ static int q6v5_init_reset(struct q6v5 *qproc)
return PTR_ERR(qproc->mss_restart);
}
- if (qproc->has_alt_reset || qproc->has_spare_reg) {
+ if (qproc->has_alt_reset || qproc->has_spare_reg || qproc->has_ext_cntl_regs) {
qproc->pdc_reset = devm_reset_control_get_exclusive(qproc->dev,
"pdc_reset");
if (IS_ERR(qproc->pdc_reset)) {
@@ -1697,6 +1892,9 @@ static int q6v5_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, qproc);
+ qproc->has_qaccept_regs = desc->has_qaccept_regs;
+ qproc->has_ext_cntl_regs = desc->has_ext_cntl_regs;
+ qproc->has_vq6 = desc->has_vq6;
qproc->has_spare_reg = desc->has_spare_reg;
ret = q6v5_init_mem(qproc, pdev);
if (ret)
@@ -1857,9 +2055,40 @@ static const struct rproc_hexagon_res sc7180_mss = {
.has_alt_reset = false,
.has_mba_logs = true,
.has_spare_reg = true,
+ .has_qaccept_regs = false,
+ .has_ext_cntl_regs = false,
+ .has_vq6 = false,
.version = MSS_SC7180,
};
+static const struct rproc_hexagon_res sc7280_mss = {
+ .hexagon_mba_image = "mba.mbn",
+ .proxy_clk_names = (char*[]){
+ "xo",
+ "pka",
+ NULL
+ },
+ .active_clk_names = (char*[]){
+ "iface",
+ "offline",
+ "snoc_axi",
+ NULL
+ },
+ .proxy_pd_names = (char*[]){
+ "cx",
+ "mss",
+ NULL
+ },
+ .need_mem_protection = true,
+ .has_alt_reset = false,
+ .has_mba_logs = true,
+ .has_spare_reg = false,
+ .has_qaccept_regs = true,
+ .has_ext_cntl_regs = true,
+ .has_vq6 = true,
+ .version = MSS_SC7280,
+};
+
static const struct rproc_hexagon_res sdm845_mss = {
.hexagon_mba_image = "mba.mbn",
.proxy_clk_names = (char*[]){
@@ -1889,6 +2118,9 @@ static const struct rproc_hexagon_res sdm845_mss = {
.has_alt_reset = true,
.has_mba_logs = false,
.has_spare_reg = false,
+ .has_qaccept_regs = false,
+ .has_ext_cntl_regs = false,
+ .has_vq6 = false,
.version = MSS_SDM845,
};
@@ -1917,6 +2149,9 @@ static const struct rproc_hexagon_res msm8998_mss = {
.has_alt_reset = false,
.has_mba_logs = false,
.has_spare_reg = false,
+ .has_qaccept_regs = false,
+ .has_ext_cntl_regs = false,
+ .has_vq6 = false,
.version = MSS_MSM8998,
};
@@ -1948,6 +2183,9 @@ static const struct rproc_hexagon_res msm8996_mss = {
.has_alt_reset = false,
.has_mba_logs = false,
.has_spare_reg = false,
+ .has_qaccept_regs = false,
+ .has_ext_cntl_regs = false,
+ .has_vq6 = false,
.version = MSS_MSM8996,
};
@@ -1990,6 +2228,9 @@ static const struct rproc_hexagon_res msm8916_mss = {
.has_alt_reset = false,
.has_mba_logs = false,
.has_spare_reg = false,
+ .has_qaccept_regs = false,
+ .has_ext_cntl_regs = false,
+ .has_vq6 = false,
.version = MSS_MSM8916,
};
@@ -2040,6 +2281,9 @@ static const struct rproc_hexagon_res msm8974_mss = {
.has_alt_reset = false,
.has_mba_logs = false,
.has_spare_reg = false,
+ .has_qaccept_regs = false,
+ .has_ext_cntl_regs = false,
+ .has_vq6 = false,
.version = MSS_MSM8974,
};
@@ -2050,6 +2294,7 @@ static const struct of_device_id q6v5_of_match[] = {
{ .compatible = "qcom,msm8996-mss-pil", .data = &msm8996_mss},
{ .compatible = "qcom,msm8998-mss-pil", .data = &msm8998_mss},
{ .compatible = "qcom,sc7180-mss-pil", .data = &sc7180_mss},
+ { .compatible = "qcom,sc7280-mss-pil", .data = &sc7280_mss},
{ .compatible = "qcom,sdm845-mss-pil", .data = &sdm845_mss},
{ },
};
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 10%]
* [PATCH v5 04/10] iommu/arm-smmu-qcom: Request direct mapping for modem device
2021-09-17 13:55 17% [PATCH v5 00/10] Add Modem support on SC7280 SoCs Sibi Sankar
` (2 preceding siblings ...)
2021-09-17 13:55 14% ` [PATCH v5 03/10] dt-bindings: remoteproc: qcom: Update Q6V5 Modem PIL binding Sibi Sankar
@ 2021-09-17 13:55 19% ` Sibi Sankar
2021-10-07 20:08 6% ` Sibi Sankar
2021-09-17 13:55 10% ` [PATCH v5 05/10] remoteproc: mss: q6v5-mss: Add modem support on SC7280 Sibi Sankar
` (7 subsequent siblings)
11 siblings, 1 reply; 200+ results
From: Sibi Sankar @ 2021-09-17 13:55 UTC (permalink / raw)
To: bjorn.andersson, robh+dt, will, saiprakash.ranjan, swboyd, mka
Cc: ohad, agross, mathieu.poirier, robin.murphy, joro, p.zabel,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
linux-arm-kernel, evgreen, dianders, Sibi Sankar
The SID configuration requirement for Modem on SC7280 is similar to the
ones found on SC7180/SDM845 SoCs. So, add the SC7280 modem compatible to
the list to defer the programming of the modem SIDs to the kernel.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index 55690af1b25d..3b9b46fca0b3 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -231,6 +231,7 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = {
{ .compatible = "qcom,sc7180-mdss" },
{ .compatible = "qcom,sc7180-mss-pil" },
{ .compatible = "qcom,sc7280-mdss" },
+ { .compatible = "qcom,sc7280-mss-pil" },
{ .compatible = "qcom,sc8180x-mdss" },
{ .compatible = "qcom,sdm845-mdss" },
{ .compatible = "qcom,sdm845-mss-pil" },
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 19%]
* [PATCH v5 02/10] remoteproc: qcom: pas: Add SC7280 Modem support
2021-09-17 13:55 17% [PATCH v5 00/10] Add Modem support on SC7280 SoCs Sibi Sankar
2021-09-17 13:55 18% ` [PATCH v5 01/10] dt-bindings: remoteproc: qcom: pas: Add SC7280 MPSS support Sibi Sankar
@ 2021-09-17 13:55 19% ` Sibi Sankar
2021-09-17 13:55 14% ` [PATCH v5 03/10] dt-bindings: remoteproc: qcom: Update Q6V5 Modem PIL binding Sibi Sankar
` (9 subsequent siblings)
11 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-09-17 13:55 UTC (permalink / raw)
To: bjorn.andersson, robh+dt, will, saiprakash.ranjan, swboyd, mka
Cc: ohad, agross, mathieu.poirier, robin.murphy, joro, p.zabel,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
linux-arm-kernel, evgreen, dianders, Sibi Sankar
Add support for booting the Modem DSP found on QTI SC7280 SoCs.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
drivers/remoteproc/qcom_q6v5_pas.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q6v5_pas.c
index 8da0362d3d85..c466b97471a5 100644
--- a/drivers/remoteproc/qcom_q6v5_pas.c
+++ b/drivers/remoteproc/qcom_q6v5_pas.c
@@ -807,6 +807,7 @@ static const struct of_device_id adsp_of_match[] = {
{ .compatible = "qcom,qcs404-cdsp-pas", .data = &cdsp_resource_init },
{ .compatible = "qcom,qcs404-wcss-pas", .data = &wcss_resource_init },
{ .compatible = "qcom,sc7180-mpss-pas", .data = &mpss_resource_init},
+ { .compatible = "qcom,sc7280-mpss-pas", .data = &mpss_resource_init},
{ .compatible = "qcom,sc8180x-adsp-pas", .data = &sm8150_adsp_resource},
{ .compatible = "qcom,sc8180x-cdsp-pas", .data = &sm8150_cdsp_resource},
{ .compatible = "qcom,sc8180x-mpss-pas", .data = &sc8180x_mpss_resource},
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 19%]
* [PATCH v5 06/10] arm64: dts: qcom: sc7280: Update reserved memory map
2021-09-17 13:55 17% [PATCH v5 00/10] Add Modem support on SC7280 SoCs Sibi Sankar
` (4 preceding siblings ...)
2021-09-17 13:55 10% ` [PATCH v5 05/10] remoteproc: mss: q6v5-mss: Add modem support on SC7280 Sibi Sankar
@ 2021-09-17 13:55 18% ` Sibi Sankar
2021-09-17 13:55 18% ` [PATCH v5 07/10] arm64: dts: qcom: sc7280: Add/Delete/Update reserved memory nodes Sibi Sankar
` (5 subsequent siblings)
11 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-09-17 13:55 UTC (permalink / raw)
To: bjorn.andersson, robh+dt, will, saiprakash.ranjan, swboyd, mka
Cc: ohad, agross, mathieu.poirier, robin.murphy, joro, p.zabel,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
linux-arm-kernel, evgreen, dianders, Sibi Sankar
Add missing reserved regions as described in v1 of SC7280 memory map.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 34 ++++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 89ed7f2b5583..386c559351d5 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -48,6 +48,16 @@
#size-cells = <2>;
ranges;
+ hyp_mem: memory@80000000 {
+ reg = <0x0 0x80000000 0x0 0x600000>;
+ no-map;
+ };
+
+ xbl_mem: memory@80600000 {
+ reg = <0x0 0x80600000 0x0 0x200000>;
+ no-map;
+ };
+
aop_mem: memory@80800000 {
reg = <0x0 0x80800000 0x0 0x60000>;
no-map;
@@ -59,6 +69,16 @@
no-map;
};
+ reserved_xbl_uefi_log: memory@80880000 {
+ reg = <0x0 0x80884000 0x0 0x10000>;
+ no-map;
+ };
+
+ sec_apps_mem: memory@808ff000 {
+ reg = <0x0 0x808ff000 0x0 0x1000>;
+ no-map;
+ };
+
smem_mem: memory@80900000 {
reg = <0x0 0x80900000 0x0 0x200000>;
no-map;
@@ -69,10 +89,24 @@
reg = <0x0 0x80b00000 0x0 0x100000>;
};
+ wlan_fw_mem: memory@80c00000 {
+ reg = <0x0 0x80c00000 0x0 0xc00000>;
+ no-map;
+ };
+
ipa_fw_mem: memory@8b700000 {
reg = <0 0x8b700000 0 0x10000>;
no-map;
};
+
+ rmtfs_mem: memory@9c900000 {
+ compatible = "qcom,rmtfs-mem";
+ reg = <0x0 0x9c900000 0x0 0x280000>;
+ no-map;
+
+ qcom,client-id = <1>;
+ qcom,vmid = <15>;
+ };
};
cpus {
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 18%]
* [PATCH v5 01/10] dt-bindings: remoteproc: qcom: pas: Add SC7280 MPSS support
2021-09-17 13:55 17% [PATCH v5 00/10] Add Modem support on SC7280 SoCs Sibi Sankar
@ 2021-09-17 13:55 18% ` Sibi Sankar
2021-09-17 13:55 19% ` [PATCH v5 02/10] remoteproc: qcom: pas: Add SC7280 Modem support Sibi Sankar
` (10 subsequent siblings)
11 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-09-17 13:55 UTC (permalink / raw)
To: bjorn.andersson, robh+dt, will, saiprakash.ranjan, swboyd, mka
Cc: ohad, agross, mathieu.poirier, robin.murphy, joro, p.zabel,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
linux-arm-kernel, evgreen, dianders, Sibi Sankar
Add MPSS PAS support for SC7280 SoCs.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml
index ff265aa365de..63e06d93bca3 100644
--- a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml
@@ -25,6 +25,7 @@ properties:
- qcom,qcs404-cdsp-pas
- qcom,qcs404-wcss-pas
- qcom,sc7180-mpss-pas
+ - qcom,sc7280-mpss-pas
- qcom,sc8180x-adsp-pas
- qcom,sc8180x-cdsp-pas
- qcom,sc8180x-mpss-pas
@@ -151,6 +152,7 @@ allOf:
- qcom,msm8998-adsp-pas
- qcom,qcs404-adsp-pas
- qcom,qcs404-wcss-pas
+ - qcom,sc7280-mpss-pas
- qcom,sc8180x-adsp-pas
- qcom,sc8180x-cdsp-pas
- qcom,sc8180x-mpss-pas
@@ -296,6 +298,7 @@ allOf:
contains:
enum:
- qcom,sc7180-mpss-pas
+ - qcom,sc7280-mpss-pas
- qcom,sc8180x-mpss-pas
- qcom,sdx55-mpss-pas
- qcom,sm8150-mpss-pas
@@ -400,6 +403,7 @@ allOf:
compatible:
contains:
enum:
+ - qcom,sc7280-mpss-pas
- qcom,sdx55-mpss-pas
- qcom,sm8150-mpss-pas
- qcom,sm8350-mpss-pas
@@ -475,6 +479,7 @@ allOf:
contains:
enum:
- qcom,sc7180-mpss-pas
+ - qcom,sc7280-mpss-pas
then:
properties:
resets:
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 18%]
* [PATCH v5 03/10] dt-bindings: remoteproc: qcom: Update Q6V5 Modem PIL binding
2021-09-17 13:55 17% [PATCH v5 00/10] Add Modem support on SC7280 SoCs Sibi Sankar
2021-09-17 13:55 18% ` [PATCH v5 01/10] dt-bindings: remoteproc: qcom: pas: Add SC7280 MPSS support Sibi Sankar
2021-09-17 13:55 19% ` [PATCH v5 02/10] remoteproc: qcom: pas: Add SC7280 Modem support Sibi Sankar
@ 2021-09-17 13:55 14% ` Sibi Sankar
2021-09-17 13:55 19% ` [PATCH v5 04/10] iommu/arm-smmu-qcom: Request direct mapping for modem device Sibi Sankar
` (8 subsequent siblings)
11 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-09-17 13:55 UTC (permalink / raw)
To: bjorn.andersson, robh+dt, will, saiprakash.ranjan, swboyd, mka
Cc: ohad, agross, mathieu.poirier, robin.murphy, joro, p.zabel,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
linux-arm-kernel, evgreen, dianders, Sibi Sankar
Add a new modem compatible string for QTI SC7280 SoCs and introduce the
"qcom,ext-regs" and "qcom,qaccept-regs" properties needed by the modem
sub-system running on SC7280 SoCs.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
v5:
* Add pka to the clock list to boot secure modem devices.
.../devicetree/bindings/remoteproc/qcom,q6v5.txt | 32 ++++++++++++++++++++--
1 file changed, 30 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
index 494257010629..8f1507052afd 100644
--- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
@@ -15,6 +15,7 @@ on the Qualcomm Hexagon core.
"qcom,msm8996-mss-pil"
"qcom,msm8998-mss-pil"
"qcom,sc7180-mss-pil"
+ "qcom,sc7280-mss-pil"
"qcom,sdm845-mss-pil"
- reg:
@@ -47,6 +48,7 @@ on the Qualcomm Hexagon core.
qcom,msm8996-mss-pil:
qcom,msm8998-mss-pil:
qcom,sc7180-mss-pil:
+ qcom,sc7280-mss-pil:
qcom,sdm845-mss-pil:
must be "wdog", "fatal", "ready", "handover", "stop-ack",
"shutdown-ack"
@@ -87,6 +89,8 @@ on the Qualcomm Hexagon core.
qcom,sc7180-mss-pil:
must be "iface", "bus", "xo", "snoc_axi", "mnoc_axi",
"nav"
+ qcom,sc7280-mss-pil:
+ must be "iface", "xo", "snoc_axi", "offline", "pka"
qcom,sdm845-mss-pil:
must be "iface", "bus", "mem", "xo", "gpll0_mss",
"snoc_axi", "mnoc_axi", "prng"
@@ -98,7 +102,7 @@ on the Qualcomm Hexagon core.
reference to the list of 3 reset-controllers for the
wcss sub-system
reference to the list of 2 reset-controllers for the modem
- sub-system on SC7180, SDM845 SoCs
+ sub-system on SC7180, SC7280, SDM845 SoCs
- reset-names:
Usage: required
@@ -107,7 +111,7 @@ on the Qualcomm Hexagon core.
must be "wcss_aon_reset", "wcss_reset", "wcss_q6_reset"
for the wcss sub-system
must be "mss_restart", "pdc_reset" for the modem
- sub-system on SC7180, SDM845 SoCs
+ sub-system on SC7180, SC7280, SDM845 SoCs
For devices where the mba and mpss sub-nodes are not specified, mba/mpss region
should be referenced as follows:
@@ -173,6 +177,9 @@ For the compatible string below the following supplies are required:
qcom,msm8998-mss-pil:
must be "cx", "mx"
qcom,sc7180-mss-pil:
+ must be "cx", "mx", "mss"
+ qcom,sc7280-mss-pil:
+ must be "cx", "mss"
qcom,sdm845-mss-pil:
must be "cx", "mx", "mss"
@@ -198,6 +205,9 @@ For the compatible string below the following supplies are required:
Definition: a phandle reference to a syscon representing TCSR followed
by the three offsets within syscon for q6, modem and nc
halt registers.
+ a phandle reference to a syscon representing TCSR followed
+ by the four offsets within syscon for q6, modem, nc and vq6
+ halt registers on SC7280 SoCs.
For the compatible strings below the following phandle references are required:
"qcom,sc7180-mss-pil"
@@ -208,6 +218,24 @@ For the compatible strings below the following phandle references are required:
by the offset within syscon for conn_box_spare0 register
used by the modem sub-system running on SC7180 SoC.
+For the compatible strings below the following phandle references are required:
+ "qcom,sc7280-mss-pil"
+- qcom,ext-regs:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: two phandle references to syscons representing TCSR_REG and
+ TCSR register space followed by the two offsets within the syscon
+ to force_clk_en/rscc_disable and axim1_clk_off/crypto_clk_off
+ registers respectively.
+
+- qcom,qaccept-regs:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: a phandle reference to a syscon representing TCSR followed
+ by the three offsets within syscon for mdm, cx and axi
+ qaccept registers used by the modem sub-system running on
+ SC7280 SoC.
+
The Hexagon node must contain iommus property as described in ../iommu/iommu.txt
on platforms which do not have TrustZone.
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 14%]
* [PATCH v5 00/10] Add Modem support on SC7280 SoCs
@ 2021-09-17 13:55 17% Sibi Sankar
2021-09-17 13:55 18% ` [PATCH v5 01/10] dt-bindings: remoteproc: qcom: pas: Add SC7280 MPSS support Sibi Sankar
` (11 more replies)
0 siblings, 12 replies; 200+ results
From: Sibi Sankar @ 2021-09-17 13:55 UTC (permalink / raw)
To: bjorn.andersson, robh+dt, will, saiprakash.ranjan, swboyd, mka
Cc: ohad, agross, mathieu.poirier, robin.murphy, joro, p.zabel,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
linux-arm-kernel, evgreen, dianders, Sibi Sankar
This patch series adds support for booting the Modem Q6 DSP found on
Qualcomm's SC7280 SoCs.
Depends on:
qmp_send: https://patchwork.kernel.org/project/linux-arm-msm/cover/1630420228-31075-1-git-send-email-deesin@codeaurora.org/
rproc qmp: https://patchwork.kernel.org/project/linux-arm-msm/cover/1631800770-371-1-git-send-email-sibis@codeaurora.org/
V5:
* Rebased to linux-next and picked up Rbs.
* Add pka to the clock list to boot secure modem devices.
V4:
* Rebased to linux-next and picked up Rbs.
* Fixed typo (patch 10).
V3:
* Keep the memory map version in commit message (patch 6). [Bjorn]
* Rename tcsr node and add qualifying compatibles to tcsr and imem nodes
(patch 8). [Bjorn]
* Place remoteproc_mpss node in alphabetical order above pinctrl
section (patch 10). [Stephen]
V2:
* Misc. typos (patch 3). [Matthias]
* Document the q-channel takedown procedure (patch 5). [Matthias]
* Split reserved memory updates between SoC and platform (patch 6). [Matthias]
Sibi Sankar (10):
dt-bindings: remoteproc: qcom: pas: Add SC7280 MPSS support
remoteproc: qcom: pas: Add SC7280 Modem support
dt-bindings: remoteproc: qcom: Update Q6V5 Modem PIL binding
iommu/arm-smmu-qcom: Request direct mapping for modem device
remoteproc: mss: q6v5-mss: Add modem support on SC7280
arm64: dts: qcom: sc7280: Update reserved memory map
arm64: dts: qcom: sc7280: Add/Delete/Update reserved memory nodes
arm64: dts: qcom: sc7280: Add nodes to boot modem
arm64: dts: qcom: sc7280: Add Q6V5 MSS node
arm64: dts: qcom: sc7280: Update Q6V5 MSS node
.../devicetree/bindings/remoteproc/qcom,adsp.yaml | 5 +
.../devicetree/bindings/remoteproc/qcom,q6v5.txt | 32 ++-
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 59 +++++
arch/arm64/boot/dts/qcom/sc7280.dtsi | 107 +++++++++
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
drivers/remoteproc/qcom_q6v5_mss.c | 253 ++++++++++++++++++++-
drivers/remoteproc/qcom_q6v5_pas.c | 1 +
7 files changed, 452 insertions(+), 6 deletions(-)
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [relevance 17%]
* RE: [PATCH v3 2/3] dt-bindings: remoteproc: qcom: Add SC7280 WPSS support
@ 2021-09-17 10:26 0% ` pillair
1 sibling, 0 replies; 200+ results
From: pillair @ 2021-09-17 10:26 UTC (permalink / raw)
To: 'Stephen Boyd',
agross, bjorn.andersson, mathieu.poirier, ohad, p.zabel, robh+dt
Cc: linux-arm-msm, devicetree, linux-kernel, sibis, mpubbise, kuabhs
> -----Original Message-----
> From: Stephen Boyd <swboyd@chromium.org>
> Sent: Friday, September 17, 2021 11:56 AM
> To: Rakesh Pillai <pillair@codeaurora.org>; agross@kernel.org;
> bjorn.andersson@linaro.org; mathieu.poirier@linaro.org; ohad@wizery.com;
> p.zabel@pengutronix.de; robh+dt@kernel.org
> Cc: linux-arm-msm@vger.kernel.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; sibis@codeaurora.org; mpubbise@codeaurora.org;
> kuabhs@chromium.org
> Subject: Re: [PATCH v3 2/3] dt-bindings: remoteproc: qcom: Add SC7280
> WPSS support
>
> Quoting Rakesh Pillai (2021-09-16 09:55:52)
> > @@ -78,6 +84,10 @@ properties:
> > Phandle reference to a syscon representing TCSR followed by the
> > three offsets within syscon for q6, modem and nc halt registers.
> >
> > + qcom,qmp:
> > + $ref: /schemas/types.yaml#/definitions/phandle
> > + description: Reference to the AOSS side-channel message RAM.
> > +
> > qcom,smem-states:
> > $ref: /schemas/types.yaml#/definitions/phandle-array
> > description: States used by the AP to signal the Hexagon core @@
> > -117,6 +127,33 @@ allOf:
> > compatible:
> > contains:
> > enum:
> > + - qcom,sc7280-wpss-pil
> > + then:
>
> Honestly I find this if/else to be a huge tangle. Why not split the binding so
> that each compatible is a different file? Then it is easier to read and see what
> properties to set.
Hi Stephen,
I will create a separate dt-bindings yaml file for sc7280-wpss-pil, which will avoid all such if-else conditions.
>
> > + properties:
> > + interrupts-extended:
> > + maxItems: 6
> > + items:
> > + - description: Watchdog interrupt
> > + - description: Fatal interrupt
> > + - description: Ready interrupt
^ permalink raw reply [relevance 0%]
* RE: [PATCH v3] arm64: dts: qcom: sc7280: Add WPSS remoteproc node
@ 2021-09-17 8:04 0% ` pillair
0 siblings, 0 replies; 200+ results
From: pillair @ 2021-09-17 8:04 UTC (permalink / raw)
To: 'Stephen Boyd', agross, bjorn.andersson, robh+dt
Cc: linux-arm-msm, devicetree, linux-kernel, sibis, mpubbise, kuabhs
> -----Original Message-----
> From: Stephen Boyd <swboyd@chromium.org>
> Sent: Friday, September 17, 2021 6:25 AM
> To: Rakesh Pillai <pillair@codeaurora.org>; agross@kernel.org;
> bjorn.andersson@linaro.org; robh+dt@kernel.org
> Cc: linux-arm-msm@vger.kernel.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; sibis@codeaurora.org; mpubbise@codeaurora.org;
> kuabhs@chromium.org
> Subject: Re: [PATCH v3] arm64: dts: qcom: sc7280: Add WPSS remoteproc
> node
>
> Quoting Rakesh Pillai (2021-09-16 09:52:01)
> > diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> > b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> > index 64fc22a..2b8bbcd 100644
> > --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> > +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> > @@ -1423,6 +1433,59 @@
> > #power-domain-cells = <1>;
> > };
> >
> > + remoteproc_wpss: remoteproc@8a00000 {
> > + compatible = "qcom,sc7280-wpss-pil";
> > + reg = <0 0x08a00000 0 0x10000>;
> > +
> > + interrupts-extended = <&intc GIC_SPI 587
> IRQ_TYPE_EDGE_RISING>,
> > + <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
> > + <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
> > + <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
> > + <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
> > + <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
> > + interrupt-names = "wdog", "fatal", "ready", "handover",
> > + "stop-ack", "shutdown-ack";
> > +
> > + clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>,
> > + <&gcc GCC_WPSS_AHB_CLK>,
> > + <&gcc GCC_WPSS_RSCP_CLK>,
> > + <&rpmhcc RPMH_CXO_CLK>;
> > + clock-names = "gcc_wpss_ahb_bdg_mst_clk",
> > + "gcc_wpss_ahb_clk",
> > + "gcc_wpss_rscp_clk",
> > + "xo";
> > +
> > + power-domains = <&rpmhpd SC7280_CX>,
> > + <&rpmhpd SC7280_MX>;
> > + power-domain-names = "cx", "mx";
> > +
> > + memory-region = <&wpss_mem>;
> > +
> > + qcom,qmp = <&aoss_qmp>;
> > +
> > + qcom,smem-states = <&wpss_smp2p_out 0>;
> > + qcom,smem-state-names = "stop";
> > +
> > + resets = <&aoss_reset AOSS_CC_WCSS_RESTART>,
> > + <&pdc_reset PDC_WPSS_SYNC_RESET>;
> > + reset-names = "restart", "pdc_sync";
> > +
> > + qcom,halt-regs = <&tcsr_mutex_regs 0x37000>;
>
> Where is this node defined? I don't see it on the mailing list for sc7280. Can
> you indicate what patches this depends on, and use git format-patch --base=
> so we can try to find them ourselves.
Hi Stephen,
My bad, it shud be "tcsr_mutex" instead of "tcsr_mutex_regs".
I will correct it and send v4.
^ permalink raw reply [relevance 0%]
* [PATCH 5.14 274/432] arm64: dts: qcom: sm8250: Fix epss_l3 unit address
@ 2021-09-16 16:00 6% ` Greg Kroah-Hartman
0 siblings, 0 replies; 200+ results
From: Greg Kroah-Hartman @ 2021-09-16 16:00 UTC (permalink / raw)
To: linux-kernel
Cc: Greg Kroah-Hartman, stable, Georgi Djakov, Dmitry Baryshkov,
Sibi Sankar, Bjorn Andersson, Sasha Levin
From: Georgi Djakov <georgi.djakov@linaro.org>
[ Upstream commit 77b53d65dc1e54321ec841912f06bcb558a079c0 ]
The unit address of the epss_l3 node is incorrect and does not match
the address of its "reg" property. Let's fix it.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Sibi Sankar <sibis@codeaurora.org>
Link: https://lore.kernel.org/r/20210211193637.9737-1-georgi.djakov@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 9a6eff1813a6..7f7c8f467bfc 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -3955,7 +3955,7 @@ apps_bcm_voter: bcm_voter {
};
};
- epss_l3: interconnect@18591000 {
+ epss_l3: interconnect@18590000 {
compatible = "qcom,sm8250-epss-l3";
reg = <0 0x18590000 0 0x1000>;
--
2.30.2
^ permalink raw reply related [relevance 6%]
* [PATCH 5.13 243/380] arm64: dts: qcom: sm8250: Fix epss_l3 unit address
@ 2021-09-16 16:00 6% ` Greg Kroah-Hartman
0 siblings, 0 replies; 200+ results
From: Greg Kroah-Hartman @ 2021-09-16 16:00 UTC (permalink / raw)
To: linux-kernel
Cc: Greg Kroah-Hartman, stable, Georgi Djakov, Dmitry Baryshkov,
Sibi Sankar, Bjorn Andersson, Sasha Levin
From: Georgi Djakov <georgi.djakov@linaro.org>
[ Upstream commit 77b53d65dc1e54321ec841912f06bcb558a079c0 ]
The unit address of the epss_l3 node is incorrect and does not match
the address of its "reg" property. Let's fix it.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Sibi Sankar <sibis@codeaurora.org>
Link: https://lore.kernel.org/r/20210211193637.9737-1-georgi.djakov@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 1316bea3eab5..6d28bfd9a8f5 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -3773,7 +3773,7 @@ apps_bcm_voter: bcm_voter {
};
};
- epss_l3: interconnect@18591000 {
+ epss_l3: interconnect@18590000 {
compatible = "qcom,sm8250-epss-l3";
reg = <0 0x18590000 0 0x1000>;
--
2.30.2
^ permalink raw reply related [relevance 6%]
* [PATCH 5.10 195/306] arm64: dts: qcom: sm8250: Fix epss_l3 unit address
@ 2021-09-16 15:59 6% ` Greg Kroah-Hartman
0 siblings, 0 replies; 200+ results
From: Greg Kroah-Hartman @ 2021-09-16 15:59 UTC (permalink / raw)
To: linux-kernel
Cc: Greg Kroah-Hartman, stable, Georgi Djakov, Dmitry Baryshkov,
Sibi Sankar, Bjorn Andersson, Sasha Levin
From: Georgi Djakov <georgi.djakov@linaro.org>
[ Upstream commit 77b53d65dc1e54321ec841912f06bcb558a079c0 ]
The unit address of the epss_l3 node is incorrect and does not match
the address of its "reg" property. Let's fix it.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Sibi Sankar <sibis@codeaurora.org>
Link: https://lore.kernel.org/r/20210211193637.9737-1-georgi.djakov@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index d4547a192748..ec356fe07ac8 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -2346,7 +2346,7 @@ apps_bcm_voter: bcm_voter {
};
};
- epss_l3: interconnect@18591000 {
+ epss_l3: interconnect@18590000 {
compatible = "qcom,sm8250-epss-l3";
reg = <0 0x18590000 0 0x1000>;
--
2.30.2
^ permalink raw reply related [relevance 6%]
* [PATCH v7 09/13] arm64: dts: qcom: sm8250: Use QMP property to control load state
2021-09-16 13:59 9% [PATCH v7 00/13] Use qmp_send to update co-processor load state Sibi Sankar
` (7 preceding siblings ...)
2021-09-16 13:59 17% ` [PATCH v7 08/13] arm64: dts: qcom: sm8150: " Sibi Sankar
@ 2021-09-16 13:59 17% ` Sibi Sankar
2021-09-16 13:59 16% ` [PATCH v7 10/13] arm64: dts: qcom: sm8350: " Sibi Sankar
` (3 subsequent siblings)
12 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-09-16 13:59 UTC (permalink / raw)
To: mka, swboyd, bjorn.andersson, robh+dt
Cc: ulf.hansson, rjw, agross, ohad, mathieu.poirier, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel, dianders, rishabhb,
sidgup, Sibi Sankar
Use the Qualcomm Mailbox Protocol (QMP) property to control the load
state resources on SM8250 SoCs and drop deprecated power-domains exposed
by AOSS QMP node.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 8c15d9fed08f..2796b27f7c04 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -13,7 +13,6 @@
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sm8250.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
-#include <dt-bindings/power/qcom-aoss-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,apr.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
@@ -2088,13 +2087,14 @@
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
- <&rpmhpd SM8250_LCX>,
+ power-domains = <&rpmhpd SM8250_LCX>,
<&rpmhpd SM8250_LMX>;
- power-domain-names = "load_state", "lcx", "lmx";
+ power-domain-names = "lcx", "lmx";
memory-region = <&slpi_mem>;
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&smp2p_slpi_out 0>;
qcom,smem-state-names = "stop";
@@ -2154,12 +2154,12 @@
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
- <&rpmhpd SM8250_CX>;
- power-domain-names = "load_state", "cx";
+ power-domains = <&rpmhpd SM8250_CX>;
memory-region = <&cdsp_mem>;
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&smp2p_cdsp_out 0>;
qcom,smem-state-names = "stop";
@@ -2907,7 +2907,6 @@
IPCC_MPROC_SIGNAL_GLINK_QMP>;
#clock-cells = <0>;
- #power-domain-cells = <1>;
};
spmi_bus: spmi@c440000 {
@@ -3824,13 +3823,14 @@
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
- <&rpmhpd SM8250_LCX>,
+ power-domains = <&rpmhpd SM8250_LCX>,
<&rpmhpd SM8250_LMX>;
- power-domain-names = "load_state", "lcx", "lmx";
+ power-domain-names = "lcx", "lmx";
memory-region = <&adsp_mem>;
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&smp2p_adsp_out 0>;
qcom,smem-state-names = "stop";
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 17%]
* [PATCH v7 13/13] dt-bindings: soc: qcom: aoss: Delete unused power-domain definitions
2021-09-16 13:59 9% [PATCH v7 00/13] Use qmp_send to update co-processor load state Sibi Sankar
` (11 preceding siblings ...)
2021-09-16 13:59 19% ` [PATCH v7 12/13] dt-bindings: msm/dp: Remove aoss-qmp header Sibi Sankar
@ 2021-09-16 13:59 19% ` Sibi Sankar
12 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-09-16 13:59 UTC (permalink / raw)
To: mka, swboyd, bjorn.andersson, robh+dt
Cc: ulf.hansson, rjw, agross, ohad, mathieu.poirier, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel, dianders, rishabhb,
sidgup, Sibi Sankar
Delete unused power-domain definitions exposed by AOSS QMP.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
---
include/dt-bindings/power/qcom-aoss-qmp.h | 14 --------------
1 file changed, 14 deletions(-)
delete mode 100644 include/dt-bindings/power/qcom-aoss-qmp.h
diff --git a/include/dt-bindings/power/qcom-aoss-qmp.h b/include/dt-bindings/power/qcom-aoss-qmp.h
deleted file mode 100644
index ec336d31dee4..000000000000
--- a/include/dt-bindings/power/qcom-aoss-qmp.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* Copyright (c) 2018, Linaro Ltd. */
-
-#ifndef __DT_BINDINGS_POWER_QCOM_AOSS_QMP_H
-#define __DT_BINDINGS_POWER_QCOM_AOSS_QMP_H
-
-#define AOSS_QMP_LS_CDSP 0
-#define AOSS_QMP_LS_LPASS 1
-#define AOSS_QMP_LS_MODEM 2
-#define AOSS_QMP_LS_SLPI 3
-#define AOSS_QMP_LS_SPSS 4
-#define AOSS_QMP_LS_VENUS 5
-
-#endif
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 19%]
* [PATCH v7 12/13] dt-bindings: msm/dp: Remove aoss-qmp header
2021-09-16 13:59 9% [PATCH v7 00/13] Use qmp_send to update co-processor load state Sibi Sankar
` (10 preceding siblings ...)
2021-09-16 13:59 15% ` [PATCH v7 11/13] soc: qcom: aoss: Drop power domain support Sibi Sankar
@ 2021-09-16 13:59 19% ` Sibi Sankar
2021-09-16 13:59 19% ` [PATCH v7 13/13] dt-bindings: soc: qcom: aoss: Delete unused power-domain definitions Sibi Sankar
12 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-09-16 13:59 UTC (permalink / raw)
To: mka, swboyd, bjorn.andersson, robh+dt
Cc: ulf.hansson, rjw, agross, ohad, mathieu.poirier, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel, dianders, rishabhb,
sidgup, Sibi Sankar
Remove the unused aoss-qmp header from the list of includes.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
Documentation/devicetree/bindings/display/msm/dp-controller.yaml | 1 -
1 file changed, 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
index 64d8d9e5e47a..d89b3c510c27 100644
--- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
@@ -95,7 +95,6 @@ examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,dispcc-sc7180.h>
- #include <dt-bindings/power/qcom-aoss-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
displayport-controller@ae90000 {
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 19%]
* [PATCH v7 07/13] arm64: dts: qcom: sdm845: Use QMP property to control load state
2021-09-16 13:59 9% [PATCH v7 00/13] Use qmp_send to update co-processor load state Sibi Sankar
` (5 preceding siblings ...)
2021-09-16 13:59 18% ` [PATCH v7 06/13] arm64: dts: qcom: sc7280: " Sibi Sankar
@ 2021-09-16 13:59 18% ` Sibi Sankar
2021-09-16 13:59 17% ` [PATCH v7 08/13] arm64: dts: qcom: sm8150: " Sibi Sankar
` (5 subsequent siblings)
12 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-09-16 13:59 UTC (permalink / raw)
To: mka, swboyd, bjorn.andersson, robh+dt
Cc: ulf.hansson, rjw, agross, ohad, mathieu.poirier, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel, dianders, rishabhb,
sidgup, Sibi Sankar
Use the Qualcomm Mailbox Protocol (QMP) property to control the load
state resources on SDM845 SoCs and drop deprecated power-domains exposed
by AOSS QMP node.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
v7:
* Let's not miss adding qcom,qmp to ADSP/CDSP on SDM845 SoC.
arch/arm64/boot/dts/qcom/sdm845.dtsi | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index d18f7b419d2e..39c136e25fb5 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -763,6 +763,8 @@
memory-region = <&adsp_mem>;
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&adsp_smp2p_out 0>;
qcom,smem-state-names = "stop";
@@ -862,6 +864,8 @@
memory-region = <&cdsp_mem>;
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&cdsp_smp2p_out 0>;
qcom,smem-state-names = "stop";
@@ -2979,6 +2983,8 @@
clock-names = "iface", "bus", "mem", "gpll0_mss",
"snoc_axi", "mnoc_axi", "prng", "xo";
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&modem_smp2p_out 0>;
qcom,smem-state-names = "stop";
@@ -2988,11 +2994,10 @@
qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
- power-domains = <&aoss_qmp 2>,
- <&rpmhpd SDM845_CX>,
+ power-domains = <&rpmhpd SDM845_CX>,
<&rpmhpd SDM845_MX>,
<&rpmhpd SDM845_MSS>;
- power-domain-names = "load_state", "cx", "mx", "mss";
+ power-domain-names = "cx", "mx", "mss";
mba {
memory-region = <&mba_region>;
@@ -4607,7 +4612,6 @@
mboxes = <&apss_shared 0>;
#clock-cells = <0>;
- #power-domain-cells = <1>;
cx_cdev: cx {
#cooling-cells = <2>;
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 18%]
* [PATCH v7 08/13] arm64: dts: qcom: sm8150: Use QMP property to control load state
2021-09-16 13:59 9% [PATCH v7 00/13] Use qmp_send to update co-processor load state Sibi Sankar
` (6 preceding siblings ...)
2021-09-16 13:59 18% ` [PATCH v7 07/13] arm64: dts: qcom: sdm845: " Sibi Sankar
@ 2021-09-16 13:59 17% ` Sibi Sankar
2021-09-16 13:59 17% ` [PATCH v7 09/13] arm64: dts: qcom: sm8250: " Sibi Sankar
` (4 subsequent siblings)
12 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-09-16 13:59 UTC (permalink / raw)
To: mka, swboyd, bjorn.andersson, robh+dt
Cc: ulf.hansson, rjw, agross, ohad, mathieu.poirier, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel, dianders, rishabhb,
sidgup, Sibi Sankar
Use the Qualcomm Mailbox Protocol (QMP) property to control the load
state resources on SM8150 SoCs and drop deprecated power-domains exposed
by AOSS QMP node.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 28 ++++++++++++++--------------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index ef0232c2cf45..8a035693b7a3 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -6,7 +6,6 @@
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/power/qcom-aoss-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
@@ -1729,13 +1728,14 @@
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
- <&rpmhpd 3>,
+ power-domains = <&rpmhpd 3>,
<&rpmhpd 2>;
- power-domain-names = "load_state", "lcx", "lmx";
+ power-domain-names = "lcx", "lmx";
memory-region = <&slpi_mem>;
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&slpi_smp2p_out 0>;
qcom,smem-state-names = "stop";
@@ -2319,13 +2319,14 @@
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
- <&rpmhpd 7>,
+ power-domains = <&rpmhpd 7>,
<&rpmhpd 0>;
- power-domain-names = "load_state", "cx", "mss";
+ power-domain-names = "cx", "mss";
memory-region = <&mpss_mem>;
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&modem_smp2p_out 0>;
qcom,smem-state-names = "stop";
@@ -2945,12 +2946,12 @@
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
- <&rpmhpd 7>;
- power-domain-names = "load_state", "cx";
+ power-domains = <&rpmhpd 7>;
memory-region = <&cdsp_mem>;
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&cdsp_smp2p_out 0>;
qcom,smem-state-names = "stop";
@@ -3174,7 +3175,6 @@
mboxes = <&apss_shared 0>;
#clock-cells = <0>;
- #power-domain-cells = <1>;
};
tsens0: thermal-sensor@c263000 {
@@ -3321,12 +3321,12 @@
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
- <&rpmhpd 7>;
- power-domain-names = "load_state", "cx";
+ power-domains = <&rpmhpd 7>;
memory-region = <&adsp_mem>;
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&adsp_smp2p_out 0>;
qcom,smem-state-names = "stop";
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 17%]
* [PATCH v7 10/13] arm64: dts: qcom: sm8350: Use QMP property to control load state
2021-09-16 13:59 9% [PATCH v7 00/13] Use qmp_send to update co-processor load state Sibi Sankar
` (8 preceding siblings ...)
2021-09-16 13:59 17% ` [PATCH v7 09/13] arm64: dts: qcom: sm8250: " Sibi Sankar
@ 2021-09-16 13:59 16% ` Sibi Sankar
2021-09-16 13:59 15% ` [PATCH v7 11/13] soc: qcom: aoss: Drop power domain support Sibi Sankar
` (2 subsequent siblings)
12 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-09-16 13:59 UTC (permalink / raw)
To: mka, swboyd, bjorn.andersson, robh+dt
Cc: ulf.hansson, rjw, agross, ohad, mathieu.poirier, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel, dianders, rishabhb,
sidgup, Sibi Sankar
Use the Qualcomm Mailbox Protocol (QMP) property to control the load
state resources on SM8350 SoCs and drop deprecated power-domains exposed
by AOSS QMP node.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 30 ++++++++++++++++--------------
1 file changed, 16 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index e91cd8a5e535..6c83cd52a279 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -8,7 +8,6 @@
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interconnect/qcom,sm8350.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
-#include <dt-bindings/power/qcom-aoss-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/thermal/thermal.h>
@@ -726,15 +725,16 @@
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
- <&rpmhpd 0>,
+ power-domains = <&rpmhpd 0>,
<&rpmhpd 12>;
- power-domain-names = "load_state", "cx", "mss";
+ power-domain-names = "cx", "mss";
interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
memory-region = <&pil_modem_mem>;
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&smp2p_modem_out 0>;
qcom,smem-state-names = "stop";
@@ -794,7 +794,6 @@
mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
#clock-cells = <0>;
- #power-domain-cells = <1>;
};
spmi_bus: spmi@c440000 {
@@ -1107,13 +1106,14 @@
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
- <&rpmhpd 4>,
+ power-domains = <&rpmhpd 4>,
<&rpmhpd 5>;
- power-domain-names = "load_state", "lcx", "lmx";
+ power-domain-names = "lcx", "lmx";
memory-region = <&pil_slpi_mem>;
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&smp2p_slpi_out 0>;
qcom,smem-state-names = "stop";
@@ -1147,15 +1147,16 @@
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
- <&rpmhpd 0>,
+ power-domains = <&rpmhpd 0>,
<&rpmhpd 10>;
- power-domain-names = "load_state", "cx", "mxc";
+ power-domain-names = "cx", "mxc";
interconnects = <&compute_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>;
memory-region = <&pil_cdsp_mem>;
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&smp2p_cdsp_out 0>;
qcom,smem-state-names = "stop";
@@ -1381,13 +1382,14 @@
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
- <&rpmhpd 4>,
+ power-domains = <&rpmhpd 4>,
<&rpmhpd 5>;
- power-domain-names = "load_state", "lcx", "lmx";
+ power-domain-names = "lcx", "lmx";
memory-region = <&pil_adsp_mem>;
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&smp2p_adsp_out 0>;
qcom,smem-state-names = "stop";
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 16%]
* [PATCH v7 06/13] arm64: dts: qcom: sc7280: Use QMP property to control load state
2021-09-16 13:59 9% [PATCH v7 00/13] Use qmp_send to update co-processor load state Sibi Sankar
` (4 preceding siblings ...)
2021-09-16 13:59 18% ` [PATCH v7 05/13] arm64: dts: qcom: sc7180: Use QMP property to control " Sibi Sankar
@ 2021-09-16 13:59 18% ` Sibi Sankar
2021-09-16 13:59 18% ` [PATCH v7 07/13] arm64: dts: qcom: sdm845: " Sibi Sankar
` (6 subsequent siblings)
12 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-09-16 13:59 UTC (permalink / raw)
To: mka, swboyd, bjorn.andersson, robh+dt
Cc: ulf.hansson, rjw, agross, ohad, mathieu.poirier, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel, dianders, rishabhb,
sidgup, Sibi Sankar
Use the Qualcomm Mailbox Protocol (QMP) property to control the load
state resources on SC7280 SoCs and drop deprecated power-domains exposed
by AOSS QMP node.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index fd78f16181dd..89ed7f2b5583 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -10,7 +10,6 @@
#include <dt-bindings/interconnect/qcom,sc7280.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
-#include <dt-bindings/power/qcom-aoss-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/reset/qcom,sdm845-aoss.h>
#include <dt-bindings/reset/qcom,sdm845-pdc.h>
@@ -1481,7 +1480,6 @@
IPCC_MPROC_SIGNAL_GLINK_QMP>;
#clock-cells = <0>;
- #power-domain-cells = <1>;
};
spmi_bus: spmi@c440000 {
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 18%]
* [PATCH v7 11/13] soc: qcom: aoss: Drop power domain support
2021-09-16 13:59 9% [PATCH v7 00/13] Use qmp_send to update co-processor load state Sibi Sankar
` (9 preceding siblings ...)
2021-09-16 13:59 16% ` [PATCH v7 10/13] arm64: dts: qcom: sm8350: " Sibi Sankar
@ 2021-09-16 13:59 15% ` Sibi Sankar
2021-09-16 13:59 19% ` [PATCH v7 12/13] dt-bindings: msm/dp: Remove aoss-qmp header Sibi Sankar
2021-09-16 13:59 19% ` [PATCH v7 13/13] dt-bindings: soc: qcom: aoss: Delete unused power-domain definitions Sibi Sankar
12 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-09-16 13:59 UTC (permalink / raw)
To: mka, swboyd, bjorn.andersson, robh+dt
Cc: ulf.hansson, rjw, agross, ohad, mathieu.poirier, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel, dianders, rishabhb,
sidgup, Sibi Sankar
Strip out the load state power-domain support from the driver since the
low power mode signalling for the co-processors is now accessible through
the direct qmp message send interface.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
drivers/soc/qcom/qcom_aoss.c | 107 -------------------------------------------
1 file changed, 107 deletions(-)
diff --git a/drivers/soc/qcom/qcom_aoss.c b/drivers/soc/qcom/qcom_aoss.c
index 9fb74aa7c9ab..d650012ca19c 100644
--- a/drivers/soc/qcom/qcom_aoss.c
+++ b/drivers/soc/qcom/qcom_aoss.c
@@ -2,7 +2,6 @@
/*
* Copyright (c) 2019, Linaro Ltd
*/
-#include <dt-bindings/power/qcom-aoss-qmp.h>
#include <linux/clk-provider.h>
#include <linux/debugfs.h>
#include <linux/interrupt.h>
@@ -11,7 +10,6 @@
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
-#include <linux/pm_domain.h>
#include <linux/thermal.h>
#include <linux/slab.h>
#include <linux/soc/qcom/qcom_aoss.h>
@@ -67,7 +65,6 @@ struct qmp_cooling_device {
* @event: wait_queue for synchronization with the IRQ
* @tx_lock: provides synchronization between multiple callers of qmp_send()
* @qdss_clk: QDSS clock hw struct
- * @pd_data: genpd data
* @cooling_devs: thermal cooling devices
*/
struct qmp {
@@ -85,18 +82,10 @@ struct qmp {
struct mutex tx_lock;
struct clk_hw qdss_clk;
- struct genpd_onecell_data pd_data;
struct qmp_cooling_device *cooling_devs;
struct dentry *debugfs_file;
};
-struct qmp_pd {
- struct qmp *qmp;
- struct generic_pm_domain pd;
-};
-
-#define to_qmp_pd_resource(res) container_of(res, struct qmp_pd, pd)
-
static void qmp_kick(struct qmp *qmp)
{
mbox_send_message(qmp->mbox_chan, NULL);
@@ -322,95 +311,6 @@ static void qmp_qdss_clk_remove(struct qmp *qmp)
clk_hw_unregister(&qmp->qdss_clk);
}
-static int qmp_pd_power_toggle(struct qmp_pd *res, bool enable)
-{
- char buf[QMP_MSG_LEN] = {};
-
- snprintf(buf, sizeof(buf),
- "{class: image, res: load_state, name: %s, val: %s}",
- res->pd.name, enable ? "on" : "off");
- return qmp_send(res->qmp, buf, sizeof(buf));
-}
-
-static int qmp_pd_power_on(struct generic_pm_domain *domain)
-{
- return qmp_pd_power_toggle(to_qmp_pd_resource(domain), true);
-}
-
-static int qmp_pd_power_off(struct generic_pm_domain *domain)
-{
- return qmp_pd_power_toggle(to_qmp_pd_resource(domain), false);
-}
-
-static const char * const sdm845_resources[] = {
- [AOSS_QMP_LS_CDSP] = "cdsp",
- [AOSS_QMP_LS_LPASS] = "adsp",
- [AOSS_QMP_LS_MODEM] = "modem",
- [AOSS_QMP_LS_SLPI] = "slpi",
- [AOSS_QMP_LS_SPSS] = "spss",
- [AOSS_QMP_LS_VENUS] = "venus",
-};
-
-static int qmp_pd_add(struct qmp *qmp)
-{
- struct genpd_onecell_data *data = &qmp->pd_data;
- struct device *dev = qmp->dev;
- struct qmp_pd *res;
- size_t num = ARRAY_SIZE(sdm845_resources);
- int ret;
- int i;
-
- res = devm_kcalloc(dev, num, sizeof(*res), GFP_KERNEL);
- if (!res)
- return -ENOMEM;
-
- data->domains = devm_kcalloc(dev, num, sizeof(*data->domains),
- GFP_KERNEL);
- if (!data->domains)
- return -ENOMEM;
-
- for (i = 0; i < num; i++) {
- res[i].qmp = qmp;
- res[i].pd.name = sdm845_resources[i];
- res[i].pd.power_on = qmp_pd_power_on;
- res[i].pd.power_off = qmp_pd_power_off;
-
- ret = pm_genpd_init(&res[i].pd, NULL, true);
- if (ret < 0) {
- dev_err(dev, "failed to init genpd\n");
- goto unroll_genpds;
- }
-
- data->domains[i] = &res[i].pd;
- }
-
- data->num_domains = i;
-
- ret = of_genpd_add_provider_onecell(dev->of_node, data);
- if (ret < 0)
- goto unroll_genpds;
-
- return 0;
-
-unroll_genpds:
- for (i--; i >= 0; i--)
- pm_genpd_remove(data->domains[i]);
-
- return ret;
-}
-
-static void qmp_pd_remove(struct qmp *qmp)
-{
- struct genpd_onecell_data *data = &qmp->pd_data;
- struct device *dev = qmp->dev;
- int i;
-
- of_genpd_del_provider(dev->of_node);
-
- for (i = 0; i < data->num_domains; i++)
- pm_genpd_remove(data->domains[i]);
-}
-
static int qmp_cdev_get_max_state(struct thermal_cooling_device *cdev,
unsigned long *state)
{
@@ -641,10 +541,6 @@ static int qmp_probe(struct platform_device *pdev)
if (ret)
goto err_close_qmp;
- ret = qmp_pd_add(qmp);
- if (ret)
- goto err_remove_qdss_clk;
-
ret = qmp_cooling_devices_register(qmp);
if (ret)
dev_err(&pdev->dev, "failed to register aoss cooling devices\n");
@@ -656,8 +552,6 @@ static int qmp_probe(struct platform_device *pdev)
return 0;
-err_remove_qdss_clk:
- qmp_qdss_clk_remove(qmp);
err_close_qmp:
qmp_close(qmp);
err_free_mbox:
@@ -673,7 +567,6 @@ static int qmp_remove(struct platform_device *pdev)
debugfs_remove(qmp->debugfs_file);
qmp_qdss_clk_remove(qmp);
- qmp_pd_remove(qmp);
qmp_cooling_devices_remove(qmp);
qmp_close(qmp);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 15%]
* [PATCH v7 05/13] arm64: dts: qcom: sc7180: Use QMP property to control load state
2021-09-16 13:59 9% [PATCH v7 00/13] Use qmp_send to update co-processor load state Sibi Sankar
` (3 preceding siblings ...)
2021-09-16 13:59 8% ` [PATCH v7 04/13] remoteproc: qcom: q6v5: Use qmp_send to update co-processor load state Sibi Sankar
@ 2021-09-16 13:59 18% ` Sibi Sankar
2021-09-16 13:59 18% ` [PATCH v7 06/13] arm64: dts: qcom: sc7280: " Sibi Sankar
` (7 subsequent siblings)
12 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-09-16 13:59 UTC (permalink / raw)
To: mka, swboyd, bjorn.andersson, robh+dt
Cc: ulf.hansson, rjw, agross, ohad, mathieu.poirier, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel, dianders, rishabhb,
sidgup, Sibi Sankar
Use the Qualcomm Mailbox Protocol (QMP) property to control the load
state resources on SC7180 SoCs and drop deprecated power-domains exposed
by AOSS QMP node.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index c8921e2d6480..24ee106b933a 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -15,7 +15,6 @@
#include <dt-bindings/interconnect/qcom,sc7180.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy-qcom-qusb2.h>
-#include <dt-bindings/power/qcom-aoss-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/reset/qcom,sdm845-aoss.h>
#include <dt-bindings/reset/qcom,sdm845-pdc.h>
@@ -1922,14 +1921,15 @@
clock-names = "iface", "bus", "nav", "snoc_axi",
"mnoc_axi", "xo";
- power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
- <&rpmhpd SC7180_CX>,
+ power-domains = <&rpmhpd SC7180_CX>,
<&rpmhpd SC7180_MX>,
<&rpmhpd SC7180_MSS>;
- power-domain-names = "load_state", "cx", "mx", "mss";
+ power-domain-names = "cx", "mx", "mss";
memory-region = <&mpss_mem>;
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&modem_smp2p_out 0>;
qcom,smem-state-names = "stop";
@@ -3224,7 +3224,6 @@
mboxes = <&apss_shared 0>;
#clock-cells = <0>;
- #power-domain-cells = <1>;
};
spmi_bus: spmi@c440000 {
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 18%]
* [PATCH v7 03/13] dt-bindings: remoteproc: qcom: Add QMP property
2021-09-16 13:59 9% [PATCH v7 00/13] Use qmp_send to update co-processor load state Sibi Sankar
2021-09-16 13:59 17% ` [PATCH v7 01/13] dt-bindings: soc: qcom: aoss: Drop the load state power-domain Sibi Sankar
2021-09-16 13:59 15% ` [PATCH v7 02/13] dt-bindings: remoteproc: qcom: pas: Add QMP property Sibi Sankar
@ 2021-09-16 13:59 18% ` Sibi Sankar
2021-09-16 13:59 8% ` [PATCH v7 04/13] remoteproc: qcom: q6v5: Use qmp_send to update co-processor load state Sibi Sankar
` (9 subsequent siblings)
12 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-09-16 13:59 UTC (permalink / raw)
To: mka, swboyd, bjorn.andersson, robh+dt
Cc: ulf.hansson, rjw, agross, ohad, mathieu.poirier, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel, dianders, rishabhb,
sidgup, Sibi Sankar
Add Qualcomm Mailbox Protocol (QMP) property to replace the power domain
exposed by the AOSS QMP node.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
index 69c49c7b2cff..494257010629 100644
--- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
@@ -174,7 +174,12 @@ For the compatible string below the following supplies are required:
must be "cx", "mx"
qcom,sc7180-mss-pil:
qcom,sdm845-mss-pil:
- must be "cx", "mx", "mss", "load_state"
+ must be "cx", "mx", "mss"
+
+- qcom,qmp:
+ Usage: optional
+ Value type: <phandle>
+ Definition: reference to the AOSS side-channel message RAM.
- qcom,smem-states:
Usage: required
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 18%]
* [PATCH v7 04/13] remoteproc: qcom: q6v5: Use qmp_send to update co-processor load state
2021-09-16 13:59 9% [PATCH v7 00/13] Use qmp_send to update co-processor load state Sibi Sankar
` (2 preceding siblings ...)
2021-09-16 13:59 18% ` [PATCH v7 03/13] dt-bindings: remoteproc: qcom: " Sibi Sankar
@ 2021-09-16 13:59 8% ` Sibi Sankar
2021-09-16 13:59 18% ` [PATCH v7 05/13] arm64: dts: qcom: sc7180: Use QMP property to control " Sibi Sankar
` (8 subsequent siblings)
12 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-09-16 13:59 UTC (permalink / raw)
To: mka, swboyd, bjorn.andersson, robh+dt
Cc: ulf.hansson, rjw, agross, ohad, mathieu.poirier, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel, dianders, rishabhb,
sidgup, Sibi Sankar
The power domains exposed by the AOSS QMP driver control the load state
resources linked to modem, adsp, cdsp remoteprocs. These are used to
notify the Always on Subsystem (AOSS) that a particular co-processor is
up/down. AOSS uses this information to wait for the co-processors to
suspend before starting its sleep sequence.
These co-processors enter low-power modes independent to that of the
application processor and the load state resources linked to them are
expected to remain unaltered across system suspend/resume cycles. To
achieve this behavior lets stop using the power-domains exposed by the
AOSS QMP node and replace them with generic qmp_send interface instead.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
v7:
* Let's not miss adding qcom,qmp to ADSP/CDSP on SDM845 SoC.
drivers/remoteproc/qcom_q6v5.c | 57 +++++++++++++++++-
drivers/remoteproc/qcom_q6v5.h | 7 ++-
drivers/remoteproc/qcom_q6v5_adsp.c | 7 ++-
drivers/remoteproc/qcom_q6v5_mss.c | 44 +++-----------
drivers/remoteproc/qcom_q6v5_pas.c | 113 ++++++++++++++----------------------
drivers/remoteproc/qcom_q6v5_wcss.c | 4 +-
6 files changed, 122 insertions(+), 110 deletions(-)
diff --git a/drivers/remoteproc/qcom_q6v5.c b/drivers/remoteproc/qcom_q6v5.c
index 7e9244c748da..eada7e34f3af 100644
--- a/drivers/remoteproc/qcom_q6v5.c
+++ b/drivers/remoteproc/qcom_q6v5.c
@@ -16,8 +16,30 @@
#include "qcom_common.h"
#include "qcom_q6v5.h"
+#define Q6V5_LOAD_STATE_MSG_LEN 64
#define Q6V5_PANIC_DELAY_MS 200
+static int q6v5_load_state_toggle(struct qcom_q6v5 *q6v5, bool enable)
+{
+ char buf[Q6V5_LOAD_STATE_MSG_LEN];
+ int ret;
+
+ if (!q6v5->qmp)
+ return 0;
+
+ ret = snprintf(buf, sizeof(buf),
+ "{class: image, res: load_state, name: %s, val: %s}",
+ q6v5->load_state, enable ? "on" : "off");
+
+ WARN_ON(ret >= Q6V5_LOAD_STATE_MSG_LEN);
+
+ ret = qmp_send(q6v5->qmp, buf, sizeof(buf));
+ if (ret)
+ dev_err(q6v5->dev, "failed to toggle load state\n");
+
+ return ret;
+}
+
/**
* qcom_q6v5_prepare() - reinitialize the qcom_q6v5 context before start
* @q6v5: reference to qcom_q6v5 context to be reinitialized
@@ -26,6 +48,12 @@
*/
int qcom_q6v5_prepare(struct qcom_q6v5 *q6v5)
{
+ int ret;
+
+ ret = q6v5_load_state_toggle(q6v5, true);
+ if (ret)
+ return ret;
+
reinit_completion(&q6v5->start_done);
reinit_completion(&q6v5->stop_done);
@@ -47,6 +75,7 @@ EXPORT_SYMBOL_GPL(qcom_q6v5_prepare);
int qcom_q6v5_unprepare(struct qcom_q6v5 *q6v5)
{
disable_irq(q6v5->handover_irq);
+ q6v5_load_state_toggle(q6v5, false);
return !q6v5->handover_issued;
}
@@ -196,12 +225,13 @@ EXPORT_SYMBOL_GPL(qcom_q6v5_panic);
* @pdev: platform_device reference for acquiring resources
* @rproc: associated remoteproc instance
* @crash_reason: SMEM id for crash reason string, or 0 if none
+ * @load_state: load state resource string
* @handover: function to be called when proxy resources should be released
*
* Return: 0 on success, negative errno on failure
*/
int qcom_q6v5_init(struct qcom_q6v5 *q6v5, struct platform_device *pdev,
- struct rproc *rproc, int crash_reason,
+ struct rproc *rproc, int crash_reason, const char *load_state,
void (*handover)(struct qcom_q6v5 *q6v5))
{
int ret;
@@ -286,9 +316,34 @@ int qcom_q6v5_init(struct qcom_q6v5 *q6v5, struct platform_device *pdev,
return PTR_ERR(q6v5->state);
}
+ q6v5->load_state = devm_kstrdup_const(&pdev->dev, load_state, GFP_KERNEL);
+ q6v5->qmp = qmp_get(&pdev->dev);
+ if (IS_ERR(q6v5->qmp)) {
+ if (PTR_ERR(q6v5->qmp) != -ENODEV)
+ return dev_err_probe(&pdev->dev, PTR_ERR(q6v5->qmp),
+ "failed to acquire load state\n");
+ q6v5->qmp = NULL;
+ } else if (!q6v5->load_state) {
+ if (!load_state)
+ dev_err(&pdev->dev, "load state resource string empty\n");
+
+ qmp_put(q6v5->qmp);
+ return load_state ? -ENOMEM : -EINVAL;
+ }
+
return 0;
}
EXPORT_SYMBOL_GPL(qcom_q6v5_init);
+/**
+ * qcom_q6v5_deinit() - deinitialize the q6v5 common struct
+ * @q6v5: reference to qcom_q6v5 context to be deinitialized
+ */
+void qcom_q6v5_deinit(struct qcom_q6v5 *q6v5)
+{
+ qmp_put(q6v5->qmp);
+}
+EXPORT_SYMBOL_GPL(qcom_q6v5_deinit);
+
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("Qualcomm Peripheral Image Loader for Q6V5");
diff --git a/drivers/remoteproc/qcom_q6v5.h b/drivers/remoteproc/qcom_q6v5.h
index 1c212f670cbc..f35e04471ed7 100644
--- a/drivers/remoteproc/qcom_q6v5.h
+++ b/drivers/remoteproc/qcom_q6v5.h
@@ -5,6 +5,7 @@
#include <linux/kernel.h>
#include <linux/completion.h>
+#include <linux/soc/qcom/qcom_aoss.h>
struct rproc;
struct qcom_smem_state;
@@ -15,6 +16,8 @@ struct qcom_q6v5 {
struct rproc *rproc;
struct qcom_smem_state *state;
+ struct qmp *qmp;
+
unsigned stop_bit;
int wdog_irq;
@@ -32,12 +35,14 @@ struct qcom_q6v5 {
bool running;
+ const char *load_state;
void (*handover)(struct qcom_q6v5 *q6v5);
};
int qcom_q6v5_init(struct qcom_q6v5 *q6v5, struct platform_device *pdev,
- struct rproc *rproc, int crash_reason,
+ struct rproc *rproc, int crash_reason, const char *load_state,
void (*handover)(struct qcom_q6v5 *q6v5));
+void qcom_q6v5_deinit(struct qcom_q6v5 *q6v5);
int qcom_q6v5_prepare(struct qcom_q6v5 *q6v5);
int qcom_q6v5_unprepare(struct qcom_q6v5 *q6v5);
diff --git a/drivers/remoteproc/qcom_q6v5_adsp.c b/drivers/remoteproc/qcom_q6v5_adsp.c
index 8b0d8bbacd2e..098362e6e233 100644
--- a/drivers/remoteproc/qcom_q6v5_adsp.c
+++ b/drivers/remoteproc/qcom_q6v5_adsp.c
@@ -185,7 +185,9 @@ static int adsp_start(struct rproc *rproc)
int ret;
unsigned int val;
- qcom_q6v5_prepare(&adsp->q6v5);
+ ret = qcom_q6v5_prepare(&adsp->q6v5);
+ if (ret)
+ return ret;
ret = clk_prepare_enable(adsp->xo);
if (ret)
@@ -465,7 +467,7 @@ static int adsp_probe(struct platform_device *pdev)
if (ret)
goto disable_pm;
- ret = qcom_q6v5_init(&adsp->q6v5, pdev, rproc, desc->crash_reason_smem,
+ ret = qcom_q6v5_init(&adsp->q6v5, pdev, rproc, desc->crash_reason_smem, NULL,
qcom_adsp_pil_handover);
if (ret)
goto disable_pm;
@@ -500,6 +502,7 @@ static int adsp_remove(struct platform_device *pdev)
rproc_del(adsp->rproc);
+ qcom_q6v5_deinit(&adsp->q6v5);
qcom_remove_glink_subdev(adsp->rproc, &adsp->glink_subdev);
qcom_remove_sysmon_subdev(adsp->sysmon);
qcom_remove_ssr_subdev(adsp->rproc, &adsp->ssr_subdev);
diff --git a/drivers/remoteproc/qcom_q6v5_mss.c b/drivers/remoteproc/qcom_q6v5_mss.c
index 423b31dfa574..7a1422bd7925 100644
--- a/drivers/remoteproc/qcom_q6v5_mss.c
+++ b/drivers/remoteproc/qcom_q6v5_mss.c
@@ -137,7 +137,6 @@ struct rproc_hexagon_res {
char **proxy_clk_names;
char **reset_clk_names;
char **active_clk_names;
- char **active_pd_names;
char **proxy_pd_names;
int version;
bool need_mem_protection;
@@ -169,12 +168,10 @@ struct q6v5 {
struct clk *active_clks[8];
struct clk *reset_clks[4];
struct clk *proxy_clks[4];
- struct device *active_pds[1];
struct device *proxy_pds[3];
int active_clk_count;
int reset_clk_count;
int proxy_clk_count;
- int active_pd_count;
int proxy_pd_count;
struct reg_info active_regs[1];
@@ -895,18 +892,14 @@ static int q6v5_mba_load(struct q6v5 *qproc)
int xfermemop_ret;
bool mba_load_err = false;
- qcom_q6v5_prepare(&qproc->q6v5);
-
- ret = q6v5_pds_enable(qproc, qproc->active_pds, qproc->active_pd_count);
- if (ret < 0) {
- dev_err(qproc->dev, "failed to enable active power domains\n");
- goto disable_irqs;
- }
+ ret = qcom_q6v5_prepare(&qproc->q6v5);
+ if (ret)
+ return ret;
ret = q6v5_pds_enable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
if (ret < 0) {
dev_err(qproc->dev, "failed to enable proxy power domains\n");
- goto disable_active_pds;
+ goto disable_irqs;
}
ret = q6v5_regulator_enable(qproc, qproc->fallback_proxy_regs,
@@ -1039,8 +1032,6 @@ static int q6v5_mba_load(struct q6v5 *qproc)
qproc->fallback_proxy_reg_count);
disable_proxy_pds:
q6v5_pds_disable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
-disable_active_pds:
- q6v5_pds_disable(qproc, qproc->active_pds, qproc->active_pd_count);
disable_irqs:
qcom_q6v5_unprepare(&qproc->q6v5);
@@ -1076,7 +1067,6 @@ static void q6v5_mba_reclaim(struct q6v5 *qproc)
qproc->active_clk_count);
q6v5_regulator_disable(qproc, qproc->active_regs,
qproc->active_reg_count);
- q6v5_pds_disable(qproc, qproc->active_pds, qproc->active_pd_count);
/* In case of failure or coredump scenario where reclaiming MBA memory
* could not happen reclaim it here.
@@ -1756,14 +1746,6 @@ static int q6v5_probe(struct platform_device *pdev)
}
qproc->active_reg_count = ret;
- ret = q6v5_pds_attach(&pdev->dev, qproc->active_pds,
- desc->active_pd_names);
- if (ret < 0) {
- dev_err(&pdev->dev, "Failed to attach active power domains\n");
- goto free_rproc;
- }
- qproc->active_pd_count = ret;
-
ret = q6v5_pds_attach(&pdev->dev, qproc->proxy_pds,
desc->proxy_pd_names);
/* Fallback to regulators for old device trees */
@@ -1773,12 +1755,12 @@ static int q6v5_probe(struct platform_device *pdev)
desc->fallback_proxy_supply);
if (ret < 0) {
dev_err(&pdev->dev, "Failed to get fallback proxy regulators.\n");
- goto detach_active_pds;
+ goto free_rproc;
}
qproc->fallback_proxy_reg_count = ret;
} else if (ret < 0) {
dev_err(&pdev->dev, "Failed to init power domains\n");
- goto detach_active_pds;
+ goto free_rproc;
} else {
qproc->proxy_pd_count = ret;
}
@@ -1792,7 +1774,7 @@ static int q6v5_probe(struct platform_device *pdev)
qproc->need_mem_protection = desc->need_mem_protection;
qproc->has_mba_logs = desc->has_mba_logs;
- ret = qcom_q6v5_init(&qproc->q6v5, pdev, rproc, MPSS_CRASH_REASON_SMEM,
+ ret = qcom_q6v5_init(&qproc->q6v5, pdev, rproc, MPSS_CRASH_REASON_SMEM, "modem",
qcom_msa_handover);
if (ret)
goto detach_proxy_pds;
@@ -1822,8 +1804,6 @@ static int q6v5_probe(struct platform_device *pdev)
qcom_remove_glink_subdev(rproc, &qproc->glink_subdev);
detach_proxy_pds:
q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
-detach_active_pds:
- q6v5_pds_detach(qproc, qproc->active_pds, qproc->active_pd_count);
free_rproc:
rproc_free(rproc);
@@ -1837,13 +1817,13 @@ static int q6v5_remove(struct platform_device *pdev)
rproc_del(rproc);
+ qcom_q6v5_deinit(&qproc->q6v5);
qcom_remove_sysmon_subdev(qproc->sysmon);
qcom_remove_ssr_subdev(rproc, &qproc->ssr_subdev);
qcom_remove_smd_subdev(rproc, &qproc->smd_subdev);
qcom_remove_glink_subdev(rproc, &qproc->glink_subdev);
q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
- q6v5_pds_detach(qproc, qproc->active_pds, qproc->active_pd_count);
rproc_free(rproc);
@@ -1867,10 +1847,6 @@ static const struct rproc_hexagon_res sc7180_mss = {
"nav",
NULL
},
- .active_pd_names = (char*[]){
- "load_state",
- NULL
- },
.proxy_pd_names = (char*[]){
"cx",
"mx",
@@ -1903,10 +1879,6 @@ static const struct rproc_hexagon_res sdm845_mss = {
"mnoc_axi",
NULL
},
- .active_pd_names = (char*[]){
- "load_state",
- NULL
- },
.proxy_pd_names = (char*[]){
"cx",
"mx",
diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q6v5_pas.c
index 401b1ec90785..8da0362d3d85 100644
--- a/drivers/remoteproc/qcom_q6v5_pas.c
+++ b/drivers/remoteproc/qcom_q6v5_pas.c
@@ -37,9 +37,9 @@ struct adsp_data {
bool has_aggre2_clk;
bool auto_boot;
- char **active_pd_names;
char **proxy_pd_names;
+ const char *load_state;
const char *ssr_name;
const char *sysmon_name;
int ssctl_id;
@@ -57,10 +57,8 @@ struct qcom_adsp {
struct regulator *cx_supply;
struct regulator *px_supply;
- struct device *active_pds[1];
struct device *proxy_pds[3];
- int active_pd_count;
int proxy_pd_count;
int pas_id;
@@ -149,15 +147,13 @@ static int adsp_start(struct rproc *rproc)
struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
int ret;
- qcom_q6v5_prepare(&adsp->q6v5);
-
- ret = adsp_pds_enable(adsp, adsp->active_pds, adsp->active_pd_count);
- if (ret < 0)
- goto disable_irqs;
+ ret = qcom_q6v5_prepare(&adsp->q6v5);
+ if (ret)
+ return ret;
ret = adsp_pds_enable(adsp, adsp->proxy_pds, adsp->proxy_pd_count);
if (ret < 0)
- goto disable_active_pds;
+ goto disable_irqs;
ret = clk_prepare_enable(adsp->xo);
if (ret)
@@ -201,8 +197,6 @@ static int adsp_start(struct rproc *rproc)
clk_disable_unprepare(adsp->xo);
disable_proxy_pds:
adsp_pds_disable(adsp, adsp->proxy_pds, adsp->proxy_pd_count);
-disable_active_pds:
- adsp_pds_disable(adsp, adsp->active_pds, adsp->active_pd_count);
disable_irqs:
qcom_q6v5_unprepare(&adsp->q6v5);
@@ -234,7 +228,6 @@ static int adsp_stop(struct rproc *rproc)
if (ret)
dev_err(adsp->dev, "failed to shutdown: %d\n", ret);
- adsp_pds_disable(adsp, adsp->active_pds, adsp->active_pd_count);
handover = qcom_q6v5_unprepare(&adsp->q6v5);
if (handover)
qcom_pas_handover(&adsp->q6v5);
@@ -456,19 +449,13 @@ static int adsp_probe(struct platform_device *pdev)
if (ret)
goto free_rproc;
- ret = adsp_pds_attach(&pdev->dev, adsp->active_pds,
- desc->active_pd_names);
- if (ret < 0)
- goto free_rproc;
- adsp->active_pd_count = ret;
-
ret = adsp_pds_attach(&pdev->dev, adsp->proxy_pds,
desc->proxy_pd_names);
if (ret < 0)
- goto detach_active_pds;
+ goto free_rproc;
adsp->proxy_pd_count = ret;
- ret = qcom_q6v5_init(&adsp->q6v5, pdev, rproc, desc->crash_reason_smem,
+ ret = qcom_q6v5_init(&adsp->q6v5, pdev, rproc, desc->crash_reason_smem, desc->load_state,
qcom_pas_handover);
if (ret)
goto detach_proxy_pds;
@@ -492,8 +479,6 @@ static int adsp_probe(struct platform_device *pdev)
detach_proxy_pds:
adsp_pds_detach(adsp, adsp->proxy_pds, adsp->proxy_pd_count);
-detach_active_pds:
- adsp_pds_detach(adsp, adsp->active_pds, adsp->active_pd_count);
free_rproc:
rproc_free(rproc);
@@ -506,6 +491,7 @@ static int adsp_remove(struct platform_device *pdev)
rproc_del(adsp->rproc);
+ qcom_q6v5_deinit(&adsp->q6v5);
qcom_remove_glink_subdev(adsp->rproc, &adsp->glink_subdev);
qcom_remove_sysmon_subdev(adsp->sysmon);
qcom_remove_smd_subdev(adsp->rproc, &adsp->smd_subdev);
@@ -526,20 +512,29 @@ static const struct adsp_data adsp_resource_init = {
.ssctl_id = 0x14,
};
+static const struct adsp_data sdm845_adsp_resource_init = {
+ .crash_reason_smem = 423,
+ .firmware_name = "adsp.mdt",
+ .pas_id = 1,
+ .has_aggre2_clk = false,
+ .auto_boot = true,
+ .load_state = "adsp",
+ .ssr_name = "lpass",
+ .sysmon_name = "adsp",
+ .ssctl_id = 0x14,
+};
+
static const struct adsp_data sm8150_adsp_resource = {
.crash_reason_smem = 423,
.firmware_name = "adsp.mdt",
.pas_id = 1,
.has_aggre2_clk = false,
.auto_boot = true,
- .active_pd_names = (char*[]){
- "load_state",
- NULL
- },
.proxy_pd_names = (char*[]){
"cx",
NULL
},
+ .load_state = "adsp",
.ssr_name = "lpass",
.sysmon_name = "adsp",
.ssctl_id = 0x14,
@@ -551,15 +546,12 @@ static const struct adsp_data sm8250_adsp_resource = {
.pas_id = 1,
.has_aggre2_clk = false,
.auto_boot = true,
- .active_pd_names = (char*[]){
- "load_state",
- NULL
- },
.proxy_pd_names = (char*[]){
"lcx",
"lmx",
NULL
},
+ .load_state = "adsp",
.ssr_name = "lpass",
.sysmon_name = "adsp",
.ssctl_id = 0x14,
@@ -571,15 +563,12 @@ static const struct adsp_data sm8350_adsp_resource = {
.pas_id = 1,
.has_aggre2_clk = false,
.auto_boot = true,
- .active_pd_names = (char*[]){
- "load_state",
- NULL
- },
.proxy_pd_names = (char*[]){
"lcx",
"lmx",
NULL
},
+ .load_state = "adsp",
.ssr_name = "lpass",
.sysmon_name = "adsp",
.ssctl_id = 0x14,
@@ -611,20 +600,29 @@ static const struct adsp_data cdsp_resource_init = {
.ssctl_id = 0x17,
};
+static const struct adsp_data sdm845_cdsp_resource_init = {
+ .crash_reason_smem = 601,
+ .firmware_name = "cdsp.mdt",
+ .pas_id = 18,
+ .has_aggre2_clk = false,
+ .auto_boot = true,
+ .load_state = "cdsp",
+ .ssr_name = "cdsp",
+ .sysmon_name = "cdsp",
+ .ssctl_id = 0x17,
+};
+
static const struct adsp_data sm8150_cdsp_resource = {
.crash_reason_smem = 601,
.firmware_name = "cdsp.mdt",
.pas_id = 18,
.has_aggre2_clk = false,
.auto_boot = true,
- .active_pd_names = (char*[]){
- "load_state",
- NULL
- },
.proxy_pd_names = (char*[]){
"cx",
NULL
},
+ .load_state = "cdsp",
.ssr_name = "cdsp",
.sysmon_name = "cdsp",
.ssctl_id = 0x17,
@@ -636,14 +634,11 @@ static const struct adsp_data sm8250_cdsp_resource = {
.pas_id = 18,
.has_aggre2_clk = false,
.auto_boot = true,
- .active_pd_names = (char*[]){
- "load_state",
- NULL
- },
.proxy_pd_names = (char*[]){
"cx",
NULL
},
+ .load_state = "cdsp",
.ssr_name = "cdsp",
.sysmon_name = "cdsp",
.ssctl_id = 0x17,
@@ -655,14 +650,11 @@ static const struct adsp_data sm8350_cdsp_resource = {
.pas_id = 18,
.has_aggre2_clk = false,
.auto_boot = true,
- .active_pd_names = (char*[]){
- "load_state",
- NULL
- },
.proxy_pd_names = (char*[]){
"cx",
NULL
},
+ .load_state = "cdsp",
.ssr_name = "cdsp",
.sysmon_name = "cdsp",
.ssctl_id = 0x17,
@@ -675,15 +667,12 @@ static const struct adsp_data mpss_resource_init = {
.minidump_id = 3,
.has_aggre2_clk = false,
.auto_boot = false,
- .active_pd_names = (char*[]){
- "load_state",
- NULL
- },
.proxy_pd_names = (char*[]){
"cx",
"mss",
NULL
},
+ .load_state = "modem",
.ssr_name = "mpss",
.sysmon_name = "modem",
.ssctl_id = 0x12,
@@ -695,14 +684,11 @@ static const struct adsp_data sc8180x_mpss_resource = {
.pas_id = 4,
.has_aggre2_clk = false,
.auto_boot = false,
- .active_pd_names = (char*[]){
- "load_state",
- NULL
- },
.proxy_pd_names = (char*[]){
"cx",
NULL
},
+ .load_state = "modem",
.ssr_name = "mpss",
.sysmon_name = "modem",
.ssctl_id = 0x12,
@@ -725,15 +711,12 @@ static const struct adsp_data sm8150_slpi_resource = {
.pas_id = 12,
.has_aggre2_clk = false,
.auto_boot = true,
- .active_pd_names = (char*[]){
- "load_state",
- NULL
- },
.proxy_pd_names = (char*[]){
"lcx",
"lmx",
NULL
},
+ .load_state = "slpi",
.ssr_name = "dsps",
.sysmon_name = "slpi",
.ssctl_id = 0x16,
@@ -745,15 +728,12 @@ static const struct adsp_data sm8250_slpi_resource = {
.pas_id = 12,
.has_aggre2_clk = false,
.auto_boot = true,
- .active_pd_names = (char*[]){
- "load_state",
- NULL
- },
.proxy_pd_names = (char*[]){
"lcx",
"lmx",
NULL
},
+ .load_state = "slpi",
.ssr_name = "dsps",
.sysmon_name = "slpi",
.ssctl_id = 0x16,
@@ -765,15 +745,12 @@ static const struct adsp_data sm8350_slpi_resource = {
.pas_id = 12,
.has_aggre2_clk = false,
.auto_boot = true,
- .active_pd_names = (char*[]){
- "load_state",
- NULL
- },
.proxy_pd_names = (char*[]){
"lcx",
"lmx",
NULL
},
+ .load_state = "slpi",
.ssr_name = "dsps",
.sysmon_name = "slpi",
.ssctl_id = 0x16,
@@ -834,8 +811,8 @@ static const struct of_device_id adsp_of_match[] = {
{ .compatible = "qcom,sc8180x-cdsp-pas", .data = &sm8150_cdsp_resource},
{ .compatible = "qcom,sc8180x-mpss-pas", .data = &sc8180x_mpss_resource},
{ .compatible = "qcom,sdm660-adsp-pas", .data = &adsp_resource_init},
- { .compatible = "qcom,sdm845-adsp-pas", .data = &adsp_resource_init},
- { .compatible = "qcom,sdm845-cdsp-pas", .data = &cdsp_resource_init},
+ { .compatible = "qcom,sdm845-adsp-pas", .data = &sdm845_adsp_resource_init},
+ { .compatible = "qcom,sdm845-cdsp-pas", .data = &sdm845_cdsp_resource_init},
{ .compatible = "qcom,sdx55-mpss-pas", .data = &sdx55_mpss_resource},
{ .compatible = "qcom,sm8150-adsp-pas", .data = &sm8150_adsp_resource},
{ .compatible = "qcom,sm8150-cdsp-pas", .data = &sm8150_cdsp_resource},
diff --git a/drivers/remoteproc/qcom_q6v5_wcss.c b/drivers/remoteproc/qcom_q6v5_wcss.c
index 20d50ec7eff1..0689288a2425 100644
--- a/drivers/remoteproc/qcom_q6v5_wcss.c
+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
@@ -1044,8 +1044,7 @@ static int q6v5_wcss_probe(struct platform_device *pdev)
if (ret)
goto free_rproc;
- ret = qcom_q6v5_init(&wcss->q6v5, pdev, rproc, desc->crash_reason_smem,
- NULL);
+ ret = qcom_q6v5_init(&wcss->q6v5, pdev, rproc, desc->crash_reason_smem, NULL, NULL);
if (ret)
goto free_rproc;
@@ -1075,6 +1074,7 @@ static int q6v5_wcss_remove(struct platform_device *pdev)
{
struct rproc *rproc = platform_get_drvdata(pdev);
+ qcom_q6v5_deinit(&qproc->q6v5);
rproc_del(rproc);
rproc_free(rproc);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 8%]
* [PATCH v7 00/13] Use qmp_send to update co-processor load state
@ 2021-09-16 13:59 9% Sibi Sankar
2021-09-16 13:59 17% ` [PATCH v7 01/13] dt-bindings: soc: qcom: aoss: Drop the load state power-domain Sibi Sankar
` (12 more replies)
0 siblings, 13 replies; 200+ results
From: Sibi Sankar @ 2021-09-16 13:59 UTC (permalink / raw)
To: mka, swboyd, bjorn.andersson, robh+dt
Cc: ulf.hansson, rjw, agross, ohad, mathieu.poirier, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel, dianders, rishabhb,
sidgup, Sibi Sankar
The power domains exposed by the AOSS QMP driver control the load state
resources linked to modem, adsp, cdsp remoteprocs. These are used to
notify the Always on Subsystem (AOSS) that a particular co-processor is
up/down. AOSS uses this information to wait for the co-processors to
suspend before starting its sleep sequence. These co-processors enter
low-power modes independent to that of the application processor and
the load state resources linked to them are expected to remain unaltered
across system suspend/resume cycles. To achieve this behavior let's stop
modeling them as power-domains and replace them with generic qmp_send
interface instead.
https://lore.kernel.org/lkml/20200913034603.GV3715@yoga/
Previous discussion on dropping power-domain support from AOSS QMP driver
Depends on:
qmp_send: https://patchwork.kernel.org/project/linux-arm-msm/cover/1630420228-31075-1-git-send-email-deesin@codeaurora.org/
V7:
* Set "qcom,qmp" property to false for unsupported devices (patch 2). [Rob]
* Let's not miss adding qcom,qmp to ADSP/CDSP on SDM845 SoC.
V6:
* Updated commit message to explain binding breakage (patch 2). [Stephen]
V5:
* Fixup power-domain count (patch 2). [Matthias]
* Add WARN_ON on truncation, remove redundant initialization
code, use dev_err_probe (patch 4). [Stephen]
* Use devm_kstrdup, handle kstrdup failure due to
no memory and set qmp to NULL when not available
(patch 4). [Bjorn]
V4:
* Rebase patch 1 due to the aoss-qmp yaml conversion (Dropping Rb).
* Commit message change and sc8180x co-processor addition
to patch 2. [Rob/Bjorn]
* Drop unused pdev and kfree the load state string in q6v5_deinit
/probe path for patch 4. [Matthias]
* Replaced "binding" with "property" across the series. [Matthias]
* Commit message change and drop incorrect cleanup on cooling
device probe failures. [Matthias]
V3:
* Misc. documentation fixes [patch 2]:
- Reduce power-domain maxItems due to load_state pd removal
- Combine compatibles where possible with the load_state pd removal
- Fixup the qcom,qmp ref to phandle type
V2:
* load_state is currently broken on mainline so be safely dropped
without side-effects.
* Rebased on top of qmp_send v3 series.
* Dropped R-b from Stephen and Rob on patch 3 due to the yaml
conversion.
* New patch [12] to drop unused aoss-qmp header.
* Commit message update [patch 1] [Rob]
* Reorder the series [Stephen]
Sibi Sankar (13):
dt-bindings: soc: qcom: aoss: Drop the load state power-domain
dt-bindings: remoteproc: qcom: pas: Add QMP property
dt-bindings: remoteproc: qcom: Add QMP property
remoteproc: qcom: q6v5: Use qmp_send to update co-processor load state
arm64: dts: qcom: sc7180: Use QMP property to control load state
arm64: dts: qcom: sc7280: Use QMP property to control load state
arm64: dts: qcom: sdm845: Use QMP property to control load state
arm64: dts: qcom: sm8150: Use QMP property to control load state
arm64: dts: qcom: sm8250: Use QMP property to control load state
arm64: dts: qcom: sm8350: Use QMP property to control load state
soc: qcom: aoss: Drop power domain support
dt-bindings: msm/dp: Remove aoss-qmp header
dt-bindings: soc: qcom: aoss: Delete unused power-domain definitions
.../bindings/display/msm/dp-controller.yaml | 1 -
.../devicetree/bindings/remoteproc/qcom,adsp.yaml | 54 +++++-----
.../devicetree/bindings/remoteproc/qcom,q6v5.txt | 7 +-
.../bindings/soc/qcom/qcom,aoss-qmp.yaml | 11 +-
arch/arm64/boot/dts/qcom/sc7180.dtsi | 9 +-
arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 -
arch/arm64/boot/dts/qcom/sdm845.dtsi | 12 ++-
arch/arm64/boot/dts/qcom/sm8150.dtsi | 28 ++---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 22 ++--
arch/arm64/boot/dts/qcom/sm8350.dtsi | 30 +++---
drivers/remoteproc/qcom_q6v5.c | 57 ++++++++++-
drivers/remoteproc/qcom_q6v5.h | 7 +-
drivers/remoteproc/qcom_q6v5_adsp.c | 7 +-
drivers/remoteproc/qcom_q6v5_mss.c | 44 ++------
drivers/remoteproc/qcom_q6v5_pas.c | 113 ++++++++-------------
drivers/remoteproc/qcom_q6v5_wcss.c | 4 +-
drivers/soc/qcom/qcom_aoss.c | 107 -------------------
include/dt-bindings/power/qcom-aoss-qmp.h | 14 ---
18 files changed, 206 insertions(+), 323 deletions(-)
delete mode 100644 include/dt-bindings/power/qcom-aoss-qmp.h
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [relevance 9%]
* [PATCH v7 01/13] dt-bindings: soc: qcom: aoss: Drop the load state power-domain
2021-09-16 13:59 9% [PATCH v7 00/13] Use qmp_send to update co-processor load state Sibi Sankar
@ 2021-09-16 13:59 17% ` Sibi Sankar
2021-09-16 13:59 15% ` [PATCH v7 02/13] dt-bindings: remoteproc: qcom: pas: Add QMP property Sibi Sankar
` (11 subsequent siblings)
12 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-09-16 13:59 UTC (permalink / raw)
To: mka, swboyd, bjorn.andersson, robh+dt
Cc: ulf.hansson, rjw, agross, ohad, mathieu.poirier, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel, dianders, rishabhb,
sidgup, Sibi Sankar
The power-domains exposed by AOSS QMP node are used to notify the Always
on Subsystem (AOSS) that a particular co-processor is up/down. These
co-processors enter low-power modes independent to that of the application
processor and their states are expected to remain unaltered across system
suspend/resume cycles. To achieve this behavior let's drop the load
power-domain and replace them with generic qmp_send interface instead.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml | 11 +----------
1 file changed, 1 insertion(+), 10 deletions(-)
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml
index 1904612fad85..e2e173dfada7 100644
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml
@@ -19,8 +19,7 @@ description:
The AOSS side channel exposes control over a set of resources, used to control
a set of debug related clocks and to affect the low power state of resources
- related to the secondary subsystems. These resources are exposed as a set of
- power-domains.
+ related to the secondary subsystems.
properties:
compatible:
@@ -58,13 +57,6 @@ properties:
description:
The single clock represents the QDSS clock.
- "#power-domain-cells":
- const: 1
- description: |
- The provided power-domains are:
- CDSP state (0), LPASS state (1), modem state (2), SLPI
- state (3), SPSS state (4) and Venus state (5).
-
required:
- compatible
- reg
@@ -102,7 +94,6 @@ examples:
mboxes = <&apss_shared 0>;
#clock-cells = <0>;
- #power-domain-cells = <1>;
cx_cdev: cx {
#cooling-cells = <2>;
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 17%]
* [PATCH v7 02/13] dt-bindings: remoteproc: qcom: pas: Add QMP property
2021-09-16 13:59 9% [PATCH v7 00/13] Use qmp_send to update co-processor load state Sibi Sankar
2021-09-16 13:59 17% ` [PATCH v7 01/13] dt-bindings: soc: qcom: aoss: Drop the load state power-domain Sibi Sankar
@ 2021-09-16 13:59 15% ` Sibi Sankar
2021-09-21 22:06 0% ` Rob Herring
2021-09-16 13:59 18% ` [PATCH v7 03/13] dt-bindings: remoteproc: qcom: " Sibi Sankar
` (10 subsequent siblings)
12 siblings, 1 reply; 200+ results
From: Sibi Sankar @ 2021-09-16 13:59 UTC (permalink / raw)
To: mka, swboyd, bjorn.andersson, robh+dt
Cc: ulf.hansson, rjw, agross, ohad, mathieu.poirier, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel, dianders, rishabhb,
sidgup, Sibi Sankar
The load state power-domain, used by the co-processors to notify the
Always on Subsystem (AOSS) that a particular co-processor is up/down,
suffers from the side-effect of changing states during suspend/resume.
However the co-processors enter low-power modes independent to that of
the application processor and their states are expected to remain
unaltered across system suspend/resume cycles. To achieve this behavior
let's drop the load state power-domain and replace them with the qmp
property for all SoCs supporting low power mode signalling.
Due to the current broken load state implementation, we can afford the
binding breakage that ensues and the remoteproc functionality will remain
the same when using newer kernels with older dtbs.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
v7:
* Set "qcom,qmp" property to false for unsupported devices. [Rob]
.../devicetree/bindings/remoteproc/qcom,adsp.yaml | 54 ++++++++++------------
1 file changed, 24 insertions(+), 30 deletions(-)
diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml
index 0c112f3264a9..ff265aa365de 100644
--- a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml
@@ -93,6 +93,10 @@ properties:
maxItems: 1
description: Reference to the reserved-memory for the Hexagon core
+ qcom,qmp:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: Reference to the AOSS side-channel message RAM.
+
qcom,smem-states:
$ref: /schemas/types.yaml#/definitions/phandle-array
description: States used by the AP to signal the Hexagon core
@@ -369,13 +373,11 @@ allOf:
properties:
power-domains:
items:
- - description: Load State power domain
- description: CX power domain
- description: MX power domain
- description: MSS power domain
power-domain-names:
items:
- - const: load_state
- const: cx
- const: mx
- const: mss
@@ -391,43 +393,20 @@ allOf:
properties:
power-domains:
items:
- - description: Load State power domain
- description: CX power domain
- power-domain-names:
- items:
- - const: load_state
- - const: cx
- if:
properties:
compatible:
contains:
enum:
+ - qcom,sdx55-mpss-pas
- qcom,sm8150-mpss-pas
- qcom,sm8350-mpss-pas
then:
properties:
power-domains:
items:
- - description: Load State power domain
- - description: CX power domain
- - description: MSS power domain
- power-domain-names:
- items:
- - const: load_state
- - const: cx
- - const: mss
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,sdx55-mpss-pas
- then:
- properties:
- power-domains:
- items:
- description: CX power domain
- description: MSS power domain
power-domain-names:
@@ -451,12 +430,10 @@ allOf:
properties:
power-domains:
items:
- - description: Load State power domain
- description: LCX power domain
- description: LMX power domain
power-domain-names:
items:
- - const: load_state
- const: lcx
- const: lmx
@@ -470,12 +447,10 @@ allOf:
properties:
power-domains:
items:
- - description: Load State power domain
- description: CX power domain
- description: MXC power domain
power-domain-names:
items:
- - const: load_state
- const: cx
- const: mxc
@@ -511,6 +486,25 @@ allOf:
- const: mss_restart
- const: pdc_reset
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,msm8974-adsp-pil
+ - qcom,msm8996-adsp-pil
+ - qcom,msm8996-slpi-pil
+ - qcom,msm8998-adsp-pas
+ - qcom,msm8998-slpi-pas
+ - qcom,qcs404-adsp-pas
+ - qcom,qcs404-cdsp-pas
+ - qcom,qcs404-wcss-pas
+ - qcom,sdm660-adsp-pas
+ - qcom,sdx55-mpss-pas
+ then:
+ properties:
+ qcom,qmp: false
+
examples:
- |
#include <dt-bindings/clock/qcom,rpmcc.h>
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 15%]
* Re: [PATCH v6 02/13] dt-bindings: remoteproc: qcom: pas: Add QMP property
2021-09-08 13:51 0% ` Rob Herring
@ 2021-09-16 3:13 6% ` Sibi Sankar
0 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-09-16 3:13 UTC (permalink / raw)
To: Rob Herring
Cc: mka, swboyd, bjorn.andersson, ulf.hansson, rjw, agross, ohad,
mathieu.poirier, linux-arm-msm, linux-remoteproc, devicetree,
linux-kernel, dianders, rishabhb, sidgup
Hey Rob,
Thanks for taking time to review
the series.
On 2021-09-08 19:21, Rob Herring wrote:
> On Mon, Sep 06, 2021 at 01:53:46PM +0530, Sibi Sankar wrote:
>> The load state power-domain, used by the co-processors to notify the
>> Always on Subsystem (AOSS) that a particular co-processor is up/down,
>> suffers from the side-effect of changing states during suspend/resume.
>> However the co-processors enter low-power modes independent to that of
>> the application processor and their states are expected to remain
>> unaltered across system suspend/resume cycles. To achieve this
>> behavior
>> let's drop the load state power-domain and replace them with the qmp
>> property for all SoCs supporting low power mode signalling.
>>
>> Due to the current broken load state implementation, we can afford the
>> binding breakage that ensues and the remoteproc functionality will
>> remain
>> the same when using newer kernels with older dtbs.
>>
>> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
>> Reviewed-by: Stephen Boyd <swboyd@chromium.org>
>> ---
>>
>> v6:
>> * Updated commit message to explain binding breakage. [Stephen]
>>
>> .../devicetree/bindings/remoteproc/qcom,adsp.yaml | 61
>> +++++++++++-----------
>> 1 file changed, 31 insertions(+), 30 deletions(-)
>>
>> diff --git
>> a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml
>> b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml
>> index 0c112f3264a9..0d2b5bd4907a 100644
>> --- a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml
>> +++ b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml
>> @@ -93,6 +93,10 @@ properties:
>> maxItems: 1
>> description: Reference to the reserved-memory for the Hexagon
>> core
>>
>> + qcom,qmp:
>> + $ref: /schemas/types.yaml#/definitions/phandle
>> + description: Reference to the AOSS side-channel message RAM.
>> +
>
> [...]
>
>> @@ -511,6 +486,32 @@ allOf:
>> - const: mss_restart
>> - const: pdc_reset
>>
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + enum:
>> + - qcom,sc7180-mpss-pas
>> + - qcom,sc8180x-adsp-pas
>> + - qcom,sc8180x-cdsp-pas
>> + - qcom,sc8180x-mpss-pas
>> + - qcom,sm8150-adsp-pas
>> + - qcom,sm8150-cdsp-pas
>> + - qcom,sm8150-mpss-pas
>> + - qcom,sm8150-slpi-pas
>> + - qcom,sm8250-adsp-pas
>> + - qcom,sm8250-cdsp-pas
>> + - qcom,sm8250-slpi-pas
>> + - qcom,sm8350-adsp-pas
>> + - qcom,sm8350-cdsp-pas
>> + - qcom,sm8350-mpss-pas
>> + - qcom,sm8350-slpi-pas
>> + then:
>> + properties:
>> + qcom,qmp:
>> + items:
>> + - description: Reference to the AOSS side-channel message
>> RAM.
>
> This doesn't do anything. The property is already allowed for all
> compatibles. Perhaps you want to negate the if and put 'qcom,qmp:
> false'
> here.
sure will fix it in the next re-spin.
>
> Rob
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply [relevance 6%]
* [PATCH 5.14 173/334] arm64: dts: qcom: sc7280: Fixup the cpufreq node
2021-09-13 13:10 2% [PATCH 5.14 000/334] 5.14.4-rc1 review Greg Kroah-Hartman
2021-09-13 13:12 8% ` [PATCH 5.14 103/334] soc: qcom: rpmhpd: Use corner in power_off Greg Kroah-Hartman
@ 2021-09-13 13:13 9% ` Greg Kroah-Hartman
1 sibling, 0 replies; 200+ results
From: Greg Kroah-Hartman @ 2021-09-13 13:13 UTC (permalink / raw)
To: linux-kernel
Cc: Greg Kroah-Hartman, stable, Sibi Sankar, Stephen Boyd,
Bjorn Andersson, Sasha Levin
From: Sibi Sankar <sibis@codeaurora.org>
[ Upstream commit 11e03d692101e484df9322f892a8b6e111a82bfd ]
Fixup the register regions used by the cpufreq node on SC7280 SoC to
support per core L3 DCVS.
Fixes: 7dbd121a2c58 ("arm64: dts: qcom: sc7280: Add cpufreq hw node")
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/1627581885-32165-4-git-send-email-sibis@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 188c5768a55a..c08f07410699 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -1437,9 +1437,9 @@
cpufreq_hw: cpufreq@18591000 {
compatible = "qcom,cpufreq-epss";
- reg = <0 0x18591000 0 0x1000>,
- <0 0x18592000 0 0x1000>,
- <0 0x18593000 0 0x1000>;
+ reg = <0 0x18591100 0 0x900>,
+ <0 0x18592100 0 0x900>,
+ <0 0x18593100 0 0x900>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
clock-names = "xo", "alternate";
#freq-domain-cells = <1>;
--
2.30.2
^ permalink raw reply related [relevance 9%]
* [PATCH 5.14 103/334] soc: qcom: rpmhpd: Use corner in power_off
2021-09-13 13:10 2% [PATCH 5.14 000/334] 5.14.4-rc1 review Greg Kroah-Hartman
@ 2021-09-13 13:12 8% ` Greg Kroah-Hartman
2021-09-13 13:13 9% ` [PATCH 5.14 173/334] arm64: dts: qcom: sc7280: Fixup the cpufreq node Greg Kroah-Hartman
1 sibling, 0 replies; 200+ results
From: Greg Kroah-Hartman @ 2021-09-13 13:12 UTC (permalink / raw)
To: linux-kernel
Cc: Greg Kroah-Hartman, stable, Rajendra Nayak, Stephen Boyd,
Sibi Sankar, Bjorn Andersson, Sasha Levin
From: Bjorn Andersson <bjorn.andersson@linaro.org>
[ Upstream commit d43b3a989bc8c06fd4bbb69a7500d180db2d68e8 ]
rpmhpd_aggregate_corner() takes a corner as parameter, but in
rpmhpd_power_off() the code requests the level of the first corner
instead.
In all (known) current cases the first corner has level 0, so this
change should be a nop, but in case that there's a power domain with a
non-zero lowest level this makes sure that rpmhpd_power_off() actually
requests the lowest level - which is the closest to "power off" we can
get.
While touching the code, also skip the unnecessary zero-initialization
of "ret".
Fixes: 279b7e8a62cc ("soc: qcom: rpmhpd: Add RPMh power domain driver")
Reviewed-by: Rajendra Nayak <rnayak@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Sibi Sankar <sibis@codeaurora.org>
Tested-by: Sibi Sankar <sibis@codeaurora.org>
Link: https://lore.kernel.org/r/20210703005416.2668319-2-bjorn.andersson@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
drivers/soc/qcom/rpmhpd.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/soc/qcom/rpmhpd.c b/drivers/soc/qcom/rpmhpd.c
index 2daa17ba54a3..fa209b479ab3 100644
--- a/drivers/soc/qcom/rpmhpd.c
+++ b/drivers/soc/qcom/rpmhpd.c
@@ -403,12 +403,11 @@ static int rpmhpd_power_on(struct generic_pm_domain *domain)
static int rpmhpd_power_off(struct generic_pm_domain *domain)
{
struct rpmhpd *pd = domain_to_rpmhpd(domain);
- int ret = 0;
+ int ret;
mutex_lock(&rpmhpd_lock);
- ret = rpmhpd_aggregate_corner(pd, pd->level[0]);
-
+ ret = rpmhpd_aggregate_corner(pd, 0);
if (!ret)
pd->enabled = false;
--
2.30.2
^ permalink raw reply related [relevance 8%]
* [PATCH 5.14 000/334] 5.14.4-rc1 review
@ 2021-09-13 13:10 2% Greg Kroah-Hartman
2021-09-13 13:12 8% ` [PATCH 5.14 103/334] soc: qcom: rpmhpd: Use corner in power_off Greg Kroah-Hartman
2021-09-13 13:13 9% ` [PATCH 5.14 173/334] arm64: dts: qcom: sc7280: Fixup the cpufreq node Greg Kroah-Hartman
0 siblings, 2 replies; 200+ results
From: Greg Kroah-Hartman @ 2021-09-13 13:10 UTC (permalink / raw)
To: linux-kernel
Cc: Greg Kroah-Hartman, torvalds, akpm, linux, shuah, patches,
lkft-triage, pavel, jonathanh, f.fainelli, stable
This is the start of the stable review cycle for the 5.14.4 release.
There are 334 patches in this series, all will be posted as a response
to this one. If anyone has any issues with these being applied, please
let me know.
Responses should be made by Wed, 15 Sep 2021 13:10:21 +0000.
Anything received after that time might be too late.
The whole patch series can be found in one patch at:
https://www.kernel.org/pub/linux/kernel/v5.x/stable-review/patch-5.14.4-rc1.gz
or in the git tree and branch at:
git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git linux-5.14.y
and the diffstat can be found below.
thanks,
greg k-h
-------------
Pseudo-Shortlog of commits:
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Linux 5.14.4-rc1
Linus Walleij <linus.walleij@linaro.org>
clk: kirkwood: Fix a clocking boot regression
Helge Deller <deller@gmx.de>
parisc: Fix unaligned-access crash in bootloader
Daniel Thompson <daniel.thompson@linaro.org>
backlight: pwm_bl: Improve bootloader/kernel device handover
Julio Faracco <jcfaracco@gmail.com>
bootconfig: Fix missing return check of xbc_node_compose_key function
Niklas Schnelle <schnelle@linux.ibm.com>
RDMA/mlx5: Fix number of allocated XLT entries
Aubrey Li <aubrey.li@intel.com>
ACPI: PRM: Find PRMT table before parsing it
Tetsuo Handa <penguin-kernel@i-love.sakura.ne.jp>
fbmem: don't allow too huge resolutions
THOBY Simon <Simon.THOBY@viveris.fr>
IMA: remove the dependency on CRYPTO_MD5
Austin Kim <austin.kim@lge.com>
IMA: remove -Wmissing-prototypes warning
Miklos Szeredi <mszeredi@redhat.com>
fuse: wait for writepages in syncfs
Miklos Szeredi <mszeredi@redhat.com>
fuse: flush extending writes
Miklos Szeredi <mszeredi@redhat.com>
fuse: truncate pagecache on atomic_o_trunc
Adrian Ratiu <adrian.ratiu@collabora.com>
char: tpm: Kconfig: remove bad i2c cr50 select
Xiao Ni <xni@redhat.com>
md/raid10: Remove unnecessary rcu_dereference in raid10_handle_discard
Jens Axboe <axboe@kernel.dk>
io-wq: check max_worker limits if a worker transitions bound state
Claudiu Beznea <claudiu.beznea@microchip.com>
ARM: dts: at91: add pinctrl-{names, 0} for all gpios
Marc Zyngier <maz@kernel.org>
KVM: arm64: vgic: Resample HW pending state on deactivation
Marc Zyngier <maz@kernel.org>
KVM: arm64: Unregister HYP sections from kmemleak in protected mode
Sean Christopherson <seanjc@google.com>
KVM: nVMX: Unconditionally clear nested.pi_pending on nested VM-Enter
Maxim Levitsky <mlevitsk@redhat.com>
KVM: VMX: avoid running vmx_handle_exit_irqoff in case of emulation
Sean Christopherson <seanjc@google.com>
KVM: x86/mmu: Avoid collision with !PRESENT SPTEs in TDP MMU lpage stats
Paolo Bonzini <pbonzini@redhat.com>
KVM: x86: clamp host mapping level to max_level in kvm_mmu_max_mapping_level
Zelin Deng <zelin.deng@linux.alibaba.com>
KVM: x86: Update vCPU's hv_clock before back to guest when tsc_offset is adjusted
Halil Pasic <pasic@linux.ibm.com>
KVM: s390: index kvm->arch.idle_mask by vcpu_idx
Sean Christopherson <seanjc@google.com>
Revert "KVM: x86: mmu: Add guest physical address check in translate_gpa()"
Alexander Antonov <alexander.antonov@linux.intel.com>
perf/x86/intel/uncore: Fix IIO cleanup mapping procedure for SNR/ICX
Nguyen Dinh Phi <phind.uet@gmail.com>
tty: Fix data race between tiocsti() and flush_to_ldisc()
Steve French <stfrench@microsoft.com>
smb3: fix posix extensions mount option
Ronnie Sahlberg <lsahlber@redhat.com>
cifs: Do not leak EDEADLK to dgetents64 for STATUS_USER_SESSION_DELETED
Guoqing Jiang <jiangguoqing@kylinos.cn>
raid1: ensure write behind bio has less than BIO_MAX_VECS sectors
Pavel Begunkov <asml.silence@gmail.com>
bio: fix page leak bio_add_hw_page failure
Pavel Begunkov <asml.silence@gmail.com>
io_uring: fail links of cancelled timeouts
Jens Axboe <axboe@kernel.dk>
io_uring: io_uring_complete() trace should take an integer
Jens Axboe <axboe@kernel.dk>
io_uring: IORING_OP_WRITE needs hash_reg_file set
Pavel Begunkov <asml.silence@gmail.com>
io_uring: limit fixed table size by RLIMIT_NOFILE
Lars Poeschel <poeschel@lemonage.de>
auxdisplay: hd44780: Fix oops on module unloading
Lukas Hannen <lukas.hannen@opensource.tttech-industrial.com>
time: Handle negative seconds correctly in timespec64_to_ns()
Jaegeuk Kim <jaegeuk@kernel.org>
f2fs: guarantee to write dirty data when enabling checkpoint back
Justin M. Forbes <jforbes@fedoraproject.org>
iwlwifi Add support for ax201 in Samsung Galaxy Book Flex2 Alpha
Douglas Anderson <dianders@chromium.org>
ASoC: rt5682: Remove unused variable in rt5682_i2c_remove()
Eric Dumazet <edumazet@google.com>
ipv4: fix endianness issue in inet_rtm_getroute_build_skb()
Sunil Goutham <sgoutham@marvell.com>
octeontx2-af: Set proper errorcode for IPv4 checksum errors
Subbaraya Sundeep <sbhatta@marvell.com>
octeontx2-af: Fix static code analyzer reported issues
Subbaraya Sundeep <sbhatta@marvell.com>
octeontx2-af: Fix mailbox errors in nix_rss_flowkey_cfg
Subbaraya Sundeep <sbhatta@marvell.com>
octeontx2-af: Fix loop in free and unmap counter
Stefan Wahren <stefan.wahren@i2se.com>
net: qualcomm: fix QCA7000 checksum handling
Xiyu Yang <xiyuyang19@fudan.edu.cn>
net: sched: Fix qdisc_rate_table refcount leak when get tcf_block failed
Maxim Mikityanskiy <maximmi@nvidia.com>
sch_htb: Fix inconsistency when leaf qdisc creation fails
Dan Carpenter <dan.carpenter@oracle.com>
net: qrtr: make checks in qrtr_endpoint_post() stricter
Eric Dumazet <edumazet@google.com>
ipv4: make exception cache less predictible
Eric Dumazet <edumazet@google.com>
ipv6: make exception cache less predictible
Ahmad Fatoum <a.fatoum@pengutronix.de>
brcmfmac: pcie: fix oops on failure to resume and reprobe
Zenghui Yu <yuzenghui@huawei.com>
bcma: Fix memory leak for internally-handled cores
Sudarsana Reddy Kalluru <skalluru@marvell.com>
atlantic: Fix driver resume flow.
Takashi Iwai <tiwai@suse.de>
ALSA: usb-audio: Add lowlatency module option
Dan Carpenter <dan.carpenter@oracle.com>
ath6kl: wmi: fix an error code in ath6kl_wmi_sync_point()
Vladimir Oltean <vladimir.oltean@nxp.com>
net: phy: marvell10g: fix broken PHY interrupts for anyone after us in the driver probe list
Brett Creeley <brett.creeley@intel.com>
ice: Only lock to update netdev dev_addr
Jacob Keller <jacob.e.keller@intel.com>
ice: restart periodic outputs around time changes
Jacob Keller <jacob.e.keller@intel.com>
ice: add lock around Tx timestamp tracker flush
Jacob Keller <jacob.e.keller@intel.com>
ice: fix Tx queue iteration for Tx timestamp enablement
Mihai Carabas <mihai.carabas@oracle.com>
misc/pvpanic: fix set driver data
Dmytro Linkin <dlinkin@nvidia.com>
net/mlx5e: Use correct eswitch for stack devices with lag
Maor Dickman <maord@nvidia.com>
net/mlx5: E-Switch, Set vhca id valid flag when creating indir fwd group
Roi Dayan <roid@nvidia.com>
net/mlx5e: Fix possible use-after-free deleting fdb rule
Leon Romanovsky <leon@kernel.org>
net/mlx5: Remove all auxiliary devices at the unregister event
Dima Chumak <dchumak@nvidia.com>
net/mlx5: Lag, fix multipath lag activation
Abhishek Naik <abhishek.naik@intel.com>
iwlwifi: skip first element in the WTAS ACPI table
Christophe JAILLET <christophe.jaillet@wanadoo.fr>
ASoC: wcd9335: Disable irq on slave ports in the remove function
Christophe JAILLET <christophe.jaillet@wanadoo.fr>
ASoC: wcd9335: Fix a memory leak in the error handling path of the probe function
Christophe JAILLET <christophe.jaillet@wanadoo.fr>
ASoC: wcd9335: Fix a double irq free in the remove function
Andy Duan <fugang.duan@nxp.com>
tty: serial: fsl_lpuart: fix the wrong mapbase value
Christophe JAILLET <christophe.jaillet@wanadoo.fr>
usb: bdc: Fix a resource leak in the error handling path of 'bdc_probe()'
Christophe JAILLET <christophe.jaillet@wanadoo.fr>
usb: bdc: Fix an error handling path in 'bdc_probe()' when no suitable DMA config is available
Evgeny Novikov <novikov@ispras.ru>
usb: ehci-orion: Handle errors of clk_prepare_enable() in probe
Yang Yingliang <yangyingliang@huawei.com>
octeontx2-pf: cn10k: Fix error return code in otx2_set_flowkey_cfg()
Sergey Shtylyov <s.shtylyov@omp.ru>
i2c: xlp9xx: fix main IRQ check
Sergey Shtylyov <s.shtylyov@omp.ru>
i2c: mt65xx: fix IRQ check
Len Baker <len.baker@gmx.com>
CIFS: Fix a potencially linear read overflow
Vitaly Kuznetsov <vkuznets@redhat.com>
hv_utils: Set the maximum packet size for VSS driver to the length of the receive buffer
Andrey Ignatov <rdna@fb.com>
bpf: Fix possible out of bound write in narrow load handling
Charles Keepax <ckeepax@opensource.cirrus.com>
ASoC: wm_adsp: Put debugfs_remove_recursive back in
Tony Lindgren <tony@atomide.com>
mmc: moxart: Fix issue with uninitialized dma_slave_config
Tony Lindgren <tony@atomide.com>
mmc: dw_mmc: Fix issue with uninitialized dma_slave_config
Tony Lindgren <tony@atomide.com>
mmc: sdhci: Fix issue with uninitialized dma_slave_config
Cezary Rojewski <cezary.rojewski@intel.com>
ASoC: Intel: Skylake: Fix module resource and format selection
Cezary Rojewski <cezary.rojewski@intel.com>
ASoC: Intel: Skylake: Leave data as is when invoking TLV IPCs
Cezary Rojewski <cezary.rojewski@intel.com>
ASoC: Intel: kbl_da7219_max98927: Fix format selection for max98373
Dan Carpenter <dan.carpenter@oracle.com>
m68k: coldfire: return success for clk_enable(NULL)
Geetha sowjanya <gakula@marvell.com>
octeontx2-af: cn10k: Use FLIT0 register instead of FLIT1
Sunil Goutham <sgoutham@marvell.com>
octeontx2-pf: Fix algorithm index in MCAM rules with RSS action
Sunil Goutham <sgoutham@marvell.com>
octeontx2-pf: Don't install VLAN offload rule if netdev is down
Geetha sowjanya <gakula@marvell.com>
octeontx2-af: Check capability flag while freeing ipolicer memory
Naveen Mamindlapalli <naveenm@marvell.com>
octeontx2-pf: send correct vlan priority mask to npc_install_flow_req
Subbaraya Sundeep <sbhatta@marvell.com>
octeontx2-af: cn10k: Fix SDP base channel number
Dan Carpenter <dan.carpenter@oracle.com>
rsi: fix an error code in rsi_probe()
Dan Carpenter <dan.carpenter@oracle.com>
rsi: fix error code in rsi_load_9116_firmware()
Wei Yongjun <weiyongjun1@huawei.com>
drm/exynos: g2d: fix missing unlock on error in g2d_runqueue_worker()
Bob Peterson <rpeterso@redhat.com>
gfs2: init system threads before freeze lock
Sergey Shtylyov <s.shtylyov@omp.ru>
i2c: hix5hd2: fix IRQ check
Sergey Shtylyov <s.shtylyov@omp.ru>
i2c: s3c2410: fix IRQ check
Sergey Shtylyov <s.shtylyov@omp.ru>
i2c: iop3xx: fix deferred probing
Pavel Skripkin <paskripkin@gmail.com>
Bluetooth: add timeout sanity check to hci_inquiry
Kevin Mitchell <kevmitch@arista.com>
lkdtm: replace SCSI_DISPATCH_CMD with SCSI_QUEUE_RQ
Xu Yu <xuyu@linux.alibaba.com>
mm/swap: consider max pages in iomap_swapfile_add_extent
Nadezda Lutovinova <lutovinova@ispras.ru>
usb: gadget: mv_u3d: request_irq() after initializing UDC
Christophe JAILLET <christophe.jaillet@wanadoo.fr>
firmware: raspberrypi: Fix a leak in 'rpi_firmware_get()'
Shengjiu Wang <shengjiu.wang@nxp.com>
ASoC: fsl_rpmsg: Check -EPROBE_DEFER for getting clocks
Lukas Bulwahn <lukas.bulwahn@gmail.com>
hwmon: remove amd_energy driver in Makefile
Chris Packham <chris.packham@alliedtelesis.co.nz>
hwmon: (pmbus/bpa-rs600) Don't use rated limits as warn limits
Sergey Shtylyov <s.shtylyov@omp.ru>
i2c: synquacer: fix deferred probing
Lukas Bulwahn <lukas.bulwahn@gmail.com>
clk: staging: correct reference to config IOMEM to config HAS_IOMEM
Pali Rohár <pali@kernel.org>
arm64: dts: marvell: armada-37xx: Extend PCIe MEM space
J. Bruce Fields <bfields@redhat.com>
nfsd4: Fix forced-expiry locking
Chuck Lever <chuck.lever@oracle.com>
SUNRPC: Fix a NULL pointer deref in trace_svc_stats_latency()
Benjamin Coddington <bcodding@redhat.com>
lockd: Fix invalid lockowner cast after vfs_test_lock
Thomas Gleixner <tglx@linutronix.de>
locking/local_lock: Add missing owner initialization
Chih-Kang Chang <gary.chang@realtek.com>
mac80211: Fix insufficient headroom issue for AMSDU
Andrii Nakryiko <andrii@kernel.org>
libbpf: Re-build libbpf.so when libbpf.map changes
Sergey Shtylyov <s.shtylyov@omp.ru>
usb: phy: tahvo: add IRQ check
Sergey Shtylyov <s.shtylyov@omp.ru>
usb: host: ohci-tmio: add IRQ check
Valentin Schneider <valentin.schneider@arm.com>
PM: cpu: Make notifier chain use a raw_spinlock_t
Kai-Heng Feng <kai.heng.feng@canonical.com>
Bluetooth: Move shutdown callback before flushing tx and rx queue
Voon Weifeng <weifeng.voon@intel.com>
net: stmmac: fix INTR TBU status affecting irq count statistic
Juhee Kang <claudiajkang@gmail.com>
samples: pktgen: add missing IPv6 option to pktgen scripts
Leon Romanovsky <leon@kernel.org>
devlink: Clear whole devlink_flash_notify struct
Ilya Leoshkevich <iii@linux.ibm.com>
selftests/bpf: Fix test_core_autosize on big-endian machines
Geert Uytterhoeven <geert+renesas@glider.be>
usb: gadget: udc: renesas_usb3: Fix soc_device_match() abuse
Sergey Shtylyov <s.shtylyov@omp.ru>
usb: phy: twl6030: add IRQ checks
Sergey Shtylyov <s.shtylyov@omp.ru>
usb: phy: fsl-usb: add IRQ check
Sergey Shtylyov <s.shtylyov@omp.ru>
usb: misc: brcmstb-usb-pinmap: add IRQ check
Dan Carpenter <dan.carpenter@oracle.com>
mac80211: remove unnecessary NULL check in ieee80211_register_hw()
Sergey Shtylyov <s.shtylyov@omp.ru>
usb: gadget: udc: s3c2410: add IRQ check
Sergey Shtylyov <s.shtylyov@omp.ru>
usb: gadget: udc: at91: add IRQ check
Sergey Shtylyov <s.shtylyov@omp.ru>
usb: dwc3: qcom: add IRQ check
Sergey Shtylyov <s.shtylyov@omp.ru>
usb: dwc3: meson-g12a: add IRQ check
Rob Clark <robdclark@chromium.org>
drm/bridge: ti-sn65dsi86: Avoid creating multiple connectors
Douglas Anderson <dianders@chromium.org>
ASoC: rt5682: Properly turn off regulators if wrong device ID
Parav Pandit <parav@nvidia.com>
net/mlx5: Fix unpublish devlink parameters
Kuogee Hsieh <khsieh@codeaurora.org>
drm/msm/dp: replug event is converted into an unplug followed by an plug events
Christophe JAILLET <christophe.jaillet@wanadoo.fr>
drm/msm/dsi: Fix some reference counted resource leaks
Desmond Cheong Zhi Xi <desmondcheongzx@gmail.com>
Bluetooth: fix repeated calls to sco_sock_kill
Curtis Malainey <cujomalainey@chromium.org>
ASoC: Intel: Fix platform ID matching
Waiman Long <longman@redhat.com>
cgroup/cpuset: Fix violation of cpuset locking rule
Waiman Long <longman@redhat.com>
cgroup/cpuset: Miscellaneous code cleanup
William Breathitt Gray <vilhelm.gray@gmail.com>
counter: 104-quad-8: Return error when invalid mode during ceiling_write
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
arm64: dts: exynos: correct GIC CPU interfaces address range on Exynos7
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
drm/msm/dpu: make dpu_hw_ctl_clear_all_blendstages clear necessary LMs
Kuogee Hsieh <khsieh@codeaurora.org>
drm/msm/dp: update is_connected status base on sink count at dp_pm_resume()
David Heidelberg <david@ixit.cz>
drm/msm/mdp4: move HW revision detection to earlier phase
David Heidelberg <david@ixit.cz>
drm/msm/mdp4: refactor HW revision detection into read_mdp_hw_revision
Wei Li <liwei391@huawei.com>
drm/msm: Fix error return code in msm_drm_init()
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
leds: lgm-sso: Propagate error codes from callee to caller
Jose Blanquicet <josebl@microsoft.com>
selftests/bpf: Fix bpf-iter-tcp4 test to print correctly the dest IP
Lukasz Luba <lukasz.luba@arm.com>
PM: EM: Increase energy calculation precision
Vladimir Oltean <vladimir.oltean@nxp.com>
net: dsa: don't disable multicast flooding to the CPU even without an IGMP querier
Vladimir Oltean <vladimir.oltean@nxp.com>
net: dsa: mt7530: remove the .port_set_mrouter implementation
Vladimir Oltean <vladimir.oltean@nxp.com>
net: dsa: stop syncing the bridge mcast_router attribute at join time
Vignesh Raghavendra <vigneshr@ti.com>
net: ti: am65-cpsw-nuss: fix RX IRQ state after .ndo_stop()
Robert Foss <robert.foss@linaro.org>
drm: bridge: it66121: Check drm_bridge_attach retval
Alex Elder <elder@linaro.org>
arm64: dts: qcom: sm8350: fix IPA interconnects
Sibi Sankar <sibis@codeaurora.org>
arm64: dts: qcom: sc7280: Fixup the cpufreq node
Colin Ian King <colin.king@canonical.com>
Bluetooth: increase BTNAMSIZ to 21 chars to fix potential buffer overflow
Sven Eckelmann <sven@narfation.org>
debugfs: Return error during {full/open}_proxy_open() on rmmod
Vladimir Oltean <vladimir.oltean@nxp.com>
net: dsa: tag_sja1105: optionally build as module when switch driver is module if PTP is enabled
Vladimir Oltean <vladimir.oltean@nxp.com>
net: dsa: build tag_8021q.c as part of DSA core
Stephan Gerhold <stephan@gerhold.net>
soc: qcom: smsm: Fix missed interrupts if state changes while masked
Matthew Cover <werekraken@gmail.com>
bpf, samples: Add missing mprog-disable to xdp_redirect_cpu's optstring
Rafael J. Wysocki <rafael.j.wysocki@intel.com>
PCI: PM: Enable PME if it can be signaled from D3cold
Rafael J. Wysocki <rafael.j.wysocki@intel.com>
PCI: PM: Avoid forcing PCI_D0 for wakeup reasons inconsistently
CK Hu <ck.hu@mediatek.com>
soc: mmsys: mediatek: add mask to mmsys routes
Mansur Alisha Shaik <mansur@codeaurora.org>
media: venus: helper: do not set constrained parameters for UBWC
Colin Ian King <colin.king@canonical.com>
media: venus: venc: Fix potential null pointer dereference on pointer fmt
Zhen Lei <thunder.leizhen@huawei.com>
media: venus: hfi: fix return value check in sys_get_prop_image_version()
Wei Yongjun <weiyongjun1@huawei.com>
media: omap3isp: Fix missing unlock in isp_subdev_notifier_complete()
Dongliang Mu <mudongliangabcd@gmail.com>
media: em28xx-input: fix refcount bug in em28xx_usb_disconnect
Hans de Goede <hdegoede@redhat.com>
leds: trigger: audio: Add an activate callback to ensure the initial brightness is set
Andy Shevchenko <andy.shevchenko@gmail.com>
leds: rt8515: Put fwnode in any case during ->probe()
Andy Shevchenko <andy.shevchenko@gmail.com>
leds: lt3593: Put fwnode in any case during ->probe()
Andy Shevchenko <andy.shevchenko@gmail.com>
leds: lgm-sso: Don't spam logs when probe is deferred
Andy Shevchenko <andy.shevchenko@gmail.com>
leds: lgm-sso: Put fwnode in any case during ->probe()
Sergey Shtylyov <s.shtylyov@omp.ru>
i2c: highlander: add IRQ check
Jiapeng Chong <jiapeng.chong@linux.alibaba.com>
net/mlx5: Fix missing return value in mlx5_devlink_eswitch_inline_mode_set()
Douglas Anderson <dianders@chromium.org>
drm/bridge: ti-sn65dsi86: Add some 100 us delays
Douglas Anderson <dianders@chromium.org>
drm/bridge: ti-sn65dsi86: Fix power off sequence
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
drm/bridge: ti-sn65dsi86: Wrap panel with panel-bridge
Douglas Anderson <dianders@chromium.org>
drm/bridge: ti-sn65dsi86: Improve probe errors with dev_err_probe()
Douglas Anderson <dianders@chromium.org>
drm/bridge: ti-sn65dsi86: Don't read EDID blob over DDC
Leon Romanovsky <leon@kernel.org>
devlink: Break parameter notification sequence to be before/after unload/load driver
Biju Das <biju.das.jz@bp.renesas.com>
arm64: dts: renesas: hihope-rzg2-ex: Add EtherAVB internal rx delay
Quentin Monnet <quentin@isovalent.com>
tools: Free BTF objects at various locations
Quentin Monnet <quentin@isovalent.com>
libbpf: Return non-null error on failures in libbpf_find_prog_btf_id()
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
lib/test_scanf: Handle n_bits == 0 in random tests
Luben Tuikov <luben.tuikov@amd.com>
drm/amd/pm: Fix a bug in semaphore double-lock
Tedd Ho-Jeong An <tedd.an@intel.com>
Bluetooth: mgmt: Fix wrong opcode in the response for add_adv cmd
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
drm: rcar-du: Don't put reference to drm_device in rcar_du_remove()
Leon Romanovsky <leon@kernel.org>
net: ti: am65-cpsw-nuss: fix wrong devlink release order
Pavel Skripkin <paskripkin@gmail.com>
net: cipso: fix warnings in netlbl_cipsov4_add_std
Marek Vasut <marex@denx.de>
drm: mxsfb: Clear FIFO_CLEAR bit
Marek Vasut <marex@denx.de>
drm: mxsfb: Increase number of outstanding requests on V4 and newer HW
Marek Vasut <marex@denx.de>
drm: mxsfb: Enable recovery on underflow
Waiman Long <longman@redhat.com>
cgroup/cpuset: Fix a partition bug with hotplug
Maxim Mikityanskiy <maximmi@nvidia.com>
net/mlx5e: Block LRO if firmware asks for tunneled LRO
Maxim Mikityanskiy <maximmi@nvidia.com>
net/mlx5e: Prohibit inner indir TIRs in IPoIB
Anand Moon <linux.amoon@gmail.com>
ARM: dts: meson8b: ec100: Fix the pwm regulator supply properties
Anand Moon <linux.amoon@gmail.com>
ARM: dts: meson8b: mxq: Fix the pwm regulator supply properties
Anand Moon <linux.amoon@gmail.com>
ARM: dts: meson8b: odroidc1: Fix the pwm regulator supply properties
Martin Blumenstingl <martin.blumenstingl@googlemail.com>
ARM: dts: meson8: Use a higher default GPU clock frequency
Martin KaFai Lau <kafai@fb.com>
tcp: seq_file: Avoid skipping sk during tcp_seek_last_pos
Luben Tuikov <luben.tuikov@amd.com>
drm/amd/pm: Fix a bug communicating with the SMU (v5)
Kai-Heng Feng <kai.heng.feng@canonical.com>
drm/amdgpu/acp: Make PM domain really work
Colin Ian King <colin.king@canonical.com>
6lowpan: iphc: Fix an off-by-one check of array index
Jun Miao <jun.miao@windriver.com>
Bluetooth: btusb: Fix a unspported condition to set available debug features
Dan Carpenter <dan.carpenter@oracle.com>
Bluetooth: sco: prevent information leak in sco_conn_defer_accept()
Yizhuo <yzhai003@ucr.edu>
media: atomisp: fix the uninitialized use and rename "retvalue"
Philipp Zabel <p.zabel@pengutronix.de>
media: coda: fix frame_mem_ctrl for YUV420 and YVU420 formats
Dan Carpenter <dan.carpenter@oracle.com>
media: rockchip/rga: fix error handling in probe
Dan Carpenter <dan.carpenter@oracle.com>
media: v4l2-subdev: fix some NULL vs IS_ERR() checks
Pavel Skripkin <paskripkin@gmail.com>
media: go7007: remove redundant initialization
Pavel Skripkin <paskripkin@gmail.com>
media: go7007: fix memory leak in go7007_usb_probe
Oleksij Rempel <linux@rempel-privat.de>
net: usb: asix: ax88772: add missing stop
Dongliang Mu <mudongliangabcd@gmail.com>
media: dvb-usb: Fix error handling in dvb_usb_i2c_init
Dongliang Mu <mudongliangabcd@gmail.com>
media: dvb-usb: fix uninit-value in vp702x_read_mac_addr
Dongliang Mu <mudongliangabcd@gmail.com>
media: dvb-usb: fix uninit-value in dvb_usb_adapter_dvb_init
Leon Romanovsky <leon@kernel.org>
ionic: cleanly release devlink instance
Zhen Lei <thunder.leizhen@huawei.com>
driver core: Fix error return code in really_probe()
Zhen Lei <thunder.leizhen@huawei.com>
firmware: fix theoretical UAF race with firmware cache and resume
John Fastabend <john.fastabend@gmail.com>
bpf, selftests: Fix test_maps now that sockmap supports UDP
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
arm64: dts: qcom: sm8250: fix usb2 qmp phy node
Colin Ian King <colin.king@canonical.com>
gfs2: Fix memory leak of object lsi on error return path
Martynas Pumputis <m@lambda.lt>
libbpf: Fix removal of inner map in bpf_object__create_map
Bjorn Andersson <bjorn.andersson@linaro.org>
soc: qcom: rpmhpd: Use corner in power_off
Judy Hsiao <judyhsiao@chromium.org>
arm64: dts: qcom: sc7180: Set adau wakeup delay to 80 ms
Stefan Assmann <sassmann@kpanic.de>
i40e: improve locking of mac_filter_hash
Geert Uytterhoeven <geert@linux-m68k.org>
arm64: dts: renesas: r8a77995: draak: Remove bogus adv7511w properties
Andrew Jeffery <andrew@aj.id.au>
ARM: dts: everest: Add phase corrections for eMMC
Dylan Hung <dylan_hung@aspeedtech.com>
ARM: dts: aspeed-g6: Fix HVI3C function-group in pinctrl dtsi
Shuyi Cheng <chengshuyi@linux.alibaba.com>
libbpf: Fix the possible memory leak on error
Haiyue Wang <haiyue.wang@intel.com>
gve: fix the wrong AdminQ buffer overflow check
Steven Price <steven.price@arm.com>
drm/of: free the iterator object on failure
He Fengqing <hefengqing@huawei.com>
bpf: Fix potential memleak and UAF in the verifier.
Kuniyuki Iwashima <kuniyu@amazon.co.jp>
bpf: Fix a typo of reuseport map in bpf.h.
Julia Lawall <Julia.Lawall@inria.fr>
drm/of: free the right object
Christophe JAILLET <christophe.jaillet@wanadoo.fr>
media: cxd2880-spi: Fix an error handling path
Geert Uytterhoeven <geert+renesas@glider.be>
soc: rockchip: ROCKCHIP_GRF should not default to y, unconditionally
Jiapeng Chong <jiapeng.chong@linux.alibaba.com>
leds: is31fl32xx: Fix missing error code in is31fl32xx_parse_dt()
Krzysztof Hałasa <khalasa@piap.pl>
media: TDA1997x: enable EDID support
Eugen Hristev <eugen.hristev@microchip.com>
media: atmel: atmel-sama5d2-isc: fix YUYV format
Marek Vasut <marex@denx.de>
ASoC: tlv320aic32x4: Fix TAS2505/TAS2521 channel count
Zhang Qilong <zhangqilong3@huawei.com>
ASoC: mediatek: mt8183: Fix Unbalanced pm_runtime_enable in mt8183_afe_pcm_dev_probe
Zhang Qilong <zhangqilong3@huawei.com>
ASoC: mediatek: mt8192:Fix Unbalanced pm_runtime_enable in mt8192_afe_pcm_dev_probe
Harshvardhan Jha <harshvardhan.jha@oracle.com>
drm/gma500: Fix end of loop tests for list_for_each_entry
Wei Yongjun <weiyongjun1@huawei.com>
drm/panfrost: Fix missing clk_disable_unprepare() on error in panfrost_clk_init()
Quanyang Wang <quanyang.wang@windriver.com>
spi: spi-zynq-qspi: use wait_for_completion_timeout to make zynq_qspi_exec_mem_op not interruptible
Chunyan Zhang <chunyan.zhang@unisoc.com>
spi: sprd: Fix the wrong WDG_LOAD_VAL
Chen-Yu Tsai <wenst@chromium.org>
regulator: vctrl: Avoid lockdep warning in enable/disable ops
Chen-Yu Tsai <wenst@chromium.org>
regulator: vctrl: Use locked regulator_get_voltage in probe path
Eric Biggers <ebiggers@google.com>
blk-crypto: fix check for too-large dun_bytes
Matija Glavinic Pecotic <matija.glavinic-pecotic.ext@nokia.com>
spi: davinci: invoke chipselect callback
Borislav Petkov <bp@alien8.de>
x86/mce: Defer processing of early errors
Qiuxu Zhuo <qiuxu.zhuo@intel.com>
EDAC/i10nm: Fix NVDIMM detection
Stefan Berger <stefanb@linux.ibm.com>
tpm: ibmvtpm: Avoid error message when process gets signal while waiting
Stefan Berger <stefanb@linux.ibm.com>
certs: Trigger creation of RSA module signing key if it's not an RSA key
Geert Uytterhoeven <geert@linux-m68k.org>
m68k: Fix asm register constraints for atomic ops
Giovanni Cabiddu <giovanni.cabiddu@intel.com>
crypto: qat - use proper type for vf_mask
Chen-Yu Tsai <wenst@chromium.org>
irqchip/gic-v3: Fix priority comparison when non-secure priorities are used
Sven Peter <sven@svenpeter.dev>
irqchip/apple-aic: Fix irq_disable from within irq handlers
Christophe JAILLET <christophe.jaillet@wanadoo.fr>
spi: coldfire-qspi: Use clk_disable_unprepare in the remove function
Pavel Skripkin <paskripkin@gmail.com>
block: nbd: add sanity check for first_minor
Hou Tao <houtao1@huawei.com>
nbd: do del_gendisk() asynchronously for NBD_DESTROY_ON_DISCONNECT
Phong Hoang <phong.hoang.wz@renesas.com>
clocksource/drivers/sh_cmt: Fix wrong setting if don't request IRQ for clock source channel
Hongbo Li <herberthbli@tencent.com>
lib/mpi: use kcalloc in mpi_resize
Huacai Chen <chenhuacai@kernel.org>
irqchip/loongson-pch-pic: Improve edge triggered interrupt support
Zhen Lei <thunder.leizhen@huawei.com>
genirq/timings: Fix error return code in irq_timings_test_irqs()
Tony Lindgren <tony@atomide.com>
spi: spi-pic32: Fix issue with uninitialized dma_slave_config
Tony Lindgren <tony@atomide.com>
spi: spi-fsl-dspi: Fix issue with uninitialized dma_slave_config
Ming Lei <ming.lei@redhat.com>
block: return ELEVATOR_DISCARD_MERGE if possible
Geert Uytterhoeven <geert@linux-m68k.org>
m68k: Fix invalid RMW_INSNS on CPUs that lack CAS
Yanfei Xu <yanfei.xu@windriver.com>
rcu: Fix stall-warning deadlock due to non-release of rcu_node ->lock
Yanfei Xu <yanfei.xu@windriver.com>
rcu: Fix to include first blocked task in stall warning
Quentin Perret <qperret@google.com>
sched: Fix UCLAMP_FLAG_IDLE setting
Mika Penttilä <mika.penttila@gmail.com>
sched/numa: Fix is_core_idle()
Mian Yousaf Kaukab <ykaukab@suse.de>
crypto: ecc - handle unaligned input buffer in ecc_swap_digits
Ard Biesheuvel <ardb@kernel.org>
crypto: x86/aes-ni - add missing error checks in XTS code
Pavel Skripkin <paskripkin@gmail.com>
m68k: emu: Fix invalid free in nfeth_cleanup()
Peter Robinson <pbrobinson@gmail.com>
power: supply: cw2015: use dev_err_probe to allow deferred probe
Valentin Schneider <valentin.schneider@arm.com>
sched/debug: Don't update sched_domain debug directories before sched_debug_init()
Alexander Gordeev <agordeev@linux.ibm.com>
s390/smp: enable DAT before CPU restart callback is called
Harald Freudenberger <freude@linux.ibm.com>
s390/ap: fix state machine hang after failure to enable irq
Peter Oberparleiter <oberpar@linux.ibm.com>
s390/debug: fix debug area life cycle
Peter Oberparleiter <oberpar@linux.ibm.com>
s390/debug: keep debug data on resize
Niklas Schnelle <schnelle@linux.ibm.com>
s390/pci: fix misleading rc in clp_set_pci_fn()
Alexander Gordeev <agordeev@linux.ibm.com>
s390/kasan: fix large PMD pages address alignment check
Jens Axboe <axboe@kernel.dk>
io-wq: remove GFP_ATOMIC allocation off schedule out path
Stian Skjelstad <stian.skjelstad@gmail.com>
udf_get_extendedattr() had no boundary checks.
Desmond Cheong Zhi Xi <desmondcheongzx@gmail.com>
fcntl: fix potential deadlock for &fasync_struct.fa_lock
Desmond Cheong Zhi Xi <desmondcheongzx@gmail.com>
fcntl: fix potential deadlocks for &fown_struct.lock
Tianjia Zhang <tianjia.zhang@linux.alibaba.com>
crypto: tcrypt - Fix missing return value check
Kai Ye <yekai13@huawei.com>
crypto: hisilicon/sec - modify the hardware endian configuration
Kai Ye <yekai13@huawei.com>
crypto: hisilicon/sec - fix the abnormal exiting process
Giovanni Cabiddu <giovanni.cabiddu@intel.com>
crypto: qat - do not export adf_iov_putmsg()
Marco Chiappero <marco.chiappero@intel.com>
crypto: qat - fix naming for init/shutdown VF to PF notifications
Marco Chiappero <marco.chiappero@intel.com>
crypto: qat - fix reuse of completion variable
Giovanni Cabiddu <giovanni.cabiddu@intel.com>
crypto: qat - handle both source of interrupt in VF ISR
Giovanni Cabiddu <giovanni.cabiddu@intel.com>
crypto: qat - do not ignore errors from enable_vf2pf_comms()
Ben Hutchings <ben.hutchings@mind.be>
crypto: omap - Fix inconsistent locking of device lists
Valentin Schneider <valentin.schneider@arm.com>
sched/topology: Skip updating masks for non-online nodes
Damien Le Moal <damien.lemoal@wdc.com>
libata: fix ata_host_start()
Harald Freudenberger <freude@linux.ibm.com>
s390/zcrypt: fix wrong offset index for APKA master key valid state
Vineeth Vijayan <vneethv@linux.ibm.com>
s390/cio: add dev_busid sysfs entry for each subchannel
Sebastian Krzyszkowiak <sebastian.krzyszkowiak@puri.sm>
power: supply: max17042_battery: fix typo in MAx17042_TOFF
Dmitry Osipenko <digetx@gmail.com>
power: supply: smb347-charger: Add missing pin control activation
Amit Engel <amit.engel@dell.com>
nvmet: pass back cntlid on successful completion
Ruozhu Li <liruozhu@huawei.com>
nvme-rdma: don't update queue count when failing to set io queues
Ruozhu Li <liruozhu@huawei.com>
nvme-tcp: don't update queue count when failing to set io queues
Chunguang Xu <brookxu@tencent.com>
blk-throtl: optimize IOPS throttle for large IO scenarios
Baokun Li <libaokun1@huawei.com>
nbd: add the check to prevent overflow in __nbd_ioctl()
Christoph Hellwig <hch@lst.de>
bcache: add proper error unwinding in bcache_device_init
Pali Rohár <pali@kernel.org>
isofs: joliet: Fix iocharset=utf8 mount option
Pali Rohár <pali@kernel.org>
udf: Fix iocharset=utf8 mount option
Jan Kara <jack@suse.cz>
udf: Check LVID earlier
Thomas Gleixner <tglx@linutronix.de>
hrtimer: Ensure timerfd notification for HIGHRES=n
Thomas Gleixner <tglx@linutronix.de>
hrtimer: Avoid double reprogramming in __hrtimer_start_range_ns()
Frederic Weisbecker <frederic@kernel.org>
posix-cpu-timers: Force next expiration recalc after itimer reset
Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
EDAC/mce_amd: Do not load edac_mce_amd module on guests
Sergey Senozhatsky <senozhatsky@chromium.org>
rcu/tree: Handle VM stoppage in stall detection
Dietmar Eggemann <dietmar.eggemann@arm.com>
sched/deadline: Fix missing clock update in migrate_task_rq_dl()
Tony Lindgren <tony@atomide.com>
crypto: omap-sham - clear dma flags only after omap_sham_update_dma_stop()
Hans de Goede <hdegoede@redhat.com>
power: supply: axp288_fuel_gauge: Report register-address on readb / writeb errors
Quentin Perret <qperret@google.com>
sched/deadline: Fix reset_on_fork reporting of DL tasks
Sean Anderson <sean.anderson@seco.com>
crypto: mxs-dcp - Check for DMA mapping errors
Dmitry Osipenko <digetx@gmail.com>
regulator: tps65910: Silence deferred probe error
Jeongtae Park <jeongtae.park@gmail.com>
regmap: fix the offset of register error log
Peter Zijlstra <peterz@infradead.org>
locking/mutex: Fix HANDOFF condition
-------------
Diffstat:
Documentation/fault-injection/provoke-crashes.rst | 2 +-
Makefile | 4 +-
arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts | 2 +-
arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi | 4 +-
arch/arm/boot/dts/at91-sam9x60ek.dts | 16 +-
arch/arm/boot/dts/at91-sama5d3_xplained.dts | 29 +++
arch/arm/boot/dts/at91-sama5d4_xplained.dts | 19 ++
arch/arm/boot/dts/meson8.dtsi | 5 +
arch/arm/boot/dts/meson8b-ec100.dts | 4 +-
arch/arm/boot/dts/meson8b-mxq.dts | 4 +-
arch/arm/boot/dts/meson8b-odroidc1.dts | 4 +-
arch/arm64/boot/dts/exynos/exynos7.dtsi | 2 +-
.../boot/dts/marvell/armada-3720-turris-mox.dts | 17 ++
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 11 +-
.../arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sc7280.dtsi | 6 +-
arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sm8350.dtsi | 8 +-
arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi | 1 +
arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 4 -
arch/arm64/kvm/arm.c | 7 +
arch/arm64/kvm/vgic/vgic-v2.c | 36 +--
arch/arm64/kvm/vgic/vgic-v3.c | 36 +--
arch/arm64/kvm/vgic/vgic.c | 38 +++
arch/arm64/kvm/vgic/vgic.h | 2 +
arch/m68k/Kconfig.cpu | 8 +-
arch/m68k/coldfire/clk.c | 2 +-
arch/m68k/emu/nfeth.c | 4 +-
arch/m68k/include/asm/atomic.h | 4 +-
arch/parisc/boot/compressed/misc.c | 2 +-
arch/s390/include/asm/kvm_host.h | 1 +
arch/s390/include/asm/lowcore.h | 3 +-
arch/s390/include/asm/processor.h | 2 +
arch/s390/kernel/asm-offsets.c | 1 +
arch/s390/kernel/debug.c | 176 ++++++++-----
arch/s390/kernel/entry.S | 11 +-
arch/s390/kernel/ipl.c | 3 -
arch/s390/kernel/machine_kexec.c | 1 -
arch/s390/kernel/setup.c | 9 +-
arch/s390/kernel/smp.c | 31 ++-
arch/s390/kvm/interrupt.c | 12 +-
arch/s390/kvm/kvm-s390.c | 2 +-
arch/s390/kvm/kvm-s390.h | 2 +-
arch/s390/mm/kasan_init.c | 41 ++-
arch/s390/pci/pci.c | 7 +-
arch/s390/pci/pci_clp.c | 33 ++-
arch/x86/crypto/aesni-intel_glue.c | 5 +
arch/x86/events/intel/uncore_snbep.c | 40 ++-
arch/x86/include/asm/mce.h | 1 +
arch/x86/kernel/cpu/mce/core.c | 11 +-
arch/x86/kvm/mmu/mmu.c | 19 +-
arch/x86/kvm/mmu/tdp_mmu.c | 20 +-
arch/x86/kvm/vmx/nested.c | 7 +-
arch/x86/kvm/vmx/vmx.c | 3 +
arch/x86/kvm/x86.c | 4 +
block/bfq-iosched.c | 3 +
block/bio.c | 15 +-
block/blk-crypto.c | 2 +-
block/blk-merge.c | 18 +-
block/blk-throttle.c | 32 +++
block/blk.h | 2 +
block/elevator.c | 3 +
block/mq-deadline.c | 2 +
certs/Makefile | 8 +
crypto/ecc.h | 5 +-
crypto/tcrypt.c | 29 ++-
drivers/acpi/prmt.c | 10 +-
drivers/ata/libata-core.c | 2 +-
drivers/auxdisplay/hd44780.c | 2 +-
drivers/base/dd.c | 16 +-
drivers/base/firmware_loader/main.c | 20 +-
drivers/base/regmap/regmap.c | 2 +-
drivers/bcma/main.c | 6 +-
drivers/block/nbd.c | 86 ++++++-
drivers/bluetooth/btusb.c | 18 +-
drivers/char/tpm/Kconfig | 1 -
drivers/char/tpm/tpm_ibmvtpm.c | 26 +-
drivers/char/tpm/tpm_ibmvtpm.h | 2 +-
drivers/clk/mvebu/kirkwood.c | 1 +
drivers/clocksource/sh_cmt.c | 30 ++-
drivers/counter/104-quad-8.c | 5 +-
drivers/crypto/hisilicon/sec2/sec.h | 5 -
drivers/crypto/hisilicon/sec2/sec_main.c | 34 +--
drivers/crypto/mxs-dcp.c | 45 +++-
drivers/crypto/omap-aes.c | 8 +-
drivers/crypto/omap-des.c | 8 +-
drivers/crypto/omap-sham.c | 14 +-
.../crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c | 4 +-
drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c | 4 +-
drivers/crypto/qat/qat_common/adf_common_drv.h | 8 +-
drivers/crypto/qat/qat_common/adf_init.c | 5 +-
drivers/crypto/qat/qat_common/adf_isr.c | 7 +-
drivers/crypto/qat/qat_common/adf_pf2vf_msg.c | 3 +-
drivers/crypto/qat/qat_common/adf_vf2pf_msg.c | 12 +-
drivers/crypto/qat/qat_common/adf_vf_isr.c | 7 +-
.../qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c | 4 +-
drivers/edac/i10nm_base.c | 6 +-
drivers/edac/mce_amd.c | 3 +
drivers/firmware/raspberrypi.c | 10 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 54 ++--
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 286 +++++++++++++++++----
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h | 3 +-
drivers/gpu/drm/bridge/ite-it66121.c | 2 +
drivers/gpu/drm/bridge/ti-sn65dsi86.c | 97 ++++---
drivers/gpu/drm/drm_of.c | 6 +-
drivers/gpu/drm/exynos/exynos_drm_g2d.c | 3 +-
drivers/gpu/drm/gma500/oaktrail_lvds.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 10 +-
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 68 ++---
drivers/gpu/drm/msm/dp/dp_display.c | 31 ++-
drivers/gpu/drm/msm/dsi/dsi.c | 6 +-
drivers/gpu/drm/msm/msm_drv.c | 1 +
drivers/gpu/drm/mxsfb/mxsfb_drv.c | 3 +
drivers/gpu/drm/mxsfb/mxsfb_drv.h | 1 +
drivers/gpu/drm/mxsfb/mxsfb_kms.c | 40 +++
drivers/gpu/drm/mxsfb/mxsfb_regs.h | 9 +
drivers/gpu/drm/panfrost/panfrost_device.c | 3 +-
drivers/gpu/drm/rcar-du/rcar_du_drv.c | 2 -
drivers/hv/hv_snapshot.c | 1 +
drivers/hwmon/Makefile | 1 -
drivers/hwmon/pmbus/bpa-rs600.c | 25 --
drivers/i2c/busses/i2c-highlander.c | 2 +-
drivers/i2c/busses/i2c-hix5hd2.c | 2 +-
drivers/i2c/busses/i2c-iop3xx.c | 6 +-
drivers/i2c/busses/i2c-mt65xx.c | 2 +-
drivers/i2c/busses/i2c-s3c2410.c | 2 +-
drivers/i2c/busses/i2c-synquacer.c | 2 +-
drivers/i2c/busses/i2c-xlp9xx.c | 2 +-
drivers/infiniband/hw/mlx5/mr.c | 2 +-
drivers/irqchip/irq-apple-aic.c | 2 +-
drivers/irqchip/irq-gic-v3.c | 23 +-
drivers/irqchip/irq-loongson-pch-pic.c | 19 +-
drivers/leds/blink/leds-lgm-sso.c | 23 +-
drivers/leds/flash/leds-rt8515.c | 4 +-
drivers/leds/leds-is31fl32xx.c | 1 +
drivers/leds/leds-lt3593.c | 5 +-
drivers/leds/trigger/ledtrig-audio.c | 37 ++-
drivers/md/bcache/super.c | 16 +-
drivers/md/raid1.c | 19 ++
drivers/md/raid10.c | 14 +-
drivers/media/i2c/tda1997x.c | 1 +
drivers/media/platform/atmel/atmel-sama5d2-isc.c | 17 ++
drivers/media/platform/coda/coda-bit.c | 18 +-
drivers/media/platform/omap3isp/isp.c | 4 +-
drivers/media/platform/qcom/venus/helpers.c | 3 +
drivers/media/platform/qcom/venus/hfi_msgs.c | 2 +-
drivers/media/platform/qcom/venus/venc.c | 2 +
drivers/media/platform/rcar-vin/rcar-v4l2.c | 4 +-
drivers/media/platform/rockchip/rga/rga.c | 27 +-
drivers/media/platform/vsp1/vsp1_entity.c | 4 +-
drivers/media/spi/cxd2880-spi.c | 7 +-
drivers/media/usb/dvb-usb/dvb-usb-i2c.c | 9 +-
drivers/media/usb/dvb-usb/dvb-usb-init.c | 2 +-
drivers/media/usb/dvb-usb/nova-t-usb2.c | 6 +-
drivers/media/usb/dvb-usb/vp702x.c | 12 +-
drivers/media/usb/em28xx/em28xx-input.c | 1 -
drivers/media/usb/go7007/go7007-driver.c | 26 --
drivers/media/usb/go7007/go7007-usb.c | 2 +-
drivers/misc/lkdtm/core.c | 2 +-
drivers/misc/pvpanic/pvpanic.c | 2 +
drivers/mmc/host/dw_mmc.c | 1 +
drivers/mmc/host/moxart-mmc.c | 1 +
drivers/mmc/host/sdhci.c | 1 +
drivers/net/dsa/b53/b53_common.c | 10 -
drivers/net/dsa/b53/b53_priv.h | 2 -
drivers/net/dsa/bcm_sf2.c | 1 -
drivers/net/dsa/mt7530.c | 13 -
drivers/net/dsa/mv88e6xxx/chip.c | 18 --
.../net/ethernet/aquantia/atlantic/aq_pci_func.c | 3 +
drivers/net/ethernet/google/gve/gve_adminq.c | 6 +-
drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c | 23 +-
drivers/net/ethernet/intel/ice/ice_main.c | 13 +-
drivers/net/ethernet/intel/ice/ice_ptp.c | 55 +++-
drivers/net/ethernet/marvell/octeontx2/af/common.h | 2 -
.../net/ethernet/marvell/octeontx2/af/rvu_cn10k.c | 35 ++-
.../net/ethernet/marvell/octeontx2/af/rvu_nix.c | 9 +-
.../net/ethernet/marvell/octeontx2/af/rvu_npc.c | 22 +-
.../net/ethernet/marvell/octeontx2/af/rvu_reg.h | 2 +-
.../ethernet/marvell/octeontx2/nic/otx2_common.c | 16 +-
.../ethernet/marvell/octeontx2/nic/otx2_common.h | 3 +
.../ethernet/marvell/octeontx2/nic/otx2_flows.c | 1 +
.../net/ethernet/marvell/octeontx2/nic/otx2_tc.c | 4 +-
drivers/net/ethernet/mellanox/mlx5/core/dev.c | 2 +-
drivers/net/ethernet/mellanox/mlx5/core/devlink.c | 1 +
drivers/net/ethernet/mellanox/mlx5/core/en/fs.h | 6 -
drivers/net/ethernet/mellanox/mlx5/core/en/qos.c | 15 +-
drivers/net/ethernet/mellanox/mlx5/core/en/qos.h | 4 +-
.../ethernet/mellanox/mlx5/core/en/tc_tun_encap.c | 4 +-
drivers/net/ethernet/mellanox/mlx5/core/en_fs.c | 10 +-
drivers/net/ethernet/mellanox/mlx5/core/en_main.c | 18 +-
drivers/net/ethernet/mellanox/mlx5/core/en_tc.c | 18 ++
.../ethernet/mellanox/mlx5/core/esw/indir_table.c | 1 +
.../ethernet/mellanox/mlx5/core/eswitch_offloads.c | 5 +-
.../net/ethernet/mellanox/mlx5/core/ipoib/ipoib.c | 18 +-
drivers/net/ethernet/mellanox/mlx5/core/lag.c | 1 +
drivers/net/ethernet/mellanox/mlx5/core/lag_mp.c | 8 +
drivers/net/ethernet/mellanox/mlx5/core/lag_mp.h | 2 +
.../net/ethernet/pensando/ionic/ionic_devlink.c | 14 +-
drivers/net/ethernet/qualcomm/qca_spi.c | 2 +-
drivers/net/ethernet/qualcomm/qca_uart.c | 2 +-
drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c | 5 +-
drivers/net/ethernet/ti/am65-cpsw-nuss.c | 47 ++--
drivers/net/ethernet/ti/am65-cpsw-nuss.h | 2 +
drivers/net/phy/marvell10g.c | 8 +
drivers/net/usb/asix_devices.c | 1 +
drivers/net/wireless/ath/ath6kl/wmi.c | 4 +-
.../wireless/broadcom/brcm80211/brcmfmac/pcie.c | 2 +-
drivers/net/wireless/intel/iwlwifi/fw/acpi.c | 14 +-
drivers/net/wireless/intel/iwlwifi/pcie/drv.c | 1 +
drivers/net/wireless/rsi/rsi_91x_hal.c | 4 +-
drivers/net/wireless/rsi/rsi_91x_usb.c | 1 +
drivers/nvme/host/rdma.c | 4 +-
drivers/nvme/host/tcp.c | 4 +-
drivers/nvme/target/fabrics-cmd.c | 9 +-
drivers/pci/pci.c | 25 +-
drivers/power/supply/axp288_fuel_gauge.c | 4 +-
drivers/power/supply/cw2015_battery.c | 4 +-
drivers/power/supply/max17042_battery.c | 2 +-
drivers/power/supply/smb347-charger.c | 10 +
drivers/regulator/tps65910-regulator.c | 10 +-
drivers/regulator/vctrl-regulator.c | 73 +++---
drivers/s390/cio/css.c | 17 ++
drivers/s390/crypto/ap_bus.c | 25 +-
drivers/s390/crypto/ap_bus.h | 10 +-
drivers/s390/crypto/ap_queue.c | 20 +-
drivers/s390/crypto/zcrypt_ccamisc.c | 8 +-
drivers/soc/mediatek/mt8183-mmsys.h | 21 +-
drivers/soc/mediatek/mtk-mmsys.c | 7 +-
drivers/soc/mediatek/mtk-mmsys.h | 133 +++++++---
drivers/soc/qcom/rpmhpd.c | 5 +-
drivers/soc/qcom/smsm.c | 11 +-
drivers/soc/rockchip/Kconfig | 4 +-
drivers/spi/spi-coldfire-qspi.c | 2 +-
drivers/spi/spi-davinci.c | 8 +-
drivers/spi/spi-fsl-dspi.c | 1 +
drivers/spi/spi-pic32.c | 1 +
drivers/spi/spi-sprd-adi.c | 2 +-
drivers/spi/spi-zynq-qspi.c | 8 +-
drivers/staging/clocking-wizard/Kconfig | 2 +-
.../staging/media/atomisp/i2c/atomisp-mt9m114.c | 11 +-
drivers/staging/media/tegra-video/vi.c | 4 +-
drivers/tty/serial/fsl_lpuart.c | 2 +-
drivers/tty/tty_io.c | 4 +-
drivers/usb/dwc3/dwc3-meson-g12a.c | 2 +
drivers/usb/dwc3/dwc3-qcom.c | 4 +
drivers/usb/gadget/udc/at91_udc.c | 4 +-
drivers/usb/gadget/udc/bdc/bdc_core.c | 30 +--
drivers/usb/gadget/udc/mv_u3d_core.c | 19 +-
drivers/usb/gadget/udc/renesas_usb3.c | 17 +-
drivers/usb/gadget/udc/s3c2410_udc.c | 4 +
drivers/usb/host/ehci-orion.c | 8 +-
drivers/usb/host/ohci-tmio.c | 3 +
drivers/usb/misc/brcmstb-usb-pinmap.c | 2 +
drivers/usb/phy/phy-fsl-usb.c | 2 +
drivers/usb/phy/phy-tahvo.c | 4 +-
drivers/usb/phy/phy-twl6030-usb.c | 5 +
drivers/video/backlight/pwm_bl.c | 54 ++--
drivers/video/fbdev/core/fbmem.c | 6 +
fs/cifs/cifs_unicode.c | 9 +-
fs/cifs/fs_context.c | 11 +-
fs/cifs/readdir.c | 23 +-
fs/debugfs/file.c | 8 +-
fs/f2fs/file.c | 5 +-
fs/f2fs/super.c | 11 +-
fs/fcntl.c | 18 +-
fs/fuse/file.c | 30 ++-
fs/fuse/fuse_i.h | 19 ++
fs/fuse/inode.c | 60 +++++
fs/gfs2/ops_fstype.c | 43 ++++
fs/gfs2/super.c | 61 +----
fs/io-wq.c | 105 +++++---
fs/io_uring.c | 5 +
fs/iomap/swapfile.c | 6 +
fs/isofs/inode.c | 27 +-
fs/isofs/isofs.h | 1 -
fs/isofs/joliet.c | 4 +-
fs/lockd/svclock.c | 2 +-
fs/nfsd/nfs4state.c | 4 +-
fs/udf/misc.c | 13 +-
fs/udf/super.c | 75 +++---
fs/udf/udf_sb.h | 2 -
fs/udf/unicode.c | 4 +-
include/linux/blkdev.h | 16 ++
include/linux/energy_model.h | 16 ++
include/linux/hrtimer.h | 5 -
include/linux/local_lock_internal.h | 42 +--
include/linux/mlx5/mlx5_ifc.h | 3 +-
include/linux/power/max17042_battery.h | 2 +-
include/linux/sunrpc/svc.h | 1 +
include/linux/time64.h | 9 +-
include/net/dsa.h | 2 -
include/net/pkt_cls.h | 3 +-
include/trace/events/io_uring.h | 6 +-
include/trace/events/sunrpc.h | 8 +-
include/uapi/linux/bpf.h | 2 +-
kernel/bpf/verifier.c | 31 ++-
kernel/cgroup/cpuset.c | 95 ++++---
kernel/cpu_pm.c | 50 +++-
kernel/irq/timings.c | 2 +
kernel/locking/mutex.c | 15 +-
kernel/power/energy_model.c | 4 +-
kernel/rcu/tree_stall.h | 26 +-
kernel/sched/core.c | 25 +-
kernel/sched/deadline.c | 8 +-
kernel/sched/debug.c | 7 +
kernel/sched/fair.c | 2 +-
kernel/sched/sched.h | 2 +
kernel/sched/topology.c | 65 +++++
kernel/time/hrtimer.c | 92 +++++--
kernel/time/posix-cpu-timers.c | 2 -
kernel/time/tick-internal.h | 3 +
lib/mpi/mpiutil.c | 2 +-
lib/test_scanf.c | 4 +-
net/6lowpan/debugfs.c | 3 +-
net/bluetooth/cmtp/cmtp.h | 2 +-
net/bluetooth/hci_core.c | 22 +-
net/bluetooth/mgmt.c | 2 +-
net/bluetooth/sco.c | 11 +-
net/core/devlink.c | 36 ++-
net/dsa/Kconfig | 13 +-
net/dsa/Makefile | 3 +-
net/dsa/dsa_priv.h | 2 -
net/dsa/port.c | 21 --
net/dsa/slave.c | 6 -
net/dsa/tag_8021q.c | 2 -
net/ipv4/route.c | 48 ++--
net/ipv4/tcp_ipv4.c | 5 +-
net/ipv6/route.c | 5 +-
net/mac80211/main.c | 2 +-
net/mac80211/tx.c | 4 +-
net/netlabel/netlabel_cipso_v4.c | 8 +-
net/qrtr/qrtr.c | 8 +-
net/sched/sch_cbq.c | 2 +-
net/sched/sch_htb.c | 97 ++++---
net/sunrpc/svc.c | 15 ++
samples/bpf/xdp_redirect_cpu_user.c | 2 +-
samples/pktgen/pktgen_sample04_many_flows.sh | 12 +-
samples/pktgen/pktgen_sample05_flow_per_thread.sh | 12 +-
security/integrity/ima/Kconfig | 1 -
security/integrity/ima/ima_mok.c | 2 +-
sound/soc/codecs/rt5682-i2c.c | 15 +-
sound/soc/codecs/tlv320aic32x4.c | 2 +-
sound/soc/codecs/wcd9335.c | 23 +-
sound/soc/codecs/wm_adsp.c | 2 +
sound/soc/fsl/fsl_rpmsg.c | 20 +-
sound/soc/intel/boards/kbl_da7219_max98927.c | 55 +---
sound/soc/intel/common/soc-acpi-intel-cml-match.c | 2 +-
sound/soc/intel/common/soc-acpi-intel-kbl-match.c | 2 +-
sound/soc/intel/skylake/skl-topology.c | 25 +-
sound/soc/mediatek/mt8183/mt8183-afe-pcm.c | 43 ++--
sound/soc/mediatek/mt8192/mt8192-afe-pcm.c | 27 +-
sound/usb/card.c | 4 +
sound/usb/pcm.c | 3 +-
sound/usb/usbaudio.h | 1 +
tools/bootconfig/main.c | 4 +-
tools/bpf/bpftool/prog.c | 5 +-
tools/include/uapi/linux/bpf.h | 2 +-
tools/lib/bpf/Makefile | 10 +-
tools/lib/bpf/libbpf.c | 20 +-
tools/perf/util/bpf-event.c | 4 +-
tools/perf/util/bpf_counter.c | 3 +-
tools/testing/selftests/bpf/prog_tests/btf.c | 1 +
tools/testing/selftests/bpf/progs/bpf_iter_tcp4.c | 2 +-
.../selftests/bpf/progs/test_core_autosize.c | 20 +-
tools/testing/selftests/bpf/test_maps.c | 4 +-
365 files changed, 3272 insertions(+), 1796 deletions(-)
^ permalink raw reply [relevance 2%]
* [PATCH 5.13 099/300] soc: qcom: rpmhpd: Use corner in power_off
@ 2021-09-13 13:12 8% ` Greg Kroah-Hartman
0 siblings, 0 replies; 200+ results
From: Greg Kroah-Hartman @ 2021-09-13 13:12 UTC (permalink / raw)
To: linux-kernel
Cc: Greg Kroah-Hartman, stable, Rajendra Nayak, Stephen Boyd,
Sibi Sankar, Bjorn Andersson, Sasha Levin
From: Bjorn Andersson <bjorn.andersson@linaro.org>
[ Upstream commit d43b3a989bc8c06fd4bbb69a7500d180db2d68e8 ]
rpmhpd_aggregate_corner() takes a corner as parameter, but in
rpmhpd_power_off() the code requests the level of the first corner
instead.
In all (known) current cases the first corner has level 0, so this
change should be a nop, but in case that there's a power domain with a
non-zero lowest level this makes sure that rpmhpd_power_off() actually
requests the lowest level - which is the closest to "power off" we can
get.
While touching the code, also skip the unnecessary zero-initialization
of "ret".
Fixes: 279b7e8a62cc ("soc: qcom: rpmhpd: Add RPMh power domain driver")
Reviewed-by: Rajendra Nayak <rnayak@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Sibi Sankar <sibis@codeaurora.org>
Tested-by: Sibi Sankar <sibis@codeaurora.org>
Link: https://lore.kernel.org/r/20210703005416.2668319-2-bjorn.andersson@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
drivers/soc/qcom/rpmhpd.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/soc/qcom/rpmhpd.c b/drivers/soc/qcom/rpmhpd.c
index bb21c4f1c0c4..90d2e5817371 100644
--- a/drivers/soc/qcom/rpmhpd.c
+++ b/drivers/soc/qcom/rpmhpd.c
@@ -382,12 +382,11 @@ static int rpmhpd_power_on(struct generic_pm_domain *domain)
static int rpmhpd_power_off(struct generic_pm_domain *domain)
{
struct rpmhpd *pd = domain_to_rpmhpd(domain);
- int ret = 0;
+ int ret;
mutex_lock(&rpmhpd_lock);
- ret = rpmhpd_aggregate_corner(pd, pd->level[0]);
-
+ ret = rpmhpd_aggregate_corner(pd, 0);
if (!ret)
pd->enabled = false;
--
2.30.2
^ permalink raw reply related [relevance 8%]
* [PATCH 5.10 085/236] soc: qcom: rpmhpd: Use corner in power_off
@ 2021-09-13 13:13 8% ` Greg Kroah-Hartman
0 siblings, 0 replies; 200+ results
From: Greg Kroah-Hartman @ 2021-09-13 13:13 UTC (permalink / raw)
To: linux-kernel
Cc: Greg Kroah-Hartman, stable, Rajendra Nayak, Stephen Boyd,
Sibi Sankar, Bjorn Andersson, Sasha Levin
From: Bjorn Andersson <bjorn.andersson@linaro.org>
[ Upstream commit d43b3a989bc8c06fd4bbb69a7500d180db2d68e8 ]
rpmhpd_aggregate_corner() takes a corner as parameter, but in
rpmhpd_power_off() the code requests the level of the first corner
instead.
In all (known) current cases the first corner has level 0, so this
change should be a nop, but in case that there's a power domain with a
non-zero lowest level this makes sure that rpmhpd_power_off() actually
requests the lowest level - which is the closest to "power off" we can
get.
While touching the code, also skip the unnecessary zero-initialization
of "ret".
Fixes: 279b7e8a62cc ("soc: qcom: rpmhpd: Add RPMh power domain driver")
Reviewed-by: Rajendra Nayak <rnayak@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Sibi Sankar <sibis@codeaurora.org>
Tested-by: Sibi Sankar <sibis@codeaurora.org>
Link: https://lore.kernel.org/r/20210703005416.2668319-2-bjorn.andersson@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
drivers/soc/qcom/rpmhpd.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/soc/qcom/rpmhpd.c b/drivers/soc/qcom/rpmhpd.c
index e72426221a69..c8b584d0c8fb 100644
--- a/drivers/soc/qcom/rpmhpd.c
+++ b/drivers/soc/qcom/rpmhpd.c
@@ -310,12 +310,11 @@ static int rpmhpd_power_on(struct generic_pm_domain *domain)
static int rpmhpd_power_off(struct generic_pm_domain *domain)
{
struct rpmhpd *pd = domain_to_rpmhpd(domain);
- int ret = 0;
+ int ret;
mutex_lock(&rpmhpd_lock);
- ret = rpmhpd_aggregate_corner(pd, pd->level[0]);
-
+ ret = rpmhpd_aggregate_corner(pd, 0);
if (!ret)
pd->enabled = false;
--
2.30.2
^ permalink raw reply related [relevance 8%]
* [PATCH 5.4 054/144] soc: qcom: rpmhpd: Use corner in power_off
@ 2021-09-13 13:13 8% ` Greg Kroah-Hartman
0 siblings, 0 replies; 200+ results
From: Greg Kroah-Hartman @ 2021-09-13 13:13 UTC (permalink / raw)
To: linux-kernel
Cc: Greg Kroah-Hartman, stable, Rajendra Nayak, Stephen Boyd,
Sibi Sankar, Bjorn Andersson, Sasha Levin
From: Bjorn Andersson <bjorn.andersson@linaro.org>
[ Upstream commit d43b3a989bc8c06fd4bbb69a7500d180db2d68e8 ]
rpmhpd_aggregate_corner() takes a corner as parameter, but in
rpmhpd_power_off() the code requests the level of the first corner
instead.
In all (known) current cases the first corner has level 0, so this
change should be a nop, but in case that there's a power domain with a
non-zero lowest level this makes sure that rpmhpd_power_off() actually
requests the lowest level - which is the closest to "power off" we can
get.
While touching the code, also skip the unnecessary zero-initialization
of "ret".
Fixes: 279b7e8a62cc ("soc: qcom: rpmhpd: Add RPMh power domain driver")
Reviewed-by: Rajendra Nayak <rnayak@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Sibi Sankar <sibis@codeaurora.org>
Tested-by: Sibi Sankar <sibis@codeaurora.org>
Link: https://lore.kernel.org/r/20210703005416.2668319-2-bjorn.andersson@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
drivers/soc/qcom/rpmhpd.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/soc/qcom/rpmhpd.c b/drivers/soc/qcom/rpmhpd.c
index 51850cc68b70..aa24237a7840 100644
--- a/drivers/soc/qcom/rpmhpd.c
+++ b/drivers/soc/qcom/rpmhpd.c
@@ -235,12 +235,11 @@ static int rpmhpd_power_on(struct generic_pm_domain *domain)
static int rpmhpd_power_off(struct generic_pm_domain *domain)
{
struct rpmhpd *pd = domain_to_rpmhpd(domain);
- int ret = 0;
+ int ret;
mutex_lock(&rpmhpd_lock);
- ret = rpmhpd_aggregate_corner(pd, pd->level[0]);
-
+ ret = rpmhpd_aggregate_corner(pd, 0);
if (!ret)
pd->enabled = false;
--
2.30.2
^ permalink raw reply related [relevance 8%]
* [PATCH AUTOSEL 5.10 089/176] arm64: dts: qcom: sm8250: Fix epss_l3 unit address
@ 2021-09-09 11:49 6% ` Sasha Levin
0 siblings, 0 replies; 200+ results
From: Sasha Levin @ 2021-09-09 11:49 UTC (permalink / raw)
To: linux-kernel, stable
Cc: Georgi Djakov, Dmitry Baryshkov, Sibi Sankar, Bjorn Andersson,
Sasha Levin, linux-arm-msm, devicetree
From: Georgi Djakov <georgi.djakov@linaro.org>
[ Upstream commit 77b53d65dc1e54321ec841912f06bcb558a079c0 ]
The unit address of the epss_l3 node is incorrect and does not match
the address of its "reg" property. Let's fix it.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Sibi Sankar <sibis@codeaurora.org>
Link: https://lore.kernel.org/r/20210211193637.9737-1-georgi.djakov@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index d4547a192748..ec356fe07ac8 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -2346,7 +2346,7 @@ apps_bcm_voter: bcm_voter {
};
};
- epss_l3: interconnect@18591000 {
+ epss_l3: interconnect@18590000 {
compatible = "qcom,sm8250-epss-l3";
reg = <0 0x18590000 0 0x1000>;
--
2.30.2
^ permalink raw reply related [relevance 6%]
* [PATCH AUTOSEL 5.13 109/219] arm64: dts: qcom: sm8250: Fix epss_l3 unit address
@ 2021-09-09 11:44 6% ` Sasha Levin
0 siblings, 0 replies; 200+ results
From: Sasha Levin @ 2021-09-09 11:44 UTC (permalink / raw)
To: linux-kernel, stable
Cc: Georgi Djakov, Dmitry Baryshkov, Sibi Sankar, Bjorn Andersson,
Sasha Levin, linux-arm-msm, devicetree
From: Georgi Djakov <georgi.djakov@linaro.org>
[ Upstream commit 77b53d65dc1e54321ec841912f06bcb558a079c0 ]
The unit address of the epss_l3 node is incorrect and does not match
the address of its "reg" property. Let's fix it.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Sibi Sankar <sibis@codeaurora.org>
Link: https://lore.kernel.org/r/20210211193637.9737-1-georgi.djakov@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 09b552396557..169412f42149 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -3773,7 +3773,7 @@ apps_bcm_voter: bcm_voter {
};
};
- epss_l3: interconnect@18591000 {
+ epss_l3: interconnect@18590000 {
compatible = "qcom,sm8250-epss-l3";
reg = <0 0x18590000 0 0x1000>;
--
2.30.2
^ permalink raw reply related [relevance 6%]
* [PATCH AUTOSEL 5.14 124/252] arm64: dts: qcom: sm8250: Fix epss_l3 unit address
@ 2021-09-09 11:38 6% ` Sasha Levin
0 siblings, 0 replies; 200+ results
From: Sasha Levin @ 2021-09-09 11:38 UTC (permalink / raw)
To: linux-kernel, stable
Cc: Georgi Djakov, Dmitry Baryshkov, Sibi Sankar, Bjorn Andersson,
Sasha Levin, linux-arm-msm, devicetree
From: Georgi Djakov <georgi.djakov@linaro.org>
[ Upstream commit 77b53d65dc1e54321ec841912f06bcb558a079c0 ]
The unit address of the epss_l3 node is incorrect and does not match
the address of its "reg" property. Let's fix it.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Sibi Sankar <sibis@codeaurora.org>
Link: https://lore.kernel.org/r/20210211193637.9737-1-georgi.djakov@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 4798368b02ef..ecfe4b538a12 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -3955,7 +3955,7 @@ apps_bcm_voter: bcm_voter {
};
};
- epss_l3: interconnect@18591000 {
+ epss_l3: interconnect@18590000 {
compatible = "qcom,sm8250-epss-l3";
reg = <0 0x18590000 0 0x1000>;
--
2.30.2
^ permalink raw reply related [relevance 6%]
* RE: [PATCH v2] arm64: dts: qcom: sc7280: Add WPSS remoteproc node
@ 2021-09-09 8:38 0% ` pillair
0 siblings, 0 replies; 200+ results
From: pillair @ 2021-09-09 8:38 UTC (permalink / raw)
To: 'Stephen Boyd', agross, bjorn.andersson, robh+dt
Cc: linux-arm-msm, devicetree, linux-kernel, sibis, mpubbise
> -----Original Message-----
> From: Stephen Boyd <swboyd@chromium.org>
> Sent: Wednesday, August 11, 2021 1:22 AM
> To: Rakesh Pillai <pillair@codeaurora.org>; agross@kernel.org;
> bjorn.andersson@linaro.org; robh+dt@kernel.org
> Cc: linux-arm-msm@vger.kernel.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; sibis@codeaurora.org; mpubbise@codeaurora.org
> Subject: Re: [PATCH v2] arm64: dts: qcom: sc7280: Add WPSS remoteproc
> node
>
> Quoting Rakesh Pillai (2021-08-10 11:11:29)
> > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > index 53a21d0..41a7826 100644
> > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > @@ -74,6 +74,16 @@
> > reg = <0 0x8b700000 0 0x10000>;
> > no-map;
> > };
> > +
> > + wlan_fw_mem: memory@80c00000 {
> > + no-map;
> > + reg = <0x0 0x80c00000 0x0 0xc00000>;
> > + };
>
> Please try to keep this sorted by reg address. 80c00000 comes before
> 8b700000.
>
Hi Stephen,
I will fix this and send v3 for this patch.
> > +
> > + wpss_mem: memory@9ae00000 {
> > + no-map;
> > + reg = <0x0 0x9ae00000 0x0 0x1900000>;
> > + };
> > };
> >
> > cpus {
> > @@ -1270,6 +1280,53 @@
> > };
> > };
> >
> > + remoteproc_wpss: remoteproc@8a00000 {
> > + compatible = "qcom,sc7280-wpss-pil";
> > + reg = <0 0x08a00000 0 0x10000>;
> > +
> > + interrupts-extended = <&intc GIC_SPI 587
> IRQ_TYPE_EDGE_RISING>,
> > + <&wpss_smp2p_in 0 IRQ_TYPE_NONE>,
> > + <&wpss_smp2p_in 1 IRQ_TYPE_NONE>,
> > + <&wpss_smp2p_in 2 IRQ_TYPE_NONE>,
> > + <&wpss_smp2p_in 3 IRQ_TYPE_NONE>,
> > + <&wpss_smp2p_in 7
> > + IRQ_TYPE_NONE>;
>
> Is this IRQ_TYPE_EDGE_RISING? Please add some type of edge or level flag.
I will change it to IRQ_TYPE_EDGE_RISING and send out the next revision.
>
> > + interrupt-names = "wdog", "fatal", "ready", "handover",
> > + "stop-ack", "shutdown-ack";
> > +
> > + clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>,
> > + <&gcc GCC_WPSS_AHB_CLK>,
> > + <&gcc GCC_WPSS_RSCP_CLK>,
> > + <&rpmhcc RPMH_CXO_CLK>;
> > + clock-names = "gcc_wpss_ahb_bdg_mst_clk",
> > + "gcc_wpss_ahb_clk",
> > + "gcc_wpss_rscp_clk",
> > + "xo";
> > +
> > + memory-region = <&wpss_mem>;
> > +
> > + qcom,smem-states = <&wpss_smp2p_out 0>;
^ permalink raw reply [relevance 0%]
* RE: [PATCH v2 2/3] dt-bindings: remoteproc: qcom: Add SC7280 WPSS support
@ 2021-09-09 8:36 0% ` pillair
0 siblings, 0 replies; 200+ results
From: pillair @ 2021-09-09 8:36 UTC (permalink / raw)
To: 'Rob Herring'
Cc: robh+dt, sibis, sboyd, bjorn.andersson, agross, linux-kernel,
devicetree, mpubbise, linux-arm-msm
> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: Wednesday, August 11, 2021 10:55 PM
> To: Rakesh Pillai <pillair@codeaurora.org>
> Cc: robh+dt@kernel.org; sibis@codeaurora.org; sboyd@kernel.org;
> bjorn.andersson@linaro.org; agross@kernel.org; linux-
> kernel@vger.kernel.org; devicetree@vger.kernel.org;
> mpubbise@codeaurora.org; linux-arm-msm@vger.kernel.org
> Subject: Re: [PATCH v2 2/3] dt-bindings: remoteproc: qcom: Add SC7280
> WPSS support
>
> On Tue, 10 Aug 2021 23:31:22 +0530, Rakesh Pillai wrote:
> > Add WPSS PIL loading support for SC7280 SoCs.
> >
> > Signed-off-by: Rakesh Pillai <pillair@codeaurora.org>
> > ---
> > .../bindings/remoteproc/qcom,hexagon-v56.yaml | 79
> ++++++++++++++++++++--
> > 1 file changed, 74 insertions(+), 5 deletions(-)
> >
>
> My bot found errors running 'make DT_CHECKER_FLAGS=-m
> dt_binding_check'
> on your patch (DT_CHECKER_FLAGS is new in v5.13):
>
> yamllint warnings/errors:
>
> dtschema/dtc warnings/errors:
> /builds/robherring/linux-dt-
> review/Documentation/devicetree/bindings/remoteproc/qcom,hexagon-
> v56.example.dt.yaml: remoteproc@17300000: 'power-domain-names' is a
> required property
> From schema: /builds/robherring/linux-dt-
> review/Documentation/devicetree/bindings/remoteproc/qcom,hexagon-
> v56.yaml
>
> doc reference errors (make refcheckdocs):
>
> See https://patchwork.ozlabs.org/patch/1515482
>
> This check can fail if there are any dependencies. The base for a patch
series
> is generally the most recent rc1.
>
> If you already ran 'make dt_binding_check' and didn't see the above
error(s),
> then make sure 'yamllint' is installed and dt-schema is up to
> date:
>
> pip3 install dtschema --upgrade
>
> Please check and re-submit.
Thanks Rob, I will submit next patchset for this and fix the issues.
^ permalink raw reply [relevance 0%]
* Re: [PATCH v6 02/13] dt-bindings: remoteproc: qcom: pas: Add QMP property
2021-09-06 8:23 15% ` [PATCH v6 02/13] dt-bindings: remoteproc: qcom: pas: Add QMP property Sibi Sankar
@ 2021-09-08 13:51 0% ` Rob Herring
2021-09-16 3:13 6% ` Sibi Sankar
0 siblings, 1 reply; 200+ results
From: Rob Herring @ 2021-09-08 13:51 UTC (permalink / raw)
To: Sibi Sankar
Cc: mka, swboyd, bjorn.andersson, ulf.hansson, rjw, agross, ohad,
mathieu.poirier, linux-arm-msm, linux-remoteproc, devicetree,
linux-kernel, dianders, rishabhb, sidgup
On Mon, Sep 06, 2021 at 01:53:46PM +0530, Sibi Sankar wrote:
> The load state power-domain, used by the co-processors to notify the
> Always on Subsystem (AOSS) that a particular co-processor is up/down,
> suffers from the side-effect of changing states during suspend/resume.
> However the co-processors enter low-power modes independent to that of
> the application processor and their states are expected to remain
> unaltered across system suspend/resume cycles. To achieve this behavior
> let's drop the load state power-domain and replace them with the qmp
> property for all SoCs supporting low power mode signalling.
>
> Due to the current broken load state implementation, we can afford the
> binding breakage that ensues and the remoteproc functionality will remain
> the same when using newer kernels with older dtbs.
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> Reviewed-by: Stephen Boyd <swboyd@chromium.org>
> ---
>
> v6:
> * Updated commit message to explain binding breakage. [Stephen]
>
> .../devicetree/bindings/remoteproc/qcom,adsp.yaml | 61 +++++++++++-----------
> 1 file changed, 31 insertions(+), 30 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml
> index 0c112f3264a9..0d2b5bd4907a 100644
> --- a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml
> +++ b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml
> @@ -93,6 +93,10 @@ properties:
> maxItems: 1
> description: Reference to the reserved-memory for the Hexagon core
>
> + qcom,qmp:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description: Reference to the AOSS side-channel message RAM.
> +
[...]
> @@ -511,6 +486,32 @@ allOf:
> - const: mss_restart
> - const: pdc_reset
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,sc7180-mpss-pas
> + - qcom,sc8180x-adsp-pas
> + - qcom,sc8180x-cdsp-pas
> + - qcom,sc8180x-mpss-pas
> + - qcom,sm8150-adsp-pas
> + - qcom,sm8150-cdsp-pas
> + - qcom,sm8150-mpss-pas
> + - qcom,sm8150-slpi-pas
> + - qcom,sm8250-adsp-pas
> + - qcom,sm8250-cdsp-pas
> + - qcom,sm8250-slpi-pas
> + - qcom,sm8350-adsp-pas
> + - qcom,sm8350-cdsp-pas
> + - qcom,sm8350-mpss-pas
> + - qcom,sm8350-slpi-pas
> + then:
> + properties:
> + qcom,qmp:
> + items:
> + - description: Reference to the AOSS side-channel message RAM.
This doesn't do anything. The property is already allowed for all
compatibles. Perhaps you want to negate the if and put 'qcom,qmp: false'
here.
Rob
^ permalink raw reply [relevance 0%]
* Re: [PATCH v4 05/10] remoteproc: mss: q6v5-mss: Add modem support on SC7280
2021-09-06 8:54 11% ` [PATCH v4 05/10] remoteproc: mss: q6v5-mss: Add modem support on SC7280 Sibi Sankar
@ 2021-09-07 20:01 0% ` Stephen Boyd
0 siblings, 0 replies; 200+ results
From: Stephen Boyd @ 2021-09-07 20:01 UTC (permalink / raw)
To: Sibi Sankar, bjorn.andersson, mka, robh+dt, saiprakash.ranjan, will
Cc: ohad, agross, mathieu.poirier, robin.murphy, joro, p.zabel,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
linux-arm-kernel, evgreen, dianders
Quoting Sibi Sankar (2021-09-06 01:54:40)
> Add out of reset sequence support for modem sub-system on SC7280 SoCs.
> It requires access to an additional set of qaccept registers, external
> power/clk control registers and halt vq6 register to put the modem back
> into reset.
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
^ permalink raw reply [relevance 0%]
* Re: [PATCH] Revert "arm64: dts: qcom: sc7280: Fixup the cpufreq node"
2021-09-07 19:12 7% [PATCH] Revert "arm64: dts: qcom: sc7280: Fixup the cpufreq node" Douglas Anderson
@ 2021-09-07 19:56 0% ` Matthias Kaehlcke
0 siblings, 0 replies; 200+ results
From: Matthias Kaehlcke @ 2021-09-07 19:56 UTC (permalink / raw)
To: Douglas Anderson
Cc: Bjorn Andersson, Sibi Sankar, Stephen Boyd, Andy Gross,
Rob Herring, devicetree, linux-arm-msm, linux-kernel
On Tue, Sep 07, 2021 at 12:12:25PM -0700, Douglas Anderson wrote:
> This reverts commit 11e03d692101e484df9322f892a8b6e111a82bfd.
>
> As per discussion [1] the patch shouldn't have landed. Let's revert.
>
> [1] https://lore.kernel.org/r/fde7bac239f796b039b9be58b391fb77@codeaurora.org/
>
> Fixes: 11e03d692101 ("arm64: dts: qcom: sc7280: Fixup the cpufreq node")
> Reported-by: Matthias Kaehlcke <mka@chromium.org>
> Cc: Sibi Sankar <sibis@codeaurora.org>
> Cc: Matthias Kaehlcke <mka@chromium.org>
> Cc: Stephen Boyd <swboyd@chromium.org>
> Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
^ permalink raw reply [relevance 0%]
* Re: [PATCH 3/4] arm64: dts: qcom: sc7280: Fixup the cpufreq node
2021-09-06 3:20 6% ` Sibi Sankar
@ 2021-09-07 19:14 6% ` Doug Anderson
0 siblings, 0 replies; 200+ results
From: Doug Anderson @ 2021-09-07 19:14 UTC (permalink / raw)
To: Sibi Sankar
Cc: Bjorn Andersson, Matthias Kaehlcke, Stephen Boyd, Rob Herring,
Viresh Kumar, Andy Gross, Rafael J. Wysocki, linux-arm-msm,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, LKML,
Linux PM, Taniya Das
Hi,
On Sun, Sep 5, 2021 at 8:20 PM Sibi Sankar <sibis@codeaurora.org> wrote:
>
> On 2021-08-31 22:34, Bjorn Andersson wrote:
> > On Tue 31 Aug 08:30 PDT 2021, Matthias Kaehlcke wrote:
> >
> >> On Thu, Jul 29, 2021 at 11:34:44PM +0530, Sibi Sankar wrote:
> >> > Fixup the register regions used by the cpufreq node on SC7280 SoC to
> >> > support per core L3 DCVS.
> >> >
> >> > Fixes: 7dbd121a2c58 ("arm64: dts: qcom: sc7280: Add cpufreq hw node")
> >> > Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> >>
> >> This patch landed in the Bjorn's tree, however the corresponding
> >> driver
> >> change ("cpufreq: qcom: Re-arrange register offsets to support per
> >> core
> >> L3 DCVS" /
> >> https://patchwork.kernel.org/project/linux-arm-msm/patch/1627581885-32165-3-git-send-email-sibis@codeaurora.org/)
> >> did not land in any maintainer tree yet AFAIK. IIUC the DT change
> >> alone
> >> breaks cpufreq since the changed register regions require the changed
> >> offset in the cpufreq driver.
> >>
> >
> > Thanks for the note Matthias, it must have slipped by as I scraped the
> > inbox for things that looked ready.
> >
> > I'm actually not in favor of splitting these memory blocks in DT to
> > facilitate the Linux implementation of splitting that in multiple
> > drivers...
> >
> > But I've not been following up on that discussion.
> >
> > Regards,
> > Bjorn
> >
> >> Sibi, please confirm or clarify that my concern is unwarranted.
>
> Let's drop the patch asap as it breaks
> SC7280 cpufreq on lnext without the driver
> changes.
It's already landed so we need a revert:
https://lore.kernel.org/r/20210907121220.1.I08460f490473b70de0d768db45f030a4d5c17828@changeid/
-Doug
^ permalink raw reply [relevance 6%]
* [PATCH] Revert "arm64: dts: qcom: sc7280: Fixup the cpufreq node"
@ 2021-09-07 19:12 7% Douglas Anderson
2021-09-07 19:56 0% ` Matthias Kaehlcke
0 siblings, 1 reply; 200+ results
From: Douglas Anderson @ 2021-09-07 19:12 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Douglas Anderson, Matthias Kaehlcke, Sibi Sankar, Stephen Boyd,
Andy Gross, Rob Herring, devicetree, linux-arm-msm, linux-kernel
This reverts commit 11e03d692101e484df9322f892a8b6e111a82bfd.
As per discussion [1] the patch shouldn't have landed. Let's revert.
[1] https://lore.kernel.org/r/fde7bac239f796b039b9be58b391fb77@codeaurora.org/
Fixes: 11e03d692101 ("arm64: dts: qcom: sc7280: Fixup the cpufreq node")
Reported-by: Matthias Kaehlcke <mka@chromium.org>
Cc: Sibi Sankar <sibis@codeaurora.org>
Cc: Matthias Kaehlcke <mka@chromium.org>
Cc: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 53a21d086178..fd78f16181dd 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -1850,9 +1850,9 @@ rpmhcc: clock-controller {
cpufreq_hw: cpufreq@18591000 {
compatible = "qcom,cpufreq-epss";
- reg = <0 0x18591100 0 0x900>,
- <0 0x18592100 0 0x900>,
- <0 0x18593100 0 0x900>;
+ reg = <0 0x18591000 0 0x1000>,
+ <0 0x18592000 0 0x1000>,
+ <0 0x18593000 0 0x1000>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
clock-names = "xo", "alternate";
#freq-domain-cells = <1>;
--
2.33.0.153.gba50c8fa24-goog
^ permalink raw reply related [relevance 7%]
* [PATCH v4 08/10] arm64: dts: qcom: sc7280: Add nodes to boot modem
2021-09-06 8:54 18% [PATCH v4 00/10] Add Modem support on SC7280 SoCs Sibi Sankar
` (6 preceding siblings ...)
2021-09-06 8:54 18% ` [PATCH v4 07/10] arm64: dts: qcom: sc7280: Add/Delete/Update reserved memory nodes Sibi Sankar
@ 2021-09-06 8:54 18% ` Sibi Sankar
2021-09-06 8:54 18% ` [PATCH v4 09/10] arm64: dts: qcom: sc7280: Add Q6V5 MSS node Sibi Sankar
2021-09-06 8:54 17% ` [PATCH v4 10/10] arm64: dts: qcom: sc7280: Update " Sibi Sankar
9 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-09-06 8:54 UTC (permalink / raw)
To: bjorn.andersson, robh+dt, will, saiprakash.ranjan, swboyd, mka
Cc: ohad, agross, mathieu.poirier, robin.murphy, joro, p.zabel,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
linux-arm-kernel, evgreen, dianders, Sibi Sankar
Add miscellaneous nodes to boot the modem and support post-mortem debug
on SC7280 SoCs.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 894106efadfe..bd1ac93017ae 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -662,6 +662,11 @@
#hwlock-cells = <1>;
};
+ tcsr: syscon@1fc0000 {
+ compatible = "qcom,sc7280-tcsr", "syscon";
+ reg = <0 0x01fc0000 0 0x30000>;
+ };
+
lpasscc: lpasscc@3000000 {
compatible = "qcom,sc7280-lpasscc";
reg = <0 0x03000000 0 0x40>,
@@ -1632,6 +1637,21 @@
};
};
+ imem@146a5000 {
+ compatible = "qcom,sc7280-imem", "syscon";
+ reg = <0 0x146a5000 0 0x6000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ranges = <0 0 0x146a5000 0x6000>;
+
+ pil-reloc@594c {
+ compatible = "qcom,pil-reloc-info";
+ reg = <0x594c 0xc8>;
+ };
+ };
+
apps_smmu: iommu@15000000 {
compatible = "qcom,sc7280-smmu-500", "arm,mmu-500";
reg = <0 0x15000000 0 0x100000>;
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 18%]
* [PATCH v4 10/10] arm64: dts: qcom: sc7280: Update Q6V5 MSS node
2021-09-06 8:54 18% [PATCH v4 00/10] Add Modem support on SC7280 SoCs Sibi Sankar
` (8 preceding siblings ...)
2021-09-06 8:54 18% ` [PATCH v4 09/10] arm64: dts: qcom: sc7280: Add Q6V5 MSS node Sibi Sankar
@ 2021-09-06 8:54 17% ` Sibi Sankar
9 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-09-06 8:54 UTC (permalink / raw)
To: bjorn.andersson, robh+dt, will, saiprakash.ranjan, swboyd, mka
Cc: ohad, agross, mathieu.poirier, robin.murphy, joro, p.zabel,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
linux-arm-kernel, evgreen, dianders, Sibi Sankar
Update MSS node to support MSA based modem boot on SC7280 SoCs.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 7 +++++++
arch/arm64/boot/dts/qcom/sc7280.dtsi | 18 +++++++++++++++---
2 files changed, 22 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
index 103d89c1e1c7..f1c8641b0c26 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
@@ -263,6 +263,13 @@
status = "okay";
};
+&remoteproc_mpss {
+ status = "okay";
+ compatible = "qcom,sc7280-mss-pil";
+ iommus = <&apps_smmu 0x124 0x0>, <&apps_smmu 0x488 0x7>;
+ memory-region = <&mba_mem &mpss_mem>;
+};
+
&sdhc_1 {
status = "okay";
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 93ae3ee8c5a6..2644d8575a23 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -701,7 +701,8 @@
remoteproc_mpss: remoteproc@4080000 {
compatible = "qcom,sc7280-mpss-pas";
- reg = <0 0x04080000 0 0x10000>;
+ reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>;
+ reg-names = "qdsp6", "rmb";
interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
@@ -712,8 +713,11 @@
interrupt-names = "wdog", "fatal", "ready", "handover",
"stop-ack", "shutdown-ack";
- clocks = <&rpmhcc RPMH_CXO_CLK>;
- clock-names = "xo";
+ clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
+ <&gcc GCC_MSS_OFFLINE_AXI_CLK>,
+ <&gcc GCC_MSS_SNOC_AXI_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "offline", "snoc_axi", "xo";
power-domains = <&rpmhpd SC7280_CX>,
<&rpmhpd SC7280_MSS>;
@@ -726,6 +730,14 @@
qcom,smem-states = <&modem_smp2p_out 0>;
qcom,smem-state-names = "stop";
+ resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
+ <&pdc_reset PDC_MODEM_SYNC_RESET>;
+ reset-names = "mss_restart", "pdc_reset";
+
+ qcom,halt-regs = <&tcsr_mutex 0x23000 0x25000 0x28000 0x33000>;
+ qcom,ext-regs = <&tcsr 0x10000 0x10004 &tcsr_mutex 0x26004 0x26008>;
+ qcom,qaccept-regs = <&tcsr_mutex 0x23030 0x23040 0x23020>;
+
status = "disabled";
glink-edge {
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 17%]
* [PATCH v4 09/10] arm64: dts: qcom: sc7280: Add Q6V5 MSS node
2021-09-06 8:54 18% [PATCH v4 00/10] Add Modem support on SC7280 SoCs Sibi Sankar
` (7 preceding siblings ...)
2021-09-06 8:54 18% ` [PATCH v4 08/10] arm64: dts: qcom: sc7280: Add nodes to boot modem Sibi Sankar
@ 2021-09-06 8:54 18% ` Sibi Sankar
2021-09-06 8:54 17% ` [PATCH v4 10/10] arm64: dts: qcom: sc7280: Update " Sibi Sankar
9 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-09-06 8:54 UTC (permalink / raw)
To: bjorn.andersson, robh+dt, will, saiprakash.ranjan, swboyd, mka
Cc: ohad, agross, mathieu.poirier, robin.murphy, joro, p.zabel,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
linux-arm-kernel, evgreen, dianders, Sibi Sankar
This patch adds Q6V5 MSS PAS remoteproc node for SC7280 SoCs.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 40 ++++++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index bd1ac93017ae..93ae3ee8c5a6 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -699,6 +699,46 @@
#power-domain-cells = <1>;
};
+ remoteproc_mpss: remoteproc@4080000 {
+ compatible = "qcom,sc7280-mpss-pas";
+ reg = <0 0x04080000 0 0x10000>;
+
+ interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog", "fatal", "ready", "handover",
+ "stop-ack", "shutdown-ack";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ power-domains = <&rpmhpd SC7280_CX>,
+ <&rpmhpd SC7280_MSS>;
+ power-domain-names = "cx", "mss";
+
+ memory-region = <&mpss_mem>;
+
+ qcom,qmp = <&aoss_qmp>;
+
+ qcom,smem-states = <&modem_smp2p_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_MPSS
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+ label = "modem";
+ qcom,remote-pid = <1>;
+ };
+ };
+
stm@6002000 {
compatible = "arm,coresight-stm", "arm,primecell";
reg = <0 0x06002000 0 0x1000>,
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 18%]
* [PATCH v4 04/10] iommu/arm-smmu-qcom: Request direct mapping for modem device
2021-09-06 8:54 18% [PATCH v4 00/10] Add Modem support on SC7280 SoCs Sibi Sankar
` (2 preceding siblings ...)
2021-09-06 8:54 14% ` [PATCH v4 03/10] dt-bindings: remoteproc: qcom: Update Q6V5 Modem PIL binding Sibi Sankar
@ 2021-09-06 8:54 19% ` Sibi Sankar
2021-09-06 8:54 11% ` [PATCH v4 05/10] remoteproc: mss: q6v5-mss: Add modem support on SC7280 Sibi Sankar
` (5 subsequent siblings)
9 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-09-06 8:54 UTC (permalink / raw)
To: bjorn.andersson, robh+dt, will, saiprakash.ranjan, swboyd, mka
Cc: ohad, agross, mathieu.poirier, robin.murphy, joro, p.zabel,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
linux-arm-kernel, evgreen, dianders, Sibi Sankar
The SID configuration requirement for Modem on SC7280 is similar to the
ones found on SC7180/SDM845 SoCs. So, add the SC7280 modem compatible to
the list to defer the programming of the modem SIDs to the kernel.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index 55690af1b25d..3b9b46fca0b3 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -231,6 +231,7 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = {
{ .compatible = "qcom,sc7180-mdss" },
{ .compatible = "qcom,sc7180-mss-pil" },
{ .compatible = "qcom,sc7280-mdss" },
+ { .compatible = "qcom,sc7280-mss-pil" },
{ .compatible = "qcom,sc8180x-mdss" },
{ .compatible = "qcom,sdm845-mdss" },
{ .compatible = "qcom,sdm845-mss-pil" },
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 19%]
* [PATCH v4 06/10] arm64: dts: qcom: sc7280: Update reserved memory map
2021-09-06 8:54 18% [PATCH v4 00/10] Add Modem support on SC7280 SoCs Sibi Sankar
` (4 preceding siblings ...)
2021-09-06 8:54 11% ` [PATCH v4 05/10] remoteproc: mss: q6v5-mss: Add modem support on SC7280 Sibi Sankar
@ 2021-09-06 8:54 18% ` Sibi Sankar
2021-09-06 8:54 18% ` [PATCH v4 07/10] arm64: dts: qcom: sc7280: Add/Delete/Update reserved memory nodes Sibi Sankar
` (3 subsequent siblings)
9 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-09-06 8:54 UTC (permalink / raw)
To: bjorn.andersson, robh+dt, will, saiprakash.ranjan, swboyd, mka
Cc: ohad, agross, mathieu.poirier, robin.murphy, joro, p.zabel,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
linux-arm-kernel, evgreen, dianders, Sibi Sankar
Add missing reserved regions as described in v1 of SC7280 memory map.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 34 ++++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 5e4f4f3b738a..894106efadfe 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -48,6 +48,16 @@
#size-cells = <2>;
ranges;
+ hyp_mem: memory@80000000 {
+ reg = <0x0 0x80000000 0x0 0x600000>;
+ no-map;
+ };
+
+ xbl_mem: memory@80600000 {
+ reg = <0x0 0x80600000 0x0 0x200000>;
+ no-map;
+ };
+
aop_mem: memory@80800000 {
reg = <0x0 0x80800000 0x0 0x60000>;
no-map;
@@ -59,6 +69,16 @@
no-map;
};
+ reserved_xbl_uefi_log: memory@80880000 {
+ reg = <0x0 0x80884000 0x0 0x10000>;
+ no-map;
+ };
+
+ sec_apps_mem: memory@808ff000 {
+ reg = <0x0 0x808ff000 0x0 0x1000>;
+ no-map;
+ };
+
smem_mem: memory@80900000 {
reg = <0x0 0x80900000 0x0 0x200000>;
no-map;
@@ -69,10 +89,24 @@
reg = <0x0 0x80b00000 0x0 0x100000>;
};
+ wlan_fw_mem: memory@80c00000 {
+ reg = <0x0 0x80c00000 0x0 0xc00000>;
+ no-map;
+ };
+
ipa_fw_mem: memory@8b700000 {
reg = <0 0x8b700000 0 0x10000>;
no-map;
};
+
+ rmtfs_mem: memory@9c900000 {
+ compatible = "qcom,rmtfs-mem";
+ reg = <0x0 0x9c900000 0x0 0x280000>;
+ no-map;
+
+ qcom,client-id = <1>;
+ qcom,vmid = <15>;
+ };
};
cpus {
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 18%]
* [PATCH v4 05/10] remoteproc: mss: q6v5-mss: Add modem support on SC7280
2021-09-06 8:54 18% [PATCH v4 00/10] Add Modem support on SC7280 SoCs Sibi Sankar
` (3 preceding siblings ...)
2021-09-06 8:54 19% ` [PATCH v4 04/10] iommu/arm-smmu-qcom: Request direct mapping for modem device Sibi Sankar
@ 2021-09-06 8:54 11% ` Sibi Sankar
2021-09-07 20:01 0% ` Stephen Boyd
2021-09-06 8:54 18% ` [PATCH v4 06/10] arm64: dts: qcom: sc7280: Update reserved memory map Sibi Sankar
` (4 subsequent siblings)
9 siblings, 1 reply; 200+ results
From: Sibi Sankar @ 2021-09-06 8:54 UTC (permalink / raw)
To: bjorn.andersson, robh+dt, will, saiprakash.ranjan, swboyd, mka
Cc: ohad, agross, mathieu.poirier, robin.murphy, joro, p.zabel,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
linux-arm-kernel, evgreen, dianders, Sibi Sankar
Add out of reset sequence support for modem sub-system on SC7280 SoCs.
It requires access to an additional set of qaccept registers, external
power/clk control registers and halt vq6 register to put the modem back
into reset.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
drivers/remoteproc/qcom_q6v5_mss.c | 252 ++++++++++++++++++++++++++++++++++++-
1 file changed, 248 insertions(+), 4 deletions(-)
diff --git a/drivers/remoteproc/qcom_q6v5_mss.c b/drivers/remoteproc/qcom_q6v5_mss.c
index 7a1422bd7925..90ff712f912c 100644
--- a/drivers/remoteproc/qcom_q6v5_mss.c
+++ b/drivers/remoteproc/qcom_q6v5_mss.c
@@ -77,6 +77,14 @@
#define HALT_ACK_TIMEOUT_US 100000
+/* QACCEPT Register Offsets */
+#define QACCEPT_ACCEPT_REG 0x0
+#define QACCEPT_ACTIVE_REG 0x4
+#define QACCEPT_DENY_REG 0x8
+#define QACCEPT_REQ_REG 0xC
+
+#define QACCEPT_TIMEOUT_US 50
+
/* QDSP6SS_RESET */
#define Q6SS_STOP_CORE BIT(0)
#define Q6SS_CORE_ARES BIT(1)
@@ -143,6 +151,9 @@ struct rproc_hexagon_res {
bool has_alt_reset;
bool has_mba_logs;
bool has_spare_reg;
+ bool has_qaccept_regs;
+ bool has_ext_cntl_regs;
+ bool has_vq6;
};
struct q6v5 {
@@ -158,8 +169,18 @@ struct q6v5 {
u32 halt_q6;
u32 halt_modem;
u32 halt_nc;
+ u32 halt_vq6;
u32 conn_box;
+ u32 qaccept_mdm;
+ u32 qaccept_cx;
+ u32 qaccept_axi;
+
+ u32 axim1_clk_off;
+ u32 crypto_clk_off;
+ u32 force_clk_on;
+ u32 rscc_disable;
+
struct reset_control *mss_restart;
struct reset_control *pdc_reset;
@@ -201,6 +222,9 @@ struct q6v5 {
bool has_alt_reset;
bool has_mba_logs;
bool has_spare_reg;
+ bool has_qaccept_regs;
+ bool has_ext_cntl_regs;
+ bool has_vq6;
int mpss_perm;
int mba_perm;
const char *hexagon_mdt_image;
@@ -213,6 +237,7 @@ enum {
MSS_MSM8996,
MSS_MSM8998,
MSS_SC7180,
+ MSS_SC7280,
MSS_SDM845,
};
@@ -473,6 +498,12 @@ static int q6v5_reset_assert(struct q6v5 *qproc)
regmap_update_bits(qproc->conn_map, qproc->conn_box,
AXI_GATING_VALID_OVERRIDE, 0);
ret = reset_control_deassert(qproc->mss_restart);
+ } else if (qproc->has_ext_cntl_regs) {
+ regmap_write(qproc->conn_map, qproc->rscc_disable, 0);
+ reset_control_assert(qproc->pdc_reset);
+ reset_control_assert(qproc->mss_restart);
+ reset_control_deassert(qproc->pdc_reset);
+ ret = reset_control_deassert(qproc->mss_restart);
} else {
ret = reset_control_assert(qproc->mss_restart);
}
@@ -490,7 +521,7 @@ static int q6v5_reset_deassert(struct q6v5 *qproc)
ret = reset_control_reset(qproc->mss_restart);
writel(0, qproc->rmb_base + RMB_MBA_ALT_RESET);
reset_control_deassert(qproc->pdc_reset);
- } else if (qproc->has_spare_reg) {
+ } else if (qproc->has_spare_reg || qproc->has_ext_cntl_regs) {
ret = reset_control_reset(qproc->mss_restart);
} else {
ret = reset_control_deassert(qproc->mss_restart);
@@ -604,7 +635,7 @@ static int q6v5proc_reset(struct q6v5 *qproc)
}
goto pbl_wait;
- } else if (qproc->version == MSS_SC7180) {
+ } else if (qproc->version == MSS_SC7180 || qproc->version == MSS_SC7280) {
val = readl(qproc->reg_base + QDSP6SS_SLEEP);
val |= Q6SS_CBCR_CLKEN;
writel(val, qproc->reg_base + QDSP6SS_SLEEP);
@@ -787,6 +818,89 @@ static int q6v5proc_reset(struct q6v5 *qproc)
return ret;
}
+static int q6v5proc_enable_qchannel(struct q6v5 *qproc, struct regmap *map, u32 offset)
+{
+ unsigned int val;
+ int ret;
+
+ if (!qproc->has_qaccept_regs)
+ return 0;
+
+ if (qproc->has_ext_cntl_regs) {
+ regmap_write(qproc->conn_map, qproc->rscc_disable, 0);
+ regmap_write(qproc->conn_map, qproc->force_clk_on, 1);
+
+ ret = regmap_read_poll_timeout(qproc->halt_map, qproc->axim1_clk_off, val,
+ !val, 1, Q6SS_CBCR_TIMEOUT_US);
+ if (ret) {
+ dev_err(qproc->dev, "failed to enable axim1 clock\n");
+ return -ETIMEDOUT;
+ }
+ }
+
+ regmap_write(map, offset + QACCEPT_REQ_REG, 1);
+
+ /* Wait for accept */
+ ret = regmap_read_poll_timeout(map, offset + QACCEPT_ACCEPT_REG, val, val, 5,
+ QACCEPT_TIMEOUT_US);
+ if (ret) {
+ dev_err(qproc->dev, "qchannel enable failed\n");
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+static void q6v5proc_disable_qchannel(struct q6v5 *qproc, struct regmap *map, u32 offset)
+{
+ int ret;
+ unsigned int val, retry;
+ unsigned int nretry = 10;
+ bool takedown_complete = false;
+
+ if (!qproc->has_qaccept_regs)
+ return;
+
+ while (!takedown_complete && nretry) {
+ nretry--;
+
+ /* Wait for active transactions to complete */
+ regmap_read_poll_timeout(map, offset + QACCEPT_ACTIVE_REG, val, !val, 5,
+ QACCEPT_TIMEOUT_US);
+
+ /* Request Q-channel transaction takedown */
+ regmap_write(map, offset + QACCEPT_REQ_REG, 0);
+
+ /*
+ * If the request is denied, reset the Q-channel takedown request,
+ * wait for active transactions to complete and retry takedown.
+ */
+ retry = 10;
+ while (retry) {
+ usleep_range(5, 10);
+ retry--;
+ ret = regmap_read(map, offset + QACCEPT_DENY_REG, &val);
+ if (!ret && val) {
+ regmap_write(map, offset + QACCEPT_REQ_REG, 1);
+ break;
+ }
+
+ ret = regmap_read(map, offset + QACCEPT_ACCEPT_REG, &val);
+ if (!ret && !val) {
+ takedown_complete = true;
+ break;
+ }
+ }
+
+ if (!retry)
+ break;
+ }
+
+ /* Rely on mss_restart to clear out pending transactions on takedown failure */
+ if (!takedown_complete)
+ dev_err(qproc->dev, "qchannel takedown failed\n");
+}
+
static void q6v5proc_halt_axi_port(struct q6v5 *qproc,
struct regmap *halt_map,
u32 offset)
@@ -950,6 +1064,12 @@ static int q6v5_mba_load(struct q6v5 *qproc)
goto assert_reset;
}
+ ret = q6v5proc_enable_qchannel(qproc, qproc->halt_map, qproc->qaccept_axi);
+ if (ret) {
+ dev_err(qproc->dev, "failed to enable axi bridge\n");
+ goto disable_active_clks;
+ }
+
/*
* Some versions of the MBA firmware will upon boot wipe the MPSS region as well, so provide
* the Q6 access to this region.
@@ -996,8 +1116,13 @@ static int q6v5_mba_load(struct q6v5 *qproc)
halt_axi_ports:
q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
+ if (qproc->has_vq6)
+ q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_vq6);
q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
+ q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_mdm);
+ q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_cx);
+ q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_axi);
mba_load_err = true;
reclaim_mba:
xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true,
@@ -1047,6 +1172,8 @@ static void q6v5_mba_reclaim(struct q6v5 *qproc)
qproc->dp_size = 0;
q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
+ if (qproc->has_vq6)
+ q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_vq6);
q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
if (qproc->version == MSS_MSM8996) {
@@ -1059,6 +1186,24 @@ static void q6v5_mba_reclaim(struct q6v5 *qproc)
writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
}
+ if (qproc->has_ext_cntl_regs) {
+ regmap_write(qproc->conn_map, qproc->rscc_disable, 1);
+
+ ret = regmap_read_poll_timeout(qproc->halt_map, qproc->axim1_clk_off, val,
+ !val, 1, Q6SS_CBCR_TIMEOUT_US);
+ if (ret)
+ dev_err(qproc->dev, "failed to enable axim1 clock\n");
+
+ ret = regmap_read_poll_timeout(qproc->halt_map, qproc->crypto_clk_off, val,
+ !val, 1, Q6SS_CBCR_TIMEOUT_US);
+ if (ret)
+ dev_err(qproc->dev, "failed to enable crypto clock\n");
+ }
+
+ q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_mdm);
+ q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_cx);
+ q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_axi);
+
q6v5_reset_assert(qproc);
q6v5_clk_disable(qproc->dev, qproc->reset_clks,
@@ -1471,6 +1616,7 @@ static int q6v5_init_mem(struct q6v5 *qproc, struct platform_device *pdev)
{
struct of_phandle_args args;
struct resource *res;
+ int halt_cell_cnt = 3;
int ret;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qdsp6");
@@ -1483,8 +1629,11 @@ static int q6v5_init_mem(struct q6v5 *qproc, struct platform_device *pdev)
if (IS_ERR(qproc->rmb_base))
return PTR_ERR(qproc->rmb_base);
+ if (qproc->has_vq6)
+ halt_cell_cnt++;
+
ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
- "qcom,halt-regs", 3, 0, &args);
+ "qcom,halt-regs", halt_cell_cnt, 0, &args);
if (ret < 0) {
dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n");
return -EINVAL;
@@ -1499,6 +1648,52 @@ static int q6v5_init_mem(struct q6v5 *qproc, struct platform_device *pdev)
qproc->halt_modem = args.args[1];
qproc->halt_nc = args.args[2];
+ if (qproc->has_vq6)
+ qproc->halt_vq6 = args.args[3];
+
+ if (qproc->has_qaccept_regs) {
+ ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
+ "qcom,qaccept-regs",
+ 3, 0, &args);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "failed to parse qaccept-regs\n");
+ return -EINVAL;
+ }
+
+ qproc->qaccept_mdm = args.args[0];
+ qproc->qaccept_cx = args.args[1];
+ qproc->qaccept_axi = args.args[2];
+ }
+
+ if (qproc->has_ext_cntl_regs) {
+ ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
+ "qcom,ext-regs",
+ 2, 0, &args);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "failed to parse ext-regs index 0\n");
+ return -EINVAL;
+ }
+
+ qproc->conn_map = syscon_node_to_regmap(args.np);
+ of_node_put(args.np);
+ if (IS_ERR(qproc->conn_map))
+ return PTR_ERR(qproc->conn_map);
+
+ qproc->force_clk_on = args.args[0];
+ qproc->rscc_disable = args.args[1];
+
+ ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
+ "qcom,ext-regs",
+ 2, 1, &args);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "failed to parse ext-regs index 1\n");
+ return -EINVAL;
+ }
+
+ qproc->axim1_clk_off = args.args[0];
+ qproc->crypto_clk_off = args.args[1];
+ }
+
if (qproc->has_spare_reg) {
ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
"qcom,spare-regs",
@@ -1590,7 +1785,7 @@ static int q6v5_init_reset(struct q6v5 *qproc)
return PTR_ERR(qproc->mss_restart);
}
- if (qproc->has_alt_reset || qproc->has_spare_reg) {
+ if (qproc->has_alt_reset || qproc->has_spare_reg || qproc->has_ext_cntl_regs) {
qproc->pdc_reset = devm_reset_control_get_exclusive(qproc->dev,
"pdc_reset");
if (IS_ERR(qproc->pdc_reset)) {
@@ -1697,6 +1892,9 @@ static int q6v5_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, qproc);
+ qproc->has_qaccept_regs = desc->has_qaccept_regs;
+ qproc->has_ext_cntl_regs = desc->has_ext_cntl_regs;
+ qproc->has_vq6 = desc->has_vq6;
qproc->has_spare_reg = desc->has_spare_reg;
ret = q6v5_init_mem(qproc, pdev);
if (ret)
@@ -1857,9 +2055,39 @@ static const struct rproc_hexagon_res sc7180_mss = {
.has_alt_reset = false,
.has_mba_logs = true,
.has_spare_reg = true,
+ .has_qaccept_regs = false,
+ .has_ext_cntl_regs = false,
+ .has_vq6 = false,
.version = MSS_SC7180,
};
+static const struct rproc_hexagon_res sc7280_mss = {
+ .hexagon_mba_image = "mba.mbn",
+ .proxy_clk_names = (char*[]){
+ "xo",
+ NULL
+ },
+ .active_clk_names = (char*[]){
+ "iface",
+ "offline",
+ "snoc_axi",
+ NULL
+ },
+ .proxy_pd_names = (char*[]){
+ "cx",
+ "mss",
+ NULL
+ },
+ .need_mem_protection = true,
+ .has_alt_reset = false,
+ .has_mba_logs = true,
+ .has_spare_reg = false,
+ .has_qaccept_regs = true,
+ .has_ext_cntl_regs = true,
+ .has_vq6 = true,
+ .version = MSS_SC7280,
+};
+
static const struct rproc_hexagon_res sdm845_mss = {
.hexagon_mba_image = "mba.mbn",
.proxy_clk_names = (char*[]){
@@ -1889,6 +2117,9 @@ static const struct rproc_hexagon_res sdm845_mss = {
.has_alt_reset = true,
.has_mba_logs = false,
.has_spare_reg = false,
+ .has_qaccept_regs = false,
+ .has_ext_cntl_regs = false,
+ .has_vq6 = false,
.version = MSS_SDM845,
};
@@ -1917,6 +2148,9 @@ static const struct rproc_hexagon_res msm8998_mss = {
.has_alt_reset = false,
.has_mba_logs = false,
.has_spare_reg = false,
+ .has_qaccept_regs = false,
+ .has_ext_cntl_regs = false,
+ .has_vq6 = false,
.version = MSS_MSM8998,
};
@@ -1948,6 +2182,9 @@ static const struct rproc_hexagon_res msm8996_mss = {
.has_alt_reset = false,
.has_mba_logs = false,
.has_spare_reg = false,
+ .has_qaccept_regs = false,
+ .has_ext_cntl_regs = false,
+ .has_vq6 = false,
.version = MSS_MSM8996,
};
@@ -1990,6 +2227,9 @@ static const struct rproc_hexagon_res msm8916_mss = {
.has_alt_reset = false,
.has_mba_logs = false,
.has_spare_reg = false,
+ .has_qaccept_regs = false,
+ .has_ext_cntl_regs = false,
+ .has_vq6 = false,
.version = MSS_MSM8916,
};
@@ -2040,6 +2280,9 @@ static const struct rproc_hexagon_res msm8974_mss = {
.has_alt_reset = false,
.has_mba_logs = false,
.has_spare_reg = false,
+ .has_qaccept_regs = false,
+ .has_ext_cntl_regs = false,
+ .has_vq6 = false,
.version = MSS_MSM8974,
};
@@ -2050,6 +2293,7 @@ static const struct of_device_id q6v5_of_match[] = {
{ .compatible = "qcom,msm8996-mss-pil", .data = &msm8996_mss},
{ .compatible = "qcom,msm8998-mss-pil", .data = &msm8998_mss},
{ .compatible = "qcom,sc7180-mss-pil", .data = &sc7180_mss},
+ { .compatible = "qcom,sc7280-mss-pil", .data = &sc7280_mss},
{ .compatible = "qcom,sdm845-mss-pil", .data = &sdm845_mss},
{ },
};
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 11%]
* [PATCH v4 07/10] arm64: dts: qcom: sc7280: Add/Delete/Update reserved memory nodes
2021-09-06 8:54 18% [PATCH v4 00/10] Add Modem support on SC7280 SoCs Sibi Sankar
` (5 preceding siblings ...)
2021-09-06 8:54 18% ` [PATCH v4 06/10] arm64: dts: qcom: sc7280: Update reserved memory map Sibi Sankar
@ 2021-09-06 8:54 18% ` Sibi Sankar
2021-09-06 8:54 18% ` [PATCH v4 08/10] arm64: dts: qcom: sc7280: Add nodes to boot modem Sibi Sankar
` (2 subsequent siblings)
9 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-09-06 8:54 UTC (permalink / raw)
To: bjorn.andersson, robh+dt, will, saiprakash.ranjan, swboyd, mka
Cc: ohad, agross, mathieu.poirier, robin.murphy, joro, p.zabel,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
linux-arm-kernel, evgreen, dianders, Sibi Sankar
Add, delete and update platform specific reserved memory nodes.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 52 ++++++++++++++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
index 371a2a9dcf7a..103d89c1e1c7 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
@@ -12,6 +12,58 @@
#include "pm8350c.dtsi"
#include "pmk8350.dtsi"
+/*
+ * Reserved memory changes
+ *
+ * Delete all unused memory nodes and define the peripheral memory regions
+ * required by the board dts.
+ *
+ */
+
+/delete-node/ &hyp_mem;
+/delete-node/ &xbl_mem;
+/delete-node/ &reserved_xbl_uefi_log;
+/delete-node/ &sec_apps_mem;
+
+/* Increase the size from 2.5MB to 8MB */
+&rmtfs_mem {
+ reg = <0x0 0x9c900000 0x0 0x800000>;
+};
+
+/ {
+ reserved-memory {
+ adsp_mem: memory@86700000 {
+ reg = <0x0 0x86700000 0x0 0x2800000>;
+ no-map;
+ };
+
+ camera_mem: memory@8ad00000 {
+ reg = <0x0 0x8ad00000 0x0 0x500000>;
+ no-map;
+ };
+
+ venus_mem: memory@8b200000 {
+ reg = <0x0 0x8b200000 0x0 0x500000>;
+ no-map;
+ };
+
+ mpss_mem: memory@8b800000 {
+ reg = <0x0 0x8b800000 0x0 0xf600000>;
+ no-map;
+ };
+
+ wpss_mem: memory@9ae00000 {
+ reg = <0x0 0x9ae00000 0x0 0x1900000>;
+ no-map;
+ };
+
+ mba_mem: memory@9c700000 {
+ reg = <0x0 0x9c700000 0x0 0x200000>;
+ no-map;
+ };
+ };
+};
+
&apps_rsc {
pm7325-regulators {
compatible = "qcom,pm7325-rpmh-regulators";
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 18%]
* [PATCH v4 03/10] dt-bindings: remoteproc: qcom: Update Q6V5 Modem PIL binding
2021-09-06 8:54 18% [PATCH v4 00/10] Add Modem support on SC7280 SoCs Sibi Sankar
2021-09-06 8:54 17% ` [PATCH v4 01/10] dt-bindings: remoteproc: qcom: pas: Add SC7280 MPSS support Sibi Sankar
2021-09-06 8:54 19% ` [PATCH v4 02/10] remoteproc: qcom: pas: Add SC7280 Modem support Sibi Sankar
@ 2021-09-06 8:54 14% ` Sibi Sankar
2021-09-06 8:54 19% ` [PATCH v4 04/10] iommu/arm-smmu-qcom: Request direct mapping for modem device Sibi Sankar
` (6 subsequent siblings)
9 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-09-06 8:54 UTC (permalink / raw)
To: bjorn.andersson, robh+dt, will, saiprakash.ranjan, swboyd, mka
Cc: ohad, agross, mathieu.poirier, robin.murphy, joro, p.zabel,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
linux-arm-kernel, evgreen, dianders, Sibi Sankar
Add a new modem compatible string for QTI SC7280 SoCs and introduce the
"qcom,ext-regs" and "qcom,qaccept-regs" properties needed by the modem
sub-system running on SC7280 SoCs.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
.../devicetree/bindings/remoteproc/qcom,q6v5.txt | 32 ++++++++++++++++++++--
1 file changed, 30 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
index 494257010629..bc1394f5d677 100644
--- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
@@ -15,6 +15,7 @@ on the Qualcomm Hexagon core.
"qcom,msm8996-mss-pil"
"qcom,msm8998-mss-pil"
"qcom,sc7180-mss-pil"
+ "qcom,sc7280-mss-pil"
"qcom,sdm845-mss-pil"
- reg:
@@ -47,6 +48,7 @@ on the Qualcomm Hexagon core.
qcom,msm8996-mss-pil:
qcom,msm8998-mss-pil:
qcom,sc7180-mss-pil:
+ qcom,sc7280-mss-pil:
qcom,sdm845-mss-pil:
must be "wdog", "fatal", "ready", "handover", "stop-ack",
"shutdown-ack"
@@ -87,6 +89,8 @@ on the Qualcomm Hexagon core.
qcom,sc7180-mss-pil:
must be "iface", "bus", "xo", "snoc_axi", "mnoc_axi",
"nav"
+ qcom,sc7280-mss-pil:
+ must be "iface", "xo", "snoc_axi", "offline"
qcom,sdm845-mss-pil:
must be "iface", "bus", "mem", "xo", "gpll0_mss",
"snoc_axi", "mnoc_axi", "prng"
@@ -98,7 +102,7 @@ on the Qualcomm Hexagon core.
reference to the list of 3 reset-controllers for the
wcss sub-system
reference to the list of 2 reset-controllers for the modem
- sub-system on SC7180, SDM845 SoCs
+ sub-system on SC7180, SC7280, SDM845 SoCs
- reset-names:
Usage: required
@@ -107,7 +111,7 @@ on the Qualcomm Hexagon core.
must be "wcss_aon_reset", "wcss_reset", "wcss_q6_reset"
for the wcss sub-system
must be "mss_restart", "pdc_reset" for the modem
- sub-system on SC7180, SDM845 SoCs
+ sub-system on SC7180, SC7280, SDM845 SoCs
For devices where the mba and mpss sub-nodes are not specified, mba/mpss region
should be referenced as follows:
@@ -173,6 +177,9 @@ For the compatible string below the following supplies are required:
qcom,msm8998-mss-pil:
must be "cx", "mx"
qcom,sc7180-mss-pil:
+ must be "cx", "mx", "mss"
+ qcom,sc7280-mss-pil:
+ must be "cx", "mss"
qcom,sdm845-mss-pil:
must be "cx", "mx", "mss"
@@ -198,6 +205,9 @@ For the compatible string below the following supplies are required:
Definition: a phandle reference to a syscon representing TCSR followed
by the three offsets within syscon for q6, modem and nc
halt registers.
+ a phandle reference to a syscon representing TCSR followed
+ by the four offsets within syscon for q6, modem, nc and vq6
+ halt registers on SC7280 SoCs.
For the compatible strings below the following phandle references are required:
"qcom,sc7180-mss-pil"
@@ -208,6 +218,24 @@ For the compatible strings below the following phandle references are required:
by the offset within syscon for conn_box_spare0 register
used by the modem sub-system running on SC7180 SoC.
+For the compatible strings below the following phandle references are required:
+ "qcom,sc7280-mss-pil"
+- qcom,ext-regs:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: two phandle references to syscons representing TCSR_REG and
+ TCSR register space followed by the two offsets within the syscon
+ to force_clk_en/rscc_disable and axim1_clk_off/crypto_clk_off
+ registers respectively.
+
+- qcom,qaccept-regs:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: a phandle reference to a syscon representing TCSR followed
+ by the three offsets within syscon for mdm, cx and axi
+ qaccept registers used by the modem sub-system running on
+ SC7280 SoC.
+
The Hexagon node must contain iommus property as described in ../iommu/iommu.txt
on platforms which do not have TrustZone.
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 14%]
* [PATCH v4 02/10] remoteproc: qcom: pas: Add SC7280 Modem support
2021-09-06 8:54 18% [PATCH v4 00/10] Add Modem support on SC7280 SoCs Sibi Sankar
2021-09-06 8:54 17% ` [PATCH v4 01/10] dt-bindings: remoteproc: qcom: pas: Add SC7280 MPSS support Sibi Sankar
@ 2021-09-06 8:54 19% ` Sibi Sankar
2021-09-06 8:54 14% ` [PATCH v4 03/10] dt-bindings: remoteproc: qcom: Update Q6V5 Modem PIL binding Sibi Sankar
` (7 subsequent siblings)
9 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-09-06 8:54 UTC (permalink / raw)
To: bjorn.andersson, robh+dt, will, saiprakash.ranjan, swboyd, mka
Cc: ohad, agross, mathieu.poirier, robin.murphy, joro, p.zabel,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
linux-arm-kernel, evgreen, dianders, Sibi Sankar
Add support for booting the Modem DSP found on QTI SC7280 SoCs.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
drivers/remoteproc/qcom_q6v5_pas.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q6v5_pas.c
index 7036e6e9eff4..89c889c041e5 100644
--- a/drivers/remoteproc/qcom_q6v5_pas.c
+++ b/drivers/remoteproc/qcom_q6v5_pas.c
@@ -783,6 +783,7 @@ static const struct of_device_id adsp_of_match[] = {
{ .compatible = "qcom,qcs404-cdsp-pas", .data = &cdsp_resource_init },
{ .compatible = "qcom,qcs404-wcss-pas", .data = &wcss_resource_init },
{ .compatible = "qcom,sc7180-mpss-pas", .data = &mpss_resource_init},
+ { .compatible = "qcom,sc7280-mpss-pas", .data = &mpss_resource_init},
{ .compatible = "qcom,sc8180x-adsp-pas", .data = &sm8150_adsp_resource},
{ .compatible = "qcom,sc8180x-cdsp-pas", .data = &sm8150_cdsp_resource},
{ .compatible = "qcom,sc8180x-mpss-pas", .data = &sc8180x_mpss_resource},
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 19%]
* [PATCH v4 00/10] Add Modem support on SC7280 SoCs
@ 2021-09-06 8:54 18% Sibi Sankar
2021-09-06 8:54 17% ` [PATCH v4 01/10] dt-bindings: remoteproc: qcom: pas: Add SC7280 MPSS support Sibi Sankar
` (9 more replies)
0 siblings, 10 replies; 200+ results
From: Sibi Sankar @ 2021-09-06 8:54 UTC (permalink / raw)
To: bjorn.andersson, robh+dt, will, saiprakash.ranjan, swboyd, mka
Cc: ohad, agross, mathieu.poirier, robin.murphy, joro, p.zabel,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
linux-arm-kernel, evgreen, dianders, Sibi Sankar
This patch series adds support for booting the Modem Q6 DSP found on
Qualcomm's SC7280 SoCs.
Depends on:
qmp_send: https://patchwork.kernel.org/project/linux-arm-msm/cover/1630420228-31075-1-git-send-email-deesin@codeaurora.org/
rproc qmp: https://patchwork.kernel.org/project/linux-arm-msm/cover/1630916637-4278-1-git-send-email-sibis@codeaurora.org/
V4:
* Rebased to linux-next and picked up Rbs.
* Fixed typo (patch 10).
V3:
* Keep the memory map version in commit message (patch 6). [Bjorn]
* Rename tcsr node and add qualifying compatibles to tcsr and imem nodes
(patch 8). [Bjorn]
* Place remoteproc_mpss node in alphabetical order above pinctrl
section (patch 10). [Stephen]
V2:
* Misc. typos (patch 3). [Matthias]
* Document the q-channel takedown procedure (patch 5). [Matthias]
* Split reserved memory updates between SoC and platform (patch 6). [Matthias]
Sibi Sankar (10):
dt-bindings: remoteproc: qcom: pas: Add SC7280 MPSS support
remoteproc: qcom: pas: Add SC7280 Modem support
dt-bindings: remoteproc: qcom: Update Q6V5 Modem PIL binding
iommu/arm-smmu-qcom: Request direct mapping for modem device
remoteproc: mss: q6v5-mss: Add modem support on SC7280
arm64: dts: qcom: sc7280: Update reserved memory map
arm64: dts: qcom: sc7280: Add/Delete/Update reserved memory nodes
arm64: dts: qcom: sc7280: Add nodes to boot modem
arm64: dts: qcom: sc7280: Add Q6V5 MSS node
arm64: dts: qcom: sc7280: Update Q6V5 MSS node
.../devicetree/bindings/remoteproc/qcom,adsp.yaml | 6 +
.../devicetree/bindings/remoteproc/qcom,q6v5.txt | 32 ++-
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 59 +++++
arch/arm64/boot/dts/qcom/sc7280.dtsi | 106 +++++++++
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
drivers/remoteproc/qcom_q6v5_mss.c | 252 ++++++++++++++++++++-
drivers/remoteproc/qcom_q6v5_pas.c | 1 +
7 files changed, 451 insertions(+), 6 deletions(-)
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [relevance 18%]
* [PATCH v4 01/10] dt-bindings: remoteproc: qcom: pas: Add SC7280 MPSS support
2021-09-06 8:54 18% [PATCH v4 00/10] Add Modem support on SC7280 SoCs Sibi Sankar
@ 2021-09-06 8:54 17% ` Sibi Sankar
2021-09-06 8:54 19% ` [PATCH v4 02/10] remoteproc: qcom: pas: Add SC7280 Modem support Sibi Sankar
` (8 subsequent siblings)
9 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-09-06 8:54 UTC (permalink / raw)
To: bjorn.andersson, robh+dt, will, saiprakash.ranjan, swboyd, mka
Cc: ohad, agross, mathieu.poirier, robin.murphy, joro, p.zabel,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
linux-arm-kernel, evgreen, dianders, Sibi Sankar
Add MPSS PAS support for SC7280 SoCs.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml
index 0d2b5bd4907a..68ee7febddd9 100644
--- a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml
@@ -25,6 +25,7 @@ properties:
- qcom,qcs404-cdsp-pas
- qcom,qcs404-wcss-pas
- qcom,sc7180-mpss-pas
+ - qcom,sc7280-mpss-pas
- qcom,sc8180x-adsp-pas
- qcom,sc8180x-cdsp-pas
- qcom,sc8180x-mpss-pas
@@ -151,6 +152,7 @@ allOf:
- qcom,msm8998-adsp-pas
- qcom,qcs404-adsp-pas
- qcom,qcs404-wcss-pas
+ - qcom,sc7280-mpss-pas
- qcom,sc8180x-adsp-pas
- qcom,sc8180x-cdsp-pas
- qcom,sc8180x-mpss-pas
@@ -296,6 +298,7 @@ allOf:
contains:
enum:
- qcom,sc7180-mpss-pas
+ - qcom,sc7280-mpss-pas
- qcom,sc8180x-mpss-pas
- qcom,sdx55-mpss-pas
- qcom,sm8150-mpss-pas
@@ -400,6 +403,7 @@ allOf:
compatible:
contains:
enum:
+ - qcom,sc7280-mpss-pas
- qcom,sdx55-mpss-pas
- qcom,sm8150-mpss-pas
- qcom,sm8350-mpss-pas
@@ -475,6 +479,7 @@ allOf:
contains:
enum:
- qcom,sc7180-mpss-pas
+ - qcom,sc7280-mpss-pas
then:
properties:
resets:
@@ -492,6 +497,7 @@ allOf:
contains:
enum:
- qcom,sc7180-mpss-pas
+ - qcom,sc7280-mpss-pas
- qcom,sc8180x-adsp-pas
- qcom,sc8180x-cdsp-pas
- qcom,sc8180x-mpss-pas
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 17%]
* [PATCH v6 11/13] soc: qcom: aoss: Drop power domain support
2021-09-06 8:23 9% [PATCH v6 00/13] Use qmp_send to update co-processor load state Sibi Sankar
` (9 preceding siblings ...)
2021-09-06 8:23 16% ` [PATCH v6 10/13] arm64: dts: qcom: sm8350: " Sibi Sankar
@ 2021-09-06 8:23 15% ` Sibi Sankar
2021-09-06 8:23 19% ` [PATCH v6 12/13] dt-bindings: msm/dp: Remove aoss-qmp header Sibi Sankar
2021-09-06 8:23 19% ` [PATCH v6 13/13] dt-bindings: soc: qcom: aoss: Delete unused power-domain definitions Sibi Sankar
12 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-09-06 8:23 UTC (permalink / raw)
To: mka, swboyd, bjorn.andersson, robh+dt
Cc: ulf.hansson, rjw, agross, ohad, mathieu.poirier, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel, dianders, rishabhb,
sidgup, Sibi Sankar
Strip out the load state power-domain support from the driver since the
low power mode signalling for the co-processors is now accessible through
the direct qmp message send interface.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
drivers/soc/qcom/qcom_aoss.c | 107 -------------------------------------------
1 file changed, 107 deletions(-)
diff --git a/drivers/soc/qcom/qcom_aoss.c b/drivers/soc/qcom/qcom_aoss.c
index 9fb74aa7c9ab..d650012ca19c 100644
--- a/drivers/soc/qcom/qcom_aoss.c
+++ b/drivers/soc/qcom/qcom_aoss.c
@@ -2,7 +2,6 @@
/*
* Copyright (c) 2019, Linaro Ltd
*/
-#include <dt-bindings/power/qcom-aoss-qmp.h>
#include <linux/clk-provider.h>
#include <linux/debugfs.h>
#include <linux/interrupt.h>
@@ -11,7 +10,6 @@
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
-#include <linux/pm_domain.h>
#include <linux/thermal.h>
#include <linux/slab.h>
#include <linux/soc/qcom/qcom_aoss.h>
@@ -67,7 +65,6 @@ struct qmp_cooling_device {
* @event: wait_queue for synchronization with the IRQ
* @tx_lock: provides synchronization between multiple callers of qmp_send()
* @qdss_clk: QDSS clock hw struct
- * @pd_data: genpd data
* @cooling_devs: thermal cooling devices
*/
struct qmp {
@@ -85,18 +82,10 @@ struct qmp {
struct mutex tx_lock;
struct clk_hw qdss_clk;
- struct genpd_onecell_data pd_data;
struct qmp_cooling_device *cooling_devs;
struct dentry *debugfs_file;
};
-struct qmp_pd {
- struct qmp *qmp;
- struct generic_pm_domain pd;
-};
-
-#define to_qmp_pd_resource(res) container_of(res, struct qmp_pd, pd)
-
static void qmp_kick(struct qmp *qmp)
{
mbox_send_message(qmp->mbox_chan, NULL);
@@ -322,95 +311,6 @@ static void qmp_qdss_clk_remove(struct qmp *qmp)
clk_hw_unregister(&qmp->qdss_clk);
}
-static int qmp_pd_power_toggle(struct qmp_pd *res, bool enable)
-{
- char buf[QMP_MSG_LEN] = {};
-
- snprintf(buf, sizeof(buf),
- "{class: image, res: load_state, name: %s, val: %s}",
- res->pd.name, enable ? "on" : "off");
- return qmp_send(res->qmp, buf, sizeof(buf));
-}
-
-static int qmp_pd_power_on(struct generic_pm_domain *domain)
-{
- return qmp_pd_power_toggle(to_qmp_pd_resource(domain), true);
-}
-
-static int qmp_pd_power_off(struct generic_pm_domain *domain)
-{
- return qmp_pd_power_toggle(to_qmp_pd_resource(domain), false);
-}
-
-static const char * const sdm845_resources[] = {
- [AOSS_QMP_LS_CDSP] = "cdsp",
- [AOSS_QMP_LS_LPASS] = "adsp",
- [AOSS_QMP_LS_MODEM] = "modem",
- [AOSS_QMP_LS_SLPI] = "slpi",
- [AOSS_QMP_LS_SPSS] = "spss",
- [AOSS_QMP_LS_VENUS] = "venus",
-};
-
-static int qmp_pd_add(struct qmp *qmp)
-{
- struct genpd_onecell_data *data = &qmp->pd_data;
- struct device *dev = qmp->dev;
- struct qmp_pd *res;
- size_t num = ARRAY_SIZE(sdm845_resources);
- int ret;
- int i;
-
- res = devm_kcalloc(dev, num, sizeof(*res), GFP_KERNEL);
- if (!res)
- return -ENOMEM;
-
- data->domains = devm_kcalloc(dev, num, sizeof(*data->domains),
- GFP_KERNEL);
- if (!data->domains)
- return -ENOMEM;
-
- for (i = 0; i < num; i++) {
- res[i].qmp = qmp;
- res[i].pd.name = sdm845_resources[i];
- res[i].pd.power_on = qmp_pd_power_on;
- res[i].pd.power_off = qmp_pd_power_off;
-
- ret = pm_genpd_init(&res[i].pd, NULL, true);
- if (ret < 0) {
- dev_err(dev, "failed to init genpd\n");
- goto unroll_genpds;
- }
-
- data->domains[i] = &res[i].pd;
- }
-
- data->num_domains = i;
-
- ret = of_genpd_add_provider_onecell(dev->of_node, data);
- if (ret < 0)
- goto unroll_genpds;
-
- return 0;
-
-unroll_genpds:
- for (i--; i >= 0; i--)
- pm_genpd_remove(data->domains[i]);
-
- return ret;
-}
-
-static void qmp_pd_remove(struct qmp *qmp)
-{
- struct genpd_onecell_data *data = &qmp->pd_data;
- struct device *dev = qmp->dev;
- int i;
-
- of_genpd_del_provider(dev->of_node);
-
- for (i = 0; i < data->num_domains; i++)
- pm_genpd_remove(data->domains[i]);
-}
-
static int qmp_cdev_get_max_state(struct thermal_cooling_device *cdev,
unsigned long *state)
{
@@ -641,10 +541,6 @@ static int qmp_probe(struct platform_device *pdev)
if (ret)
goto err_close_qmp;
- ret = qmp_pd_add(qmp);
- if (ret)
- goto err_remove_qdss_clk;
-
ret = qmp_cooling_devices_register(qmp);
if (ret)
dev_err(&pdev->dev, "failed to register aoss cooling devices\n");
@@ -656,8 +552,6 @@ static int qmp_probe(struct platform_device *pdev)
return 0;
-err_remove_qdss_clk:
- qmp_qdss_clk_remove(qmp);
err_close_qmp:
qmp_close(qmp);
err_free_mbox:
@@ -673,7 +567,6 @@ static int qmp_remove(struct platform_device *pdev)
debugfs_remove(qmp->debugfs_file);
qmp_qdss_clk_remove(qmp);
- qmp_pd_remove(qmp);
qmp_cooling_devices_remove(qmp);
qmp_close(qmp);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 15%]
* [PATCH v6 10/13] arm64: dts: qcom: sm8350: Use QMP property to control load state
2021-09-06 8:23 9% [PATCH v6 00/13] Use qmp_send to update co-processor load state Sibi Sankar
` (8 preceding siblings ...)
2021-09-06 8:23 17% ` [PATCH v6 09/13] arm64: dts: qcom: sm8250: " Sibi Sankar
@ 2021-09-06 8:23 16% ` Sibi Sankar
2021-09-06 8:23 15% ` [PATCH v6 11/13] soc: qcom: aoss: Drop power domain support Sibi Sankar
` (2 subsequent siblings)
12 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-09-06 8:23 UTC (permalink / raw)
To: mka, swboyd, bjorn.andersson, robh+dt
Cc: ulf.hansson, rjw, agross, ohad, mathieu.poirier, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel, dianders, rishabhb,
sidgup, Sibi Sankar
Use the Qualcomm Mailbox Protocol (QMP) property to control the load
state resources on SM8350 SoCs and drop deprecated power-domains exposed
by AOSS QMP node.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 30 ++++++++++++++++--------------
1 file changed, 16 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index e91cd8a5e535..6c83cd52a279 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -8,7 +8,6 @@
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interconnect/qcom,sm8350.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
-#include <dt-bindings/power/qcom-aoss-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/thermal/thermal.h>
@@ -726,15 +725,16 @@
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
- <&rpmhpd 0>,
+ power-domains = <&rpmhpd 0>,
<&rpmhpd 12>;
- power-domain-names = "load_state", "cx", "mss";
+ power-domain-names = "cx", "mss";
interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
memory-region = <&pil_modem_mem>;
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&smp2p_modem_out 0>;
qcom,smem-state-names = "stop";
@@ -794,7 +794,6 @@
mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
#clock-cells = <0>;
- #power-domain-cells = <1>;
};
spmi_bus: spmi@c440000 {
@@ -1107,13 +1106,14 @@
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
- <&rpmhpd 4>,
+ power-domains = <&rpmhpd 4>,
<&rpmhpd 5>;
- power-domain-names = "load_state", "lcx", "lmx";
+ power-domain-names = "lcx", "lmx";
memory-region = <&pil_slpi_mem>;
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&smp2p_slpi_out 0>;
qcom,smem-state-names = "stop";
@@ -1147,15 +1147,16 @@
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
- <&rpmhpd 0>,
+ power-domains = <&rpmhpd 0>,
<&rpmhpd 10>;
- power-domain-names = "load_state", "cx", "mxc";
+ power-domain-names = "cx", "mxc";
interconnects = <&compute_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>;
memory-region = <&pil_cdsp_mem>;
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&smp2p_cdsp_out 0>;
qcom,smem-state-names = "stop";
@@ -1381,13 +1382,14 @@
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
- <&rpmhpd 4>,
+ power-domains = <&rpmhpd 4>,
<&rpmhpd 5>;
- power-domain-names = "load_state", "lcx", "lmx";
+ power-domain-names = "lcx", "lmx";
memory-region = <&pil_adsp_mem>;
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&smp2p_adsp_out 0>;
qcom,smem-state-names = "stop";
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 16%]
* [PATCH v6 13/13] dt-bindings: soc: qcom: aoss: Delete unused power-domain definitions
2021-09-06 8:23 9% [PATCH v6 00/13] Use qmp_send to update co-processor load state Sibi Sankar
` (11 preceding siblings ...)
2021-09-06 8:23 19% ` [PATCH v6 12/13] dt-bindings: msm/dp: Remove aoss-qmp header Sibi Sankar
@ 2021-09-06 8:23 19% ` Sibi Sankar
12 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-09-06 8:23 UTC (permalink / raw)
To: mka, swboyd, bjorn.andersson, robh+dt
Cc: ulf.hansson, rjw, agross, ohad, mathieu.poirier, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel, dianders, rishabhb,
sidgup, Sibi Sankar
Delete unused power-domain definitions exposed by AOSS QMP.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
---
include/dt-bindings/power/qcom-aoss-qmp.h | 14 --------------
1 file changed, 14 deletions(-)
delete mode 100644 include/dt-bindings/power/qcom-aoss-qmp.h
diff --git a/include/dt-bindings/power/qcom-aoss-qmp.h b/include/dt-bindings/power/qcom-aoss-qmp.h
deleted file mode 100644
index ec336d31dee4..000000000000
--- a/include/dt-bindings/power/qcom-aoss-qmp.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* Copyright (c) 2018, Linaro Ltd. */
-
-#ifndef __DT_BINDINGS_POWER_QCOM_AOSS_QMP_H
-#define __DT_BINDINGS_POWER_QCOM_AOSS_QMP_H
-
-#define AOSS_QMP_LS_CDSP 0
-#define AOSS_QMP_LS_LPASS 1
-#define AOSS_QMP_LS_MODEM 2
-#define AOSS_QMP_LS_SLPI 3
-#define AOSS_QMP_LS_SPSS 4
-#define AOSS_QMP_LS_VENUS 5
-
-#endif
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 19%]
* [PATCH v6 12/13] dt-bindings: msm/dp: Remove aoss-qmp header
2021-09-06 8:23 9% [PATCH v6 00/13] Use qmp_send to update co-processor load state Sibi Sankar
` (10 preceding siblings ...)
2021-09-06 8:23 15% ` [PATCH v6 11/13] soc: qcom: aoss: Drop power domain support Sibi Sankar
@ 2021-09-06 8:23 19% ` Sibi Sankar
2021-09-06 8:23 19% ` [PATCH v6 13/13] dt-bindings: soc: qcom: aoss: Delete unused power-domain definitions Sibi Sankar
12 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-09-06 8:23 UTC (permalink / raw)
To: mka, swboyd, bjorn.andersson, robh+dt
Cc: ulf.hansson, rjw, agross, ohad, mathieu.poirier, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel, dianders, rishabhb,
sidgup, Sibi Sankar
Remove the unused aoss-qmp header from the list of includes.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
Documentation/devicetree/bindings/display/msm/dp-controller.yaml | 1 -
1 file changed, 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
index 64d8d9e5e47a..d89b3c510c27 100644
--- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
@@ -95,7 +95,6 @@ examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,dispcc-sc7180.h>
- #include <dt-bindings/power/qcom-aoss-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
displayport-controller@ae90000 {
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 19%]
* [PATCH v6 08/13] arm64: dts: qcom: sm8150: Use QMP property to control load state
2021-09-06 8:23 9% [PATCH v6 00/13] Use qmp_send to update co-processor load state Sibi Sankar
` (6 preceding siblings ...)
2021-09-06 8:23 18% ` [PATCH v6 07/13] arm64: dts: qcom: sdm845: " Sibi Sankar
@ 2021-09-06 8:23 17% ` Sibi Sankar
2021-09-06 8:23 17% ` [PATCH v6 09/13] arm64: dts: qcom: sm8250: " Sibi Sankar
` (4 subsequent siblings)
12 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-09-06 8:23 UTC (permalink / raw)
To: mka, swboyd, bjorn.andersson, robh+dt
Cc: ulf.hansson, rjw, agross, ohad, mathieu.poirier, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel, dianders, rishabhb,
sidgup, Sibi Sankar
Use the Qualcomm Mailbox Protocol (QMP) property to control the load
state resources on SM8150 SoCs and drop deprecated power-domains exposed
by AOSS QMP node.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 28 ++++++++++++++--------------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index ef0232c2cf45..8a035693b7a3 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -6,7 +6,6 @@
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/power/qcom-aoss-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
@@ -1729,13 +1728,14 @@
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
- <&rpmhpd 3>,
+ power-domains = <&rpmhpd 3>,
<&rpmhpd 2>;
- power-domain-names = "load_state", "lcx", "lmx";
+ power-domain-names = "lcx", "lmx";
memory-region = <&slpi_mem>;
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&slpi_smp2p_out 0>;
qcom,smem-state-names = "stop";
@@ -2319,13 +2319,14 @@
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
- <&rpmhpd 7>,
+ power-domains = <&rpmhpd 7>,
<&rpmhpd 0>;
- power-domain-names = "load_state", "cx", "mss";
+ power-domain-names = "cx", "mss";
memory-region = <&mpss_mem>;
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&modem_smp2p_out 0>;
qcom,smem-state-names = "stop";
@@ -2945,12 +2946,12 @@
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
- <&rpmhpd 7>;
- power-domain-names = "load_state", "cx";
+ power-domains = <&rpmhpd 7>;
memory-region = <&cdsp_mem>;
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&cdsp_smp2p_out 0>;
qcom,smem-state-names = "stop";
@@ -3174,7 +3175,6 @@
mboxes = <&apss_shared 0>;
#clock-cells = <0>;
- #power-domain-cells = <1>;
};
tsens0: thermal-sensor@c263000 {
@@ -3321,12 +3321,12 @@
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
- <&rpmhpd 7>;
- power-domain-names = "load_state", "cx";
+ power-domains = <&rpmhpd 7>;
memory-region = <&adsp_mem>;
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&adsp_smp2p_out 0>;
qcom,smem-state-names = "stop";
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 17%]
* [PATCH v6 07/13] arm64: dts: qcom: sdm845: Use QMP property to control load state
2021-09-06 8:23 9% [PATCH v6 00/13] Use qmp_send to update co-processor load state Sibi Sankar
` (5 preceding siblings ...)
2021-09-06 8:23 18% ` [PATCH v6 06/13] arm64: dts: qcom: sc7280: " Sibi Sankar
@ 2021-09-06 8:23 18% ` Sibi Sankar
2021-09-06 8:23 17% ` [PATCH v6 08/13] arm64: dts: qcom: sm8150: " Sibi Sankar
` (5 subsequent siblings)
12 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-09-06 8:23 UTC (permalink / raw)
To: mka, swboyd, bjorn.andersson, robh+dt
Cc: ulf.hansson, rjw, agross, ohad, mathieu.poirier, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel, dianders, rishabhb,
sidgup, Sibi Sankar
Use the Qualcomm Mailbox Protocol (QMP) property to control the load
state resources on SDM845 SoCs and drop deprecated power-domains exposed
by AOSS QMP node.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 425f169b5d1e..e13afa8f91c0 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -2979,6 +2979,8 @@
clock-names = "iface", "bus", "mem", "gpll0_mss",
"snoc_axi", "mnoc_axi", "prng", "xo";
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&modem_smp2p_out 0>;
qcom,smem-state-names = "stop";
@@ -2988,11 +2990,10 @@
qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
- power-domains = <&aoss_qmp 2>,
- <&rpmhpd SDM845_CX>,
+ power-domains = <&rpmhpd SDM845_CX>,
<&rpmhpd SDM845_MX>,
<&rpmhpd SDM845_MSS>;
- power-domain-names = "load_state", "cx", "mx", "mss";
+ power-domain-names = "cx", "mx", "mss";
mba {
memory-region = <&mba_region>;
@@ -4583,7 +4584,6 @@
mboxes = <&apss_shared 0>;
#clock-cells = <0>;
- #power-domain-cells = <1>;
cx_cdev: cx {
#cooling-cells = <2>;
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 18%]
* [PATCH v6 09/13] arm64: dts: qcom: sm8250: Use QMP property to control load state
2021-09-06 8:23 9% [PATCH v6 00/13] Use qmp_send to update co-processor load state Sibi Sankar
` (7 preceding siblings ...)
2021-09-06 8:23 17% ` [PATCH v6 08/13] arm64: dts: qcom: sm8150: " Sibi Sankar
@ 2021-09-06 8:23 17% ` Sibi Sankar
2021-09-06 8:23 16% ` [PATCH v6 10/13] arm64: dts: qcom: sm8350: " Sibi Sankar
` (3 subsequent siblings)
12 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-09-06 8:23 UTC (permalink / raw)
To: mka, swboyd, bjorn.andersson, robh+dt
Cc: ulf.hansson, rjw, agross, ohad, mathieu.poirier, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel, dianders, rishabhb,
sidgup, Sibi Sankar
Use the Qualcomm Mailbox Protocol (QMP) property to control the load
state resources on SM8250 SoCs and drop deprecated power-domains exposed
by AOSS QMP node.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 8c15d9fed08f..2796b27f7c04 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -13,7 +13,6 @@
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sm8250.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
-#include <dt-bindings/power/qcom-aoss-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,apr.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
@@ -2088,13 +2087,14 @@
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
- <&rpmhpd SM8250_LCX>,
+ power-domains = <&rpmhpd SM8250_LCX>,
<&rpmhpd SM8250_LMX>;
- power-domain-names = "load_state", "lcx", "lmx";
+ power-domain-names = "lcx", "lmx";
memory-region = <&slpi_mem>;
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&smp2p_slpi_out 0>;
qcom,smem-state-names = "stop";
@@ -2154,12 +2154,12 @@
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
- <&rpmhpd SM8250_CX>;
- power-domain-names = "load_state", "cx";
+ power-domains = <&rpmhpd SM8250_CX>;
memory-region = <&cdsp_mem>;
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&smp2p_cdsp_out 0>;
qcom,smem-state-names = "stop";
@@ -2907,7 +2907,6 @@
IPCC_MPROC_SIGNAL_GLINK_QMP>;
#clock-cells = <0>;
- #power-domain-cells = <1>;
};
spmi_bus: spmi@c440000 {
@@ -3824,13 +3823,14 @@
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
- <&rpmhpd SM8250_LCX>,
+ power-domains = <&rpmhpd SM8250_LCX>,
<&rpmhpd SM8250_LMX>;
- power-domain-names = "load_state", "lcx", "lmx";
+ power-domain-names = "lcx", "lmx";
memory-region = <&adsp_mem>;
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&smp2p_adsp_out 0>;
qcom,smem-state-names = "stop";
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 17%]
* [PATCH v6 06/13] arm64: dts: qcom: sc7280: Use QMP property to control load state
2021-09-06 8:23 9% [PATCH v6 00/13] Use qmp_send to update co-processor load state Sibi Sankar
` (4 preceding siblings ...)
2021-09-06 8:23 18% ` [PATCH v6 05/13] arm64: dts: qcom: sc7180: Use QMP property to control " Sibi Sankar
@ 2021-09-06 8:23 18% ` Sibi Sankar
2021-09-06 8:23 18% ` [PATCH v6 07/13] arm64: dts: qcom: sdm845: " Sibi Sankar
` (6 subsequent siblings)
12 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-09-06 8:23 UTC (permalink / raw)
To: mka, swboyd, bjorn.andersson, robh+dt
Cc: ulf.hansson, rjw, agross, ohad, mathieu.poirier, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel, dianders, rishabhb,
sidgup, Sibi Sankar
Use the Qualcomm Mailbox Protocol (QMP) property to control the load
state resources on SC7280 SoCs and drop deprecated power-domains exposed
by AOSS QMP node.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 53a21d086178..5e4f4f3b738a 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -10,7 +10,6 @@
#include <dt-bindings/interconnect/qcom,sc7280.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
-#include <dt-bindings/power/qcom-aoss-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/reset/qcom,sdm845-aoss.h>
#include <dt-bindings/reset/qcom,sdm845-pdc.h>
@@ -1481,7 +1480,6 @@
IPCC_MPROC_SIGNAL_GLINK_QMP>;
#clock-cells = <0>;
- #power-domain-cells = <1>;
};
spmi_bus: spmi@c440000 {
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 18%]
* [PATCH v6 04/13] remoteproc: qcom: q6v5: Use qmp_send to update co-processor load state
2021-09-06 8:23 9% [PATCH v6 00/13] Use qmp_send to update co-processor load state Sibi Sankar
` (2 preceding siblings ...)
2021-09-06 8:23 18% ` [PATCH v6 03/13] dt-bindings: remoteproc: qcom: " Sibi Sankar
@ 2021-09-06 8:23 9% ` Sibi Sankar
2021-09-06 8:23 18% ` [PATCH v6 05/13] arm64: dts: qcom: sc7180: Use QMP property to control " Sibi Sankar
` (8 subsequent siblings)
12 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-09-06 8:23 UTC (permalink / raw)
To: mka, swboyd, bjorn.andersson, robh+dt
Cc: ulf.hansson, rjw, agross, ohad, mathieu.poirier, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel, dianders, rishabhb,
sidgup, Sibi Sankar
The power domains exposed by the AOSS QMP driver control the load state
resources linked to modem, adsp, cdsp remoteprocs. These are used to
notify the Always on Subsystem (AOSS) that a particular co-processor is
up/down. AOSS uses this information to wait for the co-processors to
suspend before starting its sleep sequence.
These co-processors enter low-power modes independent to that of the
application processor and the load state resources linked to them are
expected to remain unaltered across system suspend/resume cycles. To
achieve this behavior lets stop using the power-domains exposed by the
AOSS QMP node and replace them with generic qmp_send interface instead.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
drivers/remoteproc/qcom_q6v5.c | 57 ++++++++++++++++++++++++-
drivers/remoteproc/qcom_q6v5.h | 7 ++-
drivers/remoteproc/qcom_q6v5_adsp.c | 7 ++-
drivers/remoteproc/qcom_q6v5_mss.c | 44 ++++---------------
drivers/remoteproc/qcom_q6v5_pas.c | 85 +++++++++----------------------------
drivers/remoteproc/qcom_q6v5_wcss.c | 4 +-
6 files changed, 96 insertions(+), 108 deletions(-)
diff --git a/drivers/remoteproc/qcom_q6v5.c b/drivers/remoteproc/qcom_q6v5.c
index 7e9244c748da..eada7e34f3af 100644
--- a/drivers/remoteproc/qcom_q6v5.c
+++ b/drivers/remoteproc/qcom_q6v5.c
@@ -16,8 +16,30 @@
#include "qcom_common.h"
#include "qcom_q6v5.h"
+#define Q6V5_LOAD_STATE_MSG_LEN 64
#define Q6V5_PANIC_DELAY_MS 200
+static int q6v5_load_state_toggle(struct qcom_q6v5 *q6v5, bool enable)
+{
+ char buf[Q6V5_LOAD_STATE_MSG_LEN];
+ int ret;
+
+ if (!q6v5->qmp)
+ return 0;
+
+ ret = snprintf(buf, sizeof(buf),
+ "{class: image, res: load_state, name: %s, val: %s}",
+ q6v5->load_state, enable ? "on" : "off");
+
+ WARN_ON(ret >= Q6V5_LOAD_STATE_MSG_LEN);
+
+ ret = qmp_send(q6v5->qmp, buf, sizeof(buf));
+ if (ret)
+ dev_err(q6v5->dev, "failed to toggle load state\n");
+
+ return ret;
+}
+
/**
* qcom_q6v5_prepare() - reinitialize the qcom_q6v5 context before start
* @q6v5: reference to qcom_q6v5 context to be reinitialized
@@ -26,6 +48,12 @@
*/
int qcom_q6v5_prepare(struct qcom_q6v5 *q6v5)
{
+ int ret;
+
+ ret = q6v5_load_state_toggle(q6v5, true);
+ if (ret)
+ return ret;
+
reinit_completion(&q6v5->start_done);
reinit_completion(&q6v5->stop_done);
@@ -47,6 +75,7 @@ EXPORT_SYMBOL_GPL(qcom_q6v5_prepare);
int qcom_q6v5_unprepare(struct qcom_q6v5 *q6v5)
{
disable_irq(q6v5->handover_irq);
+ q6v5_load_state_toggle(q6v5, false);
return !q6v5->handover_issued;
}
@@ -196,12 +225,13 @@ EXPORT_SYMBOL_GPL(qcom_q6v5_panic);
* @pdev: platform_device reference for acquiring resources
* @rproc: associated remoteproc instance
* @crash_reason: SMEM id for crash reason string, or 0 if none
+ * @load_state: load state resource string
* @handover: function to be called when proxy resources should be released
*
* Return: 0 on success, negative errno on failure
*/
int qcom_q6v5_init(struct qcom_q6v5 *q6v5, struct platform_device *pdev,
- struct rproc *rproc, int crash_reason,
+ struct rproc *rproc, int crash_reason, const char *load_state,
void (*handover)(struct qcom_q6v5 *q6v5))
{
int ret;
@@ -286,9 +316,34 @@ int qcom_q6v5_init(struct qcom_q6v5 *q6v5, struct platform_device *pdev,
return PTR_ERR(q6v5->state);
}
+ q6v5->load_state = devm_kstrdup_const(&pdev->dev, load_state, GFP_KERNEL);
+ q6v5->qmp = qmp_get(&pdev->dev);
+ if (IS_ERR(q6v5->qmp)) {
+ if (PTR_ERR(q6v5->qmp) != -ENODEV)
+ return dev_err_probe(&pdev->dev, PTR_ERR(q6v5->qmp),
+ "failed to acquire load state\n");
+ q6v5->qmp = NULL;
+ } else if (!q6v5->load_state) {
+ if (!load_state)
+ dev_err(&pdev->dev, "load state resource string empty\n");
+
+ qmp_put(q6v5->qmp);
+ return load_state ? -ENOMEM : -EINVAL;
+ }
+
return 0;
}
EXPORT_SYMBOL_GPL(qcom_q6v5_init);
+/**
+ * qcom_q6v5_deinit() - deinitialize the q6v5 common struct
+ * @q6v5: reference to qcom_q6v5 context to be deinitialized
+ */
+void qcom_q6v5_deinit(struct qcom_q6v5 *q6v5)
+{
+ qmp_put(q6v5->qmp);
+}
+EXPORT_SYMBOL_GPL(qcom_q6v5_deinit);
+
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("Qualcomm Peripheral Image Loader for Q6V5");
diff --git a/drivers/remoteproc/qcom_q6v5.h b/drivers/remoteproc/qcom_q6v5.h
index 1c212f670cbc..f35e04471ed7 100644
--- a/drivers/remoteproc/qcom_q6v5.h
+++ b/drivers/remoteproc/qcom_q6v5.h
@@ -5,6 +5,7 @@
#include <linux/kernel.h>
#include <linux/completion.h>
+#include <linux/soc/qcom/qcom_aoss.h>
struct rproc;
struct qcom_smem_state;
@@ -15,6 +16,8 @@ struct qcom_q6v5 {
struct rproc *rproc;
struct qcom_smem_state *state;
+ struct qmp *qmp;
+
unsigned stop_bit;
int wdog_irq;
@@ -32,12 +35,14 @@ struct qcom_q6v5 {
bool running;
+ const char *load_state;
void (*handover)(struct qcom_q6v5 *q6v5);
};
int qcom_q6v5_init(struct qcom_q6v5 *q6v5, struct platform_device *pdev,
- struct rproc *rproc, int crash_reason,
+ struct rproc *rproc, int crash_reason, const char *load_state,
void (*handover)(struct qcom_q6v5 *q6v5));
+void qcom_q6v5_deinit(struct qcom_q6v5 *q6v5);
int qcom_q6v5_prepare(struct qcom_q6v5 *q6v5);
int qcom_q6v5_unprepare(struct qcom_q6v5 *q6v5);
diff --git a/drivers/remoteproc/qcom_q6v5_adsp.c b/drivers/remoteproc/qcom_q6v5_adsp.c
index 8b0d8bbacd2e..098362e6e233 100644
--- a/drivers/remoteproc/qcom_q6v5_adsp.c
+++ b/drivers/remoteproc/qcom_q6v5_adsp.c
@@ -185,7 +185,9 @@ static int adsp_start(struct rproc *rproc)
int ret;
unsigned int val;
- qcom_q6v5_prepare(&adsp->q6v5);
+ ret = qcom_q6v5_prepare(&adsp->q6v5);
+ if (ret)
+ return ret;
ret = clk_prepare_enable(adsp->xo);
if (ret)
@@ -465,7 +467,7 @@ static int adsp_probe(struct platform_device *pdev)
if (ret)
goto disable_pm;
- ret = qcom_q6v5_init(&adsp->q6v5, pdev, rproc, desc->crash_reason_smem,
+ ret = qcom_q6v5_init(&adsp->q6v5, pdev, rproc, desc->crash_reason_smem, NULL,
qcom_adsp_pil_handover);
if (ret)
goto disable_pm;
@@ -500,6 +502,7 @@ static int adsp_remove(struct platform_device *pdev)
rproc_del(adsp->rproc);
+ qcom_q6v5_deinit(&adsp->q6v5);
qcom_remove_glink_subdev(adsp->rproc, &adsp->glink_subdev);
qcom_remove_sysmon_subdev(adsp->sysmon);
qcom_remove_ssr_subdev(adsp->rproc, &adsp->ssr_subdev);
diff --git a/drivers/remoteproc/qcom_q6v5_mss.c b/drivers/remoteproc/qcom_q6v5_mss.c
index 423b31dfa574..7a1422bd7925 100644
--- a/drivers/remoteproc/qcom_q6v5_mss.c
+++ b/drivers/remoteproc/qcom_q6v5_mss.c
@@ -137,7 +137,6 @@ struct rproc_hexagon_res {
char **proxy_clk_names;
char **reset_clk_names;
char **active_clk_names;
- char **active_pd_names;
char **proxy_pd_names;
int version;
bool need_mem_protection;
@@ -169,12 +168,10 @@ struct q6v5 {
struct clk *active_clks[8];
struct clk *reset_clks[4];
struct clk *proxy_clks[4];
- struct device *active_pds[1];
struct device *proxy_pds[3];
int active_clk_count;
int reset_clk_count;
int proxy_clk_count;
- int active_pd_count;
int proxy_pd_count;
struct reg_info active_regs[1];
@@ -895,18 +892,14 @@ static int q6v5_mba_load(struct q6v5 *qproc)
int xfermemop_ret;
bool mba_load_err = false;
- qcom_q6v5_prepare(&qproc->q6v5);
-
- ret = q6v5_pds_enable(qproc, qproc->active_pds, qproc->active_pd_count);
- if (ret < 0) {
- dev_err(qproc->dev, "failed to enable active power domains\n");
- goto disable_irqs;
- }
+ ret = qcom_q6v5_prepare(&qproc->q6v5);
+ if (ret)
+ return ret;
ret = q6v5_pds_enable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
if (ret < 0) {
dev_err(qproc->dev, "failed to enable proxy power domains\n");
- goto disable_active_pds;
+ goto disable_irqs;
}
ret = q6v5_regulator_enable(qproc, qproc->fallback_proxy_regs,
@@ -1039,8 +1032,6 @@ static int q6v5_mba_load(struct q6v5 *qproc)
qproc->fallback_proxy_reg_count);
disable_proxy_pds:
q6v5_pds_disable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
-disable_active_pds:
- q6v5_pds_disable(qproc, qproc->active_pds, qproc->active_pd_count);
disable_irqs:
qcom_q6v5_unprepare(&qproc->q6v5);
@@ -1076,7 +1067,6 @@ static void q6v5_mba_reclaim(struct q6v5 *qproc)
qproc->active_clk_count);
q6v5_regulator_disable(qproc, qproc->active_regs,
qproc->active_reg_count);
- q6v5_pds_disable(qproc, qproc->active_pds, qproc->active_pd_count);
/* In case of failure or coredump scenario where reclaiming MBA memory
* could not happen reclaim it here.
@@ -1756,14 +1746,6 @@ static int q6v5_probe(struct platform_device *pdev)
}
qproc->active_reg_count = ret;
- ret = q6v5_pds_attach(&pdev->dev, qproc->active_pds,
- desc->active_pd_names);
- if (ret < 0) {
- dev_err(&pdev->dev, "Failed to attach active power domains\n");
- goto free_rproc;
- }
- qproc->active_pd_count = ret;
-
ret = q6v5_pds_attach(&pdev->dev, qproc->proxy_pds,
desc->proxy_pd_names);
/* Fallback to regulators for old device trees */
@@ -1773,12 +1755,12 @@ static int q6v5_probe(struct platform_device *pdev)
desc->fallback_proxy_supply);
if (ret < 0) {
dev_err(&pdev->dev, "Failed to get fallback proxy regulators.\n");
- goto detach_active_pds;
+ goto free_rproc;
}
qproc->fallback_proxy_reg_count = ret;
} else if (ret < 0) {
dev_err(&pdev->dev, "Failed to init power domains\n");
- goto detach_active_pds;
+ goto free_rproc;
} else {
qproc->proxy_pd_count = ret;
}
@@ -1792,7 +1774,7 @@ static int q6v5_probe(struct platform_device *pdev)
qproc->need_mem_protection = desc->need_mem_protection;
qproc->has_mba_logs = desc->has_mba_logs;
- ret = qcom_q6v5_init(&qproc->q6v5, pdev, rproc, MPSS_CRASH_REASON_SMEM,
+ ret = qcom_q6v5_init(&qproc->q6v5, pdev, rproc, MPSS_CRASH_REASON_SMEM, "modem",
qcom_msa_handover);
if (ret)
goto detach_proxy_pds;
@@ -1822,8 +1804,6 @@ static int q6v5_probe(struct platform_device *pdev)
qcom_remove_glink_subdev(rproc, &qproc->glink_subdev);
detach_proxy_pds:
q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
-detach_active_pds:
- q6v5_pds_detach(qproc, qproc->active_pds, qproc->active_pd_count);
free_rproc:
rproc_free(rproc);
@@ -1837,13 +1817,13 @@ static int q6v5_remove(struct platform_device *pdev)
rproc_del(rproc);
+ qcom_q6v5_deinit(&qproc->q6v5);
qcom_remove_sysmon_subdev(qproc->sysmon);
qcom_remove_ssr_subdev(rproc, &qproc->ssr_subdev);
qcom_remove_smd_subdev(rproc, &qproc->smd_subdev);
qcom_remove_glink_subdev(rproc, &qproc->glink_subdev);
q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
- q6v5_pds_detach(qproc, qproc->active_pds, qproc->active_pd_count);
rproc_free(rproc);
@@ -1867,10 +1847,6 @@ static const struct rproc_hexagon_res sc7180_mss = {
"nav",
NULL
},
- .active_pd_names = (char*[]){
- "load_state",
- NULL
- },
.proxy_pd_names = (char*[]){
"cx",
"mx",
@@ -1903,10 +1879,6 @@ static const struct rproc_hexagon_res sdm845_mss = {
"mnoc_axi",
NULL
},
- .active_pd_names = (char*[]){
- "load_state",
- NULL
- },
.proxy_pd_names = (char*[]){
"cx",
"mx",
diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q6v5_pas.c
index 401b1ec90785..7036e6e9eff4 100644
--- a/drivers/remoteproc/qcom_q6v5_pas.c
+++ b/drivers/remoteproc/qcom_q6v5_pas.c
@@ -37,9 +37,9 @@ struct adsp_data {
bool has_aggre2_clk;
bool auto_boot;
- char **active_pd_names;
char **proxy_pd_names;
+ const char *load_state;
const char *ssr_name;
const char *sysmon_name;
int ssctl_id;
@@ -57,10 +57,8 @@ struct qcom_adsp {
struct regulator *cx_supply;
struct regulator *px_supply;
- struct device *active_pds[1];
struct device *proxy_pds[3];
- int active_pd_count;
int proxy_pd_count;
int pas_id;
@@ -149,15 +147,13 @@ static int adsp_start(struct rproc *rproc)
struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
int ret;
- qcom_q6v5_prepare(&adsp->q6v5);
-
- ret = adsp_pds_enable(adsp, adsp->active_pds, adsp->active_pd_count);
- if (ret < 0)
- goto disable_irqs;
+ ret = qcom_q6v5_prepare(&adsp->q6v5);
+ if (ret)
+ return ret;
ret = adsp_pds_enable(adsp, adsp->proxy_pds, adsp->proxy_pd_count);
if (ret < 0)
- goto disable_active_pds;
+ goto disable_irqs;
ret = clk_prepare_enable(adsp->xo);
if (ret)
@@ -201,8 +197,6 @@ static int adsp_start(struct rproc *rproc)
clk_disable_unprepare(adsp->xo);
disable_proxy_pds:
adsp_pds_disable(adsp, adsp->proxy_pds, adsp->proxy_pd_count);
-disable_active_pds:
- adsp_pds_disable(adsp, adsp->active_pds, adsp->active_pd_count);
disable_irqs:
qcom_q6v5_unprepare(&adsp->q6v5);
@@ -234,7 +228,6 @@ static int adsp_stop(struct rproc *rproc)
if (ret)
dev_err(adsp->dev, "failed to shutdown: %d\n", ret);
- adsp_pds_disable(adsp, adsp->active_pds, adsp->active_pd_count);
handover = qcom_q6v5_unprepare(&adsp->q6v5);
if (handover)
qcom_pas_handover(&adsp->q6v5);
@@ -456,19 +449,13 @@ static int adsp_probe(struct platform_device *pdev)
if (ret)
goto free_rproc;
- ret = adsp_pds_attach(&pdev->dev, adsp->active_pds,
- desc->active_pd_names);
- if (ret < 0)
- goto free_rproc;
- adsp->active_pd_count = ret;
-
ret = adsp_pds_attach(&pdev->dev, adsp->proxy_pds,
desc->proxy_pd_names);
if (ret < 0)
- goto detach_active_pds;
+ goto free_rproc;
adsp->proxy_pd_count = ret;
- ret = qcom_q6v5_init(&adsp->q6v5, pdev, rproc, desc->crash_reason_smem,
+ ret = qcom_q6v5_init(&adsp->q6v5, pdev, rproc, desc->crash_reason_smem, desc->load_state,
qcom_pas_handover);
if (ret)
goto detach_proxy_pds;
@@ -492,8 +479,6 @@ static int adsp_probe(struct platform_device *pdev)
detach_proxy_pds:
adsp_pds_detach(adsp, adsp->proxy_pds, adsp->proxy_pd_count);
-detach_active_pds:
- adsp_pds_detach(adsp, adsp->active_pds, adsp->active_pd_count);
free_rproc:
rproc_free(rproc);
@@ -506,6 +491,7 @@ static int adsp_remove(struct platform_device *pdev)
rproc_del(adsp->rproc);
+ qcom_q6v5_deinit(&adsp->q6v5);
qcom_remove_glink_subdev(adsp->rproc, &adsp->glink_subdev);
qcom_remove_sysmon_subdev(adsp->sysmon);
qcom_remove_smd_subdev(adsp->rproc, &adsp->smd_subdev);
@@ -532,14 +518,11 @@ static const struct adsp_data sm8150_adsp_resource = {
.pas_id = 1,
.has_aggre2_clk = false,
.auto_boot = true,
- .active_pd_names = (char*[]){
- "load_state",
- NULL
- },
.proxy_pd_names = (char*[]){
"cx",
NULL
},
+ .load_state = "adsp",
.ssr_name = "lpass",
.sysmon_name = "adsp",
.ssctl_id = 0x14,
@@ -551,15 +534,12 @@ static const struct adsp_data sm8250_adsp_resource = {
.pas_id = 1,
.has_aggre2_clk = false,
.auto_boot = true,
- .active_pd_names = (char*[]){
- "load_state",
- NULL
- },
.proxy_pd_names = (char*[]){
"lcx",
"lmx",
NULL
},
+ .load_state = "adsp",
.ssr_name = "lpass",
.sysmon_name = "adsp",
.ssctl_id = 0x14,
@@ -571,15 +551,12 @@ static const struct adsp_data sm8350_adsp_resource = {
.pas_id = 1,
.has_aggre2_clk = false,
.auto_boot = true,
- .active_pd_names = (char*[]){
- "load_state",
- NULL
- },
.proxy_pd_names = (char*[]){
"lcx",
"lmx",
NULL
},
+ .load_state = "adsp",
.ssr_name = "lpass",
.sysmon_name = "adsp",
.ssctl_id = 0x14,
@@ -617,14 +594,11 @@ static const struct adsp_data sm8150_cdsp_resource = {
.pas_id = 18,
.has_aggre2_clk = false,
.auto_boot = true,
- .active_pd_names = (char*[]){
- "load_state",
- NULL
- },
.proxy_pd_names = (char*[]){
"cx",
NULL
},
+ .load_state = "cdsp",
.ssr_name = "cdsp",
.sysmon_name = "cdsp",
.ssctl_id = 0x17,
@@ -636,14 +610,11 @@ static const struct adsp_data sm8250_cdsp_resource = {
.pas_id = 18,
.has_aggre2_clk = false,
.auto_boot = true,
- .active_pd_names = (char*[]){
- "load_state",
- NULL
- },
.proxy_pd_names = (char*[]){
"cx",
NULL
},
+ .load_state = "cdsp",
.ssr_name = "cdsp",
.sysmon_name = "cdsp",
.ssctl_id = 0x17,
@@ -655,14 +626,11 @@ static const struct adsp_data sm8350_cdsp_resource = {
.pas_id = 18,
.has_aggre2_clk = false,
.auto_boot = true,
- .active_pd_names = (char*[]){
- "load_state",
- NULL
- },
.proxy_pd_names = (char*[]){
"cx",
NULL
},
+ .load_state = "cdsp",
.ssr_name = "cdsp",
.sysmon_name = "cdsp",
.ssctl_id = 0x17,
@@ -675,15 +643,12 @@ static const struct adsp_data mpss_resource_init = {
.minidump_id = 3,
.has_aggre2_clk = false,
.auto_boot = false,
- .active_pd_names = (char*[]){
- "load_state",
- NULL
- },
.proxy_pd_names = (char*[]){
"cx",
"mss",
NULL
},
+ .load_state = "modem",
.ssr_name = "mpss",
.sysmon_name = "modem",
.ssctl_id = 0x12,
@@ -695,14 +660,11 @@ static const struct adsp_data sc8180x_mpss_resource = {
.pas_id = 4,
.has_aggre2_clk = false,
.auto_boot = false,
- .active_pd_names = (char*[]){
- "load_state",
- NULL
- },
.proxy_pd_names = (char*[]){
"cx",
NULL
},
+ .load_state = "modem",
.ssr_name = "mpss",
.sysmon_name = "modem",
.ssctl_id = 0x12,
@@ -725,15 +687,12 @@ static const struct adsp_data sm8150_slpi_resource = {
.pas_id = 12,
.has_aggre2_clk = false,
.auto_boot = true,
- .active_pd_names = (char*[]){
- "load_state",
- NULL
- },
.proxy_pd_names = (char*[]){
"lcx",
"lmx",
NULL
},
+ .load_state = "slpi",
.ssr_name = "dsps",
.sysmon_name = "slpi",
.ssctl_id = 0x16,
@@ -745,15 +704,12 @@ static const struct adsp_data sm8250_slpi_resource = {
.pas_id = 12,
.has_aggre2_clk = false,
.auto_boot = true,
- .active_pd_names = (char*[]){
- "load_state",
- NULL
- },
.proxy_pd_names = (char*[]){
"lcx",
"lmx",
NULL
},
+ .load_state = "slpi",
.ssr_name = "dsps",
.sysmon_name = "slpi",
.ssctl_id = 0x16,
@@ -765,15 +721,12 @@ static const struct adsp_data sm8350_slpi_resource = {
.pas_id = 12,
.has_aggre2_clk = false,
.auto_boot = true,
- .active_pd_names = (char*[]){
- "load_state",
- NULL
- },
.proxy_pd_names = (char*[]){
"lcx",
"lmx",
NULL
},
+ .load_state = "slpi",
.ssr_name = "dsps",
.sysmon_name = "slpi",
.ssctl_id = 0x16,
diff --git a/drivers/remoteproc/qcom_q6v5_wcss.c b/drivers/remoteproc/qcom_q6v5_wcss.c
index 20d50ec7eff1..0689288a2425 100644
--- a/drivers/remoteproc/qcom_q6v5_wcss.c
+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
@@ -1044,8 +1044,7 @@ static int q6v5_wcss_probe(struct platform_device *pdev)
if (ret)
goto free_rproc;
- ret = qcom_q6v5_init(&wcss->q6v5, pdev, rproc, desc->crash_reason_smem,
- NULL);
+ ret = qcom_q6v5_init(&wcss->q6v5, pdev, rproc, desc->crash_reason_smem, NULL, NULL);
if (ret)
goto free_rproc;
@@ -1075,6 +1074,7 @@ static int q6v5_wcss_remove(struct platform_device *pdev)
{
struct rproc *rproc = platform_get_drvdata(pdev);
+ qcom_q6v5_deinit(&qproc->q6v5);
rproc_del(rproc);
rproc_free(rproc);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 9%]
* [PATCH v6 01/13] dt-bindings: soc: qcom: aoss: Drop the load state power-domain
2021-09-06 8:23 9% [PATCH v6 00/13] Use qmp_send to update co-processor load state Sibi Sankar
@ 2021-09-06 8:23 17% ` Sibi Sankar
2021-09-06 8:23 15% ` [PATCH v6 02/13] dt-bindings: remoteproc: qcom: pas: Add QMP property Sibi Sankar
` (11 subsequent siblings)
12 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-09-06 8:23 UTC (permalink / raw)
To: mka, swboyd, bjorn.andersson, robh+dt
Cc: ulf.hansson, rjw, agross, ohad, mathieu.poirier, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel, dianders, rishabhb,
sidgup, Sibi Sankar
The power-domains exposed by AOSS QMP node are used to notify the Always
on Subsystem (AOSS) that a particular co-processor is up/down. These
co-processors enter low-power modes independent to that of the application
processor and their states are expected to remain unaltered across system
suspend/resume cycles. To achieve this behavior let's drop the load
power-domain and replace them with generic qmp_send interface instead.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml | 11 +----------
1 file changed, 1 insertion(+), 10 deletions(-)
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml
index 1904612fad85..e2e173dfada7 100644
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml
@@ -19,8 +19,7 @@ description:
The AOSS side channel exposes control over a set of resources, used to control
a set of debug related clocks and to affect the low power state of resources
- related to the secondary subsystems. These resources are exposed as a set of
- power-domains.
+ related to the secondary subsystems.
properties:
compatible:
@@ -58,13 +57,6 @@ properties:
description:
The single clock represents the QDSS clock.
- "#power-domain-cells":
- const: 1
- description: |
- The provided power-domains are:
- CDSP state (0), LPASS state (1), modem state (2), SLPI
- state (3), SPSS state (4) and Venus state (5).
-
required:
- compatible
- reg
@@ -102,7 +94,6 @@ examples:
mboxes = <&apss_shared 0>;
#clock-cells = <0>;
- #power-domain-cells = <1>;
cx_cdev: cx {
#cooling-cells = <2>;
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 17%]
* [PATCH v6 05/13] arm64: dts: qcom: sc7180: Use QMP property to control load state
2021-09-06 8:23 9% [PATCH v6 00/13] Use qmp_send to update co-processor load state Sibi Sankar
` (3 preceding siblings ...)
2021-09-06 8:23 9% ` [PATCH v6 04/13] remoteproc: qcom: q6v5: Use qmp_send to update co-processor load state Sibi Sankar
@ 2021-09-06 8:23 18% ` Sibi Sankar
2021-09-06 8:23 18% ` [PATCH v6 06/13] arm64: dts: qcom: sc7280: " Sibi Sankar
` (7 subsequent siblings)
12 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-09-06 8:23 UTC (permalink / raw)
To: mka, swboyd, bjorn.andersson, robh+dt
Cc: ulf.hansson, rjw, agross, ohad, mathieu.poirier, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel, dianders, rishabhb,
sidgup, Sibi Sankar
Use the Qualcomm Mailbox Protocol (QMP) property to control the load
state resources on SC7180 SoCs and drop deprecated power-domains exposed
by AOSS QMP node.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index c8921e2d6480..24ee106b933a 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -15,7 +15,6 @@
#include <dt-bindings/interconnect/qcom,sc7180.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy-qcom-qusb2.h>
-#include <dt-bindings/power/qcom-aoss-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/reset/qcom,sdm845-aoss.h>
#include <dt-bindings/reset/qcom,sdm845-pdc.h>
@@ -1922,14 +1921,15 @@
clock-names = "iface", "bus", "nav", "snoc_axi",
"mnoc_axi", "xo";
- power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
- <&rpmhpd SC7180_CX>,
+ power-domains = <&rpmhpd SC7180_CX>,
<&rpmhpd SC7180_MX>,
<&rpmhpd SC7180_MSS>;
- power-domain-names = "load_state", "cx", "mx", "mss";
+ power-domain-names = "cx", "mx", "mss";
memory-region = <&mpss_mem>;
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&modem_smp2p_out 0>;
qcom,smem-state-names = "stop";
@@ -3224,7 +3224,6 @@
mboxes = <&apss_shared 0>;
#clock-cells = <0>;
- #power-domain-cells = <1>;
};
spmi_bus: spmi@c440000 {
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 18%]
* [PATCH v6 03/13] dt-bindings: remoteproc: qcom: Add QMP property
2021-09-06 8:23 9% [PATCH v6 00/13] Use qmp_send to update co-processor load state Sibi Sankar
2021-09-06 8:23 17% ` [PATCH v6 01/13] dt-bindings: soc: qcom: aoss: Drop the load state power-domain Sibi Sankar
2021-09-06 8:23 15% ` [PATCH v6 02/13] dt-bindings: remoteproc: qcom: pas: Add QMP property Sibi Sankar
@ 2021-09-06 8:23 18% ` Sibi Sankar
2021-09-06 8:23 9% ` [PATCH v6 04/13] remoteproc: qcom: q6v5: Use qmp_send to update co-processor load state Sibi Sankar
` (9 subsequent siblings)
12 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-09-06 8:23 UTC (permalink / raw)
To: mka, swboyd, bjorn.andersson, robh+dt
Cc: ulf.hansson, rjw, agross, ohad, mathieu.poirier, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel, dianders, rishabhb,
sidgup, Sibi Sankar
Add Qualcomm Mailbox Protocol (QMP) property to replace the power domain
exposed by the AOSS QMP node.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
index 69c49c7b2cff..494257010629 100644
--- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
@@ -174,7 +174,12 @@ For the compatible string below the following supplies are required:
must be "cx", "mx"
qcom,sc7180-mss-pil:
qcom,sdm845-mss-pil:
- must be "cx", "mx", "mss", "load_state"
+ must be "cx", "mx", "mss"
+
+- qcom,qmp:
+ Usage: optional
+ Value type: <phandle>
+ Definition: reference to the AOSS side-channel message RAM.
- qcom,smem-states:
Usage: required
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 18%]
* [PATCH v6 02/13] dt-bindings: remoteproc: qcom: pas: Add QMP property
2021-09-06 8:23 9% [PATCH v6 00/13] Use qmp_send to update co-processor load state Sibi Sankar
2021-09-06 8:23 17% ` [PATCH v6 01/13] dt-bindings: soc: qcom: aoss: Drop the load state power-domain Sibi Sankar
@ 2021-09-06 8:23 15% ` Sibi Sankar
2021-09-08 13:51 0% ` Rob Herring
2021-09-06 8:23 18% ` [PATCH v6 03/13] dt-bindings: remoteproc: qcom: " Sibi Sankar
` (10 subsequent siblings)
12 siblings, 1 reply; 200+ results
From: Sibi Sankar @ 2021-09-06 8:23 UTC (permalink / raw)
To: mka, swboyd, bjorn.andersson, robh+dt
Cc: ulf.hansson, rjw, agross, ohad, mathieu.poirier, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel, dianders, rishabhb,
sidgup, Sibi Sankar
The load state power-domain, used by the co-processors to notify the
Always on Subsystem (AOSS) that a particular co-processor is up/down,
suffers from the side-effect of changing states during suspend/resume.
However the co-processors enter low-power modes independent to that of
the application processor and their states are expected to remain
unaltered across system suspend/resume cycles. To achieve this behavior
let's drop the load state power-domain and replace them with the qmp
property for all SoCs supporting low power mode signalling.
Due to the current broken load state implementation, we can afford the
binding breakage that ensues and the remoteproc functionality will remain
the same when using newer kernels with older dtbs.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
v6:
* Updated commit message to explain binding breakage. [Stephen]
.../devicetree/bindings/remoteproc/qcom,adsp.yaml | 61 +++++++++++-----------
1 file changed, 31 insertions(+), 30 deletions(-)
diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml
index 0c112f3264a9..0d2b5bd4907a 100644
--- a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml
@@ -93,6 +93,10 @@ properties:
maxItems: 1
description: Reference to the reserved-memory for the Hexagon core
+ qcom,qmp:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: Reference to the AOSS side-channel message RAM.
+
qcom,smem-states:
$ref: /schemas/types.yaml#/definitions/phandle-array
description: States used by the AP to signal the Hexagon core
@@ -369,13 +373,11 @@ allOf:
properties:
power-domains:
items:
- - description: Load State power domain
- description: CX power domain
- description: MX power domain
- description: MSS power domain
power-domain-names:
items:
- - const: load_state
- const: cx
- const: mx
- const: mss
@@ -391,43 +393,20 @@ allOf:
properties:
power-domains:
items:
- - description: Load State power domain
- description: CX power domain
- power-domain-names:
- items:
- - const: load_state
- - const: cx
- if:
properties:
compatible:
contains:
enum:
+ - qcom,sdx55-mpss-pas
- qcom,sm8150-mpss-pas
- qcom,sm8350-mpss-pas
then:
properties:
power-domains:
items:
- - description: Load State power domain
- - description: CX power domain
- - description: MSS power domain
- power-domain-names:
- items:
- - const: load_state
- - const: cx
- - const: mss
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,sdx55-mpss-pas
- then:
- properties:
- power-domains:
- items:
- description: CX power domain
- description: MSS power domain
power-domain-names:
@@ -451,12 +430,10 @@ allOf:
properties:
power-domains:
items:
- - description: Load State power domain
- description: LCX power domain
- description: LMX power domain
power-domain-names:
items:
- - const: load_state
- const: lcx
- const: lmx
@@ -470,12 +447,10 @@ allOf:
properties:
power-domains:
items:
- - description: Load State power domain
- description: CX power domain
- description: MXC power domain
power-domain-names:
items:
- - const: load_state
- const: cx
- const: mxc
@@ -511,6 +486,32 @@ allOf:
- const: mss_restart
- const: pdc_reset
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sc7180-mpss-pas
+ - qcom,sc8180x-adsp-pas
+ - qcom,sc8180x-cdsp-pas
+ - qcom,sc8180x-mpss-pas
+ - qcom,sm8150-adsp-pas
+ - qcom,sm8150-cdsp-pas
+ - qcom,sm8150-mpss-pas
+ - qcom,sm8150-slpi-pas
+ - qcom,sm8250-adsp-pas
+ - qcom,sm8250-cdsp-pas
+ - qcom,sm8250-slpi-pas
+ - qcom,sm8350-adsp-pas
+ - qcom,sm8350-cdsp-pas
+ - qcom,sm8350-mpss-pas
+ - qcom,sm8350-slpi-pas
+ then:
+ properties:
+ qcom,qmp:
+ items:
+ - description: Reference to the AOSS side-channel message RAM.
+
examples:
- |
#include <dt-bindings/clock/qcom,rpmcc.h>
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 15%]
* [PATCH v6 00/13] Use qmp_send to update co-processor load state
@ 2021-09-06 8:23 9% Sibi Sankar
2021-09-06 8:23 17% ` [PATCH v6 01/13] dt-bindings: soc: qcom: aoss: Drop the load state power-domain Sibi Sankar
` (12 more replies)
0 siblings, 13 replies; 200+ results
From: Sibi Sankar @ 2021-09-06 8:23 UTC (permalink / raw)
To: mka, swboyd, bjorn.andersson, robh+dt
Cc: ulf.hansson, rjw, agross, ohad, mathieu.poirier, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel, dianders, rishabhb,
sidgup, Sibi Sankar
The power domains exposed by the AOSS QMP driver control the load state
resources linked to modem, adsp, cdsp remoteprocs. These are used to
notify the Always on Subsystem (AOSS) that a particular co-processor is
up/down. AOSS uses this information to wait for the co-processors to
suspend before starting its sleep sequence. These co-processors enter
low-power modes independent to that of the application processor and
the load state resources linked to them are expected to remain unaltered
across system suspend/resume cycles. To achieve this behavior let's stop
modeling them as power-domains and replace them with generic qmp_send
interface instead.
https://lore.kernel.org/lkml/20200913034603.GV3715@yoga/
Previous discussion on dropping power-domain support from AOSS QMP driver
Depends on:
qmp_send: https://patchwork.kernel.org/project/linux-arm-msm/cover/1630420228-31075-1-git-send-email-deesin@codeaurora.org/
V6:
* Updated commit message to explain binding breakage (patch 2). [Stephen]
V5:
* Fixup power-domain count (patch 2). [Matthias]
* Add WARN_ON on truncation, remove redundant initialization
code, use dev_err_probe (patch 4). [Stephen]
* Use devm_kstrdup, handle kstrdup failure due to
no memory and set qmp to NULL when not available
(patch 4). [Bjorn]
V4:
* Rebase patch 1 due to the aoss-qmp yaml conversion (Dropping Rb).
* Commit message change and sc8180x co-processor addition
to patch 2. [Rob/Bjorn]
* Drop unused pdev and kfree the load state string in q6v5_deinit
/probe path for patch 4. [Matthias]
* Replaced "binding" with "property" across the series. [Matthias]
* Commit message change and drop incorrect cleanup on cooling
device probe failures. [Matthias]
V3:
* Misc. documentation fixes [patch 2]:
- Reduce power-domain maxItems due to load_state pd removal
- Combine compatibles where possible with the load_state pd removal
- Fixup the qcom,qmp ref to phandle type
V2:
* load_state is currently broken on mainline so be safely dropped
without side-effects.
* Rebased on top of qmp_send v3 series.
* Dropped R-b from Stephen and Rob on patch 3 due to the yaml
conversion.
* New patch [12] to drop unused aoss-qmp header.
* Commit message update [patch 1] [Rob]
* Reorder the series [Stephen]
Sibi Sankar (13):
dt-bindings: soc: qcom: aoss: Drop the load state power-domain
dt-bindings: remoteproc: qcom: pas: Add QMP property
dt-bindings: remoteproc: qcom: Add QMP property
remoteproc: qcom: q6v5: Use qmp_send to update co-processor load state
arm64: dts: qcom: sc7180: Use QMP property to control load state
arm64: dts: qcom: sc7280: Use QMP property to control load state
arm64: dts: qcom: sdm845: Use QMP property to control load state
arm64: dts: qcom: sm8150: Use QMP property to control load state
arm64: dts: qcom: sm8250: Use QMP property to control load state
arm64: dts: qcom: sm8350: Use QMP property to control load state
soc: qcom: aoss: Drop power domain support
dt-bindings: msm/dp: Remove aoss-qmp header
dt-bindings: soc: qcom: aoss: Delete unused power-domain definitions
.../bindings/display/msm/dp-controller.yaml | 1 -
.../devicetree/bindings/remoteproc/qcom,adsp.yaml | 61 ++++++------
.../devicetree/bindings/remoteproc/qcom,q6v5.txt | 7 +-
.../bindings/soc/qcom/qcom,aoss-qmp.yaml | 11 +--
arch/arm64/boot/dts/qcom/sc7180.dtsi | 9 +-
arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 -
arch/arm64/boot/dts/qcom/sdm845.dtsi | 8 +-
arch/arm64/boot/dts/qcom/sm8150.dtsi | 28 +++---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 22 ++---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 30 +++---
drivers/remoteproc/qcom_q6v5.c | 57 ++++++++++-
drivers/remoteproc/qcom_q6v5.h | 7 +-
drivers/remoteproc/qcom_q6v5_adsp.c | 7 +-
drivers/remoteproc/qcom_q6v5_mss.c | 44 ++-------
drivers/remoteproc/qcom_q6v5_pas.c | 85 ++++------------
drivers/remoteproc/qcom_q6v5_wcss.c | 4 +-
drivers/soc/qcom/qcom_aoss.c | 107 ---------------------
include/dt-bindings/power/qcom-aoss-qmp.h | 14 ---
18 files changed, 183 insertions(+), 321 deletions(-)
delete mode 100644 include/dt-bindings/power/qcom-aoss-qmp.h
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [relevance 9%]
* Re: [PATCH 3/4] arm64: dts: qcom: sc7280: Fixup the cpufreq node
2021-08-31 17:04 0% ` Bjorn Andersson
@ 2021-09-06 3:20 6% ` Sibi Sankar
2021-09-07 19:14 6% ` Doug Anderson
0 siblings, 1 reply; 200+ results
From: Sibi Sankar @ 2021-09-06 3:20 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Matthias Kaehlcke, sboyd, robh+dt, viresh.kumar, agross, rjw,
linux-arm-msm, devicetree, linux-kernel, linux-pm, dianders,
tdas
On 2021-08-31 22:34, Bjorn Andersson wrote:
> On Tue 31 Aug 08:30 PDT 2021, Matthias Kaehlcke wrote:
>
>> On Thu, Jul 29, 2021 at 11:34:44PM +0530, Sibi Sankar wrote:
>> > Fixup the register regions used by the cpufreq node on SC7280 SoC to
>> > support per core L3 DCVS.
>> >
>> > Fixes: 7dbd121a2c58 ("arm64: dts: qcom: sc7280: Add cpufreq hw node")
>> > Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
>>
>> This patch landed in the Bjorn's tree, however the corresponding
>> driver
>> change ("cpufreq: qcom: Re-arrange register offsets to support per
>> core
>> L3 DCVS" /
>> https://patchwork.kernel.org/project/linux-arm-msm/patch/1627581885-32165-3-git-send-email-sibis@codeaurora.org/)
>> did not land in any maintainer tree yet AFAIK. IIUC the DT change
>> alone
>> breaks cpufreq since the changed register regions require the changed
>> offset in the cpufreq driver.
>>
>
> Thanks for the note Matthias, it must have slipped by as I scraped the
> inbox for things that looked ready.
>
> I'm actually not in favor of splitting these memory blocks in DT to
> facilitate the Linux implementation of splitting that in multiple
> drivers...
>
> But I've not been following up on that discussion.
>
> Regards,
> Bjorn
>
>> Sibi, please confirm or clarify that my concern is unwarranted.
Let's drop the patch asap as it breaks
SC7280 cpufreq on lnext without the driver
changes.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply [relevance 6%]
* Re: [PATCH 3/4] arm64: dts: qcom: sc7280: Fixup the cpufreq node
2021-08-31 15:30 6% ` Matthias Kaehlcke
@ 2021-08-31 17:04 0% ` Bjorn Andersson
2021-09-06 3:20 6% ` Sibi Sankar
0 siblings, 1 reply; 200+ results
From: Bjorn Andersson @ 2021-08-31 17:04 UTC (permalink / raw)
To: Matthias Kaehlcke
Cc: Sibi Sankar, sboyd, robh+dt, viresh.kumar, agross, rjw,
linux-arm-msm, devicetree, linux-kernel, linux-pm, dianders,
tdas
On Tue 31 Aug 08:30 PDT 2021, Matthias Kaehlcke wrote:
> On Thu, Jul 29, 2021 at 11:34:44PM +0530, Sibi Sankar wrote:
> > Fixup the register regions used by the cpufreq node on SC7280 SoC to
> > support per core L3 DCVS.
> >
> > Fixes: 7dbd121a2c58 ("arm64: dts: qcom: sc7280: Add cpufreq hw node")
> > Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
>
> This patch landed in the Bjorn's tree, however the corresponding driver
> change ("cpufreq: qcom: Re-arrange register offsets to support per core
> L3 DCVS" / https://patchwork.kernel.org/project/linux-arm-msm/patch/1627581885-32165-3-git-send-email-sibis@codeaurora.org/)
> did not land in any maintainer tree yet AFAIK. IIUC the DT change alone
> breaks cpufreq since the changed register regions require the changed
> offset in the cpufreq driver.
>
Thanks for the note Matthias, it must have slipped by as I scraped the
inbox for things that looked ready.
I'm actually not in favor of splitting these memory blocks in DT to
facilitate the Linux implementation of splitting that in multiple
drivers...
But I've not been following up on that discussion.
Regards,
Bjorn
> Sibi, please confirm or clarify that my concern is unwarranted.
^ permalink raw reply [relevance 0%]
* Re: [PATCH 3/4] arm64: dts: qcom: sc7280: Fixup the cpufreq node
2021-07-29 18:04 19% ` [PATCH 3/4] arm64: dts: qcom: sc7280: Fixup the cpufreq node Sibi Sankar
2021-08-04 18:57 0% ` Stephen Boyd
@ 2021-08-31 15:30 6% ` Matthias Kaehlcke
2021-08-31 17:04 0% ` Bjorn Andersson
1 sibling, 1 reply; 200+ results
From: Matthias Kaehlcke @ 2021-08-31 15:30 UTC (permalink / raw)
To: Sibi Sankar
Cc: sboyd, bjorn.andersson, robh+dt, viresh.kumar, agross, rjw,
linux-arm-msm, devicetree, linux-kernel, linux-pm, dianders,
tdas
On Thu, Jul 29, 2021 at 11:34:44PM +0530, Sibi Sankar wrote:
> Fixup the register regions used by the cpufreq node on SC7280 SoC to
> support per core L3 DCVS.
>
> Fixes: 7dbd121a2c58 ("arm64: dts: qcom: sc7280: Add cpufreq hw node")
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
This patch landed in the Bjorn's tree, however the corresponding driver
change ("cpufreq: qcom: Re-arrange register offsets to support per core
L3 DCVS" / https://patchwork.kernel.org/project/linux-arm-msm/patch/1627581885-32165-3-git-send-email-sibis@codeaurora.org/)
did not land in any maintainer tree yet AFAIK. IIUC the DT change alone
breaks cpufreq since the changed register regions require the changed
offset in the cpufreq driver.
Sibi, please confirm or clarify that my concern is unwarranted.
^ permalink raw reply [relevance 6%]
* Re: [PATCH 4/4] arm64: dts: qcom: sm8350: Fixup the cpufreq node
@ 2021-08-30 6:47 6% ` Sibi Sankar
0 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-08-30 6:47 UTC (permalink / raw)
To: Matthias Kaehlcke, Bjorn Andersson
Cc: sboyd, robh+dt, viresh.kumar, agross, rjw, linux-arm-msm,
devicetree, linux-kernel, linux-pm, dianders, tdas
On 2021-08-05 05:28, Matthias Kaehlcke wrote:
> On Wed, Aug 04, 2021 at 05:59:04PM -0500, Bjorn Andersson wrote:
>> On Thu 29 Jul 13:04 CDT 2021, Sibi Sankar wrote:
>>
>> > Fixup the register regions used by the cpufreq node on SM8350 SoC to
>> > support per core L3 DCVS.
>> >
>>
>> That sounds good, but why are you dropping the platform-specific
>> compatible?
>>
>
> I also stared at this and the patch that changes the code for a while.
>
> My understanding is that removing the platform-specific compatible is
> part
> of not breaking 'old' DTBs. Old DTBs for SM8350 contain the larger
> register
> regions and must be paired with 'epss_sm8250_soc_data' (driver code)
> which
> has the 'old' 'reg_perf_state' offset. New SM8350 DTs only have the
> 'qcom,cpufreq-epss' compatible, which pairs their smaller register
> regions
> with 'epss_soc_data' with the new 'reg_perf_state' offset.
>
> It is super-confusing that the platform-specific compatible string is
> missing. The binding should probably mention that the two
> platform-specific compatible strings are for backwards compatibility
> only and should not be added to new or existing DT files that don't
> have them already. Maybe a 'qcom,sm8350-cpufreq-epss-v2' or similar
> should be added to avoid/reduce possible confusion and have to option
> to add SM8350 specific code later.
Bjorn,
https://patchwork.kernel.org/project/linux-arm-msm/cover/1629458622-4915-1-git-send-email-okukatla@codeaurora.org/
This series affects the design of the l3
provider support for sc7280 which will be
in a position to land in ~1-2 respins. So,
please share an early ACK or NACK regarding
the register re-ordering series so that we
can plan to get alternate acceptable versions
out faster on the list.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply [relevance 6%]
* Re: [PATCH v5 04/13] remoteproc: qcom: q6v5: Use qmp_send to update co-processor load state
2021-08-19 3:02 9% ` [PATCH v5 04/13] remoteproc: qcom: q6v5: Use qmp_send to update co-processor load state Sibi Sankar
@ 2021-08-23 20:17 0% ` Stephen Boyd
0 siblings, 0 replies; 200+ results
From: Stephen Boyd @ 2021-08-23 20:17 UTC (permalink / raw)
To: Sibi Sankar, bjorn.andersson, mka, robh+dt
Cc: ulf.hansson, rjw, agross, ohad, mathieu.poirier, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel, dianders, rishabhb,
sidgup
Quoting Sibi Sankar (2021-08-18 20:02:07)
> The power domains exposed by the AOSS QMP driver control the load state
> resources linked to modem, adsp, cdsp remoteprocs. These are used to
> notify the Always on Subsystem (AOSS) that a particular co-processor is
> up/down. AOSS uses this information to wait for the co-processors to
> suspend before starting its sleep sequence.
>
> These co-processors enter low-power modes independent to that of the
> application processor and the load state resources linked to them are
> expected to remain unaltered across system suspend/resume cycles. To
> achieve this behavior lets stop using the power-domains exposed by the
> AOSS QMP node and replace them with generic qmp_send interface instead.
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
^ permalink raw reply [relevance 0%]
* Re: [PATCH v3 01/10] dt-bindings: remoteproc: qcom: pas: Add SC7280 MPSS support
2021-08-19 3:36 18% ` [PATCH v3 01/10] dt-bindings: remoteproc: qcom: pas: Add SC7280 MPSS support Sibi Sankar
@ 2021-08-23 20:14 0% ` Stephen Boyd
0 siblings, 0 replies; 200+ results
From: Stephen Boyd @ 2021-08-23 20:14 UTC (permalink / raw)
To: Sibi Sankar, bjorn.andersson, mka, robh+dt, saiprakash.ranjan, will
Cc: ohad, agross, mathieu.poirier, robin.murphy, joro, p.zabel,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
linux-arm-kernel, evgreen, dianders
Quoting Sibi Sankar (2021-08-18 20:36:16)
> Add MPSS PAS support for SC7280 SoCs.
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
^ permalink raw reply [relevance 0%]
* Re: [PATCH v3 02/10] remoteproc: qcom: pas: Add SC7280 Modem support
2021-08-19 3:36 19% ` [PATCH v3 02/10] remoteproc: qcom: pas: Add SC7280 Modem support Sibi Sankar
@ 2021-08-23 20:14 0% ` Stephen Boyd
0 siblings, 0 replies; 200+ results
From: Stephen Boyd @ 2021-08-23 20:14 UTC (permalink / raw)
To: Sibi Sankar, bjorn.andersson, mka, robh+dt, saiprakash.ranjan, will
Cc: ohad, agross, mathieu.poirier, robin.murphy, joro, p.zabel,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
linux-arm-kernel, evgreen, dianders
Quoting Sibi Sankar (2021-08-18 20:36:17)
> Add support for booting the Modem DSP found on QTI SC7280 SoCs.
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
> ---
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
^ permalink raw reply [relevance 0%]
* Re: [PATCH v3 03/10] dt-bindings: remoteproc: qcom: Update Q6V5 Modem PIL binding
2021-08-19 3:36 14% ` [PATCH v3 03/10] dt-bindings: remoteproc: qcom: Update Q6V5 Modem PIL binding Sibi Sankar
@ 2021-08-23 20:14 0% ` Stephen Boyd
0 siblings, 0 replies; 200+ results
From: Stephen Boyd @ 2021-08-23 20:14 UTC (permalink / raw)
To: Sibi Sankar, bjorn.andersson, mka, robh+dt, saiprakash.ranjan, will
Cc: ohad, agross, mathieu.poirier, robin.murphy, joro, p.zabel,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
linux-arm-kernel, evgreen, dianders
Quoting Sibi Sankar (2021-08-18 20:36:18)
> Add a new modem compatible string for QTI SC7280 SoCs and introduce the
> "qcom,ext-regs" and "qcom,qaccept-regs" properties needed by the modem
> sub-system running on SC7280 SoCs.
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
^ permalink raw reply [relevance 0%]
* Re: [PATCH v3 08/10] arm64: dts: qcom: sc7280: Add nodes to boot modem
2021-08-19 3:36 18% ` [PATCH v3 08/10] arm64: dts: qcom: sc7280: Add nodes to boot modem Sibi Sankar
@ 2021-08-23 20:12 0% ` Stephen Boyd
0 siblings, 0 replies; 200+ results
From: Stephen Boyd @ 2021-08-23 20:12 UTC (permalink / raw)
To: Sibi Sankar, bjorn.andersson, mka, robh+dt, saiprakash.ranjan, will
Cc: ohad, agross, mathieu.poirier, robin.murphy, joro, p.zabel,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
linux-arm-kernel, evgreen, dianders
Quoting Sibi Sankar (2021-08-18 20:36:23)
> Add miscellaneous nodes to boot the modem and support post-mortem debug
> on SC7280 SoCs.
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
^ permalink raw reply [relevance 0%]
* Re: [PATCH v3 10/10] arm64: dts: qcom: sc7280: Update Q6V5 MSS node
2021-08-19 3:36 17% ` [PATCH v3 10/10] arm64: dts: qcom: sc7280: Update " Sibi Sankar
@ 2021-08-23 20:12 0% ` Stephen Boyd
0 siblings, 0 replies; 200+ results
From: Stephen Boyd @ 2021-08-23 20:12 UTC (permalink / raw)
To: Sibi Sankar, bjorn.andersson, mka, robh+dt, saiprakash.ranjan, will
Cc: ohad, agross, mathieu.poirier, robin.murphy, joro, p.zabel,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
linux-arm-kernel, evgreen, dianders
Quoting Sibi Sankar (2021-08-18 20:36:25)
> Update MSS node to support MSA based modem boot on SC7280 SoCs.
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
>
> v3:
> * Place remoteproc_mpss node in alphabetical order above pinctrl
> section. [Stephen]
>
> arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 7 +++++++
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 19 ++++++++++++++++---
> 2 files changed, 23 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
> index 103d89c1e1c7..f1c8641b0c26 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
> @@ -263,6 +263,13 @@
> status = "okay";
> };
>
> +&remoteproc_mpss {
> + status = "okay";
> + compatible = "qcom,sc7280-mss-pil";
> + iommus = <&apps_smmu 0x124 0x0>, <&apps_smmu 0x488 0x7>;
> + memory-region = <&mba_mem &mpss_mem>;
Nitpick:
memory-region = <&mba_mem>, <&mpss_mem>;
would be better as it indicates that &mpss_mem isn't being parsed when
&mba_mem is being parsed, i.e. they're independent phandles.
> +};
> +
> &sdhc_1 {
> status = "okay";
>
^ permalink raw reply [relevance 0%]
* Re: [PATCH v5 02/13] dt-bindings: remoteproc: qcom: pas: Add QMP property
@ 2021-08-23 16:19 6% ` Sibi Sankar
0 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-08-23 16:19 UTC (permalink / raw)
To: Stephen Boyd
Cc: bjorn.andersson, mka, robh+dt, ulf.hansson, rjw, agross, ohad,
mathieu.poirier, linux-arm-msm, linux-remoteproc, devicetree,
linux-kernel, dianders, rishabhb, sidgup
On 2021-08-21 23:47, Stephen Boyd wrote:
> Quoting Sibi Sankar (2021-08-20 07:24:02)
>> On 2021-08-20 00:25, Stephen Boyd wrote:
>> > Quoting Sibi Sankar (2021-08-18 20:02:05)
>> >> The load state power-domain, used by the co-processors to notify the
>> >> Always on Subsystem (AOSS) that a particular co-processor is up/down,
>> >> suffers from the side-effect of changing states during suspend/resume.
>> >> However the co-processors enter low-power modes independent to that of
>> >> the application processor and their states are expected to remain
>> >> unaltered across system suspend/resume cycles. To achieve this
>> >> behavior
>> >> let's drop the load state power-domain and replace them with the qmp
>> >> property for all SoCs supporting low power mode signalling.
>> >>
>> >
>> > How do we drop the load state property without breaking existing DTBs?
>> > Maybe we need to leave it there and then somehow make it optional? Or
>> > do
>> > we not care about this problem as the driver will start ignoring it?
>>
>> We can afford to break the bindings
>> because of the following reason:
>>
>> * Load state in mainline is currently
>> broken i.e. it doesn't serve its
>> main purpose of signalling AOP of
>> the correct state of Q6 during
>> system suspend/resume. Thus we
>> can maintain current functionality
>> even without the load state votes
>> i.e. when a new kernel with load
>> state removed is used with an older
>> dtb the remoteproc functionality
>> will remain the same.
>>
>
> Alright. Is that reflected somewhere in the commit text? I must have
> missed it. Can you please add it?
Commit message throughout the series
mention that the current load state
implementation is broken but it is
never mentioned explicitly that it
is the reason why bindings can be
broken. I'll wait for a couple of
days to see if I get any more
comments and will re-word it in the
next re-spin.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply [relevance 6%]
* Re: [PATCH v5 02/13] dt-bindings: remoteproc: qcom: pas: Add QMP property
@ 2021-08-20 14:24 6% ` Sibi Sankar
0 siblings, 1 reply; 200+ results
From: Sibi Sankar @ 2021-08-20 14:24 UTC (permalink / raw)
To: Stephen Boyd
Cc: bjorn.andersson, mka, robh+dt, ulf.hansson, rjw, agross, ohad,
mathieu.poirier, linux-arm-msm, linux-remoteproc, devicetree,
linux-kernel, dianders, rishabhb, sidgup
On 2021-08-20 00:25, Stephen Boyd wrote:
> Quoting Sibi Sankar (2021-08-18 20:02:05)
>> The load state power-domain, used by the co-processors to notify the
>> Always on Subsystem (AOSS) that a particular co-processor is up/down,
>> suffers from the side-effect of changing states during suspend/resume.
>> However the co-processors enter low-power modes independent to that of
>> the application processor and their states are expected to remain
>> unaltered across system suspend/resume cycles. To achieve this
>> behavior
>> let's drop the load state power-domain and replace them with the qmp
>> property for all SoCs supporting low power mode signalling.
>>
>
> How do we drop the load state property without breaking existing DTBs?
> Maybe we need to leave it there and then somehow make it optional? Or
> do
> we not care about this problem as the driver will start ignoring it?
We can afford to break the bindings
because of the following reason:
* Load state in mainline is currently
broken i.e. it doesn't serve its
main purpose of signalling AOP of
the correct state of Q6 during
system suspend/resume. Thus we
can maintain current functionality
even without the load state votes
i.e. when a new kernel with load
state removed is used with an older
dtb the remoteproc functionality
will remain the same.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply [relevance 6%]
* Re: [PATCH v3 06/10] arm64: dts: qcom: sc7280: Update reserved memory map
@ 2021-08-20 14:09 6% ` Sibi Sankar
0 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-08-20 14:09 UTC (permalink / raw)
To: Vinod Koul
Cc: bjorn.andersson, robh+dt, will, saiprakash.ranjan, swboyd, mka,
ohad, agross, mathieu.poirier, robin.murphy, joro, p.zabel,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
linux-arm-kernel, evgreen, dianders
On 2021-08-19 10:07, Vinod Koul wrote:
> Hi Sibi,
>
> On 19-08-21, 09:06, Sibi Sankar wrote:
>
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> index 5e4f4f3b738a..894106efadfe 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> @@ -48,6 +48,16 @@
>> #size-cells = <2>;
>> ranges;
>>
>> + hyp_mem: memory@80000000 {
>> + reg = <0x0 0x80000000 0x0 0x600000>;
>> + no-map;
>
> This should conflict with the memory defined in this file:
>
> memory@80000000 {
> device_type = "memory";
> /* We expect the bootloader to fill in the size */
> reg = <0 0x80000000 0 0>;
> };
>
> I think this should be updated?
Vinod,
I prefer we leave ^^ node untouched.
For platforms using hyp_mem, the
regions defined in the memory map
are valid and for the other platforms
not using hyp_mem we would just delete
them in the board files anyway.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply [relevance 6%]
* [PATCH v3 10/10] arm64: dts: qcom: sc7280: Update Q6V5 MSS node
2021-08-19 3:36 18% [PATCH v3 00/10] Add Modem support on SC7280 SoCs Sibi Sankar
` (8 preceding siblings ...)
2021-08-19 3:36 18% ` [PATCH v3 09/10] arm64: dts: qcom: sc7280: Add Q6V5 MSS node Sibi Sankar
@ 2021-08-19 3:36 17% ` Sibi Sankar
2021-08-23 20:12 0% ` Stephen Boyd
9 siblings, 1 reply; 200+ results
From: Sibi Sankar @ 2021-08-19 3:36 UTC (permalink / raw)
To: bjorn.andersson, robh+dt, will, saiprakash.ranjan, swboyd, mka
Cc: ohad, agross, mathieu.poirier, robin.murphy, joro, p.zabel,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
linux-arm-kernel, evgreen, dianders, Sibi Sankar
Update MSS node to support MSA based modem boot on SC7280 SoCs.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
v3:
* Place remoteproc_mpss node in alphabetical order above pinctrl
section. [Stephen]
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 7 +++++++
arch/arm64/boot/dts/qcom/sc7280.dtsi | 19 ++++++++++++++++---
2 files changed, 23 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
index 103d89c1e1c7..f1c8641b0c26 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
@@ -263,6 +263,13 @@
status = "okay";
};
+&remoteproc_mpss {
+ status = "okay";
+ compatible = "qcom,sc7280-mss-pil";
+ iommus = <&apps_smmu 0x124 0x0>, <&apps_smmu 0x488 0x7>;
+ memory-region = <&mba_mem &mpss_mem>;
+};
+
&sdhc_1 {
status = "okay";
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 93ae3ee8c5a6..7ad0cbe1a0a2 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -701,7 +701,8 @@
remoteproc_mpss: remoteproc@4080000 {
compatible = "qcom,sc7280-mpss-pas";
- reg = <0 0x04080000 0 0x10000>;
+ reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>;
+ reg-names = "qdsp6", "rmb";
interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
@@ -712,8 +713,11 @@
interrupt-names = "wdog", "fatal", "ready", "handover",
"stop-ack", "shutdown-ack";
- clocks = <&rpmhcc RPMH_CXO_CLK>;
- clock-names = "xo";
+ clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
+ <&gcc GCC_MSS_OFFLINE_AXI_CLK>,
+ <&gcc GCC_MSS_SNOC_AXI_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "offline", "snoc_axi", "xo";
power-domains = <&rpmhpd SC7280_CX>,
<&rpmhpd SC7280_MSS>;
@@ -726,6 +730,15 @@
qcom,smem-states = <&modem_smp2p_out 0>;
qcom,smem-state-names = "stop";
+ resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
+ <&pdc_reset PDC_MODEM_SYNC_RESET>;
+ reset-names = "mss_restart", "pdc_reset";
+
+ qcom,halt-regs = <&tcsr_mutex 0x23000 0x25000 0x28000 0x33000>;
+ qcom,ext-regs = <&tcsr_regs 0x10000 0x10004
+ &tcsr_mutex 0x26004 0x26008>;
+ qcom,qaccept-regs = <&tcsr_mutex 0x23030 0x23040 0x23020>;
+
status = "disabled";
glink-edge {
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 17%]
* [PATCH v3 09/10] arm64: dts: qcom: sc7280: Add Q6V5 MSS node
2021-08-19 3:36 18% [PATCH v3 00/10] Add Modem support on SC7280 SoCs Sibi Sankar
` (7 preceding siblings ...)
2021-08-19 3:36 18% ` [PATCH v3 08/10] arm64: dts: qcom: sc7280: Add nodes to boot modem Sibi Sankar
@ 2021-08-19 3:36 18% ` Sibi Sankar
2021-08-19 3:36 17% ` [PATCH v3 10/10] arm64: dts: qcom: sc7280: Update " Sibi Sankar
9 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-08-19 3:36 UTC (permalink / raw)
To: bjorn.andersson, robh+dt, will, saiprakash.ranjan, swboyd, mka
Cc: ohad, agross, mathieu.poirier, robin.murphy, joro, p.zabel,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
linux-arm-kernel, evgreen, dianders, Sibi Sankar
This patch adds Q6V5 MSS PAS remoteproc node for SC7280 SoCs.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 40 ++++++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index bd1ac93017ae..93ae3ee8c5a6 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -699,6 +699,46 @@
#power-domain-cells = <1>;
};
+ remoteproc_mpss: remoteproc@4080000 {
+ compatible = "qcom,sc7280-mpss-pas";
+ reg = <0 0x04080000 0 0x10000>;
+
+ interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog", "fatal", "ready", "handover",
+ "stop-ack", "shutdown-ack";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ power-domains = <&rpmhpd SC7280_CX>,
+ <&rpmhpd SC7280_MSS>;
+ power-domain-names = "cx", "mss";
+
+ memory-region = <&mpss_mem>;
+
+ qcom,qmp = <&aoss_qmp>;
+
+ qcom,smem-states = <&modem_smp2p_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_MPSS
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+ label = "modem";
+ qcom,remote-pid = <1>;
+ };
+ };
+
stm@6002000 {
compatible = "arm,coresight-stm", "arm,primecell";
reg = <0 0x06002000 0 0x1000>,
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 18%]
* [PATCH v3 08/10] arm64: dts: qcom: sc7280: Add nodes to boot modem
2021-08-19 3:36 18% [PATCH v3 00/10] Add Modem support on SC7280 SoCs Sibi Sankar
` (6 preceding siblings ...)
2021-08-19 3:36 18% ` [PATCH v3 07/10] arm64: dts: qcom: sc7280: Add/Delete/Update reserved memory nodes Sibi Sankar
@ 2021-08-19 3:36 18% ` Sibi Sankar
2021-08-23 20:12 0% ` Stephen Boyd
2021-08-19 3:36 18% ` [PATCH v3 09/10] arm64: dts: qcom: sc7280: Add Q6V5 MSS node Sibi Sankar
2021-08-19 3:36 17% ` [PATCH v3 10/10] arm64: dts: qcom: sc7280: Update " Sibi Sankar
9 siblings, 1 reply; 200+ results
From: Sibi Sankar @ 2021-08-19 3:36 UTC (permalink / raw)
To: bjorn.andersson, robh+dt, will, saiprakash.ranjan, swboyd, mka
Cc: ohad, agross, mathieu.poirier, robin.murphy, joro, p.zabel,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
linux-arm-kernel, evgreen, dianders, Sibi Sankar
Add miscellaneous nodes to boot the modem and support post-mortem debug
on SC7280 SoCs.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
v3:
* Rename tcsr node and add qualifying compatibles to tcsr and imem
nodes. [Bjorn]
arch/arm64/boot/dts/qcom/sc7280.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 894106efadfe..bd1ac93017ae 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -662,6 +662,11 @@
#hwlock-cells = <1>;
};
+ tcsr: syscon@1fc0000 {
+ compatible = "qcom,sc7280-tcsr", "syscon";
+ reg = <0 0x01fc0000 0 0x30000>;
+ };
+
lpasscc: lpasscc@3000000 {
compatible = "qcom,sc7280-lpasscc";
reg = <0 0x03000000 0 0x40>,
@@ -1632,6 +1637,21 @@
};
};
+ imem@146a5000 {
+ compatible = "qcom,sc7280-imem", "syscon";
+ reg = <0 0x146a5000 0 0x6000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ranges = <0 0 0x146a5000 0x6000>;
+
+ pil-reloc@594c {
+ compatible = "qcom,pil-reloc-info";
+ reg = <0x594c 0xc8>;
+ };
+ };
+
apps_smmu: iommu@15000000 {
compatible = "qcom,sc7280-smmu-500", "arm,mmu-500";
reg = <0 0x15000000 0 0x100000>;
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 18%]
* [PATCH v3 07/10] arm64: dts: qcom: sc7280: Add/Delete/Update reserved memory nodes
2021-08-19 3:36 18% [PATCH v3 00/10] Add Modem support on SC7280 SoCs Sibi Sankar
` (5 preceding siblings ...)
2021-08-19 3:36 18% ` [PATCH v3 06/10] arm64: dts: qcom: sc7280: Update reserved memory map Sibi Sankar
@ 2021-08-19 3:36 18% ` Sibi Sankar
2021-08-19 3:36 18% ` [PATCH v3 08/10] arm64: dts: qcom: sc7280: Add nodes to boot modem Sibi Sankar
` (2 subsequent siblings)
9 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-08-19 3:36 UTC (permalink / raw)
To: bjorn.andersson, robh+dt, will, saiprakash.ranjan, swboyd, mka
Cc: ohad, agross, mathieu.poirier, robin.murphy, joro, p.zabel,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
linux-arm-kernel, evgreen, dianders, Sibi Sankar
Add, delete and update platform specific reserved memory nodes.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 52 ++++++++++++++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
index 371a2a9dcf7a..103d89c1e1c7 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
@@ -12,6 +12,58 @@
#include "pm8350c.dtsi"
#include "pmk8350.dtsi"
+/*
+ * Reserved memory changes
+ *
+ * Delete all unused memory nodes and define the peripheral memory regions
+ * required by the board dts.
+ *
+ */
+
+/delete-node/ &hyp_mem;
+/delete-node/ &xbl_mem;
+/delete-node/ &reserved_xbl_uefi_log;
+/delete-node/ &sec_apps_mem;
+
+/* Increase the size from 2.5MB to 8MB */
+&rmtfs_mem {
+ reg = <0x0 0x9c900000 0x0 0x800000>;
+};
+
+/ {
+ reserved-memory {
+ adsp_mem: memory@86700000 {
+ reg = <0x0 0x86700000 0x0 0x2800000>;
+ no-map;
+ };
+
+ camera_mem: memory@8ad00000 {
+ reg = <0x0 0x8ad00000 0x0 0x500000>;
+ no-map;
+ };
+
+ venus_mem: memory@8b200000 {
+ reg = <0x0 0x8b200000 0x0 0x500000>;
+ no-map;
+ };
+
+ mpss_mem: memory@8b800000 {
+ reg = <0x0 0x8b800000 0x0 0xf600000>;
+ no-map;
+ };
+
+ wpss_mem: memory@9ae00000 {
+ reg = <0x0 0x9ae00000 0x0 0x1900000>;
+ no-map;
+ };
+
+ mba_mem: memory@9c700000 {
+ reg = <0x0 0x9c700000 0x0 0x200000>;
+ no-map;
+ };
+ };
+};
+
&apps_rsc {
pm7325-regulators {
compatible = "qcom,pm7325-rpmh-regulators";
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 18%]
* [PATCH v3 06/10] arm64: dts: qcom: sc7280: Update reserved memory map
2021-08-19 3:36 18% [PATCH v3 00/10] Add Modem support on SC7280 SoCs Sibi Sankar
` (4 preceding siblings ...)
2021-08-19 3:36 11% ` [PATCH v3 05/10] remoteproc: mss: q6v5-mss: Add modem support on SC7280 Sibi Sankar
@ 2021-08-19 3:36 18% ` Sibi Sankar
2021-08-19 3:36 18% ` [PATCH v3 07/10] arm64: dts: qcom: sc7280: Add/Delete/Update reserved memory nodes Sibi Sankar
` (3 subsequent siblings)
9 siblings, 1 reply; 200+ results
From: Sibi Sankar @ 2021-08-19 3:36 UTC (permalink / raw)
To: bjorn.andersson, robh+dt, will, saiprakash.ranjan, swboyd, mka
Cc: ohad, agross, mathieu.poirier, robin.murphy, joro, p.zabel,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
linux-arm-kernel, evgreen, dianders, Sibi Sankar
Add missing reserved regions as described in v1 of SC7280 memory map.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
v3:
* Keep the memory map version in commit message. [Bjorn]
arch/arm64/boot/dts/qcom/sc7280.dtsi | 34 ++++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 5e4f4f3b738a..894106efadfe 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -48,6 +48,16 @@
#size-cells = <2>;
ranges;
+ hyp_mem: memory@80000000 {
+ reg = <0x0 0x80000000 0x0 0x600000>;
+ no-map;
+ };
+
+ xbl_mem: memory@80600000 {
+ reg = <0x0 0x80600000 0x0 0x200000>;
+ no-map;
+ };
+
aop_mem: memory@80800000 {
reg = <0x0 0x80800000 0x0 0x60000>;
no-map;
@@ -59,6 +69,16 @@
no-map;
};
+ reserved_xbl_uefi_log: memory@80880000 {
+ reg = <0x0 0x80884000 0x0 0x10000>;
+ no-map;
+ };
+
+ sec_apps_mem: memory@808ff000 {
+ reg = <0x0 0x808ff000 0x0 0x1000>;
+ no-map;
+ };
+
smem_mem: memory@80900000 {
reg = <0x0 0x80900000 0x0 0x200000>;
no-map;
@@ -69,10 +89,24 @@
reg = <0x0 0x80b00000 0x0 0x100000>;
};
+ wlan_fw_mem: memory@80c00000 {
+ reg = <0x0 0x80c00000 0x0 0xc00000>;
+ no-map;
+ };
+
ipa_fw_mem: memory@8b700000 {
reg = <0 0x8b700000 0 0x10000>;
no-map;
};
+
+ rmtfs_mem: memory@9c900000 {
+ compatible = "qcom,rmtfs-mem";
+ reg = <0x0 0x9c900000 0x0 0x280000>;
+ no-map;
+
+ qcom,client-id = <1>;
+ qcom,vmid = <15>;
+ };
};
cpus {
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 18%]
* [PATCH v3 05/10] remoteproc: mss: q6v5-mss: Add modem support on SC7280
2021-08-19 3:36 18% [PATCH v3 00/10] Add Modem support on SC7280 SoCs Sibi Sankar
` (3 preceding siblings ...)
2021-08-19 3:36 19% ` [PATCH v3 04/10] iommu/arm-smmu-qcom: Request direct mapping for modem device Sibi Sankar
@ 2021-08-19 3:36 11% ` Sibi Sankar
2021-08-19 3:36 18% ` [PATCH v3 06/10] arm64: dts: qcom: sc7280: Update reserved memory map Sibi Sankar
` (4 subsequent siblings)
9 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-08-19 3:36 UTC (permalink / raw)
To: bjorn.andersson, robh+dt, will, saiprakash.ranjan, swboyd, mka
Cc: ohad, agross, mathieu.poirier, robin.murphy, joro, p.zabel,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
linux-arm-kernel, evgreen, dianders, Sibi Sankar
Add out of reset sequence support for modem sub-system on SC7280 SoCs.
It requires access to an additional set of qaccept registers, external
power/clk control registers and halt vq6 register to put the modem back
into reset.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
drivers/remoteproc/qcom_q6v5_mss.c | 252 ++++++++++++++++++++++++++++++++++++-
1 file changed, 248 insertions(+), 4 deletions(-)
diff --git a/drivers/remoteproc/qcom_q6v5_mss.c b/drivers/remoteproc/qcom_q6v5_mss.c
index 7a1422bd7925..90ff712f912c 100644
--- a/drivers/remoteproc/qcom_q6v5_mss.c
+++ b/drivers/remoteproc/qcom_q6v5_mss.c
@@ -77,6 +77,14 @@
#define HALT_ACK_TIMEOUT_US 100000
+/* QACCEPT Register Offsets */
+#define QACCEPT_ACCEPT_REG 0x0
+#define QACCEPT_ACTIVE_REG 0x4
+#define QACCEPT_DENY_REG 0x8
+#define QACCEPT_REQ_REG 0xC
+
+#define QACCEPT_TIMEOUT_US 50
+
/* QDSP6SS_RESET */
#define Q6SS_STOP_CORE BIT(0)
#define Q6SS_CORE_ARES BIT(1)
@@ -143,6 +151,9 @@ struct rproc_hexagon_res {
bool has_alt_reset;
bool has_mba_logs;
bool has_spare_reg;
+ bool has_qaccept_regs;
+ bool has_ext_cntl_regs;
+ bool has_vq6;
};
struct q6v5 {
@@ -158,8 +169,18 @@ struct q6v5 {
u32 halt_q6;
u32 halt_modem;
u32 halt_nc;
+ u32 halt_vq6;
u32 conn_box;
+ u32 qaccept_mdm;
+ u32 qaccept_cx;
+ u32 qaccept_axi;
+
+ u32 axim1_clk_off;
+ u32 crypto_clk_off;
+ u32 force_clk_on;
+ u32 rscc_disable;
+
struct reset_control *mss_restart;
struct reset_control *pdc_reset;
@@ -201,6 +222,9 @@ struct q6v5 {
bool has_alt_reset;
bool has_mba_logs;
bool has_spare_reg;
+ bool has_qaccept_regs;
+ bool has_ext_cntl_regs;
+ bool has_vq6;
int mpss_perm;
int mba_perm;
const char *hexagon_mdt_image;
@@ -213,6 +237,7 @@ enum {
MSS_MSM8996,
MSS_MSM8998,
MSS_SC7180,
+ MSS_SC7280,
MSS_SDM845,
};
@@ -473,6 +498,12 @@ static int q6v5_reset_assert(struct q6v5 *qproc)
regmap_update_bits(qproc->conn_map, qproc->conn_box,
AXI_GATING_VALID_OVERRIDE, 0);
ret = reset_control_deassert(qproc->mss_restart);
+ } else if (qproc->has_ext_cntl_regs) {
+ regmap_write(qproc->conn_map, qproc->rscc_disable, 0);
+ reset_control_assert(qproc->pdc_reset);
+ reset_control_assert(qproc->mss_restart);
+ reset_control_deassert(qproc->pdc_reset);
+ ret = reset_control_deassert(qproc->mss_restart);
} else {
ret = reset_control_assert(qproc->mss_restart);
}
@@ -490,7 +521,7 @@ static int q6v5_reset_deassert(struct q6v5 *qproc)
ret = reset_control_reset(qproc->mss_restart);
writel(0, qproc->rmb_base + RMB_MBA_ALT_RESET);
reset_control_deassert(qproc->pdc_reset);
- } else if (qproc->has_spare_reg) {
+ } else if (qproc->has_spare_reg || qproc->has_ext_cntl_regs) {
ret = reset_control_reset(qproc->mss_restart);
} else {
ret = reset_control_deassert(qproc->mss_restart);
@@ -604,7 +635,7 @@ static int q6v5proc_reset(struct q6v5 *qproc)
}
goto pbl_wait;
- } else if (qproc->version == MSS_SC7180) {
+ } else if (qproc->version == MSS_SC7180 || qproc->version == MSS_SC7280) {
val = readl(qproc->reg_base + QDSP6SS_SLEEP);
val |= Q6SS_CBCR_CLKEN;
writel(val, qproc->reg_base + QDSP6SS_SLEEP);
@@ -787,6 +818,89 @@ static int q6v5proc_reset(struct q6v5 *qproc)
return ret;
}
+static int q6v5proc_enable_qchannel(struct q6v5 *qproc, struct regmap *map, u32 offset)
+{
+ unsigned int val;
+ int ret;
+
+ if (!qproc->has_qaccept_regs)
+ return 0;
+
+ if (qproc->has_ext_cntl_regs) {
+ regmap_write(qproc->conn_map, qproc->rscc_disable, 0);
+ regmap_write(qproc->conn_map, qproc->force_clk_on, 1);
+
+ ret = regmap_read_poll_timeout(qproc->halt_map, qproc->axim1_clk_off, val,
+ !val, 1, Q6SS_CBCR_TIMEOUT_US);
+ if (ret) {
+ dev_err(qproc->dev, "failed to enable axim1 clock\n");
+ return -ETIMEDOUT;
+ }
+ }
+
+ regmap_write(map, offset + QACCEPT_REQ_REG, 1);
+
+ /* Wait for accept */
+ ret = regmap_read_poll_timeout(map, offset + QACCEPT_ACCEPT_REG, val, val, 5,
+ QACCEPT_TIMEOUT_US);
+ if (ret) {
+ dev_err(qproc->dev, "qchannel enable failed\n");
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+static void q6v5proc_disable_qchannel(struct q6v5 *qproc, struct regmap *map, u32 offset)
+{
+ int ret;
+ unsigned int val, retry;
+ unsigned int nretry = 10;
+ bool takedown_complete = false;
+
+ if (!qproc->has_qaccept_regs)
+ return;
+
+ while (!takedown_complete && nretry) {
+ nretry--;
+
+ /* Wait for active transactions to complete */
+ regmap_read_poll_timeout(map, offset + QACCEPT_ACTIVE_REG, val, !val, 5,
+ QACCEPT_TIMEOUT_US);
+
+ /* Request Q-channel transaction takedown */
+ regmap_write(map, offset + QACCEPT_REQ_REG, 0);
+
+ /*
+ * If the request is denied, reset the Q-channel takedown request,
+ * wait for active transactions to complete and retry takedown.
+ */
+ retry = 10;
+ while (retry) {
+ usleep_range(5, 10);
+ retry--;
+ ret = regmap_read(map, offset + QACCEPT_DENY_REG, &val);
+ if (!ret && val) {
+ regmap_write(map, offset + QACCEPT_REQ_REG, 1);
+ break;
+ }
+
+ ret = regmap_read(map, offset + QACCEPT_ACCEPT_REG, &val);
+ if (!ret && !val) {
+ takedown_complete = true;
+ break;
+ }
+ }
+
+ if (!retry)
+ break;
+ }
+
+ /* Rely on mss_restart to clear out pending transactions on takedown failure */
+ if (!takedown_complete)
+ dev_err(qproc->dev, "qchannel takedown failed\n");
+}
+
static void q6v5proc_halt_axi_port(struct q6v5 *qproc,
struct regmap *halt_map,
u32 offset)
@@ -950,6 +1064,12 @@ static int q6v5_mba_load(struct q6v5 *qproc)
goto assert_reset;
}
+ ret = q6v5proc_enable_qchannel(qproc, qproc->halt_map, qproc->qaccept_axi);
+ if (ret) {
+ dev_err(qproc->dev, "failed to enable axi bridge\n");
+ goto disable_active_clks;
+ }
+
/*
* Some versions of the MBA firmware will upon boot wipe the MPSS region as well, so provide
* the Q6 access to this region.
@@ -996,8 +1116,13 @@ static int q6v5_mba_load(struct q6v5 *qproc)
halt_axi_ports:
q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
+ if (qproc->has_vq6)
+ q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_vq6);
q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
+ q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_mdm);
+ q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_cx);
+ q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_axi);
mba_load_err = true;
reclaim_mba:
xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true,
@@ -1047,6 +1172,8 @@ static void q6v5_mba_reclaim(struct q6v5 *qproc)
qproc->dp_size = 0;
q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
+ if (qproc->has_vq6)
+ q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_vq6);
q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
if (qproc->version == MSS_MSM8996) {
@@ -1059,6 +1186,24 @@ static void q6v5_mba_reclaim(struct q6v5 *qproc)
writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
}
+ if (qproc->has_ext_cntl_regs) {
+ regmap_write(qproc->conn_map, qproc->rscc_disable, 1);
+
+ ret = regmap_read_poll_timeout(qproc->halt_map, qproc->axim1_clk_off, val,
+ !val, 1, Q6SS_CBCR_TIMEOUT_US);
+ if (ret)
+ dev_err(qproc->dev, "failed to enable axim1 clock\n");
+
+ ret = regmap_read_poll_timeout(qproc->halt_map, qproc->crypto_clk_off, val,
+ !val, 1, Q6SS_CBCR_TIMEOUT_US);
+ if (ret)
+ dev_err(qproc->dev, "failed to enable crypto clock\n");
+ }
+
+ q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_mdm);
+ q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_cx);
+ q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_axi);
+
q6v5_reset_assert(qproc);
q6v5_clk_disable(qproc->dev, qproc->reset_clks,
@@ -1471,6 +1616,7 @@ static int q6v5_init_mem(struct q6v5 *qproc, struct platform_device *pdev)
{
struct of_phandle_args args;
struct resource *res;
+ int halt_cell_cnt = 3;
int ret;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qdsp6");
@@ -1483,8 +1629,11 @@ static int q6v5_init_mem(struct q6v5 *qproc, struct platform_device *pdev)
if (IS_ERR(qproc->rmb_base))
return PTR_ERR(qproc->rmb_base);
+ if (qproc->has_vq6)
+ halt_cell_cnt++;
+
ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
- "qcom,halt-regs", 3, 0, &args);
+ "qcom,halt-regs", halt_cell_cnt, 0, &args);
if (ret < 0) {
dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n");
return -EINVAL;
@@ -1499,6 +1648,52 @@ static int q6v5_init_mem(struct q6v5 *qproc, struct platform_device *pdev)
qproc->halt_modem = args.args[1];
qproc->halt_nc = args.args[2];
+ if (qproc->has_vq6)
+ qproc->halt_vq6 = args.args[3];
+
+ if (qproc->has_qaccept_regs) {
+ ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
+ "qcom,qaccept-regs",
+ 3, 0, &args);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "failed to parse qaccept-regs\n");
+ return -EINVAL;
+ }
+
+ qproc->qaccept_mdm = args.args[0];
+ qproc->qaccept_cx = args.args[1];
+ qproc->qaccept_axi = args.args[2];
+ }
+
+ if (qproc->has_ext_cntl_regs) {
+ ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
+ "qcom,ext-regs",
+ 2, 0, &args);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "failed to parse ext-regs index 0\n");
+ return -EINVAL;
+ }
+
+ qproc->conn_map = syscon_node_to_regmap(args.np);
+ of_node_put(args.np);
+ if (IS_ERR(qproc->conn_map))
+ return PTR_ERR(qproc->conn_map);
+
+ qproc->force_clk_on = args.args[0];
+ qproc->rscc_disable = args.args[1];
+
+ ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
+ "qcom,ext-regs",
+ 2, 1, &args);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "failed to parse ext-regs index 1\n");
+ return -EINVAL;
+ }
+
+ qproc->axim1_clk_off = args.args[0];
+ qproc->crypto_clk_off = args.args[1];
+ }
+
if (qproc->has_spare_reg) {
ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
"qcom,spare-regs",
@@ -1590,7 +1785,7 @@ static int q6v5_init_reset(struct q6v5 *qproc)
return PTR_ERR(qproc->mss_restart);
}
- if (qproc->has_alt_reset || qproc->has_spare_reg) {
+ if (qproc->has_alt_reset || qproc->has_spare_reg || qproc->has_ext_cntl_regs) {
qproc->pdc_reset = devm_reset_control_get_exclusive(qproc->dev,
"pdc_reset");
if (IS_ERR(qproc->pdc_reset)) {
@@ -1697,6 +1892,9 @@ static int q6v5_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, qproc);
+ qproc->has_qaccept_regs = desc->has_qaccept_regs;
+ qproc->has_ext_cntl_regs = desc->has_ext_cntl_regs;
+ qproc->has_vq6 = desc->has_vq6;
qproc->has_spare_reg = desc->has_spare_reg;
ret = q6v5_init_mem(qproc, pdev);
if (ret)
@@ -1857,9 +2055,39 @@ static const struct rproc_hexagon_res sc7180_mss = {
.has_alt_reset = false,
.has_mba_logs = true,
.has_spare_reg = true,
+ .has_qaccept_regs = false,
+ .has_ext_cntl_regs = false,
+ .has_vq6 = false,
.version = MSS_SC7180,
};
+static const struct rproc_hexagon_res sc7280_mss = {
+ .hexagon_mba_image = "mba.mbn",
+ .proxy_clk_names = (char*[]){
+ "xo",
+ NULL
+ },
+ .active_clk_names = (char*[]){
+ "iface",
+ "offline",
+ "snoc_axi",
+ NULL
+ },
+ .proxy_pd_names = (char*[]){
+ "cx",
+ "mss",
+ NULL
+ },
+ .need_mem_protection = true,
+ .has_alt_reset = false,
+ .has_mba_logs = true,
+ .has_spare_reg = false,
+ .has_qaccept_regs = true,
+ .has_ext_cntl_regs = true,
+ .has_vq6 = true,
+ .version = MSS_SC7280,
+};
+
static const struct rproc_hexagon_res sdm845_mss = {
.hexagon_mba_image = "mba.mbn",
.proxy_clk_names = (char*[]){
@@ -1889,6 +2117,9 @@ static const struct rproc_hexagon_res sdm845_mss = {
.has_alt_reset = true,
.has_mba_logs = false,
.has_spare_reg = false,
+ .has_qaccept_regs = false,
+ .has_ext_cntl_regs = false,
+ .has_vq6 = false,
.version = MSS_SDM845,
};
@@ -1917,6 +2148,9 @@ static const struct rproc_hexagon_res msm8998_mss = {
.has_alt_reset = false,
.has_mba_logs = false,
.has_spare_reg = false,
+ .has_qaccept_regs = false,
+ .has_ext_cntl_regs = false,
+ .has_vq6 = false,
.version = MSS_MSM8998,
};
@@ -1948,6 +2182,9 @@ static const struct rproc_hexagon_res msm8996_mss = {
.has_alt_reset = false,
.has_mba_logs = false,
.has_spare_reg = false,
+ .has_qaccept_regs = false,
+ .has_ext_cntl_regs = false,
+ .has_vq6 = false,
.version = MSS_MSM8996,
};
@@ -1990,6 +2227,9 @@ static const struct rproc_hexagon_res msm8916_mss = {
.has_alt_reset = false,
.has_mba_logs = false,
.has_spare_reg = false,
+ .has_qaccept_regs = false,
+ .has_ext_cntl_regs = false,
+ .has_vq6 = false,
.version = MSS_MSM8916,
};
@@ -2040,6 +2280,9 @@ static const struct rproc_hexagon_res msm8974_mss = {
.has_alt_reset = false,
.has_mba_logs = false,
.has_spare_reg = false,
+ .has_qaccept_regs = false,
+ .has_ext_cntl_regs = false,
+ .has_vq6 = false,
.version = MSS_MSM8974,
};
@@ -2050,6 +2293,7 @@ static const struct of_device_id q6v5_of_match[] = {
{ .compatible = "qcom,msm8996-mss-pil", .data = &msm8996_mss},
{ .compatible = "qcom,msm8998-mss-pil", .data = &msm8998_mss},
{ .compatible = "qcom,sc7180-mss-pil", .data = &sc7180_mss},
+ { .compatible = "qcom,sc7280-mss-pil", .data = &sc7280_mss},
{ .compatible = "qcom,sdm845-mss-pil", .data = &sdm845_mss},
{ },
};
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 11%]
* [PATCH v3 02/10] remoteproc: qcom: pas: Add SC7280 Modem support
2021-08-19 3:36 18% [PATCH v3 00/10] Add Modem support on SC7280 SoCs Sibi Sankar
2021-08-19 3:36 18% ` [PATCH v3 01/10] dt-bindings: remoteproc: qcom: pas: Add SC7280 MPSS support Sibi Sankar
@ 2021-08-19 3:36 19% ` Sibi Sankar
2021-08-23 20:14 0% ` Stephen Boyd
2021-08-19 3:36 14% ` [PATCH v3 03/10] dt-bindings: remoteproc: qcom: Update Q6V5 Modem PIL binding Sibi Sankar
` (7 subsequent siblings)
9 siblings, 1 reply; 200+ results
From: Sibi Sankar @ 2021-08-19 3:36 UTC (permalink / raw)
To: bjorn.andersson, robh+dt, will, saiprakash.ranjan, swboyd, mka
Cc: ohad, agross, mathieu.poirier, robin.murphy, joro, p.zabel,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
linux-arm-kernel, evgreen, dianders, Sibi Sankar
Add support for booting the Modem DSP found on QTI SC7280 SoCs.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
---
drivers/remoteproc/qcom_q6v5_pas.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q6v5_pas.c
index 7036e6e9eff4..89c889c041e5 100644
--- a/drivers/remoteproc/qcom_q6v5_pas.c
+++ b/drivers/remoteproc/qcom_q6v5_pas.c
@@ -783,6 +783,7 @@ static const struct of_device_id adsp_of_match[] = {
{ .compatible = "qcom,qcs404-cdsp-pas", .data = &cdsp_resource_init },
{ .compatible = "qcom,qcs404-wcss-pas", .data = &wcss_resource_init },
{ .compatible = "qcom,sc7180-mpss-pas", .data = &mpss_resource_init},
+ { .compatible = "qcom,sc7280-mpss-pas", .data = &mpss_resource_init},
{ .compatible = "qcom,sc8180x-adsp-pas", .data = &sm8150_adsp_resource},
{ .compatible = "qcom,sc8180x-cdsp-pas", .data = &sm8150_cdsp_resource},
{ .compatible = "qcom,sc8180x-mpss-pas", .data = &sc8180x_mpss_resource},
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 19%]
* [PATCH v3 03/10] dt-bindings: remoteproc: qcom: Update Q6V5 Modem PIL binding
2021-08-19 3:36 18% [PATCH v3 00/10] Add Modem support on SC7280 SoCs Sibi Sankar
2021-08-19 3:36 18% ` [PATCH v3 01/10] dt-bindings: remoteproc: qcom: pas: Add SC7280 MPSS support Sibi Sankar
2021-08-19 3:36 19% ` [PATCH v3 02/10] remoteproc: qcom: pas: Add SC7280 Modem support Sibi Sankar
@ 2021-08-19 3:36 14% ` Sibi Sankar
2021-08-23 20:14 0% ` Stephen Boyd
2021-08-19 3:36 19% ` [PATCH v3 04/10] iommu/arm-smmu-qcom: Request direct mapping for modem device Sibi Sankar
` (6 subsequent siblings)
9 siblings, 1 reply; 200+ results
From: Sibi Sankar @ 2021-08-19 3:36 UTC (permalink / raw)
To: bjorn.andersson, robh+dt, will, saiprakash.ranjan, swboyd, mka
Cc: ohad, agross, mathieu.poirier, robin.murphy, joro, p.zabel,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
linux-arm-kernel, evgreen, dianders, Sibi Sankar
Add a new modem compatible string for QTI SC7280 SoCs and introduce the
"qcom,ext-regs" and "qcom,qaccept-regs" properties needed by the modem
sub-system running on SC7280 SoCs.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Acked-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/remoteproc/qcom,q6v5.txt | 32 ++++++++++++++++++++--
1 file changed, 30 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
index 494257010629..bc1394f5d677 100644
--- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
@@ -15,6 +15,7 @@ on the Qualcomm Hexagon core.
"qcom,msm8996-mss-pil"
"qcom,msm8998-mss-pil"
"qcom,sc7180-mss-pil"
+ "qcom,sc7280-mss-pil"
"qcom,sdm845-mss-pil"
- reg:
@@ -47,6 +48,7 @@ on the Qualcomm Hexagon core.
qcom,msm8996-mss-pil:
qcom,msm8998-mss-pil:
qcom,sc7180-mss-pil:
+ qcom,sc7280-mss-pil:
qcom,sdm845-mss-pil:
must be "wdog", "fatal", "ready", "handover", "stop-ack",
"shutdown-ack"
@@ -87,6 +89,8 @@ on the Qualcomm Hexagon core.
qcom,sc7180-mss-pil:
must be "iface", "bus", "xo", "snoc_axi", "mnoc_axi",
"nav"
+ qcom,sc7280-mss-pil:
+ must be "iface", "xo", "snoc_axi", "offline"
qcom,sdm845-mss-pil:
must be "iface", "bus", "mem", "xo", "gpll0_mss",
"snoc_axi", "mnoc_axi", "prng"
@@ -98,7 +102,7 @@ on the Qualcomm Hexagon core.
reference to the list of 3 reset-controllers for the
wcss sub-system
reference to the list of 2 reset-controllers for the modem
- sub-system on SC7180, SDM845 SoCs
+ sub-system on SC7180, SC7280, SDM845 SoCs
- reset-names:
Usage: required
@@ -107,7 +111,7 @@ on the Qualcomm Hexagon core.
must be "wcss_aon_reset", "wcss_reset", "wcss_q6_reset"
for the wcss sub-system
must be "mss_restart", "pdc_reset" for the modem
- sub-system on SC7180, SDM845 SoCs
+ sub-system on SC7180, SC7280, SDM845 SoCs
For devices where the mba and mpss sub-nodes are not specified, mba/mpss region
should be referenced as follows:
@@ -173,6 +177,9 @@ For the compatible string below the following supplies are required:
qcom,msm8998-mss-pil:
must be "cx", "mx"
qcom,sc7180-mss-pil:
+ must be "cx", "mx", "mss"
+ qcom,sc7280-mss-pil:
+ must be "cx", "mss"
qcom,sdm845-mss-pil:
must be "cx", "mx", "mss"
@@ -198,6 +205,9 @@ For the compatible string below the following supplies are required:
Definition: a phandle reference to a syscon representing TCSR followed
by the three offsets within syscon for q6, modem and nc
halt registers.
+ a phandle reference to a syscon representing TCSR followed
+ by the four offsets within syscon for q6, modem, nc and vq6
+ halt registers on SC7280 SoCs.
For the compatible strings below the following phandle references are required:
"qcom,sc7180-mss-pil"
@@ -208,6 +218,24 @@ For the compatible strings below the following phandle references are required:
by the offset within syscon for conn_box_spare0 register
used by the modem sub-system running on SC7180 SoC.
+For the compatible strings below the following phandle references are required:
+ "qcom,sc7280-mss-pil"
+- qcom,ext-regs:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: two phandle references to syscons representing TCSR_REG and
+ TCSR register space followed by the two offsets within the syscon
+ to force_clk_en/rscc_disable and axim1_clk_off/crypto_clk_off
+ registers respectively.
+
+- qcom,qaccept-regs:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: a phandle reference to a syscon representing TCSR followed
+ by the three offsets within syscon for mdm, cx and axi
+ qaccept registers used by the modem sub-system running on
+ SC7280 SoC.
+
The Hexagon node must contain iommus property as described in ../iommu/iommu.txt
on platforms which do not have TrustZone.
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 14%]
* [PATCH v3 04/10] iommu/arm-smmu-qcom: Request direct mapping for modem device
2021-08-19 3:36 18% [PATCH v3 00/10] Add Modem support on SC7280 SoCs Sibi Sankar
` (2 preceding siblings ...)
2021-08-19 3:36 14% ` [PATCH v3 03/10] dt-bindings: remoteproc: qcom: Update Q6V5 Modem PIL binding Sibi Sankar
@ 2021-08-19 3:36 19% ` Sibi Sankar
2021-08-19 3:36 11% ` [PATCH v3 05/10] remoteproc: mss: q6v5-mss: Add modem support on SC7280 Sibi Sankar
` (5 subsequent siblings)
9 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-08-19 3:36 UTC (permalink / raw)
To: bjorn.andersson, robh+dt, will, saiprakash.ranjan, swboyd, mka
Cc: ohad, agross, mathieu.poirier, robin.murphy, joro, p.zabel,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
linux-arm-kernel, evgreen, dianders, Sibi Sankar
The SID configuration requirement for Modem on SC7280 is similar to the
ones found on SC7180/SDM845 SoCs. So, add the SC7280 modem compatible to
the list to defer the programming of the modem SIDs to the kernel.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index 9b9d13ec5a88..a4b4c8013b3a 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -229,6 +229,7 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = {
{ .compatible = "qcom,sc7180-mdss" },
{ .compatible = "qcom,sc7180-mss-pil" },
{ .compatible = "qcom,sc7280-mdss" },
+ { .compatible = "qcom,sc7280-mss-pil" },
{ .compatible = "qcom,sc8180x-mdss" },
{ .compatible = "qcom,sdm845-mdss" },
{ .compatible = "qcom,sdm845-mss-pil" },
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 19%]
* [PATCH v3 01/10] dt-bindings: remoteproc: qcom: pas: Add SC7280 MPSS support
2021-08-19 3:36 18% [PATCH v3 00/10] Add Modem support on SC7280 SoCs Sibi Sankar
@ 2021-08-19 3:36 18% ` Sibi Sankar
2021-08-23 20:14 0% ` Stephen Boyd
2021-08-19 3:36 19% ` [PATCH v3 02/10] remoteproc: qcom: pas: Add SC7280 Modem support Sibi Sankar
` (8 subsequent siblings)
9 siblings, 1 reply; 200+ results
From: Sibi Sankar @ 2021-08-19 3:36 UTC (permalink / raw)
To: bjorn.andersson, robh+dt, will, saiprakash.ranjan, swboyd, mka
Cc: ohad, agross, mathieu.poirier, robin.murphy, joro, p.zabel,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
linux-arm-kernel, evgreen, dianders, Sibi Sankar
Add MPSS PAS support for SC7280 SoCs.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml
index 0d2b5bd4907a..68ee7febddd9 100644
--- a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml
@@ -25,6 +25,7 @@ properties:
- qcom,qcs404-cdsp-pas
- qcom,qcs404-wcss-pas
- qcom,sc7180-mpss-pas
+ - qcom,sc7280-mpss-pas
- qcom,sc8180x-adsp-pas
- qcom,sc8180x-cdsp-pas
- qcom,sc8180x-mpss-pas
@@ -151,6 +152,7 @@ allOf:
- qcom,msm8998-adsp-pas
- qcom,qcs404-adsp-pas
- qcom,qcs404-wcss-pas
+ - qcom,sc7280-mpss-pas
- qcom,sc8180x-adsp-pas
- qcom,sc8180x-cdsp-pas
- qcom,sc8180x-mpss-pas
@@ -296,6 +298,7 @@ allOf:
contains:
enum:
- qcom,sc7180-mpss-pas
+ - qcom,sc7280-mpss-pas
- qcom,sc8180x-mpss-pas
- qcom,sdx55-mpss-pas
- qcom,sm8150-mpss-pas
@@ -400,6 +403,7 @@ allOf:
compatible:
contains:
enum:
+ - qcom,sc7280-mpss-pas
- qcom,sdx55-mpss-pas
- qcom,sm8150-mpss-pas
- qcom,sm8350-mpss-pas
@@ -475,6 +479,7 @@ allOf:
contains:
enum:
- qcom,sc7180-mpss-pas
+ - qcom,sc7280-mpss-pas
then:
properties:
resets:
@@ -492,6 +497,7 @@ allOf:
contains:
enum:
- qcom,sc7180-mpss-pas
+ - qcom,sc7280-mpss-pas
- qcom,sc8180x-adsp-pas
- qcom,sc8180x-cdsp-pas
- qcom,sc8180x-mpss-pas
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 18%]
* [PATCH v3 00/10] Add Modem support on SC7280 SoCs
@ 2021-08-19 3:36 18% Sibi Sankar
2021-08-19 3:36 18% ` [PATCH v3 01/10] dt-bindings: remoteproc: qcom: pas: Add SC7280 MPSS support Sibi Sankar
` (9 more replies)
0 siblings, 10 replies; 200+ results
From: Sibi Sankar @ 2021-08-19 3:36 UTC (permalink / raw)
To: bjorn.andersson, robh+dt, will, saiprakash.ranjan, swboyd, mka
Cc: ohad, agross, mathieu.poirier, robin.murphy, joro, p.zabel,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
linux-arm-kernel, evgreen, dianders, Sibi Sankar
This patch series adds support for booting the Modem Q6 DSP found on
Qualcomm's SC7280 SoCs.
Depends on:
qmp_send: https://patchwork.kernel.org/project/linux-arm-msm/cover/1629113954-14084-1-git-send-email-deesin@codeaurora.org/
rproc qmp: https://patchwork.kernel.org/project/linux-arm-msm/cover/1629342136-3667-1-git-send-email-sibis@codeaurora.org/
V3:
* Keep the memory map version in commit message (patch 6). [Bjorn]
* Rename tcsr node and add qualifying compatibles to tcsr and imem nodes
(patch 8). [Bjorn]
* Place remoteproc_mpss node in alphabetical order above pinctrl
section (patch 10). [Stephen]
V2:
* Misc. typos (patch 3). [Matthias]
* Document the q-channel takedown procedure (patch 5). [Matthias]
* Split reserved memory updates between SoC and platform (patch 6). [Matthias]
Sibi Sankar (10):
dt-bindings: remoteproc: qcom: pas: Add SC7280 MPSS support
remoteproc: qcom: pas: Add SC7280 Modem support
dt-bindings: remoteproc: qcom: Update Q6V5 Modem PIL binding
iommu/arm-smmu-qcom: Request direct mapping for modem device
remoteproc: mss: q6v5-mss: Add modem support on SC7280
arm64: dts: qcom: sc7280: Update reserved memory map
arm64: dts: qcom: sc7280: Add/Delete/Update reserved memory nodes
arm64: dts: qcom: sc7280: Add nodes to boot modem
arm64: dts: qcom: sc7280: Add Q6V5 MSS node
arm64: dts: qcom: sc7280: Update Q6V5 MSS node
.../devicetree/bindings/remoteproc/qcom,adsp.yaml | 6 +
.../devicetree/bindings/remoteproc/qcom,q6v5.txt | 32 ++-
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 59 +++++
arch/arm64/boot/dts/qcom/sc7280.dtsi | 107 +++++++++
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
drivers/remoteproc/qcom_q6v5_mss.c | 252 ++++++++++++++++++++-
drivers/remoteproc/qcom_q6v5_pas.c | 1 +
7 files changed, 452 insertions(+), 6 deletions(-)
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [relevance 18%]
* [PATCH v5 11/13] soc: qcom: aoss: Drop power domain support
2021-08-19 3:02 9% [PATCH v5 00/13] Use qmp_send to update co-processor load state Sibi Sankar
` (9 preceding siblings ...)
2021-08-19 3:02 16% ` [PATCH v5 10/13] arm64: dts: qcom: sm8350: " Sibi Sankar
@ 2021-08-19 3:02 15% ` Sibi Sankar
2021-08-19 3:02 19% ` [PATCH v5 12/13] dt-bindings: msm/dp: Remove aoss-qmp header Sibi Sankar
2021-08-19 3:02 19% ` [PATCH v5 13/13] dt-bindings: soc: qcom: aoss: Delete unused power-domain definitions Sibi Sankar
12 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-08-19 3:02 UTC (permalink / raw)
To: mka, swboyd, bjorn.andersson, robh+dt
Cc: ulf.hansson, rjw, agross, ohad, mathieu.poirier, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel, dianders, rishabhb,
sidgup, Sibi Sankar
Strip out the load state power-domain support from the driver since the
low power mode signalling for the co-processors is now accessible through
the direct qmp message send interface.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
drivers/soc/qcom/qcom_aoss.c | 107 -------------------------------------------
1 file changed, 107 deletions(-)
diff --git a/drivers/soc/qcom/qcom_aoss.c b/drivers/soc/qcom/qcom_aoss.c
index 99ec075f0eb9..58fb9ee68f15 100644
--- a/drivers/soc/qcom/qcom_aoss.c
+++ b/drivers/soc/qcom/qcom_aoss.c
@@ -2,7 +2,6 @@
/*
* Copyright (c) 2019, Linaro Ltd
*/
-#include <dt-bindings/power/qcom-aoss-qmp.h>
#include <linux/clk-provider.h>
#include <linux/debugfs.h>
#include <linux/interrupt.h>
@@ -11,7 +10,6 @@
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
-#include <linux/pm_domain.h>
#include <linux/thermal.h>
#include <linux/slab.h>
#include <linux/soc/qcom/qcom_aoss.h>
@@ -67,7 +65,6 @@ struct qmp_cooling_device {
* @event: wait_queue for synchronization with the IRQ
* @tx_lock: provides synchronization between multiple callers of qmp_send()
* @qdss_clk: QDSS clock hw struct
- * @pd_data: genpd data
* @cooling_devs: thermal cooling devices
*/
struct qmp {
@@ -85,20 +82,12 @@ struct qmp {
struct mutex tx_lock;
struct clk_hw qdss_clk;
- struct genpd_onecell_data pd_data;
struct qmp_cooling_device *cooling_devs;
#if IS_ENABLED(CONFIG_DEBUG_FS)
struct dentry *debugfs_file;
#endif /* CONFIG_DEBUG_FS */
};
-struct qmp_pd {
- struct qmp *qmp;
- struct generic_pm_domain pd;
-};
-
-#define to_qmp_pd_resource(res) container_of(res, struct qmp_pd, pd)
-
static void qmp_kick(struct qmp *qmp)
{
mbox_send_message(qmp->mbox_chan, NULL);
@@ -324,95 +313,6 @@ static void qmp_qdss_clk_remove(struct qmp *qmp)
clk_hw_unregister(&qmp->qdss_clk);
}
-static int qmp_pd_power_toggle(struct qmp_pd *res, bool enable)
-{
- char buf[QMP_MSG_LEN] = {};
-
- snprintf(buf, sizeof(buf),
- "{class: image, res: load_state, name: %s, val: %s}",
- res->pd.name, enable ? "on" : "off");
- return qmp_send(res->qmp, buf, sizeof(buf));
-}
-
-static int qmp_pd_power_on(struct generic_pm_domain *domain)
-{
- return qmp_pd_power_toggle(to_qmp_pd_resource(domain), true);
-}
-
-static int qmp_pd_power_off(struct generic_pm_domain *domain)
-{
- return qmp_pd_power_toggle(to_qmp_pd_resource(domain), false);
-}
-
-static const char * const sdm845_resources[] = {
- [AOSS_QMP_LS_CDSP] = "cdsp",
- [AOSS_QMP_LS_LPASS] = "adsp",
- [AOSS_QMP_LS_MODEM] = "modem",
- [AOSS_QMP_LS_SLPI] = "slpi",
- [AOSS_QMP_LS_SPSS] = "spss",
- [AOSS_QMP_LS_VENUS] = "venus",
-};
-
-static int qmp_pd_add(struct qmp *qmp)
-{
- struct genpd_onecell_data *data = &qmp->pd_data;
- struct device *dev = qmp->dev;
- struct qmp_pd *res;
- size_t num = ARRAY_SIZE(sdm845_resources);
- int ret;
- int i;
-
- res = devm_kcalloc(dev, num, sizeof(*res), GFP_KERNEL);
- if (!res)
- return -ENOMEM;
-
- data->domains = devm_kcalloc(dev, num, sizeof(*data->domains),
- GFP_KERNEL);
- if (!data->domains)
- return -ENOMEM;
-
- for (i = 0; i < num; i++) {
- res[i].qmp = qmp;
- res[i].pd.name = sdm845_resources[i];
- res[i].pd.power_on = qmp_pd_power_on;
- res[i].pd.power_off = qmp_pd_power_off;
-
- ret = pm_genpd_init(&res[i].pd, NULL, true);
- if (ret < 0) {
- dev_err(dev, "failed to init genpd\n");
- goto unroll_genpds;
- }
-
- data->domains[i] = &res[i].pd;
- }
-
- data->num_domains = i;
-
- ret = of_genpd_add_provider_onecell(dev->of_node, data);
- if (ret < 0)
- goto unroll_genpds;
-
- return 0;
-
-unroll_genpds:
- for (i--; i >= 0; i--)
- pm_genpd_remove(data->domains[i]);
-
- return ret;
-}
-
-static void qmp_pd_remove(struct qmp *qmp)
-{
- struct genpd_onecell_data *data = &qmp->pd_data;
- struct device *dev = qmp->dev;
- int i;
-
- of_genpd_del_provider(dev->of_node);
-
- for (i = 0; i < data->num_domains; i++)
- pm_genpd_remove(data->domains[i]);
-}
-
static int qmp_cdev_get_max_state(struct thermal_cooling_device *cdev,
unsigned long *state)
{
@@ -642,10 +542,6 @@ static int qmp_probe(struct platform_device *pdev)
if (ret)
goto err_close_qmp;
- ret = qmp_pd_add(qmp);
- if (ret)
- goto err_remove_qdss_clk;
-
ret = qmp_cooling_devices_register(qmp);
if (ret)
dev_err(&pdev->dev, "failed to register aoss cooling devices\n");
@@ -659,8 +555,6 @@ static int qmp_probe(struct platform_device *pdev)
return 0;
-err_remove_qdss_clk:
- qmp_qdss_clk_remove(qmp);
err_close_qmp:
qmp_close(qmp);
err_free_mbox:
@@ -678,7 +572,6 @@ static int qmp_remove(struct platform_device *pdev)
#endif /* CONFIG_DEBUG_FS */
qmp_qdss_clk_remove(qmp);
- qmp_pd_remove(qmp);
qmp_cooling_devices_remove(qmp);
qmp_close(qmp);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 15%]
* [PATCH v5 09/13] arm64: dts: qcom: sm8250: Use QMP property to control load state
2021-08-19 3:02 9% [PATCH v5 00/13] Use qmp_send to update co-processor load state Sibi Sankar
` (7 preceding siblings ...)
2021-08-19 3:02 17% ` [PATCH v5 08/13] arm64: dts: qcom: sm8150: " Sibi Sankar
@ 2021-08-19 3:02 17% ` Sibi Sankar
2021-08-19 3:02 16% ` [PATCH v5 10/13] arm64: dts: qcom: sm8350: " Sibi Sankar
` (3 subsequent siblings)
12 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-08-19 3:02 UTC (permalink / raw)
To: mka, swboyd, bjorn.andersson, robh+dt
Cc: ulf.hansson, rjw, agross, ohad, mathieu.poirier, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel, dianders, rishabhb,
sidgup, Sibi Sankar
Use the Qualcomm Mailbox Protocol (QMP) property to control the load
state resources on SM8250 SoCs and drop deprecated power-domains exposed
by AOSS QMP node.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 8c15d9fed08f..2796b27f7c04 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -13,7 +13,6 @@
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sm8250.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
-#include <dt-bindings/power/qcom-aoss-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,apr.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
@@ -2088,13 +2087,14 @@
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
- <&rpmhpd SM8250_LCX>,
+ power-domains = <&rpmhpd SM8250_LCX>,
<&rpmhpd SM8250_LMX>;
- power-domain-names = "load_state", "lcx", "lmx";
+ power-domain-names = "lcx", "lmx";
memory-region = <&slpi_mem>;
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&smp2p_slpi_out 0>;
qcom,smem-state-names = "stop";
@@ -2154,12 +2154,12 @@
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
- <&rpmhpd SM8250_CX>;
- power-domain-names = "load_state", "cx";
+ power-domains = <&rpmhpd SM8250_CX>;
memory-region = <&cdsp_mem>;
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&smp2p_cdsp_out 0>;
qcom,smem-state-names = "stop";
@@ -2907,7 +2907,6 @@
IPCC_MPROC_SIGNAL_GLINK_QMP>;
#clock-cells = <0>;
- #power-domain-cells = <1>;
};
spmi_bus: spmi@c440000 {
@@ -3824,13 +3823,14 @@
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
- <&rpmhpd SM8250_LCX>,
+ power-domains = <&rpmhpd SM8250_LCX>,
<&rpmhpd SM8250_LMX>;
- power-domain-names = "load_state", "lcx", "lmx";
+ power-domain-names = "lcx", "lmx";
memory-region = <&adsp_mem>;
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&smp2p_adsp_out 0>;
qcom,smem-state-names = "stop";
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 17%]
* [PATCH v5 13/13] dt-bindings: soc: qcom: aoss: Delete unused power-domain definitions
2021-08-19 3:02 9% [PATCH v5 00/13] Use qmp_send to update co-processor load state Sibi Sankar
` (11 preceding siblings ...)
2021-08-19 3:02 19% ` [PATCH v5 12/13] dt-bindings: msm/dp: Remove aoss-qmp header Sibi Sankar
@ 2021-08-19 3:02 19% ` Sibi Sankar
12 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-08-19 3:02 UTC (permalink / raw)
To: mka, swboyd, bjorn.andersson, robh+dt
Cc: ulf.hansson, rjw, agross, ohad, mathieu.poirier, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel, dianders, rishabhb,
sidgup, Sibi Sankar
Delete unused power-domain definitions exposed by AOSS QMP.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
---
include/dt-bindings/power/qcom-aoss-qmp.h | 14 --------------
1 file changed, 14 deletions(-)
delete mode 100644 include/dt-bindings/power/qcom-aoss-qmp.h
diff --git a/include/dt-bindings/power/qcom-aoss-qmp.h b/include/dt-bindings/power/qcom-aoss-qmp.h
deleted file mode 100644
index ec336d31dee4..000000000000
--- a/include/dt-bindings/power/qcom-aoss-qmp.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* Copyright (c) 2018, Linaro Ltd. */
-
-#ifndef __DT_BINDINGS_POWER_QCOM_AOSS_QMP_H
-#define __DT_BINDINGS_POWER_QCOM_AOSS_QMP_H
-
-#define AOSS_QMP_LS_CDSP 0
-#define AOSS_QMP_LS_LPASS 1
-#define AOSS_QMP_LS_MODEM 2
-#define AOSS_QMP_LS_SLPI 3
-#define AOSS_QMP_LS_SPSS 4
-#define AOSS_QMP_LS_VENUS 5
-
-#endif
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 19%]
* [PATCH v5 12/13] dt-bindings: msm/dp: Remove aoss-qmp header
2021-08-19 3:02 9% [PATCH v5 00/13] Use qmp_send to update co-processor load state Sibi Sankar
` (10 preceding siblings ...)
2021-08-19 3:02 15% ` [PATCH v5 11/13] soc: qcom: aoss: Drop power domain support Sibi Sankar
@ 2021-08-19 3:02 19% ` Sibi Sankar
2021-08-19 3:02 19% ` [PATCH v5 13/13] dt-bindings: soc: qcom: aoss: Delete unused power-domain definitions Sibi Sankar
12 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-08-19 3:02 UTC (permalink / raw)
To: mka, swboyd, bjorn.andersson, robh+dt
Cc: ulf.hansson, rjw, agross, ohad, mathieu.poirier, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel, dianders, rishabhb,
sidgup, Sibi Sankar
Remove the unused aoss-qmp header from the list of includes.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
Documentation/devicetree/bindings/display/msm/dp-controller.yaml | 1 -
1 file changed, 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
index 64d8d9e5e47a..d89b3c510c27 100644
--- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
@@ -95,7 +95,6 @@ examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,dispcc-sc7180.h>
- #include <dt-bindings/power/qcom-aoss-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
displayport-controller@ae90000 {
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 19%]
* [PATCH v5 08/13] arm64: dts: qcom: sm8150: Use QMP property to control load state
2021-08-19 3:02 9% [PATCH v5 00/13] Use qmp_send to update co-processor load state Sibi Sankar
` (6 preceding siblings ...)
2021-08-19 3:02 18% ` [PATCH v5 07/13] arm64: dts: qcom: sdm845: " Sibi Sankar
@ 2021-08-19 3:02 17% ` Sibi Sankar
2021-08-19 3:02 17% ` [PATCH v5 09/13] arm64: dts: qcom: sm8250: " Sibi Sankar
` (4 subsequent siblings)
12 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-08-19 3:02 UTC (permalink / raw)
To: mka, swboyd, bjorn.andersson, robh+dt
Cc: ulf.hansson, rjw, agross, ohad, mathieu.poirier, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel, dianders, rishabhb,
sidgup, Sibi Sankar
Use the Qualcomm Mailbox Protocol (QMP) property to control the load
state resources on SM8150 SoCs and drop deprecated power-domains exposed
by AOSS QMP node.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 28 ++++++++++++++--------------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index ef0232c2cf45..8a035693b7a3 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -6,7 +6,6 @@
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/power/qcom-aoss-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
@@ -1729,13 +1728,14 @@
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
- <&rpmhpd 3>,
+ power-domains = <&rpmhpd 3>,
<&rpmhpd 2>;
- power-domain-names = "load_state", "lcx", "lmx";
+ power-domain-names = "lcx", "lmx";
memory-region = <&slpi_mem>;
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&slpi_smp2p_out 0>;
qcom,smem-state-names = "stop";
@@ -2319,13 +2319,14 @@
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
- <&rpmhpd 7>,
+ power-domains = <&rpmhpd 7>,
<&rpmhpd 0>;
- power-domain-names = "load_state", "cx", "mss";
+ power-domain-names = "cx", "mss";
memory-region = <&mpss_mem>;
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&modem_smp2p_out 0>;
qcom,smem-state-names = "stop";
@@ -2945,12 +2946,12 @@
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
- <&rpmhpd 7>;
- power-domain-names = "load_state", "cx";
+ power-domains = <&rpmhpd 7>;
memory-region = <&cdsp_mem>;
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&cdsp_smp2p_out 0>;
qcom,smem-state-names = "stop";
@@ -3174,7 +3175,6 @@
mboxes = <&apss_shared 0>;
#clock-cells = <0>;
- #power-domain-cells = <1>;
};
tsens0: thermal-sensor@c263000 {
@@ -3321,12 +3321,12 @@
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
- <&rpmhpd 7>;
- power-domain-names = "load_state", "cx";
+ power-domains = <&rpmhpd 7>;
memory-region = <&adsp_mem>;
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&adsp_smp2p_out 0>;
qcom,smem-state-names = "stop";
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 17%]
* [PATCH v5 10/13] arm64: dts: qcom: sm8350: Use QMP property to control load state
2021-08-19 3:02 9% [PATCH v5 00/13] Use qmp_send to update co-processor load state Sibi Sankar
` (8 preceding siblings ...)
2021-08-19 3:02 17% ` [PATCH v5 09/13] arm64: dts: qcom: sm8250: " Sibi Sankar
@ 2021-08-19 3:02 16% ` Sibi Sankar
2021-08-19 3:02 15% ` [PATCH v5 11/13] soc: qcom: aoss: Drop power domain support Sibi Sankar
` (2 subsequent siblings)
12 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-08-19 3:02 UTC (permalink / raw)
To: mka, swboyd, bjorn.andersson, robh+dt
Cc: ulf.hansson, rjw, agross, ohad, mathieu.poirier, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel, dianders, rishabhb,
sidgup, Sibi Sankar
Use the Qualcomm Mailbox Protocol (QMP) property to control the load
state resources on SM8350 SoCs and drop deprecated power-domains exposed
by AOSS QMP node.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 30 ++++++++++++++++--------------
1 file changed, 16 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index e91cd8a5e535..6c83cd52a279 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -8,7 +8,6 @@
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interconnect/qcom,sm8350.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
-#include <dt-bindings/power/qcom-aoss-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/thermal/thermal.h>
@@ -726,15 +725,16 @@
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
- <&rpmhpd 0>,
+ power-domains = <&rpmhpd 0>,
<&rpmhpd 12>;
- power-domain-names = "load_state", "cx", "mss";
+ power-domain-names = "cx", "mss";
interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
memory-region = <&pil_modem_mem>;
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&smp2p_modem_out 0>;
qcom,smem-state-names = "stop";
@@ -794,7 +794,6 @@
mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
#clock-cells = <0>;
- #power-domain-cells = <1>;
};
spmi_bus: spmi@c440000 {
@@ -1107,13 +1106,14 @@
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
- <&rpmhpd 4>,
+ power-domains = <&rpmhpd 4>,
<&rpmhpd 5>;
- power-domain-names = "load_state", "lcx", "lmx";
+ power-domain-names = "lcx", "lmx";
memory-region = <&pil_slpi_mem>;
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&smp2p_slpi_out 0>;
qcom,smem-state-names = "stop";
@@ -1147,15 +1147,16 @@
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
- <&rpmhpd 0>,
+ power-domains = <&rpmhpd 0>,
<&rpmhpd 10>;
- power-domain-names = "load_state", "cx", "mxc";
+ power-domain-names = "cx", "mxc";
interconnects = <&compute_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>;
memory-region = <&pil_cdsp_mem>;
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&smp2p_cdsp_out 0>;
qcom,smem-state-names = "stop";
@@ -1381,13 +1382,14 @@
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
- <&rpmhpd 4>,
+ power-domains = <&rpmhpd 4>,
<&rpmhpd 5>;
- power-domain-names = "load_state", "lcx", "lmx";
+ power-domain-names = "lcx", "lmx";
memory-region = <&pil_adsp_mem>;
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&smp2p_adsp_out 0>;
qcom,smem-state-names = "stop";
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 16%]
* [PATCH v5 07/13] arm64: dts: qcom: sdm845: Use QMP property to control load state
2021-08-19 3:02 9% [PATCH v5 00/13] Use qmp_send to update co-processor load state Sibi Sankar
` (5 preceding siblings ...)
2021-08-19 3:02 18% ` [PATCH v5 06/13] arm64: dts: qcom: sc7280: " Sibi Sankar
@ 2021-08-19 3:02 18% ` Sibi Sankar
2021-08-19 3:02 17% ` [PATCH v5 08/13] arm64: dts: qcom: sm8150: " Sibi Sankar
` (5 subsequent siblings)
12 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-08-19 3:02 UTC (permalink / raw)
To: mka, swboyd, bjorn.andersson, robh+dt
Cc: ulf.hansson, rjw, agross, ohad, mathieu.poirier, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel, dianders, rishabhb,
sidgup, Sibi Sankar
Use the Qualcomm Mailbox Protocol (QMP) property to control the load
state resources on SDM845 SoCs and drop deprecated power-domains exposed
by AOSS QMP node.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 6d7172e6f4c3..b96e15f088a9 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -2979,6 +2979,8 @@
clock-names = "iface", "bus", "mem", "gpll0_mss",
"snoc_axi", "mnoc_axi", "prng", "xo";
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&modem_smp2p_out 0>;
qcom,smem-state-names = "stop";
@@ -2988,11 +2990,10 @@
qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
- power-domains = <&aoss_qmp 2>,
- <&rpmhpd SDM845_CX>,
+ power-domains = <&rpmhpd SDM845_CX>,
<&rpmhpd SDM845_MX>,
<&rpmhpd SDM845_MSS>;
- power-domain-names = "load_state", "cx", "mx", "mss";
+ power-domain-names = "cx", "mx", "mss";
mba {
memory-region = <&mba_region>;
@@ -4583,7 +4584,6 @@
mboxes = <&apss_shared 0>;
#clock-cells = <0>;
- #power-domain-cells = <1>;
cx_cdev: cx {
#cooling-cells = <2>;
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 18%]
* [PATCH v5 05/13] arm64: dts: qcom: sc7180: Use QMP property to control load state
2021-08-19 3:02 9% [PATCH v5 00/13] Use qmp_send to update co-processor load state Sibi Sankar
` (3 preceding siblings ...)
2021-08-19 3:02 9% ` [PATCH v5 04/13] remoteproc: qcom: q6v5: Use qmp_send to update co-processor load state Sibi Sankar
@ 2021-08-19 3:02 18% ` Sibi Sankar
2021-08-19 3:02 18% ` [PATCH v5 06/13] arm64: dts: qcom: sc7280: " Sibi Sankar
` (7 subsequent siblings)
12 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-08-19 3:02 UTC (permalink / raw)
To: mka, swboyd, bjorn.andersson, robh+dt
Cc: ulf.hansson, rjw, agross, ohad, mathieu.poirier, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel, dianders, rishabhb,
sidgup, Sibi Sankar
Use the Qualcomm Mailbox Protocol (QMP) property to control the load
state resources on SC7180 SoCs and drop deprecated power-domains exposed
by AOSS QMP node.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 4721c155ec11..e3f45f4cae2e 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -15,7 +15,6 @@
#include <dt-bindings/interconnect/qcom,sc7180.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy-qcom-qusb2.h>
-#include <dt-bindings/power/qcom-aoss-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/reset/qcom,sdm845-aoss.h>
#include <dt-bindings/reset/qcom,sdm845-pdc.h>
@@ -1898,14 +1897,15 @@
clock-names = "iface", "bus", "nav", "snoc_axi",
"mnoc_axi", "xo";
- power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
- <&rpmhpd SC7180_CX>,
+ power-domains = <&rpmhpd SC7180_CX>,
<&rpmhpd SC7180_MX>,
<&rpmhpd SC7180_MSS>;
- power-domain-names = "load_state", "cx", "mx", "mss";
+ power-domain-names = "cx", "mx", "mss";
memory-region = <&mpss_mem>;
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&modem_smp2p_out 0>;
qcom,smem-state-names = "stop";
@@ -3200,7 +3200,6 @@
mboxes = <&apss_shared 0>;
#clock-cells = <0>;
- #power-domain-cells = <1>;
};
spmi_bus: spmi@c440000 {
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 18%]
* [PATCH v5 06/13] arm64: dts: qcom: sc7280: Use QMP property to control load state
2021-08-19 3:02 9% [PATCH v5 00/13] Use qmp_send to update co-processor load state Sibi Sankar
` (4 preceding siblings ...)
2021-08-19 3:02 18% ` [PATCH v5 05/13] arm64: dts: qcom: sc7180: Use QMP property to control " Sibi Sankar
@ 2021-08-19 3:02 18% ` Sibi Sankar
2021-08-19 3:02 18% ` [PATCH v5 07/13] arm64: dts: qcom: sdm845: " Sibi Sankar
` (6 subsequent siblings)
12 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-08-19 3:02 UTC (permalink / raw)
To: mka, swboyd, bjorn.andersson, robh+dt
Cc: ulf.hansson, rjw, agross, ohad, mathieu.poirier, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel, dianders, rishabhb,
sidgup, Sibi Sankar
Use the Qualcomm Mailbox Protocol (QMP) property to control the load
state resources on SC7280 SoCs and drop deprecated power-domains exposed
by AOSS QMP node.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 53a21d086178..5e4f4f3b738a 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -10,7 +10,6 @@
#include <dt-bindings/interconnect/qcom,sc7280.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
-#include <dt-bindings/power/qcom-aoss-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/reset/qcom,sdm845-aoss.h>
#include <dt-bindings/reset/qcom,sdm845-pdc.h>
@@ -1481,7 +1480,6 @@
IPCC_MPROC_SIGNAL_GLINK_QMP>;
#clock-cells = <0>;
- #power-domain-cells = <1>;
};
spmi_bus: spmi@c440000 {
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 18%]
* [PATCH v5 04/13] remoteproc: qcom: q6v5: Use qmp_send to update co-processor load state
2021-08-19 3:02 9% [PATCH v5 00/13] Use qmp_send to update co-processor load state Sibi Sankar
` (2 preceding siblings ...)
2021-08-19 3:02 18% ` [PATCH v5 03/13] dt-bindings: remoteproc: qcom: " Sibi Sankar
@ 2021-08-19 3:02 9% ` Sibi Sankar
2021-08-23 20:17 0% ` Stephen Boyd
2021-08-19 3:02 18% ` [PATCH v5 05/13] arm64: dts: qcom: sc7180: Use QMP property to control " Sibi Sankar
` (8 subsequent siblings)
12 siblings, 1 reply; 200+ results
From: Sibi Sankar @ 2021-08-19 3:02 UTC (permalink / raw)
To: mka, swboyd, bjorn.andersson, robh+dt
Cc: ulf.hansson, rjw, agross, ohad, mathieu.poirier, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel, dianders, rishabhb,
sidgup, Sibi Sankar
The power domains exposed by the AOSS QMP driver control the load state
resources linked to modem, adsp, cdsp remoteprocs. These are used to
notify the Always on Subsystem (AOSS) that a particular co-processor is
up/down. AOSS uses this information to wait for the co-processors to
suspend before starting its sleep sequence.
These co-processors enter low-power modes independent to that of the
application processor and the load state resources linked to them are
expected to remain unaltered across system suspend/resume cycles. To
achieve this behavior lets stop using the power-domains exposed by the
AOSS QMP node and replace them with generic qmp_send interface instead.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
v5:
* Add WARN_ON on truncation, remove redundant initialization
code, use dev_err_probe. [Stephen]
* Use devm_kstrdup, handle kstrdup failure due to no memory
and set qmp to NULL when not available. [Bjorn]
drivers/remoteproc/qcom_q6v5.c | 57 ++++++++++++++++++++++++-
drivers/remoteproc/qcom_q6v5.h | 7 ++-
drivers/remoteproc/qcom_q6v5_adsp.c | 7 ++-
drivers/remoteproc/qcom_q6v5_mss.c | 44 ++++---------------
drivers/remoteproc/qcom_q6v5_pas.c | 85 +++++++++----------------------------
drivers/remoteproc/qcom_q6v5_wcss.c | 4 +-
6 files changed, 96 insertions(+), 108 deletions(-)
diff --git a/drivers/remoteproc/qcom_q6v5.c b/drivers/remoteproc/qcom_q6v5.c
index 7e9244c748da..eada7e34f3af 100644
--- a/drivers/remoteproc/qcom_q6v5.c
+++ b/drivers/remoteproc/qcom_q6v5.c
@@ -16,8 +16,30 @@
#include "qcom_common.h"
#include "qcom_q6v5.h"
+#define Q6V5_LOAD_STATE_MSG_LEN 64
#define Q6V5_PANIC_DELAY_MS 200
+static int q6v5_load_state_toggle(struct qcom_q6v5 *q6v5, bool enable)
+{
+ char buf[Q6V5_LOAD_STATE_MSG_LEN];
+ int ret;
+
+ if (!q6v5->qmp)
+ return 0;
+
+ ret = snprintf(buf, sizeof(buf),
+ "{class: image, res: load_state, name: %s, val: %s}",
+ q6v5->load_state, enable ? "on" : "off");
+
+ WARN_ON(ret >= Q6V5_LOAD_STATE_MSG_LEN);
+
+ ret = qmp_send(q6v5->qmp, buf, sizeof(buf));
+ if (ret)
+ dev_err(q6v5->dev, "failed to toggle load state\n");
+
+ return ret;
+}
+
/**
* qcom_q6v5_prepare() - reinitialize the qcom_q6v5 context before start
* @q6v5: reference to qcom_q6v5 context to be reinitialized
@@ -26,6 +48,12 @@
*/
int qcom_q6v5_prepare(struct qcom_q6v5 *q6v5)
{
+ int ret;
+
+ ret = q6v5_load_state_toggle(q6v5, true);
+ if (ret)
+ return ret;
+
reinit_completion(&q6v5->start_done);
reinit_completion(&q6v5->stop_done);
@@ -47,6 +75,7 @@ EXPORT_SYMBOL_GPL(qcom_q6v5_prepare);
int qcom_q6v5_unprepare(struct qcom_q6v5 *q6v5)
{
disable_irq(q6v5->handover_irq);
+ q6v5_load_state_toggle(q6v5, false);
return !q6v5->handover_issued;
}
@@ -196,12 +225,13 @@ EXPORT_SYMBOL_GPL(qcom_q6v5_panic);
* @pdev: platform_device reference for acquiring resources
* @rproc: associated remoteproc instance
* @crash_reason: SMEM id for crash reason string, or 0 if none
+ * @load_state: load state resource string
* @handover: function to be called when proxy resources should be released
*
* Return: 0 on success, negative errno on failure
*/
int qcom_q6v5_init(struct qcom_q6v5 *q6v5, struct platform_device *pdev,
- struct rproc *rproc, int crash_reason,
+ struct rproc *rproc, int crash_reason, const char *load_state,
void (*handover)(struct qcom_q6v5 *q6v5))
{
int ret;
@@ -286,9 +316,34 @@ int qcom_q6v5_init(struct qcom_q6v5 *q6v5, struct platform_device *pdev,
return PTR_ERR(q6v5->state);
}
+ q6v5->load_state = devm_kstrdup_const(&pdev->dev, load_state, GFP_KERNEL);
+ q6v5->qmp = qmp_get(&pdev->dev);
+ if (IS_ERR(q6v5->qmp)) {
+ if (PTR_ERR(q6v5->qmp) != -ENODEV)
+ return dev_err_probe(&pdev->dev, PTR_ERR(q6v5->qmp),
+ "failed to acquire load state\n");
+ q6v5->qmp = NULL;
+ } else if (!q6v5->load_state) {
+ if (!load_state)
+ dev_err(&pdev->dev, "load state resource string empty\n");
+
+ qmp_put(q6v5->qmp);
+ return load_state ? -ENOMEM : -EINVAL;
+ }
+
return 0;
}
EXPORT_SYMBOL_GPL(qcom_q6v5_init);
+/**
+ * qcom_q6v5_deinit() - deinitialize the q6v5 common struct
+ * @q6v5: reference to qcom_q6v5 context to be deinitialized
+ */
+void qcom_q6v5_deinit(struct qcom_q6v5 *q6v5)
+{
+ qmp_put(q6v5->qmp);
+}
+EXPORT_SYMBOL_GPL(qcom_q6v5_deinit);
+
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("Qualcomm Peripheral Image Loader for Q6V5");
diff --git a/drivers/remoteproc/qcom_q6v5.h b/drivers/remoteproc/qcom_q6v5.h
index 1c212f670cbc..f35e04471ed7 100644
--- a/drivers/remoteproc/qcom_q6v5.h
+++ b/drivers/remoteproc/qcom_q6v5.h
@@ -5,6 +5,7 @@
#include <linux/kernel.h>
#include <linux/completion.h>
+#include <linux/soc/qcom/qcom_aoss.h>
struct rproc;
struct qcom_smem_state;
@@ -15,6 +16,8 @@ struct qcom_q6v5 {
struct rproc *rproc;
struct qcom_smem_state *state;
+ struct qmp *qmp;
+
unsigned stop_bit;
int wdog_irq;
@@ -32,12 +35,14 @@ struct qcom_q6v5 {
bool running;
+ const char *load_state;
void (*handover)(struct qcom_q6v5 *q6v5);
};
int qcom_q6v5_init(struct qcom_q6v5 *q6v5, struct platform_device *pdev,
- struct rproc *rproc, int crash_reason,
+ struct rproc *rproc, int crash_reason, const char *load_state,
void (*handover)(struct qcom_q6v5 *q6v5));
+void qcom_q6v5_deinit(struct qcom_q6v5 *q6v5);
int qcom_q6v5_prepare(struct qcom_q6v5 *q6v5);
int qcom_q6v5_unprepare(struct qcom_q6v5 *q6v5);
diff --git a/drivers/remoteproc/qcom_q6v5_adsp.c b/drivers/remoteproc/qcom_q6v5_adsp.c
index 8b0d8bbacd2e..098362e6e233 100644
--- a/drivers/remoteproc/qcom_q6v5_adsp.c
+++ b/drivers/remoteproc/qcom_q6v5_adsp.c
@@ -185,7 +185,9 @@ static int adsp_start(struct rproc *rproc)
int ret;
unsigned int val;
- qcom_q6v5_prepare(&adsp->q6v5);
+ ret = qcom_q6v5_prepare(&adsp->q6v5);
+ if (ret)
+ return ret;
ret = clk_prepare_enable(adsp->xo);
if (ret)
@@ -465,7 +467,7 @@ static int adsp_probe(struct platform_device *pdev)
if (ret)
goto disable_pm;
- ret = qcom_q6v5_init(&adsp->q6v5, pdev, rproc, desc->crash_reason_smem,
+ ret = qcom_q6v5_init(&adsp->q6v5, pdev, rproc, desc->crash_reason_smem, NULL,
qcom_adsp_pil_handover);
if (ret)
goto disable_pm;
@@ -500,6 +502,7 @@ static int adsp_remove(struct platform_device *pdev)
rproc_del(adsp->rproc);
+ qcom_q6v5_deinit(&adsp->q6v5);
qcom_remove_glink_subdev(adsp->rproc, &adsp->glink_subdev);
qcom_remove_sysmon_subdev(adsp->sysmon);
qcom_remove_ssr_subdev(adsp->rproc, &adsp->ssr_subdev);
diff --git a/drivers/remoteproc/qcom_q6v5_mss.c b/drivers/remoteproc/qcom_q6v5_mss.c
index 423b31dfa574..7a1422bd7925 100644
--- a/drivers/remoteproc/qcom_q6v5_mss.c
+++ b/drivers/remoteproc/qcom_q6v5_mss.c
@@ -137,7 +137,6 @@ struct rproc_hexagon_res {
char **proxy_clk_names;
char **reset_clk_names;
char **active_clk_names;
- char **active_pd_names;
char **proxy_pd_names;
int version;
bool need_mem_protection;
@@ -169,12 +168,10 @@ struct q6v5 {
struct clk *active_clks[8];
struct clk *reset_clks[4];
struct clk *proxy_clks[4];
- struct device *active_pds[1];
struct device *proxy_pds[3];
int active_clk_count;
int reset_clk_count;
int proxy_clk_count;
- int active_pd_count;
int proxy_pd_count;
struct reg_info active_regs[1];
@@ -895,18 +892,14 @@ static int q6v5_mba_load(struct q6v5 *qproc)
int xfermemop_ret;
bool mba_load_err = false;
- qcom_q6v5_prepare(&qproc->q6v5);
-
- ret = q6v5_pds_enable(qproc, qproc->active_pds, qproc->active_pd_count);
- if (ret < 0) {
- dev_err(qproc->dev, "failed to enable active power domains\n");
- goto disable_irqs;
- }
+ ret = qcom_q6v5_prepare(&qproc->q6v5);
+ if (ret)
+ return ret;
ret = q6v5_pds_enable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
if (ret < 0) {
dev_err(qproc->dev, "failed to enable proxy power domains\n");
- goto disable_active_pds;
+ goto disable_irqs;
}
ret = q6v5_regulator_enable(qproc, qproc->fallback_proxy_regs,
@@ -1039,8 +1032,6 @@ static int q6v5_mba_load(struct q6v5 *qproc)
qproc->fallback_proxy_reg_count);
disable_proxy_pds:
q6v5_pds_disable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
-disable_active_pds:
- q6v5_pds_disable(qproc, qproc->active_pds, qproc->active_pd_count);
disable_irqs:
qcom_q6v5_unprepare(&qproc->q6v5);
@@ -1076,7 +1067,6 @@ static void q6v5_mba_reclaim(struct q6v5 *qproc)
qproc->active_clk_count);
q6v5_regulator_disable(qproc, qproc->active_regs,
qproc->active_reg_count);
- q6v5_pds_disable(qproc, qproc->active_pds, qproc->active_pd_count);
/* In case of failure or coredump scenario where reclaiming MBA memory
* could not happen reclaim it here.
@@ -1756,14 +1746,6 @@ static int q6v5_probe(struct platform_device *pdev)
}
qproc->active_reg_count = ret;
- ret = q6v5_pds_attach(&pdev->dev, qproc->active_pds,
- desc->active_pd_names);
- if (ret < 0) {
- dev_err(&pdev->dev, "Failed to attach active power domains\n");
- goto free_rproc;
- }
- qproc->active_pd_count = ret;
-
ret = q6v5_pds_attach(&pdev->dev, qproc->proxy_pds,
desc->proxy_pd_names);
/* Fallback to regulators for old device trees */
@@ -1773,12 +1755,12 @@ static int q6v5_probe(struct platform_device *pdev)
desc->fallback_proxy_supply);
if (ret < 0) {
dev_err(&pdev->dev, "Failed to get fallback proxy regulators.\n");
- goto detach_active_pds;
+ goto free_rproc;
}
qproc->fallback_proxy_reg_count = ret;
} else if (ret < 0) {
dev_err(&pdev->dev, "Failed to init power domains\n");
- goto detach_active_pds;
+ goto free_rproc;
} else {
qproc->proxy_pd_count = ret;
}
@@ -1792,7 +1774,7 @@ static int q6v5_probe(struct platform_device *pdev)
qproc->need_mem_protection = desc->need_mem_protection;
qproc->has_mba_logs = desc->has_mba_logs;
- ret = qcom_q6v5_init(&qproc->q6v5, pdev, rproc, MPSS_CRASH_REASON_SMEM,
+ ret = qcom_q6v5_init(&qproc->q6v5, pdev, rproc, MPSS_CRASH_REASON_SMEM, "modem",
qcom_msa_handover);
if (ret)
goto detach_proxy_pds;
@@ -1822,8 +1804,6 @@ static int q6v5_probe(struct platform_device *pdev)
qcom_remove_glink_subdev(rproc, &qproc->glink_subdev);
detach_proxy_pds:
q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
-detach_active_pds:
- q6v5_pds_detach(qproc, qproc->active_pds, qproc->active_pd_count);
free_rproc:
rproc_free(rproc);
@@ -1837,13 +1817,13 @@ static int q6v5_remove(struct platform_device *pdev)
rproc_del(rproc);
+ qcom_q6v5_deinit(&qproc->q6v5);
qcom_remove_sysmon_subdev(qproc->sysmon);
qcom_remove_ssr_subdev(rproc, &qproc->ssr_subdev);
qcom_remove_smd_subdev(rproc, &qproc->smd_subdev);
qcom_remove_glink_subdev(rproc, &qproc->glink_subdev);
q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
- q6v5_pds_detach(qproc, qproc->active_pds, qproc->active_pd_count);
rproc_free(rproc);
@@ -1867,10 +1847,6 @@ static const struct rproc_hexagon_res sc7180_mss = {
"nav",
NULL
},
- .active_pd_names = (char*[]){
- "load_state",
- NULL
- },
.proxy_pd_names = (char*[]){
"cx",
"mx",
@@ -1903,10 +1879,6 @@ static const struct rproc_hexagon_res sdm845_mss = {
"mnoc_axi",
NULL
},
- .active_pd_names = (char*[]){
- "load_state",
- NULL
- },
.proxy_pd_names = (char*[]){
"cx",
"mx",
diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q6v5_pas.c
index 401b1ec90785..7036e6e9eff4 100644
--- a/drivers/remoteproc/qcom_q6v5_pas.c
+++ b/drivers/remoteproc/qcom_q6v5_pas.c
@@ -37,9 +37,9 @@ struct adsp_data {
bool has_aggre2_clk;
bool auto_boot;
- char **active_pd_names;
char **proxy_pd_names;
+ const char *load_state;
const char *ssr_name;
const char *sysmon_name;
int ssctl_id;
@@ -57,10 +57,8 @@ struct qcom_adsp {
struct regulator *cx_supply;
struct regulator *px_supply;
- struct device *active_pds[1];
struct device *proxy_pds[3];
- int active_pd_count;
int proxy_pd_count;
int pas_id;
@@ -149,15 +147,13 @@ static int adsp_start(struct rproc *rproc)
struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
int ret;
- qcom_q6v5_prepare(&adsp->q6v5);
-
- ret = adsp_pds_enable(adsp, adsp->active_pds, adsp->active_pd_count);
- if (ret < 0)
- goto disable_irqs;
+ ret = qcom_q6v5_prepare(&adsp->q6v5);
+ if (ret)
+ return ret;
ret = adsp_pds_enable(adsp, adsp->proxy_pds, adsp->proxy_pd_count);
if (ret < 0)
- goto disable_active_pds;
+ goto disable_irqs;
ret = clk_prepare_enable(adsp->xo);
if (ret)
@@ -201,8 +197,6 @@ static int adsp_start(struct rproc *rproc)
clk_disable_unprepare(adsp->xo);
disable_proxy_pds:
adsp_pds_disable(adsp, adsp->proxy_pds, adsp->proxy_pd_count);
-disable_active_pds:
- adsp_pds_disable(adsp, adsp->active_pds, adsp->active_pd_count);
disable_irqs:
qcom_q6v5_unprepare(&adsp->q6v5);
@@ -234,7 +228,6 @@ static int adsp_stop(struct rproc *rproc)
if (ret)
dev_err(adsp->dev, "failed to shutdown: %d\n", ret);
- adsp_pds_disable(adsp, adsp->active_pds, adsp->active_pd_count);
handover = qcom_q6v5_unprepare(&adsp->q6v5);
if (handover)
qcom_pas_handover(&adsp->q6v5);
@@ -456,19 +449,13 @@ static int adsp_probe(struct platform_device *pdev)
if (ret)
goto free_rproc;
- ret = adsp_pds_attach(&pdev->dev, adsp->active_pds,
- desc->active_pd_names);
- if (ret < 0)
- goto free_rproc;
- adsp->active_pd_count = ret;
-
ret = adsp_pds_attach(&pdev->dev, adsp->proxy_pds,
desc->proxy_pd_names);
if (ret < 0)
- goto detach_active_pds;
+ goto free_rproc;
adsp->proxy_pd_count = ret;
- ret = qcom_q6v5_init(&adsp->q6v5, pdev, rproc, desc->crash_reason_smem,
+ ret = qcom_q6v5_init(&adsp->q6v5, pdev, rproc, desc->crash_reason_smem, desc->load_state,
qcom_pas_handover);
if (ret)
goto detach_proxy_pds;
@@ -492,8 +479,6 @@ static int adsp_probe(struct platform_device *pdev)
detach_proxy_pds:
adsp_pds_detach(adsp, adsp->proxy_pds, adsp->proxy_pd_count);
-detach_active_pds:
- adsp_pds_detach(adsp, adsp->active_pds, adsp->active_pd_count);
free_rproc:
rproc_free(rproc);
@@ -506,6 +491,7 @@ static int adsp_remove(struct platform_device *pdev)
rproc_del(adsp->rproc);
+ qcom_q6v5_deinit(&adsp->q6v5);
qcom_remove_glink_subdev(adsp->rproc, &adsp->glink_subdev);
qcom_remove_sysmon_subdev(adsp->sysmon);
qcom_remove_smd_subdev(adsp->rproc, &adsp->smd_subdev);
@@ -532,14 +518,11 @@ static const struct adsp_data sm8150_adsp_resource = {
.pas_id = 1,
.has_aggre2_clk = false,
.auto_boot = true,
- .active_pd_names = (char*[]){
- "load_state",
- NULL
- },
.proxy_pd_names = (char*[]){
"cx",
NULL
},
+ .load_state = "adsp",
.ssr_name = "lpass",
.sysmon_name = "adsp",
.ssctl_id = 0x14,
@@ -551,15 +534,12 @@ static const struct adsp_data sm8250_adsp_resource = {
.pas_id = 1,
.has_aggre2_clk = false,
.auto_boot = true,
- .active_pd_names = (char*[]){
- "load_state",
- NULL
- },
.proxy_pd_names = (char*[]){
"lcx",
"lmx",
NULL
},
+ .load_state = "adsp",
.ssr_name = "lpass",
.sysmon_name = "adsp",
.ssctl_id = 0x14,
@@ -571,15 +551,12 @@ static const struct adsp_data sm8350_adsp_resource = {
.pas_id = 1,
.has_aggre2_clk = false,
.auto_boot = true,
- .active_pd_names = (char*[]){
- "load_state",
- NULL
- },
.proxy_pd_names = (char*[]){
"lcx",
"lmx",
NULL
},
+ .load_state = "adsp",
.ssr_name = "lpass",
.sysmon_name = "adsp",
.ssctl_id = 0x14,
@@ -617,14 +594,11 @@ static const struct adsp_data sm8150_cdsp_resource = {
.pas_id = 18,
.has_aggre2_clk = false,
.auto_boot = true,
- .active_pd_names = (char*[]){
- "load_state",
- NULL
- },
.proxy_pd_names = (char*[]){
"cx",
NULL
},
+ .load_state = "cdsp",
.ssr_name = "cdsp",
.sysmon_name = "cdsp",
.ssctl_id = 0x17,
@@ -636,14 +610,11 @@ static const struct adsp_data sm8250_cdsp_resource = {
.pas_id = 18,
.has_aggre2_clk = false,
.auto_boot = true,
- .active_pd_names = (char*[]){
- "load_state",
- NULL
- },
.proxy_pd_names = (char*[]){
"cx",
NULL
},
+ .load_state = "cdsp",
.ssr_name = "cdsp",
.sysmon_name = "cdsp",
.ssctl_id = 0x17,
@@ -655,14 +626,11 @@ static const struct adsp_data sm8350_cdsp_resource = {
.pas_id = 18,
.has_aggre2_clk = false,
.auto_boot = true,
- .active_pd_names = (char*[]){
- "load_state",
- NULL
- },
.proxy_pd_names = (char*[]){
"cx",
NULL
},
+ .load_state = "cdsp",
.ssr_name = "cdsp",
.sysmon_name = "cdsp",
.ssctl_id = 0x17,
@@ -675,15 +643,12 @@ static const struct adsp_data mpss_resource_init = {
.minidump_id = 3,
.has_aggre2_clk = false,
.auto_boot = false,
- .active_pd_names = (char*[]){
- "load_state",
- NULL
- },
.proxy_pd_names = (char*[]){
"cx",
"mss",
NULL
},
+ .load_state = "modem",
.ssr_name = "mpss",
.sysmon_name = "modem",
.ssctl_id = 0x12,
@@ -695,14 +660,11 @@ static const struct adsp_data sc8180x_mpss_resource = {
.pas_id = 4,
.has_aggre2_clk = false,
.auto_boot = false,
- .active_pd_names = (char*[]){
- "load_state",
- NULL
- },
.proxy_pd_names = (char*[]){
"cx",
NULL
},
+ .load_state = "modem",
.ssr_name = "mpss",
.sysmon_name = "modem",
.ssctl_id = 0x12,
@@ -725,15 +687,12 @@ static const struct adsp_data sm8150_slpi_resource = {
.pas_id = 12,
.has_aggre2_clk = false,
.auto_boot = true,
- .active_pd_names = (char*[]){
- "load_state",
- NULL
- },
.proxy_pd_names = (char*[]){
"lcx",
"lmx",
NULL
},
+ .load_state = "slpi",
.ssr_name = "dsps",
.sysmon_name = "slpi",
.ssctl_id = 0x16,
@@ -745,15 +704,12 @@ static const struct adsp_data sm8250_slpi_resource = {
.pas_id = 12,
.has_aggre2_clk = false,
.auto_boot = true,
- .active_pd_names = (char*[]){
- "load_state",
- NULL
- },
.proxy_pd_names = (char*[]){
"lcx",
"lmx",
NULL
},
+ .load_state = "slpi",
.ssr_name = "dsps",
.sysmon_name = "slpi",
.ssctl_id = 0x16,
@@ -765,15 +721,12 @@ static const struct adsp_data sm8350_slpi_resource = {
.pas_id = 12,
.has_aggre2_clk = false,
.auto_boot = true,
- .active_pd_names = (char*[]){
- "load_state",
- NULL
- },
.proxy_pd_names = (char*[]){
"lcx",
"lmx",
NULL
},
+ .load_state = "slpi",
.ssr_name = "dsps",
.sysmon_name = "slpi",
.ssctl_id = 0x16,
diff --git a/drivers/remoteproc/qcom_q6v5_wcss.c b/drivers/remoteproc/qcom_q6v5_wcss.c
index 20d50ec7eff1..0689288a2425 100644
--- a/drivers/remoteproc/qcom_q6v5_wcss.c
+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
@@ -1044,8 +1044,7 @@ static int q6v5_wcss_probe(struct platform_device *pdev)
if (ret)
goto free_rproc;
- ret = qcom_q6v5_init(&wcss->q6v5, pdev, rproc, desc->crash_reason_smem,
- NULL);
+ ret = qcom_q6v5_init(&wcss->q6v5, pdev, rproc, desc->crash_reason_smem, NULL, NULL);
if (ret)
goto free_rproc;
@@ -1075,6 +1074,7 @@ static int q6v5_wcss_remove(struct platform_device *pdev)
{
struct rproc *rproc = platform_get_drvdata(pdev);
+ qcom_q6v5_deinit(&qproc->q6v5);
rproc_del(rproc);
rproc_free(rproc);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 9%]
* [PATCH v5 03/13] dt-bindings: remoteproc: qcom: Add QMP property
2021-08-19 3:02 9% [PATCH v5 00/13] Use qmp_send to update co-processor load state Sibi Sankar
2021-08-19 3:02 17% ` [PATCH v5 01/13] dt-bindings: soc: qcom: aoss: Drop the load state power-domain Sibi Sankar
2021-08-19 3:02 15% ` [PATCH v5 02/13] dt-bindings: remoteproc: qcom: pas: Add QMP property Sibi Sankar
@ 2021-08-19 3:02 18% ` Sibi Sankar
2021-08-19 3:02 9% ` [PATCH v5 04/13] remoteproc: qcom: q6v5: Use qmp_send to update co-processor load state Sibi Sankar
` (9 subsequent siblings)
12 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-08-19 3:02 UTC (permalink / raw)
To: mka, swboyd, bjorn.andersson, robh+dt
Cc: ulf.hansson, rjw, agross, ohad, mathieu.poirier, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel, dianders, rishabhb,
sidgup, Sibi Sankar
Add Qualcomm Mailbox Protocol (QMP) property to replace the power domain
exposed by the AOSS QMP node.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
index 69c49c7b2cff..494257010629 100644
--- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
@@ -174,7 +174,12 @@ For the compatible string below the following supplies are required:
must be "cx", "mx"
qcom,sc7180-mss-pil:
qcom,sdm845-mss-pil:
- must be "cx", "mx", "mss", "load_state"
+ must be "cx", "mx", "mss"
+
+- qcom,qmp:
+ Usage: optional
+ Value type: <phandle>
+ Definition: reference to the AOSS side-channel message RAM.
- qcom,smem-states:
Usage: required
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 18%]
* [PATCH v5 02/13] dt-bindings: remoteproc: qcom: pas: Add QMP property
2021-08-19 3:02 9% [PATCH v5 00/13] Use qmp_send to update co-processor load state Sibi Sankar
2021-08-19 3:02 17% ` [PATCH v5 01/13] dt-bindings: soc: qcom: aoss: Drop the load state power-domain Sibi Sankar
@ 2021-08-19 3:02 15% ` Sibi Sankar
2021-08-19 3:02 18% ` [PATCH v5 03/13] dt-bindings: remoteproc: qcom: " Sibi Sankar
` (10 subsequent siblings)
12 siblings, 1 reply; 200+ results
From: Sibi Sankar @ 2021-08-19 3:02 UTC (permalink / raw)
To: mka, swboyd, bjorn.andersson, robh+dt
Cc: ulf.hansson, rjw, agross, ohad, mathieu.poirier, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel, dianders, rishabhb,
sidgup, Sibi Sankar
The load state power-domain, used by the co-processors to notify the
Always on Subsystem (AOSS) that a particular co-processor is up/down,
suffers from the side-effect of changing states during suspend/resume.
However the co-processors enter low-power modes independent to that of
the application processor and their states are expected to remain
unaltered across system suspend/resume cycles. To achieve this behavior
let's drop the load state power-domain and replace them with the qmp
property for all SoCs supporting low power mode signalling.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
v5:
* Fixup power-domain count. [Matthias]
.../devicetree/bindings/remoteproc/qcom,adsp.yaml | 61 +++++++++++-----------
1 file changed, 31 insertions(+), 30 deletions(-)
diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml
index 0c112f3264a9..0d2b5bd4907a 100644
--- a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml
@@ -93,6 +93,10 @@ properties:
maxItems: 1
description: Reference to the reserved-memory for the Hexagon core
+ qcom,qmp:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: Reference to the AOSS side-channel message RAM.
+
qcom,smem-states:
$ref: /schemas/types.yaml#/definitions/phandle-array
description: States used by the AP to signal the Hexagon core
@@ -369,13 +373,11 @@ allOf:
properties:
power-domains:
items:
- - description: Load State power domain
- description: CX power domain
- description: MX power domain
- description: MSS power domain
power-domain-names:
items:
- - const: load_state
- const: cx
- const: mx
- const: mss
@@ -391,43 +393,20 @@ allOf:
properties:
power-domains:
items:
- - description: Load State power domain
- description: CX power domain
- power-domain-names:
- items:
- - const: load_state
- - const: cx
- if:
properties:
compatible:
contains:
enum:
+ - qcom,sdx55-mpss-pas
- qcom,sm8150-mpss-pas
- qcom,sm8350-mpss-pas
then:
properties:
power-domains:
items:
- - description: Load State power domain
- - description: CX power domain
- - description: MSS power domain
- power-domain-names:
- items:
- - const: load_state
- - const: cx
- - const: mss
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,sdx55-mpss-pas
- then:
- properties:
- power-domains:
- items:
- description: CX power domain
- description: MSS power domain
power-domain-names:
@@ -451,12 +430,10 @@ allOf:
properties:
power-domains:
items:
- - description: Load State power domain
- description: LCX power domain
- description: LMX power domain
power-domain-names:
items:
- - const: load_state
- const: lcx
- const: lmx
@@ -470,12 +447,10 @@ allOf:
properties:
power-domains:
items:
- - description: Load State power domain
- description: CX power domain
- description: MXC power domain
power-domain-names:
items:
- - const: load_state
- const: cx
- const: mxc
@@ -511,6 +486,32 @@ allOf:
- const: mss_restart
- const: pdc_reset
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sc7180-mpss-pas
+ - qcom,sc8180x-adsp-pas
+ - qcom,sc8180x-cdsp-pas
+ - qcom,sc8180x-mpss-pas
+ - qcom,sm8150-adsp-pas
+ - qcom,sm8150-cdsp-pas
+ - qcom,sm8150-mpss-pas
+ - qcom,sm8150-slpi-pas
+ - qcom,sm8250-adsp-pas
+ - qcom,sm8250-cdsp-pas
+ - qcom,sm8250-slpi-pas
+ - qcom,sm8350-adsp-pas
+ - qcom,sm8350-cdsp-pas
+ - qcom,sm8350-mpss-pas
+ - qcom,sm8350-slpi-pas
+ then:
+ properties:
+ qcom,qmp:
+ items:
+ - description: Reference to the AOSS side-channel message RAM.
+
examples:
- |
#include <dt-bindings/clock/qcom,rpmcc.h>
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 15%]
* [PATCH v5 01/13] dt-bindings: soc: qcom: aoss: Drop the load state power-domain
2021-08-19 3:02 9% [PATCH v5 00/13] Use qmp_send to update co-processor load state Sibi Sankar
@ 2021-08-19 3:02 17% ` Sibi Sankar
2021-08-19 3:02 15% ` [PATCH v5 02/13] dt-bindings: remoteproc: qcom: pas: Add QMP property Sibi Sankar
` (11 subsequent siblings)
12 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-08-19 3:02 UTC (permalink / raw)
To: mka, swboyd, bjorn.andersson, robh+dt
Cc: ulf.hansson, rjw, agross, ohad, mathieu.poirier, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel, dianders, rishabhb,
sidgup, Sibi Sankar
The power-domains exposed by AOSS QMP node are used to notify the Always
on Subsystem (AOSS) that a particular co-processor is up/down. These
co-processors enter low-power modes independent to that of the application
processor and their states are expected to remain unaltered across system
suspend/resume cycles. To achieve this behavior let's drop the load
power-domain and replace them with generic qmp_send interface instead.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml | 11 +----------
1 file changed, 1 insertion(+), 10 deletions(-)
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml
index 93e4b737ee1b..c55e98fc14fa 100644
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml
@@ -19,8 +19,7 @@ description:
The AOSS side channel exposes control over a set of resources, used to control
a set of debug related clocks and to affect the low power state of resources
- related to the secondary subsystems. These resources are exposed as a set of
- power-domains.
+ related to the secondary subsystems.
properties:
compatible:
@@ -57,13 +56,6 @@ properties:
description:
The single clock represents the QDSS clock.
- "#power-domain-cells":
- const: 1
- description: |
- The provided power-domains are:
- CDSP state (0), LPASS state (1), modem state (2), SLPI
- state (3), SPSS state (4) and Venus state (5).
-
required:
- compatible
- reg
@@ -101,7 +93,6 @@ examples:
mboxes = <&apss_shared 0>;
#clock-cells = <0>;
- #power-domain-cells = <1>;
cx_cdev: cx {
#cooling-cells = <2>;
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 17%]
* [PATCH v5 00/13] Use qmp_send to update co-processor load state
@ 2021-08-19 3:02 9% Sibi Sankar
2021-08-19 3:02 17% ` [PATCH v5 01/13] dt-bindings: soc: qcom: aoss: Drop the load state power-domain Sibi Sankar
` (12 more replies)
0 siblings, 13 replies; 200+ results
From: Sibi Sankar @ 2021-08-19 3:02 UTC (permalink / raw)
To: mka, swboyd, bjorn.andersson, robh+dt
Cc: ulf.hansson, rjw, agross, ohad, mathieu.poirier, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel, dianders, rishabhb,
sidgup, Sibi Sankar
The power domains exposed by the AOSS QMP driver control the load state
resources linked to modem, adsp, cdsp remoteprocs. These are used to
notify the Always on Subsystem (AOSS) that a particular co-processor is
up/down. AOSS uses this information to wait for the co-processors to
suspend before starting its sleep sequence. These co-processors enter
low-power modes independent to that of the application processor and
the load state resources linked to them are expected to remain unaltered
across system suspend/resume cycles. To achieve this behavior let's stop
modeling them as power-domains and replace them with generic qmp_send
interface instead.
https://lore.kernel.org/lkml/20200913034603.GV3715@yoga/
Previous discussion on dropping power-domain support from AOSS QMP driver
Depends on:
qmp_send: https://patchwork.kernel.org/project/linux-arm-msm/cover/1629113954-14084-1-git-send-email-deesin@codeaurora.org/
V5:
* Fixup power-domain count (patch 2). [Matthias]
* Add WARN_ON on truncation, remove redundant initialization
code, use dev_err_probe (patch 4). [Stephen]
* Use devm_kstrdup, handle kstrdup failure due to
no memory and set qmp to NULL when not available
(patch 4). [Bjorn]
V4:
* Rebase patch 1 due to the aoss-qmp yaml conversion (Dropping Rb).
* Commit message change and sc8180x co-processor addition
to patch 2. [Rob/Bjorn]
* Drop unused pdev and kfree the load state string in q6v5_deinit
/probe path for patch 4. [Matthias]
* Replaced "binding" with "property" across the series. [Matthias]
* Commit message change and drop incorrect cleanup on cooling
device probe failures. [Matthias]
V3:
* Misc. documentation fixes [patch 2]:
- Reduce power-domain maxItems due to load_state pd removal
- Combine compatibles where possible with the load_state pd removal
- Fixup the qcom,qmp ref to phandle type
V2:
* load_state is currently broken on mainline so be safely dropped
without side-effects.
* Rebased on top of qmp_send v3 series.
* Dropped R-b from Stephen and Rob on patch 3 due to the yaml
conversion.
* New patch [12] to drop unused aoss-qmp header.
* Commit message update [patch 1] [Rob]
* Reorder the series [Stephen]
Sibi Sankar (13):
dt-bindings: soc: qcom: aoss: Drop the load state power-domain
dt-bindings: remoteproc: qcom: pas: Add QMP property
dt-bindings: remoteproc: qcom: Add QMP property
remoteproc: qcom: q6v5: Use qmp_send to update co-processor load state
arm64: dts: qcom: sc7180: Use QMP property to control load state
arm64: dts: qcom: sc7280: Use QMP property to control load state
arm64: dts: qcom: sdm845: Use QMP property to control load state
arm64: dts: qcom: sm8150: Use QMP property to control load state
arm64: dts: qcom: sm8250: Use QMP property to control load state
arm64: dts: qcom: sm8350: Use QMP property to control load state
soc: qcom: aoss: Drop power domain support
dt-bindings: msm/dp: Remove aoss-qmp header
dt-bindings: soc: qcom: aoss: Delete unused power-domain definitions
.../bindings/display/msm/dp-controller.yaml | 1 -
.../devicetree/bindings/remoteproc/qcom,adsp.yaml | 61 ++++++------
.../devicetree/bindings/remoteproc/qcom,q6v5.txt | 7 +-
.../bindings/soc/qcom/qcom,aoss-qmp.yaml | 11 +--
arch/arm64/boot/dts/qcom/sc7180.dtsi | 9 +-
arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 -
arch/arm64/boot/dts/qcom/sdm845.dtsi | 8 +-
arch/arm64/boot/dts/qcom/sm8150.dtsi | 28 +++---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 22 ++---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 30 +++---
drivers/remoteproc/qcom_q6v5.c | 57 ++++++++++-
drivers/remoteproc/qcom_q6v5.h | 7 +-
drivers/remoteproc/qcom_q6v5_adsp.c | 7 +-
drivers/remoteproc/qcom_q6v5_mss.c | 44 ++-------
drivers/remoteproc/qcom_q6v5_pas.c | 85 ++++------------
drivers/remoteproc/qcom_q6v5_wcss.c | 4 +-
drivers/soc/qcom/qcom_aoss.c | 107 ---------------------
include/dt-bindings/power/qcom-aoss-qmp.h | 14 ---
18 files changed, 183 insertions(+), 321 deletions(-)
delete mode 100644 include/dt-bindings/power/qcom-aoss-qmp.h
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [relevance 9%]
* Re: [v6 1/3] dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280
@ 2021-08-16 18:09 6% ` Sibi Sankar
0 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-08-16 18:09 UTC (permalink / raw)
To: Odelu Kukatla
Cc: georgi.djakov, bjorn.andersson, evgreen, Andy Gross,
Georgi Djakov, Rob Herring, linux-arm-msm, linux-pm, devicetree,
linux-kernel, sboyd, mdtipton, saravanak, seansw, elder,
linux-arm-msm-owner
Hey Odelu,
Thanks for the patch.
On 2021-08-10 12:16, Odelu Kukatla wrote:
> Add Epoch Subsystem (EPSS) L3 interconnect provider binding on SC7280
> SoCs.
>
> Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
> ---
> .../devicetree/bindings/interconnect/qcom,osm-l3.yaml | 9
> ++++++++-
> include/dt-bindings/interconnect/qcom,osm-l3.h | 10
> +++++++++-
> 2 files changed, 17 insertions(+), 2 deletions(-)
>
> diff --git
> a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
> b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
> index e701524..919fce4 100644
> --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
> +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
> @@ -18,13 +18,20 @@ properties:
> compatible:
> enum:
> - qcom,sc7180-osm-l3
> + - qcom,sc7280-epss-l3
> - qcom,sc8180x-osm-l3
> - qcom,sdm845-osm-l3
> - qcom,sm8150-osm-l3
> - qcom,sm8250-epss-l3
>
> reg:
> - maxItems: 1
> + minItems: 1
> + maxItems: 4
> + items:
> + - description: OSM clock domain-0 base address and size
> + - description: OSM clock domain-1 base address and size
> + - description: OSM clock domain-2 base address and size
> + - description: OSM clock domain-3 base address and size
Looks like you missed addressing
Stephen's comment from v4 i.e.
having descriptions based on
compatibles.
>
> clocks:
> items:
> diff --git a/include/dt-bindings/interconnect/qcom,osm-l3.h
> b/include/dt-bindings/interconnect/qcom,osm-l3.h
> index 61ef649..99534a5 100644
> --- a/include/dt-bindings/interconnect/qcom,osm-l3.h
> +++ b/include/dt-bindings/interconnect/qcom,osm-l3.h
> @@ -1,6 +1,6 @@
> /* SPDX-License-Identifier: GPL-2.0 */
> /*
> - * Copyright (C) 2019 The Linux Foundation. All rights reserved.
> + * Copyright (C) 2019, 2021 The Linux Foundation. All rights reserved.
> */
>
> #ifndef __DT_BINDINGS_INTERCONNECT_QCOM_OSM_L3_H
> @@ -11,5 +11,13 @@
>
> #define MASTER_EPSS_L3_APPS 0
> #define SLAVE_EPSS_L3_SHARED 1
> +#define SLAVE_EPSS_L3_CPU0 2
> +#define SLAVE_EPSS_L3_CPU1 3
> +#define SLAVE_EPSS_L3_CPU2 4
> +#define SLAVE_EPSS_L3_CPU3 5
> +#define SLAVE_EPSS_L3_CPU4 6
> +#define SLAVE_EPSS_L3_CPU5 7
> +#define SLAVE_EPSS_L3_CPU6 8
> +#define SLAVE_EPSS_L3_CPU7 9
>
> #endif
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply [relevance 6%]
* Re: [PATCH V1 1/1] soc: qcom: smp2p: Add wakeup capability to SMP2P IRQ
@ 2021-08-10 17:24 6% ` Sibi Sankar
0 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-08-10 17:24 UTC (permalink / raw)
To: Stephen Boyd
Cc: Deepak Kumar Singh, bjorn.andersson, clew, linux-kernel,
linux-arm-msm, linux-remoteproc, Andy Gross
On 2021-08-09 23:28, Stephen Boyd wrote:
> Quoting Deepak Kumar Singh (2021-08-09 04:05:08)
>>
>> On 8/6/2021 1:10 AM, Stephen Boyd wrote:
>> > Quoting Deepak Kumar Singh (2021-08-05 09:17:33)
>> >> Some use cases require SMP2P interrupts to wake up the host
>> >> from suspend.
>> > Please elaborate on this point so we understand what sort of scenarios
>> > want to wakeup from suspend.
>>
>> Once such scenario is where WiFi/modem crashes and notifies crash to
>> local host through smp2p
>>
>> if local host is in suspend it should wake up to handle the crash and
>> reboot the WiFi/modem.
>
> Does anything go wrong if the firmware crashes during suspend and the
> local host doesn't handle it until it wakes for some other reason? I'd
> like to understand if the crash handling can be delayed/combined with
> another wakeup.
If the modem firmware crashes
during suspend, the system comes
out of xo-shutdown and AFAIK stays
there until we handle the interrupt.
>
>>
>> >> Mark smp2p interrupt as wakeup capable to abort
>> >> the suspend.
>> >>
>> >> Signed-off-by: Deepak Kumar Singh <deesin@codeaurora.org>
>> >> ---
>> >> drivers/soc/qcom/smp2p.c | 11 +++++++++++
>> >> 1 file changed, 11 insertions(+)
>> >>
>> >> diff --git a/drivers/soc/qcom/smp2p.c b/drivers/soc/qcom/smp2p.c
>> >> index 2df4883..f8659b0 100644
>> >> --- a/drivers/soc/qcom/smp2p.c
>> >> +++ b/drivers/soc/qcom/smp2p.c
>> >> @@ -18,6 +18,7 @@
>> >> #include <linux/soc/qcom/smem.h>
>> >> #include <linux/soc/qcom/smem_state.h>
>> >> #include <linux/spinlock.h>
>> >> +#include <linux/pm_wakeirq.h>
>> >>
>> >> /*
>> >> * The Shared Memory Point to Point (SMP2P) protocol facilitates communication
>> >> @@ -538,9 +539,19 @@ static int qcom_smp2p_probe(struct platform_device *pdev)
>> >> goto unwind_interfaces;
>> >> }
>> >>
>> >> + ret = device_init_wakeup(&pdev->dev, true);
>> > Is smp2p supposed to wake up the device by default? If not, then this
>> > should be device_set_wakeup_capable() instead so that userspace can
>> > decide if it wants to get the wakeup.
>> yes, we want smp2p to be wake up capable by default.
>
> Why?
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply [relevance 6%]
* Re: [PATCH 2/4] cpufreq: qcom: Re-arrange register offsets to support per core L3 DCVS
2021-08-05 18:25 0% ` Stephen Boyd
@ 2021-08-06 6:42 6% ` Sibi Sankar
0 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-08-06 6:42 UTC (permalink / raw)
To: Stephen Boyd
Cc: bjorn.andersson, mka, robh+dt, viresh.kumar, agross, rjw,
linux-arm-msm, devicetree, linux-kernel, linux-pm, dianders,
tdas
On 2021-08-05 23:55, Stephen Boyd wrote:
> Quoting Sibi Sankar (2021-08-05 10:47:20)
>> Stephen,
>>
>> Thanks for taking time to review
>> the series.
>>
>> On 2021-08-05 00:31, Stephen Boyd wrote:
>> > Quoting Sibi Sankar (2021-07-29 11:04:43)
>> >> Qualcomm SoCs (starting with SM8350) support per core voting for L3
>> >> cache
>> >> frequency.
>> >
>> > And the L3 cache frequency voting code can't be put into this cpufreq
>> > driver?
>>
>> Yes, it could have gone either into
>> the cpufreq driver or l3 interconnect
>> provider driver. Taniya/Odelu preferred
>> the latter, because of the need for other
>> clients to vote for l3 frequencies in
>> the future.
>
> What other clients are those?
https://lore.kernel.org/lkml/20190814152116.GB28465@jcrouse1-lnx.qualcomm.com/
GPU was supposed to be one of the
other clients that would vote for
l3.
>
>> The other option to prevent
>> register re-arrangement would involve
>> using syscons from the cpufreq node, which
>> really wasn't necessary since there
>> wasn't any register overlap between the
>> two drivers.
>
> Let's not do that.
>
>>
>> >
>> >> So, re-arrange the cpufreq register offsets to allow access for
>> >> the L3 interconnect to implement per core control. Also prevent
>> >> binding
>> >> breakage caused by register offset shuffling by using the
>> >> SM8250/SM8350
>> >> EPSS compatible.
>> >>
>> >> Fixes: 7dbd121a2c58 ("arm64: dts: qcom: sc7280: Add cpufreq hw node")
>> >> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
>> >> ---
>> >> drivers/cpufreq/qcom-cpufreq-hw.c | 23 +++++++++++++++++++----
>> >> 1 file changed, 19 insertions(+), 4 deletions(-)
>> >>
>> >> diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c
>> >> b/drivers/cpufreq/qcom-cpufreq-hw.c
>> >> index f86859bf76f1..74ef3b38343b 100644
>> >> --- a/drivers/cpufreq/qcom-cpufreq-hw.c
>> >> +++ b/drivers/cpufreq/qcom-cpufreq-hw.c
>> >> @@ -28,6 +28,7 @@ struct qcom_cpufreq_soc_data {
>> >> u32 reg_volt_lut;
>> >> u32 reg_perf_state;
>> >> u8 lut_row_size;
>> >> + bool skip_enable;
>> >> };
>> >>
>> >> struct qcom_cpufreq_data {
>> >> @@ -257,19 +258,31 @@ static const struct qcom_cpufreq_soc_data
>> >> qcom_soc_data = {
>> >> .reg_volt_lut = 0x114,
>> >> .reg_perf_state = 0x920,
>> >> .lut_row_size = 32,
>> >> + .skip_enable = false,
>> >> };
>> >>
>> >> static const struct qcom_cpufreq_soc_data epss_soc_data = {
>> >> + .reg_freq_lut = 0x0,
>> >> + .reg_volt_lut = 0x100,
>> >> + .reg_perf_state = 0x220,
>> >> + .lut_row_size = 4,
>> >> + .skip_enable = true,
>> >> +};
>> >> +
>> >> +static const struct qcom_cpufreq_soc_data epss_sm8250_soc_data = {
>> >> .reg_enable = 0x0,
>> >> .reg_freq_lut = 0x100,
>> >> .reg_volt_lut = 0x200,
>> >> .reg_perf_state = 0x320,
>> >> .lut_row_size = 4,
>> >> + .skip_enable = false,
>> >> };
>> >>
>> >> static const struct of_device_id qcom_cpufreq_hw_match[] = {
>> >> { .compatible = "qcom,cpufreq-hw", .data = &qcom_soc_data },
>> >> { .compatible = "qcom,cpufreq-epss", .data = &epss_soc_data },
>> >> + { .compatible = "qcom,sm8250-cpufreq-epss", .data =
>> >> &epss_sm8250_soc_data },
>> >> + { .compatible = "qcom,sm8350-cpufreq-epss", .data =
>> >> &epss_sm8250_soc_data },
>> >> {}
>> >> };
>> >> MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match);
>> >> @@ -334,10 +347,12 @@ static int qcom_cpufreq_hw_cpu_init(struct
>> >> cpufreq_policy *policy)
>> >> data->res = res;
>> >>
>> >> /* HW should be in enabled state to proceed */
>> >
>> > It looks odd that we're no longer making sure that the clk domain is
>> > enabled when we probe the driver. Why is that OK?
>>
>> On newer EPSS hw it's no longer
>> required to perform the additional
>> hw enable check. IIRC we don't do
>> that on corresponding downstream
>> kernels as well.
>
> It's fairly clear that we no longer perform the additional check. The
> question is why that's OK.
Taniya probably would know more
about the history behind the change.
I'll dig up more info regarding ^^
and update the thread.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply [relevance 6%]
* Re: [PATCH 2/4] cpufreq: qcom: Re-arrange register offsets to support per core L3 DCVS
2021-08-05 17:47 6% ` Sibi Sankar
@ 2021-08-05 18:25 0% ` Stephen Boyd
2021-08-06 6:42 6% ` Sibi Sankar
0 siblings, 1 reply; 200+ results
From: Stephen Boyd @ 2021-08-05 18:25 UTC (permalink / raw)
To: Sibi Sankar
Cc: bjorn.andersson, mka, robh+dt, viresh.kumar, agross, rjw,
linux-arm-msm, devicetree, linux-kernel, linux-pm, dianders,
tdas
Quoting Sibi Sankar (2021-08-05 10:47:20)
> Stephen,
>
> Thanks for taking time to review
> the series.
>
> On 2021-08-05 00:31, Stephen Boyd wrote:
> > Quoting Sibi Sankar (2021-07-29 11:04:43)
> >> Qualcomm SoCs (starting with SM8350) support per core voting for L3
> >> cache
> >> frequency.
> >
> > And the L3 cache frequency voting code can't be put into this cpufreq
> > driver?
>
> Yes, it could have gone either into
> the cpufreq driver or l3 interconnect
> provider driver. Taniya/Odelu preferred
> the latter, because of the need for other
> clients to vote for l3 frequencies in
> the future.
What other clients are those?
> The other option to prevent
> register re-arrangement would involve
> using syscons from the cpufreq node, which
> really wasn't necessary since there
> wasn't any register overlap between the
> two drivers.
Let's not do that.
>
> >
> >> So, re-arrange the cpufreq register offsets to allow access for
> >> the L3 interconnect to implement per core control. Also prevent
> >> binding
> >> breakage caused by register offset shuffling by using the
> >> SM8250/SM8350
> >> EPSS compatible.
> >>
> >> Fixes: 7dbd121a2c58 ("arm64: dts: qcom: sc7280: Add cpufreq hw node")
> >> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> >> ---
> >> drivers/cpufreq/qcom-cpufreq-hw.c | 23 +++++++++++++++++++----
> >> 1 file changed, 19 insertions(+), 4 deletions(-)
> >>
> >> diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c
> >> b/drivers/cpufreq/qcom-cpufreq-hw.c
> >> index f86859bf76f1..74ef3b38343b 100644
> >> --- a/drivers/cpufreq/qcom-cpufreq-hw.c
> >> +++ b/drivers/cpufreq/qcom-cpufreq-hw.c
> >> @@ -28,6 +28,7 @@ struct qcom_cpufreq_soc_data {
> >> u32 reg_volt_lut;
> >> u32 reg_perf_state;
> >> u8 lut_row_size;
> >> + bool skip_enable;
> >> };
> >>
> >> struct qcom_cpufreq_data {
> >> @@ -257,19 +258,31 @@ static const struct qcom_cpufreq_soc_data
> >> qcom_soc_data = {
> >> .reg_volt_lut = 0x114,
> >> .reg_perf_state = 0x920,
> >> .lut_row_size = 32,
> >> + .skip_enable = false,
> >> };
> >>
> >> static const struct qcom_cpufreq_soc_data epss_soc_data = {
> >> + .reg_freq_lut = 0x0,
> >> + .reg_volt_lut = 0x100,
> >> + .reg_perf_state = 0x220,
> >> + .lut_row_size = 4,
> >> + .skip_enable = true,
> >> +};
> >> +
> >> +static const struct qcom_cpufreq_soc_data epss_sm8250_soc_data = {
> >> .reg_enable = 0x0,
> >> .reg_freq_lut = 0x100,
> >> .reg_volt_lut = 0x200,
> >> .reg_perf_state = 0x320,
> >> .lut_row_size = 4,
> >> + .skip_enable = false,
> >> };
> >>
> >> static const struct of_device_id qcom_cpufreq_hw_match[] = {
> >> { .compatible = "qcom,cpufreq-hw", .data = &qcom_soc_data },
> >> { .compatible = "qcom,cpufreq-epss", .data = &epss_soc_data },
> >> + { .compatible = "qcom,sm8250-cpufreq-epss", .data =
> >> &epss_sm8250_soc_data },
> >> + { .compatible = "qcom,sm8350-cpufreq-epss", .data =
> >> &epss_sm8250_soc_data },
> >> {}
> >> };
> >> MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match);
> >> @@ -334,10 +347,12 @@ static int qcom_cpufreq_hw_cpu_init(struct
> >> cpufreq_policy *policy)
> >> data->res = res;
> >>
> >> /* HW should be in enabled state to proceed */
> >
> > It looks odd that we're no longer making sure that the clk domain is
> > enabled when we probe the driver. Why is that OK?
>
> On newer EPSS hw it's no longer
> required to perform the additional
> hw enable check. IIRC we don't do
> that on corresponding downstream
> kernels as well.
It's fairly clear that we no longer perform the additional check. The
question is why that's OK.
^ permalink raw reply [relevance 0%]
* Re: [PATCH 2/4] cpufreq: qcom: Re-arrange register offsets to support per core L3 DCVS
2021-08-04 19:01 0% ` Stephen Boyd
@ 2021-08-05 17:47 6% ` Sibi Sankar
2021-08-05 18:25 0% ` Stephen Boyd
0 siblings, 1 reply; 200+ results
From: Sibi Sankar @ 2021-08-05 17:47 UTC (permalink / raw)
To: Stephen Boyd
Cc: bjorn.andersson, mka, robh+dt, viresh.kumar, agross, rjw,
linux-arm-msm, devicetree, linux-kernel, linux-pm, dianders,
tdas
Stephen,
Thanks for taking time to review
the series.
On 2021-08-05 00:31, Stephen Boyd wrote:
> Quoting Sibi Sankar (2021-07-29 11:04:43)
>> Qualcomm SoCs (starting with SM8350) support per core voting for L3
>> cache
>> frequency.
>
> And the L3 cache frequency voting code can't be put into this cpufreq
> driver?
Yes, it could have gone either into
the cpufreq driver or l3 interconnect
provider driver. Taniya/Odelu preferred
the latter, because of the need for other
clients to vote for l3 frequencies in
the future. The other option to prevent
register re-arrangement would involve
using syscons from the cpufreq node, which
really wasn't necessary since there
wasn't any register overlap between the
two drivers.
>
>> So, re-arrange the cpufreq register offsets to allow access for
>> the L3 interconnect to implement per core control. Also prevent
>> binding
>> breakage caused by register offset shuffling by using the
>> SM8250/SM8350
>> EPSS compatible.
>>
>> Fixes: 7dbd121a2c58 ("arm64: dts: qcom: sc7280: Add cpufreq hw node")
>> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
>> ---
>> drivers/cpufreq/qcom-cpufreq-hw.c | 23 +++++++++++++++++++----
>> 1 file changed, 19 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c
>> b/drivers/cpufreq/qcom-cpufreq-hw.c
>> index f86859bf76f1..74ef3b38343b 100644
>> --- a/drivers/cpufreq/qcom-cpufreq-hw.c
>> +++ b/drivers/cpufreq/qcom-cpufreq-hw.c
>> @@ -28,6 +28,7 @@ struct qcom_cpufreq_soc_data {
>> u32 reg_volt_lut;
>> u32 reg_perf_state;
>> u8 lut_row_size;
>> + bool skip_enable;
>> };
>>
>> struct qcom_cpufreq_data {
>> @@ -257,19 +258,31 @@ static const struct qcom_cpufreq_soc_data
>> qcom_soc_data = {
>> .reg_volt_lut = 0x114,
>> .reg_perf_state = 0x920,
>> .lut_row_size = 32,
>> + .skip_enable = false,
>> };
>>
>> static const struct qcom_cpufreq_soc_data epss_soc_data = {
>> + .reg_freq_lut = 0x0,
>> + .reg_volt_lut = 0x100,
>> + .reg_perf_state = 0x220,
>> + .lut_row_size = 4,
>> + .skip_enable = true,
>> +};
>> +
>> +static const struct qcom_cpufreq_soc_data epss_sm8250_soc_data = {
>> .reg_enable = 0x0,
>> .reg_freq_lut = 0x100,
>> .reg_volt_lut = 0x200,
>> .reg_perf_state = 0x320,
>> .lut_row_size = 4,
>> + .skip_enable = false,
>> };
>>
>> static const struct of_device_id qcom_cpufreq_hw_match[] = {
>> { .compatible = "qcom,cpufreq-hw", .data = &qcom_soc_data },
>> { .compatible = "qcom,cpufreq-epss", .data = &epss_soc_data },
>> + { .compatible = "qcom,sm8250-cpufreq-epss", .data =
>> &epss_sm8250_soc_data },
>> + { .compatible = "qcom,sm8350-cpufreq-epss", .data =
>> &epss_sm8250_soc_data },
>> {}
>> };
>> MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match);
>> @@ -334,10 +347,12 @@ static int qcom_cpufreq_hw_cpu_init(struct
>> cpufreq_policy *policy)
>> data->res = res;
>>
>> /* HW should be in enabled state to proceed */
>
> It looks odd that we're no longer making sure that the clk domain is
> enabled when we probe the driver. Why is that OK?
On newer EPSS hw it's no longer
required to perform the additional
hw enable check. IIRC we don't do
that on corresponding downstream
kernels as well.
>
>> - if (!(readl_relaxed(base + data->soc_data->reg_enable) & 0x1))
>> {
>> - dev_err(dev, "Domain-%d cpufreq hardware not
>> enabled\n", index);
>> - ret = -ENODEV;
>> - goto error;
>> + if (!data->soc_data->skip_enable) {
>> + if (!(readl_relaxed(base + data->soc_data->reg_enable)
>> & 0x1)) {
>> + dev_err(dev, "Domain-%d cpufreq hardware not
>> enabled\n", index);
>> + ret = -ENODEV;
>> + goto error;
>> + }
>> }
>>
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply [relevance 6%]
* Re: [PATCH 2/4] cpufreq: qcom: Re-arrange register offsets to support per core L3 DCVS
2021-08-04 23:11 0% ` Bjorn Andersson
@ 2021-08-04 23:20 0% ` Bjorn Andersson
0 siblings, 0 replies; 200+ results
From: Bjorn Andersson @ 2021-08-04 23:20 UTC (permalink / raw)
To: Sibi Sankar
Cc: sboyd, robh+dt, mka, viresh.kumar, agross, rjw, linux-arm-msm,
devicetree, linux-kernel, linux-pm, dianders, tdas
On Wed 04 Aug 18:11 CDT 2021, Bjorn Andersson wrote:
> On Thu 29 Jul 13:04 CDT 2021, Sibi Sankar wrote:
>
> > Qualcomm SoCs (starting with SM8350) support per core voting for L3 cache
> > frequency. So, re-arrange the cpufreq register offsets to allow access for
> > the L3 interconnect to implement per core control. Also prevent binding
> > breakage caused by register offset shuffling by using the SM8250/SM8350
> > EPSS compatible.
> >
> > Fixes: 7dbd121a2c58 ("arm64: dts: qcom: sc7280: Add cpufreq hw node")
> > Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> > ---
> > drivers/cpufreq/qcom-cpufreq-hw.c | 23 +++++++++++++++++++----
> > 1 file changed, 19 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c
> > index f86859bf76f1..74ef3b38343b 100644
> > --- a/drivers/cpufreq/qcom-cpufreq-hw.c
> > +++ b/drivers/cpufreq/qcom-cpufreq-hw.c
> > @@ -28,6 +28,7 @@ struct qcom_cpufreq_soc_data {
> > u32 reg_volt_lut;
> > u32 reg_perf_state;
> > u8 lut_row_size;
> > + bool skip_enable;
>
> This should probably be called "skip_enable_check".
>
> > };
> >
> > struct qcom_cpufreq_data {
> > @@ -257,19 +258,31 @@ static const struct qcom_cpufreq_soc_data qcom_soc_data = {
> > .reg_volt_lut = 0x114,
> > .reg_perf_state = 0x920,
> > .lut_row_size = 32,
> > + .skip_enable = false,
> > };
> >
> > static const struct qcom_cpufreq_soc_data epss_soc_data = {
> > + .reg_freq_lut = 0x0,
> > + .reg_volt_lut = 0x100,
> > + .reg_perf_state = 0x220,
> > + .lut_row_size = 4,
> > + .skip_enable = true,
>
> This change is not compatible with existing DTBs.
>
Continued staring at this after I sent my response, and I'm confused.
You're say in the commit message that SM8350 and beyond needs access to
some registers in the first 0x100 bytes of the register space. So
therefor you're changing the fallback, which is only used for sc7280...
In other words, you break the compatibility with the existing sc7280
dtb and leave sm8350 unchanged - after saying that this change is for
the sake of sm8350.
Lastly, why is "the L3 frequency" an interconnect and not a clock? (And
why don't we make the cpufreq driver a clock-controller for the
platforms that has this?)
Regards,
Bjorn
> Regards,
> Bjorn
>
> > +};
> > +
> > +static const struct qcom_cpufreq_soc_data epss_sm8250_soc_data = {
> > .reg_enable = 0x0,
> > .reg_freq_lut = 0x100,
> > .reg_volt_lut = 0x200,
> > .reg_perf_state = 0x320,
> > .lut_row_size = 4,
> > + .skip_enable = false,
> > };
> >
> > static const struct of_device_id qcom_cpufreq_hw_match[] = {
> > { .compatible = "qcom,cpufreq-hw", .data = &qcom_soc_data },
> > { .compatible = "qcom,cpufreq-epss", .data = &epss_soc_data },
> > + { .compatible = "qcom,sm8250-cpufreq-epss", .data = &epss_sm8250_soc_data },
> > + { .compatible = "qcom,sm8350-cpufreq-epss", .data = &epss_sm8250_soc_data },
> > {}
> > };
> > MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match);
> > @@ -334,10 +347,12 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy)
> > data->res = res;
> >
> > /* HW should be in enabled state to proceed */
> > - if (!(readl_relaxed(base + data->soc_data->reg_enable) & 0x1)) {
> > - dev_err(dev, "Domain-%d cpufreq hardware not enabled\n", index);
> > - ret = -ENODEV;
> > - goto error;
> > + if (!data->soc_data->skip_enable) {
> > + if (!(readl_relaxed(base + data->soc_data->reg_enable) & 0x1)) {
> > + dev_err(dev, "Domain-%d cpufreq hardware not enabled\n", index);
> > + ret = -ENODEV;
> > + goto error;
> > + }
> > }
> >
> > qcom_get_related_cpus(index, policy->cpus);
> > --
> > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> > a Linux Foundation Collaborative Project
> >
^ permalink raw reply [relevance 0%]
* Re: [PATCH 2/4] cpufreq: qcom: Re-arrange register offsets to support per core L3 DCVS
2021-07-29 18:04 17% ` [PATCH 2/4] cpufreq: qcom: Re-arrange register offsets to support per core L3 DCVS Sibi Sankar
2021-08-04 19:01 0% ` Stephen Boyd
@ 2021-08-04 23:11 0% ` Bjorn Andersson
2021-08-04 23:20 0% ` Bjorn Andersson
1 sibling, 1 reply; 200+ results
From: Bjorn Andersson @ 2021-08-04 23:11 UTC (permalink / raw)
To: Sibi Sankar
Cc: sboyd, robh+dt, mka, viresh.kumar, agross, rjw, linux-arm-msm,
devicetree, linux-kernel, linux-pm, dianders, tdas
On Thu 29 Jul 13:04 CDT 2021, Sibi Sankar wrote:
> Qualcomm SoCs (starting with SM8350) support per core voting for L3 cache
> frequency. So, re-arrange the cpufreq register offsets to allow access for
> the L3 interconnect to implement per core control. Also prevent binding
> breakage caused by register offset shuffling by using the SM8250/SM8350
> EPSS compatible.
>
> Fixes: 7dbd121a2c58 ("arm64: dts: qcom: sc7280: Add cpufreq hw node")
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
> drivers/cpufreq/qcom-cpufreq-hw.c | 23 +++++++++++++++++++----
> 1 file changed, 19 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c
> index f86859bf76f1..74ef3b38343b 100644
> --- a/drivers/cpufreq/qcom-cpufreq-hw.c
> +++ b/drivers/cpufreq/qcom-cpufreq-hw.c
> @@ -28,6 +28,7 @@ struct qcom_cpufreq_soc_data {
> u32 reg_volt_lut;
> u32 reg_perf_state;
> u8 lut_row_size;
> + bool skip_enable;
This should probably be called "skip_enable_check".
> };
>
> struct qcom_cpufreq_data {
> @@ -257,19 +258,31 @@ static const struct qcom_cpufreq_soc_data qcom_soc_data = {
> .reg_volt_lut = 0x114,
> .reg_perf_state = 0x920,
> .lut_row_size = 32,
> + .skip_enable = false,
> };
>
> static const struct qcom_cpufreq_soc_data epss_soc_data = {
> + .reg_freq_lut = 0x0,
> + .reg_volt_lut = 0x100,
> + .reg_perf_state = 0x220,
> + .lut_row_size = 4,
> + .skip_enable = true,
This change is not compatible with existing DTBs.
Regards,
Bjorn
> +};
> +
> +static const struct qcom_cpufreq_soc_data epss_sm8250_soc_data = {
> .reg_enable = 0x0,
> .reg_freq_lut = 0x100,
> .reg_volt_lut = 0x200,
> .reg_perf_state = 0x320,
> .lut_row_size = 4,
> + .skip_enable = false,
> };
>
> static const struct of_device_id qcom_cpufreq_hw_match[] = {
> { .compatible = "qcom,cpufreq-hw", .data = &qcom_soc_data },
> { .compatible = "qcom,cpufreq-epss", .data = &epss_soc_data },
> + { .compatible = "qcom,sm8250-cpufreq-epss", .data = &epss_sm8250_soc_data },
> + { .compatible = "qcom,sm8350-cpufreq-epss", .data = &epss_sm8250_soc_data },
> {}
> };
> MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match);
> @@ -334,10 +347,12 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy)
> data->res = res;
>
> /* HW should be in enabled state to proceed */
> - if (!(readl_relaxed(base + data->soc_data->reg_enable) & 0x1)) {
> - dev_err(dev, "Domain-%d cpufreq hardware not enabled\n", index);
> - ret = -ENODEV;
> - goto error;
> + if (!data->soc_data->skip_enable) {
> + if (!(readl_relaxed(base + data->soc_data->reg_enable) & 0x1)) {
> + dev_err(dev, "Domain-%d cpufreq hardware not enabled\n", index);
> + ret = -ENODEV;
> + goto error;
> + }
> }
>
> qcom_get_related_cpus(index, policy->cpus);
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
^ permalink raw reply [relevance 0%]
* Re: [PATCH 4/4] arm64: dts: qcom: sm8350: Fixup the cpufreq node
2021-07-29 18:04 19% ` [PATCH 4/4] arm64: dts: qcom: sm8350: " Sibi Sankar
@ 2021-08-04 22:59 0% ` Bjorn Andersson
0 siblings, 1 reply; 200+ results
From: Bjorn Andersson @ 2021-08-04 22:59 UTC (permalink / raw)
To: Sibi Sankar
Cc: sboyd, robh+dt, mka, viresh.kumar, agross, rjw, linux-arm-msm,
devicetree, linux-kernel, linux-pm, dianders, tdas
On Thu 29 Jul 13:04 CDT 2021, Sibi Sankar wrote:
> Fixup the register regions used by the cpufreq node on SM8350 SoC to
> support per core L3 DCVS.
>
That sounds good, but why are you dropping the platform-specific
compatible?
Regards,
Bjorn
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
> arch/arm64/boot/dts/qcom/sm8350.dtsi | 9 ++++-----
> 1 file changed, 4 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> index a631d58166b1..d0a5a5568602 100644
> --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> @@ -967,11 +967,10 @@
> };
>
> cpufreq_hw: cpufreq@18591000 {
> - compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss";
> - reg = <0 0x18591000 0 0x1000>,
> - <0 0x18592000 0 0x1000>,
> - <0 0x18593000 0 0x1000>;
> - reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
> + compatible = "qcom,cpufreq-epss";
> + reg = <0 0x18591100 0 0x900>,
> + <0 0x18592100 0 0x900>,
> + <0 0x18593100 0 0x900>;
>
> clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
> clock-names = "xo", "alternate";
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
^ permalink raw reply [relevance 0%]
* Re: [PATCH v4 2/2] soc: qcom: aoss: Add debugfs entry
@ 2021-08-04 19:06 0% ` Bjorn Andersson
0 siblings, 0 replies; 200+ results
From: Bjorn Andersson @ 2021-08-04 19:06 UTC (permalink / raw)
To: Sibi Sankar
Cc: agross, linux-kernel, linux-arm-msm, swboyd,
manivannan.sadhasivam, Deepak Kumar Singh, Chris Lew
On Wed 09 Jun 06:18 CDT 2021, Sibi Sankar wrote:
> From: Deepak Kumar Singh <deesin@codeaurora.org>
>
> It can be useful to control the different power states of various
> parts of hardware for device testing. Add a debugfs node for qmp so
> messages can be sent to aoss for debugging and testing purposes.
>
I thought I replied to this patch, but can't find the reply...
> Signed-off-by: Chris Lew <clew@codeaurora.org>
> Signed-off-by: Deepak Kumar Singh <deesin@codeaurora.org>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
> drivers/soc/qcom/qcom_aoss.c | 39 +++++++++++++++++++++++++++++++++++++++
> 1 file changed, 39 insertions(+)
>
> diff --git a/drivers/soc/qcom/qcom_aoss.c b/drivers/soc/qcom/qcom_aoss.c
> index e8f48760bac8..998ee7605eb2 100644
> --- a/drivers/soc/qcom/qcom_aoss.c
> +++ b/drivers/soc/qcom/qcom_aoss.c
> @@ -4,6 +4,7 @@
> */
> #include <dt-bindings/power/qcom-aoss-qmp.h>
> #include <linux/clk-provider.h>
> +#include <linux/debugfs.h>
> #include <linux/interrupt.h>
> #include <linux/io.h>
> #include <linux/mailbox_client.h>
> @@ -89,6 +90,9 @@ struct qmp {
> struct clk_hw qdss_clk;
> struct genpd_onecell_data pd_data;
> struct qmp_cooling_device *cooling_devs;
> +#if IS_ENABLED(CONFIG_DEBUG_FS)
> + struct dentry *debugfs_file;
> +#endif /* CONFIG_DEBUG_FS */
> };
>
> struct qmp_pd {
> @@ -575,6 +579,32 @@ void qmp_put(struct qmp *qmp)
> }
> EXPORT_SYMBOL(qmp_put);
>
> +#if IS_ENABLED(CONFIG_DEBUG_FS)
> +static ssize_t aoss_dbg_write(struct file *file, const char __user *userstr,
> + size_t len, loff_t *pos)
> +{
> + struct qmp *qmp = file->private_data;
> + char buf[QMP_MSG_LEN] = {};
> + int ret;
> +
> + if (!len || len >= QMP_MSG_LEN)
> + return len;
> +
> + ret = copy_from_user(buf, userstr, len);
> + if (ret)
> + return len;
> +
> + ret = qmp_send(qmp, buf, QMP_MSG_LEN);
> +
> + return ret ? ret : len;
> +}
> +
> +static const struct file_operations aoss_dbg_fops = {
> + .open = simple_open,
> + .write = aoss_dbg_write,
> +};
> +#endif /* CONFIG_DEBUG_FS */
> +
> static int qmp_probe(struct platform_device *pdev)
> {
> struct resource *res;
> @@ -632,6 +662,11 @@ static int qmp_probe(struct platform_device *pdev)
>
> atomic_set(&qmp->orphan, 0);
>
> +#if IS_ENABLED(CONFIG_DEBUG_FS)
> + qmp->debugfs_file = debugfs_create_file("aoss_send_message", 0220, NULL,
> + qmp, &aoss_dbg_fops);
> +#endif /* CONFIG_DEBUG_FS */
You shouldn't need the guards, debugfs_create_file() is stubbed if
CONFIG_DEBUG_FS isn't set, so it's better to just rely on that.
Regards,
Bjorn
> +
> return 0;
>
> err_remove_qdss_clk:
> @@ -649,6 +684,10 @@ static int qmp_remove(struct platform_device *pdev)
> {
> struct qmp *qmp = platform_get_drvdata(pdev);
>
> +#if IS_ENABLED(CONFIG_DEBUG_FS)
> + debugfs_remove(qmp->debugfs_file);
> +#endif /* CONFIG_DEBUG_FS */
> +
> qmp_qdss_clk_remove(qmp);
> qmp_pd_remove(qmp);
> qmp_cooling_devices_remove(qmp);
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
^ permalink raw reply [relevance 0%]
* Re: [PATCH 2/4] cpufreq: qcom: Re-arrange register offsets to support per core L3 DCVS
2021-07-29 18:04 17% ` [PATCH 2/4] cpufreq: qcom: Re-arrange register offsets to support per core L3 DCVS Sibi Sankar
@ 2021-08-04 19:01 0% ` Stephen Boyd
2021-08-05 17:47 6% ` Sibi Sankar
2021-08-04 23:11 0% ` Bjorn Andersson
1 sibling, 1 reply; 200+ results
From: Stephen Boyd @ 2021-08-04 19:01 UTC (permalink / raw)
To: Sibi Sankar, bjorn.andersson, mka, robh+dt
Cc: viresh.kumar, agross, rjw, linux-arm-msm, devicetree,
linux-kernel, linux-pm, dianders, tdas
Quoting Sibi Sankar (2021-07-29 11:04:43)
> Qualcomm SoCs (starting with SM8350) support per core voting for L3 cache
> frequency.
And the L3 cache frequency voting code can't be put into this cpufreq
driver?
> So, re-arrange the cpufreq register offsets to allow access for
> the L3 interconnect to implement per core control. Also prevent binding
> breakage caused by register offset shuffling by using the SM8250/SM8350
> EPSS compatible.
>
> Fixes: 7dbd121a2c58 ("arm64: dts: qcom: sc7280: Add cpufreq hw node")
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
> drivers/cpufreq/qcom-cpufreq-hw.c | 23 +++++++++++++++++++----
> 1 file changed, 19 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c
> index f86859bf76f1..74ef3b38343b 100644
> --- a/drivers/cpufreq/qcom-cpufreq-hw.c
> +++ b/drivers/cpufreq/qcom-cpufreq-hw.c
> @@ -28,6 +28,7 @@ struct qcom_cpufreq_soc_data {
> u32 reg_volt_lut;
> u32 reg_perf_state;
> u8 lut_row_size;
> + bool skip_enable;
> };
>
> struct qcom_cpufreq_data {
> @@ -257,19 +258,31 @@ static const struct qcom_cpufreq_soc_data qcom_soc_data = {
> .reg_volt_lut = 0x114,
> .reg_perf_state = 0x920,
> .lut_row_size = 32,
> + .skip_enable = false,
> };
>
> static const struct qcom_cpufreq_soc_data epss_soc_data = {
> + .reg_freq_lut = 0x0,
> + .reg_volt_lut = 0x100,
> + .reg_perf_state = 0x220,
> + .lut_row_size = 4,
> + .skip_enable = true,
> +};
> +
> +static const struct qcom_cpufreq_soc_data epss_sm8250_soc_data = {
> .reg_enable = 0x0,
> .reg_freq_lut = 0x100,
> .reg_volt_lut = 0x200,
> .reg_perf_state = 0x320,
> .lut_row_size = 4,
> + .skip_enable = false,
> };
>
> static const struct of_device_id qcom_cpufreq_hw_match[] = {
> { .compatible = "qcom,cpufreq-hw", .data = &qcom_soc_data },
> { .compatible = "qcom,cpufreq-epss", .data = &epss_soc_data },
> + { .compatible = "qcom,sm8250-cpufreq-epss", .data = &epss_sm8250_soc_data },
> + { .compatible = "qcom,sm8350-cpufreq-epss", .data = &epss_sm8250_soc_data },
> {}
> };
> MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match);
> @@ -334,10 +347,12 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy)
> data->res = res;
>
> /* HW should be in enabled state to proceed */
It looks odd that we're no longer making sure that the clk domain is
enabled when we probe the driver. Why is that OK?
> - if (!(readl_relaxed(base + data->soc_data->reg_enable) & 0x1)) {
> - dev_err(dev, "Domain-%d cpufreq hardware not enabled\n", index);
> - ret = -ENODEV;
> - goto error;
> + if (!data->soc_data->skip_enable) {
> + if (!(readl_relaxed(base + data->soc_data->reg_enable) & 0x1)) {
> + dev_err(dev, "Domain-%d cpufreq hardware not enabled\n", index);
> + ret = -ENODEV;
> + goto error;
> + }
> }
>
^ permalink raw reply [relevance 0%]
* Re: [PATCH 3/4] arm64: dts: qcom: sc7280: Fixup the cpufreq node
2021-07-29 18:04 19% ` [PATCH 3/4] arm64: dts: qcom: sc7280: Fixup the cpufreq node Sibi Sankar
@ 2021-08-04 18:57 0% ` Stephen Boyd
2021-08-31 15:30 6% ` Matthias Kaehlcke
1 sibling, 0 replies; 200+ results
From: Stephen Boyd @ 2021-08-04 18:57 UTC (permalink / raw)
To: Sibi Sankar, bjorn.andersson, mka, robh+dt
Cc: viresh.kumar, agross, rjw, linux-arm-msm, devicetree,
linux-kernel, linux-pm, dianders, tdas
Quoting Sibi Sankar (2021-07-29 11:04:44)
> Fixup the register regions used by the cpufreq node on SC7280 SoC to
> support per core L3 DCVS.
>
> Fixes: 7dbd121a2c58 ("arm64: dts: qcom: sc7280: Add cpufreq hw node")
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
^ permalink raw reply [relevance 0%]
* Re: [PATCH 1/4] dt-bindings: cpufreq: cpufreq-qcom-hw: Add compatible for SM8250/8350
2021-07-29 18:04 19% ` [PATCH 1/4] dt-bindings: cpufreq: cpufreq-qcom-hw: Add compatible for SM8250/8350 Sibi Sankar
2021-08-03 19:23 0% ` Rob Herring
@ 2021-08-04 18:56 0% ` Stephen Boyd
1 sibling, 0 replies; 200+ results
From: Stephen Boyd @ 2021-08-04 18:56 UTC (permalink / raw)
To: Sibi Sankar, bjorn.andersson, mka, robh+dt
Cc: viresh.kumar, agross, rjw, linux-arm-msm, devicetree,
linux-kernel, linux-pm, dianders, tdas
Quoting Sibi Sankar (2021-07-29 11:04:42)
> Re-arranging the register regions to support per core L3 DCVS would lead
> to bindings breakage when using an older dt with a newer kernel. So,
> document the EPSS compatible for SM8250/SM8350 SoCs and use them in the
> CPUFreq-hw driver to prevent such breakages.
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
^ permalink raw reply [relevance 0%]
* Re: [PATCH 1/4] dt-bindings: cpufreq: cpufreq-qcom-hw: Add compatible for SM8250/8350
2021-07-29 18:04 19% ` [PATCH 1/4] dt-bindings: cpufreq: cpufreq-qcom-hw: Add compatible for SM8250/8350 Sibi Sankar
@ 2021-08-03 19:23 0% ` Rob Herring
2021-08-04 18:56 0% ` Stephen Boyd
1 sibling, 0 replies; 200+ results
From: Rob Herring @ 2021-08-03 19:23 UTC (permalink / raw)
To: Sibi Sankar
Cc: mka, bjorn.andersson, linux-pm, agross, rjw, dianders,
linux-arm-msm, sboyd, tdas, devicetree, viresh.kumar,
linux-kernel, robh+dt
On Thu, 29 Jul 2021 23:34:42 +0530, Sibi Sankar wrote:
> Re-arranging the register regions to support per core L3 DCVS would lead
> to bindings breakage when using an older dt with a newer kernel. So,
> document the EPSS compatible for SM8250/SM8350 SoCs and use them in the
> CPUFreq-hw driver to prevent such breakages.
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
> Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [relevance 0%]
* Re: [PATCH v3 2/2] arm64: dts: qcom: sc7280: Add cpu OPP tables
2021-07-30 22:20 6% ` Doug Anderson
@ 2021-08-02 3:28 13% ` Sibi Sankar
0 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2021-08-02 3:28 UTC (permalink / raw)
To: Doug Anderson
Cc: Bjorn Andersson, Matthias Kaehlcke, Viresh Kumar, Stephen Boyd,
Andy Gross, Rob Herring, Rafael J. Wysocki, linux-arm-msm,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, LKML,
Linux PM
On 2021-07-31 03:50, Doug Anderson wrote:
> Hi,
>
> On Wed, May 12, 2021 at 1:11 AM Sibi Sankar <sibis@codeaurora.org>
> wrote:
>>
>> Add OPP tables required to scale DDR/L3 per freq-domain on SC7280
>> SoCs.
>>
>> Reviewed-by: Douglas Anderson <dianders@chromium.org>
>> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
>> ---
>>
>> V3:
>> * Rename cpu opp table nodes [Matthias]
>> * Rename opp phandles [Doug]
>>
>> Depends on the following patch series:
>> L3 Provider Support:
>> https://lore.kernel.org/lkml/1618556290-28303-1-git-send-email-okukatla@codeaurora.org/
>> CPUfreq Support:
>> https://lore.kernel.org/lkml/1618020280-5470-2-git-send-email-tdas@codeaurora.org/
>> RPMH Provider Support:
>> https://lore.kernel.org/lkml/1619517059-12109-1-git-send-email-okukatla@codeaurora.org/
>>
Doug,
2 of the above 3 dependencies have
landed. L3 provider still needs a
re-spin.
https://patchwork.kernel.org/project/linux-arm-msm/cover/1627581885-32165-1-git-send-email-sibis@codeaurora.org/
We also have a new series ^^ on the
list which will affect #2 merge.
>> It also depends on L3 and cpufreq dt nodes from the ^^ series to not
>> have
>> overlapping memory regions.
>>
>> arch/arm64/boot/dts/qcom/sc7280.dtsi | 215
>> +++++++++++++++++++++++++++++++++++
>> 1 file changed, 215 insertions(+)
>
> I see patch #1 in mainline now. Does that mean it's time to land patch
> #2 in the Qualcomm tree now? ...or maybe it needs to be re-posted?
>
> -Doug
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply [relevance 13%]
* Re: [PATCH v3 2/2] arm64: dts: qcom: sc7280: Add cpu OPP tables
@ 2021-07-30 22:20 6% ` Doug Anderson
2021-08-02 3:28 13% ` Sibi Sankar
0 siblings, 1 reply; 200+ results
From: Doug Anderson @ 2021-07-30 22:20 UTC (permalink / raw)
To: Sibi Sankar
Cc: Bjorn Andersson, Matthias Kaehlcke, Viresh Kumar, Stephen Boyd,
Andy Gross, Rob Herring, Rafael J. Wysocki, linux-arm-msm,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, LKML,
Linux PM
Hi,
On Wed, May 12, 2021 at 1:11 AM Sibi Sankar <sibis@codeaurora.org> wrote:
>
> Add OPP tables required to scale DDR/L3 per freq-domain on SC7280 SoCs.
>
> Reviewed-by: Douglas Anderson <dianders@chromium.org>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
>
> V3:
> * Rename cpu opp table nodes [Matthias]
> * Rename opp phandles [Doug]
>
> Depends on the following patch series:
> L3 Provider Support: https://lore.kernel.org/lkml/1618556290-28303-1-git-send-email-okukatla@codeaurora.org/
> CPUfreq Support: https://lore.kernel.org/lkml/1618020280-5470-2-git-send-email-tdas@codeaurora.org/
> RPMH Provider Support: https://lore.kernel.org/lkml/1619517059-12109-1-git-send-email-okukatla@codeaurora.org/
>
> It also depends on L3 and cpufreq dt nodes from the ^^ series to not have
> overlapping memory regions.
>
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 215 +++++++++++++++++++++++++++++++++++
> 1 file changed, 215 insertions(+)
I see patch #1 in mainline now. Does that mean it's time to land patch
#2 in the Qualcomm tree now? ...or maybe it needs to be re-posted?
-Doug
^ permalink raw reply [relevance 6%]
* Re: [PATCH 9/9] arm64: dts: qcom: sc7280: Update Q6V5 MSS node
@ 2021-07-30 18:14 0% ` Bjorn Andersson
0 siblings, 0 replies; 200+ results
From: Bjorn Andersson @ 2021-07-30 18:14 UTC (permalink / raw)
To: Sibi Sankar
Cc: Matthias Kaehlcke, robh+dt, will, saiprakash.ranjan, ohad,
agross, mathieu.poirier, robin.murphy, joro, p.zabel,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
linux-arm-kernel, evgreen, dianders, swboyd
On Wed 30 Jun 15:08 CDT 2021, Sibi Sankar wrote:
> On 2021-06-29 00:35, Matthias Kaehlcke wrote:
> > On Fri, Jun 25, 2021 at 01:17:38AM +0530, Sibi Sankar wrote:
> > > Update MSS node to support MSA based modem boot on SC7280 SoCs.
> > >
> > > Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> > > ---
> > > arch/arm64/boot/dts/qcom/sc7280-idp.dts | 7 +++++++
> > > arch/arm64/boot/dts/qcom/sc7280.dtsi | 19 ++++++++++++++++---
> > > 2 files changed, 23 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> > > b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> > > index 191e8a92d153..d66e3ca42ad5 100644
> > > --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> > > +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> > > @@ -343,3 +343,10 @@
> > > bias-pull-up;
> > > };
> > > };
> > > +
> > > +&remoteproc_mpss {
> > > + status = "okay";
> > > + compatible = "qcom,sc7280-mss-pil";
> > > + iommus = <&apps_smmu 0x124 0x0>, <&apps_smmu 0x488 0x7>;
> > > + memory-region = <&mba_mem &mpss_mem>;
> > > +};
> > > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > > b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > > index 56ea172f641f..6d3687744440 100644
> > > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > > @@ -586,7 +586,8 @@
> > >
> > > remoteproc_mpss: remoteproc@4080000 {
> > > compatible = "qcom,sc7280-mpss-pas";
> > > - reg = <0 0x04080000 0 0x10000>;
> > > + reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>;
> > > + reg-names = "qdsp6", "rmb";
> >
> > Binding needs update?
> >
> > Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml:
> >
> > reg:
> > maxItems: 1
> >
> > >
> > > interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
> > > <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
> > > @@ -597,8 +598,11 @@
> > > interrupt-names = "wdog", "fatal", "ready", "handover",
> > > "stop-ack", "shutdown-ack";
> > >
> > > - clocks = <&rpmhcc RPMH_CXO_CLK>;
> > > - clock-names = "xo";
> > > + clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
> > > + <&gcc GCC_MSS_OFFLINE_AXI_CLK>,
> > > + <&gcc GCC_MSS_SNOC_AXI_CLK>,
> > > + <&rpmhcc RPMH_CXO_CLK>;
> > > + clock-names = "iface", "offline", "snoc_axi", "xo";
> >
> > Binding needs update?
> >
> > Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml:
> >
> > clocks:
> > items:
> > - description: XO clock
> > clock-names:
> > items:
> > - const: xo
>
> qcom,sc7280-mpss-pas compatible requires
> just the xo clock and one reg space whereas
> the qcom,sc7280-mss-pil compatible requires
> the additional clks and reg spaces. We just
> overload properties where re-use is possible
> across boards. Hence it would be wrong to
> list those clks/reg spaces as requirements
> for the pas compatible.
>
Our decision to describe the platform node as a superset of the
resources needed by the pas and pil variants was never reflected in the
DT bindings; resulting in the issue that the superset doesn't validate
against the pas binding and both bindings are full of platform-specific
conditionals.
To resolve the two issues I think we should split the current binding(s)
in a set of platform-centric bindings, that captures the idea of
describing the superset.
To reduce the duplication - that already exists between the two
bindings - I think we should break those out in a common part.
I'm however fine with not delaying this series further, if we agree that
the end result matches what we would put in a combined qcom,sc7280-mpss
binding.
Regards,
Bjorn
^ permalink raw reply [relevance 0%]
* Re: [PATCH 8/9] arm64: dts: qcom: sc7280: Add Q6V5 MSS node
@ 2021-07-30 18:01 0% ` Bjorn Andersson
0 siblings, 0 replies; 200+ results
From: Bjorn Andersson @ 2021-07-30 18:01 UTC (permalink / raw)
To: Sibi Sankar
Cc: robh+dt, will, saiprakash.ranjan, ohad, agross, mathieu.poirier,
robin.murphy, joro, p.zabel, linux-arm-msm, linux-remoteproc,
devicetree, linux-kernel, linux-arm-kernel, evgreen, dianders,
swboyd
On Thu 24 Jun 14:47 CDT 2021, Sibi Sankar wrote:
> This patch adds Q6V5 MSS PAS remoteproc node for SC7280 SoCs.
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Regards,
Bjorn
> ---
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 40 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 40 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 3fb6a6ef39f8..56ea172f641f 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -584,6 +584,46 @@
> #power-domain-cells = <1>;
> };
>
> + remoteproc_mpss: remoteproc@4080000 {
> + compatible = "qcom,sc7280-mpss-pas";
> + reg = <0 0x04080000 0 0x10000>;
> +
> + interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
> + <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
> + <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
> + <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
> + <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
> + <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "wdog", "fatal", "ready", "handover",
> + "stop-ack", "shutdown-ack";
> +
> + clocks = <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "xo";
> +
> + power-domains = <&rpmhpd SC7280_CX>,
> + <&rpmhpd SC7280_MSS>;
> + power-domain-names = "cx", "mss";
> +
> + memory-region = <&mpss_mem>;
> +
> + qcom,qmp = <&aoss_qmp>;
> +
> + qcom,smem-states = <&modem_smp2p_out 0>;
> + qcom,smem-state-names = "stop";
> +
> + status = "disabled";
> +
> + glink-edge {
> + interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
> + IPCC_MPROC_SIGNAL_GLINK_QMP
> + IRQ_TYPE_EDGE_RISING>;
> + mboxes = <&ipcc IPCC_CLIENT_MPSS
> + IPCC_MPROC_SIGNAL_GLINK_QMP>;
> + label = "modem";
> + qcom,remote-pid = <1>;
> + };
> + };
> +
> stm@6002000 {
> compatible = "arm,coresight-stm", "arm,primecell";
> reg = <0 0x06002000 0 0x1000>,
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
^ permalink raw reply [relevance 0%]
* Re: [PATCH 7/9] arm64: dts: qcom: sc7280: Add nodes to boot modem
@ 2021-07-30 18:00 0% ` Bjorn Andersson
0 siblings, 0 replies; 200+ results
From: Bjorn Andersson @ 2021-07-30 18:00 UTC (permalink / raw)
To: Sibi Sankar
Cc: robh+dt, will, saiprakash.ranjan, ohad, agross, mathieu.poirier,
robin.murphy, joro, p.zabel, linux-arm-msm, linux-remoteproc,
devicetree, linux-kernel, linux-arm-kernel, evgreen, dianders,
swboyd
On Thu 24 Jun 14:47 CDT 2021, Sibi Sankar wrote:
> Add miscellaneous nodes to boot the modem and support post-mortem debug
> on SC7280 SoCs.
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 5ed7a511bfc9..3fb6a6ef39f8 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -547,6 +547,11 @@
> #hwlock-cells = <1>;
> };
>
> + tcsr_regs: syscon@1fc0000 {
Is there a different "tcsr"? Does the "_regs" suffix add any value?
> + compatible = "syscon";
Rob has pointed out a few times that a lone "syscon" isn't going to be
accepted going forward. Could you also add a qualifying
"qcom,sc7280-tcsr" or something like that?
> + reg = <0 0x01fc0000 0 0x30000>;
> + };
> +
> lpasscc: lpasscc@3000000 {
> compatible = "qcom,sc7280-lpasscc";
> reg = <0 0x03000000 0 0x40>,
> @@ -1219,6 +1224,21 @@
> };
> };
>
> + imem@146aa000 {
> + compatible = "syscon", "simple-mfd";
As above "qcom,sc7280-imem"?
I presume we need some new binding documents for these two though,
perhaps you can add the specific compatibles and we agree that one of us
will write these two bindings soon?
Regards,
Bjorn
> + reg = <0 0x146aa000 0 0x2000>;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + ranges = <0 0x0 0 0x146aa000 0 0x2000>;
> +
> + pil-reloc@94c {
> + compatible = "qcom,pil-reloc-info";
> + reg = <0 0x94c 0 0xc8>;
> + };
> + };
> +
> apps_smmu: iommu@15000000 {
> compatible = "qcom,sc7280-smmu-500", "arm,mmu-500";
> reg = <0 0x15000000 0 0x100000>;
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
^ permalink raw reply [relevance 0%]
* Re: [PATCH v4 04/13] remoteproc: qcom: q6v5: Use qmp_send to update co-processor load state
@ 2021-07-30 16:36 0% ` Bjorn Andersson
0 siblings, 0 replies; 200+ results
From: Bjorn Andersson @ 2021-07-30 16:36 UTC (permalink / raw)
To: Sibi Sankar
Cc: mka, swboyd, robh+dt, ulf.hansson, rjw, agross, ohad,
mathieu.poirier, linux-arm-msm, linux-remoteproc, devicetree,
linux-kernel, dianders, rishabhb, sidgup
On Mon 19 Jul 23:36 CDT 2021, Sibi Sankar wrote:
> The power domains exposed by the AOSS QMP driver control the load state
> resources linked to modem, adsp, cdsp remoteprocs. These are used to
> notify the Always on Subsystem (AOSS) that a particular co-processor is
> up/down. AOSS uses this information to wait for the co-processors to
> suspend before starting its sleep sequence.
>
> These co-processors enter low-power modes independent to that of the
> application processor and the load state resources linked to them are
> expected to remain unaltered across system suspend/resume cycles. To
> achieve this behavior lets stop using the power-domains exposed by the
> AOSS QMP node and replace them with generic qmp_send interface instead.
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
>
> v4:
> * Drop unused pdev and kfree the load state string in q6v5_deinit
> /probe path for patch 4. [Matthias]
>
> drivers/remoteproc/qcom_q6v5.c | 57 ++++++++++++++++++++++++-
> drivers/remoteproc/qcom_q6v5.h | 7 ++-
> drivers/remoteproc/qcom_q6v5_adsp.c | 7 ++-
> drivers/remoteproc/qcom_q6v5_mss.c | 44 ++++---------------
> drivers/remoteproc/qcom_q6v5_pas.c | 85 +++++++++----------------------------
> drivers/remoteproc/qcom_q6v5_wcss.c | 4 +-
> 6 files changed, 96 insertions(+), 108 deletions(-)
>
> diff --git a/drivers/remoteproc/qcom_q6v5.c b/drivers/remoteproc/qcom_q6v5.c
> index 7e9244c748da..997ff21271f7 100644
> --- a/drivers/remoteproc/qcom_q6v5.c
> +++ b/drivers/remoteproc/qcom_q6v5.c
> @@ -16,8 +16,28 @@
> #include "qcom_common.h"
> #include "qcom_q6v5.h"
>
> +#define Q6V5_LOAD_STATE_MSG_LEN 64
> #define Q6V5_PANIC_DELAY_MS 200
>
> +static int q6v5_load_state_toggle(struct qcom_q6v5 *q6v5, bool enable)
> +{
> + char buf[Q6V5_LOAD_STATE_MSG_LEN] = {};
> + int ret;
> +
> + if (IS_ERR(q6v5->qmp))
I would prefer that you keep it NULL when there's no qmp.
> + return 0;
> +
> + snprintf(buf, sizeof(buf),
> + "{class: image, res: load_state, name: %s, val: %s}",
> + q6v5->load_state, enable ? "on" : "off");
> +
> + ret = qmp_send(q6v5->qmp, buf, sizeof(buf));
> + if (ret)
> + dev_err(q6v5->dev, "failed to toggle load state\n");
> +
> + return ret;
> +}
> +
> /**
> * qcom_q6v5_prepare() - reinitialize the qcom_q6v5 context before start
> * @q6v5: reference to qcom_q6v5 context to be reinitialized
> @@ -26,6 +46,12 @@
> */
> int qcom_q6v5_prepare(struct qcom_q6v5 *q6v5)
> {
> + int ret;
> +
> + ret = q6v5_load_state_toggle(q6v5, true);
> + if (ret)
> + return ret;
> +
> reinit_completion(&q6v5->start_done);
> reinit_completion(&q6v5->stop_done);
>
> @@ -47,6 +73,7 @@ EXPORT_SYMBOL_GPL(qcom_q6v5_prepare);
> int qcom_q6v5_unprepare(struct qcom_q6v5 *q6v5)
> {
> disable_irq(q6v5->handover_irq);
> + q6v5_load_state_toggle(q6v5, false);
>
> return !q6v5->handover_issued;
> }
> @@ -196,12 +223,13 @@ EXPORT_SYMBOL_GPL(qcom_q6v5_panic);
> * @pdev: platform_device reference for acquiring resources
> * @rproc: associated remoteproc instance
> * @crash_reason: SMEM id for crash reason string, or 0 if none
> + * @load_state: load state resource string
> * @handover: function to be called when proxy resources should be released
> *
> * Return: 0 on success, negative errno on failure
> */
> int qcom_q6v5_init(struct qcom_q6v5 *q6v5, struct platform_device *pdev,
> - struct rproc *rproc, int crash_reason,
> + struct rproc *rproc, int crash_reason, const char *load_state,
> void (*handover)(struct qcom_q6v5 *q6v5))
> {
> int ret;
> @@ -286,9 +314,36 @@ int qcom_q6v5_init(struct qcom_q6v5 *q6v5, struct platform_device *pdev,
> return PTR_ERR(q6v5->state);
> }
>
> + q6v5->load_state = kstrdup_const(load_state, GFP_KERNEL);
Can't you use devm_kstrdup_const(&pdev->dev, ...) for this?
> + q6v5->qmp = qmp_get(&pdev->dev);
> + if (IS_ERR(q6v5->qmp)) {
> + if (PTR_ERR(q6v5->qmp) != -ENODEV) {
> + if (PTR_ERR(q6v5->qmp) != -EPROBE_DEFER)
> + dev_err(&pdev->dev, "failed to acquire load state\n");
> + kfree_const(q6v5->load_state);
Then you don't need to free it here.
> + return PTR_ERR(q6v5->qmp);
> + }
> + } else {
> + if (!q6v5->load_state) {
> + dev_err(&pdev->dev, "load state resource string empty\n");
> + return -EINVAL;
I see two cases here:
1) kstrdup_const() failed to allocate memory, the error print is
unnecessary and misleading and it would be more appropriate to return
-ENOMEM.
2) kstrdup_const() failed because you passed load_state == NULL, in
which case the error message could be more helpful by saying "unexpected
qcom,qmp property found" or something like that.
> + }
> + }
> +
> return 0;
> }
> EXPORT_SYMBOL_GPL(qcom_q6v5_init);
>
> +/**
> + * qcom_q6v5_deinit() - deinitialize the q6v5 common struct
> + * @q6v5: reference to qcom_q6v5 context to be deinitialized
> + */
> +void qcom_q6v5_deinit(struct qcom_q6v5 *q6v5)
> +{
> + kfree_const(q6v5->load_state);
> + qmp_put(q6v5->qmp);
> +}
> +EXPORT_SYMBOL_GPL(qcom_q6v5_deinit);
> +
> MODULE_LICENSE("GPL v2");
> MODULE_DESCRIPTION("Qualcomm Peripheral Image Loader for Q6V5");
> diff --git a/drivers/remoteproc/qcom_q6v5.h b/drivers/remoteproc/qcom_q6v5.h
> index 1c212f670cbc..f35e04471ed7 100644
> --- a/drivers/remoteproc/qcom_q6v5.h
> +++ b/drivers/remoteproc/qcom_q6v5.h
> @@ -5,6 +5,7 @@
>
> #include <linux/kernel.h>
> #include <linux/completion.h>
> +#include <linux/soc/qcom/qcom_aoss.h>
>
> struct rproc;
> struct qcom_smem_state;
> @@ -15,6 +16,8 @@ struct qcom_q6v5 {
> struct rproc *rproc;
>
> struct qcom_smem_state *state;
> + struct qmp *qmp;
> +
> unsigned stop_bit;
>
> int wdog_irq;
> @@ -32,12 +35,14 @@ struct qcom_q6v5 {
>
> bool running;
>
> + const char *load_state;
> void (*handover)(struct qcom_q6v5 *q6v5);
> };
>
> int qcom_q6v5_init(struct qcom_q6v5 *q6v5, struct platform_device *pdev,
> - struct rproc *rproc, int crash_reason,
> + struct rproc *rproc, int crash_reason, const char *load_state,
> void (*handover)(struct qcom_q6v5 *q6v5));
> +void qcom_q6v5_deinit(struct qcom_q6v5 *q6v5);
>
> int qcom_q6v5_prepare(struct qcom_q6v5 *q6v5);
> int qcom_q6v5_unprepare(struct qcom_q6v5 *q6v5);
> diff --git a/drivers/remoteproc/qcom_q6v5_adsp.c b/drivers/remoteproc/qcom_q6v5_adsp.c
> index 8b0d8bbacd2e..098362e6e233 100644
> --- a/drivers/remoteproc/qcom_q6v5_adsp.c
> +++ b/drivers/remoteproc/qcom_q6v5_adsp.c
> @@ -185,7 +185,9 @@ static int adsp_start(struct rproc *rproc)
> int ret;
> unsigned int val;
>
> - qcom_q6v5_prepare(&adsp->q6v5);
> + ret = qcom_q6v5_prepare(&adsp->q6v5);
> + if (ret)
> + return ret;
In the (hopefully unlikely) case that we have instances of
qcom_q6v5_prepare() failing today, the switch to the new qmp interface
would also introduce a regression in the same commit.
Could you please add the error handling in a separate commit? Just so
that we can pinpoint which of the two changes caused any issues if we
need to bisect this?
Regards,
Bjorn
^ permalink raw reply [relevance 0%]
* [PATCH 4/4] arm64: dts: qcom: sm8350: Fixup the cpufreq node
2021-07-29 18:04 12% [PATCH 0/4] Fixup register offsets to support per core L3 DCVS Sibi Sankar
` (2 preceding siblings ...)
2021-07-29 18:04 19% ` [PATCH 3/4] arm64: dts: qcom: sc7280: Fixup the cpufreq node Sibi Sankar
@ 2021-07-29 18:04 19% ` Sibi Sankar
2021-08-04 22:59 0% ` Bjorn Andersson
3 siblings, 1 reply; 200+ results
From: Sibi Sankar @ 2021-07-29 18:04 UTC (permalink / raw)
To: sboyd, bjorn.andersson, robh+dt, mka
Cc: viresh.kumar, agross, rjw, linux-arm-msm, devicetree,
linux-kernel, linux-pm, dianders, tdas, Sibi Sankar
Fixup the register regions used by the cpufreq node on SM8350 SoC to
support per core L3 DCVS.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index a631d58166b1..d0a5a5568602 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -967,11 +967,10 @@
};
cpufreq_hw: cpufreq@18591000 {
- compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss";
- reg = <0 0x18591000 0 0x1000>,
- <0 0x18592000 0 0x1000>,
- <0 0x18593000 0 0x1000>;
- reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
+ compatible = "qcom,cpufreq-epss";
+ reg = <0 0x18591100 0 0x900>,
+ <0 0x18592100 0 0x900>,
+ <0 0x18593100 0 0x900>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
clock-names = "xo", "alternate";
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 19%]
* [PATCH 1/4] dt-bindings: cpufreq: cpufreq-qcom-hw: Add compatible for SM8250/8350
2021-07-29 18:04 12% [PATCH 0/4] Fixup register offsets to support per core L3 DCVS Sibi Sankar
@ 2021-07-29 18:04 19% ` Sibi Sankar
2021-08-03 19:23 0% ` Rob Herring
2021-08-04 18:56 0% ` Stephen Boyd
2021-07-29 18:04 17% ` [PATCH 2/4] cpufreq: qcom: Re-arrange register offsets to support per core L3 DCVS Sibi Sankar
` (2 subsequent siblings)
3 siblings, 2 replies; 200+ results
From: Sibi Sankar @ 2021-07-29 18:04 UTC (permalink / raw)
To: sboyd, bjorn.andersson, robh+dt, mka
Cc: viresh.kumar, agross, rjw, linux-arm-msm, devicetree,
linux-kernel, linux-pm, dianders, tdas, Sibi Sankar
Re-arranging the register regions to support per core L3 DCVS would lead
to bindings breakage when using an older dt with a newer kernel. So,
document the EPSS compatible for SM8250/SM8350 SoCs and use them in the
CPUFreq-hw driver to prevent such breakages.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt
index 9299028ee712..ee52fd8d3c9a 100644
--- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt
+++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt
@@ -8,7 +8,11 @@ Properties:
- compatible
Usage: required
Value type: <string>
- Definition: must be "qcom,cpufreq-hw" or "qcom,cpufreq-epss".
+ Definition: must be one of:
+ "qcom,cpufreq-epss"
+ "qcom,cpufreq-hw"
+ "qcom,sm8250-cpufreq-epss"
+ "qcom,sm8350-cpufreq-epss"
- clocks
Usage: required
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 19%]
* [PATCH 2/4] cpufreq: qcom: Re-arrange register offsets to support per core L3 DCVS
2021-07-29 18:04 12% [PATCH 0/4] Fixup register offsets to support per core L3 DCVS Sibi Sankar
2021-07-29 18:04 19% ` [PATCH 1/4] dt-bindings: cpufreq: cpufreq-qcom-hw: Add compatible for SM8250/8350 Sibi Sankar
@ 2021-07-29 18:04 17% ` Sibi Sankar
2021-08-04 19:01 0% ` Stephen Boyd
2021-08-04 23:11 0% ` Bjorn Andersson
2021-07-29 18:04 19% ` [PATCH 3/4] arm64: dts: qcom: sc7280: Fixup the cpufreq node Sibi Sankar
2021-07-29 18:04 19% ` [PATCH 4/4] arm64: dts: qcom: sm8350: " Sibi Sankar
3 siblings, 2 replies; 200+ results
From: Sibi Sankar @ 2021-07-29 18:04 UTC (permalink / raw)
To: sboyd, bjorn.andersson, robh+dt, mka
Cc: viresh.kumar, agross, rjw, linux-arm-msm, devicetree,
linux-kernel, linux-pm, dianders, tdas, Sibi Sankar
Qualcomm SoCs (starting with SM8350) support per core voting for L3 cache
frequency. So, re-arrange the cpufreq register offsets to allow access for
the L3 interconnect to implement per core control. Also prevent binding
breakage caused by register offset shuffling by using the SM8250/SM8350
EPSS compatible.
Fixes: 7dbd121a2c58 ("arm64: dts: qcom: sc7280: Add cpufreq hw node")
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
drivers/cpufreq/qcom-cpufreq-hw.c | 23 +++++++++++++++++++----
1 file changed, 19 insertions(+), 4 deletions(-)
diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c
index f86859bf76f1..74ef3b38343b 100644
--- a/drivers/cpufreq/qcom-cpufreq-hw.c
+++ b/drivers/cpufreq/qcom-cpufreq-hw.c
@@ -28,6 +28,7 @@ struct qcom_cpufreq_soc_data {
u32 reg_volt_lut;
u32 reg_perf_state;
u8 lut_row_size;
+ bool skip_enable;
};
struct qcom_cpufreq_data {
@@ -257,19 +258,31 @@ static const struct qcom_cpufreq_soc_data qcom_soc_data = {
.reg_volt_lut = 0x114,
.reg_perf_state = 0x920,
.lut_row_size = 32,
+ .skip_enable = false,
};
static const struct qcom_cpufreq_soc_data epss_soc_data = {
+ .reg_freq_lut = 0x0,
+ .reg_volt_lut = 0x100,
+ .reg_perf_state = 0x220,
+ .lut_row_size = 4,
+ .skip_enable = true,
+};
+
+static const struct qcom_cpufreq_soc_data epss_sm8250_soc_data = {
.reg_enable = 0x0,
.reg_freq_lut = 0x100,
.reg_volt_lut = 0x200,
.reg_perf_state = 0x320,
.lut_row_size = 4,
+ .skip_enable = false,
};
static const struct of_device_id qcom_cpufreq_hw_match[] = {
{ .compatible = "qcom,cpufreq-hw", .data = &qcom_soc_data },
{ .compatible = "qcom,cpufreq-epss", .data = &epss_soc_data },
+ { .compatible = "qcom,sm8250-cpufreq-epss", .data = &epss_sm8250_soc_data },
+ { .compatible = "qcom,sm8350-cpufreq-epss", .data = &epss_sm8250_soc_data },
{}
};
MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match);
@@ -334,10 +347,12 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy)
data->res = res;
/* HW should be in enabled state to proceed */
- if (!(readl_relaxed(base + data->soc_data->reg_enable) & 0x1)) {
- dev_err(dev, "Domain-%d cpufreq hardware not enabled\n", index);
- ret = -ENODEV;
- goto error;
+ if (!data->soc_data->skip_enable) {
+ if (!(readl_relaxed(base + data->soc_data->reg_enable) & 0x1)) {
+ dev_err(dev, "Domain-%d cpufreq hardware not enabled\n", index);
+ ret = -ENODEV;
+ goto error;
+ }
}
qcom_get_related_cpus(index, policy->cpus);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 17%]
* [PATCH 3/4] arm64: dts: qcom: sc7280: Fixup the cpufreq node
2021-07-29 18:04 12% [PATCH 0/4] Fixup register offsets to support per core L3 DCVS Sibi Sankar
2021-07-29 18:04 19% ` [PATCH 1/4] dt-bindings: cpufreq: cpufreq-qcom-hw: Add compatible for SM8250/8350 Sibi Sankar
2021-07-29 18:04 17% ` [PATCH 2/4] cpufreq: qcom: Re-arrange register offsets to support per core L3 DCVS Sibi Sankar
@ 2021-07-29 18:04 19% ` Sibi Sankar
2021-08-04 18:57 0% ` Stephen Boyd
2021-08-31 15:30 6% ` Matthias Kaehlcke
2021-07-29 18:04 19% ` [PATCH 4/4] arm64: dts: qcom: sm8350: " Sibi Sankar
3 siblings, 2 replies; 200+ results
From: Sibi Sankar @ 2021-07-29 18:04 UTC (permalink / raw)
To: sboyd, bjorn.andersson, robh+dt, mka
Cc: viresh.kumar, agross, rjw, linux-arm-msm, devicetree,
linux-kernel, linux-pm, dianders, tdas, Sibi Sankar
Fixup the register regions used by the cpufreq node on SC7280 SoC to
support per core L3 DCVS.
Fixes: 7dbd121a2c58 ("arm64: dts: qcom: sc7280: Add cpufreq hw node")
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 5764c5b5cae1..ddb8697aff9f 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -1829,9 +1829,9 @@
cpufreq_hw: cpufreq@18591000 {
compatible = "qcom,cpufreq-epss";
- reg = <0 0x18591000 0 0x1000>,
- <0 0x18592000 0 0x1000>,
- <0 0x18593000 0 0x1000>;
+ reg = <0 0x18591100 0 0x900>,
+ <0 0x18592100 0 0x900>,
+ <0 0x18593100 0 0x900>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
clock-names = "xo", "alternate";
#freq-domain-cells = <1>;
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 19%]
* [PATCH 0/4] Fixup register offsets to support per core L3 DCVS
@ 2021-07-29 18:04 12% Sibi Sankar
2021-07-29 18:04 19% ` [PATCH 1/4] dt-bindings: cpufreq: cpufreq-qcom-hw: Add compatible for SM8250/8350 Sibi Sankar
` (3 more replies)
0 siblings, 4 replies; 200+ results
From: Sibi Sankar @ 2021-07-29 18:04 UTC (permalink / raw)
To: sboyd, bjorn.andersson, robh+dt, mka
Cc: viresh.kumar, agross, rjw, linux-arm-msm, devicetree,
linux-kernel, linux-pm, dianders, tdas, Sibi Sankar
Qualcomm SoCs (starting with SM8350) support per core voting for L3 cache
frequency. The patch series re-arranges the cpufreq register offsets to
allow access for the L3 interconnect to implement per core control i.e.
the first 0x100 is now accessed by the L3 interconnect driver instead.
L3 interconnect provider node on SC7280 SoC:
epss_l3: interconnect@18590000 {
compatible = "qcom,sc7280-epss-l3";
reg = <0 0x18590000 0 0x1000>, <0 0x18591000 0 0x100>,
<0 0x18592000 0 0x100>, <0 0x18593000 0 0x100>;
...
};
CPUFREQ node on SC7280 SoC:
cpufreq_hw: cpufreq@18591000 {
compatible = "qcom,cpufreq-epss";
reg = <0 0x18591100 0 0x900>,
<0 0x18592100 0 0x900>,
<0 0x18593100 0 0x900>;
...
};
The patch series also prevents binding breakage by using the
SM8250/SM8350 EPSS compatible.
Sibi Sankar (4):
dt-bindings: cpufreq: cpufreq-qcom-hw: Add compatible for SM8250/8350
cpufreq: qcom: Re-arrange register offsets to support per core L3 DCVS
arm64: dts: qcom: sc7280: Fixup the cpufreq node
arm64: dts: qcom: sm8350: Fixup the cpufreq node
.../bindings/cpufreq/cpufreq-qcom-hw.txt | 6 +++++-
arch/arm64/boot/dts/qcom/sc7280.dtsi | 6 +++---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 9 ++++-----
drivers/cpufreq/qcom-cpufreq-hw.c | 23 ++++++++++++++++++----
4 files changed, 31 insertions(+), 13 deletions(-)
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [relevance 12%]
* Re: [PATCH v4 01/13] dt-bindings: soc: qcom: aoss: Drop the load state power-domain
@ 2021-07-26 22:37 0% ` Rob Herring
0 siblings, 0 replies; 200+ results
From: Rob Herring @ 2021-07-26 22:37 UTC (permalink / raw)
To: Sibi Sankar
Cc: rishabhb, devicetree, dianders, linux-kernel, agross,
mathieu.poirier, linux-arm-msm, linux-remoteproc, sidgup, ohad,
swboyd, bjorn.andersson, ulf.hansson, robh+dt, rjw, mka
On Tue, 20 Jul 2021 10:06:35 +0530, Sibi Sankar wrote:
> The power-domains exposed by AOSS QMP node are used to notify the Always
> on Subsystem (AOSS) that a particular co-processor is up/down. These
> co-processors enter low-power modes independent to that of the application
> processor and their states are expected to remain unaltered across system
> suspend/resume cycles. To achieve this behavior let's drop the load
> power-domain and replace them with generic qmp_send interface instead.
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
>
> v4:
> * Rebase patch due to the recent aoss-qmp yaml conversion (Dropping Rb).
>
> Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml | 11 +----------
> 1 file changed, 1 insertion(+), 10 deletions(-)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [relevance 0%]
* Re: [PATCH v4 1/2] soc: qcom: aoss: Expose send for generic usecase
2021-07-23 9:51 0% ` Deepak Kumar Singh
@ 2021-07-23 19:28 0% ` Stephen Boyd
0 siblings, 0 replies; 200+ results
From: Stephen Boyd @ 2021-07-23 19:28 UTC (permalink / raw)
To: Deepak Kumar Singh, Sibi Sankar, bjorn.andersson
Cc: agross, linux-kernel, linux-arm-msm, manivannan.sadhasivam, Chris Lew
Quoting Deepak Kumar Singh (2021-07-23 02:51:50)
>
> On 7/21/2021 12:07 PM, Stephen Boyd wrote:
> > Quoting Sibi Sankar (2021-06-09 04:18:51)
> >> From: Deepak Kumar Singh <deesin@codeaurora.org>
> >>
> >> Not all upcoming usecases will have an interface to allow the aoss
> >> driver to hook onto. Expose the send api and create a get function to
> >> enable drivers to send their own messages to aoss.
> >>
> >> Signed-off-by: Chris Lew <clew@codeaurora.org>
> >> Signed-off-by: Deepak Kumar Singh <deesin@codeaurora.org>
> >> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> >> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> >> ---
> >>
> >> v4:
> >> * Fix compilation error due to missing qmp_put
> >> * Minor typos [s/tarcks/tracks]
> >>
> >> drivers/soc/qcom/qcom_aoss.c | 70 ++++++++++++++++++++++++++++++++++++--
> >> include/linux/soc/qcom/qcom_aoss.h | 36 ++++++++++++++++++++
> >> 2 files changed, 104 insertions(+), 2 deletions(-)
> >> create mode 100644 include/linux/soc/qcom/qcom_aoss.h
> >>
> >> diff --git a/drivers/soc/qcom/qcom_aoss.c b/drivers/soc/qcom/qcom_aoss.c
> >> index 934fcc4d2b05..e8f48760bac8 100644
> >> --- a/drivers/soc/qcom/qcom_aoss.c
> >> +++ b/drivers/soc/qcom/qcom_aoss.c
> >> @@ -522,13 +582,14 @@ static int qmp_probe(struct platform_device *pdev)
> >> int irq;
> >> int ret;
> >>
> >> - qmp = devm_kzalloc(&pdev->dev, sizeof(*qmp), GFP_KERNEL);
> >> + qmp = kzalloc(sizeof(*qmp), GFP_KERNEL);
> >> if (!qmp)
> >> return -ENOMEM;
> >>
> >> qmp->dev = &pdev->dev;
> >> init_waitqueue_head(&qmp->event);
> >> mutex_init(&qmp->tx_lock);
> >> + kref_init(&qmp->refcount);
> >>
> >> res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> >> qmp->msgram = devm_ioremap_resource(&pdev->dev, res);
> >> @@ -569,6 +630,8 @@ static int qmp_probe(struct platform_device *pdev)
> >>
> >> platform_set_drvdata(pdev, qmp);
> >>
> >> + atomic_set(&qmp->orphan, 0);
> >> +
> >> return 0;
> >>
> >> err_remove_qdss_clk:
> >> @@ -577,6 +640,7 @@ static int qmp_probe(struct platform_device *pdev)
> >> qmp_close(qmp);
> >> err_free_mbox:
> >> mbox_free_channel(qmp->mbox_chan);
> >> + kfree(qmp);
> >>
> >> return ret;
> >> }
> >> @@ -590,7 +654,9 @@ static int qmp_remove(struct platform_device *pdev)
> >> qmp_cooling_devices_remove(qmp);
> >>
> >> qmp_close(qmp);
> >> + atomic_set(&qmp->orphan, 1);
> > This looks odd. Why are we letting the device be removed while it is in
> > use by other drivers? Can't we pin the device with get_device() so it
> > can't be removed and then prevent the driver from being removed until
> > all the consumer drivers drop the reference, i.e. suppress sysfs unbind?
> >
> > Otherwise it looks like a generic problem that all provider devices,
> > clks, regulators, gpios, etc. have to deal with and thus this
> > hand-rolled mechanism can't be right.
>
> As per my earlier discussion with Bjorn, device could be unbound using
> sysfs, in which case
>
> remove() is called irrespective of whether any client driver is holding
> struct device reference
>
> or not. That's why i have added separate refcount for qmp handle and
> marking it invalid if
>
> qmp_remove() is called.
>
We have struct device_driver::suppress_bind_attrs for that. Can you set
it?
^ permalink raw reply [relevance 0%]
* Re: [PATCH v4 1/2] soc: qcom: aoss: Expose send for generic usecase
@ 2021-07-23 9:51 0% ` Deepak Kumar Singh
2021-07-23 19:28 0% ` Stephen Boyd
0 siblings, 1 reply; 200+ results
From: Deepak Kumar Singh @ 2021-07-23 9:51 UTC (permalink / raw)
To: Stephen Boyd, Sibi Sankar, bjorn.andersson
Cc: agross, linux-kernel, linux-arm-msm, manivannan.sadhasivam, Chris Lew
On 7/21/2021 12:07 PM, Stephen Boyd wrote:
> Quoting Sibi Sankar (2021-06-09 04:18:51)
>> From: Deepak Kumar Singh <deesin@codeaurora.org>
>>
>> Not all upcoming usecases will have an interface to allow the aoss
>> driver to hook onto. Expose the send api and create a get function to
>> enable drivers to send their own messages to aoss.
>>
>> Signed-off-by: Chris Lew <clew@codeaurora.org>
>> Signed-off-by: Deepak Kumar Singh <deesin@codeaurora.org>
>> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
>> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
>> ---
>>
>> v4:
>> * Fix compilation error due to missing qmp_put
>> * Minor typos [s/tarcks/tracks]
>>
>> drivers/soc/qcom/qcom_aoss.c | 70 ++++++++++++++++++++++++++++++++++++--
>> include/linux/soc/qcom/qcom_aoss.h | 36 ++++++++++++++++++++
>> 2 files changed, 104 insertions(+), 2 deletions(-)
>> create mode 100644 include/linux/soc/qcom/qcom_aoss.h
>>
>> diff --git a/drivers/soc/qcom/qcom_aoss.c b/drivers/soc/qcom/qcom_aoss.c
>> index 934fcc4d2b05..e8f48760bac8 100644
>> --- a/drivers/soc/qcom/qcom_aoss.c
>> +++ b/drivers/soc/qcom/qcom_aoss.c
>> @@ -522,13 +582,14 @@ static int qmp_probe(struct platform_device *pdev)
>> int irq;
>> int ret;
>>
>> - qmp = devm_kzalloc(&pdev->dev, sizeof(*qmp), GFP_KERNEL);
>> + qmp = kzalloc(sizeof(*qmp), GFP_KERNEL);
>> if (!qmp)
>> return -ENOMEM;
>>
>> qmp->dev = &pdev->dev;
>> init_waitqueue_head(&qmp->event);
>> mutex_init(&qmp->tx_lock);
>> + kref_init(&qmp->refcount);
>>
>> res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> qmp->msgram = devm_ioremap_resource(&pdev->dev, res);
>> @@ -569,6 +630,8 @@ static int qmp_probe(struct platform_device *pdev)
>>
>> platform_set_drvdata(pdev, qmp);
>>
>> + atomic_set(&qmp->orphan, 0);
>> +
>> return 0;
>>
>> err_remove_qdss_clk:
>> @@ -577,6 +640,7 @@ static int qmp_probe(struct platform_device *pdev)
>> qmp_close(qmp);
>> err_free_mbox:
>> mbox_free_channel(qmp->mbox_chan);
>> + kfree(qmp);
>>
>> return ret;
>> }
>> @@ -590,7 +654,9 @@ static int qmp_remove(struct platform_device *pdev)
>> qmp_cooling_devices_remove(qmp);
>>
>> qmp_close(qmp);
>> + atomic_set(&qmp->orphan, 1);
> This looks odd. Why are we letting the device be removed while it is in
> use by other drivers? Can't we pin the device with get_device() so it
> can't be removed and then prevent the driver from being removed until
> all the consumer drivers drop the reference, i.e. suppress sysfs unbind?
>
> Otherwise it looks like a generic problem that all provider devices,
> clks, regulators, gpios, etc. have to deal with and thus this
> hand-rolled mechanism can't be right.
As per my earlier discussion with Bjorn, device could be unbound using
sysfs, in which case
remove() is called irrespective of whether any client driver is holding
struct device reference
or not. That's why i have added separate refcount for qmp handle and
marking it invalid if
qmp_remove() is called.
>> mbox_free_channel(qmp->mbox_chan);
>> + kref_put(&qmp->refcount, qmp_handle_release);
>>
>> return 0;
>> }
^ permalink raw reply [relevance 0%]
Results 1-200 of ~2000 next (older) | reverse | options above
-- pct% links below jump to the message on this page, permalinks otherwise --
2021-03-10 7:28 [PATCH 0/2] Add support for sc7280 WPSS PIL loading Rakesh Pillai
2021-03-10 7:28 ` [PATCH 2/2] remoteproc: qcom: q6v5_wpss: Add support for sc7280 WPSS Rakesh Pillai
2021-03-10 16:44 ` Bjorn Andersson
2021-03-15 12:08 ` Rakesh Pillai
2021-10-04 15:29 0% ` Bjorn Andersson
2021-10-28 7:43 0% ` pillair
2021-05-12 8:11 [PATCH v3 0/2] DDR/L3 Scaling support on SC7280 SoCs Sibi Sankar
2021-05-12 8:11 ` [PATCH v3 2/2] arm64: dts: qcom: sc7280: Add cpu OPP tables Sibi Sankar
2021-07-30 22:20 6% ` Doug Anderson
2021-08-02 3:28 13% ` Sibi Sankar
2021-06-09 11:18 [PATCH v4 0/2] soc: qcom: aoss: Expose send for generic usecase Sibi Sankar
2021-06-09 11:18 ` [PATCH v4 1/2] " Sibi Sankar
2021-07-21 6:37 ` Stephen Boyd
2021-07-23 9:51 0% ` Deepak Kumar Singh
2021-07-23 19:28 0% ` Stephen Boyd
2021-06-09 11:18 ` [PATCH v4 2/2] soc: qcom: aoss: Add debugfs entry Sibi Sankar
2021-08-04 19:06 0% ` Bjorn Andersson
2021-06-24 18:33 [PATCH] remoteproc: qcom: pas: Add missing power-domain "mxc" for CDSP Sibi Sankar
2021-11-17 18:57 0% ` Bjorn Andersson
2021-06-24 19:47 [PATCH 0/9] Add Modem support on SC7280 SoCs Sibi Sankar
2021-06-24 19:47 ` [PATCH 7/9] arm64: dts: qcom: sc7280: Add nodes to boot modem Sibi Sankar
2021-07-30 18:00 0% ` Bjorn Andersson
2021-06-24 19:47 ` [PATCH 8/9] arm64: dts: qcom: sc7280: Add Q6V5 MSS node Sibi Sankar
2021-07-30 18:01 0% ` Bjorn Andersson
2021-06-24 19:47 ` [PATCH 9/9] arm64: dts: qcom: sc7280: Update " Sibi Sankar
2021-06-28 19:05 ` Matthias Kaehlcke
2021-06-30 20:08 ` Sibi Sankar
2021-07-30 18:14 0% ` Bjorn Andersson
2021-07-20 4:36 [PATCH v4 00/13] Use qmp_send to update co-processor load state Sibi Sankar
2021-07-20 4:36 ` [PATCH v4 01/13] dt-bindings: soc: qcom: aoss: Drop the load state power-domain Sibi Sankar
2021-07-26 22:37 0% ` Rob Herring
2021-07-20 4:36 ` [PATCH v4 04/13] remoteproc: qcom: q6v5: Use qmp_send to update co-processor load state Sibi Sankar
2021-07-30 16:36 0% ` Bjorn Andersson
2021-07-29 18:04 12% [PATCH 0/4] Fixup register offsets to support per core L3 DCVS Sibi Sankar
2021-07-29 18:04 19% ` [PATCH 1/4] dt-bindings: cpufreq: cpufreq-qcom-hw: Add compatible for SM8250/8350 Sibi Sankar
2021-08-03 19:23 0% ` Rob Herring
2021-08-04 18:56 0% ` Stephen Boyd
2021-07-29 18:04 17% ` [PATCH 2/4] cpufreq: qcom: Re-arrange register offsets to support per core L3 DCVS Sibi Sankar
2021-08-04 19:01 0% ` Stephen Boyd
2021-08-05 17:47 6% ` Sibi Sankar
2021-08-05 18:25 0% ` Stephen Boyd
2021-08-06 6:42 6% ` Sibi Sankar
2021-08-04 23:11 0% ` Bjorn Andersson
2021-08-04 23:20 0% ` Bjorn Andersson
2021-07-29 18:04 19% ` [PATCH 3/4] arm64: dts: qcom: sc7280: Fixup the cpufreq node Sibi Sankar
2021-08-04 18:57 0% ` Stephen Boyd
2021-08-31 15:30 6% ` Matthias Kaehlcke
2021-08-31 17:04 0% ` Bjorn Andersson
2021-09-06 3:20 6% ` Sibi Sankar
2021-09-07 19:14 6% ` Doug Anderson
2021-07-29 18:04 19% ` [PATCH 4/4] arm64: dts: qcom: sm8350: " Sibi Sankar
2021-08-04 22:59 0% ` Bjorn Andersson
2021-08-04 23:58 ` Matthias Kaehlcke
2021-08-30 6:47 6% ` Sibi Sankar
2021-08-05 16:17 [PATCH V1 1/1] soc: qcom: smp2p: Add wakeup capability to SMP2P IRQ Deepak Kumar Singh
2021-08-05 19:40 ` Stephen Boyd
2021-08-09 11:05 ` Deepak Kumar Singh
2021-08-09 17:58 ` Stephen Boyd
2021-08-10 17:24 6% ` Sibi Sankar
2021-08-10 6:45 [v6 0/3] Add L3 provider support for SC7280 Odelu Kukatla
2021-08-10 6:46 ` [v6 1/3] dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280 Odelu Kukatla
2021-08-16 18:09 6% ` Sibi Sankar
2021-08-10 18:01 [PATCH v2 0/3] Add support for sc7280 WPSS PIL loading Rakesh Pillai
2021-08-10 18:01 ` [PATCH v2 2/3] dt-bindings: remoteproc: qcom: Add SC7280 WPSS support Rakesh Pillai
2021-08-11 17:24 ` Rob Herring
2021-09-09 8:36 0% ` pillair
2021-08-10 18:11 [PATCH v2] arm64: dts: qcom: sc7280: Add WPSS remoteproc node Rakesh Pillai
2021-08-10 19:51 ` Stephen Boyd
2021-09-09 8:38 0% ` pillair
2021-08-19 3:02 9% [PATCH v5 00/13] Use qmp_send to update co-processor load state Sibi Sankar
2021-08-19 3:02 17% ` [PATCH v5 01/13] dt-bindings: soc: qcom: aoss: Drop the load state power-domain Sibi Sankar
2021-08-19 3:02 15% ` [PATCH v5 02/13] dt-bindings: remoteproc: qcom: pas: Add QMP property Sibi Sankar
2021-08-19 18:55 ` Stephen Boyd
2021-08-20 14:24 6% ` Sibi Sankar
2021-08-21 18:17 ` Stephen Boyd
2021-08-23 16:19 6% ` Sibi Sankar
2021-08-19 3:02 18% ` [PATCH v5 03/13] dt-bindings: remoteproc: qcom: " Sibi Sankar
2021-08-19 3:02 9% ` [PATCH v5 04/13] remoteproc: qcom: q6v5: Use qmp_send to update co-processor load state Sibi Sankar
2021-08-23 20:17 0% ` Stephen Boyd
2021-08-19 3:02 18% ` [PATCH v5 05/13] arm64: dts: qcom: sc7180: Use QMP property to control " Sibi Sankar
2021-08-19 3:02 18% ` [PATCH v5 06/13] arm64: dts: qcom: sc7280: " Sibi Sankar
2021-08-19 3:02 18% ` [PATCH v5 07/13] arm64: dts: qcom: sdm845: " Sibi Sankar
2021-08-19 3:02 17% ` [PATCH v5 08/13] arm64: dts: qcom: sm8150: " Sibi Sankar
2021-08-19 3:02 17% ` [PATCH v5 09/13] arm64: dts: qcom: sm8250: " Sibi Sankar
2021-08-19 3:02 16% ` [PATCH v5 10/13] arm64: dts: qcom: sm8350: " Sibi Sankar
2021-08-19 3:02 15% ` [PATCH v5 11/13] soc: qcom: aoss: Drop power domain support Sibi Sankar
2021-08-19 3:02 19% ` [PATCH v5 12/13] dt-bindings: msm/dp: Remove aoss-qmp header Sibi Sankar
2021-08-19 3:02 19% ` [PATCH v5 13/13] dt-bindings: soc: qcom: aoss: Delete unused power-domain definitions Sibi Sankar
2021-08-19 3:36 18% [PATCH v3 00/10] Add Modem support on SC7280 SoCs Sibi Sankar
2021-08-19 3:36 18% ` [PATCH v3 01/10] dt-bindings: remoteproc: qcom: pas: Add SC7280 MPSS support Sibi Sankar
2021-08-23 20:14 0% ` Stephen Boyd
2021-08-19 3:36 19% ` [PATCH v3 02/10] remoteproc: qcom: pas: Add SC7280 Modem support Sibi Sankar
2021-08-23 20:14 0% ` Stephen Boyd
2021-08-19 3:36 14% ` [PATCH v3 03/10] dt-bindings: remoteproc: qcom: Update Q6V5 Modem PIL binding Sibi Sankar
2021-08-23 20:14 0% ` Stephen Boyd
2021-08-19 3:36 19% ` [PATCH v3 04/10] iommu/arm-smmu-qcom: Request direct mapping for modem device Sibi Sankar
2021-08-19 3:36 11% ` [PATCH v3 05/10] remoteproc: mss: q6v5-mss: Add modem support on SC7280 Sibi Sankar
2021-08-19 3:36 18% ` [PATCH v3 06/10] arm64: dts: qcom: sc7280: Update reserved memory map Sibi Sankar
2021-08-19 4:37 ` Vinod Koul
2021-08-20 14:09 6% ` Sibi Sankar
2021-08-19 3:36 18% ` [PATCH v3 07/10] arm64: dts: qcom: sc7280: Add/Delete/Update reserved memory nodes Sibi Sankar
2021-08-19 3:36 18% ` [PATCH v3 08/10] arm64: dts: qcom: sc7280: Add nodes to boot modem Sibi Sankar
2021-08-23 20:12 0% ` Stephen Boyd
2021-08-19 3:36 18% ` [PATCH v3 09/10] arm64: dts: qcom: sc7280: Add Q6V5 MSS node Sibi Sankar
2021-08-19 3:36 17% ` [PATCH v3 10/10] arm64: dts: qcom: sc7280: Update " Sibi Sankar
2021-08-23 20:12 0% ` Stephen Boyd
2021-09-06 8:23 9% [PATCH v6 00/13] Use qmp_send to update co-processor load state Sibi Sankar
2021-09-06 8:23 17% ` [PATCH v6 01/13] dt-bindings: soc: qcom: aoss: Drop the load state power-domain Sibi Sankar
2021-09-06 8:23 15% ` [PATCH v6 02/13] dt-bindings: remoteproc: qcom: pas: Add QMP property Sibi Sankar
2021-09-08 13:51 0% ` Rob Herring
2021-09-16 3:13 6% ` Sibi Sankar
2021-09-06 8:23 18% ` [PATCH v6 03/13] dt-bindings: remoteproc: qcom: " Sibi Sankar
2021-09-06 8:23 9% ` [PATCH v6 04/13] remoteproc: qcom: q6v5: Use qmp_send to update co-processor load state Sibi Sankar
2021-09-06 8:23 18% ` [PATCH v6 05/13] arm64: dts: qcom: sc7180: Use QMP property to control " Sibi Sankar
2021-09-06 8:23 18% ` [PATCH v6 06/13] arm64: dts: qcom: sc7280: " Sibi Sankar
2021-09-06 8:23 18% ` [PATCH v6 07/13] arm64: dts: qcom: sdm845: " Sibi Sankar
2021-09-06 8:23 17% ` [PATCH v6 08/13] arm64: dts: qcom: sm8150: " Sibi Sankar
2021-09-06 8:23 17% ` [PATCH v6 09/13] arm64: dts: qcom: sm8250: " Sibi Sankar
2021-09-06 8:23 16% ` [PATCH v6 10/13] arm64: dts: qcom: sm8350: " Sibi Sankar
2021-09-06 8:23 15% ` [PATCH v6 11/13] soc: qcom: aoss: Drop power domain support Sibi Sankar
2021-09-06 8:23 19% ` [PATCH v6 12/13] dt-bindings: msm/dp: Remove aoss-qmp header Sibi Sankar
2021-09-06 8:23 19% ` [PATCH v6 13/13] dt-bindings: soc: qcom: aoss: Delete unused power-domain definitions Sibi Sankar
2021-09-06 8:54 18% [PATCH v4 00/10] Add Modem support on SC7280 SoCs Sibi Sankar
2021-09-06 8:54 17% ` [PATCH v4 01/10] dt-bindings: remoteproc: qcom: pas: Add SC7280 MPSS support Sibi Sankar
2021-09-06 8:54 19% ` [PATCH v4 02/10] remoteproc: qcom: pas: Add SC7280 Modem support Sibi Sankar
2021-09-06 8:54 14% ` [PATCH v4 03/10] dt-bindings: remoteproc: qcom: Update Q6V5 Modem PIL binding Sibi Sankar
2021-09-06 8:54 19% ` [PATCH v4 04/10] iommu/arm-smmu-qcom: Request direct mapping for modem device Sibi Sankar
2021-09-06 8:54 11% ` [PATCH v4 05/10] remoteproc: mss: q6v5-mss: Add modem support on SC7280 Sibi Sankar
2021-09-07 20:01 0% ` Stephen Boyd
2021-09-06 8:54 18% ` [PATCH v4 06/10] arm64: dts: qcom: sc7280: Update reserved memory map Sibi Sankar
2021-09-06 8:54 18% ` [PATCH v4 07/10] arm64: dts: qcom: sc7280: Add/Delete/Update reserved memory nodes Sibi Sankar
2021-09-06 8:54 18% ` [PATCH v4 08/10] arm64: dts: qcom: sc7280: Add nodes to boot modem Sibi Sankar
2021-09-06 8:54 18% ` [PATCH v4 09/10] arm64: dts: qcom: sc7280: Add Q6V5 MSS node Sibi Sankar
2021-09-06 8:54 17% ` [PATCH v4 10/10] arm64: dts: qcom: sc7280: Update " Sibi Sankar
2021-09-07 19:12 7% [PATCH] Revert "arm64: dts: qcom: sc7280: Fixup the cpufreq node" Douglas Anderson
2021-09-07 19:56 0% ` Matthias Kaehlcke
2021-09-09 11:36 [PATCH AUTOSEL 5.14 001/252] drm/bridge: ti-sn65dsi86: Don't read EDID blob over DDC Sasha Levin
2021-09-09 11:38 6% ` [PATCH AUTOSEL 5.14 124/252] arm64: dts: qcom: sm8250: Fix epss_l3 unit address Sasha Levin
2021-09-09 11:42 [PATCH AUTOSEL 5.13 001/219] drm/vmwgfx: Fix subresource updates with new contexts Sasha Levin
2021-09-09 11:44 6% ` [PATCH AUTOSEL 5.13 109/219] arm64: dts: qcom: sm8250: Fix epss_l3 unit address Sasha Levin
2021-09-09 11:48 [PATCH AUTOSEL 5.10 001/176] drm/vc4: hdmi: Set HD_CTL_WHOLSMP and HD_CTL_CHALIGN_SET Sasha Levin
2021-09-09 11:49 6% ` [PATCH AUTOSEL 5.10 089/176] arm64: dts: qcom: sm8250: Fix epss_l3 unit address Sasha Levin
2021-09-13 13:10 2% [PATCH 5.14 000/334] 5.14.4-rc1 review Greg Kroah-Hartman
2021-09-13 13:12 8% ` [PATCH 5.14 103/334] soc: qcom: rpmhpd: Use corner in power_off Greg Kroah-Hartman
2021-09-13 13:13 9% ` [PATCH 5.14 173/334] arm64: dts: qcom: sc7280: Fixup the cpufreq node Greg Kroah-Hartman
2021-09-13 13:11 [PATCH 5.13 000/300] 5.13.17-rc1 review Greg Kroah-Hartman
2021-09-13 13:12 8% ` [PATCH 5.13 099/300] soc: qcom: rpmhpd: Use corner in power_off Greg Kroah-Hartman
2021-09-13 13:11 [PATCH 5.10 000/236] 5.10.65-rc1 review Greg Kroah-Hartman
2021-09-13 13:13 8% ` [PATCH 5.10 085/236] soc: qcom: rpmhpd: Use corner in power_off Greg Kroah-Hartman
2021-09-13 13:13 [PATCH 5.4 000/144] 5.4.146-rc1 review Greg Kroah-Hartman
2021-09-13 13:13 8% ` [PATCH 5.4 054/144] soc: qcom: rpmhpd: Use corner in power_off Greg Kroah-Hartman
2021-09-16 13:59 9% [PATCH v7 00/13] Use qmp_send to update co-processor load state Sibi Sankar
2021-09-16 13:59 17% ` [PATCH v7 01/13] dt-bindings: soc: qcom: aoss: Drop the load state power-domain Sibi Sankar
2021-09-16 13:59 15% ` [PATCH v7 02/13] dt-bindings: remoteproc: qcom: pas: Add QMP property Sibi Sankar
2021-09-21 22:06 0% ` Rob Herring
2021-09-16 13:59 18% ` [PATCH v7 03/13] dt-bindings: remoteproc: qcom: " Sibi Sankar
2021-09-16 13:59 8% ` [PATCH v7 04/13] remoteproc: qcom: q6v5: Use qmp_send to update co-processor load state Sibi Sankar
2021-09-16 13:59 18% ` [PATCH v7 05/13] arm64: dts: qcom: sc7180: Use QMP property to control " Sibi Sankar
2021-09-16 13:59 18% ` [PATCH v7 06/13] arm64: dts: qcom: sc7280: " Sibi Sankar
2021-09-16 13:59 18% ` [PATCH v7 07/13] arm64: dts: qcom: sdm845: " Sibi Sankar
2021-09-16 13:59 17% ` [PATCH v7 08/13] arm64: dts: qcom: sm8150: " Sibi Sankar
2021-09-16 13:59 17% ` [PATCH v7 09/13] arm64: dts: qcom: sm8250: " Sibi Sankar
2021-09-16 13:59 16% ` [PATCH v7 10/13] arm64: dts: qcom: sm8350: " Sibi Sankar
2021-09-16 13:59 15% ` [PATCH v7 11/13] soc: qcom: aoss: Drop power domain support Sibi Sankar
2021-09-16 13:59 19% ` [PATCH v7 12/13] dt-bindings: msm/dp: Remove aoss-qmp header Sibi Sankar
2021-09-16 13:59 19% ` [PATCH v7 13/13] dt-bindings: soc: qcom: aoss: Delete unused power-domain definitions Sibi Sankar
2021-09-16 15:55 [PATCH 5.10 000/306] 5.10.67-rc1 review Greg Kroah-Hartman
2021-09-16 15:59 6% ` [PATCH 5.10 195/306] arm64: dts: qcom: sm8250: Fix epss_l3 unit address Greg Kroah-Hartman
2021-09-16 15:55 [PATCH 5.14 000/432] 5.14.6-rc1 review Greg Kroah-Hartman
2021-09-16 16:00 6% ` [PATCH 5.14 274/432] arm64: dts: qcom: sm8250: Fix epss_l3 unit address Greg Kroah-Hartman
2021-09-16 15:55 [PATCH 5.13 000/380] 5.13.19-rc1 review Greg Kroah-Hartman
2021-09-16 16:00 6% ` [PATCH 5.13 243/380] arm64: dts: qcom: sm8250: Fix epss_l3 unit address Greg Kroah-Hartman
2021-09-16 16:52 [PATCH v3] arm64: dts: qcom: sc7280: Add WPSS remoteproc node Rakesh Pillai
2021-09-17 0:55 ` Stephen Boyd
2021-09-17 8:04 0% ` pillair
2021-09-16 16:55 [PATCH v3 0/3] Add support for sc7280 WPSS PIL loading Rakesh Pillai
2021-09-16 16:55 ` [PATCH v3 1/3] dt-bindings: remoteproc: qcom: adsp: Convert binding to YAML Rakesh Pillai
2021-09-17 6:24 ` Stephen Boyd
2021-09-21 23:28 ` Rob Herring
2021-09-22 5:01 0% ` pillair
2021-09-16 16:55 ` [PATCH v3 2/3] dt-bindings: remoteproc: qcom: Add SC7280 WPSS support Rakesh Pillai
2021-09-17 6:25 ` Stephen Boyd
2021-09-17 10:26 0% ` pillair
2021-09-21 23:37 ` Bjorn Andersson
2021-09-22 5:03 0% ` pillair
2021-09-17 10:34 [PATCH v4] arm64: dts: qcom: sc7280: Add WPSS remoteproc node Rakesh Pillai
2021-10-04 9:33 0% ` pillair
2021-09-17 10:35 [PATCH v4 0/2] Add support for sc7280 WPSS PIL loading Rakesh Pillai
2021-09-17 10:35 ` [PATCH v4 1/2] dt-bindings: remoteproc: qcom: Add SC7280 WPSS support Rakesh Pillai
2021-09-22 17:28 ` Rob Herring
2021-09-23 17:12 0% ` pillair
2021-09-17 13:55 17% [PATCH v5 00/10] Add Modem support on SC7280 SoCs Sibi Sankar
2021-09-17 13:55 18% ` [PATCH v5 01/10] dt-bindings: remoteproc: qcom: pas: Add SC7280 MPSS support Sibi Sankar
2021-09-17 13:55 19% ` [PATCH v5 02/10] remoteproc: qcom: pas: Add SC7280 Modem support Sibi Sankar
2021-09-17 13:55 14% ` [PATCH v5 03/10] dt-bindings: remoteproc: qcom: Update Q6V5 Modem PIL binding Sibi Sankar
2021-09-17 13:55 19% ` [PATCH v5 04/10] iommu/arm-smmu-qcom: Request direct mapping for modem device Sibi Sankar
2021-10-07 20:08 6% ` Sibi Sankar
2021-09-17 13:55 10% ` [PATCH v5 05/10] remoteproc: mss: q6v5-mss: Add modem support on SC7280 Sibi Sankar
2021-09-17 13:55 18% ` [PATCH v5 06/10] arm64: dts: qcom: sc7280: Update reserved memory map Sibi Sankar
2021-09-17 13:55 18% ` [PATCH v5 07/10] arm64: dts: qcom: sc7280: Add/Delete/Update reserved memory nodes Sibi Sankar
2021-09-17 13:55 18% ` [PATCH v5 08/10] arm64: dts: qcom: sc7280: Add nodes to boot modem Sibi Sankar
2021-09-17 13:55 18% ` [PATCH v5 09/10] arm64: dts: qcom: sc7280: Add Q6V5 MSS node Sibi Sankar
2021-09-17 13:55 17% ` [PATCH v5 10/10] arm64: dts: qcom: sc7280: Update " Sibi Sankar
2021-09-27 22:56 0% ` (subset) [PATCH v5 00/10] Add Modem support on SC7280 SoCs Bjorn Andersson
2021-10-08 12:53 0% ` Will Deacon
2021-10-03 3:04 [PATCH v5 0/3] Add support for sc7280 WPSS PIL loading Rakesh Pillai
2021-10-03 3:07 0% ` pillair
2021-10-04 6:48 [PATCH v6 " Rakesh Pillai
2021-10-04 6:48 ` [PATCH v6 1/3] dt-bindings: remoteproc: qcom: adsp: Convert binding to YAML Rakesh Pillai
2021-10-12 1:18 ` Rob Herring
2021-10-28 13:09 0% ` pillair
2021-10-04 6:48 ` [PATCH v6 2/3] dt-bindings: remoteproc: qcom: Add SC7280 WPSS support Rakesh Pillai
2021-10-04 12:21 ` Rob Herring
2021-10-06 5:09 0% ` pillair
2021-10-06 7:09 ` Stephen Boyd
2021-10-06 16:56 0% ` pillair
2021-10-07 18:34 ` [PATCH v6 0/3] Add support for sc7280 WPSS PIL loading Stephen Boyd
2021-10-28 13:08 0% ` pillair
2021-10-28 22:01 0% ` Stephen Boyd
2021-10-29 6:21 0% ` pillair
2021-10-11 13:44 [PATCH 5.14 000/151] 5.14.12-rc1 review Greg Kroah-Hartman
2021-10-11 13:45 6% ` [PATCH 5.14 039/151] Revert "arm64: dts: qcom: sc7280: Fixup the cpufreq node" Greg Kroah-Hartman
2021-10-21 10:40 [v8 0/3] Add L3 provider support for SC7280 Odelu Kukatla
2021-10-21 10:40 ` [v8 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider Odelu Kukatla
2021-10-28 23:27 6% ` Bjorn Andersson
2021-11-01 13:39 6% ` okukatla
2021-10-28 8:13 [PATCH v7 0/3] Add support for sc7280 WPSS PIL loading Rakesh Pillai
2021-10-28 8:13 ` [PATCH v7 2/3] dt-bindings: remoteproc: qcom: Add SC7280 WPSS support Rakesh Pillai
2021-10-28 22:08 ` Stephen Boyd
2021-10-29 10:46 0% ` pillair
2021-10-29 19:04 ` Stephen Boyd
2021-11-02 13:45 0% ` pillair
2021-11-02 13:44 [PATCH v8 0/3] Add support for sc7280 WPSS PIL loading Rakesh Pillai
2021-11-02 13:44 ` [PATCH v8 3/3] remoteproc: qcom: q6v5_wpss: Add support for sc7280 WPSS Rakesh Pillai
2021-11-15 23:43 ` Stephen Boyd
2021-11-16 17:49 0% ` pillair
2021-11-16 22:54 ` Stephen Boyd
2021-11-17 6:31 0% ` Rakesh Pillai
2021-11-17 6:39 0% ` Stephen Boyd
2021-11-18 15:56 [PATCH v6] arm64: dts: qcom: sc7280: Add WPSS remoteproc node Rakesh Pillai
2021-11-19 0:51 ` Stephen Boyd
2021-11-19 5:25 0% ` Rakesh Pillai
2021-11-19 5:24 [PATCH v7] " Rakesh Pillai
2021-11-29 9:55 6% ` Sibi Sankar
2021-12-11 6:46 5% [PATCH] remoteproc: qcom: q6v5: make symbols modular when QCOM_AOSS_QMP=m Randy Dunlap
2022-01-15 1:13 5% [PATCH] remoteproc: qcom: q6v5: fix service routines build errors Randy Dunlap
2022-01-15 8:09 0% ` Stephen Boyd
2022-01-17 22:43 0% ` Bjorn Andersson
2022-01-18 16:05 4% [PATCH 5.15 00/28] 5.15.16-rc1 review Greg Kroah-Hartman
2022-01-18 16:05 9% ` [PATCH 5.15 11/28] remoteproc: qcom: pas: Add missing power-domain "mxc" for CDSP Greg Kroah-Hartman
2022-01-22 0:29 0% ` [PATCH 5.15 00/28] 5.15.16-rc1 review Allen
2022-01-18 16:05 4% [PATCH 5.16 00/28] 5.16.2-rc1 review Greg Kroah-Hartman
2022-01-18 16:06 9% ` [PATCH 5.16 11/28] remoteproc: qcom: pas: Add missing power-domain "mxc" for CDSP Greg Kroah-Hartman
2022-01-19 23:21 7% [PATCH] remoteproc: Fix count check in rproc_coredump_write() Alistair Delva
2022-01-20 0:24 0% ` Bjorn Andersson
2022-01-31 10:54 [PATCH 5.16 000/200] 5.16.5-rc1 review Greg Kroah-Hartman
2022-01-31 10:56 5% ` [PATCH 5.16 127/200] remoteproc: qcom: q6v5: fix service routines build errors Greg Kroah-Hartman
2022-04-05 7:12 [PATCH 5.17 0000/1126] 5.17.2-rc1 review Greg Kroah-Hartman
2022-04-05 7:13 6% ` [PATCH 5.17 0062/1126] remoteproc: Fix count check in rproc_coredump_write() Greg Kroah-Hartman
2022-04-05 7:15 [PATCH 5.16 0000/1017] 5.16.19-rc1 review Greg Kroah-Hartman
2022-04-05 7:16 6% ` [PATCH 5.16 0073/1017] remoteproc: Fix count check in rproc_coredump_write() Greg Kroah-Hartman
2022-04-05 7:17 [PATCH 5.15 000/913] 5.15.33-rc1 review Greg Kroah-Hartman
2022-04-05 7:18 6% ` [PATCH 5.15 070/913] remoteproc: Fix count check in rproc_coredump_write() Greg Kroah-Hartman
2022-04-05 7:24 [PATCH 5.10 000/599] 5.10.110-rc1 review Greg Kroah-Hartman
2022-04-05 7:25 6% ` [PATCH 5.10 051/599] remoteproc: Fix count check in rproc_coredump_write() Greg Kroah-Hartman
2022-05-07 15:01 [PATCH v2 0/5] PM / devfreq: Add cpu based scaling support to passive governor Chanwoo Choi
2022-05-07 15:01 4% ` [PATCH v2 2/5] " Chanwoo Choi
2022-05-09 12:03 [PATCH v3 0/4] " Chanwoo Choi
2022-05-09 12:03 4% ` [PATCH v3 2/4] " Chanwoo Choi
2022-05-11 9:35 [PATCH v4 0/4] " Chanwoo Choi
2022-05-11 9:35 4% ` [PATCH v4 2/4] " Chanwoo Choi
[not found] ` <CGME20220512223450eucas1p203b702e114dd2cd1bafcfd7d4c80b638@eucas1p2.samsung.com>
2022-05-12 22:34 0% ` Marek Szyprowski
2022-05-13 4:46 0% ` Chanwoo Choi
2022-05-17 9:21 [PATCH v5 0/4] " Chanwoo Choi
[not found] ` <CGME20220517085448epcas1p46423db24a3211003238b6c5947228923@epcas1p4.samsung.com>
2022-05-17 9:21 4% ` [PATCH v5 2/4] " Chanwoo Choi
2022-06-02 0:48 11% [PATCH 1/3] dt-bindings: interconnect: Update email address Sibi Sankar
2022-06-02 0:48 11% ` [PATCH 2/3] dt-bindings: reset: aoss: Update e-mail address Sibi Sankar
2022-06-02 0:48 11% ` [PATCH 3/3] dt-bindings: reset: pdc: Update email address Sibi Sankar
2022-10-14 21:53 8% [PATCH 5.10] arm64: dts: qcom: sc7180-trogdor: Fixup modem memory region Stephen Boyd
2022-10-16 10:50 0% ` Greg KH
2022-10-16 12:47 0% ` Alex Elder
2022-10-17 18:22 8% [PATCH] " Stephen Boyd
2022-10-27 10:14 0% ` Greg KH
2022-10-27 16:55 3% [PATCH 5.10 00/79] 5.10.151-rc1 review Greg Kroah-Hartman
2022-10-28 12:02 3% [PATCH 5.10 00/73] 5.10.152-rc1 review Greg Kroah-Hartman
[not found] <20221107235654.1769462-1-bryan.odonoghue@linaro.org>
2022-11-07 23:56 6% ` [PATCH v2 14/18] arm64: dts: qcom: sc7280: Add compat qcom,mdss-dsi-ctrl-sc7280 Bryan O'Donoghue
2022-11-08 16:41 0% ` Doug Anderson
2023-07-20 21:02 8% [PATCH] mailmap: Update remaining active codeaurora.org email addresses Bjorn Andersson
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