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From: Xingyu Wu <xingyu.wu@starfivetech.com>
To: <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>,
	"Michael Turquette" <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Conor Dooley <conor@kernel.org>,
	"Emil Renner Berthing" <kernel@esmil.dk>
Cc: Rob Herring <robh+dt@kernel.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Hal Feng <hal.feng@starfivetech.com>,
	Xingyu Wu <xingyu.wu@starfivetech.com>,
	William Qiu <william.qiu@starfivetech.com>,
	<linux-kernel@vger.kernel.org>, <linux-clk@vger.kernel.org>
Subject: [PATCH v4 5/7] dt-bindings: soc: starfive: Add StarFive syscon module
Date: Fri, 12 May 2023 10:20:34 +0800	[thread overview]
Message-ID: <20230512022036.97987-6-xingyu.wu@starfivetech.com> (raw)
In-Reply-To: <20230512022036.97987-1-xingyu.wu@starfivetech.com>

From: William Qiu <william.qiu@starfivetech.com>

Add documentation to describe StarFive System Controller Registers.

Co-developed-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
---
 .../soc/starfive/starfive,jh7110-syscon.yaml  | 67 +++++++++++++++++++
 MAINTAINERS                                   |  7 ++
 2 files changed, 74 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml

diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
new file mode 100644
index 000000000000..26dc99cb0c89
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 SoC system controller
+
+maintainers:
+  - William Qiu <william.qiu@starfivetech.com>
+
+description: |
+  The StarFive JH7110 SoC system controller provides register information such
+  as offset, mask and shift to configure related modules such as MMC and PCIe.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - const: starfive,jh7110-sys-syscon
+          - const: syscon
+          - const: simple-mfd
+      - items:
+          - enum:
+              - starfive,jh7110-aon-syscon
+              - starfive,jh7110-stg-syscon
+          - const: syscon
+
+  reg:
+    maxItems: 1
+
+  clock-controller:
+    $ref: /schemas/clock/starfive,jh7110-pll.yaml#
+    type: object
+
+  "#power-domain-cells":
+    const: 1
+
+required:
+  - compatible
+  - reg
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: starfive,jh7110-aon-syscon
+    then:
+      required:
+        - "#power-domain-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    syscon@10240000 {
+        compatible = "starfive,jh7110-stg-syscon", "syscon";
+        reg = <0x10240000 0x1000>;
+    };
+
+    syscon@13030000 {
+        compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd";
+        reg = <0x13030000 0x1000>;
+    };
+
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 0fb4a703f66f..60bbc3a05d79 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -20093,6 +20093,12 @@ S:	Supported
 F:	Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml
 F:	drivers/clk/starfive/clk-starfive-jh7110-pll.*
 
+STARFIVE JH7110 SYSCON
+M:	William Qiu <william.qiu@starfivetech.com>
+M:	Xingyu Wu <xingyu.wu@starfivetech.com>
+S:	Supported
+F:	Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
+
 STARFIVE JH71X0 CLOCK DRIVERS
 M:	Emil Renner Berthing <kernel@esmil.dk>
 M:	Hal Feng <hal.feng@starfivetech.com>
@@ -20130,6 +20136,7 @@ STARFIVE SOC DRIVERS
 M:	Conor Dooley <conor@kernel.org>
 S:	Maintained
 T:	git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
+F:	Documentation/devicetree/bindings/soc/starfive/
 F:	drivers/soc/starfive/
 
 STARFIVE TRNG DRIVER
-- 
2.25.1


WARNING: multiple messages have this Message-ID (diff)
From: Xingyu Wu <xingyu.wu@starfivetech.com>
To: <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>,
	"Michael Turquette" <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Conor Dooley <conor@kernel.org>,
	"Emil Renner Berthing" <kernel@esmil.dk>
Cc: Rob Herring <robh+dt@kernel.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Hal Feng <hal.feng@starfivetech.com>,
	Xingyu Wu <xingyu.wu@starfivetech.com>,
	William Qiu <william.qiu@starfivetech.com>,
	<linux-kernel@vger.kernel.org>, <linux-clk@vger.kernel.org>
Subject: [PATCH v4 5/7] dt-bindings: soc: starfive: Add StarFive syscon module
Date: Fri, 12 May 2023 10:20:34 +0800	[thread overview]
Message-ID: <20230512022036.97987-6-xingyu.wu@starfivetech.com> (raw)
In-Reply-To: <20230512022036.97987-1-xingyu.wu@starfivetech.com>

From: William Qiu <william.qiu@starfivetech.com>

Add documentation to describe StarFive System Controller Registers.

Co-developed-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
---
 .../soc/starfive/starfive,jh7110-syscon.yaml  | 67 +++++++++++++++++++
 MAINTAINERS                                   |  7 ++
 2 files changed, 74 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml

diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
new file mode 100644
index 000000000000..26dc99cb0c89
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 SoC system controller
+
+maintainers:
+  - William Qiu <william.qiu@starfivetech.com>
+
+description: |
+  The StarFive JH7110 SoC system controller provides register information such
+  as offset, mask and shift to configure related modules such as MMC and PCIe.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - const: starfive,jh7110-sys-syscon
+          - const: syscon
+          - const: simple-mfd
+      - items:
+          - enum:
+              - starfive,jh7110-aon-syscon
+              - starfive,jh7110-stg-syscon
+          - const: syscon
+
+  reg:
+    maxItems: 1
+
+  clock-controller:
+    $ref: /schemas/clock/starfive,jh7110-pll.yaml#
+    type: object
+
+  "#power-domain-cells":
+    const: 1
+
+required:
+  - compatible
+  - reg
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: starfive,jh7110-aon-syscon
+    then:
+      required:
+        - "#power-domain-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    syscon@10240000 {
+        compatible = "starfive,jh7110-stg-syscon", "syscon";
+        reg = <0x10240000 0x1000>;
+    };
+
+    syscon@13030000 {
+        compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd";
+        reg = <0x13030000 0x1000>;
+    };
+
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 0fb4a703f66f..60bbc3a05d79 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -20093,6 +20093,12 @@ S:	Supported
 F:	Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml
 F:	drivers/clk/starfive/clk-starfive-jh7110-pll.*
 
+STARFIVE JH7110 SYSCON
+M:	William Qiu <william.qiu@starfivetech.com>
+M:	Xingyu Wu <xingyu.wu@starfivetech.com>
+S:	Supported
+F:	Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
+
 STARFIVE JH71X0 CLOCK DRIVERS
 M:	Emil Renner Berthing <kernel@esmil.dk>
 M:	Hal Feng <hal.feng@starfivetech.com>
@@ -20130,6 +20136,7 @@ STARFIVE SOC DRIVERS
 M:	Conor Dooley <conor@kernel.org>
 S:	Maintained
 T:	git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
+F:	Documentation/devicetree/bindings/soc/starfive/
 F:	drivers/soc/starfive/
 
 STARFIVE TRNG DRIVER
-- 
2.25.1


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  parent reply	other threads:[~2023-05-12  2:22 UTC|newest]

Thread overview: 102+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-12  2:20 [PATCH v4 0/7] Add PLL clocks driver and syscon for StarFive JH7110 SoC Xingyu Wu
2023-05-12  2:20 ` Xingyu Wu
2023-05-12  2:20 ` [PATCH v4 1/7] dt-bindings: clock: Add StarFive JH7110 PLL clock generator Xingyu Wu
2023-05-12  2:20   ` Xingyu Wu
2023-05-19 13:57   ` Torsten Duwe
2023-05-19 13:57     ` Torsten Duwe
2023-05-19 14:16     ` Conor Dooley
2023-05-19 14:16       ` Conor Dooley
2023-05-23  2:40       ` Xingyu Wu
2023-05-23  2:40         ` Xingyu Wu
2023-05-23  2:42       ` Xingyu Wu
2023-05-23  2:42         ` Xingyu Wu
2023-05-23  2:56       ` Xingyu Wu
2023-05-23  2:56         ` Xingyu Wu
2023-05-23  8:28         ` Conor Dooley
2023-05-23  8:28           ` Conor Dooley
2023-05-23 11:10           ` Torsten Duwe
2023-05-23 11:10             ` Torsten Duwe
2023-05-23 11:28             ` Conor Dooley
2023-05-23 11:28               ` Conor Dooley
2023-05-24  9:00               ` Xingyu Wu
2023-05-24  9:00                 ` Xingyu Wu
2023-05-24 10:19                 ` Conor Dooley
2023-05-24 10:19                   ` Conor Dooley
2023-05-26  7:34                   ` Torsten Duwe
2023-05-26  7:34                     ` Torsten Duwe
2023-05-26 12:23                     ` Conor Dooley
2023-05-26 12:23                       ` Conor Dooley
2023-06-02  9:42                       ` Xingyu Wu
2023-06-02  9:42                         ` Xingyu Wu
2023-06-12  3:06                       ` Xingyu Wu
2023-06-12  3:06                         ` Xingyu Wu
2023-06-02 16:39         ` Torsten Duwe
2023-06-02 16:39           ` Torsten Duwe
2023-06-02 16:43           ` Conor Dooley
2023-06-02 16:43             ` Conor Dooley
2023-06-02 16:57             ` Torsten Duwe
2023-06-02 16:57               ` Torsten Duwe
2023-06-02 16:59               ` Conor Dooley
2023-06-02 16:59                 ` Conor Dooley
2023-06-02 22:56                 ` Torsten Duwe
2023-06-02 22:56                   ` Torsten Duwe
2023-05-12  2:20 ` [PATCH v4 2/7] clk: starfive: Add StarFive JH7110 PLL clock driver Xingyu Wu
2023-05-12  2:20   ` Xingyu Wu
2023-06-01 11:02   ` Emil Renner Berthing
2023-06-01 11:02     ` Emil Renner Berthing
2023-06-02  9:39     ` Xingyu Wu
2023-06-02  9:39       ` Xingyu Wu
2023-06-02 14:53       ` Emil Renner Berthing
2023-06-02 14:53         ` Emil Renner Berthing
2023-05-12  2:20 ` [PATCH v4 3/7] dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs Xingyu Wu
2023-05-12  2:20   ` Xingyu Wu
2023-05-12  6:47   ` Conor Dooley
2023-05-12  6:47     ` Conor Dooley
2023-05-12  8:07     ` Xingyu Wu
2023-05-12  8:07       ` Xingyu Wu
2023-05-12  9:35       ` Conor Dooley
2023-05-12  9:35         ` Conor Dooley
2023-05-12  9:56         ` Xingyu Wu
2023-05-12  9:56           ` Xingyu Wu
2023-05-12 13:49           ` Conor Dooley
2023-05-12 13:49             ` Conor Dooley
2023-05-19  7:59             ` Xingyu Wu
2023-05-19  7:59               ` Xingyu Wu
2023-05-19  8:12               ` Conor Dooley
2023-05-19  8:12                 ` Conor Dooley
2023-05-19  8:26                 ` Xingyu Wu
2023-05-19  8:26                   ` Xingyu Wu
2023-05-12  2:20 ` [PATCH v4 4/7] clk: starfive: jh7110-sys: Modify PLL clocks source Xingyu Wu
2023-05-12  2:20   ` Xingyu Wu
2023-05-12  2:20 ` Xingyu Wu [this message]
2023-05-12  2:20   ` [PATCH v4 5/7] dt-bindings: soc: starfive: Add StarFive syscon module Xingyu Wu
2023-05-12  6:35   ` Krzysztof Kozlowski
2023-05-12  6:35     ` Krzysztof Kozlowski
2023-05-12  6:43     ` Conor Dooley
2023-05-12  6:43       ` Conor Dooley
2023-05-12  6:50       ` Krzysztof Kozlowski
2023-05-12  6:50         ` Krzysztof Kozlowski
2023-05-12  7:24         ` Xingyu Wu
2023-05-12  7:24           ` Xingyu Wu
2023-05-12  7:34           ` Krzysztof Kozlowski
2023-05-12  7:34             ` Krzysztof Kozlowski
2023-05-12  6:50   ` Krzysztof Kozlowski
2023-05-12  6:50     ` Krzysztof Kozlowski
2023-05-12  7:51     ` Xingyu Wu
2023-05-12  7:51       ` Xingyu Wu
2023-05-12 16:15       ` Krzysztof Kozlowski
2023-05-12 16:15         ` Krzysztof Kozlowski
2023-05-12  2:20 ` [PATCH v4 6/7] riscv: dts: starfive: jh7110: Add syscon nodes Xingyu Wu
2023-05-12  2:20   ` Xingyu Wu
2023-05-12  6:36   ` Krzysztof Kozlowski
2023-05-12  6:36     ` Krzysztof Kozlowski
2023-05-12  2:20 ` [PATCH v4 7/7] riscv: dts: starfive: jh7110: Add PLL clock node and modify syscrg node Xingyu Wu
2023-05-12  2:20   ` Xingyu Wu
2023-05-12  6:37   ` Krzysztof Kozlowski
2023-05-12  6:37     ` Krzysztof Kozlowski
2023-05-12  7:15     ` Xingyu Wu
2023-05-12  7:15       ` Xingyu Wu
2023-05-12  7:22       ` Krzysztof Kozlowski
2023-05-12  7:22         ` Krzysztof Kozlowski
2023-05-12  7:25         ` Xingyu Wu
2023-05-12  7:25           ` Xingyu Wu

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