From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> To: Xingyu Wu <xingyu.wu@starfivetech.com>, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Philipp Zabel <p.zabel@pengutronix.de>, Conor Dooley <conor@kernel.org>, Emil Renner Berthing <kernel@esmil.dk> Cc: Rob Herring <robh+dt@kernel.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Hal Feng <hal.feng@starfivetech.com>, William Qiu <william.qiu@starfivetech.com>, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: Re: [PATCH v4 7/7] riscv: dts: starfive: jh7110: Add PLL clock node and modify syscrg node Date: Fri, 12 May 2023 08:37:11 +0200 [thread overview] Message-ID: <c432c26b-27d3-80dc-fe6b-457996234871@linaro.org> (raw) In-Reply-To: <20230512022036.97987-8-xingyu.wu@starfivetech.com> On 12/05/2023 04:20, Xingyu Wu wrote: > Add the PLL clock node for the Starfive JH7110 SoC and > modify the SYSCRG node to add PLL clocks input. > @@ -465,6 +469,12 @@ syscrg: clock-controller@13020000 { > sys_syscon: syscon@13030000 { > compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd"; > reg = <0x0 0x13030000 0x0 0x1000>; > + > + pllclk: clock-controller { > + compatible = "starfive,jh7110-pll"; > + clocks = <&osc>; > + #clock-cells = <1>; This should be part of previous patch. You just added that node. Don't add half of devices but entire device. Best regards, Krzysztof _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
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From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> To: Xingyu Wu <xingyu.wu@starfivetech.com>, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Philipp Zabel <p.zabel@pengutronix.de>, Conor Dooley <conor@kernel.org>, Emil Renner Berthing <kernel@esmil.dk> Cc: Rob Herring <robh+dt@kernel.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Hal Feng <hal.feng@starfivetech.com>, William Qiu <william.qiu@starfivetech.com>, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: Re: [PATCH v4 7/7] riscv: dts: starfive: jh7110: Add PLL clock node and modify syscrg node Date: Fri, 12 May 2023 08:37:11 +0200 [thread overview] Message-ID: <c432c26b-27d3-80dc-fe6b-457996234871@linaro.org> (raw) In-Reply-To: <20230512022036.97987-8-xingyu.wu@starfivetech.com> On 12/05/2023 04:20, Xingyu Wu wrote: > Add the PLL clock node for the Starfive JH7110 SoC and > modify the SYSCRG node to add PLL clocks input. > @@ -465,6 +469,12 @@ syscrg: clock-controller@13020000 { > sys_syscon: syscon@13030000 { > compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd"; > reg = <0x0 0x13030000 0x0 0x1000>; > + > + pllclk: clock-controller { > + compatible = "starfive,jh7110-pll"; > + clocks = <&osc>; > + #clock-cells = <1>; This should be part of previous patch. You just added that node. Don't add half of devices but entire device. Best regards, Krzysztof
next prev parent reply other threads:[~2023-05-12 6:37 UTC|newest] Thread overview: 102+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-05-12 2:20 [PATCH v4 0/7] Add PLL clocks driver and syscon for StarFive JH7110 SoC Xingyu Wu 2023-05-12 2:20 ` Xingyu Wu 2023-05-12 2:20 ` [PATCH v4 1/7] dt-bindings: clock: Add StarFive JH7110 PLL clock generator Xingyu Wu 2023-05-12 2:20 ` Xingyu Wu 2023-05-19 13:57 ` Torsten Duwe 2023-05-19 13:57 ` Torsten Duwe 2023-05-19 14:16 ` Conor Dooley 2023-05-19 14:16 ` Conor Dooley 2023-05-23 2:40 ` Xingyu Wu 2023-05-23 2:40 ` Xingyu Wu 2023-05-23 2:42 ` Xingyu Wu 2023-05-23 2:42 ` Xingyu Wu 2023-05-23 2:56 ` Xingyu Wu 2023-05-23 2:56 ` Xingyu Wu 2023-05-23 8:28 ` Conor Dooley 2023-05-23 8:28 ` Conor Dooley 2023-05-23 11:10 ` Torsten Duwe 2023-05-23 11:10 ` Torsten Duwe 2023-05-23 11:28 ` Conor Dooley 2023-05-23 11:28 ` Conor Dooley 2023-05-24 9:00 ` Xingyu Wu 2023-05-24 9:00 ` Xingyu Wu 2023-05-24 10:19 ` Conor Dooley 2023-05-24 10:19 ` Conor Dooley 2023-05-26 7:34 ` Torsten Duwe 2023-05-26 7:34 ` Torsten Duwe 2023-05-26 12:23 ` Conor Dooley 2023-05-26 12:23 ` Conor Dooley 2023-06-02 9:42 ` Xingyu Wu 2023-06-02 9:42 ` Xingyu Wu 2023-06-12 3:06 ` Xingyu Wu 2023-06-12 3:06 ` Xingyu Wu 2023-06-02 16:39 ` Torsten Duwe 2023-06-02 16:39 ` Torsten Duwe 2023-06-02 16:43 ` Conor Dooley 2023-06-02 16:43 ` Conor Dooley 2023-06-02 16:57 ` Torsten Duwe 2023-06-02 16:57 ` Torsten Duwe 2023-06-02 16:59 ` Conor Dooley 2023-06-02 16:59 ` Conor Dooley 2023-06-02 22:56 ` Torsten Duwe 2023-06-02 22:56 ` Torsten Duwe 2023-05-12 2:20 ` [PATCH v4 2/7] clk: starfive: Add StarFive JH7110 PLL clock driver Xingyu Wu 2023-05-12 2:20 ` Xingyu Wu 2023-06-01 11:02 ` Emil Renner Berthing 2023-06-01 11:02 ` Emil Renner Berthing 2023-06-02 9:39 ` Xingyu Wu 2023-06-02 9:39 ` Xingyu Wu 2023-06-02 14:53 ` Emil Renner Berthing 2023-06-02 14:53 ` Emil Renner Berthing 2023-05-12 2:20 ` [PATCH v4 3/7] dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs Xingyu Wu 2023-05-12 2:20 ` Xingyu Wu 2023-05-12 6:47 ` Conor Dooley 2023-05-12 6:47 ` Conor Dooley 2023-05-12 8:07 ` Xingyu Wu 2023-05-12 8:07 ` Xingyu Wu 2023-05-12 9:35 ` Conor Dooley 2023-05-12 9:35 ` Conor Dooley 2023-05-12 9:56 ` Xingyu Wu 2023-05-12 9:56 ` Xingyu Wu 2023-05-12 13:49 ` Conor Dooley 2023-05-12 13:49 ` Conor Dooley 2023-05-19 7:59 ` Xingyu Wu 2023-05-19 7:59 ` Xingyu Wu 2023-05-19 8:12 ` Conor Dooley 2023-05-19 8:12 ` Conor Dooley 2023-05-19 8:26 ` Xingyu Wu 2023-05-19 8:26 ` Xingyu Wu 2023-05-12 2:20 ` [PATCH v4 4/7] clk: starfive: jh7110-sys: Modify PLL clocks source Xingyu Wu 2023-05-12 2:20 ` Xingyu Wu 2023-05-12 2:20 ` [PATCH v4 5/7] dt-bindings: soc: starfive: Add StarFive syscon module Xingyu Wu 2023-05-12 2:20 ` Xingyu Wu 2023-05-12 6:35 ` Krzysztof Kozlowski 2023-05-12 6:35 ` Krzysztof Kozlowski 2023-05-12 6:43 ` Conor Dooley 2023-05-12 6:43 ` Conor Dooley 2023-05-12 6:50 ` Krzysztof Kozlowski 2023-05-12 6:50 ` Krzysztof Kozlowski 2023-05-12 7:24 ` Xingyu Wu 2023-05-12 7:24 ` Xingyu Wu 2023-05-12 7:34 ` Krzysztof Kozlowski 2023-05-12 7:34 ` Krzysztof Kozlowski 2023-05-12 6:50 ` Krzysztof Kozlowski 2023-05-12 6:50 ` Krzysztof Kozlowski 2023-05-12 7:51 ` Xingyu Wu 2023-05-12 7:51 ` Xingyu Wu 2023-05-12 16:15 ` Krzysztof Kozlowski 2023-05-12 16:15 ` Krzysztof Kozlowski 2023-05-12 2:20 ` [PATCH v4 6/7] riscv: dts: starfive: jh7110: Add syscon nodes Xingyu Wu 2023-05-12 2:20 ` Xingyu Wu 2023-05-12 6:36 ` Krzysztof Kozlowski 2023-05-12 6:36 ` Krzysztof Kozlowski 2023-05-12 2:20 ` [PATCH v4 7/7] riscv: dts: starfive: jh7110: Add PLL clock node and modify syscrg node Xingyu Wu 2023-05-12 2:20 ` Xingyu Wu 2023-05-12 6:37 ` Krzysztof Kozlowski [this message] 2023-05-12 6:37 ` Krzysztof Kozlowski 2023-05-12 7:15 ` Xingyu Wu 2023-05-12 7:15 ` Xingyu Wu 2023-05-12 7:22 ` Krzysztof Kozlowski 2023-05-12 7:22 ` Krzysztof Kozlowski 2023-05-12 7:25 ` Xingyu Wu 2023-05-12 7:25 ` Xingyu Wu
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