Re: [PATCH v4 3/7] dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs

From: Xingyu Wu <xingyu.wu@starfivetech.com>
To: Conor Dooley <conor.dooley@microchip.com>
Cc: <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>,
	"Michael Turquette" <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Conor Dooley <conor@kernel.org>,
	"Emil Renner Berthing" <kernel@esmil.dk>,
	Rob Herring <robh+dt@kernel.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Hal Feng <hal.feng@starfivetech.com>,
	William Qiu <william.qiu@starfivetech.com>,
	<linux-kernel@vger.kernel.org>, <linux-clk@vger.kernel.org>
Subject: Re: [PATCH v4 3/7] dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs
Date: Fri, 12 May 2023 17:56:16 +0800	[thread overview]
Message-ID: <be85aa2a-c72c-5272-ee40-f1265768e7b3@starfivetech.com> (raw)
In-Reply-To: <20230512-backlit-radiated-ded0b38b4a94@wendy>

On 2023/5/12 17:35, Conor Dooley wrote:
> On Fri, May 12, 2023 at 04:07:47PM +0800, Xingyu Wu wrote:
>> On 2023/5/12 14:47, Conor Dooley wrote:
>> > On Fri, May 12, 2023 at 10:20:32AM +0800, Xingyu Wu wrote:
>> >> Add PLL clock inputs from PLL clock generator.
>> >> 
>> >> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>> >> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
>> >> ---
>> >>  .../clock/starfive,jh7110-syscrg.yaml         | 20 +++++++++++++++++--
>> >>  1 file changed, 18 insertions(+), 2 deletions(-)
>> > 
>> > /tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dtb: clock-controller@13020000: clocks: 'oneOf' conditional failed, one must be fixed:
>> > 	[[19], [20], [21], [22], [23], [24], [25], [26], [27]] is too short
>> > 	From schema: /Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
>> > /tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dtb: clock-controller@13020000: clock-names: 'oneOf' conditional failed, one must be fixed:
>> > 	['osc', 'gmac1_rmii_refin', 'gmac1_rgmii_rxin', 'i2stx_bclk_ext', 'i2stx_lrck_ext', 'i2srx_bclk_ext', 'i2srx_lrck_ext', 'tdm_ext', 'mclk_ext'] is too short
>> > 	'i2stx_bclk_ext' was expected
>> > 	'i2stx_lrck_ext' was expected
>> > 	'i2srx_bclk_ext' was expected
>> > 	'i2srx_lrck_ext' was expected
>> > 	'tdm_ext' was expected
>> > 	'mclk_ext' was expected
>> > 	'pll0_out' was expected
>> > 	From schema: /Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
>> > /tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dtb: clock-controller@13020000: clocks: 'oneOf' conditional failed, one must be fixed:
>> > 	[[19], [20], [21], [22], [23], [24], [25], [26], [27]] is too short
>> > 	From schema: Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
>> > /tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dtb: clock-controller@13020000: clock-names: 'oneOf' conditional failed, one must be fixed:
>> > 	['osc', 'gmac1_rmii_refin', 'gmac1_rgmii_rxin', 'i2stx_bclk_ext', 'i2stx_lrck_ext', 'i2srx_bclk_ext', 'i2srx_lrck_ext', 'tdm_ext', 'mclk_ext'] is too short
>> > 	'i2stx_bclk_ext' was expected
>> > 	'i2stx_lrck_ext' was expected
>> > 	'i2srx_bclk_ext' was expected
>> > 	'i2srx_lrck_ext' was expected
>> > 	'tdm_ext' was expected
>> > 	'mclk_ext' was expected
>> > 	'pll0_out' was expected
>> > 	Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
>> > 
>> > This binding change is incompatible with the existing devicetrees for
>> > the visionfive 2.
>> 
>> This looks like less clocks about PLL in SYSCRG node. And I add this in patch 7.
> 
> The existing devicetree is a valid, albeit limited, description of the
> hardware.
> After your changes to the clock driver in this series, but *without* the
> changes to the devicetrees, does the system still function?
> From a quick check of 4/7, it looks like it will not?

I just tested it on the board and the system still worked without the changes
about devicetree. But these clocks' rate were 0 because these could not get
the PLL clocks from devicetree.

Best regards,
Xingyu Wu