From: Xingyu Wu <xingyu.wu@starfivetech.com>
To: Conor Dooley <conor.dooley@microchip.com>, Torsten Duwe <duwe@lst.de>
Cc: <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>,
<yanhong.wang@starfivetech.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Conor Dooley <conor@kernel.org>,
Emil Renner Berthing <kernel@esmil.dk>,
"Rob Herring" <robh+dt@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
"Hal Feng" <hal.feng@starfivetech.com>,
William Qiu <william.qiu@starfivetech.com>,
<linux-kernel@vger.kernel.org>, <linux-clk@vger.kernel.org>
Subject: Re: [PATCH v4 1/7] dt-bindings: clock: Add StarFive JH7110 PLL clock generator
Date: Tue, 23 May 2023 10:56:43 +0800 [thread overview]
Message-ID: <df43411e-8982-74f5-6148-e7281c37dada@starfivetech.com> (raw)
In-Reply-To: <20230519-smokeless-guileless-2a71cae06509@wendy>
On 2023/5/19 22:16, Conor Dooley wrote:
> On Fri, May 19, 2023 at 03:57:33PM +0200, Torsten Duwe wrote:
>> On Fri, May 12, 2023 at 10:20:30AM +0800, Xingyu Wu wrote:
>> [...]
>> > #ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__
>> > #define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__
>> >
>> > +/* PLL clocks */
>> > +#define JH7110_CLK_PLL0_OUT 0
>> > +#define JH7110_CLK_PLL1_OUT 1
>> > +#define JH7110_CLK_PLL2_OUT 2
>>
>> In U-Boot commit 58c9c60b Yanhong Wang added:
>>
>> +
>> +#define JH7110_SYSCLK_PLL0_OUT 190
>> +#define JH7110_SYSCLK_PLL1_OUT 191
>> +#define JH7110_SYSCLK_PLL2_OUT 192
>> +
>> +#define JH7110_SYSCLK_END 193
>>
>> in that respective file.
>>
>> > +#define JH7110_PLLCLK_END 3
>> > +
>> > /* SYSCRG clocks */
>> > #define JH7110_SYSCLK_CPU_ROOT 0
>>
>> If the symbolic names referred to the same items, would it be possible
>> to keep the two files in sync somehow?
>
> Ohh, that's not good.. If you pass the U-Boot dtb to Linux it won't
> understand the numbering. The headers are part of the dt-binding :/
Because PLL driver is separated from SYSCRG drivers in Linux, the numbering
starts from 0. But in Uboot, the PLL driver is included in the SYSCRG driver,
and the number follows the SYSCRG.
Best regards,
Xingyu Wu
WARNING: multiple messages have this Message-ID (diff)
From: Xingyu Wu <xingyu.wu@starfivetech.com>
To: Conor Dooley <conor.dooley@microchip.com>, Torsten Duwe <duwe@lst.de>
Cc: <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>,
<yanhong.wang@starfivetech.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Conor Dooley <conor@kernel.org>,
Emil Renner Berthing <kernel@esmil.dk>,
"Rob Herring" <robh+dt@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
"Hal Feng" <hal.feng@starfivetech.com>,
William Qiu <william.qiu@starfivetech.com>,
<linux-kernel@vger.kernel.org>, <linux-clk@vger.kernel.org>
Subject: Re: [PATCH v4 1/7] dt-bindings: clock: Add StarFive JH7110 PLL clock generator
Date: Tue, 23 May 2023 10:56:43 +0800 [thread overview]
Message-ID: <df43411e-8982-74f5-6148-e7281c37dada@starfivetech.com> (raw)
In-Reply-To: <20230519-smokeless-guileless-2a71cae06509@wendy>
On 2023/5/19 22:16, Conor Dooley wrote:
> On Fri, May 19, 2023 at 03:57:33PM +0200, Torsten Duwe wrote:
>> On Fri, May 12, 2023 at 10:20:30AM +0800, Xingyu Wu wrote:
>> [...]
>> > #ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__
>> > #define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__
>> >
>> > +/* PLL clocks */
>> > +#define JH7110_CLK_PLL0_OUT 0
>> > +#define JH7110_CLK_PLL1_OUT 1
>> > +#define JH7110_CLK_PLL2_OUT 2
>>
>> In U-Boot commit 58c9c60b Yanhong Wang added:
>>
>> +
>> +#define JH7110_SYSCLK_PLL0_OUT 190
>> +#define JH7110_SYSCLK_PLL1_OUT 191
>> +#define JH7110_SYSCLK_PLL2_OUT 192
>> +
>> +#define JH7110_SYSCLK_END 193
>>
>> in that respective file.
>>
>> > +#define JH7110_PLLCLK_END 3
>> > +
>> > /* SYSCRG clocks */
>> > #define JH7110_SYSCLK_CPU_ROOT 0
>>
>> If the symbolic names referred to the same items, would it be possible
>> to keep the two files in sync somehow?
>
> Ohh, that's not good.. If you pass the U-Boot dtb to Linux it won't
> understand the numbering. The headers are part of the dt-binding :/
Because PLL driver is separated from SYSCRG drivers in Linux, the numbering
starts from 0. But in Uboot, the PLL driver is included in the SYSCRG driver,
and the number follows the SYSCRG.
Best regards,
Xingyu Wu
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linux-riscv@lists.infradead.org
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next prev parent reply other threads:[~2023-05-23 2:58 UTC|newest]
Thread overview: 102+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-12 2:20 [PATCH v4 0/7] Add PLL clocks driver and syscon for StarFive JH7110 SoC Xingyu Wu
2023-05-12 2:20 ` Xingyu Wu
2023-05-12 2:20 ` [PATCH v4 1/7] dt-bindings: clock: Add StarFive JH7110 PLL clock generator Xingyu Wu
2023-05-12 2:20 ` Xingyu Wu
2023-05-19 13:57 ` Torsten Duwe
2023-05-19 13:57 ` Torsten Duwe
2023-05-19 14:16 ` Conor Dooley
2023-05-19 14:16 ` Conor Dooley
2023-05-23 2:40 ` Xingyu Wu
2023-05-23 2:40 ` Xingyu Wu
2023-05-23 2:42 ` Xingyu Wu
2023-05-23 2:42 ` Xingyu Wu
2023-05-23 2:56 ` Xingyu Wu [this message]
2023-05-23 2:56 ` Xingyu Wu
2023-05-23 8:28 ` Conor Dooley
2023-05-23 8:28 ` Conor Dooley
2023-05-23 11:10 ` Torsten Duwe
2023-05-23 11:10 ` Torsten Duwe
2023-05-23 11:28 ` Conor Dooley
2023-05-23 11:28 ` Conor Dooley
2023-05-24 9:00 ` Xingyu Wu
2023-05-24 9:00 ` Xingyu Wu
2023-05-24 10:19 ` Conor Dooley
2023-05-24 10:19 ` Conor Dooley
2023-05-26 7:34 ` Torsten Duwe
2023-05-26 7:34 ` Torsten Duwe
2023-05-26 12:23 ` Conor Dooley
2023-05-26 12:23 ` Conor Dooley
2023-06-02 9:42 ` Xingyu Wu
2023-06-02 9:42 ` Xingyu Wu
2023-06-12 3:06 ` Xingyu Wu
2023-06-12 3:06 ` Xingyu Wu
2023-06-02 16:39 ` Torsten Duwe
2023-06-02 16:39 ` Torsten Duwe
2023-06-02 16:43 ` Conor Dooley
2023-06-02 16:43 ` Conor Dooley
2023-06-02 16:57 ` Torsten Duwe
2023-06-02 16:57 ` Torsten Duwe
2023-06-02 16:59 ` Conor Dooley
2023-06-02 16:59 ` Conor Dooley
2023-06-02 22:56 ` Torsten Duwe
2023-06-02 22:56 ` Torsten Duwe
2023-05-12 2:20 ` [PATCH v4 2/7] clk: starfive: Add StarFive JH7110 PLL clock driver Xingyu Wu
2023-05-12 2:20 ` Xingyu Wu
2023-06-01 11:02 ` Emil Renner Berthing
2023-06-01 11:02 ` Emil Renner Berthing
2023-06-02 9:39 ` Xingyu Wu
2023-06-02 9:39 ` Xingyu Wu
2023-06-02 14:53 ` Emil Renner Berthing
2023-06-02 14:53 ` Emil Renner Berthing
2023-05-12 2:20 ` [PATCH v4 3/7] dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs Xingyu Wu
2023-05-12 2:20 ` Xingyu Wu
2023-05-12 6:47 ` Conor Dooley
2023-05-12 6:47 ` Conor Dooley
2023-05-12 8:07 ` Xingyu Wu
2023-05-12 8:07 ` Xingyu Wu
2023-05-12 9:35 ` Conor Dooley
2023-05-12 9:35 ` Conor Dooley
2023-05-12 9:56 ` Xingyu Wu
2023-05-12 9:56 ` Xingyu Wu
2023-05-12 13:49 ` Conor Dooley
2023-05-12 13:49 ` Conor Dooley
2023-05-19 7:59 ` Xingyu Wu
2023-05-19 7:59 ` Xingyu Wu
2023-05-19 8:12 ` Conor Dooley
2023-05-19 8:12 ` Conor Dooley
2023-05-19 8:26 ` Xingyu Wu
2023-05-19 8:26 ` Xingyu Wu
2023-05-12 2:20 ` [PATCH v4 4/7] clk: starfive: jh7110-sys: Modify PLL clocks source Xingyu Wu
2023-05-12 2:20 ` Xingyu Wu
2023-05-12 2:20 ` [PATCH v4 5/7] dt-bindings: soc: starfive: Add StarFive syscon module Xingyu Wu
2023-05-12 2:20 ` Xingyu Wu
2023-05-12 6:35 ` Krzysztof Kozlowski
2023-05-12 6:35 ` Krzysztof Kozlowski
2023-05-12 6:43 ` Conor Dooley
2023-05-12 6:43 ` Conor Dooley
2023-05-12 6:50 ` Krzysztof Kozlowski
2023-05-12 6:50 ` Krzysztof Kozlowski
2023-05-12 7:24 ` Xingyu Wu
2023-05-12 7:24 ` Xingyu Wu
2023-05-12 7:34 ` Krzysztof Kozlowski
2023-05-12 7:34 ` Krzysztof Kozlowski
2023-05-12 6:50 ` Krzysztof Kozlowski
2023-05-12 6:50 ` Krzysztof Kozlowski
2023-05-12 7:51 ` Xingyu Wu
2023-05-12 7:51 ` Xingyu Wu
2023-05-12 16:15 ` Krzysztof Kozlowski
2023-05-12 16:15 ` Krzysztof Kozlowski
2023-05-12 2:20 ` [PATCH v4 6/7] riscv: dts: starfive: jh7110: Add syscon nodes Xingyu Wu
2023-05-12 2:20 ` Xingyu Wu
2023-05-12 6:36 ` Krzysztof Kozlowski
2023-05-12 6:36 ` Krzysztof Kozlowski
2023-05-12 2:20 ` [PATCH v4 7/7] riscv: dts: starfive: jh7110: Add PLL clock node and modify syscrg node Xingyu Wu
2023-05-12 2:20 ` Xingyu Wu
2023-05-12 6:37 ` Krzysztof Kozlowski
2023-05-12 6:37 ` Krzysztof Kozlowski
2023-05-12 7:15 ` Xingyu Wu
2023-05-12 7:15 ` Xingyu Wu
2023-05-12 7:22 ` Krzysztof Kozlowski
2023-05-12 7:22 ` Krzysztof Kozlowski
2023-05-12 7:25 ` Xingyu Wu
2023-05-12 7:25 ` Xingyu Wu
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