From: Xingyu Wu <xingyu.wu@starfivetech.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Cc: William Qiu <william.qiu@starfivetech.com>,
<linux-clk@vger.kernel.org>, Stephen Boyd <sboyd@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Conor Dooley <conor@kernel.org>,
Emil Renner Berthing <kernel@esmil.dk>,
<devicetree@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
"Michael Turquette" <mturquette@baylibre.com>,
Rob Herring <robh+dt@kernel.org>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
<linux-kernel@vger.kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
Hal Feng <hal.feng@starfivetech.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
"Albert Ou" <aou@eecs.berkeley.edu>
Subject: Re: [PATCH v4 5/7] dt-bindings: soc: starfive: Add StarFive syscon module
Date: Fri, 12 May 2023 15:51:27 +0800 [thread overview]
Message-ID: <6cb0a92b-df60-7b04-775e-d7f0147ce737@starfivetech.com> (raw)
In-Reply-To: <20230512065046.bhblj4uci7hnjoof@krzk-bin>
On 2023/5/12 14:50, Krzysztof Kozlowski wrote:
> On Fri, 12 May 2023 10:20:34 +0800, Xingyu Wu wrote:
>> From: William Qiu <william.qiu@starfivetech.com>
>>
>> Add documentation to describe StarFive System Controller Registers.
>>
>> Co-developed-by: Xingyu Wu <xingyu.wu@starfivetech.com>
>> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
>> Reviewed-by: Rob Herring <robh@kernel.org>
>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>> ---
>> .../soc/starfive/starfive,jh7110-syscon.yaml | 67 +++++++++++++++++++
>> MAINTAINERS | 7 ++
>> 2 files changed, 74 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>>
>
> My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
> on your patch (DT_CHECKER_FLAGS is new in v5.13):
>
> yamllint warnings/errors:
>
> dtschema/dtc warnings/errors:
> ./Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml: Unable to find schema file matching $id: http://devicetree.org/schemas/clock/starfive,jh7110-pll.yaml
>
> See https://patchwork.ozlabs.org/patch/1780353
>
> This check can fail if there are any dependencies. The base for a patch
> series is generally the most recent rc1.
>
> If you already ran 'make dt_binding_check' and didn't see the above
> error(s), then make sure 'yamllint' is installed and dt-schema is up to
> date:
>
> pip3 install dtschema --upgrade
>
> Please check and re-submit.
This patch need patch 1 about pll clock driver binding.
Do I need to merge syscon binding and pll binding together?
Best regards,
Xingyu Wu
WARNING: multiple messages have this Message-ID (diff)
From: Xingyu Wu <xingyu.wu@starfivetech.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Cc: William Qiu <william.qiu@starfivetech.com>,
<linux-clk@vger.kernel.org>, Stephen Boyd <sboyd@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Conor Dooley <conor@kernel.org>,
Emil Renner Berthing <kernel@esmil.dk>,
<devicetree@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
"Michael Turquette" <mturquette@baylibre.com>,
Rob Herring <robh+dt@kernel.org>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
<linux-kernel@vger.kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
Hal Feng <hal.feng@starfivetech.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
"Albert Ou" <aou@eecs.berkeley.edu>
Subject: Re: [PATCH v4 5/7] dt-bindings: soc: starfive: Add StarFive syscon module
Date: Fri, 12 May 2023 15:51:27 +0800 [thread overview]
Message-ID: <6cb0a92b-df60-7b04-775e-d7f0147ce737@starfivetech.com> (raw)
In-Reply-To: <20230512065046.bhblj4uci7hnjoof@krzk-bin>
On 2023/5/12 14:50, Krzysztof Kozlowski wrote:
> On Fri, 12 May 2023 10:20:34 +0800, Xingyu Wu wrote:
>> From: William Qiu <william.qiu@starfivetech.com>
>>
>> Add documentation to describe StarFive System Controller Registers.
>>
>> Co-developed-by: Xingyu Wu <xingyu.wu@starfivetech.com>
>> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
>> Reviewed-by: Rob Herring <robh@kernel.org>
>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>> ---
>> .../soc/starfive/starfive,jh7110-syscon.yaml | 67 +++++++++++++++++++
>> MAINTAINERS | 7 ++
>> 2 files changed, 74 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>>
>
> My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
> on your patch (DT_CHECKER_FLAGS is new in v5.13):
>
> yamllint warnings/errors:
>
> dtschema/dtc warnings/errors:
> ./Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml: Unable to find schema file matching $id: http://devicetree.org/schemas/clock/starfive,jh7110-pll.yaml
>
> See https://patchwork.ozlabs.org/patch/1780353
>
> This check can fail if there are any dependencies. The base for a patch
> series is generally the most recent rc1.
>
> If you already ran 'make dt_binding_check' and didn't see the above
> error(s), then make sure 'yamllint' is installed and dt-schema is up to
> date:
>
> pip3 install dtschema --upgrade
>
> Please check and re-submit.
This patch need patch 1 about pll clock driver binding.
Do I need to merge syscon binding and pll binding together?
Best regards,
Xingyu Wu
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next prev parent reply other threads:[~2023-05-12 7:53 UTC|newest]
Thread overview: 102+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-12 2:20 [PATCH v4 0/7] Add PLL clocks driver and syscon for StarFive JH7110 SoC Xingyu Wu
2023-05-12 2:20 ` Xingyu Wu
2023-05-12 2:20 ` [PATCH v4 1/7] dt-bindings: clock: Add StarFive JH7110 PLL clock generator Xingyu Wu
2023-05-12 2:20 ` Xingyu Wu
2023-05-19 13:57 ` Torsten Duwe
2023-05-19 13:57 ` Torsten Duwe
2023-05-19 14:16 ` Conor Dooley
2023-05-19 14:16 ` Conor Dooley
2023-05-23 2:40 ` Xingyu Wu
2023-05-23 2:40 ` Xingyu Wu
2023-05-23 2:42 ` Xingyu Wu
2023-05-23 2:42 ` Xingyu Wu
2023-05-23 2:56 ` Xingyu Wu
2023-05-23 2:56 ` Xingyu Wu
2023-05-23 8:28 ` Conor Dooley
2023-05-23 8:28 ` Conor Dooley
2023-05-23 11:10 ` Torsten Duwe
2023-05-23 11:10 ` Torsten Duwe
2023-05-23 11:28 ` Conor Dooley
2023-05-23 11:28 ` Conor Dooley
2023-05-24 9:00 ` Xingyu Wu
2023-05-24 9:00 ` Xingyu Wu
2023-05-24 10:19 ` Conor Dooley
2023-05-24 10:19 ` Conor Dooley
2023-05-26 7:34 ` Torsten Duwe
2023-05-26 7:34 ` Torsten Duwe
2023-05-26 12:23 ` Conor Dooley
2023-05-26 12:23 ` Conor Dooley
2023-06-02 9:42 ` Xingyu Wu
2023-06-02 9:42 ` Xingyu Wu
2023-06-12 3:06 ` Xingyu Wu
2023-06-12 3:06 ` Xingyu Wu
2023-06-02 16:39 ` Torsten Duwe
2023-06-02 16:39 ` Torsten Duwe
2023-06-02 16:43 ` Conor Dooley
2023-06-02 16:43 ` Conor Dooley
2023-06-02 16:57 ` Torsten Duwe
2023-06-02 16:57 ` Torsten Duwe
2023-06-02 16:59 ` Conor Dooley
2023-06-02 16:59 ` Conor Dooley
2023-06-02 22:56 ` Torsten Duwe
2023-06-02 22:56 ` Torsten Duwe
2023-05-12 2:20 ` [PATCH v4 2/7] clk: starfive: Add StarFive JH7110 PLL clock driver Xingyu Wu
2023-05-12 2:20 ` Xingyu Wu
2023-06-01 11:02 ` Emil Renner Berthing
2023-06-01 11:02 ` Emil Renner Berthing
2023-06-02 9:39 ` Xingyu Wu
2023-06-02 9:39 ` Xingyu Wu
2023-06-02 14:53 ` Emil Renner Berthing
2023-06-02 14:53 ` Emil Renner Berthing
2023-05-12 2:20 ` [PATCH v4 3/7] dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs Xingyu Wu
2023-05-12 2:20 ` Xingyu Wu
2023-05-12 6:47 ` Conor Dooley
2023-05-12 6:47 ` Conor Dooley
2023-05-12 8:07 ` Xingyu Wu
2023-05-12 8:07 ` Xingyu Wu
2023-05-12 9:35 ` Conor Dooley
2023-05-12 9:35 ` Conor Dooley
2023-05-12 9:56 ` Xingyu Wu
2023-05-12 9:56 ` Xingyu Wu
2023-05-12 13:49 ` Conor Dooley
2023-05-12 13:49 ` Conor Dooley
2023-05-19 7:59 ` Xingyu Wu
2023-05-19 7:59 ` Xingyu Wu
2023-05-19 8:12 ` Conor Dooley
2023-05-19 8:12 ` Conor Dooley
2023-05-19 8:26 ` Xingyu Wu
2023-05-19 8:26 ` Xingyu Wu
2023-05-12 2:20 ` [PATCH v4 4/7] clk: starfive: jh7110-sys: Modify PLL clocks source Xingyu Wu
2023-05-12 2:20 ` Xingyu Wu
2023-05-12 2:20 ` [PATCH v4 5/7] dt-bindings: soc: starfive: Add StarFive syscon module Xingyu Wu
2023-05-12 2:20 ` Xingyu Wu
2023-05-12 6:35 ` Krzysztof Kozlowski
2023-05-12 6:35 ` Krzysztof Kozlowski
2023-05-12 6:43 ` Conor Dooley
2023-05-12 6:43 ` Conor Dooley
2023-05-12 6:50 ` Krzysztof Kozlowski
2023-05-12 6:50 ` Krzysztof Kozlowski
2023-05-12 7:24 ` Xingyu Wu
2023-05-12 7:24 ` Xingyu Wu
2023-05-12 7:34 ` Krzysztof Kozlowski
2023-05-12 7:34 ` Krzysztof Kozlowski
2023-05-12 6:50 ` Krzysztof Kozlowski
2023-05-12 6:50 ` Krzysztof Kozlowski
2023-05-12 7:51 ` Xingyu Wu [this message]
2023-05-12 7:51 ` Xingyu Wu
2023-05-12 16:15 ` Krzysztof Kozlowski
2023-05-12 16:15 ` Krzysztof Kozlowski
2023-05-12 2:20 ` [PATCH v4 6/7] riscv: dts: starfive: jh7110: Add syscon nodes Xingyu Wu
2023-05-12 2:20 ` Xingyu Wu
2023-05-12 6:36 ` Krzysztof Kozlowski
2023-05-12 6:36 ` Krzysztof Kozlowski
2023-05-12 2:20 ` [PATCH v4 7/7] riscv: dts: starfive: jh7110: Add PLL clock node and modify syscrg node Xingyu Wu
2023-05-12 2:20 ` Xingyu Wu
2023-05-12 6:37 ` Krzysztof Kozlowski
2023-05-12 6:37 ` Krzysztof Kozlowski
2023-05-12 7:15 ` Xingyu Wu
2023-05-12 7:15 ` Xingyu Wu
2023-05-12 7:22 ` Krzysztof Kozlowski
2023-05-12 7:22 ` Krzysztof Kozlowski
2023-05-12 7:25 ` Xingyu Wu
2023-05-12 7:25 ` Xingyu Wu
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