From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> To: Xingyu Wu <xingyu.wu@starfivetech.com>, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Philipp Zabel <p.zabel@pengutronix.de>, Conor Dooley <conor@kernel.org>, Emil Renner Berthing <kernel@esmil.dk> Cc: Rob Herring <robh+dt@kernel.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Hal Feng <hal.feng@starfivetech.com>, William Qiu <william.qiu@starfivetech.com>, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: Re: [PATCH v4 5/7] dt-bindings: soc: starfive: Add StarFive syscon module Date: Fri, 12 May 2023 08:35:43 +0200 [thread overview] Message-ID: <2fb8c88a-dab5-791b-eefe-c983decad5e8@linaro.org> (raw) In-Reply-To: <20230512022036.97987-6-xingyu.wu@starfivetech.com> On 12/05/2023 04:20, Xingyu Wu wrote: > From: William Qiu <william.qiu@starfivetech.com> > > Add documentation to describe StarFive System Controller Registers. > > Co-developed-by: Xingyu Wu <xingyu.wu@starfivetech.com> > Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> > Reviewed-by: Rob Herring <robh@kernel.org> You made significant changes. Explain them in changelog here and drop the tag. > Signed-off-by: William Qiu <william.qiu@starfivetech.com> > --- > .../soc/starfive/starfive,jh7110-syscon.yaml | 67 +++++++++++++++++++ > MAINTAINERS | 7 ++ > 2 files changed, 74 insertions(+) > create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml > > diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml > new file mode 100644 > index 000000000000..26dc99cb0c89 > --- /dev/null > +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml > @@ -0,0 +1,67 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: StarFive JH7110 SoC system controller > + > +maintainers: > + - William Qiu <william.qiu@starfivetech.com> > + > +description: | > + The StarFive JH7110 SoC system controller provides register information such > + as offset, mask and shift to configure related modules such as MMC and PCIe. > + > +properties: > + compatible: > + oneOf: > + - items: > + - const: starfive,jh7110-sys-syscon > + - const: syscon > + - const: simple-mfd > + - items: > + - enum: > + - starfive,jh7110-aon-syscon > + - starfive,jh7110-stg-syscon > + - const: syscon > + > + reg: > + maxItems: 1 > + > + clock-controller: > + $ref: /schemas/clock/starfive,jh7110-pll.yaml# > + type: object > + > + "#power-domain-cells": > + const: 1 Add it to the existing examples. This part confuses me... why aon appeared here? Why power-controller disappeared? I don't think that Rob or me proposed any of this. > + > +required: > + - compatible > + - reg > + > +allOf: > + - if: > + properties: > + compatible: > + contains: > + const: starfive,jh7110-aon-syscon > + then: > + required: > + - "#power-domain-cells" > + > +additionalProperties: false > + > +examples: > + - | > + syscon@10240000 { > + compatible = "starfive,jh7110-stg-syscon", "syscon"; > + reg = <0x10240000 0x1000>; > + }; > + > + syscon@13030000 { > + compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd"; > + reg = <0x13030000 0x1000>; Why simple-mfd? You do not have any children here. Best regards, Krzysztof
WARNING: multiple messages have this Message-ID (diff)
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> To: Xingyu Wu <xingyu.wu@starfivetech.com>, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Philipp Zabel <p.zabel@pengutronix.de>, Conor Dooley <conor@kernel.org>, Emil Renner Berthing <kernel@esmil.dk> Cc: Rob Herring <robh+dt@kernel.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Hal Feng <hal.feng@starfivetech.com>, William Qiu <william.qiu@starfivetech.com>, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: Re: [PATCH v4 5/7] dt-bindings: soc: starfive: Add StarFive syscon module Date: Fri, 12 May 2023 08:35:43 +0200 [thread overview] Message-ID: <2fb8c88a-dab5-791b-eefe-c983decad5e8@linaro.org> (raw) In-Reply-To: <20230512022036.97987-6-xingyu.wu@starfivetech.com> On 12/05/2023 04:20, Xingyu Wu wrote: > From: William Qiu <william.qiu@starfivetech.com> > > Add documentation to describe StarFive System Controller Registers. > > Co-developed-by: Xingyu Wu <xingyu.wu@starfivetech.com> > Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> > Reviewed-by: Rob Herring <robh@kernel.org> You made significant changes. Explain them in changelog here and drop the tag. > Signed-off-by: William Qiu <william.qiu@starfivetech.com> > --- > .../soc/starfive/starfive,jh7110-syscon.yaml | 67 +++++++++++++++++++ > MAINTAINERS | 7 ++ > 2 files changed, 74 insertions(+) > create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml > > diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml > new file mode 100644 > index 000000000000..26dc99cb0c89 > --- /dev/null > +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml > @@ -0,0 +1,67 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: StarFive JH7110 SoC system controller > + > +maintainers: > + - William Qiu <william.qiu@starfivetech.com> > + > +description: | > + The StarFive JH7110 SoC system controller provides register information such > + as offset, mask and shift to configure related modules such as MMC and PCIe. > + > +properties: > + compatible: > + oneOf: > + - items: > + - const: starfive,jh7110-sys-syscon > + - const: syscon > + - const: simple-mfd > + - items: > + - enum: > + - starfive,jh7110-aon-syscon > + - starfive,jh7110-stg-syscon > + - const: syscon > + > + reg: > + maxItems: 1 > + > + clock-controller: > + $ref: /schemas/clock/starfive,jh7110-pll.yaml# > + type: object > + > + "#power-domain-cells": > + const: 1 Add it to the existing examples. This part confuses me... why aon appeared here? Why power-controller disappeared? I don't think that Rob or me proposed any of this. > + > +required: > + - compatible > + - reg > + > +allOf: > + - if: > + properties: > + compatible: > + contains: > + const: starfive,jh7110-aon-syscon > + then: > + required: > + - "#power-domain-cells" > + > +additionalProperties: false > + > +examples: > + - | > + syscon@10240000 { > + compatible = "starfive,jh7110-stg-syscon", "syscon"; > + reg = <0x10240000 0x1000>; > + }; > + > + syscon@13030000 { > + compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd"; > + reg = <0x13030000 0x1000>; Why simple-mfd? You do not have any children here. Best regards, Krzysztof _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-05-12 6:36 UTC|newest] Thread overview: 102+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-05-12 2:20 [PATCH v4 0/7] Add PLL clocks driver and syscon for StarFive JH7110 SoC Xingyu Wu 2023-05-12 2:20 ` Xingyu Wu 2023-05-12 2:20 ` [PATCH v4 1/7] dt-bindings: clock: Add StarFive JH7110 PLL clock generator Xingyu Wu 2023-05-12 2:20 ` Xingyu Wu 2023-05-19 13:57 ` Torsten Duwe 2023-05-19 13:57 ` Torsten Duwe 2023-05-19 14:16 ` Conor Dooley 2023-05-19 14:16 ` Conor Dooley 2023-05-23 2:40 ` Xingyu Wu 2023-05-23 2:40 ` Xingyu Wu 2023-05-23 2:42 ` Xingyu Wu 2023-05-23 2:42 ` Xingyu Wu 2023-05-23 2:56 ` Xingyu Wu 2023-05-23 2:56 ` Xingyu Wu 2023-05-23 8:28 ` Conor Dooley 2023-05-23 8:28 ` Conor Dooley 2023-05-23 11:10 ` Torsten Duwe 2023-05-23 11:10 ` Torsten Duwe 2023-05-23 11:28 ` Conor Dooley 2023-05-23 11:28 ` Conor Dooley 2023-05-24 9:00 ` Xingyu Wu 2023-05-24 9:00 ` Xingyu Wu 2023-05-24 10:19 ` Conor Dooley 2023-05-24 10:19 ` Conor Dooley 2023-05-26 7:34 ` Torsten Duwe 2023-05-26 7:34 ` Torsten Duwe 2023-05-26 12:23 ` Conor Dooley 2023-05-26 12:23 ` Conor Dooley 2023-06-02 9:42 ` Xingyu Wu 2023-06-02 9:42 ` Xingyu Wu 2023-06-12 3:06 ` Xingyu Wu 2023-06-12 3:06 ` Xingyu Wu 2023-06-02 16:39 ` Torsten Duwe 2023-06-02 16:39 ` Torsten Duwe 2023-06-02 16:43 ` Conor Dooley 2023-06-02 16:43 ` Conor Dooley 2023-06-02 16:57 ` Torsten Duwe 2023-06-02 16:57 ` Torsten Duwe 2023-06-02 16:59 ` Conor Dooley 2023-06-02 16:59 ` Conor Dooley 2023-06-02 22:56 ` Torsten Duwe 2023-06-02 22:56 ` Torsten Duwe 2023-05-12 2:20 ` [PATCH v4 2/7] clk: starfive: Add StarFive JH7110 PLL clock driver Xingyu Wu 2023-05-12 2:20 ` Xingyu Wu 2023-06-01 11:02 ` Emil Renner Berthing 2023-06-01 11:02 ` Emil Renner Berthing 2023-06-02 9:39 ` Xingyu Wu 2023-06-02 9:39 ` Xingyu Wu 2023-06-02 14:53 ` Emil Renner Berthing 2023-06-02 14:53 ` Emil Renner Berthing 2023-05-12 2:20 ` [PATCH v4 3/7] dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs Xingyu Wu 2023-05-12 2:20 ` Xingyu Wu 2023-05-12 6:47 ` Conor Dooley 2023-05-12 6:47 ` Conor Dooley 2023-05-12 8:07 ` Xingyu Wu 2023-05-12 8:07 ` Xingyu Wu 2023-05-12 9:35 ` Conor Dooley 2023-05-12 9:35 ` Conor Dooley 2023-05-12 9:56 ` Xingyu Wu 2023-05-12 9:56 ` Xingyu Wu 2023-05-12 13:49 ` Conor Dooley 2023-05-12 13:49 ` Conor Dooley 2023-05-19 7:59 ` Xingyu Wu 2023-05-19 7:59 ` Xingyu Wu 2023-05-19 8:12 ` Conor Dooley 2023-05-19 8:12 ` Conor Dooley 2023-05-19 8:26 ` Xingyu Wu 2023-05-19 8:26 ` Xingyu Wu 2023-05-12 2:20 ` [PATCH v4 4/7] clk: starfive: jh7110-sys: Modify PLL clocks source Xingyu Wu 2023-05-12 2:20 ` Xingyu Wu 2023-05-12 2:20 ` [PATCH v4 5/7] dt-bindings: soc: starfive: Add StarFive syscon module Xingyu Wu 2023-05-12 2:20 ` Xingyu Wu 2023-05-12 6:35 ` Krzysztof Kozlowski [this message] 2023-05-12 6:35 ` Krzysztof Kozlowski 2023-05-12 6:43 ` Conor Dooley 2023-05-12 6:43 ` Conor Dooley 2023-05-12 6:50 ` Krzysztof Kozlowski 2023-05-12 6:50 ` Krzysztof Kozlowski 2023-05-12 7:24 ` Xingyu Wu 2023-05-12 7:24 ` Xingyu Wu 2023-05-12 7:34 ` Krzysztof Kozlowski 2023-05-12 7:34 ` Krzysztof Kozlowski 2023-05-12 6:50 ` Krzysztof Kozlowski 2023-05-12 6:50 ` Krzysztof Kozlowski 2023-05-12 7:51 ` Xingyu Wu 2023-05-12 7:51 ` Xingyu Wu 2023-05-12 16:15 ` Krzysztof Kozlowski 2023-05-12 16:15 ` Krzysztof Kozlowski 2023-05-12 2:20 ` [PATCH v4 6/7] riscv: dts: starfive: jh7110: Add syscon nodes Xingyu Wu 2023-05-12 2:20 ` Xingyu Wu 2023-05-12 6:36 ` Krzysztof Kozlowski 2023-05-12 6:36 ` Krzysztof Kozlowski 2023-05-12 2:20 ` [PATCH v4 7/7] riscv: dts: starfive: jh7110: Add PLL clock node and modify syscrg node Xingyu Wu 2023-05-12 2:20 ` Xingyu Wu 2023-05-12 6:37 ` Krzysztof Kozlowski 2023-05-12 6:37 ` Krzysztof Kozlowski 2023-05-12 7:15 ` Xingyu Wu 2023-05-12 7:15 ` Xingyu Wu 2023-05-12 7:22 ` Krzysztof Kozlowski 2023-05-12 7:22 ` Krzysztof Kozlowski 2023-05-12 7:25 ` Xingyu Wu 2023-05-12 7:25 ` Xingyu Wu
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