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From: Torsten Duwe <duwe@lst.de>
To: Conor Dooley <conor@kernel.org>
Cc: Xingyu Wu <xingyu.wu@starfivetech.com>,
	Conor Dooley <conor.dooley@microchip.com>,
	linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
	yanhong.wang@starfivetech.com,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Emil Renner Berthing <kernel@esmil.dk>,
	Rob Herring <robh+dt@kernel.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Hal Feng <hal.feng@starfivetech.com>,
	William Qiu <william.qiu@starfivetech.com>,
	linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org
Subject: Re: [PATCH v4 1/7] dt-bindings: clock: Add StarFive JH7110 PLL clock generator
Date: Sat, 3 Jun 2023 00:56:21 +0200	[thread overview]
Message-ID: <20230602225621.GC27915@lst.de> (raw)
In-Reply-To: <20230602-wise-entomb-975a2474d97a@spud>

On Fri, Jun 02, 2023 at 05:59:29PM +0100, Conor Dooley wrote:
> On Fri, Jun 02, 2023 at 06:57:13PM +0200, Torsten Duwe wrote:
> > On Fri, Jun 02, 2023 at 05:43:25PM +0100, Conor Dooley wrote:
> > > > 
> > > > Can you _please_ point me at that "PLL driver" "in Linux" ?
> > > 
> > > It's patch 2 in this series:
> > > https://lore.kernel.org/linux-riscv/20230512022036.97987-1-xingyu.wu@starfivetech.com/T/#m4b2d74c36b3bb961a1187ec5cda1a0a0de875f0e
> > > 
> > Unfortunately, it's not, AFAICS. I'm looking for the driver that
> > will control the PLLs' parameters, grepping for "pll" should yield
> > results, to start with. The thing should act on the SYS_SYSCON iomem,
> > at 0x13030000. Ideally, a DT node should point it there...
> 
> The driver binds against a child node of the syscon @ 1303_0000:
> https://lore.kernel.org/linux-riscv/20230512022036.97987-1-xingyu.wu@starfivetech.com/T/#m882de9210850eb6f871cafc3418f3202ba915de8
> 
> Am I missing something?

No, you're right. Seems I took a wrong turn somewhere. I prefer
patchwork, where available, and probably got into the wrong series.
Found the correct one:

https://patchwork.kernel.org/project/linux-riscv/patch/20230512022036.97987-3-xingyu.wu@starfivetech.com/

Now only the device tree needs to match against that, and U-Boot
needs to remain still functional...

Thanks and sorry for the noise.

	Torsten



WARNING: multiple messages have this Message-ID (diff)
From: Torsten Duwe <duwe@lst.de>
To: Conor Dooley <conor@kernel.org>
Cc: Xingyu Wu <xingyu.wu@starfivetech.com>,
	Conor Dooley <conor.dooley@microchip.com>,
	linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
	yanhong.wang@starfivetech.com,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Emil Renner Berthing <kernel@esmil.dk>,
	Rob Herring <robh+dt@kernel.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Hal Feng <hal.feng@starfivetech.com>,
	William Qiu <william.qiu@starfivetech.com>,
	linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org
Subject: Re: [PATCH v4 1/7] dt-bindings: clock: Add StarFive JH7110 PLL clock generator
Date: Sat, 3 Jun 2023 00:56:21 +0200	[thread overview]
Message-ID: <20230602225621.GC27915@lst.de> (raw)
In-Reply-To: <20230602-wise-entomb-975a2474d97a@spud>

On Fri, Jun 02, 2023 at 05:59:29PM +0100, Conor Dooley wrote:
> On Fri, Jun 02, 2023 at 06:57:13PM +0200, Torsten Duwe wrote:
> > On Fri, Jun 02, 2023 at 05:43:25PM +0100, Conor Dooley wrote:
> > > > 
> > > > Can you _please_ point me at that "PLL driver" "in Linux" ?
> > > 
> > > It's patch 2 in this series:
> > > https://lore.kernel.org/linux-riscv/20230512022036.97987-1-xingyu.wu@starfivetech.com/T/#m4b2d74c36b3bb961a1187ec5cda1a0a0de875f0e
> > > 
> > Unfortunately, it's not, AFAICS. I'm looking for the driver that
> > will control the PLLs' parameters, grepping for "pll" should yield
> > results, to start with. The thing should act on the SYS_SYSCON iomem,
> > at 0x13030000. Ideally, a DT node should point it there...
> 
> The driver binds against a child node of the syscon @ 1303_0000:
> https://lore.kernel.org/linux-riscv/20230512022036.97987-1-xingyu.wu@starfivetech.com/T/#m882de9210850eb6f871cafc3418f3202ba915de8
> 
> Am I missing something?

No, you're right. Seems I took a wrong turn somewhere. I prefer
patchwork, where available, and probably got into the wrong series.
Found the correct one:

https://patchwork.kernel.org/project/linux-riscv/patch/20230512022036.97987-3-xingyu.wu@starfivetech.com/

Now only the device tree needs to match against that, and U-Boot
needs to remain still functional...

Thanks and sorry for the noise.

	Torsten



_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  reply	other threads:[~2023-06-02 22:56 UTC|newest]

Thread overview: 102+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-12  2:20 [PATCH v4 0/7] Add PLL clocks driver and syscon for StarFive JH7110 SoC Xingyu Wu
2023-05-12  2:20 ` Xingyu Wu
2023-05-12  2:20 ` [PATCH v4 1/7] dt-bindings: clock: Add StarFive JH7110 PLL clock generator Xingyu Wu
2023-05-12  2:20   ` Xingyu Wu
2023-05-19 13:57   ` Torsten Duwe
2023-05-19 13:57     ` Torsten Duwe
2023-05-19 14:16     ` Conor Dooley
2023-05-19 14:16       ` Conor Dooley
2023-05-23  2:40       ` Xingyu Wu
2023-05-23  2:40         ` Xingyu Wu
2023-05-23  2:42       ` Xingyu Wu
2023-05-23  2:42         ` Xingyu Wu
2023-05-23  2:56       ` Xingyu Wu
2023-05-23  2:56         ` Xingyu Wu
2023-05-23  8:28         ` Conor Dooley
2023-05-23  8:28           ` Conor Dooley
2023-05-23 11:10           ` Torsten Duwe
2023-05-23 11:10             ` Torsten Duwe
2023-05-23 11:28             ` Conor Dooley
2023-05-23 11:28               ` Conor Dooley
2023-05-24  9:00               ` Xingyu Wu
2023-05-24  9:00                 ` Xingyu Wu
2023-05-24 10:19                 ` Conor Dooley
2023-05-24 10:19                   ` Conor Dooley
2023-05-26  7:34                   ` Torsten Duwe
2023-05-26  7:34                     ` Torsten Duwe
2023-05-26 12:23                     ` Conor Dooley
2023-05-26 12:23                       ` Conor Dooley
2023-06-02  9:42                       ` Xingyu Wu
2023-06-02  9:42                         ` Xingyu Wu
2023-06-12  3:06                       ` Xingyu Wu
2023-06-12  3:06                         ` Xingyu Wu
2023-06-02 16:39         ` Torsten Duwe
2023-06-02 16:39           ` Torsten Duwe
2023-06-02 16:43           ` Conor Dooley
2023-06-02 16:43             ` Conor Dooley
2023-06-02 16:57             ` Torsten Duwe
2023-06-02 16:57               ` Torsten Duwe
2023-06-02 16:59               ` Conor Dooley
2023-06-02 16:59                 ` Conor Dooley
2023-06-02 22:56                 ` Torsten Duwe [this message]
2023-06-02 22:56                   ` Torsten Duwe
2023-05-12  2:20 ` [PATCH v4 2/7] clk: starfive: Add StarFive JH7110 PLL clock driver Xingyu Wu
2023-05-12  2:20   ` Xingyu Wu
2023-06-01 11:02   ` Emil Renner Berthing
2023-06-01 11:02     ` Emil Renner Berthing
2023-06-02  9:39     ` Xingyu Wu
2023-06-02  9:39       ` Xingyu Wu
2023-06-02 14:53       ` Emil Renner Berthing
2023-06-02 14:53         ` Emil Renner Berthing
2023-05-12  2:20 ` [PATCH v4 3/7] dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs Xingyu Wu
2023-05-12  2:20   ` Xingyu Wu
2023-05-12  6:47   ` Conor Dooley
2023-05-12  6:47     ` Conor Dooley
2023-05-12  8:07     ` Xingyu Wu
2023-05-12  8:07       ` Xingyu Wu
2023-05-12  9:35       ` Conor Dooley
2023-05-12  9:35         ` Conor Dooley
2023-05-12  9:56         ` Xingyu Wu
2023-05-12  9:56           ` Xingyu Wu
2023-05-12 13:49           ` Conor Dooley
2023-05-12 13:49             ` Conor Dooley
2023-05-19  7:59             ` Xingyu Wu
2023-05-19  7:59               ` Xingyu Wu
2023-05-19  8:12               ` Conor Dooley
2023-05-19  8:12                 ` Conor Dooley
2023-05-19  8:26                 ` Xingyu Wu
2023-05-19  8:26                   ` Xingyu Wu
2023-05-12  2:20 ` [PATCH v4 4/7] clk: starfive: jh7110-sys: Modify PLL clocks source Xingyu Wu
2023-05-12  2:20   ` Xingyu Wu
2023-05-12  2:20 ` [PATCH v4 5/7] dt-bindings: soc: starfive: Add StarFive syscon module Xingyu Wu
2023-05-12  2:20   ` Xingyu Wu
2023-05-12  6:35   ` Krzysztof Kozlowski
2023-05-12  6:35     ` Krzysztof Kozlowski
2023-05-12  6:43     ` Conor Dooley
2023-05-12  6:43       ` Conor Dooley
2023-05-12  6:50       ` Krzysztof Kozlowski
2023-05-12  6:50         ` Krzysztof Kozlowski
2023-05-12  7:24         ` Xingyu Wu
2023-05-12  7:24           ` Xingyu Wu
2023-05-12  7:34           ` Krzysztof Kozlowski
2023-05-12  7:34             ` Krzysztof Kozlowski
2023-05-12  6:50   ` Krzysztof Kozlowski
2023-05-12  6:50     ` Krzysztof Kozlowski
2023-05-12  7:51     ` Xingyu Wu
2023-05-12  7:51       ` Xingyu Wu
2023-05-12 16:15       ` Krzysztof Kozlowski
2023-05-12 16:15         ` Krzysztof Kozlowski
2023-05-12  2:20 ` [PATCH v4 6/7] riscv: dts: starfive: jh7110: Add syscon nodes Xingyu Wu
2023-05-12  2:20   ` Xingyu Wu
2023-05-12  6:36   ` Krzysztof Kozlowski
2023-05-12  6:36     ` Krzysztof Kozlowski
2023-05-12  2:20 ` [PATCH v4 7/7] riscv: dts: starfive: jh7110: Add PLL clock node and modify syscrg node Xingyu Wu
2023-05-12  2:20   ` Xingyu Wu
2023-05-12  6:37   ` Krzysztof Kozlowski
2023-05-12  6:37     ` Krzysztof Kozlowski
2023-05-12  7:15     ` Xingyu Wu
2023-05-12  7:15       ` Xingyu Wu
2023-05-12  7:22       ` Krzysztof Kozlowski
2023-05-12  7:22         ` Krzysztof Kozlowski
2023-05-12  7:25         ` Xingyu Wu
2023-05-12  7:25           ` Xingyu Wu

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