From: Xingyu Wu <xingyu.wu@starfivetech.com> To: <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>, "Michael Turquette" <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Philipp Zabel <p.zabel@pengutronix.de>, Conor Dooley <conor@kernel.org>, "Emil Renner Berthing" <kernel@esmil.dk> Cc: Rob Herring <robh+dt@kernel.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Hal Feng <hal.feng@starfivetech.com>, Xingyu Wu <xingyu.wu@starfivetech.com>, William Qiu <william.qiu@starfivetech.com>, <linux-kernel@vger.kernel.org>, <linux-clk@vger.kernel.org> Subject: [PATCH v4 6/7] riscv: dts: starfive: jh7110: Add syscon nodes Date: Fri, 12 May 2023 10:20:35 +0800 [thread overview] Message-ID: <20230512022036.97987-7-xingyu.wu@starfivetech.com> (raw) In-Reply-To: <20230512022036.97987-1-xingyu.wu@starfivetech.com> From: William Qiu <william.qiu@starfivetech.com> Add stg_syscon/sys_syscon/aon_syscon nodes for JH7110 Soc. Co-developed-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: William Qiu <william.qiu@starfivetech.com> --- arch/riscv/boot/dts/starfive/jh7110.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 4c5fdb905da8..fa27fd4169a8 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -353,6 +353,11 @@ i2c2: i2c@10050000 { status = "disabled"; }; + stg_syscon: syscon@10240000 { + compatible = "starfive,jh7110-stg-syscon", "syscon"; + reg = <0x0 0x10240000 0x0 0x1000>; + }; + uart3: serial@12000000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x12000000 0x0 0x10000>; @@ -457,6 +462,11 @@ syscrg: clock-controller@13020000 { #reset-cells = <1>; }; + sys_syscon: syscon@13030000 { + compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd"; + reg = <0x0 0x13030000 0x0 0x1000>; + }; + sysgpio: pinctrl@13040000 { compatible = "starfive,jh7110-sys-pinctrl"; reg = <0x0 0x13040000 0x0 0x10000>; @@ -486,6 +496,12 @@ aoncrg: clock-controller@17000000 { #reset-cells = <1>; }; + aon_syscon: syscon@17010000 { + compatible = "starfive,jh7110-aon-syscon", "syscon"; + reg = <0x0 0x17010000 0x0 0x1000>; + #power-domain-cells = <1>; + }; + aongpio: pinctrl@17020000 { compatible = "starfive,jh7110-aon-pinctrl"; reg = <0x0 0x17020000 0x0 0x10000>; -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Xingyu Wu <xingyu.wu@starfivetech.com> To: <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>, "Michael Turquette" <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Philipp Zabel <p.zabel@pengutronix.de>, Conor Dooley <conor@kernel.org>, "Emil Renner Berthing" <kernel@esmil.dk> Cc: Rob Herring <robh+dt@kernel.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Hal Feng <hal.feng@starfivetech.com>, Xingyu Wu <xingyu.wu@starfivetech.com>, William Qiu <william.qiu@starfivetech.com>, <linux-kernel@vger.kernel.org>, <linux-clk@vger.kernel.org> Subject: [PATCH v4 6/7] riscv: dts: starfive: jh7110: Add syscon nodes Date: Fri, 12 May 2023 10:20:35 +0800 [thread overview] Message-ID: <20230512022036.97987-7-xingyu.wu@starfivetech.com> (raw) In-Reply-To: <20230512022036.97987-1-xingyu.wu@starfivetech.com> From: William Qiu <william.qiu@starfivetech.com> Add stg_syscon/sys_syscon/aon_syscon nodes for JH7110 Soc. Co-developed-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: William Qiu <william.qiu@starfivetech.com> --- arch/riscv/boot/dts/starfive/jh7110.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 4c5fdb905da8..fa27fd4169a8 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -353,6 +353,11 @@ i2c2: i2c@10050000 { status = "disabled"; }; + stg_syscon: syscon@10240000 { + compatible = "starfive,jh7110-stg-syscon", "syscon"; + reg = <0x0 0x10240000 0x0 0x1000>; + }; + uart3: serial@12000000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x12000000 0x0 0x10000>; @@ -457,6 +462,11 @@ syscrg: clock-controller@13020000 { #reset-cells = <1>; }; + sys_syscon: syscon@13030000 { + compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd"; + reg = <0x0 0x13030000 0x0 0x1000>; + }; + sysgpio: pinctrl@13040000 { compatible = "starfive,jh7110-sys-pinctrl"; reg = <0x0 0x13040000 0x0 0x10000>; @@ -486,6 +496,12 @@ aoncrg: clock-controller@17000000 { #reset-cells = <1>; }; + aon_syscon: syscon@17010000 { + compatible = "starfive,jh7110-aon-syscon", "syscon"; + reg = <0x0 0x17010000 0x0 0x1000>; + #power-domain-cells = <1>; + }; + aongpio: pinctrl@17020000 { compatible = "starfive,jh7110-aon-pinctrl"; reg = <0x0 0x17020000 0x0 0x10000>; -- 2.25.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-05-12 2:22 UTC|newest] Thread overview: 102+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-05-12 2:20 [PATCH v4 0/7] Add PLL clocks driver and syscon for StarFive JH7110 SoC Xingyu Wu 2023-05-12 2:20 ` Xingyu Wu 2023-05-12 2:20 ` [PATCH v4 1/7] dt-bindings: clock: Add StarFive JH7110 PLL clock generator Xingyu Wu 2023-05-12 2:20 ` Xingyu Wu 2023-05-19 13:57 ` Torsten Duwe 2023-05-19 13:57 ` Torsten Duwe 2023-05-19 14:16 ` Conor Dooley 2023-05-19 14:16 ` Conor Dooley 2023-05-23 2:40 ` Xingyu Wu 2023-05-23 2:40 ` Xingyu Wu 2023-05-23 2:42 ` Xingyu Wu 2023-05-23 2:42 ` Xingyu Wu 2023-05-23 2:56 ` Xingyu Wu 2023-05-23 2:56 ` Xingyu Wu 2023-05-23 8:28 ` Conor Dooley 2023-05-23 8:28 ` Conor Dooley 2023-05-23 11:10 ` Torsten Duwe 2023-05-23 11:10 ` Torsten Duwe 2023-05-23 11:28 ` Conor Dooley 2023-05-23 11:28 ` Conor Dooley 2023-05-24 9:00 ` Xingyu Wu 2023-05-24 9:00 ` Xingyu Wu 2023-05-24 10:19 ` Conor Dooley 2023-05-24 10:19 ` Conor Dooley 2023-05-26 7:34 ` Torsten Duwe 2023-05-26 7:34 ` Torsten Duwe 2023-05-26 12:23 ` Conor Dooley 2023-05-26 12:23 ` Conor Dooley 2023-06-02 9:42 ` Xingyu Wu 2023-06-02 9:42 ` Xingyu Wu 2023-06-12 3:06 ` Xingyu Wu 2023-06-12 3:06 ` Xingyu Wu 2023-06-02 16:39 ` Torsten Duwe 2023-06-02 16:39 ` Torsten Duwe 2023-06-02 16:43 ` Conor Dooley 2023-06-02 16:43 ` Conor Dooley 2023-06-02 16:57 ` Torsten Duwe 2023-06-02 16:57 ` Torsten Duwe 2023-06-02 16:59 ` Conor Dooley 2023-06-02 16:59 ` Conor Dooley 2023-06-02 22:56 ` Torsten Duwe 2023-06-02 22:56 ` Torsten Duwe 2023-05-12 2:20 ` [PATCH v4 2/7] clk: starfive: Add StarFive JH7110 PLL clock driver Xingyu Wu 2023-05-12 2:20 ` Xingyu Wu 2023-06-01 11:02 ` Emil Renner Berthing 2023-06-01 11:02 ` Emil Renner Berthing 2023-06-02 9:39 ` Xingyu Wu 2023-06-02 9:39 ` Xingyu Wu 2023-06-02 14:53 ` Emil Renner Berthing 2023-06-02 14:53 ` Emil Renner Berthing 2023-05-12 2:20 ` [PATCH v4 3/7] dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs Xingyu Wu 2023-05-12 2:20 ` Xingyu Wu 2023-05-12 6:47 ` Conor Dooley 2023-05-12 6:47 ` Conor Dooley 2023-05-12 8:07 ` Xingyu Wu 2023-05-12 8:07 ` Xingyu Wu 2023-05-12 9:35 ` Conor Dooley 2023-05-12 9:35 ` Conor Dooley 2023-05-12 9:56 ` Xingyu Wu 2023-05-12 9:56 ` Xingyu Wu 2023-05-12 13:49 ` Conor Dooley 2023-05-12 13:49 ` Conor Dooley 2023-05-19 7:59 ` Xingyu Wu 2023-05-19 7:59 ` Xingyu Wu 2023-05-19 8:12 ` Conor Dooley 2023-05-19 8:12 ` Conor Dooley 2023-05-19 8:26 ` Xingyu Wu 2023-05-19 8:26 ` Xingyu Wu 2023-05-12 2:20 ` [PATCH v4 4/7] clk: starfive: jh7110-sys: Modify PLL clocks source Xingyu Wu 2023-05-12 2:20 ` Xingyu Wu 2023-05-12 2:20 ` [PATCH v4 5/7] dt-bindings: soc: starfive: Add StarFive syscon module Xingyu Wu 2023-05-12 2:20 ` Xingyu Wu 2023-05-12 6:35 ` Krzysztof Kozlowski 2023-05-12 6:35 ` Krzysztof Kozlowski 2023-05-12 6:43 ` Conor Dooley 2023-05-12 6:43 ` Conor Dooley 2023-05-12 6:50 ` Krzysztof Kozlowski 2023-05-12 6:50 ` Krzysztof Kozlowski 2023-05-12 7:24 ` Xingyu Wu 2023-05-12 7:24 ` Xingyu Wu 2023-05-12 7:34 ` Krzysztof Kozlowski 2023-05-12 7:34 ` Krzysztof Kozlowski 2023-05-12 6:50 ` Krzysztof Kozlowski 2023-05-12 6:50 ` Krzysztof Kozlowski 2023-05-12 7:51 ` Xingyu Wu 2023-05-12 7:51 ` Xingyu Wu 2023-05-12 16:15 ` Krzysztof Kozlowski 2023-05-12 16:15 ` Krzysztof Kozlowski 2023-05-12 2:20 ` Xingyu Wu [this message] 2023-05-12 2:20 ` [PATCH v4 6/7] riscv: dts: starfive: jh7110: Add syscon nodes Xingyu Wu 2023-05-12 6:36 ` Krzysztof Kozlowski 2023-05-12 6:36 ` Krzysztof Kozlowski 2023-05-12 2:20 ` [PATCH v4 7/7] riscv: dts: starfive: jh7110: Add PLL clock node and modify syscrg node Xingyu Wu 2023-05-12 2:20 ` Xingyu Wu 2023-05-12 6:37 ` Krzysztof Kozlowski 2023-05-12 6:37 ` Krzysztof Kozlowski 2023-05-12 7:15 ` Xingyu Wu 2023-05-12 7:15 ` Xingyu Wu 2023-05-12 7:22 ` Krzysztof Kozlowski 2023-05-12 7:22 ` Krzysztof Kozlowski 2023-05-12 7:25 ` Xingyu Wu 2023-05-12 7:25 ` Xingyu Wu
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