From: Torsten Duwe <duwe@lst.de> To: Conor Dooley <conor.dooley@microchip.com> Cc: Xingyu Wu <xingyu.wu@starfivetech.com>, <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>, <yanhong.wang@starfivetech.com>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Philipp Zabel <p.zabel@pengutronix.de>, Conor Dooley <conor@kernel.org>, Emil Renner Berthing <kernel@esmil.dk>, Rob Herring <robh+dt@kernel.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Hal Feng <hal.feng@starfivetech.com>, William Qiu <william.qiu@starfivetech.com>, <linux-kernel@vger.kernel.org>, <linux-clk@vger.kernel.org> Subject: Re: [PATCH v4 1/7] dt-bindings: clock: Add StarFive JH7110 PLL clock generator Date: Tue, 23 May 2023 13:10:06 +0200 [thread overview] Message-ID: <20230523131006.46997d84@blackhole.lan> (raw) In-Reply-To: <20230523-fondue-monotype-0c751a8f0c13@wendy> On Tue, 23 May 2023 09:28:39 +0100 Conor Dooley <conor.dooley@microchip.com> wrote: > On Tue, May 23, 2023 at 10:56:43AM +0800, Xingyu Wu wrote: > > On 2023/5/19 22:16, Conor Dooley wrote: > > > On Fri, May 19, 2023 at 03:57:33PM +0200, Torsten Duwe wrote: > > >> On Fri, May 12, 2023 at 10:20:30AM +0800, Xingyu Wu wrote: > > >> [...] > > >> > +/* PLL clocks */ > > >> > +#define JH7110_CLK_PLL0_OUT 0 > > >> > +#define JH7110_CLK_PLL1_OUT 1 > > >> > +#define JH7110_CLK_PLL2_OUT 2 > > >> > > >> In U-Boot commit 58c9c60b Yanhong Wang added: > > >> > > >> + > > >> +#define JH7110_SYSCLK_PLL0_OUT 190 > > >> +#define JH7110_SYSCLK_PLL1_OUT 191 > > >> +#define JH7110_SYSCLK_PLL2_OUT 192 > > >> + > > >> +#define JH7110_SYSCLK_END 193 [...] > > > Ohh, that's not good.. If you pass the U-Boot dtb to Linux it > > > won't understand the numbering. The headers are part of the > > > dt-binding :/ In fact, the clock index >= 190 makes linux hang on boot, waiting with EPROBE_DEFER for every device's clock, because the sysclk driver errors out with EINVAL (jh7110_sysclk_get()). > > Because PLL driver is separated from SYSCRG drivers in Linux, the > > numbering starts from 0. But in Uboot, the PLL driver is included > > in the SYSCRG driver, and the number follows the SYSCRG. > > Unfortunately, how you choose to construct your drivers has nothing to > do with this. > These defines/numbers appear in the dts and are part of the DT ABI. > The same dts is supposed to work for Linux & U-Boot. The JH7110 has 6 blocks of 64k iomem in that functional area: {SYS,STG,AON} x {CRG,SYSCON}. None of these has 190 clocks. The good news: the current DTS, as proposed here and in U-Boot master, provides nodes for all 6 entities. The bad news is that the clock assignments to those nodes and their numbering is messed up. AFAICT PLL{0,1,2} _are_ generated in SYS_SYSCON and thus U-Boot gets it wrong, in addition to the erroneous DTS. Torsten
WARNING: multiple messages have this Message-ID (diff)
From: Torsten Duwe <duwe@lst.de> To: Conor Dooley <conor.dooley@microchip.com> Cc: Xingyu Wu <xingyu.wu@starfivetech.com>, <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>, <yanhong.wang@starfivetech.com>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Philipp Zabel <p.zabel@pengutronix.de>, Conor Dooley <conor@kernel.org>, Emil Renner Berthing <kernel@esmil.dk>, Rob Herring <robh+dt@kernel.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Hal Feng <hal.feng@starfivetech.com>, William Qiu <william.qiu@starfivetech.com>, <linux-kernel@vger.kernel.org>, <linux-clk@vger.kernel.org> Subject: Re: [PATCH v4 1/7] dt-bindings: clock: Add StarFive JH7110 PLL clock generator Date: Tue, 23 May 2023 13:10:06 +0200 [thread overview] Message-ID: <20230523131006.46997d84@blackhole.lan> (raw) In-Reply-To: <20230523-fondue-monotype-0c751a8f0c13@wendy> On Tue, 23 May 2023 09:28:39 +0100 Conor Dooley <conor.dooley@microchip.com> wrote: > On Tue, May 23, 2023 at 10:56:43AM +0800, Xingyu Wu wrote: > > On 2023/5/19 22:16, Conor Dooley wrote: > > > On Fri, May 19, 2023 at 03:57:33PM +0200, Torsten Duwe wrote: > > >> On Fri, May 12, 2023 at 10:20:30AM +0800, Xingyu Wu wrote: > > >> [...] > > >> > +/* PLL clocks */ > > >> > +#define JH7110_CLK_PLL0_OUT 0 > > >> > +#define JH7110_CLK_PLL1_OUT 1 > > >> > +#define JH7110_CLK_PLL2_OUT 2 > > >> > > >> In U-Boot commit 58c9c60b Yanhong Wang added: > > >> > > >> + > > >> +#define JH7110_SYSCLK_PLL0_OUT 190 > > >> +#define JH7110_SYSCLK_PLL1_OUT 191 > > >> +#define JH7110_SYSCLK_PLL2_OUT 192 > > >> + > > >> +#define JH7110_SYSCLK_END 193 [...] > > > Ohh, that's not good.. If you pass the U-Boot dtb to Linux it > > > won't understand the numbering. The headers are part of the > > > dt-binding :/ In fact, the clock index >= 190 makes linux hang on boot, waiting with EPROBE_DEFER for every device's clock, because the sysclk driver errors out with EINVAL (jh7110_sysclk_get()). > > Because PLL driver is separated from SYSCRG drivers in Linux, the > > numbering starts from 0. But in Uboot, the PLL driver is included > > in the SYSCRG driver, and the number follows the SYSCRG. > > Unfortunately, how you choose to construct your drivers has nothing to > do with this. > These defines/numbers appear in the dts and are part of the DT ABI. > The same dts is supposed to work for Linux & U-Boot. The JH7110 has 6 blocks of 64k iomem in that functional area: {SYS,STG,AON} x {CRG,SYSCON}. None of these has 190 clocks. The good news: the current DTS, as proposed here and in U-Boot master, provides nodes for all 6 entities. The bad news is that the clock assignments to those nodes and their numbering is messed up. AFAICT PLL{0,1,2} _are_ generated in SYS_SYSCON and thus U-Boot gets it wrong, in addition to the erroneous DTS. Torsten _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-05-23 11:10 UTC|newest] Thread overview: 102+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-05-12 2:20 [PATCH v4 0/7] Add PLL clocks driver and syscon for StarFive JH7110 SoC Xingyu Wu 2023-05-12 2:20 ` Xingyu Wu 2023-05-12 2:20 ` [PATCH v4 1/7] dt-bindings: clock: Add StarFive JH7110 PLL clock generator Xingyu Wu 2023-05-12 2:20 ` Xingyu Wu 2023-05-19 13:57 ` Torsten Duwe 2023-05-19 13:57 ` Torsten Duwe 2023-05-19 14:16 ` Conor Dooley 2023-05-19 14:16 ` Conor Dooley 2023-05-23 2:40 ` Xingyu Wu 2023-05-23 2:40 ` Xingyu Wu 2023-05-23 2:42 ` Xingyu Wu 2023-05-23 2:42 ` Xingyu Wu 2023-05-23 2:56 ` Xingyu Wu 2023-05-23 2:56 ` Xingyu Wu 2023-05-23 8:28 ` Conor Dooley 2023-05-23 8:28 ` Conor Dooley 2023-05-23 11:10 ` Torsten Duwe [this message] 2023-05-23 11:10 ` Torsten Duwe 2023-05-23 11:28 ` Conor Dooley 2023-05-23 11:28 ` Conor Dooley 2023-05-24 9:00 ` Xingyu Wu 2023-05-24 9:00 ` Xingyu Wu 2023-05-24 10:19 ` Conor Dooley 2023-05-24 10:19 ` Conor Dooley 2023-05-26 7:34 ` Torsten Duwe 2023-05-26 7:34 ` Torsten Duwe 2023-05-26 12:23 ` Conor Dooley 2023-05-26 12:23 ` Conor Dooley 2023-06-02 9:42 ` Xingyu Wu 2023-06-02 9:42 ` Xingyu Wu 2023-06-12 3:06 ` Xingyu Wu 2023-06-12 3:06 ` Xingyu Wu 2023-06-02 16:39 ` Torsten Duwe 2023-06-02 16:39 ` Torsten Duwe 2023-06-02 16:43 ` Conor Dooley 2023-06-02 16:43 ` Conor Dooley 2023-06-02 16:57 ` Torsten Duwe 2023-06-02 16:57 ` Torsten Duwe 2023-06-02 16:59 ` Conor Dooley 2023-06-02 16:59 ` Conor Dooley 2023-06-02 22:56 ` Torsten Duwe 2023-06-02 22:56 ` Torsten Duwe 2023-05-12 2:20 ` [PATCH v4 2/7] clk: starfive: Add StarFive JH7110 PLL clock driver Xingyu Wu 2023-05-12 2:20 ` Xingyu Wu 2023-06-01 11:02 ` Emil Renner Berthing 2023-06-01 11:02 ` Emil Renner Berthing 2023-06-02 9:39 ` Xingyu Wu 2023-06-02 9:39 ` Xingyu Wu 2023-06-02 14:53 ` Emil Renner Berthing 2023-06-02 14:53 ` Emil Renner Berthing 2023-05-12 2:20 ` [PATCH v4 3/7] dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs Xingyu Wu 2023-05-12 2:20 ` Xingyu Wu 2023-05-12 6:47 ` Conor Dooley 2023-05-12 6:47 ` Conor Dooley 2023-05-12 8:07 ` Xingyu Wu 2023-05-12 8:07 ` Xingyu Wu 2023-05-12 9:35 ` Conor Dooley 2023-05-12 9:35 ` Conor Dooley 2023-05-12 9:56 ` Xingyu Wu 2023-05-12 9:56 ` Xingyu Wu 2023-05-12 13:49 ` Conor Dooley 2023-05-12 13:49 ` Conor Dooley 2023-05-19 7:59 ` Xingyu Wu 2023-05-19 7:59 ` Xingyu Wu 2023-05-19 8:12 ` Conor Dooley 2023-05-19 8:12 ` Conor Dooley 2023-05-19 8:26 ` Xingyu Wu 2023-05-19 8:26 ` Xingyu Wu 2023-05-12 2:20 ` [PATCH v4 4/7] clk: starfive: jh7110-sys: Modify PLL clocks source Xingyu Wu 2023-05-12 2:20 ` Xingyu Wu 2023-05-12 2:20 ` [PATCH v4 5/7] dt-bindings: soc: starfive: Add StarFive syscon module Xingyu Wu 2023-05-12 2:20 ` Xingyu Wu 2023-05-12 6:35 ` Krzysztof Kozlowski 2023-05-12 6:35 ` Krzysztof Kozlowski 2023-05-12 6:43 ` Conor Dooley 2023-05-12 6:43 ` Conor Dooley 2023-05-12 6:50 ` Krzysztof Kozlowski 2023-05-12 6:50 ` Krzysztof Kozlowski 2023-05-12 7:24 ` Xingyu Wu 2023-05-12 7:24 ` Xingyu Wu 2023-05-12 7:34 ` Krzysztof Kozlowski 2023-05-12 7:34 ` Krzysztof Kozlowski 2023-05-12 6:50 ` Krzysztof Kozlowski 2023-05-12 6:50 ` Krzysztof Kozlowski 2023-05-12 7:51 ` Xingyu Wu 2023-05-12 7:51 ` Xingyu Wu 2023-05-12 16:15 ` Krzysztof Kozlowski 2023-05-12 16:15 ` Krzysztof Kozlowski 2023-05-12 2:20 ` [PATCH v4 6/7] riscv: dts: starfive: jh7110: Add syscon nodes Xingyu Wu 2023-05-12 2:20 ` Xingyu Wu 2023-05-12 6:36 ` Krzysztof Kozlowski 2023-05-12 6:36 ` Krzysztof Kozlowski 2023-05-12 2:20 ` [PATCH v4 7/7] riscv: dts: starfive: jh7110: Add PLL clock node and modify syscrg node Xingyu Wu 2023-05-12 2:20 ` Xingyu Wu 2023-05-12 6:37 ` Krzysztof Kozlowski 2023-05-12 6:37 ` Krzysztof Kozlowski 2023-05-12 7:15 ` Xingyu Wu 2023-05-12 7:15 ` Xingyu Wu 2023-05-12 7:22 ` Krzysztof Kozlowski 2023-05-12 7:22 ` Krzysztof Kozlowski 2023-05-12 7:25 ` Xingyu Wu 2023-05-12 7:25 ` Xingyu Wu
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20230523131006.46997d84@blackhole.lan \ --to=duwe@lst.de \ --cc=aou@eecs.berkeley.edu \ --cc=conor.dooley@microchip.com \ --cc=conor@kernel.org \ --cc=devicetree@vger.kernel.org \ --cc=hal.feng@starfivetech.com \ --cc=kernel@esmil.dk \ --cc=krzysztof.kozlowski+dt@linaro.org \ --cc=linux-clk@vger.kernel.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-riscv@lists.infradead.org \ --cc=mturquette@baylibre.com \ --cc=p.zabel@pengutronix.de \ --cc=palmer@dabbelt.com \ --cc=paul.walmsley@sifive.com \ --cc=robh+dt@kernel.org \ --cc=sboyd@kernel.org \ --cc=william.qiu@starfivetech.com \ --cc=xingyu.wu@starfivetech.com \ --cc=yanhong.wang@starfivetech.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.