* [U-Boot] (no subject)
@ 2012-09-19 0:02 Troy Kisky
2012-09-19 0:02 ` [U-Boot] [PATCH 01/11] imximage: make header variable length Troy Kisky
` (11 more replies)
0 siblings, 12 replies; 430+ messages in thread
From: Troy Kisky @ 2012-09-19 0:02 UTC (permalink / raw)
To: u-boot
This is the 1st part of a series meant to add mx6solo/mx6duallite
support for a saberlite. I stopped at the last patch because
with it applied, Linux will no longer boot. However, the same
plugin code used under imx-android-r13.3 will work fine.
So, the last patch in the series is not ready to be applied.
I also, tried initializing in the normal manner and running
the plugin with nothing to do. That also fails to boot Linux.
Any advice????
Thanks
Troy
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH 01/11] imximage: make header variable length
2012-09-19 0:02 [U-Boot] (no subject) Troy Kisky
@ 2012-09-19 0:02 ` Troy Kisky
2012-09-19 0:03 ` [U-Boot] [PATCH 02/11] imximage: check dcd_len as entries added Troy Kisky
` (10 subsequent siblings)
11 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-09-19 0:02 UTC (permalink / raw)
To: u-boot
Also, the header offset is no longer
right before the code starts.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
tools/imximage.c | 142 +++++++++++++++++++++++++++++++-----------------------
tools/imximage.h | 10 ++--
2 files changed, 87 insertions(+), 65 deletions(-)
diff --git a/tools/imximage.c b/tools/imximage.c
index 03a7716..25d3b74 100644
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -65,12 +65,15 @@ static table_entry_t imximage_versions[] = {
{-1, "", " (Invalid)", },
};
-static struct imx_header imximage_header;
static uint32_t imximage_version;
static set_dcd_val_t set_dcd_val;
static set_dcd_rst_t set_dcd_rst;
static set_imx_hdr_t set_imx_hdr;
+static set_imx_size_t set_imx_size;
+static uint32_t g_flash_offset;
+
+static struct image_type_params imximage_params;
static uint32_t get_cfg_value(char *token, char *name, int linenr)
{
@@ -207,85 +210,79 @@ static void set_dcd_rst_v2(struct imx_header *imxhdr, uint32_t dcd_len,
dcd_v2->write_dcd_command.param = DCD_COMMAND_PARAM;
}
-static void set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,
- struct stat *sbuf,
- struct mkimage_params *params)
+static int set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,
+ uint32_t entry_point, uint32_t flash_offset)
{
imx_header_v1_t *hdr_v1 = &imxhdr->header.hdr_v1;
flash_header_v1_t *fhdr_v1 = &hdr_v1->fhdr;
dcd_v1_t *dcd_v1 = &hdr_v1->dcd_table;
- uint32_t base_offset;
-
- /* Exit if there is no BOOT_FROM field specifying the flash_offset */
- if(imxhdr->flash_offset == FLASH_OFFSET_UNDEFINED) {
- fprintf(stderr, "Error: Header v1: No BOOT_FROM tag in %s\n",
- params->imagename);
- exit(EXIT_FAILURE);
- }
+ uint32_t hdr_base;
+ uint32_t header_length = (((char *)&dcd_v1->addr_data[dcd_len].addr)
+ - ((char *)imxhdr));
/* Set magic number */
fhdr_v1->app_code_barker = APP_CODE_BARKER;
- fhdr_v1->app_dest_ptr = params->addr;
- fhdr_v1->app_dest_ptr = params->ep - imxhdr->flash_offset -
- sizeof(struct imx_header);
- fhdr_v1->app_code_jump_vector = params->ep;
+ hdr_base = entry_point - header_length;
+ fhdr_v1->app_dest_ptr = hdr_base - flash_offset;
+ fhdr_v1->app_code_jump_vector = entry_point;
- base_offset = fhdr_v1->app_dest_ptr + imxhdr->flash_offset ;
- fhdr_v1->dcd_ptr_ptr =
- (uint32_t) (offsetof(flash_header_v1_t, dcd_ptr) -
- offsetof(flash_header_v1_t, app_code_jump_vector) +
- base_offset);
-
- fhdr_v1->dcd_ptr = base_offset +
- offsetof(imx_header_v1_t, dcd_table);
-
- /* The external flash header must be at the end of the DCD table */
- dcd_v1->addr_data[dcd_len].type = sbuf->st_size +
- imxhdr->flash_offset +
- sizeof(struct imx_header);
+ fhdr_v1->dcd_ptr_ptr = hdr_base + offsetof(flash_header_v1_t, dcd_ptr);
+ fhdr_v1->dcd_ptr = hdr_base + offsetof(imx_header_v1_t, dcd_table);
/* Security feature are not supported */
fhdr_v1->app_code_csf = 0;
fhdr_v1->super_root_key = 0;
+ return header_length;
+}
+
+static void set_imx_size_v1(struct imx_header *imxhdr, uint32_t file_size,
+ uint32_t flash_offset)
+{
+ uint32_t *p = (uint32_t *)(((char *)imxhdr)
+ + imximage_params.header_size);
+
+ /* The external flash header must be at the end of the DCD table */
+ /* file_size includes header */
+ p[-1] = file_size + flash_offset;
}
-static void set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t dcd_len,
- struct stat *sbuf,
- struct mkimage_params *params)
+static int set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t dcd_len,
+ uint32_t entry_point, uint32_t flash_offset)
{
imx_header_v2_t *hdr_v2 = &imxhdr->header.hdr_v2;
flash_header_v2_t *fhdr_v2 = &hdr_v2->fhdr;
-
- /* Exit if there is no BOOT_FROM field specifying the flash_offset */
- if(imxhdr->flash_offset == FLASH_OFFSET_UNDEFINED) {
- fprintf(stderr, "Error: Header v2: No BOOT_FROM tag in %s\n",
- params->imagename);
- exit(EXIT_FAILURE);
- }
+ uint32_t hdr_base;
+ uint32_t header_length = (dcd_len) ?
+ (char *)&hdr_v2->dcd_table.addr_data[dcd_len] - ((char*)imxhdr)
+ : offsetof(imx_header_v2_t, dcd_table);
/* Set magic number */
fhdr_v2->header.tag = IVT_HEADER_TAG; /* 0xD1 */
fhdr_v2->header.length = cpu_to_be16(sizeof(flash_header_v2_t));
fhdr_v2->header.version = IVT_VERSION; /* 0x40 */
- fhdr_v2->entry = params->ep;
+ fhdr_v2->entry = entry_point;
fhdr_v2->reserved1 = fhdr_v2->reserved2 = 0;
- fhdr_v2->self = params->ep - sizeof(struct imx_header);
-
- fhdr_v2->dcd_ptr = fhdr_v2->self +
- offsetof(imx_header_v2_t, dcd_table);
+ fhdr_v2->self = hdr_base = entry_point - header_length;
- fhdr_v2->boot_data_ptr = fhdr_v2->self +
- offsetof(imx_header_v2_t, boot_data);
-
- hdr_v2->boot_data.start = fhdr_v2->self - imxhdr->flash_offset;
- hdr_v2->boot_data.size = sbuf->st_size +
- imxhdr->flash_offset +
- sizeof(struct imx_header);
+ fhdr_v2->dcd_ptr = (dcd_len) ? hdr_base
+ + offsetof(imx_header_v2_t, dcd_table) : 0;
+ fhdr_v2->boot_data_ptr = hdr_base
+ + offsetof(imx_header_v2_t, boot_data);
+ hdr_v2->boot_data.start = hdr_base - flash_offset;
/* Security feature are not supported */
fhdr_v2->csf = 0;
+ return header_length;
+}
+
+static void set_imx_size_v2(struct imx_header *imxhdr, uint32_t file_size,
+ uint32_t flash_offset)
+{
+ imx_header_v2_t *hdr_v2 = &imxhdr->header.hdr_v2;
+ /* file_size includes header */
+ hdr_v2->boot_data.size = file_size + flash_offset;
}
static void set_hdr_func(struct imx_header *imxhdr)
@@ -295,11 +292,13 @@ static void set_hdr_func(struct imx_header *imxhdr)
set_dcd_val = set_dcd_val_v1;
set_dcd_rst = set_dcd_rst_v1;
set_imx_hdr = set_imx_hdr_v1;
+ set_imx_size = set_imx_size_v1;
break;
case IMXIMAGE_V2:
set_dcd_val = set_dcd_val_v2;
set_dcd_rst = set_dcd_rst_v2;
set_imx_hdr = set_imx_hdr_v2;
+ set_imx_size = set_imx_size_v2;
break;
default:
err_imximage_version(imximage_version);
@@ -381,9 +380,9 @@ static void parse_cfg_cmd(struct imx_header *imxhdr, int32_t cmd, char *token,
set_hdr_func(imxhdr);
break;
case CMD_BOOT_FROM:
- imxhdr->flash_offset = get_table_entry_id(imximage_bootops,
+ g_flash_offset = get_table_entry_id(imximage_bootops,
"imximage boot option", token);
- if (imxhdr->flash_offset == -1) {
+ if (g_flash_offset == -1) {
fprintf(stderr, "Error: %s[%d] -Invalid boot device"
"(%s)\n", name, lineno, token);
exit(EXIT_FAILURE);
@@ -521,12 +520,17 @@ static void imximage_print_header(const void *ptr)
}
}
-static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd,
- struct mkimage_params *params)
+int imximage_vrec_header(struct mkimage_params *params,
+ struct image_type_params *tparams)
{
- struct imx_header *imxhdr = (struct imx_header *)ptr;
+ struct imx_header *imxhdr;
uint32_t dcd_len;
+ imxhdr = calloc(1, MAX_HEADER_SIZE);
+ if (!imxhdr) {
+ fprintf(stderr, "Error: out of memory\n");
+ exit(EXIT_FAILURE);
+ }
/*
* In order to not change the old imx cfg file
* by adding VERSION command into it, here need
@@ -534,14 +538,31 @@ static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd,
*/
imximage_version = IMXIMAGE_V1;
/* Be able to detect if the cfg file has no BOOT_FROM tag */
- imxhdr->flash_offset = FLASH_OFFSET_UNDEFINED;
+ g_flash_offset = FLASH_OFFSET_UNDEFINED;
set_hdr_func(imxhdr);
/* Parse dcd configuration file */
dcd_len = parse_cfg_file(imxhdr, params->imagename);
+ /* Exit if there is no BOOT_FROM field specifying the flash_offset */
+ if (g_flash_offset == FLASH_OFFSET_UNDEFINED) {
+ fprintf(stderr, "Error: No BOOT_FROM tag in %s\n",
+ params->imagename);
+ exit(EXIT_FAILURE);
+ }
/* Set the imx header */
- (*set_imx_hdr)(imxhdr, dcd_len, sbuf, params);
+ imximage_params.header_size = (*set_imx_hdr)(imxhdr, dcd_len,
+ params->ep, g_flash_offset);
+ imximage_params.hdr = imxhdr;
+ return 0;
+}
+
+static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd,
+ struct mkimage_params *params)
+{
+ /* Set the size in header */
+ (*set_imx_size)((struct imx_header *)ptr, sbuf->st_size,
+ g_flash_offset);
}
int imximage_check_params(struct mkimage_params *params)
@@ -571,8 +592,9 @@ int imximage_check_params(struct mkimage_params *params)
*/
static struct image_type_params imximage_params = {
.name = "Freescale i.MX 5x Boot Image support",
- .header_size = sizeof(struct imx_header),
- .hdr = (void *)&imximage_header,
+ .header_size = 0,
+ .hdr = NULL,
+ .vrec_header = imximage_vrec_header,
.check_image_type = imximage_check_image_types,
.verify_header = imximage_verify_header,
.print_header = imximage_print_header,
diff --git a/tools/imximage.h b/tools/imximage.h
index 34f293d..5fe3a8a 100644
--- a/tools/imximage.h
+++ b/tools/imximage.h
@@ -30,6 +30,7 @@
#define DCD_BARKER 0xB17219E9
#define HEADER_OFFSET 0x400
+#define MAX_HEADER_SIZE (16 << 10)
#define CMD_DATA_STR "DATA"
#define FLASH_OFFSET_UNDEFINED 0xFFFFFFFF
@@ -156,7 +157,6 @@ struct imx_header {
imx_header_v1_t hdr_v1;
imx_header_v2_t hdr_v2;
} header;
- uint32_t flash_offset;
};
typedef void (*set_dcd_val_t)(struct imx_header *imxhdr,
@@ -168,9 +168,9 @@ typedef void (*set_dcd_rst_t)(struct imx_header *imxhdr,
uint32_t dcd_len,
char *name, int lineno);
-typedef void (*set_imx_hdr_t)(struct imx_header *imxhdr,
- uint32_t dcd_len,
- struct stat *sbuf,
- struct mkimage_params *params);
+typedef int (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t dcd_len,
+ uint32_t entry_point, uint32_t flash_offset);
+typedef void (*set_imx_size_t)(struct imx_header *imxhdr, uint32_t file_size,
+ uint32_t flash_offset);
#endif /* _IMXIMAGE_H_ */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH 02/11] imximage: check dcd_len as entries added
2012-09-19 0:02 [U-Boot] (no subject) Troy Kisky
2012-09-19 0:02 ` [U-Boot] [PATCH 01/11] imximage: make header variable length Troy Kisky
@ 2012-09-19 0:03 ` Troy Kisky
2012-09-19 0:03 ` [U-Boot] [PATCH 03/11] imximage: enable word writes for version2 header Troy Kisky
` (9 subsequent siblings)
11 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-09-19 0:03 UTC (permalink / raw)
To: u-boot
Before the len was checked after the entire file
was processed, so it could have already overflowed.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
tools/imximage.c | 26 +++++++++++---------------
1 file changed, 11 insertions(+), 15 deletions(-)
diff --git a/tools/imximage.c b/tools/imximage.c
index 25d3b74..0bfbec3 100644
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -71,6 +71,7 @@ static set_dcd_val_t set_dcd_val;
static set_dcd_rst_t set_dcd_rst;
static set_imx_hdr_t set_imx_hdr;
static set_imx_size_t set_imx_size;
+static uint32_t max_dcd_entries;
static uint32_t g_flash_offset;
static struct image_type_params imximage_params;
@@ -173,13 +174,6 @@ static void set_dcd_rst_v1(struct imx_header *imxhdr, uint32_t dcd_len,
{
dcd_v1_t *dcd_v1 = &imxhdr->header.hdr_v1.dcd_table;
- if (dcd_len > MAX_HW_CFG_SIZE_V1) {
- fprintf(stderr, "Error: %s[%d] -"
- "DCD table exceeds maximum size(%d)\n",
- name, lineno, MAX_HW_CFG_SIZE_V1);
- exit(EXIT_FAILURE);
- }
-
dcd_v1->preamble.barker = DCD_BARKER;
dcd_v1->preamble.length = dcd_len * sizeof(dcd_type_addr_data_t);
}
@@ -193,13 +187,6 @@ static void set_dcd_rst_v2(struct imx_header *imxhdr, uint32_t dcd_len,
{
dcd_v2_t *dcd_v2 = &imxhdr->header.hdr_v2.dcd_table;
- if (dcd_len > MAX_HW_CFG_SIZE_V2) {
- fprintf(stderr, "Error: %s[%d] -"
- "DCD table exceeds maximum size(%d)\n",
- name, lineno, MAX_HW_CFG_SIZE_V2);
- exit(EXIT_FAILURE);
- }
-
dcd_v2->header.tag = DCD_HEADER_TAG;
dcd_v2->header.length = cpu_to_be16(
dcd_len * sizeof(dcd_addr_data_t) + 8);
@@ -293,12 +280,14 @@ static void set_hdr_func(struct imx_header *imxhdr)
set_dcd_rst = set_dcd_rst_v1;
set_imx_hdr = set_imx_hdr_v1;
set_imx_size = set_imx_size_v1;
+ max_dcd_entries = MAX_HW_CFG_SIZE_V1;
break;
case IMXIMAGE_V2:
set_dcd_val = set_dcd_val_v2;
set_dcd_rst = set_dcd_rst_v2;
set_imx_hdr = set_imx_hdr_v2;
set_imx_size = set_imx_size_v2;
+ max_dcd_entries = MAX_HW_CFG_SIZE_V2;
break;
default:
err_imximage_version(imximage_version);
@@ -425,8 +414,15 @@ static void parse_cfg_fld(struct imx_header *imxhdr, int32_t *cmd,
value = get_cfg_value(token, name, lineno);
(*set_dcd_val)(imxhdr, name, lineno, fld, value, *dcd_len);
- if (fld == CFG_REG_VALUE)
+ if (fld == CFG_REG_VALUE) {
(*dcd_len)++;
+ if (*dcd_len > max_dcd_entries) {
+ fprintf(stderr, "Error: %s[%d] -"
+ "DCD table exceeds maximum size(%d)\n",
+ name, lineno, max_dcd_entries);
+ exit(EXIT_FAILURE);
+ }
+ }
break;
default:
break;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH 03/11] imximage: enable word writes for version2 header
2012-09-19 0:02 [U-Boot] (no subject) Troy Kisky
2012-09-19 0:02 ` [U-Boot] [PATCH 01/11] imximage: make header variable length Troy Kisky
2012-09-19 0:03 ` [U-Boot] [PATCH 02/11] imximage: check dcd_len as entries added Troy Kisky
@ 2012-09-19 0:03 ` Troy Kisky
2012-09-19 0:03 ` [U-Boot] [PATCH 04/11] imximage: cleanup parsing Troy Kisky
` (8 subsequent siblings)
11 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-09-19 0:03 UTC (permalink / raw)
To: u-boot
Before, only 1 write_dcd_command table was built.
Now, a new table is built when the size changes.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
tools/imximage.c | 153 ++++++++++++++++++++++++++----------------------------
tools/imximage.h | 15 ++----
2 files changed, 77 insertions(+), 91 deletions(-)
diff --git a/tools/imximage.c b/tools/imximage.c
index 0bfbec3..21c49e6 100644
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -68,10 +68,9 @@ static table_entry_t imximage_versions[] = {
static uint32_t imximage_version;
static set_dcd_val_t set_dcd_val;
-static set_dcd_rst_t set_dcd_rst;
static set_imx_hdr_t set_imx_hdr;
static set_imx_size_t set_imx_size;
-static uint32_t max_dcd_entries;
+static uint32_t *p_max_dcd;
static uint32_t g_flash_offset;
static struct image_type_params imximage_params;
@@ -119,8 +118,10 @@ static void err_imximage_version(int version)
exit(EXIT_FAILURE);
}
+static uint32_t *p_entry;
+
static void set_dcd_val_v1(struct imx_header *imxhdr, char *name, int lineno,
- int fld, uint32_t value, uint32_t off)
+ int fld, uint32_t value)
{
dcd_v1_t *dcd_v1 = &imxhdr->header.hdr_v1.dcd_table;
@@ -133,13 +134,15 @@ static void set_dcd_val_v1(struct imx_header *imxhdr, char *name, int lineno,
name, lineno, value);
exit(EXIT_FAILURE);
}
- dcd_v1->addr_data[off].type = value;
+ *p_entry++ = value;
break;
case CFG_REG_ADDRESS:
- dcd_v1->addr_data[off].addr = value;
+ *p_entry++ = value;
break;
case CFG_REG_VALUE:
- dcd_v1->addr_data[off].value = value;
+ *p_entry++ = value;
+ dcd_v1->preamble.length = (char *)p_entry
+ - (char *)&dcd_v1->addr_data[0].type;
break;
default:
break;
@@ -147,17 +150,45 @@ static void set_dcd_val_v1(struct imx_header *imxhdr, char *name, int lineno,
}
}
+static write_dcd_command_t *p_dcd;
+
static void set_dcd_val_v2(struct imx_header *imxhdr, char *name, int lineno,
- int fld, uint32_t value, uint32_t off)
+ int fld, uint32_t value)
{
+ uint32_t len;
dcd_v2_t *dcd_v2 = &imxhdr->header.hdr_v2.dcd_table;
switch (fld) {
+ case CFG_REG_SIZE:
+ /* Byte, halfword, word */
+ if ((value != 1) && (value != 2) && (value != 4)) {
+ fprintf(stderr, "Error: %s[%d] - "
+ "Invalid register size " "(%d)\n",
+ name, lineno, value);
+ exit(EXIT_FAILURE);
+ }
+ if (p_dcd && (p_dcd->param == value))
+ break;
+ if (!p_dcd) {
+ dcd_v2->header.tag = DCD_HEADER_TAG;
+ dcd_v2->header.version = DCD_VERSION;
+ p_dcd = &dcd_v2->write_dcd_command;
+ } else {
+ p_dcd = (write_dcd_command_t *)p_entry;
+ }
+ p_dcd->param = value;
+ p_dcd->tag = DCD_COMMAND_TAG;
+ p_entry = (uint32_t *)(p_dcd + 1);
+ break;
case CFG_REG_ADDRESS:
- dcd_v2->addr_data[off].addr = cpu_to_be32(value);
+ *p_entry++ = cpu_to_be32(value);
break;
case CFG_REG_VALUE:
- dcd_v2->addr_data[off].value = cpu_to_be32(value);
+ *p_entry++ = cpu_to_be32(value);
+ len = (char *)p_entry - (char *)&dcd_v2->header;
+ dcd_v2->header.length = cpu_to_be16(len);
+ len = (char *)p_entry - (char *)p_dcd;
+ p_dcd->length = cpu_to_be16(len);
break;
default:
break;
@@ -165,47 +196,13 @@ static void set_dcd_val_v2(struct imx_header *imxhdr, char *name, int lineno,
}
}
-/*
- * Complete setting up the rest field of DCD of V1
- * such as barker code and DCD data length.
- */
-static void set_dcd_rst_v1(struct imx_header *imxhdr, uint32_t dcd_len,
- char *name, int lineno)
-{
- dcd_v1_t *dcd_v1 = &imxhdr->header.hdr_v1.dcd_table;
-
- dcd_v1->preamble.barker = DCD_BARKER;
- dcd_v1->preamble.length = dcd_len * sizeof(dcd_type_addr_data_t);
-}
-
-/*
- * Complete setting up the reset field of DCD of V2
- * such as DCD tag, version, length, etc.
- */
-static void set_dcd_rst_v2(struct imx_header *imxhdr, uint32_t dcd_len,
- char *name, int lineno)
-{
- dcd_v2_t *dcd_v2 = &imxhdr->header.hdr_v2.dcd_table;
-
- dcd_v2->header.tag = DCD_HEADER_TAG;
- dcd_v2->header.length = cpu_to_be16(
- dcd_len * sizeof(dcd_addr_data_t) + 8);
- dcd_v2->header.version = DCD_VERSION;
- dcd_v2->write_dcd_command.tag = DCD_COMMAND_TAG;
- dcd_v2->write_dcd_command.length = cpu_to_be16(
- dcd_len * sizeof(dcd_addr_data_t) + 4);
- dcd_v2->write_dcd_command.param = DCD_COMMAND_PARAM;
-}
-
-static int set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,
+static int set_imx_hdr_v1(struct imx_header *imxhdr,
uint32_t entry_point, uint32_t flash_offset)
{
imx_header_v1_t *hdr_v1 = &imxhdr->header.hdr_v1;
flash_header_v1_t *fhdr_v1 = &hdr_v1->fhdr;
- dcd_v1_t *dcd_v1 = &hdr_v1->dcd_table;
uint32_t hdr_base;
- uint32_t header_length = (((char *)&dcd_v1->addr_data[dcd_len].addr)
- - ((char *)imxhdr));
+ uint32_t header_length = ((char *)p_entry) + 4 - ((char *)imxhdr);
/* Set magic number */
fhdr_v1->app_code_barker = APP_CODE_BARKER;
@@ -234,15 +231,13 @@ static void set_imx_size_v1(struct imx_header *imxhdr, uint32_t file_size,
p[-1] = file_size + flash_offset;
}
-static int set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t dcd_len,
+static int set_imx_hdr_v2(struct imx_header *imxhdr,
uint32_t entry_point, uint32_t flash_offset)
{
imx_header_v2_t *hdr_v2 = &imxhdr->header.hdr_v2;
flash_header_v2_t *fhdr_v2 = &hdr_v2->fhdr;
uint32_t hdr_base;
- uint32_t header_length = (dcd_len) ?
- (char *)&hdr_v2->dcd_table.addr_data[dcd_len] - ((char*)imxhdr)
- : offsetof(imx_header_v2_t, dcd_table);
+ uint32_t header_length = ((char *)p_entry) - ((char *)imxhdr);
/* Set magic number */
fhdr_v2->header.tag = IVT_HEADER_TAG; /* 0xD1 */
@@ -253,7 +248,7 @@ static int set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t dcd_len,
fhdr_v2->reserved1 = fhdr_v2->reserved2 = 0;
fhdr_v2->self = hdr_base = entry_point - header_length;
- fhdr_v2->dcd_ptr = (dcd_len) ? hdr_base
+ fhdr_v2->dcd_ptr = (p_dcd) ? hdr_base
+ offsetof(imx_header_v2_t, dcd_table) : 0;
fhdr_v2->boot_data_ptr = hdr_base
+ offsetof(imx_header_v2_t, boot_data);
@@ -277,17 +272,19 @@ static void set_hdr_func(struct imx_header *imxhdr)
switch (imximage_version) {
case IMXIMAGE_V1:
set_dcd_val = set_dcd_val_v1;
- set_dcd_rst = set_dcd_rst_v1;
set_imx_hdr = set_imx_hdr_v1;
set_imx_size = set_imx_size_v1;
- max_dcd_entries = MAX_HW_CFG_SIZE_V1;
+ p_entry = &imxhdr->header.hdr_v1.dcd_table.addr_data[0].type;
+ p_max_dcd = &imxhdr->header.hdr_v1.dcd_table
+ .addr_data[MAX_HW_CFG_SIZE_V1].type;
+ imxhdr->header.hdr_v1.dcd_table.preamble.barker = DCD_BARKER;
break;
case IMXIMAGE_V2:
set_dcd_val = set_dcd_val_v2;
- set_dcd_rst = set_dcd_rst_v2;
set_imx_hdr = set_imx_hdr_v2;
set_imx_size = set_imx_size_v2;
- max_dcd_entries = MAX_HW_CFG_SIZE_V2;
+ p_entry = (uint32_t *)&imxhdr->header.hdr_v2.dcd_table;
+ p_max_dcd = (uint32_t *)((char *)imxhdr + MAX_HEADER_SIZE);
break;
default:
err_imximage_version(imximage_version);
@@ -351,7 +348,7 @@ static void print_hdr_v2(struct imx_header *imx_hdr)
}
static void parse_cfg_cmd(struct imx_header *imxhdr, int32_t cmd, char *token,
- char *name, int lineno, int fld, int dcd_len)
+ char *name, int lineno, int fld)
{
int value;
static int cmd_ver_first = ~0;
@@ -381,7 +378,7 @@ static void parse_cfg_cmd(struct imx_header *imxhdr, int32_t cmd, char *token,
break;
case CMD_DATA:
value = get_cfg_value(token, name, lineno);
- (*set_dcd_val)(imxhdr, name, lineno, fld, value, dcd_len);
+ (*set_dcd_val)(imxhdr, name, lineno, fld, value);
if (unlikely(cmd_ver_first != 1))
cmd_ver_first = 0;
break;
@@ -389,7 +386,7 @@ static void parse_cfg_cmd(struct imx_header *imxhdr, int32_t cmd, char *token,
}
static void parse_cfg_fld(struct imx_header *imxhdr, int32_t *cmd,
- char *token, char *name, int lineno, int fld, int *dcd_len)
+ char *token, char *name, int lineno, int fld)
{
int value;
@@ -404,7 +401,7 @@ static void parse_cfg_fld(struct imx_header *imxhdr, int32_t *cmd,
}
break;
case CFG_REG_SIZE:
- parse_cfg_cmd(imxhdr, *cmd, token, name, lineno, fld, *dcd_len);
+ parse_cfg_cmd(imxhdr, *cmd, token, name, lineno, fld);
break;
case CFG_REG_ADDRESS:
case CFG_REG_VALUE:
@@ -412,23 +409,20 @@ static void parse_cfg_fld(struct imx_header *imxhdr, int32_t *cmd,
return;
value = get_cfg_value(token, name, lineno);
- (*set_dcd_val)(imxhdr, name, lineno, fld, value, *dcd_len);
-
- if (fld == CFG_REG_VALUE) {
- (*dcd_len)++;
- if (*dcd_len > max_dcd_entries) {
- fprintf(stderr, "Error: %s[%d] -"
- "DCD table exceeds maximum size(%d)\n",
- name, lineno, max_dcd_entries);
- exit(EXIT_FAILURE);
- }
+ (*set_dcd_val)(imxhdr, name, lineno, fld, value);
+ if (p_entry > p_max_dcd) {
+ uint32_t size = (char *)p_max_dcd - (char *)imxhdr;
+ fprintf(stderr, "Error: %s[%d] -"
+ "header exceeds maximum size(%d)\n",
+ name, lineno, size);
+ exit(EXIT_FAILURE);
}
break;
default:
break;
}
}
-static uint32_t parse_cfg_file(struct imx_header *imxhdr, char *name)
+static void parse_cfg_file(struct imx_header *imxhdr, char *name)
{
FILE *fd = NULL;
char *line = NULL;
@@ -436,7 +430,6 @@ static uint32_t parse_cfg_file(struct imx_header *imxhdr, char *name)
int lineno = 0;
int fld;
size_t len;
- int dcd_len = 0;
int32_t cmd;
fd = fopen(name, "r");
@@ -467,15 +460,12 @@ static uint32_t parse_cfg_file(struct imx_header *imxhdr, char *name)
break;
parse_cfg_fld(imxhdr, &cmd, token, name,
- lineno, fld, &dcd_len);
+ lineno, fld);
}
}
-
- (*set_dcd_rst)(imxhdr, dcd_len, name, lineno);
fclose(fd);
-
- return dcd_len;
+ return;
}
@@ -520,9 +510,12 @@ int imximage_vrec_header(struct mkimage_params *params,
struct image_type_params *tparams)
{
struct imx_header *imxhdr;
- uint32_t dcd_len;
- imxhdr = calloc(1, MAX_HEADER_SIZE);
+ /*
+ * A little extra space to avoid access violation on dcd table overflow.
+ * Overflow is checked after entry is added.
+ */
+ imxhdr = calloc(1, MAX_HEADER_SIZE + 32);
if (!imxhdr) {
fprintf(stderr, "Error: out of memory\n");
exit(EXIT_FAILURE);
@@ -538,7 +531,7 @@ int imximage_vrec_header(struct mkimage_params *params,
set_hdr_func(imxhdr);
/* Parse dcd configuration file */
- dcd_len = parse_cfg_file(imxhdr, params->imagename);
+ parse_cfg_file(imxhdr, params->imagename);
/* Exit if there is no BOOT_FROM field specifying the flash_offset */
if (g_flash_offset == FLASH_OFFSET_UNDEFINED) {
@@ -547,8 +540,8 @@ int imximage_vrec_header(struct mkimage_params *params,
exit(EXIT_FAILURE);
}
/* Set the imx header */
- imximage_params.header_size = (*set_imx_hdr)(imxhdr, dcd_len,
- params->ep, g_flash_offset);
+ imximage_params.header_size = (*set_imx_hdr)(imxhdr, params->ep,
+ g_flash_offset);
imximage_params.hdr = imxhdr;
return 0;
}
diff --git a/tools/imximage.h b/tools/imximage.h
index 5fe3a8a..0319c02 100644
--- a/tools/imximage.h
+++ b/tools/imximage.h
@@ -47,7 +47,6 @@
#define DCD_HEADER_TAG 0xD2
#define DCD_COMMAND_TAG 0xCC
#define DCD_VERSION 0x40
-#define DCD_COMMAND_PARAM 0x4
enum imximage_cmd {
CMD_INVALID,
@@ -159,17 +158,11 @@ struct imx_header {
} header;
};
-typedef void (*set_dcd_val_t)(struct imx_header *imxhdr,
- char *name, int lineno,
- int fld, uint32_t value,
- uint32_t off);
+typedef void (*set_dcd_val_t)(struct imx_header *imxhdr, char *name,
+ int lineno, int fld, uint32_t value);
-typedef void (*set_dcd_rst_t)(struct imx_header *imxhdr,
- uint32_t dcd_len,
- char *name, int lineno);
-
-typedef int (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t dcd_len,
- uint32_t entry_point, uint32_t flash_offset);
+typedef int (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t entry_point,
+ uint32_t flash_offset);
typedef void (*set_imx_size_t)(struct imx_header *imxhdr, uint32_t file_size,
uint32_t flash_offset);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH 04/11] imximage: cleanup parsing
2012-09-19 0:02 [U-Boot] (no subject) Troy Kisky
` (2 preceding siblings ...)
2012-09-19 0:03 ` [U-Boot] [PATCH 03/11] imximage: enable word writes for version2 header Troy Kisky
@ 2012-09-19 0:03 ` Troy Kisky
2012-09-19 0:03 ` [U-Boot] [PATCH 05/11] imximage: add expression evaluation Troy Kisky
` (7 subsequent siblings)
11 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-09-19 0:03 UTC (permalink / raw)
To: u-boot
Move to pulling tokens instead of pushing them.
Remove need for switch statements to process commands.
Add error messages such as "command not finished",
"extra data at end of line", and "invalid token"
Add ';' as command separator.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
tools/imximage.c | 380 ++++++++++++++++++++++++++++++------------------------
tools/imximage.h | 25 ++--
2 files changed, 226 insertions(+), 179 deletions(-)
diff --git a/tools/imximage.c b/tools/imximage.c
index 21c49e6..1e120354 100644
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -75,21 +75,6 @@ static uint32_t g_flash_offset;
static struct image_type_params imximage_params;
-static uint32_t get_cfg_value(char *token, char *name, int linenr)
-{
- char *endptr;
- uint32_t value;
-
- errno = 0;
- value = strtoul(token, &endptr, 16);
- if (errno || (token == endptr)) {
- fprintf(stderr, "Error: %s[%d] - Invalid hex data(%s)\n",
- name, linenr, token);
- exit(EXIT_FAILURE);
- }
- return value;
-}
-
static uint32_t detect_imximage_version(struct imx_header *imx_hdr)
{
imx_header_v1_t *hdr_v1 = &imx_hdr->header.hdr_v1;
@@ -120,55 +105,38 @@ static void err_imximage_version(int version)
static uint32_t *p_entry;
-static void set_dcd_val_v1(struct imx_header *imxhdr, char *name, int lineno,
- int fld, uint32_t value)
+static int set_dcd_val_v1(struct imx_header *imxhdr, uint32_t *data)
{
dcd_v1_t *dcd_v1 = &imxhdr->header.hdr_v1.dcd_table;
+ uint32_t val = *data++;
- switch (fld) {
- case CFG_REG_SIZE:
- /* Byte, halfword, word */
- if ((value != 1) && (value != 2) && (value != 4)) {
- fprintf(stderr, "Error: %s[%d] - "
- "Invalid register size " "(%d)\n",
- name, lineno, value);
- exit(EXIT_FAILURE);
- }
- *p_entry++ = value;
- break;
- case CFG_REG_ADDRESS:
- *p_entry++ = value;
- break;
- case CFG_REG_VALUE:
- *p_entry++ = value;
- dcd_v1->preamble.length = (char *)p_entry
- - (char *)&dcd_v1->addr_data[0].type;
- break;
- default:
- break;
-
+ /* Byte, halfword, word */
+ if ((val != 1) && (val != 2) && (val != 4)) {
+ fprintf(stderr, "Error: Invalid register size (%d)\n", val);
+ return -1;
}
+ *p_entry++ = val;
+ *p_entry++ = *data++;
+ *p_entry++ = *data++;
+ dcd_v1->preamble.length = (char *)p_entry - (char *)&dcd_v1->
+ addr_data[0].type;
+ return 0;
}
static write_dcd_command_t *p_dcd;
-static void set_dcd_val_v2(struct imx_header *imxhdr, char *name, int lineno,
- int fld, uint32_t value)
+static int set_dcd_val_v2(struct imx_header *imxhdr, uint32_t *data)
{
uint32_t len;
dcd_v2_t *dcd_v2 = &imxhdr->header.hdr_v2.dcd_table;
+ uint32_t val = *data++;
- switch (fld) {
- case CFG_REG_SIZE:
- /* Byte, halfword, word */
- if ((value != 1) && (value != 2) && (value != 4)) {
- fprintf(stderr, "Error: %s[%d] - "
- "Invalid register size " "(%d)\n",
- name, lineno, value);
- exit(EXIT_FAILURE);
- }
- if (p_dcd && (p_dcd->param == value))
- break;
+ /* Byte, halfword, word */
+ if ((val != 1) && (val != 2) && (val != 4)) {
+ fprintf(stderr, "Error: Invalid register size (%d)\n", val);
+ return -1;
+ }
+ if (!(p_dcd && (p_dcd->param == val))) {
if (!p_dcd) {
dcd_v2->header.tag = DCD_HEADER_TAG;
dcd_v2->header.version = DCD_VERSION;
@@ -176,24 +144,19 @@ static void set_dcd_val_v2(struct imx_header *imxhdr, char *name, int lineno,
} else {
p_dcd = (write_dcd_command_t *)p_entry;
}
- p_dcd->param = value;
+ p_dcd->param = val;
p_dcd->tag = DCD_COMMAND_TAG;
p_entry = (uint32_t *)(p_dcd + 1);
- break;
- case CFG_REG_ADDRESS:
- *p_entry++ = cpu_to_be32(value);
- break;
- case CFG_REG_VALUE:
- *p_entry++ = cpu_to_be32(value);
- len = (char *)p_entry - (char *)&dcd_v2->header;
- dcd_v2->header.length = cpu_to_be16(len);
- len = (char *)p_entry - (char *)p_dcd;
- p_dcd->length = cpu_to_be16(len);
- break;
- default:
- break;
-
}
+ val = *data++;
+ *p_entry++ = cpu_to_be32(val);
+ val = *data++;
+ *p_entry++ = cpu_to_be32(val);
+ len = (char *)p_entry - (char *)&dcd_v2->header;
+ dcd_v2->header.length = cpu_to_be16(len);
+ len = (char *)p_entry - (char *)p_dcd;
+ p_dcd->length = cpu_to_be16(len);
+ return 0;
}
static int set_imx_hdr_v1(struct imx_header *imxhdr,
@@ -347,93 +310,186 @@ static void print_hdr_v2(struct imx_header *imx_hdr)
printf("Entry Point: %08x\n", (uint32_t)fhdr_v2->entry);
}
-static void parse_cfg_cmd(struct imx_header *imxhdr, int32_t cmd, char *token,
- char *name, int lineno, int fld)
+static int cmd_cnt;
+
+int skip_separators(struct data_src *ds)
{
- int value;
- static int cmd_ver_first = ~0;
-
- switch (cmd) {
- case CMD_IMAGE_VERSION:
- imximage_version = get_cfg_value(token, name, lineno);
- if (cmd_ver_first == 0) {
- fprintf(stderr, "Error: %s[%d] - IMAGE_VERSION "
- "command need be the first before other "
- "valid command in the file\n", name, lineno);
- exit(EXIT_FAILURE);
+ int line_no = ds->lineno;
+ char *p = ds->p;
+
+ for (;;) {
+ char c;
+ if (!p) {
+ if (getline(&ds->line, &ds->len, ds->fd) <= 0)
+ return -1;
+ ds->lineno++;
+ p = ds->line;
+ if (ds->cmd_started) {
+ fprintf(stderr, "warning: continuing command on"
+ " next line, line %s[%d](%s)\n",
+ ds->filename, ds->lineno, p);
+ }
}
- cmd_ver_first = 1;
- set_hdr_func(imxhdr);
- break;
- case CMD_BOOT_FROM:
- g_flash_offset = get_table_entry_id(imximage_bootops,
- "imximage boot option", token);
- if (g_flash_offset == -1) {
- fprintf(stderr, "Error: %s[%d] -Invalid boot device"
- "(%s)\n", name, lineno, token);
- exit(EXIT_FAILURE);
+ c = *p;
+ if ((c == ' ') || (c == '\t')) {
+ p++;
+ continue;
}
- if (unlikely(cmd_ver_first != 1))
- cmd_ver_first = 0;
- break;
- case CMD_DATA:
- value = get_cfg_value(token, name, lineno);
- (*set_dcd_val)(imxhdr, name, lineno, fld, value);
- if (unlikely(cmd_ver_first != 1))
- cmd_ver_first = 0;
- break;
+ /* Drop all text starting with '#' as comments */
+ if ((c == '#') || (c == '\r') || (c == '\n')
+ || !c) {
+ p = NULL;
+ continue;
+ }
+ if (c == ';') {
+ if (ds->cmd_started) {
+ fprintf(stderr, "Error: command not "
+ "finished:%s[%d](%s)\n",
+ ds->filename, ds->lineno, p);
+ exit(EXIT_FAILURE);
+ }
+ p++;
+ continue;
+ }
+ if (!ds->cmd_started && line_no == ds->lineno) {
+ fprintf(stderr, "warning: extra data at end "
+ "of line %s[%d](%s)\n",
+ ds->filename, ds->lineno, p);
+ p = NULL;
+ continue;
+ }
+ ds->p = p;
+ return 0;
}
}
-static void parse_cfg_fld(struct imx_header *imxhdr, int32_t *cmd,
- char *token, char *name, int lineno, int fld)
+char *grab_token(char *dest, int size, char *src)
{
- int value;
-
- switch (fld) {
- case CFG_COMMAND:
- *cmd = get_table_entry_id(imximage_cmds,
- "imximage commands", token);
- if (*cmd < 0) {
- fprintf(stderr, "Error: %s[%d] - Invalid command"
- "(%s)\n", name, lineno, token);
- exit(EXIT_FAILURE);
- }
- break;
- case CFG_REG_SIZE:
- parse_cfg_cmd(imxhdr, *cmd, token, name, lineno, fld);
- break;
- case CFG_REG_ADDRESS:
- case CFG_REG_VALUE:
- if (*cmd != CMD_DATA)
- return;
-
- value = get_cfg_value(token, name, lineno);
- (*set_dcd_val)(imxhdr, name, lineno, fld, value);
- if (p_entry > p_max_dcd) {
- uint32_t size = (char *)p_max_dcd - (char *)imxhdr;
- fprintf(stderr, "Error: %s[%d] -"
- "header exceeds maximum size(%d)\n",
- name, lineno, size);
- exit(EXIT_FAILURE);
- }
- break;
- default:
- break;
+ while (size) {
+ char c = *src;
+ if ((c == ' ') || (c == '\t') || (c == '\r') || (c == '\n')
+ || (c == '#') || !c)
+ break;
+ *dest++ = c;
+ size--;
+ src++;
+ }
+ if (!size)
+ return NULL;
+ *dest = 0;
+ return src;
+}
+
+static uint32_t get_cfg_value(struct data_src *ds, uint32_t *pval)
+{
+ char *endptr;
+ uint32_t value;
+
+ if (skip_separators(ds))
+ return -1;
+ errno = 0;
+ value = strtoul(ds->p, &endptr, 16);
+ if (errno || (ds->p == endptr))
+ return -1;
+ *pval = value;
+ ds->p = endptr;
+ return 0;
+}
+
+static int parse_cmd_data(struct data_src *ds)
+{
+ uint32_t data[3];
+ int ret = get_cfg_value(ds, &data[0]);
+
+ if (ret)
+ return ret;
+ ret = get_cfg_value(ds, &data[1]);
+ if (ret)
+ return ret;
+ ret = get_cfg_value(ds, &data[2]);
+ if (ret)
+ return ret;
+ ret = (*set_dcd_val)(ds->imxhdr, data);
+ if (ret)
+ return ret;
+ if (p_entry > p_max_dcd) {
+ uint32_t size = (char *)p_max_dcd - (char *)ds->imxhdr;
+ fprintf(stderr, "Error: header exceeds maximum size(%d)\n",
+ size);
+ return -1;
+ }
+ return 0;
+}
+
+static int parse_image_version(struct data_src *ds)
+{
+ int ret;
+
+ ret = get_cfg_value(ds, &imximage_version);
+ if (ret)
+ return ret;
+ if (cmd_cnt) {
+ fprintf(stderr, "Error: IMAGE_VERSION command needs be "
+ "before other valid commands in the file\n");
+ return -1;
+ }
+ set_hdr_func(ds->imxhdr);
+ return 0;
+}
+
+int get_from_array(struct data_src *ds,
+ const table_entry_t *table, const char *table_name)
+{
+ int val;
+ char token[16];
+ char *p;
+
+ if (skip_separators(ds))
+ return -1;
+ p = grab_token(token, sizeof(token), ds->p);
+ if (!p)
+ return -1;
+ val = get_table_entry_id(table, table_name, token);
+ if (val != -1)
+ ds->p = p;
+ return val;
+}
+
+static int parse_boot_from(struct data_src *ds)
+{
+ g_flash_offset = get_from_array(ds, imximage_bootops,
+ "imximage boot option");
+ if (g_flash_offset == -1) {
+ fprintf(stderr, "Error: Invalid boot device\n");
+ return -1;
}
+ return 0;
}
+
+parse_fld_t cmd_table[] = {
+ parse_image_version, parse_boot_from, parse_cmd_data
+};
+
+static int parse_command(struct data_src *ds)
+{
+ int cmd = get_from_array(ds, imximage_cmds, "imximage commands");
+ if (cmd < 0)
+ return cmd;
+ return cmd_table[cmd](ds);
+}
+
static void parse_cfg_file(struct imx_header *imxhdr, char *name)
{
- FILE *fd = NULL;
- char *line = NULL;
- char *token, *saveptr1, *saveptr2;
- int lineno = 0;
- int fld;
- size_t len;
- int32_t cmd;
-
- fd = fopen(name, "r");
- if (fd == 0) {
+ struct data_src ds;
+
+ ds.line = NULL;
+ ds.len = 0;
+ ds.lineno = 0;
+ ds.filename = name;
+ ds.fd = fopen(name, "r");
+ ds.imxhdr = imxhdr;
+ ds.p = NULL;
+ if (ds.fd == 0) {
fprintf(stderr, "Error: %s - Can't open DCD file\n", name);
exit(EXIT_FAILURE);
}
@@ -441,34 +497,22 @@ static void parse_cfg_file(struct imx_header *imxhdr, char *name)
/* Very simple parsing, line starting with # are comments
* and are dropped
*/
- while ((getline(&line, &len, fd)) > 0) {
- lineno++;
-
- token = strtok_r(line, "\r\n", &saveptr1);
- if (token == NULL)
- continue;
-
- /* Check inside the single line */
- for (fld = CFG_COMMAND, cmd = CMD_INVALID,
- line = token; ; line = NULL, fld++) {
- token = strtok_r(line, " \t", &saveptr2);
- if (token == NULL)
- break;
-
- /* Drop all text starting with '#' as comments */
- if (token[0] == '#')
- break;
-
- parse_cfg_fld(imxhdr, &cmd, token, name,
- lineno, fld);
+ for (;;) {
+ ds.cmd_started = 0;
+ if (skip_separators(&ds))
+ break;
+ ds.cmd_started = 1;
+ if (parse_command(&ds)) {
+ fprintf(stderr, "Error: invalid token "
+ "%s[%d](%s)\n", name, ds.lineno, ds.p);
+ exit(EXIT_FAILURE);
}
-
+ cmd_cnt++;
}
- fclose(fd);
+ fclose(ds.fd);
return;
}
-
static int imximage_check_image_types(uint8_t type)
{
if (type == IH_TYPE_IMXIMAGE)
@@ -557,12 +601,12 @@ static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd,
int imximage_check_params(struct mkimage_params *params)
{
if (!params)
- return CFG_INVALID;
+ return -1;
if (!strlen(params->imagename)) {
fprintf(stderr, "Error: %s - Configuration file not specified, "
"it is needed for imximage generation\n",
params->cmdname);
- return CFG_INVALID;
+ return -1;
}
/*
* Check parameters:
diff --git a/tools/imximage.h b/tools/imximage.h
index 0319c02..efd249b 100644
--- a/tools/imximage.h
+++ b/tools/imximage.h
@@ -49,20 +49,11 @@
#define DCD_VERSION 0x40
enum imximage_cmd {
- CMD_INVALID,
CMD_IMAGE_VERSION,
CMD_BOOT_FROM,
CMD_DATA
};
-enum imximage_fld_types {
- CFG_INVALID = -1,
- CFG_COMMAND,
- CFG_REG_SIZE,
- CFG_REG_ADDRESS,
- CFG_REG_VALUE
-};
-
enum imximage_version {
IMXIMAGE_VER_INVALID = -1,
IMXIMAGE_V1 = 1,
@@ -158,8 +149,20 @@ struct imx_header {
} header;
};
-typedef void (*set_dcd_val_t)(struct imx_header *imxhdr, char *name,
- int lineno, int fld, uint32_t value);
+struct data_src {
+ char *line;
+ size_t len;
+ FILE *fd;
+ int lineno;
+ char cmd_started;
+ char *filename;
+ struct imx_header *imxhdr;
+ char *p;
+};
+
+typedef int (*parse_fld_t)(struct data_src *ds);
+
+typedef int (*set_dcd_val_t)(struct imx_header *imxhdr, uint32_t *data);
typedef int (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t entry_point,
uint32_t flash_offset);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH 05/11] imximage: add expression evaluation
2012-09-19 0:02 [U-Boot] (no subject) Troy Kisky
` (3 preceding siblings ...)
2012-09-19 0:03 ` [U-Boot] [PATCH 04/11] imximage: cleanup parsing Troy Kisky
@ 2012-09-19 0:03 ` Troy Kisky
2012-09-19 0:03 ` [U-Boot] [PATCH 06/11] imximage: add plugin commands Troy Kisky
` (6 subsequent siblings)
11 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-09-19 0:03 UTC (permalink / raw)
To: u-boot
Basic expressions with order precedence is
now supported.
ie. (----3 + ((1+2*3)/--2 + --5 *(8/4))) is 16.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
tools/imximage.c | 172 ++++++++++++++++++++++++++++++++++++++++++++++++++----
1 file changed, 162 insertions(+), 10 deletions(-)
diff --git a/tools/imximage.c b/tools/imximage.c
index 1e120354..2c5a622 100644
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -380,20 +380,172 @@ char *grab_token(char *dest, int size, char *src)
return src;
}
+char precedence[] = {
+ /* ( + - * / & ^ | ) */
+ 0, 2, 2, 1, 1, 3, 4, 5, 6
+};
+char unary_operations[] = "(+-";
+char binary_operations[] = " +-*/&^|)";
+
+uint32_t do_func(uint32_t val1, uint32_t val2, int op)
+{
+ switch (op) {
+ case 1:
+ return val1 + val2;
+ case 2:
+ return val1 - val2;
+ case 3:
+ return val1 * val2;
+ case 4:
+ return val1 / val2;
+ case 5:
+ return val1 & val2;
+ case 6:
+ return val1 ^ val2;
+ case 7:
+ return val1 | val2;
+ }
+ fprintf(stderr, "Error: in func %s: val1=%d val2=%d op = %d\n",
+ __func__, val1, val2, op);
+ exit(EXIT_FAILURE);
+}
+
+int find_op(char c, char *p)
+{
+ int i;
+ for (i = 0; ; i++) {
+ if (c == p[i])
+ return i;
+ if (!p[i])
+ break;
+ }
+ return -1;
+}
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
static uint32_t get_cfg_value(struct data_src *ds, uint32_t *pval)
{
char *endptr;
- uint32_t value;
+ int op_i = 0;
+ int val_i = 0;
+ unsigned char op[16];
+ uint32_t val[16];
+ int unary = 1;
+ char *p;
- if (skip_separators(ds))
- return -1;
- errno = 0;
- value = strtoul(ds->p, &endptr, 16);
- if (errno || (ds->p == endptr))
- return -1;
- *pval = value;
- ds->p = endptr;
- return 0;
+ p = ds->p;
+ for (;;) {
+ char c;
+ int i, j;
+ char *ops = unary ? unary_operations : binary_operations;
+
+ if (unary) {
+ ds->p = p;
+ if (skip_separators(ds))
+ return -1;
+ p = ds->p;
+ c = *p;
+ } else {
+ for (;;) {
+ c = *p;
+ if ((c != ' ') && (c != '\t'))
+ break;
+ p++;
+ }
+ }
+ i = find_op(c, ops);
+ debug("%d,%c,%d:%s\n", i, c, unary, p);
+ if ((i < 0) && unary) {
+ if (val_i >= ARRAY_SIZE(val))
+ return -1;
+ errno = 0;
+ val[val_i++] = strtoul(p, &endptr, 16);
+ if (errno || (p == endptr)) {
+ ds->p = p;
+ return -1;
+ }
+ p = endptr;
+ unary = 0;
+ debug("val[%d]=%x,%d,%d\n", val_i - 1, val[val_i - 1],
+ op_i, val_i);
+do_unary:
+ while (op_i) {
+ j = op[op_i - 1];
+ if (!(j & 0x80))
+ break;
+ op_i--;
+ val[val_i - 1] = do_func(0,
+ val[val_i - 1], j & 0x7f);
+ debug("un:%d,%x,%d,%d\n", val[val_i - 1], j,
+ op_i, val_i);
+ }
+ continue;
+ }
+ if (i < 0) {
+ c = 0;
+ i = 8;
+ } else {
+ p++;
+ }
+ if (c == '(') {
+ if (op_i >= ARRAY_SIZE(op))
+ return -1;
+ op[op_i++] = i;
+ debug("op[%d]=%x,%d,%d\n", op_i - 1, op[op_i - 1],
+ op_i, val_i);
+ unary = 1;
+ continue;
+ }
+ for (;;) {
+ if (!op_i || unary)
+ break;
+ j = op[op_i - 1];
+ if (j == 0) {
+ if (c == ')') {
+ op_i--;
+ goto do_unary;
+ }
+ break;
+ }
+ if ((j & 0x80)) {
+ op_i--;
+ val[val_i - 1] = do_func(0,
+ val[val_i - 1], j & 0x7f);
+ debug("unary:%d,%x\n", val[val_i - 1], j);
+ continue;
+ }
+ if (precedence[i] < precedence[j])
+ break;
+ if (val_i < 2)
+ return -1;
+ op_i--;
+ val[val_i - 2] = do_func(val[val_i - 2],
+ val[val_i - 1], j);
+ val_i--;
+ debug("binary:%d,%x,%d,%d\n", val[val_i - 1], j,
+ op_i, val_i);
+ }
+ if (c == ')') {
+ fprintf(stderr, "Error: unmatched parenthesis\n");
+ return -1;
+ }
+ if (i == 8) {
+ if ((op_i != 0) || (val_i != 1)) {
+ fprintf(stderr, "Error: syntax %d %d\n",
+ op_i, val_i);
+ return -1;
+ }
+ ds->p = p;
+ *pval = val[0];
+ return 0;
+ }
+ if (op_i >= ARRAY_SIZE(op))
+ return -1;
+ op[op_i++] = i | (unary << 7);
+ debug("op[%d]=%x,%d,%d\n", op_i - 1, op[op_i - 1], op_i, val_i);
+ unary = 1;
+ }
}
static int parse_cmd_data(struct data_src *ds)
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH 06/11] imximage: add plugin commands
2012-09-19 0:02 [U-Boot] (no subject) Troy Kisky
` (4 preceding siblings ...)
2012-09-19 0:03 ` [U-Boot] [PATCH 05/11] imximage: add expression evaluation Troy Kisky
@ 2012-09-19 0:03 ` Troy Kisky
2012-09-19 0:03 ` [U-Boot] [PATCH 07/11] imximage.cfg: run files through C preprocessor Troy Kisky
` (5 subsequent siblings)
11 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-09-19 0:03 UTC (permalink / raw)
To: u-boot
Add commands
plugin address filename
iomux_entry addr, data1 [, data2, [, data3]]
write_entry addr, data1 [, data2, [, data3]]
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
tools/imximage.c | 338 ++++++++++++++++++++++++++++++++++++++++++++----------
tools/imximage.h | 11 +-
2 files changed, 287 insertions(+), 62 deletions(-)
diff --git a/tools/imximage.c b/tools/imximage.c
index 2c5a622..63252be 100644
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -31,7 +31,6 @@
#include "mkimage.h"
#include <image.h>
#include "imximage.h"
-
/*
* Supported commands for configuration file
*/
@@ -39,6 +38,9 @@ static table_entry_t imximage_cmds[] = {
{CMD_BOOT_FROM, "BOOT_FROM", "boot command", },
{CMD_DATA, "DATA", "Reg Write Data", },
{CMD_IMAGE_VERSION, "IMAGE_VERSION", "image version", },
+ {CMD_PLUGIN, "plugin", "plugin addr,file", },
+ {CMD_IOMUX_ENTRY, "iomux_entry", "Write iomux reg", },
+ {CMD_WRITE_ENTRY, "write_entry", "Write register", },
{-1, "", "", },
};
@@ -69,8 +71,8 @@ static uint32_t imximage_version;
static set_dcd_val_t set_dcd_val;
static set_imx_hdr_t set_imx_hdr;
-static set_imx_size_t set_imx_size;
static uint32_t *p_max_dcd;
+static uint32_t *header_size_ptr;
static uint32_t g_flash_offset;
static struct image_type_params imximage_params;
@@ -88,8 +90,7 @@ static uint32_t detect_imximage_version(struct imx_header *imx_hdr)
return IMXIMAGE_V1;
/* Try to detect V2 */
- if ((fhdr_v2->header.tag == IVT_HEADER_TAG) &&
- (hdr_v2->dcd_table.header.tag == DCD_HEADER_TAG))
+ if ((fhdr_v2->header.tag == IVT_HEADER_TAG))
return IMXIMAGE_V2;
return IMXIMAGE_VER_INVALID;
@@ -160,7 +161,7 @@ static int set_dcd_val_v2(struct imx_header *imxhdr, uint32_t *data)
}
static int set_imx_hdr_v1(struct imx_header *imxhdr,
- uint32_t entry_point, uint32_t flash_offset)
+ uint32_t entry_point, uint32_t flash_offset, int plugin)
{
imx_header_v1_t *hdr_v1 = &imxhdr->header.hdr_v1;
flash_header_v1_t *fhdr_v1 = &hdr_v1->fhdr;
@@ -180,22 +181,12 @@ static int set_imx_hdr_v1(struct imx_header *imxhdr,
/* Security feature are not supported */
fhdr_v1->app_code_csf = 0;
fhdr_v1->super_root_key = 0;
+ header_size_ptr = (uint32_t *)(((char *)imxhdr) + header_length - 4);
return header_length;
}
-static void set_imx_size_v1(struct imx_header *imxhdr, uint32_t file_size,
- uint32_t flash_offset)
-{
- uint32_t *p = (uint32_t *)(((char *)imxhdr)
- + imximage_params.header_size);
-
- /* The external flash header must be at the end of the DCD table */
- /* file_size includes header */
- p[-1] = file_size + flash_offset;
-}
-
static int set_imx_hdr_v2(struct imx_header *imxhdr,
- uint32_t entry_point, uint32_t flash_offset)
+ uint32_t entry_point, uint32_t flash_offset, int plugin)
{
imx_header_v2_t *hdr_v2 = &imxhdr->header.hdr_v2;
flash_header_v2_t *fhdr_v2 = &hdr_v2->fhdr;
@@ -216,27 +207,20 @@ static int set_imx_hdr_v2(struct imx_header *imxhdr,
fhdr_v2->boot_data_ptr = hdr_base
+ offsetof(imx_header_v2_t, boot_data);
hdr_v2->boot_data.start = hdr_base - flash_offset;
+ hdr_v2->boot_data.plugin = plugin;
/* Security feature are not supported */
fhdr_v2->csf = 0;
+ header_size_ptr = &hdr_v2->boot_data.size;
return header_length;
}
-static void set_imx_size_v2(struct imx_header *imxhdr, uint32_t file_size,
- uint32_t flash_offset)
-{
- imx_header_v2_t *hdr_v2 = &imxhdr->header.hdr_v2;
- /* file_size includes header */
- hdr_v2->boot_data.size = file_size + flash_offset;
-}
-
static void set_hdr_func(struct imx_header *imxhdr)
{
switch (imximage_version) {
case IMXIMAGE_V1:
set_dcd_val = set_dcd_val_v1;
set_imx_hdr = set_imx_hdr_v1;
- set_imx_size = set_imx_size_v1;
p_entry = &imxhdr->header.hdr_v1.dcd_table.addr_data[0].type;
p_max_dcd = &imxhdr->header.hdr_v1.dcd_table
.addr_data[MAX_HW_CFG_SIZE_V1].type;
@@ -245,7 +229,6 @@ static void set_hdr_func(struct imx_header *imxhdr)
case IMXIMAGE_V2:
set_dcd_val = set_dcd_val_v2;
set_imx_hdr = set_imx_hdr_v2;
- set_imx_size = set_imx_size_v2;
p_entry = (uint32_t *)&imxhdr->header.hdr_v2.dcd_table;
p_max_dcd = (uint32_t *)((char *)imxhdr + MAX_HEADER_SIZE);
break;
@@ -283,31 +266,49 @@ static void print_hdr_v1(struct imx_header *imx_hdr)
printf("Entry Point: %08x\n", (uint32_t)fhdr_v1->app_code_jump_vector);
}
-static void print_hdr_v2(struct imx_header *imx_hdr)
+static void print_header_info2(struct imx_header *imx_hdr)
{
imx_header_v2_t *hdr_v2 = &imx_hdr->header.hdr_v2;
flash_header_v2_t *fhdr_v2 = &hdr_v2->fhdr;
+
+ printf("Data Size: ");
+ genimg_print_size(hdr_v2->boot_data.size);
+ printf("Load Address: %08x\n", (uint32_t)fhdr_v2->boot_data_ptr);
+ printf("Entry Point: %08x\n", (uint32_t)fhdr_v2->entry);
+}
+
+static void print_hdr_v2(struct imx_header *imxhdr)
+{
+ imx_header_v2_t *hdr_v2 = &imxhdr->header.hdr_v2;
dcd_v2_t *dcd_v2 = &hdr_v2->dcd_table;
uint32_t size, version;
- size = be16_to_cpu(dcd_v2->header.length) - 8;
- if (size > (MAX_HW_CFG_SIZE_V2 * sizeof(dcd_addr_data_t))) {
- fprintf(stderr,
- "Error: Image corrupt DCD size %d exceed maximum %d\n",
- (uint32_t)(size / sizeof(dcd_addr_data_t)),
- MAX_HW_CFG_SIZE_V2);
- exit(EXIT_FAILURE);
+ if (hdr_v2->fhdr.dcd_ptr) {
+ size = be16_to_cpu(dcd_v2->header.length) - 8;
+ if (size > (MAX_HW_CFG_SIZE_V2 * sizeof(dcd_addr_data_t))) {
+ fprintf(stderr, "Error: Image corrupt DCD size "
+ "%d exceed maximum %d\n",
+ (uint32_t)(size / sizeof(dcd_addr_data_t)),
+ MAX_HW_CFG_SIZE_V2);
+ exit(EXIT_FAILURE);
+ }
}
-
- version = detect_imximage_version(imx_hdr);
+ version = detect_imximage_version(imxhdr);
printf("Image Type: Freescale IMX Boot Image\n");
printf("Image Ver: %x", version);
printf("%s\n", get_table_entry_name(imximage_versions, NULL, version));
- printf("Data Size: ");
- genimg_print_size(hdr_v2->boot_data.size);
- printf("Load Address: %08x\n", (uint32_t)fhdr_v2->boot_data_ptr);
- printf("Entry Point: %08x\n", (uint32_t)fhdr_v2->entry);
+ print_header_info2(imxhdr);
+ if (hdr_v2->boot_data.plugin) {
+ uint32_t flash_offset =
+ hdr_v2->fhdr.self - hdr_v2->boot_data.start;
+ /* The 1st size includes flash offset and the next header */
+ uint32_t plugin_length = hdr_v2->boot_data.size - flash_offset
+ - offsetof(imx_header_v2_t, dcd_table);
+
+ imxhdr = (struct imx_header *)((char *)imxhdr + plugin_length);
+ print_header_info2(imxhdr);
+ }
}
static int cmd_cnt;
@@ -363,6 +364,24 @@ int skip_separators(struct data_src *ds)
}
}
+int skip_comma(struct data_src *ds)
+{
+ char *p = ds->p;
+
+ for (;;) {
+ char c = *p++;
+ if ((c == '#') || (c == '\r') || (c == '\n') || !c)
+ return 0;
+ if (c == ',') {
+ ds->p = p;
+ skip_separators(ds);
+ return 1;
+ }
+ if ((c != ' ') && (c == '\t'))
+ return 0;
+ }
+}
+
char *grab_token(char *dest, int size, char *src)
{
while (size) {
@@ -551,16 +570,18 @@ do_unary:
static int parse_cmd_data(struct data_src *ds)
{
uint32_t data[3];
- int ret = get_cfg_value(ds, &data[0]);
+ int ret, i;
- if (ret)
- return ret;
- ret = get_cfg_value(ds, &data[1]);
- if (ret)
- return ret;
- ret = get_cfg_value(ds, &data[2]);
- if (ret)
- return ret;
+ if (ds->plugin) {
+ fprintf(stderr, "DATA should be before plug command\n");
+ return -1;
+ }
+ for (i = 0; i < 3; i++) {
+ int ret = get_cfg_value(ds, &data[i]);
+ if (ret)
+ return ret;
+ skip_comma(ds); /* comma is optional */
+ }
ret = (*set_dcd_val)(ds->imxhdr, data);
if (ret)
return ret;
@@ -573,6 +594,103 @@ static int parse_cmd_data(struct data_src *ds)
return 0;
}
+static int get_data(struct data_src *ds, uint32_t *data, int cnt)
+{
+ int i = 0;
+
+ if (!ds->plugin) {
+ fprintf(stderr, "missing plug command\n");
+ return -1;
+ }
+ for (;;) {
+ int ret = get_cfg_value(ds, &data[i++]);
+ if (ret)
+ return ret;
+ if (i >= cnt)
+ break;
+ if (!skip_comma(ds))
+ break;
+ }
+ if (i < 2) {
+ fprintf(stderr, "missing ','\n");
+ return -1;
+ }
+ while (i < 4) {
+ data[i] = data[i - 1];
+ i++;
+ }
+ return 0;
+}
+
+static int store_data(struct data_src *ds, uint32_t *data, int cnt)
+{
+ int i;
+
+ for (i = 0; i < cnt; i++)
+ *p_entry++ = data[i];
+
+ ds->prev[1] = data[1];
+ ds->prev[2] = data[2];
+ ds->prev[3] = data[3];
+ if (p_entry > p_max_dcd) {
+ uint32_t size = (char *)p_max_dcd - (char *)ds->imxhdr;
+ fprintf(stderr, "Error: header exceeds maximum size(%d)\n",
+ size);
+ return -1;
+ }
+ return 0;
+}
+
+static int parse_iomux_entry(struct data_src *ds)
+{
+ uint32_t data[4];
+ int ret, i, j;
+
+ ret = get_data(ds, data, 4);
+ if (ret)
+ return ret;
+ if (data[0] & (3 << 30)) {
+ fprintf(stderr, "bad 1st value\n");
+ return -1;
+ }
+ if ((data[1] == ds->prev[1]) && (data[2] == ds->prev[2])
+ && (data[3] == ds->prev[3])) {
+ i = j = 1;
+ } else if ((data[1] == data[2]) && (data[2] == data[3])) {
+ i = j = 2;
+ } else {
+ i = 3;
+ j = 4;
+ }
+ data[0] |= (i << 30);
+ return store_data(ds, data, j);
+}
+
+static int parse_write_entry(struct data_src *ds)
+{
+ uint32_t data[4];
+ int ret, i;
+
+ ret = get_data(ds, data, 4);
+ if (ret)
+ return ret;
+ if (data[0] & 3) {
+ fprintf(stderr, "Address must be aligned on word boundary\n");
+ return -1;
+ }
+ if ((data[1] == ds->prev[1]) && (data[2] == ds->prev[2])
+ && (data[3] == ds->prev[3]))
+ i = 0;
+ else if ((data[1] == data[2]) && (data[2] == data[3]))
+ i = 1;
+ else if (data[2] == data[3])
+ i = 2;
+ else
+ i = 3;
+ data[0] |= i;
+ return store_data(ds, data, i + 1);
+}
+
static int parse_image_version(struct data_src *ds)
{
int ret;
@@ -618,8 +736,82 @@ static int parse_boot_from(struct data_src *ds)
return 0;
}
+static int parse_plugin(struct data_src *ds)
+{
+ struct stat sbuf;
+ int plug_file;
+ unsigned char *ptr;
+ char *p;
+ char c;
+ int ret;
+ uint32_t plug_base;
+ uint32_t header_length;
+
+ if (g_flash_offset == FLASH_OFFSET_UNDEFINED) {
+ fprintf(stderr, "Error: Place BOOT_FROM before plugin\n");
+ return -1;
+ }
+ ret = get_cfg_value(ds, &plug_base);
+ if (ret)
+ return ret;
+
+ if (skip_separators(ds))
+ return -1;
+ p = ds->p;
+ for (;;) {
+ c = *p;
+ if (!c)
+ break;
+ if ((c == ' ') || (c == '\t') || (c == ';') || (c == '#')
+ || (c == '\r') || (c == '\n')) {
+ *p = 0;
+ break;
+ }
+ p++;
+ }
+ plug_file = open(ds->p, O_RDONLY|O_BINARY);
+ if (plug_file < 0) {
+ fprintf(stderr, "Can't open plugin file %s: %s\n",
+ ds->p, strerror(errno));
+ *p = c;
+ return -1;
+ }
+ if (fstat(plug_file, &sbuf) < 0) {
+ fprintf(stderr, "Can't stat %s: %s\n",
+ ds->p, strerror(errno));
+ close(plug_file);
+ return -1;
+ }
+ ptr = mmap(0, sbuf.st_size, PROT_READ, MAP_SHARED, plug_file, 0);
+ if (ptr == MAP_FAILED) {
+ fprintf(stderr, "Can't read %s: %s\n",
+ ds->p, strerror(errno));
+ return -1;
+ }
+ *p = c;
+ ds->p = p;
+ /* Set the plugin header */
+ header_length = (*set_imx_hdr)(ds->imxhdr, plug_base,
+ g_flash_offset, 1);
+
+ p = ((char *)ds->imxhdr) + header_length;
+ if ((p + sbuf.st_size) >= (char *)p_max_dcd) {
+ fprintf(stderr, "Out of space\n");
+ return -1;
+ }
+
+ ds->plugin = 1;
+ memcpy(p, ptr, sbuf.st_size);
+ munmap((void *)ptr, sbuf.st_size);
+ close(plug_file);
+
+ p_entry = (uint32_t *)(p + sbuf.st_size);
+ return 0;
+}
+
parse_fld_t cmd_table[] = {
- parse_image_version, parse_boot_from, parse_cmd_data
+ parse_image_version, parse_boot_from, parse_cmd_data, parse_plugin,
+ parse_iomux_entry, parse_write_entry
};
static int parse_command(struct data_src *ds)
@@ -630,9 +822,11 @@ static int parse_command(struct data_src *ds)
return cmd_table[cmd](ds);
}
-static void parse_cfg_file(struct imx_header *imxhdr, char *name)
+static void parse_cfg_file(struct imx_header *imxhdr, char *name,
+ uint32_t entry_point)
{
struct data_src ds;
+ uint32_t plugin_length = 0;
ds.line = NULL;
ds.len = 0;
@@ -662,6 +856,35 @@ static void parse_cfg_file(struct imx_header *imxhdr, char *name)
cmd_cnt++;
}
fclose(ds.fd);
+
+ if (ds.plugin) {
+ uint32_t header_length, more;
+ struct imx_header *next_imxhdr;
+
+ *p_entry++ = 0;
+ header_length = ((char *)p_entry) - ((char *)imxhdr);
+ plugin_length = ((header_length - 1) | 0x3f) + 1;
+ more = plugin_length - header_length;
+ if (more)
+ memset(p_entry, 0, more);
+ next_imxhdr = (struct imx_header *)
+ (((char *)imxhdr) + plugin_length);
+ p_entry = (imximage_version == IMXIMAGE_V1) ? (uint32_t *)
+ &next_imxhdr->header.hdr_v1.dcd_table.addr_data[0].type
+ : (uint32_t *)&next_imxhdr->header.hdr_v2.dcd_table;
+ if (p_entry > p_max_dcd) {
+ fprintf(stderr, "Out of space\n");
+ exit(EXIT_FAILURE);
+ }
+
+ /* Set the plugin size in header to include next header */
+ *header_size_ptr = ((char *)p_entry) - ((char *)imxhdr)
+ + g_flash_offset;
+ imxhdr = next_imxhdr;
+ }
+ /* Set the imx header */
+ imximage_params.header_size = (*set_imx_hdr)(imxhdr, entry_point,
+ g_flash_offset + plugin_length, 0) + plugin_length;
return;
}
@@ -727,7 +950,7 @@ int imximage_vrec_header(struct mkimage_params *params,
set_hdr_func(imxhdr);
/* Parse dcd configuration file */
- parse_cfg_file(imxhdr, params->imagename);
+ parse_cfg_file(imxhdr, params->imagename, params->ep);
/* Exit if there is no BOOT_FROM field specifying the flash_offset */
if (g_flash_offset == FLASH_OFFSET_UNDEFINED) {
@@ -735,9 +958,6 @@ int imximage_vrec_header(struct mkimage_params *params,
params->imagename);
exit(EXIT_FAILURE);
}
- /* Set the imx header */
- imximage_params.header_size = (*set_imx_hdr)(imxhdr, params->ep,
- g_flash_offset);
imximage_params.hdr = imxhdr;
return 0;
}
@@ -746,8 +966,10 @@ static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd,
struct mkimage_params *params)
{
/* Set the size in header */
- (*set_imx_size)((struct imx_header *)ptr, sbuf->st_size,
- g_flash_offset);
+ uint32_t offset = (char *)header_size_ptr - (char *)imximage_params.hdr;
+ uint32_t *p = (uint32_t *)((char *)ptr + offset);
+
+ *p = sbuf->st_size + g_flash_offset;
}
int imximage_check_params(struct mkimage_params *params)
diff --git a/tools/imximage.h b/tools/imximage.h
index efd249b..79f0156 100644
--- a/tools/imximage.h
+++ b/tools/imximage.h
@@ -51,7 +51,10 @@
enum imximage_cmd {
CMD_IMAGE_VERSION,
CMD_BOOT_FROM,
- CMD_DATA
+ CMD_DATA,
+ CMD_PLUGIN,
+ CMD_IOMUX_ENTRY,
+ CMD_WRITE_ENTRY,
};
enum imximage_version {
@@ -158,6 +161,8 @@ struct data_src {
char *filename;
struct imx_header *imxhdr;
char *p;
+ int plugin;
+ uint32_t prev[4];
};
typedef int (*parse_fld_t)(struct data_src *ds);
@@ -165,8 +170,6 @@ typedef int (*parse_fld_t)(struct data_src *ds);
typedef int (*set_dcd_val_t)(struct imx_header *imxhdr, uint32_t *data);
typedef int (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t entry_point,
- uint32_t flash_offset);
-typedef void (*set_imx_size_t)(struct imx_header *imxhdr, uint32_t file_size,
- uint32_t flash_offset);
+ uint32_t flash_offset, int plugin);
#endif /* _IMXIMAGE_H_ */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH 07/11] imximage.cfg: run files through C preprocessor
2012-09-19 0:02 [U-Boot] (no subject) Troy Kisky
` (5 preceding siblings ...)
2012-09-19 0:03 ` [U-Boot] [PATCH 06/11] imximage: add plugin commands Troy Kisky
@ 2012-09-19 0:03 ` Troy Kisky
2012-09-19 0:03 ` [U-Boot] [PATCH 08/11] mx6: add plugin file for use with imximage.cfg Troy Kisky
` (4 subsequent siblings)
11 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-09-19 0:03 UTC (permalink / raw)
To: u-boot
The '#' used as comments in the files cause the preprocessor
trouble, so change to /* */.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
Makefile | 3 +-
board/esg/ima3-mx53/imximage.cfg | 120 ++++++-----
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 90 ++++----
board/freescale/mx25pdk/imximage.cfg | 77 +++----
board/freescale/mx51evk/imximage.cfg | 114 +++++-----
board/freescale/mx53ard/imximage_dd3.cfg | 83 ++++----
board/freescale/mx53evk/imximage.cfg | 86 ++++----
board/freescale/mx53loco/imximage.cfg | 83 ++++----
board/freescale/mx53smd/imximage.cfg | 83 ++++----
board/freescale/mx6qarm2/imximage.cfg | 88 ++++----
board/genesi/mx51_efikamx/imximage_mx.cfg | 132 ++++++------
board/genesi/mx51_efikamx/imximage_sb.cfg | 126 +++++------
board/ttcontrol/vision2/imximage_hynix.cfg | 295 ++++++++++++++------------
13 files changed, 727 insertions(+), 653 deletions(-)
diff --git a/Makefile b/Makefile
index fe2f98c..edf647e 100644
--- a/Makefile
+++ b/Makefile
@@ -425,7 +425,8 @@ $(obj)u-boot.img: $(obj)u-boot.bin
-d $< $@
$(obj)u-boot.imx: $(obj)u-boot.bin
- $(obj)tools/mkimage -n $(CONFIG_IMX_CONFIG) -T imximage \
+ $(CC) -E -x c $(CONFIG_IMX_CONFIG) -I./include -o $(obj)imxcfg.imx
+ $(obj)tools/mkimage -n $(obj)imxcfg.imx -T imximage \
-e $(CONFIG_SYS_TEXT_BASE) -d $< $@
$(obj)u-boot.kwb: $(obj)u-boot.bin
diff --git a/board/esg/ima3-mx53/imximage.cfg b/board/esg/ima3-mx53/imximage.cfg
index fa6b42d..fce7492 100644
--- a/board/esg/ima3-mx53/imximage.cfg
+++ b/board/esg/ima3-mx53/imximage.cfg
@@ -1,50 +1,52 @@
-#
-# (C) Copyright 2012
-# Stefano Babic DENX Software Engineering sbabic at denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not write to the Free Software
-# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
-# MA 02110-1301 USA
-#
-# Refer docs/README.imxmage for more details about how-to configure
-# and create imximage boot image
-#
-# The syntax is taken as close as possible with the kwbimage
-
-# image version
+/*
+ * (C) Copyright 2012
+ * Stefano Babic DENX Software Engineering sbabic at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+/* image version */
IMAGE_VERSION 2
-# Boot Device : one of
-# spi, sd (the board has no nand neither onenand)
-
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
BOOT_FROM nor
-# Device Configuration Data (DCD)
-#
-# Each entry must have the format:
-# Addr-type Address Value
-#
-# where:
-# Addr-type register length (1,2 or 4 bytes)
-# Address absolute address of the register
-# value value to be stored in the register
-
-# IOMUX for RAM only
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+/* IOMUX for RAM only */
DATA 4 0x53fa8554 0x300020
DATA 4 0x53fa8560 0x300020
DATA 4 0x53fa8594 0x300020
@@ -72,37 +74,47 @@ DATA 4 0x53fa86fc 0x0
DATA 4 0x53fa86f4 0x0
DATA 4 0x53fa8714 0x0
DATA 4 0x53fa8724 0x4000000
-#
-# DDR RAM
+
+/* DDR RAM */
DATA 4 0x63fd9088 0x40404040
DATA 4 0x63fd9090 0x40404040
DATA 4 0x63fd907C 0x01420143
DATA 4 0x63fd9080 0x01450146
DATA 4 0x63fd9018 0x00111740
DATA 4 0x63fd9000 0x84190000
-# esdcfgX
+
+/* esdcfgX */
DATA 4 0x63fd900C 0x9f5152e3
DATA 4 0x63fd9010 0xb68e8a63
DATA 4 0x63fd9014 0x01ff00db
-# Read/Write command delay
+
+/* Read/Write command delay */
DATA 4 0x63fd902c 0x000026d2
-# Out of reset delays
+
+/* Out of reset delays */
DATA 4 0x63fd9030 0x00ff0e21
-# ESDCTL ODT timing control
+
+/* ESDCTL ODT timing control */
DATA 4 0x63fd9008 0x12273030
-# ESDCTL power down control
+
+/* ESDCTL power down control */
DATA 4 0x63fd9004 0x0002002d
-# Set registers in DDR memory chips
+
+/* Set registers in DDR memory chips */
DATA 4 0x63fd901c 0x00008032
DATA 4 0x63fd901c 0x00008033
DATA 4 0x63fd901c 0x00028031
DATA 4 0x63fd901c 0x052080b0
DATA 4 0x63fd901c 0x04008040
-# ESDCTL refresh control
+
+/* ESDCTL refresh control */
DATA 4 0x63fd9020 0x00005800
-# PHY ZQ HW control
+
+/* PHY ZQ HW control */
DATA 4 0x63fd9040 0x05380003
-# PHY ODT control
+
+/* PHY ODT control */
DATA 4 0x63fd9058 0x00022222
-# start DDR3
+
+/* start DDR3 */
DATA 4 0x63fd901c 0x00000000
diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
index 62498ab..c86cd40 100644
--- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
@@ -1,47 +1,51 @@
-# Copyright (C) 2011 Freescale Semiconductor, Inc.
-# Jason Liu <r64343@freescale.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not write to the Free Software
-# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
-# MA 02110-1301 USA
-#
-# Refer docs/README.imxmage for more details about how-to configure
-# and create imximage boot image
-#
-# The syntax is taken as close as possible with the kwbimage
-
-# image version
-
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * Jason Liu <r64343@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
IMAGE_VERSION 2
-# Boot Device : one of
-# spi, sd (the board has no nand neither onenand)
-
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
BOOT_FROM sd
-# Device Configuration Data (DCD)
-#
-# Each entry must have the format:
-# Addr-type Address Value
-#
-# where:
-# Addr-type register length (1,2 or 4 bytes)
-# Address absolute address of the register
-# value value to be stored in the register
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
DATA 4 0x020e05a8 0x00000030
DATA 4 0x020e05b0 0x00000030
DATA 4 0x020e0524 0x00000030
@@ -154,7 +158,7 @@ DATA 4 0x021b48b8 0x00000800
DATA 4 0x021b001c 0x00000000
DATA 4 0x021b0404 0x00011006
-# set the default clock gate to save power
+/* set the default clock gate to save power */
DATA 4 0x020c4068 0x00C03F3F
DATA 4 0x020c406c 0x0030FC03
DATA 4 0x020c4070 0x0FFFC000
@@ -163,8 +167,8 @@ DATA 4 0x020c4078 0x00FFF300
DATA 4 0x020c407c 0x0F0000C3
DATA 4 0x020c4080 0x000003FF
-# enable AXI cache for VDOA/VPU/IPU
+/* enable AXI cache for VDOA/VPU/IPU */
DATA 4 0x020e0010 0xF00000CF
-# set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
DATA 4 0x020e0018 0x007F007F
DATA 4 0x020e001c 0x007F007F
diff --git a/board/freescale/mx25pdk/imximage.cfg b/board/freescale/mx25pdk/imximage.cfg
index f7af7ff..c42a283 100644
--- a/board/freescale/mx25pdk/imximage.cfg
+++ b/board/freescale/mx25pdk/imximage.cfg
@@ -1,46 +1,49 @@
-#
-# (C) Copyright 2009
-# Stefano Babic DENX Software Engineering sbabic at denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# Refer docs/README.imxmage for more details about how-to configure
-# and create imximage boot image
-#
-# The syntax is taken as close as possible with the kwbimage
-
-# Boot Device : one of
-# spi, sd (the board has no nand neither onenand)
+/*
+ * (C) Copyright 2009
+ * Stefano Babic DENX Software Engineering sbabic at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
BOOT_FROM sd
-# Device Configuration Data (DCD)
-#
-# Each entry must have the format:
-# Addr-type Address Value
-#
-# where:
-# Addr-type register length (1,2 or 4 bytes)
-# Address absolute address of the register
-# value value to be stored in the register
-
-# EIM config-CS5 init -- CPLD
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+/* EIM config-CS5 init -- CPLD */
DATA 4 0xB8002050 0x0000D843
DATA 4 0xB8002054 0x22252521
DATA 4 0xB8002058 0x22220A00
-# DDR2 init
+/* DDR2 init */
DATA 4 0xB8001004 0x0076E83A
DATA 4 0xB8001010 0x00000204
DATA 4 0xB8001000 0x92210000
@@ -67,7 +70,7 @@ DATA 4 0x43FAC454 0x00001000
DATA 4 0x53F80008 0x20034000
-# Enable the clocks
+/* Enable the clocks */
DATA 4 0x53f8000c 0x1fffffff
DATA 4 0x53f80010 0xffffffff
DATA 4 0x53f80014 0xfdfff
diff --git a/board/freescale/mx51evk/imximage.cfg b/board/freescale/mx51evk/imximage.cfg
index a875e8f..3e141ee 100644
--- a/board/freescale/mx51evk/imximage.cfg
+++ b/board/freescale/mx51evk/imximage.cfg
@@ -1,46 +1,50 @@
-#
-# (C Copyright 2009
-# Stefano Babic DENX Software Engineering sbabic at denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not write to the Free Software
-# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
-# MA 02110-1301 USA
-#
-# Refer docs/README.imxmage for more details about how-to configure
-# and create imximage boot image
-#
-# The syntax is taken as close as possible with the kwbimage
-
-# Boot Device : one of
-# spi, sd (the board has no nand neither onenand)
+/*
+ * (C Copyright 2009
+ * Stefano Babic DENX Software Engineering sbabic at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
BOOT_FROM spi
-# Device Configuration Data (DCD)
-#
-# Each entry must have the format:
-# Addr-type Address Value
-#
-# where:
-# Addr-type register length (1,2 or 4 bytes)
-# Address absolute address of the register
-# value value to be stored in the register
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
-# Setting IOMUXC
+/* Setting IOMUXC */
DATA 4 0x73FA88a0 0x200
DATA 4 0x73FA850c 0x20c5
DATA 4 0x73FA8510 0x20c5
@@ -65,22 +69,24 @@ DATA 4 0x73FA88a4 0x6
DATA 4 0x73FA88ac 0x6
DATA 4 0x73FA88b8 0x6
-# Setting DDR for micron
-# 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
-# CAS=3 BL=4
-# ESDCTL_ESDCTL0
+/*
+ * Setting DDR for micron
+ * 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
+ * CAS=3 BL=4
+ */
+/* ESDCTL_ESDCTL0 */
DATA 4 0x83FD9000 0x82a20000
-# ESDCTL_ESDCTL1
+/* ESDCTL_ESDCTL1 */
DATA 4 0x83FD9008 0x82a20000
-# ESDCTL_ESDMISC
+/* ESDCTL_ESDMISC */
DATA 4 0x83FD9010 0x000ad0d0
-# ESDCTL_ESDCFG0
+/* ESDCTL_ESDCFG0 */
DATA 4 0x83FD9004 0x333574aa
-# ESDCTL_ESDCFG1
+/* ESDCTL_ESDCFG1 */
DATA 4 0x83FD900C 0x333574aa
-# Init DRAM on CS0
-# ESDCTL_ESDSCR
+/* Init DRAM on CS0 */
+/* ESDCTL_ESDSCR */
DATA 4 0x83FD9014 0x04008008
DATA 4 0x83FD9014 0x0000801a
DATA 4 0x83FD9014 0x0000801b
@@ -94,7 +100,7 @@ DATA 4 0x83FD9014 0x03808019
DATA 4 0x83FD9014 0x00408019
DATA 4 0x83FD9014 0x00008000
-# Init DRAM on CS1
+/* Init DRAM on CS1 */
DATA 4 0x83FD9014 0x0400800c
DATA 4 0x83FD9014 0x0000801e
DATA 4 0x83FD9014 0x0000801f
@@ -108,12 +114,12 @@ DATA 4 0x83FD9014 0x0380801d
DATA 4 0x83FD9014 0x0040801d
DATA 4 0x83FD9014 0x00008004
-# Write to CTL0
+/* Write to CTL0 */
DATA 4 0x83FD9000 0xb2a20000
-# Write to CTL1
+/* Write to CTL1 */
DATA 4 0x83FD9008 0xb2a20000
-# ESDMISC
+/* ESDMISC */
DATA 4 0x83FD9010 0x000ad6d0
-#ESDCTL_ESDCDLYGD
+/* ESDCTL_ESDCDLYGD */
DATA 4 0x83FD9034 0x90000000
DATA 4 0x83FD9014 0x00000000
diff --git a/board/freescale/mx53ard/imximage_dd3.cfg b/board/freescale/mx53ard/imximage_dd3.cfg
index 614d29e..4633e4d 100644
--- a/board/freescale/mx53ard/imximage_dd3.cfg
+++ b/board/freescale/mx53ard/imximage_dd3.cfg
@@ -1,48 +1,51 @@
-#
-# (C) Copyright 2009
-# Stefano Babic DENX Software Engineering sbabic at denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not write to the Free Software
-# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
-# MA 02110-1301 USA
-#
-# Refer docs/README.imxmage for more details about how-to configure
-# and create imximage boot image
-#
-# The syntax is taken as close as possible with the kwbimage
-
-# image version
+/*
+ * (C) Copyright 2009
+ * Stefano Babic DENX Software Engineering sbabic at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+/* image version */
IMAGE_VERSION 2
-# Boot Device : one of
-# spi, sd (the board has no nand neither onenand)
-
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
BOOT_FROM sd
-# Device Configuration Data (DCD)
-#
-# Each entry must have the format:
-# Addr-type Address Value
-#
-# where:
-# Addr-type register length (1,2 or 4 bytes)
-# Address absolute address of the register
-# value value to be stored in the register
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
DATA 4 0x53fa8554 0x00300000
DATA 4 0x53fa8558 0x00300040
DATA 4 0x53fa8560 0x00300000
diff --git a/board/freescale/mx53evk/imximage.cfg b/board/freescale/mx53evk/imximage.cfg
index 915fb2c..1cd61d5 100644
--- a/board/freescale/mx53evk/imximage.cfg
+++ b/board/freescale/mx53evk/imximage.cfg
@@ -1,50 +1,52 @@
-#
-# (C Copyright 2009
-# Stefano Babic DENX Software Engineering sbabic at denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not write to the Free Software
-# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
-# MA 02110-1301 USA
-#
-# Refer docs/README.imxmage for more details about how-to configure
-# and create imximage boot image
-#
-# The syntax is taken as close as possible with the kwbimage
-
-# image version
+/*
+ * (C Copyright 2009
+ * Stefano Babic DENX Software Engineering sbabic at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+/* image version */
IMAGE_VERSION 2
-# Boot Device : one of
-# spi, sd (the board has no nand neither onenand)
-
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
BOOT_FROM sd
-# Device Configuration Data (DCD)
-#
-# Each entry must have the format:
-# Addr-type Address Value
-#
-# where:
-# Addr-type register length (1,2 or 4 bytes)
-# Address absolute address of the register
-# value value to be stored in the register
-
-# Setting IOMUXC
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+/* Setting IOMUXC */
DATA 4 0x53fa8554 0x00200000
DATA 4 0x53fa8560 0x00200000
DATA 4 0x53fa8594 0x00200000
diff --git a/board/freescale/mx53loco/imximage.cfg b/board/freescale/mx53loco/imximage.cfg
index 2ce5f8d..e6b90c1 100644
--- a/board/freescale/mx53loco/imximage.cfg
+++ b/board/freescale/mx53loco/imximage.cfg
@@ -1,48 +1,51 @@
-# Copyright (C) 2011 Freescale Semiconductor, Inc.
-# Jason Liu <r64343@freescale.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not write to the Free Software
-# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
-# MA 02110-1301 USA
-#
-# Refer docs/README.imxmage for more details about how-to configure
-# and create imximage boot image
-#
-# The syntax is taken as close as possible with the kwbimage
-
-# image version
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * Jason Liu <r64343@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+/* image version */
IMAGE_VERSION 2
-# Boot Device : one of
-# spi, sd (the board has no nand neither onenand)
-
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
BOOT_FROM sd
-# Device Configuration Data (DCD)
-#
-# Each entry must have the format:
-# Addr-type Address Value
-#
-# where:
-# Addr-type register length (1,2 or 4 bytes)
-# Address absolute address of the register
-# value value to be stored in the register
-
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
DATA 4 0x53fa8554 0x00300000
DATA 4 0x53fa8558 0x00300040
DATA 4 0x53fa8560 0x00300000
diff --git a/board/freescale/mx53smd/imximage.cfg b/board/freescale/mx53smd/imximage.cfg
index 614d29e..4633e4d 100644
--- a/board/freescale/mx53smd/imximage.cfg
+++ b/board/freescale/mx53smd/imximage.cfg
@@ -1,48 +1,51 @@
-#
-# (C) Copyright 2009
-# Stefano Babic DENX Software Engineering sbabic at denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not write to the Free Software
-# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
-# MA 02110-1301 USA
-#
-# Refer docs/README.imxmage for more details about how-to configure
-# and create imximage boot image
-#
-# The syntax is taken as close as possible with the kwbimage
-
-# image version
+/*
+ * (C) Copyright 2009
+ * Stefano Babic DENX Software Engineering sbabic at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+/* image version */
IMAGE_VERSION 2
-# Boot Device : one of
-# spi, sd (the board has no nand neither onenand)
-
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
BOOT_FROM sd
-# Device Configuration Data (DCD)
-#
-# Each entry must have the format:
-# Addr-type Address Value
-#
-# where:
-# Addr-type register length (1,2 or 4 bytes)
-# Address absolute address of the register
-# value value to be stored in the register
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
DATA 4 0x53fa8554 0x00300000
DATA 4 0x53fa8558 0x00300040
DATA 4 0x53fa8560 0x00300000
diff --git a/board/freescale/mx6qarm2/imximage.cfg b/board/freescale/mx6qarm2/imximage.cfg
index bf941a3..4ed211e 100644
--- a/board/freescale/mx6qarm2/imximage.cfg
+++ b/board/freescale/mx6qarm2/imximage.cfg
@@ -1,47 +1,51 @@
-# Copyright (C) 2011 Freescale Semiconductor, Inc.
-# Jason Liu <r64343@freescale.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not write to the Free Software
-# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
-# MA 02110-1301 USA
-#
-# Refer docs/README.imxmage for more details about how-to configure
-# and create imximage boot image
-#
-# The syntax is taken as close as possible with the kwbimage
-
-# image version
-
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * Jason Liu <r64343@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
IMAGE_VERSION 2
-# Boot Device : one of
-# spi, sd (the board has no nand neither onenand)
-
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
BOOT_FROM sd
-# Device Configuration Data (DCD)
-#
-# Each entry must have the format:
-# Addr-type Address Value
-#
-# where:
-# Addr-type register length (1,2 or 4 bytes)
-# Address absolute address of the register
-# value value to be stored in the register
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
DATA 4 0x020e05a8 0x00000030
DATA 4 0x020e05b0 0x00000030
DATA 4 0x020e0524 0x00000030
@@ -166,8 +170,8 @@ DATA 4 0x020c4078 0x00FFF300
DATA 4 0x020c407c 0x0F0000C3
DATA 4 0x020c4080 0x000003FF
-# enable AXI cache for VDOA/VPU/IPU
+/* enable AXI cache for VDOA/VPU/IPU */
DATA 4 0x020e0010 0xF00000CF
-# set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
DATA 4 0x020e0018 0x007F007F
DATA 4 0x020e001c 0x007F007F
diff --git a/board/genesi/mx51_efikamx/imximage_mx.cfg b/board/genesi/mx51_efikamx/imximage_mx.cfg
index 38fa760..21ff6d6 100644
--- a/board/genesi/mx51_efikamx/imximage_mx.cfg
+++ b/board/genesi/mx51_efikamx/imximage_mx.cfg
@@ -1,52 +1,58 @@
-#
-# Copyright (C) 2009 Pegatron Corporation
-# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
-# Copyright (C) 2009-2012 Genesi USA, Inc.
-#
-# BASED ON: imx51evk
-#
-# (C) Copyright 2009
-# Stefano Babic DENX Software Engineering sbabic at denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not write to the Free Software
-# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
-# MA 02110-1301 USA
-#
-# Refer docs/README.imxmage for more details about how-to configure
-# and create imximage boot image
-#
-# The syntax is taken as close as possible with the kwbimage
+/*
+ * Copyright (C) 2009 Pegatron Corporation
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ * Copyright (C) 2009-2012 Genesi USA, Inc.
+ *
+ * BASED ON: imx51evk
+ *
+ * (C) Copyright 2009
+ * Stefano Babic DENX Software Engineering sbabic at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
-# Boot Device : one of
-# spi, sd (the board has no nand neither onenand)
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
BOOT_FROM spi
-# Device Configuration Data (DCD)
-#
-# Each entry must have the format:
-# Addr-type Address Value
-#
-# where:
-# Addr-type register length (1,2 or 4 bytes)
-# Address absolute address of the register
-# value value to be stored in the register
-
-# Essential GPIO settings to be done as early as possible
-# PCBIDn pad settings are all the defaults except #2 which needs HVE off
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+/*
+ * Essential GPIO settings to be done as early as possible
+ * PCBIDn pad settings are all the defaults except #2 which needs HVE off
+ */
DATA 4 0x73fa8134 0x3 # PCBID0 ALT3 GPIO 3_16
DATA 4 0x73fa8130 0x3 # PCBID1 ALT3 GPIO 3_17
DATA 4 0x73fa8128 0x3 # PCBID2 ALT3 GPIO 3_11
@@ -55,7 +61,7 @@ DATA 4 0x73fa8198 0x3 # LED0 ALT3 GPIO 3_13
DATA 4 0x73fa81c4 0x3 # LED1 ALT3 GPIO 3_14
DATA 4 0x73fa81c8 0x3 # LED2 ALT3 GPIO 3_15
-# DDR bus IOMUX PAD settings
+/* DDR bus IOMUX PAD settings */
DATA 4 0x73fa850c 0x20c5 # SDODT1
DATA 4 0x73fa8510 0x20c5 # SDODT0
DATA 4 0x73fa84ac 0xc5 # SDWE
@@ -72,22 +78,24 @@ DATA 4 0x73fa84d8 0xc5 # DRAM_DQM1
DATA 4 0x73fa84dc 0xc5 # DRAM_DQM2
DATA 4 0x73fa84e0 0xc5 # DRAM_DQM3
-# Setting DDR for micron
-# 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
-# CAS=3 BL=4
-# ESDCTL_ESDCTL0
+/*
+ * Setting DDR for micron
+ * 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
+ * CAS=3 BL=4
+ */
+/* ESDCTL_ESDCTL0 */
DATA 4 0x83fd9000 0x82a20000
-# ESDCTL_ESDCTL1
+/* ESDCTL_ESDCTL1 */
DATA 4 0x83fd9008 0x82a20000
-# ESDCTL_ESDMISC
+/* ESDCTL_ESDMISC */
DATA 4 0x83fd9010 0xcaaaf6d0
-# ESDCTL_ESDCFG0
+/* ESDCTL_ESDCFG0 */
DATA 4 0x83fd9004 0x3f3574aa
-# ESDCTL_ESDCFG1
+/* ESDCTL_ESDCFG1 */
DATA 4 0x83fd900c 0x3f3574aa
-# Init DRAM on CS0
-# ESDCTL_ESDSCR
+/* Init DRAM on CS0 */
+/* ESDCTL_ESDSCR */
DATA 4 0x83fd9014 0x04008008
DATA 4 0x83fd9014 0x0000801a
DATA 4 0x83fd9014 0x0000801b
@@ -101,7 +109,7 @@ DATA 4 0x83fd9014 0x03808019
DATA 4 0x83fd9014 0x00408019
DATA 4 0x83fd9014 0x00008000
-# Init DRAM on CS1
+/* Init DRAM on CS1 */
DATA 4 0x83fd9014 0x0400800c
DATA 4 0x83fd9014 0x0000801e
DATA 4 0x83fd9014 0x0000801f
@@ -115,12 +123,12 @@ DATA 4 0x83fd9014 0x0380801d
DATA 4 0x83fd9014 0x0040801d
DATA 4 0x83fd9014 0x00008004
-# Write to CTL0
+/* Write to CTL0 */
DATA 4 0x83fd9000 0xb2a20000
-# Write to CTL1
+/* Write to CTL1 */
DATA 4 0x83fd9008 0xb2a20000
-# ESDMISC
+/* ESDMISC */
DATA 4 0x83fd9010 0x000ad6d0
-#ESDCTL_ESDCDLYGD
+/* ESDCTL_ESDCDLYGD */
DATA 4 0x83fd9034 0x90000000
DATA 4 0x83fd9014 0x00000000
diff --git a/board/genesi/mx51_efikamx/imximage_sb.cfg b/board/genesi/mx51_efikamx/imximage_sb.cfg
index 26d259f..7ddd0b1 100644
--- a/board/genesi/mx51_efikamx/imximage_sb.cfg
+++ b/board/genesi/mx51_efikamx/imximage_sb.cfg
@@ -1,51 +1,55 @@
-#
-# Copyright (C) 2009 Pegatron Corporation
-# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
-# Copyright (C) 2009-2012 Genesi USA, Inc.
-#
-# BASED ON: imx51evk
-#
-# (C) Copyright 2009
-# Stefano Babic DENX Software Engineering sbabic at denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not write to the Free Software
-# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
-# MA 02110-1301 USA
-#
-# Refer docs/README.imxmage for more details about how-to configure
-# and create imximage boot image
-#
-# The syntax is taken as close as possible with the kwbimage
+/*
+ * Copyright (C) 2009 Pegatron Corporation
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ * Copyright (C) 2009-2012 Genesi USA, Inc.
+ *
+ * BASED ON: imx51evk
+ *
+ * (C) Copyright 2009
+ * Stefano Babic DENX Software Engineering sbabic at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
-# Boot Device : one of
-# spi, sd (the board has no nand neither onenand)
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
BOOT_FROM spi
-# Device Configuration Data (DCD)
-#
-# Each entry must have the format:
-# Addr-type Address Value
-#
-# where:
-# Addr-type register length (1,2 or 4 bytes)
-# Address absolute address of the register
-# value value to be stored in the register
-
-# DDR bus IOMUX PAD settings
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+*/
+/* DDR bus IOMUX PAD settings */
DATA 4 0x73fa88a0 0x200 # GRP_INMODE1
DATA 4 0x73fa850c 0x20c5 # SDODT1
DATA 4 0x73fa8510 0x20c5 # SDODT0
@@ -62,22 +66,24 @@ DATA 4 0x73fa84b4 0xe5 # SDCKE1
DATA 4 0x73fa84cc 0xe5 # DRAM_CS0
DATA 4 0x73fa84d0 0xe4 # DRAM_CS1
-# Setting DDR for micron
-# 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
-# CAS=3 BL=4
-# ESDCTL_ESDCTL0
+/*
+ * Setting DDR for micron
+ * 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
+ * CAS=3 BL=4
+ */
+/* ESDCTL_ESDCTL0 */
DATA 4 0x83fd9000 0x82a20000
-# ESDCTL_ESDCTL1
+/* ESDCTL_ESDCTL1 */
DATA 4 0x83fd9008 0x82a20000
-# ESDCTL_ESDMISC
+/* ESDCTL_ESDMISC */
DATA 4 0x83fd9010 0xcaaaf6d0
-# ESDCTL_ESDCFG0
+/* ESDCTL_ESDCFG0 */
DATA 4 0x83fd9004 0x333574aa
-# ESDCTL_ESDCFG1
+/* ESDCTL_ESDCFG1 */
DATA 4 0x83fd900c 0x333574aa
-# Init DRAM on CS0
-# ESDCTL_ESDSCR
+/* Init DRAM on CS0 */
+/* ESDCTL_ESDSCR */
DATA 4 0x83fd9014 0x04008008
DATA 4 0x83fd9014 0x0000801a
DATA 4 0x83fd9014 0x0000801b
@@ -91,7 +97,7 @@ DATA 4 0x83fd9014 0x03808019
DATA 4 0x83fd9014 0x00408019
DATA 4 0x83fd9014 0x00008000
-# Init DRAM on CS1
+/* Init DRAM on CS1 */
DATA 4 0x83fd9014 0x0400800c
DATA 4 0x83fd9014 0x0000801e
DATA 4 0x83fd9014 0x0000801f
@@ -105,12 +111,12 @@ DATA 4 0x83fd9014 0x0380801d
DATA 4 0x83fd9014 0x0042801d
DATA 4 0x83fd9014 0x00008004
-# Write to CTL0
+/* Write to CTL0 */
DATA 4 0x83fd9000 0xb2a20000
-# Write to CTL1
+/* Write to CTL1 */
DATA 4 0x83fd9008 0xb2a20000
-# ESDMISC
+/* ESDMISC */
DATA 4 0x83fd9010 0xcaaaf6d0
-#ESDCTL_ESDCDLYGD
+/* ESDCTL_ESDCDLYGD */
DATA 4 0x83fd9034 0x90000000
DATA 4 0x83fd9014 0x00000000
diff --git a/board/ttcontrol/vision2/imximage_hynix.cfg b/board/ttcontrol/vision2/imximage_hynix.cfg
index ed531db..c1de94f 100644
--- a/board/ttcontrol/vision2/imximage_hynix.cfg
+++ b/board/ttcontrol/vision2/imximage_hynix.cfg
@@ -1,209 +1,228 @@
-#
-# (C) Copyright 2009
-# Stefano Babic DENX Software Engineering sbabic at denx.de.
-#
-# (C) Copyright 2010
-# Klaus Steinhammer TTECH Control Gmbh kst at tttech.com
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not write to the Free Software
-# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
-# MA 02110-1301 USA
-#
-# Refer docs/README.imxmage for more details about how-to configure
-# and create imximage boot image
-#
-# The syntax is taken as close as possible with the kwbimage
-
-# Boot Device : one of
-# spi, nand, onenand, sd
-
+/*
+ * (C) Copyright 2009
+ * Stefano Babic DENX Software Engineering sbabic at denx.de.
+ *
+ * (C) Copyright 2010
+ * Klaus Steinhammer TTECH Control Gmbh kst at tttech.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/*
+ * Boot Device : one of
+ * spi, nand, onenand, sd
+ */
BOOT_FROM spi
-# Device Configuration Data (DCD)
-#
-# Each entry must have the format:
-# Addr-type Address Value
-#
-# where:
-# Addr-type register length (1,2 or 4 bytes)
-# Address absolute address of the register
-# value value to be stored in the register
-
-#######################
-### Disable WDOG ###
-#######################
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+/*
+ * #######################
+ * ### Disable WDOG ###
+ * #######################
+ */
DATA 2 0x73f98000 0x30
-#######################
-### SET DDR Clk ###
-#######################
-
-# CCM: CBMCR - ddr_clk_sel: axi_b (133MHz)
+/*
+ * #######################
+ * ### SET DDR Clk ###
+ * #######################
+ */
+/* CCM: CBMCR - ddr_clk_sel: axi_b (133MHz) */
DATA 4 0x73FD4018 0x000024C0
-# DOUBLE SPI CLK (13MHz->26 MHz Clock)
+/* DOUBLE SPI CLK (13MHz->26 MHz Clock) */
DATA 4 0x73FD4038 0x2010241
-#IOMUXC_SW_PAD_CTL_PAD_CSPI1_MOSI HYS_ENABLE | DRV_MAX | SRE_FAST
+/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_MOSI HYS_ENABLE | DRV_MAX | SRE_FAST */
DATA 4 0x73fa8600 0x00000107
-#IOMUXC_SW_PAD_CTL_PAD_CSPI1_MISO HYS_ENABLE | DRV_MAX | SRE_FAST
+/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_MISO HYS_ENABLE | DRV_MAX | SRE_FAST */
DATA 4 0x73fa8604 0x00000107
-#IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS0 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST
+/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS0 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST */
DATA 4 0x73fa8608 0x00000187
-#IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS1 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST
+/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS1 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST */
DATA 4 0x73fa860c 0x00000187
-#IOMUXC_SW_PAD_CTL_PAD_CSPI1_SCLK HYS_ENABLE | DRV_MAX | SRE_FAST
+/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SCLK HYS_ENABLE | DRV_MAX | SRE_FAST */
DATA 4 0x73fa8614 0x00000107
-#IOMUXC_SW_PAD_CTL_PAD_DI1_PIN11 HYS_ENABLE | DRV_MAX | SRE_FAST (CSPI1_SS2)
+/* IOMUXC_SW_PAD_CTL_PAD_DI1_PIN11 HYS_ENABLE | DRV_MAX | SRE_FAST (CSPI1_SS2) */
DATA 4 0x73fa86a8 0x00000187
-#######################
-### Settings IOMUXC ###
-#######################
-
-# DDR IOMUX configuration
-# Control, Data, Address pads are in their default state: HIGH DS, FAST SR.
-# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK MAX DS
+/*
+ * #######################
+ * ### Settings IOMUXC ###
+ * #######################
+ */
+/*
+ * DDR IOMUX configuration
+ * Control, Data, Address pads are in their default state: HIGH DS, FAST SR.
+ * IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK MAX DS
+ */
DATA 4 0x73fa84b8 0x000000e7
-# PVTC MAX (at GPC, PGR reg)
-#DATA 4 0x73FD8004 0x1fc00000
+/* PVTC MAX (at GPC, PGR reg) */
+/* DATA 4 0x73FD8004 0x1fc00000 */
-#DQM0 DS high slew rate slow
+/* DQM0 DS high slew rate slow */
DATA 4 0x73fa84d4 0x000000e4
-#DQM1 DS high slew rate slow
+/* DQM1 DS high slew rate slow */
DATA 4 0x73fa84d8 0x000000e4
-#DQM2 DS high slew rate slow
+/* DQM2 DS high slew rate slow */
DATA 4 0x73fa84dc 0x000000e4
-#DQM3 DS high slew rate slow
+/* DQM3 DS high slew rate slow */
DATA 4 0x73fa84e0 0x000000e4
-#IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 DS high & SLEW slow
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 DS high & SLEW slow */
DATA 4 0x73fa84bc 0x000000c4
-#IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 DS high & SLEW slow
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 DS high & SLEW slow */
DATA 4 0x73fa84c0 0x000000c4
-#IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 DS high & SLEW slow
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 DS high & SLEW slow */
DATA 4 0x73fa84c4 0x000000c4
-#IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 DS high & SLEW slow
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 DS high & SLEW slow */
DATA 4 0x73fa84c8 0x000000c4
-#DRAM_DATA B0
+/* DRAM_DATA B0 */
DATA 4 0x73fa88a4 0x00000004
-#DRAM_DATA B1
+/* DRAM_DATA B1 */
DATA 4 0x73fa88ac 0x00000004
-#DRAM_DATA B2
+/* DRAM_DATA B2 */
DATA 4 0x73fa88b8 0x00000004
-#DRAM_DATA B3
+/* DRAM_DATA B3 */
DATA 4 0x73fa882c 0x00000004
-#DRAM_DATA B0 slew rate
+/* DRAM_DATA B0 slew rate */
DATA 4 0x73fa8878 0x00000000
-#DRAM_DATA B1 slew rate
+/* DRAM_DATA B1 slew rate */
DATA 4 0x73fa8880 0x00000000
-#DRAM_DATA B2 slew rate
+/* DRAM_DATA B2 slew rate */
DATA 4 0x73fa888c 0x00000000
-#DRAM_DATA B3 slew rate
+/* DRAM_DATA B3 slew rate */
DATA 4 0x73fa889c 0x00000000
-#######################
-### Configure SDRAM ###
-#######################
+/*
+ * #######################
+ * ### Configure SDRAM ###
+ * #######################
+ */
-# Configure CS0
-#######################
+/* Configure CS0 */
+/* ####################### */
-# ESDCTL0: Enable controller
+/* ESDCTL0: Enable controller */
DATA 4 0x83fd9000 0x83220000
-# Init DRAM on CS0
-# ESDSCR: Precharge command
+/* Init DRAM on CS0 /
+/* ESDSCR: Precharge command */
DATA 4 0x83fd9014 0x04008008
-# ESDSCR: Refresh command
+/* ESDSCR: Refresh command */
DATA 4 0x83fd9014 0x00008010
-# ESDSCR: Refresh command
+/* ESDSCR: Refresh command */
DATA 4 0x83fd9014 0x00008010
-# ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8)
+/* ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8) */
DATA 4 0x83fd9014 0x00338018
-# ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51)
+/* ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51) */
DATA 4 0x83fd9014 0x0020801a
-# ESDSCR
+/* ESDSCR */
DATA 4 0x83fd9014 0x00008000
-# ESDSCR: EMR with full Drive strength
-#DATA 4 0x83fd9014 0x0000801a
+/* ESDSCR: EMR with full Drive strength */
+/* DATA 4 0x83fd9014 0x0000801a */
-# ESDCTL0: 14 ROW, 10 COL, 32Bit, SREF=8
+/* ESDCTL0: 14 ROW, 10 COL, 32Bit, SREF=8 */
DATA 4 0x83fd9000 0xC3220000
-# ESDCFG0: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
-# tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
-#DATA 4 0x83fd9004 0xC33574AA
-
-#micron mDDR
-# ESDCFG0: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks
-# tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
-#DATA 4 0x83FD9004 0x101564a8
-
-#hynix mDDR
-# ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks
-# tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
+/*
+ * ESDCFG0: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
+ * tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
+ * DATA 4 0x83fd9004 0xC33574AA
+ */
+/*
+ * micron mDDR
+ * ESDCFG0: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks
+ * tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
+ * DATA 4 0x83FD9004 0x101564a8
+ */
+/*
+ * hynix mDDR
+ * ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks
+ * tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
+ */
DATA 4 0x83FD9004 0x704564a8
-# ESDMISC: AP=10, Bank interleaving on, MIF3 en, RALAT=2
+/* ESDMISC: AP=10, Bank interleaving on, MIF3 en, RALAT=2 */
DATA 4 0x83fd9010 0x000a1700
-# Configure CS1
-#######################
+/* Configure CS1 */
+/* ####################### */
-# ESDCTL1: Enable controller
+/* ESDCTL1: Enable controller */
DATA 4 0x83fd9008 0x83220000
-# Init DRAM on CS1
-# ESDSCR: Precharge command
+/* Init DRAM on CS1 */
+/* ESDSCR: Precharge command */
DATA 4 0x83fd9014 0x0400800c
-# ESDSCR: Refresh command
+/* ESDSCR: Refresh command */
DATA 4 0x83fd9014 0x00008014
-# ESDSCR: Refresh command
+/* ESDSCR: Refresh command */
DATA 4 0x83fd9014 0x00008014
-# ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8)
+/* ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8) */
DATA 4 0x83fd9014 0x0033801c
-# ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51)
+/* ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51) */
DATA 4 0x83fd9014 0x0020801e
-# ESDSCR
+/* ESDSCR */
DATA 4 0x83fd9014 0x00008004
-# ESDCTL1: 14 ROW, 10 COL, 32Bit, SREF=8
+/* ESDCTL1: 14 ROW, 10 COL, 32Bit, SREF=8 */
DATA 4 0x83fd9008 0xC3220000
-
-# ESDCFG1: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
-# tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
-#DATA 4 0x83fd900c 0xC33574AA
-
-#micron mDDR
-# ESDCFG1: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks
-# tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
-#DATA 4 0x83FD900C 0x101564a8
-
-#hynix mDDR
-# ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks
-# tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
+/*
+ * ESDCFG1: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
+ * tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
+ * DATA 4 0x83fd900c 0xC33574AA
+ */
+/*
+ * micron mDDR
+ * ESDCFG1: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks
+ * tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
+ * DATA 4 0x83FD900C 0x101564a8
+ */
+/*
+ * hynix mDDR
+ * ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks
+ * tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
+ */
DATA 4 0x83FD900C 0x704564a8
-# ESDSCR (mDRAM configuration finished)
+/* ESDSCR (mDRAM configuration finished) */
DATA 4 0x83FD9014 0x00000004
-# ESDSCR - clear "configuration request" bit
+/* ESDSCR - clear "configuration request" bit */
DATA 4 0x83fd9014 0x00000000
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH 08/11] mx6: add plugin file for use with imximage.cfg
2012-09-19 0:02 [U-Boot] (no subject) Troy Kisky
` (6 preceding siblings ...)
2012-09-19 0:03 ` [U-Boot] [PATCH 07/11] imximage.cfg: run files through C preprocessor Troy Kisky
@ 2012-09-19 0:03 ` Troy Kisky
2012-09-19 1:40 ` Troy Kisky
2012-09-19 0:03 ` [U-Boot] [PATCH 09/11] mx6qsabrelite: imximage.cfg: use symbols instead of hardcoded constants Troy Kisky
` (3 subsequent siblings)
11 siblings, 1 reply; 430+ messages in thread
From: Troy Kisky @ 2012-09-19 0:03 UTC (permalink / raw)
To: u-boot
The "plugin" command of mkimage can take this
file as an argument.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
arch/arm/cpu/armv7/mx6/Makefile | 5 +-
arch/arm/cpu/armv7/mx6/plugin.S | 141 +++++++++++++++++++++++++++++++++++++++
2 files changed, 145 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/cpu/armv7/mx6/plugin.S
diff --git a/arch/arm/cpu/armv7/mx6/Makefile b/arch/arm/cpu/armv7/mx6/Makefile
index cbce411..b1fce4e 100644
--- a/arch/arm/cpu/armv7/mx6/Makefile
+++ b/arch/arm/cpu/armv7/mx6/Makefile
@@ -33,11 +33,14 @@ SOBJS = lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
-all: $(obj).depend $(LIB)
+all: $(obj).depend $(LIB) plugin.bin
$(LIB): $(OBJS)
$(call cmd_link_o_target, $(OBJS))
+plugin.bin: plugin.o
+ $(OBJCOPY) -O binary --gap-fill 0xff $< $@
+
#########################################################################
# defines $(obj).depend target
diff --git a/arch/arm/cpu/armv7/mx6/plugin.S b/arch/arm/cpu/armv7/mx6/plugin.S
new file mode 100644
index 0000000..e2a45d7
--- /dev/null
+++ b/arch/arm/cpu/armv7/mx6/plugin.S
@@ -0,0 +1,141 @@
+/*
+ * Copyright (C) 2012 Boundary Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+#include <config.h>
+#include <asm/arch/imx-regs.h>
+
+#define HAB_RVT_ENTRY 0x98
+#define HAB_RVT_FAIL_SAFE_VECT 0xbc
+#define HAB_RVT_LOAD_DATA 0xc8
+
+#define HDR_SELF_PTR 0x14
+#define HDR_BOOT_DATA 0x20
+#define HDR_IMAGE_LEN 0x24
+
+/*
+ * plugin_start(void **start, size_t *bytes, UINT32 *ivt_offset)
+ */
+plugin_start:
+/* Save the return address and the function arguments */
+ push {r0-r8, lr}
+
+/* r0-r2 must not be 0 and must be 4 byte aligned */
+ tst r0, r0
+ tstne r1, r1
+ tstne r2, r2
+ mov r3, r0
+ orreq r3, r3, #1
+ orr r3, r3, r1
+ orr r3, r3, r2
+#if 0
+ ldr r0, plugin
+ tst r0, r0
+ orreq r3, r3, #1
+#endif
+
+#define rCPU r2 /* 22 - mx6q, 12 - mx6dl, 2 sololite */
+#define rFlag r3
+#define rIomux r4
+#define rVal0 r5
+#define rVal1 r6
+#define rVal2 r7
+#define rTable r8
+ mov rCPU, #2
+
+ ldr r1, =ANATOP_BASE_ADDR
+ ldr r0, [r1, #0x280]
+ mov r0, r0, LSR #16
+ cmp r0, #0x60
+ movne rCPU, #12
+ ldrne r0, [r1, #0x260]
+ movne r0, r0, LSR #16
+ cmpne r0, #0x61
+ movne rCPU, #22
+
+ mov rVal0, #0
+ mov rVal1, #0
+ mov rVal2, #0
+ ldr rIomux, =IOMUXC_BASE_ADDR
+ adr rTable, mx6_table
+ b 3f
+
+1: movs r0, r1, LSR #30
+ beq 2f
+ mov r1, r1, LSL rCPU
+ movs r1, r1, LSR #32-10
+ addne r1, rIomux, r1, LSL #2
+ cmp r0, #3
+ subne r0, r0, #1
+ orr r1, r1, r0
+
+2: ands r0, r1, #3
+ bic r1, r1, #3
+ ldrne rVal0, [rTable], #4
+ movne rVal1, rVal0
+ movne rVal2, rVal0
+ subnes r0, r0, #1
+ ldrne rVal1, [rTable], #4
+ movne rVal2, rVal1
+ subnes r0, r0, #1
+ ldrne rVal2, [rTable], #4
+
+ mov r0, rVal0
+ cmp rCPU, #12
+ moveq r0, rVal1
+ cmp rCPU, #2
+ moveq r0, rVal2
+ cmp r1, #0
+ strne r0, [r1]
+3: ldr r1, [rTable], #4
+ cmp r1, #0
+ bne 1b
+
+ ands rFlag, rFlag, #3
+ bne 4f /* Branch if not called as plugin */
+/* Align end of table to 64 byte boundary */
+ sub rTable, rTable, #1
+ orr rTable, rTable, #0x3f
+ add rTable, rTable, #1
+ ldr r2, [rTable, #HDR_SELF_PTR]
+ ldr r0, [rTable, #HDR_BOOT_DATA]
+ ldr r1, [rTable, #HDR_IMAGE_LEN]
+ sub rTable, r2, r0
+ mov r2, r0
+ mov r3, r1
+ mov r4, #0
+ push {r0-r4}
+ mov r0, #HAB_RVT_LOAD_DATA
+ ldr r4, [r0]
+ mov r0, sp
+ add r1, sp, #4
+ add r2, sp, #8
+ blx r4
+
+ pop {r4, r5}
+ add sp, sp, #12
+ pop {r0-r3}
+/*
+ * Before returning to ROM, we need to fill the return values arguments
+ * to our function.
+ * plugin_start(void **start, size_t *bytes, UINT32 *ivt_offset)
+ */
+
+ str r4, [r0]
+ str r5, [r1]
+ str rTable, [r2]
+ mov r0, #1
+ pop {r4-r8, pc}
+
+/* Not called as plugin */
+4: popne {r0-r8, lr}
+ mov r0, #HAB_RVT_ENTRY
+ ldr lr, [r0]
+ blx lr
+ mov r0, #HAB_RVT_FAIL_SAFE_VECT
+ ldr lr, [r0]
+ blx lr
+
+ .ltorg
+mx6_table:
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH 09/11] mx6qsabrelite: imximage.cfg: use symbols instead of hardcoded constants
2012-09-19 0:02 [U-Boot] (no subject) Troy Kisky
` (7 preceding siblings ...)
2012-09-19 0:03 ` [U-Boot] [PATCH 08/11] mx6: add plugin file for use with imximage.cfg Troy Kisky
@ 2012-09-19 0:03 ` Troy Kisky
2012-09-19 0:03 ` [U-Boot] [PATCH 10/11] mx6qsabrelite: imximage.cfg: allow plugin to work Troy Kisky
` (2 subsequent siblings)
11 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-09-19 0:03 UTC (permalink / raw)
To: u-boot
This allows us to generate plugin data or
DCD rom style data simply by defining USE_PLUGIN
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
arch/arm/include/asm/arch-mx6/imx-mkimage.h | 163 +++++++++++++++++
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 248 +++++++++++++-------------
2 files changed, 290 insertions(+), 121 deletions(-)
create mode 100644 arch/arm/include/asm/arch-mx6/imx-mkimage.h
diff --git a/arch/arm/include/asm/arch-mx6/imx-mkimage.h b/arch/arm/include/asm/arch-mx6/imx-mkimage.h
new file mode 100644
index 0000000..e61d5b6
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/imx-mkimage.h
@@ -0,0 +1,163 @@
+/*
+ * Copyright (C) 2012 Boundary Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+#ifndef __ASM_ARCH_IMX_MKIMAGE_H__
+#define __ASM_ARCH_IMX_MKIMAGE_H__
+
+/* mx6 duallite and solo have same offsets */
+/*
+ * Bits 31:30 :
+ * 0 : 29:2 absolute address, 1:0 # of data values,
+ * followed by 0-3 data values in (mx6q, mx6dl, mx6_sololite)
+ * 0 means repeat last data value
+ * 1 : iomuxc relative address, 9:0 mx6q offset, 19:10 mx6dl offset,
+ * 29:20 mx6_sololite offset, 0 offset means skip if this processor
+ * previous data repeated
+ * 2 : same as 1, but single data value follows
+ * 3 : same as 1. but 3 data values follow
+ */
+#define MA(mx6q, mx6dl, mx6solo_lite) ((mx6q / 4 & 0x3ff) | \
+ ((mx6dl / 4 & 0x3ff) * 0x400) | \
+ ((mx6solo_lite / 4 & 0x3ff) * 0x100000))
+
+#define IOM_DRAM_DQM0 MA(0x5ac, 0x470, 0x0)
+#define IOM_DRAM_DQM1 MA(0x5b4, 0x474, 0x0)
+#define IOM_DRAM_DQM2 MA(0x528, 0x478, 0x0)
+#define IOM_DRAM_DQM3 MA(0x520, 0x47c, 0x0)
+#define IOM_DRAM_DQM4 MA(0x514, 0x480, 0x0)
+#define IOM_DRAM_DQM5 MA(0x510, 0x484, 0x0)
+#define IOM_DRAM_DQM6 MA(0x5bc, 0x488, 0x0)
+#define IOM_DRAM_DQM7 MA(0x5c4, 0x48c, 0x0)
+
+#define IOM_DRAM_CAS MA(0x56c, 0x464, 0x0)
+#define IOM_DRAM_RAS MA(0x578, 0x490, 0x0)
+#define IOM_DRAM_RESET MA(0x57c, 0x494, 0x0)
+#define IOM_DRAM_SDCLK_0 MA(0x588, 0x4ac, 0x0)
+#define IOM_DRAM_SDCLK_1 MA(0x594, 0x4b0, 0x0)
+#define IOM_DRAM_SDBA2 MA(0x58c, 0x4a0, 0x0)
+#define IOM_DRAM_SDCKE0 MA(0x590, 0x4a4, 0x0)
+#define IOM_DRAM_SDCKE1 MA(0x598, 0x4a8, 0x0)
+#define IOM_DRAM_SDODT0 MA(0x59c, 0x4b4, 0x0)
+#define IOM_DRAM_SDODT1 MA(0x5a0, 0x4b8, 0x0)
+
+#define IOM_DRAM_SDQS0 MA(0x5a8, 0x4bc, 0x0)
+#define IOM_DRAM_SDQS1 MA(0x5b0, 0x4c0, 0x0)
+#define IOM_DRAM_SDQS2 MA(0x524, 0x4c4, 0x0)
+#define IOM_DRAM_SDQS3 MA(0x51c, 0x4c8, 0x0)
+#define IOM_DRAM_SDQS4 MA(0x518, 0x4cc, 0x0)
+#define IOM_DRAM_SDQS5 MA(0x50c, 0x4d0, 0x0)
+#define IOM_DRAM_SDQS6 MA(0x5b8, 0x4d4, 0x0)
+#define IOM_DRAM_SDQS7 MA(0x5c0, 0x4d8, 0x0)
+
+#define IOM_GRP_B0DS MA(0x784, 0x764, 0x0)
+#define IOM_GRP_B1DS MA(0x788, 0x770, 0x0)
+#define IOM_GRP_B2DS MA(0x794, 0x778, 0x0)
+#define IOM_GRP_B3DS MA(0x79c, 0x77c, 0x0)
+#define IOM_GRP_B4DS MA(0x7a0, 0x780, 0x0)
+#define IOM_GRP_B5DS MA(0x7a4, 0x784, 0x0)
+#define IOM_GRP_B6DS MA(0x7a8, 0x78c, 0x0)
+#define IOM_GRP_B7DS MA(0x748, 0x748, 0x0)
+#define IOM_GRP_ADDDS MA(0x74c, 0x74c, 0x0)
+#define IOM_DDRMODE_CTL MA(0x750, 0x750, 0x0)
+#define IOM_GRP_DDRPKE MA(0x758, 0x754, 0x0)
+#define IOM_GRP_DDRMODE MA(0x774, 0x760, 0x0)
+#define IOM_GRP_CTLDS MA(0x78c, 0x76c, 0x0)
+#define IOM_GRP_DDR_TYPE MA(0x798, 0x774, 0x0)
+
+#define MMDC_P0 0x021b0000
+#define MMDC_P1 0x021b4000
+#define IOMUXC_BASE_ADDR 0x020e0000
+#define CCM_BASE 0x020C4000
+#define IRAM_FREE_START 0x00907000
+
+#define IOMUXC_GPR4 (IOMUXC_BASE_ADDR + 0x010)
+#define IOMUXC_GPR6 (IOMUXC_BASE_ADDR + 0x018)
+#define IOMUXC_GPR7 (IOMUXC_BASE_ADDR + 0x01c)
+
+#define MMDC_MDCTL 0x000
+#define MMDC_MDPDC 0x004
+#define MMDC_MDOTC 0x008
+#define MMDC_MDCFG0 0x00c
+#define MMDC_MDCFG1 0x010
+#define MMDC_MDCFG2 0x014
+#define MMDC_MDMISC 0x018
+#define MMDC_MDSCR 0x01c
+#define MMDC_MDREF 0x020
+#define MMDC_MDRWD 0x02c
+#define MMDC_MDOR 0x030
+#define MMDC_MDASP 0x040
+#define MMDC_MAPSR 0x404
+#define MMDC_MPZQHWCTRL 0x800
+#define MMDC_MPWLDECTRL0 0x80c
+#define MMDC_MPWLDECTRL1 0x810
+#define MMDC_MPODTCTRL 0x818
+#define MMDC_MPRDDQBY0DL 0x81c
+#define MMDC_MPRDDQBY1DL 0x820
+#define MMDC_MPRDDQBY2DL 0x824
+#define MMDC_MPRDDQBY3DL 0x828
+#define MMDC_MPDGCTRL0 0x83c
+#define MMDC_MPDGCTRL1 0x840
+#define MMDC_MPRDDLCTL 0x848
+#define MMDC_MPWRDLCTL 0x850
+#define MMDC_MPMUR0 0x8b8
+
+#define CCM_CCGR0 0x068
+#define CCM_CCGR1 0x06c
+#define CCM_CCGR2 0x070
+#define CCM_CCGR3 0x074
+#define CCM_CCGR4 0x078
+#define CCM_CCGR5 0x07c
+#define CCM_CCGR6 0x080
+
+#ifdef USE_PLUGIN
+#define IOMUX_ENTRY(addr, args...) iomux_entry addr, args
+#define IOMUX_ENTRY1 IOMUX_ENTRY
+#define IOMUX_ENTRY2 IOMUX_ENTRY
+#define IOMUX_ENTRY3 IOMUX_ENTRY
+#define WRITE_ENTRY(addr, args...) write_entry addr, args
+#define WRITE_ENTRY1 WRITE_ENTRY
+#define WRITE_ENTRY2 WRITE_ENTRY
+#define WRITE_ENTRY3 WRITE_ENTRY
+#else
+#ifdef FOR_MX6Q
+#define IOMUX_ENTRY1(addr, mx6q) DATA 4, \
+ (IOMUXC_BASE_ADDR+(((addr) & 0x3ff) * 4)), mx6q
+#define IOMUX_ENTRY2(addr, mx6q, mx6dl) DATA 4, \
+ (IOMUXC_BASE_ADDR+(((addr) & 0x3ff) * 4)), mx6q
+#define IOMUX_ENTRY3(addr, mx6q, mx6dl, mx6sl) DATA 4, \
+ (IOMUXC_BASE_ADDR+(((addr) & 0x3ff) * 4)), mx6q
+#define WRITE_ENTRY1(addr, mx6q) DATA 4, addr, mx6q
+#define WRITE_ENTRY2(addr, mx6q, mx6dl) DATA 4, addr, mx6q
+#define WRITE_ENTRY3(addr, mx6q, mx6dl, mx6sl) DATA 4, addr, mx6q
+#else
+#ifdef FOR_MX6DL
+#define IOMUX_ENTRY1(addr, mx6q) DATA 4, \
+ (IOMUXC_BASE_ADDR+(((addr) / 0x400 & 0x3ff) * 4)), mx6q
+#define IOMUX_ENTRY2(addr, mx6q, mx6dl) DATA 4, \
+ (IOMUXC_BASE_ADDR+(((addr) / 0x400 & 0x3ff) * 4)), mx6dl
+#define IOMUX_ENTRY3(addr, mx6q, mx6dl, mx6sl) DATA 4, \
+ (IOMUXC_BASE_ADDR+(((addr) / 0x400 & 0x3ff) * 4)), mx6dl
+#define WRITE_ENTRY1(addr, mx6q) DATA 4, addr, mx6q
+#define WRITE_ENTRY2(addr, mx6q, mx6dl) DATA 4, addr, mx6dl
+#define WRITE_ENTRY3(addr, mx6q, mx6dl, mx6sl) DATA 4, addr, mx6dl
+#else
+#ifdef FOR_MX6SL
+#define IOMUX_ENTRY1(addr, mx6q) DATA 4, \
+ (IOMUXC_BASE_ADDR+(((addr) / 0x100000 & 0x3ff) * 4)), mx6q
+#define IOMUX_ENTRY2(addr, mx6q, mx6dl) DATA 4, \
+ (IOMUXC_BASE_ADDR+(((addr) / 0x100000 & 0x3ff) * 4)), mx6dl
+#define IOMUX_ENTRY3(addr, mx6q, mx6dl, mx6sl) DATA 4, \
+ (IOMUXC_BASE_ADDR+(((addr) / 0x100000 & 0x3ff) * 4)), mx6sl
+#define WRITE_ENTRY1(addr, mx6q) DATA 4, addr, mx6q
+#define WRITE_ENTRY2(addr, mx6q, mx6dl) DATA 4, addr, mx6dl
+#define WRITE_ENTRY3(addr, mx6q, mx6dl, mx6sl) DATA 4, addr, mx6sl
+#else
+#error "Please select cpu"
+#endif
+#endif
+#endif
+#endif
+
+#endif
diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
index c86cd40..a95831f 100644
--- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
@@ -25,6 +25,9 @@
*
* The syntax is taken as close as possible with the kwbimage
*/
+#define FOR_MX6Q
+
+#include <asm/arch/imx-mkimage.h>
/* image version */
IMAGE_VERSION 2
@@ -35,6 +38,9 @@ IMAGE_VERSION 2
*/
BOOT_FROM sd
+#ifdef USE_PLUGIN
+ plugin IRAM_FREE_START+0x42c arch/arm/cpu/armv7/mx6/plugin.bin
+#endif
/*
* Device Configuration Data (DCD)
*
@@ -46,129 +52,129 @@ BOOT_FROM sd
* Address absolute address of the register
* value value to be stored in the register
*/
-DATA 4 0x020e05a8 0x00000030
-DATA 4 0x020e05b0 0x00000030
-DATA 4 0x020e0524 0x00000030
-DATA 4 0x020e051c 0x00000030
-
-DATA 4 0x020e0518 0x00000030
-DATA 4 0x020e050c 0x00000030
-DATA 4 0x020e05b8 0x00000030
-DATA 4 0x020e05c0 0x00000030
-
-DATA 4 0x020e05ac 0x00020030
-DATA 4 0x020e05b4 0x00020030
-DATA 4 0x020e0528 0x00020030
-DATA 4 0x020e0520 0x00020030
-
-DATA 4 0x020e0514 0x00020030
-DATA 4 0x020e0510 0x00020030
-DATA 4 0x020e05bc 0x00020030
-DATA 4 0x020e05c4 0x00020030
-
-DATA 4 0x020e056c 0x00020030
-DATA 4 0x020e0578 0x00020030
-DATA 4 0x020e0588 0x00020030
-DATA 4 0x020e0594 0x00020030
-
-DATA 4 0x020e057c 0x00020030
-DATA 4 0x020e0590 0x00003000
-DATA 4 0x020e0598 0x00003000
-DATA 4 0x020e058c 0x00000000
-
-DATA 4 0x020e059c 0x00003030
-DATA 4 0x020e05a0 0x00003030
-DATA 4 0x020e0784 0x00000030
-DATA 4 0x020e0788 0x00000030
-
-DATA 4 0x020e0794 0x00000030
-DATA 4 0x020e079c 0x00000030
-DATA 4 0x020e07a0 0x00000030
-DATA 4 0x020e07a4 0x00000030
-
-DATA 4 0x020e07a8 0x00000030
-DATA 4 0x020e0748 0x00000030
-DATA 4 0x020e074c 0x00000030
-DATA 4 0x020e0750 0x00020000
-
-DATA 4 0x020e0758 0x00000000
-DATA 4 0x020e0774 0x00020000
-DATA 4 0x020e078c 0x00000030
-DATA 4 0x020e0798 0x000C0000
-
-DATA 4 0x021b081c 0x33333333
-DATA 4 0x021b0820 0x33333333
-DATA 4 0x021b0824 0x33333333
-DATA 4 0x021b0828 0x33333333
-
-DATA 4 0x021b481c 0x33333333
-DATA 4 0x021b4820 0x33333333
-DATA 4 0x021b4824 0x33333333
-DATA 4 0x021b4828 0x33333333
-
-DATA 4 0x021b0018 0x00081740
-
-DATA 4 0x021b001c 0x00008000
-DATA 4 0x021b000c 0x555A7975
-DATA 4 0x021b0010 0xFF538E64
-DATA 4 0x021b0014 0x01FF00DB
-DATA 4 0x021b002c 0x000026D2
-
-DATA 4 0x021b0030 0x005B0E21
-DATA 4 0x021b0008 0x09444040
-DATA 4 0x021b0004 0x00025576
-DATA 4 0x021b0040 0x00000027
-DATA 4 0x021b0000 0x831A0000
-
-DATA 4 0x021b001c 0x04088032
-DATA 4 0x021b001c 0x0408803A
-DATA 4 0x021b001c 0x00008033
-DATA 4 0x021b001c 0x0000803B
-DATA 4 0x021b001c 0x00428031
-DATA 4 0x021b001c 0x00428039
-DATA 4 0x021b001c 0x09408030
-DATA 4 0x021b001c 0x09408038
-
-DATA 4 0x021b001c 0x04008040
-DATA 4 0x021b001c 0x04008048
-DATA 4 0x021b0800 0xA1380003
-DATA 4 0x021b4800 0xA1380003
-DATA 4 0x021b0020 0x00005800
-DATA 4 0x021b0818 0x00022227
-DATA 4 0x021b4818 0x00022227
-
-DATA 4 0x021b083c 0x434B0350
-DATA 4 0x021b0840 0x034C0359
-DATA 4 0x021b483c 0x434B0350
-DATA 4 0x021b4840 0x03650348
-DATA 4 0x021b0848 0x4436383B
-DATA 4 0x021b4848 0x39393341
-DATA 4 0x021b0850 0x35373933
-DATA 4 0x021b4850 0x48254A36
-
-DATA 4 0x021b080c 0x001F001F
-DATA 4 0x021b0810 0x001F001F
-
-DATA 4 0x021b480c 0x00440044
-DATA 4 0x021b4810 0x00440044
-
-DATA 4 0x021b08b8 0x00000800
-DATA 4 0x021b48b8 0x00000800
-
-DATA 4 0x021b001c 0x00000000
-DATA 4 0x021b0404 0x00011006
+IOMUX_ENTRY1(IOM_DRAM_SDQS0, 0x00000030)
+IOMUX_ENTRY1(IOM_DRAM_SDQS1, 0x00000030)
+IOMUX_ENTRY1(IOM_DRAM_SDQS2, 0x00000030)
+IOMUX_ENTRY1(IOM_DRAM_SDQS3, 0x00000030)
+
+IOMUX_ENTRY1(IOM_DRAM_SDQS4, 0x00000030)
+IOMUX_ENTRY1(IOM_DRAM_SDQS5, 0x00000030)
+IOMUX_ENTRY1(IOM_DRAM_SDQS6, 0x00000030)
+IOMUX_ENTRY1(IOM_DRAM_SDQS7, 0x00000030)
+
+IOMUX_ENTRY1(IOM_DRAM_DQM0, 0x00020030)
+IOMUX_ENTRY1(IOM_DRAM_DQM1, 0x00020030)
+IOMUX_ENTRY1(IOM_DRAM_DQM2, 0x00020030)
+IOMUX_ENTRY1(IOM_DRAM_DQM3, 0x00020030)
+
+IOMUX_ENTRY1(IOM_DRAM_DQM4, 0x00020030)
+IOMUX_ENTRY1(IOM_DRAM_DQM5, 0x00020030)
+IOMUX_ENTRY1(IOM_DRAM_DQM6, 0x00020030)
+IOMUX_ENTRY1(IOM_DRAM_DQM7, 0x00020030)
+
+IOMUX_ENTRY1(IOM_DRAM_CAS, 0x00020030)
+IOMUX_ENTRY1(IOM_DRAM_RAS, 0x00020030)
+IOMUX_ENTRY1(IOM_DRAM_SDCLK_0, 0x00020030)
+IOMUX_ENTRY1(IOM_DRAM_SDCLK_1, 0x00020030)
+
+IOMUX_ENTRY1(IOM_DRAM_RESET, 0x00020030)
+IOMUX_ENTRY1(IOM_DRAM_SDCKE0, 0x00003000)
+IOMUX_ENTRY1(IOM_DRAM_SDCKE1, 0x00003000)
+IOMUX_ENTRY1(IOM_DRAM_SDBA2, 0x00000000)
+
+IOMUX_ENTRY1(IOM_DRAM_SDODT0, 0x00003030)
+IOMUX_ENTRY1(IOM_DRAM_SDODT1, 0x00003030)
+IOMUX_ENTRY1(IOM_GRP_B0DS, 0x00000030)
+IOMUX_ENTRY1(IOM_GRP_B1DS, 0x00000030)
+
+IOMUX_ENTRY1(IOM_GRP_B2DS, 0x00000030)
+IOMUX_ENTRY1(IOM_GRP_B3DS, 0x00000030)
+IOMUX_ENTRY1(IOM_GRP_B4DS, 0x00000030)
+IOMUX_ENTRY1(IOM_GRP_B5DS, 0x00000030)
+
+IOMUX_ENTRY1(IOM_GRP_B6DS, 0x00000030)
+IOMUX_ENTRY1(IOM_GRP_B7DS, 0x00000030)
+IOMUX_ENTRY1(IOM_GRP_ADDDS, 0x00000030)
+IOMUX_ENTRY1(IOM_DDRMODE_CTL, 0x00020000)
+
+IOMUX_ENTRY1(IOM_GRP_DDRPKE, 0x00000000)
+IOMUX_ENTRY1(IOM_GRP_DDRMODE, 0x00020000)
+IOMUX_ENTRY1(IOM_GRP_CTLDS, 0x00000030)
+IOMUX_ENTRY1(IOM_GRP_DDR_TYPE, 0x000C0000)
+
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPRDDQBY0DL, 0x33333333)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPRDDQBY1DL, 0x33333333)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPRDDQBY2DL, 0x33333333)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPRDDQBY3DL, 0x33333333)
+
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPRDDQBY0DL, 0x33333333)
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPRDDQBY1DL, 0x33333333)
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPRDDQBY2DL, 0x33333333)
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPRDDQBY3DL, 0x33333333)
+
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDMISC, 0x00081740)
+
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x00008000)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDCFG0, 0x555A7975)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDCFG1, 0xFF538E64)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDCFG2, 0x01FF00DB)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDRWD, 0x000026D2)
+
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDOR, 0x005B0E21)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDOTC, 0x09444040)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDPDC, 0x00025576)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDASP, 0x00000027)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDCTL, 0x831A0000)
+
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x04088032)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x0408803A)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x00008033)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x0000803B)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x00428031)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x00428039)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x09408030)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x09408038)
+
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x04008040)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x04008048)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPZQHWCTRL, 0xA1380003)
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPZQHWCTRL, 0xA1380003)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDREF, 0x00005800)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPODTCTRL, 0x00022227)
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPODTCTRL, 0x00022227)
+
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPDGCTRL0, 0x434B0350)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPDGCTRL1, 0x034C0359)
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPDGCTRL0, 0x434B0350)
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPDGCTRL1, 0x03650348)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPRDDLCTL, 0x4436383B)
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPRDDLCTL, 0x39393341)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPWRDLCTL, 0x35373933)
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPWRDLCTL, 0x48254A36)
+
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPWLDECTRL0, 0x001F001F)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPWLDECTRL1, 0x001F001F)
+
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPWLDECTRL0, 0x00440044)
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPWLDECTRL1, 0x00440044)
+
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPMUR0, 0x00000800)
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPMUR0, 0x00000800)
+
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x00000000)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MAPSR, 0x00011006)
/* set the default clock gate to save power */
-DATA 4 0x020c4068 0x00C03F3F
-DATA 4 0x020c406c 0x0030FC03
-DATA 4 0x020c4070 0x0FFFC000
-DATA 4 0x020c4074 0x3FF00000
-DATA 4 0x020c4078 0x00FFF300
-DATA 4 0x020c407c 0x0F0000C3
-DATA 4 0x020c4080 0x000003FF
+WRITE_ENTRY1(CCM_BASE + CCM_CCGR0, 0x00C03F3F)
+WRITE_ENTRY1(CCM_BASE + CCM_CCGR1, 0x0030FC03)
+WRITE_ENTRY1(CCM_BASE + CCM_CCGR2, 0x0FFFC000)
+WRITE_ENTRY1(CCM_BASE + CCM_CCGR3, 0x3FF00000)
+WRITE_ENTRY1(CCM_BASE + CCM_CCGR4, 0x00FFF300)
+WRITE_ENTRY1(CCM_BASE + CCM_CCGR5, 0x0F0000C3)
+WRITE_ENTRY1(CCM_BASE + CCM_CCGR6, 0x000003FF)
/* enable AXI cache for VDOA/VPU/IPU */
-DATA 4 0x020e0010 0xF00000CF
+WRITE_ENTRY1(IOMUXC_GPR4, 0xF00000CF)
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-DATA 4 0x020e0018 0x007F007F
-DATA 4 0x020e001c 0x007F007F
+WRITE_ENTRY1(IOMUXC_GPR6, 0x007F007F)
+WRITE_ENTRY1(IOMUXC_GPR7, 0x007F007F)
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH 10/11] mx6qsabrelite: imximage.cfg: allow plugin to work
2012-09-19 0:02 [U-Boot] (no subject) Troy Kisky
` (8 preceding siblings ...)
2012-09-19 0:03 ` [U-Boot] [PATCH 09/11] mx6qsabrelite: imximage.cfg: use symbols instead of hardcoded constants Troy Kisky
@ 2012-09-19 0:03 ` Troy Kisky
2012-09-19 0:03 ` [U-Boot] [PATCH 11/11] RFC mx6qsabrelite: imximage.cfg: enable plugin mode Troy Kisky
2012-09-22 2:38 ` [U-Boot] [PATCH V2 00/21] Add mx6solo/mx6duallite support Troy Kisky
11 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-09-19 0:03 UTC (permalink / raw)
To: u-boot
Enabling plugin mode seems to require this additional
memory write for ddr3 initialization.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 2 ++
1 file changed, 2 insertions(+)
diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
index a95831f..eea8d3a 100644
--- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
@@ -111,6 +111,8 @@ WRITE_ENTRY1(MMDC_P1 + MMDC_MPRDDQBY0DL, 0x33333333)
WRITE_ENTRY1(MMDC_P1 + MMDC_MPRDDQBY1DL, 0x33333333)
WRITE_ENTRY1(MMDC_P1 + MMDC_MPRDDQBY2DL, 0x33333333)
WRITE_ENTRY1(MMDC_P1 + MMDC_MPRDDQBY3DL, 0x33333333)
+/* MDPDC - CKE pulse width = 3 cycles. CKSRE = 6 cycles, CKSRX = 6 cycles */
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDPDC, 0x00020036)
WRITE_ENTRY1(MMDC_P0 + MMDC_MDMISC, 0x00081740)
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH 11/11] RFC mx6qsabrelite: imximage.cfg: enable plugin mode
2012-09-19 0:02 [U-Boot] (no subject) Troy Kisky
` (9 preceding siblings ...)
2012-09-19 0:03 ` [U-Boot] [PATCH 10/11] mx6qsabrelite: imximage.cfg: allow plugin to work Troy Kisky
@ 2012-09-19 0:03 ` Troy Kisky
2012-09-19 1:52 ` Troy Kisky
2012-09-22 2:38 ` [U-Boot] [PATCH V2 00/21] Add mx6solo/mx6duallite support Troy Kisky
11 siblings, 1 reply; 430+ messages in thread
From: Troy Kisky @ 2012-09-19 0:03 UTC (permalink / raw)
To: u-boot
Don't apply this patch yet, because although u-boot
will boot, Linux won't!!!!
The other CPU's won't come online, and L2 cache
initialization crashes
Calibrating delay loop... 1581.05 BogoMIPS (lpj=7905280)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 512
Initializing cgroup subsys cpuacct
CPU: Testing write buffer coherency: ok
hw perfevents: enabled with ARMv7 Cortex-A9 PMU driver, 7 counters available
CPU1: failed to come online
CPU2: failed to come online
CPU3: failed to come online
Brought up 1 CPUs
SMP: Total of 1 processors activated (1581.05 BogoMIPS).
print_constraints: dummy:
NET: Registered protocol family 16
print_constraints: vddpu: 725 <--> 1300 mV at 1100 mV fast normal
print_constraints: vddcore: 725 <--> 1300 mV at 1100 mV fast normal
print_constraints: vddsoc: 725 <--> 1300 mV at 1200 mV fast normal
print_constraints: vdd2p5: 2000 <--> 2775 mV at 2400 mV fast normal
print_constraints: vdd1p1: 800 <--> 1400 mV at 1100 mV fast normal
print_constraints: vdd3p0: 2800 <--> 3150 mV at 3000 mV fast normal
------------ Board type Nitrogen6X/W
hw-breakpoint: found 6 breakpoint and 1 watchpoint registers.
hw-breakpoint: 1 breakpoint(s) reserved for watchpoint single-step.
hw-breakpoint: maximum watchpoint size is 4 bytes.
Unhandled fault: imprecise external abort (0x1c06) at 0x1d4c07b4
Internal error: : 1c06 [#1] PREEMPT SMP
Modules linked in:
CPU: 0 Not tainted (3.0.35-1968-gd3f7f36-03060-ga3844c7 #1)
PC is at mxc_init_l2x0+0x50/0x120
Anyone have a clue?
The same thing under freescale's imx-android-r13.3
works fine. Only mainline doesn't work
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
index eea8d3a..2af4265 100644
--- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
@@ -26,7 +26,7 @@
* The syntax is taken as close as possible with the kwbimage
*/
#define FOR_MX6Q
-
+#define USE_PLUGIN
#include <asm/arch/imx-mkimage.h>
/* image version */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH 08/11] mx6: add plugin file for use with imximage.cfg
2012-09-19 0:03 ` [U-Boot] [PATCH 08/11] mx6: add plugin file for use with imximage.cfg Troy Kisky
@ 2012-09-19 1:40 ` Troy Kisky
0 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-09-19 1:40 UTC (permalink / raw)
To: u-boot
On 9/18/2012 5:03 PM, Troy Kisky wrote:
> The "plugin" command of mkimage can take this
> file as an argument.
>
> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
> ---
> arch/arm/cpu/armv7/mx6/Makefile | 5 +-
> arch/arm/cpu/armv7/mx6/plugin.S | 141 +++++++++++++++++++++++++++++++++++++++
> 2 files changed, 145 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/cpu/armv7/mx6/plugin.S
>
>
Ok, I found the issue with Linux not booting, and I'll need to change
this patch to add
disabling of L2 cache and a cache clean.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH 11/11] RFC mx6qsabrelite: imximage.cfg: enable plugin mode
2012-09-19 0:03 ` [U-Boot] [PATCH 11/11] RFC mx6qsabrelite: imximage.cfg: enable plugin mode Troy Kisky
@ 2012-09-19 1:52 ` Troy Kisky
0 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-09-19 1:52 UTC (permalink / raw)
To: u-boot
On 9/18/2012 5:03 PM, Troy Kisky wrote:
> Don't apply this patch yet, because although u-boot
> will boot, Linux won't!!!!
>
> The other CPU's won't come online, and L2 cache
> initialization crashes
>
> Calibrating delay loop... 1581.05 BogoMIPS (lpj=7905280)
> pid_max: default: 32768 minimum: 301
> Mount-cache hash table entries: 512
> Initializing cgroup subsys cpuacct
> CPU: Testing write buffer coherency: ok
> hw perfevents: enabled with ARMv7 Cortex-A9 PMU driver, 7 counters available
> CPU1: failed to come online
> CPU2: failed to come online
> CPU3: failed to come online
> Brought up 1 CPUs
> SMP: Total of 1 processors activated (1581.05 BogoMIPS).
> print_constraints: dummy:
> NET: Registered protocol family 16
> print_constraints: vddpu: 725 <--> 1300 mV at 1100 mV fast normal
> print_constraints: vddcore: 725 <--> 1300 mV at 1100 mV fast normal
> print_constraints: vddsoc: 725 <--> 1300 mV at 1200 mV fast normal
> print_constraints: vdd2p5: 2000 <--> 2775 mV at 2400 mV fast normal
> print_constraints: vdd1p1: 800 <--> 1400 mV at 1100 mV fast normal
> print_constraints: vdd3p0: 2800 <--> 3150 mV at 3000 mV fast normal
> ------------ Board type Nitrogen6X/W
> hw-breakpoint: found 6 breakpoint and 1 watchpoint registers.
> hw-breakpoint: 1 breakpoint(s) reserved for watchpoint single-step.
> hw-breakpoint: maximum watchpoint size is 4 bytes.
> Unhandled fault: imprecise external abort (0x1c06) at 0x1d4c07b4
> Internal error: : 1c06 [#1] PREEMPT SMP
> Modules linked in:
> CPU: 0 Not tainted (3.0.35-1968-gd3f7f36-03060-ga3844c7 #1)
> PC is at mxc_init_l2x0+0x50/0x120
>
> Anyone have a clue?
>
> The same thing under freescale's imx-android-r13.3
> works fine. Only mainline doesn't work
>
> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
> ---
> board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
> index eea8d3a..2af4265 100644
> --- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
> +++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
> @@ -26,7 +26,7 @@
> * The syntax is taken as close as possible with the kwbimage
> */
> #define FOR_MX6Q
> -
> +#define USE_PLUGIN
> #include <asm/arch/imx-mkimage.h>
>
> /* image version */
Never mind. I found the issue. I need to disable the L2 cache before
returning from plugin.
Thanks
Troy
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 00/21] Add mx6solo/mx6duallite support
2012-09-19 0:02 [U-Boot] (no subject) Troy Kisky
` (10 preceding siblings ...)
2012-09-19 0:03 ` [U-Boot] [PATCH 11/11] RFC mx6qsabrelite: imximage.cfg: enable plugin mode Troy Kisky
@ 2012-09-22 2:38 ` Troy Kisky
2012-09-22 2:38 ` [U-Boot] [PATCH V2 01/21] imximage: make header variable length Troy Kisky
` (22 more replies)
11 siblings, 23 replies; 430+ messages in thread
From: Troy Kisky @ 2012-09-22 2:38 UTC (permalink / raw)
To: u-boot
After this series the same binary will run on a
Saberlite board using any of the pin compatible processors
mx6 quad, mx6 duallite, or mx6 solo. This is accomplished
using a plugin and a table built by mkimage.
I made it easy to revert back to the current method by
removing
#define USE_PLUGIN
from imximage.cfg file so that it is easy to
support a single processor.
In that case, you should also add
#define FOR_MX6Q/FOR_MX6DL/FOR_MX6SOLO/FOR_MX6SOLOLITE
to select which processor you are building for.
Patches 1-5 of the series are unchanged from version 1.
Troy Kisky (21):
imximage: make header variable length
imximage: check dcd_len as entries added
imximage: enable word writes for version2 header
imximage: cleanup parsing
imximage: add expression evaluation
imximage: add plugin commands
imximage.cfg: run files through C preprocessor
mx6: add plugin file for use with imximage.cfg
mx6q_4x_mt41j128.cfg: use symbols instead of hardcoded constants
mx6q_4x_mt41j128.cfg: allow plugin to work
mx6q_4x_mt41j128.cfg: enable plugin mode
mx6q_4x_mt41j128.cfg: add comments
mx6q_4x_mt41j128.cfg: use ddr3 mode for reset
mx6q_4x_mt41j128.cfg: skip initiailizing non-existent memory
mx6q_4x_mt41j128.cfg: reorder for more efficient storage
mx6q_4x_mt41j128.cfg: force ZQ calibration
mx6: soc: add get_cpu_type
arch-mx6: add mx6dl_pins.h
mx6qsabrelite: add support for mx6 solo/duallite
mx6q_4x_mt41j128.cfg: add mx6 solo/duallite support
mx6qsabrelite: change CONFIG_SYS_PROMPT
Makefile | 3 +-
arch/arm/cpu/armv7/mx6/Makefile | 5 +-
arch/arm/cpu/armv7/mx6/plugin.S | 164 +++++
arch/arm/cpu/armv7/mx6/soc.c | 26 +
arch/arm/include/asm/arch-mx6/imx-mkimage.h | 177 +++++
arch/arm/include/asm/arch-mx6/imx-regs.h | 1 +
arch/arm/include/asm/arch-mx6/mx6dl_pins.h | 118 +++
arch/arm/include/asm/arch-mx6/sys_proto.h | 6 +
board/esg/ima3-mx53/imximage.cfg | 120 +--
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 433 ++++++-----
board/freescale/mx25pdk/imximage.cfg | 77 +-
board/freescale/mx51evk/imximage.cfg | 114 +--
board/freescale/mx53ard/imximage_dd3.cfg | 83 ++-
board/freescale/mx53evk/imximage.cfg | 86 +--
board/freescale/mx53loco/imximage.cfg | 83 ++-
board/freescale/mx53smd/imximage.cfg | 83 ++-
board/freescale/mx6qarm2/imximage.cfg | 88 +--
board/freescale/mx6qsabrelite/mx6qsabrelite.c | 231 ++----
board/freescale/mx6qsabrelite/pads.h | 172 +++++
board/genesi/mx51_efikamx/imximage_mx.cfg | 132 ++--
board/genesi/mx51_efikamx/imximage_sb.cfg | 126 ++--
board/ttcontrol/vision2/imximage_hynix.cfg | 295 ++++----
include/configs/mx6qsabrelite.h | 2 +-
tools/imximage.c | 967 ++++++++++++++++++-------
tools/imximage.h | 45 +-
25 files changed, 2389 insertions(+), 1248 deletions(-)
create mode 100644 arch/arm/cpu/armv7/mx6/plugin.S
create mode 100644 arch/arm/include/asm/arch-mx6/imx-mkimage.h
create mode 100644 arch/arm/include/asm/arch-mx6/mx6dl_pins.h
create mode 100644 board/freescale/mx6qsabrelite/pads.h
--
1.7.9.5
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 01/21] imximage: make header variable length
2012-09-22 2:38 ` [U-Boot] [PATCH V2 00/21] Add mx6solo/mx6duallite support Troy Kisky
@ 2012-09-22 2:38 ` Troy Kisky
2012-09-23 10:57 ` Stefano Babic
2012-09-22 2:38 ` [U-Boot] [PATCH V2 02/21] imximage: check dcd_len as entries added Troy Kisky
` (21 subsequent siblings)
22 siblings, 1 reply; 430+ messages in thread
From: Troy Kisky @ 2012-09-22 2:38 UTC (permalink / raw)
To: u-boot
Also, the header offset is no longer
right before the code starts.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
Series tested on an mx51 and mx6q
---
tools/imximage.c | 142 +++++++++++++++++++++++++++++++-----------------------
tools/imximage.h | 10 ++--
2 files changed, 87 insertions(+), 65 deletions(-)
diff --git a/tools/imximage.c b/tools/imximage.c
index 03a7716..25d3b74 100644
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -65,12 +65,15 @@ static table_entry_t imximage_versions[] = {
{-1, "", " (Invalid)", },
};
-static struct imx_header imximage_header;
static uint32_t imximage_version;
static set_dcd_val_t set_dcd_val;
static set_dcd_rst_t set_dcd_rst;
static set_imx_hdr_t set_imx_hdr;
+static set_imx_size_t set_imx_size;
+static uint32_t g_flash_offset;
+
+static struct image_type_params imximage_params;
static uint32_t get_cfg_value(char *token, char *name, int linenr)
{
@@ -207,85 +210,79 @@ static void set_dcd_rst_v2(struct imx_header *imxhdr, uint32_t dcd_len,
dcd_v2->write_dcd_command.param = DCD_COMMAND_PARAM;
}
-static void set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,
- struct stat *sbuf,
- struct mkimage_params *params)
+static int set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,
+ uint32_t entry_point, uint32_t flash_offset)
{
imx_header_v1_t *hdr_v1 = &imxhdr->header.hdr_v1;
flash_header_v1_t *fhdr_v1 = &hdr_v1->fhdr;
dcd_v1_t *dcd_v1 = &hdr_v1->dcd_table;
- uint32_t base_offset;
-
- /* Exit if there is no BOOT_FROM field specifying the flash_offset */
- if(imxhdr->flash_offset == FLASH_OFFSET_UNDEFINED) {
- fprintf(stderr, "Error: Header v1: No BOOT_FROM tag in %s\n",
- params->imagename);
- exit(EXIT_FAILURE);
- }
+ uint32_t hdr_base;
+ uint32_t header_length = (((char *)&dcd_v1->addr_data[dcd_len].addr)
+ - ((char *)imxhdr));
/* Set magic number */
fhdr_v1->app_code_barker = APP_CODE_BARKER;
- fhdr_v1->app_dest_ptr = params->addr;
- fhdr_v1->app_dest_ptr = params->ep - imxhdr->flash_offset -
- sizeof(struct imx_header);
- fhdr_v1->app_code_jump_vector = params->ep;
+ hdr_base = entry_point - header_length;
+ fhdr_v1->app_dest_ptr = hdr_base - flash_offset;
+ fhdr_v1->app_code_jump_vector = entry_point;
- base_offset = fhdr_v1->app_dest_ptr + imxhdr->flash_offset ;
- fhdr_v1->dcd_ptr_ptr =
- (uint32_t) (offsetof(flash_header_v1_t, dcd_ptr) -
- offsetof(flash_header_v1_t, app_code_jump_vector) +
- base_offset);
-
- fhdr_v1->dcd_ptr = base_offset +
- offsetof(imx_header_v1_t, dcd_table);
-
- /* The external flash header must be at the end of the DCD table */
- dcd_v1->addr_data[dcd_len].type = sbuf->st_size +
- imxhdr->flash_offset +
- sizeof(struct imx_header);
+ fhdr_v1->dcd_ptr_ptr = hdr_base + offsetof(flash_header_v1_t, dcd_ptr);
+ fhdr_v1->dcd_ptr = hdr_base + offsetof(imx_header_v1_t, dcd_table);
/* Security feature are not supported */
fhdr_v1->app_code_csf = 0;
fhdr_v1->super_root_key = 0;
+ return header_length;
+}
+
+static void set_imx_size_v1(struct imx_header *imxhdr, uint32_t file_size,
+ uint32_t flash_offset)
+{
+ uint32_t *p = (uint32_t *)(((char *)imxhdr)
+ + imximage_params.header_size);
+
+ /* The external flash header must be at the end of the DCD table */
+ /* file_size includes header */
+ p[-1] = file_size + flash_offset;
}
-static void set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t dcd_len,
- struct stat *sbuf,
- struct mkimage_params *params)
+static int set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t dcd_len,
+ uint32_t entry_point, uint32_t flash_offset)
{
imx_header_v2_t *hdr_v2 = &imxhdr->header.hdr_v2;
flash_header_v2_t *fhdr_v2 = &hdr_v2->fhdr;
-
- /* Exit if there is no BOOT_FROM field specifying the flash_offset */
- if(imxhdr->flash_offset == FLASH_OFFSET_UNDEFINED) {
- fprintf(stderr, "Error: Header v2: No BOOT_FROM tag in %s\n",
- params->imagename);
- exit(EXIT_FAILURE);
- }
+ uint32_t hdr_base;
+ uint32_t header_length = (dcd_len) ?
+ (char *)&hdr_v2->dcd_table.addr_data[dcd_len] - ((char*)imxhdr)
+ : offsetof(imx_header_v2_t, dcd_table);
/* Set magic number */
fhdr_v2->header.tag = IVT_HEADER_TAG; /* 0xD1 */
fhdr_v2->header.length = cpu_to_be16(sizeof(flash_header_v2_t));
fhdr_v2->header.version = IVT_VERSION; /* 0x40 */
- fhdr_v2->entry = params->ep;
+ fhdr_v2->entry = entry_point;
fhdr_v2->reserved1 = fhdr_v2->reserved2 = 0;
- fhdr_v2->self = params->ep - sizeof(struct imx_header);
-
- fhdr_v2->dcd_ptr = fhdr_v2->self +
- offsetof(imx_header_v2_t, dcd_table);
+ fhdr_v2->self = hdr_base = entry_point - header_length;
- fhdr_v2->boot_data_ptr = fhdr_v2->self +
- offsetof(imx_header_v2_t, boot_data);
-
- hdr_v2->boot_data.start = fhdr_v2->self - imxhdr->flash_offset;
- hdr_v2->boot_data.size = sbuf->st_size +
- imxhdr->flash_offset +
- sizeof(struct imx_header);
+ fhdr_v2->dcd_ptr = (dcd_len) ? hdr_base
+ + offsetof(imx_header_v2_t, dcd_table) : 0;
+ fhdr_v2->boot_data_ptr = hdr_base
+ + offsetof(imx_header_v2_t, boot_data);
+ hdr_v2->boot_data.start = hdr_base - flash_offset;
/* Security feature are not supported */
fhdr_v2->csf = 0;
+ return header_length;
+}
+
+static void set_imx_size_v2(struct imx_header *imxhdr, uint32_t file_size,
+ uint32_t flash_offset)
+{
+ imx_header_v2_t *hdr_v2 = &imxhdr->header.hdr_v2;
+ /* file_size includes header */
+ hdr_v2->boot_data.size = file_size + flash_offset;
}
static void set_hdr_func(struct imx_header *imxhdr)
@@ -295,11 +292,13 @@ static void set_hdr_func(struct imx_header *imxhdr)
set_dcd_val = set_dcd_val_v1;
set_dcd_rst = set_dcd_rst_v1;
set_imx_hdr = set_imx_hdr_v1;
+ set_imx_size = set_imx_size_v1;
break;
case IMXIMAGE_V2:
set_dcd_val = set_dcd_val_v2;
set_dcd_rst = set_dcd_rst_v2;
set_imx_hdr = set_imx_hdr_v2;
+ set_imx_size = set_imx_size_v2;
break;
default:
err_imximage_version(imximage_version);
@@ -381,9 +380,9 @@ static void parse_cfg_cmd(struct imx_header *imxhdr, int32_t cmd, char *token,
set_hdr_func(imxhdr);
break;
case CMD_BOOT_FROM:
- imxhdr->flash_offset = get_table_entry_id(imximage_bootops,
+ g_flash_offset = get_table_entry_id(imximage_bootops,
"imximage boot option", token);
- if (imxhdr->flash_offset == -1) {
+ if (g_flash_offset == -1) {
fprintf(stderr, "Error: %s[%d] -Invalid boot device"
"(%s)\n", name, lineno, token);
exit(EXIT_FAILURE);
@@ -521,12 +520,17 @@ static void imximage_print_header(const void *ptr)
}
}
-static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd,
- struct mkimage_params *params)
+int imximage_vrec_header(struct mkimage_params *params,
+ struct image_type_params *tparams)
{
- struct imx_header *imxhdr = (struct imx_header *)ptr;
+ struct imx_header *imxhdr;
uint32_t dcd_len;
+ imxhdr = calloc(1, MAX_HEADER_SIZE);
+ if (!imxhdr) {
+ fprintf(stderr, "Error: out of memory\n");
+ exit(EXIT_FAILURE);
+ }
/*
* In order to not change the old imx cfg file
* by adding VERSION command into it, here need
@@ -534,14 +538,31 @@ static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd,
*/
imximage_version = IMXIMAGE_V1;
/* Be able to detect if the cfg file has no BOOT_FROM tag */
- imxhdr->flash_offset = FLASH_OFFSET_UNDEFINED;
+ g_flash_offset = FLASH_OFFSET_UNDEFINED;
set_hdr_func(imxhdr);
/* Parse dcd configuration file */
dcd_len = parse_cfg_file(imxhdr, params->imagename);
+ /* Exit if there is no BOOT_FROM field specifying the flash_offset */
+ if (g_flash_offset == FLASH_OFFSET_UNDEFINED) {
+ fprintf(stderr, "Error: No BOOT_FROM tag in %s\n",
+ params->imagename);
+ exit(EXIT_FAILURE);
+ }
/* Set the imx header */
- (*set_imx_hdr)(imxhdr, dcd_len, sbuf, params);
+ imximage_params.header_size = (*set_imx_hdr)(imxhdr, dcd_len,
+ params->ep, g_flash_offset);
+ imximage_params.hdr = imxhdr;
+ return 0;
+}
+
+static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd,
+ struct mkimage_params *params)
+{
+ /* Set the size in header */
+ (*set_imx_size)((struct imx_header *)ptr, sbuf->st_size,
+ g_flash_offset);
}
int imximage_check_params(struct mkimage_params *params)
@@ -571,8 +592,9 @@ int imximage_check_params(struct mkimage_params *params)
*/
static struct image_type_params imximage_params = {
.name = "Freescale i.MX 5x Boot Image support",
- .header_size = sizeof(struct imx_header),
- .hdr = (void *)&imximage_header,
+ .header_size = 0,
+ .hdr = NULL,
+ .vrec_header = imximage_vrec_header,
.check_image_type = imximage_check_image_types,
.verify_header = imximage_verify_header,
.print_header = imximage_print_header,
diff --git a/tools/imximage.h b/tools/imximage.h
index 34f293d..5fe3a8a 100644
--- a/tools/imximage.h
+++ b/tools/imximage.h
@@ -30,6 +30,7 @@
#define DCD_BARKER 0xB17219E9
#define HEADER_OFFSET 0x400
+#define MAX_HEADER_SIZE (16 << 10)
#define CMD_DATA_STR "DATA"
#define FLASH_OFFSET_UNDEFINED 0xFFFFFFFF
@@ -156,7 +157,6 @@ struct imx_header {
imx_header_v1_t hdr_v1;
imx_header_v2_t hdr_v2;
} header;
- uint32_t flash_offset;
};
typedef void (*set_dcd_val_t)(struct imx_header *imxhdr,
@@ -168,9 +168,9 @@ typedef void (*set_dcd_rst_t)(struct imx_header *imxhdr,
uint32_t dcd_len,
char *name, int lineno);
-typedef void (*set_imx_hdr_t)(struct imx_header *imxhdr,
- uint32_t dcd_len,
- struct stat *sbuf,
- struct mkimage_params *params);
+typedef int (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t dcd_len,
+ uint32_t entry_point, uint32_t flash_offset);
+typedef void (*set_imx_size_t)(struct imx_header *imxhdr, uint32_t file_size,
+ uint32_t flash_offset);
#endif /* _IMXIMAGE_H_ */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 02/21] imximage: check dcd_len as entries added
2012-09-22 2:38 ` [U-Boot] [PATCH V2 00/21] Add mx6solo/mx6duallite support Troy Kisky
2012-09-22 2:38 ` [U-Boot] [PATCH V2 01/21] imximage: make header variable length Troy Kisky
@ 2012-09-22 2:38 ` Troy Kisky
2012-09-23 11:05 ` Stefano Babic
2012-09-22 2:39 ` [U-Boot] [PATCH V2 03/21] imximage: enable word writes for version2 header Troy Kisky
` (20 subsequent siblings)
22 siblings, 1 reply; 430+ messages in thread
From: Troy Kisky @ 2012-09-22 2:38 UTC (permalink / raw)
To: u-boot
Before the len was checked after the entire file
was processed, so it could have already overflowed.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
tools/imximage.c | 26 +++++++++++---------------
1 file changed, 11 insertions(+), 15 deletions(-)
diff --git a/tools/imximage.c b/tools/imximage.c
index 25d3b74..0bfbec3 100644
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -71,6 +71,7 @@ static set_dcd_val_t set_dcd_val;
static set_dcd_rst_t set_dcd_rst;
static set_imx_hdr_t set_imx_hdr;
static set_imx_size_t set_imx_size;
+static uint32_t max_dcd_entries;
static uint32_t g_flash_offset;
static struct image_type_params imximage_params;
@@ -173,13 +174,6 @@ static void set_dcd_rst_v1(struct imx_header *imxhdr, uint32_t dcd_len,
{
dcd_v1_t *dcd_v1 = &imxhdr->header.hdr_v1.dcd_table;
- if (dcd_len > MAX_HW_CFG_SIZE_V1) {
- fprintf(stderr, "Error: %s[%d] -"
- "DCD table exceeds maximum size(%d)\n",
- name, lineno, MAX_HW_CFG_SIZE_V1);
- exit(EXIT_FAILURE);
- }
-
dcd_v1->preamble.barker = DCD_BARKER;
dcd_v1->preamble.length = dcd_len * sizeof(dcd_type_addr_data_t);
}
@@ -193,13 +187,6 @@ static void set_dcd_rst_v2(struct imx_header *imxhdr, uint32_t dcd_len,
{
dcd_v2_t *dcd_v2 = &imxhdr->header.hdr_v2.dcd_table;
- if (dcd_len > MAX_HW_CFG_SIZE_V2) {
- fprintf(stderr, "Error: %s[%d] -"
- "DCD table exceeds maximum size(%d)\n",
- name, lineno, MAX_HW_CFG_SIZE_V2);
- exit(EXIT_FAILURE);
- }
-
dcd_v2->header.tag = DCD_HEADER_TAG;
dcd_v2->header.length = cpu_to_be16(
dcd_len * sizeof(dcd_addr_data_t) + 8);
@@ -293,12 +280,14 @@ static void set_hdr_func(struct imx_header *imxhdr)
set_dcd_rst = set_dcd_rst_v1;
set_imx_hdr = set_imx_hdr_v1;
set_imx_size = set_imx_size_v1;
+ max_dcd_entries = MAX_HW_CFG_SIZE_V1;
break;
case IMXIMAGE_V2:
set_dcd_val = set_dcd_val_v2;
set_dcd_rst = set_dcd_rst_v2;
set_imx_hdr = set_imx_hdr_v2;
set_imx_size = set_imx_size_v2;
+ max_dcd_entries = MAX_HW_CFG_SIZE_V2;
break;
default:
err_imximage_version(imximage_version);
@@ -425,8 +414,15 @@ static void parse_cfg_fld(struct imx_header *imxhdr, int32_t *cmd,
value = get_cfg_value(token, name, lineno);
(*set_dcd_val)(imxhdr, name, lineno, fld, value, *dcd_len);
- if (fld == CFG_REG_VALUE)
+ if (fld == CFG_REG_VALUE) {
(*dcd_len)++;
+ if (*dcd_len > max_dcd_entries) {
+ fprintf(stderr, "Error: %s[%d] -"
+ "DCD table exceeds maximum size(%d)\n",
+ name, lineno, max_dcd_entries);
+ exit(EXIT_FAILURE);
+ }
+ }
break;
default:
break;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 03/21] imximage: enable word writes for version2 header
2012-09-22 2:38 ` [U-Boot] [PATCH V2 00/21] Add mx6solo/mx6duallite support Troy Kisky
2012-09-22 2:38 ` [U-Boot] [PATCH V2 01/21] imximage: make header variable length Troy Kisky
2012-09-22 2:38 ` [U-Boot] [PATCH V2 02/21] imximage: check dcd_len as entries added Troy Kisky
@ 2012-09-22 2:39 ` Troy Kisky
2012-09-22 2:39 ` [U-Boot] [PATCH V2 04/21] imximage: cleanup parsing Troy Kisky
` (19 subsequent siblings)
22 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-09-22 2:39 UTC (permalink / raw)
To: u-boot
Before, only 1 write_dcd_command table was built.
Now, a new table is built when the size changes.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
tools/imximage.c | 153 ++++++++++++++++++++++++++----------------------------
tools/imximage.h | 15 ++----
2 files changed, 77 insertions(+), 91 deletions(-)
diff --git a/tools/imximage.c b/tools/imximage.c
index 0bfbec3..21c49e6 100644
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -68,10 +68,9 @@ static table_entry_t imximage_versions[] = {
static uint32_t imximage_version;
static set_dcd_val_t set_dcd_val;
-static set_dcd_rst_t set_dcd_rst;
static set_imx_hdr_t set_imx_hdr;
static set_imx_size_t set_imx_size;
-static uint32_t max_dcd_entries;
+static uint32_t *p_max_dcd;
static uint32_t g_flash_offset;
static struct image_type_params imximage_params;
@@ -119,8 +118,10 @@ static void err_imximage_version(int version)
exit(EXIT_FAILURE);
}
+static uint32_t *p_entry;
+
static void set_dcd_val_v1(struct imx_header *imxhdr, char *name, int lineno,
- int fld, uint32_t value, uint32_t off)
+ int fld, uint32_t value)
{
dcd_v1_t *dcd_v1 = &imxhdr->header.hdr_v1.dcd_table;
@@ -133,13 +134,15 @@ static void set_dcd_val_v1(struct imx_header *imxhdr, char *name, int lineno,
name, lineno, value);
exit(EXIT_FAILURE);
}
- dcd_v1->addr_data[off].type = value;
+ *p_entry++ = value;
break;
case CFG_REG_ADDRESS:
- dcd_v1->addr_data[off].addr = value;
+ *p_entry++ = value;
break;
case CFG_REG_VALUE:
- dcd_v1->addr_data[off].value = value;
+ *p_entry++ = value;
+ dcd_v1->preamble.length = (char *)p_entry
+ - (char *)&dcd_v1->addr_data[0].type;
break;
default:
break;
@@ -147,17 +150,45 @@ static void set_dcd_val_v1(struct imx_header *imxhdr, char *name, int lineno,
}
}
+static write_dcd_command_t *p_dcd;
+
static void set_dcd_val_v2(struct imx_header *imxhdr, char *name, int lineno,
- int fld, uint32_t value, uint32_t off)
+ int fld, uint32_t value)
{
+ uint32_t len;
dcd_v2_t *dcd_v2 = &imxhdr->header.hdr_v2.dcd_table;
switch (fld) {
+ case CFG_REG_SIZE:
+ /* Byte, halfword, word */
+ if ((value != 1) && (value != 2) && (value != 4)) {
+ fprintf(stderr, "Error: %s[%d] - "
+ "Invalid register size " "(%d)\n",
+ name, lineno, value);
+ exit(EXIT_FAILURE);
+ }
+ if (p_dcd && (p_dcd->param == value))
+ break;
+ if (!p_dcd) {
+ dcd_v2->header.tag = DCD_HEADER_TAG;
+ dcd_v2->header.version = DCD_VERSION;
+ p_dcd = &dcd_v2->write_dcd_command;
+ } else {
+ p_dcd = (write_dcd_command_t *)p_entry;
+ }
+ p_dcd->param = value;
+ p_dcd->tag = DCD_COMMAND_TAG;
+ p_entry = (uint32_t *)(p_dcd + 1);
+ break;
case CFG_REG_ADDRESS:
- dcd_v2->addr_data[off].addr = cpu_to_be32(value);
+ *p_entry++ = cpu_to_be32(value);
break;
case CFG_REG_VALUE:
- dcd_v2->addr_data[off].value = cpu_to_be32(value);
+ *p_entry++ = cpu_to_be32(value);
+ len = (char *)p_entry - (char *)&dcd_v2->header;
+ dcd_v2->header.length = cpu_to_be16(len);
+ len = (char *)p_entry - (char *)p_dcd;
+ p_dcd->length = cpu_to_be16(len);
break;
default:
break;
@@ -165,47 +196,13 @@ static void set_dcd_val_v2(struct imx_header *imxhdr, char *name, int lineno,
}
}
-/*
- * Complete setting up the rest field of DCD of V1
- * such as barker code and DCD data length.
- */
-static void set_dcd_rst_v1(struct imx_header *imxhdr, uint32_t dcd_len,
- char *name, int lineno)
-{
- dcd_v1_t *dcd_v1 = &imxhdr->header.hdr_v1.dcd_table;
-
- dcd_v1->preamble.barker = DCD_BARKER;
- dcd_v1->preamble.length = dcd_len * sizeof(dcd_type_addr_data_t);
-}
-
-/*
- * Complete setting up the reset field of DCD of V2
- * such as DCD tag, version, length, etc.
- */
-static void set_dcd_rst_v2(struct imx_header *imxhdr, uint32_t dcd_len,
- char *name, int lineno)
-{
- dcd_v2_t *dcd_v2 = &imxhdr->header.hdr_v2.dcd_table;
-
- dcd_v2->header.tag = DCD_HEADER_TAG;
- dcd_v2->header.length = cpu_to_be16(
- dcd_len * sizeof(dcd_addr_data_t) + 8);
- dcd_v2->header.version = DCD_VERSION;
- dcd_v2->write_dcd_command.tag = DCD_COMMAND_TAG;
- dcd_v2->write_dcd_command.length = cpu_to_be16(
- dcd_len * sizeof(dcd_addr_data_t) + 4);
- dcd_v2->write_dcd_command.param = DCD_COMMAND_PARAM;
-}
-
-static int set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,
+static int set_imx_hdr_v1(struct imx_header *imxhdr,
uint32_t entry_point, uint32_t flash_offset)
{
imx_header_v1_t *hdr_v1 = &imxhdr->header.hdr_v1;
flash_header_v1_t *fhdr_v1 = &hdr_v1->fhdr;
- dcd_v1_t *dcd_v1 = &hdr_v1->dcd_table;
uint32_t hdr_base;
- uint32_t header_length = (((char *)&dcd_v1->addr_data[dcd_len].addr)
- - ((char *)imxhdr));
+ uint32_t header_length = ((char *)p_entry) + 4 - ((char *)imxhdr);
/* Set magic number */
fhdr_v1->app_code_barker = APP_CODE_BARKER;
@@ -234,15 +231,13 @@ static void set_imx_size_v1(struct imx_header *imxhdr, uint32_t file_size,
p[-1] = file_size + flash_offset;
}
-static int set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t dcd_len,
+static int set_imx_hdr_v2(struct imx_header *imxhdr,
uint32_t entry_point, uint32_t flash_offset)
{
imx_header_v2_t *hdr_v2 = &imxhdr->header.hdr_v2;
flash_header_v2_t *fhdr_v2 = &hdr_v2->fhdr;
uint32_t hdr_base;
- uint32_t header_length = (dcd_len) ?
- (char *)&hdr_v2->dcd_table.addr_data[dcd_len] - ((char*)imxhdr)
- : offsetof(imx_header_v2_t, dcd_table);
+ uint32_t header_length = ((char *)p_entry) - ((char *)imxhdr);
/* Set magic number */
fhdr_v2->header.tag = IVT_HEADER_TAG; /* 0xD1 */
@@ -253,7 +248,7 @@ static int set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t dcd_len,
fhdr_v2->reserved1 = fhdr_v2->reserved2 = 0;
fhdr_v2->self = hdr_base = entry_point - header_length;
- fhdr_v2->dcd_ptr = (dcd_len) ? hdr_base
+ fhdr_v2->dcd_ptr = (p_dcd) ? hdr_base
+ offsetof(imx_header_v2_t, dcd_table) : 0;
fhdr_v2->boot_data_ptr = hdr_base
+ offsetof(imx_header_v2_t, boot_data);
@@ -277,17 +272,19 @@ static void set_hdr_func(struct imx_header *imxhdr)
switch (imximage_version) {
case IMXIMAGE_V1:
set_dcd_val = set_dcd_val_v1;
- set_dcd_rst = set_dcd_rst_v1;
set_imx_hdr = set_imx_hdr_v1;
set_imx_size = set_imx_size_v1;
- max_dcd_entries = MAX_HW_CFG_SIZE_V1;
+ p_entry = &imxhdr->header.hdr_v1.dcd_table.addr_data[0].type;
+ p_max_dcd = &imxhdr->header.hdr_v1.dcd_table
+ .addr_data[MAX_HW_CFG_SIZE_V1].type;
+ imxhdr->header.hdr_v1.dcd_table.preamble.barker = DCD_BARKER;
break;
case IMXIMAGE_V2:
set_dcd_val = set_dcd_val_v2;
- set_dcd_rst = set_dcd_rst_v2;
set_imx_hdr = set_imx_hdr_v2;
set_imx_size = set_imx_size_v2;
- max_dcd_entries = MAX_HW_CFG_SIZE_V2;
+ p_entry = (uint32_t *)&imxhdr->header.hdr_v2.dcd_table;
+ p_max_dcd = (uint32_t *)((char *)imxhdr + MAX_HEADER_SIZE);
break;
default:
err_imximage_version(imximage_version);
@@ -351,7 +348,7 @@ static void print_hdr_v2(struct imx_header *imx_hdr)
}
static void parse_cfg_cmd(struct imx_header *imxhdr, int32_t cmd, char *token,
- char *name, int lineno, int fld, int dcd_len)
+ char *name, int lineno, int fld)
{
int value;
static int cmd_ver_first = ~0;
@@ -381,7 +378,7 @@ static void parse_cfg_cmd(struct imx_header *imxhdr, int32_t cmd, char *token,
break;
case CMD_DATA:
value = get_cfg_value(token, name, lineno);
- (*set_dcd_val)(imxhdr, name, lineno, fld, value, dcd_len);
+ (*set_dcd_val)(imxhdr, name, lineno, fld, value);
if (unlikely(cmd_ver_first != 1))
cmd_ver_first = 0;
break;
@@ -389,7 +386,7 @@ static void parse_cfg_cmd(struct imx_header *imxhdr, int32_t cmd, char *token,
}
static void parse_cfg_fld(struct imx_header *imxhdr, int32_t *cmd,
- char *token, char *name, int lineno, int fld, int *dcd_len)
+ char *token, char *name, int lineno, int fld)
{
int value;
@@ -404,7 +401,7 @@ static void parse_cfg_fld(struct imx_header *imxhdr, int32_t *cmd,
}
break;
case CFG_REG_SIZE:
- parse_cfg_cmd(imxhdr, *cmd, token, name, lineno, fld, *dcd_len);
+ parse_cfg_cmd(imxhdr, *cmd, token, name, lineno, fld);
break;
case CFG_REG_ADDRESS:
case CFG_REG_VALUE:
@@ -412,23 +409,20 @@ static void parse_cfg_fld(struct imx_header *imxhdr, int32_t *cmd,
return;
value = get_cfg_value(token, name, lineno);
- (*set_dcd_val)(imxhdr, name, lineno, fld, value, *dcd_len);
-
- if (fld == CFG_REG_VALUE) {
- (*dcd_len)++;
- if (*dcd_len > max_dcd_entries) {
- fprintf(stderr, "Error: %s[%d] -"
- "DCD table exceeds maximum size(%d)\n",
- name, lineno, max_dcd_entries);
- exit(EXIT_FAILURE);
- }
+ (*set_dcd_val)(imxhdr, name, lineno, fld, value);
+ if (p_entry > p_max_dcd) {
+ uint32_t size = (char *)p_max_dcd - (char *)imxhdr;
+ fprintf(stderr, "Error: %s[%d] -"
+ "header exceeds maximum size(%d)\n",
+ name, lineno, size);
+ exit(EXIT_FAILURE);
}
break;
default:
break;
}
}
-static uint32_t parse_cfg_file(struct imx_header *imxhdr, char *name)
+static void parse_cfg_file(struct imx_header *imxhdr, char *name)
{
FILE *fd = NULL;
char *line = NULL;
@@ -436,7 +430,6 @@ static uint32_t parse_cfg_file(struct imx_header *imxhdr, char *name)
int lineno = 0;
int fld;
size_t len;
- int dcd_len = 0;
int32_t cmd;
fd = fopen(name, "r");
@@ -467,15 +460,12 @@ static uint32_t parse_cfg_file(struct imx_header *imxhdr, char *name)
break;
parse_cfg_fld(imxhdr, &cmd, token, name,
- lineno, fld, &dcd_len);
+ lineno, fld);
}
}
-
- (*set_dcd_rst)(imxhdr, dcd_len, name, lineno);
fclose(fd);
-
- return dcd_len;
+ return;
}
@@ -520,9 +510,12 @@ int imximage_vrec_header(struct mkimage_params *params,
struct image_type_params *tparams)
{
struct imx_header *imxhdr;
- uint32_t dcd_len;
- imxhdr = calloc(1, MAX_HEADER_SIZE);
+ /*
+ * A little extra space to avoid access violation on dcd table overflow.
+ * Overflow is checked after entry is added.
+ */
+ imxhdr = calloc(1, MAX_HEADER_SIZE + 32);
if (!imxhdr) {
fprintf(stderr, "Error: out of memory\n");
exit(EXIT_FAILURE);
@@ -538,7 +531,7 @@ int imximage_vrec_header(struct mkimage_params *params,
set_hdr_func(imxhdr);
/* Parse dcd configuration file */
- dcd_len = parse_cfg_file(imxhdr, params->imagename);
+ parse_cfg_file(imxhdr, params->imagename);
/* Exit if there is no BOOT_FROM field specifying the flash_offset */
if (g_flash_offset == FLASH_OFFSET_UNDEFINED) {
@@ -547,8 +540,8 @@ int imximage_vrec_header(struct mkimage_params *params,
exit(EXIT_FAILURE);
}
/* Set the imx header */
- imximage_params.header_size = (*set_imx_hdr)(imxhdr, dcd_len,
- params->ep, g_flash_offset);
+ imximage_params.header_size = (*set_imx_hdr)(imxhdr, params->ep,
+ g_flash_offset);
imximage_params.hdr = imxhdr;
return 0;
}
diff --git a/tools/imximage.h b/tools/imximage.h
index 5fe3a8a..0319c02 100644
--- a/tools/imximage.h
+++ b/tools/imximage.h
@@ -47,7 +47,6 @@
#define DCD_HEADER_TAG 0xD2
#define DCD_COMMAND_TAG 0xCC
#define DCD_VERSION 0x40
-#define DCD_COMMAND_PARAM 0x4
enum imximage_cmd {
CMD_INVALID,
@@ -159,17 +158,11 @@ struct imx_header {
} header;
};
-typedef void (*set_dcd_val_t)(struct imx_header *imxhdr,
- char *name, int lineno,
- int fld, uint32_t value,
- uint32_t off);
+typedef void (*set_dcd_val_t)(struct imx_header *imxhdr, char *name,
+ int lineno, int fld, uint32_t value);
-typedef void (*set_dcd_rst_t)(struct imx_header *imxhdr,
- uint32_t dcd_len,
- char *name, int lineno);
-
-typedef int (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t dcd_len,
- uint32_t entry_point, uint32_t flash_offset);
+typedef int (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t entry_point,
+ uint32_t flash_offset);
typedef void (*set_imx_size_t)(struct imx_header *imxhdr, uint32_t file_size,
uint32_t flash_offset);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 04/21] imximage: cleanup parsing
2012-09-22 2:38 ` [U-Boot] [PATCH V2 00/21] Add mx6solo/mx6duallite support Troy Kisky
` (2 preceding siblings ...)
2012-09-22 2:39 ` [U-Boot] [PATCH V2 03/21] imximage: enable word writes for version2 header Troy Kisky
@ 2012-09-22 2:39 ` Troy Kisky
2012-09-23 11:08 ` Stefano Babic
2012-09-22 2:39 ` [U-Boot] [PATCH V2 05/21] imximage: add expression evaluation Troy Kisky
` (18 subsequent siblings)
22 siblings, 1 reply; 430+ messages in thread
From: Troy Kisky @ 2012-09-22 2:39 UTC (permalink / raw)
To: u-boot
Move to pulling tokens instead of pushing them.
Remove need for switch statements to process commands.
Add error messages such as "command not finished",
"extra data at end of line", and "invalid token"
Add ';' as command separator.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
tools/imximage.c | 380 ++++++++++++++++++++++++++++++------------------------
tools/imximage.h | 25 ++--
2 files changed, 226 insertions(+), 179 deletions(-)
diff --git a/tools/imximage.c b/tools/imximage.c
index 21c49e6..1e120354 100644
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -75,21 +75,6 @@ static uint32_t g_flash_offset;
static struct image_type_params imximage_params;
-static uint32_t get_cfg_value(char *token, char *name, int linenr)
-{
- char *endptr;
- uint32_t value;
-
- errno = 0;
- value = strtoul(token, &endptr, 16);
- if (errno || (token == endptr)) {
- fprintf(stderr, "Error: %s[%d] - Invalid hex data(%s)\n",
- name, linenr, token);
- exit(EXIT_FAILURE);
- }
- return value;
-}
-
static uint32_t detect_imximage_version(struct imx_header *imx_hdr)
{
imx_header_v1_t *hdr_v1 = &imx_hdr->header.hdr_v1;
@@ -120,55 +105,38 @@ static void err_imximage_version(int version)
static uint32_t *p_entry;
-static void set_dcd_val_v1(struct imx_header *imxhdr, char *name, int lineno,
- int fld, uint32_t value)
+static int set_dcd_val_v1(struct imx_header *imxhdr, uint32_t *data)
{
dcd_v1_t *dcd_v1 = &imxhdr->header.hdr_v1.dcd_table;
+ uint32_t val = *data++;
- switch (fld) {
- case CFG_REG_SIZE:
- /* Byte, halfword, word */
- if ((value != 1) && (value != 2) && (value != 4)) {
- fprintf(stderr, "Error: %s[%d] - "
- "Invalid register size " "(%d)\n",
- name, lineno, value);
- exit(EXIT_FAILURE);
- }
- *p_entry++ = value;
- break;
- case CFG_REG_ADDRESS:
- *p_entry++ = value;
- break;
- case CFG_REG_VALUE:
- *p_entry++ = value;
- dcd_v1->preamble.length = (char *)p_entry
- - (char *)&dcd_v1->addr_data[0].type;
- break;
- default:
- break;
-
+ /* Byte, halfword, word */
+ if ((val != 1) && (val != 2) && (val != 4)) {
+ fprintf(stderr, "Error: Invalid register size (%d)\n", val);
+ return -1;
}
+ *p_entry++ = val;
+ *p_entry++ = *data++;
+ *p_entry++ = *data++;
+ dcd_v1->preamble.length = (char *)p_entry - (char *)&dcd_v1->
+ addr_data[0].type;
+ return 0;
}
static write_dcd_command_t *p_dcd;
-static void set_dcd_val_v2(struct imx_header *imxhdr, char *name, int lineno,
- int fld, uint32_t value)
+static int set_dcd_val_v2(struct imx_header *imxhdr, uint32_t *data)
{
uint32_t len;
dcd_v2_t *dcd_v2 = &imxhdr->header.hdr_v2.dcd_table;
+ uint32_t val = *data++;
- switch (fld) {
- case CFG_REG_SIZE:
- /* Byte, halfword, word */
- if ((value != 1) && (value != 2) && (value != 4)) {
- fprintf(stderr, "Error: %s[%d] - "
- "Invalid register size " "(%d)\n",
- name, lineno, value);
- exit(EXIT_FAILURE);
- }
- if (p_dcd && (p_dcd->param == value))
- break;
+ /* Byte, halfword, word */
+ if ((val != 1) && (val != 2) && (val != 4)) {
+ fprintf(stderr, "Error: Invalid register size (%d)\n", val);
+ return -1;
+ }
+ if (!(p_dcd && (p_dcd->param == val))) {
if (!p_dcd) {
dcd_v2->header.tag = DCD_HEADER_TAG;
dcd_v2->header.version = DCD_VERSION;
@@ -176,24 +144,19 @@ static void set_dcd_val_v2(struct imx_header *imxhdr, char *name, int lineno,
} else {
p_dcd = (write_dcd_command_t *)p_entry;
}
- p_dcd->param = value;
+ p_dcd->param = val;
p_dcd->tag = DCD_COMMAND_TAG;
p_entry = (uint32_t *)(p_dcd + 1);
- break;
- case CFG_REG_ADDRESS:
- *p_entry++ = cpu_to_be32(value);
- break;
- case CFG_REG_VALUE:
- *p_entry++ = cpu_to_be32(value);
- len = (char *)p_entry - (char *)&dcd_v2->header;
- dcd_v2->header.length = cpu_to_be16(len);
- len = (char *)p_entry - (char *)p_dcd;
- p_dcd->length = cpu_to_be16(len);
- break;
- default:
- break;
-
}
+ val = *data++;
+ *p_entry++ = cpu_to_be32(val);
+ val = *data++;
+ *p_entry++ = cpu_to_be32(val);
+ len = (char *)p_entry - (char *)&dcd_v2->header;
+ dcd_v2->header.length = cpu_to_be16(len);
+ len = (char *)p_entry - (char *)p_dcd;
+ p_dcd->length = cpu_to_be16(len);
+ return 0;
}
static int set_imx_hdr_v1(struct imx_header *imxhdr,
@@ -347,93 +310,186 @@ static void print_hdr_v2(struct imx_header *imx_hdr)
printf("Entry Point: %08x\n", (uint32_t)fhdr_v2->entry);
}
-static void parse_cfg_cmd(struct imx_header *imxhdr, int32_t cmd, char *token,
- char *name, int lineno, int fld)
+static int cmd_cnt;
+
+int skip_separators(struct data_src *ds)
{
- int value;
- static int cmd_ver_first = ~0;
-
- switch (cmd) {
- case CMD_IMAGE_VERSION:
- imximage_version = get_cfg_value(token, name, lineno);
- if (cmd_ver_first == 0) {
- fprintf(stderr, "Error: %s[%d] - IMAGE_VERSION "
- "command need be the first before other "
- "valid command in the file\n", name, lineno);
- exit(EXIT_FAILURE);
+ int line_no = ds->lineno;
+ char *p = ds->p;
+
+ for (;;) {
+ char c;
+ if (!p) {
+ if (getline(&ds->line, &ds->len, ds->fd) <= 0)
+ return -1;
+ ds->lineno++;
+ p = ds->line;
+ if (ds->cmd_started) {
+ fprintf(stderr, "warning: continuing command on"
+ " next line, line %s[%d](%s)\n",
+ ds->filename, ds->lineno, p);
+ }
}
- cmd_ver_first = 1;
- set_hdr_func(imxhdr);
- break;
- case CMD_BOOT_FROM:
- g_flash_offset = get_table_entry_id(imximage_bootops,
- "imximage boot option", token);
- if (g_flash_offset == -1) {
- fprintf(stderr, "Error: %s[%d] -Invalid boot device"
- "(%s)\n", name, lineno, token);
- exit(EXIT_FAILURE);
+ c = *p;
+ if ((c == ' ') || (c == '\t')) {
+ p++;
+ continue;
}
- if (unlikely(cmd_ver_first != 1))
- cmd_ver_first = 0;
- break;
- case CMD_DATA:
- value = get_cfg_value(token, name, lineno);
- (*set_dcd_val)(imxhdr, name, lineno, fld, value);
- if (unlikely(cmd_ver_first != 1))
- cmd_ver_first = 0;
- break;
+ /* Drop all text starting with '#' as comments */
+ if ((c == '#') || (c == '\r') || (c == '\n')
+ || !c) {
+ p = NULL;
+ continue;
+ }
+ if (c == ';') {
+ if (ds->cmd_started) {
+ fprintf(stderr, "Error: command not "
+ "finished:%s[%d](%s)\n",
+ ds->filename, ds->lineno, p);
+ exit(EXIT_FAILURE);
+ }
+ p++;
+ continue;
+ }
+ if (!ds->cmd_started && line_no == ds->lineno) {
+ fprintf(stderr, "warning: extra data at end "
+ "of line %s[%d](%s)\n",
+ ds->filename, ds->lineno, p);
+ p = NULL;
+ continue;
+ }
+ ds->p = p;
+ return 0;
}
}
-static void parse_cfg_fld(struct imx_header *imxhdr, int32_t *cmd,
- char *token, char *name, int lineno, int fld)
+char *grab_token(char *dest, int size, char *src)
{
- int value;
-
- switch (fld) {
- case CFG_COMMAND:
- *cmd = get_table_entry_id(imximage_cmds,
- "imximage commands", token);
- if (*cmd < 0) {
- fprintf(stderr, "Error: %s[%d] - Invalid command"
- "(%s)\n", name, lineno, token);
- exit(EXIT_FAILURE);
- }
- break;
- case CFG_REG_SIZE:
- parse_cfg_cmd(imxhdr, *cmd, token, name, lineno, fld);
- break;
- case CFG_REG_ADDRESS:
- case CFG_REG_VALUE:
- if (*cmd != CMD_DATA)
- return;
-
- value = get_cfg_value(token, name, lineno);
- (*set_dcd_val)(imxhdr, name, lineno, fld, value);
- if (p_entry > p_max_dcd) {
- uint32_t size = (char *)p_max_dcd - (char *)imxhdr;
- fprintf(stderr, "Error: %s[%d] -"
- "header exceeds maximum size(%d)\n",
- name, lineno, size);
- exit(EXIT_FAILURE);
- }
- break;
- default:
- break;
+ while (size) {
+ char c = *src;
+ if ((c == ' ') || (c == '\t') || (c == '\r') || (c == '\n')
+ || (c == '#') || !c)
+ break;
+ *dest++ = c;
+ size--;
+ src++;
+ }
+ if (!size)
+ return NULL;
+ *dest = 0;
+ return src;
+}
+
+static uint32_t get_cfg_value(struct data_src *ds, uint32_t *pval)
+{
+ char *endptr;
+ uint32_t value;
+
+ if (skip_separators(ds))
+ return -1;
+ errno = 0;
+ value = strtoul(ds->p, &endptr, 16);
+ if (errno || (ds->p == endptr))
+ return -1;
+ *pval = value;
+ ds->p = endptr;
+ return 0;
+}
+
+static int parse_cmd_data(struct data_src *ds)
+{
+ uint32_t data[3];
+ int ret = get_cfg_value(ds, &data[0]);
+
+ if (ret)
+ return ret;
+ ret = get_cfg_value(ds, &data[1]);
+ if (ret)
+ return ret;
+ ret = get_cfg_value(ds, &data[2]);
+ if (ret)
+ return ret;
+ ret = (*set_dcd_val)(ds->imxhdr, data);
+ if (ret)
+ return ret;
+ if (p_entry > p_max_dcd) {
+ uint32_t size = (char *)p_max_dcd - (char *)ds->imxhdr;
+ fprintf(stderr, "Error: header exceeds maximum size(%d)\n",
+ size);
+ return -1;
+ }
+ return 0;
+}
+
+static int parse_image_version(struct data_src *ds)
+{
+ int ret;
+
+ ret = get_cfg_value(ds, &imximage_version);
+ if (ret)
+ return ret;
+ if (cmd_cnt) {
+ fprintf(stderr, "Error: IMAGE_VERSION command needs be "
+ "before other valid commands in the file\n");
+ return -1;
+ }
+ set_hdr_func(ds->imxhdr);
+ return 0;
+}
+
+int get_from_array(struct data_src *ds,
+ const table_entry_t *table, const char *table_name)
+{
+ int val;
+ char token[16];
+ char *p;
+
+ if (skip_separators(ds))
+ return -1;
+ p = grab_token(token, sizeof(token), ds->p);
+ if (!p)
+ return -1;
+ val = get_table_entry_id(table, table_name, token);
+ if (val != -1)
+ ds->p = p;
+ return val;
+}
+
+static int parse_boot_from(struct data_src *ds)
+{
+ g_flash_offset = get_from_array(ds, imximage_bootops,
+ "imximage boot option");
+ if (g_flash_offset == -1) {
+ fprintf(stderr, "Error: Invalid boot device\n");
+ return -1;
}
+ return 0;
}
+
+parse_fld_t cmd_table[] = {
+ parse_image_version, parse_boot_from, parse_cmd_data
+};
+
+static int parse_command(struct data_src *ds)
+{
+ int cmd = get_from_array(ds, imximage_cmds, "imximage commands");
+ if (cmd < 0)
+ return cmd;
+ return cmd_table[cmd](ds);
+}
+
static void parse_cfg_file(struct imx_header *imxhdr, char *name)
{
- FILE *fd = NULL;
- char *line = NULL;
- char *token, *saveptr1, *saveptr2;
- int lineno = 0;
- int fld;
- size_t len;
- int32_t cmd;
-
- fd = fopen(name, "r");
- if (fd == 0) {
+ struct data_src ds;
+
+ ds.line = NULL;
+ ds.len = 0;
+ ds.lineno = 0;
+ ds.filename = name;
+ ds.fd = fopen(name, "r");
+ ds.imxhdr = imxhdr;
+ ds.p = NULL;
+ if (ds.fd == 0) {
fprintf(stderr, "Error: %s - Can't open DCD file\n", name);
exit(EXIT_FAILURE);
}
@@ -441,34 +497,22 @@ static void parse_cfg_file(struct imx_header *imxhdr, char *name)
/* Very simple parsing, line starting with # are comments
* and are dropped
*/
- while ((getline(&line, &len, fd)) > 0) {
- lineno++;
-
- token = strtok_r(line, "\r\n", &saveptr1);
- if (token == NULL)
- continue;
-
- /* Check inside the single line */
- for (fld = CFG_COMMAND, cmd = CMD_INVALID,
- line = token; ; line = NULL, fld++) {
- token = strtok_r(line, " \t", &saveptr2);
- if (token == NULL)
- break;
-
- /* Drop all text starting with '#' as comments */
- if (token[0] == '#')
- break;
-
- parse_cfg_fld(imxhdr, &cmd, token, name,
- lineno, fld);
+ for (;;) {
+ ds.cmd_started = 0;
+ if (skip_separators(&ds))
+ break;
+ ds.cmd_started = 1;
+ if (parse_command(&ds)) {
+ fprintf(stderr, "Error: invalid token "
+ "%s[%d](%s)\n", name, ds.lineno, ds.p);
+ exit(EXIT_FAILURE);
}
-
+ cmd_cnt++;
}
- fclose(fd);
+ fclose(ds.fd);
return;
}
-
static int imximage_check_image_types(uint8_t type)
{
if (type == IH_TYPE_IMXIMAGE)
@@ -557,12 +601,12 @@ static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd,
int imximage_check_params(struct mkimage_params *params)
{
if (!params)
- return CFG_INVALID;
+ return -1;
if (!strlen(params->imagename)) {
fprintf(stderr, "Error: %s - Configuration file not specified, "
"it is needed for imximage generation\n",
params->cmdname);
- return CFG_INVALID;
+ return -1;
}
/*
* Check parameters:
diff --git a/tools/imximage.h b/tools/imximage.h
index 0319c02..efd249b 100644
--- a/tools/imximage.h
+++ b/tools/imximage.h
@@ -49,20 +49,11 @@
#define DCD_VERSION 0x40
enum imximage_cmd {
- CMD_INVALID,
CMD_IMAGE_VERSION,
CMD_BOOT_FROM,
CMD_DATA
};
-enum imximage_fld_types {
- CFG_INVALID = -1,
- CFG_COMMAND,
- CFG_REG_SIZE,
- CFG_REG_ADDRESS,
- CFG_REG_VALUE
-};
-
enum imximage_version {
IMXIMAGE_VER_INVALID = -1,
IMXIMAGE_V1 = 1,
@@ -158,8 +149,20 @@ struct imx_header {
} header;
};
-typedef void (*set_dcd_val_t)(struct imx_header *imxhdr, char *name,
- int lineno, int fld, uint32_t value);
+struct data_src {
+ char *line;
+ size_t len;
+ FILE *fd;
+ int lineno;
+ char cmd_started;
+ char *filename;
+ struct imx_header *imxhdr;
+ char *p;
+};
+
+typedef int (*parse_fld_t)(struct data_src *ds);
+
+typedef int (*set_dcd_val_t)(struct imx_header *imxhdr, uint32_t *data);
typedef int (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t entry_point,
uint32_t flash_offset);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 05/21] imximage: add expression evaluation
2012-09-22 2:38 ` [U-Boot] [PATCH V2 00/21] Add mx6solo/mx6duallite support Troy Kisky
` (3 preceding siblings ...)
2012-09-22 2:39 ` [U-Boot] [PATCH V2 04/21] imximage: cleanup parsing Troy Kisky
@ 2012-09-22 2:39 ` Troy Kisky
2012-09-23 14:56 ` Stefano Babic
2012-09-22 2:39 ` [U-Boot] [PATCH V2 06/21] imximage: add plugin commands Troy Kisky
` (17 subsequent siblings)
22 siblings, 1 reply; 430+ messages in thread
From: Troy Kisky @ 2012-09-22 2:39 UTC (permalink / raw)
To: u-boot
Basic expressions with order precedence is
now supported.
ie. (----3 + ((1+2*3)/--2 + --5 *(8/4))) is 16.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
tools/imximage.c | 172 ++++++++++++++++++++++++++++++++++++++++++++++++++----
1 file changed, 162 insertions(+), 10 deletions(-)
diff --git a/tools/imximage.c b/tools/imximage.c
index 1e120354..2c5a622 100644
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -380,20 +380,172 @@ char *grab_token(char *dest, int size, char *src)
return src;
}
+char precedence[] = {
+ /* ( + - * / & ^ | ) */
+ 0, 2, 2, 1, 1, 3, 4, 5, 6
+};
+char unary_operations[] = "(+-";
+char binary_operations[] = " +-*/&^|)";
+
+uint32_t do_func(uint32_t val1, uint32_t val2, int op)
+{
+ switch (op) {
+ case 1:
+ return val1 + val2;
+ case 2:
+ return val1 - val2;
+ case 3:
+ return val1 * val2;
+ case 4:
+ return val1 / val2;
+ case 5:
+ return val1 & val2;
+ case 6:
+ return val1 ^ val2;
+ case 7:
+ return val1 | val2;
+ }
+ fprintf(stderr, "Error: in func %s: val1=%d val2=%d op = %d\n",
+ __func__, val1, val2, op);
+ exit(EXIT_FAILURE);
+}
+
+int find_op(char c, char *p)
+{
+ int i;
+ for (i = 0; ; i++) {
+ if (c == p[i])
+ return i;
+ if (!p[i])
+ break;
+ }
+ return -1;
+}
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
static uint32_t get_cfg_value(struct data_src *ds, uint32_t *pval)
{
char *endptr;
- uint32_t value;
+ int op_i = 0;
+ int val_i = 0;
+ unsigned char op[16];
+ uint32_t val[16];
+ int unary = 1;
+ char *p;
- if (skip_separators(ds))
- return -1;
- errno = 0;
- value = strtoul(ds->p, &endptr, 16);
- if (errno || (ds->p == endptr))
- return -1;
- *pval = value;
- ds->p = endptr;
- return 0;
+ p = ds->p;
+ for (;;) {
+ char c;
+ int i, j;
+ char *ops = unary ? unary_operations : binary_operations;
+
+ if (unary) {
+ ds->p = p;
+ if (skip_separators(ds))
+ return -1;
+ p = ds->p;
+ c = *p;
+ } else {
+ for (;;) {
+ c = *p;
+ if ((c != ' ') && (c != '\t'))
+ break;
+ p++;
+ }
+ }
+ i = find_op(c, ops);
+ debug("%d,%c,%d:%s\n", i, c, unary, p);
+ if ((i < 0) && unary) {
+ if (val_i >= ARRAY_SIZE(val))
+ return -1;
+ errno = 0;
+ val[val_i++] = strtoul(p, &endptr, 16);
+ if (errno || (p == endptr)) {
+ ds->p = p;
+ return -1;
+ }
+ p = endptr;
+ unary = 0;
+ debug("val[%d]=%x,%d,%d\n", val_i - 1, val[val_i - 1],
+ op_i, val_i);
+do_unary:
+ while (op_i) {
+ j = op[op_i - 1];
+ if (!(j & 0x80))
+ break;
+ op_i--;
+ val[val_i - 1] = do_func(0,
+ val[val_i - 1], j & 0x7f);
+ debug("un:%d,%x,%d,%d\n", val[val_i - 1], j,
+ op_i, val_i);
+ }
+ continue;
+ }
+ if (i < 0) {
+ c = 0;
+ i = 8;
+ } else {
+ p++;
+ }
+ if (c == '(') {
+ if (op_i >= ARRAY_SIZE(op))
+ return -1;
+ op[op_i++] = i;
+ debug("op[%d]=%x,%d,%d\n", op_i - 1, op[op_i - 1],
+ op_i, val_i);
+ unary = 1;
+ continue;
+ }
+ for (;;) {
+ if (!op_i || unary)
+ break;
+ j = op[op_i - 1];
+ if (j == 0) {
+ if (c == ')') {
+ op_i--;
+ goto do_unary;
+ }
+ break;
+ }
+ if ((j & 0x80)) {
+ op_i--;
+ val[val_i - 1] = do_func(0,
+ val[val_i - 1], j & 0x7f);
+ debug("unary:%d,%x\n", val[val_i - 1], j);
+ continue;
+ }
+ if (precedence[i] < precedence[j])
+ break;
+ if (val_i < 2)
+ return -1;
+ op_i--;
+ val[val_i - 2] = do_func(val[val_i - 2],
+ val[val_i - 1], j);
+ val_i--;
+ debug("binary:%d,%x,%d,%d\n", val[val_i - 1], j,
+ op_i, val_i);
+ }
+ if (c == ')') {
+ fprintf(stderr, "Error: unmatched parenthesis\n");
+ return -1;
+ }
+ if (i == 8) {
+ if ((op_i != 0) || (val_i != 1)) {
+ fprintf(stderr, "Error: syntax %d %d\n",
+ op_i, val_i);
+ return -1;
+ }
+ ds->p = p;
+ *pval = val[0];
+ return 0;
+ }
+ if (op_i >= ARRAY_SIZE(op))
+ return -1;
+ op[op_i++] = i | (unary << 7);
+ debug("op[%d]=%x,%d,%d\n", op_i - 1, op[op_i - 1], op_i, val_i);
+ unary = 1;
+ }
}
static int parse_cmd_data(struct data_src *ds)
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 06/21] imximage: add plugin commands
2012-09-22 2:38 ` [U-Boot] [PATCH V2 00/21] Add mx6solo/mx6duallite support Troy Kisky
` (4 preceding siblings ...)
2012-09-22 2:39 ` [U-Boot] [PATCH V2 05/21] imximage: add expression evaluation Troy Kisky
@ 2012-09-22 2:39 ` Troy Kisky
2012-09-23 15:38 ` Stefano Babic
2012-09-22 2:39 ` [U-Boot] [PATCH V2 07/21] imximage.cfg: run files through C preprocessor Troy Kisky
` (16 subsequent siblings)
22 siblings, 1 reply; 430+ messages in thread
From: Troy Kisky @ 2012-09-22 2:39 UTC (permalink / raw)
To: u-boot
Add commands
plugin address filename
iomux_entry addr, data1 [, data2, [, data3]]
write_entry addr, data1 [, data2, [, data3]]
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
tools/imximage.c | 334 ++++++++++++++++++++++++++++++++++++++++++++----------
tools/imximage.h | 11 +-
2 files changed, 283 insertions(+), 62 deletions(-)
diff --git a/tools/imximage.c b/tools/imximage.c
index 2c5a622..fae786a 100644
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -31,7 +31,6 @@
#include "mkimage.h"
#include <image.h>
#include "imximage.h"
-
/*
* Supported commands for configuration file
*/
@@ -39,6 +38,9 @@ static table_entry_t imximage_cmds[] = {
{CMD_BOOT_FROM, "BOOT_FROM", "boot command", },
{CMD_DATA, "DATA", "Reg Write Data", },
{CMD_IMAGE_VERSION, "IMAGE_VERSION", "image version", },
+ {CMD_PLUGIN, "plugin", "plugin addr,file", },
+ {CMD_IOMUX_ENTRY, "iomux_entry", "Write iomux reg", },
+ {CMD_WRITE_ENTRY, "write_entry", "Write register", },
{-1, "", "", },
};
@@ -69,8 +71,8 @@ static uint32_t imximage_version;
static set_dcd_val_t set_dcd_val;
static set_imx_hdr_t set_imx_hdr;
-static set_imx_size_t set_imx_size;
static uint32_t *p_max_dcd;
+static uint32_t *header_size_ptr;
static uint32_t g_flash_offset;
static struct image_type_params imximage_params;
@@ -88,8 +90,7 @@ static uint32_t detect_imximage_version(struct imx_header *imx_hdr)
return IMXIMAGE_V1;
/* Try to detect V2 */
- if ((fhdr_v2->header.tag == IVT_HEADER_TAG) &&
- (hdr_v2->dcd_table.header.tag == DCD_HEADER_TAG))
+ if ((fhdr_v2->header.tag == IVT_HEADER_TAG))
return IMXIMAGE_V2;
return IMXIMAGE_VER_INVALID;
@@ -160,7 +161,7 @@ static int set_dcd_val_v2(struct imx_header *imxhdr, uint32_t *data)
}
static int set_imx_hdr_v1(struct imx_header *imxhdr,
- uint32_t entry_point, uint32_t flash_offset)
+ uint32_t entry_point, uint32_t flash_offset, int plugin)
{
imx_header_v1_t *hdr_v1 = &imxhdr->header.hdr_v1;
flash_header_v1_t *fhdr_v1 = &hdr_v1->fhdr;
@@ -180,22 +181,12 @@ static int set_imx_hdr_v1(struct imx_header *imxhdr,
/* Security feature are not supported */
fhdr_v1->app_code_csf = 0;
fhdr_v1->super_root_key = 0;
+ header_size_ptr = (uint32_t *)(((char *)imxhdr) + header_length - 4);
return header_length;
}
-static void set_imx_size_v1(struct imx_header *imxhdr, uint32_t file_size,
- uint32_t flash_offset)
-{
- uint32_t *p = (uint32_t *)(((char *)imxhdr)
- + imximage_params.header_size);
-
- /* The external flash header must be at the end of the DCD table */
- /* file_size includes header */
- p[-1] = file_size + flash_offset;
-}
-
static int set_imx_hdr_v2(struct imx_header *imxhdr,
- uint32_t entry_point, uint32_t flash_offset)
+ uint32_t entry_point, uint32_t flash_offset, int plugin)
{
imx_header_v2_t *hdr_v2 = &imxhdr->header.hdr_v2;
flash_header_v2_t *fhdr_v2 = &hdr_v2->fhdr;
@@ -216,27 +207,20 @@ static int set_imx_hdr_v2(struct imx_header *imxhdr,
fhdr_v2->boot_data_ptr = hdr_base
+ offsetof(imx_header_v2_t, boot_data);
hdr_v2->boot_data.start = hdr_base - flash_offset;
+ hdr_v2->boot_data.plugin = plugin;
/* Security feature are not supported */
fhdr_v2->csf = 0;
+ header_size_ptr = &hdr_v2->boot_data.size;
return header_length;
}
-static void set_imx_size_v2(struct imx_header *imxhdr, uint32_t file_size,
- uint32_t flash_offset)
-{
- imx_header_v2_t *hdr_v2 = &imxhdr->header.hdr_v2;
- /* file_size includes header */
- hdr_v2->boot_data.size = file_size + flash_offset;
-}
-
static void set_hdr_func(struct imx_header *imxhdr)
{
switch (imximage_version) {
case IMXIMAGE_V1:
set_dcd_val = set_dcd_val_v1;
set_imx_hdr = set_imx_hdr_v1;
- set_imx_size = set_imx_size_v1;
p_entry = &imxhdr->header.hdr_v1.dcd_table.addr_data[0].type;
p_max_dcd = &imxhdr->header.hdr_v1.dcd_table
.addr_data[MAX_HW_CFG_SIZE_V1].type;
@@ -245,7 +229,6 @@ static void set_hdr_func(struct imx_header *imxhdr)
case IMXIMAGE_V2:
set_dcd_val = set_dcd_val_v2;
set_imx_hdr = set_imx_hdr_v2;
- set_imx_size = set_imx_size_v2;
p_entry = (uint32_t *)&imxhdr->header.hdr_v2.dcd_table;
p_max_dcd = (uint32_t *)((char *)imxhdr + MAX_HEADER_SIZE);
break;
@@ -283,31 +266,49 @@ static void print_hdr_v1(struct imx_header *imx_hdr)
printf("Entry Point: %08x\n", (uint32_t)fhdr_v1->app_code_jump_vector);
}
-static void print_hdr_v2(struct imx_header *imx_hdr)
+static void print_header_info2(struct imx_header *imx_hdr)
{
imx_header_v2_t *hdr_v2 = &imx_hdr->header.hdr_v2;
flash_header_v2_t *fhdr_v2 = &hdr_v2->fhdr;
+
+ printf("Data Size: ");
+ genimg_print_size(hdr_v2->boot_data.size);
+ printf("Load Address: %08x\n", (uint32_t)fhdr_v2->boot_data_ptr);
+ printf("Entry Point: %08x\n", (uint32_t)fhdr_v2->entry);
+}
+
+static void print_hdr_v2(struct imx_header *imxhdr)
+{
+ imx_header_v2_t *hdr_v2 = &imxhdr->header.hdr_v2;
dcd_v2_t *dcd_v2 = &hdr_v2->dcd_table;
uint32_t size, version;
- size = be16_to_cpu(dcd_v2->header.length) - 8;
- if (size > (MAX_HW_CFG_SIZE_V2 * sizeof(dcd_addr_data_t))) {
- fprintf(stderr,
- "Error: Image corrupt DCD size %d exceed maximum %d\n",
- (uint32_t)(size / sizeof(dcd_addr_data_t)),
- MAX_HW_CFG_SIZE_V2);
- exit(EXIT_FAILURE);
+ if (hdr_v2->fhdr.dcd_ptr) {
+ size = be16_to_cpu(dcd_v2->header.length) - 8;
+ if (size > (MAX_HW_CFG_SIZE_V2 * sizeof(dcd_addr_data_t))) {
+ fprintf(stderr, "Error: Image corrupt DCD size "
+ "%d exceed maximum %d\n",
+ (uint32_t)(size / sizeof(dcd_addr_data_t)),
+ MAX_HW_CFG_SIZE_V2);
+ exit(EXIT_FAILURE);
+ }
}
-
- version = detect_imximage_version(imx_hdr);
+ version = detect_imximage_version(imxhdr);
printf("Image Type: Freescale IMX Boot Image\n");
printf("Image Ver: %x", version);
printf("%s\n", get_table_entry_name(imximage_versions, NULL, version));
- printf("Data Size: ");
- genimg_print_size(hdr_v2->boot_data.size);
- printf("Load Address: %08x\n", (uint32_t)fhdr_v2->boot_data_ptr);
- printf("Entry Point: %08x\n", (uint32_t)fhdr_v2->entry);
+ print_header_info2(imxhdr);
+ if (hdr_v2->boot_data.plugin) {
+ uint32_t flash_offset =
+ hdr_v2->fhdr.self - hdr_v2->boot_data.start;
+ /* The 1st size includes flash offset and the next header */
+ uint32_t plugin_length = hdr_v2->boot_data.size - flash_offset
+ - offsetof(imx_header_v2_t, dcd_table);
+
+ imxhdr = (struct imx_header *)((char *)imxhdr + plugin_length);
+ print_header_info2(imxhdr);
+ }
}
static int cmd_cnt;
@@ -363,6 +364,24 @@ int skip_separators(struct data_src *ds)
}
}
+int skip_comma(struct data_src *ds)
+{
+ char *p = ds->p;
+
+ for (;;) {
+ char c = *p++;
+ if ((c == '#') || (c == '\r') || (c == '\n') || !c)
+ return 0;
+ if (c == ',') {
+ ds->p = p;
+ skip_separators(ds);
+ return 1;
+ }
+ if ((c != ' ') && (c == '\t'))
+ return 0;
+ }
+}
+
char *grab_token(char *dest, int size, char *src)
{
while (size) {
@@ -551,16 +570,18 @@ do_unary:
static int parse_cmd_data(struct data_src *ds)
{
uint32_t data[3];
- int ret = get_cfg_value(ds, &data[0]);
+ int ret, i;
- if (ret)
- return ret;
- ret = get_cfg_value(ds, &data[1]);
- if (ret)
- return ret;
- ret = get_cfg_value(ds, &data[2]);
- if (ret)
- return ret;
+ if (ds->plugin) {
+ fprintf(stderr, "DATA should be before plug command\n");
+ return -1;
+ }
+ for (i = 0; i < 3; i++) {
+ int ret = get_cfg_value(ds, &data[i]);
+ if (ret)
+ return ret;
+ skip_comma(ds); /* comma is optional */
+ }
ret = (*set_dcd_val)(ds->imxhdr, data);
if (ret)
return ret;
@@ -573,6 +594,99 @@ static int parse_cmd_data(struct data_src *ds)
return 0;
}
+static int get_data(struct data_src *ds, uint32_t *data, int cnt)
+{
+ int i = 0;
+
+ if (!ds->plugin) {
+ fprintf(stderr, "missing plug command\n");
+ return -1;
+ }
+ for (;;) {
+ int ret = get_cfg_value(ds, &data[i++]);
+ if (ret)
+ return ret;
+ if (i >= cnt)
+ break;
+ if (!skip_comma(ds))
+ break;
+ }
+ if (i < 2) {
+ fprintf(stderr, "missing ','\n");
+ return -1;
+ }
+ while (i < cnt) {
+ data[i] = data[i - 1];
+ i++;
+ }
+ if ((data[1] == ds->prev[1]) && (data[2] == ds->prev[2])
+ && (data[3] == ds->prev[3])
+ && (data[4] == ds->prev[4]))
+ i = 0;
+ else if ((data[1] == data[2]) && (data[2] == data[3])
+ && (data[3] == data[4]))
+ i = 1;
+ else if ((data[2] == data[3]) && (data[3] == data[4]))
+ i = 2;
+ else
+ i = 3;
+ return i;
+}
+
+static int store_data(struct data_src *ds, uint32_t *data, int cnt)
+{
+ int i;
+
+ for (i = 0; i < cnt; i++)
+ *p_entry++ = data[i];
+
+ ds->prev[1] = data[1];
+ ds->prev[2] = data[2];
+ ds->prev[3] = data[3];
+ ds->prev[4] = data[4];
+ if (p_entry > p_max_dcd) {
+ uint32_t size = (char *)p_max_dcd - (char *)ds->imxhdr;
+ fprintf(stderr, "Error: header exceeds maximum size(%d)\n",
+ size);
+ return -1;
+ }
+ return 0;
+}
+
+static int parse_iomux_entry(struct data_src *ds)
+{
+ uint32_t data[5];
+ int i;
+
+ i = get_data(ds, data, 5);
+ if (i < 0)
+ return i;
+ if (data[0] & (3 << 30)) {
+ fprintf(stderr, "bad 1st value\n");
+ return -1;
+ }
+ if (i < 3)
+ i++;
+ data[0] |= (i << 30);
+ return store_data(ds, data, (i == 3) ? 5 : i);
+}
+
+static int parse_write_entry(struct data_src *ds)
+{
+ uint32_t data[5];
+ int i;
+
+ i = get_data(ds, data, 5);
+ if (i < 0)
+ return i;
+ if (data[0] & 3) {
+ fprintf(stderr, "Address must be aligned on word boundary\n");
+ return -1;
+ }
+ data[0] |= i;
+ return store_data(ds, data, (i == 3) ? 5 : (i + 1));
+}
+
static int parse_image_version(struct data_src *ds)
{
int ret;
@@ -618,8 +732,82 @@ static int parse_boot_from(struct data_src *ds)
return 0;
}
+static int parse_plugin(struct data_src *ds)
+{
+ struct stat sbuf;
+ int plug_file;
+ unsigned char *ptr;
+ char *p;
+ char c;
+ int ret;
+ uint32_t plug_base;
+ uint32_t header_length;
+
+ if (g_flash_offset == FLASH_OFFSET_UNDEFINED) {
+ fprintf(stderr, "Error: Place BOOT_FROM before plugin\n");
+ return -1;
+ }
+ ret = get_cfg_value(ds, &plug_base);
+ if (ret)
+ return ret;
+
+ if (skip_separators(ds))
+ return -1;
+ p = ds->p;
+ for (;;) {
+ c = *p;
+ if (!c)
+ break;
+ if ((c == ' ') || (c == '\t') || (c == ';') || (c == '#')
+ || (c == '\r') || (c == '\n')) {
+ *p = 0;
+ break;
+ }
+ p++;
+ }
+ plug_file = open(ds->p, O_RDONLY|O_BINARY);
+ if (plug_file < 0) {
+ fprintf(stderr, "Can't open plugin file %s: %s\n",
+ ds->p, strerror(errno));
+ *p = c;
+ return -1;
+ }
+ if (fstat(plug_file, &sbuf) < 0) {
+ fprintf(stderr, "Can't stat %s: %s\n",
+ ds->p, strerror(errno));
+ close(plug_file);
+ return -1;
+ }
+ ptr = mmap(0, sbuf.st_size, PROT_READ, MAP_SHARED, plug_file, 0);
+ if (ptr == MAP_FAILED) {
+ fprintf(stderr, "Can't read %s: %s\n",
+ ds->p, strerror(errno));
+ return -1;
+ }
+ *p = c;
+ ds->p = p;
+ /* Set the plugin header */
+ header_length = (*set_imx_hdr)(ds->imxhdr, plug_base,
+ g_flash_offset, 1);
+
+ p = ((char *)ds->imxhdr) + header_length;
+ if ((p + sbuf.st_size) >= (char *)p_max_dcd) {
+ fprintf(stderr, "Out of space\n");
+ return -1;
+ }
+
+ ds->plugin = 1;
+ memcpy(p, ptr, sbuf.st_size);
+ munmap((void *)ptr, sbuf.st_size);
+ close(plug_file);
+
+ p_entry = (uint32_t *)(p + sbuf.st_size);
+ return 0;
+}
+
parse_fld_t cmd_table[] = {
- parse_image_version, parse_boot_from, parse_cmd_data
+ parse_image_version, parse_boot_from, parse_cmd_data, parse_plugin,
+ parse_iomux_entry, parse_write_entry
};
static int parse_command(struct data_src *ds)
@@ -630,9 +818,11 @@ static int parse_command(struct data_src *ds)
return cmd_table[cmd](ds);
}
-static void parse_cfg_file(struct imx_header *imxhdr, char *name)
+static void parse_cfg_file(struct imx_header *imxhdr, char *name,
+ uint32_t entry_point)
{
struct data_src ds;
+ uint32_t plugin_length = 0;
ds.line = NULL;
ds.len = 0;
@@ -662,6 +852,35 @@ static void parse_cfg_file(struct imx_header *imxhdr, char *name)
cmd_cnt++;
}
fclose(ds.fd);
+
+ if (ds.plugin) {
+ uint32_t header_length, more;
+ struct imx_header *next_imxhdr;
+
+ *p_entry++ = 0;
+ header_length = ((char *)p_entry) - ((char *)imxhdr);
+ plugin_length = ((header_length - 1) | 0x3f) + 1;
+ more = plugin_length - header_length;
+ if (more)
+ memset(p_entry, 0, more);
+ next_imxhdr = (struct imx_header *)
+ (((char *)imxhdr) + plugin_length);
+ p_entry = (imximage_version == IMXIMAGE_V1) ? (uint32_t *)
+ &next_imxhdr->header.hdr_v1.dcd_table.addr_data[0].type
+ : (uint32_t *)&next_imxhdr->header.hdr_v2.dcd_table;
+ if (p_entry > p_max_dcd) {
+ fprintf(stderr, "Out of space\n");
+ exit(EXIT_FAILURE);
+ }
+
+ /* Set the plugin size in header to include next header */
+ *header_size_ptr = ((char *)p_entry) - ((char *)imxhdr)
+ + g_flash_offset;
+ imxhdr = next_imxhdr;
+ }
+ /* Set the imx header */
+ imximage_params.header_size = (*set_imx_hdr)(imxhdr, entry_point,
+ g_flash_offset + plugin_length, 0) + plugin_length;
return;
}
@@ -727,7 +946,7 @@ int imximage_vrec_header(struct mkimage_params *params,
set_hdr_func(imxhdr);
/* Parse dcd configuration file */
- parse_cfg_file(imxhdr, params->imagename);
+ parse_cfg_file(imxhdr, params->imagename, params->ep);
/* Exit if there is no BOOT_FROM field specifying the flash_offset */
if (g_flash_offset == FLASH_OFFSET_UNDEFINED) {
@@ -735,9 +954,6 @@ int imximage_vrec_header(struct mkimage_params *params,
params->imagename);
exit(EXIT_FAILURE);
}
- /* Set the imx header */
- imximage_params.header_size = (*set_imx_hdr)(imxhdr, params->ep,
- g_flash_offset);
imximage_params.hdr = imxhdr;
return 0;
}
@@ -746,8 +962,10 @@ static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd,
struct mkimage_params *params)
{
/* Set the size in header */
- (*set_imx_size)((struct imx_header *)ptr, sbuf->st_size,
- g_flash_offset);
+ uint32_t offset = (char *)header_size_ptr - (char *)imximage_params.hdr;
+ uint32_t *p = (uint32_t *)((char *)ptr + offset);
+
+ *p = sbuf->st_size + g_flash_offset;
}
int imximage_check_params(struct mkimage_params *params)
diff --git a/tools/imximage.h b/tools/imximage.h
index efd249b..7613386 100644
--- a/tools/imximage.h
+++ b/tools/imximage.h
@@ -51,7 +51,10 @@
enum imximage_cmd {
CMD_IMAGE_VERSION,
CMD_BOOT_FROM,
- CMD_DATA
+ CMD_DATA,
+ CMD_PLUGIN,
+ CMD_IOMUX_ENTRY,
+ CMD_WRITE_ENTRY,
};
enum imximage_version {
@@ -158,6 +161,8 @@ struct data_src {
char *filename;
struct imx_header *imxhdr;
char *p;
+ int plugin;
+ uint32_t prev[5];
};
typedef int (*parse_fld_t)(struct data_src *ds);
@@ -165,8 +170,6 @@ typedef int (*parse_fld_t)(struct data_src *ds);
typedef int (*set_dcd_val_t)(struct imx_header *imxhdr, uint32_t *data);
typedef int (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t entry_point,
- uint32_t flash_offset);
-typedef void (*set_imx_size_t)(struct imx_header *imxhdr, uint32_t file_size,
- uint32_t flash_offset);
+ uint32_t flash_offset, int plugin);
#endif /* _IMXIMAGE_H_ */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 07/21] imximage.cfg: run files through C preprocessor
2012-09-22 2:38 ` [U-Boot] [PATCH V2 00/21] Add mx6solo/mx6duallite support Troy Kisky
` (5 preceding siblings ...)
2012-09-22 2:39 ` [U-Boot] [PATCH V2 06/21] imximage: add plugin commands Troy Kisky
@ 2012-09-22 2:39 ` Troy Kisky
2012-09-22 2:39 ` [U-Boot] [PATCH V2 08/21] mx6: add plugin file for use with imximage.cfg Troy Kisky
` (15 subsequent siblings)
22 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-09-22 2:39 UTC (permalink / raw)
To: u-boot
The '#' used as comments in the files cause the preprocessor
trouble, so change to /* */.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
Makefile | 3 +-
board/esg/ima3-mx53/imximage.cfg | 120 ++++++-----
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 90 ++++----
board/freescale/mx25pdk/imximage.cfg | 77 +++----
board/freescale/mx51evk/imximage.cfg | 114 +++++-----
board/freescale/mx53ard/imximage_dd3.cfg | 83 ++++----
board/freescale/mx53evk/imximage.cfg | 86 ++++----
board/freescale/mx53loco/imximage.cfg | 83 ++++----
board/freescale/mx53smd/imximage.cfg | 83 ++++----
board/freescale/mx6qarm2/imximage.cfg | 88 ++++----
board/genesi/mx51_efikamx/imximage_mx.cfg | 132 ++++++------
board/genesi/mx51_efikamx/imximage_sb.cfg | 126 +++++------
board/ttcontrol/vision2/imximage_hynix.cfg | 295 ++++++++++++++------------
13 files changed, 727 insertions(+), 653 deletions(-)
diff --git a/Makefile b/Makefile
index fe2f98c..edf647e 100644
--- a/Makefile
+++ b/Makefile
@@ -425,7 +425,8 @@ $(obj)u-boot.img: $(obj)u-boot.bin
-d $< $@
$(obj)u-boot.imx: $(obj)u-boot.bin
- $(obj)tools/mkimage -n $(CONFIG_IMX_CONFIG) -T imximage \
+ $(CC) -E -x c $(CONFIG_IMX_CONFIG) -I./include -o $(obj)imxcfg.imx
+ $(obj)tools/mkimage -n $(obj)imxcfg.imx -T imximage \
-e $(CONFIG_SYS_TEXT_BASE) -d $< $@
$(obj)u-boot.kwb: $(obj)u-boot.bin
diff --git a/board/esg/ima3-mx53/imximage.cfg b/board/esg/ima3-mx53/imximage.cfg
index fa6b42d..fce7492 100644
--- a/board/esg/ima3-mx53/imximage.cfg
+++ b/board/esg/ima3-mx53/imximage.cfg
@@ -1,50 +1,52 @@
-#
-# (C) Copyright 2012
-# Stefano Babic DENX Software Engineering sbabic at denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not write to the Free Software
-# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
-# MA 02110-1301 USA
-#
-# Refer docs/README.imxmage for more details about how-to configure
-# and create imximage boot image
-#
-# The syntax is taken as close as possible with the kwbimage
-
-# image version
+/*
+ * (C) Copyright 2012
+ * Stefano Babic DENX Software Engineering sbabic at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+/* image version */
IMAGE_VERSION 2
-# Boot Device : one of
-# spi, sd (the board has no nand neither onenand)
-
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
BOOT_FROM nor
-# Device Configuration Data (DCD)
-#
-# Each entry must have the format:
-# Addr-type Address Value
-#
-# where:
-# Addr-type register length (1,2 or 4 bytes)
-# Address absolute address of the register
-# value value to be stored in the register
-
-# IOMUX for RAM only
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+/* IOMUX for RAM only */
DATA 4 0x53fa8554 0x300020
DATA 4 0x53fa8560 0x300020
DATA 4 0x53fa8594 0x300020
@@ -72,37 +74,47 @@ DATA 4 0x53fa86fc 0x0
DATA 4 0x53fa86f4 0x0
DATA 4 0x53fa8714 0x0
DATA 4 0x53fa8724 0x4000000
-#
-# DDR RAM
+
+/* DDR RAM */
DATA 4 0x63fd9088 0x40404040
DATA 4 0x63fd9090 0x40404040
DATA 4 0x63fd907C 0x01420143
DATA 4 0x63fd9080 0x01450146
DATA 4 0x63fd9018 0x00111740
DATA 4 0x63fd9000 0x84190000
-# esdcfgX
+
+/* esdcfgX */
DATA 4 0x63fd900C 0x9f5152e3
DATA 4 0x63fd9010 0xb68e8a63
DATA 4 0x63fd9014 0x01ff00db
-# Read/Write command delay
+
+/* Read/Write command delay */
DATA 4 0x63fd902c 0x000026d2
-# Out of reset delays
+
+/* Out of reset delays */
DATA 4 0x63fd9030 0x00ff0e21
-# ESDCTL ODT timing control
+
+/* ESDCTL ODT timing control */
DATA 4 0x63fd9008 0x12273030
-# ESDCTL power down control
+
+/* ESDCTL power down control */
DATA 4 0x63fd9004 0x0002002d
-# Set registers in DDR memory chips
+
+/* Set registers in DDR memory chips */
DATA 4 0x63fd901c 0x00008032
DATA 4 0x63fd901c 0x00008033
DATA 4 0x63fd901c 0x00028031
DATA 4 0x63fd901c 0x052080b0
DATA 4 0x63fd901c 0x04008040
-# ESDCTL refresh control
+
+/* ESDCTL refresh control */
DATA 4 0x63fd9020 0x00005800
-# PHY ZQ HW control
+
+/* PHY ZQ HW control */
DATA 4 0x63fd9040 0x05380003
-# PHY ODT control
+
+/* PHY ODT control */
DATA 4 0x63fd9058 0x00022222
-# start DDR3
+
+/* start DDR3 */
DATA 4 0x63fd901c 0x00000000
diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
index 62498ab..c86cd40 100644
--- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
@@ -1,47 +1,51 @@
-# Copyright (C) 2011 Freescale Semiconductor, Inc.
-# Jason Liu <r64343@freescale.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not write to the Free Software
-# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
-# MA 02110-1301 USA
-#
-# Refer docs/README.imxmage for more details about how-to configure
-# and create imximage boot image
-#
-# The syntax is taken as close as possible with the kwbimage
-
-# image version
-
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * Jason Liu <r64343@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
IMAGE_VERSION 2
-# Boot Device : one of
-# spi, sd (the board has no nand neither onenand)
-
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
BOOT_FROM sd
-# Device Configuration Data (DCD)
-#
-# Each entry must have the format:
-# Addr-type Address Value
-#
-# where:
-# Addr-type register length (1,2 or 4 bytes)
-# Address absolute address of the register
-# value value to be stored in the register
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
DATA 4 0x020e05a8 0x00000030
DATA 4 0x020e05b0 0x00000030
DATA 4 0x020e0524 0x00000030
@@ -154,7 +158,7 @@ DATA 4 0x021b48b8 0x00000800
DATA 4 0x021b001c 0x00000000
DATA 4 0x021b0404 0x00011006
-# set the default clock gate to save power
+/* set the default clock gate to save power */
DATA 4 0x020c4068 0x00C03F3F
DATA 4 0x020c406c 0x0030FC03
DATA 4 0x020c4070 0x0FFFC000
@@ -163,8 +167,8 @@ DATA 4 0x020c4078 0x00FFF300
DATA 4 0x020c407c 0x0F0000C3
DATA 4 0x020c4080 0x000003FF
-# enable AXI cache for VDOA/VPU/IPU
+/* enable AXI cache for VDOA/VPU/IPU */
DATA 4 0x020e0010 0xF00000CF
-# set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
DATA 4 0x020e0018 0x007F007F
DATA 4 0x020e001c 0x007F007F
diff --git a/board/freescale/mx25pdk/imximage.cfg b/board/freescale/mx25pdk/imximage.cfg
index f7af7ff..c42a283 100644
--- a/board/freescale/mx25pdk/imximage.cfg
+++ b/board/freescale/mx25pdk/imximage.cfg
@@ -1,46 +1,49 @@
-#
-# (C) Copyright 2009
-# Stefano Babic DENX Software Engineering sbabic at denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# Refer docs/README.imxmage for more details about how-to configure
-# and create imximage boot image
-#
-# The syntax is taken as close as possible with the kwbimage
-
-# Boot Device : one of
-# spi, sd (the board has no nand neither onenand)
+/*
+ * (C) Copyright 2009
+ * Stefano Babic DENX Software Engineering sbabic at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
BOOT_FROM sd
-# Device Configuration Data (DCD)
-#
-# Each entry must have the format:
-# Addr-type Address Value
-#
-# where:
-# Addr-type register length (1,2 or 4 bytes)
-# Address absolute address of the register
-# value value to be stored in the register
-
-# EIM config-CS5 init -- CPLD
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+/* EIM config-CS5 init -- CPLD */
DATA 4 0xB8002050 0x0000D843
DATA 4 0xB8002054 0x22252521
DATA 4 0xB8002058 0x22220A00
-# DDR2 init
+/* DDR2 init */
DATA 4 0xB8001004 0x0076E83A
DATA 4 0xB8001010 0x00000204
DATA 4 0xB8001000 0x92210000
@@ -67,7 +70,7 @@ DATA 4 0x43FAC454 0x00001000
DATA 4 0x53F80008 0x20034000
-# Enable the clocks
+/* Enable the clocks */
DATA 4 0x53f8000c 0x1fffffff
DATA 4 0x53f80010 0xffffffff
DATA 4 0x53f80014 0xfdfff
diff --git a/board/freescale/mx51evk/imximage.cfg b/board/freescale/mx51evk/imximage.cfg
index a875e8f..3e141ee 100644
--- a/board/freescale/mx51evk/imximage.cfg
+++ b/board/freescale/mx51evk/imximage.cfg
@@ -1,46 +1,50 @@
-#
-# (C Copyright 2009
-# Stefano Babic DENX Software Engineering sbabic at denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not write to the Free Software
-# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
-# MA 02110-1301 USA
-#
-# Refer docs/README.imxmage for more details about how-to configure
-# and create imximage boot image
-#
-# The syntax is taken as close as possible with the kwbimage
-
-# Boot Device : one of
-# spi, sd (the board has no nand neither onenand)
+/*
+ * (C Copyright 2009
+ * Stefano Babic DENX Software Engineering sbabic at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
BOOT_FROM spi
-# Device Configuration Data (DCD)
-#
-# Each entry must have the format:
-# Addr-type Address Value
-#
-# where:
-# Addr-type register length (1,2 or 4 bytes)
-# Address absolute address of the register
-# value value to be stored in the register
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
-# Setting IOMUXC
+/* Setting IOMUXC */
DATA 4 0x73FA88a0 0x200
DATA 4 0x73FA850c 0x20c5
DATA 4 0x73FA8510 0x20c5
@@ -65,22 +69,24 @@ DATA 4 0x73FA88a4 0x6
DATA 4 0x73FA88ac 0x6
DATA 4 0x73FA88b8 0x6
-# Setting DDR for micron
-# 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
-# CAS=3 BL=4
-# ESDCTL_ESDCTL0
+/*
+ * Setting DDR for micron
+ * 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
+ * CAS=3 BL=4
+ */
+/* ESDCTL_ESDCTL0 */
DATA 4 0x83FD9000 0x82a20000
-# ESDCTL_ESDCTL1
+/* ESDCTL_ESDCTL1 */
DATA 4 0x83FD9008 0x82a20000
-# ESDCTL_ESDMISC
+/* ESDCTL_ESDMISC */
DATA 4 0x83FD9010 0x000ad0d0
-# ESDCTL_ESDCFG0
+/* ESDCTL_ESDCFG0 */
DATA 4 0x83FD9004 0x333574aa
-# ESDCTL_ESDCFG1
+/* ESDCTL_ESDCFG1 */
DATA 4 0x83FD900C 0x333574aa
-# Init DRAM on CS0
-# ESDCTL_ESDSCR
+/* Init DRAM on CS0 */
+/* ESDCTL_ESDSCR */
DATA 4 0x83FD9014 0x04008008
DATA 4 0x83FD9014 0x0000801a
DATA 4 0x83FD9014 0x0000801b
@@ -94,7 +100,7 @@ DATA 4 0x83FD9014 0x03808019
DATA 4 0x83FD9014 0x00408019
DATA 4 0x83FD9014 0x00008000
-# Init DRAM on CS1
+/* Init DRAM on CS1 */
DATA 4 0x83FD9014 0x0400800c
DATA 4 0x83FD9014 0x0000801e
DATA 4 0x83FD9014 0x0000801f
@@ -108,12 +114,12 @@ DATA 4 0x83FD9014 0x0380801d
DATA 4 0x83FD9014 0x0040801d
DATA 4 0x83FD9014 0x00008004
-# Write to CTL0
+/* Write to CTL0 */
DATA 4 0x83FD9000 0xb2a20000
-# Write to CTL1
+/* Write to CTL1 */
DATA 4 0x83FD9008 0xb2a20000
-# ESDMISC
+/* ESDMISC */
DATA 4 0x83FD9010 0x000ad6d0
-#ESDCTL_ESDCDLYGD
+/* ESDCTL_ESDCDLYGD */
DATA 4 0x83FD9034 0x90000000
DATA 4 0x83FD9014 0x00000000
diff --git a/board/freescale/mx53ard/imximage_dd3.cfg b/board/freescale/mx53ard/imximage_dd3.cfg
index 614d29e..4633e4d 100644
--- a/board/freescale/mx53ard/imximage_dd3.cfg
+++ b/board/freescale/mx53ard/imximage_dd3.cfg
@@ -1,48 +1,51 @@
-#
-# (C) Copyright 2009
-# Stefano Babic DENX Software Engineering sbabic at denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not write to the Free Software
-# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
-# MA 02110-1301 USA
-#
-# Refer docs/README.imxmage for more details about how-to configure
-# and create imximage boot image
-#
-# The syntax is taken as close as possible with the kwbimage
-
-# image version
+/*
+ * (C) Copyright 2009
+ * Stefano Babic DENX Software Engineering sbabic at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+/* image version */
IMAGE_VERSION 2
-# Boot Device : one of
-# spi, sd (the board has no nand neither onenand)
-
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
BOOT_FROM sd
-# Device Configuration Data (DCD)
-#
-# Each entry must have the format:
-# Addr-type Address Value
-#
-# where:
-# Addr-type register length (1,2 or 4 bytes)
-# Address absolute address of the register
-# value value to be stored in the register
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
DATA 4 0x53fa8554 0x00300000
DATA 4 0x53fa8558 0x00300040
DATA 4 0x53fa8560 0x00300000
diff --git a/board/freescale/mx53evk/imximage.cfg b/board/freescale/mx53evk/imximage.cfg
index 915fb2c..1cd61d5 100644
--- a/board/freescale/mx53evk/imximage.cfg
+++ b/board/freescale/mx53evk/imximage.cfg
@@ -1,50 +1,52 @@
-#
-# (C Copyright 2009
-# Stefano Babic DENX Software Engineering sbabic at denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not write to the Free Software
-# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
-# MA 02110-1301 USA
-#
-# Refer docs/README.imxmage for more details about how-to configure
-# and create imximage boot image
-#
-# The syntax is taken as close as possible with the kwbimage
-
-# image version
+/*
+ * (C Copyright 2009
+ * Stefano Babic DENX Software Engineering sbabic at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+/* image version */
IMAGE_VERSION 2
-# Boot Device : one of
-# spi, sd (the board has no nand neither onenand)
-
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
BOOT_FROM sd
-# Device Configuration Data (DCD)
-#
-# Each entry must have the format:
-# Addr-type Address Value
-#
-# where:
-# Addr-type register length (1,2 or 4 bytes)
-# Address absolute address of the register
-# value value to be stored in the register
-
-# Setting IOMUXC
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+/* Setting IOMUXC */
DATA 4 0x53fa8554 0x00200000
DATA 4 0x53fa8560 0x00200000
DATA 4 0x53fa8594 0x00200000
diff --git a/board/freescale/mx53loco/imximage.cfg b/board/freescale/mx53loco/imximage.cfg
index 2ce5f8d..e6b90c1 100644
--- a/board/freescale/mx53loco/imximage.cfg
+++ b/board/freescale/mx53loco/imximage.cfg
@@ -1,48 +1,51 @@
-# Copyright (C) 2011 Freescale Semiconductor, Inc.
-# Jason Liu <r64343@freescale.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not write to the Free Software
-# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
-# MA 02110-1301 USA
-#
-# Refer docs/README.imxmage for more details about how-to configure
-# and create imximage boot image
-#
-# The syntax is taken as close as possible with the kwbimage
-
-# image version
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * Jason Liu <r64343@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+/* image version */
IMAGE_VERSION 2
-# Boot Device : one of
-# spi, sd (the board has no nand neither onenand)
-
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
BOOT_FROM sd
-# Device Configuration Data (DCD)
-#
-# Each entry must have the format:
-# Addr-type Address Value
-#
-# where:
-# Addr-type register length (1,2 or 4 bytes)
-# Address absolute address of the register
-# value value to be stored in the register
-
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
DATA 4 0x53fa8554 0x00300000
DATA 4 0x53fa8558 0x00300040
DATA 4 0x53fa8560 0x00300000
diff --git a/board/freescale/mx53smd/imximage.cfg b/board/freescale/mx53smd/imximage.cfg
index 614d29e..4633e4d 100644
--- a/board/freescale/mx53smd/imximage.cfg
+++ b/board/freescale/mx53smd/imximage.cfg
@@ -1,48 +1,51 @@
-#
-# (C) Copyright 2009
-# Stefano Babic DENX Software Engineering sbabic at denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not write to the Free Software
-# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
-# MA 02110-1301 USA
-#
-# Refer docs/README.imxmage for more details about how-to configure
-# and create imximage boot image
-#
-# The syntax is taken as close as possible with the kwbimage
-
-# image version
+/*
+ * (C) Copyright 2009
+ * Stefano Babic DENX Software Engineering sbabic at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+/* image version */
IMAGE_VERSION 2
-# Boot Device : one of
-# spi, sd (the board has no nand neither onenand)
-
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
BOOT_FROM sd
-# Device Configuration Data (DCD)
-#
-# Each entry must have the format:
-# Addr-type Address Value
-#
-# where:
-# Addr-type register length (1,2 or 4 bytes)
-# Address absolute address of the register
-# value value to be stored in the register
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
DATA 4 0x53fa8554 0x00300000
DATA 4 0x53fa8558 0x00300040
DATA 4 0x53fa8560 0x00300000
diff --git a/board/freescale/mx6qarm2/imximage.cfg b/board/freescale/mx6qarm2/imximage.cfg
index bf941a3..4ed211e 100644
--- a/board/freescale/mx6qarm2/imximage.cfg
+++ b/board/freescale/mx6qarm2/imximage.cfg
@@ -1,47 +1,51 @@
-# Copyright (C) 2011 Freescale Semiconductor, Inc.
-# Jason Liu <r64343@freescale.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not write to the Free Software
-# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
-# MA 02110-1301 USA
-#
-# Refer docs/README.imxmage for more details about how-to configure
-# and create imximage boot image
-#
-# The syntax is taken as close as possible with the kwbimage
-
-# image version
-
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * Jason Liu <r64343@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
IMAGE_VERSION 2
-# Boot Device : one of
-# spi, sd (the board has no nand neither onenand)
-
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
BOOT_FROM sd
-# Device Configuration Data (DCD)
-#
-# Each entry must have the format:
-# Addr-type Address Value
-#
-# where:
-# Addr-type register length (1,2 or 4 bytes)
-# Address absolute address of the register
-# value value to be stored in the register
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
DATA 4 0x020e05a8 0x00000030
DATA 4 0x020e05b0 0x00000030
DATA 4 0x020e0524 0x00000030
@@ -166,8 +170,8 @@ DATA 4 0x020c4078 0x00FFF300
DATA 4 0x020c407c 0x0F0000C3
DATA 4 0x020c4080 0x000003FF
-# enable AXI cache for VDOA/VPU/IPU
+/* enable AXI cache for VDOA/VPU/IPU */
DATA 4 0x020e0010 0xF00000CF
-# set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
DATA 4 0x020e0018 0x007F007F
DATA 4 0x020e001c 0x007F007F
diff --git a/board/genesi/mx51_efikamx/imximage_mx.cfg b/board/genesi/mx51_efikamx/imximage_mx.cfg
index 38fa760..21ff6d6 100644
--- a/board/genesi/mx51_efikamx/imximage_mx.cfg
+++ b/board/genesi/mx51_efikamx/imximage_mx.cfg
@@ -1,52 +1,58 @@
-#
-# Copyright (C) 2009 Pegatron Corporation
-# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
-# Copyright (C) 2009-2012 Genesi USA, Inc.
-#
-# BASED ON: imx51evk
-#
-# (C) Copyright 2009
-# Stefano Babic DENX Software Engineering sbabic at denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not write to the Free Software
-# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
-# MA 02110-1301 USA
-#
-# Refer docs/README.imxmage for more details about how-to configure
-# and create imximage boot image
-#
-# The syntax is taken as close as possible with the kwbimage
+/*
+ * Copyright (C) 2009 Pegatron Corporation
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ * Copyright (C) 2009-2012 Genesi USA, Inc.
+ *
+ * BASED ON: imx51evk
+ *
+ * (C) Copyright 2009
+ * Stefano Babic DENX Software Engineering sbabic at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
-# Boot Device : one of
-# spi, sd (the board has no nand neither onenand)
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
BOOT_FROM spi
-# Device Configuration Data (DCD)
-#
-# Each entry must have the format:
-# Addr-type Address Value
-#
-# where:
-# Addr-type register length (1,2 or 4 bytes)
-# Address absolute address of the register
-# value value to be stored in the register
-
-# Essential GPIO settings to be done as early as possible
-# PCBIDn pad settings are all the defaults except #2 which needs HVE off
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+/*
+ * Essential GPIO settings to be done as early as possible
+ * PCBIDn pad settings are all the defaults except #2 which needs HVE off
+ */
DATA 4 0x73fa8134 0x3 # PCBID0 ALT3 GPIO 3_16
DATA 4 0x73fa8130 0x3 # PCBID1 ALT3 GPIO 3_17
DATA 4 0x73fa8128 0x3 # PCBID2 ALT3 GPIO 3_11
@@ -55,7 +61,7 @@ DATA 4 0x73fa8198 0x3 # LED0 ALT3 GPIO 3_13
DATA 4 0x73fa81c4 0x3 # LED1 ALT3 GPIO 3_14
DATA 4 0x73fa81c8 0x3 # LED2 ALT3 GPIO 3_15
-# DDR bus IOMUX PAD settings
+/* DDR bus IOMUX PAD settings */
DATA 4 0x73fa850c 0x20c5 # SDODT1
DATA 4 0x73fa8510 0x20c5 # SDODT0
DATA 4 0x73fa84ac 0xc5 # SDWE
@@ -72,22 +78,24 @@ DATA 4 0x73fa84d8 0xc5 # DRAM_DQM1
DATA 4 0x73fa84dc 0xc5 # DRAM_DQM2
DATA 4 0x73fa84e0 0xc5 # DRAM_DQM3
-# Setting DDR for micron
-# 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
-# CAS=3 BL=4
-# ESDCTL_ESDCTL0
+/*
+ * Setting DDR for micron
+ * 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
+ * CAS=3 BL=4
+ */
+/* ESDCTL_ESDCTL0 */
DATA 4 0x83fd9000 0x82a20000
-# ESDCTL_ESDCTL1
+/* ESDCTL_ESDCTL1 */
DATA 4 0x83fd9008 0x82a20000
-# ESDCTL_ESDMISC
+/* ESDCTL_ESDMISC */
DATA 4 0x83fd9010 0xcaaaf6d0
-# ESDCTL_ESDCFG0
+/* ESDCTL_ESDCFG0 */
DATA 4 0x83fd9004 0x3f3574aa
-# ESDCTL_ESDCFG1
+/* ESDCTL_ESDCFG1 */
DATA 4 0x83fd900c 0x3f3574aa
-# Init DRAM on CS0
-# ESDCTL_ESDSCR
+/* Init DRAM on CS0 */
+/* ESDCTL_ESDSCR */
DATA 4 0x83fd9014 0x04008008
DATA 4 0x83fd9014 0x0000801a
DATA 4 0x83fd9014 0x0000801b
@@ -101,7 +109,7 @@ DATA 4 0x83fd9014 0x03808019
DATA 4 0x83fd9014 0x00408019
DATA 4 0x83fd9014 0x00008000
-# Init DRAM on CS1
+/* Init DRAM on CS1 */
DATA 4 0x83fd9014 0x0400800c
DATA 4 0x83fd9014 0x0000801e
DATA 4 0x83fd9014 0x0000801f
@@ -115,12 +123,12 @@ DATA 4 0x83fd9014 0x0380801d
DATA 4 0x83fd9014 0x0040801d
DATA 4 0x83fd9014 0x00008004
-# Write to CTL0
+/* Write to CTL0 */
DATA 4 0x83fd9000 0xb2a20000
-# Write to CTL1
+/* Write to CTL1 */
DATA 4 0x83fd9008 0xb2a20000
-# ESDMISC
+/* ESDMISC */
DATA 4 0x83fd9010 0x000ad6d0
-#ESDCTL_ESDCDLYGD
+/* ESDCTL_ESDCDLYGD */
DATA 4 0x83fd9034 0x90000000
DATA 4 0x83fd9014 0x00000000
diff --git a/board/genesi/mx51_efikamx/imximage_sb.cfg b/board/genesi/mx51_efikamx/imximage_sb.cfg
index 26d259f..7ddd0b1 100644
--- a/board/genesi/mx51_efikamx/imximage_sb.cfg
+++ b/board/genesi/mx51_efikamx/imximage_sb.cfg
@@ -1,51 +1,55 @@
-#
-# Copyright (C) 2009 Pegatron Corporation
-# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
-# Copyright (C) 2009-2012 Genesi USA, Inc.
-#
-# BASED ON: imx51evk
-#
-# (C) Copyright 2009
-# Stefano Babic DENX Software Engineering sbabic at denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not write to the Free Software
-# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
-# MA 02110-1301 USA
-#
-# Refer docs/README.imxmage for more details about how-to configure
-# and create imximage boot image
-#
-# The syntax is taken as close as possible with the kwbimage
+/*
+ * Copyright (C) 2009 Pegatron Corporation
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ * Copyright (C) 2009-2012 Genesi USA, Inc.
+ *
+ * BASED ON: imx51evk
+ *
+ * (C) Copyright 2009
+ * Stefano Babic DENX Software Engineering sbabic at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
-# Boot Device : one of
-# spi, sd (the board has no nand neither onenand)
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
BOOT_FROM spi
-# Device Configuration Data (DCD)
-#
-# Each entry must have the format:
-# Addr-type Address Value
-#
-# where:
-# Addr-type register length (1,2 or 4 bytes)
-# Address absolute address of the register
-# value value to be stored in the register
-
-# DDR bus IOMUX PAD settings
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+*/
+/* DDR bus IOMUX PAD settings */
DATA 4 0x73fa88a0 0x200 # GRP_INMODE1
DATA 4 0x73fa850c 0x20c5 # SDODT1
DATA 4 0x73fa8510 0x20c5 # SDODT0
@@ -62,22 +66,24 @@ DATA 4 0x73fa84b4 0xe5 # SDCKE1
DATA 4 0x73fa84cc 0xe5 # DRAM_CS0
DATA 4 0x73fa84d0 0xe4 # DRAM_CS1
-# Setting DDR for micron
-# 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
-# CAS=3 BL=4
-# ESDCTL_ESDCTL0
+/*
+ * Setting DDR for micron
+ * 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
+ * CAS=3 BL=4
+ */
+/* ESDCTL_ESDCTL0 */
DATA 4 0x83fd9000 0x82a20000
-# ESDCTL_ESDCTL1
+/* ESDCTL_ESDCTL1 */
DATA 4 0x83fd9008 0x82a20000
-# ESDCTL_ESDMISC
+/* ESDCTL_ESDMISC */
DATA 4 0x83fd9010 0xcaaaf6d0
-# ESDCTL_ESDCFG0
+/* ESDCTL_ESDCFG0 */
DATA 4 0x83fd9004 0x333574aa
-# ESDCTL_ESDCFG1
+/* ESDCTL_ESDCFG1 */
DATA 4 0x83fd900c 0x333574aa
-# Init DRAM on CS0
-# ESDCTL_ESDSCR
+/* Init DRAM on CS0 */
+/* ESDCTL_ESDSCR */
DATA 4 0x83fd9014 0x04008008
DATA 4 0x83fd9014 0x0000801a
DATA 4 0x83fd9014 0x0000801b
@@ -91,7 +97,7 @@ DATA 4 0x83fd9014 0x03808019
DATA 4 0x83fd9014 0x00408019
DATA 4 0x83fd9014 0x00008000
-# Init DRAM on CS1
+/* Init DRAM on CS1 */
DATA 4 0x83fd9014 0x0400800c
DATA 4 0x83fd9014 0x0000801e
DATA 4 0x83fd9014 0x0000801f
@@ -105,12 +111,12 @@ DATA 4 0x83fd9014 0x0380801d
DATA 4 0x83fd9014 0x0042801d
DATA 4 0x83fd9014 0x00008004
-# Write to CTL0
+/* Write to CTL0 */
DATA 4 0x83fd9000 0xb2a20000
-# Write to CTL1
+/* Write to CTL1 */
DATA 4 0x83fd9008 0xb2a20000
-# ESDMISC
+/* ESDMISC */
DATA 4 0x83fd9010 0xcaaaf6d0
-#ESDCTL_ESDCDLYGD
+/* ESDCTL_ESDCDLYGD */
DATA 4 0x83fd9034 0x90000000
DATA 4 0x83fd9014 0x00000000
diff --git a/board/ttcontrol/vision2/imximage_hynix.cfg b/board/ttcontrol/vision2/imximage_hynix.cfg
index ed531db..c1de94f 100644
--- a/board/ttcontrol/vision2/imximage_hynix.cfg
+++ b/board/ttcontrol/vision2/imximage_hynix.cfg
@@ -1,209 +1,228 @@
-#
-# (C) Copyright 2009
-# Stefano Babic DENX Software Engineering sbabic at denx.de.
-#
-# (C) Copyright 2010
-# Klaus Steinhammer TTECH Control Gmbh kst at tttech.com
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not write to the Free Software
-# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
-# MA 02110-1301 USA
-#
-# Refer docs/README.imxmage for more details about how-to configure
-# and create imximage boot image
-#
-# The syntax is taken as close as possible with the kwbimage
-
-# Boot Device : one of
-# spi, nand, onenand, sd
-
+/*
+ * (C) Copyright 2009
+ * Stefano Babic DENX Software Engineering sbabic at denx.de.
+ *
+ * (C) Copyright 2010
+ * Klaus Steinhammer TTECH Control Gmbh kst at tttech.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/*
+ * Boot Device : one of
+ * spi, nand, onenand, sd
+ */
BOOT_FROM spi
-# Device Configuration Data (DCD)
-#
-# Each entry must have the format:
-# Addr-type Address Value
-#
-# where:
-# Addr-type register length (1,2 or 4 bytes)
-# Address absolute address of the register
-# value value to be stored in the register
-
-#######################
-### Disable WDOG ###
-#######################
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+/*
+ * #######################
+ * ### Disable WDOG ###
+ * #######################
+ */
DATA 2 0x73f98000 0x30
-#######################
-### SET DDR Clk ###
-#######################
-
-# CCM: CBMCR - ddr_clk_sel: axi_b (133MHz)
+/*
+ * #######################
+ * ### SET DDR Clk ###
+ * #######################
+ */
+/* CCM: CBMCR - ddr_clk_sel: axi_b (133MHz) */
DATA 4 0x73FD4018 0x000024C0
-# DOUBLE SPI CLK (13MHz->26 MHz Clock)
+/* DOUBLE SPI CLK (13MHz->26 MHz Clock) */
DATA 4 0x73FD4038 0x2010241
-#IOMUXC_SW_PAD_CTL_PAD_CSPI1_MOSI HYS_ENABLE | DRV_MAX | SRE_FAST
+/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_MOSI HYS_ENABLE | DRV_MAX | SRE_FAST */
DATA 4 0x73fa8600 0x00000107
-#IOMUXC_SW_PAD_CTL_PAD_CSPI1_MISO HYS_ENABLE | DRV_MAX | SRE_FAST
+/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_MISO HYS_ENABLE | DRV_MAX | SRE_FAST */
DATA 4 0x73fa8604 0x00000107
-#IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS0 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST
+/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS0 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST */
DATA 4 0x73fa8608 0x00000187
-#IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS1 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST
+/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS1 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST */
DATA 4 0x73fa860c 0x00000187
-#IOMUXC_SW_PAD_CTL_PAD_CSPI1_SCLK HYS_ENABLE | DRV_MAX | SRE_FAST
+/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SCLK HYS_ENABLE | DRV_MAX | SRE_FAST */
DATA 4 0x73fa8614 0x00000107
-#IOMUXC_SW_PAD_CTL_PAD_DI1_PIN11 HYS_ENABLE | DRV_MAX | SRE_FAST (CSPI1_SS2)
+/* IOMUXC_SW_PAD_CTL_PAD_DI1_PIN11 HYS_ENABLE | DRV_MAX | SRE_FAST (CSPI1_SS2) */
DATA 4 0x73fa86a8 0x00000187
-#######################
-### Settings IOMUXC ###
-#######################
-
-# DDR IOMUX configuration
-# Control, Data, Address pads are in their default state: HIGH DS, FAST SR.
-# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK MAX DS
+/*
+ * #######################
+ * ### Settings IOMUXC ###
+ * #######################
+ */
+/*
+ * DDR IOMUX configuration
+ * Control, Data, Address pads are in their default state: HIGH DS, FAST SR.
+ * IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK MAX DS
+ */
DATA 4 0x73fa84b8 0x000000e7
-# PVTC MAX (at GPC, PGR reg)
-#DATA 4 0x73FD8004 0x1fc00000
+/* PVTC MAX (at GPC, PGR reg) */
+/* DATA 4 0x73FD8004 0x1fc00000 */
-#DQM0 DS high slew rate slow
+/* DQM0 DS high slew rate slow */
DATA 4 0x73fa84d4 0x000000e4
-#DQM1 DS high slew rate slow
+/* DQM1 DS high slew rate slow */
DATA 4 0x73fa84d8 0x000000e4
-#DQM2 DS high slew rate slow
+/* DQM2 DS high slew rate slow */
DATA 4 0x73fa84dc 0x000000e4
-#DQM3 DS high slew rate slow
+/* DQM3 DS high slew rate slow */
DATA 4 0x73fa84e0 0x000000e4
-#IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 DS high & SLEW slow
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 DS high & SLEW slow */
DATA 4 0x73fa84bc 0x000000c4
-#IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 DS high & SLEW slow
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 DS high & SLEW slow */
DATA 4 0x73fa84c0 0x000000c4
-#IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 DS high & SLEW slow
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 DS high & SLEW slow */
DATA 4 0x73fa84c4 0x000000c4
-#IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 DS high & SLEW slow
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 DS high & SLEW slow */
DATA 4 0x73fa84c8 0x000000c4
-#DRAM_DATA B0
+/* DRAM_DATA B0 */
DATA 4 0x73fa88a4 0x00000004
-#DRAM_DATA B1
+/* DRAM_DATA B1 */
DATA 4 0x73fa88ac 0x00000004
-#DRAM_DATA B2
+/* DRAM_DATA B2 */
DATA 4 0x73fa88b8 0x00000004
-#DRAM_DATA B3
+/* DRAM_DATA B3 */
DATA 4 0x73fa882c 0x00000004
-#DRAM_DATA B0 slew rate
+/* DRAM_DATA B0 slew rate */
DATA 4 0x73fa8878 0x00000000
-#DRAM_DATA B1 slew rate
+/* DRAM_DATA B1 slew rate */
DATA 4 0x73fa8880 0x00000000
-#DRAM_DATA B2 slew rate
+/* DRAM_DATA B2 slew rate */
DATA 4 0x73fa888c 0x00000000
-#DRAM_DATA B3 slew rate
+/* DRAM_DATA B3 slew rate */
DATA 4 0x73fa889c 0x00000000
-#######################
-### Configure SDRAM ###
-#######################
+/*
+ * #######################
+ * ### Configure SDRAM ###
+ * #######################
+ */
-# Configure CS0
-#######################
+/* Configure CS0 */
+/* ####################### */
-# ESDCTL0: Enable controller
+/* ESDCTL0: Enable controller */
DATA 4 0x83fd9000 0x83220000
-# Init DRAM on CS0
-# ESDSCR: Precharge command
+/* Init DRAM on CS0 /
+/* ESDSCR: Precharge command */
DATA 4 0x83fd9014 0x04008008
-# ESDSCR: Refresh command
+/* ESDSCR: Refresh command */
DATA 4 0x83fd9014 0x00008010
-# ESDSCR: Refresh command
+/* ESDSCR: Refresh command */
DATA 4 0x83fd9014 0x00008010
-# ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8)
+/* ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8) */
DATA 4 0x83fd9014 0x00338018
-# ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51)
+/* ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51) */
DATA 4 0x83fd9014 0x0020801a
-# ESDSCR
+/* ESDSCR */
DATA 4 0x83fd9014 0x00008000
-# ESDSCR: EMR with full Drive strength
-#DATA 4 0x83fd9014 0x0000801a
+/* ESDSCR: EMR with full Drive strength */
+/* DATA 4 0x83fd9014 0x0000801a */
-# ESDCTL0: 14 ROW, 10 COL, 32Bit, SREF=8
+/* ESDCTL0: 14 ROW, 10 COL, 32Bit, SREF=8 */
DATA 4 0x83fd9000 0xC3220000
-# ESDCFG0: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
-# tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
-#DATA 4 0x83fd9004 0xC33574AA
-
-#micron mDDR
-# ESDCFG0: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks
-# tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
-#DATA 4 0x83FD9004 0x101564a8
-
-#hynix mDDR
-# ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks
-# tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
+/*
+ * ESDCFG0: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
+ * tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
+ * DATA 4 0x83fd9004 0xC33574AA
+ */
+/*
+ * micron mDDR
+ * ESDCFG0: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks
+ * tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
+ * DATA 4 0x83FD9004 0x101564a8
+ */
+/*
+ * hynix mDDR
+ * ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks
+ * tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
+ */
DATA 4 0x83FD9004 0x704564a8
-# ESDMISC: AP=10, Bank interleaving on, MIF3 en, RALAT=2
+/* ESDMISC: AP=10, Bank interleaving on, MIF3 en, RALAT=2 */
DATA 4 0x83fd9010 0x000a1700
-# Configure CS1
-#######################
+/* Configure CS1 */
+/* ####################### */
-# ESDCTL1: Enable controller
+/* ESDCTL1: Enable controller */
DATA 4 0x83fd9008 0x83220000
-# Init DRAM on CS1
-# ESDSCR: Precharge command
+/* Init DRAM on CS1 */
+/* ESDSCR: Precharge command */
DATA 4 0x83fd9014 0x0400800c
-# ESDSCR: Refresh command
+/* ESDSCR: Refresh command */
DATA 4 0x83fd9014 0x00008014
-# ESDSCR: Refresh command
+/* ESDSCR: Refresh command */
DATA 4 0x83fd9014 0x00008014
-# ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8)
+/* ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8) */
DATA 4 0x83fd9014 0x0033801c
-# ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51)
+/* ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51) */
DATA 4 0x83fd9014 0x0020801e
-# ESDSCR
+/* ESDSCR */
DATA 4 0x83fd9014 0x00008004
-# ESDCTL1: 14 ROW, 10 COL, 32Bit, SREF=8
+/* ESDCTL1: 14 ROW, 10 COL, 32Bit, SREF=8 */
DATA 4 0x83fd9008 0xC3220000
-
-# ESDCFG1: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
-# tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
-#DATA 4 0x83fd900c 0xC33574AA
-
-#micron mDDR
-# ESDCFG1: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks
-# tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
-#DATA 4 0x83FD900C 0x101564a8
-
-#hynix mDDR
-# ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks
-# tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
+/*
+ * ESDCFG1: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
+ * tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
+ * DATA 4 0x83fd900c 0xC33574AA
+ */
+/*
+ * micron mDDR
+ * ESDCFG1: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks
+ * tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
+ * DATA 4 0x83FD900C 0x101564a8
+ */
+/*
+ * hynix mDDR
+ * ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks
+ * tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
+ */
DATA 4 0x83FD900C 0x704564a8
-# ESDSCR (mDRAM configuration finished)
+/* ESDSCR (mDRAM configuration finished) */
DATA 4 0x83FD9014 0x00000004
-# ESDSCR - clear "configuration request" bit
+/* ESDSCR - clear "configuration request" bit */
DATA 4 0x83fd9014 0x00000000
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 08/21] mx6: add plugin file for use with imximage.cfg
2012-09-22 2:38 ` [U-Boot] [PATCH V2 00/21] Add mx6solo/mx6duallite support Troy Kisky
` (6 preceding siblings ...)
2012-09-22 2:39 ` [U-Boot] [PATCH V2 07/21] imximage.cfg: run files through C preprocessor Troy Kisky
@ 2012-09-22 2:39 ` Troy Kisky
2012-09-22 4:06 ` Vikram Narayanan
2012-09-23 10:17 ` Stefano Babic
2012-09-22 2:39 ` [U-Boot] [PATCH V2 09/21] mx6q_4x_mt41j128.cfg: use symbols instead of hardcoded constants Troy Kisky
` (14 subsequent siblings)
22 siblings, 2 replies; 430+ messages in thread
From: Troy Kisky @ 2012-09-22 2:39 UTC (permalink / raw)
To: u-boot
The "plugin" command of mkimage can take this
file as an argument.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
arch/arm/cpu/armv7/mx6/Makefile | 5 +-
arch/arm/cpu/armv7/mx6/plugin.S | 164 ++++++++++++++++++++++++++++++
arch/arm/include/asm/arch-mx6/imx-regs.h | 1 +
3 files changed, 169 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/cpu/armv7/mx6/plugin.S
diff --git a/arch/arm/cpu/armv7/mx6/Makefile b/arch/arm/cpu/armv7/mx6/Makefile
index cbce411..b1fce4e 100644
--- a/arch/arm/cpu/armv7/mx6/Makefile
+++ b/arch/arm/cpu/armv7/mx6/Makefile
@@ -33,11 +33,14 @@ SOBJS = lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
-all: $(obj).depend $(LIB)
+all: $(obj).depend $(LIB) plugin.bin
$(LIB): $(OBJS)
$(call cmd_link_o_target, $(OBJS))
+plugin.bin: plugin.o
+ $(OBJCOPY) -O binary --gap-fill 0xff $< $@
+
#########################################################################
# defines $(obj).depend target
diff --git a/arch/arm/cpu/armv7/mx6/plugin.S b/arch/arm/cpu/armv7/mx6/plugin.S
new file mode 100644
index 0000000..99c6b20
--- /dev/null
+++ b/arch/arm/cpu/armv7/mx6/plugin.S
@@ -0,0 +1,164 @@
+/*
+ * Copyright (C) 2012 Boundary Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+#include <config.h>
+#include <asm/arch/imx-regs.h>
+
+#define HAB_RVT_ENTRY 0x98
+#define HAB_RVT_FAIL_SAFE_VECT 0xbc
+#define HAB_RVT_LOAD_DATA 0xc8
+
+#define HDR_SELF_PTR 0x14
+#define HDR_BOOT_DATA 0x20
+#define HDR_IMAGE_LEN 0x24
+
+#define L2X0_CTRL 0x100
+#define SCU_CONFIG 0x004
+
+/*
+ * Disable L2 cache because ROM will turn it on when a plugin is used.
+ * There are cache coherence problems if cache is on when Linux kernel
+ * expects it to be off.
+ */
+.macro disable_l2_cache
+ ldr r1, =L2_BASE_ADDR
+ mov r0, #0x0
+ str r0, [r1, #L2X0_CTRL]
+.endm
+
+
+/*
+ * plugin_start(void **start, size_t *bytes, UINT32 *ivt_offset)
+ */
+plugin_start:
+/* Save the return address and the function arguments */
+ push {r0-r8, lr}
+
+/* r0-r2 must be >= 0x100 and must be 4 byte aligned */
+ cmp r0, #0x100
+ cmphs r1, #0x100
+ cmphs r2, #0x100
+
+/* rCPU: 22 - mx6q, 12 - mx6dl, 12|0x100 - solo, 2 - sololite */
+#define rCPU r2
+#define rIomux r3
+#define rVal0 r4 /* mx6q value */
+#define rVal1 r5 /* mx6dl value */
+#define rVal2 r6 /* mx6solo value */
+#define rVal3 r7 /* mx6sololite value */
+#define rFlag lr
+#define rTable r8
+
+ orr rFlag, r0, r1
+ orr rFlag, rFlag, r2
+ orrlo rFlag, rFlag, #1
+
+ mov rCPU, #22 /* mx6q */
+ mov r1, #SCU_BASE_ADDR
+ ldr r0, [r1, #SCU_CONFIG]
+ and r0, r0, #3
+ cmp r0, #3 /* is mx6q? */
+ movne rCPU, #12 /* mx6dl */
+ cmpne r0, #1 /* is mx6dl? */
+ movne rCPU, #2 /* mx6 sololite */
+
+ ldrne r1, =ANATOP_BASE_ADDR
+ ldrne r0, [r1, #0x280]
+ movne r0, r0, LSR #16
+ cmpne r0, #0x60 /* is mx6 Sololite? */
+ movne rCPU, #12 | 0x100 /* Solo */
+
+ mov rVal0, #0
+ mov rVal1, #0
+ mov rVal2, #0
+ mov rVal3, #0
+ ldr rIomux, =IOMUXC_BASE_ADDR
+ adr rTable, mx6_table
+ b 3f
+
+1: movs r0, r1, LSR #30
+ beq 2f
+ mov r1, r1, LSL rCPU
+ movs r1, r1, LSR #32-10
+ addne r1, rIomux, r1, LSL #2
+ cmp r0, #3
+ subne r0, r0, #1
+ orr r1, r1, r0
+
+2: ands r0, r1, #3
+ bic r1, r1, #3
+ ldrne rVal0, [rTable], #4
+ movne rVal1, rVal0
+ movne rVal2, rVal0
+ movne rVal3, rVal0
+ subnes r0, r0, #1
+ ldrne rVal1, [rTable], #4
+ movne rVal2, rVal1
+ movne rVal3, rVal1
+ subnes r0, r0, #1
+ ldrne rVal2, [rTable], #4
+ ldrne rVal3, [rTable], #4
+
+ mov r0, rVal0
+ cmp rCPU, #22
+ movne r0, rVal1
+ cmpne rCPU, #12
+ movne r0, rVal2
+ cmpne rCPU, #12|0x100
+ movne r0, rVal3
+ cmp r1, #0
+ strne r0, [r1]
+3: ldr r1, [rTable], #4
+ cmp r1, #0
+ bne 1b
+
+ tst rFlag, #3
+ bne 4f /* Branch if not called as plugin */
+/* Align end of table to 64 byte boundary */
+ sub rTable, rTable, #1
+ orr rTable, rTable, #0x3f
+ add rTable, rTable, #1
+ ldr r2, [rTable, #HDR_SELF_PTR]
+ ldr r0, [rTable, #HDR_BOOT_DATA]
+ ldr r1, [rTable, #HDR_IMAGE_LEN]
+ sub rTable, r2, r0
+ mov r2, r0
+ mov r3, r1
+ mov r4, #0
+ push {r0-r4}
+ mov r0, #HAB_RVT_LOAD_DATA
+ ldr r4, [r0]
+ mov r0, sp
+ add r1, sp, #4
+ add r2, sp, #8
+ blx r4
+
+ disable_l2_cache
+ pop {r4, r5}
+ add sp, sp, #12
+ pop {r0-r3}
+/*
+ * Before returning to ROM, we need to fill the return values arguments
+ * to our function.
+ * plugin_start(void **start, size_t *bytes, UINT32 *ivt_offset)
+ */
+
+ str r4, [r0]
+ str r5, [r1]
+ str rTable, [r2]
+ mov r0, #1
+ pop {r4-r8, pc}
+
+/* Not called as plugin */
+4: popne {r0-r8, lr}
+ mov r0, #HAB_RVT_ENTRY
+ ldr lr, [r0]
+ blx lr
+ mov r0, #HAB_RVT_FAIL_SAFE_VECT
+ ldr lr, [r0]
+ blx lr
+
+ .ltorg
+mx6_table:
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 8834c59..5c133b2 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -48,6 +48,7 @@
#define GLOBAL_TIMER_BASE_ADDR 0x00A00200
#define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600
#define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000
+#define L2_BASE_ADDR 0x00A02000
#define GPV0_BASE_ADDR 0x00B00000
#define GPV1_BASE_ADDR 0x00C00000
#define PCIE_ARB_BASE_ADDR 0x01000000
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 09/21] mx6q_4x_mt41j128.cfg: use symbols instead of hardcoded constants
2012-09-22 2:38 ` [U-Boot] [PATCH V2 00/21] Add mx6solo/mx6duallite support Troy Kisky
` (7 preceding siblings ...)
2012-09-22 2:39 ` [U-Boot] [PATCH V2 08/21] mx6: add plugin file for use with imximage.cfg Troy Kisky
@ 2012-09-22 2:39 ` Troy Kisky
2012-09-22 2:39 ` [U-Boot] [PATCH V2 10/21] mx6q_4x_mt41j128.cfg: allow plugin to work Troy Kisky
` (13 subsequent siblings)
22 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-09-22 2:39 UTC (permalink / raw)
To: u-boot
This allows us to generate plugin data or
DCD rom style data simply by defining USE_PLUGIN
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
arch/arm/include/asm/arch-mx6/imx-mkimage.h | 177 ++++++++++++++++++
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 248 +++++++++++++-------------
2 files changed, 304 insertions(+), 121 deletions(-)
create mode 100644 arch/arm/include/asm/arch-mx6/imx-mkimage.h
diff --git a/arch/arm/include/asm/arch-mx6/imx-mkimage.h b/arch/arm/include/asm/arch-mx6/imx-mkimage.h
new file mode 100644
index 0000000..be71983
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/imx-mkimage.h
@@ -0,0 +1,177 @@
+/*
+ * Copyright (C) 2012 Boundary Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+#ifndef __ASM_ARCH_IMX_MKIMAGE_H__
+#define __ASM_ARCH_IMX_MKIMAGE_H__
+
+/* mx6 duallite and solo have same offsets */
+/*
+ * Bits 31:30 :
+ * 0 : 29:2 absolute address, 1:0 # of data values,
+ * followed by 0,1,2,4 data values
+ * 0 means repeat last data value
+ * 1 : iomuxc relative address, 9:0 mx6q offset, 19:10 mx6dl/solo offset,
+ * 29:20 mx6_sololite offset, 0 offset means skip if this processor
+ * previous data repeated
+ * 2 : same as 1, but single data value follows
+ * 3 : same as 1, but 4 data values follow
+ *
+ * data order is mx6q, mx6dl, mx6solo, mx6_sololite
+ * if no data given, repeat previous line data
+ * if not all data given, repeat prior value
+ */
+#define MA(mx6q, mx6dl_solo, mx6sololite) ((mx6q / 4 & 0x3ff) | \
+ ((mx6dl_solo / 4 & 0x3ff) * 0x400) | \
+ ((mx6sololite / 4 & 0x3ff) * 0x100000))
+
+#define IOM_DRAM_DQM0 MA(0x5ac, 0x470, 0x0)
+#define IOM_DRAM_DQM1 MA(0x5b4, 0x474, 0x0)
+#define IOM_DRAM_DQM2 MA(0x528, 0x478, 0x0)
+#define IOM_DRAM_DQM3 MA(0x520, 0x47c, 0x0)
+#define IOM_DRAM_DQM4 MA(0x514, 0x480, 0x0)
+#define IOM_DRAM_DQM5 MA(0x510, 0x484, 0x0)
+#define IOM_DRAM_DQM6 MA(0x5bc, 0x488, 0x0)
+#define IOM_DRAM_DQM7 MA(0x5c4, 0x48c, 0x0)
+
+#define IOM_DRAM_CAS MA(0x56c, 0x464, 0x0)
+#define IOM_DRAM_RAS MA(0x578, 0x490, 0x0)
+#define IOM_DRAM_RESET MA(0x57c, 0x494, 0x0)
+#define IOM_DRAM_SDCLK_0 MA(0x588, 0x4ac, 0x0)
+#define IOM_DRAM_SDCLK_1 MA(0x594, 0x4b0, 0x0)
+#define IOM_DRAM_SDBA2 MA(0x58c, 0x4a0, 0x0)
+#define IOM_DRAM_SDCKE0 MA(0x590, 0x4a4, 0x0)
+#define IOM_DRAM_SDCKE1 MA(0x598, 0x4a8, 0x0)
+#define IOM_DRAM_SDODT0 MA(0x59c, 0x4b4, 0x0)
+#define IOM_DRAM_SDODT1 MA(0x5a0, 0x4b8, 0x0)
+
+#define IOM_DRAM_SDQS0 MA(0x5a8, 0x4bc, 0x0)
+#define IOM_DRAM_SDQS1 MA(0x5b0, 0x4c0, 0x0)
+#define IOM_DRAM_SDQS2 MA(0x524, 0x4c4, 0x0)
+#define IOM_DRAM_SDQS3 MA(0x51c, 0x4c8, 0x0)
+#define IOM_DRAM_SDQS4 MA(0x518, 0x4cc, 0x0)
+#define IOM_DRAM_SDQS5 MA(0x50c, 0x4d0, 0x0)
+#define IOM_DRAM_SDQS6 MA(0x5b8, 0x4d4, 0x0)
+#define IOM_DRAM_SDQS7 MA(0x5c0, 0x4d8, 0x0)
+
+#define IOM_GRP_B0DS MA(0x784, 0x764, 0x0)
+#define IOM_GRP_B1DS MA(0x788, 0x770, 0x0)
+#define IOM_GRP_B2DS MA(0x794, 0x778, 0x0)
+#define IOM_GRP_B3DS MA(0x79c, 0x77c, 0x0)
+#define IOM_GRP_B4DS MA(0x7a0, 0x780, 0x0)
+#define IOM_GRP_B5DS MA(0x7a4, 0x784, 0x0)
+#define IOM_GRP_B6DS MA(0x7a8, 0x78c, 0x0)
+#define IOM_GRP_B7DS MA(0x748, 0x748, 0x0)
+#define IOM_GRP_ADDDS MA(0x74c, 0x74c, 0x0)
+#define IOM_DDRMODE_CTL MA(0x750, 0x750, 0x0)
+#define IOM_GRP_DDRPKE MA(0x758, 0x754, 0x0)
+#define IOM_GRP_DDRMODE MA(0x774, 0x760, 0x0)
+#define IOM_GRP_CTLDS MA(0x78c, 0x76c, 0x0)
+#define IOM_GRP_DDR_TYPE MA(0x798, 0x774, 0x0)
+
+#define MMDC_P0 0x021b0000
+#define MMDC_P1 0x021b4000
+#define IOMUXC_BASE_ADDR 0x020e0000
+#define CCM_BASE 0x020C4000
+#define IRAM_FREE_START 0x00907000
+
+#define IOMUXC_GPR4 (IOMUXC_BASE_ADDR + 0x010)
+#define IOMUXC_GPR6 (IOMUXC_BASE_ADDR + 0x018)
+#define IOMUXC_GPR7 (IOMUXC_BASE_ADDR + 0x01c)
+
+#define MMDC_MDCTL 0x000
+#define MMDC_MDPDC 0x004
+#define MMDC_MDOTC 0x008
+#define MMDC_MDCFG0 0x00c
+#define MMDC_MDCFG1 0x010
+#define MMDC_MDCFG2 0x014
+#define MMDC_MDMISC 0x018
+#define MMDC_MDSCR 0x01c
+#define MMDC_MDREF 0x020
+#define MMDC_MDRWD 0x02c
+#define MMDC_MDOR 0x030
+#define MMDC_MDASP 0x040
+#define MMDC_MAPSR 0x404
+#define MMDC_MPZQHWCTRL 0x800
+#define MMDC_MPWLDECTRL0 0x80c
+#define MMDC_MPWLDECTRL1 0x810
+#define MMDC_MPODTCTRL 0x818
+#define MMDC_MPRDDQBY0DL 0x81c
+#define MMDC_MPRDDQBY1DL 0x820
+#define MMDC_MPRDDQBY2DL 0x824
+#define MMDC_MPRDDQBY3DL 0x828
+#define MMDC_MPDGCTRL0 0x83c
+#define MMDC_MPDGCTRL1 0x840
+#define MMDC_MPRDDLCTL 0x848
+#define MMDC_MPWRDLCTL 0x850
+#define MMDC_MPMUR0 0x8b8
+
+#define CCM_CCGR0 0x068
+#define CCM_CCGR1 0x06c
+#define CCM_CCGR2 0x070
+#define CCM_CCGR3 0x074
+#define CCM_CCGR4 0x078
+#define CCM_CCGR5 0x07c
+#define CCM_CCGR6 0x080
+
+
+#ifdef USE_PLUGIN
+#define IOMUX_ENTRY(addr, args...) iomux_entry addr, args
+#define IOMUX_ENTRY1(addr, q) IOMUX_ENTRY(addr, q)
+#define IOMUX_ENTRY2(addr, q, dl) IOMUX_ENTRY(addr, q, dl)
+#define IOMUX_ENTRY3(addr, q, dl, solo) IOMUX_ENTRY(addr, q, dl, solo)
+#define IOMUX_ENTRY4(addr, q, dl, solo, sl) IOMUX_ENTRY(addr, q, dl, solo, sl)
+#define WRITE_ENTRY(addr, args...) write_entry addr, args
+#define WRITE_ENTRY1(addr, q) WRITE_ENTRY(addr, q)
+#define WRITE_ENTRY2(addr, q, dl) WRITE_ENTRY(addr, q, dl)
+#define WRITE_ENTRY3(addr, q, dl, solo) WRITE_ENTRY(addr, q, dl, solo)
+#define WRITE_ENTRY4(addr, q, dl, solo, sl) WRITE_ENTRY(addr, q, dl, solo, sl)
+#else
+
+#define IOMUX_ADDR(addr, div) (IOMUXC_BASE_ADDR + \
+ ((((addr) / (div)) & 0x3ff) * 4))
+#define IOMUX_ENTRY1(addr, q) DATA 4, IOMUX_ADDR(addr, _FOR_DIV), q
+#define WRITE_ENTRY1(addr, q) DATA 4, addr, q
+#ifdef FOR_MX6Q
+#define _FOR_DIV 1
+#define IOMUX_ENTRY2(addr, q, dl) IOMUX_ENTRY1(addr, q)
+#define WRITE_ENTRY2(addr, q, dl) WRITE_ENTRY1(addr, q)
+#define IOMUX_ENTRY3(addr, q, dl, solo) IOMUX_ENTRY1(addr, q)
+#define WRITE_ENTRY3(addr, q, dl, solo) WRITE_ENTRY1(addr, q)
+#define IOMUX_ENTRY4(addr, q, dl, solo, sl) IOMUX_ENTRY1(addr, q)
+#define WRITE_ENTRY4(addr, q, dl, solo, sl) WRITE_ENTRY1(addr, q)
+#else
+
+#define IOMUX_ENTRY2(addr, q, dl) IOMUX_ENTRY1(addr, dl)
+#define WRITE_ENTRY2(addr, q, dl) WRITE_ENTRY1(addr, dl)
+#ifdef FOR_MX6DL
+#define _FOR_DIV 0x400
+#define IOMUX_ENTRY3(addr, q, dl, solo) IOMUX_ENTRY1(addr, dl)
+#define WRITE_ENTRY3(addr, q, dl, solo) WRITE_ENTRY1(addr, dl)
+#define IOMUX_ENTRY4(addr, q, dl, solo, sl) IOMUX_ENTRY1(addr, dl)
+#define WRITE_ENTRY4(addr, q, dl, solo, sl) WRITE_ENTRY1(addr, dl)
+#else
+
+#define IOMUX_ENTRY3(addr, q, dl, solo) IOMUX_ENTRY1(addr, solo)
+#define WRITE_ENTRY3(addr, q, dl, solo) WRITE_ENTRY1(addr, solo)
+#ifdef FOR_MX6SOLO
+#define _FOR_DIV 0x400
+#define IOMUX_ENTRY4(addr, q, dl, solo, sl) IOMUX_ENTRY1(addr, solo)
+#define WRITE_ENTRY4(addr, q, dl, solo, sl) WRITE_ENTRY1(addr, solo)
+#else
+
+#define IOMUX_ENTRY4(addr, q, dl, solo, sl) IOMUX_ENTRY1(addr, sl)
+#define WRITE_ENTRY4(addr, q, dl, solo, sl) WRITE_ENTRY1(addr, sl)
+#ifdef FOR_MX6SOLOLITE
+#define _FOR_DIV 0x100000
+#else
+
+#error "Please select cpu"
+#endif /* FOR_MX6SOLOLITE */
+#endif /* FOR_MX6SOLO */
+#endif /* FOR_MX6DL */
+#endif /* FOR_MX6Q */
+#endif /* USE_PLUGIN */
+
+#endif /*__ASM_ARCH_IMX_MKIMAGE_H__ */
diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
index c86cd40..a95831f 100644
--- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
@@ -25,6 +25,9 @@
*
* The syntax is taken as close as possible with the kwbimage
*/
+#define FOR_MX6Q
+
+#include <asm/arch/imx-mkimage.h>
/* image version */
IMAGE_VERSION 2
@@ -35,6 +38,9 @@ IMAGE_VERSION 2
*/
BOOT_FROM sd
+#ifdef USE_PLUGIN
+ plugin IRAM_FREE_START+0x42c arch/arm/cpu/armv7/mx6/plugin.bin
+#endif
/*
* Device Configuration Data (DCD)
*
@@ -46,129 +52,129 @@ BOOT_FROM sd
* Address absolute address of the register
* value value to be stored in the register
*/
-DATA 4 0x020e05a8 0x00000030
-DATA 4 0x020e05b0 0x00000030
-DATA 4 0x020e0524 0x00000030
-DATA 4 0x020e051c 0x00000030
-
-DATA 4 0x020e0518 0x00000030
-DATA 4 0x020e050c 0x00000030
-DATA 4 0x020e05b8 0x00000030
-DATA 4 0x020e05c0 0x00000030
-
-DATA 4 0x020e05ac 0x00020030
-DATA 4 0x020e05b4 0x00020030
-DATA 4 0x020e0528 0x00020030
-DATA 4 0x020e0520 0x00020030
-
-DATA 4 0x020e0514 0x00020030
-DATA 4 0x020e0510 0x00020030
-DATA 4 0x020e05bc 0x00020030
-DATA 4 0x020e05c4 0x00020030
-
-DATA 4 0x020e056c 0x00020030
-DATA 4 0x020e0578 0x00020030
-DATA 4 0x020e0588 0x00020030
-DATA 4 0x020e0594 0x00020030
-
-DATA 4 0x020e057c 0x00020030
-DATA 4 0x020e0590 0x00003000
-DATA 4 0x020e0598 0x00003000
-DATA 4 0x020e058c 0x00000000
-
-DATA 4 0x020e059c 0x00003030
-DATA 4 0x020e05a0 0x00003030
-DATA 4 0x020e0784 0x00000030
-DATA 4 0x020e0788 0x00000030
-
-DATA 4 0x020e0794 0x00000030
-DATA 4 0x020e079c 0x00000030
-DATA 4 0x020e07a0 0x00000030
-DATA 4 0x020e07a4 0x00000030
-
-DATA 4 0x020e07a8 0x00000030
-DATA 4 0x020e0748 0x00000030
-DATA 4 0x020e074c 0x00000030
-DATA 4 0x020e0750 0x00020000
-
-DATA 4 0x020e0758 0x00000000
-DATA 4 0x020e0774 0x00020000
-DATA 4 0x020e078c 0x00000030
-DATA 4 0x020e0798 0x000C0000
-
-DATA 4 0x021b081c 0x33333333
-DATA 4 0x021b0820 0x33333333
-DATA 4 0x021b0824 0x33333333
-DATA 4 0x021b0828 0x33333333
-
-DATA 4 0x021b481c 0x33333333
-DATA 4 0x021b4820 0x33333333
-DATA 4 0x021b4824 0x33333333
-DATA 4 0x021b4828 0x33333333
-
-DATA 4 0x021b0018 0x00081740
-
-DATA 4 0x021b001c 0x00008000
-DATA 4 0x021b000c 0x555A7975
-DATA 4 0x021b0010 0xFF538E64
-DATA 4 0x021b0014 0x01FF00DB
-DATA 4 0x021b002c 0x000026D2
-
-DATA 4 0x021b0030 0x005B0E21
-DATA 4 0x021b0008 0x09444040
-DATA 4 0x021b0004 0x00025576
-DATA 4 0x021b0040 0x00000027
-DATA 4 0x021b0000 0x831A0000
-
-DATA 4 0x021b001c 0x04088032
-DATA 4 0x021b001c 0x0408803A
-DATA 4 0x021b001c 0x00008033
-DATA 4 0x021b001c 0x0000803B
-DATA 4 0x021b001c 0x00428031
-DATA 4 0x021b001c 0x00428039
-DATA 4 0x021b001c 0x09408030
-DATA 4 0x021b001c 0x09408038
-
-DATA 4 0x021b001c 0x04008040
-DATA 4 0x021b001c 0x04008048
-DATA 4 0x021b0800 0xA1380003
-DATA 4 0x021b4800 0xA1380003
-DATA 4 0x021b0020 0x00005800
-DATA 4 0x021b0818 0x00022227
-DATA 4 0x021b4818 0x00022227
-
-DATA 4 0x021b083c 0x434B0350
-DATA 4 0x021b0840 0x034C0359
-DATA 4 0x021b483c 0x434B0350
-DATA 4 0x021b4840 0x03650348
-DATA 4 0x021b0848 0x4436383B
-DATA 4 0x021b4848 0x39393341
-DATA 4 0x021b0850 0x35373933
-DATA 4 0x021b4850 0x48254A36
-
-DATA 4 0x021b080c 0x001F001F
-DATA 4 0x021b0810 0x001F001F
-
-DATA 4 0x021b480c 0x00440044
-DATA 4 0x021b4810 0x00440044
-
-DATA 4 0x021b08b8 0x00000800
-DATA 4 0x021b48b8 0x00000800
-
-DATA 4 0x021b001c 0x00000000
-DATA 4 0x021b0404 0x00011006
+IOMUX_ENTRY1(IOM_DRAM_SDQS0, 0x00000030)
+IOMUX_ENTRY1(IOM_DRAM_SDQS1, 0x00000030)
+IOMUX_ENTRY1(IOM_DRAM_SDQS2, 0x00000030)
+IOMUX_ENTRY1(IOM_DRAM_SDQS3, 0x00000030)
+
+IOMUX_ENTRY1(IOM_DRAM_SDQS4, 0x00000030)
+IOMUX_ENTRY1(IOM_DRAM_SDQS5, 0x00000030)
+IOMUX_ENTRY1(IOM_DRAM_SDQS6, 0x00000030)
+IOMUX_ENTRY1(IOM_DRAM_SDQS7, 0x00000030)
+
+IOMUX_ENTRY1(IOM_DRAM_DQM0, 0x00020030)
+IOMUX_ENTRY1(IOM_DRAM_DQM1, 0x00020030)
+IOMUX_ENTRY1(IOM_DRAM_DQM2, 0x00020030)
+IOMUX_ENTRY1(IOM_DRAM_DQM3, 0x00020030)
+
+IOMUX_ENTRY1(IOM_DRAM_DQM4, 0x00020030)
+IOMUX_ENTRY1(IOM_DRAM_DQM5, 0x00020030)
+IOMUX_ENTRY1(IOM_DRAM_DQM6, 0x00020030)
+IOMUX_ENTRY1(IOM_DRAM_DQM7, 0x00020030)
+
+IOMUX_ENTRY1(IOM_DRAM_CAS, 0x00020030)
+IOMUX_ENTRY1(IOM_DRAM_RAS, 0x00020030)
+IOMUX_ENTRY1(IOM_DRAM_SDCLK_0, 0x00020030)
+IOMUX_ENTRY1(IOM_DRAM_SDCLK_1, 0x00020030)
+
+IOMUX_ENTRY1(IOM_DRAM_RESET, 0x00020030)
+IOMUX_ENTRY1(IOM_DRAM_SDCKE0, 0x00003000)
+IOMUX_ENTRY1(IOM_DRAM_SDCKE1, 0x00003000)
+IOMUX_ENTRY1(IOM_DRAM_SDBA2, 0x00000000)
+
+IOMUX_ENTRY1(IOM_DRAM_SDODT0, 0x00003030)
+IOMUX_ENTRY1(IOM_DRAM_SDODT1, 0x00003030)
+IOMUX_ENTRY1(IOM_GRP_B0DS, 0x00000030)
+IOMUX_ENTRY1(IOM_GRP_B1DS, 0x00000030)
+
+IOMUX_ENTRY1(IOM_GRP_B2DS, 0x00000030)
+IOMUX_ENTRY1(IOM_GRP_B3DS, 0x00000030)
+IOMUX_ENTRY1(IOM_GRP_B4DS, 0x00000030)
+IOMUX_ENTRY1(IOM_GRP_B5DS, 0x00000030)
+
+IOMUX_ENTRY1(IOM_GRP_B6DS, 0x00000030)
+IOMUX_ENTRY1(IOM_GRP_B7DS, 0x00000030)
+IOMUX_ENTRY1(IOM_GRP_ADDDS, 0x00000030)
+IOMUX_ENTRY1(IOM_DDRMODE_CTL, 0x00020000)
+
+IOMUX_ENTRY1(IOM_GRP_DDRPKE, 0x00000000)
+IOMUX_ENTRY1(IOM_GRP_DDRMODE, 0x00020000)
+IOMUX_ENTRY1(IOM_GRP_CTLDS, 0x00000030)
+IOMUX_ENTRY1(IOM_GRP_DDR_TYPE, 0x000C0000)
+
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPRDDQBY0DL, 0x33333333)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPRDDQBY1DL, 0x33333333)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPRDDQBY2DL, 0x33333333)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPRDDQBY3DL, 0x33333333)
+
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPRDDQBY0DL, 0x33333333)
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPRDDQBY1DL, 0x33333333)
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPRDDQBY2DL, 0x33333333)
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPRDDQBY3DL, 0x33333333)
+
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDMISC, 0x00081740)
+
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x00008000)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDCFG0, 0x555A7975)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDCFG1, 0xFF538E64)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDCFG2, 0x01FF00DB)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDRWD, 0x000026D2)
+
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDOR, 0x005B0E21)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDOTC, 0x09444040)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDPDC, 0x00025576)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDASP, 0x00000027)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDCTL, 0x831A0000)
+
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x04088032)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x0408803A)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x00008033)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x0000803B)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x00428031)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x00428039)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x09408030)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x09408038)
+
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x04008040)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x04008048)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPZQHWCTRL, 0xA1380003)
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPZQHWCTRL, 0xA1380003)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDREF, 0x00005800)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPODTCTRL, 0x00022227)
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPODTCTRL, 0x00022227)
+
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPDGCTRL0, 0x434B0350)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPDGCTRL1, 0x034C0359)
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPDGCTRL0, 0x434B0350)
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPDGCTRL1, 0x03650348)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPRDDLCTL, 0x4436383B)
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPRDDLCTL, 0x39393341)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPWRDLCTL, 0x35373933)
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPWRDLCTL, 0x48254A36)
+
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPWLDECTRL0, 0x001F001F)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPWLDECTRL1, 0x001F001F)
+
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPWLDECTRL0, 0x00440044)
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPWLDECTRL1, 0x00440044)
+
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPMUR0, 0x00000800)
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPMUR0, 0x00000800)
+
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x00000000)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MAPSR, 0x00011006)
/* set the default clock gate to save power */
-DATA 4 0x020c4068 0x00C03F3F
-DATA 4 0x020c406c 0x0030FC03
-DATA 4 0x020c4070 0x0FFFC000
-DATA 4 0x020c4074 0x3FF00000
-DATA 4 0x020c4078 0x00FFF300
-DATA 4 0x020c407c 0x0F0000C3
-DATA 4 0x020c4080 0x000003FF
+WRITE_ENTRY1(CCM_BASE + CCM_CCGR0, 0x00C03F3F)
+WRITE_ENTRY1(CCM_BASE + CCM_CCGR1, 0x0030FC03)
+WRITE_ENTRY1(CCM_BASE + CCM_CCGR2, 0x0FFFC000)
+WRITE_ENTRY1(CCM_BASE + CCM_CCGR3, 0x3FF00000)
+WRITE_ENTRY1(CCM_BASE + CCM_CCGR4, 0x00FFF300)
+WRITE_ENTRY1(CCM_BASE + CCM_CCGR5, 0x0F0000C3)
+WRITE_ENTRY1(CCM_BASE + CCM_CCGR6, 0x000003FF)
/* enable AXI cache for VDOA/VPU/IPU */
-DATA 4 0x020e0010 0xF00000CF
+WRITE_ENTRY1(IOMUXC_GPR4, 0xF00000CF)
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-DATA 4 0x020e0018 0x007F007F
-DATA 4 0x020e001c 0x007F007F
+WRITE_ENTRY1(IOMUXC_GPR6, 0x007F007F)
+WRITE_ENTRY1(IOMUXC_GPR7, 0x007F007F)
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 10/21] mx6q_4x_mt41j128.cfg: allow plugin to work
2012-09-22 2:38 ` [U-Boot] [PATCH V2 00/21] Add mx6solo/mx6duallite support Troy Kisky
` (8 preceding siblings ...)
2012-09-22 2:39 ` [U-Boot] [PATCH V2 09/21] mx6q_4x_mt41j128.cfg: use symbols instead of hardcoded constants Troy Kisky
@ 2012-09-22 2:39 ` Troy Kisky
2012-09-22 2:39 ` [U-Boot] [PATCH V2 11/21] mx6q_4x_mt41j128.cfg: enable plugin mode Troy Kisky
` (12 subsequent siblings)
22 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-09-22 2:39 UTC (permalink / raw)
To: u-boot
Enabling plugin mode seems to require this additional
memory write for ddr3 initialization.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 2 ++
1 file changed, 2 insertions(+)
diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
index a95831f..eea8d3a 100644
--- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
@@ -111,6 +111,8 @@ WRITE_ENTRY1(MMDC_P1 + MMDC_MPRDDQBY0DL, 0x33333333)
WRITE_ENTRY1(MMDC_P1 + MMDC_MPRDDQBY1DL, 0x33333333)
WRITE_ENTRY1(MMDC_P1 + MMDC_MPRDDQBY2DL, 0x33333333)
WRITE_ENTRY1(MMDC_P1 + MMDC_MPRDDQBY3DL, 0x33333333)
+/* MDPDC - CKE pulse width = 3 cycles. CKSRE = 6 cycles, CKSRX = 6 cycles */
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDPDC, 0x00020036)
WRITE_ENTRY1(MMDC_P0 + MMDC_MDMISC, 0x00081740)
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 11/21] mx6q_4x_mt41j128.cfg: enable plugin mode
2012-09-22 2:38 ` [U-Boot] [PATCH V2 00/21] Add mx6solo/mx6duallite support Troy Kisky
` (9 preceding siblings ...)
2012-09-22 2:39 ` [U-Boot] [PATCH V2 10/21] mx6q_4x_mt41j128.cfg: allow plugin to work Troy Kisky
@ 2012-09-22 2:39 ` Troy Kisky
2012-09-22 2:39 ` [U-Boot] [PATCH V2 12/21] mx6q_4x_mt41j128.cfg: add comments Troy Kisky
` (11 subsequent siblings)
22 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-09-22 2:39 UTC (permalink / raw)
To: u-boot
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
index eea8d3a..2af4265 100644
--- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
@@ -26,7 +26,7 @@
* The syntax is taken as close as possible with the kwbimage
*/
#define FOR_MX6Q
-
+#define USE_PLUGIN
#include <asm/arch/imx-mkimage.h>
/* image version */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 12/21] mx6q_4x_mt41j128.cfg: add comments
2012-09-22 2:38 ` [U-Boot] [PATCH V2 00/21] Add mx6solo/mx6duallite support Troy Kisky
` (10 preceding siblings ...)
2012-09-22 2:39 ` [U-Boot] [PATCH V2 11/21] mx6q_4x_mt41j128.cfg: enable plugin mode Troy Kisky
@ 2012-09-22 2:39 ` Troy Kisky
2012-09-22 2:39 ` [U-Boot] [PATCH V2 13/21] mx6q_4x_mt41j128.cfg: use ddr3 mode for reset Troy Kisky
` (10 subsequent siblings)
22 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-09-22 2:39 UTC (permalink / raw)
To: u-boot
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 56 ++++++++++++++++++++++----
1 file changed, 48 insertions(+), 8 deletions(-)
diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
index 2af4265..3a1f1bc 100644
--- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
@@ -56,7 +56,6 @@ IOMUX_ENTRY1(IOM_DRAM_SDQS0, 0x00000030)
IOMUX_ENTRY1(IOM_DRAM_SDQS1, 0x00000030)
IOMUX_ENTRY1(IOM_DRAM_SDQS2, 0x00000030)
IOMUX_ENTRY1(IOM_DRAM_SDQS3, 0x00000030)
-
IOMUX_ENTRY1(IOM_DRAM_SDQS4, 0x00000030)
IOMUX_ENTRY1(IOM_DRAM_SDQS5, 0x00000030)
IOMUX_ENTRY1(IOM_DRAM_SDQS6, 0x00000030)
@@ -66,7 +65,6 @@ IOMUX_ENTRY1(IOM_DRAM_DQM0, 0x00020030)
IOMUX_ENTRY1(IOM_DRAM_DQM1, 0x00020030)
IOMUX_ENTRY1(IOM_DRAM_DQM2, 0x00020030)
IOMUX_ENTRY1(IOM_DRAM_DQM3, 0x00020030)
-
IOMUX_ENTRY1(IOM_DRAM_DQM4, 0x00020030)
IOMUX_ENTRY1(IOM_DRAM_DQM5, 0x00020030)
IOMUX_ENTRY1(IOM_DRAM_DQM6, 0x00020030)
@@ -84,67 +82,108 @@ IOMUX_ENTRY1(IOM_DRAM_SDBA2, 0x00000000)
IOMUX_ENTRY1(IOM_DRAM_SDODT0, 0x00003030)
IOMUX_ENTRY1(IOM_DRAM_SDODT1, 0x00003030)
+
IOMUX_ENTRY1(IOM_GRP_B0DS, 0x00000030)
IOMUX_ENTRY1(IOM_GRP_B1DS, 0x00000030)
-
IOMUX_ENTRY1(IOM_GRP_B2DS, 0x00000030)
IOMUX_ENTRY1(IOM_GRP_B3DS, 0x00000030)
IOMUX_ENTRY1(IOM_GRP_B4DS, 0x00000030)
IOMUX_ENTRY1(IOM_GRP_B5DS, 0x00000030)
-
IOMUX_ENTRY1(IOM_GRP_B6DS, 0x00000030)
IOMUX_ENTRY1(IOM_GRP_B7DS, 0x00000030)
+
IOMUX_ENTRY1(IOM_GRP_ADDDS, 0x00000030)
+/* (differential input) */
IOMUX_ENTRY1(IOM_DDRMODE_CTL, 0x00020000)
-
+/* disable ddr pullups */
IOMUX_ENTRY1(IOM_GRP_DDRPKE, 0x00000000)
+/* (differential input) */
IOMUX_ENTRY1(IOM_GRP_DDRMODE, 0x00020000)
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
IOMUX_ENTRY1(IOM_GRP_CTLDS, 0x00000030)
IOMUX_ENTRY1(IOM_GRP_DDR_TYPE, 0x000C0000)
+/* Read data DQ Byte0-3 delay */
WRITE_ENTRY1(MMDC_P0 + MMDC_MPRDDQBY0DL, 0x33333333)
WRITE_ENTRY1(MMDC_P0 + MMDC_MPRDDQBY1DL, 0x33333333)
WRITE_ENTRY1(MMDC_P0 + MMDC_MPRDDQBY2DL, 0x33333333)
WRITE_ENTRY1(MMDC_P0 + MMDC_MPRDDQBY3DL, 0x33333333)
-
WRITE_ENTRY1(MMDC_P1 + MMDC_MPRDDQBY0DL, 0x33333333)
WRITE_ENTRY1(MMDC_P1 + MMDC_MPRDDQBY1DL, 0x33333333)
WRITE_ENTRY1(MMDC_P1 + MMDC_MPRDDQBY2DL, 0x33333333)
WRITE_ENTRY1(MMDC_P1 + MMDC_MPRDDQBY3DL, 0x33333333)
+
/* MDPDC - CKE pulse width = 3 cycles. CKSRE = 6 cycles, CKSRX = 6 cycles */
WRITE_ENTRY1(MMDC_P0 + MMDC_MDPDC, 0x00020036)
+/*
+ * MDMISC, mirroring, interleaved (row/bank/col)
+ */
WRITE_ENTRY1(MMDC_P0 + MMDC_MDMISC, 0x00081740)
+/*
+ * MDSCR, con_req
+ */
WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x00008000)
+/*
+ * MDCFG0, tRFC=0x56 clocks, tXS=0x5b clocks
+ * tXP=4 clocks, tXPDLL=13 clocks
+ * tFAW=24 clocks, cas=8 cycles
+ */
WRITE_ENTRY1(MMDC_P0 + MMDC_MDCFG0, 0x555A7975)
+/*
+ * MDCFG1, tRDC=8, tRP=8, tRC=27,tRAS=20,tRPA=tRP+1,tWR=8
+ * tMRD=4, tCWL=6
+ */
WRITE_ENTRY1(MMDC_P0 + MMDC_MDCFG1, 0xFF538E64)
+/*
+ * MDCFG2,tDLLK=512,tRTP=4,tWTR=4,tRRD=4
+ */
WRITE_ENTRY1(MMDC_P0 + MMDC_MDCFG2, 0x01FF00DB)
WRITE_ENTRY1(MMDC_P0 + MMDC_MDRWD, 0x000026D2)
WRITE_ENTRY1(MMDC_P0 + MMDC_MDOR, 0x005B0E21)
WRITE_ENTRY1(MMDC_P0 + MMDC_MDOTC, 0x09444040)
WRITE_ENTRY1(MMDC_P0 + MMDC_MDPDC, 0x00025576)
+
+/*
+ * Mx6Q - 64 bit wide ddr
+ * last address is (1<<28 (base) + 1<<30 - 1) / (1<<25) =
+ * 1<<3 + 1<<5 - 1 = 8 + 0x20 -1 = 0x27
+ */
+/* MDASP, CS0_END */
WRITE_ENTRY1(MMDC_P0 + MMDC_MDASP, 0x00000027)
+/*
+ * MDCTL, CS0 enable, CS1 disabled, row=14, col=10, burst=8, width=64/32bit
+ * mx6q : row+col+bank+width=14+10+3+3=30 = 1G
+ */
WRITE_ENTRY1(MMDC_P0 + MMDC_MDCTL, 0x831A0000)
+/* MDSCR, con_req, LOAD MR2, CS0, A3,A10 set (CAS Write=6), RZQ/2 */
WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x04088032)
WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x0408803A)
+/* LOAD MR3, CS0 */
WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x00008033)
WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x0000803B)
+/* LOAD MR1, CS0, A1,A6 set Rtt=RZQ/2, ODI=RZQ/7 */
WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x00428031)
WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x00428039)
+/* LOAD MR0, CS0, A6,A8,A11 set CAS=8, WR=8, DLL reset */
WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x09408030)
WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x09408038)
+/* ZQ calibrate, CS0 */
WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x04008040)
WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x04008048)
WRITE_ENTRY1(MMDC_P0 + MMDC_MPZQHWCTRL, 0xA1380003)
WRITE_ENTRY1(MMDC_P1 + MMDC_MPZQHWCTRL, 0xA1380003)
+
+/* MDREF, 32KHz refresh, 4 refeshes each */
WRITE_ENTRY1(MMDC_P0 + MMDC_MDREF, 0x00005800)
WRITE_ENTRY1(MMDC_P0 + MMDC_MPODTCTRL, 0x00022227)
WRITE_ENTRY1(MMDC_P1 + MMDC_MPODTCTRL, 0x00022227)
+/* MPDGCTRL0/1 DQS GATE*/
WRITE_ENTRY1(MMDC_P0 + MMDC_MPDGCTRL0, 0x434B0350)
WRITE_ENTRY1(MMDC_P0 + MMDC_MPDGCTRL1, 0x034C0359)
WRITE_ENTRY1(MMDC_P1 + MMDC_MPDGCTRL0, 0x434B0350)
@@ -153,17 +192,18 @@ WRITE_ENTRY1(MMDC_P0 + MMDC_MPRDDLCTL, 0x4436383B)
WRITE_ENTRY1(MMDC_P1 + MMDC_MPRDDLCTL, 0x39393341)
WRITE_ENTRY1(MMDC_P0 + MMDC_MPWRDLCTL, 0x35373933)
WRITE_ENTRY1(MMDC_P1 + MMDC_MPWRDLCTL, 0x48254A36)
-
WRITE_ENTRY1(MMDC_P0 + MMDC_MPWLDECTRL0, 0x001F001F)
WRITE_ENTRY1(MMDC_P0 + MMDC_MPWLDECTRL1, 0x001F001F)
-
WRITE_ENTRY1(MMDC_P1 + MMDC_MPWLDECTRL0, 0x00440044)
WRITE_ENTRY1(MMDC_P1 + MMDC_MPWLDECTRL1, 0x00440044)
+/* MPMUR0 - Complete calibration by forced measurement */
WRITE_ENTRY1(MMDC_P0 + MMDC_MPMUR0, 0x00000800)
WRITE_ENTRY1(MMDC_P1 + MMDC_MPMUR0, 0x00000800)
+/* MDSCR, enable ddr */
WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x00000000)
+/* MAPSR, 1024 cycles idle before self-refresh */
WRITE_ENTRY1(MMDC_P0 + MMDC_MAPSR, 0x00011006)
/* set the default clock gate to save power */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 13/21] mx6q_4x_mt41j128.cfg: use ddr3 mode for reset
2012-09-22 2:38 ` [U-Boot] [PATCH V2 00/21] Add mx6solo/mx6duallite support Troy Kisky
` (11 preceding siblings ...)
2012-09-22 2:39 ` [U-Boot] [PATCH V2 12/21] mx6q_4x_mt41j128.cfg: add comments Troy Kisky
@ 2012-09-22 2:39 ` Troy Kisky
2012-09-22 2:39 ` [U-Boot] [PATCH V2 14/21] mx6q_4x_mt41j128.cfg: skip initiailizing non-existent memory Troy Kisky
` (9 subsequent siblings)
22 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-09-22 2:39 UTC (permalink / raw)
To: u-boot
Bits 19-18 of IOMUXC_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET
should be 3 for DDR3 mode. The current value of 0 is
reserved in TRM.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
index 3a1f1bc..904276a 100644
--- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
@@ -75,7 +75,7 @@ IOMUX_ENTRY1(IOM_DRAM_RAS, 0x00020030)
IOMUX_ENTRY1(IOM_DRAM_SDCLK_0, 0x00020030)
IOMUX_ENTRY1(IOM_DRAM_SDCLK_1, 0x00020030)
-IOMUX_ENTRY1(IOM_DRAM_RESET, 0x00020030)
+IOMUX_ENTRY1(IOM_DRAM_RESET, 0x000e0030)
IOMUX_ENTRY1(IOM_DRAM_SDCKE0, 0x00003000)
IOMUX_ENTRY1(IOM_DRAM_SDCKE1, 0x00003000)
IOMUX_ENTRY1(IOM_DRAM_SDBA2, 0x00000000)
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 14/21] mx6q_4x_mt41j128.cfg: skip initiailizing non-existent memory
2012-09-22 2:38 ` [U-Boot] [PATCH V2 00/21] Add mx6solo/mx6duallite support Troy Kisky
` (12 preceding siblings ...)
2012-09-22 2:39 ` [U-Boot] [PATCH V2 13/21] mx6q_4x_mt41j128.cfg: use ddr3 mode for reset Troy Kisky
@ 2012-09-22 2:39 ` Troy Kisky
2012-09-22 2:39 ` [U-Boot] [PATCH V2 15/21] mx6q_4x_mt41j128.cfg: reorder for more efficient storage Troy Kisky
` (8 subsequent siblings)
22 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-09-22 2:39 UTC (permalink / raw)
To: u-boot
Sabrelite does not have memory associated with CS1
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 5 -----
1 file changed, 5 deletions(-)
diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
index 904276a..18cdb7b 100644
--- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
@@ -161,20 +161,15 @@ WRITE_ENTRY1(MMDC_P0 + MMDC_MDCTL, 0x831A0000)
/* MDSCR, con_req, LOAD MR2, CS0, A3,A10 set (CAS Write=6), RZQ/2 */
WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x04088032)
-WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x0408803A)
/* LOAD MR3, CS0 */
WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x00008033)
-WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x0000803B)
/* LOAD MR1, CS0, A1,A6 set Rtt=RZQ/2, ODI=RZQ/7 */
WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x00428031)
-WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x00428039)
/* LOAD MR0, CS0, A6,A8,A11 set CAS=8, WR=8, DLL reset */
WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x09408030)
-WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x09408038)
/* ZQ calibrate, CS0 */
WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x04008040)
-WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x04008048)
WRITE_ENTRY1(MMDC_P0 + MMDC_MPZQHWCTRL, 0xA1380003)
WRITE_ENTRY1(MMDC_P1 + MMDC_MPZQHWCTRL, 0xA1380003)
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 15/21] mx6q_4x_mt41j128.cfg: reorder for more efficient storage
2012-09-22 2:38 ` [U-Boot] [PATCH V2 00/21] Add mx6solo/mx6duallite support Troy Kisky
` (13 preceding siblings ...)
2012-09-22 2:39 ` [U-Boot] [PATCH V2 14/21] mx6q_4x_mt41j128.cfg: skip initiailizing non-existent memory Troy Kisky
@ 2012-09-22 2:39 ` Troy Kisky
2012-09-22 17:27 ` Fabio Estevam
2012-09-22 2:39 ` [U-Boot] [PATCH V2 16/21] mx6q_4x_mt41j128.cfg: force ZQ calibration Troy Kisky
` (7 subsequent siblings)
22 siblings, 1 reply; 430+ messages in thread
From: Troy Kisky @ 2012-09-22 2:39 UTC (permalink / raw)
To: u-boot
Repeating data values can be stored more efficiently.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 31 +++++++++++++-------------
1 file changed, 15 insertions(+), 16 deletions(-)
diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
index 18cdb7b..00712c6 100644
--- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
@@ -60,6 +60,17 @@ IOMUX_ENTRY1(IOM_DRAM_SDQS4, 0x00000030)
IOMUX_ENTRY1(IOM_DRAM_SDQS5, 0x00000030)
IOMUX_ENTRY1(IOM_DRAM_SDQS6, 0x00000030)
IOMUX_ENTRY1(IOM_DRAM_SDQS7, 0x00000030)
+IOMUX_ENTRY1(IOM_GRP_B0DS, 0x00000030)
+IOMUX_ENTRY1(IOM_GRP_B1DS, 0x00000030)
+IOMUX_ENTRY1(IOM_GRP_B2DS, 0x00000030)
+IOMUX_ENTRY1(IOM_GRP_B3DS, 0x00000030)
+IOMUX_ENTRY1(IOM_GRP_B4DS, 0x00000030)
+IOMUX_ENTRY1(IOM_GRP_B5DS, 0x00000030)
+IOMUX_ENTRY1(IOM_GRP_B6DS, 0x00000030)
+IOMUX_ENTRY1(IOM_GRP_B7DS, 0x00000030)
+IOMUX_ENTRY1(IOM_GRP_ADDDS, 0x00000030)
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+IOMUX_ENTRY1(IOM_GRP_CTLDS, 0x00000030)
IOMUX_ENTRY1(IOM_DRAM_DQM0, 0x00020030)
IOMUX_ENTRY1(IOM_DRAM_DQM1, 0x00020030)
@@ -78,29 +89,17 @@ IOMUX_ENTRY1(IOM_DRAM_SDCLK_1, 0x00020030)
IOMUX_ENTRY1(IOM_DRAM_RESET, 0x000e0030)
IOMUX_ENTRY1(IOM_DRAM_SDCKE0, 0x00003000)
IOMUX_ENTRY1(IOM_DRAM_SDCKE1, 0x00003000)
-IOMUX_ENTRY1(IOM_DRAM_SDBA2, 0x00000000)
IOMUX_ENTRY1(IOM_DRAM_SDODT0, 0x00003030)
IOMUX_ENTRY1(IOM_DRAM_SDODT1, 0x00003030)
-IOMUX_ENTRY1(IOM_GRP_B0DS, 0x00000030)
-IOMUX_ENTRY1(IOM_GRP_B1DS, 0x00000030)
-IOMUX_ENTRY1(IOM_GRP_B2DS, 0x00000030)
-IOMUX_ENTRY1(IOM_GRP_B3DS, 0x00000030)
-IOMUX_ENTRY1(IOM_GRP_B4DS, 0x00000030)
-IOMUX_ENTRY1(IOM_GRP_B5DS, 0x00000030)
-IOMUX_ENTRY1(IOM_GRP_B6DS, 0x00000030)
-IOMUX_ENTRY1(IOM_GRP_B7DS, 0x00000030)
-
-IOMUX_ENTRY1(IOM_GRP_ADDDS, 0x00000030)
/* (differential input) */
IOMUX_ENTRY1(IOM_DDRMODE_CTL, 0x00020000)
-/* disable ddr pullups */
-IOMUX_ENTRY1(IOM_GRP_DDRPKE, 0x00000000)
/* (differential input) */
IOMUX_ENTRY1(IOM_GRP_DDRMODE, 0x00020000)
-/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
-IOMUX_ENTRY1(IOM_GRP_CTLDS, 0x00000030)
+/* disable ddr pullups */
+IOMUX_ENTRY1(IOM_GRP_DDRPKE, 0x00000000)
+IOMUX_ENTRY1(IOM_DRAM_SDBA2, 0x00000000)
IOMUX_ENTRY1(IOM_GRP_DDR_TYPE, 0x000C0000)
/* Read data DQ Byte0-3 delay */
@@ -180,8 +179,8 @@ WRITE_ENTRY1(MMDC_P1 + MMDC_MPODTCTRL, 0x00022227)
/* MPDGCTRL0/1 DQS GATE*/
WRITE_ENTRY1(MMDC_P0 + MMDC_MPDGCTRL0, 0x434B0350)
-WRITE_ENTRY1(MMDC_P0 + MMDC_MPDGCTRL1, 0x034C0359)
WRITE_ENTRY1(MMDC_P1 + MMDC_MPDGCTRL0, 0x434B0350)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPDGCTRL1, 0x034C0359)
WRITE_ENTRY1(MMDC_P1 + MMDC_MPDGCTRL1, 0x03650348)
WRITE_ENTRY1(MMDC_P0 + MMDC_MPRDDLCTL, 0x4436383B)
WRITE_ENTRY1(MMDC_P1 + MMDC_MPRDDLCTL, 0x39393341)
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 16/21] mx6q_4x_mt41j128.cfg: force ZQ calibration
2012-09-22 2:38 ` [U-Boot] [PATCH V2 00/21] Add mx6solo/mx6duallite support Troy Kisky
` (14 preceding siblings ...)
2012-09-22 2:39 ` [U-Boot] [PATCH V2 15/21] mx6q_4x_mt41j128.cfg: reorder for more efficient storage Troy Kisky
@ 2012-09-22 2:39 ` Troy Kisky
2012-09-22 2:39 ` [U-Boot] [PATCH V2 17/21] mx6: soc: add get_cpu_type Troy Kisky
` (6 subsequent siblings)
22 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-09-22 2:39 UTC (permalink / raw)
To: u-boot
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
index 00712c6..60eae86 100644
--- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
@@ -169,8 +169,8 @@ WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x09408030)
/* ZQ calibrate, CS0 */
WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x04008040)
-WRITE_ENTRY1(MMDC_P0 + MMDC_MPZQHWCTRL, 0xA1380003)
-WRITE_ENTRY1(MMDC_P1 + MMDC_MPZQHWCTRL, 0xA1380003)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPZQHWCTRL, 0xA1390003)
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPZQHWCTRL, 0xA1390003)
/* MDREF, 32KHz refresh, 4 refeshes each */
WRITE_ENTRY1(MMDC_P0 + MMDC_MDREF, 0x00005800)
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 17/21] mx6: soc: add get_cpu_type
2012-09-22 2:38 ` [U-Boot] [PATCH V2 00/21] Add mx6solo/mx6duallite support Troy Kisky
` (15 preceding siblings ...)
2012-09-22 2:39 ` [U-Boot] [PATCH V2 16/21] mx6q_4x_mt41j128.cfg: force ZQ calibration Troy Kisky
@ 2012-09-22 2:39 ` Troy Kisky
2012-09-22 2:50 ` Fabio Estevam
2012-09-22 2:39 ` [U-Boot] [PATCH V2 18/21] arch-mx6: add mx6dl_pins.h Troy Kisky
` (5 subsequent siblings)
22 siblings, 1 reply; 430+ messages in thread
From: Troy Kisky @ 2012-09-22 2:39 UTC (permalink / raw)
To: u-boot
Add function to return the processor type.
i.e. MX6Q, MX6DL, MX6SOLO, MX6SOLOLITE
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
arch/arm/cpu/armv7/mx6/soc.c | 26 ++++++++++++++++++++++++++
arch/arm/include/asm/arch-mx6/sys_proto.h | 6 ++++++
2 files changed, 32 insertions(+)
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 7380ffe..5fce682 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -44,6 +44,32 @@ u32 get_cpu_rev(void)
return system_rev;
}
+struct scu_regs {
+ uint32_t ctrl;
+ uint32_t config;
+ uint32_t status;
+ uint32_t invalidate;
+ uint32_t fpga_rev;
+};
+
+signed char cpu_type[] = {MXC_CPU_MX6SOLO, MXC_CPU_MX6DL, -1, MXC_CPU_MX6Q};
+
+int get_cpu_type(void)
+{
+ struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
+ uint32_t reg = readl(&scu->config) & 3;
+ int type = cpu_type[reg];
+
+ if (!reg) {
+ u32 cpu_type = readl(ANATOP_BASE_ADDR + 0x280);
+
+ cpu_type >>= 16;
+ if (cpu_type == 0x60)
+ type = MXC_CPU_MX6SL; /* this is a soloLite */
+ }
+ return type;
+}
+
void init_aips(void)
{
struct aipstz_regs *aips1, *aips2;
diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h
index 711b30d..997fc8e 100644
--- a/arch/arm/include/asm/arch-mx6/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx6/sys_proto.h
@@ -28,6 +28,12 @@
u32 get_cpu_rev(void);
+#define MXC_CPU_MX6SL 60
+#define MXC_CPU_MX6DL 61
+#define MXC_CPU_MX6SOLO 62
+#define MXC_CPU_MX6Q 63
+
+int get_cpu_type(void);
void set_vddsoc(u32 mv);
/*
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 18/21] arch-mx6: add mx6dl_pins.h
2012-09-22 2:38 ` [U-Boot] [PATCH V2 00/21] Add mx6solo/mx6duallite support Troy Kisky
` (16 preceding siblings ...)
2012-09-22 2:39 ` [U-Boot] [PATCH V2 17/21] mx6: soc: add get_cpu_type Troy Kisky
@ 2012-09-22 2:39 ` Troy Kisky
2012-09-22 4:10 ` Vikram Narayanan
2012-09-22 2:39 ` [U-Boot] [PATCH V2 19/21] mx6qsabrelite: add support for mx6 solo/duallite Troy Kisky
` (4 subsequent siblings)
22 siblings, 1 reply; 430+ messages in thread
From: Troy Kisky @ 2012-09-22 2:39 UTC (permalink / raw)
To: u-boot
Only the values used in the sabrelite board are
added currently. Add more as other boards use them.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
arch/arm/include/asm/arch-mx6/mx6dl_pins.h | 118 ++++++++++++++++++++++++++++
1 file changed, 118 insertions(+)
create mode 100644 arch/arm/include/asm/arch-mx6/mx6dl_pins.h
diff --git a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
new file mode 100644
index 0000000..5848013
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
@@ -0,0 +1,118 @@
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+#ifndef __ASM_ARCH_MX6_MX6DL_PINS_H__
+#define __ASM_ARCH_MX6_MX6DL_PINS_H__
+
+#include <asm/imx-common/iomux-v3.h>
+
+/* Use to set PAD control */
+#define PAD_CTL_HYS (1 << 16)
+#define PAD_CTL_PUS_100K_DOWN (0 << 14)
+#define PAD_CTL_PUS_47K_UP (1 << 14)
+#define PAD_CTL_PUS_100K_UP (2 << 14)
+#define PAD_CTL_PUS_22K_UP (3 << 14)
+
+#define PAD_CTL_PUE (1 << 13)
+#define PAD_CTL_PKE (1 << 12)
+#define PAD_CTL_ODE (1 << 11)
+#define PAD_CTL_SPEED_LOW (1 << 6)
+#define PAD_CTL_SPEED_MED (2 << 6)
+#define PAD_CTL_SPEED_HIGH (3 << 6)
+#define PAD_CTL_DSE_DISABLE (0 << 3)
+#define PAD_CTL_DSE_240ohm (1 << 3)
+#define PAD_CTL_DSE_120ohm (2 << 3)
+#define PAD_CTL_DSE_80ohm (3 << 3)
+#define PAD_CTL_DSE_60ohm (4 << 3)
+#define PAD_CTL_DSE_48ohm (5 << 3)
+#define PAD_CTL_DSE_40ohm (6 << 3)
+#define PAD_CTL_DSE_34ohm (7 << 3)
+#define PAD_CTL_SRE_FAST (1 << 0)
+#define PAD_CTL_SRE_SLOW (0 << 0)
+
+#define IOMUX_CONFIG_SION 0x10
+#define NO_MUX_I 0
+#define NO_PAD_I 0
+enum {
+ MX6DL_PAD_EIM_D16__ECSPI1_SCLK = IOMUX_PAD(0x0514, 0x0144, 1, 0x07D8, 2, 0),
+ MX6DL_PAD_EIM_D17__ECSPI1_MISO = IOMUX_PAD(0x0518, 0x0148, 1, 0x07DC, 2, 0),
+ MX6DL_PAD_EIM_D18__ECSPI1_MOSI = IOMUX_PAD(0x051C, 0x014C, 1, 0x07E0, 2, 0),
+ MX6DL_PAD_EIM_D19__GPIO_3_19 = IOMUX_PAD(0x0520, 0x0150, 5, 0x0000, 0, 0),
+ MX6DL_PAD_EIM_D21__GPIO_3_21 = IOMUX_PAD(0x0528, 0x0158, 5, 0x0000, 0, 0),
+ MX6DL_PAD_EIM_D21__I2C1_SCL = IOMUX_PAD(0x0528, 0x0158, 6 | IOMUX_CONFIG_SION, 0x0868, 1, 0),
+ MX6DL_PAD_EIM_D23__GPIO_3_23 = IOMUX_PAD(0x0530, 0x0160, 5, 0x0000, 0, 0),
+ MX6DL_PAD_EIM_D26__UART2_TXD = IOMUX_PAD(0x053C, 0x016C, 4, 0x0000, 0, 0),
+ MX6DL_PAD_EIM_D27__UART2_RXD = IOMUX_PAD(0x0540, 0x0170, 4, 0x0904, 1, 0),
+ MX6DL_PAD_EIM_D28__I2C1_SDA = IOMUX_PAD(0x0544, 0x0174, 1 | IOMUX_CONFIG_SION, 0x086C, 1, 0),
+ MX6DL_PAD_EIM_D28__GPIO_3_28 = IOMUX_PAD(0x0544, 0x0174, 5, 0x0000, 0, 0),
+ MX6DL_PAD_ENET_MDC__ENET_MDC = IOMUX_PAD(0x05B8, 0x01E8, 1, 0x0000, 0, 0),
+ MX6DL_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x05BC, 0x01EC, 1, 0x0810, 0, 0),
+ MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK = IOMUX_PAD(0x05C0, 0x01F0, 1, 0x0000, 0, 0),
+ MX6DL_PAD_ENET_RXD0__GPIO_1_27 = IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0),
+ MX6DL_PAD_GPIO_16__GPIO_7_11 = IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0),
+ MX6DL_PAD_GPIO_16__I2C3_SDA = IOMUX_PAD(0x05E4, 0x0214, 6 | IOMUX_CONFIG_SION, 0x087C, 1, 0),
+ MX6DL_PAD_GPIO_17__GPIO_7_12 = IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0),
+ MX6DL_PAD_GPIO_18__GPIO_7_13 = IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0),
+ MX6DL_PAD_GPIO_19__GPIO_4_5 = IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0),
+ MX6DL_PAD_GPIO_5__GPIO_1_5 = IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0),
+ MX6DL_PAD_GPIO_5__I2C3_SCL = IOMUX_PAD(0x0600, 0x0230, 6 | IOMUX_CONFIG_SION, 0x0878, 2, 0),
+ MX6DL_PAD_KEY_COL3__I2C2_SCL = IOMUX_PAD(0x0638, 0x0250, 4 | IOMUX_CONFIG_SION, 0x0870, 1, 0),
+ MX6DL_PAD_KEY_COL3__GPIO_4_12 = IOMUX_PAD(0x0638, 0x0250, 5, 0x0000, 0, 0),
+ MX6DL_PAD_KEY_ROW3__I2C2_SDA = IOMUX_PAD(0x064C, 0x0264, 4 | IOMUX_CONFIG_SION, 0x0874, 1, 0),
+ MX6DL_PAD_KEY_ROW3__GPIO_4_13 = IOMUX_PAD(0x064C, 0x0264, 5, 0x0000, 0, 0),
+ MX6DL_PAD_NANDF_D1__GPIO_2_1 = IOMUX_PAD(0x0670, 0x0288, 5, 0x0000, 0, 0),
+ MX6DL_PAD_NANDF_D2__GPIO_2_2 = IOMUX_PAD(0x0674, 0x028C, 5, 0x0000, 0, 0),
+ MX6DL_PAD_NANDF_D3__GPIO_2_3 = IOMUX_PAD(0x0678, 0x0290, 5, 0x0000, 0, 0),
+ MX6DL_PAD_NANDF_D4__GPIO_2_4 = IOMUX_PAD(0x067C, 0x0294, 5, 0x0000, 0, 0),
+ MX6DL_PAD_NANDF_D6__GPIO_2_6 = IOMUX_PAD(0x0684, 0x029C, 5, 0x0000, 0, 0),
+ MX6DL_PAD_RGMII_RD0__ENET_RGMII_RD0 = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0818, 1, 0),
+ MX6DL_PAD_RGMII_RD0__GPIO_6_25 = IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0),
+ MX6DL_PAD_RGMII_RD1__ENET_RGMII_RD1 = IOMUX_PAD(0x0698, 0x02B0, 1, 0x081C, 1, 0),
+ MX6DL_PAD_RGMII_RD1__GPIO_6_27 = IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0),
+ MX6DL_PAD_RGMII_RD2__ENET_RGMII_RD2 = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0820, 1, 0),
+ MX6DL_PAD_RGMII_RD2__GPIO_6_28 = IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0),
+ MX6DL_PAD_RGMII_RD3__ENET_RGMII_RD3 = IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0824, 1, 0),
+ MX6DL_PAD_RGMII_RD3__GPIO_6_29 = IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0),
+ MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0828, 1, 0),
+ MX6DL_PAD_RGMII_RX_CTL__GPIO_6_24 = IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0),
+ MX6DL_PAD_RGMII_RXC__ENET_RGMII_RXC = IOMUX_PAD(0x06A8, 0x02C0, 1, 0x0814, 1, 0),
+ MX6DL_PAD_RGMII_RXC__GPIO_6_30 = IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0),
+ MX6DL_PAD_RGMII_TD0__ENET_RGMII_TD0 = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0),
+ MX6DL_PAD_RGMII_TD1__ENET_RGMII_TD1 = IOMUX_PAD(0x06B0, 0x02C8, 1, 0x0000, 0, 0),
+ MX6DL_PAD_RGMII_TD2__ENET_RGMII_TD2 = IOMUX_PAD(0x06B4, 0x02CC, 1, 0x0000, 0, 0),
+ MX6DL_PAD_RGMII_TD3__ENET_RGMII_TD3 = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0),
+ MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL = IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0),
+ MX6DL_PAD_RGMII_TXC__ENET_RGMII_TXC = IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0),
+ MX6DL_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x06F4, 0x030C, 0, 0x0934, 1, 0),
+ MX6DL_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x06F8, 0x0310, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+ MX6DL_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0),
+ MX6DL_PAD_SD3_DAT1__USDHC3_DAT1 = IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0),
+ MX6DL_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0),
+ MX6DL_PAD_SD3_DAT3__USDHC3_DAT3 = IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0),
+ MX6DL_PAD_SD3_DAT5__GPIO_7_0 = IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0),
+ MX6DL_PAD_SD3_DAT6__UART1_RXD = IOMUX_PAD(0x0714, 0x032C, 1, 0x08FC, 2, 0),
+ MX6DL_PAD_SD3_DAT7__UART1_TXD = IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0),
+ MX6DL_PAD_SD4_CLK__USDHC4_CLK = IOMUX_PAD(0x0720, 0x0338, 0, 0x0938, 1, 0),
+ MX6DL_PAD_SD4_CMD__USDHC4_CMD = IOMUX_PAD(0x0724, 0x033C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+ MX6DL_PAD_SD4_DAT0__USDHC4_DAT0 = IOMUX_PAD(0x0728, 0x0340, 1, 0x0000, 0, 0),
+ MX6DL_PAD_SD4_DAT1__USDHC4_DAT1 = IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0),
+ MX6DL_PAD_SD4_DAT2__USDHC4_DAT2 = IOMUX_PAD(0x0730, 0x0348, 1, 0x0000, 0, 0),
+ MX6DL_PAD_SD4_DAT3__USDHC4_DAT3 = IOMUX_PAD(0x0734, 0x034C, 1, 0x0000, 0, 0),
+};
+#endif /* __ASM_ARCH_MX6_MX6DL_PINS_H__ */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 19/21] mx6qsabrelite: add support for mx6 solo/duallite
2012-09-22 2:38 ` [U-Boot] [PATCH V2 00/21] Add mx6solo/mx6duallite support Troy Kisky
` (17 preceding siblings ...)
2012-09-22 2:39 ` [U-Boot] [PATCH V2 18/21] arch-mx6: add mx6dl_pins.h Troy Kisky
@ 2012-09-22 2:39 ` Troy Kisky
2012-09-22 4:12 ` Vikram Narayanan
2012-09-22 2:39 ` [U-Boot] [PATCH V2 20/21] mx6q_4x_mt41j128.cfg: add mx6 solo/duallite support Troy Kisky
` (3 subsequent siblings)
22 siblings, 1 reply; 430+ messages in thread
From: Troy Kisky @ 2012-09-22 2:39 UTC (permalink / raw)
To: u-boot
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
board/freescale/mx6qsabrelite/mx6qsabrelite.c | 231 ++++++-------------------
board/freescale/mx6qsabrelite/pads.h | 172 ++++++++++++++++++
2 files changed, 226 insertions(+), 177 deletions(-)
create mode 100644 board/freescale/mx6qsabrelite/pads.h
diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
index 4b4e89b..ad2347d 100644
--- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
@@ -26,6 +26,8 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6x_pins.h>
+#include <asm/arch/mx6dl_pins.h>
+#include <asm/arch/sys_proto.h>
#include <asm/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
@@ -38,163 +40,46 @@
#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
-#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+#include "pads.h"
+#define FOR_DL_SOLO
+#include "pads.h"
-#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
- PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+int cpu_is_mx6q(void)
+{
+ return get_cpu_type() == MXC_CPU_MX6Q;
+}
-#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+#define IOMUX_SETUP(list) iomux_setup(mx6q_##list, ARRAY_SIZE(mx6q_##list), \
+ mx6dl_solo_##list, ARRAY_SIZE(mx6dl_solo_##list))
-#define SPI_PAD_CTRL (PAD_CTL_HYS | \
- PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+int iomux_setup(iomux_v3_cfg_t *mx6q_pad_list, int mx6q_pad_cnt,
+ iomux_v3_cfg_t *mx6dl_solo_pad_list, int mx6dl_solo_pad_cnt)
+{
+ int mx6q = cpu_is_mx6q();
+ iomux_v3_cfg_t *p = mx6q ? mx6q_pad_list : mx6dl_solo_pad_list;
+ int cnt = mx6q ? mx6q_pad_cnt : mx6dl_solo_pad_cnt;
-#define BUTTON_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+ return imx_iomux_v3_setup_multiple_pads(p, cnt);
+}
-#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
- PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
+static const unsigned char bank_lookup[] = {3, 2};
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
-
- return 0;
+ unsigned mdctl = readl(MMDC_P0_BASE_ADDR + 0x000);
+ unsigned mdmisc = readl(MMDC_P0_BASE_ADDR + 0x018);
+ int bits = 11 + 0 + 0 + 1; /* row+col+bank+width */
+
+ bits += (mdctl >> 24) & 7; /* row */
+ bits += col_lookup[(mdctl >> 20) & 7]; /* col */
+ bits += bank_lookup[(mdmisc >> 5) & 1]; /* bank */
+ bits += (mdctl >> 16) & 3; /* width */
+ bits += (mdctl >> 30) & 1; /* cs1 enabled*/
+ gd->ram_size = 1 << bits;
+ return 0;
}
-iomux_v3_cfg_t uart1_pads[] = {
- MX6Q_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6Q_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-iomux_v3_cfg_t uart2_pads[] = {
- MX6Q_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-
-/* I2C1, SGTL5000 */
-struct i2c_pads_info i2c_pad_info0 = {
- .scl = {
- .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
- .gpio_mode = MX6Q_PAD_EIM_D21__GPIO_3_21 | PC,
- .gp = IMX_GPIO_NR(3, 21)
- },
- .sda = {
- .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
- .gpio_mode = MX6Q_PAD_EIM_D28__GPIO_3_28 | PC,
- .gp = IMX_GPIO_NR(3, 28)
- }
-};
-
-/* I2C2 Camera, MIPI */
-struct i2c_pads_info i2c_pad_info1 = {
- .scl = {
- .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
- .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO_4_12 | PC,
- .gp = IMX_GPIO_NR(4, 12)
- },
- .sda = {
- .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
- .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO_4_13 | PC,
- .gp = IMX_GPIO_NR(4, 13)
- }
-};
-
-/* I2C3, J15 - RGB connector */
-struct i2c_pads_info i2c_pad_info2 = {
- .scl = {
- .i2c_mode = MX6Q_PAD_GPIO_5__I2C3_SCL | PC,
- .gpio_mode = MX6Q_PAD_GPIO_5__GPIO_1_5 | PC,
- .gp = IMX_GPIO_NR(1, 5)
- },
- .sda = {
- .i2c_mode = MX6Q_PAD_GPIO_16__I2C3_SDA | PC,
- .gpio_mode = MX6Q_PAD_GPIO_16__GPIO_7_11 | PC,
- .gp = IMX_GPIO_NR(7, 11)
- }
-};
-
-iomux_v3_cfg_t usdhc3_pads[] = {
- MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
-};
-
-iomux_v3_cfg_t usdhc4_pads[] = {
- MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
-};
-
-iomux_v3_cfg_t enet_pads1[] = {
- MX6Q_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
- /* pin 35 - 1 (PHY_AD2) on reset */
- MX6Q_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* pin 32 - 1 - (MODE0) all */
- MX6Q_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* pin 31 - 1 - (MODE1) all */
- MX6Q_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* pin 28 - 1 - (MODE2) all */
- MX6Q_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* pin 27 - 1 - (MODE3) all */
- MX6Q_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
- MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* pin 42 PHY nRST */
- MX6Q_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-iomux_v3_cfg_t enet_pads2[] = {
- MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
-};
-
-/* Button assignments for J14 */
-static iomux_v3_cfg_t button_pads[] = {
- /* Menu */
- MX6Q_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
- /* Back */
- MX6Q_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
- /* Labelled Search (mapped to Power under Android) */
- MX6Q_PAD_NANDF_D3__GPIO_2_3 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
- /* Home */
- MX6Q_PAD_NANDF_D4__GPIO_2_4 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
- /* Volume Down */
- MX6Q_PAD_GPIO_19__GPIO_4_5 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
- /* Volume Up */
- MX6Q_PAD_GPIO_18__GPIO_7_13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
-};
-
static void setup_iomux_enet(void)
{
gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
@@ -203,30 +88,26 @@ static void setup_iomux_enet(void)
gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
- imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
+ IOMUX_SETUP(enet_pads1);
gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
/* Need delay 10ms according to KSZ9021 spec */
udelay(1000 * 10);
gpio_set_value(IMX_GPIO_NR(3, 23), 1);
- imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
+ IOMUX_SETUP(enet_pads2);
}
-iomux_v3_cfg_t usb_pads[] = {
- MX6Q_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
static void setup_iomux_uart(void)
{
- imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
- imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+ IOMUX_SETUP(uart1_pads);
+ IOMUX_SETUP(uart2_pads);
}
#ifdef CONFIG_USB_EHCI_MX6
int board_ehci_hcd_init(int port)
{
- imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
+ IOMUX_SETUP(usb_pads);
/* Reset USB hub */
gpio_direction_output(IMX_GPIO_NR(7, 12), 0);
@@ -267,12 +148,10 @@ int board_mmc_init(bd_t *bis)
for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
switch (index) {
case 0:
- imx_iomux_v3_setup_multiple_pads(
- usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ IOMUX_SETUP(usdhc3_pads);
break;
case 1:
- imx_iomux_v3_setup_multiple_pads(
- usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+ IOMUX_SETUP(usdhc4_pads);
break;
default:
printf("Warning: you configured more USDHC controllers"
@@ -294,19 +173,10 @@ u32 get_board_rev(void)
}
#ifdef CONFIG_MXC_SPI
-iomux_v3_cfg_t ecspi1_pads[] = {
- /* SS1 */
- MX6Q_PAD_EIM_D19__GPIO_3_19 | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX6Q_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX6Q_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
-};
-
void setup_spi(void)
{
gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1);
- imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
- ARRAY_SIZE(ecspi1_pads));
+ IOMUX_SETUP(ecspi1_pads);
}
#endif
@@ -342,8 +212,7 @@ int board_eth_init(bd_t *bis)
static void setup_buttons(void)
{
- imx_iomux_v3_setup_multiple_pads(button_pads,
- ARRAY_SIZE(button_pads));
+ IOMUX_SETUP(button_pads);
}
#ifdef CONFIG_CMD_SATA
@@ -382,15 +251,18 @@ int board_early_init_f(void)
int board_init(void)
{
+ struct i2c_pads_info *p = cpu_is_mx6q() ? mx6q_i2c_pad_info :
+ mx6dl_solo_i2c_pad_info;
+
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
#ifdef CONFIG_MXC_SPI
setup_spi();
#endif
- setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
- setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
- setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &p[0]);
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &p[1]);
+ setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &p[2]);
#ifdef CONFIG_CMD_SATA
setup_sata();
@@ -401,9 +273,14 @@ int board_init(void)
int checkboard(void)
{
- puts("Board: MX6Q-Sabre Lite\n");
+ int cpu_type = get_cpu_type();
- return 0;
+ puts("Board: MX6");
+ puts((cpu_type == MXC_CPU_MX6Q) ? "Q" :
+ (cpu_type == MXC_CPU_MX6DL) ? "DL" : "SOLO");
+ puts("-Sabre Lite\n");
+
+ return 0;
}
struct button_key {
diff --git a/board/freescale/mx6qsabrelite/pads.h b/board/freescale/mx6qsabrelite/pads.h
new file mode 100644
index 0000000..e7ffe21
--- /dev/null
+++ b/board/freescale/mx6qsabrelite/pads.h
@@ -0,0 +1,172 @@
+#undef MX6PAD
+#undef MX6NAME
+
+#ifdef FOR_DL_SOLO
+#define MX6PAD(a) MX6DL_PAD_##a
+#define MX6NAME(a) mx6dl_solo_##a
+#else
+#define MX6PAD(a) MX6Q_PAD_##a
+#define MX6NAME(a) mx6q_##a
+#endif
+
+#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | \
+ PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define BUTTON_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+iomux_v3_cfg_t MX6NAME(uart1_pads)[] = {
+ MX6PAD(SD3_DAT6__UART1_RXD) | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6PAD(SD3_DAT7__UART1_TXD) | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+iomux_v3_cfg_t MX6NAME(uart2_pads)[] = {
+ MX6PAD(EIM_D26__UART2_TXD) | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6PAD(EIM_D27__UART2_RXD) | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+struct i2c_pads_info MX6NAME(i2c_pad_info)[] = {
+ {
+ /* I2C1, SGTL5000 */
+ .scl = {
+ .i2c_mode = MX6PAD(EIM_D21__I2C1_SCL) | PC,
+ .gpio_mode = MX6PAD(EIM_D21__GPIO_3_21) | PC,
+ .gp = IMX_GPIO_NR(3, 21)
+ },
+ .sda = {
+ .i2c_mode = MX6PAD(EIM_D28__I2C1_SDA) | PC,
+ .gpio_mode = MX6PAD(EIM_D28__GPIO_3_28) | PC,
+ .gp = IMX_GPIO_NR(3, 28)
+ }
+ }, {
+ /* I2C2 Camera, MIPI */
+ .scl = {
+ .i2c_mode = MX6PAD(KEY_COL3__I2C2_SCL) | PC,
+ .gpio_mode = MX6PAD(KEY_COL3__GPIO_4_12) | PC,
+ .gp = IMX_GPIO_NR(4, 12)
+ },
+ .sda = {
+ .i2c_mode = MX6PAD(KEY_ROW3__I2C2_SDA) | PC,
+ .gpio_mode = MX6PAD(KEY_ROW3__GPIO_4_13) | PC,
+ .gp = IMX_GPIO_NR(4, 13)
+ }
+ }, {
+ /* I2C3, J15 - RGB connector */
+ .scl = {
+ .i2c_mode = MX6PAD(GPIO_5__I2C3_SCL) | PC,
+ .gpio_mode = MX6PAD(GPIO_5__GPIO_1_5) | PC,
+ .gp = IMX_GPIO_NR(1, 5)
+ },
+ .sda = {
+ .i2c_mode = MX6PAD(GPIO_16__I2C3_SDA) | PC,
+ .gpio_mode = MX6PAD(GPIO_16__GPIO_7_11) | PC,
+ .gp = IMX_GPIO_NR(7, 11)
+ }
+ }
+};
+
+iomux_v3_cfg_t MX6NAME(usdhc3_pads)[] = {
+ MX6PAD(SD3_CLK__USDHC3_CLK) | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6PAD(SD3_CMD__USDHC3_CMD) | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6PAD(SD3_DAT0__USDHC3_DAT0) | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6PAD(SD3_DAT1__USDHC3_DAT1) | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6PAD(SD3_DAT2__USDHC3_DAT2) | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6PAD(SD3_DAT3__USDHC3_DAT3) | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6PAD(SD3_DAT5__GPIO_7_0) | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+iomux_v3_cfg_t MX6NAME(usdhc4_pads)[] = {
+ MX6PAD(SD4_CLK__USDHC4_CLK) | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6PAD(SD4_CMD__USDHC4_CMD) | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6PAD(SD4_DAT0__USDHC4_DAT0) | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6PAD(SD4_DAT1__USDHC4_DAT1) | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6PAD(SD4_DAT2__USDHC4_DAT2) | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6PAD(SD4_DAT3__USDHC4_DAT3) | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6PAD(NANDF_D6__GPIO_2_6) | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+iomux_v3_cfg_t MX6NAME(enet_pads1)[] = {
+ MX6PAD(ENET_MDIO__ENET_MDIO) | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6PAD(ENET_MDC__ENET_MDC) | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6PAD(RGMII_TXC__ENET_RGMII_TXC) | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6PAD(RGMII_TD0__ENET_RGMII_TD0) | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6PAD(RGMII_TD1__ENET_RGMII_TD1) | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6PAD(RGMII_TD2__ENET_RGMII_TD2) | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6PAD(RGMII_TD3__ENET_RGMII_TD3) | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6PAD(RGMII_TX_CTL__RGMII_TX_CTL) | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6PAD(ENET_REF_CLK__ENET_TX_CLK) | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ /* pin 35 - 1 (PHY_AD2) on reset */
+ MX6PAD(RGMII_RXC__GPIO_6_30) | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 32 - 1 - (MODE0) all */
+ MX6PAD(RGMII_RD0__GPIO_6_25) | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 31 - 1 - (MODE1) all */
+ MX6PAD(RGMII_RD1__GPIO_6_27) | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 28 - 1 - (MODE2) all */
+ MX6PAD(RGMII_RD2__GPIO_6_28) | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 27 - 1 - (MODE3) all */
+ MX6PAD(RGMII_RD3__GPIO_6_29) | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
+ MX6PAD(RGMII_RX_CTL__GPIO_6_24) | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 42 PHY nRST */
+ MX6PAD(EIM_D23__GPIO_3_23) | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+iomux_v3_cfg_t MX6NAME(enet_pads2)[] = {
+ MX6PAD(RGMII_RXC__ENET_RGMII_RXC) | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6PAD(RGMII_RD0__ENET_RGMII_RD0) | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6PAD(RGMII_RD1__ENET_RGMII_RD1) | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6PAD(RGMII_RD2__ENET_RGMII_RD2) | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6PAD(RGMII_RD3__ENET_RGMII_RD3) | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6PAD(RGMII_RX_CTL__RGMII_RX_CTL) | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+/* Button assignments for J14 */
+static iomux_v3_cfg_t MX6NAME(button_pads)[] = {
+ /* Menu */
+ MX6PAD(NANDF_D1__GPIO_2_1) | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+ /* Back */
+ MX6PAD(NANDF_D2__GPIO_2_2) | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+ /* Labelled Search (mapped to Power under Android) */
+ MX6PAD(NANDF_D3__GPIO_2_3) | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+ /* Home */
+ MX6PAD(NANDF_D4__GPIO_2_4) | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+ /* Volume Down */
+ MX6PAD(GPIO_19__GPIO_4_5) | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+ /* Volume Up */
+ MX6PAD(GPIO_18__GPIO_7_13) | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+};
+
+iomux_v3_cfg_t MX6NAME(usb_pads)[] = {
+ MX6PAD(GPIO_17__GPIO_7_12) | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+#ifdef CONFIG_MXC_SPI
+iomux_v3_cfg_t MX6NAME(ecspi1_pads)[] = {
+ /* SS1 */
+ MX6PAD(EIM_D19__GPIO_3_19) | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6PAD(EIM_D17__ECSPI1_MISO) | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6PAD(EIM_D18__ECSPI1_MOSI) | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6PAD(EIM_D16__ECSPI1_SCLK) | MUX_PAD_CTRL(SPI_PAD_CTRL),
+};
+#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 20/21] mx6q_4x_mt41j128.cfg: add mx6 solo/duallite support
2012-09-22 2:38 ` [U-Boot] [PATCH V2 00/21] Add mx6solo/mx6duallite support Troy Kisky
` (18 preceding siblings ...)
2012-09-22 2:39 ` [U-Boot] [PATCH V2 19/21] mx6qsabrelite: add support for mx6 solo/duallite Troy Kisky
@ 2012-09-22 2:39 ` Troy Kisky
2012-09-22 2:39 ` [U-Boot] [PATCH V2 21/21] mx6qsabrelite: change CONFIG_SYS_PROMPT Troy Kisky
` (2 subsequent siblings)
22 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-09-22 2:39 UTC (permalink / raw)
To: u-boot
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 127 +++++++++++++++++++-------
1 file changed, 92 insertions(+), 35 deletions(-)
diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
index 60eae86..46fd1dc 100644
--- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
@@ -52,6 +52,15 @@ BOOT_FROM sd
* Address absolute address of the register
* value value to be stored in the register
*/
+/*
+ * DDR3 settings
+ * MX6Q ddr is limited to 1066 Mhz, currently 1056 MHz(528 MHz clock),
+ * memory bus width: 64 bits, x16/x32/x64
+ * MX6DL ddr is limited to 800 MHz(400 MHz clock)
+ * memory bus width: 64 bits, x16/x32/x64
+ * MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
+ * memory bus width: 32 bits, x16/x32
+ */
IOMUX_ENTRY1(IOM_DRAM_SDQS0, 0x00000030)
IOMUX_ENTRY1(IOM_DRAM_SDQS1, 0x00000030)
IOMUX_ENTRY1(IOM_DRAM_SDQS2, 0x00000030)
@@ -112,8 +121,12 @@ WRITE_ENTRY1(MMDC_P1 + MMDC_MPRDDQBY1DL, 0x33333333)
WRITE_ENTRY1(MMDC_P1 + MMDC_MPRDDQBY2DL, 0x33333333)
WRITE_ENTRY1(MMDC_P1 + MMDC_MPRDDQBY3DL, 0x33333333)
-/* MDPDC - CKE pulse width = 3 cycles. CKSRE = 6 cycles, CKSRX = 6 cycles */
-WRITE_ENTRY1(MMDC_P0 + MMDC_MDPDC, 0x00020036)
+/*
+ * MDPDC - [17:16](2) => CKE pulse width = 3 cycles.
+ * MX6Q: [2:0](6) => CKSRE = 6 cycles, [5:3](6) => CKSRX = 6 cycles
+ * MX6DL/SOLO: [2:0](5) => CKSRE = 5 cycles, [5:3](5) => CKSRX = 5 cycles
+ */
+WRITE_ENTRY2(MMDC_P0 + MMDC_MDPDC, 0x00020036, 0x0002002D)
/*
* MDMISC, mirroring, interleaved (row/bank/col)
@@ -124,48 +137,92 @@ WRITE_ENTRY1(MMDC_P0 + MMDC_MDMISC, 0x00081740)
* MDSCR, con_req
*/
WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x00008000)
+
/*
- * MDCFG0, tRFC=0x56 clocks, tXS=0x5b clocks
- * tXP=4 clocks, tXPDLL=13 clocks
- * tFAW=24 clocks, cas=8 cycles
+ * MDCFG0,
+ * MX6Q:
+ * tRFC=0x56 clocks, tXS=0x5b clocks, tXP=4 clocks, tXPDLL=13 clocks
+ * tFAW=24 clocks, cas=8 cycles
+ * MX6DL/SOLO:
+ * tRFC=0x6a clocks, tXS=0x6e clocks, tXP=3 clocks, tXPDLL=10 clocks
+ * tFAW=19 clocks, cas=6 cycles
*/
-WRITE_ENTRY1(MMDC_P0 + MMDC_MDCFG0, 0x555A7975)
+WRITE_ENTRY2(MMDC_P0 + MMDC_MDCFG0, 0x555A7975, 0x696D5323)
+
/*
- * MDCFG1, tRDC=8, tRP=8, tRC=27,tRAS=20,tRPA=tRP+1,tWR=8
- * tMRD=4, tCWL=6
+ * MDCFG1,
+ * MX6Q:
+ * tRDC=8, tRP=8, tRC=27, tRAS=20, tRPA=tRP+1, tWR=8, tMRD=4, tCWL=6
+ * MX6DL/SOLO:
+ * tRDC=6, tRP=6, tRC=20, tRAS=15, tRPA=tRP+1, tWR=7, tMRD=4, tCWL=5
*/
-WRITE_ENTRY1(MMDC_P0 + MMDC_MDCFG1, 0xFF538E64)
+WRITE_ENTRY2(MMDC_P0 + MMDC_MDCFG1, 0xFF538E64, 0xB66E8C63)
+
/*
* MDCFG2,tDLLK=512,tRTP=4,tWTR=4,tRRD=4
*/
WRITE_ENTRY1(MMDC_P0 + MMDC_MDCFG2, 0x01FF00DB)
WRITE_ENTRY1(MMDC_P0 + MMDC_MDRWD, 0x000026D2)
-
WRITE_ENTRY1(MMDC_P0 + MMDC_MDOR, 0x005B0E21)
-WRITE_ENTRY1(MMDC_P0 + MMDC_MDOTC, 0x09444040)
-WRITE_ENTRY1(MMDC_P0 + MMDC_MDPDC, 0x00025576)
/*
- * Mx6Q - 64 bit wide ddr
+ * MMDC_MDOTC,
+ * MX6Q:
+ * tAOFPD=2 cycles, tAONPD=2, tANPD=5, tAXPD=5, tODTLon=5, tODT_idle_off=5
+ * MX6DL/SOLO:
+ * tAOFPD=1 cycles, tAONPD=1, tANPD=4, tAXPD=4, tODTLon=4, tODT_idle_off=4
+ */
+WRITE_ENTRY2(MMDC_P0 + MMDC_MDOTC, 0x09444040, 0x00333030)
+
+/*
+ * MDPDC - [17:16](2) => CKE pulse width = 3 cycles.
+ * [15:12](5) => PWDT_1 = 256 cycles
+ * [11:8](5) =>PWDR_0 = 256 cycles
+ * MX6Q: [2:0](6) => CKSRE = 6 cycles, [5:3](6) => CKSRX = 6 cycles
+ * MX6DL/SOLO: [2:0](5) => CKSRE = 5 cycles, [5:3](5) => CKSRX = 5 cycles
+ */
+WRITE_ENTRY2(MMDC_P0 + MMDC_MDPDC, 0x00025576, 0x0002556D)
+
+/*
+ * MX6Q/DL - 64 bit wide ddr
* last address is (1<<28 (base) + 1<<30 - 1) / (1<<25) =
* 1<<3 + 1<<5 - 1 = 8 + 0x20 -1 = 0x27
*/
+/*
+ * MX6SOLO - 32 bit wide ddr
+ * last address is (1<<28 (base) + 1<<29 - 1) / (1<<25) =
+ * 1<<3 + 1<<4 - 1 = 8 + 0x10 -1 = 0x17
+ */
/* MDASP, CS0_END */
-WRITE_ENTRY1(MMDC_P0 + MMDC_MDASP, 0x00000027)
+WRITE_ENTRY3(MMDC_P0 + MMDC_MDASP, 0x00000027, 0x00000027, 0x00000017)
/*
- * MDCTL, CS0 enable, CS1 disabled, row=14, col=10, burst=8, width=64/32bit
- * mx6q : row+col+bank+width=14+10+3+3=30 = 1G
+ * MDCTL, CS0 enable, CS1 disabled, row=14, col=10, burst=8
+ * MX6Q/DL: width=64bit row+col+bank+width=14+10+3+3=30 = 1G
+ * MX6SOLO: width=32bit row+col+bank+width=14+10+3+2=29 = 512M
*/
-WRITE_ENTRY1(MMDC_P0 + MMDC_MDCTL, 0x831A0000)
+WRITE_ENTRY3(MMDC_P0 + MMDC_MDCTL, 0x831A0000, 0x831A0000, 0x83190000)
-/* MDSCR, con_req, LOAD MR2, CS0, A3,A10 set (CAS Write=6), RZQ/2 */
-WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x04088032)
+/*
+ * LOAD MR2: MDSCR, con_req, CS0, A10 set - RZQ/2
+ * MX6Q: A3 set(CAS Write=6)
+ * MX6DL/SOLO: (CAS Write=5)
+ */
+WRITE_ENTRY2(MMDC_P0 + MMDC_MDSCR, 0x04088032, 0x04008032)
/* LOAD MR3, CS0 */
WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x00008033)
-/* LOAD MR1, CS0, A1,A6 set Rtt=RZQ/2, ODI=RZQ/7 */
-WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x00428031)
-/* LOAD MR0, CS0, A6,A8,A11 set CAS=8, WR=8, DLL reset */
-WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x09408030)
+
+/*
+ * LOAD MR1, CS0
+ * MX6Q: A6 set: Rtt=RZQ/2, A1 set: ODI=RZQ/7
+ * MX6DL/SOLO: A2 set: Rtt=RZQ/4, ODI=RZQ/6
+ */
+WRITE_ENTRY2(MMDC_P0 + MMDC_MDSCR, 0x00428031, 0x00048031)
+
+/* LOAD MR0, CS0 A8 set: DLL Reset
+ * MX6Q: A6 set: CAS=8 A11 set: WR=8
+ * MX6DL/SOLO: A4 set: CAS=5, A9,A10 set: WR=7
+ */
+WRITE_ENTRY2(MMDC_P0 + MMDC_MDSCR, 0x09408030, 0x07208030)
/* ZQ calibrate, CS0 */
WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x04008040)
@@ -178,18 +235,18 @@ WRITE_ENTRY1(MMDC_P0 + MMDC_MPODTCTRL, 0x00022227)
WRITE_ENTRY1(MMDC_P1 + MMDC_MPODTCTRL, 0x00022227)
/* MPDGCTRL0/1 DQS GATE*/
-WRITE_ENTRY1(MMDC_P0 + MMDC_MPDGCTRL0, 0x434B0350)
-WRITE_ENTRY1(MMDC_P1 + MMDC_MPDGCTRL0, 0x434B0350)
-WRITE_ENTRY1(MMDC_P0 + MMDC_MPDGCTRL1, 0x034C0359)
-WRITE_ENTRY1(MMDC_P1 + MMDC_MPDGCTRL1, 0x03650348)
-WRITE_ENTRY1(MMDC_P0 + MMDC_MPRDDLCTL, 0x4436383B)
-WRITE_ENTRY1(MMDC_P1 + MMDC_MPRDDLCTL, 0x39393341)
-WRITE_ENTRY1(MMDC_P0 + MMDC_MPWRDLCTL, 0x35373933)
-WRITE_ENTRY1(MMDC_P1 + MMDC_MPWRDLCTL, 0x48254A36)
-WRITE_ENTRY1(MMDC_P0 + MMDC_MPWLDECTRL0, 0x001F001F)
-WRITE_ENTRY1(MMDC_P0 + MMDC_MPWLDECTRL1, 0x001F001F)
-WRITE_ENTRY1(MMDC_P1 + MMDC_MPWLDECTRL0, 0x00440044)
-WRITE_ENTRY1(MMDC_P1 + MMDC_MPWLDECTRL1, 0x00440044)
+WRITE_ENTRY2(MMDC_P0 + MMDC_MPDGCTRL0, 0x434B0350, 0x42350231)
+WRITE_ENTRY2(MMDC_P1 + MMDC_MPDGCTRL0, 0x434B0350, 0x42350231)
+WRITE_ENTRY2(MMDC_P0 + MMDC_MPDGCTRL1, 0x034C0359, 0x021A0218)
+WRITE_ENTRY2(MMDC_P1 + MMDC_MPDGCTRL1, 0x03650348, 0x021A0218)
+WRITE_ENTRY2(MMDC_P0 + MMDC_MPRDDLCTL, 0x4436383B, 0x4B4B4E49)
+WRITE_ENTRY2(MMDC_P1 + MMDC_MPRDDLCTL, 0x39393341, 0x4B4B4E49)
+WRITE_ENTRY2(MMDC_P0 + MMDC_MPWRDLCTL, 0x35373933, 0x3F3F3035)
+WRITE_ENTRY2(MMDC_P1 + MMDC_MPWRDLCTL, 0x48254A36, 0x3F3F3035)
+WRITE_ENTRY2(MMDC_P0 + MMDC_MPWLDECTRL0, 0x001F001F, 0x0040003C)
+WRITE_ENTRY2(MMDC_P0 + MMDC_MPWLDECTRL1, 0x001F001F, 0x0032003E)
+WRITE_ENTRY2(MMDC_P1 + MMDC_MPWLDECTRL0, 0x00440044, 0x0040003C)
+WRITE_ENTRY2(MMDC_P1 + MMDC_MPWLDECTRL1, 0x00440044, 0x0032003E)
/* MPMUR0 - Complete calibration by forced measurement */
WRITE_ENTRY1(MMDC_P0 + MMDC_MPMUR0, 0x00000800)
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 21/21] mx6qsabrelite: change CONFIG_SYS_PROMPT
2012-09-22 2:38 ` [U-Boot] [PATCH V2 00/21] Add mx6solo/mx6duallite support Troy Kisky
` (19 preceding siblings ...)
2012-09-22 2:39 ` [U-Boot] [PATCH V2 20/21] mx6q_4x_mt41j128.cfg: add mx6 solo/duallite support Troy Kisky
@ 2012-09-22 2:39 ` Troy Kisky
2012-09-22 6:21 ` [U-Boot] [PATCH V2 00/21] Add mx6solo/mx6duallite support Dirk Behme
2012-10-04 1:47 ` [U-Boot] [PATCH V3 00/32] " Troy Kisky
22 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-09-22 2:39 UTC (permalink / raw)
To: u-boot
The prompt is not appropriate if not running on
a mx6q processor.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
include/configs/mx6qsabrelite.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
index 72d0154..98fbb8d 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -182,7 +182,7 @@
/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT "MX6QSABRELITE U-Boot > "
+#define CONFIG_SYS_PROMPT "U-Boot > "
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE 256
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 17/21] mx6: soc: add get_cpu_type
2012-09-22 2:39 ` [U-Boot] [PATCH V2 17/21] mx6: soc: add get_cpu_type Troy Kisky
@ 2012-09-22 2:50 ` Fabio Estevam
2012-09-22 17:07 ` Troy Kisky
0 siblings, 1 reply; 430+ messages in thread
From: Fabio Estevam @ 2012-09-22 2:50 UTC (permalink / raw)
To: u-boot
Hi Troy,
On Fri, Sep 21, 2012 at 11:39 PM, Troy Kisky
<troy.kisky@boundarydevices.com> wrote:
> Add function to return the processor type.
>
> i.e. MX6Q, MX6DL, MX6SOLO, MX6SOLOLITE
On arch/arm/imx-common/cpu.c we have:
static const char *get_imx_type(u32 imxtype)
{
switch (imxtype) {
case 0x63:
return "6Q"; /* Quad-core version of the mx6 */
case 0x61:
return "6DS"; /* Dual/Solo version of the mx6 */
case 0x60:
return "6SL"; /* Solo-Lite version of the mx6 */
case 0x51:
return "51";
case 0x53:
return "53";
default:
return "??";
}
}
,which seems to serve the same purpose.
Regards,
Fabio Estevam
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 08/21] mx6: add plugin file for use with imximage.cfg
2012-09-22 2:39 ` [U-Boot] [PATCH V2 08/21] mx6: add plugin file for use with imximage.cfg Troy Kisky
@ 2012-09-22 4:06 ` Vikram Narayanan
2012-09-23 10:17 ` Stefano Babic
1 sibling, 0 replies; 430+ messages in thread
From: Vikram Narayanan @ 2012-09-22 4:06 UTC (permalink / raw)
To: u-boot
On 9/22/2012 8:09 AM, Troy Kisky wrote:
> The "plugin" command of mkimage can take this
> file as an argument.
An explanation of what is "plugin" and what the file plugin.S does
should be better. Not in the subject of the patch, you can place it as a
README.
>
> Signed-off-by: Troy Kisky<troy.kisky@boundarydevices.com>
> ---
> arch/arm/cpu/armv7/mx6/Makefile | 5 +-
> arch/arm/cpu/armv7/mx6/plugin.S | 164 ++++++++++++++++++++++++++++++
> arch/arm/include/asm/arch-mx6/imx-regs.h | 1 +
> 3 files changed, 169 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/cpu/armv7/mx6/plugin.S
>
> diff --git a/arch/arm/cpu/armv7/mx6/Makefile b/arch/arm/cpu/armv7/mx6/Makefile
> index cbce411..b1fce4e 100644
> --- a/arch/arm/cpu/armv7/mx6/Makefile
> +++ b/arch/arm/cpu/armv7/mx6/Makefile
> @@ -33,11 +33,14 @@ SOBJS = lowlevel_init.o
> SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
> OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
>
> -all: $(obj).depend $(LIB)
> +all: $(obj).depend $(LIB) plugin.bin
>
> $(LIB): $(OBJS)
> $(call cmd_link_o_target, $(OBJS))
>
> +plugin.bin: plugin.o
> + $(OBJCOPY) -O binary --gap-fill 0xff $< $@
> +
> #########################################################################
>
> # defines $(obj).depend target
> diff --git a/arch/arm/cpu/armv7/mx6/plugin.S b/arch/arm/cpu/armv7/mx6/plugin.S
> new file mode 100644
> index 0000000..99c6b20
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/mx6/plugin.S
> @@ -0,0 +1,164 @@
> +/*
> + * Copyright (C) 2012 Boundary Devices Inc.
> + *
> + * Licensed under the GPL-2 or later.
> + */
> +#include<config.h>
> +#include<asm/arch/imx-regs.h>
> +
> +#define HAB_RVT_ENTRY 0x98
> +#define HAB_RVT_FAIL_SAFE_VECT 0xbc
> +#define HAB_RVT_LOAD_DATA 0xc8
> +
> +#define HDR_SELF_PTR 0x14
> +#define HDR_BOOT_DATA 0x20
> +#define HDR_IMAGE_LEN 0x24
> +
> +#define L2X0_CTRL 0x100
> +#define SCU_CONFIG 0x004
> +
> +/*
> + * Disable L2 cache because ROM will turn it on when a plugin is used.
> + * There are cache coherence problems if cache is on when Linux kernel
> + * expects it to be off.
> + */
> +.macro disable_l2_cache
> + ldr r1, =L2_BASE_ADDR
> + mov r0, #0x0
> + str r0, [r1, #L2X0_CTRL]
> +.endm
> +
> +
> +/*
> + * plugin_start(void **start, size_t *bytes, UINT32 *ivt_offset)
> + */
> +plugin_start:
> +/* Save the return address and the function arguments */
> + push {r0-r8, lr}
> +
> +/* r0-r2 must be>= 0x100 and must be 4 byte aligned */
> + cmp r0, #0x100
> + cmphs r1, #0x100
> + cmphs r2, #0x100
> +
> +/* rCPU: 22 - mx6q, 12 - mx6dl, 12|0x100 - solo, 2 - sololite */
> +#define rCPU r2
> +#define rIomux r3
> +#define rVal0 r4 /* mx6q value */
> +#define rVal1 r5 /* mx6dl value */
> +#define rVal2 r6 /* mx6solo value */
> +#define rVal3 r7 /* mx6sololite value */
> +#define rFlag lr
> +#define rTable r8
> +
> + orr rFlag, r0, r1
> + orr rFlag, rFlag, r2
> + orrlo rFlag, rFlag, #1
> +
> + mov rCPU, #22 /* mx6q */
> + mov r1, #SCU_BASE_ADDR
> + ldr r0, [r1, #SCU_CONFIG]
> + and r0, r0, #3
> + cmp r0, #3 /* is mx6q? */
> + movne rCPU, #12 /* mx6dl */
> + cmpne r0, #1 /* is mx6dl? */
> + movne rCPU, #2 /* mx6 sololite */
> +
> + ldrne r1, =ANATOP_BASE_ADDR
> + ldrne r0, [r1, #0x280]
> + movne r0, r0, LSR #16
> + cmpne r0, #0x60 /* is mx6 Sololite? */
> + movne rCPU, #12 | 0x100 /* Solo */
> +
> + mov rVal0, #0
> + mov rVal1, #0
> + mov rVal2, #0
> + mov rVal3, #0
> + ldr rIomux, =IOMUXC_BASE_ADDR
> + adr rTable, mx6_table
> + b 3f
> +
> +1: movs r0, r1, LSR #30
> + beq 2f
> + mov r1, r1, LSL rCPU
> + movs r1, r1, LSR #32-10
> + addne r1, rIomux, r1, LSL #2
> + cmp r0, #3
> + subne r0, r0, #1
> + orr r1, r1, r0
> +
> +2: ands r0, r1, #3
> + bic r1, r1, #3
> + ldrne rVal0, [rTable], #4
> + movne rVal1, rVal0
> + movne rVal2, rVal0
> + movne rVal3, rVal0
> + subnes r0, r0, #1
> + ldrne rVal1, [rTable], #4
> + movne rVal2, rVal1
> + movne rVal3, rVal1
> + subnes r0, r0, #1
> + ldrne rVal2, [rTable], #4
> + ldrne rVal3, [rTable], #4
> +
> + mov r0, rVal0
> + cmp rCPU, #22
> + movne r0, rVal1
> + cmpne rCPU, #12
> + movne r0, rVal2
> + cmpne rCPU, #12|0x100
> + movne r0, rVal3
> + cmp r1, #0
> + strne r0, [r1]
> +3: ldr r1, [rTable], #4
> + cmp r1, #0
> + bne 1b
> +
> + tst rFlag, #3
> + bne 4f /* Branch if not called as plugin */
> +/* Align end of table to 64 byte boundary */
> + sub rTable, rTable, #1
> + orr rTable, rTable, #0x3f
> + add rTable, rTable, #1
> + ldr r2, [rTable, #HDR_SELF_PTR]
> + ldr r0, [rTable, #HDR_BOOT_DATA]
> + ldr r1, [rTable, #HDR_IMAGE_LEN]
> + sub rTable, r2, r0
> + mov r2, r0
> + mov r3, r1
> + mov r4, #0
> + push {r0-r4}
> + mov r0, #HAB_RVT_LOAD_DATA
> + ldr r4, [r0]
> + mov r0, sp
> + add r1, sp, #4
> + add r2, sp, #8
> + blx r4
> +
> + disable_l2_cache
> + pop {r4, r5}
> + add sp, sp, #12
> + pop {r0-r3}
> +/*
> + * Before returning to ROM, we need to fill the return values arguments
> + * to our function.
> + * plugin_start(void **start, size_t *bytes, UINT32 *ivt_offset)
> + */
> +
> + str r4, [r0]
> + str r5, [r1]
> + str rTable, [r2]
> + mov r0, #1
> + pop {r4-r8, pc}
> +
> +/* Not called as plugin */
> +4: popne {r0-r8, lr}
> + mov r0, #HAB_RVT_ENTRY
> + ldr lr, [r0]
> + blx lr
> + mov r0, #HAB_RVT_FAIL_SAFE_VECT
> + ldr lr, [r0]
> + blx lr
> +
> + .ltorg
> +mx6_table:
> diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
> index 8834c59..5c133b2 100644
> --- a/arch/arm/include/asm/arch-mx6/imx-regs.h
> +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
> @@ -48,6 +48,7 @@
> #define GLOBAL_TIMER_BASE_ADDR 0x00A00200
> #define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600
> #define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000
> +#define L2_BASE_ADDR 0x00A02000
> #define GPV0_BASE_ADDR 0x00B00000
> #define GPV1_BASE_ADDR 0x00C00000
> #define PCIE_ARB_BASE_ADDR 0x01000000
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 18/21] arch-mx6: add mx6dl_pins.h
2012-09-22 2:39 ` [U-Boot] [PATCH V2 18/21] arch-mx6: add mx6dl_pins.h Troy Kisky
@ 2012-09-22 4:10 ` Vikram Narayanan
2012-09-22 17:17 ` Troy Kisky
0 siblings, 1 reply; 430+ messages in thread
From: Vikram Narayanan @ 2012-09-22 4:10 UTC (permalink / raw)
To: u-boot
On 9/22/2012 8:09 AM, Troy Kisky wrote:
> Only the values used in the sabrelite board are
> added currently. Add more as other boards use them.
Though there are no users, better add it for completeness. This should
also avoid people patching this file often.
> Signed-off-by: Troy Kisky<troy.kisky@boundarydevices.com>
> ---
> arch/arm/include/asm/arch-mx6/mx6dl_pins.h | 118 ++++++++++++++++++++++++++++
> 1 file changed, 118 insertions(+)
> create mode 100644 arch/arm/include/asm/arch-mx6/mx6dl_pins.h
>
> diff --git a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
> new file mode 100644
> index 0000000..5848013
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
> @@ -0,0 +1,118 @@
> +/*
> + * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> +
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> +
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, write to the Free Software Foundation, Inc.,
> + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
> + *
> + */
> +
> +#ifndef __ASM_ARCH_MX6_MX6DL_PINS_H__
> +#define __ASM_ARCH_MX6_MX6DL_PINS_H__
> +
> +#include<asm/imx-common/iomux-v3.h>
> +
> +/* Use to set PAD control */
> +#define PAD_CTL_HYS (1<< 16)
> +#define PAD_CTL_PUS_100K_DOWN (0<< 14)
> +#define PAD_CTL_PUS_47K_UP (1<< 14)
> +#define PAD_CTL_PUS_100K_UP (2<< 14)
> +#define PAD_CTL_PUS_22K_UP (3<< 14)
> +
> +#define PAD_CTL_PUE (1<< 13)
> +#define PAD_CTL_PKE (1<< 12)
> +#define PAD_CTL_ODE (1<< 11)
> +#define PAD_CTL_SPEED_LOW (1<< 6)
> +#define PAD_CTL_SPEED_MED (2<< 6)
> +#define PAD_CTL_SPEED_HIGH (3<< 6)
> +#define PAD_CTL_DSE_DISABLE (0<< 3)
> +#define PAD_CTL_DSE_240ohm (1<< 3)
> +#define PAD_CTL_DSE_120ohm (2<< 3)
> +#define PAD_CTL_DSE_80ohm (3<< 3)
> +#define PAD_CTL_DSE_60ohm (4<< 3)
> +#define PAD_CTL_DSE_48ohm (5<< 3)
> +#define PAD_CTL_DSE_40ohm (6<< 3)
> +#define PAD_CTL_DSE_34ohm (7<< 3)
> +#define PAD_CTL_SRE_FAST (1<< 0)
> +#define PAD_CTL_SRE_SLOW (0<< 0)
> +
> +#define IOMUX_CONFIG_SION 0x10
> +#define NO_MUX_I 0
> +#define NO_PAD_I 0
> +enum {
> + MX6DL_PAD_EIM_D16__ECSPI1_SCLK = IOMUX_PAD(0x0514, 0x0144, 1, 0x07D8, 2, 0),
> + MX6DL_PAD_EIM_D17__ECSPI1_MISO = IOMUX_PAD(0x0518, 0x0148, 1, 0x07DC, 2, 0),
> + MX6DL_PAD_EIM_D18__ECSPI1_MOSI = IOMUX_PAD(0x051C, 0x014C, 1, 0x07E0, 2, 0),
> + MX6DL_PAD_EIM_D19__GPIO_3_19 = IOMUX_PAD(0x0520, 0x0150, 5, 0x0000, 0, 0),
> + MX6DL_PAD_EIM_D21__GPIO_3_21 = IOMUX_PAD(0x0528, 0x0158, 5, 0x0000, 0, 0),
> + MX6DL_PAD_EIM_D21__I2C1_SCL = IOMUX_PAD(0x0528, 0x0158, 6 | IOMUX_CONFIG_SION, 0x0868, 1, 0),
> + MX6DL_PAD_EIM_D23__GPIO_3_23 = IOMUX_PAD(0x0530, 0x0160, 5, 0x0000, 0, 0),
> + MX6DL_PAD_EIM_D26__UART2_TXD = IOMUX_PAD(0x053C, 0x016C, 4, 0x0000, 0, 0),
> + MX6DL_PAD_EIM_D27__UART2_RXD = IOMUX_PAD(0x0540, 0x0170, 4, 0x0904, 1, 0),
> + MX6DL_PAD_EIM_D28__I2C1_SDA = IOMUX_PAD(0x0544, 0x0174, 1 | IOMUX_CONFIG_SION, 0x086C, 1, 0),
> + MX6DL_PAD_EIM_D28__GPIO_3_28 = IOMUX_PAD(0x0544, 0x0174, 5, 0x0000, 0, 0),
> + MX6DL_PAD_ENET_MDC__ENET_MDC = IOMUX_PAD(0x05B8, 0x01E8, 1, 0x0000, 0, 0),
> + MX6DL_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x05BC, 0x01EC, 1, 0x0810, 0, 0),
> + MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK = IOMUX_PAD(0x05C0, 0x01F0, 1, 0x0000, 0, 0),
> + MX6DL_PAD_ENET_RXD0__GPIO_1_27 = IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0),
> + MX6DL_PAD_GPIO_16__GPIO_7_11 = IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0),
> + MX6DL_PAD_GPIO_16__I2C3_SDA = IOMUX_PAD(0x05E4, 0x0214, 6 | IOMUX_CONFIG_SION, 0x087C, 1, 0),
> + MX6DL_PAD_GPIO_17__GPIO_7_12 = IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0),
> + MX6DL_PAD_GPIO_18__GPIO_7_13 = IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0),
> + MX6DL_PAD_GPIO_19__GPIO_4_5 = IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0),
> + MX6DL_PAD_GPIO_5__GPIO_1_5 = IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0),
> + MX6DL_PAD_GPIO_5__I2C3_SCL = IOMUX_PAD(0x0600, 0x0230, 6 | IOMUX_CONFIG_SION, 0x0878, 2, 0),
> + MX6DL_PAD_KEY_COL3__I2C2_SCL = IOMUX_PAD(0x0638, 0x0250, 4 | IOMUX_CONFIG_SION, 0x0870, 1, 0),
> + MX6DL_PAD_KEY_COL3__GPIO_4_12 = IOMUX_PAD(0x0638, 0x0250, 5, 0x0000, 0, 0),
> + MX6DL_PAD_KEY_ROW3__I2C2_SDA = IOMUX_PAD(0x064C, 0x0264, 4 | IOMUX_CONFIG_SION, 0x0874, 1, 0),
> + MX6DL_PAD_KEY_ROW3__GPIO_4_13 = IOMUX_PAD(0x064C, 0x0264, 5, 0x0000, 0, 0),
> + MX6DL_PAD_NANDF_D1__GPIO_2_1 = IOMUX_PAD(0x0670, 0x0288, 5, 0x0000, 0, 0),
> + MX6DL_PAD_NANDF_D2__GPIO_2_2 = IOMUX_PAD(0x0674, 0x028C, 5, 0x0000, 0, 0),
> + MX6DL_PAD_NANDF_D3__GPIO_2_3 = IOMUX_PAD(0x0678, 0x0290, 5, 0x0000, 0, 0),
> + MX6DL_PAD_NANDF_D4__GPIO_2_4 = IOMUX_PAD(0x067C, 0x0294, 5, 0x0000, 0, 0),
> + MX6DL_PAD_NANDF_D6__GPIO_2_6 = IOMUX_PAD(0x0684, 0x029C, 5, 0x0000, 0, 0),
> + MX6DL_PAD_RGMII_RD0__ENET_RGMII_RD0 = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0818, 1, 0),
> + MX6DL_PAD_RGMII_RD0__GPIO_6_25 = IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0),
> + MX6DL_PAD_RGMII_RD1__ENET_RGMII_RD1 = IOMUX_PAD(0x0698, 0x02B0, 1, 0x081C, 1, 0),
> + MX6DL_PAD_RGMII_RD1__GPIO_6_27 = IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0),
> + MX6DL_PAD_RGMII_RD2__ENET_RGMII_RD2 = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0820, 1, 0),
> + MX6DL_PAD_RGMII_RD2__GPIO_6_28 = IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0),
> + MX6DL_PAD_RGMII_RD3__ENET_RGMII_RD3 = IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0824, 1, 0),
> + MX6DL_PAD_RGMII_RD3__GPIO_6_29 = IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0),
> + MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0828, 1, 0),
> + MX6DL_PAD_RGMII_RX_CTL__GPIO_6_24 = IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0),
> + MX6DL_PAD_RGMII_RXC__ENET_RGMII_RXC = IOMUX_PAD(0x06A8, 0x02C0, 1, 0x0814, 1, 0),
> + MX6DL_PAD_RGMII_RXC__GPIO_6_30 = IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0),
> + MX6DL_PAD_RGMII_TD0__ENET_RGMII_TD0 = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0),
> + MX6DL_PAD_RGMII_TD1__ENET_RGMII_TD1 = IOMUX_PAD(0x06B0, 0x02C8, 1, 0x0000, 0, 0),
> + MX6DL_PAD_RGMII_TD2__ENET_RGMII_TD2 = IOMUX_PAD(0x06B4, 0x02CC, 1, 0x0000, 0, 0),
> + MX6DL_PAD_RGMII_TD3__ENET_RGMII_TD3 = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0),
> + MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL = IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0),
> + MX6DL_PAD_RGMII_TXC__ENET_RGMII_TXC = IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0),
> + MX6DL_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x06F4, 0x030C, 0, 0x0934, 1, 0),
> + MX6DL_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x06F8, 0x0310, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
> + MX6DL_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0),
> + MX6DL_PAD_SD3_DAT1__USDHC3_DAT1 = IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0),
> + MX6DL_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0),
> + MX6DL_PAD_SD3_DAT3__USDHC3_DAT3 = IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0),
> + MX6DL_PAD_SD3_DAT5__GPIO_7_0 = IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0),
> + MX6DL_PAD_SD3_DAT6__UART1_RXD = IOMUX_PAD(0x0714, 0x032C, 1, 0x08FC, 2, 0),
> + MX6DL_PAD_SD3_DAT7__UART1_TXD = IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0),
> + MX6DL_PAD_SD4_CLK__USDHC4_CLK = IOMUX_PAD(0x0720, 0x0338, 0, 0x0938, 1, 0),
> + MX6DL_PAD_SD4_CMD__USDHC4_CMD = IOMUX_PAD(0x0724, 0x033C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
> + MX6DL_PAD_SD4_DAT0__USDHC4_DAT0 = IOMUX_PAD(0x0728, 0x0340, 1, 0x0000, 0, 0),
> + MX6DL_PAD_SD4_DAT1__USDHC4_DAT1 = IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0),
> + MX6DL_PAD_SD4_DAT2__USDHC4_DAT2 = IOMUX_PAD(0x0730, 0x0348, 1, 0x0000, 0, 0),
> + MX6DL_PAD_SD4_DAT3__USDHC4_DAT3 = IOMUX_PAD(0x0734, 0x034C, 1, 0x0000, 0, 0),
> +};
> +#endif /* __ASM_ARCH_MX6_MX6DL_PINS_H__ */
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 19/21] mx6qsabrelite: add support for mx6 solo/duallite
2012-09-22 2:39 ` [U-Boot] [PATCH V2 19/21] mx6qsabrelite: add support for mx6 solo/duallite Troy Kisky
@ 2012-09-22 4:12 ` Vikram Narayanan
2012-09-22 17:24 ` Troy Kisky
0 siblings, 1 reply; 430+ messages in thread
From: Vikram Narayanan @ 2012-09-22 4:12 UTC (permalink / raw)
To: u-boot
On 9/22/2012 8:09 AM, Troy Kisky wrote:
> Signed-off-by: Troy Kisky<troy.kisky@boundarydevices.com>
> ---
> board/freescale/mx6qsabrelite/mx6qsabrelite.c | 231 ++++++-------------------
> board/freescale/mx6qsabrelite/pads.h | 172 ++++++++++++++++++
> 2 files changed, 226 insertions(+), 177 deletions(-)
> create mode 100644 board/freescale/mx6qsabrelite/pads.h
>
> diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
> index 4b4e89b..ad2347d 100644
> --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
> +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
> @@ -26,6 +26,8 @@
> #include<asm/arch/imx-regs.h>
> #include<asm/arch/iomux.h>
> #include<asm/arch/mx6x_pins.h>
> +#include<asm/arch/mx6dl_pins.h>
> +#include<asm/arch/sys_proto.h>
> #include<asm/errno.h>
> #include<asm/gpio.h>
> #include<asm/imx-common/iomux-v3.h>
> @@ -38,163 +40,46 @@
> #include<netdev.h>
> DECLARE_GLOBAL_DATA_PTR;
>
> -#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
> - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
> - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
> +#include "pads.h"
> +#define FOR_DL_SOLO
> +#include "pads.h"
>
> -#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
> - PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
> - PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
> +int cpu_is_mx6q(void)
> +{
> + return get_cpu_type() == MXC_CPU_MX6Q;
> +}
>
> -#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
> - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
> - PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
> +#define IOMUX_SETUP(list) iomux_setup(mx6q_##list, ARRAY_SIZE(mx6q_##list), \
> + mx6dl_solo_##list, ARRAY_SIZE(mx6dl_solo_##list))
>
> -#define SPI_PAD_CTRL (PAD_CTL_HYS | \
> - PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
> - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
> +int iomux_setup(iomux_v3_cfg_t *mx6q_pad_list, int mx6q_pad_cnt,
> + iomux_v3_cfg_t *mx6dl_solo_pad_list, int mx6dl_solo_pad_cnt)
> +{
> + int mx6q = cpu_is_mx6q();
> + iomux_v3_cfg_t *p = mx6q ? mx6q_pad_list : mx6dl_solo_pad_list;
> + int cnt = mx6q ? mx6q_pad_cnt : mx6dl_solo_pad_cnt;
>
> -#define BUTTON_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
> - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
> - PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
> + return imx_iomux_v3_setup_multiple_pads(p, cnt);
> +}
>
> -#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
> - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
> - PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
> - PAD_CTL_ODE | PAD_CTL_SRE_FAST)
> +static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
> +static const unsigned char bank_lookup[] = {3, 2};
>
> int dram_init(void)
> {
> - gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
> -
> - return 0;
> + unsigned mdctl = readl(MMDC_P0_BASE_ADDR + 0x000);
> + unsigned mdmisc = readl(MMDC_P0_BASE_ADDR + 0x018);
> + int bits = 11 + 0 + 0 + 1; /* row+col+bank+width */
> +
> + bits += (mdctl>> 24)& 7; /* row */
> + bits += col_lookup[(mdctl>> 20)& 7]; /* col */
> + bits += bank_lookup[(mdmisc>> 5)& 1]; /* bank */
> + bits += (mdctl>> 16)& 3; /* width */
> + bits += (mdctl>> 30)& 1; /* cs1 enabled*/
> + gd->ram_size = 1<< bits;
> + return 0;
> }
>
No magic numbers please. Replace it with macros.
Regards,
Vikram
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 00/21] Add mx6solo/mx6duallite support
2012-09-22 2:38 ` [U-Boot] [PATCH V2 00/21] Add mx6solo/mx6duallite support Troy Kisky
` (20 preceding siblings ...)
2012-09-22 2:39 ` [U-Boot] [PATCH V2 21/21] mx6qsabrelite: change CONFIG_SYS_PROMPT Troy Kisky
@ 2012-09-22 6:21 ` Dirk Behme
2012-09-22 16:53 ` Troy Kisky
2012-10-04 1:47 ` [U-Boot] [PATCH V3 00/32] " Troy Kisky
22 siblings, 1 reply; 430+ messages in thread
From: Dirk Behme @ 2012-09-22 6:21 UTC (permalink / raw)
To: u-boot
Hi Troy,
On 22.09.2012 04:38, Troy Kisky wrote:
> After this series the same binary will run on a
> Saberlite board using any of the pin compatible processors
> mx6 quad, mx6 duallite, or mx6 solo. This is accomplished
> using a plugin and a table built by mkimage.
Could you briefly explain or give a link to some documentation how
this does work? It sounds to me that the plugin concept is something
the boot ROM has to understand? Or in other words: How does the boot
ROM decide on which processor it runs and which DCD table to execute then?
Sorry if I misunderstood something, I'm not so familiar with the boot
ROM options.
Many thanks
Dirk
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 00/21] Add mx6solo/mx6duallite support
2012-09-22 6:21 ` [U-Boot] [PATCH V2 00/21] Add mx6solo/mx6duallite support Dirk Behme
@ 2012-09-22 16:53 ` Troy Kisky
0 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-09-22 16:53 UTC (permalink / raw)
To: u-boot
On 9/21/2012 11:21 PM, Dirk Behme wrote:
> Hi Troy,
>
> On 22.09.2012 04:38, Troy Kisky wrote:
>> After this series the same binary will run on a
>> Saberlite board using any of the pin compatible processors
>> mx6 quad, mx6 duallite, or mx6 solo. This is accomplished
>> using a plugin and a table built by mkimage.
>
> Could you briefly explain or give a link to some documentation how
> this does work? It sounds to me that the plugin concept is something
> the boot ROM has to understand? Or in other words: How does the boot
> ROM decide on which processor it runs and which DCD table to execute
> then?
>
> Sorry if I misunderstood something, I'm not so familiar with the boot
> ROM options.
>
> Many thanks
>
> Dirk
>
The table generated by mkimage for use with the plugin is not a standard
ROM decodable table.
Only the plugin itself will decode the table. After it processes the
table to initialize memory,
it calls back into the ROM to finish the u-boot load.
see file arch/arm/include/asm/arch-mx6/imx-mkimage.h
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 17/21] mx6: soc: add get_cpu_type
2012-09-22 2:50 ` Fabio Estevam
@ 2012-09-22 17:07 ` Troy Kisky
2012-09-23 14:59 ` Stefano Babic
0 siblings, 1 reply; 430+ messages in thread
From: Troy Kisky @ 2012-09-22 17:07 UTC (permalink / raw)
To: u-boot
On 9/21/2012 7:50 PM, Fabio Estevam wrote:
> Hi Troy,
>
> On Fri, Sep 21, 2012 at 11:39 PM, Troy Kisky
> <troy.kisky@boundarydevices.com> wrote:
>> Add function to return the processor type.
>>
>> i.e. MX6Q, MX6DL, MX6SOLO, MX6SOLOLITE
> On arch/arm/imx-common/cpu.c we have:
>
> static const char *get_imx_type(u32 imxtype)
> {
> switch (imxtype) {
> case 0x63:
> return "6Q"; /* Quad-core version of the mx6 */
> case 0x61:
> return "6DS"; /* Dual/Solo version of the mx6 */
> case 0x60:
> return "6SL"; /* Solo-Lite version of the mx6 */
> case 0x51:
> return "51";
> case 0x53:
> return "53";
> default:
> return "??";
> }
> }
>
> ,which seems to serve the same purpose.
>
> Regards,
>
> Fabio Estevam
>
No, not similar to get_imx_type, but it is similar to get_cpu_rev.
I guess I should fix get_imx_type, and get_cpu_rev, instead of
adding a new one.
Thanks for the heads up!
Troy
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 18/21] arch-mx6: add mx6dl_pins.h
2012-09-22 4:10 ` Vikram Narayanan
@ 2012-09-22 17:17 ` Troy Kisky
0 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-09-22 17:17 UTC (permalink / raw)
To: u-boot
On 9/21/2012 9:10 PM, Vikram Narayanan wrote:
> On 9/22/2012 8:09 AM, Troy Kisky wrote:
>> Only the values used in the sabrelite board are
>> added currently. Add more as other boards use them.
>
> Though there are no users, better add it for completeness. This should
> also avoid people patching this file often.
>
>
U-boot has a policy of not adding dead code. One patch per added board
will not cause a burden. Also,
since the entries are sorted, merge conflicts should be rare.
Troy
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 19/21] mx6qsabrelite: add support for mx6 solo/duallite
2012-09-22 4:12 ` Vikram Narayanan
@ 2012-09-22 17:24 ` Troy Kisky
0 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-09-22 17:24 UTC (permalink / raw)
To: u-boot
On 9/21/2012 9:12 PM, Vikram Narayanan wrote:
> On 9/22/2012 8:09 AM, Troy Kisky wrote:
>> Signed-off-by: Troy Kisky<troy.kisky@boundarydevices.com>
>> ---
>> board/freescale/mx6qsabrelite/mx6qsabrelite.c | 231
>> ++++++-------------------
>> board/freescale/mx6qsabrelite/pads.h | 172
>> ++++++++++++++++++
>> 2 files changed, 226 insertions(+), 177 deletions(-)
>> create mode 100644 board/freescale/mx6qsabrelite/pads.h
>>
>> diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
>> b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
>> index 4b4e89b..ad2347d 100644
>> --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
>> +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
>> @@ -26,6 +26,8 @@
>> #include<asm/arch/imx-regs.h>
>> #include<asm/arch/iomux.h>
>> #include<asm/arch/mx6x_pins.h>
>> +#include<asm/arch/mx6dl_pins.h>
>> +#include<asm/arch/sys_proto.h>
>> #include<asm/errno.h>
>> #include<asm/gpio.h>
>> #include<asm/imx-common/iomux-v3.h>
>> @@ -38,163 +40,46 @@
>> #include<netdev.h>
>> DECLARE_GLOBAL_DATA_PTR;
>>
>> -#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
>> - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
>> - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
>> +#include "pads.h"
>> +#define FOR_DL_SOLO
>> +#include "pads.h"
>>
>> -#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
>> - PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
>> - PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
>> +int cpu_is_mx6q(void)
>> +{
>> + return get_cpu_type() == MXC_CPU_MX6Q;
>> +}
>>
>> -#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
>> - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
>> - PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
>> +#define IOMUX_SETUP(list) iomux_setup(mx6q_##list,
>> ARRAY_SIZE(mx6q_##list), \
>> + mx6dl_solo_##list, ARRAY_SIZE(mx6dl_solo_##list))
>>
>> -#define SPI_PAD_CTRL (PAD_CTL_HYS | \
>> - PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
>> - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
>> +int iomux_setup(iomux_v3_cfg_t *mx6q_pad_list, int mx6q_pad_cnt,
>> + iomux_v3_cfg_t *mx6dl_solo_pad_list, int mx6dl_solo_pad_cnt)
>> +{
>> + int mx6q = cpu_is_mx6q();
>> + iomux_v3_cfg_t *p = mx6q ? mx6q_pad_list : mx6dl_solo_pad_list;
>> + int cnt = mx6q ? mx6q_pad_cnt : mx6dl_solo_pad_cnt;
>>
>> -#define BUTTON_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
>> - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
>> - PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
>> + return imx_iomux_v3_setup_multiple_pads(p, cnt);
>> +}
>>
>> -#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
>> - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
>> - PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
>> - PAD_CTL_ODE | PAD_CTL_SRE_FAST)
>> +static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
>> +static const unsigned char bank_lookup[] = {3, 2};
>>
>> int dram_init(void)
>> {
>> - gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
>> PHYS_SDRAM_SIZE);
>> -
>> - return 0;
>> + unsigned mdctl = readl(MMDC_P0_BASE_ADDR + 0x000);
>> + unsigned mdmisc = readl(MMDC_P0_BASE_ADDR + 0x018);
>> + int bits = 11 + 0 + 0 + 1; /* row+col+bank+width */
>> +
>> + bits += (mdctl>> 24)& 7; /* row */
>> + bits += col_lookup[(mdctl>> 20)& 7]; /* col */
>> + bits += bank_lookup[(mdmisc>> 5)& 1]; /* bank */
>> + bits += (mdctl>> 16)& 3; /* width */
>> + bits += (mdctl>> 30)& 1; /* cs1 enabled*/
>> + gd->ram_size = 1<< bits;
>> + return 0;
>> }
>>
>
> No magic numbers please. Replace it with macros.
Right, will move to a common file as well so that other may use it.
Troy
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 15/21] mx6q_4x_mt41j128.cfg: reorder for more efficient storage
2012-09-22 2:39 ` [U-Boot] [PATCH V2 15/21] mx6q_4x_mt41j128.cfg: reorder for more efficient storage Troy Kisky
@ 2012-09-22 17:27 ` Fabio Estevam
2012-09-22 17:34 ` Troy Kisky
0 siblings, 1 reply; 430+ messages in thread
From: Fabio Estevam @ 2012-09-22 17:27 UTC (permalink / raw)
To: u-boot
Hi Troy,
On Fri, Sep 21, 2012 at 11:39 PM, Troy Kisky
<troy.kisky@boundarydevices.com> wrote:
> Repeating data values can be stored more efficiently.
>
> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
I am not a ddr init expert, but my understanding is that the DDR init sequence
is important and probably we should keep it as is.
Regards,
Fabio Estevam
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 15/21] mx6q_4x_mt41j128.cfg: reorder for more efficient storage
2012-09-22 17:27 ` Fabio Estevam
@ 2012-09-22 17:34 ` Troy Kisky
0 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-09-22 17:34 UTC (permalink / raw)
To: u-boot
On 9/22/2012 10:27 AM, Fabio Estevam wrote:
> Hi Troy,
>
> On Fri, Sep 21, 2012 at 11:39 PM, Troy Kisky
> <troy.kisky@boundarydevices.com> wrote:
>> Repeating data values can be stored more efficiently.
>>
>> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
> I am not a ddr init expert, but my understanding is that the DDR init sequence
> is important and probably we should keep it as is.
>
> Regards,
>
> Fabio Estevam
>
The order of writes to IOMUXC registers is not important, other than to
be finished
before accessing the DDR chips.
Troy
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 08/21] mx6: add plugin file for use with imximage.cfg
2012-09-22 2:39 ` [U-Boot] [PATCH V2 08/21] mx6: add plugin file for use with imximage.cfg Troy Kisky
2012-09-22 4:06 ` Vikram Narayanan
@ 2012-09-23 10:17 ` Stefano Babic
2012-09-23 16:23 ` Eric Nelson
2012-09-24 20:46 ` Troy Kisky
1 sibling, 2 replies; 430+ messages in thread
From: Stefano Babic @ 2012-09-23 10:17 UTC (permalink / raw)
To: u-boot
On 22/09/2012 04:39, Troy Kisky wrote:
> The "plugin" command of mkimage can take this
> file as an argument.
>
> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
> ---
Hi Troy,
I agree with Vikram that a better explanation of what a plugin is can
help to understand without reading deeply into the i.MX6 manual.
So a "plugin" is a chunk of code that can be called directly by the
BootROM of i.MX processors supporting V2 version of the i.MX header.
In my understanding, this is supported by i.MX53, too. After the plugin
run, the control is returned to the BootROM.
Now that we have some basis, why do we need this mechanism to boot this
board ? Is it not possible to make the same initialization directly in
u-boot ?
In principle, this adds stil some code that is not so easy to maintain.
> arch/arm/cpu/armv7/mx6/Makefile | 5 +-
> arch/arm/cpu/armv7/mx6/plugin.S | 164 ++++++++++++++++++++++++++++++
> arch/arm/include/asm/arch-mx6/imx-regs.h | 1 +
> 3 files changed, 169 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/cpu/armv7/mx6/plugin.S
>
> diff --git a/arch/arm/cpu/armv7/mx6/Makefile b/arch/arm/cpu/armv7/mx6/Makefile
> index cbce411..b1fce4e 100644
> --- a/arch/arm/cpu/armv7/mx6/Makefile
> +++ b/arch/arm/cpu/armv7/mx6/Makefile
> @@ -33,11 +33,14 @@ SOBJS = lowlevel_init.o
> SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
> OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
>
> -all: $(obj).depend $(LIB)
> +all: $(obj).depend $(LIB) plugin.bin
>
> $(LIB): $(OBJS)
> $(call cmd_link_o_target, $(OBJS))
>
> +plugin.bin: plugin.o
> + $(OBJCOPY) -O binary --gap-fill 0xff $< $@
If we add a plugin mechanism, we can have several plugins (booting
directly from Net, maybe ?). We should then have a general mechanism. A
directory "plugins" here can contain the code, and it is compiled only
if a CONFIG_ is set or better if required from imximage.cfg
> +
> #########################################################################
>
> # defines $(obj).depend target
> diff --git a/arch/arm/cpu/armv7/mx6/plugin.S b/arch/arm/cpu/armv7/mx6/plugin.S
> new file mode 100644
> index 0000000..99c6b20
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/mx6/plugin.S
> @@ -0,0 +1,164 @@
> +/*
> + * Copyright (C) 2012 Boundary Devices Inc.
> + *
> + * Licensed under the GPL-2 or later.
> + */
> +#include <config.h>
> +#include <asm/arch/imx-regs.h>
> +
> +#define HAB_RVT_ENTRY 0x98
> +#define HAB_RVT_FAIL_SAFE_VECT 0xbc
> +#define HAB_RVT_LOAD_DATA 0xc8
> +
> +#define HDR_SELF_PTR 0x14
> +#define HDR_BOOT_DATA 0x20
> +#define HDR_IMAGE_LEN 0x24
> +
> +#define L2X0_CTRL 0x100
> +#define SCU_CONFIG 0x004
> +
> +/*
> + * Disable L2 cache because ROM will turn it on when a plugin is used.
> + * There are cache coherence problems if cache is on when Linux kernel
> + * expects it to be off.
> + */
> +.macro disable_l2_cache
> + ldr r1, =L2_BASE_ADDR
> + mov r0, #0x0
> + str r0, [r1, #L2X0_CTRL]
> +.endm
> +
> +
> +/*
> + * plugin_start(void **start, size_t *bytes, UINT32 *ivt_offset)
> + */
> +plugin_start:
> +/* Save the return address and the function arguments */
> + push {r0-r8, lr}
> +
> +/* r0-r2 must be >= 0x100 and must be 4 byte aligned */
> + cmp r0, #0x100
> + cmphs r1, #0x100
> + cmphs r2, #0x100
> +
> +/* rCPU: 22 - mx6q, 12 - mx6dl, 12|0x100 - solo, 2 - sololite */
> +#define rCPU r2
> +#define rIomux r3
> +#define rVal0 r4 /* mx6q value */
> +#define rVal1 r5 /* mx6dl value */
> +#define rVal2 r6 /* mx6solo value */
> +#define rVal3 r7 /* mx6sololite value */
> +#define rFlag lr
> +#define rTable r8
> +
> + orr rFlag, r0, r1
> + orr rFlag, rFlag, r2
> + orrlo rFlag, rFlag, #1
> +
> + mov rCPU, #22 /* mx6q */
> + mov r1, #SCU_BASE_ADDR
> + ldr r0, [r1, #SCU_CONFIG]
> + and r0, r0, #3
> + cmp r0, #3 /* is mx6q? */
> + movne rCPU, #12 /* mx6dl */
> + cmpne r0, #1 /* is mx6dl? */
> + movne rCPU, #2 /* mx6 sololite */
> +
> + ldrne r1, =ANATOP_BASE_ADDR
> + ldrne r0, [r1, #0x280]
> + movne r0, r0, LSR #16
> + cmpne r0, #0x60 /* is mx6 Sololite? */
> + movne rCPU, #12 | 0x100 /* Solo */
Ok - until here you have checked which processor is running. Now the
more obscure code:
> +
> + mov rVal0, #0
> + mov rVal1, #0
> + mov rVal2, #0
> + mov rVal3, #0
> + ldr rIomux, =IOMUXC_BASE_ADDR
> + adr rTable, mx6_table
> + b 3f
> +
> +1: movs r0, r1, LSR #30
> + beq 2f
> + mov r1, r1, LSL rCPU
> + movs r1, r1, LSR #32-10
> + addne r1, rIomux, r1, LSL #2
> + cmp r0, #3
> + subne r0, r0, #1
> + orr r1, r1, r0
> +
The reason is to write GPR12 ? But why do we need a plugin for that ? I
do not understand why we cannot do it in the initialization code of the
SOC, as we usually do.
> +2: ands r0, r1, #3
> + bic r1, r1, #3
> + ldrne rVal0, [rTable], #4
> + movne rVal1, rVal0
> + movne rVal2, rVal0
> + movne rVal3, rVal0
> + subnes r0, r0, #1
> + ldrne rVal1, [rTable], #4
> + movne rVal2, rVal1
> + movne rVal3, rVal1
> + subnes r0, r0, #1
> + ldrne rVal2, [rTable], #4
> + ldrne rVal3, [rTable], #4
> +
> + mov r0, rVal0
> + cmp rCPU, #22
> + movne r0, rVal1
> + cmpne rCPU, #12
> + movne r0, rVal2
> + cmpne rCPU, #12|0x100
> + movne r0, rVal3
> + cmp r1, #0
> + strne r0, [r1]
> +3: ldr r1, [rTable], #4
> + cmp r1, #0
> + bne 1b
> +
> + tst rFlag, #3
> + bne 4f /* Branch if not called as plugin */
> +/* Align end of table to 64 byte boundary */
> + sub rTable, rTable, #1
> + orr rTable, rTable, #0x3f
> + add rTable, rTable, #1
> + ldr r2, [rTable, #HDR_SELF_PTR]
> + ldr r0, [rTable, #HDR_BOOT_DATA]
> + ldr r1, [rTable, #HDR_IMAGE_LEN]
> + sub rTable, r2, r0
> + mov r2, r0
> + mov r3, r1
> + mov r4, #0
> + push {r0-r4}
> + mov r0, #HAB_RVT_LOAD_DATA
> + ldr r4, [r0]
> + mov r0, sp
> + add r1, sp, #4
> + add r2, sp, #8
> + blx r4
Sorry, I need help to understand this code
> +
> + disable_l2_cache
> + pop {r4, r5}
> + add sp, sp, #12
> + pop {r0-r3}
> +/*
> + * Before returning to ROM, we need to fill the return values arguments
> + * to our function.
> + * plugin_start(void **start, size_t *bytes, UINT32 *ivt_offset)
As the i.MX and the API suggest, it should be possible to write C code
for a plugin. Or am I wrong ?
> diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
> index 8834c59..5c133b2 100644
> --- a/arch/arm/include/asm/arch-mx6/imx-regs.h
> +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
> @@ -48,6 +48,7 @@
> #define GLOBAL_TIMER_BASE_ADDR 0x00A00200
> #define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600
> #define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000
> +#define L2_BASE_ADDR 0x00A02000
> #define GPV0_BASE_ADDR 0x00B00000
> #define GPV1_BASE_ADDR 0x00C00000
> #define PCIE_ARB_BASE_ADDR 0x01000000
>
This is useful in any case. I suggest you put this define in a separate
patch, that can flow independently into mainline.
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 01/21] imximage: make header variable length
2012-09-22 2:38 ` [U-Boot] [PATCH V2 01/21] imximage: make header variable length Troy Kisky
@ 2012-09-23 10:57 ` Stefano Babic
2012-09-24 20:30 ` Troy Kisky
0 siblings, 1 reply; 430+ messages in thread
From: Stefano Babic @ 2012-09-23 10:57 UTC (permalink / raw)
To: u-boot
On 22/09/2012 04:38, Troy Kisky wrote:
Hi Troy,
> Also, the header offset is no longer
> right before the code starts.
Comment and subject of the patch do not match. Can you better explain it
? What have "making header variable length", that is, a new feature,
with " the header offset is no longer rigth", that is, a bug ?
Do we already have a variable header the we add a vrec_header function
to image_type_params ?
> Series tested on an mx51 and mx6q
> ---
> tools/imximage.c | 142 +++++++++++++++++++++++++++++++-----------------------
> tools/imximage.h | 10 ++--
> 2 files changed, 87 insertions(+), 65 deletions(-)
>
> diff --git a/tools/imximage.c b/tools/imximage.c
> index 03a7716..25d3b74 100644
> --- a/tools/imximage.c
> +++ b/tools/imximage.c
> @@ -65,12 +65,15 @@ static table_entry_t imximage_versions[] = {
> {-1, "", " (Invalid)", },
> };
>
> -static struct imx_header imximage_header;
> static uint32_t imximage_version;
>
> static set_dcd_val_t set_dcd_val;
> static set_dcd_rst_t set_dcd_rst;
> static set_imx_hdr_t set_imx_hdr;
> +static set_imx_size_t set_imx_size;
> +static uint32_t g_flash_offset;
> +
> +static struct image_type_params imximage_params;
>
> static uint32_t get_cfg_value(char *token, char *name, int linenr)
> {
> @@ -207,85 +210,79 @@ static void set_dcd_rst_v2(struct imx_header *imxhdr, uint32_t dcd_len,
> dcd_v2->write_dcd_command.param = DCD_COMMAND_PARAM;
> }
>
> -static void set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,
> - struct stat *sbuf,
> - struct mkimage_params *params)
> +static int set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,
> + uint32_t entry_point, uint32_t flash_offset)
> {
> imx_header_v1_t *hdr_v1 = &imxhdr->header.hdr_v1;
> flash_header_v1_t *fhdr_v1 = &hdr_v1->fhdr;
> dcd_v1_t *dcd_v1 = &hdr_v1->dcd_table;
> - uint32_t base_offset;
> -
> - /* Exit if there is no BOOT_FROM field specifying the flash_offset */
> - if(imxhdr->flash_offset == FLASH_OFFSET_UNDEFINED) {
> - fprintf(stderr, "Error: Header v1: No BOOT_FROM tag in %s\n",
> - params->imagename);
> - exit(EXIT_FAILURE);
> - }
Do you drop BOOT_FROM ? Then this should be documented. Is this to allow
that the same image can be loaded from different media, that share the
same flash offset ? Then, instead of drop it, I suggest to add more
entries in the imximage file, one for each media that is allow.
Something like:
BOOT_FROM sd, nand, spi
and maybe a check in the code if all entries do not share the same start
address.
> + uint32_t hdr_base;
> + uint32_t header_length = (((char *)&dcd_v1->addr_data[dcd_len].addr)
> + - ((char *)imxhdr));
>
For V1, the header is preallocated with the maximum size, that is the
maximum number of DCD entries the SOC in V1 can support. Why do we need
a dynamic length for V1 processors ? As far as I know, the number of
entries and fields for theses SOCs (i.MX25, i.MX35, i.MX51) is fixed.
> /* Set magic number */
> fhdr_v1->app_code_barker = APP_CODE_BARKER;
>
> - fhdr_v1->app_dest_ptr = params->addr;
> - fhdr_v1->app_dest_ptr = params->ep - imxhdr->flash_offset -
> - sizeof(struct imx_header);
> - fhdr_v1->app_code_jump_vector = params->ep;
> + hdr_base = entry_point - header_length;
> + fhdr_v1->app_dest_ptr = hdr_base - flash_offset;
> + fhdr_v1->app_code_jump_vector = entry_point;
>
> - base_offset = fhdr_v1->app_dest_ptr + imxhdr->flash_offset ;
> - fhdr_v1->dcd_ptr_ptr =
> - (uint32_t) (offsetof(flash_header_v1_t, dcd_ptr) -
> - offsetof(flash_header_v1_t, app_code_jump_vector) +
> - base_offset);
> -
> - fhdr_v1->dcd_ptr = base_offset +
> - offsetof(imx_header_v1_t, dcd_table);
> -
> - /* The external flash header must be at the end of the DCD table */
> - dcd_v1->addr_data[dcd_len].type = sbuf->st_size +
> - imxhdr->flash_offset +
> - sizeof(struct imx_header);
> + fhdr_v1->dcd_ptr_ptr = hdr_base + offsetof(flash_header_v1_t, dcd_ptr);
> + fhdr_v1->dcd_ptr = hdr_base + offsetof(imx_header_v1_t, dcd_table);
>
> /* Security feature are not supported */
> fhdr_v1->app_code_csf = 0;
> fhdr_v1->super_root_key = 0;
> + return header_length;
> +}
> +
Ok, I skip review of this part - it depends on your answer on the
previous question.
>
> -static void set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t dcd_len,
> - struct stat *sbuf,
> - struct mkimage_params *params)
> +static int set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t dcd_len,
> + uint32_t entry_point, uint32_t flash_offset)
> {
> imx_header_v2_t *hdr_v2 = &imxhdr->header.hdr_v2;
> flash_header_v2_t *fhdr_v2 = &hdr_v2->fhdr;
> -
> - /* Exit if there is no BOOT_FROM field specifying the flash_offset */
> - if(imxhdr->flash_offset == FLASH_OFFSET_UNDEFINED) {
> - fprintf(stderr, "Error: Header v2: No BOOT_FROM tag in %s\n",
> - params->imagename);
> - exit(EXIT_FAILURE);
> - }
> + uint32_t hdr_base;
> + uint32_t header_length = (dcd_len) ?
> + (char *)&hdr_v2->dcd_table.addr_data[dcd_len] - ((char*)imxhdr)
> + : offsetof(imx_header_v2_t, dcd_table);
So you add a case where there is no DCD table at all. Apart that this
van be a use case, but does it happen in the real life ?
> /* Set magic number */
> fhdr_v2->header.tag = IVT_HEADER_TAG; /* 0xD1 */
> fhdr_v2->header.length = cpu_to_be16(sizeof(flash_header_v2_t));
> fhdr_v2->header.version = IVT_VERSION; /* 0x40 */
>
> - fhdr_v2->entry = params->ep;
> + fhdr_v2->entry = entry_point;
> fhdr_v2->reserved1 = fhdr_v2->reserved2 = 0;
> - fhdr_v2->self = params->ep - sizeof(struct imx_header);
> -
> - fhdr_v2->dcd_ptr = fhdr_v2->self +
> - offsetof(imx_header_v2_t, dcd_table);
> + fhdr_v2->self = hdr_base = entry_point - header_length;
>
> - fhdr_v2->boot_data_ptr = fhdr_v2->self +
> - offsetof(imx_header_v2_t, boot_data);
> -
> - hdr_v2->boot_data.start = fhdr_v2->self - imxhdr->flash_offset;
> - hdr_v2->boot_data.size = sbuf->st_size +
> - imxhdr->flash_offset +
> - sizeof(struct imx_header);
> + fhdr_v2->dcd_ptr = (dcd_len) ? hdr_base
> + + offsetof(imx_header_v2_t, dcd_table) : 0;
> + fhdr_v2->boot_data_ptr = hdr_base
> + + offsetof(imx_header_v2_t, boot_data);
> + hdr_v2->boot_data.start = hdr_base - flash_offset;
>
> /* Security feature are not supported */
> fhdr_v2->csf = 0;
> + return header_length;
> +}
> +
> +static void set_imx_size_v2(struct imx_header *imxhdr, uint32_t file_size,
> + uint32_t flash_offset)
> +{
> + imx_header_v2_t *hdr_v2 = &imxhdr->header.hdr_v2;
> + /* file_size includes header */
> + hdr_v2->boot_data.size = file_size + flash_offset;
> }
>
> static void set_hdr_func(struct imx_header *imxhdr)
> @@ -295,11 +292,13 @@ static void set_hdr_func(struct imx_header *imxhdr)
> set_dcd_val = set_dcd_val_v1;
> set_dcd_rst = set_dcd_rst_v1;
> set_imx_hdr = set_imx_hdr_v1;
> + set_imx_size = set_imx_size_v1;
> break;
> case IMXIMAGE_V2:
> set_dcd_val = set_dcd_val_v2;
> set_dcd_rst = set_dcd_rst_v2;
> set_imx_hdr = set_imx_hdr_v2;
> + set_imx_size = set_imx_size_v2;
> break;
> default:
> err_imximage_version(imximage_version);
> @@ -381,9 +380,9 @@ static void parse_cfg_cmd(struct imx_header *imxhdr, int32_t cmd, char *token,
> set_hdr_func(imxhdr);
> break;
> case CMD_BOOT_FROM:
> - imxhdr->flash_offset = get_table_entry_id(imximage_bootops,
> + g_flash_offset = get_table_entry_id(imximage_bootops,
> "imximage boot option", token);
> - if (imxhdr->flash_offset == -1) {
Why do we need a global when we have already a way to not use a global ?
> + if (g_flash_offset == -1) {
> fprintf(stderr, "Error: %s[%d] -Invalid boot device"
> "(%s)\n", name, lineno, token);
> exit(EXIT_FAILURE);
> @@ -521,12 +520,17 @@ static void imximage_print_header(const void *ptr)
> }
> }
>
> -static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd,
> - struct mkimage_params *params)
> +int imximage_vrec_header(struct mkimage_params *params,
> + struct image_type_params *tparams)
> {
> - struct imx_header *imxhdr = (struct imx_header *)ptr;
> + struct imx_header *imxhdr;
> uint32_t dcd_len;
>
> + imxhdr = calloc(1, MAX_HEADER_SIZE);
> + if (!imxhdr) {
> + fprintf(stderr, "Error: out of memory\n");
> + exit(EXIT_FAILURE);
> + }
> /*
> * In order to not change the old imx cfg file
> * by adding VERSION command into it, here need
> @@ -534,14 +538,31 @@ static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd,
> */
> imximage_version = IMXIMAGE_V1;
> /* Be able to detect if the cfg file has no BOOT_FROM tag */
> - imxhdr->flash_offset = FLASH_OFFSET_UNDEFINED;
> + g_flash_offset = FLASH_OFFSET_UNDEFINED;
> set_hdr_func(imxhdr);
>
> /* Parse dcd configuration file */
> dcd_len = parse_cfg_file(imxhdr, params->imagename);
>
> + /* Exit if there is no BOOT_FROM field specifying the flash_offset */
> + if (g_flash_offset == FLASH_OFFSET_UNDEFINED) {
> + fprintf(stderr, "Error: No BOOT_FROM tag in %s\n",
> + params->imagename);
> + exit(EXIT_FAILURE);
> + }
> /* Set the imx header */
> - (*set_imx_hdr)(imxhdr, dcd_len, sbuf, params);
> + imximage_params.header_size = (*set_imx_hdr)(imxhdr, dcd_len,
> + params->ep, g_flash_offset);
> + imximage_params.hdr = imxhdr;
> + return 0;
> +}
> +
> +static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd,
> + struct mkimage_params *params)
> +{
> + /* Set the size in header */
> + (*set_imx_size)((struct imx_header *)ptr, sbuf->st_size,
> + g_flash_offset);
> }
>
> int imximage_check_params(struct mkimage_params *params)
> @@ -571,8 +592,9 @@ int imximage_check_params(struct mkimage_params *params)
> */
> static struct image_type_params imximage_params = {
> .name = "Freescale i.MX 5x Boot Image support",
> - .header_size = sizeof(struct imx_header),
> - .hdr = (void *)&imximage_header,
> + .header_size = 0,
> + .hdr = NULL,
> + .vrec_header = imximage_vrec_header,
> .check_image_type = imximage_check_image_types,
> .verify_header = imximage_verify_header,
> .print_header = imximage_print_header,
> diff --git a/tools/imximage.h b/tools/imximage.h
> index 34f293d..5fe3a8a 100644
> --- a/tools/imximage.h
> +++ b/tools/imximage.h
> @@ -30,6 +30,7 @@
> #define DCD_BARKER 0xB17219E9
>
> #define HEADER_OFFSET 0x400
> +#define MAX_HEADER_SIZE (16 << 10)
>
> #define CMD_DATA_STR "DATA"
> #define FLASH_OFFSET_UNDEFINED 0xFFFFFFFF
> @@ -156,7 +157,6 @@ struct imx_header {
> imx_header_v1_t hdr_v1;
> imx_header_v2_t hdr_v2;
> } header;
> - uint32_t flash_offset;
> };
>
> typedef void (*set_dcd_val_t)(struct imx_header *imxhdr,
> @@ -168,9 +168,9 @@ typedef void (*set_dcd_rst_t)(struct imx_header *imxhdr,
> uint32_t dcd_len,
> char *name, int lineno);
>
> -typedef void (*set_imx_hdr_t)(struct imx_header *imxhdr,
> - uint32_t dcd_len,
> - struct stat *sbuf,
> - struct mkimage_params *params);
> +typedef int (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t dcd_len,
> + uint32_t entry_point, uint32_t flash_offset);
> +typedef void (*set_imx_size_t)(struct imx_header *imxhdr, uint32_t file_size,
> + uint32_t flash_offset);
I disagree here. mkimage is valid for all architecture, we must not have
special entries here for a SOC or SOC family. For all other SOCs, DCD,
iMX header have no sense.
Anyway, why do you need to add set_imx_size_t when you call it only in
imximage.c ?
>
> #endif /* _IMXIMAGE_H_ */
You should split changes in image.h, that are valid for all
architecture, from changes to imximage.c, that are only for i.MX, into
different patches.
In my understanding you add additional entry points to have a variable
header lenght, but this feature is already used on TI with the AIS
image. You use also vrec_header. What am I missing here ?
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 02/21] imximage: check dcd_len as entries added
2012-09-22 2:38 ` [U-Boot] [PATCH V2 02/21] imximage: check dcd_len as entries added Troy Kisky
@ 2012-09-23 11:05 ` Stefano Babic
2012-09-24 20:54 ` Troy Kisky
0 siblings, 1 reply; 430+ messages in thread
From: Stefano Babic @ 2012-09-23 11:05 UTC (permalink / raw)
To: u-boot
On 22/09/2012 04:38, Troy Kisky wrote:
> Before the len was checked after the entire file
> was processed, so it could have already overflowed.
>
Hi Troy,
> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
> ---
> tools/imximage.c | 26 +++++++++++---------------
> 1 file changed, 11 insertions(+), 15 deletions(-)
>
> diff --git a/tools/imximage.c b/tools/imximage.c
> index 25d3b74..0bfbec3 100644
> --- a/tools/imximage.c
> +++ b/tools/imximage.c
> @@ -71,6 +71,7 @@ static set_dcd_val_t set_dcd_val;
> static set_dcd_rst_t set_dcd_rst;
> static set_imx_hdr_t set_imx_hdr;
> static set_imx_size_t set_imx_size;
> +static uint32_t max_dcd_entries;
> static uint32_t g_flash_offset;
>
> static struct image_type_params imximage_params;
> @@ -173,13 +174,6 @@ static void set_dcd_rst_v1(struct imx_header *imxhdr, uint32_t dcd_len,
> {
> dcd_v1_t *dcd_v1 = &imxhdr->header.hdr_v1.dcd_table;
>
> - if (dcd_len > MAX_HW_CFG_SIZE_V1) {
> - fprintf(stderr, "Error: %s[%d] -"
> - "DCD table exceeds maximum size(%d)\n",
> - name, lineno, MAX_HW_CFG_SIZE_V1);
> - exit(EXIT_FAILURE);
> - }
> -
> dcd_v1->preamble.barker = DCD_BARKER;
> dcd_v1->preamble.length = dcd_len * sizeof(dcd_type_addr_data_t);
> }
> @@ -193,13 +187,6 @@ static void set_dcd_rst_v2(struct imx_header *imxhdr, uint32_t dcd_len,
> {
> dcd_v2_t *dcd_v2 = &imxhdr->header.hdr_v2.dcd_table;
>
> - if (dcd_len > MAX_HW_CFG_SIZE_V2) {
> - fprintf(stderr, "Error: %s[%d] -"
> - "DCD table exceeds maximum size(%d)\n",
> - name, lineno, MAX_HW_CFG_SIZE_V2);
> - exit(EXIT_FAILURE);
> - }
> -
> dcd_v2->header.tag = DCD_HEADER_TAG;
> dcd_v2->header.length = cpu_to_be16(
> dcd_len * sizeof(dcd_addr_data_t) + 8);
> @@ -293,12 +280,14 @@ static void set_hdr_func(struct imx_header *imxhdr)
> set_dcd_rst = set_dcd_rst_v1;
> set_imx_hdr = set_imx_hdr_v1;
> set_imx_size = set_imx_size_v1;
> + max_dcd_entries = MAX_HW_CFG_SIZE_V1;
> break;
> case IMXIMAGE_V2:
> set_dcd_val = set_dcd_val_v2;
> set_dcd_rst = set_dcd_rst_v2;
> set_imx_hdr = set_imx_hdr_v2;
> set_imx_size = set_imx_size_v2;
> + max_dcd_entries = MAX_HW_CFG_SIZE_V2;
> break;
> default:
> err_imximage_version(imximage_version);
> @@ -425,8 +414,15 @@ static void parse_cfg_fld(struct imx_header *imxhdr, int32_t *cmd,
> value = get_cfg_value(token, name, lineno);
> (*set_dcd_val)(imxhdr, name, lineno, fld, value, *dcd_len);
>
> - if (fld == CFG_REG_VALUE)
> + if (fld == CFG_REG_VALUE) {
> (*dcd_len)++;
> + if (*dcd_len > max_dcd_entries) {
> + fprintf(stderr, "Error: %s[%d] -"
> + "DCD table exceeds maximum size(%d)\n",
> + name, lineno, max_dcd_entries);
> + exit(EXIT_FAILURE);
> + }
> + }
> break;
> default:
> break;
>
This patch seems to me unrelated to the rest, and fixes the case when
too much DCD entries are put into the imximage.cfg file. What about to
rebase it on the current code and post it as separate patch ? I think
this can be merged directly, also in the current realease.
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 04/21] imximage: cleanup parsing
2012-09-22 2:39 ` [U-Boot] [PATCH V2 04/21] imximage: cleanup parsing Troy Kisky
@ 2012-09-23 11:08 ` Stefano Babic
2012-09-24 20:59 ` Troy Kisky
0 siblings, 1 reply; 430+ messages in thread
From: Stefano Babic @ 2012-09-23 11:08 UTC (permalink / raw)
To: u-boot
On 22/09/2012 04:39, Troy Kisky wrote:
> Move to pulling tokens instead of pushing them.
> Remove need for switch statements to process commands.
> Add error messages such as "command not finished",
> "extra data at end of line", and "invalid token"
> Add ';' as command separator.
>
> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
> ---
Hi Troy,
you add code in previous patch and you remove it in this one. This makes
quite difficult to review them.
Normally, we do do have this case, and code is not added and removed in
the same patches series. Should you not squash patches together and / or
rearrange them with different topic ?
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 05/21] imximage: add expression evaluation
2012-09-22 2:39 ` [U-Boot] [PATCH V2 05/21] imximage: add expression evaluation Troy Kisky
@ 2012-09-23 14:56 ` Stefano Babic
2012-09-24 21:18 ` Troy Kisky
0 siblings, 1 reply; 430+ messages in thread
From: Stefano Babic @ 2012-09-23 14:56 UTC (permalink / raw)
To: u-boot
On 22/09/2012 04:39, Troy Kisky wrote:
> Basic expressions with order precedence is
> now supported.
> ie. (----3 + ((1+2*3)/--2 + --5 *(8/4))) is 16.
>
> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
> ---
Hi Troy,
> tools/imximage.c | 172 ++++++++++++++++++++++++++++++++++++++++++++++++++----
> 1 file changed, 162 insertions(+), 10 deletions(-)
>
> diff --git a/tools/imximage.c b/tools/imximage.c
> index 1e120354..2c5a622 100644
I have some general considerations. First, if you plan to add support
for expression evaluation, this feature should be available generally
for mkimage, that means also other processors / architecture can profit
of it. It should be moved away from imximage.c code.
Then, you want also let that the preprocesso can parse the imximage
code. I can imagine that in such terms it could be then possible to
define in imximage.cfg something like:
#define DDR_VAL (1 <<17 | 3 << 7)
#define ADDRESS 0x0x53something
DATA 4 ADDRESS DDR_VAL
Else, why do we need the power of C preprocessor ?
If this is true, can you explain us which is the use case using the C
preprocessor and which is the one for the expression evaluator ? And why
do we need both ?
> --- a/tools/imximage.c
> +++ b/tools/imximage.c
> @@ -380,20 +380,172 @@ char *grab_token(char *dest, int size, char *src)
> return src;
> }
>
> +char precedence[] = {
> + /* ( + - * / & ^ | ) */
> + 0, 2, 2, 1, 1, 3, 4, 5, 6
> +};
> +char unary_operations[] = "(+-";
> +char binary_operations[] = " +-*/&^|)";
> +
> +uint32_t do_func(uint32_t val1, uint32_t val2, int op)
> +{
> + switch (op) {
> + case 1:
> + return val1 + val2;
> + case 2:
> + return val1 - val2;
> + case 3:
> + return val1 * val2;
> + case 4:
> + return val1 / val2;
> + case 5:
> + return val1 & val2;
> + case 6:
> + return val1 ^ val2;
> + case 7:
> + return val1 | val2;
> + }
> + fprintf(stderr, "Error: in func %s: val1=%d val2=%d op = %d\n",
> + __func__, val1, val2, op);
> + exit(EXIT_FAILURE);
> +}
> +
> +int find_op(char c, char *p)
> +{
> + int i;
> + for (i = 0; ; i++) {
> + if (c == p[i])
> + return i;
> + if (!p[i])
> + break;
> + }
> + return -1;
> +}
> +
> +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
> +
> static uint32_t get_cfg_value(struct data_src *ds, uint32_t *pval)
> {
> char *endptr;
> - uint32_t value;
> + int op_i = 0;
> + int val_i = 0;
> + unsigned char op[16];
> + uint32_t val[16];
> + int unary = 1;
> + char *p;
>
> - if (skip_separators(ds))
> - return -1;
> - errno = 0;
> - value = strtoul(ds->p, &endptr, 16);
> - if (errno || (ds->p == endptr))
> - return -1;
> - *pval = value;
> - ds->p = endptr;
> - return 0;
> + p = ds->p;
> + for (;;) {
> + char c;
> + int i, j;
> + char *ops = unary ? unary_operations : binary_operations;
> +
> + if (unary) {
> + ds->p = p;
> + if (skip_separators(ds))
> + return -1;
> + p = ds->p;
> + c = *p;
> + } else {
> + for (;;) {
> + c = *p;
> + if ((c != ' ') && (c != '\t'))
> + break;
> + p++;
> + }
> + }
> + i = find_op(c, ops);
> + debug("%d,%c,%d:%s\n", i, c, unary, p);
> + if ((i < 0) && unary) {
> + if (val_i >= ARRAY_SIZE(val))
> + return -1;
> + errno = 0;
> + val[val_i++] = strtoul(p, &endptr, 16);
> + if (errno || (p == endptr)) {
> + ds->p = p;
> + return -1;
> + }
> + p = endptr;
> + unary = 0;
> + debug("val[%d]=%x,%d,%d\n", val_i - 1, val[val_i - 1],
> + op_i, val_i);
> +do_unary:
> + while (op_i) {
> + j = op[op_i - 1];
> + if (!(j & 0x80))
> + break;
> + op_i--;
> + val[val_i - 1] = do_func(0,
> + val[val_i - 1], j & 0x7f);
> + debug("un:%d,%x,%d,%d\n", val[val_i - 1], j,
> + op_i, val_i);
> + }
> + continue;
> + }
> + if (i < 0) {
> + c = 0;
> + i = 8;
> + } else {
> + p++;
> + }
> + if (c == '(') {
> + if (op_i >= ARRAY_SIZE(op))
> + return -1;
> + op[op_i++] = i;
> + debug("op[%d]=%x,%d,%d\n", op_i - 1, op[op_i - 1],
> + op_i, val_i);
> + unary = 1;
> + continue;
> + }
> + for (;;) {
> + if (!op_i || unary)
> + break;
> + j = op[op_i - 1];
> + if (j == 0) {
> + if (c == ')') {
> + op_i--;
> + goto do_unary;
> + }
> + break;
> + }
> + if ((j & 0x80)) {
> + op_i--;
> + val[val_i - 1] = do_func(0,
> + val[val_i - 1], j & 0x7f);
> + debug("unary:%d,%x\n", val[val_i - 1], j);
> + continue;
> + }
> + if (precedence[i] < precedence[j])
> + break;
> + if (val_i < 2)
> + return -1;
> + op_i--;
> + val[val_i - 2] = do_func(val[val_i - 2],
> + val[val_i - 1], j);
> + val_i--;
> + debug("binary:%d,%x,%d,%d\n", val[val_i - 1], j,
> + op_i, val_i);
> + }
> + if (c == ')') {
> + fprintf(stderr, "Error: unmatched parenthesis\n");
> + return -1;
> + }
> + if (i == 8) {
> + if ((op_i != 0) || (val_i != 1)) {
> + fprintf(stderr, "Error: syntax %d %d\n",
> + op_i, val_i);
> + return -1;
> + }
> + ds->p = p;
> + *pval = val[0];
> + return 0;
> + }
> + if (op_i >= ARRAY_SIZE(op))
> + return -1;
> + op[op_i++] = i | (unary << 7);
> + debug("op[%d]=%x,%d,%d\n", op_i - 1, op[op_i - 1], op_i, val_i);
> + unary = 1;
> + }
> }
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 17/21] mx6: soc: add get_cpu_type
2012-09-22 17:07 ` Troy Kisky
@ 2012-09-23 14:59 ` Stefano Babic
0 siblings, 0 replies; 430+ messages in thread
From: Stefano Babic @ 2012-09-23 14:59 UTC (permalink / raw)
To: u-boot
On 22/09/2012 19:07, Troy Kisky wrote:
> On 9/21/2012 7:50 PM, Fabio Estevam wrote:
>> Hi Troy,
>>
>> On Fri, Sep 21, 2012 at 11:39 PM, Troy Kisky
>> <troy.kisky@boundarydevices.com> wrote:
>>> Add function to return the processor type.
>>>
>>> i.e. MX6Q, MX6DL, MX6SOLO, MX6SOLOLITE
>> On arch/arm/imx-common/cpu.c we have:
>>
>> static const char *get_imx_type(u32 imxtype)
>> {
>> switch (imxtype) {
>> case 0x63:
>> return "6Q"; /* Quad-core version of the mx6 */
>> case 0x61:
>> return "6DS"; /* Dual/Solo version of the mx6 */
>> case 0x60:
>> return "6SL"; /* Solo-Lite version of the mx6 */
>> case 0x51:
>> return "51";
>> case 0x53:
>> return "53";
>> default:
>> return "??";
>> }
>> }
>>
>> ,which seems to serve the same purpose.
>>
>> Regards,
>>
>> Fabio Estevam
>>
>
> No, not similar to get_imx_type, but it is similar to get_cpu_rev.
>
> I guess I should fix get_imx_type, and get_cpu_rev, instead of
> adding a new one.
>
Indeed. Try to use as much as possible code in imx-common, avoiding to
duplicate code.
Best regards,
Stefano
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 06/21] imximage: add plugin commands
2012-09-22 2:39 ` [U-Boot] [PATCH V2 06/21] imximage: add plugin commands Troy Kisky
@ 2012-09-23 15:38 ` Stefano Babic
2012-09-24 21:46 ` Troy Kisky
0 siblings, 1 reply; 430+ messages in thread
From: Stefano Babic @ 2012-09-23 15:38 UTC (permalink / raw)
To: u-boot
On 22/09/2012 04:39, Troy Kisky wrote:
> Add commands
> plugin address filename
> iomux_entry addr, data1 [, data2, [, data3]]
> write_entry addr, data1 [, data2, [, data3]]
Why do we need explicitely an IOMUX command ? As far as I can see, the
program image defined in V2 defines a plugin, but not an iomux.
I am expecting that the imximage generates a iMX header only, without
moving some code from the initialization code directly here. In the
manula there is a "Write Data" (what we have always had), a "Check data"
and an "Unlock" commands.
If we start to add special commands, maybe we are staring again to
reimplement U-Boot. We could have some SET_CLK, SET_CPU_FREQ, and so on.
What I am really mising in this series is why you are moving a lot of
things from U-Boot into the iMX header.
It seems to me we want to put much more code in the iMX header as what
it is really required to boot the device.
Adding / modifying the syntax requires to update doc/README.imximage, too.
>
> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
> ---
> tools/imximage.c | 334 ++++++++++++++++++++++++++++++++++++++++++++----------
> tools/imximage.h | 11 +-
> 2 files changed, 283 insertions(+), 62 deletions(-)
>
> diff --git a/tools/imximage.c b/tools/imximage.c
> index 2c5a622..fae786a 100644
> --- a/tools/imximage.c
> +++ b/tools/imximage.c
> @@ -31,7 +31,6 @@
> #include "mkimage.h"
> #include <image.h>
> #include "imximage.h"
> -
> /*
> * Supported commands for configuration file
> */
> @@ -39,6 +38,9 @@ static table_entry_t imximage_cmds[] = {
> {CMD_BOOT_FROM, "BOOT_FROM", "boot command", },
> {CMD_DATA, "DATA", "Reg Write Data", },
> {CMD_IMAGE_VERSION, "IMAGE_VERSION", "image version", },
> + {CMD_PLUGIN, "plugin", "plugin addr,file", },
> + {CMD_IOMUX_ENTRY, "iomux_entry", "Write iomux reg", },
> + {CMD_WRITE_ENTRY, "write_entry", "Write register", },
> {-1, "", "", },
> };
>
> @@ -69,8 +71,8 @@ static uint32_t imximage_version;
>
> static set_dcd_val_t set_dcd_val;
> static set_imx_hdr_t set_imx_hdr;
> -static set_imx_size_t set_imx_size;
> static uint32_t *p_max_dcd;
> +static uint32_t *header_size_ptr;
> static uint32_t g_flash_offset;
>
> static struct image_type_params imximage_params;
> @@ -88,8 +90,7 @@ static uint32_t detect_imximage_version(struct imx_header *imx_hdr)
> return IMXIMAGE_V1;
>
> /* Try to detect V2 */
> - if ((fhdr_v2->header.tag == IVT_HEADER_TAG) &&
> - (hdr_v2->dcd_table.header.tag == DCD_HEADER_TAG))
> + if ((fhdr_v2->header.tag == IVT_HEADER_TAG))
> return IMXIMAGE_V2;
Help me to understand. I am reading i.MX6 manual and, even if the number
of DCD entries could be variable, I do not see why the header tag of DCD
is moving. At least, this is what I can see on picture 7-19, Image
Vector table.
>
> return IMXIMAGE_VER_INVALID;
> @@ -160,7 +161,7 @@ static int set_dcd_val_v2(struct imx_header *imxhdr, uint32_t *data)
> }
>
> static int set_imx_hdr_v1(struct imx_header *imxhdr,
> - uint32_t entry_point, uint32_t flash_offset)
> + uint32_t entry_point, uint32_t flash_offset, int plugin)
> {
> imx_header_v1_t *hdr_v1 = &imxhdr->header.hdr_v1;
> flash_header_v1_t *fhdr_v1 = &hdr_v1->fhdr;
> @@ -180,22 +181,12 @@ static int set_imx_hdr_v1(struct imx_header *imxhdr,
> /* Security feature are not supported */
> fhdr_v1->app_code_csf = 0;
> fhdr_v1->super_root_key = 0;
> + header_size_ptr = (uint32_t *)(((char *)imxhdr) + header_length - 4);
> return header_length;
> }
>
> -static void set_imx_size_v1(struct imx_header *imxhdr, uint32_t file_size,
> - uint32_t flash_offset)
> -{
> - uint32_t *p = (uint32_t *)(((char *)imxhdr)
> - + imximage_params.header_size);
> -
> - /* The external flash header must be at the end of the DCD table */
> - /* file_size includes header */
> - p[-1] = file_size + flash_offset;
> -}
I think you have to squash some of your patches or to defines them in
another way. You added this code previously, and you drop now. This
makes more difficult to review your patches.
> -
> static int set_imx_hdr_v2(struct imx_header *imxhdr,
> - uint32_t entry_point, uint32_t flash_offset)
> + uint32_t entry_point, uint32_t flash_offset, int plugin)
> {
> imx_header_v2_t *hdr_v2 = &imxhdr->header.hdr_v2;
> flash_header_v2_t *fhdr_v2 = &hdr_v2->fhdr;
> @@ -216,27 +207,20 @@ static int set_imx_hdr_v2(struct imx_header *imxhdr,
> fhdr_v2->boot_data_ptr = hdr_base
> + offsetof(imx_header_v2_t, boot_data);
> hdr_v2->boot_data.start = hdr_base - flash_offset;
> + hdr_v2->boot_data.plugin = plugin;
>
> /* Security feature are not supported */
> fhdr_v2->csf = 0;
> + header_size_ptr = &hdr_v2->boot_data.size;
> return header_length;
> }
>
> -static void set_imx_size_v2(struct imx_header *imxhdr, uint32_t file_size,
> - uint32_t flash_offset)
> -{
> - imx_header_v2_t *hdr_v2 = &imxhdr->header.hdr_v2;
> - /* file_size includes header */
> - hdr_v2->boot_data.size = file_size + flash_offset;
> -}
> -
> static void set_hdr_func(struct imx_header *imxhdr)
> {
> switch (imximage_version) {
> case IMXIMAGE_V1:
> set_dcd_val = set_dcd_val_v1;
> set_imx_hdr = set_imx_hdr_v1;
> - set_imx_size = set_imx_size_v1;
> p_entry = &imxhdr->header.hdr_v1.dcd_table.addr_data[0].type;
> p_max_dcd = &imxhdr->header.hdr_v1.dcd_table
> .addr_data[MAX_HW_CFG_SIZE_V1].type;
> @@ -245,7 +229,6 @@ static void set_hdr_func(struct imx_header *imxhdr)
> case IMXIMAGE_V2:
> set_dcd_val = set_dcd_val_v2;
> set_imx_hdr = set_imx_hdr_v2;
> - set_imx_size = set_imx_size_v2;
> p_entry = (uint32_t *)&imxhdr->header.hdr_v2.dcd_table;
> p_max_dcd = (uint32_t *)((char *)imxhdr + MAX_HEADER_SIZE);
> break;
> @@ -283,31 +266,49 @@ static void print_hdr_v1(struct imx_header *imx_hdr)
> printf("Entry Point: %08x\n", (uint32_t)fhdr_v1->app_code_jump_vector);
> }
>
> -static void print_hdr_v2(struct imx_header *imx_hdr)
> +static void print_header_info2(struct imx_header *imx_hdr)
> {
> imx_header_v2_t *hdr_v2 = &imx_hdr->header.hdr_v2;
> flash_header_v2_t *fhdr_v2 = &hdr_v2->fhdr;
> +
> + printf("Data Size: ");
> + genimg_print_size(hdr_v2->boot_data.size);
> + printf("Load Address: %08x\n", (uint32_t)fhdr_v2->boot_data_ptr);
> + printf("Entry Point: %08x\n", (uint32_t)fhdr_v2->entry);
> +}
> +
> +static void print_hdr_v2(struct imx_header *imxhdr)
> +{
> + imx_header_v2_t *hdr_v2 = &imxhdr->header.hdr_v2;
> dcd_v2_t *dcd_v2 = &hdr_v2->dcd_table;
> uint32_t size, version;
>
> - size = be16_to_cpu(dcd_v2->header.length) - 8;
> - if (size > (MAX_HW_CFG_SIZE_V2 * sizeof(dcd_addr_data_t))) {
> - fprintf(stderr,
> - "Error: Image corrupt DCD size %d exceed maximum %d\n",
> - (uint32_t)(size / sizeof(dcd_addr_data_t)),
> - MAX_HW_CFG_SIZE_V2);
> - exit(EXIT_FAILURE);
> + if (hdr_v2->fhdr.dcd_ptr) {
> + size = be16_to_cpu(dcd_v2->header.length) - 8;
> + if (size > (MAX_HW_CFG_SIZE_V2 * sizeof(dcd_addr_data_t))) {
> + fprintf(stderr, "Error: Image corrupt DCD size "
> + "%d exceed maximum %d\n",
> + (uint32_t)(size / sizeof(dcd_addr_data_t)),
> + MAX_HW_CFG_SIZE_V2);
> + exit(EXIT_FAILURE);
> + }
> }
> -
> - version = detect_imximage_version(imx_hdr);
> + version = detect_imximage_version(imxhdr);
>
> printf("Image Type: Freescale IMX Boot Image\n");
> printf("Image Ver: %x", version);
> printf("%s\n", get_table_entry_name(imximage_versions, NULL, version));
> - printf("Data Size: ");
> - genimg_print_size(hdr_v2->boot_data.size);
> - printf("Load Address: %08x\n", (uint32_t)fhdr_v2->boot_data_ptr);
> - printf("Entry Point: %08x\n", (uint32_t)fhdr_v2->entry);
> + print_header_info2(imxhdr);
> + if (hdr_v2->boot_data.plugin) {
> + uint32_t flash_offset =
> + hdr_v2->fhdr.self - hdr_v2->boot_data.start;
> + /* The 1st size includes flash offset and the next header */
> + uint32_t plugin_length = hdr_v2->boot_data.size - flash_offset
> + - offsetof(imx_header_v2_t, dcd_table);
> +
> + imxhdr = (struct imx_header *)((char *)imxhdr + plugin_length);
> + print_header_info2(imxhdr);
> + }
> }
>
> static int cmd_cnt;
> @@ -363,6 +364,24 @@ int skip_separators(struct data_src *ds)
> }
> }
>
> +int skip_comma(struct data_src *ds)
> +{
> + char *p = ds->p;
> +
> + for (;;) {
> + char c = *p++;
> + if ((c == '#') || (c == '\r') || (c == '\n') || !c)
> + return 0;
> + if (c == ',') {
> + ds->p = p;
> + skip_separators(ds);
> + return 1;
> + }
> + if ((c != ' ') && (c == '\t'))
> + return 0;
> + }
> +}
> +
> char *grab_token(char *dest, int size, char *src)
> {
> while (size) {
> @@ -551,16 +570,18 @@ do_unary:
> static int parse_cmd_data(struct data_src *ds)
> {
> uint32_t data[3];
> - int ret = get_cfg_value(ds, &data[0]);
> + int ret, i;
>
> - if (ret)
> - return ret;
> - ret = get_cfg_value(ds, &data[1]);
> - if (ret)
> - return ret;
> - ret = get_cfg_value(ds, &data[2]);
> - if (ret)
> - return ret;
> + if (ds->plugin) {
> + fprintf(stderr, "DATA should be before plug command\n");
> + return -1;
> + }
> + for (i = 0; i < 3; i++) {
> + int ret = get_cfg_value(ds, &data[i]);
> + if (ret)
> + return ret;
> + skip_comma(ds); /* comma is optional */
> + }
> ret = (*set_dcd_val)(ds->imxhdr, data);
> if (ret)
> return ret;
> @@ -573,6 +594,99 @@ static int parse_cmd_data(struct data_src *ds)
> return 0;
> }
>
> +static int get_data(struct data_src *ds, uint32_t *data, int cnt)
> +{
> + int i = 0;
> +
> + if (!ds->plugin) {
> + fprintf(stderr, "missing plug command\n");
> + return -1;
> + }
> + for (;;) {
> + int ret = get_cfg_value(ds, &data[i++]);
> + if (ret)
> + return ret;
> + if (i >= cnt)
> + break;
> + if (!skip_comma(ds))
> + break;
> + }
> + if (i < 2) {
> + fprintf(stderr, "missing ','\n");
> + return -1;
> + }
> + while (i < cnt) {
> + data[i] = data[i - 1];
> + i++;
> + }
> + if ((data[1] == ds->prev[1]) && (data[2] == ds->prev[2])
> + && (data[3] == ds->prev[3])
> + && (data[4] == ds->prev[4]))
> + i = 0;
> + else if ((data[1] == data[2]) && (data[2] == data[3])
> + && (data[3] == data[4]))
> + i = 1;
> + else if ((data[2] == data[3]) && (data[3] == data[4]))
> + i = 2;
> + else
> + i = 3;
> + return i;
> +}
> +
> +static int store_data(struct data_src *ds, uint32_t *data, int cnt)
> +{
> + int i;
> +
> + for (i = 0; i < cnt; i++)
> + *p_entry++ = data[i];
> +
> + ds->prev[1] = data[1];
> + ds->prev[2] = data[2];
> + ds->prev[3] = data[3];
> + ds->prev[4] = data[4];
> + if (p_entry > p_max_dcd) {
> + uint32_t size = (char *)p_max_dcd - (char *)ds->imxhdr;
> + fprintf(stderr, "Error: header exceeds maximum size(%d)\n",
> + size);
> + return -1;
> + }
> + return 0;
> +}
> +
> +static int parse_iomux_entry(struct data_src *ds)
> +{
> + uint32_t data[5];
> + int i;
> +
> + i = get_data(ds, data, 5);
> + if (i < 0)
> + return i;
> + if (data[0] & (3 << 30)) {
> + fprintf(stderr, "bad 1st value\n");
> + return -1;
> + }
> + if (i < 3)
> + i++;
> + data[0] |= (i << 30);
> + return store_data(ds, data, (i == 3) ? 5 : i);
> +}
> +
> +static int parse_write_entry(struct data_src *ds)
> +{
> + uint32_t data[5];
> + int i;
> +
> + i = get_data(ds, data, 5);
> + if (i < 0)
> + return i;
> + if (data[0] & 3) {
> + fprintf(stderr, "Address must be aligned on word boundary\n");
> + return -1;
> + }
> + data[0] |= i;
> + return store_data(ds, data, (i == 3) ? 5 : (i + 1));
> +}
> +
> static int parse_image_version(struct data_src *ds)
> {
> int ret;
> @@ -618,8 +732,82 @@ static int parse_boot_from(struct data_src *ds)
> return 0;
> }
>
> +static int parse_plugin(struct data_src *ds)
> +{
> + struct stat sbuf;
> + int plug_file;
> + unsigned char *ptr;
> + char *p;
> + char c;
> + int ret;
> + uint32_t plug_base;
> + uint32_t header_length;
> +
> + if (g_flash_offset == FLASH_OFFSET_UNDEFINED) {
> + fprintf(stderr, "Error: Place BOOT_FROM before plugin\n");
> + return -1;
> + }
> + ret = get_cfg_value(ds, &plug_base);
> + if (ret)
> + return ret;
> +
> + if (skip_separators(ds))
> + return -1;
> + p = ds->p;
> + for (;;) {
> + c = *p;
> + if (!c)
> + break;
> + if ((c == ' ') || (c == '\t') || (c == ';') || (c == '#')
> + || (c == '\r') || (c == '\n')) {
> + *p = 0;
> + break;
> + }
> + p++;
> + }
> + plug_file = open(ds->p, O_RDONLY|O_BINARY);
> + if (plug_file < 0) {
> + fprintf(stderr, "Can't open plugin file %s: %s\n",
> + ds->p, strerror(errno));
> + *p = c;
> + return -1;
> + }
> + if (fstat(plug_file, &sbuf) < 0) {
> + fprintf(stderr, "Can't stat %s: %s\n",
> + ds->p, strerror(errno));
> + close(plug_file);
> + return -1;
> + }
> + ptr = mmap(0, sbuf.st_size, PROT_READ, MAP_SHARED, plug_file, 0);
> + if (ptr == MAP_FAILED) {
> + fprintf(stderr, "Can't read %s: %s\n",
> + ds->p, strerror(errno));
> + return -1;
> + }
> + *p = c;
> + ds->p = p;
> + /* Set the plugin header */
> + header_length = (*set_imx_hdr)(ds->imxhdr, plug_base,
> + g_flash_offset, 1);
> +
> + p = ((char *)ds->imxhdr) + header_length;
> + if ((p + sbuf.st_size) >= (char *)p_max_dcd) {
> + fprintf(stderr, "Out of space\n");
> + return -1;
> + }
> +
> + ds->plugin = 1;
> + memcpy(p, ptr, sbuf.st_size);
> + munmap((void *)ptr, sbuf.st_size);
> + close(plug_file);
> +
> + p_entry = (uint32_t *)(p + sbuf.st_size);
> + return 0;
> +}
> +
> parse_fld_t cmd_table[] = {
> - parse_image_version, parse_boot_from, parse_cmd_data
> + parse_image_version, parse_boot_from, parse_cmd_data, parse_plugin,
> + parse_iomux_entry, parse_write_entry
> };
>
> static int parse_command(struct data_src *ds)
> @@ -630,9 +818,11 @@ static int parse_command(struct data_src *ds)
> return cmd_table[cmd](ds);
> }
>
> -static void parse_cfg_file(struct imx_header *imxhdr, char *name)
> +static void parse_cfg_file(struct imx_header *imxhdr, char *name,
> + uint32_t entry_point)
> {
> struct data_src ds;
> + uint32_t plugin_length = 0;
>
> ds.line = NULL;
> ds.len = 0;
> @@ -662,6 +852,35 @@ static void parse_cfg_file(struct imx_header *imxhdr, char *name)
> cmd_cnt++;
> }
> fclose(ds.fd);
> +
> + if (ds.plugin) {
> + uint32_t header_length, more;
> + struct imx_header *next_imxhdr;
> +
> + *p_entry++ = 0;
> + header_length = ((char *)p_entry) - ((char *)imxhdr);
> + plugin_length = ((header_length - 1) | 0x3f) + 1;
> + more = plugin_length - header_length;
> + if (more)
> + memset(p_entry, 0, more);
> + next_imxhdr = (struct imx_header *)
> + (((char *)imxhdr) + plugin_length);
> + p_entry = (imximage_version == IMXIMAGE_V1) ? (uint32_t *)
> + &next_imxhdr->header.hdr_v1.dcd_table.addr_data[0].type
> + : (uint32_t *)&next_imxhdr->header.hdr_v2.dcd_table;
> + if (p_entry > p_max_dcd) {
> + fprintf(stderr, "Out of space\n");
> + exit(EXIT_FAILURE);
> + }
> +
> + /* Set the plugin size in header to include next header */
> + *header_size_ptr = ((char *)p_entry) - ((char *)imxhdr)
> + + g_flash_offset;
> + imxhdr = next_imxhdr;
> + }
> + /* Set the imx header */
> + imximage_params.header_size = (*set_imx_hdr)(imxhdr, entry_point,
> + g_flash_offset + plugin_length, 0) + plugin_length;
> return;
> }
>
> @@ -727,7 +946,7 @@ int imximage_vrec_header(struct mkimage_params *params,
> set_hdr_func(imxhdr);
>
> /* Parse dcd configuration file */
> - parse_cfg_file(imxhdr, params->imagename);
> + parse_cfg_file(imxhdr, params->imagename, params->ep);
>
> /* Exit if there is no BOOT_FROM field specifying the flash_offset */
> if (g_flash_offset == FLASH_OFFSET_UNDEFINED) {
> @@ -735,9 +954,6 @@ int imximage_vrec_header(struct mkimage_params *params,
> params->imagename);
> exit(EXIT_FAILURE);
> }
> - /* Set the imx header */
---> - imximage_params.header_size = (*set_imx_hdr)(imxhdr, params->ep,
> - g_flash_offset);
> imximage_params.hdr = imxhdr;
> return 0;
> }
> @@ -746,8 +962,10 @@ static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd,
> struct mkimage_params *params)
> {
> /* Set the size in header */
> - (*set_imx_size)((struct imx_header *)ptr, sbuf->st_size,
> - g_flash_offset);
> + uint32_t offset = (char *)header_size_ptr - (char *)imximage_params.hdr;
> + uint32_t *p = (uint32_t *)((char *)ptr + offset);
> +
> + *p = sbuf->st_size + g_flash_offset;
> }
>
> int imximage_check_params(struct mkimage_params *params)
> diff --git a/tools/imximage.h b/tools/imximage.h
> index efd249b..7613386 100644
> --- a/tools/imximage.h
> +++ b/tools/imximage.h
> @@ -51,7 +51,10 @@
> enum imximage_cmd {
> CMD_IMAGE_VERSION,
> CMD_BOOT_FROM,
> - CMD_DATA
> + CMD_DATA,
> + CMD_PLUGIN,
> + CMD_IOMUX_ENTRY,
> + CMD_WRITE_ENTRY,
> };
>
> enum imximage_version {
> @@ -158,6 +161,8 @@ struct data_src {
> char *filename;
> struct imx_header *imxhdr;
> char *p;
> + int plugin;
> + uint32_t prev[5];
> };
>
> typedef int (*parse_fld_t)(struct data_src *ds);
> @@ -165,8 +170,6 @@ typedef int (*parse_fld_t)(struct data_src *ds);
> typedef int (*set_dcd_val_t)(struct imx_header *imxhdr, uint32_t *data);
>
> typedef int (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t entry_point,
> - uint32_t flash_offset);
> -typedef void (*set_imx_size_t)(struct imx_header *imxhdr, uint32_t file_size,
> - uint32_t flash_offset);
> + uint32_t flash_offset, int plugin);
>
> #endif /* _IMXIMAGE_H_ */
>
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 08/21] mx6: add plugin file for use with imximage.cfg
2012-09-23 10:17 ` Stefano Babic
@ 2012-09-23 16:23 ` Eric Nelson
2012-09-23 17:08 ` Stefano Babic
2012-09-24 20:46 ` Troy Kisky
1 sibling, 1 reply; 430+ messages in thread
From: Eric Nelson @ 2012-09-23 16:23 UTC (permalink / raw)
To: u-boot
On 09/23/2012 03:17 AM, Stefano Babic wrote:
> On 22/09/2012 04:39, Troy Kisky wrote:
>> The "plugin" command of mkimage can take this
>> file as an argument.
>>
>> Signed-off-by: Troy Kisky<troy.kisky@boundarydevices.com>
>> ---
>
> Hi Troy,
>
> I agree with Vikram that a better explanation of what a plugin is can
> help to understand without reading deeply into the i.MX6 manual.
>
> So a "plugin" is a chunk of code that can be called directly by the
> BootROM of i.MX processors supporting V2 version of the i.MX header.
> In my understanding, this is supported by i.MX53, too. After the plugin
> run, the control is returned to the BootROM.
>
Hi Stefano,
It seems that there's some general confusion on the list, so I think
a little more background and commentary is in order.
The primary rationale for plugins is to allow separate link maps in
a single image loaded by the BootROM.
The idea is to allow first-level code to initialize resources (usually
DDR) while running in internal RAM, then return to the boot rom for
further image loading (typically into DDR). This prevents the need
for the first-level code to support all boot sources (SPI-NOR,
NAND, SD card, etc) and allows it to focus on machine setup.
The feature is normally needed to allow the first level to access
a PMIC. I'm surprised that the 51evk and 53Loco boards aren't
using it.
Troy's rationale for using it now is to enable a single image on
i.MX6Quad, Dual lite and Solo processors, which have very slight
initialization differences. The 6Solo processor has 32-bit DDR
bus, so it would otherwise require a separate binary.
By doing this in code (plugin), we can introduce a conditional
based on processor type and have a single image that will boot
on any of the three.
The other key change for these processors is the location of
the iomux controller (moved on 6Solo/Duallite from 6Quad).
6Solo has 32-bit DDR and iomux controller moved from 6Q
6Duallite has 64-bit DDR but same iomux location as 6Q
Note that this highlights a slight down side to the plugin approach.
Because of the movement of the iomux controller, we can't use
a universal i.MX6 image header to write any IOMUX registers
through imximage.cfg.
Regards,
Eric
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 08/21] mx6: add plugin file for use with imximage.cfg
2012-09-23 16:23 ` Eric Nelson
@ 2012-09-23 17:08 ` Stefano Babic
2012-09-23 23:29 ` Eric Nelson
2012-09-24 22:23 ` Troy Kisky
0 siblings, 2 replies; 430+ messages in thread
From: Stefano Babic @ 2012-09-23 17:08 UTC (permalink / raw)
To: u-boot
On 23/09/2012 18:23, Eric Nelson wrote:
> On 09/23/2012 03:17 AM, Stefano Babic wrote:
>> On 22/09/2012 04:39, Troy Kisky wrote:
>>> The "plugin" command of mkimage can take this
>>> file as an argument.
>>>
>>> Signed-off-by: Troy Kisky<troy.kisky@boundarydevices.com>
>>> ---
>>
>> Hi Troy,
>>
>> I agree with Vikram that a better explanation of what a plugin is can
>> help to understand without reading deeply into the i.MX6 manual.
>>
>> So a "plugin" is a chunk of code that can be called directly by the
>> BootROM of i.MX processors supporting V2 version of the i.MX header.
>> In my understanding, this is supported by i.MX53, too. After the plugin
>> run, the control is returned to the BootROM.
>>
> Hi Stefano,
>
> It seems that there's some general confusion on the list, so I think
> a little more background and commentary is in order.
Well, it is - thanks for explanation.
>
> The primary rationale for plugins is to allow separate link maps in
> a single image loaded by the BootROM.
>
> The idea is to allow first-level code to initialize resources (usually
> DDR) while running in internal RAM, then return to the boot rom for
> further image loading (typically into DDR). This prevents the need
> for the first-level code to support all boot sources (SPI-NOR,
> NAND, SD card, etc) and allows it to focus on machine setup.
>
> The feature is normally needed to allow the first level to access
> a PMIC. I'm surprised that the 51evk and 53Loco boards aren't
> using it.
The mx51 uses a V1 header and the plugin feature is not supported at
all. So, it can't, simply. The mx53 can, but it is not needed.
Both boards boot without plugin. So it seem we have a misunderstanding,
and thanks to raise this issue ;-)
The setup is done by the SOC interpreting the DCD data into the iMX
header. After this setup, that in any case cannot be very long, the
control is still taken by the bootROM, that copies data from the media
device to the DDR according to the values set into the iMX header. Still
without plugin. After the copy, the bootROM gives the control to U-Boot
for the rest that starts with the usual initialization.
There is no need to setup the pMIC on mx51evk and mx53qsb to get the DDR
running. However, even if we need it, we can do it in another way, as I
will explain now.
>
> Troy's rationale for using it now is to enable a single image on
> i.MX6Quad, Dual lite and Solo processors, which have very slight
> initialization differences. The 6Solo processor has 32-bit DDR
> bus, so it would otherwise require a separate binary.
>
> By doing this in code (plugin), we can introduce a conditional
> based on processor type and have a single image that will boot
> on any of the three.
Ok - but why cannot this check be done directly by U-Boot ?
My understanding is that you want to add a plugin written in assembly to
allow different setup of the DDR controller. Let's see how we can do
with standard U-Boot code.
Core of the startup is that the SOC copies itself some code into the
internal RAM and started. This is done by bootROM, running is own code
and running the plugin.
We have already this mechanism with the SPL framework. The big advantage
for this approach is that the same mechanism can be used on SOC of
different vendors, while the one in this series is a solution strictly
bound with (some) Freescale's SOC.
The imx header can be still adapted to copy the SPL code into the
internal RAM. When SPL is running, you have all freedom to check which
is the CPU running and to adjust your DDR setting, and everything is C
code. Both MX5 and MX6 have plenty of internal RAM to do this, because
SPL requires ~30KB.
I think the goal to have the same U-Boot binary can be reached using the
SPL framework. As you are running U-Boot code, you have the possibility
to do whatever you want.
So my question is: if the main reason is to have a single image for all
your iMX6 boards, why cannot we do it in a standard way using SPL ?
>
> The other key change for these processors is the location of
> the iomux controller (moved on 6Solo/Duallite from 6Quad).
>
> 6Solo has 32-bit DDR and iomux controller moved from 6Q
> 6Duallite has 64-bit DDR but same iomux location as 6Q
>
> Note that this highlights a slight down side to the plugin approach.
>
> Because of the movement of the iomux controller, we can't use
> a universal i.MX6 image header to write any IOMUX registers
> through imximage.cfg.
However, you can do it with this approach:
- you have a general imx header, that does not write into IOMUX
It is your choice if this should set the DDR or not. You could also
decide to have an empty DCD table.
- your imx Header is generated for your SPL code, and the destination
address for the SPL code is put into internal RAM
- the bootROM will start reading the iMX header and DCD data and copies
data from media (NAND, SPI, ..) into iRAM. There is no need for any
special setup because the iRAM is always available. Then it gives the
control to the SPL.
- the SPL starts and performs the setup of the DDR, checking the SOC if
it is required. The usual SOC initialization is done here.
- At the end, the SPL loads from media the U-Boot or directly the kernel
and starts it. Or whatever image you want.
The further advantage we can have with this approach is that we can
profit for further development in u-boot. What I mean really is using
TPL, that means putting u-boot into a UBL volume, see:
http://lists.celinuxforum.org/pipermail/celinux-dev/2012-April/000543.html
I know there is not yet activity on this topic, but it does not mean we
have not in future.
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 08/21] mx6: add plugin file for use with imximage.cfg
2012-09-23 17:08 ` Stefano Babic
@ 2012-09-23 23:29 ` Eric Nelson
2012-09-24 7:22 ` Stefano Babic
2012-09-24 22:23 ` Troy Kisky
1 sibling, 1 reply; 430+ messages in thread
From: Eric Nelson @ 2012-09-23 23:29 UTC (permalink / raw)
To: u-boot
On 09/23/2012 10:08 AM, Stefano Babic wrote:
> On 23/09/2012 18:23, Eric Nelson wrote:
>> On 09/23/2012 03:17 AM, Stefano Babic wrote:
>>> On 22/09/2012 04:39, Troy Kisky wrote:
>>>> The "plugin" command of mkimage can take this
>>>> file as an argument.
>>>>
>>>> Signed-off-by: Troy Kisky<troy.kisky@boundarydevices.com>
>>>> ---
>>>
>>> Hi Troy,
>>>
>>> I agree with Vikram that a better explanation of what a plugin is can
>>> help to understand without reading deeply into the i.MX6 manual.
>>>
>>> So a "plugin" is a chunk of code that can be called directly by the
>>> BootROM of i.MX processors supporting V2 version of the i.MX header.
>>> In my understanding, this is supported by i.MX53, too. After the plugin
>>> run, the control is returned to the BootROM.
>>>
>> Hi Stefano,
>>
>> It seems that there's some general confusion on the list, so I think
>> a little more background and commentary is in order.
>
> Well, it is - thanks for explanation.
>
>>
>> The primary rationale for plugins is to allow separate link maps in
>> a single image loaded by the BootROM.
>>
>> The idea is to allow first-level code to initialize resources (usually
>> DDR) while running in internal RAM, then return to the boot rom for
>> further image loading (typically into DDR). This prevents the need
>> for the first-level code to support all boot sources (SPI-NOR,
>> NAND, SD card, etc) and allows it to focus on machine setup.
>>
>> The feature is normally needed to allow the first level to access
>> a PMIC. I'm surprised that the 51evk and 53Loco boards aren't
>> using it.
>
> The mx51 uses a V1 header and the plugin feature is not supported at
> all. So, it can't, simply. The mx53 can, but it is not needed.
> Both boards boot without plugin. So it seem we have a misunderstanding,
> and thanks to raise this issue ;-)
>
> The setup is done by the SOC interpreting the DCD data into the iMX
> header. After this setup, that in any case cannot be very long, the
> control is still taken by the bootROM, that copies data from the media
> device to the DDR according to the values set into the iMX header. Still
> without plugin. After the copy, the bootROM gives the control to U-Boot
> for the rest that starts with the usual initialization.
>
> There is no need to setup the pMIC on mx51evk and mx53qsb to get the DDR
> running. However, even if we need it, we can do it in another way, as I
> will explain now.
>
>>
>> Troy's rationale for using it now is to enable a single image on
>> i.MX6Quad, Dual lite and Solo processors, which have very slight
>> initialization differences. The 6Solo processor has 32-bit DDR
>> bus, so it would otherwise require a separate binary.
>>
>> By doing this in code (plugin), we can introduce a conditional
>> based on processor type and have a single image that will boot
>> on any of the three.
>
> Ok - but why cannot this check be done directly by U-Boot ?
>
> My understanding is that you want to add a plugin written in assembly to
> allow different setup of the DDR controller. Let's see how we can do
> with standard U-Boot code.
>
> Core of the startup is that the SOC copies itself some code into the
> internal RAM and started. This is done by bootROM, running is own code
> and running the plugin.
>
> We have already this mechanism with the SPL framework. The big advantage
> for this approach is that the same mechanism can be used on SOC of
> different vendors, while the one in this series is a solution strictly
> bound with (some) Freescale's SOC.
>
> The imx header can be still adapted to copy the SPL code into the
> internal RAM. When SPL is running, you have all freedom to check which
> is the CPU running and to adjust your DDR setting, and everything is C
> code. Both MX5 and MX6 have plenty of internal RAM to do this, because
> SPL requires ~30KB.
>
This is the part that gets interesting.
You're right that SPL **can** do the job, but only if it supports
the boot media. For the most part, it's reasonable to expect the
code to be written in U-Boot for that, since the boot media may
also be used to load kernels, RAM disks and the like.
But what about the serial boot modes (especially USB)? We likely
wouldn't implement them (we haven't yet pulled in USB slave support)
and to paraphrase US bumper stickers:
You can take imx_usb away from me when you pry it
from my cold dead hands ;)
If you're not aware of imx_usb, it's a utility that Troy wrote
to allow download over the boot ROM's USB protocol.
Some commentary is here:
http://boundarydevices.com/unbricking-nitrogen6x-sabre-lite-i-mx6-board/
The sources are here (requires libusb):
https://github.com/boundarydevices/imx_usb_loader
> I think the goal to have the same U-Boot binary can be reached using the
> SPL framework. As you are running U-Boot code, you have the possibility
> to do whatever you want.
>
> So my question is: if the main reason is to have a single image for all
> your iMX6 boards, why cannot we do it in a standard way using SPL ?
>
The related question is whether or not the benefits of a single
image is worth the carrying cost.
This is probably more useful for those who boot directly to
SD card, where the cost of creation or modification of the SD
card is high.
Since our boards are booting to SPI-NOR, I'm not completely
convinced.
It seems that simply creating three targets for each is okay, since
we know what processor we placed on the board and our boot mode
switches make it relatively easy to recover from a screw-up.
>>
>> The other key change for these processors is the location of
>> the iomux controller (moved on 6Solo/Duallite from 6Quad).
>>
>> 6Solo has 32-bit DDR and iomux controller moved from 6Q
>> 6Duallite has 64-bit DDR but same iomux location as 6Q
>>
>> Note that this highlights a slight down side to the plugin approach.
>>
>> Because of the movement of the iomux controller, we can't use
>> a universal i.MX6 image header to write any IOMUX registers
>> through imximage.cfg.
>
> However, you can do it with this approach:
>
> - you have a general imx header, that does not write into IOMUX
> It is your choice if this should set the DDR or not. You could also
> decide to have an empty DCD table.
> - your imx Header is generated for your SPL code, and the destination
> address for the SPL code is put into internal RAM
> - the bootROM will start reading the iMX header and DCD data and copies
> data from media (NAND, SPI, ..) into iRAM. There is no need for any
> special setup because the iRAM is always available. Then it gives the
> control to the SPL.
> - the SPL starts and performs the setup of the DDR, checking the SOC if
> it is required. The usual SOC initialization is done here.
> - At the end, the SPL loads from media the U-Boot or directly the kernel
> and starts it. Or whatever image you want.
>
> The further advantage we can have with this approach is that we can
> profit for further development in u-boot. What I mean really is using
> TPL, that means putting u-boot into a UBL volume, see:
>
> http://lists.celinuxforum.org/pipermail/celinux-dev/2012-April/000543.html
>
> I know there is not yet activity on this topic, but it does not mean we
> have not in future.
>
This is a good conversation to have.
Regards,
Eric
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 08/21] mx6: add plugin file for use with imximage.cfg
2012-09-23 23:29 ` Eric Nelson
@ 2012-09-24 7:22 ` Stefano Babic
2012-09-24 13:48 ` Eric Nelson
0 siblings, 1 reply; 430+ messages in thread
From: Stefano Babic @ 2012-09-24 7:22 UTC (permalink / raw)
To: u-boot
On 24/09/2012 01:29, Eric Nelson wrote:
>
> This is the part that gets interesting.
>
> You're right that SPL **can** do the job, but only if it supports
> the boot media. For the most part, it's reasonable to expect the
> code to be written in U-Boot for that, since the boot media may
> also be used to load kernels, RAM disks and the like.
>
> But what about the serial boot modes (especially USB)? We likely
> wouldn't implement them (we haven't yet pulled in USB slave support)
> and to paraphrase US bumper stickers:
>
> You can take imx_usb away from me when you pry it
> from my cold dead hands ;)
>
> If you're not aware of imx_usb, it's a utility that Troy wrote
> to allow download over the boot ROM's USB protocol.
>
> Some commentary is here:
> http://boundarydevices.com/unbricking-nitrogen6x-sabre-lite-i-mx6-board/
>
>
> The sources are here (requires libusb):
> https://github.com/boundarydevices/imx_usb_loader
>
Nice job ! This is very valuable tool !
But I do not get the connection with the imximage and the need for the
plugin. If the SOC boots with "Serial Downloader", it polls the USB OTG
waiting for command as specified in the protocol. With your tool you set
the registers you need and you can download the file you want,
independently from the structure of the imxImage.
By the way, I have missed that Troy had implemented this tool - thanks
for the tipp and to share it !
>> I think the goal to have the same U-Boot binary can be reached using the
>> SPL framework. As you are running U-Boot code, you have the possibility
>> to do whatever you want.
>>
>> So my question is: if the main reason is to have a single image for all
>> your iMX6 boards, why cannot we do it in a standard way using SPL ?
>>
>
> The related question is whether or not the benefits of a single
> image is worth the carrying cost.
I have interpreted from your answers that it was a goal for you. I think
the costs are higher than the benefits.
>
> This is probably more useful for those who boot directly to
> SD card, where the cost of creation or modification of the SD
> card is high.
>
> Since our boards are booting to SPI-NOR, I'm not completely
> convinced.
>
> It seems that simply creating three targets for each is okay, since
> we know what processor we placed on the board and our boot mode
> switches make it relatively easy to recover from a screw-up.
Fully agree.
>
>>>
>>> The other key change for these processors is the location of
>>> the iomux controller (moved on 6Solo/Duallite from 6Quad).
>>>
>>> 6Solo has 32-bit DDR and iomux controller moved from 6Q
>>> 6Duallite has 64-bit DDR but same iomux location as 6Q
>>>
>>> Note that this highlights a slight down side to the plugin approach.
>>>
>>> Because of the movement of the iomux controller, we can't use
>>> a universal i.MX6 image header to write any IOMUX registers
>>> through imximage.cfg.
>>
>> However, you can do it with this approach:
>>
>> - you have a general imx header, that does not write into IOMUX
>> It is your choice if this should set the DDR or not. You could also
>> decide to have an empty DCD table.
>> - your imx Header is generated for your SPL code, and the destination
>> address for the SPL code is put into internal RAM
>> - the bootROM will start reading the iMX header and DCD data and copies
>> data from media (NAND, SPI, ..) into iRAM. There is no need for any
>> special setup because the iRAM is always available. Then it gives the
>> control to the SPL.
>> - the SPL starts and performs the setup of the DDR, checking the SOC if
>> it is required. The usual SOC initialization is done here.
>> - At the end, the SPL loads from media the U-Boot or directly the kernel
>> and starts it. Or whatever image you want.
>>
>> The further advantage we can have with this approach is that we can
>> profit for further development in u-boot. What I mean really is using
>> TPL, that means putting u-boot into a UBL volume, see:
>>
>> http://lists.celinuxforum.org/pipermail/celinux-dev/2012-April/000543.html
>>
>>
>> I know there is not yet activity on this topic, but it does not mean we
>> have not in future.
>>
>
> This is a good conversation to have.
Best regards,
Stefano
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 08/21] mx6: add plugin file for use with imximage.cfg
2012-09-24 7:22 ` Stefano Babic
@ 2012-09-24 13:48 ` Eric Nelson
2012-09-24 15:17 ` Stefano Babic
0 siblings, 1 reply; 430+ messages in thread
From: Eric Nelson @ 2012-09-24 13:48 UTC (permalink / raw)
To: u-boot
Hi Stefano,
On 09/24/2012 12:22 AM, Stefano Babic wrote:
> On 24/09/2012 01:29, Eric Nelson wrote:
>>
>> This is the part that gets interesting.
>>
>> You're right that SPL **can** do the job, but only if it supports
>> the boot media. For the most part, it's reasonable to expect the
>> code to be written in U-Boot for that, since the boot media may
>> also be used to load kernels, RAM disks and the like.
>>
>> But what about the serial boot modes (especially USB)? We likely
>> wouldn't implement them (we haven't yet pulled in USB slave support)
>> and to paraphrase US bumper stickers:
>>
>> You can take imx_usb away from me when you pry it
>> from my cold dead hands ;)
>>
>> If you're not aware of imx_usb, it's a utility that Troy wrote
>> to allow download over the boot ROM's USB protocol.
>>
>> Some commentary is here:
>> http://boundarydevices.com/unbricking-nitrogen6x-sabre-lite-i-mx6-board/
>>
>>
>> The sources are here (requires libusb):
>> https://github.com/boundarydevices/imx_usb_loader
>>
>
> Nice job ! This is very valuable tool !
>
> But I do not get the connection with the imximage and the need for the
> plugin. If the SOC boots with "Serial Downloader", it polls the USB OTG
> waiting for command as specified in the protocol. With your tool you set
> the registers you need and you can download the file you want,
> independently from the structure of the imxImage.
>
The relationship is this: if we build a combined SPL image for
a universal i.MX6 U-Boot, how would it know/decide that it's
being loaded via USB and how would it support this?
imx_usb supports plugins, so we can use it directly with that
approach.
> By the way, I have missed that Troy had implemented this tool - thanks
> for the tipp and to share it !
>
NP.
It really helps the compile/test cycle time, especially when used with the
'bmode usb' command.
>>> I think the goal to have the same U-Boot binary can be reached using the
>>> SPL framework. As you are running U-Boot code, you have the possibility
>>> to do whatever you want.
>>>
>>> So my question is: if the main reason is to have a single image for all
>>> your iMX6 boards, why cannot we do it in a standard way using SPL ?
>>>
>>
>> The related question is whether or not the benefits of a single
>> image is worth the carrying cost.
>
> I have interpreted from your answers that it was a goal for you. I think
> the costs are higher than the benefits.
>
>>
>> This is probably more useful for those who boot directly to
>> SD card, where the cost of creation or modification of the SD
>> card is high.
>>
>> Since our boards are booting to SPI-NOR, I'm not completely
>> convinced.
>>
>> It seems that simply creating three targets for each is okay, since
>> we know what processor we placed on the board and our boot mode
>> switches make it relatively easy to recover from a screw-up.
>
> Fully agree.
>
>>
>>>>
>>>> The other key change for these processors is the location of
>>>> the iomux controller (moved on 6Solo/Duallite from 6Quad).
>>>>
>>>> 6Solo has 32-bit DDR and iomux controller moved from 6Q
>>>> 6Duallite has 64-bit DDR but same iomux location as 6Q
>>>>
>>>> Note that this highlights a slight down side to the plugin approach.
>>>>
>>>> Because of the movement of the iomux controller, we can't use
>>>> a universal i.MX6 image header to write any IOMUX registers
>>>> through imximage.cfg.
>>>
>>> However, you can do it with this approach:
>>>
>>> - you have a general imx header, that does not write into IOMUX
>>> It is your choice if this should set the DDR or not. You could also
>>> decide to have an empty DCD table.
>>> - your imx Header is generated for your SPL code, and the destination
>>> address for the SPL code is put into internal RAM
>>> - the bootROM will start reading the iMX header and DCD data and copies
>>> data from media (NAND, SPI, ..) into iRAM. There is no need for any
>>> special setup because the iRAM is always available. Then it gives the
>>> control to the SPL.
>>> - the SPL starts and performs the setup of the DDR, checking the SOC if
>>> it is required. The usual SOC initialization is done here.
>>> - At the end, the SPL loads from media the U-Boot or directly the kernel
>>> and starts it. Or whatever image you want.
>>>
>>> The further advantage we can have with this approach is that we can
>>> profit for further development in u-boot. What I mean really is using
>>> TPL, that means putting u-boot into a UBL volume, see:
>>>
>>> http://lists.celinuxforum.org/pipermail/celinux-dev/2012-April/000543.html
>>>
>>>
>>> I know there is not yet activity on this topic, but it does not mean we
>>> have not in future.
>>>
>>
>> This is a good conversation to have.
>
> Best regards,
> Stefano
>
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 08/21] mx6: add plugin file for use with imximage.cfg
2012-09-24 13:48 ` Eric Nelson
@ 2012-09-24 15:17 ` Stefano Babic
0 siblings, 0 replies; 430+ messages in thread
From: Stefano Babic @ 2012-09-24 15:17 UTC (permalink / raw)
To: u-boot
On 24/09/2012 15:48, Eric Nelson wrote:
> Hi Stefano,
>
Hi Eric,
>> But I do not get the connection with the imximage and the need for the
>> plugin. If the SOC boots with "Serial Downloader", it polls the USB OTG
>> waiting for command as specified in the protocol. With your tool you set
>> the registers you need and you can download the file you want,
>> independently from the structure of the imxImage.
>>
>
> The relationship is this: if we build a combined SPL image for
> a universal i.MX6 U-Boot, how would it know/decide that it's
> being loaded via USB and how would it support this?
>
> imx_usb supports plugins, so we can use it directly with that
> approach.
But this seems to me an implementation choice rather a constraint of the
SOC. As I see in your code, imx_usb parses the iMX header making
decisions according to it. Then there is a hard dependency between
imx_usb and u-boot code.
The other way is that they are independently, let's say, openOCD
approach ;-).
imx_usb could get an independent file to configure the DDR controller
(for example, but it is not limited to), and then load a u-boot (or SPL,
or...) where you want. Then there is no strict dependency with the
imx_usb tool. The SOC allows this approach, too.
Best regards,
Stefano
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 01/21] imximage: make header variable length
2012-09-23 10:57 ` Stefano Babic
@ 2012-09-24 20:30 ` Troy Kisky
2012-09-25 11:08 ` Stefano Babic
0 siblings, 1 reply; 430+ messages in thread
From: Troy Kisky @ 2012-09-24 20:30 UTC (permalink / raw)
To: u-boot
On 9/23/2012 3:57 AM, Stefano Babic wrote:
> On 22/09/2012 04:38, Troy Kisky wrote:
>
> Hi Troy,
>
>> Also, the header offset is no longer
>> right before the code starts.
> Comment and subject of the patch do not match. Can you better explain it
> ? What have "making header variable length", that is, a new feature,
> with " the header offset is no longer rigth", that is, a bug ?
>
> Do we already have a variable header the we add a vrec_header function
> to image_type_params ?
Before this patch we have
000000 402000d1 17800000 00000000 177ffc2c
000010 177ffc20 177ffc00 00000000 00000000
000020 177ff800 00042b58 00000000 402803d2
000030 042403cc a8050e02 30000000 b0050e02
... more DCD table
000340 cf0000f0 18000e02 7f007f00 1c000e02
000350 7f007f00 00000000 00000000 00000000
000360 00000000 00000000 00000000 00000000
*
0003f0 00000000 00000000 00000000 00000400
000400 ea000014 e59ff014 e59ff014 e59ff014
Notice offset 3fc contains 0x400. This
is the header offset. There is no reason
for this to be in the file, and I have
removed it.
After this patch we have
000000 402000d1 17800000 00000000 177ffcd8
000010 177ffccc 177ffcac 00000000 00000000
000020 177ff8ac 000426ac 00000000 402803d2
000030 042403cc a8050e02 30000000 b0050e02
... more DCD table
000340 cf0000f0 18000e02 7f007f00 1c000e02
000350 7f007f00 ea000014 e59ff014 e59ff014
000360 e59ff014 e59ff014 e59ff014 e59ff014
Notice the zeros between 0x354 and 0x3fb have
been removed. That is what I mean by making it
a variable length header.
>> Series tested on an mx51 and mx6q
>> ---
>> tools/imximage.c | 142 +++++++++++++++++++++++++++++++-----------------------
>> tools/imximage.h | 10 ++--
>> 2 files changed, 87 insertions(+), 65 deletions(-)
>>
>> diff --git a/tools/imximage.c b/tools/imximage.c
>> index 03a7716..25d3b74 100644
>> --- a/tools/imximage.c
>> +++ b/tools/imximage.c
>> @@ -65,12 +65,15 @@ static table_entry_t imximage_versions[] = {
>> {-1, "", " (Invalid)", },
>> };
>>
>> -static struct imx_header imximage_header;
>> static uint32_t imximage_version;
>>
>> static set_dcd_val_t set_dcd_val;
>> static set_dcd_rst_t set_dcd_rst;
>> static set_imx_hdr_t set_imx_hdr;
>> +static set_imx_size_t set_imx_size;
>> +static uint32_t g_flash_offset;
>> +
>> +static struct image_type_params imximage_params;
>>
>> static uint32_t get_cfg_value(char *token, char *name, int linenr)
>> {
>> @@ -207,85 +210,79 @@ static void set_dcd_rst_v2(struct imx_header *imxhdr, uint32_t dcd_len,
>> dcd_v2->write_dcd_command.param = DCD_COMMAND_PARAM;
>> }
>>
>> -static void set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,
>> - struct stat *sbuf,
>> - struct mkimage_params *params)
>> +static int set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,
>> + uint32_t entry_point, uint32_t flash_offset)
>> {
>> imx_header_v1_t *hdr_v1 = &imxhdr->header.hdr_v1;
>> flash_header_v1_t *fhdr_v1 = &hdr_v1->fhdr;
>> dcd_v1_t *dcd_v1 = &hdr_v1->dcd_table;
>> - uint32_t base_offset;
>> -
>> - /* Exit if there is no BOOT_FROM field specifying the flash_offset */
>> - if(imxhdr->flash_offset == FLASH_OFFSET_UNDEFINED) {
>> - fprintf(stderr, "Error: Header v1: No BOOT_FROM tag in %s\n",
>> - params->imagename);
>> - exit(EXIT_FAILURE);
>> - }
> Do you drop BOOT_FROM ? Then this should be documented. Is this to allow
> that the same image can be loaded from different media, that share the
> same flash offset ? Then, instead of drop it, I suggest to add more
> entries in the imximage file, one for each media that is allow.
No I did not drop the BOOT_FROM command. I merely moved this check before
the function call, as it was common to both set_imx_hdr_v1 and
set_imx_hdr_v2
I can make it a separate patch to make it obvious.
>
> Something like:
> BOOT_FROM sd, nand, spi
>
> and maybe a check in the code if all entries do not share the same start
> address.
>
>> + uint32_t hdr_base;
>> + uint32_t header_length = (((char *)&dcd_v1->addr_data[dcd_len].addr)
>> + - ((char *)imxhdr));
>>
> For V1, the header is preallocated with the maximum size, that is the
> maximum number of DCD entries the SOC in V1 can support. Why do we need
> a dynamic length for V1 processors ? As far as I know, the number of
> entries and fields for theses SOCs (i.MX25, i.MX35, i.MX51) is fixed.
You right the DCD table maximum size is fixed. But why should we be
forced to use
the maximum size? Why make V1 headers a special case?
>
>> /* Set magic number */
>> fhdr_v1->app_code_barker = APP_CODE_BARKER;
>>
>> - fhdr_v1->app_dest_ptr = params->addr;
>> - fhdr_v1->app_dest_ptr = params->ep - imxhdr->flash_offset -
>> - sizeof(struct imx_header);
>> - fhdr_v1->app_code_jump_vector = params->ep;
>> + hdr_base = entry_point - header_length;
>> + fhdr_v1->app_dest_ptr = hdr_base - flash_offset;
>> + fhdr_v1->app_code_jump_vector = entry_point;
>>
>> - base_offset = fhdr_v1->app_dest_ptr + imxhdr->flash_offset ;
>> - fhdr_v1->dcd_ptr_ptr =
>> - (uint32_t) (offsetof(flash_header_v1_t, dcd_ptr) -
>> - offsetof(flash_header_v1_t, app_code_jump_vector) +
>> - base_offset);
>> -
>> - fhdr_v1->dcd_ptr = base_offset +
>> - offsetof(imx_header_v1_t, dcd_table);
>> -
>> - /* The external flash header must be at the end of the DCD table */
>> - dcd_v1->addr_data[dcd_len].type = sbuf->st_size +
>> - imxhdr->flash_offset +
>> - sizeof(struct imx_header);
>> + fhdr_v1->dcd_ptr_ptr = hdr_base + offsetof(flash_header_v1_t, dcd_ptr);
>> + fhdr_v1->dcd_ptr = hdr_base + offsetof(imx_header_v1_t, dcd_table);
>>
>> /* Security feature are not supported */
>> fhdr_v1->app_code_csf = 0;
>> fhdr_v1->super_root_key = 0;
>> + return header_length;
>> +}
>> +
> Ok, I skip review of this part - it depends on your answer on the
> previous question.
>
>>
>> -static void set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t dcd_len,
>> - struct stat *sbuf,
>> - struct mkimage_params *params)
>> +static int set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t dcd_len,
>> + uint32_t entry_point, uint32_t flash_offset)
>> {
>> imx_header_v2_t *hdr_v2 = &imxhdr->header.hdr_v2;
>> flash_header_v2_t *fhdr_v2 = &hdr_v2->fhdr;
>> -
>> - /* Exit if there is no BOOT_FROM field specifying the flash_offset */
>> - if(imxhdr->flash_offset == FLASH_OFFSET_UNDEFINED) {
>> - fprintf(stderr, "Error: Header v2: No BOOT_FROM tag in %s\n",
>> - params->imagename);
>> - exit(EXIT_FAILURE);
>> - }
>> + uint32_t hdr_base;
>> + uint32_t header_length = (dcd_len) ?
>> + (char *)&hdr_v2->dcd_table.addr_data[dcd_len] - ((char*)imxhdr)
>> + : offsetof(imx_header_v2_t, dcd_table);
> So you add a case where there is no DCD table at all. Apart that this
> van be a use case, but does it happen in the real life ?
Yes, after this patch series, sabrelite with use a plugin with no DCD
table at all.
Even your SPL route could use no DCD table.
>
>> /* Set magic number */
>> fhdr_v2->header.tag = IVT_HEADER_TAG; /* 0xD1 */
>> fhdr_v2->header.length = cpu_to_be16(sizeof(flash_header_v2_t));
>> fhdr_v2->header.version = IVT_VERSION; /* 0x40 */
>>
>> - fhdr_v2->entry = params->ep;
>> + fhdr_v2->entry = entry_point;
>> fhdr_v2->reserved1 = fhdr_v2->reserved2 = 0;
>> - fhdr_v2->self = params->ep - sizeof(struct imx_header);
>> -
>> - fhdr_v2->dcd_ptr = fhdr_v2->self +
>> - offsetof(imx_header_v2_t, dcd_table);
>> + fhdr_v2->self = hdr_base = entry_point - header_length;
>>
>> - fhdr_v2->boot_data_ptr = fhdr_v2->self +
>> - offsetof(imx_header_v2_t, boot_data);
>> -
>> - hdr_v2->boot_data.start = fhdr_v2->self - imxhdr->flash_offset;
>> - hdr_v2->boot_data.size = sbuf->st_size +
>> - imxhdr->flash_offset +
>> - sizeof(struct imx_header);
>> + fhdr_v2->dcd_ptr = (dcd_len) ? hdr_base
>> + + offsetof(imx_header_v2_t, dcd_table) : 0;
>> + fhdr_v2->boot_data_ptr = hdr_base
>> + + offsetof(imx_header_v2_t, boot_data);
>> + hdr_v2->boot_data.start = hdr_base - flash_offset;
>>
>> /* Security feature are not supported */
>> fhdr_v2->csf = 0;
>> + return header_length;
>> +}
>> +
>> +static void set_imx_size_v2(struct imx_header *imxhdr, uint32_t file_size,
>> + uint32_t flash_offset)
>> +{
>> + imx_header_v2_t *hdr_v2 = &imxhdr->header.hdr_v2;
>> + /* file_size includes header */
>> + hdr_v2->boot_data.size = file_size + flash_offset;
>> }
>>
>> static void set_hdr_func(struct imx_header *imxhdr)
>> @@ -295,11 +292,13 @@ static void set_hdr_func(struct imx_header *imxhdr)
>> set_dcd_val = set_dcd_val_v1;
>> set_dcd_rst = set_dcd_rst_v1;
>> set_imx_hdr = set_imx_hdr_v1;
>> + set_imx_size = set_imx_size_v1;
>> break;
>> case IMXIMAGE_V2:
>> set_dcd_val = set_dcd_val_v2;
>> set_dcd_rst = set_dcd_rst_v2;
>> set_imx_hdr = set_imx_hdr_v2;
>> + set_imx_size = set_imx_size_v2;
>> break;
>> default:
>> err_imximage_version(imximage_version);
>> @@ -381,9 +380,9 @@ static void parse_cfg_cmd(struct imx_header *imxhdr, int32_t cmd, char *token,
>> set_hdr_func(imxhdr);
>> break;
>> case CMD_BOOT_FROM:
>> - imxhdr->flash_offset = get_table_entry_id(imximage_bootops,
>> + g_flash_offset = get_table_entry_id(imximage_bootops,
>> "imximage boot option", token);
>> - if (imxhdr->flash_offset == -1) {
> Why do we need a global when we have already a way to not use a global ?
Because that flash_offset is unnecessarily taking up space in the output
file, and with
variable length headers, I might overwrite it with other data.
>
>> + if (g_flash_offset == -1) {
>> fprintf(stderr, "Error: %s[%d] -Invalid boot device"
>> "(%s)\n", name, lineno, token);
>> exit(EXIT_FAILURE);
>> @@ -521,12 +520,17 @@ static void imximage_print_header(const void *ptr)
>> }
>> }
>>
>> -static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd,
>> - struct mkimage_params *params)
>> +int imximage_vrec_header(struct mkimage_params *params,
>> + struct image_type_params *tparams)
>> {
>> - struct imx_header *imxhdr = (struct imx_header *)ptr;
>> + struct imx_header *imxhdr;
>> uint32_t dcd_len;
>>
>> + imxhdr = calloc(1, MAX_HEADER_SIZE);
>> + if (!imxhdr) {
>> + fprintf(stderr, "Error: out of memory\n");
>> + exit(EXIT_FAILURE);
>> + }
>> /*
>> * In order to not change the old imx cfg file
>> * by adding VERSION command into it, here need
>> @@ -534,14 +538,31 @@ static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd,
>> */
>> imximage_version = IMXIMAGE_V1;
>> /* Be able to detect if the cfg file has no BOOT_FROM tag */
>> - imxhdr->flash_offset = FLASH_OFFSET_UNDEFINED;
>> + g_flash_offset = FLASH_OFFSET_UNDEFINED;
>> set_hdr_func(imxhdr);
>>
>> /* Parse dcd configuration file */
>> dcd_len = parse_cfg_file(imxhdr, params->imagename);
>>
>> + /* Exit if there is no BOOT_FROM field specifying the flash_offset */
>> + if (g_flash_offset == FLASH_OFFSET_UNDEFINED) {
>> + fprintf(stderr, "Error: No BOOT_FROM tag in %s\n",
>> + params->imagename);
>> + exit(EXIT_FAILURE);
>> + }
>> /* Set the imx header */
>> - (*set_imx_hdr)(imxhdr, dcd_len, sbuf, params);
>> + imximage_params.header_size = (*set_imx_hdr)(imxhdr, dcd_len,
>> + params->ep, g_flash_offset);
>> + imximage_params.hdr = imxhdr;
>> + return 0;
>> +}
>> +
>> +static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd,
>> + struct mkimage_params *params)
>> +{
>> + /* Set the size in header */
>> + (*set_imx_size)((struct imx_header *)ptr, sbuf->st_size,
>> + g_flash_offset);
>> }
>>
>> int imximage_check_params(struct mkimage_params *params)
>> @@ -571,8 +592,9 @@ int imximage_check_params(struct mkimage_params *params)
>> */
>> static struct image_type_params imximage_params = {
>> .name = "Freescale i.MX 5x Boot Image support",
>> - .header_size = sizeof(struct imx_header),
>> - .hdr = (void *)&imximage_header,
>> + .header_size = 0,
>> + .hdr = NULL,
>> + .vrec_header = imximage_vrec_header,
>> .check_image_type = imximage_check_image_types,
>> .verify_header = imximage_verify_header,
>> .print_header = imximage_print_header,
>> diff --git a/tools/imximage.h b/tools/imximage.h
>> index 34f293d..5fe3a8a 100644
>
>> --- a/tools/imximage.h
>> +++ b/tools/imximage.h
>> @@ -30,6 +30,7 @@
>> #define DCD_BARKER 0xB17219E9
>>
>> #define HEADER_OFFSET 0x400
>> +#define MAX_HEADER_SIZE (16 << 10)
>>
>> #define CMD_DATA_STR "DATA"
>> #define FLASH_OFFSET_UNDEFINED 0xFFFFFFFF
>> @@ -156,7 +157,6 @@ struct imx_header {
>> imx_header_v1_t hdr_v1;
>> imx_header_v2_t hdr_v2;
>> } header;
>> - uint32_t flash_offset;
>> };
>>
>> typedef void (*set_dcd_val_t)(struct imx_header *imxhdr,
>> @@ -168,9 +168,9 @@ typedef void (*set_dcd_rst_t)(struct imx_header *imxhdr,
>> uint32_t dcd_len,
>> char *name, int lineno);
>>
>> -typedef void (*set_imx_hdr_t)(struct imx_header *imxhdr,
>> - uint32_t dcd_len,
>> - struct stat *sbuf,
>> - struct mkimage_params *params);
>> +typedef int (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t dcd_len,
>> + uint32_t entry_point, uint32_t flash_offset);
>> +typedef void (*set_imx_size_t)(struct imx_header *imxhdr, uint32_t file_size,
>> + uint32_t flash_offset);
> I disagree here. mkimage is valid for all architecture, we must not have
> special entries here for a SOC or SOC family. For all other SOCs, DCD,
> iMX header have no sense.
> Anyway, why do you need to add set_imx_size_t when you call it only in
> imximage.c ?
I think you misread the file name. This is imximage.h.
But I will squash the removal of set_imx_size_t done in a later
patch with this one to make it easier to review.
>
>>
>> #endif /* _IMXIMAGE_H_ */
> You should split changes in image.h, that are valid for all
> architecture, from changes to imximage.c, that are only for i.MX, into
> different patches.
>
> In my understanding you add additional entry points to have a variable
> header lenght, but this feature is already used on TI with the AIS
> image. You use also vrec_header. What am I missing here ?
I did not change image.h at all.
>
>
> Best regards,
> Stefano Babic
>
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 08/21] mx6: add plugin file for use with imximage.cfg
2012-09-23 10:17 ` Stefano Babic
2012-09-23 16:23 ` Eric Nelson
@ 2012-09-24 20:46 ` Troy Kisky
2012-09-25 11:57 ` Stefano Babic
1 sibling, 1 reply; 430+ messages in thread
From: Troy Kisky @ 2012-09-24 20:46 UTC (permalink / raw)
To: u-boot
On 9/23/2012 3:17 AM, Stefano Babic wrote:
> On 22/09/2012 04:39, Troy Kisky wrote:
>> The "plugin" command of mkimage can take this
>> file as an argument.
>>
>> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
>> ---
> Hi Troy,
>
> I agree with Vikram that a better explanation of what a plugin is can
> help to understand without reading deeply into the i.MX6 manual.
>
> So a "plugin" is a chunk of code that can be called directly by the
> BootROM of i.MX processors supporting V2 version of the i.MX header.
> In my understanding, this is supported by i.MX53, too. After the plugin
> run, the control is returned to the BootROM.
>
> Now that we have some basis, why do we need this mechanism to boot this
> board ? Is it not possible to make the same initialization directly in
> u-boot ?
>
> In principle, this adds stil some code that is not so easy to maintain.
I can add to README.imximage. But I'm beginning to doubt if plugins are
going
to be accepted at all.
>
>> arch/arm/cpu/armv7/mx6/Makefile | 5 +-
>> arch/arm/cpu/armv7/mx6/plugin.S | 164 ++++++++++++++++++++++++++++++
>> arch/arm/include/asm/arch-mx6/imx-regs.h | 1 +
>> 3 files changed, 169 insertions(+), 1 deletion(-)
>> create mode 100644 arch/arm/cpu/armv7/mx6/plugin.S
>>
>> diff --git a/arch/arm/cpu/armv7/mx6/Makefile b/arch/arm/cpu/armv7/mx6/Makefile
>> index cbce411..b1fce4e 100644
>> --- a/arch/arm/cpu/armv7/mx6/Makefile
>> +++ b/arch/arm/cpu/armv7/mx6/Makefile
>> @@ -33,11 +33,14 @@ SOBJS = lowlevel_init.o
>> SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
>> OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
>>
>> -all: $(obj).depend $(LIB)
>> +all: $(obj).depend $(LIB) plugin.bin
>>
>> $(LIB): $(OBJS)
>> $(call cmd_link_o_target, $(OBJS))
>>
>> +plugin.bin: plugin.o
>> + $(OBJCOPY) -O binary --gap-fill 0xff $< $@
> If we add a plugin mechanism, we can have several plugins (booting
> directly from Net, maybe ?). We should then have a general mechanism. A
> directory "plugins" here can contain the code, and it is compiled only
> if a CONFIG_ is set or better if required from imximage.cfg
CONFIG_xx I understand, but can you describe an implementation from
imximage.cfg?
>
>
>> +
>> #########################################################################
>>
>> # defines $(obj).depend target
>> diff --git a/arch/arm/cpu/armv7/mx6/plugin.S b/arch/arm/cpu/armv7/mx6/plugin.S
>> new file mode 100644
>> index 0000000..99c6b20
>> --- /dev/null
>> +++ b/arch/arm/cpu/armv7/mx6/plugin.S
>> @@ -0,0 +1,164 @@
>> +/*
>> + * Copyright (C) 2012 Boundary Devices Inc.
>> + *
>> + * Licensed under the GPL-2 or later.
>> + */
>> +#include <config.h>
>> +#include <asm/arch/imx-regs.h>
>> +
>> +#define HAB_RVT_ENTRY 0x98
>> +#define HAB_RVT_FAIL_SAFE_VECT 0xbc
>> +#define HAB_RVT_LOAD_DATA 0xc8
>> +
>> +#define HDR_SELF_PTR 0x14
>> +#define HDR_BOOT_DATA 0x20
>> +#define HDR_IMAGE_LEN 0x24
>> +
>> +#define L2X0_CTRL 0x100
>> +#define SCU_CONFIG 0x004
>> +
>> +/*
>> + * Disable L2 cache because ROM will turn it on when a plugin is used.
>> + * There are cache coherence problems if cache is on when Linux kernel
>> + * expects it to be off.
>> + */
>> +.macro disable_l2_cache
>> + ldr r1, =L2_BASE_ADDR
>> + mov r0, #0x0
>> + str r0, [r1, #L2X0_CTRL]
>> +.endm
>> +
>> +
>> +/*
>> + * plugin_start(void **start, size_t *bytes, UINT32 *ivt_offset)
>> + */
>> +plugin_start:
>> +/* Save the return address and the function arguments */
>> + push {r0-r8, lr}
>> +
>> +/* r0-r2 must be >= 0x100 and must be 4 byte aligned */
>> + cmp r0, #0x100
>> + cmphs r1, #0x100
>> + cmphs r2, #0x100
>> +
>> +/* rCPU: 22 - mx6q, 12 - mx6dl, 12|0x100 - solo, 2 - sololite */
>> +#define rCPU r2
>> +#define rIomux r3
>> +#define rVal0 r4 /* mx6q value */
>> +#define rVal1 r5 /* mx6dl value */
>> +#define rVal2 r6 /* mx6solo value */
>> +#define rVal3 r7 /* mx6sololite value */
>> +#define rFlag lr
>> +#define rTable r8
>> +
>> + orr rFlag, r0, r1
>> + orr rFlag, rFlag, r2
>> + orrlo rFlag, rFlag, #1
>> +
>> + mov rCPU, #22 /* mx6q */
>> + mov r1, #SCU_BASE_ADDR
>> + ldr r0, [r1, #SCU_CONFIG]
>> + and r0, r0, #3
>> + cmp r0, #3 /* is mx6q? */
>> + movne rCPU, #12 /* mx6dl */
>> + cmpne r0, #1 /* is mx6dl? */
>> + movne rCPU, #2 /* mx6 sololite */
>> +
>> + ldrne r1, =ANATOP_BASE_ADDR
>> + ldrne r0, [r1, #0x280]
>> + movne r0, r0, LSR #16
>> + cmpne r0, #0x60 /* is mx6 Sololite? */
>> + movne rCPU, #12 | 0x100 /* Solo */
> Ok - until here you have checked which processor is running. Now the
> more obscure code:
>
>> +
>> + mov rVal0, #0
>> + mov rVal1, #0
>> + mov rVal2, #0
>> + mov rVal3, #0
>> + ldr rIomux, =IOMUXC_BASE_ADDR
>> + adr rTable, mx6_table
>> + b 3f
>
>
>> +
>> +1: movs r0, r1, LSR #30
>> + beq 2f
>> + mov r1, r1, LSL rCPU
>> + movs r1, r1, LSR #32-10
>> + addne r1, rIomux, r1, LSL #2
>> + cmp r0, #3
>> + subne r0, r0, #1
>> + orr r1, r1, r0
>> +
> The reason is to write GPR12 ? But why do we need a plugin for that ? I
> do not understand why we cannot do it in the initialization code of the
> SOC, as we usually do.
This is not GPR12. The address value from the cfg file is actually 3
addresses. One for
mx6q, one for mx6 duallite/solo, one for mx6 sololite. Each is specified
as a 10 bit
field which we use as a 12 bit offset within IOMUXC_BASE_ADDR (A0/A1
forced to 0).
>
>> +2: ands r0, r1, #3
>> + bic r1, r1, #3
>> + ldrne rVal0, [rTable], #4
>> + movne rVal1, rVal0
>> + movne rVal2, rVal0
>> + movne rVal3, rVal0
>> + subnes r0, r0, #1
>> + ldrne rVal1, [rTable], #4
>> + movne rVal2, rVal1
>> + movne rVal3, rVal1
>> + subnes r0, r0, #1
>> + ldrne rVal2, [rTable], #4
>> + ldrne rVal3, [rTable], #4
>> +
>> + mov r0, rVal0
>> + cmp rCPU, #22
>> + movne r0, rVal1
>> + cmpne rCPU, #12
>> + movne r0, rVal2
>> + cmpne rCPU, #12|0x100
>> + movne r0, rVal3
>> + cmp r1, #0
>> + strne r0, [r1]
>> +3: ldr r1, [rTable], #4
>> + cmp r1, #0
>> + bne 1b
>> +
>> + tst rFlag, #3
>> + bne 4f /* Branch if not called as plugin */
>> +/* Align end of table to 64 byte boundary */
>> + sub rTable, rTable, #1
>> + orr rTable, rTable, #0x3f
>> + add rTable, rTable, #1
>> + ldr r2, [rTable, #HDR_SELF_PTR]
>> + ldr r0, [rTable, #HDR_BOOT_DATA]
>> + ldr r1, [rTable, #HDR_IMAGE_LEN]
>> + sub rTable, r2, r0
>> + mov r2, r0
>> + mov r3, r1
>> + mov r4, #0
>> + push {r0-r4}
>> + mov r0, #HAB_RVT_LOAD_DATA
>> + ldr r4, [r0]
>> + mov r0, sp
>> + add r1, sp, #4
>> + add r2, sp, #8
>> + blx r4
> Sorry, I need help to understand this code
Now that DDR is initialized, this is calling back into the ROM code
so that it can finish loading u-boot.
>
>> +
>> + disable_l2_cache
>> + pop {r4, r5}
>> + add sp, sp, #12
>> + pop {r0-r3}
>> +/*
>> + * Before returning to ROM, we need to fill the return values arguments
>> + * to our function.
>> + * plugin_start(void **start, size_t *bytes, UINT32 *ivt_offset)
> As the i.MX and the API suggest, it should be possible to write C code
> for a plugin. Or am I wrong ?
I don't see why not. But this code is currently position independent. It
would be nice to maintain that.
>
>
>> diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
>> index 8834c59..5c133b2 100644
>> --- a/arch/arm/include/asm/arch-mx6/imx-regs.h
>> +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
>> @@ -48,6 +48,7 @@
>> #define GLOBAL_TIMER_BASE_ADDR 0x00A00200
>> #define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600
>> #define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000
>> +#define L2_BASE_ADDR 0x00A02000
>> #define GPV0_BASE_ADDR 0x00B00000
>> #define GPV1_BASE_ADDR 0x00C00000
>> #define PCIE_ARB_BASE_ADDR 0x01000000
>>
> This is useful in any case. I suggest you put this define in a separate
> patch, that can flow independently into mainline.
>
> Best regards,
> Stefano Babic
>
Hmm, do you suggest moving the L2 disable code to another spot as well ?
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 02/21] imximage: check dcd_len as entries added
2012-09-23 11:05 ` Stefano Babic
@ 2012-09-24 20:54 ` Troy Kisky
2012-09-25 11:12 ` Stefano Babic
0 siblings, 1 reply; 430+ messages in thread
From: Troy Kisky @ 2012-09-24 20:54 UTC (permalink / raw)
To: u-boot
On 9/23/2012 4:05 AM, Stefano Babic wrote:
> On 22/09/2012 04:38, Troy Kisky wrote:
>> Before the len was checked after the entire file
>> was processed, so it could have already overflowed.
>>
> Hi Troy,
>
>> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
>> ---
>> tools/imximage.c | 26 +++++++++++---------------
>> 1 file changed, 11 insertions(+), 15 deletions(-)
>>
>> diff --git a/tools/imximage.c b/tools/imximage.c
>> index 25d3b74..0bfbec3 100644
>> --- a/tools/imximage.c
>> +++ b/tools/imximage.c
>> @@ -71,6 +71,7 @@ static set_dcd_val_t set_dcd_val;
>> static set_dcd_rst_t set_dcd_rst;
>> static set_imx_hdr_t set_imx_hdr;
>> static set_imx_size_t set_imx_size;
>> +static uint32_t max_dcd_entries;
>> static uint32_t g_flash_offset;
>>
>> static struct image_type_params imximage_params;
>> @@ -173,13 +174,6 @@ static void set_dcd_rst_v1(struct imx_header *imxhdr, uint32_t dcd_len,
>> {
>> dcd_v1_t *dcd_v1 = &imxhdr->header.hdr_v1.dcd_table;
>>
>> - if (dcd_len > MAX_HW_CFG_SIZE_V1) {
>> - fprintf(stderr, "Error: %s[%d] -"
>> - "DCD table exceeds maximum size(%d)\n",
>> - name, lineno, MAX_HW_CFG_SIZE_V1);
>> - exit(EXIT_FAILURE);
>> - }
>> -
>> dcd_v1->preamble.barker = DCD_BARKER;
>> dcd_v1->preamble.length = dcd_len * sizeof(dcd_type_addr_data_t);
>> }
>> @@ -193,13 +187,6 @@ static void set_dcd_rst_v2(struct imx_header *imxhdr, uint32_t dcd_len,
>> {
>> dcd_v2_t *dcd_v2 = &imxhdr->header.hdr_v2.dcd_table;
>>
>> - if (dcd_len > MAX_HW_CFG_SIZE_V2) {
>> - fprintf(stderr, "Error: %s[%d] -"
>> - "DCD table exceeds maximum size(%d)\n",
>> - name, lineno, MAX_HW_CFG_SIZE_V2);
>> - exit(EXIT_FAILURE);
>> - }
>> -
>> dcd_v2->header.tag = DCD_HEADER_TAG;
>> dcd_v2->header.length = cpu_to_be16(
>> dcd_len * sizeof(dcd_addr_data_t) + 8);
>> @@ -293,12 +280,14 @@ static void set_hdr_func(struct imx_header *imxhdr)
>> set_dcd_rst = set_dcd_rst_v1;
>> set_imx_hdr = set_imx_hdr_v1;
>> set_imx_size = set_imx_size_v1;
>> + max_dcd_entries = MAX_HW_CFG_SIZE_V1;
>> break;
>> case IMXIMAGE_V2:
>> set_dcd_val = set_dcd_val_v2;
>> set_dcd_rst = set_dcd_rst_v2;
>> set_imx_hdr = set_imx_hdr_v2;
>> set_imx_size = set_imx_size_v2;
>> + max_dcd_entries = MAX_HW_CFG_SIZE_V2;
>> break;
>> default:
>> err_imximage_version(imximage_version);
>> @@ -425,8 +414,15 @@ static void parse_cfg_fld(struct imx_header *imxhdr, int32_t *cmd,
>> value = get_cfg_value(token, name, lineno);
>> (*set_dcd_val)(imxhdr, name, lineno, fld, value, *dcd_len);
>>
>> - if (fld == CFG_REG_VALUE)
>> + if (fld == CFG_REG_VALUE) {
>> (*dcd_len)++;
>> + if (*dcd_len > max_dcd_entries) {
>> + fprintf(stderr, "Error: %s[%d] -"
>> + "DCD table exceeds maximum size(%d)\n",
>> + name, lineno, max_dcd_entries);
>> + exit(EXIT_FAILURE);
>> + }
>> + }
>> break;
>> default:
>> break;
>>
> This patch seems to me unrelated to the rest, and fixes the case when
> too much DCD entries are put into the imximage.cfg file. What about to
> rebase it on the current code and post it as separate patch ? I think
> this can be merged directly, also in the current realease.
>
> Best regards,
> Stefano Babic
>
It is a fix, but for a bug that has never happened. So I think it is
very low priority.
But I can reorder the patches so that this is the 1st in the series, in case
the other patches are never accepted.
I don't think it belongs in the current release.
Troy
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 04/21] imximage: cleanup parsing
2012-09-23 11:08 ` Stefano Babic
@ 2012-09-24 20:59 ` Troy Kisky
0 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-09-24 20:59 UTC (permalink / raw)
To: u-boot
On 9/23/2012 4:08 AM, Stefano Babic wrote:
> On 22/09/2012 04:39, Troy Kisky wrote:
>> Move to pulling tokens instead of pushing them.
>> Remove need for switch statements to process commands.
>> Add error messages such as "command not finished",
>> "extra data at end of line", and "invalid token"
>> Add ';' as command separator.
>>
>> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
>> ---
> Hi Troy,
>
> you add code in previous patch and you remove it in this one. This makes
> quite difficult to review them.
>
> Normally, we do do have this case, and code is not added and removed in
> the same patches series. Should you not squash patches together and / or
> rearrange them with different topic ?
>
> Best regards,
> Stefano Babic
>
>
Yes, I should have done this. A lot of time passed between when I added it
and when I removed it, so I forgot that I was the one that added it!
I had finished the series and was debugging before I saw a better way.
Will fix.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 05/21] imximage: add expression evaluation
2012-09-23 14:56 ` Stefano Babic
@ 2012-09-24 21:18 ` Troy Kisky
0 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-09-24 21:18 UTC (permalink / raw)
To: u-boot
On 9/23/2012 7:56 AM, Stefano Babic wrote:
> On 22/09/2012 04:39, Troy Kisky wrote:
>> Basic expressions with order precedence is
>> now supported.
>> ie. (----3 + ((1+2*3)/--2 + --5 *(8/4))) is 16.
>>
>> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
>> ---
> Hi Troy,
>
>> tools/imximage.c | 172 ++++++++++++++++++++++++++++++++++++++++++++++++++----
>> 1 file changed, 162 insertions(+), 10 deletions(-)
>>
>> diff --git a/tools/imximage.c b/tools/imximage.c
>> index 1e120354..2c5a622 100644
> I have some general considerations. First, if you plan to add support
> for expression evaluation, this feature should be available generally
> for mkimage, that means also other processors / architecture can profit
> of it. It should be moved away from imximage.c code.
That makes sense.
>
> Then, you want also let that the preprocesso can parse the imximage
> code. I can imagine that in such terms it could be then possible to
> define in imximage.cfg something like:
>
> #define DDR_VAL (1 <<17 | 3 << 7)
> #define ADDRESS 0x0x53something
>
> DATA 4 ADDRESS DDR_VAL
>
> Else, why do we need the power of C preprocessor ?
>
> If this is true, can you explain us which is the use case using the C
> preprocessor and which is the one for the expression evaluator ? And why
> do we need both ?
>
>
>
I want to easily switch from plugins back to the normal DCD list method.
#ifdef 's and and #define's make this possible.
Plus the cfg file is more readable with #define's.
But if plugins are rejected, expressions aren't as important.
I can still see a cfg file doing
DATA 4, MMDC_P0 + MMDC_MPZQHWCTRL, 0xA1380003
DATA 4, MMDC_P1 + MMDC_MPZQHWCTRL, 0xA1380003
patch 09/21 mx6q_4x_mt41j128.cfg: use symbols instead of hardcoded constants
has
+#define MA(mx6q, mx6dl_solo, mx6sololite) ((mx6q / 4 & 0x3ff) | \
+ ((mx6dl_solo / 4 & 0x3ff) * 0x400) | \
+ ((mx6sololite / 4 & 0x3ff) * 0x100000))
+
+#define IOM_DRAM_DQM0 MA(0x5ac, 0x470, 0x0)
+#define IOMUX_ADDR(addr, div) (IOMUXC_BASE_ADDR + \
+ ((((addr) / (div)) & 0x3ff) * 4))
+#define IOMUX_ENTRY1(addr, q) DATA 4, IOMUX_ADDR(addr, _FOR_DIV), q
+#define WRITE_ENTRY1(addr, q) DATA 4, addr, q
+#ifdef FOR_MX6Q
+#define _FOR_DIV 1
+#define IOMUX_ENTRY2(addr, q, dl) IOMUX_ENTRY1(addr, q)
+#define WRITE_ENTRY2(addr, q, dl) WRITE_ENTRY1(addr, q)
to choose which offset for IOM_DRAM_DQM0 should be selected.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 06/21] imximage: add plugin commands
2012-09-23 15:38 ` Stefano Babic
@ 2012-09-24 21:46 ` Troy Kisky
0 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-09-24 21:46 UTC (permalink / raw)
To: u-boot
On 9/23/2012 8:38 AM, Stefano Babic wrote:
> On 22/09/2012 04:39, Troy Kisky wrote:
>> Add commands
>> plugin address filename
>> iomux_entry addr, data1 [, data2, [, data3]]
>> write_entry addr, data1 [, data2, [, data3]]
> Why do we need explicitely an IOMUX command ? As far as I can see, the
> program image defined in V2 defines a plugin, but not an iomux.
> I am expecting that the imximage generates a iMX header only, without
> moving some code from the initialization code directly here. In the
> manula there is a "Write Data" (what we have always had), a "Check data"
> and an "Unlock" commands.
The table built by iomux_entry and write_entry are not used by the ROM.
The plugin.S file that I add will interpret these entries.
I could have repurposed the "DATA" command if I didn't mind bloating
the table.
Having separate commands made it easy to generate small tables.
>
> If we start to add special commands, maybe we are staring again to
> reimplement U-Boot. We could have some SET_CLK, SET_CPU_FREQ, and so on.
> What I am really mising in this series is why you are moving a lot of
> things from U-Boot into the iMX header.
The cfg file after this patch series does no more setup/initialization
than before
this series. I don't know what "moving" you are referring to.
>
> It seems to me we want to put much more code in the iMX header as what
> it is really required to boot the device.
>
> Adding / modifying the syntax requires to update doc/README.imximage, too.
Yes, if leaning toward acceptance I will add this.
>
>> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
>> ---
>> tools/imximage.c | 334 ++++++++++++++++++++++++++++++++++++++++++++----------
>> tools/imximage.h | 11 +-
>> 2 files changed, 283 insertions(+), 62 deletions(-)
>>
>> diff --git a/tools/imximage.c b/tools/imximage.c
>> index 2c5a622..fae786a 100644
>> --- a/tools/imximage.c
>> +++ b/tools/imximage.c
>> @@ -31,7 +31,6 @@
>> #include "mkimage.h"
>> #include <image.h>
>> #include "imximage.h"
>> -
>> /*
>> * Supported commands for configuration file
>> */
>> @@ -39,6 +38,9 @@ static table_entry_t imximage_cmds[] = {
>> {CMD_BOOT_FROM, "BOOT_FROM", "boot command", },
>> {CMD_DATA, "DATA", "Reg Write Data", },
>> {CMD_IMAGE_VERSION, "IMAGE_VERSION", "image version", },
>> + {CMD_PLUGIN, "plugin", "plugin addr,file", },
>> + {CMD_IOMUX_ENTRY, "iomux_entry", "Write iomux reg", },
>> + {CMD_WRITE_ENTRY, "write_entry", "Write register", },
>> {-1, "", "", },
>> };
>>
>> @@ -69,8 +71,8 @@ static uint32_t imximage_version;
>>
>> static set_dcd_val_t set_dcd_val;
>> static set_imx_hdr_t set_imx_hdr;
>> -static set_imx_size_t set_imx_size;
>> static uint32_t *p_max_dcd;
>> +static uint32_t *header_size_ptr;
>> static uint32_t g_flash_offset;
>>
>> static struct image_type_params imximage_params;
>> @@ -88,8 +90,7 @@ static uint32_t detect_imximage_version(struct imx_header *imx_hdr)
>> return IMXIMAGE_V1;
>>
>> /* Try to detect V2 */
>> - if ((fhdr_v2->header.tag == IVT_HEADER_TAG) &&
>> - (hdr_v2->dcd_table.header.tag == DCD_HEADER_TAG))
>> + if ((fhdr_v2->header.tag == IVT_HEADER_TAG))
>> return IMXIMAGE_V2;
> Help me to understand. I am reading i.MX6 manual and, even if the number
> of DCD entries could be variable, I do not see why the header tag of DCD
> is moving. At least, this is what I can see on picture 7-19, Image
> Vector table.
If the DCD table is missing, there is no DCD_HEADER_TAG.
DCD table is not required, so there is no need to check for it.
>>
>> return IMXIMAGE_VER_INVALID;
>> @@ -160,7 +161,7 @@ static int set_dcd_val_v2(struct imx_header *imxhdr, uint32_t *data)
>> }
>>
>> static int set_imx_hdr_v1(struct imx_header *imxhdr,
>> - uint32_t entry_point, uint32_t flash_offset)
>> + uint32_t entry_point, uint32_t flash_offset, int plugin)
>> {
>> imx_header_v1_t *hdr_v1 = &imxhdr->header.hdr_v1;
>> flash_header_v1_t *fhdr_v1 = &hdr_v1->fhdr;
>> @@ -180,22 +181,12 @@ static int set_imx_hdr_v1(struct imx_header *imxhdr,
>> /* Security feature are not supported */
>> fhdr_v1->app_code_csf = 0;
>> fhdr_v1->super_root_key = 0;
>> + header_size_ptr = (uint32_t *)(((char *)imxhdr) + header_length - 4);
>> return header_length;
>> }
>>
>> -static void set_imx_size_v1(struct imx_header *imxhdr, uint32_t file_size,
>> - uint32_t flash_offset)
>> -{
>> - uint32_t *p = (uint32_t *)(((char *)imxhdr)
>> - + imximage_params.header_size);
>> -
>> - /* The external flash header must be at the end of the DCD table */
>> - /* file_size includes header */
>> - p[-1] = file_size + flash_offset;
>> -}
> I think you have to squash some of your patches or to defines them in
> another way. You added this code previously, and you drop now. This
> makes more difficult to review your patches.
I though this is what you were referring to in patch 4/21 response. So my
agreement there, should have been here. Now I don't know what in 4/21
you were referring to, but I'll reexamine before next version.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 08/21] mx6: add plugin file for use with imximage.cfg
2012-09-23 17:08 ` Stefano Babic
2012-09-23 23:29 ` Eric Nelson
@ 2012-09-24 22:23 ` Troy Kisky
2012-09-25 12:13 ` Stefano Babic
1 sibling, 1 reply; 430+ messages in thread
From: Troy Kisky @ 2012-09-24 22:23 UTC (permalink / raw)
To: u-boot
On 9/23/2012 10:08 AM, Stefano Babic wrote:
> On 23/09/2012 18:23, Eric Nelson wrote:
>> On 09/23/2012 03:17 AM, Stefano Babic wrote:
>>> On 22/09/2012 04:39, Troy Kisky wrote:
>>>> The "plugin" command of mkimage can take this
>>>> file as an argument.
>>>>
>>>> Signed-off-by: Troy Kisky<troy.kisky@boundarydevices.com>
>>>> ---
>>> Hi Troy,
>>>
>>> I agree with Vikram that a better explanation of what a plugin is can
>>> help to understand without reading deeply into the i.MX6 manual.
>>>
>>> So a "plugin" is a chunk of code that can be called directly by the
>>> BootROM of i.MX processors supporting V2 version of the i.MX header.
>>> In my understanding, this is supported by i.MX53, too. After the plugin
>>> run, the control is returned to the BootROM.
>>>
>> Hi Stefano,
>>
>> It seems that there's some general confusion on the list, so I think
>> a little more background and commentary is in order.
> Well, it is - thanks for explanation.
>
>> The primary rationale for plugins is to allow separate link maps in
>> a single image loaded by the BootROM.
>>
>> The idea is to allow first-level code to initialize resources (usually
>> DDR) while running in internal RAM, then return to the boot rom for
>> further image loading (typically into DDR). This prevents the need
>> for the first-level code to support all boot sources (SPI-NOR,
>> NAND, SD card, etc) and allows it to focus on machine setup.
>>
>> The feature is normally needed to allow the first level to access
>> a PMIC. I'm surprised that the 51evk and 53Loco boards aren't
>> using it.
> The mx51 uses a V1 header and the plugin feature is not supported at
> all. So, it can't, simply. The mx53 can, but it is not needed.
> Both boards boot without plugin. So it seem we have a misunderstanding,
> and thanks to raise this issue ;-)
>
> The setup is done by the SOC interpreting the DCD data into the iMX
> header. After this setup, that in any case cannot be very long, the
> control is still taken by the bootROM, that copies data from the media
> device to the DDR according to the values set into the iMX header. Still
> without plugin. After the copy, the bootROM gives the control to U-Boot
> for the rest that starts with the usual initialization.
>
> There is no need to setup the pMIC on mx51evk and mx53qsb to get the DDR
> running. However, even if we need it, we can do it in another way, as I
> will explain now.
>
>> Troy's rationale for using it now is to enable a single image on
>> i.MX6Quad, Dual lite and Solo processors, which have very slight
>> initialization differences. The 6Solo processor has 32-bit DDR
>> bus, so it would otherwise require a separate binary.
>>
>> By doing this in code (plugin), we can introduce a conditional
>> based on processor type and have a single image that will boot
>> on any of the three.
> Ok - but why cannot this check be done directly by U-Boot ?
>
> My understanding is that you want to add a plugin written in assembly to
> allow different setup of the DDR controller. Let's see how we can do
> with standard U-Boot code.
>
> Core of the startup is that the SOC copies itself some code into the
> internal RAM and started. This is done by bootROM, running is own code
> and running the plugin.
>
> We have already this mechanism with the SPL framework. The big advantage
> for this approach is that the same mechanism can be used on SOC of
> different vendors, while the one in this series is a solution strictly
> bound with (some) Freescale's SOC.
>
> The imx header can be still adapted to copy the SPL code into the
> internal RAM. When SPL is running, you have all freedom to check which
> is the CPU running and to adjust your DDR setting, and everything is C
> code. Both MX5 and MX6 have plenty of internal RAM to do this, because
> SPL requires ~30KB.
>
> I think the goal to have the same U-Boot binary can be reached using the
> SPL framework. As you are running U-Boot code, you have the possibility
> to do whatever you want.
>
> So my question is: if the main reason is to have a single image for all
> your iMX6 boards, why cannot we do it in a standard way using SPL ?
>
>> The other key change for these processors is the location of
>> the iomux controller (moved on 6Solo/Duallite from 6Quad).
>>
>> 6Solo has 32-bit DDR and iomux controller moved from 6Q
>> 6Duallite has 64-bit DDR but same iomux location as 6Q
>>
>> Note that this highlights a slight down side to the plugin approach.
>>
>> Because of the movement of the iomux controller, we can't use
>> a universal i.MX6 image header to write any IOMUX registers
>> through imximage.cfg.
> However, you can do it with this approach:
>
> - you have a general imx header, that does not write into IOMUX
> It is your choice if this should set the DDR or not. You could also
> decide to have an empty DCD table.
> - your imx Header is generated for your SPL code, and the destination
> address for the SPL code is put into internal RAM
> - the bootROM will start reading the iMX header and DCD data and copies
> data from media (NAND, SPI, ..) into iRAM. There is no need for any
> special setup because the iRAM is always available. Then it gives the
> control to the SPL.
> - the SPL starts and performs the setup of the DDR, checking the SOC if
> it is required. The usual SOC initialization is done here.
> - At the end, the SPL loads from media the U-Boot or directly the kernel
> and starts it. Or whatever image you want.
>
> The further advantage we can have with this approach is that we can
> profit for further development in u-boot. What I mean really is using
> TPL, that means putting u-boot into a UBL volume, see:
>
> http://lists.celinuxforum.org/pipermail/celinux-dev/2012-April/000543.html
>
> I know there is not yet activity on this topic, but it does not mean we
> have not in future.
>
> Best regards,
> Stefano Babic
>
The advantages of a plugin over spl are
1. smaller code 0x190 bytes, plus the table.
relying on the ROM to do the heavy lifting.
2. support all boot modes that the ROM does.
NOR/NAND/ONENAND/MMC/eMMC
Hard Disk and SSD devices using SATA
Serial ROM through SPI/I2C
3. Easy to switch back to previous DCD tables
for debugging or permanently. I can see that many
people will never use either plugin or SPL and will stick
with the current method, or have separate cfg
files for each processor type. I could still have
the separate cfg files #include a common file.
ie
#define FOR_MX6Q
#include "imx-common.cfg"
------------
#define FOR_MX6DL
#include "imx-common.cfg"
4. plugin method is already working.
Let me know which features might make it to mainline
1. variable length headers
2. parsing of cfg to pull the file, instead of push
3. C preprocessor
4. expression evaluation.
5 plugins
and I'll post a new series.
Thanks
Troy
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 01/21] imximage: make header variable length
2012-09-24 20:30 ` Troy Kisky
@ 2012-09-25 11:08 ` Stefano Babic
0 siblings, 0 replies; 430+ messages in thread
From: Stefano Babic @ 2012-09-25 11:08 UTC (permalink / raw)
To: u-boot
On 24/09/2012 22:30, Troy Kisky wrote:
> On 9/23/2012 3:57 AM, Stefano Babic wrote:
>> On 22/09/2012 04:38, Troy Kisky wrote:
>>
Hi Troy,
>>> Also, the header offset is no longer
>>> right before the code starts.
>> Comment and subject of the patch do not match. Can you better explain it
>> ? What have "making header variable length", that is, a new feature,
>> with " the header offset is no longer rigth", that is, a bug ?
>>
>> Do we already have a variable header the we add a vrec_header function
>> to image_type_params ?
> Before this patch we have
> 000000 402000d1 17800000 00000000 177ffc2c
> 000010 177ffc20 177ffc00 00000000 00000000
> 000020 177ff800 00042b58 00000000 402803d2
> 000030 042403cc a8050e02 30000000 b0050e02
> ... more DCD table
> 000340 cf0000f0 18000e02 7f007f00 1c000e02
> 000350 7f007f00 00000000 00000000 00000000
> 000360 00000000 00000000 00000000 00000000
> *
> 0003f0 00000000 00000000 00000000 00000400
> 000400 ea000014 e59ff014 e59ff014 e59ff014
>
>
> Notice offset 3fc contains 0x400. This
> is the header offset. There is no reason
> for this to be in the file, and I have
> removed it.
Right - I do not know anymore the reason why it was explicitely set. It
is not useful and not required by the SOC, no reason to have it, agree.
>
>
> After this patch we have
> 000000 402000d1 17800000 00000000 177ffcd8
> 000010 177ffccc 177ffcac 00000000 00000000
> 000020 177ff8ac 000426ac 00000000 402803d2
> 000030 042403cc a8050e02 30000000 b0050e02
> ... more DCD table
> 000340 cf0000f0 18000e02 7f007f00 1c000e02
> 000350 7f007f00 ea000014 e59ff014 e59ff014
> 000360 e59ff014 e59ff014 e59ff014 e59ff014
>
> Notice the zeros between 0x354 and 0x3fb have
> been removed. That is what I mean by making it
> a variable length header.
Ok - I understan that the whole header have a different lenght, but
really it is the DCD table that has now a variable length. Please change
commit header and comment to explain it. Feel free to add this example
>
>>> Series tested on an mx51 and mx6q
>>> ---
>>> tools/imximage.c | 142
>>> +++++++++++++++++++++++++++++++-----------------------
>>> tools/imximage.h | 10 ++--
>>> 2 files changed, 87 insertions(+), 65 deletions(-)
>>>
>>> diff --git a/tools/imximage.c b/tools/imximage.c
>>> index 03a7716..25d3b74 100644
>>> --- a/tools/imximage.c
>>> +++ b/tools/imximage.c
>>> @@ -65,12 +65,15 @@ static table_entry_t imximage_versions[] = {
>>> {-1, "", " (Invalid)", },
>>> };
>>> -static struct imx_header imximage_header;
>>> static uint32_t imximage_version;
>>> static set_dcd_val_t set_dcd_val;
>>> static set_dcd_rst_t set_dcd_rst;
>>> static set_imx_hdr_t set_imx_hdr;
>>> +static set_imx_size_t set_imx_size;
>>> +static uint32_t g_flash_offset;
>>> +
>>> +static struct image_type_params imximage_params;
>>> static uint32_t get_cfg_value(char *token, char *name, int linenr)
>>> {
>>> @@ -207,85 +210,79 @@ static void set_dcd_rst_v2(struct imx_header
>>> *imxhdr, uint32_t dcd_len,
>>> dcd_v2->write_dcd_command.param = DCD_COMMAND_PARAM;
>>> }
>>> -static void set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t
>>> dcd_len,
>>> - struct stat *sbuf,
>>> - struct mkimage_params *params)
>>> +static int set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,
>>> + uint32_t entry_point, uint32_t flash_offset)
>>> {
>>> imx_header_v1_t *hdr_v1 = &imxhdr->header.hdr_v1;
>>> flash_header_v1_t *fhdr_v1 = &hdr_v1->fhdr;
>>> dcd_v1_t *dcd_v1 = &hdr_v1->dcd_table;
>>> - uint32_t base_offset;
>>> -
>>> - /* Exit if there is no BOOT_FROM field specifying the
>>> flash_offset */
>>> - if(imxhdr->flash_offset == FLASH_OFFSET_UNDEFINED) {
>>> - fprintf(stderr, "Error: Header v1: No BOOT_FROM tag in %s\n",
>>> - params->imagename);
>>> - exit(EXIT_FAILURE);
>>> - }
>> Do you drop BOOT_FROM ? Then this should be documented. Is this to allow
>> that the same image can be loaded from different media, that share the
>> same flash offset ? Then, instead of drop it, I suggest to add more
>> entries in the imximage file, one for each media that is allow.
>
> No I did not drop the BOOT_FROM command. I merely moved this check before
> the function call, as it was common to both set_imx_hdr_v1 and
> set_imx_hdr_v2
>
> I can make it a separate patch to make it obvious.
Yes, please.
>>
>> Something like:
>> BOOT_FROM sd, nand, spi
>>
>> and maybe a check in the code if all entries do not share the same start
>> address.
>>
>>> + uint32_t hdr_base;
>>> + uint32_t header_length = (((char
>>> *)&dcd_v1->addr_data[dcd_len].addr)
>>> + - ((char *)imxhdr));
>>>
>> For V1, the header is preallocated with the maximum size, that is the
>> maximum number of DCD entries the SOC in V1 can support. Why do we need
>> a dynamic length for V1 processors ? As far as I know, the number of
>> entries and fields for theses SOCs (i.MX25, i.MX35, i.MX51) is fixed.
>
> You right the DCD table maximum size is fixed. But why should we be
> forced to use
> the maximum size? Why make V1 headers a special case?
No, it should not be - I want only be sure that changes are clear
enough. It is absolutely ok that there is no padding after the DCD
table. What I see, you fix several different issues with this single
patch, and this can make confusion. Split into several patches or at
least add a complete and exhaurient commit message.
>>> /* Set magic number */
>>> fhdr_v1->app_code_barker = APP_CODE_BARKER;
>>> - fhdr_v1->app_dest_ptr = params->addr;
>>> - fhdr_v1->app_dest_ptr = params->ep - imxhdr->flash_offset -
>>> - sizeof(struct imx_header);
>>> - fhdr_v1->app_code_jump_vector = params->ep;
>>> + hdr_base = entry_point - header_length;
>>> + fhdr_v1->app_dest_ptr = hdr_base - flash_offset;
>>> + fhdr_v1->app_code_jump_vector = entry_point;
>>> - base_offset = fhdr_v1->app_dest_ptr + imxhdr->flash_offset ;
>>> - fhdr_v1->dcd_ptr_ptr =
>>> - (uint32_t) (offsetof(flash_header_v1_t, dcd_ptr) -
>>> - offsetof(flash_header_v1_t, app_code_jump_vector) +
>>> - base_offset);
>>> -
>>> - fhdr_v1->dcd_ptr = base_offset +
>>> - offsetof(imx_header_v1_t, dcd_table);
>>> -
>>> - /* The external flash header must be at the end of the DCD table */
>>> - dcd_v1->addr_data[dcd_len].type = sbuf->st_size +
>>> - imxhdr->flash_offset +
>>> - sizeof(struct imx_header);
>>> + fhdr_v1->dcd_ptr_ptr = hdr_base + offsetof(flash_header_v1_t,
>>> dcd_ptr);
>>> + fhdr_v1->dcd_ptr = hdr_base + offsetof(imx_header_v1_t, dcd_table);
>>> /* Security feature are not supported */
>>> fhdr_v1->app_code_csf = 0;
>>> fhdr_v1->super_root_key = 0;
>>> + return header_length;
>>> +}
>>> +
>> Ok, I skip review of this part - it depends on your answer on the
>> previous question.
>>
>>> -static void set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t
>>> dcd_len,
>>> - struct stat *sbuf,
>>> - struct mkimage_params *params)
>>> +static int set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t dcd_len,
>>> + uint32_t entry_point, uint32_t flash_offset)
>>> {
>>> imx_header_v2_t *hdr_v2 = &imxhdr->header.hdr_v2;
>>> flash_header_v2_t *fhdr_v2 = &hdr_v2->fhdr;
>>> -
>>> - /* Exit if there is no BOOT_FROM field specifying the
>>> flash_offset */
>>> - if(imxhdr->flash_offset == FLASH_OFFSET_UNDEFINED) {
>>> - fprintf(stderr, "Error: Header v2: No BOOT_FROM tag in %s\n",
>>> - params->imagename);
>>> - exit(EXIT_FAILURE);
>>> - }
>>> + uint32_t hdr_base;
>>> + uint32_t header_length = (dcd_len) ?
>>> + (char *)&hdr_v2->dcd_table.addr_data[dcd_len] - ((char*)imxhdr)
>>> + : offsetof(imx_header_v2_t, dcd_table);
>> So you add a case where there is no DCD table at all. Apart that this
>> van be a use case, but does it happen in the real life ?
>
> Yes, after this patch series, sabrelite with use a plugin with no DCD
> table at all.
> Even your SPL route could use no DCD table.
Ok - then this is also a bug fix. The SOCs support an empty DCD table,
and the current imximage does not. Add also this fix in the commit
message, or move it into a separate patch if you can.
>
>>
>>> + if (g_flash_offset == -1) {
>>> fprintf(stderr, "Error: %s[%d] -Invalid boot device"
>>> "(%s)\n", name, lineno, token);
>>> exit(EXIT_FAILURE);
>>> @@ -521,12 +520,17 @@ static void imximage_print_header(const void *ptr)
>>> }
>>> }
>>> -static void imximage_set_header(void *ptr, struct stat *sbuf, int
>>> ifd,
>>> - struct mkimage_params *params)
>>> +int imximage_vrec_header(struct mkimage_params *params,
>>> + struct image_type_params *tparams)
>>> {
>>> - struct imx_header *imxhdr = (struct imx_header *)ptr;
>>> + struct imx_header *imxhdr;
>>> uint32_t dcd_len;
>>> + imxhdr = calloc(1, MAX_HEADER_SIZE);
>>> + if (!imxhdr) {
>>> + fprintf(stderr, "Error: out of memory\n");
>>> + exit(EXIT_FAILURE);
>>> + }
>>> /*
>>> * In order to not change the old imx cfg file
>>> * by adding VERSION command into it, here need
>>> @@ -534,14 +538,31 @@ static void imximage_set_header(void *ptr,
>>> struct stat *sbuf, int ifd,
>>> */
>>> imximage_version = IMXIMAGE_V1;
>>> /* Be able to detect if the cfg file has no BOOT_FROM tag */
>>> - imxhdr->flash_offset = FLASH_OFFSET_UNDEFINED;
>>> + g_flash_offset = FLASH_OFFSET_UNDEFINED;
>>> set_hdr_func(imxhdr);
>>> /* Parse dcd configuration file */
>>> dcd_len = parse_cfg_file(imxhdr, params->imagename);
>>> + /* Exit if there is no BOOT_FROM field specifying the
>>> flash_offset */
>>> + if (g_flash_offset == FLASH_OFFSET_UNDEFINED) {
>>> + fprintf(stderr, "Error: No BOOT_FROM tag in %s\n",
>>> + params->imagename);
>>> + exit(EXIT_FAILURE);
>>> + }
>>> /* Set the imx header */
>>> - (*set_imx_hdr)(imxhdr, dcd_len, sbuf, params);
>>> + imximage_params.header_size = (*set_imx_hdr)(imxhdr, dcd_len,
>>> + params->ep, g_flash_offset);
>>> + imximage_params.hdr = imxhdr;
>>> + return 0;
>>> +}
>>> +
>>> +static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd,
>>> + struct mkimage_params *params)
>>> +{
>>> + /* Set the size in header */
>>> + (*set_imx_size)((struct imx_header *)ptr, sbuf->st_size,
>>> + g_flash_offset);
>>> }
>>> int imximage_check_params(struct mkimage_params *params)
>>> @@ -571,8 +592,9 @@ int imximage_check_params(struct mkimage_params
>>> *params)
>>> */
>>> static struct image_type_params imximage_params = {
>>> .name = "Freescale i.MX 5x Boot Image support",
>>> - .header_size = sizeof(struct imx_header),
>>> - .hdr = (void *)&imximage_header,
>>> + .header_size = 0,
>>> + .hdr = NULL,
>>> + .vrec_header = imximage_vrec_header,
>>> .check_image_type = imximage_check_image_types,
>>> .verify_header = imximage_verify_header,
>>> .print_header = imximage_print_header,
>>> diff --git a/tools/imximage.h b/tools/imximage.h
>>> index 34f293d..5fe3a8a 100644
>>
>>> --- a/tools/imximage.h
>>> +++ b/tools/imximage.h
>>> @@ -30,6 +30,7 @@
>>> #define DCD_BARKER 0xB17219E9
>>> #define HEADER_OFFSET 0x400
>>> +#define MAX_HEADER_SIZE (16 << 10)
>>> #define CMD_DATA_STR "DATA"
>>> #define FLASH_OFFSET_UNDEFINED 0xFFFFFFFF
>>> @@ -156,7 +157,6 @@ struct imx_header {
>>> imx_header_v1_t hdr_v1;
>>> imx_header_v2_t hdr_v2;
>>> } header;
>>> - uint32_t flash_offset;
>>> };
>>> typedef void (*set_dcd_val_t)(struct imx_header *imxhdr,
>>> @@ -168,9 +168,9 @@ typedef void (*set_dcd_rst_t)(struct imx_header
>>> *imxhdr,
>>> uint32_t dcd_len,
>>> char *name, int lineno);
>>> -typedef void (*set_imx_hdr_t)(struct imx_header *imxhdr,
>>> - uint32_t dcd_len,
>>> - struct stat *sbuf,
>>> - struct mkimage_params *params);
>>> +typedef int (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t
>>> dcd_len,
>>> + uint32_t entry_point, uint32_t flash_offset);
>>> +typedef void (*set_imx_size_t)(struct imx_header *imxhdr, uint32_t
>>> file_size,
>>> + uint32_t flash_offset);
>> I disagree here. mkimage is valid for all architecture, we must not have
>> special entries here for a SOC or SOC family. For all other SOCs, DCD,
>> iMX header have no sense.
>> Anyway, why do you need to add set_imx_size_t when you call it only in
>> imximage.c ?
>
> I think you misread the file name. This is imximage.h.
Sorry, my fault here.
> But I will squash the removal of set_imx_size_t done in a later
> patch with this one to make it easier to review.
>
>>
>>> #endif /* _IMXIMAGE_H_ */
>> You should split changes in image.h, that are valid for all
>> architecture, from changes to imximage.c, that are only for i.MX, into
>> different patches.
>>
>> In my understanding you add additional entry points to have a variable
>> header lenght, but this feature is already used on TI with the AIS
>> image. You use also vrec_header. What am I missing here ?
>
> I did not change image.h at all.
That is fine, then.
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 02/21] imximage: check dcd_len as entries added
2012-09-24 20:54 ` Troy Kisky
@ 2012-09-25 11:12 ` Stefano Babic
0 siblings, 0 replies; 430+ messages in thread
From: Stefano Babic @ 2012-09-25 11:12 UTC (permalink / raw)
To: u-boot
On 24/09/2012 22:54, Troy Kisky wrote:
> It is a fix, but for a bug that has never happened.
Right, but anyway it is a fix ;-)
> So I think it is
> very low priority.
> But I can reorder the patches so that this is the 1st in the series, in
> case
> the other patches are never accepted.
The reason is that simply and easy patches could be merged soon.
> I don't think it belongs in the current release.
Right, this should go in -next
Best regards,
Stefano
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 08/21] mx6: add plugin file for use with imximage.cfg
2012-09-24 20:46 ` Troy Kisky
@ 2012-09-25 11:57 ` Stefano Babic
0 siblings, 0 replies; 430+ messages in thread
From: Stefano Babic @ 2012-09-25 11:57 UTC (permalink / raw)
To: u-boot
On 24/09/2012 22:46, Troy Kisky wrote:
> On 9/23/2012 3:17 AM, Stefano Babic wrote:
>> On 22/09/2012 04:39, Troy Kisky wrote:
>>> The "plugin" command of mkimage can take this
>>> file as an argument.
>>>
>>> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
>>> ---
Hi Troy,
>>
>> I agree with Vikram that a better explanation of what a plugin is can
>> help to understand without reading deeply into the i.MX6 manual.
>>
>> So a "plugin" is a chunk of code that can be called directly by the
>> BootROM of i.MX processors supporting V2 version of the i.MX header.
>> In my understanding, this is supported by i.MX53, too. After the plugin
>> run, the control is returned to the BootROM.
>>
>> Now that we have some basis, why do we need this mechanism to boot this
>> board ? Is it not possible to make the same initialization directly in
>> u-boot ?
>>
>> In principle, this adds stil some code that is not so easy to maintain.
>
> I can add to README.imximage. But I'm beginning to doubt if plugins are
> going
> to be accepted at all.
I have several doubts about using the plugin. First at all, this make
the development of new iMX completely different as the rest of U-boot.
Plugin ist a feature so strictly bounded to the Freescale's iMX. The
risk here is that U-Boot imx diverges from the other SOCs, while we are
currently in a phase where we want to uniform as much as possible the
behavior with different architectures.
I am also not convinced why introducing the plugin is strictly required.
Reading Eric's answer, I get that costs for having and maintaing a
single image U-boot for different boards overcomes the benefits, and I
fully agree with him. But reading your patch and from your explanation
of plugin code, I understand that the plugin is used to detect which CPU
is running, and then to set differently registers, because offsets are
different. So the goal is again to have a single image.
>>> +
>>> +1: movs r0, r1, LSR #30
>>> + beq 2f
>>> + mov r1, r1, LSL rCPU
>>> + movs r1, r1, LSR #32-10
>>> + addne r1, rIomux, r1, LSL #2
>>> + cmp r0, #3
>>> + subne r0, r0, #1
>>> + orr r1, r1, r0
>>> +
>> The reason is to write GPR12 ? But why do we need a plugin for that ? I
>> do not understand why we cannot do it in the initialization code of the
>> SOC, as we usually do.
>
> This is not GPR12. The address value from the cfg file is actually 3
> addresses. One for
> mx6q, one for mx6 duallite/solo, one for mx6 sololite. Each is specified
> as a 10 bit
> field which we use as a 12 bit offset within IOMUXC_BASE_ADDR (A0/A1
> forced to 0).
Ok, thanks for explanation - I had not understood before.
>>> @@ -48,6 +48,7 @@
>>> #define GLOBAL_TIMER_BASE_ADDR 0x00A00200
>>> #define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600
>>> #define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000
>>> +#define L2_BASE_ADDR 0x00A02000
>>> #define GPV0_BASE_ADDR 0x00B00000
>>> #define GPV1_BASE_ADDR 0x00C00000
>>> #define PCIE_ARB_BASE_ADDR 0x01000000
>>>
>> This is useful in any case. I suggest you put this define in a separate
>> patch, that can flow independently into mainline.
> Hmm, do you suggest moving the L2 disable code to another spot as well ?
Easier - I suggest you put this define in a separate patch, because it
can be accessed by other U-Boot code as well.
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V2 08/21] mx6: add plugin file for use with imximage.cfg
2012-09-24 22:23 ` Troy Kisky
@ 2012-09-25 12:13 ` Stefano Babic
0 siblings, 0 replies; 430+ messages in thread
From: Stefano Babic @ 2012-09-25 12:13 UTC (permalink / raw)
To: u-boot
On 25/09/2012 00:23, Troy Kisky wrote:
> The advantages of a plugin over spl are
> 1. smaller code 0x190 bytes, plus the table.
> relying on the ROM to do the heavy lifting.
This is true. However, as you are writing in the next line, the bootROM
boots from devices having much more space as some bytes. Even on small
SPI-NOR (the smallest device I used with MX5), this was not an issue.
On the other side, you cannot influence the behavior of the bootROM, and
much more job is let to the bootROM, less possibilities to fix some
things. SPL is part of U-Boot, all sources are availbale and it is
easier to fix.
>
> 2. support all boot modes that the ROM does.
> NOR/NAND/ONENAND/MMC/eMMC
> Hard Disk and SSD devices using SATA
> Serial ROM through SPI/I2C
I do not know about booting from SATA, if a plugin is a must - but this
means that it fixes a problem in the bootROM.
Apart of that, there are no hardware limitation that avoi to use SPL
with these media devices.
> 3. Easy to switch back to previous DCD tables
> for debugging or permanently. I can see that many
> people will never use either plugin or SPL
I think you are talking specifically about mainlined i.MX boards. This
is correct, because patches to make SPL available will be merged now.
But if we see U-Boot in its globality, quite all TI's boards have a SPL.
> and will stick
> with the current method, or have separate cfg
> files for each processor type. I could still have
> the separate cfg files #include a common file.
> ie
> #define FOR_MX6Q
> #include "imx-common.cfg"
Using common file is a practice we should improve, definitely. But it
has nothing to do with plugin. Agree that similar boards and / or SOCs
should better share code.
> ------------
> #define FOR_MX6DL
> #include "imx-common.cfg"
>
> 4. plugin method is already working.
ok, this is right
> Let me know which features might make it to mainline
> 1. variable length headers
Absolutely yes !
> 2. parsing of cfg to pull the file, instead of push
> 3. C preprocessor
Yes, I agree with you that it is useful. As you said, using #define make
it more readable.
> 4. expression evaluation.
As you posted previously, this depends on plugin.
> 5 plugins
Currently, I do not see that plugin is strictly required and can move
iMX away from the rest of U-Boot development.
>
> and I'll post a new series.
Ok, thanks.
Best regards,
Stefano
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 00/32] Add mx6solo/mx6duallite support
2012-09-22 2:38 ` [U-Boot] [PATCH V2 00/21] Add mx6solo/mx6duallite support Troy Kisky
` (21 preceding siblings ...)
2012-09-22 6:21 ` [U-Boot] [PATCH V2 00/21] Add mx6solo/mx6duallite support Dirk Behme
@ 2012-10-04 1:47 ` Troy Kisky
2012-10-04 1:47 ` [U-Boot] [PATCH V3 01/32] imximage: check dcd_len as entries added Troy Kisky
` (34 more replies)
22 siblings, 35 replies; 430+ messages in thread
From: Troy Kisky @ 2012-10-04 1:47 UTC (permalink / raw)
To: u-boot
This series goal is to add support for mx6solo and mx6duallite
variants of mx6qsabrelite board. The new targets are
called mx6ssabrelite and mx6dlsabrelite.
The 1st 16 patches perform cleanup on imximage
The final 2 patches add support for expressions to mkimage.
If found not to be worth the effort, they can be omitted.
Troy Kisky (32):
imximage: check dcd_len as entries added
imximage: remove redundant setting of app_dest_ptr
imximage: move flash_offset check to common location
imximage: fix size of image to load.
imximage: delay setting of image size
imximage: change parameters to set_imx_hdr
imximage: make set_imx_hdr_v1/v2 easier to read
imximage: make header variable length
imximage: remove static imximage_version
imximage: prepare to move static variables to struct data_src
imximage: change parameters for set_dcd_val/set_imx_hdr
imximage: move set_imx_hdr to struct data_src
imximage: move set_dcd_val to struct data_src
imximage: enable word writes for version2 header
tools: add parse_helper file
imximage: use parse_helper functions
imximage.cfg: run files through C preprocessor
mx6q_4x_mt41j128.cfg: use symbols instead of hardcoded constants
mx6q_4x_mt41j128.cfg: add comments
mx6q_4x_mt41j128.cfg: use ddr3 mode for reset
mx6q_4x_mt41j128.cfg: skip initiailizing non-existent memory
mx6q_4x_mt41j128.cfg: force ZQ calibration
mx6: soc: update get_cpu_rev and get_imx_type for mx6solo/sololite
mx6: use CONFIG_MX6 instead of CONFIG_MX6Q
imx-common: cpu: add imx_ddr_size
arch-mx6: add mx6dl_pins.h
mx6qsabrelite: add support for mx6 solo/duallite
mx6q_4x_mt41j128.cfg: add mx6 solo/duallite support
Add boards for sabrelite variants mx6s(solo) and mx6dl(duallite)
mx6qsabrelite: change CONFIG_SYS_PROMPT
parse_helper: add expression evaluation
imx-mkimage.h: use base + offset syntax
Makefile | 3 +-
arch/arm/cpu/armv7/mx6/soc.c | 32 +-
arch/arm/imx-common/cpu.c | 66 +++-
arch/arm/include/asm/arch-mx5/sys_proto.h | 10 +-
arch/arm/include/asm/arch-mx6/imx-mkimage.h | 133 +++++++
arch/arm/include/asm/arch-mx6/imx-regs.h | 2 +
arch/arm/include/asm/arch-mx6/mx6dl_pins.h | 118 ++++++
arch/arm/include/asm/arch-mx6/sys_proto.h | 10 +-
board/esg/ima3-mx53/imximage.cfg | 120 +++---
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 425 ++++++++++++---------
board/freescale/mx25pdk/imximage.cfg | 77 ++--
board/freescale/mx51evk/imximage.cfg | 114 +++---
board/freescale/mx53ard/imximage_dd3.cfg | 83 +++--
board/freescale/mx53evk/imximage.cfg | 86 ++---
board/freescale/mx53loco/imximage.cfg | 83 +++--
board/freescale/mx53smd/imximage.cfg | 83 +++--
board/freescale/mx6qarm2/imximage.cfg | 88 ++---
board/freescale/mx6qsabrelite/mx6qsabrelite.c | 235 +++---------
board/freescale/mx6qsabrelite/pads.h | 172 +++++++++
board/genesi/mx51_efikamx/imximage_mx.cfg | 132 +++----
board/genesi/mx51_efikamx/imximage_sb.cfg | 126 ++++---
board/ttcontrol/vision2/imximage_hynix.cfg | 295 ++++++++-------
boards.cfg | 4 +-
drivers/gpio/mxc_gpio.c | 6 +-
drivers/video/ipu_regs.h | 2 +-
include/configs/mx6qarm2.h | 1 +
include/configs/mx6qsabre_common.h | 1 +
include/configs/mx6qsabrelite.h | 4 +-
tools/Makefile | 2 +
tools/imximage.c | 487 ++++++++++---------------
tools/imximage.h | 39 +-
tools/parse_helper.c | 325 +++++++++++++++++
tools/parse_helper.h | 28 ++
33 files changed, 2106 insertions(+), 1286 deletions(-)
create mode 100644 arch/arm/include/asm/arch-mx6/imx-mkimage.h
create mode 100644 arch/arm/include/asm/arch-mx6/mx6dl_pins.h
create mode 100644 board/freescale/mx6qsabrelite/pads.h
create mode 100644 tools/parse_helper.c
create mode 100644 tools/parse_helper.h
--
1.7.9.5
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 01/32] imximage: check dcd_len as entries added
2012-10-04 1:47 ` [U-Boot] [PATCH V3 00/32] " Troy Kisky
@ 2012-10-04 1:47 ` Troy Kisky
2012-10-20 15:45 ` Stefano Babic
2012-10-04 1:47 ` [U-Boot] [PATCH V3 02/32] imximage: remove redundant setting of app_dest_ptr Troy Kisky
` (33 subsequent siblings)
34 siblings, 1 reply; 430+ messages in thread
From: Troy Kisky @ 2012-10-04 1:47 UTC (permalink / raw)
To: u-boot
Before the len was checked after the entire file
was processed, so it could have already overflowed.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
v3 changed to the 1st patch of the series
---
tools/imximage.c | 26 +++++++++++---------------
1 file changed, 11 insertions(+), 15 deletions(-)
diff --git a/tools/imximage.c b/tools/imximage.c
index 03a7716..c917036 100644
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -71,6 +71,7 @@ static uint32_t imximage_version;
static set_dcd_val_t set_dcd_val;
static set_dcd_rst_t set_dcd_rst;
static set_imx_hdr_t set_imx_hdr;
+static uint32_t max_dcd_entries;
static uint32_t get_cfg_value(char *token, char *name, int linenr)
{
@@ -170,13 +171,6 @@ static void set_dcd_rst_v1(struct imx_header *imxhdr, uint32_t dcd_len,
{
dcd_v1_t *dcd_v1 = &imxhdr->header.hdr_v1.dcd_table;
- if (dcd_len > MAX_HW_CFG_SIZE_V1) {
- fprintf(stderr, "Error: %s[%d] -"
- "DCD table exceeds maximum size(%d)\n",
- name, lineno, MAX_HW_CFG_SIZE_V1);
- exit(EXIT_FAILURE);
- }
-
dcd_v1->preamble.barker = DCD_BARKER;
dcd_v1->preamble.length = dcd_len * sizeof(dcd_type_addr_data_t);
}
@@ -190,13 +184,6 @@ static void set_dcd_rst_v2(struct imx_header *imxhdr, uint32_t dcd_len,
{
dcd_v2_t *dcd_v2 = &imxhdr->header.hdr_v2.dcd_table;
- if (dcd_len > MAX_HW_CFG_SIZE_V2) {
- fprintf(stderr, "Error: %s[%d] -"
- "DCD table exceeds maximum size(%d)\n",
- name, lineno, MAX_HW_CFG_SIZE_V2);
- exit(EXIT_FAILURE);
- }
-
dcd_v2->header.tag = DCD_HEADER_TAG;
dcd_v2->header.length = cpu_to_be16(
dcd_len * sizeof(dcd_addr_data_t) + 8);
@@ -295,11 +282,13 @@ static void set_hdr_func(struct imx_header *imxhdr)
set_dcd_val = set_dcd_val_v1;
set_dcd_rst = set_dcd_rst_v1;
set_imx_hdr = set_imx_hdr_v1;
+ max_dcd_entries = MAX_HW_CFG_SIZE_V1;
break;
case IMXIMAGE_V2:
set_dcd_val = set_dcd_val_v2;
set_dcd_rst = set_dcd_rst_v2;
set_imx_hdr = set_imx_hdr_v2;
+ max_dcd_entries = MAX_HW_CFG_SIZE_V2;
break;
default:
err_imximage_version(imximage_version);
@@ -426,8 +415,15 @@ static void parse_cfg_fld(struct imx_header *imxhdr, int32_t *cmd,
value = get_cfg_value(token, name, lineno);
(*set_dcd_val)(imxhdr, name, lineno, fld, value, *dcd_len);
- if (fld == CFG_REG_VALUE)
+ if (fld == CFG_REG_VALUE) {
(*dcd_len)++;
+ if (*dcd_len > max_dcd_entries) {
+ fprintf(stderr, "Error: %s[%d] -"
+ "DCD table exceeds maximum size(%d)\n",
+ name, lineno, max_dcd_entries);
+ exit(EXIT_FAILURE);
+ }
+ }
break;
default:
break;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 02/32] imximage: remove redundant setting of app_dest_ptr
2012-10-04 1:47 ` [U-Boot] [PATCH V3 00/32] " Troy Kisky
2012-10-04 1:47 ` [U-Boot] [PATCH V3 01/32] imximage: check dcd_len as entries added Troy Kisky
@ 2012-10-04 1:47 ` Troy Kisky
2012-10-08 13:17 ` Stefano Babic
2012-10-20 15:46 ` Stefano Babic
2012-10-04 1:47 ` [U-Boot] [PATCH V3 03/32] imximage: move flash_offset check to common location Troy Kisky
` (32 subsequent siblings)
34 siblings, 2 replies; 430+ messages in thread
From: Troy Kisky @ 2012-10-04 1:47 UTC (permalink / raw)
To: u-boot
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
v3: split into its own patch
---
tools/imximage.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/tools/imximage.c b/tools/imximage.c
index c917036..bda1a75 100644
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -213,7 +213,6 @@ static void set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,
/* Set magic number */
fhdr_v1->app_code_barker = APP_CODE_BARKER;
- fhdr_v1->app_dest_ptr = params->addr;
fhdr_v1->app_dest_ptr = params->ep - imxhdr->flash_offset -
sizeof(struct imx_header);
fhdr_v1->app_code_jump_vector = params->ep;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 03/32] imximage: move flash_offset check to common location
2012-10-04 1:47 ` [U-Boot] [PATCH V3 00/32] " Troy Kisky
2012-10-04 1:47 ` [U-Boot] [PATCH V3 01/32] imximage: check dcd_len as entries added Troy Kisky
2012-10-04 1:47 ` [U-Boot] [PATCH V3 02/32] imximage: remove redundant setting of app_dest_ptr Troy Kisky
@ 2012-10-04 1:47 ` Troy Kisky
2012-10-08 13:19 ` Stefano Babic
2012-10-20 15:46 ` Stefano Babic
2012-10-04 1:47 ` [U-Boot] [PATCH V3 04/32] imximage: fix size of image to load Troy Kisky
` (31 subsequent siblings)
34 siblings, 2 replies; 430+ messages in thread
From: Troy Kisky @ 2012-10-04 1:47 UTC (permalink / raw)
To: u-boot
Both set_imx_hdr_v1 and set_imx_hdr_v2 perform the
same check. Move check to before the set_imx_hdr call.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
v3: split into its own patch
---
tools/imximage.c | 19 +++++--------------
1 file changed, 5 insertions(+), 14 deletions(-)
diff --git a/tools/imximage.c b/tools/imximage.c
index bda1a75..3e9ee6a 100644
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -203,13 +203,6 @@ static void set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,
dcd_v1_t *dcd_v1 = &hdr_v1->dcd_table;
uint32_t base_offset;
- /* Exit if there is no BOOT_FROM field specifying the flash_offset */
- if(imxhdr->flash_offset == FLASH_OFFSET_UNDEFINED) {
- fprintf(stderr, "Error: Header v1: No BOOT_FROM tag in %s\n",
- params->imagename);
- exit(EXIT_FAILURE);
- }
-
/* Set magic number */
fhdr_v1->app_code_barker = APP_CODE_BARKER;
@@ -243,13 +236,6 @@ static void set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t dcd_len,
imx_header_v2_t *hdr_v2 = &imxhdr->header.hdr_v2;
flash_header_v2_t *fhdr_v2 = &hdr_v2->fhdr;
- /* Exit if there is no BOOT_FROM field specifying the flash_offset */
- if(imxhdr->flash_offset == FLASH_OFFSET_UNDEFINED) {
- fprintf(stderr, "Error: Header v2: No BOOT_FROM tag in %s\n",
- params->imagename);
- exit(EXIT_FAILURE);
- }
-
/* Set magic number */
fhdr_v2->header.tag = IVT_HEADER_TAG; /* 0xD1 */
fhdr_v2->header.length = cpu_to_be16(sizeof(flash_header_v2_t));
@@ -475,6 +461,11 @@ static uint32_t parse_cfg_file(struct imx_header *imxhdr, char *name)
(*set_dcd_rst)(imxhdr, dcd_len, name, lineno);
fclose(fd);
+ /* Exit if there is no BOOT_FROM field specifying the flash_offset */
+ if (imxhdr->flash_offset == FLASH_OFFSET_UNDEFINED) {
+ fprintf(stderr, "Error: No BOOT_FROM tag in %s\n", name);
+ exit(EXIT_FAILURE);
+ }
return dcd_len;
}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 04/32] imximage: fix size of image to load.
2012-10-04 1:47 ` [U-Boot] [PATCH V3 00/32] " Troy Kisky
` (2 preceding siblings ...)
2012-10-04 1:47 ` [U-Boot] [PATCH V3 03/32] imximage: move flash_offset check to common location Troy Kisky
@ 2012-10-04 1:47 ` Troy Kisky
2012-10-20 15:47 ` Stefano Babic
2012-10-04 1:47 ` [U-Boot] [PATCH V3 05/32] imximage: delay setting of image size Troy Kisky
` (30 subsequent siblings)
34 siblings, 1 reply; 430+ messages in thread
From: Troy Kisky @ 2012-10-04 1:47 UTC (permalink / raw)
To: u-boot
sbuf->st_size already includes sizeof(struct imx_header),
so remove extra addition.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
v3: split into its own patch
---
tools/imximage.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/tools/imximage.c b/tools/imximage.c
index 3e9ee6a..7dbf36c 100644
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -221,8 +221,7 @@ static void set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,
/* The external flash header must be at the end of the DCD table */
dcd_v1->addr_data[dcd_len].type = sbuf->st_size +
- imxhdr->flash_offset +
- sizeof(struct imx_header);
+ imxhdr->flash_offset;
/* Security feature are not supported */
fhdr_v1->app_code_csf = 0;
@@ -253,8 +252,7 @@ static void set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t dcd_len,
hdr_v2->boot_data.start = fhdr_v2->self - imxhdr->flash_offset;
hdr_v2->boot_data.size = sbuf->st_size +
- imxhdr->flash_offset +
- sizeof(struct imx_header);
+ imxhdr->flash_offset;
/* Security feature are not supported */
fhdr_v2->csf = 0;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 05/32] imximage: delay setting of image size
2012-10-04 1:47 ` [U-Boot] [PATCH V3 00/32] " Troy Kisky
` (3 preceding siblings ...)
2012-10-04 1:47 ` [U-Boot] [PATCH V3 04/32] imximage: fix size of image to load Troy Kisky
@ 2012-10-04 1:47 ` Troy Kisky
2012-10-20 15:47 ` Stefano Babic
2012-10-04 1:47 ` [U-Boot] [PATCH V3 06/32] imximage: change parameters to set_imx_hdr Troy Kisky
` (29 subsequent siblings)
34 siblings, 1 reply; 430+ messages in thread
From: Troy Kisky @ 2012-10-04 1:47 UTC (permalink / raw)
To: u-boot
When later we change to variable length
header, we won't know the file size when
set_imx_hdr is called. So this is prep work.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
v3: split into its own patch
---
tools/imximage.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/tools/imximage.c b/tools/imximage.c
index 7dbf36c..bed53f0 100644
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -72,6 +72,7 @@ static set_dcd_val_t set_dcd_val;
static set_dcd_rst_t set_dcd_rst;
static set_imx_hdr_t set_imx_hdr;
static uint32_t max_dcd_entries;
+static uint32_t *header_size_ptr;
static uint32_t get_cfg_value(char *token, char *name, int linenr)
{
@@ -202,6 +203,8 @@ static void set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,
flash_header_v1_t *fhdr_v1 = &hdr_v1->fhdr;
dcd_v1_t *dcd_v1 = &hdr_v1->dcd_table;
uint32_t base_offset;
+ uint32_t header_length = (((char *)&dcd_v1->addr_data[dcd_len].addr)
+ - ((char *)imxhdr));
/* Set magic number */
fhdr_v1->app_code_barker = APP_CODE_BARKER;
@@ -219,13 +222,10 @@ static void set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,
fhdr_v1->dcd_ptr = base_offset +
offsetof(imx_header_v1_t, dcd_table);
- /* The external flash header must be at the end of the DCD table */
- dcd_v1->addr_data[dcd_len].type = sbuf->st_size +
- imxhdr->flash_offset;
-
/* Security feature are not supported */
fhdr_v1->app_code_csf = 0;
fhdr_v1->super_root_key = 0;
+ header_size_ptr = (uint32_t *)(((char *)imxhdr) + header_length - 4);
}
static void set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t dcd_len,
@@ -251,11 +251,10 @@ static void set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t dcd_len,
offsetof(imx_header_v2_t, boot_data);
hdr_v2->boot_data.start = fhdr_v2->self - imxhdr->flash_offset;
- hdr_v2->boot_data.size = sbuf->st_size +
- imxhdr->flash_offset;
/* Security feature are not supported */
fhdr_v2->csf = 0;
+ header_size_ptr = &hdr_v2->boot_data.size;
}
static void set_hdr_func(struct imx_header *imxhdr)
@@ -526,6 +525,7 @@ static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd,
/* Set the imx header */
(*set_imx_hdr)(imxhdr, dcd_len, sbuf, params);
+ *header_size_ptr = sbuf->st_size + imxhdr->flash_offset;
}
int imximage_check_params(struct mkimage_params *params)
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 06/32] imximage: change parameters to set_imx_hdr
2012-10-04 1:47 ` [U-Boot] [PATCH V3 00/32] " Troy Kisky
` (4 preceding siblings ...)
2012-10-04 1:47 ` [U-Boot] [PATCH V3 05/32] imximage: delay setting of image size Troy Kisky
@ 2012-10-04 1:47 ` Troy Kisky
2012-10-20 15:48 ` Stefano Babic
2012-10-04 1:47 ` [U-Boot] [PATCH V3 07/32] imximage: make set_imx_hdr_v1/v2 easier to read Troy Kisky
` (28 subsequent siblings)
34 siblings, 1 reply; 430+ messages in thread
From: Troy Kisky @ 2012-10-04 1:47 UTC (permalink / raw)
To: u-boot
Call with the value the function will use
instead of going through a pointer.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
v3: split into its own patch
---
tools/imximage.c | 20 +++++++++-----------
tools/imximage.h | 6 ++----
2 files changed, 11 insertions(+), 15 deletions(-)
diff --git a/tools/imximage.c b/tools/imximage.c
index bed53f0..87a6b59 100644
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -196,8 +196,7 @@ static void set_dcd_rst_v2(struct imx_header *imxhdr, uint32_t dcd_len,
}
static void set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,
- struct stat *sbuf,
- struct mkimage_params *params)
+ uint32_t entry_point, uint32_t flash_offset)
{
imx_header_v1_t *hdr_v1 = &imxhdr->header.hdr_v1;
flash_header_v1_t *fhdr_v1 = &hdr_v1->fhdr;
@@ -209,11 +208,11 @@ static void set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,
/* Set magic number */
fhdr_v1->app_code_barker = APP_CODE_BARKER;
- fhdr_v1->app_dest_ptr = params->ep - imxhdr->flash_offset -
+ fhdr_v1->app_dest_ptr = entry_point - flash_offset -
sizeof(struct imx_header);
- fhdr_v1->app_code_jump_vector = params->ep;
+ fhdr_v1->app_code_jump_vector = entry_point;
- base_offset = fhdr_v1->app_dest_ptr + imxhdr->flash_offset ;
+ base_offset = fhdr_v1->app_dest_ptr + flash_offset;
fhdr_v1->dcd_ptr_ptr =
(uint32_t) (offsetof(flash_header_v1_t, dcd_ptr) -
offsetof(flash_header_v1_t, app_code_jump_vector) +
@@ -229,8 +228,7 @@ static void set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,
}
static void set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t dcd_len,
- struct stat *sbuf,
- struct mkimage_params *params)
+ uint32_t entry_point, uint32_t flash_offset)
{
imx_header_v2_t *hdr_v2 = &imxhdr->header.hdr_v2;
flash_header_v2_t *fhdr_v2 = &hdr_v2->fhdr;
@@ -240,9 +238,9 @@ static void set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t dcd_len,
fhdr_v2->header.length = cpu_to_be16(sizeof(flash_header_v2_t));
fhdr_v2->header.version = IVT_VERSION; /* 0x40 */
- fhdr_v2->entry = params->ep;
+ fhdr_v2->entry = entry_point;
fhdr_v2->reserved1 = fhdr_v2->reserved2 = 0;
- fhdr_v2->self = params->ep - sizeof(struct imx_header);
+ fhdr_v2->self = entry_point - sizeof(struct imx_header);
fhdr_v2->dcd_ptr = fhdr_v2->self +
offsetof(imx_header_v2_t, dcd_table);
@@ -250,7 +248,7 @@ static void set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t dcd_len,
fhdr_v2->boot_data_ptr = fhdr_v2->self +
offsetof(imx_header_v2_t, boot_data);
- hdr_v2->boot_data.start = fhdr_v2->self - imxhdr->flash_offset;
+ hdr_v2->boot_data.start = fhdr_v2->self - flash_offset;
/* Security feature are not supported */
fhdr_v2->csf = 0;
@@ -524,7 +522,7 @@ static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd,
dcd_len = parse_cfg_file(imxhdr, params->imagename);
/* Set the imx header */
- (*set_imx_hdr)(imxhdr, dcd_len, sbuf, params);
+ (*set_imx_hdr)(imxhdr, dcd_len, params->ep, imxhdr->flash_offset);
*header_size_ptr = sbuf->st_size + imxhdr->flash_offset;
}
diff --git a/tools/imximage.h b/tools/imximage.h
index 34f293d..42b6090 100644
--- a/tools/imximage.h
+++ b/tools/imximage.h
@@ -168,9 +168,7 @@ typedef void (*set_dcd_rst_t)(struct imx_header *imxhdr,
uint32_t dcd_len,
char *name, int lineno);
-typedef void (*set_imx_hdr_t)(struct imx_header *imxhdr,
- uint32_t dcd_len,
- struct stat *sbuf,
- struct mkimage_params *params);
+typedef void (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t dcd_len,
+ uint32_t entry_point, uint32_t flash_offset);
#endif /* _IMXIMAGE_H_ */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 07/32] imximage: make set_imx_hdr_v1/v2 easier to read
2012-10-04 1:47 ` [U-Boot] [PATCH V3 00/32] " Troy Kisky
` (5 preceding siblings ...)
2012-10-04 1:47 ` [U-Boot] [PATCH V3 06/32] imximage: change parameters to set_imx_hdr Troy Kisky
@ 2012-10-04 1:47 ` Troy Kisky
2012-10-20 15:48 ` Stefano Babic
2012-10-04 1:47 ` [U-Boot] [PATCH V3 08/32] imximage: make header variable length Troy Kisky
` (27 subsequent siblings)
34 siblings, 1 reply; 430+ messages in thread
From: Troy Kisky @ 2012-10-04 1:47 UTC (permalink / raw)
To: u-boot
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
v3: split into own patch
---
tools/imximage.c | 30 +++++++++++-------------------
1 file changed, 11 insertions(+), 19 deletions(-)
diff --git a/tools/imximage.c b/tools/imximage.c
index 87a6b59..63f88b6 100644
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -201,25 +201,19 @@ static void set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,
imx_header_v1_t *hdr_v1 = &imxhdr->header.hdr_v1;
flash_header_v1_t *fhdr_v1 = &hdr_v1->fhdr;
dcd_v1_t *dcd_v1 = &hdr_v1->dcd_table;
- uint32_t base_offset;
+ uint32_t hdr_base;
uint32_t header_length = (((char *)&dcd_v1->addr_data[dcd_len].addr)
- ((char *)imxhdr));
/* Set magic number */
fhdr_v1->app_code_barker = APP_CODE_BARKER;
- fhdr_v1->app_dest_ptr = entry_point - flash_offset -
- sizeof(struct imx_header);
+ hdr_base = entry_point - sizeof(struct imx_header);
+ fhdr_v1->app_dest_ptr = hdr_base - flash_offset;
fhdr_v1->app_code_jump_vector = entry_point;
- base_offset = fhdr_v1->app_dest_ptr + flash_offset;
- fhdr_v1->dcd_ptr_ptr =
- (uint32_t) (offsetof(flash_header_v1_t, dcd_ptr) -
- offsetof(flash_header_v1_t, app_code_jump_vector) +
- base_offset);
-
- fhdr_v1->dcd_ptr = base_offset +
- offsetof(imx_header_v1_t, dcd_table);
+ fhdr_v1->dcd_ptr_ptr = hdr_base + offsetof(flash_header_v1_t, dcd_ptr);
+ fhdr_v1->dcd_ptr = hdr_base + offsetof(imx_header_v1_t, dcd_table);
/* Security feature are not supported */
fhdr_v1->app_code_csf = 0;
@@ -232,6 +226,7 @@ static void set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t dcd_len,
{
imx_header_v2_t *hdr_v2 = &imxhdr->header.hdr_v2;
flash_header_v2_t *fhdr_v2 = &hdr_v2->fhdr;
+ uint32_t hdr_base;
/* Set magic number */
fhdr_v2->header.tag = IVT_HEADER_TAG; /* 0xD1 */
@@ -240,15 +235,12 @@ static void set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t dcd_len,
fhdr_v2->entry = entry_point;
fhdr_v2->reserved1 = fhdr_v2->reserved2 = 0;
- fhdr_v2->self = entry_point - sizeof(struct imx_header);
-
- fhdr_v2->dcd_ptr = fhdr_v2->self +
- offsetof(imx_header_v2_t, dcd_table);
-
- fhdr_v2->boot_data_ptr = fhdr_v2->self +
- offsetof(imx_header_v2_t, boot_data);
+ fhdr_v2->self = hdr_base = entry_point - sizeof(struct imx_header);
- hdr_v2->boot_data.start = fhdr_v2->self - flash_offset;
+ fhdr_v2->dcd_ptr = hdr_base + offsetof(imx_header_v2_t, dcd_table);
+ fhdr_v2->boot_data_ptr = hdr_base
+ + offsetof(imx_header_v2_t, boot_data);
+ hdr_v2->boot_data.start = hdr_base - flash_offset;
/* Security feature are not supported */
fhdr_v2->csf = 0;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 08/32] imximage: make header variable length
2012-10-04 1:47 ` [U-Boot] [PATCH V3 00/32] " Troy Kisky
` (6 preceding siblings ...)
2012-10-04 1:47 ` [U-Boot] [PATCH V3 07/32] imximage: make set_imx_hdr_v1/v2 easier to read Troy Kisky
@ 2012-10-04 1:47 ` Troy Kisky
2012-10-20 15:52 ` Stefano Babic
2012-11-28 1:31 ` [U-Boot] [PATCH V4 00/11] imximage series Troy Kisky
2012-10-04 1:47 ` [U-Boot] [PATCH V3 09/32] imximage: remove static imximage_version Troy Kisky
` (26 subsequent siblings)
34 siblings, 2 replies; 430+ messages in thread
From: Troy Kisky @ 2012-10-04 1:47 UTC (permalink / raw)
To: u-boot
This makes the dcd table options as well for v2.
Also, the header offset is no longer
right before the code starts.
Before this patch we have
000000 402000d1 17800000 00000000 177ffc2c
000010 177ffc20 177ffc00 00000000 00000000
000020 177ff800 00042b58 00000000 402803d2
000030 042403cc a8050e02 30000000 b0050e02
... more DCD table
000340 cf0000f0 18000e02 7f007f00 1c000e02
000350 7f007f00 00000000 00000000 00000000
000360 00000000 00000000 00000000 00000000
*
0003f0 00000000 00000000 00000000 00000400
000400 ea000014 e59ff014 e59ff014 e59ff014
Notice offset 3fc contains 0x400. This
is the header offset. There is no reason
for this to be in the file, and I have
removed it.
After this patch we have
000000 402000d1 17800000 00000000 177ffcd8
000010 177ffccc 177ffcac 00000000 00000000
000020 177ff8ac 000426ac 00000000 402803d2
000030 042403cc a8050e02 30000000 b0050e02
... more DCD table
000340 cf0000f0 18000e02 7f007f00 1c000e02
000350 7f007f00 ea000014 e59ff014 e59ff014
000360 e59ff014 e59ff014 e59ff014 e59ff014
Notice the zeros between 0x354 and 0x3fb have
been removed.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
v3: other patches split from this one
---
tools/imximage.c | 61 +++++++++++++++++++++++++++++++++++++-----------------
tools/imximage.h | 4 ++--
2 files changed, 44 insertions(+), 21 deletions(-)
diff --git a/tools/imximage.c b/tools/imximage.c
index 63f88b6..1365b1e 100644
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -65,7 +65,6 @@ static table_entry_t imximage_versions[] = {
{-1, "", " (Invalid)", },
};
-static struct imx_header imximage_header;
static uint32_t imximage_version;
static set_dcd_val_t set_dcd_val;
@@ -73,6 +72,9 @@ static set_dcd_rst_t set_dcd_rst;
static set_imx_hdr_t set_imx_hdr;
static uint32_t max_dcd_entries;
static uint32_t *header_size_ptr;
+static uint32_t g_flash_offset;
+
+static struct image_type_params imximage_params;
static uint32_t get_cfg_value(char *token, char *name, int linenr)
{
@@ -102,8 +104,7 @@ static uint32_t detect_imximage_version(struct imx_header *imx_hdr)
return IMXIMAGE_V1;
/* Try to detect V2 */
- if ((fhdr_v2->header.tag == IVT_HEADER_TAG) &&
- (hdr_v2->dcd_table.header.tag == DCD_HEADER_TAG))
+ if (fhdr_v2->header.tag == IVT_HEADER_TAG)
return IMXIMAGE_V2;
return IMXIMAGE_VER_INVALID;
@@ -195,7 +196,7 @@ static void set_dcd_rst_v2(struct imx_header *imxhdr, uint32_t dcd_len,
dcd_v2->write_dcd_command.param = DCD_COMMAND_PARAM;
}
-static void set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,
+static int set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,
uint32_t entry_point, uint32_t flash_offset)
{
imx_header_v1_t *hdr_v1 = &imxhdr->header.hdr_v1;
@@ -208,7 +209,7 @@ static void set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,
/* Set magic number */
fhdr_v1->app_code_barker = APP_CODE_BARKER;
- hdr_base = entry_point - sizeof(struct imx_header);
+ hdr_base = entry_point - header_length;
fhdr_v1->app_dest_ptr = hdr_base - flash_offset;
fhdr_v1->app_code_jump_vector = entry_point;
@@ -219,14 +220,18 @@ static void set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,
fhdr_v1->app_code_csf = 0;
fhdr_v1->super_root_key = 0;
header_size_ptr = (uint32_t *)(((char *)imxhdr) + header_length - 4);
+ return header_length;
}
-static void set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t dcd_len,
+static int set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t dcd_len,
uint32_t entry_point, uint32_t flash_offset)
{
imx_header_v2_t *hdr_v2 = &imxhdr->header.hdr_v2;
flash_header_v2_t *fhdr_v2 = &hdr_v2->fhdr;
uint32_t hdr_base;
+ uint32_t header_length = (dcd_len) ?
+ (char *)&hdr_v2->dcd_table.addr_data[dcd_len] - ((char*)imxhdr)
+ : offsetof(imx_header_v2_t, dcd_table);
/* Set magic number */
fhdr_v2->header.tag = IVT_HEADER_TAG; /* 0xD1 */
@@ -235,9 +240,10 @@ static void set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t dcd_len,
fhdr_v2->entry = entry_point;
fhdr_v2->reserved1 = fhdr_v2->reserved2 = 0;
- fhdr_v2->self = hdr_base = entry_point - sizeof(struct imx_header);
+ fhdr_v2->self = hdr_base = entry_point - header_length;
- fhdr_v2->dcd_ptr = hdr_base + offsetof(imx_header_v2_t, dcd_table);
+ fhdr_v2->dcd_ptr = (dcd_len) ? hdr_base
+ + offsetof(imx_header_v2_t, dcd_table) : 0;
fhdr_v2->boot_data_ptr = hdr_base
+ offsetof(imx_header_v2_t, boot_data);
hdr_v2->boot_data.start = hdr_base - flash_offset;
@@ -245,6 +251,7 @@ static void set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t dcd_len,
/* Security feature are not supported */
fhdr_v2->csf = 0;
header_size_ptr = &hdr_v2->boot_data.size;
+ return header_length;
}
static void set_hdr_func(struct imx_header *imxhdr)
@@ -342,9 +349,9 @@ static void parse_cfg_cmd(struct imx_header *imxhdr, int32_t cmd, char *token,
set_hdr_func(imxhdr);
break;
case CMD_BOOT_FROM:
- imxhdr->flash_offset = get_table_entry_id(imximage_bootops,
+ g_flash_offset = get_table_entry_id(imximage_bootops,
"imximage boot option", token);
- if (imxhdr->flash_offset == -1) {
+ if (g_flash_offset == -1) {
fprintf(stderr, "Error: %s[%d] -Invalid boot device"
"(%s)\n", name, lineno, token);
exit(EXIT_FAILURE);
@@ -449,7 +456,7 @@ static uint32_t parse_cfg_file(struct imx_header *imxhdr, char *name)
fclose(fd);
/* Exit if there is no BOOT_FROM field specifying the flash_offset */
- if (imxhdr->flash_offset == FLASH_OFFSET_UNDEFINED) {
+ if (g_flash_offset == FLASH_OFFSET_UNDEFINED) {
fprintf(stderr, "Error: No BOOT_FROM tag in %s\n", name);
exit(EXIT_FAILURE);
}
@@ -494,12 +501,17 @@ static void imximage_print_header(const void *ptr)
}
}
-static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd,
- struct mkimage_params *params)
+int imximage_vrec_header(struct mkimage_params *params,
+ struct image_type_params *tparams)
{
- struct imx_header *imxhdr = (struct imx_header *)ptr;
+ struct imx_header *imxhdr;
uint32_t dcd_len;
+ imxhdr = calloc(1, MAX_HEADER_SIZE);
+ if (!imxhdr) {
+ fprintf(stderr, "Error: out of memory\n");
+ exit(EXIT_FAILURE);
+ }
/*
* In order to not change the old imx cfg file
* by adding VERSION command into it, here need
@@ -507,15 +519,27 @@ static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd,
*/
imximage_version = IMXIMAGE_V1;
/* Be able to detect if the cfg file has no BOOT_FROM tag */
- imxhdr->flash_offset = FLASH_OFFSET_UNDEFINED;
+ g_flash_offset = FLASH_OFFSET_UNDEFINED;
set_hdr_func(imxhdr);
/* Parse dcd configuration file */
dcd_len = parse_cfg_file(imxhdr, params->imagename);
/* Set the imx header */
- (*set_imx_hdr)(imxhdr, dcd_len, params->ep, imxhdr->flash_offset);
- *header_size_ptr = sbuf->st_size + imxhdr->flash_offset;
+ imximage_params.header_size = (*set_imx_hdr)(imxhdr, dcd_len,
+ params->ep, g_flash_offset);
+ imximage_params.hdr = imxhdr;
+ return 0;
+}
+
+static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd,
+ struct mkimage_params *params)
+{
+ /* Set the size in header */
+ uint32_t offset = (char *)header_size_ptr - (char *)imximage_params.hdr;
+ uint32_t *p = (uint32_t *)((char *)ptr + offset);
+
+ *p = sbuf->st_size + g_flash_offset;
}
int imximage_check_params(struct mkimage_params *params)
@@ -545,8 +569,7 @@ int imximage_check_params(struct mkimage_params *params)
*/
static struct image_type_params imximage_params = {
.name = "Freescale i.MX 5x Boot Image support",
- .header_size = sizeof(struct imx_header),
- .hdr = (void *)&imximage_header,
+ .vrec_header = imximage_vrec_header,
.check_image_type = imximage_check_image_types,
.verify_header = imximage_verify_header,
.print_header = imximage_print_header,
diff --git a/tools/imximage.h b/tools/imximage.h
index 42b6090..0f39447 100644
--- a/tools/imximage.h
+++ b/tools/imximage.h
@@ -30,6 +30,7 @@
#define DCD_BARKER 0xB17219E9
#define HEADER_OFFSET 0x400
+#define MAX_HEADER_SIZE (16 << 10)
#define CMD_DATA_STR "DATA"
#define FLASH_OFFSET_UNDEFINED 0xFFFFFFFF
@@ -156,7 +157,6 @@ struct imx_header {
imx_header_v1_t hdr_v1;
imx_header_v2_t hdr_v2;
} header;
- uint32_t flash_offset;
};
typedef void (*set_dcd_val_t)(struct imx_header *imxhdr,
@@ -168,7 +168,7 @@ typedef void (*set_dcd_rst_t)(struct imx_header *imxhdr,
uint32_t dcd_len,
char *name, int lineno);
-typedef void (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t dcd_len,
+typedef int (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t dcd_len,
uint32_t entry_point, uint32_t flash_offset);
#endif /* _IMXIMAGE_H_ */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 09/32] imximage: remove static imximage_version
2012-10-04 1:47 ` [U-Boot] [PATCH V3 00/32] " Troy Kisky
` (7 preceding siblings ...)
2012-10-04 1:47 ` [U-Boot] [PATCH V3 08/32] imximage: make header variable length Troy Kisky
@ 2012-10-04 1:47 ` Troy Kisky
2012-10-04 1:47 ` [U-Boot] [PATCH V3 10/32] imximage: prepare to move static variables to struct data_src Troy Kisky
` (25 subsequent siblings)
34 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-10-04 1:47 UTC (permalink / raw)
To: u-boot
This variable does not need to have file scope.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
tools/imximage.c | 21 +++++++++------------
1 file changed, 9 insertions(+), 12 deletions(-)
diff --git a/tools/imximage.c b/tools/imximage.c
index 1365b1e..10ccfa9 100644
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -65,8 +65,6 @@ static table_entry_t imximage_versions[] = {
{-1, "", " (Invalid)", },
};
-static uint32_t imximage_version;
-
static set_dcd_val_t set_dcd_val;
static set_dcd_rst_t set_dcd_rst;
static set_imx_hdr_t set_imx_hdr;
@@ -254,7 +252,7 @@ static int set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t dcd_len,
return header_length;
}
-static void set_hdr_func(struct imx_header *imxhdr)
+static void set_hdr_func(struct imx_header *imxhdr, uint32_t imximage_version)
{
switch (imximage_version) {
case IMXIMAGE_V1:
@@ -335,6 +333,7 @@ static void parse_cfg_cmd(struct imx_header *imxhdr, int32_t cmd, char *token,
{
int value;
static int cmd_ver_first = ~0;
+ uint32_t imximage_version;
switch (cmd) {
case CMD_IMAGE_VERSION:
@@ -346,7 +345,7 @@ static void parse_cfg_cmd(struct imx_header *imxhdr, int32_t cmd, char *token,
exit(EXIT_FAILURE);
}
cmd_ver_first = 1;
- set_hdr_func(imxhdr);
+ set_hdr_func(imxhdr, imximage_version);
break;
case CMD_BOOT_FROM:
g_flash_offset = get_table_entry_id(imximage_bootops,
@@ -419,6 +418,12 @@ static uint32_t parse_cfg_file(struct imx_header *imxhdr, char *name)
int dcd_len = 0;
int32_t cmd;
+ /*
+ * In order to not change the old imx cfg file
+ * by adding VERSION command into it, here need
+ * set up function ptr group to V1 by default.
+ */
+ set_hdr_func(imxhdr, IMXIMAGE_V1);
fd = fopen(name, "r");
if (fd == 0) {
fprintf(stderr, "Error: %s - Can't open DCD file\n", name);
@@ -512,16 +517,8 @@ int imximage_vrec_header(struct mkimage_params *params,
fprintf(stderr, "Error: out of memory\n");
exit(EXIT_FAILURE);
}
- /*
- * In order to not change the old imx cfg file
- * by adding VERSION command into it, here need
- * set up function ptr group to V1 by default.
- */
- imximage_version = IMXIMAGE_V1;
/* Be able to detect if the cfg file has no BOOT_FROM tag */
g_flash_offset = FLASH_OFFSET_UNDEFINED;
- set_hdr_func(imxhdr);
-
/* Parse dcd configuration file */
dcd_len = parse_cfg_file(imxhdr, params->imagename);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 10/32] imximage: prepare to move static variables to struct data_src
2012-10-04 1:47 ` [U-Boot] [PATCH V3 00/32] " Troy Kisky
` (8 preceding siblings ...)
2012-10-04 1:47 ` [U-Boot] [PATCH V3 09/32] imximage: remove static imximage_version Troy Kisky
@ 2012-10-04 1:47 ` Troy Kisky
2012-10-04 1:47 ` [U-Boot] [PATCH V3 11/32] imximage: change parameters for set_dcd_val/set_imx_hdr Troy Kisky
` (24 subsequent siblings)
34 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-10-04 1:47 UTC (permalink / raw)
To: u-boot
Need to move accesses to the static variables to
a function where struct data_src is used.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
v3: new patch
---
tools/imximage.c | 24 +++++++++++++-----------
tools/imximage.h | 3 +++
2 files changed, 16 insertions(+), 11 deletions(-)
diff --git a/tools/imximage.c b/tools/imximage.c
index 10ccfa9..a2460d6 100644
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -407,8 +407,11 @@ static void parse_cfg_fld(struct imx_header *imxhdr, int32_t *cmd,
break;
}
}
-static uint32_t parse_cfg_file(struct imx_header *imxhdr, char *name)
+
+static int parse_cfg_file(struct imx_header *imxhdr, char *name,
+ uint32_t entry_point)
{
+ struct data_src ds;
FILE *fd = NULL;
char *line = NULL;
char *token, *saveptr1, *saveptr2;
@@ -418,6 +421,10 @@ static uint32_t parse_cfg_file(struct imx_header *imxhdr, char *name)
int dcd_len = 0;
int32_t cmd;
+ /* Be able to detect if the cfg file has no BOOT_FROM tag */
+ g_flash_offset = FLASH_OFFSET_UNDEFINED;
+ memset(&ds, 0, sizeof(struct data_src));
+ ds.imxhdr = imxhdr;
/*
* In order to not change the old imx cfg file
* by adding VERSION command into it, here need
@@ -465,10 +472,10 @@ static uint32_t parse_cfg_file(struct imx_header *imxhdr, char *name)
fprintf(stderr, "Error: No BOOT_FROM tag in %s\n", name);
exit(EXIT_FAILURE);
}
- return dcd_len;
+ /* Set the imx header */
+ return (*set_imx_hdr)(imxhdr, dcd_len, entry_point, g_flash_offset);
}
-
static int imximage_check_image_types(uint8_t type)
{
if (type == IH_TYPE_IMXIMAGE)
@@ -510,21 +517,16 @@ int imximage_vrec_header(struct mkimage_params *params,
struct image_type_params *tparams)
{
struct imx_header *imxhdr;
- uint32_t dcd_len;
imxhdr = calloc(1, MAX_HEADER_SIZE);
if (!imxhdr) {
fprintf(stderr, "Error: out of memory\n");
exit(EXIT_FAILURE);
}
- /* Be able to detect if the cfg file has no BOOT_FROM tag */
- g_flash_offset = FLASH_OFFSET_UNDEFINED;
- /* Parse dcd configuration file */
- dcd_len = parse_cfg_file(imxhdr, params->imagename);
- /* Set the imx header */
- imximage_params.header_size = (*set_imx_hdr)(imxhdr, dcd_len,
- params->ep, g_flash_offset);
+ /* Parse dcd configuration file */
+ imximage_params.header_size = parse_cfg_file(imxhdr, params->imagename,
+ params->ep);
imximage_params.hdr = imxhdr;
return 0;
}
diff --git a/tools/imximage.h b/tools/imximage.h
index 0f39447..2895378 100644
--- a/tools/imximage.h
+++ b/tools/imximage.h
@@ -171,4 +171,7 @@ typedef void (*set_dcd_rst_t)(struct imx_header *imxhdr,
typedef int (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t dcd_len,
uint32_t entry_point, uint32_t flash_offset);
+struct data_src {
+ struct imx_header *imxhdr;
+};
#endif /* _IMXIMAGE_H_ */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 11/32] imximage: change parameters for set_dcd_val/set_imx_hdr
2012-10-04 1:47 ` [U-Boot] [PATCH V3 00/32] " Troy Kisky
` (9 preceding siblings ...)
2012-10-04 1:47 ` [U-Boot] [PATCH V3 10/32] imximage: prepare to move static variables to struct data_src Troy Kisky
@ 2012-10-04 1:47 ` Troy Kisky
2012-10-04 1:47 ` [U-Boot] [PATCH V3 12/32] imximage: move set_imx_hdr to struct data_src Troy Kisky
` (23 subsequent siblings)
34 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-10-04 1:47 UTC (permalink / raw)
To: u-boot
Change 1st argument of set_imx_hdr/set_dcd_val
to struct data_src.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
tools/imximage.c | 41 +++++++++++++++++++++--------------------
tools/imximage.h | 5 +++--
2 files changed, 24 insertions(+), 22 deletions(-)
diff --git a/tools/imximage.c b/tools/imximage.c
index a2460d6..85d3753 100644
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -116,10 +116,10 @@ static void err_imximage_version(int version)
exit(EXIT_FAILURE);
}
-static void set_dcd_val_v1(struct imx_header *imxhdr, char *name, int lineno,
+static void set_dcd_val_v1(struct data_src *ds, char *name, int lineno,
int fld, uint32_t value, uint32_t off)
{
- dcd_v1_t *dcd_v1 = &imxhdr->header.hdr_v1.dcd_table;
+ dcd_v1_t *dcd_v1 = &ds->imxhdr->header.hdr_v1.dcd_table;
switch (fld) {
case CFG_REG_SIZE:
@@ -144,10 +144,10 @@ static void set_dcd_val_v1(struct imx_header *imxhdr, char *name, int lineno,
}
}
-static void set_dcd_val_v2(struct imx_header *imxhdr, char *name, int lineno,
+static void set_dcd_val_v2(struct data_src *ds, char *name, int lineno,
int fld, uint32_t value, uint32_t off)
{
- dcd_v2_t *dcd_v2 = &imxhdr->header.hdr_v2.dcd_table;
+ dcd_v2_t *dcd_v2 = &ds->imxhdr->header.hdr_v2.dcd_table;
switch (fld) {
case CFG_REG_ADDRESS:
@@ -194,15 +194,15 @@ static void set_dcd_rst_v2(struct imx_header *imxhdr, uint32_t dcd_len,
dcd_v2->write_dcd_command.param = DCD_COMMAND_PARAM;
}
-static int set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,
+static int set_imx_hdr_v1(struct data_src *ds, uint32_t dcd_len,
uint32_t entry_point, uint32_t flash_offset)
{
- imx_header_v1_t *hdr_v1 = &imxhdr->header.hdr_v1;
+ imx_header_v1_t *hdr_v1 = &ds->imxhdr->header.hdr_v1;
flash_header_v1_t *fhdr_v1 = &hdr_v1->fhdr;
dcd_v1_t *dcd_v1 = &hdr_v1->dcd_table;
uint32_t hdr_base;
uint32_t header_length = (((char *)&dcd_v1->addr_data[dcd_len].addr)
- - ((char *)imxhdr));
+ - ((char *)ds->imxhdr));
/* Set magic number */
fhdr_v1->app_code_barker = APP_CODE_BARKER;
@@ -217,19 +217,20 @@ static int set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,
/* Security feature are not supported */
fhdr_v1->app_code_csf = 0;
fhdr_v1->super_root_key = 0;
- header_size_ptr = (uint32_t *)(((char *)imxhdr) + header_length - 4);
+ header_size_ptr = (uint32_t *)(((char *)ds->imxhdr) +
+ header_length - 4);
return header_length;
}
-static int set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t dcd_len,
+static int set_imx_hdr_v2(struct data_src *ds, uint32_t dcd_len,
uint32_t entry_point, uint32_t flash_offset)
{
- imx_header_v2_t *hdr_v2 = &imxhdr->header.hdr_v2;
+ imx_header_v2_t *hdr_v2 = &ds->imxhdr->header.hdr_v2;
flash_header_v2_t *fhdr_v2 = &hdr_v2->fhdr;
uint32_t hdr_base;
uint32_t header_length = (dcd_len) ?
- (char *)&hdr_v2->dcd_table.addr_data[dcd_len] - ((char*)imxhdr)
- : offsetof(imx_header_v2_t, dcd_table);
+ (char *)&hdr_v2->dcd_table.addr_data[dcd_len] -
+ ((char *)ds->imxhdr) : offsetof(imx_header_v2_t, dcd_table);
/* Set magic number */
fhdr_v2->header.tag = IVT_HEADER_TAG; /* 0xD1 */
@@ -328,7 +329,7 @@ static void print_hdr_v2(struct imx_header *imx_hdr)
printf("Entry Point: %08x\n", (uint32_t)fhdr_v2->entry);
}
-static void parse_cfg_cmd(struct imx_header *imxhdr, int32_t cmd, char *token,
+static void parse_cfg_cmd(struct data_src *ds, int32_t cmd, char *token,
char *name, int lineno, int fld, int dcd_len)
{
int value;
@@ -345,7 +346,7 @@ static void parse_cfg_cmd(struct imx_header *imxhdr, int32_t cmd, char *token,
exit(EXIT_FAILURE);
}
cmd_ver_first = 1;
- set_hdr_func(imxhdr, imximage_version);
+ set_hdr_func(ds->imxhdr, imximage_version);
break;
case CMD_BOOT_FROM:
g_flash_offset = get_table_entry_id(imximage_bootops,
@@ -360,14 +361,14 @@ static void parse_cfg_cmd(struct imx_header *imxhdr, int32_t cmd, char *token,
break;
case CMD_DATA:
value = get_cfg_value(token, name, lineno);
- (*set_dcd_val)(imxhdr, name, lineno, fld, value, dcd_len);
+ (*set_dcd_val)(ds, name, lineno, fld, value, dcd_len);
if (unlikely(cmd_ver_first != 1))
cmd_ver_first = 0;
break;
}
}
-static void parse_cfg_fld(struct imx_header *imxhdr, int32_t *cmd,
+static void parse_cfg_fld(struct data_src *ds, int32_t *cmd,
char *token, char *name, int lineno, int fld, int *dcd_len)
{
int value;
@@ -383,7 +384,7 @@ static void parse_cfg_fld(struct imx_header *imxhdr, int32_t *cmd,
}
break;
case CFG_REG_SIZE:
- parse_cfg_cmd(imxhdr, *cmd, token, name, lineno, fld, *dcd_len);
+ parse_cfg_cmd(ds, *cmd, token, name, lineno, fld, *dcd_len);
break;
case CFG_REG_ADDRESS:
case CFG_REG_VALUE:
@@ -391,7 +392,7 @@ static void parse_cfg_fld(struct imx_header *imxhdr, int32_t *cmd,
return;
value = get_cfg_value(token, name, lineno);
- (*set_dcd_val)(imxhdr, name, lineno, fld, value, *dcd_len);
+ (*set_dcd_val)(ds, name, lineno, fld, value, *dcd_len);
if (fld == CFG_REG_VALUE) {
(*dcd_len)++;
@@ -458,7 +459,7 @@ static int parse_cfg_file(struct imx_header *imxhdr, char *name,
if (token[0] == '#')
break;
- parse_cfg_fld(imxhdr, &cmd, token, name,
+ parse_cfg_fld(&ds, &cmd, token, name,
lineno, fld, &dcd_len);
}
@@ -473,7 +474,7 @@ static int parse_cfg_file(struct imx_header *imxhdr, char *name,
exit(EXIT_FAILURE);
}
/* Set the imx header */
- return (*set_imx_hdr)(imxhdr, dcd_len, entry_point, g_flash_offset);
+ return (*set_imx_hdr)(&ds, dcd_len, entry_point, g_flash_offset);
}
static int imximage_check_image_types(uint8_t type)
diff --git a/tools/imximage.h b/tools/imximage.h
index 2895378..3054d55 100644
--- a/tools/imximage.h
+++ b/tools/imximage.h
@@ -159,7 +159,8 @@ struct imx_header {
} header;
};
-typedef void (*set_dcd_val_t)(struct imx_header *imxhdr,
+struct data_src;
+typedef void (*set_dcd_val_t)(struct data_src *ds,
char *name, int lineno,
int fld, uint32_t value,
uint32_t off);
@@ -168,7 +169,7 @@ typedef void (*set_dcd_rst_t)(struct imx_header *imxhdr,
uint32_t dcd_len,
char *name, int lineno);
-typedef int (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t dcd_len,
+typedef int (*set_imx_hdr_t)(struct data_src *ds, uint32_t dcd_len,
uint32_t entry_point, uint32_t flash_offset);
struct data_src {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 12/32] imximage: move set_imx_hdr to struct data_src
2012-10-04 1:47 ` [U-Boot] [PATCH V3 00/32] " Troy Kisky
` (10 preceding siblings ...)
2012-10-04 1:47 ` [U-Boot] [PATCH V3 11/32] imximage: change parameters for set_dcd_val/set_imx_hdr Troy Kisky
@ 2012-10-04 1:47 ` Troy Kisky
2012-10-04 1:47 ` [U-Boot] [PATCH V3 13/32] imximage: move set_dcd_val " Troy Kisky
` (22 subsequent siblings)
34 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-10-04 1:47 UTC (permalink / raw)
To: u-boot
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
v3: new patch
---
tools/imximage.c | 13 ++++++-------
tools/imximage.h | 1 +
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/tools/imximage.c b/tools/imximage.c
index 85d3753..eb1ab62 100644
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -67,7 +67,6 @@ static table_entry_t imximage_versions[] = {
static set_dcd_val_t set_dcd_val;
static set_dcd_rst_t set_dcd_rst;
-static set_imx_hdr_t set_imx_hdr;
static uint32_t max_dcd_entries;
static uint32_t *header_size_ptr;
static uint32_t g_flash_offset;
@@ -253,19 +252,19 @@ static int set_imx_hdr_v2(struct data_src *ds, uint32_t dcd_len,
return header_length;
}
-static void set_hdr_func(struct imx_header *imxhdr, uint32_t imximage_version)
+static void set_hdr_func(struct data_src *ds, uint32_t imximage_version)
{
switch (imximage_version) {
case IMXIMAGE_V1:
set_dcd_val = set_dcd_val_v1;
set_dcd_rst = set_dcd_rst_v1;
- set_imx_hdr = set_imx_hdr_v1;
+ ds->set_imx_hdr = set_imx_hdr_v1;
max_dcd_entries = MAX_HW_CFG_SIZE_V1;
break;
case IMXIMAGE_V2:
set_dcd_val = set_dcd_val_v2;
set_dcd_rst = set_dcd_rst_v2;
- set_imx_hdr = set_imx_hdr_v2;
+ ds->set_imx_hdr = set_imx_hdr_v2;
max_dcd_entries = MAX_HW_CFG_SIZE_V2;
break;
default:
@@ -346,7 +345,7 @@ static void parse_cfg_cmd(struct data_src *ds, int32_t cmd, char *token,
exit(EXIT_FAILURE);
}
cmd_ver_first = 1;
- set_hdr_func(ds->imxhdr, imximage_version);
+ set_hdr_func(ds, imximage_version);
break;
case CMD_BOOT_FROM:
g_flash_offset = get_table_entry_id(imximage_bootops,
@@ -431,7 +430,7 @@ static int parse_cfg_file(struct imx_header *imxhdr, char *name,
* by adding VERSION command into it, here need
* set up function ptr group to V1 by default.
*/
- set_hdr_func(imxhdr, IMXIMAGE_V1);
+ set_hdr_func(&ds, IMXIMAGE_V1);
fd = fopen(name, "r");
if (fd == 0) {
fprintf(stderr, "Error: %s - Can't open DCD file\n", name);
@@ -474,7 +473,7 @@ static int parse_cfg_file(struct imx_header *imxhdr, char *name,
exit(EXIT_FAILURE);
}
/* Set the imx header */
- return (*set_imx_hdr)(&ds, dcd_len, entry_point, g_flash_offset);
+ return (*ds.set_imx_hdr)(&ds, dcd_len, entry_point, g_flash_offset);
}
static int imximage_check_image_types(uint8_t type)
diff --git a/tools/imximage.h b/tools/imximage.h
index 3054d55..f27a2ef 100644
--- a/tools/imximage.h
+++ b/tools/imximage.h
@@ -174,5 +174,6 @@ typedef int (*set_imx_hdr_t)(struct data_src *ds, uint32_t dcd_len,
struct data_src {
struct imx_header *imxhdr;
+ set_imx_hdr_t set_imx_hdr;
};
#endif /* _IMXIMAGE_H_ */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 13/32] imximage: move set_dcd_val to struct data_src
2012-10-04 1:47 ` [U-Boot] [PATCH V3 00/32] " Troy Kisky
` (11 preceding siblings ...)
2012-10-04 1:47 ` [U-Boot] [PATCH V3 12/32] imximage: move set_imx_hdr to struct data_src Troy Kisky
@ 2012-10-04 1:47 ` Troy Kisky
2012-10-04 1:47 ` [U-Boot] [PATCH V3 14/32] imximage: enable word writes for version2 header Troy Kisky
` (21 subsequent siblings)
34 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-10-04 1:47 UTC (permalink / raw)
To: u-boot
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
v3: new patch
---
tools/imximage.c | 9 ++++-----
tools/imximage.h | 1 +
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/tools/imximage.c b/tools/imximage.c
index eb1ab62..6fcb6ee 100644
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -65,7 +65,6 @@ static table_entry_t imximage_versions[] = {
{-1, "", " (Invalid)", },
};
-static set_dcd_val_t set_dcd_val;
static set_dcd_rst_t set_dcd_rst;
static uint32_t max_dcd_entries;
static uint32_t *header_size_ptr;
@@ -256,13 +255,13 @@ static void set_hdr_func(struct data_src *ds, uint32_t imximage_version)
{
switch (imximage_version) {
case IMXIMAGE_V1:
- set_dcd_val = set_dcd_val_v1;
+ ds->set_dcd_val = set_dcd_val_v1;
set_dcd_rst = set_dcd_rst_v1;
ds->set_imx_hdr = set_imx_hdr_v1;
max_dcd_entries = MAX_HW_CFG_SIZE_V1;
break;
case IMXIMAGE_V2:
- set_dcd_val = set_dcd_val_v2;
+ ds->set_dcd_val = set_dcd_val_v2;
set_dcd_rst = set_dcd_rst_v2;
ds->set_imx_hdr = set_imx_hdr_v2;
max_dcd_entries = MAX_HW_CFG_SIZE_V2;
@@ -360,7 +359,7 @@ static void parse_cfg_cmd(struct data_src *ds, int32_t cmd, char *token,
break;
case CMD_DATA:
value = get_cfg_value(token, name, lineno);
- (*set_dcd_val)(ds, name, lineno, fld, value, dcd_len);
+ (*ds->set_dcd_val)(ds, name, lineno, fld, value, dcd_len);
if (unlikely(cmd_ver_first != 1))
cmd_ver_first = 0;
break;
@@ -391,7 +390,7 @@ static void parse_cfg_fld(struct data_src *ds, int32_t *cmd,
return;
value = get_cfg_value(token, name, lineno);
- (*set_dcd_val)(ds, name, lineno, fld, value, *dcd_len);
+ (*ds->set_dcd_val)(ds, name, lineno, fld, value, *dcd_len);
if (fld == CFG_REG_VALUE) {
(*dcd_len)++;
diff --git a/tools/imximage.h b/tools/imximage.h
index f27a2ef..444ddce 100644
--- a/tools/imximage.h
+++ b/tools/imximage.h
@@ -175,5 +175,6 @@ typedef int (*set_imx_hdr_t)(struct data_src *ds, uint32_t dcd_len,
struct data_src {
struct imx_header *imxhdr;
set_imx_hdr_t set_imx_hdr;
+ set_dcd_val_t set_dcd_val;
};
#endif /* _IMXIMAGE_H_ */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 14/32] imximage: enable word writes for version2 header
2012-10-04 1:47 ` [U-Boot] [PATCH V3 00/32] " Troy Kisky
` (12 preceding siblings ...)
2012-10-04 1:47 ` [U-Boot] [PATCH V3 13/32] imximage: move set_dcd_val " Troy Kisky
@ 2012-10-04 1:47 ` Troy Kisky
2012-10-04 1:47 ` [U-Boot] [PATCH V3 15/32] tools: add parse_helper file Troy Kisky
` (20 subsequent siblings)
34 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-10-04 1:47 UTC (permalink / raw)
To: u-boot
Before, only 1 write_dcd_command table was built.
Now, a new table is built when the size changes.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
v3: moved static variables together
---
tools/imximage.c | 143 ++++++++++++++++++++++++++----------------------------
tools/imximage.h | 18 +++----
2 files changed, 76 insertions(+), 85 deletions(-)
diff --git a/tools/imximage.c b/tools/imximage.c
index 6fcb6ee..29a12bc 100644
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -65,8 +65,6 @@ static table_entry_t imximage_versions[] = {
{-1, "", " (Invalid)", },
};
-static set_dcd_rst_t set_dcd_rst;
-static uint32_t max_dcd_entries;
static uint32_t *header_size_ptr;
static uint32_t g_flash_offset;
@@ -115,7 +113,7 @@ static void err_imximage_version(int version)
}
static void set_dcd_val_v1(struct data_src *ds, char *name, int lineno,
- int fld, uint32_t value, uint32_t off)
+ int fld, uint32_t value)
{
dcd_v1_t *dcd_v1 = &ds->imxhdr->header.hdr_v1.dcd_table;
@@ -128,13 +126,15 @@ static void set_dcd_val_v1(struct data_src *ds, char *name, int lineno,
name, lineno, value);
exit(EXIT_FAILURE);
}
- dcd_v1->addr_data[off].type = value;
+ *ds->p_entry++ = value;
break;
case CFG_REG_ADDRESS:
- dcd_v1->addr_data[off].addr = value;
+ *ds->p_entry++ = value;
break;
case CFG_REG_VALUE:
- dcd_v1->addr_data[off].value = value;
+ *ds->p_entry++ = value;
+ dcd_v1->preamble.length = (char *)ds->p_entry
+ - (char *)&dcd_v1->addr_data[0].type;
break;
default:
break;
@@ -143,16 +143,42 @@ static void set_dcd_val_v1(struct data_src *ds, char *name, int lineno,
}
static void set_dcd_val_v2(struct data_src *ds, char *name, int lineno,
- int fld, uint32_t value, uint32_t off)
+ int fld, uint32_t value)
{
+ uint32_t len;
dcd_v2_t *dcd_v2 = &ds->imxhdr->header.hdr_v2.dcd_table;
switch (fld) {
+ case CFG_REG_SIZE:
+ /* Byte, halfword, word */
+ if ((value != 1) && (value != 2) && (value != 4)) {
+ fprintf(stderr, "Error: %s[%d] - "
+ "Invalid register size " "(%d)\n",
+ name, lineno, value);
+ exit(EXIT_FAILURE);
+ }
+ if (ds->p_dcd && (ds->p_dcd->param == value))
+ break;
+ if (!ds->p_dcd) {
+ dcd_v2->header.tag = DCD_HEADER_TAG;
+ dcd_v2->header.version = DCD_VERSION;
+ ds->p_dcd = &dcd_v2->write_dcd_command;
+ } else {
+ ds->p_dcd = (write_dcd_command_t *)ds->p_entry;
+ }
+ ds->p_dcd->param = value;
+ ds->p_dcd->tag = DCD_COMMAND_TAG;
+ ds->p_entry = (uint32_t *)(ds->p_dcd + 1);
+ break;
case CFG_REG_ADDRESS:
- dcd_v2->addr_data[off].addr = cpu_to_be32(value);
+ *ds->p_entry++ = cpu_to_be32(value);
break;
case CFG_REG_VALUE:
- dcd_v2->addr_data[off].value = cpu_to_be32(value);
+ *ds->p_entry++ = cpu_to_be32(value);
+ len = (char *)ds->p_entry - (char *)&dcd_v2->header;
+ dcd_v2->header.length = cpu_to_be16(len);
+ len = (char *)ds->p_entry - (char *)ds->p_dcd;
+ ds->p_dcd->length = cpu_to_be16(len);
break;
default:
break;
@@ -160,47 +186,14 @@ static void set_dcd_val_v2(struct data_src *ds, char *name, int lineno,
}
}
-/*
- * Complete setting up the rest field of DCD of V1
- * such as barker code and DCD data length.
- */
-static void set_dcd_rst_v1(struct imx_header *imxhdr, uint32_t dcd_len,
- char *name, int lineno)
-{
- dcd_v1_t *dcd_v1 = &imxhdr->header.hdr_v1.dcd_table;
-
- dcd_v1->preamble.barker = DCD_BARKER;
- dcd_v1->preamble.length = dcd_len * sizeof(dcd_type_addr_data_t);
-}
-
-/*
- * Complete setting up the reset field of DCD of V2
- * such as DCD tag, version, length, etc.
- */
-static void set_dcd_rst_v2(struct imx_header *imxhdr, uint32_t dcd_len,
- char *name, int lineno)
-{
- dcd_v2_t *dcd_v2 = &imxhdr->header.hdr_v2.dcd_table;
-
- dcd_v2->header.tag = DCD_HEADER_TAG;
- dcd_v2->header.length = cpu_to_be16(
- dcd_len * sizeof(dcd_addr_data_t) + 8);
- dcd_v2->header.version = DCD_VERSION;
- dcd_v2->write_dcd_command.tag = DCD_COMMAND_TAG;
- dcd_v2->write_dcd_command.length = cpu_to_be16(
- dcd_len * sizeof(dcd_addr_data_t) + 4);
- dcd_v2->write_dcd_command.param = DCD_COMMAND_PARAM;
-}
-
-static int set_imx_hdr_v1(struct data_src *ds, uint32_t dcd_len,
+static int set_imx_hdr_v1(struct data_src *ds,
uint32_t entry_point, uint32_t flash_offset)
{
imx_header_v1_t *hdr_v1 = &ds->imxhdr->header.hdr_v1;
flash_header_v1_t *fhdr_v1 = &hdr_v1->fhdr;
- dcd_v1_t *dcd_v1 = &hdr_v1->dcd_table;
uint32_t hdr_base;
- uint32_t header_length = (((char *)&dcd_v1->addr_data[dcd_len].addr)
- - ((char *)ds->imxhdr));
+ uint32_t header_length = ((char *)ds->p_entry) + 4
+ - ((char *)ds->imxhdr);
/* Set magic number */
fhdr_v1->app_code_barker = APP_CODE_BARKER;
@@ -220,15 +213,13 @@ static int set_imx_hdr_v1(struct data_src *ds, uint32_t dcd_len,
return header_length;
}
-static int set_imx_hdr_v2(struct data_src *ds, uint32_t dcd_len,
+static int set_imx_hdr_v2(struct data_src *ds,
uint32_t entry_point, uint32_t flash_offset)
{
imx_header_v2_t *hdr_v2 = &ds->imxhdr->header.hdr_v2;
flash_header_v2_t *fhdr_v2 = &hdr_v2->fhdr;
uint32_t hdr_base;
- uint32_t header_length = (dcd_len) ?
- (char *)&hdr_v2->dcd_table.addr_data[dcd_len] -
- ((char *)ds->imxhdr) : offsetof(imx_header_v2_t, dcd_table);
+ uint32_t header_length = ((char *)ds->p_entry) - ((char *)ds->imxhdr);
/* Set magic number */
fhdr_v2->header.tag = IVT_HEADER_TAG; /* 0xD1 */
@@ -239,7 +230,7 @@ static int set_imx_hdr_v2(struct data_src *ds, uint32_t dcd_len,
fhdr_v2->reserved1 = fhdr_v2->reserved2 = 0;
fhdr_v2->self = hdr_base = entry_point - header_length;
- fhdr_v2->dcd_ptr = (dcd_len) ? hdr_base
+ fhdr_v2->dcd_ptr = (ds->p_dcd) ? hdr_base
+ offsetof(imx_header_v2_t, dcd_table) : 0;
fhdr_v2->boot_data_ptr = hdr_base
+ offsetof(imx_header_v2_t, boot_data);
@@ -256,15 +247,20 @@ static void set_hdr_func(struct data_src *ds, uint32_t imximage_version)
switch (imximage_version) {
case IMXIMAGE_V1:
ds->set_dcd_val = set_dcd_val_v1;
- set_dcd_rst = set_dcd_rst_v1;
ds->set_imx_hdr = set_imx_hdr_v1;
- max_dcd_entries = MAX_HW_CFG_SIZE_V1;
+ ds->p_entry = &ds->imxhdr->header.hdr_v1.dcd_table
+ .addr_data[0].type;
+ ds->p_max_dcd = &ds->imxhdr->header.hdr_v1.dcd_table
+ .addr_data[MAX_HW_CFG_SIZE_V1].type;
+ ds->imxhdr->header.hdr_v1.dcd_table.preamble.barker =
+ DCD_BARKER;
break;
case IMXIMAGE_V2:
ds->set_dcd_val = set_dcd_val_v2;
- set_dcd_rst = set_dcd_rst_v2;
ds->set_imx_hdr = set_imx_hdr_v2;
- max_dcd_entries = MAX_HW_CFG_SIZE_V2;
+ ds->p_entry = (uint32_t *)&ds->imxhdr->header.hdr_v2.dcd_table;
+ ds->p_max_dcd = (uint32_t *)
+ ((char *)ds->imxhdr + MAX_HEADER_SIZE);
break;
default:
err_imximage_version(imximage_version);
@@ -328,7 +324,7 @@ static void print_hdr_v2(struct imx_header *imx_hdr)
}
static void parse_cfg_cmd(struct data_src *ds, int32_t cmd, char *token,
- char *name, int lineno, int fld, int dcd_len)
+ char *name, int lineno, int fld)
{
int value;
static int cmd_ver_first = ~0;
@@ -359,7 +355,7 @@ static void parse_cfg_cmd(struct data_src *ds, int32_t cmd, char *token,
break;
case CMD_DATA:
value = get_cfg_value(token, name, lineno);
- (*ds->set_dcd_val)(ds, name, lineno, fld, value, dcd_len);
+ (*ds->set_dcd_val)(ds, name, lineno, fld, value);
if (unlikely(cmd_ver_first != 1))
cmd_ver_first = 0;
break;
@@ -367,7 +363,7 @@ static void parse_cfg_cmd(struct data_src *ds, int32_t cmd, char *token,
}
static void parse_cfg_fld(struct data_src *ds, int32_t *cmd,
- char *token, char *name, int lineno, int fld, int *dcd_len)
+ char *token, char *name, int lineno, int fld)
{
int value;
@@ -382,7 +378,7 @@ static void parse_cfg_fld(struct data_src *ds, int32_t *cmd,
}
break;
case CFG_REG_SIZE:
- parse_cfg_cmd(ds, *cmd, token, name, lineno, fld, *dcd_len);
+ parse_cfg_cmd(ds, *cmd, token, name, lineno, fld);
break;
case CFG_REG_ADDRESS:
case CFG_REG_VALUE:
@@ -390,16 +386,14 @@ static void parse_cfg_fld(struct data_src *ds, int32_t *cmd,
return;
value = get_cfg_value(token, name, lineno);
- (*ds->set_dcd_val)(ds, name, lineno, fld, value, *dcd_len);
-
- if (fld == CFG_REG_VALUE) {
- (*dcd_len)++;
- if (*dcd_len > max_dcd_entries) {
- fprintf(stderr, "Error: %s[%d] -"
- "DCD table exceeds maximum size(%d)\n",
- name, lineno, max_dcd_entries);
- exit(EXIT_FAILURE);
- }
+ (*ds->set_dcd_val)(ds, name, lineno, fld, value);
+ if (ds->p_entry > ds->p_max_dcd) {
+ uint32_t size = (char *)ds->p_max_dcd -
+ (char *)ds->imxhdr;
+ fprintf(stderr, "Error: %s[%d] -"
+ "header exceeds maximum size(%d)\n",
+ name, lineno, size);
+ exit(EXIT_FAILURE);
}
break;
default:
@@ -417,7 +411,6 @@ static int parse_cfg_file(struct imx_header *imxhdr, char *name,
int lineno = 0;
int fld;
size_t len;
- int dcd_len = 0;
int32_t cmd;
/* Be able to detect if the cfg file has no BOOT_FROM tag */
@@ -458,12 +451,10 @@ static int parse_cfg_file(struct imx_header *imxhdr, char *name,
break;
parse_cfg_fld(&ds, &cmd, token, name,
- lineno, fld, &dcd_len);
+ lineno, fld);
}
}
-
- (*set_dcd_rst)(imxhdr, dcd_len, name, lineno);
fclose(fd);
/* Exit if there is no BOOT_FROM field specifying the flash_offset */
@@ -472,7 +463,7 @@ static int parse_cfg_file(struct imx_header *imxhdr, char *name,
exit(EXIT_FAILURE);
}
/* Set the imx header */
- return (*ds.set_imx_hdr)(&ds, dcd_len, entry_point, g_flash_offset);
+ return (*ds.set_imx_hdr)(&ds, entry_point, g_flash_offset);
}
static int imximage_check_image_types(uint8_t type)
@@ -517,7 +508,11 @@ int imximage_vrec_header(struct mkimage_params *params,
{
struct imx_header *imxhdr;
- imxhdr = calloc(1, MAX_HEADER_SIZE);
+ /*
+ * A little extra space to avoid access violation on dcd table overflow.
+ * Overflow is checked after entry is added.
+ */
+ imxhdr = calloc(1, MAX_HEADER_SIZE + 32);
if (!imxhdr) {
fprintf(stderr, "Error: out of memory\n");
exit(EXIT_FAILURE);
diff --git a/tools/imximage.h b/tools/imximage.h
index 444ddce..196bb51 100644
--- a/tools/imximage.h
+++ b/tools/imximage.h
@@ -47,7 +47,6 @@
#define DCD_HEADER_TAG 0xD2
#define DCD_COMMAND_TAG 0xCC
#define DCD_VERSION 0x40
-#define DCD_COMMAND_PARAM 0x4
enum imximage_cmd {
CMD_INVALID,
@@ -160,21 +159,18 @@ struct imx_header {
};
struct data_src;
-typedef void (*set_dcd_val_t)(struct data_src *ds,
- char *name, int lineno,
- int fld, uint32_t value,
- uint32_t off);
+typedef void (*set_dcd_val_t)(struct data_src *ds, char *name,
+ int lineno, int fld, uint32_t value);
-typedef void (*set_dcd_rst_t)(struct imx_header *imxhdr,
- uint32_t dcd_len,
- char *name, int lineno);
-
-typedef int (*set_imx_hdr_t)(struct data_src *ds, uint32_t dcd_len,
- uint32_t entry_point, uint32_t flash_offset);
+typedef int (*set_imx_hdr_t)(struct data_src *ds, uint32_t entry_point,
+ uint32_t flash_offset);
struct data_src {
struct imx_header *imxhdr;
set_imx_hdr_t set_imx_hdr;
set_dcd_val_t set_dcd_val;
+ uint32_t *p_max_dcd;
+ uint32_t *p_entry;
+ write_dcd_command_t *p_dcd;
};
#endif /* _IMXIMAGE_H_ */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 15/32] tools: add parse_helper file
2012-10-04 1:47 ` [U-Boot] [PATCH V3 00/32] " Troy Kisky
` (13 preceding siblings ...)
2012-10-04 1:47 ` [U-Boot] [PATCH V3 14/32] imximage: enable word writes for version2 header Troy Kisky
@ 2012-10-04 1:47 ` Troy Kisky
2012-10-04 1:47 ` [U-Boot] [PATCH V3 16/32] imximage: use parse_helper functions Troy Kisky
` (19 subsequent siblings)
34 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-10-04 1:47 UTC (permalink / raw)
To: u-boot
This file can help you parse
configuration files.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
tools/Makefile | 2 +
tools/parse_helper.c | 173 ++++++++++++++++++++++++++++++++++++++++++++++++++
tools/parse_helper.h | 28 ++++++++
3 files changed, 203 insertions(+)
create mode 100644 tools/parse_helper.c
create mode 100644 tools/parse_helper.h
diff --git a/tools/Makefile b/tools/Makefile
index c31437e..a540274 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -94,6 +94,7 @@ NOPED_OBJ_FILES-y += aisimage.o
NOPED_OBJ_FILES-y += kwbimage.o
NOPED_OBJ_FILES-y += pblimage.o
NOPED_OBJ_FILES-y += imximage.o
+NOPED_OBJ_FILES-y += parse_helper.o
NOPED_OBJ_FILES-y += omapimage.o
NOPED_OBJ_FILES-y += mkenvimage.o
NOPED_OBJ_FILES-y += mkimage.o
@@ -208,6 +209,7 @@ $(obj)mkimage$(SFX): $(obj)aisimage.o \
$(obj)fit_image.o \
$(obj)image.o \
$(obj)imximage.o \
+ $(obj)parse_helper.o \
$(obj)kwbimage.o \
$(obj)pblimage.o \
$(obj)md5.o \
diff --git a/tools/parse_helper.c b/tools/parse_helper.c
new file mode 100644
index 0000000..0a5c5f6
--- /dev/null
+++ b/tools/parse_helper.c
@@ -0,0 +1,173 @@
+/*
+ * (C) Copyright 20012 Boundary Devices Inc, troy.kisky at boundarydevices.com
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+/* Required to obtain the getline prototype from stdio.h */
+#define _GNU_SOURCE
+
+#include "mkimage.h"
+#include <image.h>
+#include "parse_helper.h"
+
+int ph_open(struct parse_helper *ph, char *filename)
+{
+ ph->line = NULL;
+ ph->len = 0;
+ ph->fd = fopen(filename, "r");
+ ph->lineno = 0;
+ ph->cmd_started = 0;
+ ph->filename = filename;
+ ph->p = NULL;
+ return (!ph->fd) ? -1 : 0;
+}
+
+void ph_close(struct parse_helper *ph)
+{
+ fclose(ph->fd);
+ ph->fd = NULL;
+}
+
+int ph_skip_separators(struct parse_helper *ph)
+{
+ int line_no = ph->lineno;
+ char *p = ph->p;
+
+ for (;;) {
+ char c;
+ if (!p) {
+ if (getline(&ph->line, &ph->len, ph->fd) <= 0)
+ return -1;
+ ph->lineno++;
+ p = ph->line;
+ if (ph->cmd_started) {
+ fprintf(stderr, "warning: continuing command on"
+ " next line, line %s[%d](%s)\n",
+ ph->filename, ph->lineno, p);
+ }
+ }
+ c = *p;
+ if ((c == ' ') || (c == '\t')) {
+ p++;
+ continue;
+ }
+ /* Drop all text starting with '#' as comments */
+ if ((c == '#') || (c == '\r') || (c == '\n')
+ || !c) {
+ p = NULL;
+ continue;
+ }
+ if (c == ';') {
+ if (ph->cmd_started) {
+ fprintf(stderr, "Error: command not "
+ "finished:%s[%d](%s)\n",
+ ph->filename, ph->lineno, p);
+ exit(EXIT_FAILURE);
+ }
+ p++;
+ continue;
+ }
+ if (!ph->cmd_started && line_no == ph->lineno) {
+ fprintf(stderr, "Error: extra data at end "
+ "of line %s[%d](%s)\n",
+ ph->filename, ph->lineno, p);
+ exit(EXIT_FAILURE);
+ }
+ ph->p = p;
+ return 0;
+ }
+}
+
+int ph_skip_comma(struct parse_helper *ph)
+{
+ char *p = ph->p;
+
+ for (;;) {
+ char c = *p++;
+ if ((c == '#') || (c == '\r') || (c == '\n') || !c)
+ return 0;
+ if (c == ',') {
+ ph->p = p;
+ ph_skip_separators(ph);
+ return 1;
+ }
+ if ((c != ' ') && (c == '\t'))
+ return 0;
+ }
+}
+
+int ph_get_value(struct parse_helper *ph, uint32_t *pval)
+{
+ char *endptr;
+ uint32_t value;
+
+ if (ph_skip_separators(ph))
+ return -1;
+ errno = 0;
+ value = strtoul(ph->p, &endptr, 16);
+ if (errno || (ph->p == endptr))
+ return -1;
+ *pval = value;
+ ph->p = endptr;
+ return 0;
+}
+
+/*
+ * Comma separator optional
+ * Input:
+ * ph - input source
+ * data - array to fill in
+ * cnt - exact number of elements to parse
+ * Return: number of elements parsed, or error
+ */
+int ph_get_array(struct parse_helper *ph, uint32_t *data, int cnt)
+{
+ int i = 0;
+
+ for (;;) {
+ int ret = ph_get_value(ph, &data[i++]);
+ if (ret)
+ return ret;
+ if (i >= cnt)
+ break;
+ ph_skip_comma(ph); /* comma is optional */
+ }
+ return i;
+}
+
+static char *grab_token(char *dest, int size, char *src)
+{
+ while (size) {
+ char c = *src;
+ if ((c == ' ') || (c == '\t') || (c == '\r') || (c == '\n')
+ || (c == '#') || !c)
+ break;
+ *dest++ = c;
+ size--;
+ src++;
+ }
+ if (!size)
+ return NULL;
+ *dest = 0;
+ return src;
+}
+
+int ph_get_table_entry_id(struct parse_helper *ph,
+ const table_entry_t *table, const char *table_name)
+{
+ int val;
+ char token[16];
+ char *p;
+
+ if (ph_skip_separators(ph))
+ return -1;
+ p = grab_token(token, sizeof(token), ph->p);
+ if (!p)
+ return -1;
+ val = get_table_entry_id(table, table_name, token);
+ if (val != -1)
+ ph->p = p;
+ return val;
+}
+
diff --git a/tools/parse_helper.h b/tools/parse_helper.h
new file mode 100644
index 0000000..1ff98a3
--- /dev/null
+++ b/tools/parse_helper.h
@@ -0,0 +1,28 @@
+/*
+ * (C) Copyright 20012 Boundary Devices Inc, troy.kisky at boundarydevices.com
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef _PARSE_HELPER_H_
+#define _PARSE_HELPER_H_
+
+struct parse_helper {
+ char *line;
+ size_t len;
+ FILE *fd;
+ int lineno;
+ char cmd_started;
+ char *filename;
+ char *p;
+};
+
+int ph_open(struct parse_helper *ph, char *filename);
+void ph_close(struct parse_helper *ph);
+int ph_skip_separators(struct parse_helper *ph);
+int ph_skip_comma(struct parse_helper *ph);
+int ph_get_value(struct parse_helper *ph, uint32_t *pval);
+int ph_get_array(struct parse_helper *ph, uint32_t *data, int cnt);
+int ph_get_table_entry_id(struct parse_helper *ph,
+ const table_entry_t *table, const char *table_name);
+#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 16/32] imximage: use parse_helper functions
2012-10-04 1:47 ` [U-Boot] [PATCH V3 00/32] " Troy Kisky
` (14 preceding siblings ...)
2012-10-04 1:47 ` [U-Boot] [PATCH V3 15/32] tools: add parse_helper file Troy Kisky
@ 2012-10-04 1:47 ` Troy Kisky
2012-10-04 1:47 ` [U-Boot] [PATCH V3 17/32] imximage.cfg: run files through C preprocessor Troy Kisky
` (18 subsequent siblings)
34 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-10-04 1:47 UTC (permalink / raw)
To: u-boot
Use parse_helper functions to pulling tokens instead
of pushing them.
Remove need for switch statements to process commands.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
v2: uses file parse_helper added in previous patch
changed patch subject, was cleanup parsing
---
tools/imximage.c | 267 +++++++++++++++++++-----------------------------------
tools/imximage.h | 17 ++--
2 files changed, 101 insertions(+), 183 deletions(-)
diff --git a/tools/imximage.c b/tools/imximage.c
index 29a12bc..c13fee1 100644
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -25,9 +25,6 @@
* MA 02111-1307 USA
*/
-/* Required to obtain the getline prototype from stdio.h */
-#define _GNU_SOURCE
-
#include "mkimage.h"
#include <image.h>
#include "imximage.h"
@@ -70,21 +67,6 @@ static uint32_t g_flash_offset;
static struct image_type_params imximage_params;
-static uint32_t get_cfg_value(char *token, char *name, int linenr)
-{
- char *endptr;
- uint32_t value;
-
- errno = 0;
- value = strtoul(token, &endptr, 16);
- if (errno || (token == endptr)) {
- fprintf(stderr, "Error: %s[%d] - Invalid hex data(%s)\n",
- name, linenr, token);
- exit(EXIT_FAILURE);
- }
- return value;
-}
-
static uint32_t detect_imximage_version(struct imx_header *imx_hdr)
{
imx_header_v1_t *hdr_v1 = &imx_hdr->header.hdr_v1;
@@ -112,53 +94,36 @@ static void err_imximage_version(int version)
exit(EXIT_FAILURE);
}
-static void set_dcd_val_v1(struct data_src *ds, char *name, int lineno,
- int fld, uint32_t value)
+static int set_dcd_val_v1(struct data_src *ds, uint32_t *data)
{
dcd_v1_t *dcd_v1 = &ds->imxhdr->header.hdr_v1.dcd_table;
+ uint32_t val = *data++;
- switch (fld) {
- case CFG_REG_SIZE:
- /* Byte, halfword, word */
- if ((value != 1) && (value != 2) && (value != 4)) {
- fprintf(stderr, "Error: %s[%d] - "
- "Invalid register size " "(%d)\n",
- name, lineno, value);
- exit(EXIT_FAILURE);
- }
- *ds->p_entry++ = value;
- break;
- case CFG_REG_ADDRESS:
- *ds->p_entry++ = value;
- break;
- case CFG_REG_VALUE:
- *ds->p_entry++ = value;
- dcd_v1->preamble.length = (char *)ds->p_entry
- - (char *)&dcd_v1->addr_data[0].type;
- break;
- default:
- break;
-
+ /* Byte, halfword, word */
+ if ((val != 1) && (val != 2) && (val != 4)) {
+ fprintf(stderr, "Error: Invalid register size (%d)\n", val);
+ return -1;
}
+ *ds->p_entry++ = val;
+ *ds->p_entry++ = *data++;
+ *ds->p_entry++ = *data++;
+ dcd_v1->preamble.length = (char *)ds->p_entry - (char *)&dcd_v1->
+ addr_data[0].type;
+ return 0;
}
-static void set_dcd_val_v2(struct data_src *ds, char *name, int lineno,
- int fld, uint32_t value)
+static int set_dcd_val_v2(struct data_src *ds, uint32_t *data)
{
uint32_t len;
dcd_v2_t *dcd_v2 = &ds->imxhdr->header.hdr_v2.dcd_table;
+ uint32_t val = *data++;
- switch (fld) {
- case CFG_REG_SIZE:
- /* Byte, halfword, word */
- if ((value != 1) && (value != 2) && (value != 4)) {
- fprintf(stderr, "Error: %s[%d] - "
- "Invalid register size " "(%d)\n",
- name, lineno, value);
- exit(EXIT_FAILURE);
- }
- if (ds->p_dcd && (ds->p_dcd->param == value))
- break;
+ /* Byte, halfword, word */
+ if ((val != 1) && (val != 2) && (val != 4)) {
+ fprintf(stderr, "Error: Invalid register size (%d)\n", val);
+ return -1;
+ }
+ if (!(ds->p_dcd && (ds->p_dcd->param == val))) {
if (!ds->p_dcd) {
dcd_v2->header.tag = DCD_HEADER_TAG;
dcd_v2->header.version = DCD_VERSION;
@@ -166,24 +131,19 @@ static void set_dcd_val_v2(struct data_src *ds, char *name, int lineno,
} else {
ds->p_dcd = (write_dcd_command_t *)ds->p_entry;
}
- ds->p_dcd->param = value;
+ ds->p_dcd->param = val;
ds->p_dcd->tag = DCD_COMMAND_TAG;
ds->p_entry = (uint32_t *)(ds->p_dcd + 1);
- break;
- case CFG_REG_ADDRESS:
- *ds->p_entry++ = cpu_to_be32(value);
- break;
- case CFG_REG_VALUE:
- *ds->p_entry++ = cpu_to_be32(value);
- len = (char *)ds->p_entry - (char *)&dcd_v2->header;
- dcd_v2->header.length = cpu_to_be16(len);
- len = (char *)ds->p_entry - (char *)ds->p_dcd;
- ds->p_dcd->length = cpu_to_be16(len);
- break;
- default:
- break;
-
}
+ val = *data++;
+ *ds->p_entry++ = cpu_to_be32(val);
+ val = *data++;
+ *ds->p_entry++ = cpu_to_be32(val);
+ len = (char *)ds->p_entry - (char *)&dcd_v2->header;
+ dcd_v2->header.length = cpu_to_be16(len);
+ len = (char *)ds->p_entry - (char *)ds->p_dcd;
+ ds->p_dcd->length = cpu_to_be16(len);
+ return 0;
}
static int set_imx_hdr_v1(struct data_src *ds,
@@ -323,95 +283,71 @@ static void print_hdr_v2(struct imx_header *imx_hdr)
printf("Entry Point: %08x\n", (uint32_t)fhdr_v2->entry);
}
-static void parse_cfg_cmd(struct data_src *ds, int32_t cmd, char *token,
- char *name, int lineno, int fld)
+static int parse_cmd_data(struct data_src *ds)
+{
+ uint32_t data[3];
+ int ret = ph_get_array(&ds->ph, data, 3);
+
+ if (ret < 0)
+ return ret;
+ ret = (*ds->set_dcd_val)(ds, data);
+ if (ret)
+ return ret;
+ if (ds->p_entry > ds->p_max_dcd) {
+ uint32_t size = (char *)ds->p_max_dcd - (char *)ds->imxhdr;
+ fprintf(stderr, "Error: header exceeds maximum size(%d)\n",
+ size);
+ return -1;
+ }
+ return 0;
+}
+
+static int parse_image_version(struct data_src *ds)
{
- int value;
- static int cmd_ver_first = ~0;
+ int ret;
uint32_t imximage_version;
- switch (cmd) {
- case CMD_IMAGE_VERSION:
- imximage_version = get_cfg_value(token, name, lineno);
- if (cmd_ver_first == 0) {
- fprintf(stderr, "Error: %s[%d] - IMAGE_VERSION "
- "command need be the first before other "
- "valid command in the file\n", name, lineno);
- exit(EXIT_FAILURE);
- }
- cmd_ver_first = 1;
- set_hdr_func(ds, imximage_version);
- break;
- case CMD_BOOT_FROM:
- g_flash_offset = get_table_entry_id(imximage_bootops,
- "imximage boot option", token);
- if (g_flash_offset == -1) {
- fprintf(stderr, "Error: %s[%d] -Invalid boot device"
- "(%s)\n", name, lineno, token);
- exit(EXIT_FAILURE);
- }
- if (unlikely(cmd_ver_first != 1))
- cmd_ver_first = 0;
- break;
- case CMD_DATA:
- value = get_cfg_value(token, name, lineno);
- (*ds->set_dcd_val)(ds, name, lineno, fld, value);
- if (unlikely(cmd_ver_first != 1))
- cmd_ver_first = 0;
- break;
+ ret = ph_get_value(&ds->ph, &imximage_version);
+ if (ret)
+ return ret;
+ if (ds->cmd_cnt) {
+ fprintf(stderr, "Error: IMAGE_VERSION command needs be "
+ "before other valid commands in the file\n");
+ return -1;
}
+ set_hdr_func(ds, imximage_version);
+ return 0;
}
-static void parse_cfg_fld(struct data_src *ds, int32_t *cmd,
- char *token, char *name, int lineno, int fld)
+static int parse_boot_from(struct data_src *ds)
{
- int value;
-
- switch (fld) {
- case CFG_COMMAND:
- *cmd = get_table_entry_id(imximage_cmds,
- "imximage commands", token);
- if (*cmd < 0) {
- fprintf(stderr, "Error: %s[%d] - Invalid command"
- "(%s)\n", name, lineno, token);
- exit(EXIT_FAILURE);
- }
- break;
- case CFG_REG_SIZE:
- parse_cfg_cmd(ds, *cmd, token, name, lineno, fld);
- break;
- case CFG_REG_ADDRESS:
- case CFG_REG_VALUE:
- if (*cmd != CMD_DATA)
- return;
-
- value = get_cfg_value(token, name, lineno);
- (*ds->set_dcd_val)(ds, name, lineno, fld, value);
- if (ds->p_entry > ds->p_max_dcd) {
- uint32_t size = (char *)ds->p_max_dcd -
- (char *)ds->imxhdr;
- fprintf(stderr, "Error: %s[%d] -"
- "header exceeds maximum size(%d)\n",
- name, lineno, size);
- exit(EXIT_FAILURE);
- }
- break;
- default:
- break;
+ g_flash_offset = ph_get_table_entry_id(&ds->ph, imximage_bootops,
+ "imximage boot option");
+ if (g_flash_offset == -1) {
+ fprintf(stderr, "Error: Invalid boot device\n");
+ return -1;
}
+ return 0;
+}
+
+static const parse_fld_t cmd_table[] = {
+ parse_image_version, parse_boot_from, parse_cmd_data
+};
+
+static int parse_command(struct data_src *ds)
+{
+ int cmd = ph_get_table_entry_id(&ds->ph, imximage_cmds,
+ "imximage commands");
+ if (cmd < 0)
+ return cmd;
+ return cmd_table[cmd](ds);
}
static int parse_cfg_file(struct imx_header *imxhdr, char *name,
uint32_t entry_point)
{
struct data_src ds;
- FILE *fd = NULL;
- char *line = NULL;
- char *token, *saveptr1, *saveptr2;
- int lineno = 0;
- int fld;
- size_t len;
- int32_t cmd;
+ struct parse_helper *ph = &ds.ph;
/* Be able to detect if the cfg file has no BOOT_FROM tag */
g_flash_offset = FLASH_OFFSET_UNDEFINED;
@@ -423,8 +359,7 @@ static int parse_cfg_file(struct imx_header *imxhdr, char *name,
* set up function ptr group to V1 by default.
*/
set_hdr_func(&ds, IMXIMAGE_V1);
- fd = fopen(name, "r");
- if (fd == 0) {
+ if (ph_open(ph, name)) {
fprintf(stderr, "Error: %s - Can't open DCD file\n", name);
exit(EXIT_FAILURE);
}
@@ -432,31 +367,19 @@ static int parse_cfg_file(struct imx_header *imxhdr, char *name,
/* Very simple parsing, line starting with # are comments
* and are dropped
*/
- while ((getline(&line, &len, fd)) > 0) {
- lineno++;
-
- token = strtok_r(line, "\r\n", &saveptr1);
- if (token == NULL)
- continue;
-
- /* Check inside the single line */
- for (fld = CFG_COMMAND, cmd = CMD_INVALID,
- line = token; ; line = NULL, fld++) {
- token = strtok_r(line, " \t", &saveptr2);
- if (token == NULL)
- break;
-
- /* Drop all text starting with '#' as comments */
- if (token[0] == '#')
- break;
-
- parse_cfg_fld(&ds, &cmd, token, name,
- lineno, fld);
+ for (;;) {
+ ph->cmd_started = 0;
+ if (ph_skip_separators(ph))
+ break;
+ ph->cmd_started = 1;
+ if (parse_command(&ds)) {
+ fprintf(stderr, "Error: invalid token %s[%d](%s)\n",
+ name, ph->lineno, ph->p);
+ exit(EXIT_FAILURE);
}
-
+ ds.cmd_cnt++;
}
- fclose(fd);
-
+ ph_close(ph);
/* Exit if there is no BOOT_FROM field specifying the flash_offset */
if (g_flash_offset == FLASH_OFFSET_UNDEFINED) {
fprintf(stderr, "Error: No BOOT_FROM tag in %s\n", name);
@@ -538,12 +461,12 @@ static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd,
int imximage_check_params(struct mkimage_params *params)
{
if (!params)
- return CFG_INVALID;
+ return -1;
if (!strlen(params->imagename)) {
fprintf(stderr, "Error: %s - Configuration file not specified, "
"it is needed for imximage generation\n",
params->cmdname);
- return CFG_INVALID;
+ return -1;
}
/*
* Check parameters:
diff --git a/tools/imximage.h b/tools/imximage.h
index 196bb51..6bcd082 100644
--- a/tools/imximage.h
+++ b/tools/imximage.h
@@ -23,6 +23,7 @@
#ifndef _IMXIMAGE_H_
#define _IMXIMAGE_H_
+#include "parse_helper.h"
#define MAX_HW_CFG_SIZE_V2 121 /* Max number of registers imx can set for v2 */
#define MAX_HW_CFG_SIZE_V1 60 /* Max number of registers imx can set for v1 */
@@ -49,20 +50,11 @@
#define DCD_VERSION 0x40
enum imximage_cmd {
- CMD_INVALID,
CMD_IMAGE_VERSION,
CMD_BOOT_FROM,
CMD_DATA
};
-enum imximage_fld_types {
- CFG_INVALID = -1,
- CFG_COMMAND,
- CFG_REG_SIZE,
- CFG_REG_ADDRESS,
- CFG_REG_VALUE
-};
-
enum imximage_version {
IMXIMAGE_VER_INVALID = -1,
IMXIMAGE_V1 = 1,
@@ -159,14 +151,17 @@ struct imx_header {
};
struct data_src;
-typedef void (*set_dcd_val_t)(struct data_src *ds, char *name,
- int lineno, int fld, uint32_t value);
+typedef int (*parse_fld_t)(struct data_src *ds);
+
+typedef int (*set_dcd_val_t)(struct data_src *ds, uint32_t *data);
typedef int (*set_imx_hdr_t)(struct data_src *ds, uint32_t entry_point,
uint32_t flash_offset);
struct data_src {
+ struct parse_helper ph;
struct imx_header *imxhdr;
+ int cmd_cnt;
set_imx_hdr_t set_imx_hdr;
set_dcd_val_t set_dcd_val;
uint32_t *p_max_dcd;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 17/32] imximage.cfg: run files through C preprocessor
2012-10-04 1:47 ` [U-Boot] [PATCH V3 00/32] " Troy Kisky
` (15 preceding siblings ...)
2012-10-04 1:47 ` [U-Boot] [PATCH V3 16/32] imximage: use parse_helper functions Troy Kisky
@ 2012-10-04 1:47 ` Troy Kisky
2012-10-07 18:19 ` Eric Nelson
2012-10-08 13:38 ` Stefano Babic
2012-10-04 1:47 ` [U-Boot] [PATCH V3 18/32] mx6q_4x_mt41j128.cfg: use symbols instead of hardcoded constants Troy Kisky
` (17 subsequent siblings)
34 siblings, 2 replies; 430+ messages in thread
From: Troy Kisky @ 2012-10-04 1:47 UTC (permalink / raw)
To: u-boot
The '#' used as comments in the files cause the preprocessor
trouble, so change to /* */.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
Makefile | 3 +-
board/esg/ima3-mx53/imximage.cfg | 120 ++++++-----
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 90 ++++----
board/freescale/mx25pdk/imximage.cfg | 77 +++----
board/freescale/mx51evk/imximage.cfg | 114 +++++-----
board/freescale/mx53ard/imximage_dd3.cfg | 83 ++++----
board/freescale/mx53evk/imximage.cfg | 86 ++++----
board/freescale/mx53loco/imximage.cfg | 83 ++++----
board/freescale/mx53smd/imximage.cfg | 83 ++++----
board/freescale/mx6qarm2/imximage.cfg | 88 ++++----
board/genesi/mx51_efikamx/imximage_mx.cfg | 132 ++++++------
board/genesi/mx51_efikamx/imximage_sb.cfg | 126 +++++------
board/ttcontrol/vision2/imximage_hynix.cfg | 295 ++++++++++++++------------
13 files changed, 727 insertions(+), 653 deletions(-)
diff --git a/Makefile b/Makefile
index a40d4cc..64ff1b8 100644
--- a/Makefile
+++ b/Makefile
@@ -431,7 +431,8 @@ $(obj)u-boot.img: $(obj)u-boot.bin
-d $< $@
$(obj)u-boot.imx: $(obj)u-boot.bin
- $(obj)tools/mkimage -n $(CONFIG_IMX_CONFIG) -T imximage \
+ $(CC) -E -x c $(CONFIG_IMX_CONFIG) -I./include -o $(obj)imxcfg.imx
+ $(obj)tools/mkimage -n $(obj)imxcfg.imx -T imximage \
-e $(CONFIG_SYS_TEXT_BASE) -d $< $@
$(obj)u-boot.kwb: $(obj)u-boot.bin
diff --git a/board/esg/ima3-mx53/imximage.cfg b/board/esg/ima3-mx53/imximage.cfg
index fa6b42d..fce7492 100644
--- a/board/esg/ima3-mx53/imximage.cfg
+++ b/board/esg/ima3-mx53/imximage.cfg
@@ -1,50 +1,52 @@
-#
-# (C) Copyright 2012
-# Stefano Babic DENX Software Engineering sbabic at denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not write to the Free Software
-# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
-# MA 02110-1301 USA
-#
-# Refer docs/README.imxmage for more details about how-to configure
-# and create imximage boot image
-#
-# The syntax is taken as close as possible with the kwbimage
-
-# image version
+/*
+ * (C) Copyright 2012
+ * Stefano Babic DENX Software Engineering sbabic at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+/* image version */
IMAGE_VERSION 2
-# Boot Device : one of
-# spi, sd (the board has no nand neither onenand)
-
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
BOOT_FROM nor
-# Device Configuration Data (DCD)
-#
-# Each entry must have the format:
-# Addr-type Address Value
-#
-# where:
-# Addr-type register length (1,2 or 4 bytes)
-# Address absolute address of the register
-# value value to be stored in the register
-
-# IOMUX for RAM only
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+/* IOMUX for RAM only */
DATA 4 0x53fa8554 0x300020
DATA 4 0x53fa8560 0x300020
DATA 4 0x53fa8594 0x300020
@@ -72,37 +74,47 @@ DATA 4 0x53fa86fc 0x0
DATA 4 0x53fa86f4 0x0
DATA 4 0x53fa8714 0x0
DATA 4 0x53fa8724 0x4000000
-#
-# DDR RAM
+
+/* DDR RAM */
DATA 4 0x63fd9088 0x40404040
DATA 4 0x63fd9090 0x40404040
DATA 4 0x63fd907C 0x01420143
DATA 4 0x63fd9080 0x01450146
DATA 4 0x63fd9018 0x00111740
DATA 4 0x63fd9000 0x84190000
-# esdcfgX
+
+/* esdcfgX */
DATA 4 0x63fd900C 0x9f5152e3
DATA 4 0x63fd9010 0xb68e8a63
DATA 4 0x63fd9014 0x01ff00db
-# Read/Write command delay
+
+/* Read/Write command delay */
DATA 4 0x63fd902c 0x000026d2
-# Out of reset delays
+
+/* Out of reset delays */
DATA 4 0x63fd9030 0x00ff0e21
-# ESDCTL ODT timing control
+
+/* ESDCTL ODT timing control */
DATA 4 0x63fd9008 0x12273030
-# ESDCTL power down control
+
+/* ESDCTL power down control */
DATA 4 0x63fd9004 0x0002002d
-# Set registers in DDR memory chips
+
+/* Set registers in DDR memory chips */
DATA 4 0x63fd901c 0x00008032
DATA 4 0x63fd901c 0x00008033
DATA 4 0x63fd901c 0x00028031
DATA 4 0x63fd901c 0x052080b0
DATA 4 0x63fd901c 0x04008040
-# ESDCTL refresh control
+
+/* ESDCTL refresh control */
DATA 4 0x63fd9020 0x00005800
-# PHY ZQ HW control
+
+/* PHY ZQ HW control */
DATA 4 0x63fd9040 0x05380003
-# PHY ODT control
+
+/* PHY ODT control */
DATA 4 0x63fd9058 0x00022222
-# start DDR3
+
+/* start DDR3 */
DATA 4 0x63fd901c 0x00000000
diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
index 62498ab..c86cd40 100644
--- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
@@ -1,47 +1,51 @@
-# Copyright (C) 2011 Freescale Semiconductor, Inc.
-# Jason Liu <r64343@freescale.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not write to the Free Software
-# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
-# MA 02110-1301 USA
-#
-# Refer docs/README.imxmage for more details about how-to configure
-# and create imximage boot image
-#
-# The syntax is taken as close as possible with the kwbimage
-
-# image version
-
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * Jason Liu <r64343@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
IMAGE_VERSION 2
-# Boot Device : one of
-# spi, sd (the board has no nand neither onenand)
-
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
BOOT_FROM sd
-# Device Configuration Data (DCD)
-#
-# Each entry must have the format:
-# Addr-type Address Value
-#
-# where:
-# Addr-type register length (1,2 or 4 bytes)
-# Address absolute address of the register
-# value value to be stored in the register
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
DATA 4 0x020e05a8 0x00000030
DATA 4 0x020e05b0 0x00000030
DATA 4 0x020e0524 0x00000030
@@ -154,7 +158,7 @@ DATA 4 0x021b48b8 0x00000800
DATA 4 0x021b001c 0x00000000
DATA 4 0x021b0404 0x00011006
-# set the default clock gate to save power
+/* set the default clock gate to save power */
DATA 4 0x020c4068 0x00C03F3F
DATA 4 0x020c406c 0x0030FC03
DATA 4 0x020c4070 0x0FFFC000
@@ -163,8 +167,8 @@ DATA 4 0x020c4078 0x00FFF300
DATA 4 0x020c407c 0x0F0000C3
DATA 4 0x020c4080 0x000003FF
-# enable AXI cache for VDOA/VPU/IPU
+/* enable AXI cache for VDOA/VPU/IPU */
DATA 4 0x020e0010 0xF00000CF
-# set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
DATA 4 0x020e0018 0x007F007F
DATA 4 0x020e001c 0x007F007F
diff --git a/board/freescale/mx25pdk/imximage.cfg b/board/freescale/mx25pdk/imximage.cfg
index f7af7ff..c42a283 100644
--- a/board/freescale/mx25pdk/imximage.cfg
+++ b/board/freescale/mx25pdk/imximage.cfg
@@ -1,46 +1,49 @@
-#
-# (C) Copyright 2009
-# Stefano Babic DENX Software Engineering sbabic at denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# Refer docs/README.imxmage for more details about how-to configure
-# and create imximage boot image
-#
-# The syntax is taken as close as possible with the kwbimage
-
-# Boot Device : one of
-# spi, sd (the board has no nand neither onenand)
+/*
+ * (C) Copyright 2009
+ * Stefano Babic DENX Software Engineering sbabic at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
BOOT_FROM sd
-# Device Configuration Data (DCD)
-#
-# Each entry must have the format:
-# Addr-type Address Value
-#
-# where:
-# Addr-type register length (1,2 or 4 bytes)
-# Address absolute address of the register
-# value value to be stored in the register
-
-# EIM config-CS5 init -- CPLD
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+/* EIM config-CS5 init -- CPLD */
DATA 4 0xB8002050 0x0000D843
DATA 4 0xB8002054 0x22252521
DATA 4 0xB8002058 0x22220A00
-# DDR2 init
+/* DDR2 init */
DATA 4 0xB8001004 0x0076E83A
DATA 4 0xB8001010 0x00000204
DATA 4 0xB8001000 0x92210000
@@ -67,7 +70,7 @@ DATA 4 0x43FAC454 0x00001000
DATA 4 0x53F80008 0x20034000
-# Enable the clocks
+/* Enable the clocks */
DATA 4 0x53f8000c 0x1fffffff
DATA 4 0x53f80010 0xffffffff
DATA 4 0x53f80014 0xfdfff
diff --git a/board/freescale/mx51evk/imximage.cfg b/board/freescale/mx51evk/imximage.cfg
index a875e8f..3e141ee 100644
--- a/board/freescale/mx51evk/imximage.cfg
+++ b/board/freescale/mx51evk/imximage.cfg
@@ -1,46 +1,50 @@
-#
-# (C Copyright 2009
-# Stefano Babic DENX Software Engineering sbabic at denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not write to the Free Software
-# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
-# MA 02110-1301 USA
-#
-# Refer docs/README.imxmage for more details about how-to configure
-# and create imximage boot image
-#
-# The syntax is taken as close as possible with the kwbimage
-
-# Boot Device : one of
-# spi, sd (the board has no nand neither onenand)
+/*
+ * (C Copyright 2009
+ * Stefano Babic DENX Software Engineering sbabic at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
BOOT_FROM spi
-# Device Configuration Data (DCD)
-#
-# Each entry must have the format:
-# Addr-type Address Value
-#
-# where:
-# Addr-type register length (1,2 or 4 bytes)
-# Address absolute address of the register
-# value value to be stored in the register
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
-# Setting IOMUXC
+/* Setting IOMUXC */
DATA 4 0x73FA88a0 0x200
DATA 4 0x73FA850c 0x20c5
DATA 4 0x73FA8510 0x20c5
@@ -65,22 +69,24 @@ DATA 4 0x73FA88a4 0x6
DATA 4 0x73FA88ac 0x6
DATA 4 0x73FA88b8 0x6
-# Setting DDR for micron
-# 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
-# CAS=3 BL=4
-# ESDCTL_ESDCTL0
+/*
+ * Setting DDR for micron
+ * 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
+ * CAS=3 BL=4
+ */
+/* ESDCTL_ESDCTL0 */
DATA 4 0x83FD9000 0x82a20000
-# ESDCTL_ESDCTL1
+/* ESDCTL_ESDCTL1 */
DATA 4 0x83FD9008 0x82a20000
-# ESDCTL_ESDMISC
+/* ESDCTL_ESDMISC */
DATA 4 0x83FD9010 0x000ad0d0
-# ESDCTL_ESDCFG0
+/* ESDCTL_ESDCFG0 */
DATA 4 0x83FD9004 0x333574aa
-# ESDCTL_ESDCFG1
+/* ESDCTL_ESDCFG1 */
DATA 4 0x83FD900C 0x333574aa
-# Init DRAM on CS0
-# ESDCTL_ESDSCR
+/* Init DRAM on CS0 */
+/* ESDCTL_ESDSCR */
DATA 4 0x83FD9014 0x04008008
DATA 4 0x83FD9014 0x0000801a
DATA 4 0x83FD9014 0x0000801b
@@ -94,7 +100,7 @@ DATA 4 0x83FD9014 0x03808019
DATA 4 0x83FD9014 0x00408019
DATA 4 0x83FD9014 0x00008000
-# Init DRAM on CS1
+/* Init DRAM on CS1 */
DATA 4 0x83FD9014 0x0400800c
DATA 4 0x83FD9014 0x0000801e
DATA 4 0x83FD9014 0x0000801f
@@ -108,12 +114,12 @@ DATA 4 0x83FD9014 0x0380801d
DATA 4 0x83FD9014 0x0040801d
DATA 4 0x83FD9014 0x00008004
-# Write to CTL0
+/* Write to CTL0 */
DATA 4 0x83FD9000 0xb2a20000
-# Write to CTL1
+/* Write to CTL1 */
DATA 4 0x83FD9008 0xb2a20000
-# ESDMISC
+/* ESDMISC */
DATA 4 0x83FD9010 0x000ad6d0
-#ESDCTL_ESDCDLYGD
+/* ESDCTL_ESDCDLYGD */
DATA 4 0x83FD9034 0x90000000
DATA 4 0x83FD9014 0x00000000
diff --git a/board/freescale/mx53ard/imximage_dd3.cfg b/board/freescale/mx53ard/imximage_dd3.cfg
index 614d29e..4633e4d 100644
--- a/board/freescale/mx53ard/imximage_dd3.cfg
+++ b/board/freescale/mx53ard/imximage_dd3.cfg
@@ -1,48 +1,51 @@
-#
-# (C) Copyright 2009
-# Stefano Babic DENX Software Engineering sbabic at denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not write to the Free Software
-# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
-# MA 02110-1301 USA
-#
-# Refer docs/README.imxmage for more details about how-to configure
-# and create imximage boot image
-#
-# The syntax is taken as close as possible with the kwbimage
-
-# image version
+/*
+ * (C) Copyright 2009
+ * Stefano Babic DENX Software Engineering sbabic at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+/* image version */
IMAGE_VERSION 2
-# Boot Device : one of
-# spi, sd (the board has no nand neither onenand)
-
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
BOOT_FROM sd
-# Device Configuration Data (DCD)
-#
-# Each entry must have the format:
-# Addr-type Address Value
-#
-# where:
-# Addr-type register length (1,2 or 4 bytes)
-# Address absolute address of the register
-# value value to be stored in the register
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
DATA 4 0x53fa8554 0x00300000
DATA 4 0x53fa8558 0x00300040
DATA 4 0x53fa8560 0x00300000
diff --git a/board/freescale/mx53evk/imximage.cfg b/board/freescale/mx53evk/imximage.cfg
index 915fb2c..1cd61d5 100644
--- a/board/freescale/mx53evk/imximage.cfg
+++ b/board/freescale/mx53evk/imximage.cfg
@@ -1,50 +1,52 @@
-#
-# (C Copyright 2009
-# Stefano Babic DENX Software Engineering sbabic at denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not write to the Free Software
-# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
-# MA 02110-1301 USA
-#
-# Refer docs/README.imxmage for more details about how-to configure
-# and create imximage boot image
-#
-# The syntax is taken as close as possible with the kwbimage
-
-# image version
+/*
+ * (C Copyright 2009
+ * Stefano Babic DENX Software Engineering sbabic at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+/* image version */
IMAGE_VERSION 2
-# Boot Device : one of
-# spi, sd (the board has no nand neither onenand)
-
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
BOOT_FROM sd
-# Device Configuration Data (DCD)
-#
-# Each entry must have the format:
-# Addr-type Address Value
-#
-# where:
-# Addr-type register length (1,2 or 4 bytes)
-# Address absolute address of the register
-# value value to be stored in the register
-
-# Setting IOMUXC
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+/* Setting IOMUXC */
DATA 4 0x53fa8554 0x00200000
DATA 4 0x53fa8560 0x00200000
DATA 4 0x53fa8594 0x00200000
diff --git a/board/freescale/mx53loco/imximage.cfg b/board/freescale/mx53loco/imximage.cfg
index 2ce5f8d..e6b90c1 100644
--- a/board/freescale/mx53loco/imximage.cfg
+++ b/board/freescale/mx53loco/imximage.cfg
@@ -1,48 +1,51 @@
-# Copyright (C) 2011 Freescale Semiconductor, Inc.
-# Jason Liu <r64343@freescale.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not write to the Free Software
-# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
-# MA 02110-1301 USA
-#
-# Refer docs/README.imxmage for more details about how-to configure
-# and create imximage boot image
-#
-# The syntax is taken as close as possible with the kwbimage
-
-# image version
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * Jason Liu <r64343@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+/* image version */
IMAGE_VERSION 2
-# Boot Device : one of
-# spi, sd (the board has no nand neither onenand)
-
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
BOOT_FROM sd
-# Device Configuration Data (DCD)
-#
-# Each entry must have the format:
-# Addr-type Address Value
-#
-# where:
-# Addr-type register length (1,2 or 4 bytes)
-# Address absolute address of the register
-# value value to be stored in the register
-
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
DATA 4 0x53fa8554 0x00300000
DATA 4 0x53fa8558 0x00300040
DATA 4 0x53fa8560 0x00300000
diff --git a/board/freescale/mx53smd/imximage.cfg b/board/freescale/mx53smd/imximage.cfg
index 614d29e..4633e4d 100644
--- a/board/freescale/mx53smd/imximage.cfg
+++ b/board/freescale/mx53smd/imximage.cfg
@@ -1,48 +1,51 @@
-#
-# (C) Copyright 2009
-# Stefano Babic DENX Software Engineering sbabic at denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not write to the Free Software
-# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
-# MA 02110-1301 USA
-#
-# Refer docs/README.imxmage for more details about how-to configure
-# and create imximage boot image
-#
-# The syntax is taken as close as possible with the kwbimage
-
-# image version
+/*
+ * (C) Copyright 2009
+ * Stefano Babic DENX Software Engineering sbabic at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+/* image version */
IMAGE_VERSION 2
-# Boot Device : one of
-# spi, sd (the board has no nand neither onenand)
-
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
BOOT_FROM sd
-# Device Configuration Data (DCD)
-#
-# Each entry must have the format:
-# Addr-type Address Value
-#
-# where:
-# Addr-type register length (1,2 or 4 bytes)
-# Address absolute address of the register
-# value value to be stored in the register
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
DATA 4 0x53fa8554 0x00300000
DATA 4 0x53fa8558 0x00300040
DATA 4 0x53fa8560 0x00300000
diff --git a/board/freescale/mx6qarm2/imximage.cfg b/board/freescale/mx6qarm2/imximage.cfg
index bf941a3..4ed211e 100644
--- a/board/freescale/mx6qarm2/imximage.cfg
+++ b/board/freescale/mx6qarm2/imximage.cfg
@@ -1,47 +1,51 @@
-# Copyright (C) 2011 Freescale Semiconductor, Inc.
-# Jason Liu <r64343@freescale.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not write to the Free Software
-# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
-# MA 02110-1301 USA
-#
-# Refer docs/README.imxmage for more details about how-to configure
-# and create imximage boot image
-#
-# The syntax is taken as close as possible with the kwbimage
-
-# image version
-
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * Jason Liu <r64343@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
IMAGE_VERSION 2
-# Boot Device : one of
-# spi, sd (the board has no nand neither onenand)
-
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
BOOT_FROM sd
-# Device Configuration Data (DCD)
-#
-# Each entry must have the format:
-# Addr-type Address Value
-#
-# where:
-# Addr-type register length (1,2 or 4 bytes)
-# Address absolute address of the register
-# value value to be stored in the register
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
DATA 4 0x020e05a8 0x00000030
DATA 4 0x020e05b0 0x00000030
DATA 4 0x020e0524 0x00000030
@@ -166,8 +170,8 @@ DATA 4 0x020c4078 0x00FFF300
DATA 4 0x020c407c 0x0F0000C3
DATA 4 0x020c4080 0x000003FF
-# enable AXI cache for VDOA/VPU/IPU
+/* enable AXI cache for VDOA/VPU/IPU */
DATA 4 0x020e0010 0xF00000CF
-# set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
DATA 4 0x020e0018 0x007F007F
DATA 4 0x020e001c 0x007F007F
diff --git a/board/genesi/mx51_efikamx/imximage_mx.cfg b/board/genesi/mx51_efikamx/imximage_mx.cfg
index 38fa760..21ff6d6 100644
--- a/board/genesi/mx51_efikamx/imximage_mx.cfg
+++ b/board/genesi/mx51_efikamx/imximage_mx.cfg
@@ -1,52 +1,58 @@
-#
-# Copyright (C) 2009 Pegatron Corporation
-# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
-# Copyright (C) 2009-2012 Genesi USA, Inc.
-#
-# BASED ON: imx51evk
-#
-# (C) Copyright 2009
-# Stefano Babic DENX Software Engineering sbabic at denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not write to the Free Software
-# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
-# MA 02110-1301 USA
-#
-# Refer docs/README.imxmage for more details about how-to configure
-# and create imximage boot image
-#
-# The syntax is taken as close as possible with the kwbimage
+/*
+ * Copyright (C) 2009 Pegatron Corporation
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ * Copyright (C) 2009-2012 Genesi USA, Inc.
+ *
+ * BASED ON: imx51evk
+ *
+ * (C) Copyright 2009
+ * Stefano Babic DENX Software Engineering sbabic at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
-# Boot Device : one of
-# spi, sd (the board has no nand neither onenand)
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
BOOT_FROM spi
-# Device Configuration Data (DCD)
-#
-# Each entry must have the format:
-# Addr-type Address Value
-#
-# where:
-# Addr-type register length (1,2 or 4 bytes)
-# Address absolute address of the register
-# value value to be stored in the register
-
-# Essential GPIO settings to be done as early as possible
-# PCBIDn pad settings are all the defaults except #2 which needs HVE off
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+/*
+ * Essential GPIO settings to be done as early as possible
+ * PCBIDn pad settings are all the defaults except #2 which needs HVE off
+ */
DATA 4 0x73fa8134 0x3 # PCBID0 ALT3 GPIO 3_16
DATA 4 0x73fa8130 0x3 # PCBID1 ALT3 GPIO 3_17
DATA 4 0x73fa8128 0x3 # PCBID2 ALT3 GPIO 3_11
@@ -55,7 +61,7 @@ DATA 4 0x73fa8198 0x3 # LED0 ALT3 GPIO 3_13
DATA 4 0x73fa81c4 0x3 # LED1 ALT3 GPIO 3_14
DATA 4 0x73fa81c8 0x3 # LED2 ALT3 GPIO 3_15
-# DDR bus IOMUX PAD settings
+/* DDR bus IOMUX PAD settings */
DATA 4 0x73fa850c 0x20c5 # SDODT1
DATA 4 0x73fa8510 0x20c5 # SDODT0
DATA 4 0x73fa84ac 0xc5 # SDWE
@@ -72,22 +78,24 @@ DATA 4 0x73fa84d8 0xc5 # DRAM_DQM1
DATA 4 0x73fa84dc 0xc5 # DRAM_DQM2
DATA 4 0x73fa84e0 0xc5 # DRAM_DQM3
-# Setting DDR for micron
-# 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
-# CAS=3 BL=4
-# ESDCTL_ESDCTL0
+/*
+ * Setting DDR for micron
+ * 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
+ * CAS=3 BL=4
+ */
+/* ESDCTL_ESDCTL0 */
DATA 4 0x83fd9000 0x82a20000
-# ESDCTL_ESDCTL1
+/* ESDCTL_ESDCTL1 */
DATA 4 0x83fd9008 0x82a20000
-# ESDCTL_ESDMISC
+/* ESDCTL_ESDMISC */
DATA 4 0x83fd9010 0xcaaaf6d0
-# ESDCTL_ESDCFG0
+/* ESDCTL_ESDCFG0 */
DATA 4 0x83fd9004 0x3f3574aa
-# ESDCTL_ESDCFG1
+/* ESDCTL_ESDCFG1 */
DATA 4 0x83fd900c 0x3f3574aa
-# Init DRAM on CS0
-# ESDCTL_ESDSCR
+/* Init DRAM on CS0 */
+/* ESDCTL_ESDSCR */
DATA 4 0x83fd9014 0x04008008
DATA 4 0x83fd9014 0x0000801a
DATA 4 0x83fd9014 0x0000801b
@@ -101,7 +109,7 @@ DATA 4 0x83fd9014 0x03808019
DATA 4 0x83fd9014 0x00408019
DATA 4 0x83fd9014 0x00008000
-# Init DRAM on CS1
+/* Init DRAM on CS1 */
DATA 4 0x83fd9014 0x0400800c
DATA 4 0x83fd9014 0x0000801e
DATA 4 0x83fd9014 0x0000801f
@@ -115,12 +123,12 @@ DATA 4 0x83fd9014 0x0380801d
DATA 4 0x83fd9014 0x0040801d
DATA 4 0x83fd9014 0x00008004
-# Write to CTL0
+/* Write to CTL0 */
DATA 4 0x83fd9000 0xb2a20000
-# Write to CTL1
+/* Write to CTL1 */
DATA 4 0x83fd9008 0xb2a20000
-# ESDMISC
+/* ESDMISC */
DATA 4 0x83fd9010 0x000ad6d0
-#ESDCTL_ESDCDLYGD
+/* ESDCTL_ESDCDLYGD */
DATA 4 0x83fd9034 0x90000000
DATA 4 0x83fd9014 0x00000000
diff --git a/board/genesi/mx51_efikamx/imximage_sb.cfg b/board/genesi/mx51_efikamx/imximage_sb.cfg
index 26d259f..7ddd0b1 100644
--- a/board/genesi/mx51_efikamx/imximage_sb.cfg
+++ b/board/genesi/mx51_efikamx/imximage_sb.cfg
@@ -1,51 +1,55 @@
-#
-# Copyright (C) 2009 Pegatron Corporation
-# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
-# Copyright (C) 2009-2012 Genesi USA, Inc.
-#
-# BASED ON: imx51evk
-#
-# (C) Copyright 2009
-# Stefano Babic DENX Software Engineering sbabic at denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not write to the Free Software
-# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
-# MA 02110-1301 USA
-#
-# Refer docs/README.imxmage for more details about how-to configure
-# and create imximage boot image
-#
-# The syntax is taken as close as possible with the kwbimage
+/*
+ * Copyright (C) 2009 Pegatron Corporation
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ * Copyright (C) 2009-2012 Genesi USA, Inc.
+ *
+ * BASED ON: imx51evk
+ *
+ * (C) Copyright 2009
+ * Stefano Babic DENX Software Engineering sbabic at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
-# Boot Device : one of
-# spi, sd (the board has no nand neither onenand)
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
BOOT_FROM spi
-# Device Configuration Data (DCD)
-#
-# Each entry must have the format:
-# Addr-type Address Value
-#
-# where:
-# Addr-type register length (1,2 or 4 bytes)
-# Address absolute address of the register
-# value value to be stored in the register
-
-# DDR bus IOMUX PAD settings
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+*/
+/* DDR bus IOMUX PAD settings */
DATA 4 0x73fa88a0 0x200 # GRP_INMODE1
DATA 4 0x73fa850c 0x20c5 # SDODT1
DATA 4 0x73fa8510 0x20c5 # SDODT0
@@ -62,22 +66,24 @@ DATA 4 0x73fa84b4 0xe5 # SDCKE1
DATA 4 0x73fa84cc 0xe5 # DRAM_CS0
DATA 4 0x73fa84d0 0xe4 # DRAM_CS1
-# Setting DDR for micron
-# 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
-# CAS=3 BL=4
-# ESDCTL_ESDCTL0
+/*
+ * Setting DDR for micron
+ * 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
+ * CAS=3 BL=4
+ */
+/* ESDCTL_ESDCTL0 */
DATA 4 0x83fd9000 0x82a20000
-# ESDCTL_ESDCTL1
+/* ESDCTL_ESDCTL1 */
DATA 4 0x83fd9008 0x82a20000
-# ESDCTL_ESDMISC
+/* ESDCTL_ESDMISC */
DATA 4 0x83fd9010 0xcaaaf6d0
-# ESDCTL_ESDCFG0
+/* ESDCTL_ESDCFG0 */
DATA 4 0x83fd9004 0x333574aa
-# ESDCTL_ESDCFG1
+/* ESDCTL_ESDCFG1 */
DATA 4 0x83fd900c 0x333574aa
-# Init DRAM on CS0
-# ESDCTL_ESDSCR
+/* Init DRAM on CS0 */
+/* ESDCTL_ESDSCR */
DATA 4 0x83fd9014 0x04008008
DATA 4 0x83fd9014 0x0000801a
DATA 4 0x83fd9014 0x0000801b
@@ -91,7 +97,7 @@ DATA 4 0x83fd9014 0x03808019
DATA 4 0x83fd9014 0x00408019
DATA 4 0x83fd9014 0x00008000
-# Init DRAM on CS1
+/* Init DRAM on CS1 */
DATA 4 0x83fd9014 0x0400800c
DATA 4 0x83fd9014 0x0000801e
DATA 4 0x83fd9014 0x0000801f
@@ -105,12 +111,12 @@ DATA 4 0x83fd9014 0x0380801d
DATA 4 0x83fd9014 0x0042801d
DATA 4 0x83fd9014 0x00008004
-# Write to CTL0
+/* Write to CTL0 */
DATA 4 0x83fd9000 0xb2a20000
-# Write to CTL1
+/* Write to CTL1 */
DATA 4 0x83fd9008 0xb2a20000
-# ESDMISC
+/* ESDMISC */
DATA 4 0x83fd9010 0xcaaaf6d0
-#ESDCTL_ESDCDLYGD
+/* ESDCTL_ESDCDLYGD */
DATA 4 0x83fd9034 0x90000000
DATA 4 0x83fd9014 0x00000000
diff --git a/board/ttcontrol/vision2/imximage_hynix.cfg b/board/ttcontrol/vision2/imximage_hynix.cfg
index ed531db..c1de94f 100644
--- a/board/ttcontrol/vision2/imximage_hynix.cfg
+++ b/board/ttcontrol/vision2/imximage_hynix.cfg
@@ -1,209 +1,228 @@
-#
-# (C) Copyright 2009
-# Stefano Babic DENX Software Engineering sbabic at denx.de.
-#
-# (C) Copyright 2010
-# Klaus Steinhammer TTECH Control Gmbh kst at tttech.com
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not write to the Free Software
-# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
-# MA 02110-1301 USA
-#
-# Refer docs/README.imxmage for more details about how-to configure
-# and create imximage boot image
-#
-# The syntax is taken as close as possible with the kwbimage
-
-# Boot Device : one of
-# spi, nand, onenand, sd
-
+/*
+ * (C) Copyright 2009
+ * Stefano Babic DENX Software Engineering sbabic at denx.de.
+ *
+ * (C) Copyright 2010
+ * Klaus Steinhammer TTECH Control Gmbh kst at tttech.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/*
+ * Boot Device : one of
+ * spi, nand, onenand, sd
+ */
BOOT_FROM spi
-# Device Configuration Data (DCD)
-#
-# Each entry must have the format:
-# Addr-type Address Value
-#
-# where:
-# Addr-type register length (1,2 or 4 bytes)
-# Address absolute address of the register
-# value value to be stored in the register
-
-#######################
-### Disable WDOG ###
-#######################
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+/*
+ * #######################
+ * ### Disable WDOG ###
+ * #######################
+ */
DATA 2 0x73f98000 0x30
-#######################
-### SET DDR Clk ###
-#######################
-
-# CCM: CBMCR - ddr_clk_sel: axi_b (133MHz)
+/*
+ * #######################
+ * ### SET DDR Clk ###
+ * #######################
+ */
+/* CCM: CBMCR - ddr_clk_sel: axi_b (133MHz) */
DATA 4 0x73FD4018 0x000024C0
-# DOUBLE SPI CLK (13MHz->26 MHz Clock)
+/* DOUBLE SPI CLK (13MHz->26 MHz Clock) */
DATA 4 0x73FD4038 0x2010241
-#IOMUXC_SW_PAD_CTL_PAD_CSPI1_MOSI HYS_ENABLE | DRV_MAX | SRE_FAST
+/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_MOSI HYS_ENABLE | DRV_MAX | SRE_FAST */
DATA 4 0x73fa8600 0x00000107
-#IOMUXC_SW_PAD_CTL_PAD_CSPI1_MISO HYS_ENABLE | DRV_MAX | SRE_FAST
+/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_MISO HYS_ENABLE | DRV_MAX | SRE_FAST */
DATA 4 0x73fa8604 0x00000107
-#IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS0 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST
+/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS0 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST */
DATA 4 0x73fa8608 0x00000187
-#IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS1 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST
+/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS1 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST */
DATA 4 0x73fa860c 0x00000187
-#IOMUXC_SW_PAD_CTL_PAD_CSPI1_SCLK HYS_ENABLE | DRV_MAX | SRE_FAST
+/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SCLK HYS_ENABLE | DRV_MAX | SRE_FAST */
DATA 4 0x73fa8614 0x00000107
-#IOMUXC_SW_PAD_CTL_PAD_DI1_PIN11 HYS_ENABLE | DRV_MAX | SRE_FAST (CSPI1_SS2)
+/* IOMUXC_SW_PAD_CTL_PAD_DI1_PIN11 HYS_ENABLE | DRV_MAX | SRE_FAST (CSPI1_SS2) */
DATA 4 0x73fa86a8 0x00000187
-#######################
-### Settings IOMUXC ###
-#######################
-
-# DDR IOMUX configuration
-# Control, Data, Address pads are in their default state: HIGH DS, FAST SR.
-# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK MAX DS
+/*
+ * #######################
+ * ### Settings IOMUXC ###
+ * #######################
+ */
+/*
+ * DDR IOMUX configuration
+ * Control, Data, Address pads are in their default state: HIGH DS, FAST SR.
+ * IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK MAX DS
+ */
DATA 4 0x73fa84b8 0x000000e7
-# PVTC MAX (at GPC, PGR reg)
-#DATA 4 0x73FD8004 0x1fc00000
+/* PVTC MAX (at GPC, PGR reg) */
+/* DATA 4 0x73FD8004 0x1fc00000 */
-#DQM0 DS high slew rate slow
+/* DQM0 DS high slew rate slow */
DATA 4 0x73fa84d4 0x000000e4
-#DQM1 DS high slew rate slow
+/* DQM1 DS high slew rate slow */
DATA 4 0x73fa84d8 0x000000e4
-#DQM2 DS high slew rate slow
+/* DQM2 DS high slew rate slow */
DATA 4 0x73fa84dc 0x000000e4
-#DQM3 DS high slew rate slow
+/* DQM3 DS high slew rate slow */
DATA 4 0x73fa84e0 0x000000e4
-#IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 DS high & SLEW slow
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 DS high & SLEW slow */
DATA 4 0x73fa84bc 0x000000c4
-#IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 DS high & SLEW slow
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 DS high & SLEW slow */
DATA 4 0x73fa84c0 0x000000c4
-#IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 DS high & SLEW slow
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 DS high & SLEW slow */
DATA 4 0x73fa84c4 0x000000c4
-#IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 DS high & SLEW slow
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 DS high & SLEW slow */
DATA 4 0x73fa84c8 0x000000c4
-#DRAM_DATA B0
+/* DRAM_DATA B0 */
DATA 4 0x73fa88a4 0x00000004
-#DRAM_DATA B1
+/* DRAM_DATA B1 */
DATA 4 0x73fa88ac 0x00000004
-#DRAM_DATA B2
+/* DRAM_DATA B2 */
DATA 4 0x73fa88b8 0x00000004
-#DRAM_DATA B3
+/* DRAM_DATA B3 */
DATA 4 0x73fa882c 0x00000004
-#DRAM_DATA B0 slew rate
+/* DRAM_DATA B0 slew rate */
DATA 4 0x73fa8878 0x00000000
-#DRAM_DATA B1 slew rate
+/* DRAM_DATA B1 slew rate */
DATA 4 0x73fa8880 0x00000000
-#DRAM_DATA B2 slew rate
+/* DRAM_DATA B2 slew rate */
DATA 4 0x73fa888c 0x00000000
-#DRAM_DATA B3 slew rate
+/* DRAM_DATA B3 slew rate */
DATA 4 0x73fa889c 0x00000000
-#######################
-### Configure SDRAM ###
-#######################
+/*
+ * #######################
+ * ### Configure SDRAM ###
+ * #######################
+ */
-# Configure CS0
-#######################
+/* Configure CS0 */
+/* ####################### */
-# ESDCTL0: Enable controller
+/* ESDCTL0: Enable controller */
DATA 4 0x83fd9000 0x83220000
-# Init DRAM on CS0
-# ESDSCR: Precharge command
+/* Init DRAM on CS0 /
+/* ESDSCR: Precharge command */
DATA 4 0x83fd9014 0x04008008
-# ESDSCR: Refresh command
+/* ESDSCR: Refresh command */
DATA 4 0x83fd9014 0x00008010
-# ESDSCR: Refresh command
+/* ESDSCR: Refresh command */
DATA 4 0x83fd9014 0x00008010
-# ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8)
+/* ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8) */
DATA 4 0x83fd9014 0x00338018
-# ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51)
+/* ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51) */
DATA 4 0x83fd9014 0x0020801a
-# ESDSCR
+/* ESDSCR */
DATA 4 0x83fd9014 0x00008000
-# ESDSCR: EMR with full Drive strength
-#DATA 4 0x83fd9014 0x0000801a
+/* ESDSCR: EMR with full Drive strength */
+/* DATA 4 0x83fd9014 0x0000801a */
-# ESDCTL0: 14 ROW, 10 COL, 32Bit, SREF=8
+/* ESDCTL0: 14 ROW, 10 COL, 32Bit, SREF=8 */
DATA 4 0x83fd9000 0xC3220000
-# ESDCFG0: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
-# tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
-#DATA 4 0x83fd9004 0xC33574AA
-
-#micron mDDR
-# ESDCFG0: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks
-# tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
-#DATA 4 0x83FD9004 0x101564a8
-
-#hynix mDDR
-# ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks
-# tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
+/*
+ * ESDCFG0: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
+ * tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
+ * DATA 4 0x83fd9004 0xC33574AA
+ */
+/*
+ * micron mDDR
+ * ESDCFG0: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks
+ * tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
+ * DATA 4 0x83FD9004 0x101564a8
+ */
+/*
+ * hynix mDDR
+ * ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks
+ * tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
+ */
DATA 4 0x83FD9004 0x704564a8
-# ESDMISC: AP=10, Bank interleaving on, MIF3 en, RALAT=2
+/* ESDMISC: AP=10, Bank interleaving on, MIF3 en, RALAT=2 */
DATA 4 0x83fd9010 0x000a1700
-# Configure CS1
-#######################
+/* Configure CS1 */
+/* ####################### */
-# ESDCTL1: Enable controller
+/* ESDCTL1: Enable controller */
DATA 4 0x83fd9008 0x83220000
-# Init DRAM on CS1
-# ESDSCR: Precharge command
+/* Init DRAM on CS1 */
+/* ESDSCR: Precharge command */
DATA 4 0x83fd9014 0x0400800c
-# ESDSCR: Refresh command
+/* ESDSCR: Refresh command */
DATA 4 0x83fd9014 0x00008014
-# ESDSCR: Refresh command
+/* ESDSCR: Refresh command */
DATA 4 0x83fd9014 0x00008014
-# ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8)
+/* ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8) */
DATA 4 0x83fd9014 0x0033801c
-# ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51)
+/* ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51) */
DATA 4 0x83fd9014 0x0020801e
-# ESDSCR
+/* ESDSCR */
DATA 4 0x83fd9014 0x00008004
-# ESDCTL1: 14 ROW, 10 COL, 32Bit, SREF=8
+/* ESDCTL1: 14 ROW, 10 COL, 32Bit, SREF=8 */
DATA 4 0x83fd9008 0xC3220000
-
-# ESDCFG1: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
-# tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
-#DATA 4 0x83fd900c 0xC33574AA
-
-#micron mDDR
-# ESDCFG1: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks
-# tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
-#DATA 4 0x83FD900C 0x101564a8
-
-#hynix mDDR
-# ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks
-# tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
+/*
+ * ESDCFG1: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
+ * tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
+ * DATA 4 0x83fd900c 0xC33574AA
+ */
+/*
+ * micron mDDR
+ * ESDCFG1: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks
+ * tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
+ * DATA 4 0x83FD900C 0x101564a8
+ */
+/*
+ * hynix mDDR
+ * ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks
+ * tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
+ */
DATA 4 0x83FD900C 0x704564a8
-# ESDSCR (mDRAM configuration finished)
+/* ESDSCR (mDRAM configuration finished) */
DATA 4 0x83FD9014 0x00000004
-# ESDSCR - clear "configuration request" bit
+/* ESDSCR - clear "configuration request" bit */
DATA 4 0x83fd9014 0x00000000
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 18/32] mx6q_4x_mt41j128.cfg: use symbols instead of hardcoded constants
2012-10-04 1:47 ` [U-Boot] [PATCH V3 00/32] " Troy Kisky
` (16 preceding siblings ...)
2012-10-04 1:47 ` [U-Boot] [PATCH V3 17/32] imximage.cfg: run files through C preprocessor Troy Kisky
@ 2012-10-04 1:47 ` Troy Kisky
2012-10-04 1:47 ` [U-Boot] [PATCH V3 19/32] mx6q_4x_mt41j128.cfg: add comments Troy Kisky
` (16 subsequent siblings)
34 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-10-04 1:47 UTC (permalink / raw)
To: u-boot
This allows us to generate DCD table data appropriate
for MX6Q, MX6DL, or MX6Solo simply by defining
CONFIG_MX6Q, CONFIG_MX6DL, or CONFIG_MX6S
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
arch/arm/include/asm/arch-mx6/imx-mkimage.h | 156 ++++++++++++++++
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 245 +++++++++++++-------------
2 files changed, 280 insertions(+), 121 deletions(-)
create mode 100644 arch/arm/include/asm/arch-mx6/imx-mkimage.h
diff --git a/arch/arm/include/asm/arch-mx6/imx-mkimage.h b/arch/arm/include/asm/arch-mx6/imx-mkimage.h
new file mode 100644
index 0000000..4abd3f1
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/imx-mkimage.h
@@ -0,0 +1,156 @@
+/*
+ * Copyright (C) 2012 Boundary Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+#ifndef __ASM_ARCH_IMX_MKIMAGE_H__
+#define __ASM_ARCH_IMX_MKIMAGE_H__
+
+#define IOMUXC_GPR4 0x020e0010
+#define IOMUXC_GPR6 0x020e0018
+#define IOMUXC_GPR7 0x020e001c
+
+/* mx6 duallite and solo have same offsets */
+
+#define IOM_DRAM_DQM0 MA(0x020e05ac, 0x020e0470, 0x0)
+#define IOM_DRAM_DQM1 MA(0x020e05b4, 0x020e0474, 0x0)
+#define IOM_DRAM_DQM2 MA(0x020e0528, 0x020e0478, 0x0)
+#define IOM_DRAM_DQM3 MA(0x020e0520, 0x020e047c, 0x0)
+#define IOM_DRAM_DQM4 MA(0x020e0514, 0x020e0480, 0x0)
+#define IOM_DRAM_DQM5 MA(0x020e0510, 0x020e0484, 0x0)
+#define IOM_DRAM_DQM6 MA(0x020e05bc, 0x020e0488, 0x0)
+#define IOM_DRAM_DQM7 MA(0x020e05c4, 0x020e048c, 0x0)
+
+#define IOM_DRAM_CAS MA(0x020e056c, 0x020e0464, 0x0)
+#define IOM_DRAM_RAS MA(0x020e0578, 0x020e0490, 0x0)
+#define IOM_DRAM_RESET MA(0x020e057c, 0x020e0494, 0x0)
+#define IOM_DRAM_SDCLK_0 MA(0x020e0588, 0x020e04ac, 0x0)
+#define IOM_DRAM_SDCLK_1 MA(0x020e0594, 0x020e04b0, 0x0)
+#define IOM_DRAM_SDBA2 MA(0x020e058c, 0x020e04a0, 0x0)
+#define IOM_DRAM_SDCKE0 MA(0x020e0590, 0x020e04a4, 0x0)
+#define IOM_DRAM_SDCKE1 MA(0x020e0598, 0x020e04a8, 0x0)
+#define IOM_DRAM_SDODT0 MA(0x020e059c, 0x020e04b4, 0x0)
+#define IOM_DRAM_SDODT1 MA(0x020e05a0, 0x020e04b8, 0x0)
+
+#define IOM_DRAM_SDQS0 MA(0x020e05a8, 0x020e04bc, 0x0)
+#define IOM_DRAM_SDQS1 MA(0x020e05b0, 0x020e04c0, 0x0)
+#define IOM_DRAM_SDQS2 MA(0x020e0524, 0x020e04c4, 0x0)
+#define IOM_DRAM_SDQS3 MA(0x020e051c, 0x020e04c8, 0x0)
+#define IOM_DRAM_SDQS4 MA(0x020e0518, 0x020e04cc, 0x0)
+#define IOM_DRAM_SDQS5 MA(0x020e050c, 0x020e04d0, 0x0)
+#define IOM_DRAM_SDQS6 MA(0x020e05b8, 0x020e04d4, 0x0)
+#define IOM_DRAM_SDQS7 MA(0x020e05c0, 0x020e04d8, 0x0)
+
+#define IOM_GRP_B0DS MA(0x020e0784, 0x020e0764, 0x0)
+#define IOM_GRP_B1DS MA(0x020e0788, 0x020e0770, 0x0)
+#define IOM_GRP_B2DS MA(0x020e0794, 0x020e0778, 0x0)
+#define IOM_GRP_B3DS MA(0x020e079c, 0x020e077c, 0x0)
+#define IOM_GRP_B4DS MA(0x020e07a0, 0x020e0780, 0x0)
+#define IOM_GRP_B5DS MA(0x020e07a4, 0x020e0784, 0x0)
+#define IOM_GRP_B6DS MA(0x020e07a8, 0x020e078c, 0x0)
+#define IOM_GRP_B7DS MA(0x020e0748, 0x020e0748, 0x0)
+#define IOM_GRP_ADDDS MA(0x020e074c, 0x020e074c, 0x0)
+#define IOM_DDRMODE_CTL MA(0x020e0750, 0x020e0750, 0x0)
+#define IOM_GRP_DDRPKE MA(0x020e0758, 0x020e0754, 0x0)
+#define IOM_GRP_DDRMODE MA(0x020e0774, 0x020e0760, 0x0)
+#define IOM_GRP_CTLDS MA(0x020e078c, 0x020e076c, 0x0)
+#define IOM_GRP_DDR_TYPE MA(0x020e0798, 0x020e0774, 0x0)
+
+#define IRAM_FREE_START 0x00907000
+
+#define MMDC_P0_MDCTL 0x021b0000
+#define MMDC_P0_MDPDC 0x021b0004
+#define MMDC_P0_MDOTC 0x021b0008
+#define MMDC_P0_MDCFG0 0x021b000c
+#define MMDC_P0_MDCFG1 0x021b0010
+#define MMDC_P0_MDCFG2 0x021b0014
+#define MMDC_P0_MDMISC 0x021b0018
+#define MMDC_P0_MDSCR 0x021b001c
+#define MMDC_P0_MDREF 0x021b0020
+#define MMDC_P0_MDRWD 0x021b002c
+#define MMDC_P0_MDOR 0x021b0030
+#define MMDC_P0_MDASP 0x021b0040
+#define MMDC_P0_MAPSR 0x021b0404
+#define MMDC_P0_MPZQHWCTRL 0x021b0800
+#define MMDC_P0_MPWLDECTRL0 0x021b080c
+#define MMDC_P0_MPWLDECTRL1 0x021b0810
+#define MMDC_P0_MPODTCTRL 0x021b0818
+#define MMDC_P0_MPRDDQBY0DL 0x021b081c
+#define MMDC_P0_MPRDDQBY1DL 0x021b0820
+#define MMDC_P0_MPRDDQBY2DL 0x021b0824
+#define MMDC_P0_MPRDDQBY3DL 0x021b0828
+#define MMDC_P0_MPDGCTRL0 0x021b083c
+#define MMDC_P0_MPDGCTRL1 0x021b0840
+#define MMDC_P0_MPRDDLCTL 0x021b0848
+#define MMDC_P0_MPWRDLCTL 0x021b0850
+#define MMDC_P0_MPMUR0 0x021b08b8
+
+#define MMDC_P1_MDCTL 0x021b4000
+#define MMDC_P1_MDPDC 0x021b4004
+#define MMDC_P1_MDOTC 0x021b4008
+#define MMDC_P1_MDCFG0 0x021b400c
+#define MMDC_P1_MDCFG1 0x021b4010
+#define MMDC_P1_MDCFG2 0x021b4014
+#define MMDC_P1_MDMISC 0x021b4018
+#define MMDC_P1_MDSCR 0x021b401c
+#define MMDC_P1_MDREF 0x021b4020
+#define MMDC_P1_MDRWD 0x021b402c
+#define MMDC_P1_MDOR 0x021b4030
+#define MMDC_P1_MDASP 0x021b4040
+#define MMDC_P1_MAPSR 0x021b4404
+#define MMDC_P1_MPZQHWCTRL 0x021b4800
+#define MMDC_P1_MPWLDECTRL0 0x021b480c
+#define MMDC_P1_MPWLDECTRL1 0x021b4810
+#define MMDC_P1_MPODTCTRL 0x021b4818
+#define MMDC_P1_MPRDDQBY0DL 0x021b481c
+#define MMDC_P1_MPRDDQBY1DL 0x021b4820
+#define MMDC_P1_MPRDDQBY2DL 0x021b4824
+#define MMDC_P1_MPRDDQBY3DL 0x021b4828
+#define MMDC_P1_MPDGCTRL0 0x021b483c
+#define MMDC_P1_MPDGCTRL1 0x021b4840
+#define MMDC_P1_MPRDDLCTL 0x021b4848
+#define MMDC_P1_MPWRDLCTL 0x021b4850
+#define MMDC_P1_MPMUR0 0x021b48b8
+
+#define CCM_CCGR0 0x020C4068
+#define CCM_CCGR1 0x020C406c
+#define CCM_CCGR2 0x020C4070
+#define CCM_CCGR3 0x020C4074
+#define CCM_CCGR4 0x020C4078
+#define CCM_CCGR5 0x020C407c
+#define CCM_CCGR6 0x020C4080
+
+
+#define WRITE_ENTRY1(addr, q) DATA 4, addr, q
+#ifdef CONFIG_MX6Q
+#define MA(mx6q, mx6dl_solo, mx6sololite) mx6q
+#define WRITE_ENTRY2(addr, q, dl) WRITE_ENTRY1(addr, q)
+#define WRITE_ENTRY3(addr, q, dl, solo) WRITE_ENTRY1(addr, q)
+#define WRITE_ENTRY4(addr, q, dl, solo, sl) WRITE_ENTRY1(addr, q)
+#else
+
+#define WRITE_ENTRY2(addr, q, dl) WRITE_ENTRY1(addr, dl)
+#ifdef CONFIG_MX6DL
+#define MA(mx6q, mx6dl_solo, mx6sololite) mx6dl_solo
+#define WRITE_ENTRY3(addr, q, dl, solo) WRITE_ENTRY1(addr, dl)
+#define WRITE_ENTRY4(addr, q, dl, solo, sl) WRITE_ENTRY1(addr, dl)
+#else
+
+#define WRITE_ENTRY3(addr, q, dl, solo) WRITE_ENTRY1(addr, solo)
+#ifdef CONFIG_MX6S
+#define MA(mx6q, mx6dl_solo, mx6sololite) mx6dl_solo
+#define WRITE_ENTRY4(addr, q, dl, solo, sl) WRITE_ENTRY1(addr, solo)
+#else
+
+#define WRITE_ENTRY4(addr, q, dl, solo, sl) WRITE_ENTRY1(addr, sl)
+#ifdef CONFIG_MX6SL
+#define MA(mx6q, mx6dl_solo, mx6sololite) mx6sololite
+#else
+
+#error "Please select cpu"
+#endif /* CONFIG_MX6SL */
+#endif /* CONFIG_MX6S */
+#endif /* CONFIG_MX6DL */
+#endif /* CONFIG_MX6Q */
+
+#endif /*__ASM_ARCH_IMX_MKIMAGE_H__ */
diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
index c86cd40..84823f8 100644
--- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
@@ -25,6 +25,9 @@
*
* The syntax is taken as close as possible with the kwbimage
*/
+#define __ASSEMBLY__
+#include <config.h>
+#include <asm/arch/imx-mkimage.h>
/* image version */
IMAGE_VERSION 2
@@ -46,129 +49,129 @@ BOOT_FROM sd
* Address absolute address of the register
* value value to be stored in the register
*/
-DATA 4 0x020e05a8 0x00000030
-DATA 4 0x020e05b0 0x00000030
-DATA 4 0x020e0524 0x00000030
-DATA 4 0x020e051c 0x00000030
-
-DATA 4 0x020e0518 0x00000030
-DATA 4 0x020e050c 0x00000030
-DATA 4 0x020e05b8 0x00000030
-DATA 4 0x020e05c0 0x00000030
-
-DATA 4 0x020e05ac 0x00020030
-DATA 4 0x020e05b4 0x00020030
-DATA 4 0x020e0528 0x00020030
-DATA 4 0x020e0520 0x00020030
-
-DATA 4 0x020e0514 0x00020030
-DATA 4 0x020e0510 0x00020030
-DATA 4 0x020e05bc 0x00020030
-DATA 4 0x020e05c4 0x00020030
-
-DATA 4 0x020e056c 0x00020030
-DATA 4 0x020e0578 0x00020030
-DATA 4 0x020e0588 0x00020030
-DATA 4 0x020e0594 0x00020030
-
-DATA 4 0x020e057c 0x00020030
-DATA 4 0x020e0590 0x00003000
-DATA 4 0x020e0598 0x00003000
-DATA 4 0x020e058c 0x00000000
-
-DATA 4 0x020e059c 0x00003030
-DATA 4 0x020e05a0 0x00003030
-DATA 4 0x020e0784 0x00000030
-DATA 4 0x020e0788 0x00000030
-
-DATA 4 0x020e0794 0x00000030
-DATA 4 0x020e079c 0x00000030
-DATA 4 0x020e07a0 0x00000030
-DATA 4 0x020e07a4 0x00000030
-
-DATA 4 0x020e07a8 0x00000030
-DATA 4 0x020e0748 0x00000030
-DATA 4 0x020e074c 0x00000030
-DATA 4 0x020e0750 0x00020000
-
-DATA 4 0x020e0758 0x00000000
-DATA 4 0x020e0774 0x00020000
-DATA 4 0x020e078c 0x00000030
-DATA 4 0x020e0798 0x000C0000
-
-DATA 4 0x021b081c 0x33333333
-DATA 4 0x021b0820 0x33333333
-DATA 4 0x021b0824 0x33333333
-DATA 4 0x021b0828 0x33333333
-
-DATA 4 0x021b481c 0x33333333
-DATA 4 0x021b4820 0x33333333
-DATA 4 0x021b4824 0x33333333
-DATA 4 0x021b4828 0x33333333
-
-DATA 4 0x021b0018 0x00081740
-
-DATA 4 0x021b001c 0x00008000
-DATA 4 0x021b000c 0x555A7975
-DATA 4 0x021b0010 0xFF538E64
-DATA 4 0x021b0014 0x01FF00DB
-DATA 4 0x021b002c 0x000026D2
-
-DATA 4 0x021b0030 0x005B0E21
-DATA 4 0x021b0008 0x09444040
-DATA 4 0x021b0004 0x00025576
-DATA 4 0x021b0040 0x00000027
-DATA 4 0x021b0000 0x831A0000
-
-DATA 4 0x021b001c 0x04088032
-DATA 4 0x021b001c 0x0408803A
-DATA 4 0x021b001c 0x00008033
-DATA 4 0x021b001c 0x0000803B
-DATA 4 0x021b001c 0x00428031
-DATA 4 0x021b001c 0x00428039
-DATA 4 0x021b001c 0x09408030
-DATA 4 0x021b001c 0x09408038
-
-DATA 4 0x021b001c 0x04008040
-DATA 4 0x021b001c 0x04008048
-DATA 4 0x021b0800 0xA1380003
-DATA 4 0x021b4800 0xA1380003
-DATA 4 0x021b0020 0x00005800
-DATA 4 0x021b0818 0x00022227
-DATA 4 0x021b4818 0x00022227
-
-DATA 4 0x021b083c 0x434B0350
-DATA 4 0x021b0840 0x034C0359
-DATA 4 0x021b483c 0x434B0350
-DATA 4 0x021b4840 0x03650348
-DATA 4 0x021b0848 0x4436383B
-DATA 4 0x021b4848 0x39393341
-DATA 4 0x021b0850 0x35373933
-DATA 4 0x021b4850 0x48254A36
-
-DATA 4 0x021b080c 0x001F001F
-DATA 4 0x021b0810 0x001F001F
-
-DATA 4 0x021b480c 0x00440044
-DATA 4 0x021b4810 0x00440044
-
-DATA 4 0x021b08b8 0x00000800
-DATA 4 0x021b48b8 0x00000800
-
-DATA 4 0x021b001c 0x00000000
-DATA 4 0x021b0404 0x00011006
+WRITE_ENTRY1(IOM_DRAM_SDQS0, 0x00000030)
+WRITE_ENTRY1(IOM_DRAM_SDQS1, 0x00000030)
+WRITE_ENTRY1(IOM_DRAM_SDQS2, 0x00000030)
+WRITE_ENTRY1(IOM_DRAM_SDQS3, 0x00000030)
+
+WRITE_ENTRY1(IOM_DRAM_SDQS4, 0x00000030)
+WRITE_ENTRY1(IOM_DRAM_SDQS5, 0x00000030)
+WRITE_ENTRY1(IOM_DRAM_SDQS6, 0x00000030)
+WRITE_ENTRY1(IOM_DRAM_SDQS7, 0x00000030)
+
+WRITE_ENTRY1(IOM_DRAM_DQM0, 0x00020030)
+WRITE_ENTRY1(IOM_DRAM_DQM1, 0x00020030)
+WRITE_ENTRY1(IOM_DRAM_DQM2, 0x00020030)
+WRITE_ENTRY1(IOM_DRAM_DQM3, 0x00020030)
+
+WRITE_ENTRY1(IOM_DRAM_DQM4, 0x00020030)
+WRITE_ENTRY1(IOM_DRAM_DQM5, 0x00020030)
+WRITE_ENTRY1(IOM_DRAM_DQM6, 0x00020030)
+WRITE_ENTRY1(IOM_DRAM_DQM7, 0x00020030)
+
+WRITE_ENTRY1(IOM_DRAM_CAS, 0x00020030)
+WRITE_ENTRY1(IOM_DRAM_RAS, 0x00020030)
+WRITE_ENTRY1(IOM_DRAM_SDCLK_0, 0x00020030)
+WRITE_ENTRY1(IOM_DRAM_SDCLK_1, 0x00020030)
+
+WRITE_ENTRY1(IOM_DRAM_RESET, 0x00020030)
+WRITE_ENTRY1(IOM_DRAM_SDCKE0, 0x00003000)
+WRITE_ENTRY1(IOM_DRAM_SDCKE1, 0x00003000)
+WRITE_ENTRY1(IOM_DRAM_SDBA2, 0x00000000)
+
+WRITE_ENTRY1(IOM_DRAM_SDODT0, 0x00003030)
+WRITE_ENTRY1(IOM_DRAM_SDODT1, 0x00003030)
+WRITE_ENTRY1(IOM_GRP_B0DS, 0x00000030)
+WRITE_ENTRY1(IOM_GRP_B1DS, 0x00000030)
+
+WRITE_ENTRY1(IOM_GRP_B2DS, 0x00000030)
+WRITE_ENTRY1(IOM_GRP_B3DS, 0x00000030)
+WRITE_ENTRY1(IOM_GRP_B4DS, 0x00000030)
+WRITE_ENTRY1(IOM_GRP_B5DS, 0x00000030)
+
+WRITE_ENTRY1(IOM_GRP_B6DS, 0x00000030)
+WRITE_ENTRY1(IOM_GRP_B7DS, 0x00000030)
+WRITE_ENTRY1(IOM_GRP_ADDDS, 0x00000030)
+WRITE_ENTRY1(IOM_DDRMODE_CTL, 0x00020000)
+
+WRITE_ENTRY1(IOM_GRP_DDRPKE, 0x00000000)
+WRITE_ENTRY1(IOM_GRP_DDRMODE, 0x00020000)
+WRITE_ENTRY1(IOM_GRP_CTLDS, 0x00000030)
+WRITE_ENTRY1(IOM_GRP_DDR_TYPE, 0x000C0000)
+
+WRITE_ENTRY1(MMDC_P0_MPRDDQBY0DL, 0x33333333)
+WRITE_ENTRY1(MMDC_P0_MPRDDQBY1DL, 0x33333333)
+WRITE_ENTRY1(MMDC_P0_MPRDDQBY2DL, 0x33333333)
+WRITE_ENTRY1(MMDC_P0_MPRDDQBY3DL, 0x33333333)
+
+WRITE_ENTRY1(MMDC_P1_MPRDDQBY0DL, 0x33333333)
+WRITE_ENTRY1(MMDC_P1_MPRDDQBY1DL, 0x33333333)
+WRITE_ENTRY1(MMDC_P1_MPRDDQBY2DL, 0x33333333)
+WRITE_ENTRY1(MMDC_P1_MPRDDQBY3DL, 0x33333333)
+
+WRITE_ENTRY1(MMDC_P0_MDMISC, 0x00081740)
+
+WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00008000)
+WRITE_ENTRY1(MMDC_P0_MDCFG0, 0x555A7975)
+WRITE_ENTRY1(MMDC_P0_MDCFG1, 0xFF538E64)
+WRITE_ENTRY1(MMDC_P0_MDCFG2, 0x01FF00DB)
+WRITE_ENTRY1(MMDC_P0_MDRWD, 0x000026D2)
+
+WRITE_ENTRY1(MMDC_P0_MDOR, 0x005B0E21)
+WRITE_ENTRY1(MMDC_P0_MDOTC, 0x09444040)
+WRITE_ENTRY1(MMDC_P0_MDPDC, 0x00025576)
+WRITE_ENTRY1(MMDC_P0_MDASP, 0x00000027)
+WRITE_ENTRY1(MMDC_P0_MDCTL, 0x831A0000)
+
+WRITE_ENTRY1(MMDC_P0_MDSCR, 0x04088032)
+WRITE_ENTRY1(MMDC_P0_MDSCR, 0x0408803A)
+WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00008033)
+WRITE_ENTRY1(MMDC_P0_MDSCR, 0x0000803B)
+WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00428031)
+WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00428039)
+WRITE_ENTRY1(MMDC_P0_MDSCR, 0x09408030)
+WRITE_ENTRY1(MMDC_P0_MDSCR, 0x09408038)
+
+WRITE_ENTRY1(MMDC_P0_MDSCR, 0x04008040)
+WRITE_ENTRY1(MMDC_P0_MDSCR, 0x04008048)
+WRITE_ENTRY1(MMDC_P0_MPZQHWCTRL, 0xA1380003)
+WRITE_ENTRY1(MMDC_P1_MPZQHWCTRL, 0xA1380003)
+WRITE_ENTRY1(MMDC_P0_MDREF, 0x00005800)
+WRITE_ENTRY1(MMDC_P0_MPODTCTRL, 0x00022227)
+WRITE_ENTRY1(MMDC_P1_MPODTCTRL, 0x00022227)
+
+WRITE_ENTRY1(MMDC_P0_MPDGCTRL0, 0x434B0350)
+WRITE_ENTRY1(MMDC_P0_MPDGCTRL1, 0x034C0359)
+WRITE_ENTRY1(MMDC_P1_MPDGCTRL0, 0x434B0350)
+WRITE_ENTRY1(MMDC_P1_MPDGCTRL1, 0x03650348)
+WRITE_ENTRY1(MMDC_P0_MPRDDLCTL, 0x4436383B)
+WRITE_ENTRY1(MMDC_P1_MPRDDLCTL, 0x39393341)
+WRITE_ENTRY1(MMDC_P0_MPWRDLCTL, 0x35373933)
+WRITE_ENTRY1(MMDC_P1_MPWRDLCTL, 0x48254A36)
+
+WRITE_ENTRY1(MMDC_P0_MPWLDECTRL0, 0x001F001F)
+WRITE_ENTRY1(MMDC_P0_MPWLDECTRL1, 0x001F001F)
+
+WRITE_ENTRY1(MMDC_P1_MPWLDECTRL0, 0x00440044)
+WRITE_ENTRY1(MMDC_P1_MPWLDECTRL1, 0x00440044)
+
+WRITE_ENTRY1(MMDC_P0_MPMUR0, 0x00000800)
+WRITE_ENTRY1(MMDC_P1_MPMUR0, 0x00000800)
+
+WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00000000)
+WRITE_ENTRY1(MMDC_P0_MAPSR, 0x00011006)
/* set the default clock gate to save power */
-DATA 4 0x020c4068 0x00C03F3F
-DATA 4 0x020c406c 0x0030FC03
-DATA 4 0x020c4070 0x0FFFC000
-DATA 4 0x020c4074 0x3FF00000
-DATA 4 0x020c4078 0x00FFF300
-DATA 4 0x020c407c 0x0F0000C3
-DATA 4 0x020c4080 0x000003FF
+WRITE_ENTRY1(CCM_CCGR0, 0x00C03F3F)
+WRITE_ENTRY1(CCM_CCGR1, 0x0030FC03)
+WRITE_ENTRY1(CCM_CCGR2, 0x0FFFC000)
+WRITE_ENTRY1(CCM_CCGR3, 0x3FF00000)
+WRITE_ENTRY1(CCM_CCGR4, 0x00FFF300)
+WRITE_ENTRY1(CCM_CCGR5, 0x0F0000C3)
+WRITE_ENTRY1(CCM_CCGR6, 0x000003FF)
/* enable AXI cache for VDOA/VPU/IPU */
-DATA 4 0x020e0010 0xF00000CF
+WRITE_ENTRY1(IOMUXC_GPR4, 0xF00000CF)
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-DATA 4 0x020e0018 0x007F007F
-DATA 4 0x020e001c 0x007F007F
+WRITE_ENTRY1(IOMUXC_GPR6, 0x007F007F)
+WRITE_ENTRY1(IOMUXC_GPR7, 0x007F007F)
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 19/32] mx6q_4x_mt41j128.cfg: add comments
2012-10-04 1:47 ` [U-Boot] [PATCH V3 00/32] " Troy Kisky
` (17 preceding siblings ...)
2012-10-04 1:47 ` [U-Boot] [PATCH V3 18/32] mx6q_4x_mt41j128.cfg: use symbols instead of hardcoded constants Troy Kisky
@ 2012-10-04 1:47 ` Troy Kisky
2012-10-04 1:47 ` [U-Boot] [PATCH V3 20/32] mx6q_4x_mt41j128.cfg: use ddr3 mode for reset Troy Kisky
` (15 subsequent siblings)
34 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-10-04 1:47 UTC (permalink / raw)
To: u-boot
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 55 ++++++++++++++++++++++----
1 file changed, 47 insertions(+), 8 deletions(-)
diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
index 84823f8..b859e2f 100644
--- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
@@ -53,7 +53,6 @@ WRITE_ENTRY1(IOM_DRAM_SDQS0, 0x00000030)
WRITE_ENTRY1(IOM_DRAM_SDQS1, 0x00000030)
WRITE_ENTRY1(IOM_DRAM_SDQS2, 0x00000030)
WRITE_ENTRY1(IOM_DRAM_SDQS3, 0x00000030)
-
WRITE_ENTRY1(IOM_DRAM_SDQS4, 0x00000030)
WRITE_ENTRY1(IOM_DRAM_SDQS5, 0x00000030)
WRITE_ENTRY1(IOM_DRAM_SDQS6, 0x00000030)
@@ -63,7 +62,6 @@ WRITE_ENTRY1(IOM_DRAM_DQM0, 0x00020030)
WRITE_ENTRY1(IOM_DRAM_DQM1, 0x00020030)
WRITE_ENTRY1(IOM_DRAM_DQM2, 0x00020030)
WRITE_ENTRY1(IOM_DRAM_DQM3, 0x00020030)
-
WRITE_ENTRY1(IOM_DRAM_DQM4, 0x00020030)
WRITE_ENTRY1(IOM_DRAM_DQM5, 0x00020030)
WRITE_ENTRY1(IOM_DRAM_DQM6, 0x00020030)
@@ -81,65 +79,105 @@ WRITE_ENTRY1(IOM_DRAM_SDBA2, 0x00000000)
WRITE_ENTRY1(IOM_DRAM_SDODT0, 0x00003030)
WRITE_ENTRY1(IOM_DRAM_SDODT1, 0x00003030)
+
WRITE_ENTRY1(IOM_GRP_B0DS, 0x00000030)
WRITE_ENTRY1(IOM_GRP_B1DS, 0x00000030)
-
WRITE_ENTRY1(IOM_GRP_B2DS, 0x00000030)
WRITE_ENTRY1(IOM_GRP_B3DS, 0x00000030)
WRITE_ENTRY1(IOM_GRP_B4DS, 0x00000030)
WRITE_ENTRY1(IOM_GRP_B5DS, 0x00000030)
-
WRITE_ENTRY1(IOM_GRP_B6DS, 0x00000030)
WRITE_ENTRY1(IOM_GRP_B7DS, 0x00000030)
+
WRITE_ENTRY1(IOM_GRP_ADDDS, 0x00000030)
+/* (differential input) */
WRITE_ENTRY1(IOM_DDRMODE_CTL, 0x00020000)
-
+/* disable ddr pullups */
WRITE_ENTRY1(IOM_GRP_DDRPKE, 0x00000000)
+/* (differential input) */
WRITE_ENTRY1(IOM_GRP_DDRMODE, 0x00020000)
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
WRITE_ENTRY1(IOM_GRP_CTLDS, 0x00000030)
WRITE_ENTRY1(IOM_GRP_DDR_TYPE, 0x000C0000)
+/* Read data DQ Byte0-3 delay */
WRITE_ENTRY1(MMDC_P0_MPRDDQBY0DL, 0x33333333)
WRITE_ENTRY1(MMDC_P0_MPRDDQBY1DL, 0x33333333)
WRITE_ENTRY1(MMDC_P0_MPRDDQBY2DL, 0x33333333)
WRITE_ENTRY1(MMDC_P0_MPRDDQBY3DL, 0x33333333)
-
WRITE_ENTRY1(MMDC_P1_MPRDDQBY0DL, 0x33333333)
WRITE_ENTRY1(MMDC_P1_MPRDDQBY1DL, 0x33333333)
WRITE_ENTRY1(MMDC_P1_MPRDDQBY2DL, 0x33333333)
WRITE_ENTRY1(MMDC_P1_MPRDDQBY3DL, 0x33333333)
+/*
+ * MDMISC, mirroring, interleaved (row/bank/col)
+ */
WRITE_ENTRY1(MMDC_P0_MDMISC, 0x00081740)
+/*
+ * MDSCR, con_req
+ */
WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00008000)
+/*
+ * MDCFG0, tRFC=0x56 clocks, tXS=0x5b clocks
+ * tXP=4 clocks, tXPDLL=13 clocks
+ * tFAW=24 clocks, cas=8 cycles
+ */
WRITE_ENTRY1(MMDC_P0_MDCFG0, 0x555A7975)
+/*
+ * MDCFG1, tRDC=8, tRP=8, tRC=27,tRAS=20,tRPA=tRP+1,tWR=8
+ * tMRD=4, tCWL=6
+ */
WRITE_ENTRY1(MMDC_P0_MDCFG1, 0xFF538E64)
+/*
+ * MDCFG2,tDLLK=512,tRTP=4,tWTR=4,tRRD=4
+ */
WRITE_ENTRY1(MMDC_P0_MDCFG2, 0x01FF00DB)
WRITE_ENTRY1(MMDC_P0_MDRWD, 0x000026D2)
WRITE_ENTRY1(MMDC_P0_MDOR, 0x005B0E21)
WRITE_ENTRY1(MMDC_P0_MDOTC, 0x09444040)
WRITE_ENTRY1(MMDC_P0_MDPDC, 0x00025576)
+
+/*
+ * Mx6Q - 64 bit wide ddr
+ * last address is (1<<28 (base) + 1<<30 - 1) / (1<<25) =
+ * 1<<3 + 1<<5 - 1 = 8 + 0x20 -1 = 0x27
+ */
+/* MDASP, CS0_END */
WRITE_ENTRY1(MMDC_P0_MDASP, 0x00000027)
+/*
+ * MDCTL, CS0 enable, CS1 disabled, row=14, col=10, burst=8, width=64/32bit
+ * mx6q : row+col+bank+width=14+10+3+3=30 = 1G
+ */
WRITE_ENTRY1(MMDC_P0_MDCTL, 0x831A0000)
+/* MDSCR, con_req, LOAD MR2, CS0, A3,A10 set (CAS Write=6), RZQ/2 */
WRITE_ENTRY1(MMDC_P0_MDSCR, 0x04088032)
WRITE_ENTRY1(MMDC_P0_MDSCR, 0x0408803A)
+/* LOAD MR3, CS0 */
WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00008033)
WRITE_ENTRY1(MMDC_P0_MDSCR, 0x0000803B)
+/* LOAD MR1, CS0, A1,A6 set Rtt=RZQ/2, ODI=RZQ/7 */
WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00428031)
WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00428039)
+/* LOAD MR0, CS0, A6,A8,A11 set CAS=8, WR=8, DLL reset */
WRITE_ENTRY1(MMDC_P0_MDSCR, 0x09408030)
WRITE_ENTRY1(MMDC_P0_MDSCR, 0x09408038)
+/* ZQ calibrate, CS0 */
WRITE_ENTRY1(MMDC_P0_MDSCR, 0x04008040)
WRITE_ENTRY1(MMDC_P0_MDSCR, 0x04008048)
WRITE_ENTRY1(MMDC_P0_MPZQHWCTRL, 0xA1380003)
WRITE_ENTRY1(MMDC_P1_MPZQHWCTRL, 0xA1380003)
+
+/* MDREF, 32KHz refresh, 4 refeshes each */
WRITE_ENTRY1(MMDC_P0_MDREF, 0x00005800)
WRITE_ENTRY1(MMDC_P0_MPODTCTRL, 0x00022227)
WRITE_ENTRY1(MMDC_P1_MPODTCTRL, 0x00022227)
+/* MPDGCTRL0/1 DQS GATE*/
WRITE_ENTRY1(MMDC_P0_MPDGCTRL0, 0x434B0350)
WRITE_ENTRY1(MMDC_P0_MPDGCTRL1, 0x034C0359)
WRITE_ENTRY1(MMDC_P1_MPDGCTRL0, 0x434B0350)
@@ -148,17 +186,18 @@ WRITE_ENTRY1(MMDC_P0_MPRDDLCTL, 0x4436383B)
WRITE_ENTRY1(MMDC_P1_MPRDDLCTL, 0x39393341)
WRITE_ENTRY1(MMDC_P0_MPWRDLCTL, 0x35373933)
WRITE_ENTRY1(MMDC_P1_MPWRDLCTL, 0x48254A36)
-
WRITE_ENTRY1(MMDC_P0_MPWLDECTRL0, 0x001F001F)
WRITE_ENTRY1(MMDC_P0_MPWLDECTRL1, 0x001F001F)
-
WRITE_ENTRY1(MMDC_P1_MPWLDECTRL0, 0x00440044)
WRITE_ENTRY1(MMDC_P1_MPWLDECTRL1, 0x00440044)
+/* MPMUR0 - Complete calibration by forced measurement */
WRITE_ENTRY1(MMDC_P0_MPMUR0, 0x00000800)
WRITE_ENTRY1(MMDC_P1_MPMUR0, 0x00000800)
+/* MDSCR, enable ddr */
WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00000000)
+/* MAPSR, 1024 cycles idle before self-refresh */
WRITE_ENTRY1(MMDC_P0_MAPSR, 0x00011006)
/* set the default clock gate to save power */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 20/32] mx6q_4x_mt41j128.cfg: use ddr3 mode for reset
2012-10-04 1:47 ` [U-Boot] [PATCH V3 00/32] " Troy Kisky
` (18 preceding siblings ...)
2012-10-04 1:47 ` [U-Boot] [PATCH V3 19/32] mx6q_4x_mt41j128.cfg: add comments Troy Kisky
@ 2012-10-04 1:47 ` Troy Kisky
2012-10-04 1:47 ` [U-Boot] [PATCH V3 21/32] mx6q_4x_mt41j128.cfg: skip initiailizing non-existent memory Troy Kisky
` (14 subsequent siblings)
34 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-10-04 1:47 UTC (permalink / raw)
To: u-boot
Bits 19-18 of IOMUXC_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET
should be 3 for DDR3 mode. The current value of 0 is
reserved in TRM.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
index b859e2f..9c622c8 100644
--- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
@@ -72,7 +72,7 @@ WRITE_ENTRY1(IOM_DRAM_RAS, 0x00020030)
WRITE_ENTRY1(IOM_DRAM_SDCLK_0, 0x00020030)
WRITE_ENTRY1(IOM_DRAM_SDCLK_1, 0x00020030)
-WRITE_ENTRY1(IOM_DRAM_RESET, 0x00020030)
+WRITE_ENTRY1(IOM_DRAM_RESET, 0x000e0030)
WRITE_ENTRY1(IOM_DRAM_SDCKE0, 0x00003000)
WRITE_ENTRY1(IOM_DRAM_SDCKE1, 0x00003000)
WRITE_ENTRY1(IOM_DRAM_SDBA2, 0x00000000)
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 21/32] mx6q_4x_mt41j128.cfg: skip initiailizing non-existent memory
2012-10-04 1:47 ` [U-Boot] [PATCH V3 00/32] " Troy Kisky
` (19 preceding siblings ...)
2012-10-04 1:47 ` [U-Boot] [PATCH V3 20/32] mx6q_4x_mt41j128.cfg: use ddr3 mode for reset Troy Kisky
@ 2012-10-04 1:47 ` Troy Kisky
2012-10-07 21:01 ` Eric Nelson
2012-10-04 1:47 ` [U-Boot] [PATCH V3 22/32] mx6q_4x_mt41j128.cfg: force ZQ calibration Troy Kisky
` (13 subsequent siblings)
34 siblings, 1 reply; 430+ messages in thread
From: Troy Kisky @ 2012-10-04 1:47 UTC (permalink / raw)
To: u-boot
Sabrelite does not have memory associated with CS1
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 5 -----
1 file changed, 5 deletions(-)
diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
index 9c622c8..2d03ff7 100644
--- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
@@ -155,20 +155,15 @@ WRITE_ENTRY1(MMDC_P0_MDCTL, 0x831A0000)
/* MDSCR, con_req, LOAD MR2, CS0, A3,A10 set (CAS Write=6), RZQ/2 */
WRITE_ENTRY1(MMDC_P0_MDSCR, 0x04088032)
-WRITE_ENTRY1(MMDC_P0_MDSCR, 0x0408803A)
/* LOAD MR3, CS0 */
WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00008033)
-WRITE_ENTRY1(MMDC_P0_MDSCR, 0x0000803B)
/* LOAD MR1, CS0, A1,A6 set Rtt=RZQ/2, ODI=RZQ/7 */
WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00428031)
-WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00428039)
/* LOAD MR0, CS0, A6,A8,A11 set CAS=8, WR=8, DLL reset */
WRITE_ENTRY1(MMDC_P0_MDSCR, 0x09408030)
-WRITE_ENTRY1(MMDC_P0_MDSCR, 0x09408038)
/* ZQ calibrate, CS0 */
WRITE_ENTRY1(MMDC_P0_MDSCR, 0x04008040)
-WRITE_ENTRY1(MMDC_P0_MDSCR, 0x04008048)
WRITE_ENTRY1(MMDC_P0_MPZQHWCTRL, 0xA1380003)
WRITE_ENTRY1(MMDC_P1_MPZQHWCTRL, 0xA1380003)
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 22/32] mx6q_4x_mt41j128.cfg: force ZQ calibration
2012-10-04 1:47 ` [U-Boot] [PATCH V3 00/32] " Troy Kisky
` (20 preceding siblings ...)
2012-10-04 1:47 ` [U-Boot] [PATCH V3 21/32] mx6q_4x_mt41j128.cfg: skip initiailizing non-existent memory Troy Kisky
@ 2012-10-04 1:47 ` Troy Kisky
2012-10-04 1:47 ` [U-Boot] [PATCH V3 23/32] mx6: soc: update get_cpu_rev and get_imx_type for mx6solo/sololite Troy Kisky
` (12 subsequent siblings)
34 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-10-04 1:47 UTC (permalink / raw)
To: u-boot
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
index 2d03ff7..9e20db0 100644
--- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
@@ -164,8 +164,8 @@ WRITE_ENTRY1(MMDC_P0_MDSCR, 0x09408030)
/* ZQ calibrate, CS0 */
WRITE_ENTRY1(MMDC_P0_MDSCR, 0x04008040)
-WRITE_ENTRY1(MMDC_P0_MPZQHWCTRL, 0xA1380003)
-WRITE_ENTRY1(MMDC_P1_MPZQHWCTRL, 0xA1380003)
+WRITE_ENTRY1(MMDC_P0_MPZQHWCTRL, 0xA1390003)
+WRITE_ENTRY1(MMDC_P1_MPZQHWCTRL, 0xA1390003)
/* MDREF, 32KHz refresh, 4 refeshes each */
WRITE_ENTRY1(MMDC_P0_MDREF, 0x00005800)
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 23/32] mx6: soc: update get_cpu_rev and get_imx_type for mx6solo/sololite
2012-10-04 1:47 ` [U-Boot] [PATCH V3 00/32] " Troy Kisky
` (21 preceding siblings ...)
2012-10-04 1:47 ` [U-Boot] [PATCH V3 22/32] mx6q_4x_mt41j128.cfg: force ZQ calibration Troy Kisky
@ 2012-10-04 1:47 ` Troy Kisky
2012-10-04 1:47 ` [U-Boot] [PATCH V3 24/32] mx6: use CONFIG_MX6 instead of CONFIG_MX6Q Troy Kisky
` (11 subsequent siblings)
34 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-10-04 1:47 UTC (permalink / raw)
To: u-boot
Previously, the same value was returned for both mx6dl and mx6solo.
Check number of processors to differeniate.
Also, a freescale patch says that sololite has its cpu/rev
stored at 0x280 instead of 0x260.
I don't have a sololite to verify.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
Changed in V3.
V2 had created in new function get_cpu_type instead.
---
arch/arm/cpu/armv7/mx6/soc.c | 32 +++++++++++++++++++++--------
arch/arm/imx-common/cpu.c | 16 ++++++++-------
arch/arm/include/asm/arch-mx5/sys_proto.h | 9 +++++++-
arch/arm/include/asm/arch-mx6/imx-regs.h | 2 ++
arch/arm/include/asm/arch-mx6/sys_proto.h | 9 +++++++-
5 files changed, 51 insertions(+), 17 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index bc65767..a8aad5d 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -31,17 +31,33 @@
#include <asm/arch/sys_proto.h>
#include <asm/imx-common/boot_mode.h>
+struct scu_regs {
+ u32 ctrl;
+ u32 config;
+ u32 status;
+ u32 invalidate;
+ u32 fpga_rev;
+};
+
u32 get_cpu_rev(void)
{
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
- int reg = readl(&anatop->digprog);
-
- /* Read mx6 variant: quad, dual or solo */
- int system_rev = (reg >> 4) & 0xFF000;
- /* Read mx6 silicon revision */
- system_rev |= (reg & 0xFF) + 0x10;
-
- return system_rev;
+ u32 reg = readl(&anatop->digprog_sololite);
+ u32 type = ((reg >> 16) & 0xff);
+
+ if (type != MXC_CPU_MX6SL) {
+ reg = readl(&anatop->digprog);
+ type = ((reg >> 16) & 0xff);
+ if (type == MXC_CPU_MX6DL) {
+ struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
+ u32 cfg = readl(&scu->config) & 3;
+
+ if (!cfg)
+ type = MXC_CPU_MX6SOLO;
+ }
+ }
+ reg &= 0xff; /* mx6 silicon revision */
+ return (type << 12) | (reg + 0x10);
}
void init_aips(void)
diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
index a10d12d..102c254 100644
--- a/arch/arm/imx-common/cpu.c
+++ b/arch/arm/imx-common/cpu.c
@@ -67,18 +67,20 @@ char *get_reset_cause(void)
#if defined(CONFIG_DISPLAY_CPUINFO)
-static const char *get_imx_type(u32 imxtype)
+const char *get_imx_type(u32 imxtype)
{
switch (imxtype) {
- case 0x63:
+ case MXC_CPU_MX6Q:
return "6Q"; /* Quad-core version of the mx6 */
- case 0x61:
- return "6DS"; /* Dual/Solo version of the mx6 */
- case 0x60:
+ case MXC_CPU_MX6DL:
+ return "6DL"; /* Dual Lite version of the mx6 */
+ case MXC_CPU_MX6SOLO:
+ return "6SOLO"; /* Solo version of the mx6 */
+ case MXC_CPU_MX6SL:
return "6SL"; /* Solo-Lite version of the mx6 */
- case 0x51:
+ case MXC_CPU_MX51:
return "51";
- case 0x53:
+ case MXC_CPU_MX53:
return "53";
default:
return "??";
diff --git a/arch/arm/include/asm/arch-mx5/sys_proto.h b/arch/arm/include/asm/arch-mx5/sys_proto.h
index 7b5246e..4435be1 100644
--- a/arch/arm/include/asm/arch-mx5/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx5/sys_proto.h
@@ -24,8 +24,15 @@
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
-u32 get_cpu_rev(void);
+#define MXC_CPU_MX51 0x51
+#define MXC_CPU_MX53 0x53
+#define MXC_CPU_MX6SL 0x60
+#define MXC_CPU_MX6DL 0x61
+#define MXC_CPU_MX6SOLO 0x62
+#define MXC_CPU_MX6Q 0x63
+
#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev)
+u32 get_cpu_rev(void);
void sdelay(unsigned long);
void set_chipselect_size(int const);
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index dc737ba..b3a0d90 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -558,6 +558,8 @@ struct anatop_regs {
u32 usb2_misc_clr; /* 0x258 */
u32 usb2_misc_tog; /* 0x25c */
u32 digprog; /* 0x260 */
+ u32 reserved1[7];
+ u32 digprog_sololite; /* 0x280 */
};
#define ANATOP_PFD_480_PFD0_FRAC_SHIFT 0
diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h
index 711b30d..6627bbc 100644
--- a/arch/arm/include/asm/arch-mx6/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx6/sys_proto.h
@@ -24,9 +24,16 @@
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
-#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev)
+#define MXC_CPU_MX51 0x51
+#define MXC_CPU_MX53 0x53
+#define MXC_CPU_MX6SL 0x60
+#define MXC_CPU_MX6DL 0x61
+#define MXC_CPU_MX6SOLO 0x62
+#define MXC_CPU_MX6Q 0x63
+#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev)
u32 get_cpu_rev(void);
+const char *get_imx_type(u32 imxtype);
void set_vddsoc(u32 mv);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 24/32] mx6: use CONFIG_MX6 instead of CONFIG_MX6Q
2012-10-04 1:47 ` [U-Boot] [PATCH V3 00/32] " Troy Kisky
` (22 preceding siblings ...)
2012-10-04 1:47 ` [U-Boot] [PATCH V3 23/32] mx6: soc: update get_cpu_rev and get_imx_type for mx6solo/sololite Troy Kisky
@ 2012-10-04 1:47 ` Troy Kisky
2012-10-08 13:41 ` Stefano Babic
2012-10-04 1:47 ` [U-Boot] [PATCH V3 25/32] imx-common: cpu: add imx_ddr_size Troy Kisky
` (10 subsequent siblings)
34 siblings, 1 reply; 430+ messages in thread
From: Troy Kisky @ 2012-10-04 1:47 UTC (permalink / raw)
To: u-boot
Use CONFIG_MX6 when the particular processor
variant isn't important.
Reserve the use of CONFIG_MX6Q to
specifically test for quad cores variant.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
drivers/gpio/mxc_gpio.c | 6 +++---
drivers/video/ipu_regs.h | 2 +-
include/configs/mx6qarm2.h | 1 +
include/configs/mx6qsabre_common.h | 1 +
include/configs/mx6qsabrelite.h | 1 +
5 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c
index 2c79bff..a388064 100644
--- a/drivers/gpio/mxc_gpio.c
+++ b/drivers/gpio/mxc_gpio.c
@@ -42,14 +42,14 @@ static unsigned long gpio_ports[] = {
[1] = GPIO2_BASE_ADDR,
[2] = GPIO3_BASE_ADDR,
#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
- defined(CONFIG_MX53) || defined(CONFIG_MX6Q)
+ defined(CONFIG_MX53) || defined(CONFIG_MX6)
[3] = GPIO4_BASE_ADDR,
#endif
-#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6Q)
+#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6)
[4] = GPIO5_BASE_ADDR,
[5] = GPIO6_BASE_ADDR,
#endif
-#if defined(CONFIG_MX53) || defined(CONFIG_MX6Q)
+#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
[6] = GPIO7_BASE_ADDR,
#endif
};
diff --git a/drivers/video/ipu_regs.h b/drivers/video/ipu_regs.h
index a43aa03..982e252 100644
--- a/drivers/video/ipu_regs.h
+++ b/drivers/video/ipu_regs.h
@@ -55,7 +55,7 @@
#define IPU_TPM_REG_BASE 0x01060000
#define IPU_DC_TMPL_REG_BASE 0x01080000
#define IPU_ISP_TBPR_REG_BASE 0x010C0000
-#elif defined(CONFIG_MX6Q)
+#elif defined(CONFIG_MX6)
#define IPU_CPMEM_REG_BASE 0x00100000
#define IPU_LUT_REG_BASE 0x00120000
#define IPU_SRM_REG_BASE 0x00140000
diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h
index 965bea3..8e5b81e 100644
--- a/include/configs/mx6qarm2.h
+++ b/include/configs/mx6qarm2.h
@@ -22,6 +22,7 @@
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_MX6
#define CONFIG_MX6Q
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
diff --git a/include/configs/mx6qsabre_common.h b/include/configs/mx6qsabre_common.h
index 247e8d6..5a940da 100644
--- a/include/configs/mx6qsabre_common.h
+++ b/include/configs/mx6qsabre_common.h
@@ -17,6 +17,7 @@
#ifndef __MX6QSABRE_COMMON_CONFIG_H
#define __MX6QSABRE_COMMON_CONFIG_H
+#define CONFIG_MX6
#define CONFIG_MX6Q
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
index e7bf658..6a10232 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -22,6 +22,7 @@
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_MX6
#define CONFIG_MX6Q
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 25/32] imx-common: cpu: add imx_ddr_size
2012-10-04 1:47 ` [U-Boot] [PATCH V3 00/32] " Troy Kisky
` (23 preceding siblings ...)
2012-10-04 1:47 ` [U-Boot] [PATCH V3 24/32] mx6: use CONFIG_MX6 instead of CONFIG_MX6Q Troy Kisky
@ 2012-10-04 1:47 ` Troy Kisky
2012-10-08 13:06 ` Stefano Babic
2012-10-04 1:47 ` [U-Boot] [PATCH V3 26/32] arch-mx6: add mx6dl_pins.h Troy Kisky
` (9 subsequent siblings)
34 siblings, 1 reply; 430+ messages in thread
From: Troy Kisky @ 2012-10-04 1:47 UTC (permalink / raw)
To: u-boot
Read memory setup registers to determine size
of available ram. This routine works for mx53/mx6x
I need this because when mx6solo called get_ram_size
with a too large maximum size, the system hanged.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
New patch with V3. V2 had code in mx6qsabrelite.c
---
arch/arm/imx-common/cpu.c | 50 +++++++++++++++++++++++++++++
arch/arm/include/asm/arch-mx5/sys_proto.h | 1 +
arch/arm/include/asm/arch-mx6/sys_proto.h | 1 +
3 files changed, 52 insertions(+)
diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
index 102c254..5081908 100644
--- a/arch/arm/imx-common/cpu.c
+++ b/arch/arm/imx-common/cpu.c
@@ -65,6 +65,56 @@ char *get_reset_cause(void)
}
}
+#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
+#if defined(CONFIG_MX53)
+#define MEMCTL_BASE ESDCTL_BASE_ADDR;
+#else
+#define MEMCTL_BASE MMDC_P0_BASE_ADDR;
+#endif
+static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
+static const unsigned char bank_lookup[] = {3, 2};
+
+struct esd_mmdc_regs {
+ uint32_t ctl;
+ uint32_t pdc;
+ uint32_t otc;
+ uint32_t cfg0;
+ uint32_t cfg1;
+ uint32_t cfg2;
+ uint32_t misc;
+ uint32_t scr;
+ uint32_t ref;
+ uint32_t rsvd1;
+ uint32_t rsvd2;
+ uint32_t rwd;
+ uint32_t or;
+ uint32_t mrr;
+ uint32_t cfg3lp;
+ uint32_t mr4;
+};
+
+#define ESD_MMDC_CTL_GET_ROW(mdctl) ((ctl >> 24) & 7)
+#define ESD_MMDC_CTL_GET_COLUMN(mdctl) ((ctl >> 20) & 7)
+#define ESD_MMDC_CTL_GET_WIDTH(mdctl) ((ctl >> 16) & 3)
+#define ESD_MMDC_CTL_GET_CS1(mdctl) ((ctl >> 30) & 1)
+#define ESD_MMDC_MISC_GET_BANK(mdmisc) ((misc >> 5) & 1)
+
+unsigned imx_ddr_size(void)
+{
+ struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE;
+ unsigned ctl = readl(&mem->ctl);
+ unsigned misc = readl(&mem->misc);
+ int bits = 11 + 0 + 0 + 1; /* row + col + bank + width */
+
+ bits += ESD_MMDC_CTL_GET_ROW(ctl);
+ bits += col_lookup[ESD_MMDC_CTL_GET_COLUMN(ctl)];
+ bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)];
+ bits += ESD_MMDC_CTL_GET_WIDTH(ctl);
+ bits += ESD_MMDC_CTL_GET_CS1(ctl);
+ return 1 << bits;
+}
+#endif
+
#if defined(CONFIG_DISPLAY_CPUINFO)
const char *get_imx_type(u32 imxtype)
diff --git a/arch/arm/include/asm/arch-mx5/sys_proto.h b/arch/arm/include/asm/arch-mx5/sys_proto.h
index 4435be1..93ad1c6 100644
--- a/arch/arm/include/asm/arch-mx5/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx5/sys_proto.h
@@ -33,6 +33,7 @@
#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev)
u32 get_cpu_rev(void);
+unsigned imx_ddr_size(void);
void sdelay(unsigned long);
void set_chipselect_size(int const);
diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h
index 6627bbc..3193297 100644
--- a/arch/arm/include/asm/arch-mx6/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx6/sys_proto.h
@@ -34,6 +34,7 @@
#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev)
u32 get_cpu_rev(void);
const char *get_imx_type(u32 imxtype);
+unsigned imx_ddr_size(void);
void set_vddsoc(u32 mv);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 26/32] arch-mx6: add mx6dl_pins.h
2012-10-04 1:47 ` [U-Boot] [PATCH V3 00/32] " Troy Kisky
` (24 preceding siblings ...)
2012-10-04 1:47 ` [U-Boot] [PATCH V3 25/32] imx-common: cpu: add imx_ddr_size Troy Kisky
@ 2012-10-04 1:47 ` Troy Kisky
2012-10-04 1:47 ` [U-Boot] [PATCH V3 27/32] mx6qsabrelite: add support for mx6 solo/duallite Troy Kisky
` (8 subsequent siblings)
34 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-10-04 1:47 UTC (permalink / raw)
To: u-boot
Only the values used in the sabrelite board are
added currently. Add more as other boards use them.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
arch/arm/include/asm/arch-mx6/mx6dl_pins.h | 118 ++++++++++++++++++++++++++++
1 file changed, 118 insertions(+)
create mode 100644 arch/arm/include/asm/arch-mx6/mx6dl_pins.h
diff --git a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
new file mode 100644
index 0000000..5848013
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
@@ -0,0 +1,118 @@
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+#ifndef __ASM_ARCH_MX6_MX6DL_PINS_H__
+#define __ASM_ARCH_MX6_MX6DL_PINS_H__
+
+#include <asm/imx-common/iomux-v3.h>
+
+/* Use to set PAD control */
+#define PAD_CTL_HYS (1 << 16)
+#define PAD_CTL_PUS_100K_DOWN (0 << 14)
+#define PAD_CTL_PUS_47K_UP (1 << 14)
+#define PAD_CTL_PUS_100K_UP (2 << 14)
+#define PAD_CTL_PUS_22K_UP (3 << 14)
+
+#define PAD_CTL_PUE (1 << 13)
+#define PAD_CTL_PKE (1 << 12)
+#define PAD_CTL_ODE (1 << 11)
+#define PAD_CTL_SPEED_LOW (1 << 6)
+#define PAD_CTL_SPEED_MED (2 << 6)
+#define PAD_CTL_SPEED_HIGH (3 << 6)
+#define PAD_CTL_DSE_DISABLE (0 << 3)
+#define PAD_CTL_DSE_240ohm (1 << 3)
+#define PAD_CTL_DSE_120ohm (2 << 3)
+#define PAD_CTL_DSE_80ohm (3 << 3)
+#define PAD_CTL_DSE_60ohm (4 << 3)
+#define PAD_CTL_DSE_48ohm (5 << 3)
+#define PAD_CTL_DSE_40ohm (6 << 3)
+#define PAD_CTL_DSE_34ohm (7 << 3)
+#define PAD_CTL_SRE_FAST (1 << 0)
+#define PAD_CTL_SRE_SLOW (0 << 0)
+
+#define IOMUX_CONFIG_SION 0x10
+#define NO_MUX_I 0
+#define NO_PAD_I 0
+enum {
+ MX6DL_PAD_EIM_D16__ECSPI1_SCLK = IOMUX_PAD(0x0514, 0x0144, 1, 0x07D8, 2, 0),
+ MX6DL_PAD_EIM_D17__ECSPI1_MISO = IOMUX_PAD(0x0518, 0x0148, 1, 0x07DC, 2, 0),
+ MX6DL_PAD_EIM_D18__ECSPI1_MOSI = IOMUX_PAD(0x051C, 0x014C, 1, 0x07E0, 2, 0),
+ MX6DL_PAD_EIM_D19__GPIO_3_19 = IOMUX_PAD(0x0520, 0x0150, 5, 0x0000, 0, 0),
+ MX6DL_PAD_EIM_D21__GPIO_3_21 = IOMUX_PAD(0x0528, 0x0158, 5, 0x0000, 0, 0),
+ MX6DL_PAD_EIM_D21__I2C1_SCL = IOMUX_PAD(0x0528, 0x0158, 6 | IOMUX_CONFIG_SION, 0x0868, 1, 0),
+ MX6DL_PAD_EIM_D23__GPIO_3_23 = IOMUX_PAD(0x0530, 0x0160, 5, 0x0000, 0, 0),
+ MX6DL_PAD_EIM_D26__UART2_TXD = IOMUX_PAD(0x053C, 0x016C, 4, 0x0000, 0, 0),
+ MX6DL_PAD_EIM_D27__UART2_RXD = IOMUX_PAD(0x0540, 0x0170, 4, 0x0904, 1, 0),
+ MX6DL_PAD_EIM_D28__I2C1_SDA = IOMUX_PAD(0x0544, 0x0174, 1 | IOMUX_CONFIG_SION, 0x086C, 1, 0),
+ MX6DL_PAD_EIM_D28__GPIO_3_28 = IOMUX_PAD(0x0544, 0x0174, 5, 0x0000, 0, 0),
+ MX6DL_PAD_ENET_MDC__ENET_MDC = IOMUX_PAD(0x05B8, 0x01E8, 1, 0x0000, 0, 0),
+ MX6DL_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x05BC, 0x01EC, 1, 0x0810, 0, 0),
+ MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK = IOMUX_PAD(0x05C0, 0x01F0, 1, 0x0000, 0, 0),
+ MX6DL_PAD_ENET_RXD0__GPIO_1_27 = IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0),
+ MX6DL_PAD_GPIO_16__GPIO_7_11 = IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0),
+ MX6DL_PAD_GPIO_16__I2C3_SDA = IOMUX_PAD(0x05E4, 0x0214, 6 | IOMUX_CONFIG_SION, 0x087C, 1, 0),
+ MX6DL_PAD_GPIO_17__GPIO_7_12 = IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0),
+ MX6DL_PAD_GPIO_18__GPIO_7_13 = IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0),
+ MX6DL_PAD_GPIO_19__GPIO_4_5 = IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0),
+ MX6DL_PAD_GPIO_5__GPIO_1_5 = IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0),
+ MX6DL_PAD_GPIO_5__I2C3_SCL = IOMUX_PAD(0x0600, 0x0230, 6 | IOMUX_CONFIG_SION, 0x0878, 2, 0),
+ MX6DL_PAD_KEY_COL3__I2C2_SCL = IOMUX_PAD(0x0638, 0x0250, 4 | IOMUX_CONFIG_SION, 0x0870, 1, 0),
+ MX6DL_PAD_KEY_COL3__GPIO_4_12 = IOMUX_PAD(0x0638, 0x0250, 5, 0x0000, 0, 0),
+ MX6DL_PAD_KEY_ROW3__I2C2_SDA = IOMUX_PAD(0x064C, 0x0264, 4 | IOMUX_CONFIG_SION, 0x0874, 1, 0),
+ MX6DL_PAD_KEY_ROW3__GPIO_4_13 = IOMUX_PAD(0x064C, 0x0264, 5, 0x0000, 0, 0),
+ MX6DL_PAD_NANDF_D1__GPIO_2_1 = IOMUX_PAD(0x0670, 0x0288, 5, 0x0000, 0, 0),
+ MX6DL_PAD_NANDF_D2__GPIO_2_2 = IOMUX_PAD(0x0674, 0x028C, 5, 0x0000, 0, 0),
+ MX6DL_PAD_NANDF_D3__GPIO_2_3 = IOMUX_PAD(0x0678, 0x0290, 5, 0x0000, 0, 0),
+ MX6DL_PAD_NANDF_D4__GPIO_2_4 = IOMUX_PAD(0x067C, 0x0294, 5, 0x0000, 0, 0),
+ MX6DL_PAD_NANDF_D6__GPIO_2_6 = IOMUX_PAD(0x0684, 0x029C, 5, 0x0000, 0, 0),
+ MX6DL_PAD_RGMII_RD0__ENET_RGMII_RD0 = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0818, 1, 0),
+ MX6DL_PAD_RGMII_RD0__GPIO_6_25 = IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0),
+ MX6DL_PAD_RGMII_RD1__ENET_RGMII_RD1 = IOMUX_PAD(0x0698, 0x02B0, 1, 0x081C, 1, 0),
+ MX6DL_PAD_RGMII_RD1__GPIO_6_27 = IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0),
+ MX6DL_PAD_RGMII_RD2__ENET_RGMII_RD2 = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0820, 1, 0),
+ MX6DL_PAD_RGMII_RD2__GPIO_6_28 = IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0),
+ MX6DL_PAD_RGMII_RD3__ENET_RGMII_RD3 = IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0824, 1, 0),
+ MX6DL_PAD_RGMII_RD3__GPIO_6_29 = IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0),
+ MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0828, 1, 0),
+ MX6DL_PAD_RGMII_RX_CTL__GPIO_6_24 = IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0),
+ MX6DL_PAD_RGMII_RXC__ENET_RGMII_RXC = IOMUX_PAD(0x06A8, 0x02C0, 1, 0x0814, 1, 0),
+ MX6DL_PAD_RGMII_RXC__GPIO_6_30 = IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0),
+ MX6DL_PAD_RGMII_TD0__ENET_RGMII_TD0 = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0),
+ MX6DL_PAD_RGMII_TD1__ENET_RGMII_TD1 = IOMUX_PAD(0x06B0, 0x02C8, 1, 0x0000, 0, 0),
+ MX6DL_PAD_RGMII_TD2__ENET_RGMII_TD2 = IOMUX_PAD(0x06B4, 0x02CC, 1, 0x0000, 0, 0),
+ MX6DL_PAD_RGMII_TD3__ENET_RGMII_TD3 = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0),
+ MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL = IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0),
+ MX6DL_PAD_RGMII_TXC__ENET_RGMII_TXC = IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0),
+ MX6DL_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x06F4, 0x030C, 0, 0x0934, 1, 0),
+ MX6DL_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x06F8, 0x0310, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+ MX6DL_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0),
+ MX6DL_PAD_SD3_DAT1__USDHC3_DAT1 = IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0),
+ MX6DL_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0),
+ MX6DL_PAD_SD3_DAT3__USDHC3_DAT3 = IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0),
+ MX6DL_PAD_SD3_DAT5__GPIO_7_0 = IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0),
+ MX6DL_PAD_SD3_DAT6__UART1_RXD = IOMUX_PAD(0x0714, 0x032C, 1, 0x08FC, 2, 0),
+ MX6DL_PAD_SD3_DAT7__UART1_TXD = IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0),
+ MX6DL_PAD_SD4_CLK__USDHC4_CLK = IOMUX_PAD(0x0720, 0x0338, 0, 0x0938, 1, 0),
+ MX6DL_PAD_SD4_CMD__USDHC4_CMD = IOMUX_PAD(0x0724, 0x033C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+ MX6DL_PAD_SD4_DAT0__USDHC4_DAT0 = IOMUX_PAD(0x0728, 0x0340, 1, 0x0000, 0, 0),
+ MX6DL_PAD_SD4_DAT1__USDHC4_DAT1 = IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0),
+ MX6DL_PAD_SD4_DAT2__USDHC4_DAT2 = IOMUX_PAD(0x0730, 0x0348, 1, 0x0000, 0, 0),
+ MX6DL_PAD_SD4_DAT3__USDHC4_DAT3 = IOMUX_PAD(0x0734, 0x034C, 1, 0x0000, 0, 0),
+};
+#endif /* __ASM_ARCH_MX6_MX6DL_PINS_H__ */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 27/32] mx6qsabrelite: add support for mx6 solo/duallite
2012-10-04 1:47 ` [U-Boot] [PATCH V3 00/32] " Troy Kisky
` (25 preceding siblings ...)
2012-10-04 1:47 ` [U-Boot] [PATCH V3 26/32] arch-mx6: add mx6dl_pins.h Troy Kisky
@ 2012-10-04 1:47 ` Troy Kisky
2012-10-04 3:23 ` Otavio Salvador
2012-10-04 1:47 ` [U-Boot] [PATCH V3 28/32] mx6q_4x_mt41j128.cfg: add mx6 solo/duallite support Troy Kisky
` (7 subsequent siblings)
34 siblings, 1 reply; 430+ messages in thread
From: Troy Kisky @ 2012-10-04 1:47 UTC (permalink / raw)
To: u-boot
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
board/freescale/mx6qsabrelite/mx6qsabrelite.c | 235 ++++++-------------------
board/freescale/mx6qsabrelite/pads.h | 172 ++++++++++++++++++
2 files changed, 229 insertions(+), 178 deletions(-)
create mode 100644 board/freescale/mx6qsabrelite/pads.h
diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
index 4b4e89b..454972c 100644
--- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
@@ -26,6 +26,8 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6x_pins.h>
+#include <asm/arch/mx6dl_pins.h>
+#include <asm/arch/sys_proto.h>
#include <asm/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
@@ -38,162 +40,52 @@
#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
-#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
- PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-#define SPI_PAD_CTRL (PAD_CTL_HYS | \
- PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
-
-#define BUTTON_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
- PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+#ifdef CONFIG_MX6Q
+#include "pads.h"
+#endif
+#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
+#define FOR_DL_SOLO
+#include "pads.h"
+#endif
-int dram_init(void)
+int cpu_is_mx6q(void)
{
- gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
-
- return 0;
+ return (get_cpu_rev() >> 12) == MXC_CPU_MX6Q;
}
-iomux_v3_cfg_t uart1_pads[] = {
- MX6Q_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6Q_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-iomux_v3_cfg_t uart2_pads[] = {
- MX6Q_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-
-/* I2C1, SGTL5000 */
-struct i2c_pads_info i2c_pad_info0 = {
- .scl = {
- .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
- .gpio_mode = MX6Q_PAD_EIM_D21__GPIO_3_21 | PC,
- .gp = IMX_GPIO_NR(3, 21)
- },
- .sda = {
- .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
- .gpio_mode = MX6Q_PAD_EIM_D28__GPIO_3_28 | PC,
- .gp = IMX_GPIO_NR(3, 28)
- }
-};
-
-/* I2C2 Camera, MIPI */
-struct i2c_pads_info i2c_pad_info1 = {
- .scl = {
- .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
- .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO_4_12 | PC,
- .gp = IMX_GPIO_NR(4, 12)
- },
- .sda = {
- .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
- .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO_4_13 | PC,
- .gp = IMX_GPIO_NR(4, 13)
- }
-};
-
-/* I2C3, J15 - RGB connector */
-struct i2c_pads_info i2c_pad_info2 = {
- .scl = {
- .i2c_mode = MX6Q_PAD_GPIO_5__I2C3_SCL | PC,
- .gpio_mode = MX6Q_PAD_GPIO_5__GPIO_1_5 | PC,
- .gp = IMX_GPIO_NR(1, 5)
- },
- .sda = {
- .i2c_mode = MX6Q_PAD_GPIO_16__I2C3_SDA | PC,
- .gpio_mode = MX6Q_PAD_GPIO_16__GPIO_7_11 | PC,
- .gp = IMX_GPIO_NR(7, 11)
- }
-};
+#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
+#ifdef CONFIG_MX6Q
+#define GET_MX6_REF(ref) (cpu_is_mx6q() ? mx6q_##ref : mx6dl_solo_##ref)
+#define IOMUX_SETUP(list) iomux_setup(mx6q_##list, ARRAY_SIZE(mx6q_##list), \
+ mx6dl_solo_##list, ARRAY_SIZE(mx6dl_solo_##list))
-iomux_v3_cfg_t usdhc3_pads[] = {
- MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
-};
+int iomux_setup(iomux_v3_cfg_t *mx6q_pad_list, int mx6q_pad_cnt,
+ iomux_v3_cfg_t *mx6dl_solo_pad_list, int mx6dl_solo_pad_cnt)
+{
+ int mx6q = cpu_is_mx6q();
+ iomux_v3_cfg_t *p = mx6q ? mx6q_pad_list : mx6dl_solo_pad_list;
+ int cnt = mx6q ? mx6q_pad_cnt : mx6dl_solo_pad_cnt;
-iomux_v3_cfg_t usdhc4_pads[] = {
- MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
-};
+ return imx_iomux_v3_setup_multiple_pads(p, cnt);
+}
-iomux_v3_cfg_t enet_pads1[] = {
- MX6Q_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
- /* pin 35 - 1 (PHY_AD2) on reset */
- MX6Q_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* pin 32 - 1 - (MODE0) all */
- MX6Q_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* pin 31 - 1 - (MODE1) all */
- MX6Q_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* pin 28 - 1 - (MODE2) all */
- MX6Q_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* pin 27 - 1 - (MODE3) all */
- MX6Q_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
- MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* pin 42 PHY nRST */
- MX6Q_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
+#else
+#define GET_MX6_REF(ref) (mx6dl_solo_##ref)
+#define IOMUX_SETUP(list) imx_iomux_v3_setup_multiple_pads( \
+ mx6dl_solo_##list, ARRAY_SIZE(mx6dl_solo_##list))
+#endif
+#else
-iomux_v3_cfg_t enet_pads2[] = {
- MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
-};
+#define GET_MX6_REF(ref) (mx6q_##ref)
+#define IOMUX_SETUP(list) imx_iomux_v3_setup_multiple_pads( \
+ mx6q_##list, ARRAY_SIZE(mx6q_##list))
+#endif
-/* Button assignments for J14 */
-static iomux_v3_cfg_t button_pads[] = {
- /* Menu */
- MX6Q_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
- /* Back */
- MX6Q_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
- /* Labelled Search (mapped to Power under Android) */
- MX6Q_PAD_NANDF_D3__GPIO_2_3 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
- /* Home */
- MX6Q_PAD_NANDF_D4__GPIO_2_4 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
- /* Volume Down */
- MX6Q_PAD_GPIO_19__GPIO_4_5 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
- /* Volume Up */
- MX6Q_PAD_GPIO_18__GPIO_7_13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
-};
+int dram_init(void)
+{
+ gd->ram_size = imx_ddr_size();
+ return 0;
+}
static void setup_iomux_enet(void)
{
@@ -203,30 +95,26 @@ static void setup_iomux_enet(void)
gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
- imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
+ IOMUX_SETUP(enet_pads1);
gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
/* Need delay 10ms according to KSZ9021 spec */
udelay(1000 * 10);
gpio_set_value(IMX_GPIO_NR(3, 23), 1);
- imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
+ IOMUX_SETUP(enet_pads2);
}
-iomux_v3_cfg_t usb_pads[] = {
- MX6Q_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
static void setup_iomux_uart(void)
{
- imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
- imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+ IOMUX_SETUP(uart1_pads);
+ IOMUX_SETUP(uart2_pads);
}
#ifdef CONFIG_USB_EHCI_MX6
int board_ehci_hcd_init(int port)
{
- imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
+ IOMUX_SETUP(usb_pads);
/* Reset USB hub */
gpio_direction_output(IMX_GPIO_NR(7, 12), 0);
@@ -267,12 +155,10 @@ int board_mmc_init(bd_t *bis)
for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
switch (index) {
case 0:
- imx_iomux_v3_setup_multiple_pads(
- usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ IOMUX_SETUP(usdhc3_pads);
break;
case 1:
- imx_iomux_v3_setup_multiple_pads(
- usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+ IOMUX_SETUP(usdhc4_pads);
break;
default:
printf("Warning: you configured more USDHC controllers"
@@ -294,19 +180,10 @@ u32 get_board_rev(void)
}
#ifdef CONFIG_MXC_SPI
-iomux_v3_cfg_t ecspi1_pads[] = {
- /* SS1 */
- MX6Q_PAD_EIM_D19__GPIO_3_19 | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX6Q_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX6Q_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
-};
-
void setup_spi(void)
{
gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1);
- imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
- ARRAY_SIZE(ecspi1_pads));
+ IOMUX_SETUP(ecspi1_pads);
}
#endif
@@ -342,8 +219,7 @@ int board_eth_init(bd_t *bis)
static void setup_buttons(void)
{
- imx_iomux_v3_setup_multiple_pads(button_pads,
- ARRAY_SIZE(button_pads));
+ IOMUX_SETUP(button_pads);
}
#ifdef CONFIG_CMD_SATA
@@ -382,15 +258,17 @@ int board_early_init_f(void)
int board_init(void)
{
+ struct i2c_pads_info *p = GET_MX6_REF(i2c_pad_info);
+
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
#ifdef CONFIG_MXC_SPI
setup_spi();
#endif
- setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
- setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
- setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &p[0]);
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &p[1]);
+ setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &p[2]);
#ifdef CONFIG_CMD_SATA
setup_sata();
@@ -401,9 +279,10 @@ int board_init(void)
int checkboard(void)
{
- puts("Board: MX6Q-Sabre Lite\n");
-
- return 0;
+ puts("Board: MX");
+ puts(get_imx_type(get_cpu_rev() >> 12));
+ puts("-Sabre Lite\n");
+ return 0;
}
struct button_key {
diff --git a/board/freescale/mx6qsabrelite/pads.h b/board/freescale/mx6qsabrelite/pads.h
new file mode 100644
index 0000000..e7ffe21
--- /dev/null
+++ b/board/freescale/mx6qsabrelite/pads.h
@@ -0,0 +1,172 @@
+#undef MX6PAD
+#undef MX6NAME
+
+#ifdef FOR_DL_SOLO
+#define MX6PAD(a) MX6DL_PAD_##a
+#define MX6NAME(a) mx6dl_solo_##a
+#else
+#define MX6PAD(a) MX6Q_PAD_##a
+#define MX6NAME(a) mx6q_##a
+#endif
+
+#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | \
+ PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define BUTTON_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+iomux_v3_cfg_t MX6NAME(uart1_pads)[] = {
+ MX6PAD(SD3_DAT6__UART1_RXD) | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6PAD(SD3_DAT7__UART1_TXD) | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+iomux_v3_cfg_t MX6NAME(uart2_pads)[] = {
+ MX6PAD(EIM_D26__UART2_TXD) | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6PAD(EIM_D27__UART2_RXD) | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+struct i2c_pads_info MX6NAME(i2c_pad_info)[] = {
+ {
+ /* I2C1, SGTL5000 */
+ .scl = {
+ .i2c_mode = MX6PAD(EIM_D21__I2C1_SCL) | PC,
+ .gpio_mode = MX6PAD(EIM_D21__GPIO_3_21) | PC,
+ .gp = IMX_GPIO_NR(3, 21)
+ },
+ .sda = {
+ .i2c_mode = MX6PAD(EIM_D28__I2C1_SDA) | PC,
+ .gpio_mode = MX6PAD(EIM_D28__GPIO_3_28) | PC,
+ .gp = IMX_GPIO_NR(3, 28)
+ }
+ }, {
+ /* I2C2 Camera, MIPI */
+ .scl = {
+ .i2c_mode = MX6PAD(KEY_COL3__I2C2_SCL) | PC,
+ .gpio_mode = MX6PAD(KEY_COL3__GPIO_4_12) | PC,
+ .gp = IMX_GPIO_NR(4, 12)
+ },
+ .sda = {
+ .i2c_mode = MX6PAD(KEY_ROW3__I2C2_SDA) | PC,
+ .gpio_mode = MX6PAD(KEY_ROW3__GPIO_4_13) | PC,
+ .gp = IMX_GPIO_NR(4, 13)
+ }
+ }, {
+ /* I2C3, J15 - RGB connector */
+ .scl = {
+ .i2c_mode = MX6PAD(GPIO_5__I2C3_SCL) | PC,
+ .gpio_mode = MX6PAD(GPIO_5__GPIO_1_5) | PC,
+ .gp = IMX_GPIO_NR(1, 5)
+ },
+ .sda = {
+ .i2c_mode = MX6PAD(GPIO_16__I2C3_SDA) | PC,
+ .gpio_mode = MX6PAD(GPIO_16__GPIO_7_11) | PC,
+ .gp = IMX_GPIO_NR(7, 11)
+ }
+ }
+};
+
+iomux_v3_cfg_t MX6NAME(usdhc3_pads)[] = {
+ MX6PAD(SD3_CLK__USDHC3_CLK) | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6PAD(SD3_CMD__USDHC3_CMD) | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6PAD(SD3_DAT0__USDHC3_DAT0) | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6PAD(SD3_DAT1__USDHC3_DAT1) | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6PAD(SD3_DAT2__USDHC3_DAT2) | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6PAD(SD3_DAT3__USDHC3_DAT3) | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6PAD(SD3_DAT5__GPIO_7_0) | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+iomux_v3_cfg_t MX6NAME(usdhc4_pads)[] = {
+ MX6PAD(SD4_CLK__USDHC4_CLK) | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6PAD(SD4_CMD__USDHC4_CMD) | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6PAD(SD4_DAT0__USDHC4_DAT0) | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6PAD(SD4_DAT1__USDHC4_DAT1) | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6PAD(SD4_DAT2__USDHC4_DAT2) | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6PAD(SD4_DAT3__USDHC4_DAT3) | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6PAD(NANDF_D6__GPIO_2_6) | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+iomux_v3_cfg_t MX6NAME(enet_pads1)[] = {
+ MX6PAD(ENET_MDIO__ENET_MDIO) | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6PAD(ENET_MDC__ENET_MDC) | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6PAD(RGMII_TXC__ENET_RGMII_TXC) | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6PAD(RGMII_TD0__ENET_RGMII_TD0) | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6PAD(RGMII_TD1__ENET_RGMII_TD1) | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6PAD(RGMII_TD2__ENET_RGMII_TD2) | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6PAD(RGMII_TD3__ENET_RGMII_TD3) | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6PAD(RGMII_TX_CTL__RGMII_TX_CTL) | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6PAD(ENET_REF_CLK__ENET_TX_CLK) | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ /* pin 35 - 1 (PHY_AD2) on reset */
+ MX6PAD(RGMII_RXC__GPIO_6_30) | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 32 - 1 - (MODE0) all */
+ MX6PAD(RGMII_RD0__GPIO_6_25) | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 31 - 1 - (MODE1) all */
+ MX6PAD(RGMII_RD1__GPIO_6_27) | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 28 - 1 - (MODE2) all */
+ MX6PAD(RGMII_RD2__GPIO_6_28) | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 27 - 1 - (MODE3) all */
+ MX6PAD(RGMII_RD3__GPIO_6_29) | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
+ MX6PAD(RGMII_RX_CTL__GPIO_6_24) | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 42 PHY nRST */
+ MX6PAD(EIM_D23__GPIO_3_23) | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+iomux_v3_cfg_t MX6NAME(enet_pads2)[] = {
+ MX6PAD(RGMII_RXC__ENET_RGMII_RXC) | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6PAD(RGMII_RD0__ENET_RGMII_RD0) | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6PAD(RGMII_RD1__ENET_RGMII_RD1) | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6PAD(RGMII_RD2__ENET_RGMII_RD2) | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6PAD(RGMII_RD3__ENET_RGMII_RD3) | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6PAD(RGMII_RX_CTL__RGMII_RX_CTL) | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+/* Button assignments for J14 */
+static iomux_v3_cfg_t MX6NAME(button_pads)[] = {
+ /* Menu */
+ MX6PAD(NANDF_D1__GPIO_2_1) | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+ /* Back */
+ MX6PAD(NANDF_D2__GPIO_2_2) | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+ /* Labelled Search (mapped to Power under Android) */
+ MX6PAD(NANDF_D3__GPIO_2_3) | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+ /* Home */
+ MX6PAD(NANDF_D4__GPIO_2_4) | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+ /* Volume Down */
+ MX6PAD(GPIO_19__GPIO_4_5) | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+ /* Volume Up */
+ MX6PAD(GPIO_18__GPIO_7_13) | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+};
+
+iomux_v3_cfg_t MX6NAME(usb_pads)[] = {
+ MX6PAD(GPIO_17__GPIO_7_12) | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+#ifdef CONFIG_MXC_SPI
+iomux_v3_cfg_t MX6NAME(ecspi1_pads)[] = {
+ /* SS1 */
+ MX6PAD(EIM_D19__GPIO_3_19) | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6PAD(EIM_D17__ECSPI1_MISO) | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6PAD(EIM_D18__ECSPI1_MOSI) | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6PAD(EIM_D16__ECSPI1_SCLK) | MUX_PAD_CTRL(SPI_PAD_CTRL),
+};
+#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 28/32] mx6q_4x_mt41j128.cfg: add mx6 solo/duallite support
2012-10-04 1:47 ` [U-Boot] [PATCH V3 00/32] " Troy Kisky
` (26 preceding siblings ...)
2012-10-04 1:47 ` [U-Boot] [PATCH V3 27/32] mx6qsabrelite: add support for mx6 solo/duallite Troy Kisky
@ 2012-10-04 1:47 ` Troy Kisky
2012-10-08 18:46 ` Eric Nelson
2012-10-04 1:47 ` [U-Boot] [PATCH V3 29/32] Add boards for sabrelite variants mx6s(solo) and mx6dl(duallite) Troy Kisky
` (6 subsequent siblings)
34 siblings, 1 reply; 430+ messages in thread
From: Troy Kisky @ 2012-10-04 1:47 UTC (permalink / raw)
To: u-boot
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 120 +++++++++++++++++++-------
1 file changed, 87 insertions(+), 33 deletions(-)
diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
index 9e20db0..f45f93e 100644
--- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
@@ -49,6 +49,15 @@ BOOT_FROM sd
* Address absolute address of the register
* value value to be stored in the register
*/
+/*
+ * DDR3 settings
+ * MX6Q ddr is limited to 1066 Mhz, currently 1056 MHz(528 MHz clock),
+ * memory bus width: 64 bits, x16/x32/x64
+ * MX6DL ddr is limited to 800 MHz(400 MHz clock)
+ * memory bus width: 64 bits, x16/x32/x64
+ * MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
+ * memory bus width: 32 bits, x16/x32
+ */
WRITE_ENTRY1(IOM_DRAM_SDQS0, 0x00000030)
WRITE_ENTRY1(IOM_DRAM_SDQS1, 0x00000030)
WRITE_ENTRY1(IOM_DRAM_SDQS2, 0x00000030)
@@ -90,6 +99,7 @@ WRITE_ENTRY1(IOM_GRP_B6DS, 0x00000030)
WRITE_ENTRY1(IOM_GRP_B7DS, 0x00000030)
WRITE_ENTRY1(IOM_GRP_ADDDS, 0x00000030)
+
/* (differential input) */
WRITE_ENTRY1(IOM_DDRMODE_CTL, 0x00020000)
/* disable ddr pullups */
@@ -119,48 +129,92 @@ WRITE_ENTRY1(MMDC_P0_MDMISC, 0x00081740)
* MDSCR, con_req
*/
WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00008000)
+
/*
- * MDCFG0, tRFC=0x56 clocks, tXS=0x5b clocks
- * tXP=4 clocks, tXPDLL=13 clocks
- * tFAW=24 clocks, cas=8 cycles
+ * MDCFG0,
+ * MX6Q:
+ * tRFC=0x56 clocks, tXS=0x5b clocks, tXP=4 clocks, tXPDLL=13 clocks
+ * tFAW=24 clocks, cas=8 cycles
+ * MX6DL/SOLO:
+ * tRFC=0x6a clocks, tXS=0x6e clocks, tXP=3 clocks, tXPDLL=10 clocks
+ * tFAW=19 clocks, cas=6 cycles
*/
-WRITE_ENTRY1(MMDC_P0_MDCFG0, 0x555A7975)
+WRITE_ENTRY2(MMDC_P0_MDCFG0, 0x555A7975, 0x696D5323)
+
/*
- * MDCFG1, tRDC=8, tRP=8, tRC=27,tRAS=20,tRPA=tRP+1,tWR=8
- * tMRD=4, tCWL=6
+ * MDCFG1,
+ * MX6Q:
+ * tRDC=8, tRP=8, tRC=27, tRAS=20, tRPA=tRP+1, tWR=8, tMRD=4, tCWL=6
+ * MX6DL/SOLO:
+ * tRDC=6, tRP=6, tRC=20, tRAS=15, tRPA=tRP+1, tWR=7, tMRD=4, tCWL=5
*/
-WRITE_ENTRY1(MMDC_P0_MDCFG1, 0xFF538E64)
+WRITE_ENTRY2(MMDC_P0_MDCFG1, 0xFF538E64, 0xB66E8C63)
+
/*
* MDCFG2,tDLLK=512,tRTP=4,tWTR=4,tRRD=4
*/
WRITE_ENTRY1(MMDC_P0_MDCFG2, 0x01FF00DB)
WRITE_ENTRY1(MMDC_P0_MDRWD, 0x000026D2)
-
WRITE_ENTRY1(MMDC_P0_MDOR, 0x005B0E21)
-WRITE_ENTRY1(MMDC_P0_MDOTC, 0x09444040)
-WRITE_ENTRY1(MMDC_P0_MDPDC, 0x00025576)
/*
- * Mx6Q - 64 bit wide ddr
+ * MMDC_MDOTC,
+ * MX6Q:
+ * tAOFPD=2 cycles, tAONPD=2, tANPD=5, tAXPD=5, tODTLon=5, tODT_idle_off=5
+ * MX6DL/SOLO:
+ * tAOFPD=1 cycles, tAONPD=1, tANPD=4, tAXPD=4, tODTLon=4, tODT_idle_off=4
+ */
+WRITE_ENTRY2(MMDC_P0_MDOTC, 0x09444040, 0x00333030)
+
+/*
+ * MDPDC - [17:16](2) => CKE pulse width = 3 cycles.
+ * [15:12](5) => PWDT_1 = 256 cycles
+ * [11:8](5) =>PWDR_0 = 256 cycles
+ * MX6Q: [2:0](6) => CKSRE = 6 cycles, [5:3](6) => CKSRX = 6 cycles
+ * MX6DL/SOLO: [2:0](5) => CKSRE = 5 cycles, [5:3](5) => CKSRX = 5 cycles
+ */
+WRITE_ENTRY2(MMDC_P0_MDPDC, 0x00025576, 0x0002556D)
+
+/*
+ * MX6Q/DL - 64 bit wide ddr
* last address is (1<<28 (base) + 1<<30 - 1) / (1<<25) =
* 1<<3 + 1<<5 - 1 = 8 + 0x20 -1 = 0x27
*/
+/*
+ * MX6SOLO - 32 bit wide ddr
+ * last address is (1<<28 (base) + 1<<29 - 1) / (1<<25) =
+ * 1<<3 + 1<<4 - 1 = 8 + 0x10 -1 = 0x17
+ */
/* MDASP, CS0_END */
-WRITE_ENTRY1(MMDC_P0_MDASP, 0x00000027)
+WRITE_ENTRY3(MMDC_P0_MDASP, 0x00000027, 0x00000027, 0x00000017)
/*
- * MDCTL, CS0 enable, CS1 disabled, row=14, col=10, burst=8, width=64/32bit
- * mx6q : row+col+bank+width=14+10+3+3=30 = 1G
+ * MDCTL, CS0 enable, CS1 disabled, row=14, col=10, burst=8
+ * MX6Q/DL: width=64bit row+col+bank+width=14+10+3+3=30 = 1G
+ * MX6SOLO: width=32bit row+col+bank+width=14+10+3+2=29 = 512M
*/
-WRITE_ENTRY1(MMDC_P0_MDCTL, 0x831A0000)
+WRITE_ENTRY3(MMDC_P0_MDCTL, 0x831A0000, 0x831A0000, 0x83190000)
-/* MDSCR, con_req, LOAD MR2, CS0, A3,A10 set (CAS Write=6), RZQ/2 */
-WRITE_ENTRY1(MMDC_P0_MDSCR, 0x04088032)
+/*
+ * LOAD MR2: MDSCR, con_req, CS0, A10 set - RZQ/2
+ * MX6Q: A3 set(CAS Write=6)
+ * MX6DL/SOLO: (CAS Write=5)
+ */
+WRITE_ENTRY2(MMDC_P0_MDSCR, 0x04088032, 0x04008032)
/* LOAD MR3, CS0 */
WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00008033)
-/* LOAD MR1, CS0, A1,A6 set Rtt=RZQ/2, ODI=RZQ/7 */
-WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00428031)
-/* LOAD MR0, CS0, A6,A8,A11 set CAS=8, WR=8, DLL reset */
-WRITE_ENTRY1(MMDC_P0_MDSCR, 0x09408030)
+
+/*
+ * LOAD MR1, CS0
+ * MX6Q: A6 set: Rtt=RZQ/2, A1 set: ODI=RZQ/7
+ * MX6DL/SOLO: A2 set: Rtt=RZQ/4, ODI=RZQ/6
+ */
+WRITE_ENTRY2(MMDC_P0_MDSCR, 0x00428031, 0x00048031)
+
+/* LOAD MR0, CS0 A8 set: DLL Reset
+ * MX6Q: A6 set: CAS=8 A11 set: WR=8
+ * MX6DL/SOLO: A4 set: CAS=5, A9,A10 set: WR=7
+ */
+WRITE_ENTRY2(MMDC_P0_MDSCR, 0x09408030, 0x07208030)
/* ZQ calibrate, CS0 */
WRITE_ENTRY1(MMDC_P0_MDSCR, 0x04008040)
@@ -173,18 +227,18 @@ WRITE_ENTRY1(MMDC_P0_MPODTCTRL, 0x00022227)
WRITE_ENTRY1(MMDC_P1_MPODTCTRL, 0x00022227)
/* MPDGCTRL0/1 DQS GATE*/
-WRITE_ENTRY1(MMDC_P0_MPDGCTRL0, 0x434B0350)
-WRITE_ENTRY1(MMDC_P0_MPDGCTRL1, 0x034C0359)
-WRITE_ENTRY1(MMDC_P1_MPDGCTRL0, 0x434B0350)
-WRITE_ENTRY1(MMDC_P1_MPDGCTRL1, 0x03650348)
-WRITE_ENTRY1(MMDC_P0_MPRDDLCTL, 0x4436383B)
-WRITE_ENTRY1(MMDC_P1_MPRDDLCTL, 0x39393341)
-WRITE_ENTRY1(MMDC_P0_MPWRDLCTL, 0x35373933)
-WRITE_ENTRY1(MMDC_P1_MPWRDLCTL, 0x48254A36)
-WRITE_ENTRY1(MMDC_P0_MPWLDECTRL0, 0x001F001F)
-WRITE_ENTRY1(MMDC_P0_MPWLDECTRL1, 0x001F001F)
-WRITE_ENTRY1(MMDC_P1_MPWLDECTRL0, 0x00440044)
-WRITE_ENTRY1(MMDC_P1_MPWLDECTRL1, 0x00440044)
+WRITE_ENTRY2(MMDC_P0_MPDGCTRL0, 0x434B0350, 0x42350231)
+WRITE_ENTRY2(MMDC_P0_MPDGCTRL1, 0x034C0359, 0x021A0218)
+WRITE_ENTRY2(MMDC_P1_MPDGCTRL0, 0x434B0350, 0x42350231)
+WRITE_ENTRY2(MMDC_P1_MPDGCTRL1, 0x03650348, 0x021A0218)
+WRITE_ENTRY2(MMDC_P0_MPRDDLCTL, 0x4436383B, 0x4B4B4E49)
+WRITE_ENTRY2(MMDC_P1_MPRDDLCTL, 0x39393341, 0x4B4B4E49)
+WRITE_ENTRY2(MMDC_P0_MPWRDLCTL, 0x35373933, 0x3F3F3035)
+WRITE_ENTRY2(MMDC_P1_MPWRDLCTL, 0x48254A36, 0x3F3F3035)
+WRITE_ENTRY2(MMDC_P0_MPWLDECTRL0, 0x001F001F, 0x0040003C)
+WRITE_ENTRY2(MMDC_P0_MPWLDECTRL1, 0x001F001F, 0x0032003E)
+WRITE_ENTRY2(MMDC_P1_MPWLDECTRL0, 0x00440044, 0x0040003C)
+WRITE_ENTRY2(MMDC_P1_MPWLDECTRL1, 0x00440044, 0x0032003E)
/* MPMUR0 - Complete calibration by forced measurement */
WRITE_ENTRY1(MMDC_P0_MPMUR0, 0x00000800)
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 29/32] Add boards for sabrelite variants mx6s(solo) and mx6dl(duallite)
2012-10-04 1:47 ` [U-Boot] [PATCH V3 00/32] " Troy Kisky
` (27 preceding siblings ...)
2012-10-04 1:47 ` [U-Boot] [PATCH V3 28/32] mx6q_4x_mt41j128.cfg: add mx6 solo/duallite support Troy Kisky
@ 2012-10-04 1:47 ` Troy Kisky
2012-10-04 1:47 ` [U-Boot] [PATCH V3 30/32] mx6qsabrelite: change CONFIG_SYS_PROMPT Troy Kisky
` (5 subsequent siblings)
34 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-10-04 1:47 UTC (permalink / raw)
To: u-boot
mx6dlsabrelite - for duallite
mx6ssabrelite - for solo
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
boards.cfg | 4 +++-
include/configs/mx6qsabrelite.h | 1 -
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/boards.cfg b/boards.cfg
index e9e073e..abc95d4 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -232,7 +232,9 @@ ima3-mx53 arm armv7 ima3-mx53 esg
vision2 arm armv7 vision2 ttcontrol mx5 vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg
mx6qarm2 arm armv7 mx6qarm2 freescale mx6 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg
mx6qsabreauto arm armv7 mx6qsabreauto freescale mx6 mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg
-mx6qsabrelite arm armv7 mx6qsabrelite freescale mx6 mx6qsabrelite:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+mx6dlsabrelite arm armv7 mx6qsabrelite freescale mx6 mx6qsabrelite:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6DL
+mx6qsabrelite arm armv7 mx6qsabrelite freescale mx6 mx6qsabrelite:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q
+mx6ssabrelite arm armv7 mx6qsabrelite freescale mx6 mx6qsabrelite:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6S
mx6qsabresd arm armv7 mx6qsabresd freescale mx6 mx6qsabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
cm_t35 arm armv7 cm_t35 - omap3
omap3_overo arm armv7 overo - omap3
diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
index 6a10232..8890e4c 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -23,7 +23,6 @@
#define __CONFIG_H
#define CONFIG_MX6
-#define CONFIG_MX6Q
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 30/32] mx6qsabrelite: change CONFIG_SYS_PROMPT
2012-10-04 1:47 ` [U-Boot] [PATCH V3 00/32] " Troy Kisky
` (28 preceding siblings ...)
2012-10-04 1:47 ` [U-Boot] [PATCH V3 29/32] Add boards for sabrelite variants mx6s(solo) and mx6dl(duallite) Troy Kisky
@ 2012-10-04 1:47 ` Troy Kisky
2012-10-04 3:00 ` Otavio Salvador
2012-10-04 1:47 ` [U-Boot] [PATCH V3 31/32] parse_helper: add expression evaluation Troy Kisky
` (4 subsequent siblings)
34 siblings, 1 reply; 430+ messages in thread
From: Troy Kisky @ 2012-10-04 1:47 UTC (permalink / raw)
To: u-boot
The prompt is not appropriate if not running on
a mx6q processor.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
include/configs/mx6qsabrelite.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
index 8890e4c..8fd35a6 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -180,7 +180,7 @@
/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT "MX6QSABRELITE U-Boot > "
+#define CONFIG_SYS_PROMPT "U-Boot > "
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE 256
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 31/32] parse_helper: add expression evaluation
2012-10-04 1:47 ` [U-Boot] [PATCH V3 00/32] " Troy Kisky
` (29 preceding siblings ...)
2012-10-04 1:47 ` [U-Boot] [PATCH V3 30/32] mx6qsabrelite: change CONFIG_SYS_PROMPT Troy Kisky
@ 2012-10-04 1:47 ` Troy Kisky
2012-10-04 1:47 ` [U-Boot] [PATCH V3 32/32] imx-mkimage.h: use base + offset syntax Troy Kisky
` (3 subsequent siblings)
34 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-10-04 1:47 UTC (permalink / raw)
To: u-boot
Basic expressions with order precedence is
now supported.
ie. (----3 + ((1+2*3)/--2 + --5 *(8/4))) is 16.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
tools/parse_helper.c | 172 +++++++++++++++++++++++++++++++++++++++++++++++---
1 file changed, 162 insertions(+), 10 deletions(-)
diff --git a/tools/parse_helper.c b/tools/parse_helper.c
index 0a5c5f6..50be832 100644
--- a/tools/parse_helper.c
+++ b/tools/parse_helper.c
@@ -97,20 +97,172 @@ int ph_skip_comma(struct parse_helper *ph)
}
}
+static const char precedence[] = {
+ /* ( + - * / & ^ | ) */
+ 0, 2, 2, 1, 1, 3, 4, 5, 6
+};
+static const char unary_operations[] = "(+-";
+static const char binary_operations[] = " +-*/&^|)";
+
+static uint32_t do_func(uint32_t val1, uint32_t val2, int op)
+{
+ switch (op) {
+ case 1:
+ return val1 + val2;
+ case 2:
+ return val1 - val2;
+ case 3:
+ return val1 * val2;
+ case 4:
+ return val1 / val2;
+ case 5:
+ return val1 & val2;
+ case 6:
+ return val1 ^ val2;
+ case 7:
+ return val1 | val2;
+ }
+ fprintf(stderr, "Error: in func %s: val1=%d val2=%d op = %d\n",
+ __func__, val1, val2, op);
+ exit(EXIT_FAILURE);
+}
+
+static int find_op(char c, const char *p)
+{
+ int i;
+ for (i = 0; ; i++) {
+ if (c == p[i])
+ return i;
+ if (!p[i])
+ break;
+ }
+ return -1;
+}
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
int ph_get_value(struct parse_helper *ph, uint32_t *pval)
{
char *endptr;
- uint32_t value;
+ int op_i = 0;
+ int val_i = 0;
+ unsigned char op[16];
+ uint32_t val[16];
+ int unary = 1;
+ char *p;
- if (ph_skip_separators(ph))
- return -1;
- errno = 0;
- value = strtoul(ph->p, &endptr, 16);
- if (errno || (ph->p == endptr))
- return -1;
- *pval = value;
- ph->p = endptr;
- return 0;
+ p = ph->p;
+ for (;;) {
+ char c;
+ int i, j;
+ const char *ops = unary ? unary_operations : binary_operations;
+
+ if (unary) {
+ ph->p = p;
+ if (ph_skip_separators(ph))
+ return -1;
+ p = ph->p;
+ c = *p;
+ } else {
+ for (;;) {
+ c = *p;
+ if ((c != ' ') && (c != '\t'))
+ break;
+ p++;
+ }
+ }
+ i = find_op(c, ops);
+ debug("%d,%c,%d:%s\n", i, c, unary, p);
+ if ((i < 0) && unary) {
+ if (val_i >= ARRAY_SIZE(val))
+ return -1;
+ errno = 0;
+ val[val_i++] = strtoul(p, &endptr, 16);
+ if (errno || (p == endptr)) {
+ ph->p = p;
+ return -1;
+ }
+ p = endptr;
+ unary = 0;
+ debug("val[%d]=%x,%d,%d\n", val_i - 1, val[val_i - 1],
+ op_i, val_i);
+do_unary:
+ while (op_i) {
+ j = op[op_i - 1];
+ if (!(j & 0x80))
+ break;
+ op_i--;
+ val[val_i - 1] = do_func(0,
+ val[val_i - 1], j & 0x7f);
+ debug("un:%d,%x,%d,%d\n", val[val_i - 1], j,
+ op_i, val_i);
+ }
+ continue;
+ }
+ if (i < 0) {
+ c = 0;
+ i = 8;
+ } else {
+ p++;
+ }
+ if (c == '(') {
+ if (op_i >= ARRAY_SIZE(op))
+ return -1;
+ op[op_i++] = i;
+ debug("op[%d]=%x,%d,%d\n", op_i - 1, op[op_i - 1],
+ op_i, val_i);
+ unary = 1;
+ continue;
+ }
+ for (;;) {
+ if (!op_i || unary)
+ break;
+ j = op[op_i - 1];
+ if (j == 0) {
+ if (c == ')') {
+ op_i--;
+ goto do_unary;
+ }
+ break;
+ }
+ if ((j & 0x80)) {
+ op_i--;
+ val[val_i - 1] = do_func(0,
+ val[val_i - 1], j & 0x7f);
+ debug("unary:%d,%x\n", val[val_i - 1], j);
+ continue;
+ }
+ if (precedence[i] < precedence[j])
+ break;
+ if (val_i < 2)
+ return -1;
+ op_i--;
+ val[val_i - 2] = do_func(val[val_i - 2],
+ val[val_i - 1], j);
+ val_i--;
+ debug("binary:%d,%x,%d,%d\n", val[val_i - 1], j,
+ op_i, val_i);
+ }
+ if (c == ')') {
+ fprintf(stderr, "Error: unmatched parenthesis\n");
+ return -1;
+ }
+ if (i == 8) {
+ if ((op_i != 0) || (val_i != 1)) {
+ fprintf(stderr, "Error: syntax %d %d\n",
+ op_i, val_i);
+ return -1;
+ }
+ ph->p = p;
+ *pval = val[0];
+ return 0;
+ }
+ if (op_i >= ARRAY_SIZE(op))
+ return -1;
+ op[op_i++] = i | (unary << 7);
+ debug("op[%d]=%x,%d,%d\n", op_i - 1, op[op_i - 1], op_i, val_i);
+ unary = 1;
+ }
}
/*
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 32/32] imx-mkimage.h: use base + offset syntax
2012-10-04 1:47 ` [U-Boot] [PATCH V3 00/32] " Troy Kisky
` (30 preceding siblings ...)
2012-10-04 1:47 ` [U-Boot] [PATCH V3 31/32] parse_helper: add expression evaluation Troy Kisky
@ 2012-10-04 1:47 ` Troy Kisky
2012-10-04 10:18 ` [U-Boot] [PATCH V3 00/32] Add mx6solo/mx6duallite support Albert ARIBAUD
` (2 subsequent siblings)
34 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-10-04 1:47 UTC (permalink / raw)
To: u-boot
Now that expression work, we can delete
the redundant MMC_P1_xxx defines and
just define MMC_P0 and MMC_P1 bases.
The other addresses are changed to a base
+ offset syntax as well.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
arch/arm/include/asm/arch-mx6/imx-mkimage.h | 205 ++++++++++++--------------
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 90 +++++------
2 files changed, 136 insertions(+), 159 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx6/imx-mkimage.h b/arch/arm/include/asm/arch-mx6/imx-mkimage.h
index 4abd3f1..dc9dadf 100644
--- a/arch/arm/include/asm/arch-mx6/imx-mkimage.h
+++ b/arch/arm/include/asm/arch-mx6/imx-mkimage.h
@@ -6,124 +6,101 @@
#ifndef __ASM_ARCH_IMX_MKIMAGE_H__
#define __ASM_ARCH_IMX_MKIMAGE_H__
-#define IOMUXC_GPR4 0x020e0010
-#define IOMUXC_GPR6 0x020e0018
-#define IOMUXC_GPR7 0x020e001c
-
-/* mx6 duallite and solo have same offsets */
+#define IRAM_FREE_START 0x00907000
+#define MMDC_P0 0x021b0000
+#define MMDC_P1 0x021b4000
+#define IOMUXC_BASE 0x020e0000
+#define CCM_BASE 0x020c4000
-#define IOM_DRAM_DQM0 MA(0x020e05ac, 0x020e0470, 0x0)
-#define IOM_DRAM_DQM1 MA(0x020e05b4, 0x020e0474, 0x0)
-#define IOM_DRAM_DQM2 MA(0x020e0528, 0x020e0478, 0x0)
-#define IOM_DRAM_DQM3 MA(0x020e0520, 0x020e047c, 0x0)
-#define IOM_DRAM_DQM4 MA(0x020e0514, 0x020e0480, 0x0)
-#define IOM_DRAM_DQM5 MA(0x020e0510, 0x020e0484, 0x0)
-#define IOM_DRAM_DQM6 MA(0x020e05bc, 0x020e0488, 0x0)
-#define IOM_DRAM_DQM7 MA(0x020e05c4, 0x020e048c, 0x0)
-
-#define IOM_DRAM_CAS MA(0x020e056c, 0x020e0464, 0x0)
-#define IOM_DRAM_RAS MA(0x020e0578, 0x020e0490, 0x0)
-#define IOM_DRAM_RESET MA(0x020e057c, 0x020e0494, 0x0)
-#define IOM_DRAM_SDCLK_0 MA(0x020e0588, 0x020e04ac, 0x0)
-#define IOM_DRAM_SDCLK_1 MA(0x020e0594, 0x020e04b0, 0x0)
-#define IOM_DRAM_SDBA2 MA(0x020e058c, 0x020e04a0, 0x0)
-#define IOM_DRAM_SDCKE0 MA(0x020e0590, 0x020e04a4, 0x0)
-#define IOM_DRAM_SDCKE1 MA(0x020e0598, 0x020e04a8, 0x0)
-#define IOM_DRAM_SDODT0 MA(0x020e059c, 0x020e04b4, 0x0)
-#define IOM_DRAM_SDODT1 MA(0x020e05a0, 0x020e04b8, 0x0)
-
-#define IOM_DRAM_SDQS0 MA(0x020e05a8, 0x020e04bc, 0x0)
-#define IOM_DRAM_SDQS1 MA(0x020e05b0, 0x020e04c0, 0x0)
-#define IOM_DRAM_SDQS2 MA(0x020e0524, 0x020e04c4, 0x0)
-#define IOM_DRAM_SDQS3 MA(0x020e051c, 0x020e04c8, 0x0)
-#define IOM_DRAM_SDQS4 MA(0x020e0518, 0x020e04cc, 0x0)
-#define IOM_DRAM_SDQS5 MA(0x020e050c, 0x020e04d0, 0x0)
-#define IOM_DRAM_SDQS6 MA(0x020e05b8, 0x020e04d4, 0x0)
-#define IOM_DRAM_SDQS7 MA(0x020e05c0, 0x020e04d8, 0x0)
-
-#define IOM_GRP_B0DS MA(0x020e0784, 0x020e0764, 0x0)
-#define IOM_GRP_B1DS MA(0x020e0788, 0x020e0770, 0x0)
-#define IOM_GRP_B2DS MA(0x020e0794, 0x020e0778, 0x0)
-#define IOM_GRP_B3DS MA(0x020e079c, 0x020e077c, 0x0)
-#define IOM_GRP_B4DS MA(0x020e07a0, 0x020e0780, 0x0)
-#define IOM_GRP_B5DS MA(0x020e07a4, 0x020e0784, 0x0)
-#define IOM_GRP_B6DS MA(0x020e07a8, 0x020e078c, 0x0)
-#define IOM_GRP_B7DS MA(0x020e0748, 0x020e0748, 0x0)
-#define IOM_GRP_ADDDS MA(0x020e074c, 0x020e074c, 0x0)
-#define IOM_DDRMODE_CTL MA(0x020e0750, 0x020e0750, 0x0)
-#define IOM_GRP_DDRPKE MA(0x020e0758, 0x020e0754, 0x0)
-#define IOM_GRP_DDRMODE MA(0x020e0774, 0x020e0760, 0x0)
-#define IOM_GRP_CTLDS MA(0x020e078c, 0x020e076c, 0x0)
-#define IOM_GRP_DDR_TYPE MA(0x020e0798, 0x020e0774, 0x0)
+#define IOMUXC_GPR4 (IOMUXC_BASE + 0x010)
+#define IOMUXC_GPR6 (IOMUXC_BASE + 0x018)
+#define IOMUXC_GPR7 (IOMUXC_BASE + 0x01c)
-#define IRAM_FREE_START 0x00907000
+/* mx6 duallite and solo have same offsets */
-#define MMDC_P0_MDCTL 0x021b0000
-#define MMDC_P0_MDPDC 0x021b0004
-#define MMDC_P0_MDOTC 0x021b0008
-#define MMDC_P0_MDCFG0 0x021b000c
-#define MMDC_P0_MDCFG1 0x021b0010
-#define MMDC_P0_MDCFG2 0x021b0014
-#define MMDC_P0_MDMISC 0x021b0018
-#define MMDC_P0_MDSCR 0x021b001c
-#define MMDC_P0_MDREF 0x021b0020
-#define MMDC_P0_MDRWD 0x021b002c
-#define MMDC_P0_MDOR 0x021b0030
-#define MMDC_P0_MDASP 0x021b0040
-#define MMDC_P0_MAPSR 0x021b0404
-#define MMDC_P0_MPZQHWCTRL 0x021b0800
-#define MMDC_P0_MPWLDECTRL0 0x021b080c
-#define MMDC_P0_MPWLDECTRL1 0x021b0810
-#define MMDC_P0_MPODTCTRL 0x021b0818
-#define MMDC_P0_MPRDDQBY0DL 0x021b081c
-#define MMDC_P0_MPRDDQBY1DL 0x021b0820
-#define MMDC_P0_MPRDDQBY2DL 0x021b0824
-#define MMDC_P0_MPRDDQBY3DL 0x021b0828
-#define MMDC_P0_MPDGCTRL0 0x021b083c
-#define MMDC_P0_MPDGCTRL1 0x021b0840
-#define MMDC_P0_MPRDDLCTL 0x021b0848
-#define MMDC_P0_MPWRDLCTL 0x021b0850
-#define MMDC_P0_MPMUR0 0x021b08b8
-
-#define MMDC_P1_MDCTL 0x021b4000
-#define MMDC_P1_MDPDC 0x021b4004
-#define MMDC_P1_MDOTC 0x021b4008
-#define MMDC_P1_MDCFG0 0x021b400c
-#define MMDC_P1_MDCFG1 0x021b4010
-#define MMDC_P1_MDCFG2 0x021b4014
-#define MMDC_P1_MDMISC 0x021b4018
-#define MMDC_P1_MDSCR 0x021b401c
-#define MMDC_P1_MDREF 0x021b4020
-#define MMDC_P1_MDRWD 0x021b402c
-#define MMDC_P1_MDOR 0x021b4030
-#define MMDC_P1_MDASP 0x021b4040
-#define MMDC_P1_MAPSR 0x021b4404
-#define MMDC_P1_MPZQHWCTRL 0x021b4800
-#define MMDC_P1_MPWLDECTRL0 0x021b480c
-#define MMDC_P1_MPWLDECTRL1 0x021b4810
-#define MMDC_P1_MPODTCTRL 0x021b4818
-#define MMDC_P1_MPRDDQBY0DL 0x021b481c
-#define MMDC_P1_MPRDDQBY1DL 0x021b4820
-#define MMDC_P1_MPRDDQBY2DL 0x021b4824
-#define MMDC_P1_MPRDDQBY3DL 0x021b4828
-#define MMDC_P1_MPDGCTRL0 0x021b483c
-#define MMDC_P1_MPDGCTRL1 0x021b4840
-#define MMDC_P1_MPRDDLCTL 0x021b4848
-#define MMDC_P1_MPWRDLCTL 0x021b4850
-#define MMDC_P1_MPMUR0 0x021b48b8
-
-#define CCM_CCGR0 0x020C4068
-#define CCM_CCGR1 0x020C406c
-#define CCM_CCGR2 0x020C4070
-#define CCM_CCGR3 0x020C4074
-#define CCM_CCGR4 0x020C4078
-#define CCM_CCGR5 0x020C407c
-#define CCM_CCGR6 0x020C4080
+#define IOM_DRAM_DQM0 MA(0x5ac, 0x470, 0x0)
+#define IOM_DRAM_DQM1 MA(0x5b4, 0x474, 0x0)
+#define IOM_DRAM_DQM2 MA(0x528, 0x478, 0x0)
+#define IOM_DRAM_DQM3 MA(0x520, 0x47c, 0x0)
+#define IOM_DRAM_DQM4 MA(0x514, 0x480, 0x0)
+#define IOM_DRAM_DQM5 MA(0x510, 0x484, 0x0)
+#define IOM_DRAM_DQM6 MA(0x5bc, 0x488, 0x0)
+#define IOM_DRAM_DQM7 MA(0x5c4, 0x48c, 0x0)
+
+#define IOM_DRAM_CAS MA(0x56c, 0x464, 0x0)
+#define IOM_DRAM_RAS MA(0x578, 0x490, 0x0)
+#define IOM_DRAM_RESET MA(0x57c, 0x494, 0x0)
+#define IOM_DRAM_SDCLK_0 MA(0x588, 0x4ac, 0x0)
+#define IOM_DRAM_SDCLK_1 MA(0x594, 0x4b0, 0x0)
+#define IOM_DRAM_SDBA2 MA(0x58c, 0x4a0, 0x0)
+#define IOM_DRAM_SDCKE0 MA(0x590, 0x4a4, 0x0)
+#define IOM_DRAM_SDCKE1 MA(0x598, 0x4a8, 0x0)
+#define IOM_DRAM_SDODT0 MA(0x59c, 0x4b4, 0x0)
+#define IOM_DRAM_SDODT1 MA(0x5a0, 0x4b8, 0x0)
+
+#define IOM_DRAM_SDQS0 MA(0x5a8, 0x4bc, 0x0)
+#define IOM_DRAM_SDQS1 MA(0x5b0, 0x4c0, 0x0)
+#define IOM_DRAM_SDQS2 MA(0x524, 0x4c4, 0x0)
+#define IOM_DRAM_SDQS3 MA(0x51c, 0x4c8, 0x0)
+#define IOM_DRAM_SDQS4 MA(0x518, 0x4cc, 0x0)
+#define IOM_DRAM_SDQS5 MA(0x50c, 0x4d0, 0x0)
+#define IOM_DRAM_SDQS6 MA(0x5b8, 0x4d4, 0x0)
+#define IOM_DRAM_SDQS7 MA(0x5c0, 0x4d8, 0x0)
+
+#define IOM_GRP_B0DS MA(0x784, 0x764, 0x0)
+#define IOM_GRP_B1DS MA(0x788, 0x770, 0x0)
+#define IOM_GRP_B2DS MA(0x794, 0x778, 0x0)
+#define IOM_GRP_B3DS MA(0x79c, 0x77c, 0x0)
+#define IOM_GRP_B4DS MA(0x7a0, 0x780, 0x0)
+#define IOM_GRP_B5DS MA(0x7a4, 0x784, 0x0)
+#define IOM_GRP_B6DS MA(0x7a8, 0x78c, 0x0)
+#define IOM_GRP_B7DS MA(0x748, 0x748, 0x0)
+#define IOM_GRP_ADDDS MA(0x74c, 0x74c, 0x0)
+#define IOM_DDRMODE_CTL MA(0x750, 0x750, 0x0)
+#define IOM_GRP_DDRPKE MA(0x758, 0x754, 0x0)
+#define IOM_GRP_DDRMODE MA(0x774, 0x760, 0x0)
+#define IOM_GRP_CTLDS MA(0x78c, 0x76c, 0x0)
+#define IOM_GRP_DDR_TYPE MA(0x798, 0x774, 0x0)
+
+#define MMDC_MDCTL 0x000
+#define MMDC_MDPDC 0x004
+#define MMDC_MDOTC 0x008
+#define MMDC_MDCFG0 0x00c
+#define MMDC_MDCFG1 0x010
+#define MMDC_MDCFG2 0x014
+#define MMDC_MDMISC 0x018
+#define MMDC_MDSCR 0x01c
+#define MMDC_MDREF 0x020
+#define MMDC_MDRWD 0x02c
+#define MMDC_MDOR 0x030
+#define MMDC_MDASP 0x040
+#define MMDC_MAPSR 0x404
+#define MMDC_MPZQHWCTRL 0x800
+#define MMDC_MPWLDECTRL0 0x80c
+#define MMDC_MPWLDECTRL1 0x810
+#define MMDC_MPODTCTRL 0x818
+#define MMDC_MPRDDQBY0DL 0x81c
+#define MMDC_MPRDDQBY1DL 0x820
+#define MMDC_MPRDDQBY2DL 0x824
+#define MMDC_MPRDDQBY3DL 0x828
+#define MMDC_MPDGCTRL0 0x83c
+#define MMDC_MPDGCTRL1 0x840
+#define MMDC_MPRDDLCTL 0x848
+#define MMDC_MPWRDLCTL 0x850
+#define MMDC_MPMUR0 0x8b8
+
+#define CCM_CCGR0 (CCM_BASE + 0x068)
+#define CCM_CCGR1 (CCM_BASE + 0x06c)
+#define CCM_CCGR2 (CCM_BASE + 0x070)
+#define CCM_CCGR3 (CCM_BASE + 0x074)
+#define CCM_CCGR4 (CCM_BASE + 0x078)
+#define CCM_CCGR5 (CCM_BASE + 0x07c)
+#define CCM_CCGR6 (CCM_BASE + 0x080)
#define WRITE_ENTRY1(addr, q) DATA 4, addr, q
#ifdef CONFIG_MX6Q
-#define MA(mx6q, mx6dl_solo, mx6sololite) mx6q
+#define MA(mx6q, mx6dl_solo, mx6sololite) (IOMUXC_BASE + mx6q)
#define WRITE_ENTRY2(addr, q, dl) WRITE_ENTRY1(addr, q)
#define WRITE_ENTRY3(addr, q, dl, solo) WRITE_ENTRY1(addr, q)
#define WRITE_ENTRY4(addr, q, dl, solo, sl) WRITE_ENTRY1(addr, q)
@@ -131,20 +108,20 @@
#define WRITE_ENTRY2(addr, q, dl) WRITE_ENTRY1(addr, dl)
#ifdef CONFIG_MX6DL
-#define MA(mx6q, mx6dl_solo, mx6sololite) mx6dl_solo
+#define MA(mx6q, mx6dl_solo, mx6sololite) (IOMUXC_BASE + mx6dl_solo)
#define WRITE_ENTRY3(addr, q, dl, solo) WRITE_ENTRY1(addr, dl)
#define WRITE_ENTRY4(addr, q, dl, solo, sl) WRITE_ENTRY1(addr, dl)
#else
#define WRITE_ENTRY3(addr, q, dl, solo) WRITE_ENTRY1(addr, solo)
#ifdef CONFIG_MX6S
-#define MA(mx6q, mx6dl_solo, mx6sololite) mx6dl_solo
+#define MA(mx6q, mx6dl_solo, mx6sololite) (IOMUXC_BASE + mx6dl_solo)
#define WRITE_ENTRY4(addr, q, dl, solo, sl) WRITE_ENTRY1(addr, solo)
#else
#define WRITE_ENTRY4(addr, q, dl, solo, sl) WRITE_ENTRY1(addr, sl)
#ifdef CONFIG_MX6SL
-#define MA(mx6q, mx6dl_solo, mx6sololite) mx6sololite
+#define MA(mx6q, mx6dl_solo, mx6sololite) (IOMUXC_BASE + mx6sololite)
#else
#error "Please select cpu"
diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
index f45f93e..5de0f30 100644
--- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
@@ -111,24 +111,24 @@ WRITE_ENTRY1(IOM_GRP_CTLDS, 0x00000030)
WRITE_ENTRY1(IOM_GRP_DDR_TYPE, 0x000C0000)
/* Read data DQ Byte0-3 delay */
-WRITE_ENTRY1(MMDC_P0_MPRDDQBY0DL, 0x33333333)
-WRITE_ENTRY1(MMDC_P0_MPRDDQBY1DL, 0x33333333)
-WRITE_ENTRY1(MMDC_P0_MPRDDQBY2DL, 0x33333333)
-WRITE_ENTRY1(MMDC_P0_MPRDDQBY3DL, 0x33333333)
-WRITE_ENTRY1(MMDC_P1_MPRDDQBY0DL, 0x33333333)
-WRITE_ENTRY1(MMDC_P1_MPRDDQBY1DL, 0x33333333)
-WRITE_ENTRY1(MMDC_P1_MPRDDQBY2DL, 0x33333333)
-WRITE_ENTRY1(MMDC_P1_MPRDDQBY3DL, 0x33333333)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPRDDQBY0DL, 0x33333333)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPRDDQBY1DL, 0x33333333)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPRDDQBY2DL, 0x33333333)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPRDDQBY3DL, 0x33333333)
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPRDDQBY0DL, 0x33333333)
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPRDDQBY1DL, 0x33333333)
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPRDDQBY2DL, 0x33333333)
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPRDDQBY3DL, 0x33333333)
/*
* MDMISC, mirroring, interleaved (row/bank/col)
*/
-WRITE_ENTRY1(MMDC_P0_MDMISC, 0x00081740)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDMISC, 0x00081740)
/*
* MDSCR, con_req
*/
-WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00008000)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x00008000)
/*
* MDCFG0,
@@ -139,7 +139,7 @@ WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00008000)
* tRFC=0x6a clocks, tXS=0x6e clocks, tXP=3 clocks, tXPDLL=10 clocks
* tFAW=19 clocks, cas=6 cycles
*/
-WRITE_ENTRY2(MMDC_P0_MDCFG0, 0x555A7975, 0x696D5323)
+WRITE_ENTRY2(MMDC_P0 + MMDC_MDCFG0, 0x555A7975, 0x696D5323)
/*
* MDCFG1,
@@ -148,14 +148,14 @@ WRITE_ENTRY2(MMDC_P0_MDCFG0, 0x555A7975, 0x696D5323)
* MX6DL/SOLO:
* tRDC=6, tRP=6, tRC=20, tRAS=15, tRPA=tRP+1, tWR=7, tMRD=4, tCWL=5
*/
-WRITE_ENTRY2(MMDC_P0_MDCFG1, 0xFF538E64, 0xB66E8C63)
+WRITE_ENTRY2(MMDC_P0 + MMDC_MDCFG1, 0xFF538E64, 0xB66E8C63)
/*
* MDCFG2,tDLLK=512,tRTP=4,tWTR=4,tRRD=4
*/
-WRITE_ENTRY1(MMDC_P0_MDCFG2, 0x01FF00DB)
-WRITE_ENTRY1(MMDC_P0_MDRWD, 0x000026D2)
-WRITE_ENTRY1(MMDC_P0_MDOR, 0x005B0E21)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDCFG2, 0x01FF00DB)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDRWD, 0x000026D2)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDOR, 0x005B0E21)
/*
* MMDC_MDOTC,
@@ -164,7 +164,7 @@ WRITE_ENTRY1(MMDC_P0_MDOR, 0x005B0E21)
* MX6DL/SOLO:
* tAOFPD=1 cycles, tAONPD=1, tANPD=4, tAXPD=4, tODTLon=4, tODT_idle_off=4
*/
-WRITE_ENTRY2(MMDC_P0_MDOTC, 0x09444040, 0x00333030)
+WRITE_ENTRY2(MMDC_P0 + MMDC_MDOTC, 0x09444040, 0x00333030)
/*
* MDPDC - [17:16](2) => CKE pulse width = 3 cycles.
@@ -173,7 +173,7 @@ WRITE_ENTRY2(MMDC_P0_MDOTC, 0x09444040, 0x00333030)
* MX6Q: [2:0](6) => CKSRE = 6 cycles, [5:3](6) => CKSRX = 6 cycles
* MX6DL/SOLO: [2:0](5) => CKSRE = 5 cycles, [5:3](5) => CKSRX = 5 cycles
*/
-WRITE_ENTRY2(MMDC_P0_MDPDC, 0x00025576, 0x0002556D)
+WRITE_ENTRY2(MMDC_P0 + MMDC_MDPDC, 0x00025576, 0x0002556D)
/*
* MX6Q/DL - 64 bit wide ddr
@@ -186,68 +186,68 @@ WRITE_ENTRY2(MMDC_P0_MDPDC, 0x00025576, 0x0002556D)
* 1<<3 + 1<<4 - 1 = 8 + 0x10 -1 = 0x17
*/
/* MDASP, CS0_END */
-WRITE_ENTRY3(MMDC_P0_MDASP, 0x00000027, 0x00000027, 0x00000017)
+WRITE_ENTRY3(MMDC_P0 + MMDC_MDASP, 0x00000027, 0x00000027, 0x00000017)
/*
* MDCTL, CS0 enable, CS1 disabled, row=14, col=10, burst=8
* MX6Q/DL: width=64bit row+col+bank+width=14+10+3+3=30 = 1G
* MX6SOLO: width=32bit row+col+bank+width=14+10+3+2=29 = 512M
*/
-WRITE_ENTRY3(MMDC_P0_MDCTL, 0x831A0000, 0x831A0000, 0x83190000)
+WRITE_ENTRY3(MMDC_P0 + MMDC_MDCTL, 0x831A0000, 0x831A0000, 0x83190000)
/*
* LOAD MR2: MDSCR, con_req, CS0, A10 set - RZQ/2
* MX6Q: A3 set(CAS Write=6)
* MX6DL/SOLO: (CAS Write=5)
*/
-WRITE_ENTRY2(MMDC_P0_MDSCR, 0x04088032, 0x04008032)
+WRITE_ENTRY2(MMDC_P0 + MMDC_MDSCR, 0x04088032, 0x04008032)
/* LOAD MR3, CS0 */
-WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00008033)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x00008033)
/*
* LOAD MR1, CS0
* MX6Q: A6 set: Rtt=RZQ/2, A1 set: ODI=RZQ/7
* MX6DL/SOLO: A2 set: Rtt=RZQ/4, ODI=RZQ/6
*/
-WRITE_ENTRY2(MMDC_P0_MDSCR, 0x00428031, 0x00048031)
+WRITE_ENTRY2(MMDC_P0 + MMDC_MDSCR, 0x00428031, 0x00048031)
/* LOAD MR0, CS0 A8 set: DLL Reset
* MX6Q: A6 set: CAS=8 A11 set: WR=8
* MX6DL/SOLO: A4 set: CAS=5, A9,A10 set: WR=7
*/
-WRITE_ENTRY2(MMDC_P0_MDSCR, 0x09408030, 0x07208030)
+WRITE_ENTRY2(MMDC_P0 + MMDC_MDSCR, 0x09408030, 0x07208030)
/* ZQ calibrate, CS0 */
-WRITE_ENTRY1(MMDC_P0_MDSCR, 0x04008040)
-WRITE_ENTRY1(MMDC_P0_MPZQHWCTRL, 0xA1390003)
-WRITE_ENTRY1(MMDC_P1_MPZQHWCTRL, 0xA1390003)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x04008040)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPZQHWCTRL, 0xA1390003)
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPZQHWCTRL, 0xA1390003)
/* MDREF, 32KHz refresh, 4 refeshes each */
-WRITE_ENTRY1(MMDC_P0_MDREF, 0x00005800)
-WRITE_ENTRY1(MMDC_P0_MPODTCTRL, 0x00022227)
-WRITE_ENTRY1(MMDC_P1_MPODTCTRL, 0x00022227)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDREF, 0x00005800)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPODTCTRL, 0x00022227)
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPODTCTRL, 0x00022227)
/* MPDGCTRL0/1 DQS GATE*/
-WRITE_ENTRY2(MMDC_P0_MPDGCTRL0, 0x434B0350, 0x42350231)
-WRITE_ENTRY2(MMDC_P0_MPDGCTRL1, 0x034C0359, 0x021A0218)
-WRITE_ENTRY2(MMDC_P1_MPDGCTRL0, 0x434B0350, 0x42350231)
-WRITE_ENTRY2(MMDC_P1_MPDGCTRL1, 0x03650348, 0x021A0218)
-WRITE_ENTRY2(MMDC_P0_MPRDDLCTL, 0x4436383B, 0x4B4B4E49)
-WRITE_ENTRY2(MMDC_P1_MPRDDLCTL, 0x39393341, 0x4B4B4E49)
-WRITE_ENTRY2(MMDC_P0_MPWRDLCTL, 0x35373933, 0x3F3F3035)
-WRITE_ENTRY2(MMDC_P1_MPWRDLCTL, 0x48254A36, 0x3F3F3035)
-WRITE_ENTRY2(MMDC_P0_MPWLDECTRL0, 0x001F001F, 0x0040003C)
-WRITE_ENTRY2(MMDC_P0_MPWLDECTRL1, 0x001F001F, 0x0032003E)
-WRITE_ENTRY2(MMDC_P1_MPWLDECTRL0, 0x00440044, 0x0040003C)
-WRITE_ENTRY2(MMDC_P1_MPWLDECTRL1, 0x00440044, 0x0032003E)
+WRITE_ENTRY2(MMDC_P0 + MMDC_MPDGCTRL0, 0x434B0350, 0x42350231)
+WRITE_ENTRY2(MMDC_P0 + MMDC_MPDGCTRL1, 0x034C0359, 0x021A0218)
+WRITE_ENTRY2(MMDC_P1 + MMDC_MPDGCTRL0, 0x434B0350, 0x42350231)
+WRITE_ENTRY2(MMDC_P1 + MMDC_MPDGCTRL1, 0x03650348, 0x021A0218)
+WRITE_ENTRY2(MMDC_P0 + MMDC_MPRDDLCTL, 0x4436383B, 0x4B4B4E49)
+WRITE_ENTRY2(MMDC_P1 + MMDC_MPRDDLCTL, 0x39393341, 0x4B4B4E49)
+WRITE_ENTRY2(MMDC_P0 + MMDC_MPWRDLCTL, 0x35373933, 0x3F3F3035)
+WRITE_ENTRY2(MMDC_P1 + MMDC_MPWRDLCTL, 0x48254A36, 0x3F3F3035)
+WRITE_ENTRY2(MMDC_P0 + MMDC_MPWLDECTRL0, 0x001F001F, 0x0040003C)
+WRITE_ENTRY2(MMDC_P0 + MMDC_MPWLDECTRL1, 0x001F001F, 0x0032003E)
+WRITE_ENTRY2(MMDC_P1 + MMDC_MPWLDECTRL0, 0x00440044, 0x0040003C)
+WRITE_ENTRY2(MMDC_P1 + MMDC_MPWLDECTRL1, 0x00440044, 0x0032003E)
/* MPMUR0 - Complete calibration by forced measurement */
-WRITE_ENTRY1(MMDC_P0_MPMUR0, 0x00000800)
-WRITE_ENTRY1(MMDC_P1_MPMUR0, 0x00000800)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPMUR0, 0x00000800)
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPMUR0, 0x00000800)
/* MDSCR, enable ddr */
-WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00000000)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x00000000)
/* MAPSR, 1024 cycles idle before self-refresh */
-WRITE_ENTRY1(MMDC_P0_MAPSR, 0x00011006)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MAPSR, 0x00011006)
/* set the default clock gate to save power */
WRITE_ENTRY1(CCM_CCGR0, 0x00C03F3F)
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 30/32] mx6qsabrelite: change CONFIG_SYS_PROMPT
2012-10-04 1:47 ` [U-Boot] [PATCH V3 30/32] mx6qsabrelite: change CONFIG_SYS_PROMPT Troy Kisky
@ 2012-10-04 3:00 ` Otavio Salvador
2012-10-04 23:28 ` Troy Kisky
0 siblings, 1 reply; 430+ messages in thread
From: Otavio Salvador @ 2012-10-04 3:00 UTC (permalink / raw)
To: u-boot
On Wed, Oct 3, 2012 at 10:47 PM, Troy Kisky
<troy.kisky@boundarydevices.com> wrote:
> The prompt is not appropriate if not running on
> a mx6q processor.
>
> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
But in this case the board name will change, no?
--
Otavio Salvador O.S. Systems
E-mail: otavio at ossystems.com.br http://www.ossystems.com.br
Mobile: +55 53 9981-7854 http://projetos.ossystems.com.br
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 27/32] mx6qsabrelite: add support for mx6 solo/duallite
2012-10-04 1:47 ` [U-Boot] [PATCH V3 27/32] mx6qsabrelite: add support for mx6 solo/duallite Troy Kisky
@ 2012-10-04 3:23 ` Otavio Salvador
2012-10-04 23:34 ` Troy Kisky
0 siblings, 1 reply; 430+ messages in thread
From: Otavio Salvador @ 2012-10-04 3:23 UTC (permalink / raw)
To: u-boot
On Wed, Oct 3, 2012 at 10:47 PM, Troy Kisky
<troy.kisky@boundarydevices.com> wrote:
> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
> ---
> board/freescale/mx6qsabrelite/mx6qsabrelite.c | 235 ++++++-------------------
> board/freescale/mx6qsabrelite/pads.h | 172 ++++++++++++++++++
I'd say mx6qsabrelite could be renamed to mx6sabrelite so it is not confusing.
--
Otavio Salvador O.S. Systems
E-mail: otavio at ossystems.com.br http://www.ossystems.com.br
Mobile: +55 53 9981-7854 http://projetos.ossystems.com.br
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 00/32] Add mx6solo/mx6duallite support
2012-10-04 1:47 ` [U-Boot] [PATCH V3 00/32] " Troy Kisky
` (31 preceding siblings ...)
2012-10-04 1:47 ` [U-Boot] [PATCH V3 32/32] imx-mkimage.h: use base + offset syntax Troy Kisky
@ 2012-10-04 10:18 ` Albert ARIBAUD
2012-10-04 14:36 ` Eric Nelson
2012-10-04 14:52 ` Eric Nelson
2012-10-08 13:15 ` Stefano Babic
34 siblings, 1 reply; 430+ messages in thread
From: Albert ARIBAUD @ 2012-10-04 10:18 UTC (permalink / raw)
To: u-boot
Hi Troy,
On Wed, 3 Oct 2012 18:47:02 -0700, Troy Kisky
<troy.kisky@boundarydevices.com> wrote:
> This series goal is to add support for mx6solo and mx6duallite
> variants of mx6qsabrelite board. The new targets are
> called mx6ssabrelite and mx6dlsabrelite.
If the boards are known as 'mx6solo' and 'mx6duallite', they should be
named so rather than called yet another nickname.
> The 1st 16 patches perform cleanup on imximage
>
> The final 2 patches add support for expressions to mkimage.
> If found not to be worth the effort, they can be omitted.
>
>
> Troy Kisky (32):
> imximage: check dcd_len as entries added
> imximage: remove redundant setting of app_dest_ptr
> imximage: move flash_offset check to common location
> imximage: fix size of image to load.
> imximage: delay setting of image size
> imximage: change parameters to set_imx_hdr
> imximage: make set_imx_hdr_v1/v2 easier to read
> imximage: make header variable length
> imximage: remove static imximage_version
> imximage: prepare to move static variables to struct data_src
> imximage: change parameters for set_dcd_val/set_imx_hdr
> imximage: move set_imx_hdr to struct data_src
> imximage: move set_dcd_val to struct data_src
> imximage: enable word writes for version2 header
> tools: add parse_helper file
> imximage: use parse_helper functions
> imximage.cfg: run files through C preprocessor
> mx6q_4x_mt41j128.cfg: use symbols instead of hardcoded constants
> mx6q_4x_mt41j128.cfg: add comments
> mx6q_4x_mt41j128.cfg: use ddr3 mode for reset
> mx6q_4x_mt41j128.cfg: skip initiailizing non-existent memory
> mx6q_4x_mt41j128.cfg: force ZQ calibration
> mx6: soc: update get_cpu_rev and get_imx_type for mx6solo/sololite
> mx6: use CONFIG_MX6 instead of CONFIG_MX6Q
> imx-common: cpu: add imx_ddr_size
> arch-mx6: add mx6dl_pins.h
> mx6qsabrelite: add support for mx6 solo/duallite
> mx6q_4x_mt41j128.cfg: add mx6 solo/duallite support
> Add boards for sabrelite variants mx6s(solo) and mx6dl(duallite)
> mx6qsabrelite: change CONFIG_SYS_PROMPT
> parse_helper: add expression evaluation
> imx-mkimage.h: use base + offset syntax
>
> Makefile | 3 +-
> arch/arm/cpu/armv7/mx6/soc.c | 32 +-
> arch/arm/imx-common/cpu.c | 66 +++-
> arch/arm/include/asm/arch-mx5/sys_proto.h | 10 +-
> arch/arm/include/asm/arch-mx6/imx-mkimage.h | 133 +++++++
> arch/arm/include/asm/arch-mx6/imx-regs.h | 2 +
> arch/arm/include/asm/arch-mx6/mx6dl_pins.h | 118 ++++++
> arch/arm/include/asm/arch-mx6/sys_proto.h | 10 +-
> board/esg/ima3-mx53/imximage.cfg | 120 +++---
> board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 425 ++++++++++++---------
> board/freescale/mx25pdk/imximage.cfg | 77 ++--
> board/freescale/mx51evk/imximage.cfg | 114 +++---
> board/freescale/mx53ard/imximage_dd3.cfg | 83 +++--
> board/freescale/mx53evk/imximage.cfg | 86 ++---
> board/freescale/mx53loco/imximage.cfg | 83 +++--
> board/freescale/mx53smd/imximage.cfg | 83 +++--
> board/freescale/mx6qarm2/imximage.cfg | 88 ++---
> board/freescale/mx6qsabrelite/mx6qsabrelite.c | 235 +++---------
> board/freescale/mx6qsabrelite/pads.h | 172 +++++++++
> board/genesi/mx51_efikamx/imximage_mx.cfg | 132 +++----
> board/genesi/mx51_efikamx/imximage_sb.cfg | 126 ++++---
> board/ttcontrol/vision2/imximage_hynix.cfg | 295 ++++++++-------
> boards.cfg | 4 +-
> drivers/gpio/mxc_gpio.c | 6 +-
> drivers/video/ipu_regs.h | 2 +-
> include/configs/mx6qarm2.h | 1 +
> include/configs/mx6qsabre_common.h | 1 +
> include/configs/mx6qsabrelite.h | 4 +-
> tools/Makefile | 2 +
> tools/imximage.c | 487 ++++++++++---------------
> tools/imximage.h | 39 +-
> tools/parse_helper.c | 325 +++++++++++++++++
> tools/parse_helper.h | 28 ++
> 33 files changed, 2106 insertions(+), 1286 deletions(-)
> create mode 100644 arch/arm/include/asm/arch-mx6/imx-mkimage.h
> create mode 100644 arch/arm/include/asm/arch-mx6/mx6dl_pins.h
> create mode 100644 board/freescale/mx6qsabrelite/pads.h
> create mode 100644 tools/parse_helper.c
> create mode 100644 tools/parse_helper.h
>
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 00/32] Add mx6solo/mx6duallite support
2012-10-04 10:18 ` [U-Boot] [PATCH V3 00/32] Add mx6solo/mx6duallite support Albert ARIBAUD
@ 2012-10-04 14:36 ` Eric Nelson
2012-10-04 19:51 ` Albert ARIBAUD
0 siblings, 1 reply; 430+ messages in thread
From: Eric Nelson @ 2012-10-04 14:36 UTC (permalink / raw)
To: u-boot
On 10/04/2012 03:18 AM, Albert ARIBAUD wrote:
> Hi Troy,
>
> On Wed, 3 Oct 2012 18:47:02 -0700, Troy Kisky
> <troy.kisky@boundarydevices.com> wrote:
>
>> This series goal is to add support for mx6solo and mx6duallite
>> variants of mx6qsabrelite board. The new targets are
>> called mx6ssabrelite and mx6dlsabrelite.
>
> If the boards are known as 'mx6solo' and 'mx6duallite', they should be
> named so rather than called yet another nickname.
>
Hi Albert,
I'm not sure I understand your comment.
mx6solo and mx6duallite are the CPU names, not the
board names.
mx6dlsabrelite is a version of the SABRE Lite board containing
the mx6duallite CPU instead of the mx6quad.
We'll also be offering Nitrogen6X in mx6solo and mx6duallite
variants.
Regards,
Eric
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 00/32] Add mx6solo/mx6duallite support
2012-10-04 1:47 ` [U-Boot] [PATCH V3 00/32] " Troy Kisky
` (32 preceding siblings ...)
2012-10-04 10:18 ` [U-Boot] [PATCH V3 00/32] Add mx6solo/mx6duallite support Albert ARIBAUD
@ 2012-10-04 14:52 ` Eric Nelson
2012-10-08 13:15 ` Stefano Babic
34 siblings, 0 replies; 430+ messages in thread
From: Eric Nelson @ 2012-10-04 14:52 UTC (permalink / raw)
To: u-boot
Hi Troy,
On 10/03/2012 06:47 PM, Troy Kisky wrote:
> This series goal is to add support for mx6solo and mx6duallite
> variants of mx6qsabrelite board. The new targets are
> called mx6ssabrelite and mx6dlsabrelite.
>
> The 1st 16 patches perform cleanup on imximage
>
> The final 2 patches add support for expressions to mkimage.
> If found not to be worth the effort, they can be omitted.
>
>
> Troy Kisky (32):
> imximage: check dcd_len as entries added
> imximage: remove redundant setting of app_dest_ptr
> imximage: move flash_offset check to common location
> imximage: fix size of image to load.
> imximage: delay setting of image size
> imximage: change parameters to set_imx_hdr
> imximage: make set_imx_hdr_v1/v2 easier to read
> imximage: make header variable length
> imximage: remove static imximage_version
> imximage: prepare to move static variables to struct data_src
> imximage: change parameters for set_dcd_val/set_imx_hdr
> imximage: move set_imx_hdr to struct data_src
> imximage: move set_dcd_val to struct data_src
> imximage: enable word writes for version2 header
> tools: add parse_helper file
> imximage: use parse_helper functions
> imximage.cfg: run files through C preprocessor
> mx6q_4x_mt41j128.cfg: use symbols instead of hardcoded constants
> mx6q_4x_mt41j128.cfg: add comments
> mx6q_4x_mt41j128.cfg: use ddr3 mode for reset
> mx6q_4x_mt41j128.cfg: skip initiailizing non-existent memory
> mx6q_4x_mt41j128.cfg: force ZQ calibration
> mx6: soc: update get_cpu_rev and get_imx_type for mx6solo/sololite
> mx6: use CONFIG_MX6 instead of CONFIG_MX6Q
> imx-common: cpu: add imx_ddr_size
> arch-mx6: add mx6dl_pins.h
> mx6qsabrelite: add support for mx6 solo/duallite
> mx6q_4x_mt41j128.cfg: add mx6 solo/duallite support
> Add boards for sabrelite variants mx6s(solo) and mx6dl(duallite)
> mx6qsabrelite: change CONFIG_SYS_PROMPT
> parse_helper: add expression evaluation
> imx-mkimage.h: use base + offset syntax
>
> Makefile | 3 +-
> arch/arm/cpu/armv7/mx6/soc.c | 32 +-
> arch/arm/imx-common/cpu.c | 66 +++-
> arch/arm/include/asm/arch-mx5/sys_proto.h | 10 +-
> arch/arm/include/asm/arch-mx6/imx-mkimage.h | 133 +++++++
> arch/arm/include/asm/arch-mx6/imx-regs.h | 2 +
> arch/arm/include/asm/arch-mx6/mx6dl_pins.h | 118 ++++++
> arch/arm/include/asm/arch-mx6/sys_proto.h | 10 +-
> board/esg/ima3-mx53/imximage.cfg | 120 +++---
> board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 425 ++++++++++++---------
> board/freescale/mx25pdk/imximage.cfg | 77 ++--
> board/freescale/mx51evk/imximage.cfg | 114 +++---
> board/freescale/mx53ard/imximage_dd3.cfg | 83 +++--
> board/freescale/mx53evk/imximage.cfg | 86 ++---
> board/freescale/mx53loco/imximage.cfg | 83 +++--
> board/freescale/mx53smd/imximage.cfg | 83 +++--
> board/freescale/mx6qarm2/imximage.cfg | 88 ++---
> board/freescale/mx6qsabrelite/mx6qsabrelite.c | 235 +++---------
> board/freescale/mx6qsabrelite/pads.h | 172 +++++++++
> board/genesi/mx51_efikamx/imximage_mx.cfg | 132 +++----
> board/genesi/mx51_efikamx/imximage_sb.cfg | 126 ++++---
> board/ttcontrol/vision2/imximage_hynix.cfg | 295 ++++++++-------
> boards.cfg | 4 +-
> drivers/gpio/mxc_gpio.c | 6 +-
> drivers/video/ipu_regs.h | 2 +-
> include/configs/mx6qarm2.h | 1 +
> include/configs/mx6qsabre_common.h | 1 +
> include/configs/mx6qsabrelite.h | 4 +-
> tools/Makefile | 2 +
> tools/imximage.c | 487 ++++++++++---------------
> tools/imximage.h | 39 +-
> tools/parse_helper.c | 325 +++++++++++++++++
> tools/parse_helper.h | 28 ++
> 33 files changed, 2106 insertions(+), 1286 deletions(-)
> create mode 100644 arch/arm/include/asm/arch-mx6/imx-mkimage.h
> create mode 100644 arch/arm/include/asm/arch-mx6/mx6dl_pins.h
> create mode 100644 board/freescale/mx6qsabrelite/pads.h
> create mode 100644 tools/parse_helper.c
> create mode 100644 tools/parse_helper.h
>
There's clearly a lot going on in this patch set. Does it make
sense to split this into parts that can be reviewed and checked
separately?
It seems that there are
- bug fixes to imximage
- enhancements to imximage
- enhancements to build for imximage.cfg (CPP)
- core i.MX6 changes (cpu types, etc)
- rework of imximage.cfg files to use CPP
...
And there's that simple one changing the prompt we can
probably get a quick ack/nak on ;)
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 00/32] Add mx6solo/mx6duallite support
2012-10-04 14:36 ` Eric Nelson
@ 2012-10-04 19:51 ` Albert ARIBAUD
0 siblings, 0 replies; 430+ messages in thread
From: Albert ARIBAUD @ 2012-10-04 19:51 UTC (permalink / raw)
To: u-boot
Hi Eric,
On Thu, 04 Oct 2012 07:36:45 -0700, Eric Nelson
<eric.nelson@boundarydevices.com> wrote:
> On 10/04/2012 03:18 AM, Albert ARIBAUD wrote:
> > Hi Troy,
> >
> > On Wed, 3 Oct 2012 18:47:02 -0700, Troy Kisky
> > <troy.kisky@boundarydevices.com> wrote:
> >
> >> This series goal is to add support for mx6solo and mx6duallite
> >> variants of mx6qsabrelite board. The new targets are
> >> called mx6ssabrelite and mx6dlsabrelite.
> >
> > If the boards are known as 'mx6solo' and 'mx6duallite', they should be
> > named so rather than called yet another nickname.
> >
>
> Hi Albert,
>
> I'm not sure I understand your comment.
>
> mx6solo and mx6duallite are the CPU names, not the
> board names.
That's where the misunderstanding crept in: I thought these were board
names, not CPU names.
> mx6dlsabrelite is a version of the SABRE Lite board containing
> the mx6duallite CPU instead of the mx6quad.
>
> We'll also be offering Nitrogen6X in mx6solo and mx6duallite
> variants.
Understood now -- and disregard my initial comment.
> Regards,
>
>
> Eric
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 30/32] mx6qsabrelite: change CONFIG_SYS_PROMPT
2012-10-04 3:00 ` Otavio Salvador
@ 2012-10-04 23:28 ` Troy Kisky
2012-10-08 13:54 ` Stefano Babic
0 siblings, 1 reply; 430+ messages in thread
From: Troy Kisky @ 2012-10-04 23:28 UTC (permalink / raw)
To: u-boot
On 10/3/2012 8:00 PM, Otavio Salvador wrote:
> On Wed, Oct 3, 2012 at 10:47 PM, Troy Kisky
> <troy.kisky@boundarydevices.com> wrote:
>> The prompt is not appropriate if not running on
>> a mx6q processor.
>>
>> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
> But in this case the board name will change, no?
>
No, patch 29/32 sets the new boards to use the same config file
(mx6qsabrelite.h) only adding ",MX6DL" or ",MX6S" or ",MX6Q"
to the end of the line in boards.cfg
Troy
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 27/32] mx6qsabrelite: add support for mx6 solo/duallite
2012-10-04 3:23 ` Otavio Salvador
@ 2012-10-04 23:34 ` Troy Kisky
2012-10-08 13:47 ` Stefano Babic
0 siblings, 1 reply; 430+ messages in thread
From: Troy Kisky @ 2012-10-04 23:34 UTC (permalink / raw)
To: u-boot
On 10/3/2012 8:23 PM, Otavio Salvador wrote:
> On Wed, Oct 3, 2012 at 10:47 PM, Troy Kisky
> <troy.kisky@boundarydevices.com> wrote:
>> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
>> ---
>> board/freescale/mx6qsabrelite/mx6qsabrelite.c | 235 ++++++-------------------
>> board/freescale/mx6qsabrelite/pads.h | 172 ++++++++++++++++++
> I'd say mx6qsabrelite could be renamed to mx6sabrelite so it is not confusing.
>
Both mx6qsabrelite.c and mx6qsabrelite.h should be renamed to drop the q.
Also, the directory could be renamed ?
I think a follow on patch later to reduced conflicts with others work
would be
appropriate.
Troy
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 17/32] imximage.cfg: run files through C preprocessor
2012-10-04 1:47 ` [U-Boot] [PATCH V3 17/32] imximage.cfg: run files through C preprocessor Troy Kisky
@ 2012-10-07 18:19 ` Eric Nelson
2012-10-08 19:11 ` Troy Kisky
2012-10-08 13:38 ` Stefano Babic
1 sibling, 1 reply; 430+ messages in thread
From: Eric Nelson @ 2012-10-07 18:19 UTC (permalink / raw)
To: u-boot
Hi Troy,
On 10/03/2012 06:47 PM, Troy Kisky wrote:
> The '#' used as comments in the files cause the preprocessor
> trouble, so change to /* */.
>
> Signed-off-by: Troy Kisky<troy.kisky@boundarydevices.com>
> ---
> Makefile | 3 +-
> board/esg/ima3-mx53/imximage.cfg | 120 ++++++-----
> board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 90 ++++----
> board/freescale/mx25pdk/imximage.cfg | 77 +++----
> board/freescale/mx51evk/imximage.cfg | 114 +++++-----
> board/freescale/mx53ard/imximage_dd3.cfg | 83 ++++----
> board/freescale/mx53evk/imximage.cfg | 86 ++++----
> board/freescale/mx53loco/imximage.cfg | 83 ++++----
> board/freescale/mx53smd/imximage.cfg | 83 ++++----
> board/freescale/mx6qarm2/imximage.cfg | 88 ++++----
> board/genesi/mx51_efikamx/imximage_mx.cfg | 132 ++++++------
> board/genesi/mx51_efikamx/imximage_sb.cfg | 126 +++++------
> board/ttcontrol/vision2/imximage_hynix.cfg | 295 ++++++++++++++------------
> 13 files changed, 727 insertions(+), 653 deletions(-)
>
> diff --git a/Makefile b/Makefile
> index a40d4cc..64ff1b8 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -431,7 +431,8 @@ $(obj)u-boot.img: $(obj)u-boot.bin
> -d $< $@
>
> $(obj)u-boot.imx: $(obj)u-boot.bin
> - $(obj)tools/mkimage -n $(CONFIG_IMX_CONFIG) -T imximage \
> + $(CC) -E -x c $(CONFIG_IMX_CONFIG) -I./include -o $(obj)imxcfg.imx
> + $(obj)tools/mkimage -n $(obj)imxcfg.imx -T imximage \
> -e $(CONFIG_SYS_TEXT_BASE) -d $< $@
This bit creates imxcfg.imx.
If built in-tree, the file will be reported as a new file in 'git status'.
Is there a reason it can't be deleted after the build?
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 21/32] mx6q_4x_mt41j128.cfg: skip initiailizing non-existent memory
2012-10-04 1:47 ` [U-Boot] [PATCH V3 21/32] mx6q_4x_mt41j128.cfg: skip initiailizing non-existent memory Troy Kisky
@ 2012-10-07 21:01 ` Eric Nelson
0 siblings, 0 replies; 430+ messages in thread
From: Eric Nelson @ 2012-10-07 21:01 UTC (permalink / raw)
To: u-boot
Hi Troy,
On 10/03/2012 06:47 PM, Troy Kisky wrote:
> Sabrelite does not have memory associated with CS1
>
> Signed-off-by: Troy Kisky<troy.kisky@boundarydevices.com>
> ---
> board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 5 -----
> 1 file changed, 5 deletions(-)
>
> diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
> index 9c622c8..2d03ff7 100644
> --- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
> +++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
> @@ -155,20 +155,15 @@ WRITE_ENTRY1(MMDC_P0_MDCTL, 0x831A0000)
>
> /* MDSCR, con_req, LOAD MR2, CS0, A3,A10 set (CAS Write=6), RZQ/2 */
> WRITE_ENTRY1(MMDC_P0_MDSCR, 0x04088032)
> -WRITE_ENTRY1(MMDC_P0_MDSCR, 0x0408803A)
> /* LOAD MR3, CS0 */
> WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00008033)
> -WRITE_ENTRY1(MMDC_P0_MDSCR, 0x0000803B)
> /* LOAD MR1, CS0, A1,A6 set Rtt=RZQ/2, ODI=RZQ/7 */
> WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00428031)
> -WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00428039)
> /* LOAD MR0, CS0, A6,A8,A11 set CAS=8, WR=8, DLL reset */
> WRITE_ENTRY1(MMDC_P0_MDSCR, 0x09408030)
> -WRITE_ENTRY1(MMDC_P0_MDSCR, 0x09408038)
>
> /* ZQ calibrate, CS0 */
> WRITE_ENTRY1(MMDC_P0_MDSCR, 0x04008040)
> -WRITE_ENTRY1(MMDC_P0_MDSCR, 0x04008048)
> WRITE_ENTRY1(MMDC_P0_MPZQHWCTRL, 0xA1380003)
> WRITE_ENTRY1(MMDC_P1_MPZQHWCTRL, 0xA1380003)
>
Note that mx6qsabreauto and mx6qsabresd also use this config file.
That said, none of these boards have pad DRAM_CS1 connected.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 25/32] imx-common: cpu: add imx_ddr_size
2012-10-04 1:47 ` [U-Boot] [PATCH V3 25/32] imx-common: cpu: add imx_ddr_size Troy Kisky
@ 2012-10-08 13:06 ` Stefano Babic
2012-10-08 21:35 ` Troy Kisky
0 siblings, 1 reply; 430+ messages in thread
From: Stefano Babic @ 2012-10-08 13:06 UTC (permalink / raw)
To: u-boot
On 04/10/2012 03:47, Troy Kisky wrote:
> Read memory setup registers to determine size
> of available ram. This routine works for mx53/mx6x
>
> I need this because when mx6solo called get_ram_size
> with a too large maximum size, the system hanged.
>
> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
>
Hi Troy,
I am interested to better understand why get_ram_size() does not work.
It seems to me you discovered a bug in this function, and you circumvent
it decoding the DRAM controller setup to get the RAM size.
Because the max size is added to the start address in get_ram_size(), I
have the feeling that this overwlow the long value, and maybe can be
fixed swithcing to a "long long". With which parameters to
get_ram_size() does your board hang ?
> ---
> New patch with V3. V2 had code in mx6qsabrelite.c
> ---
> arch/arm/imx-common/cpu.c | 50 +++++++++++++++++++++++++++++
> arch/arm/include/asm/arch-mx5/sys_proto.h | 1 +
> arch/arm/include/asm/arch-mx6/sys_proto.h | 1 +
> 3 files changed, 52 insertions(+)
>
> diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
> index 102c254..5081908 100644
> --- a/arch/arm/imx-common/cpu.c
> +++ b/arch/arm/imx-common/cpu.c
> @@ -65,6 +65,56 @@ char *get_reset_cause(void)
> }
> }
>
> +#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
> +#if defined(CONFIG_MX53)
> +#define MEMCTL_BASE ESDCTL_BASE_ADDR;
> +#else
> +#define MEMCTL_BASE MMDC_P0_BASE_ADDR;
> +#endif
> +static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
> +static const unsigned char bank_lookup[] = {3, 2};
> +
> +struct esd_mmdc_regs {
> + uint32_t ctl;
> + uint32_t pdc;
> + uint32_t otc;
> + uint32_t cfg0;
> + uint32_t cfg1;
> + uint32_t cfg2;
> + uint32_t misc;
> + uint32_t scr;
> + uint32_t ref;
> + uint32_t rsvd1;
> + uint32_t rsvd2;
> + uint32_t rwd;
> + uint32_t or;
> + uint32_t mrr;
> + uint32_t cfg3lp;
> + uint32_t mr4;
> +};
> +
> +#define ESD_MMDC_CTL_GET_ROW(mdctl) ((ctl >> 24) & 7)
> +#define ESD_MMDC_CTL_GET_COLUMN(mdctl) ((ctl >> 20) & 7)
> +#define ESD_MMDC_CTL_GET_WIDTH(mdctl) ((ctl >> 16) & 3)
> +#define ESD_MMDC_CTL_GET_CS1(mdctl) ((ctl >> 30) & 1)
> +#define ESD_MMDC_MISC_GET_BANK(mdmisc) ((misc >> 5) & 1)
> +
> +unsigned imx_ddr_size(void)
> +{
> + struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE;
> + unsigned ctl = readl(&mem->ctl);
> + unsigned misc = readl(&mem->misc);
> + int bits = 11 + 0 + 0 + 1; /* row + col + bank + width */
> +
> + bits += ESD_MMDC_CTL_GET_ROW(ctl);
> + bits += col_lookup[ESD_MMDC_CTL_GET_COLUMN(ctl)];
> + bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)];
> + bits += ESD_MMDC_CTL_GET_WIDTH(ctl);
> + bits += ESD_MMDC_CTL_GET_CS1(ctl);
> + return 1 << bits;
> +}
> +#endif
> +
> #if defined(CONFIG_DISPLAY_CPUINFO)
>
> const char *get_imx_type(u32 imxtype)
> diff --git a/arch/arm/include/asm/arch-mx5/sys_proto.h b/arch/arm/include/asm/arch-mx5/sys_proto.h
> index 4435be1..93ad1c6 100644
> --- a/arch/arm/include/asm/arch-mx5/sys_proto.h
> +++ b/arch/arm/include/asm/arch-mx5/sys_proto.h
> @@ -33,6 +33,7 @@
>
> #define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev)
> u32 get_cpu_rev(void);
> +unsigned imx_ddr_size(void);
> void sdelay(unsigned long);
> void set_chipselect_size(int const);
>
> diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h
> index 6627bbc..3193297 100644
> --- a/arch/arm/include/asm/arch-mx6/sys_proto.h
> +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h
> @@ -34,6 +34,7 @@
> #define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev)
> u32 get_cpu_rev(void);
> const char *get_imx_type(u32 imxtype);
> +unsigned imx_ddr_size(void);
>
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 00/32] Add mx6solo/mx6duallite support
2012-10-04 1:47 ` [U-Boot] [PATCH V3 00/32] " Troy Kisky
` (33 preceding siblings ...)
2012-10-04 14:52 ` Eric Nelson
@ 2012-10-08 13:15 ` Stefano Babic
2012-10-08 23:58 ` Troy Kisky
34 siblings, 1 reply; 430+ messages in thread
From: Stefano Babic @ 2012-10-08 13:15 UTC (permalink / raw)
To: u-boot
On 04/10/2012 03:47, Troy Kisky wrote:
> This series goal is to add support for mx6solo and mx6duallite
> variants of mx6qsabrelite board. The new targets are
> called mx6ssabrelite and mx6dlsabrelite.
>
> The 1st 16 patches perform cleanup on imximage
Hi Troy,
I have some difficulties to understand which are the dependencies of
this patchset. IMHO there are very different topics here, and some
patches can be applied independently from the other one.
imximage patches. For example, why "add mx6dl_pins" belong to imximage
patchset ? It is surely easier to split for each topic, so that each
patcheset can be applied independently if on a different topic there is
still an open issue.
I see at least:
- imximage fixes: they are really fix and can be applied soon.
- imximage new features
- mx6 patches
It is surely easier if you split your changes in separate patchset, as
they covered different topics.
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 02/32] imximage: remove redundant setting of app_dest_ptr
2012-10-04 1:47 ` [U-Boot] [PATCH V3 02/32] imximage: remove redundant setting of app_dest_ptr Troy Kisky
@ 2012-10-08 13:17 ` Stefano Babic
2012-10-20 15:46 ` Stefano Babic
1 sibling, 0 replies; 430+ messages in thread
From: Stefano Babic @ 2012-10-08 13:17 UTC (permalink / raw)
To: u-boot
On 04/10/2012 03:47, Troy Kisky wrote:
> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
>
> ---
> v3: split into its own patch
> ---
> tools/imximage.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/tools/imximage.c b/tools/imximage.c
> index c917036..bda1a75 100644
> --- a/tools/imximage.c
> +++ b/tools/imximage.c
> @@ -213,7 +213,6 @@ static void set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,
> /* Set magic number */
> fhdr_v1->app_code_barker = APP_CODE_BARKER;
>
> - fhdr_v1->app_dest_ptr = params->addr;
> fhdr_v1->app_dest_ptr = params->ep - imxhdr->flash_offset -
> sizeof(struct imx_header);
> fhdr_v1->app_code_jump_vector = params->ep;
>
I think we do not need to discuss on this. I put in in my -next queue
and I will apply it soon.
Acked-by: Stefano Babic <sbabic@denx.de>
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 03/32] imximage: move flash_offset check to common location
2012-10-04 1:47 ` [U-Boot] [PATCH V3 03/32] imximage: move flash_offset check to common location Troy Kisky
@ 2012-10-08 13:19 ` Stefano Babic
2012-10-18 18:40 ` Troy Kisky
2012-10-20 15:46 ` Stefano Babic
1 sibling, 1 reply; 430+ messages in thread
From: Stefano Babic @ 2012-10-08 13:19 UTC (permalink / raw)
To: u-boot
On 04/10/2012 03:47, Troy Kisky wrote:
> Both set_imx_hdr_v1 and set_imx_hdr_v2 perform the
> same check. Move check to before the set_imx_hdr call.
>
> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
>
> ---
> v3: split into its own patch
> ---
> tools/imximage.c | 19 +++++--------------
> 1 file changed, 5 insertions(+), 14 deletions(-)
>
> diff --git a/tools/imximage.c b/tools/imximage.c
> index bda1a75..3e9ee6a 100644
> --- a/tools/imximage.c
> +++ b/tools/imximage.c
> @@ -203,13 +203,6 @@ static void set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,
> dcd_v1_t *dcd_v1 = &hdr_v1->dcd_table;
> uint32_t base_offset;
>
> - /* Exit if there is no BOOT_FROM field specifying the flash_offset */
> - if(imxhdr->flash_offset == FLASH_OFFSET_UNDEFINED) {
> - fprintf(stderr, "Error: Header v1: No BOOT_FROM tag in %s\n",
> - params->imagename);
> - exit(EXIT_FAILURE);
> - }
> -
> /* Set magic number */
> fhdr_v1->app_code_barker = APP_CODE_BARKER;
>
> @@ -243,13 +236,6 @@ static void set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t dcd_len,
> imx_header_v2_t *hdr_v2 = &imxhdr->header.hdr_v2;
> flash_header_v2_t *fhdr_v2 = &hdr_v2->fhdr;
>
> - /* Exit if there is no BOOT_FROM field specifying the flash_offset */
> - if(imxhdr->flash_offset == FLASH_OFFSET_UNDEFINED) {
> - fprintf(stderr, "Error: Header v2: No BOOT_FROM tag in %s\n",
> - params->imagename);
> - exit(EXIT_FAILURE);
> - }
> -
> /* Set magic number */
> fhdr_v2->header.tag = IVT_HEADER_TAG; /* 0xD1 */
> fhdr_v2->header.length = cpu_to_be16(sizeof(flash_header_v2_t));
> @@ -475,6 +461,11 @@ static uint32_t parse_cfg_file(struct imx_header *imxhdr, char *name)
> (*set_dcd_rst)(imxhdr, dcd_len, name, lineno);
> fclose(fd);
>
> + /* Exit if there is no BOOT_FROM field specifying the flash_offset */
> + if (imxhdr->flash_offset == FLASH_OFFSET_UNDEFINED) {
> + fprintf(stderr, "Error: No BOOT_FROM tag in %s\n", name);
> + exit(EXIT_FAILURE);
> + }
> return dcd_len;
> }
>
Acked-by: Stefano Babic <sbabic@denx.de>
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 17/32] imximage.cfg: run files through C preprocessor
2012-10-04 1:47 ` [U-Boot] [PATCH V3 17/32] imximage.cfg: run files through C preprocessor Troy Kisky
2012-10-07 18:19 ` Eric Nelson
@ 2012-10-08 13:38 ` Stefano Babic
2012-10-08 21:48 ` Troy Kisky
2012-10-10 2:03 ` Troy Kisky
1 sibling, 2 replies; 430+ messages in thread
From: Stefano Babic @ 2012-10-08 13:38 UTC (permalink / raw)
To: u-boot
On 04/10/2012 03:47, Troy Kisky wrote:
> The '#' used as comments in the files cause the preprocessor
> trouble, so change to /* */.
>
> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
> ---
Hi Troy,
> Makefile | 3 +-
> board/esg/ima3-mx53/imximage.cfg | 120 ++++++-----
> board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 90 ++++----
> board/freescale/mx25pdk/imximage.cfg | 77 +++----
> board/freescale/mx51evk/imximage.cfg | 114 +++++-----
> board/freescale/mx53ard/imximage_dd3.cfg | 83 ++++----
> board/freescale/mx53evk/imximage.cfg | 86 ++++----
> board/freescale/mx53loco/imximage.cfg | 83 ++++----
> board/freescale/mx53smd/imximage.cfg | 83 ++++----
> board/freescale/mx6qarm2/imximage.cfg | 88 ++++----
> board/genesi/mx51_efikamx/imximage_mx.cfg | 132 ++++++------
> board/genesi/mx51_efikamx/imximage_sb.cfg | 126 +++++------
> board/ttcontrol/vision2/imximage_hynix.cfg | 295 ++++++++++++++------------
> 13 files changed, 727 insertions(+), 653 deletions(-)
>
I see the C preprocessor as an optional feature, instead of a rule
everybody must follow.
> diff --git a/Makefile b/Makefile
> index a40d4cc..64ff1b8 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -431,7 +431,8 @@ $(obj)u-boot.img: $(obj)u-boot.bin
> -d $< $@
>
> $(obj)u-boot.imx: $(obj)u-boot.bin
> - $(obj)tools/mkimage -n $(CONFIG_IMX_CONFIG) -T imximage \
> + $(CC) -E -x c $(CONFIG_IMX_CONFIG) -I./include -o $(obj)imxcfg.imx
> + $(obj)tools/mkimage -n $(obj)imxcfg.imx -T imximage \
> -e $(CONFIG_SYS_TEXT_BASE) -d $< $@
In fact, adding this rule here requires that each board configuration
must be changed. And for all of them, running the preprocessor is
unnnecessary.
What about to add this rule only to the Makefile of the boards that
require preprocessing ?
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 24/32] mx6: use CONFIG_MX6 instead of CONFIG_MX6Q
2012-10-04 1:47 ` [U-Boot] [PATCH V3 24/32] mx6: use CONFIG_MX6 instead of CONFIG_MX6Q Troy Kisky
@ 2012-10-08 13:41 ` Stefano Babic
2012-10-08 21:49 ` Troy Kisky
0 siblings, 1 reply; 430+ messages in thread
From: Stefano Babic @ 2012-10-08 13:41 UTC (permalink / raw)
To: u-boot
On 04/10/2012 03:47, Troy Kisky wrote:
> Use CONFIG_MX6 when the particular processor
> variant isn't important.
>
> Reserve the use of CONFIG_MX6Q to
> specifically test for quad cores variant.
>
> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
> ---
> drivers/gpio/mxc_gpio.c | 6 +++---
> drivers/video/ipu_regs.h | 2 +-
> include/configs/mx6qarm2.h | 1 +
> include/configs/mx6qsabre_common.h | 1 +
> include/configs/mx6qsabrelite.h | 1 +
> 5 files changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c
> index 2c79bff..a388064 100644
> --- a/drivers/gpio/mxc_gpio.c
> +++ b/drivers/gpio/mxc_gpio.c
> @@ -42,14 +42,14 @@ static unsigned long gpio_ports[] = {
> [1] = GPIO2_BASE_ADDR,
> [2] = GPIO3_BASE_ADDR,
> #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
> - defined(CONFIG_MX53) || defined(CONFIG_MX6Q)
> + defined(CONFIG_MX53) || defined(CONFIG_MX6)
> [3] = GPIO4_BASE_ADDR,
> #endif
> -#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6Q)
> +#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6)
> [4] = GPIO5_BASE_ADDR,
> [5] = GPIO6_BASE_ADDR,
> #endif
> -#if defined(CONFIG_MX53) || defined(CONFIG_MX6Q)
> +#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
> [6] = GPIO7_BASE_ADDR,
> #endif
> };
> diff --git a/drivers/video/ipu_regs.h b/drivers/video/ipu_regs.h
> index a43aa03..982e252 100644
> --- a/drivers/video/ipu_regs.h
> +++ b/drivers/video/ipu_regs.h
> @@ -55,7 +55,7 @@
> #define IPU_TPM_REG_BASE 0x01060000
> #define IPU_DC_TMPL_REG_BASE 0x01080000
> #define IPU_ISP_TBPR_REG_BASE 0x010C0000
> -#elif defined(CONFIG_MX6Q)
> +#elif defined(CONFIG_MX6)
> #define IPU_CPMEM_REG_BASE 0x00100000
> #define IPU_LUT_REG_BASE 0x00120000
> #define IPU_SRM_REG_BASE 0x00140000
> diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h
> index 965bea3..8e5b81e 100644
> --- a/include/configs/mx6qarm2.h
> +++ b/include/configs/mx6qarm2.h
> @@ -22,6 +22,7 @@
> #ifndef __CONFIG_H
> #define __CONFIG_H
>
> +#define CONFIG_MX6
> #define CONFIG_MX6Q
> #define CONFIG_DISPLAY_CPUINFO
> #define CONFIG_DISPLAY_BOARDINFO
> diff --git a/include/configs/mx6qsabre_common.h b/include/configs/mx6qsabre_common.h
> index 247e8d6..5a940da 100644
> --- a/include/configs/mx6qsabre_common.h
> +++ b/include/configs/mx6qsabre_common.h
> @@ -17,6 +17,7 @@
> #ifndef __MX6QSABRE_COMMON_CONFIG_H
> #define __MX6QSABRE_COMMON_CONFIG_H
>
> +#define CONFIG_MX6
> #define CONFIG_MX6Q
> #define CONFIG_DISPLAY_CPUINFO
> #define CONFIG_DISPLAY_BOARDINFO
> diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
> index e7bf658..6a10232 100644
> --- a/include/configs/mx6qsabrelite.h
> +++ b/include/configs/mx6qsabrelite.h
> @@ -22,6 +22,7 @@
> #ifndef __CONFIG_H
> #define __CONFIG_H
>
> +#define CONFIG_MX6
> #define CONFIG_MX6Q
> #define CONFIG_DISPLAY_CPUINFO
> #define CONFIG_DISPLAY_BOARDINFO
>
This changes affects also mx6qsabreauto and mx6qsabresd, that I have
already merged.
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 27/32] mx6qsabrelite: add support for mx6 solo/duallite
2012-10-04 23:34 ` Troy Kisky
@ 2012-10-08 13:47 ` Stefano Babic
0 siblings, 0 replies; 430+ messages in thread
From: Stefano Babic @ 2012-10-08 13:47 UTC (permalink / raw)
To: u-boot
On 05/10/2012 01:34, Troy Kisky wrote:
> On 10/3/2012 8:23 PM, Otavio Salvador wrote:
>> On Wed, Oct 3, 2012 at 10:47 PM, Troy Kisky
>> <troy.kisky@boundarydevices.com> wrote:
>>> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
>>> ---
>>> board/freescale/mx6qsabrelite/mx6qsabrelite.c | 235
>>> ++++++-------------------
>>> board/freescale/mx6qsabrelite/pads.h | 172
>>> ++++++++++++++++++
>> I'd say mx6qsabrelite could be renamed to mx6sabrelite so it is not
>> confusing.
>>
> Both mx6qsabrelite.c and mx6qsabrelite.h should be renamed to drop the q.
> Also, the directory could be renamed ?
Yes, it can, but add board's maintainer (Fabio) to the discussion.
Regards,
Stefano
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 30/32] mx6qsabrelite: change CONFIG_SYS_PROMPT
2012-10-04 23:28 ` Troy Kisky
@ 2012-10-08 13:54 ` Stefano Babic
2012-10-08 21:58 ` Troy Kisky
0 siblings, 1 reply; 430+ messages in thread
From: Stefano Babic @ 2012-10-08 13:54 UTC (permalink / raw)
To: u-boot
On 05/10/2012 01:28, Troy Kisky wrote:
> On 10/3/2012 8:00 PM, Otavio Salvador wrote:
>> On Wed, Oct 3, 2012 at 10:47 PM, Troy Kisky
>> <troy.kisky@boundarydevices.com> wrote:
>>> The prompt is not appropriate if not running on
>>> a mx6q processor.
>>>
>>> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
>> But in this case the board name will change, no?
>>
> No, patch 29/32 sets the new boards to use the same config file
> (mx6qsabrelite.h) only adding ",MX6DL" or ",MX6S" or ",MX6Q"
> to the end of the line in boards.cfg
This means that CONFIG_MX6Dx is set. You can use it to set appropriately
the prompt or use a more generic name including the board name, as
"MX6SABRELITE U-Boot > ". The board is always the same, what is
different is the SOC. I can compare this with a motherboard for a PC
that can mount a dual or quad core. The board is always the same, and
how many core are running is read in a different way (cat /proc/cpuinfo
under Linux or get_cpu_rev in U-Boot with the patch you sent).
Best regards,
Stefano
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 28/32] mx6q_4x_mt41j128.cfg: add mx6 solo/duallite support
2012-10-04 1:47 ` [U-Boot] [PATCH V3 28/32] mx6q_4x_mt41j128.cfg: add mx6 solo/duallite support Troy Kisky
@ 2012-10-08 18:46 ` Eric Nelson
2012-10-08 21:08 ` Troy Kisky
0 siblings, 1 reply; 430+ messages in thread
From: Eric Nelson @ 2012-10-08 18:46 UTC (permalink / raw)
To: u-boot
Hi Troy,
This seems to be the patch where the rubber meets the road in
much of this series.
On 10/03/2012 06:47 PM, Troy Kisky wrote:
> Signed-off-by: Troy Kisky<troy.kisky@boundarydevices.com>
> ---
> board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 120 +++++++++++++++++++-------
> 1 file changed, 87 insertions(+), 33 deletions(-)
>
> diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
> index 9e20db0..f45f93e 100644
> --- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
> +++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
> @@ -49,6 +49,15 @@ BOOT_FROM sd
> * Address absolute address of the register
> * value value to be stored in the register
> */
> +/*
> + * DDR3 settings
> + * MX6Q ddr is limited to 1066 Mhz, currently 1056 MHz(528 MHz clock),
> + * memory bus width: 64 bits, x16/x32/x64
> + * MX6DL ddr is limited to 800 MHz(400 MHz clock)
> + * memory bus width: 64 bits, x16/x32/x64
> + * MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
> + * memory bus width: 32 bits, x16/x32
> + */
This comment seems to be critical to understanding some of
what's below, since now three **different** memory configurations
are represented in this file.
At a minimum, the file name should be changed to get rid of
'6q' and '4x' since those don't necessarily apply.
> WRITE_ENTRY1(IOM_DRAM_SDQS0, 0x00000030)
> WRITE_ENTRY1(IOM_DRAM_SDQS1, 0x00000030)
> WRITE_ENTRY1(IOM_DRAM_SDQS2, 0x00000030)
> @@ -90,6 +99,7 @@ WRITE_ENTRY1(IOM_GRP_B6DS, 0x00000030)
> WRITE_ENTRY1(IOM_GRP_B7DS, 0x00000030)
>
> WRITE_ENTRY1(IOM_GRP_ADDDS, 0x00000030)
> +
> /* (differential input) */
> WRITE_ENTRY1(IOM_DDRMODE_CTL, 0x00020000)
> /* disable ddr pullups */
> @@ -119,48 +129,92 @@ WRITE_ENTRY1(MMDC_P0_MDMISC, 0x00081740)
> * MDSCR, con_req
> */
> WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00008000)
> +
> /*
> - * MDCFG0, tRFC=0x56 clocks, tXS=0x5b clocks
> - * tXP=4 clocks, tXPDLL=13 clocks
> - * tFAW=24 clocks, cas=8 cycles
> + * MDCFG0,
> + * MX6Q:
> + * tRFC=0x56 clocks, tXS=0x5b clocks, tXP=4 clocks, tXPDLL=13 clocks
> + * tFAW=24 clocks, cas=8 cycles
> + * MX6DL/SOLO:
> + * tRFC=0x6a clocks, tXS=0x6e clocks, tXP=3 clocks, tXPDLL=10 clocks
> + * tFAW=19 clocks, cas=6 cycles
> */
> -WRITE_ENTRY1(MMDC_P0_MDCFG0, 0x555A7975)
> +WRITE_ENTRY2(MMDC_P0_MDCFG0, 0x555A7975, 0x696D5323)
> +
Here's where I start to get lost in the macro-fu.
The WRITE_ENTRY1 macros make some sense to me in that they
always write a single value to an offset whose address
changes based on the processor type.
In order to understand WRITE_ENTRY2, you really have to
know that the dual, solo, and sololite share many
characteristics.
It's kinda hard to infer that knowledge from the code
and I wonder if this structure will hold up under future
revisions.
> /*
> - * MDCFG1, tRDC=8, tRP=8, tRC=27,tRAS=20,tRPA=tRP+1,tWR=8
> - * tMRD=4, tCWL=6
> + * MDCFG1,
> + * MX6Q:
> + * tRDC=8, tRP=8, tRC=27, tRAS=20, tRPA=tRP+1, tWR=8, tMRD=4, tCWL=6
> + * MX6DL/SOLO:
> + * tRDC=6, tRP=6, tRC=20, tRAS=15, tRPA=tRP+1, tWR=7, tMRD=4, tCWL=5
> */
> -WRITE_ENTRY1(MMDC_P0_MDCFG1, 0xFF538E64)
> +WRITE_ENTRY2(MMDC_P0_MDCFG1, 0xFF538E64, 0xB66E8C63)
> +
> /*
> * MDCFG2,tDLLK=512,tRTP=4,tWTR=4,tRRD=4
> */
> WRITE_ENTRY1(MMDC_P0_MDCFG2, 0x01FF00DB)
> WRITE_ENTRY1(MMDC_P0_MDRWD, 0x000026D2)
> -
> WRITE_ENTRY1(MMDC_P0_MDOR, 0x005B0E21)
> -WRITE_ENTRY1(MMDC_P0_MDOTC, 0x09444040)
> -WRITE_ENTRY1(MMDC_P0_MDPDC, 0x00025576)
>
> /*
> - * Mx6Q - 64 bit wide ddr
> + * MMDC_MDOTC,
> + * MX6Q:
> + * tAOFPD=2 cycles, tAONPD=2, tANPD=5, tAXPD=5, tODTLon=5, tODT_idle_off=5
> + * MX6DL/SOLO:
> + * tAOFPD=1 cycles, tAONPD=1, tANPD=4, tAXPD=4, tODTLon=4, tODT_idle_off=4
> + */
> +WRITE_ENTRY2(MMDC_P0_MDOTC, 0x09444040, 0x00333030)
> +
> +/*
> + * MDPDC - [17:16](2) => CKE pulse width = 3 cycles.
> + * [15:12](5) => PWDT_1 = 256 cycles
> + * [11:8](5) =>PWDR_0 = 256 cycles
> + * MX6Q: [2:0](6) => CKSRE = 6 cycles, [5:3](6) => CKSRX = 6 cycles
> + * MX6DL/SOLO: [2:0](5) => CKSRE = 5 cycles, [5:3](5) => CKSRX = 5 cycles
> + */
> +WRITE_ENTRY2(MMDC_P0_MDPDC, 0x00025576, 0x0002556D)
> +
> +/*
> + * MX6Q/DL - 64 bit wide ddr
> * last address is (1<<28 (base) + 1<<30 - 1) / (1<<25) =
> * 1<<3 + 1<<5 - 1 = 8 + 0x20 -1 = 0x27
> */
> +/*
> + * MX6SOLO - 32 bit wide ddr
> + * last address is (1<<28 (base) + 1<<29 - 1) / (1<<25) =
> + * 1<<3 + 1<<4 - 1 = 8 + 0x10 -1 = 0x17
> + */
> /* MDASP, CS0_END */
> -WRITE_ENTRY1(MMDC_P0_MDASP, 0x00000027)
> +WRITE_ENTRY3(MMDC_P0_MDASP, 0x00000027, 0x00000027, 0x00000017)
Is it unreasonable to think there's a use case for 32-bit wide
memory on a dual or quad?
What happens when we populate 256Mx16 DDR chips?
Sabre Auto is already doing this.
> /*
> - * MDCTL, CS0 enable, CS1 disabled, row=14, col=10, burst=8, width=64/32bit
> - * mx6q : row+col+bank+width=14+10+3+3=30 = 1G
> + * MDCTL, CS0 enable, CS1 disabled, row=14, col=10, burst=8
> + * MX6Q/DL: width=64bit row+col+bank+width=14+10+3+3=30 = 1G
> + * MX6SOLO: width=32bit row+col+bank+width=14+10+3+2=29 = 512M
> */
> -WRITE_ENTRY1(MMDC_P0_MDCTL, 0x831A0000)
> +WRITE_ENTRY3(MMDC_P0_MDCTL, 0x831A0000, 0x831A0000, 0x83190000)
>
> -/* MDSCR, con_req, LOAD MR2, CS0, A3,A10 set (CAS Write=6), RZQ/2 */
> -WRITE_ENTRY1(MMDC_P0_MDSCR, 0x04088032)
> +/*
> + * LOAD MR2: MDSCR, con_req, CS0, A10 set - RZQ/2
> + * MX6Q: A3 set(CAS Write=6)
> + * MX6DL/SOLO: (CAS Write=5)
> + */
> +WRITE_ENTRY2(MMDC_P0_MDSCR, 0x04088032, 0x04008032)
> /* LOAD MR3, CS0 */
> WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00008033)
> -/* LOAD MR1, CS0, A1,A6 set Rtt=RZQ/2, ODI=RZQ/7 */
> -WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00428031)
> -/* LOAD MR0, CS0, A6,A8,A11 set CAS=8, WR=8, DLL reset */
> -WRITE_ENTRY1(MMDC_P0_MDSCR, 0x09408030)
> +
> +/*
> + * LOAD MR1, CS0
> + * MX6Q: A6 set: Rtt=RZQ/2, A1 set: ODI=RZQ/7
> + * MX6DL/SOLO: A2 set: Rtt=RZQ/4, ODI=RZQ/6
> + */
> +WRITE_ENTRY2(MMDC_P0_MDSCR, 0x00428031, 0x00048031)
> +
> +/* LOAD MR0, CS0 A8 set: DLL Reset
> + * MX6Q: A6 set: CAS=8 A11 set: WR=8
> + * MX6DL/SOLO: A4 set: CAS=5, A9,A10 set: WR=7
> + */
> +WRITE_ENTRY2(MMDC_P0_MDSCR, 0x09408030, 0x07208030)
>
> /* ZQ calibrate, CS0 */
> WRITE_ENTRY1(MMDC_P0_MDSCR, 0x04008040)
> @@ -173,18 +227,18 @@ WRITE_ENTRY1(MMDC_P0_MPODTCTRL, 0x00022227)
> WRITE_ENTRY1(MMDC_P1_MPODTCTRL, 0x00022227)
>
> /* MPDGCTRL0/1 DQS GATE*/
> -WRITE_ENTRY1(MMDC_P0_MPDGCTRL0, 0x434B0350)
> -WRITE_ENTRY1(MMDC_P0_MPDGCTRL1, 0x034C0359)
> -WRITE_ENTRY1(MMDC_P1_MPDGCTRL0, 0x434B0350)
> -WRITE_ENTRY1(MMDC_P1_MPDGCTRL1, 0x03650348)
> -WRITE_ENTRY1(MMDC_P0_MPRDDLCTL, 0x4436383B)
> -WRITE_ENTRY1(MMDC_P1_MPRDDLCTL, 0x39393341)
> -WRITE_ENTRY1(MMDC_P0_MPWRDLCTL, 0x35373933)
> -WRITE_ENTRY1(MMDC_P1_MPWRDLCTL, 0x48254A36)
> -WRITE_ENTRY1(MMDC_P0_MPWLDECTRL0, 0x001F001F)
> -WRITE_ENTRY1(MMDC_P0_MPWLDECTRL1, 0x001F001F)
> -WRITE_ENTRY1(MMDC_P1_MPWLDECTRL0, 0x00440044)
> -WRITE_ENTRY1(MMDC_P1_MPWLDECTRL1, 0x00440044)
> +WRITE_ENTRY2(MMDC_P0_MPDGCTRL0, 0x434B0350, 0x42350231)
> +WRITE_ENTRY2(MMDC_P0_MPDGCTRL1, 0x034C0359, 0x021A0218)
> +WRITE_ENTRY2(MMDC_P1_MPDGCTRL0, 0x434B0350, 0x42350231)
> +WRITE_ENTRY2(MMDC_P1_MPDGCTRL1, 0x03650348, 0x021A0218)
> +WRITE_ENTRY2(MMDC_P0_MPRDDLCTL, 0x4436383B, 0x4B4B4E49)
> +WRITE_ENTRY2(MMDC_P1_MPRDDLCTL, 0x39393341, 0x4B4B4E49)
> +WRITE_ENTRY2(MMDC_P0_MPWRDLCTL, 0x35373933, 0x3F3F3035)
> +WRITE_ENTRY2(MMDC_P1_MPWRDLCTL, 0x48254A36, 0x3F3F3035)
> +WRITE_ENTRY2(MMDC_P0_MPWLDECTRL0, 0x001F001F, 0x0040003C)
> +WRITE_ENTRY2(MMDC_P0_MPWLDECTRL1, 0x001F001F, 0x0032003E)
> +WRITE_ENTRY2(MMDC_P1_MPWLDECTRL0, 0x00440044, 0x0040003C)
> +WRITE_ENTRY2(MMDC_P1_MPWLDECTRL1, 0x00440044, 0x0032003E)
>
> /* MPMUR0 - Complete calibration by forced measurement */
> WRITE_ENTRY1(MMDC_P0_MPMUR0, 0x00000800)
It appears that only the memory configuration registers use
WRITE_ENTRY2 or WRITE_ENTRY3 macros, and if so, I'd much
rather see three separate files expressing the values, i.e.:
mx6q_4x_mt41j128.cfg
mx6dl_4x_mt41j128.cfg
mx6s_2x_mt41j128.cfg
I'm not certain the processor part of the name is the
right designator though. If I understand correctly,
the differences in values between 6q and 6dl are mostly
based on the memory speed.
Is that right?
It also seems valid that a board would want to use an
i.mx6quad with a lower memory bus speed.
If the address differences are taken care of by the
preprocessor, it seems that a set like this would
be more appropriate (and processor independent):
mx6_4x_mt41j128_1066.cfg
mx6_4x_mt41j128_800.cfg
mx6_2x_mt41j128_800.cfg
By splitting up the files, we can still check for
differences between them using 'diff', and it will
be easier to extend the set.
Note that meaningful diffs will require the use of
symbolic names rather than varying addresses for
registers.
It's also conceivable that calibration on a given
layout will require per-board tweaks, but that's
not clear at the moment.
You've clearly been through this in more detail than
I have. Please let me know your thoughts.
Regards,
Eric
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 17/32] imximage.cfg: run files through C preprocessor
2012-10-07 18:19 ` Eric Nelson
@ 2012-10-08 19:11 ` Troy Kisky
0 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-10-08 19:11 UTC (permalink / raw)
To: u-boot
On 10/7/2012 11:19 AM, Eric Nelson wrote:
> Hi Troy,
>
> On 10/03/2012 06:47 PM, Troy Kisky wrote:
>> The '#' used as comments in the files cause the preprocessor
>> trouble, so change to /* */.
>>
>> Signed-off-by: Troy Kisky<troy.kisky@boundarydevices.com>
>> ---
>> Makefile | 3 +-
>> board/esg/ima3-mx53/imximage.cfg | 120 ++++++-----
>> board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 90 ++++----
>> board/freescale/mx25pdk/imximage.cfg | 77 +++----
>> board/freescale/mx51evk/imximage.cfg | 114 +++++-----
>> board/freescale/mx53ard/imximage_dd3.cfg | 83 ++++----
>> board/freescale/mx53evk/imximage.cfg | 86 ++++----
>> board/freescale/mx53loco/imximage.cfg | 83 ++++----
>> board/freescale/mx53smd/imximage.cfg | 83 ++++----
>> board/freescale/mx6qarm2/imximage.cfg | 88 ++++----
>> board/genesi/mx51_efikamx/imximage_mx.cfg | 132 ++++++------
>> board/genesi/mx51_efikamx/imximage_sb.cfg | 126 +++++------
>> board/ttcontrol/vision2/imximage_hynix.cfg | 295
>> ++++++++++++++------------
>> 13 files changed, 727 insertions(+), 653 deletions(-)
>>
>> diff --git a/Makefile b/Makefile
>> index a40d4cc..64ff1b8 100644
>> --- a/Makefile
>> +++ b/Makefile
>> @@ -431,7 +431,8 @@ $(obj)u-boot.img: $(obj)u-boot.bin
>> -d $< $@
>>
>> $(obj)u-boot.imx: $(obj)u-boot.bin
>> - $(obj)tools/mkimage -n $(CONFIG_IMX_CONFIG) -T imximage \
>> + $(CC) -E -x c $(CONFIG_IMX_CONFIG) -I./include -o
>> $(obj)imxcfg.imx
>> + $(obj)tools/mkimage -n $(obj)imxcfg.imx -T imximage \
>> -e $(CONFIG_SYS_TEXT_BASE) -d $< $@
>
> This bit creates imxcfg.imx.
>
> If built in-tree, the file will be reported as a new file in 'git
> status'.
> Is there a reason it can't be deleted after the build?
>
Just being able to look at it to see that the output makes sense.
I should make sure that make clean, deletes it, but I kinda like being
able to look at it after a make all.
Is an entry in gitignore ok?
Is everyone OK was the file name imxcfg.imx, or should some other
extension be used?
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 28/32] mx6q_4x_mt41j128.cfg: add mx6 solo/duallite support
2012-10-08 18:46 ` Eric Nelson
@ 2012-10-08 21:08 ` Troy Kisky
0 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-10-08 21:08 UTC (permalink / raw)
To: u-boot
On 10/8/2012 11:46 AM, Eric Nelson wrote:
> Hi Troy,
>
> This seems to be the patch where the rubber meets the road in
> much of this series.
>
> On 10/03/2012 06:47 PM, Troy Kisky wrote:
>> Signed-off-by: Troy Kisky<troy.kisky@boundarydevices.com>
>> ---
>> board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 120
>> +++++++++++++++++++-------
>> 1 file changed, 87 insertions(+), 33 deletions(-)
>>
>> diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
>> b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
>> index 9e20db0..f45f93e 100644
>> --- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
>> +++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
>> @@ -49,6 +49,15 @@ BOOT_FROM sd
>> * Address absolute address of the register
>> * value value to be stored in the register
>> */
>> +/*
>> + * DDR3 settings
>> + * MX6Q ddr is limited to 1066 Mhz, currently 1056 MHz(528 MHz
>> clock),
>> + * memory bus width: 64 bits, x16/x32/x64
>> + * MX6DL ddr is limited to 800 MHz(400 MHz clock)
>> + * memory bus width: 64 bits, x16/x32/x64
>> + * MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
>> + * memory bus width: 32 bits, x16/x32
>> + */
>
> This comment seems to be critical to understanding some of
> what's below, since now three **different** memory configurations
> are represented in this file.
>
> At a minimum, the file name should be changed to get rid of
> '6q' and '4x' since those don't necessarily apply.
Right, my preference is to put at back in
board/freescale/mx6qsabrelite/imximage.cfg
since MPDGCTRL0/1 DQS GATE registers and MMDC_MPRDDQBYnDL should be very
board specific,
but that may be meet by objections from Fabio.
>
>> WRITE_ENTRY1(IOM_DRAM_SDQS0, 0x00000030)
>> WRITE_ENTRY1(IOM_DRAM_SDQS1, 0x00000030)
>> WRITE_ENTRY1(IOM_DRAM_SDQS2, 0x00000030)
>> @@ -90,6 +99,7 @@ WRITE_ENTRY1(IOM_GRP_B6DS, 0x00000030)
>> WRITE_ENTRY1(IOM_GRP_B7DS, 0x00000030)
>>
>> WRITE_ENTRY1(IOM_GRP_ADDDS, 0x00000030)
>> +
>> /* (differential input) */
>> WRITE_ENTRY1(IOM_DDRMODE_CTL, 0x00020000)
>> /* disable ddr pullups */
>> @@ -119,48 +129,92 @@ WRITE_ENTRY1(MMDC_P0_MDMISC, 0x00081740)
>> * MDSCR, con_req
>> */
>> WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00008000)
>> +
>> /*
>> - * MDCFG0, tRFC=0x56 clocks, tXS=0x5b clocks
>> - * tXP=4 clocks, tXPDLL=13 clocks
>> - * tFAW=24 clocks, cas=8 cycles
>> + * MDCFG0,
>> + * MX6Q:
>> + * tRFC=0x56 clocks, tXS=0x5b clocks, tXP=4 clocks, tXPDLL=13 clocks
>> + * tFAW=24 clocks, cas=8 cycles
>> + * MX6DL/SOLO:
>> + * tRFC=0x6a clocks, tXS=0x6e clocks, tXP=3 clocks, tXPDLL=10 clocks
>> + * tFAW=19 clocks, cas=6 cycles
>> */
>> -WRITE_ENTRY1(MMDC_P0_MDCFG0, 0x555A7975)
>> +WRITE_ENTRY2(MMDC_P0_MDCFG0, 0x555A7975, 0x696D5323)
>> +
>
> Here's where I start to get lost in the macro-fu.
>
> The WRITE_ENTRY1 macros make some sense to me in that they
> always write a single value to an offset whose address
> changes based on the processor type.
>
> In order to understand WRITE_ENTRY2, you really have to
> know that the dual, solo, and sololite share many
> characteristics.
RIght, ENTRY2 is used when there are differences between
mx6q, and mx6dl/solo. In the case above, the value
0x555A7975 is written if a mx6quad, and the value 0x696D5323
is written if a mx6duallite or mx6solo.
>
> It's kinda hard to infer that knowledge from the code
> and I wonder if this structure will hold up under future
> revisions.
>
>> /*
>> - * MDCFG1, tRDC=8, tRP=8, tRC=27,tRAS=20,tRPA=tRP+1,tWR=8
>> - * tMRD=4, tCWL=6
>> + * MDCFG1,
>> + * MX6Q:
>> + * tRDC=8, tRP=8, tRC=27, tRAS=20, tRPA=tRP+1, tWR=8, tMRD=4, tCWL=6
>> + * MX6DL/SOLO:
>> + * tRDC=6, tRP=6, tRC=20, tRAS=15, tRPA=tRP+1, tWR=7, tMRD=4, tCWL=5
>> */
>> -WRITE_ENTRY1(MMDC_P0_MDCFG1, 0xFF538E64)
>> +WRITE_ENTRY2(MMDC_P0_MDCFG1, 0xFF538E64, 0xB66E8C63)
>> +
>> /*
>> * MDCFG2,tDLLK=512,tRTP=4,tWTR=4,tRRD=4
>> */
>> WRITE_ENTRY1(MMDC_P0_MDCFG2, 0x01FF00DB)
>> WRITE_ENTRY1(MMDC_P0_MDRWD, 0x000026D2)
>> -
>> WRITE_ENTRY1(MMDC_P0_MDOR, 0x005B0E21)
>> -WRITE_ENTRY1(MMDC_P0_MDOTC, 0x09444040)
>> -WRITE_ENTRY1(MMDC_P0_MDPDC, 0x00025576)
>>
>> /*
>> - * Mx6Q - 64 bit wide ddr
>> + * MMDC_MDOTC,
>> + * MX6Q:
>> + * tAOFPD=2 cycles, tAONPD=2, tANPD=5, tAXPD=5, tODTLon=5,
>> tODT_idle_off=5
>> + * MX6DL/SOLO:
>> + * tAOFPD=1 cycles, tAONPD=1, tANPD=4, tAXPD=4, tODTLon=4,
>> tODT_idle_off=4
>> + */
>> +WRITE_ENTRY2(MMDC_P0_MDOTC, 0x09444040, 0x00333030)
>> +
>> +/*
>> + * MDPDC - [17:16](2) => CKE pulse width = 3 cycles.
>> + * [15:12](5) => PWDT_1 = 256 cycles
>> + * [11:8](5) =>PWDR_0 = 256 cycles
>> + * MX6Q: [2:0](6) => CKSRE = 6 cycles, [5:3](6) => CKSRX = 6
>> cycles
>> + * MX6DL/SOLO: [2:0](5) => CKSRE = 5 cycles, [5:3](5) => CKSRX = 5
>> cycles
>> + */
>> +WRITE_ENTRY2(MMDC_P0_MDPDC, 0x00025576, 0x0002556D)
>> +
>> +/*
>> + * MX6Q/DL - 64 bit wide ddr
>> * last address is (1<<28 (base) + 1<<30 - 1) / (1<<25) =
>> * 1<<3 + 1<<5 - 1 = 8 + 0x20 -1 = 0x27
>> */
>> +/*
>> + * MX6SOLO - 32 bit wide ddr
>> + * last address is (1<<28 (base) + 1<<29 - 1) / (1<<25) =
>> + * 1<<3 + 1<<4 - 1 = 8 + 0x10 -1 = 0x17
>> + */
>> /* MDASP, CS0_END */
>> -WRITE_ENTRY1(MMDC_P0_MDASP, 0x00000027)
>> +WRITE_ENTRY3(MMDC_P0_MDASP, 0x00000027, 0x00000027, 0x00000017)
>
> Is it unreasonable to think there's a use case for 32-bit wide
> memory on a dual or quad?
Sure, they just would not use this file.
>
> What happens when we populate 256Mx16 DDR chips?
>
> Sabre Auto is already doing this.
Again, definitely a new file would be needed.
>
>> /*
>> - * MDCTL, CS0 enable, CS1 disabled, row=14, col=10, burst=8,
>> width=64/32bit
>> - * mx6q : row+col+bank+width=14+10+3+3=30 = 1G
>> + * MDCTL, CS0 enable, CS1 disabled, row=14, col=10, burst=8
>> + * MX6Q/DL: width=64bit row+col+bank+width=14+10+3+3=30 = 1G
>> + * MX6SOLO: width=32bit row+col+bank+width=14+10+3+2=29 = 512M
>> */
>> -WRITE_ENTRY1(MMDC_P0_MDCTL, 0x831A0000)
>> +WRITE_ENTRY3(MMDC_P0_MDCTL, 0x831A0000, 0x831A0000, 0x83190000)
>>
>> -/* MDSCR, con_req, LOAD MR2, CS0, A3,A10 set (CAS Write=6), RZQ/2 */
>> -WRITE_ENTRY1(MMDC_P0_MDSCR, 0x04088032)
>> +/*
>> + * LOAD MR2: MDSCR, con_req, CS0, A10 set - RZQ/2
>> + * MX6Q: A3 set(CAS Write=6)
>> + * MX6DL/SOLO: (CAS Write=5)
>> + */
>> +WRITE_ENTRY2(MMDC_P0_MDSCR, 0x04088032, 0x04008032)
>> /* LOAD MR3, CS0 */
>> WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00008033)
>> -/* LOAD MR1, CS0, A1,A6 set Rtt=RZQ/2, ODI=RZQ/7 */
>> -WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00428031)
>> -/* LOAD MR0, CS0, A6,A8,A11 set CAS=8, WR=8, DLL reset */
>> -WRITE_ENTRY1(MMDC_P0_MDSCR, 0x09408030)
>> +
>> +/*
>> + * LOAD MR1, CS0
>> + * MX6Q: A6 set: Rtt=RZQ/2, A1 set: ODI=RZQ/7
>> + * MX6DL/SOLO: A2 set: Rtt=RZQ/4, ODI=RZQ/6
>> + */
>> +WRITE_ENTRY2(MMDC_P0_MDSCR, 0x00428031, 0x00048031)
>> +
>> +/* LOAD MR0, CS0 A8 set: DLL Reset
>> + * MX6Q: A6 set: CAS=8 A11 set: WR=8
>> + * MX6DL/SOLO: A4 set: CAS=5, A9,A10 set: WR=7
>> + */
>> +WRITE_ENTRY2(MMDC_P0_MDSCR, 0x09408030, 0x07208030)
>>
>> /* ZQ calibrate, CS0 */
>> WRITE_ENTRY1(MMDC_P0_MDSCR, 0x04008040)
>> @@ -173,18 +227,18 @@ WRITE_ENTRY1(MMDC_P0_MPODTCTRL, 0x00022227)
>> WRITE_ENTRY1(MMDC_P1_MPODTCTRL, 0x00022227)
>>
>> /* MPDGCTRL0/1 DQS GATE*/
>> -WRITE_ENTRY1(MMDC_P0_MPDGCTRL0, 0x434B0350)
>> -WRITE_ENTRY1(MMDC_P0_MPDGCTRL1, 0x034C0359)
>> -WRITE_ENTRY1(MMDC_P1_MPDGCTRL0, 0x434B0350)
>> -WRITE_ENTRY1(MMDC_P1_MPDGCTRL1, 0x03650348)
>> -WRITE_ENTRY1(MMDC_P0_MPRDDLCTL, 0x4436383B)
>> -WRITE_ENTRY1(MMDC_P1_MPRDDLCTL, 0x39393341)
>> -WRITE_ENTRY1(MMDC_P0_MPWRDLCTL, 0x35373933)
>> -WRITE_ENTRY1(MMDC_P1_MPWRDLCTL, 0x48254A36)
>> -WRITE_ENTRY1(MMDC_P0_MPWLDECTRL0, 0x001F001F)
>> -WRITE_ENTRY1(MMDC_P0_MPWLDECTRL1, 0x001F001F)
>> -WRITE_ENTRY1(MMDC_P1_MPWLDECTRL0, 0x00440044)
>> -WRITE_ENTRY1(MMDC_P1_MPWLDECTRL1, 0x00440044)
>> +WRITE_ENTRY2(MMDC_P0_MPDGCTRL0, 0x434B0350, 0x42350231)
>> +WRITE_ENTRY2(MMDC_P0_MPDGCTRL1, 0x034C0359, 0x021A0218)
>> +WRITE_ENTRY2(MMDC_P1_MPDGCTRL0, 0x434B0350, 0x42350231)
>> +WRITE_ENTRY2(MMDC_P1_MPDGCTRL1, 0x03650348, 0x021A0218)
>> +WRITE_ENTRY2(MMDC_P0_MPRDDLCTL, 0x4436383B, 0x4B4B4E49)
>> +WRITE_ENTRY2(MMDC_P1_MPRDDLCTL, 0x39393341, 0x4B4B4E49)
>> +WRITE_ENTRY2(MMDC_P0_MPWRDLCTL, 0x35373933, 0x3F3F3035)
>> +WRITE_ENTRY2(MMDC_P1_MPWRDLCTL, 0x48254A36, 0x3F3F3035)
>> +WRITE_ENTRY2(MMDC_P0_MPWLDECTRL0, 0x001F001F, 0x0040003C)
>> +WRITE_ENTRY2(MMDC_P0_MPWLDECTRL1, 0x001F001F, 0x0032003E)
>> +WRITE_ENTRY2(MMDC_P1_MPWLDECTRL0, 0x00440044, 0x0040003C)
>> +WRITE_ENTRY2(MMDC_P1_MPWLDECTRL1, 0x00440044, 0x0032003E)
>>
>> /* MPMUR0 - Complete calibration by forced measurement */
>> WRITE_ENTRY1(MMDC_P0_MPMUR0, 0x00000800)
>
> It appears that only the memory configuration registers use
> WRITE_ENTRY2 or WRITE_ENTRY3 macros, and if so, I'd much
> rather see three separate files expressing the values, i.e.:
>
> mx6q_4x_mt41j128.cfg
> mx6dl_4x_mt41j128.cfg
> mx6s_2x_mt41j128.cfg
That is definitely a valid option. But you lose the common settings
of the iomux registers. Cut-n-pasting the files isn't so bad I guess,
but updates such as
mx6q_4x_mt41j128.cfg: use ddr3 mode for reset
Bits 19-18 of IOMUXC_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET
should be 3 for DDR3 mode. The current value of 0 is
reserved in TRM.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
index b859e2f..9c622c8 100644
--- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
@@ -72,7 +72,7 @@ WRITE_ENTRY1(IOM_DRAM_RAS, 0x00020030)
WRITE_ENTRY1(IOM_DRAM_SDCLK_0, 0x00020030)
WRITE_ENTRY1(IOM_DRAM_SDCLK_1, 0x00020030)
-WRITE_ENTRY1(IOM_DRAM_RESET, 0x00020030)
+WRITE_ENTRY1(IOM_DRAM_RESET, 0x000e0030)
WRITE_ENTRY1(IOM_DRAM_SDCKE0, 0x00003000)
WRITE_ENTRY1(IOM_DRAM_SDCKE1, 0x00003000)
WRITE_ENTRY1(IOM_DRAM_SDBA2, 0x00000000)
Would then need to be applied to all three files.
>
> I'm not certain the processor part of the name is the
> right designator though. If I understand correctly,
> the differences in values between 6q and 6dl are mostly
> based on the memory speed.
>
> Is that right?
Correct...
>
> It also seems valid that a board would want to use an
> i.mx6quad with a lower memory bus speed.
Especially if there is a layout problem.
>
> If the address differences are taken care of by the
> preprocessor, it seems that a set like this would
> be more appropriate (and processor independent):
>
> mx6_4x_mt41j128_1066.cfg
> mx6_4x_mt41j128_800.cfg
> mx6_2x_mt41j128_800.cfg
Right, this is definitely a valid option. And if different
boards calibrated their DDR to the same settings
(DQS and byte delays) it would make more sense.
But I still see this file as board specific and not so much
memory type specific.
>
> By splitting up the files, we can still check for
> differences between them using 'diff', and it will
> be easier to extend the set.
>
> Note that meaningful diffs will require the use of
> symbolic names rather than varying addresses for
> registers.
>
> It's also conceivable that calibration on a given
> layout will require per-board tweaks, but that's
> not clear at the moment.
>
> You've clearly been through this in more detail than
> I have. Please let me know your thoughts.
>
> Regards,
>
>
> Eric
>
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 25/32] imx-common: cpu: add imx_ddr_size
2012-10-08 13:06 ` Stefano Babic
@ 2012-10-08 21:35 ` Troy Kisky
0 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-10-08 21:35 UTC (permalink / raw)
To: u-boot
On 10/8/2012 6:06 AM, Stefano Babic wrote:
> On 04/10/2012 03:47, Troy Kisky wrote:
>> Read memory setup registers to determine size
>> of available ram. This routine works for mx53/mx6x
>>
>> I need this because when mx6solo called get_ram_size
>> with a too large maximum size, the system hanged.
>>
>> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
>>
> Hi Troy,
>
> I am interested to better understand why get_ram_size() does not work.
> It seems to me you discovered a bug in this function, and you circumvent
> it decoding the DRAM controller setup to get the RAM size.
>
> Because the max size is added to the start address in get_ram_size(), I
> have the feeling that this overwlow the long value, and maybe can be
> fixed swithcing to a "long long". With which parameters to
> get_ram_size() does your board hang ?
>
>
#define MMDC0_ARB_BASE_ADDR 0x10000000
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
So, base + size = 0x50000000
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 17/32] imximage.cfg: run files through C preprocessor
2012-10-08 13:38 ` Stefano Babic
@ 2012-10-08 21:48 ` Troy Kisky
2012-10-10 2:03 ` Troy Kisky
1 sibling, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-10-08 21:48 UTC (permalink / raw)
To: u-boot
On 10/8/2012 6:38 AM, Stefano Babic wrote:
> On 04/10/2012 03:47, Troy Kisky wrote:
>> The '#' used as comments in the files cause the preprocessor
>> trouble, so change to /* */.
>>
>> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
>> ---
> Hi Troy,
>
>> Makefile | 3 +-
>> board/esg/ima3-mx53/imximage.cfg | 120 ++++++-----
>> board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 90 ++++----
>> board/freescale/mx25pdk/imximage.cfg | 77 +++----
>> board/freescale/mx51evk/imximage.cfg | 114 +++++-----
>> board/freescale/mx53ard/imximage_dd3.cfg | 83 ++++----
>> board/freescale/mx53evk/imximage.cfg | 86 ++++----
>> board/freescale/mx53loco/imximage.cfg | 83 ++++----
>> board/freescale/mx53smd/imximage.cfg | 83 ++++----
>> board/freescale/mx6qarm2/imximage.cfg | 88 ++++----
>> board/genesi/mx51_efikamx/imximage_mx.cfg | 132 ++++++------
>> board/genesi/mx51_efikamx/imximage_sb.cfg | 126 +++++------
>> board/ttcontrol/vision2/imximage_hynix.cfg | 295 ++++++++++++++------------
>> 13 files changed, 727 insertions(+), 653 deletions(-)
>>
> I see the C preprocessor as an optional feature, instead of a rule
> everybody must follow.
>
>> diff --git a/Makefile b/Makefile
>> index a40d4cc..64ff1b8 100644
>> --- a/Makefile
>> +++ b/Makefile
>> @@ -431,7 +431,8 @@ $(obj)u-boot.img: $(obj)u-boot.bin
>> -d $< $@
>>
>> $(obj)u-boot.imx: $(obj)u-boot.bin
>> - $(obj)tools/mkimage -n $(CONFIG_IMX_CONFIG) -T imximage \
>> + $(CC) -E -x c $(CONFIG_IMX_CONFIG) -I./include -o $(obj)imxcfg.imx
>> + $(obj)tools/mkimage -n $(obj)imxcfg.imx -T imximage \
>> -e $(CONFIG_SYS_TEXT_BASE) -d $< $@
> In fact, adding this rule here requires that each board configuration
> must be changed. And for all of them, running the preprocessor is
> unnnecessary.
>
> What about to add this rule only to the Makefile of the boards that
> require preprocessing ?
>
> Best regards,
> Stefano Babic
>
That would be great. But I don't know how to accomplish that. Can you
point to similar magic that
I can try to understand?
Thanks
Troy
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 24/32] mx6: use CONFIG_MX6 instead of CONFIG_MX6Q
2012-10-08 13:41 ` Stefano Babic
@ 2012-10-08 21:49 ` Troy Kisky
0 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-10-08 21:49 UTC (permalink / raw)
To: u-boot
On 10/8/2012 6:41 AM, Stefano Babic wrote:
> On 04/10/2012 03:47, Troy Kisky wrote:
>> Use CONFIG_MX6 when the particular processor
>> variant isn't important.
>>
>> Reserve the use of CONFIG_MX6Q to
>> specifically test for quad cores variant.
>>
>> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
>> ---
>> drivers/gpio/mxc_gpio.c | 6 +++---
>> drivers/video/ipu_regs.h | 2 +-
>> include/configs/mx6qarm2.h | 1 +
>> include/configs/mx6qsabre_common.h | 1 +
>> include/configs/mx6qsabrelite.h | 1 +
>> 5 files changed, 7 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c
>> index 2c79bff..a388064 100644
>> --- a/drivers/gpio/mxc_gpio.c
>> +++ b/drivers/gpio/mxc_gpio.c
>> @@ -42,14 +42,14 @@ static unsigned long gpio_ports[] = {
>> [1] = GPIO2_BASE_ADDR,
>> [2] = GPIO3_BASE_ADDR,
>> #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
>> - defined(CONFIG_MX53) || defined(CONFIG_MX6Q)
>> + defined(CONFIG_MX53) || defined(CONFIG_MX6)
>> [3] = GPIO4_BASE_ADDR,
>> #endif
>> -#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6Q)
>> +#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6)
>> [4] = GPIO5_BASE_ADDR,
>> [5] = GPIO6_BASE_ADDR,
>> #endif
>> -#if defined(CONFIG_MX53) || defined(CONFIG_MX6Q)
>> +#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
>> [6] = GPIO7_BASE_ADDR,
>> #endif
>> };
>> diff --git a/drivers/video/ipu_regs.h b/drivers/video/ipu_regs.h
>> index a43aa03..982e252 100644
>> --- a/drivers/video/ipu_regs.h
>> +++ b/drivers/video/ipu_regs.h
>> @@ -55,7 +55,7 @@
>> #define IPU_TPM_REG_BASE 0x01060000
>> #define IPU_DC_TMPL_REG_BASE 0x01080000
>> #define IPU_ISP_TBPR_REG_BASE 0x010C0000
>> -#elif defined(CONFIG_MX6Q)
>> +#elif defined(CONFIG_MX6)
>> #define IPU_CPMEM_REG_BASE 0x00100000
>> #define IPU_LUT_REG_BASE 0x00120000
>> #define IPU_SRM_REG_BASE 0x00140000
>> diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h
>> index 965bea3..8e5b81e 100644
>> --- a/include/configs/mx6qarm2.h
>> +++ b/include/configs/mx6qarm2.h
>> @@ -22,6 +22,7 @@
>> #ifndef __CONFIG_H
>> #define __CONFIG_H
>>
>> +#define CONFIG_MX6
>> #define CONFIG_MX6Q
>> #define CONFIG_DISPLAY_CPUINFO
>> #define CONFIG_DISPLAY_BOARDINFO
>> diff --git a/include/configs/mx6qsabre_common.h b/include/configs/mx6qsabre_common.h
>> index 247e8d6..5a940da 100644
>> --- a/include/configs/mx6qsabre_common.h
>> +++ b/include/configs/mx6qsabre_common.h
>> @@ -17,6 +17,7 @@
>> #ifndef __MX6QSABRE_COMMON_CONFIG_H
>> #define __MX6QSABRE_COMMON_CONFIG_H
>>
>> +#define CONFIG_MX6
>> #define CONFIG_MX6Q
>> #define CONFIG_DISPLAY_CPUINFO
>> #define CONFIG_DISPLAY_BOARDINFO
>> diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
>> index e7bf658..6a10232 100644
>> --- a/include/configs/mx6qsabrelite.h
>> +++ b/include/configs/mx6qsabrelite.h
>> @@ -22,6 +22,7 @@
>> #ifndef __CONFIG_H
>> #define __CONFIG_H
>>
>> +#define CONFIG_MX6
>> #define CONFIG_MX6Q
>> #define CONFIG_DISPLAY_CPUINFO
>> #define CONFIG_DISPLAY_BOARDINFO
>>
> This changes affects also mx6qsabreauto and mx6qsabresd, that I have
> already merged.
>
> Best regards,
> Stefano Babic
They should be covered by
#include "mx6qsabre_common.h"
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 30/32] mx6qsabrelite: change CONFIG_SYS_PROMPT
2012-10-08 13:54 ` Stefano Babic
@ 2012-10-08 21:58 ` Troy Kisky
2012-10-08 22:05 ` Fabio Estevam
` (2 more replies)
0 siblings, 3 replies; 430+ messages in thread
From: Troy Kisky @ 2012-10-08 21:58 UTC (permalink / raw)
To: u-boot
On 10/8/2012 6:54 AM, Stefano Babic wrote:
> On 05/10/2012 01:28, Troy Kisky wrote:
>> On 10/3/2012 8:00 PM, Otavio Salvador wrote:
>>> On Wed, Oct 3, 2012 at 10:47 PM, Troy Kisky
>>> <troy.kisky@boundarydevices.com> wrote:
>>>> The prompt is not appropriate if not running on
>>>> a mx6q processor.
>>>>
>>>> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
>>> But in this case the board name will change, no?
>>>
>> No, patch 29/32 sets the new boards to use the same config file
>> (mx6qsabrelite.h) only adding ",MX6DL" or ",MX6S" or ",MX6Q"
>> to the end of the line in boards.cfg
> This means that CONFIG_MX6Dx is set. You can use it to set appropriately
> the prompt or use a more generic name including the board name, as
> "MX6SABRELITE U-Boot > ". The board is always the same, what is
I can live with "MX6SABRELITE U-Boot" but I prefer a plain "U-Boot".
The rest seems a waste of screen real estate. The long u-boot commands
are more likely to wrap. Anyone else have an opinion???
Thanks
Troy
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 30/32] mx6qsabrelite: change CONFIG_SYS_PROMPT
2012-10-08 21:58 ` Troy Kisky
@ 2012-10-08 22:05 ` Fabio Estevam
2012-10-08 22:18 ` stefano babic
2012-10-08 22:21 ` Eric Nelson
2 siblings, 0 replies; 430+ messages in thread
From: Fabio Estevam @ 2012-10-08 22:05 UTC (permalink / raw)
To: u-boot
On Mon, Oct 8, 2012 at 6:58 PM, Troy Kisky
<troy.kisky@boundarydevices.com> wrote:
> I can live with "MX6SABRELITE U-Boot" but I prefer a plain "U-Boot".
> The rest seems a waste of screen real estate. The long u-boot commands
> are more likely to wrap. Anyone else have an opinion???
Agreed.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 30/32] mx6qsabrelite: change CONFIG_SYS_PROMPT
2012-10-08 21:58 ` Troy Kisky
2012-10-08 22:05 ` Fabio Estevam
@ 2012-10-08 22:18 ` stefano babic
2012-10-08 22:22 ` Eric Nelson
2012-10-08 22:21 ` Eric Nelson
2 siblings, 1 reply; 430+ messages in thread
From: stefano babic @ 2012-10-08 22:18 UTC (permalink / raw)
To: u-boot
Am 08/10/2012 23:58, schrieb Troy Kisky:
> On 10/8/2012 6:54 AM, Stefano Babic wrote:
>> On 05/10/2012 01:28, Troy Kisky wrote:
>>> On 10/3/2012 8:00 PM, Otavio Salvador wrote:
>>>> On Wed, Oct 3, 2012 at 10:47 PM, Troy Kisky
>>>> <troy.kisky@boundarydevices.com> wrote:
>>>>> The prompt is not appropriate if not running on
>>>>> a mx6q processor.
>>>>>
>>>>> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
>>>> But in this case the board name will change, no?
>>>>
>>> No, patch 29/32 sets the new boards to use the same config file
>>> (mx6qsabrelite.h) only adding ",MX6DL" or ",MX6S" or ",MX6Q"
>>> to the end of the line in boards.cfg
>> This means that CONFIG_MX6Dx is set. You can use it to set appropriately
>> the prompt or use a more generic name including the board name, as
>> "MX6SABRELITE U-Boot > ". The board is always the same, what is
>
> I can live with "MX6SABRELITE U-Boot" but I prefer a plain "U-Boot".
> The rest seems a waste of screen real estate. The long u-boot commands
> are more likely to wrap.
Personally agree, shorter is better.
Regards,
Stefano
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 30/32] mx6qsabrelite: change CONFIG_SYS_PROMPT
2012-10-08 21:58 ` Troy Kisky
2012-10-08 22:05 ` Fabio Estevam
2012-10-08 22:18 ` stefano babic
@ 2012-10-08 22:21 ` Eric Nelson
2 siblings, 0 replies; 430+ messages in thread
From: Eric Nelson @ 2012-10-08 22:21 UTC (permalink / raw)
To: u-boot
On 10/08/2012 02:58 PM, Troy Kisky wrote:
> On 10/8/2012 6:54 AM, Stefano Babic wrote:
>> On 05/10/2012 01:28, Troy Kisky wrote:
>>> On 10/3/2012 8:00 PM, Otavio Salvador wrote:
>>>> On Wed, Oct 3, 2012 at 10:47 PM, Troy Kisky
>>>> <troy.kisky@boundarydevices.com> wrote:
>>>>> The prompt is not appropriate if not running on
>>>>> a mx6q processor.
>>>>>
>>>>> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
>>>> But in this case the board name will change, no?
>>>>
>>> No, patch 29/32 sets the new boards to use the same config file
>>> (mx6qsabrelite.h) only adding ",MX6DL" or ",MX6S" or ",MX6Q"
>>> to the end of the line in boards.cfg
>> This means that CONFIG_MX6Dx is set. You can use it to set appropriately
>> the prompt or use a more generic name including the board name, as
>> "MX6SABRELITE U-Boot > ". The board is always the same, what is
>
> I can live with "MX6SABRELITE U-Boot" but I prefer a plain "U-Boot".
> The rest seems a waste of screen real estate. The long u-boot commands
> are more likely to wrap. Anyone else have an opinion???
>
I'm with you, for selfish reasons.
When I write up instructions like these, things tend to wrap
with the longer prompt (so I usually hand-edit them):
http://boundarydevices.com/configuring-i-mx6-machines-different-screens-nitrogen6x-sabre-lite/#timesys
The marketing value of MX6SABRELITE is pretty small when someone as one on
their desk.
Regards,
Eric
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 30/32] mx6qsabrelite: change CONFIG_SYS_PROMPT
2012-10-08 22:18 ` stefano babic
@ 2012-10-08 22:22 ` Eric Nelson
0 siblings, 0 replies; 430+ messages in thread
From: Eric Nelson @ 2012-10-08 22:22 UTC (permalink / raw)
To: u-boot
On 10/08/2012 03:18 PM, stefano babic wrote:
> Am 08/10/2012 23:58, schrieb Troy Kisky:
>> On 10/8/2012 6:54 AM, Stefano Babic wrote:
>>> On 05/10/2012 01:28, Troy Kisky wrote:
>>>> On 10/3/2012 8:00 PM, Otavio Salvador wrote:
>>>>> On Wed, Oct 3, 2012 at 10:47 PM, Troy Kisky
>>>>> <troy.kisky@boundarydevices.com> wrote:
>>>>>> The prompt is not appropriate if not running on
>>>>>> a mx6q processor.
>>>>>>
>>>>>> Signed-off-by: Troy Kisky<troy.kisky@boundarydevices.com>
>>>>> But in this case the board name will change, no?
>>>>>
>>>> No, patch 29/32 sets the new boards to use the same config file
>>>> (mx6qsabrelite.h) only adding ",MX6DL" or ",MX6S" or ",MX6Q"
>>>> to the end of the line in boards.cfg
>>> This means that CONFIG_MX6Dx is set. You can use it to set appropriately
>>> the prompt or use a more generic name including the board name, as
>>> "MX6SABRELITE U-Boot> ". The board is always the same, what is
>>
>> I can live with "MX6SABRELITE U-Boot" but I prefer a plain "U-Boot".
>> The rest seems a waste of screen real estate. The long u-boot commands
>> are more likely to wrap.
>
> Personally agree, shorter is better.
>
Shh! Nobody tell the marketing folks!
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 00/32] Add mx6solo/mx6duallite support
2012-10-08 13:15 ` Stefano Babic
@ 2012-10-08 23:58 ` Troy Kisky
0 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-10-08 23:58 UTC (permalink / raw)
To: u-boot
On 10/8/2012 6:15 AM, Stefano Babic wrote:
> On 04/10/2012 03:47, Troy Kisky wrote:
>> This series goal is to add support for mx6solo and mx6duallite
>> variants of mx6qsabrelite board. The new targets are
>> called mx6ssabrelite and mx6dlsabrelite.
>>
>> The 1st 16 patches perform cleanup on imximage
> Hi Troy,
>
> I have some difficulties to understand which are the dependencies of
> this patchset. IMHO there are very different topics here, and some
> patches can be applied independently from the other one.
> imximage patches. For example, why "add mx6dl_pins" belong to imximage
> patchset ? It is surely easier to split for each topic, so that each
> patcheset can be applied independently if on a different topic there is
> still an open issue.
>
>
> I see at least:
> - imximage fixes: they are really fix and can be applied soon.
> - imximage new features
> - mx6 patches
>
> It is surely easier if you split your changes in separate patchset, as
> they covered different topics.
>
> Best regards,
> Stefano Babic
>
Yes, Eric made the same comment. I'll split the next version up.
Thanks
Troy
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 17/32] imximage.cfg: run files through C preprocessor
2012-10-08 13:38 ` Stefano Babic
2012-10-08 21:48 ` Troy Kisky
@ 2012-10-10 2:03 ` Troy Kisky
2012-10-11 11:11 ` Stefano Babic
1 sibling, 1 reply; 430+ messages in thread
From: Troy Kisky @ 2012-10-10 2:03 UTC (permalink / raw)
To: u-boot
On 10/8/2012 6:38 AM, Stefano Babic wrote:
> On 04/10/2012 03:47, Troy Kisky wrote:
>> The '#' used as comments in the files cause the preprocessor
>> trouble, so change to /* */.
>>
>> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
>> ---
> Hi Troy,
>
>> Makefile | 3 +-
>> board/esg/ima3-mx53/imximage.cfg | 120 ++++++-----
>> board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 90 ++++----
>> board/freescale/mx25pdk/imximage.cfg | 77 +++----
>> board/freescale/mx51evk/imximage.cfg | 114 +++++-----
>> board/freescale/mx53ard/imximage_dd3.cfg | 83 ++++----
>> board/freescale/mx53evk/imximage.cfg | 86 ++++----
>> board/freescale/mx53loco/imximage.cfg | 83 ++++----
>> board/freescale/mx53smd/imximage.cfg | 83 ++++----
>> board/freescale/mx6qarm2/imximage.cfg | 88 ++++----
>> board/genesi/mx51_efikamx/imximage_mx.cfg | 132 ++++++------
>> board/genesi/mx51_efikamx/imximage_sb.cfg | 126 +++++------
>> board/ttcontrol/vision2/imximage_hynix.cfg | 295 ++++++++++++++------------
>> 13 files changed, 727 insertions(+), 653 deletions(-)
>>
> I see the C preprocessor as an optional feature, instead of a rule
> everybody must follow.
>
>> diff --git a/Makefile b/Makefile
>> index a40d4cc..64ff1b8 100644
>> --- a/Makefile
>> +++ b/Makefile
>> @@ -431,7 +431,8 @@ $(obj)u-boot.img: $(obj)u-boot.bin
>> -d $< $@
>>
>> $(obj)u-boot.imx: $(obj)u-boot.bin
>> - $(obj)tools/mkimage -n $(CONFIG_IMX_CONFIG) -T imximage \
>> + $(CC) -E -x c $(CONFIG_IMX_CONFIG) -I./include -o $(obj)imxcfg.imx
>> + $(obj)tools/mkimage -n $(obj)imxcfg.imx -T imximage \
>> -e $(CONFIG_SYS_TEXT_BASE) -d $< $@
> In fact, adding this rule here requires that each board configuration
> must be changed. And for all of them, running the preprocessor is
> unnnecessary.
>
> What about to add this rule only to the Makefile of the boards that
> require preprocessing ?
>
> Best regards,
> Stefano Babic
>
How about this to do the job....
Subject: [PATCH 17/32] boards.cfg: run mx6q_4x_mt41j128.pcfg through C
preprocessor
The '#' used as comments in the cfg file cause the preprocessor
trouble, so change to /* */. Also, rename mx6q_4x_mt41j128.cfg
to mx6q_4x_mt41j128.pcfg.
Files with extension of .pcfg are run through the preprocessor
before being given to mkimage.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
v4: Don't run every file through preprocessor, only .pcfg files
---
.gitignore | 1 +
Makefile | 16 +++-
...{mx6q_4x_mt41j128.cfg => mx6q_4x_mt41j128.pcfg} | 90
++++++++++----------
boards.cfg | 4 +-
4 files changed, 63 insertions(+), 48 deletions(-)
rename board/freescale/imx/ddr/{mx6q_4x_mt41j128.cfg =>
mx6q_4x_mt41j128.pcfg} (65%)
diff --git a/.gitignore b/.gitignore
index d91e91b..e5273bd 100644
--- a/.gitignore
+++ b/.gitignore
@@ -15,6 +15,7 @@
*.swp
*.patch
*.bin
+*.pcfgtmp
# Build tree
/build-*
diff --git a/Makefile b/Makefile
index a40d4cc..99666b9 100644
--- a/Makefile
+++ b/Makefile
@@ -430,8 +430,17 @@ $(obj)u-boot.img: $(obj)u-boot.bin
sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \
-d $< $@
-$(obj)u-boot.imx: $(obj)u-boot.bin
- $(obj)tools/mkimage -n $(CONFIG_IMX_CONFIG) -T imximage \
+ifeq ($(suffix $(patsubst "%",%,$(CONFIG_IMX_CONFIG))),.pcfg)
+$(obj)$(patsubst "%",%,$(CONFIG_IMX_CONFIG))tmp: %.pcfgtmp : %.pcfg
+ $(CC) -E -x c $< -I./include -o $@
+
+$(obj)u-boot.imx: %.imx : %.bin $(obj)$(patsubst
"%",%,$(CONFIG_IMX_CONFIG))tmp
+else
+$(obj)u-boot.imx: %.imx : %.bin $(patsubst "%",%,$(CONFIG_IMX_CONFIG))
+endif
+
+$(obj)u-boot.imx:
+ $(obj)tools/mkimage -n $(filter-out %.bin,$^) -T imximage \
-e $(CONFIG_SYS_TEXT_BASE) -d $< $@
$(obj)u-boot.kwb: $(obj)u-boot.bin
@@ -794,7 +803,8 @@ clean:
@rm -f $(TIMESTAMP_FILE) $(VERSION_FILE)
@find $(OBJTREE) -type f \
\( -name 'core' -o -name '*.bak' -o -name '*~' -o -name
'*.su' \
- -o -name '*.o' -o -name '*.a' -o -name '*.exe' \) -print \
+ -o -name '*.o' -o -name '*.a' -o -name '*.exe' \
+ -o -name '*.pcfgtmp' \) -print \
| xargs rm -f
# Removes everything not needed for testing u-boot
diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
b/board/freescale/imx/ddr/mx6q_4x_mt41j128.pcfg
similarity index 65%
rename from board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
rename to board/freescale/imx/ddr/mx6q_4x_mt41j128.pcfg
diff --git a/boards.cfg b/boards.cfg
index e9e073e..677beac 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -232,8 +232,8 @@ ima3-mx53 arm armv7
ima3-mx53 esg
vision2 arm armv7 vision2
ttcontrol mx5 vision2:IMX_CONFIG=board/ttcontrol/vision2/imx
image_hynix.cfg
mx6qarm2 arm armv7 mx6qarm2
freescale mx6 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/i
mximage.cfg
mx6qsabreauto arm armv7 mx6qsabreauto
freescale mx6 mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qs
abreauto/imximage.cfg
-mx6qsabrelite arm armv7 mx6qsabrelite
freescale mx6 mx6qsabrelite:IMX_CONFIG=board/freescale/imx/d
dr/mx6q_4x_mt41j128.cfg
-mx6qsabresd arm armv7 mx6qsabresd
freescale mx6 mx6qsabresd:IMX_CONFIG=board/freescale/imx/ddr
/mx6q_4x_mt41j128.cfg
+mx6qsabrelite arm armv7 mx6qsabrelite
freescale mx6 mx6qsabrelite:IMX_CONFIG=board/freescale/imx/d
dr/mx6q_4x_mt41j128.pcfg
+mx6qsabresd arm armv7 mx6qsabresd
freescale mx6 mx6qsabresd:IMX_CONFIG=board/freescale/imx/ddr
/mx6q_4x_mt41j128.pcfg
cm_t35 arm armv7 cm_t35
- omap3
omap3_overo arm armv7 overo
- omap3
omap3_pandora arm armv7 pandora
- omap3
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 17/32] imximage.cfg: run files through C preprocessor
2012-10-10 2:03 ` Troy Kisky
@ 2012-10-11 11:11 ` Stefano Babic
2012-10-11 20:33 ` Troy Kisky
0 siblings, 1 reply; 430+ messages in thread
From: Stefano Babic @ 2012-10-11 11:11 UTC (permalink / raw)
To: u-boot
Am 10/10/2012 04:03, schrieb Troy Kisky:
> On 10/8/2012 6:38 AM, Stefano Babic wrote:
>> On 04/10/2012 03:47, Troy Kisky wrote:
>>> The '#' used as comments in the files cause the preprocessor
>>> trouble, so change to /* */.
>>>
>>> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
>>> ---
>> Hi Troy,
>>
>>> Makefile | 3 +-
>>> board/esg/ima3-mx53/imximage.cfg | 120 ++++++-----
>>> board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 90 ++++----
>>> board/freescale/mx25pdk/imximage.cfg | 77 +++----
>>> board/freescale/mx51evk/imximage.cfg | 114 +++++-----
>>> board/freescale/mx53ard/imximage_dd3.cfg | 83 ++++----
>>> board/freescale/mx53evk/imximage.cfg | 86 ++++----
>>> board/freescale/mx53loco/imximage.cfg | 83 ++++----
>>> board/freescale/mx53smd/imximage.cfg | 83 ++++----
>>> board/freescale/mx6qarm2/imximage.cfg | 88 ++++----
>>> board/genesi/mx51_efikamx/imximage_mx.cfg | 132 ++++++------
>>> board/genesi/mx51_efikamx/imximage_sb.cfg | 126 +++++------
>>> board/ttcontrol/vision2/imximage_hynix.cfg | 295
>>> ++++++++++++++------------
>>> 13 files changed, 727 insertions(+), 653 deletions(-)
>>>
>> I see the C preprocessor as an optional feature, instead of a rule
>> everybody must follow.
>>
>>> diff --git a/Makefile b/Makefile
>>> index a40d4cc..64ff1b8 100644
>>> --- a/Makefile
>>> +++ b/Makefile
>>> @@ -431,7 +431,8 @@ $(obj)u-boot.img: $(obj)u-boot.bin
>>> -d $< $@
>>> $(obj)u-boot.imx: $(obj)u-boot.bin
>>> - $(obj)tools/mkimage -n $(CONFIG_IMX_CONFIG) -T imximage \
>>> + $(CC) -E -x c $(CONFIG_IMX_CONFIG) -I./include -o
>>> $(obj)imxcfg.imx
>>> + $(obj)tools/mkimage -n $(obj)imxcfg.imx -T imximage \
>>> -e $(CONFIG_SYS_TEXT_BASE) -d $< $@
>> In fact, adding this rule here requires that each board configuration
>> must be changed. And for all of them, running the preprocessor is
>> unnnecessary.
>>
>> What about to add this rule only to the Makefile of the boards that
>> require preprocessing ?
>>
>> Best regards,
>> Stefano Babic
>>
> How about this to do the job....
>
>
>
>
>
> Subject: [PATCH 17/32] boards.cfg: run mx6q_4x_mt41j128.pcfg through C
> preprocessor
>
> The '#' used as comments in the cfg file cause the preprocessor
> trouble, so change to /* */. Also, rename mx6q_4x_mt41j128.cfg
> to mx6q_4x_mt41j128.pcfg.
>
> Files with extension of .pcfg are run through the preprocessor
> before being given to mkimage.
>
> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
>
> ---
> v4: Don't run every file through preprocessor, only .pcfg files
> ---
> .gitignore | 1 +
> Makefile | 16 +++-
> ...{mx6q_4x_mt41j128.cfg => mx6q_4x_mt41j128.pcfg} | 90
> ++++++++++----------
> boards.cfg | 4 +-
> 4 files changed, 63 insertions(+), 48 deletions(-)
> rename board/freescale/imx/ddr/{mx6q_4x_mt41j128.cfg =>
> mx6q_4x_mt41j128.pcfg} (65%)
>
> diff --git a/.gitignore b/.gitignore
> index d91e91b..e5273bd 100644
> --- a/.gitignore
> +++ b/.gitignore
> @@ -15,6 +15,7 @@
> *.swp
> *.patch
> *.bin
> +*.pcfgtmp
>
> # Build tree
> /build-*
> diff --git a/Makefile b/Makefile
> index a40d4cc..99666b9 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -430,8 +430,17 @@ $(obj)u-boot.img: $(obj)u-boot.bin
> sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \
> -d $< $@
>
> -$(obj)u-boot.imx: $(obj)u-boot.bin
> - $(obj)tools/mkimage -n $(CONFIG_IMX_CONFIG) -T imximage \
> +ifeq ($(suffix $(patsubst "%",%,$(CONFIG_IMX_CONFIG))),.pcfg)
> +$(obj)$(patsubst "%",%,$(CONFIG_IMX_CONFIG))tmp: %.pcfgtmp : %.pcfg
> + $(CC) -E -x c $< -I./include -o $@
> +
> +$(obj)u-boot.imx: %.imx : %.bin $(obj)$(patsubst
> "%",%,$(CONFIG_IMX_CONFIG))tmp
> +else
> +$(obj)u-boot.imx: %.imx : %.bin $(patsubst "%",%,$(CONFIG_IMX_CONFIG))
> +endif
> +
> +$(obj)u-boot.imx:
> + $(obj)tools/mkimage -n $(filter-out %.bin,$^) -T
> imximage \
> -e $(CONFIG_SYS_TEXT_BASE) -d $< $@
>
Does it work something more direct (I have not tested, really...) ?
In board Makefile, for example board/freescale/mx6qsabrelite, a rule for
the imximage file:
$(CONFIG_IMX_CONFIG): <your base file, mx6q_4x_mt41j128.cfg maybe>
$(CC) -E -x c $< -I./include -o $@
And let unchanged in the main Makefile. So CONFIG_IMX_CONFIG is produced
and you do not need to change logic in the main Makefile.
Regards,
Stefano
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 17/32] imximage.cfg: run files through C preprocessor
2012-10-11 11:11 ` Stefano Babic
@ 2012-10-11 20:33 ` Troy Kisky
2012-10-11 22:27 ` stefano babic
0 siblings, 1 reply; 430+ messages in thread
From: Troy Kisky @ 2012-10-11 20:33 UTC (permalink / raw)
To: u-boot
On 10/11/2012 4:11 AM, Stefano Babic wrote:
> Does it work something more direct (I have not tested, really...) ?
>
> In board Makefile, for example board/freescale/mx6qsabrelite, a rule for
> the imximage file:
>
> $(CONFIG_IMX_CONFIG): <your base file, mx6q_4x_mt41j128.cfg maybe>
> $(CC) -E -x c $< -I./include -o $@
>
> And let unchanged in the main Makefile. So CONFIG_IMX_CONFIG is produced
> and you do not need to change logic in the main Makefile.
>
> Regards,
> Stefano
>
The advantages I see of changing the main Makefile are
1. Easy for other boards to use the preprocessor. You merely
need to change the file extension to pcfg.
2. Easy to clean the temporary generated file. The main Makefile
deletes files with .pcfgtmp extension.
3. The file referred to by boards.cfg actually exists before the build
starts.
4. The temporary file can be placed in an out-of-tree directory for
make -O builds
Using the file extension to determine whether to use the preprocessor is
also
what gcc uses to preprocess ".S" files while skipping this for ".s" files.
I believe that at least other mx6 boards will quickly change to using
the preprocessor
as well to add support for solo/duallite, so total line count should
eventually be
less with changes to the main makefile.
Having said that, I really have no problem going your route, I just
don't prefer it.
Let me know.
Thanks
Troy
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 17/32] imximage.cfg: run files through C preprocessor
2012-10-11 20:33 ` Troy Kisky
@ 2012-10-11 22:27 ` stefano babic
2012-10-11 23:15 ` Tom Rini
0 siblings, 1 reply; 430+ messages in thread
From: stefano babic @ 2012-10-11 22:27 UTC (permalink / raw)
To: u-boot
Am 11/10/2012 22:33, schrieb Troy Kisky:
> On 10/11/2012 4:11 AM, Stefano Babic wrote:
>> Does it work something more direct (I have not tested, really...) ?
>>
>> In board Makefile, for example board/freescale/mx6qsabrelite, a rule for
>> the imximage file:
>>
>> $(CONFIG_IMX_CONFIG): <your base file, mx6q_4x_mt41j128.cfg maybe>
>> $(CC) -E -x c $< -I./include -o $@
>>
>> And let unchanged in the main Makefile. So CONFIG_IMX_CONFIG is produced
>> and you do not need to change logic in the main Makefile.
>>
>> Regards,
>> Stefano
>>
>
> The advantages I see of changing the main Makefile are
> 1. Easy for other boards to use the preprocessor. You merely
> need to change the file extension to pcfg.
I set Tom in CC, because changing the main Makefile is more related to
the whole project, and not only for the i.MX.
One reason to move into the board directory is that there was a decision
to move rules related to only one arch or SOC where they belong to, that
is in the corresponding arch/ or board/ directory.
>
> 2. Easy to clean the temporary generated file. The main Makefile
> deletes files with .pcfgtmp extension.
>
> 3. The file referred to by boards.cfg actually exists before the build
> starts.
This is true, but I do not understand which is the advantage. A lot of
files are generated, also .c or .S files. If it exists or not, it does
not matter.
>
> 4. The temporary file can be placed in an out-of-tree directory for
> make -O builds
>
> Using the file extension to determine whether to use the preprocessor is
> also
> what gcc uses to preprocess ".S" files while skipping this for ".s" files.
>
> I believe that at least other mx6 boards will quickly change to using
> the preprocessor
> as well to add support for solo/duallite, so total line count should
> eventually be
> less with changes to the main makefile.
Ok, but if this true, the rule should be moved to the mx6 directory, and
should not be valid for other i.MX that do not need it.
> Having said that, I really have no problem going your route, I just
> don't prefer it.
> Let me know.
Let's wait to know Tom's opinion.
Regards,
Stefano
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 17/32] imximage.cfg: run files through C preprocessor
2012-10-11 22:27 ` stefano babic
@ 2012-10-11 23:15 ` Tom Rini
2012-10-13 10:11 ` [U-Boot] File placement in Soc / board dirs and make issues (was: [PATCH V3 17/32] imximage.cfg: run files through C preprocessor) Albert ARIBAUD
2012-10-17 20:32 ` [U-Boot] [PATCH V3 17/32] imximage.cfg: run files through C preprocessor Troy Kisky
0 siblings, 2 replies; 430+ messages in thread
From: Tom Rini @ 2012-10-11 23:15 UTC (permalink / raw)
To: u-boot
On Fri, Oct 12, 2012 at 12:27:09AM +0200, stefano babic wrote:
[snip]
> One reason to move into the board directory is that there was a decision
> to move rules related to only one arch or SOC where they belong to, that
> is in the corresponding arch/ or board/ directory.
I'll admit that maybe my make-fu is off, but that idea doesn't work, at
least for SPL. So I'd really like someone to make that work first.
> > 2. Easy to clean the temporary generated file. The main Makefile
> > deletes files with .pcfgtmp extension.
> >
> > 3. The file referred to by boards.cfg actually exists before the build
> > starts.
>
> This is true, but I do not understand which is the advantage. A lot of
> files are generated, also .c or .S files. If it exists or not, it does
> not matter.
>
> >
> > 4. The temporary file can be placed in an out-of-tree directory for
> > make -O builds
> >
> > Using the file extension to determine whether to use the preprocessor is
> > also
> > what gcc uses to preprocess ".S" files while skipping this for ".s" files.
> >
> > I believe that at least other mx6 boards will quickly change to using
> > the preprocessor
> > as well to add support for solo/duallite, so total line count should
> > eventually be
> > less with changes to the main makefile.
>
> Ok, but if this true, the rule should be moved to the mx6 directory, and
> should not be valid for other i.MX that do not need it.
Introducing slight differences to the image generation rules per family
generation when we could just have one rule that works fine for all
generations is one worry I have about the notion of moving things out of
a top level Makefile and putting them elsewhere.
> > Having said that, I really have no problem going your route, I just
> > don't prefer it.
> > Let me know.
>
> Let's wait to know Tom's opinion.
How about this, if we convert the existing cfg files to '@' comments and
use the LDSCRIPT style preprocessor rule instead of another one? I
assume there's improvements that could be done to the mx5 ones if we
preprocessed them. Or no? I'm looking for opinions here myself still..
--
Tom
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^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] File placement in Soc / board dirs and make issues (was: [PATCH V3 17/32] imximage.cfg: run files through C preprocessor)
2012-10-11 23:15 ` Tom Rini
@ 2012-10-13 10:11 ` Albert ARIBAUD
2012-10-13 15:17 ` Tom Rini
2012-10-17 20:32 ` [U-Boot] [PATCH V3 17/32] imximage.cfg: run files through C preprocessor Troy Kisky
1 sibling, 1 reply; 430+ messages in thread
From: Albert ARIBAUD @ 2012-10-13 10:11 UTC (permalink / raw)
To: u-boot
Hi Tom,
On Thu, 11 Oct 2012 16:15:02 -0700, Tom Rini <trini@ti.com> wrote:
> On Fri, Oct 12, 2012 at 12:27:09AM +0200, stefano babic wrote:
>
> [snip]
> > One reason to move into the board directory is that there was a decision
> > to move rules related to only one arch or SOC where they belong to, that
> > is in the corresponding arch/ or board/ directory.
>
> I'll admit that maybe my make-fu is off, but that idea doesn't work, at
> least for SPL. So I'd really like someone to make that work first.
Tom, can you be more specific than 'it doesn't work'? :)
Seriously, though, I'm interested in understand what the make issue is
there, because I am indeed a proponent of putting files where they
belong to, so if help is needed there, I would try to.
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] File placement in Soc / board dirs and make issues (was: [PATCH V3 17/32] imximage.cfg: run files through C preprocessor)
2012-10-13 10:11 ` [U-Boot] File placement in Soc / board dirs and make issues (was: [PATCH V3 17/32] imximage.cfg: run files through C preprocessor) Albert ARIBAUD
@ 2012-10-13 15:17 ` Tom Rini
2012-10-14 8:37 ` [U-Boot] File placement in Soc / board dirs and make issues Albert ARIBAUD
0 siblings, 1 reply; 430+ messages in thread
From: Tom Rini @ 2012-10-13 15:17 UTC (permalink / raw)
To: u-boot
On Sat, Oct 13, 2012 at 3:11 AM, Albert ARIBAUD
<albert.u.boot@aribaud.net> wrote:
> Hi Tom,
>
> On Thu, 11 Oct 2012 16:15:02 -0700, Tom Rini <trini@ti.com> wrote:
>
>> On Fri, Oct 12, 2012 at 12:27:09AM +0200, stefano babic wrote:
>>
>> [snip]
>> > One reason to move into the board directory is that there was a decision
>> > to move rules related to only one arch or SOC where they belong to, that
>> > is in the corresponding arch/ or board/ directory.
>>
>> I'll admit that maybe my make-fu is off, but that idea doesn't work, at
>> least for SPL. So I'd really like someone to make that work first.
>
> Tom, can you be more specific than 'it doesn't work'? :)
>
> Seriously, though, I'm interested in understand what the make issue is
> there, because I am indeed a proponent of putting files where they
> belong to, so if help is needed there, I would try to.
I have had no luck moving things like the 'MLO' rule from spl/Makefile
to anywhere else. Same with the 'checkthumb' rule in the top-level
Makefile.
--
Tom
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] File placement in Soc / board dirs and make issues
2012-10-13 15:17 ` Tom Rini
@ 2012-10-14 8:37 ` Albert ARIBAUD
2012-10-15 1:24 ` Tom Rini
0 siblings, 1 reply; 430+ messages in thread
From: Albert ARIBAUD @ 2012-10-14 8:37 UTC (permalink / raw)
To: u-boot
Hi Tom,
(seems like gmail does not honor the rule that replies should drop the
"(was: xxxxx)" part in an e-mail subject; but hey, neither does Claws
apparently. Sigh.)
On Sat, 13 Oct 2012 08:17:41 -0700, Tom Rini <trini@ti.com> wrote:
> On Sat, Oct 13, 2012 at 3:11 AM, Albert ARIBAUD
> <albert.u.boot@aribaud.net> wrote:
> > Hi Tom,
> >
> > On Thu, 11 Oct 2012 16:15:02 -0700, Tom Rini <trini@ti.com> wrote:
> >
> >> On Fri, Oct 12, 2012 at 12:27:09AM +0200, stefano babic wrote:
> >>
> >> [snip]
> >> > One reason to move into the board directory is that there was a decision
> >> > to move rules related to only one arch or SOC where they belong to, that
> >> > is in the corresponding arch/ or board/ directory.
> >>
> >> I'll admit that maybe my make-fu is off, but that idea doesn't work, at
> >> least for SPL. So I'd really like someone to make that work first.
> >
> > Tom, can you be more specific than 'it doesn't work'? :)
> >
> > Seriously, though, I'm interested in understand what the make issue is
> > there, because I am indeed a proponent of putting files where they
> > belong to, so if help is needed there, I would try to.
>
> I have had no luck moving things like the 'MLO' rule from spl/Makefile
> to anywhere else. Same with the 'checkthumb' rule in the top-level
> Makefile.
Ok, now it is more precise :) but still not enough for me to
efficiently try and analyze the issue.
Let's take the checkthumb rule. Where did you try to move it?
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] File placement in Soc / board dirs and make issues
2012-10-14 8:37 ` [U-Boot] File placement in Soc / board dirs and make issues Albert ARIBAUD
@ 2012-10-15 1:24 ` Tom Rini
2012-10-23 6:30 ` Albert ARIBAUD
0 siblings, 1 reply; 430+ messages in thread
From: Tom Rini @ 2012-10-15 1:24 UTC (permalink / raw)
To: u-boot
On Sun, Oct 14, 2012 at 1:37 AM, Albert ARIBAUD
<albert.u.boot@aribaud.net> wrote:
> Hi Tom,
>
> (seems like gmail does not honor the rule that replies should drop the
> "(was: xxxxx)" part in an e-mail subject; but hey, neither does Claws
> apparently. Sigh.)
>
> On Sat, 13 Oct 2012 08:17:41 -0700, Tom Rini <trini@ti.com> wrote:
>
>> On Sat, Oct 13, 2012 at 3:11 AM, Albert ARIBAUD
>> <albert.u.boot@aribaud.net> wrote:
>> > Hi Tom,
>> >
>> > On Thu, 11 Oct 2012 16:15:02 -0700, Tom Rini <trini@ti.com> wrote:
>> >
>> >> On Fri, Oct 12, 2012 at 12:27:09AM +0200, stefano babic wrote:
>> >>
>> >> [snip]
>> >> > One reason to move into the board directory is that there was a decision
>> >> > to move rules related to only one arch or SOC where they belong to, that
>> >> > is in the corresponding arch/ or board/ directory.
>> >>
>> >> I'll admit that maybe my make-fu is off, but that idea doesn't work, at
>> >> least for SPL. So I'd really like someone to make that work first.
>> >
>> > Tom, can you be more specific than 'it doesn't work'? :)
>> >
>> > Seriously, though, I'm interested in understand what the make issue is
>> > there, because I am indeed a proponent of putting files where they
>> > belong to, so if help is needed there, I would try to.
>>
>> I have had no luck moving things like the 'MLO' rule from spl/Makefile
>> to anywhere else. Same with the 'checkthumb' rule in the top-level
>> Makefile.
>
> Ok, now it is more precise :) but still not enough for me to
> efficiently try and analyze the issue.
>
> Let's take the checkthumb rule. Where did you try to move it?
I tried both arch/arm/config.mk arch/arm/Makefile and couldn't make either work.
--
Tom
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 17/32] imximage.cfg: run files through C preprocessor
2012-10-11 23:15 ` Tom Rini
2012-10-13 10:11 ` [U-Boot] File placement in Soc / board dirs and make issues (was: [PATCH V3 17/32] imximage.cfg: run files through C preprocessor) Albert ARIBAUD
@ 2012-10-17 20:32 ` Troy Kisky
2012-10-17 21:05 ` Tom Rini
1 sibling, 1 reply; 430+ messages in thread
From: Troy Kisky @ 2012-10-17 20:32 UTC (permalink / raw)
To: u-boot
On 10/11/2012 4:15 PM, Tom Rini wrote:
> On Fri, Oct 12, 2012 at 12:27:09AM +0200, stefano babic wrote:
>
> [snip]
>> One reason to move into the board directory is that there was a decision
>> to move rules related to only one arch or SOC where they belong to, that
>> is in the corresponding arch/ or board/ directory.
> I'll admit that maybe my make-fu is off, but that idea doesn't work, at
> least for SPL. So I'd really like someone to make that work first.
>
>>> 2. Easy to clean the temporary generated file. The main Makefile
>>> deletes files with .pcfgtmp extension.
>>>
>>> 3. The file referred to by boards.cfg actually exists before the build
>>> starts.
>> This is true, but I do not understand which is the advantage. A lot of
>> files are generated, also .c or .S files. If it exists or not, it does
>> not matter.
Consistency was my point here. Every other file in boards.cfg exists
prior to build.
>>> 4. The temporary file can be placed in an out-of-tree directory for
>>> make -O builds
>>>
>>> Using the file extension to determine whether to use the preprocessor is
>>> also
>>> what gcc uses to preprocess ".S" files while skipping this for ".s" files.
>>>
>>> I believe that at least other mx6 boards will quickly change to using
>>> the preprocessor
>>> as well to add support for solo/duallite, so total line count should
>>> eventually be
>>> less with changes to the main makefile.
>> Ok, but if this true, the rule should be moved to the mx6 directory, and
>> should not be valid for other i.MX that do not need it.
> Introducing slight differences to the image generation rules per family
> generation when we could just have one rule that works fine for all
> generations is one worry I have about the notion of moving things out of
> a top level Makefile and putting them elsewhere.
>
>>> Having said that, I really have no problem going your route, I just
>>> don't prefer it.
>>> Let me know.
>> Let's wait to know Tom's opinion.
> How about this, if we convert the existing cfg files to '@' comments and
> use the LDSCRIPT style preprocessor rule instead of another one? I
> assume there's improvements that could be done to the mx5 ones if we
> preprocessed them. Or no? I'm looking for opinions here myself still..
>
I had previously converted all existing cfg files to /* */ comments.
That style of
comment seems common for LDSCRIPTs as well. '@''s actually give me an error.
arm-eabi-ld:u-boot.lds:1: ignoring invalid character `@' in expression
I do believe mx5 files can benefit from preprocessing. I can see the
advantage of
converting everything now. I also like flexibility of not forcing every
cfg file to
change now. So, I am setting on the fence. If I have to take a position, I'd
fall on the side of the smaller patch set of a gradual conversion, just
because I
like smaller patches.
Troy
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 17/32] imximage.cfg: run files through C preprocessor
2012-10-17 20:32 ` [U-Boot] [PATCH V3 17/32] imximage.cfg: run files through C preprocessor Troy Kisky
@ 2012-10-17 21:05 ` Tom Rini
2012-10-17 21:38 ` Troy Kisky
0 siblings, 1 reply; 430+ messages in thread
From: Tom Rini @ 2012-10-17 21:05 UTC (permalink / raw)
To: u-boot
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
On 10/17/12 13:32, Troy Kisky wrote:
> On 10/11/2012 4:15 PM, Tom Rini wrote:
>> On Fri, Oct 12, 2012 at 12:27:09AM +0200, stefano babic wrote:
>>
>> [snip]
>>> One reason to move into the board directory is that there was a
>>> decision to move rules related to only one arch or SOC where
>>> they belong to, that is in the corresponding arch/ or board/
>>> directory.
>> I'll admit that maybe my make-fu is off, but that idea doesn't
>> work, at least for SPL. So I'd really like someone to make that
>> work first.
>>
>>>> 2. Easy to clean the temporary generated file. The main
>>>> Makefile deletes files with .pcfgtmp extension.
>>>>
>>>> 3. The file referred to by boards.cfg actually exists before
>>>> the build starts.
>>> This is true, but I do not understand which is the advantage. A
>>> lot of files are generated, also .c or .S files. If it exists
>>> or not, it does not matter.
>
> Consistency was my point here. Every other file in boards.cfg
> exists prior to build.
>
>>>> 4. The temporary file can be placed in an out-of-tree
>>>> directory for make -O builds
>>>>
>>>> Using the file extension to determine whether to use the
>>>> preprocessor is also what gcc uses to preprocess ".S" files
>>>> while skipping this for ".s" files.
>>>>
>>>> I believe that at least other mx6 boards will quickly change
>>>> to using the preprocessor as well to add support for
>>>> solo/duallite, so total line count should eventually be less
>>>> with changes to the main makefile.
>>> Ok, but if this true, the rule should be moved to the mx6
>>> directory, and should not be valid for other i.MX that do not
>>> need it.
>> Introducing slight differences to the image generation rules per
>> family generation when we could just have one rule that works
>> fine for all generations is one worry I have about the notion of
>> moving things out of a top level Makefile and putting them
>> elsewhere.
>>
>>>> Having said that, I really have no problem going your route,
>>>> I just don't prefer it. Let me know.
>>> Let's wait to know Tom's opinion.
>> How about this, if we convert the existing cfg files to '@'
>> comments and use the LDSCRIPT style preprocessor rule instead of
>> another one? I assume there's improvements that could be done to
>> the mx5 ones if we preprocessed them. Or no? I'm looking for
>> opinions here myself still..
>>
>
> I had previously converted all existing cfg files to /* */
> comments. That style of comment seems common for LDSCRIPTs as well.
> '@''s actually give me an error.
>
> arm-eabi-ld:u-boot.lds:1: ignoring invalid character `@' in
> expression
Right, but in u-boot.lds.S it gets preprocessed away, at least I swear
I changed and tested that. My thinking being it was a smaller diff
delta. But my final point being I don't think we should start
introducing artificial differences here just because older boards may
not use it. That doing that leads to bit rot.
> I do believe mx5 files can benefit from preprocessing. I can see
> the advantage of converting everything now. I also like flexibility
> of not forcing every cfg file to change now. So, I am setting on
> the fence. If I have to take a position, I'd fall on the side of
> the smaller patch set of a gradual conversion, just because I like
> smaller patches.
I'm on the other side only because "later" sometimes never happens.
Doing it as a series of smaller patches, now might be fine too...
- --
Tom
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^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 17/32] imximage.cfg: run files through C preprocessor
2012-10-17 21:05 ` Tom Rini
@ 2012-10-17 21:38 ` Troy Kisky
2012-10-17 22:29 ` Tom Rini
0 siblings, 1 reply; 430+ messages in thread
From: Troy Kisky @ 2012-10-17 21:38 UTC (permalink / raw)
To: u-boot
On 10/17/2012 2:05 PM, Tom Rini wrote:
> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA1
>
> On 10/17/12 13:32, Troy Kisky wrote:
>> On 10/11/2012 4:15 PM, Tom Rini wrote:
>>> On Fri, Oct 12, 2012 at 12:27:09AM +0200, stefano babic wrote:
>>>
>>> [snip]
>>>> One reason to move into the board directory is that there was a
>>>> decision to move rules related to only one arch or SOC where
>>>> they belong to, that is in the corresponding arch/ or board/
>>>> directory.
>>> I'll admit that maybe my make-fu is off, but that idea doesn't
>>> work, at least for SPL. So I'd really like someone to make that
>>> work first.
>>>
>>>>> 2. Easy to clean the temporary generated file. The main
>>>>> Makefile deletes files with .pcfgtmp extension.
>>>>>
>>>>> 3. The file referred to by boards.cfg actually exists before
>>>>> the build starts.
>>>> This is true, but I do not understand which is the advantage. A
>>>> lot of files are generated, also .c or .S files. If it exists
>>>> or not, it does not matter.
>> Consistency was my point here. Every other file in boards.cfg
>> exists prior to build.
>>
>>>>> 4. The temporary file can be placed in an out-of-tree
>>>>> directory for make -O builds
>>>>>
>>>>> Using the file extension to determine whether to use the
>>>>> preprocessor is also what gcc uses to preprocess ".S" files
>>>>> while skipping this for ".s" files.
>>>>>
>>>>> I believe that at least other mx6 boards will quickly change
>>>>> to using the preprocessor as well to add support for
>>>>> solo/duallite, so total line count should eventually be less
>>>>> with changes to the main makefile.
>>>> Ok, but if this true, the rule should be moved to the mx6
>>>> directory, and should not be valid for other i.MX that do not
>>>> need it.
>>> Introducing slight differences to the image generation rules per
>>> family generation when we could just have one rule that works
>>> fine for all generations is one worry I have about the notion of
>>> moving things out of a top level Makefile and putting them
>>> elsewhere.
>>>
>>>>> Having said that, I really have no problem going your route,
>>>>> I just don't prefer it. Let me know.
>>>> Let's wait to know Tom's opinion.
>>> How about this, if we convert the existing cfg files to '@'
>>> comments and use the LDSCRIPT style preprocessor rule instead of
>>> another one? I assume there's improvements that could be done to
>>> the mx5 ones if we preprocessed them. Or no? I'm looking for
>>> opinions here myself still..
>>>
>> I had previously converted all existing cfg files to /* */
>> comments. That style of comment seems common for LDSCRIPTs as well.
>> '@''s actually give me an error.
>>
>> arm-eabi-ld:u-boot.lds:1: ignoring invalid character `@' in
>> expression
> Right, but in u-boot.lds.S it gets preprocessed away, at least I swear
> I changed and tested that. My thinking being it was a smaller diff
> delta.
Good point. Is there some magic parameter to pass to gcc to strip @. My
current
command line is expanded to
arm-eabi-gcc -E -x c board/freescale/imx/ddr/mx6q_4x_mt41j128.pcfg -g -Os
-fno-common -ffixed-r8 -msoft-float -D__KERNEL__
-DCONFIG_SYS_TEXT_BASE=0x17800000
-I/home/tkisky/u-boot-imx6/include -fno-builtin -ffreestanding -nostdinc
-isystem
/home/tkisky/myandroid/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/../lib/gcc/arm-eabi/4.4.3/include
-pipe
-DCONFIG_ARM -D__ARM__ -marm -mno-thumb-interwork -mabi=aapcs-linux
-march=armv7-a
-o board/freescale/imx/ddr/mx6q_4x_mt41j128.pcfgtmp
Alternatively, I could send a small patch to mkimage to ignore @ lines
along with the currently
ignored # lines.
I grepped all lds files in u-boot, but could not find one that used @ as
a comment indicator.
I don't know what/where u-boot.lds.S is.
> But my final point being I don't think we should start
> introducing artificial differences here just because older boards may
> not use it. That doing that leads to bit rot.
>
>> I do believe mx5 files can benefit from preprocessing. I can see
>> the advantage of converting everything now. I also like flexibility
>> of not forcing every cfg file to change now. So, I am setting on
>> the fence. If I have to take a position, I'd fall on the side of
>> the smaller patch set of a gradual conversion, just because I like
>> smaller patches.
> I'm on the other side only because "later" sometimes never happens.
> Doing it as a series of smaller patches, now might be fine too...
>
> - --
> Tom
>
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 17/32] imximage.cfg: run files through C preprocessor
2012-10-17 21:38 ` Troy Kisky
@ 2012-10-17 22:29 ` Tom Rini
0 siblings, 0 replies; 430+ messages in thread
From: Tom Rini @ 2012-10-17 22:29 UTC (permalink / raw)
To: u-boot
On Wed, Oct 17, 2012 at 02:38:47PM -0700, Troy Kisky wrote:
> On 10/17/2012 2:05 PM, Tom Rini wrote:
> >-----BEGIN PGP SIGNED MESSAGE-----
> >Hash: SHA1
> >
> >On 10/17/12 13:32, Troy Kisky wrote:
> >>On 10/11/2012 4:15 PM, Tom Rini wrote:
> >>>On Fri, Oct 12, 2012 at 12:27:09AM +0200, stefano babic wrote:
> >>>
> >>>[snip]
> >>>>One reason to move into the board directory is that there was a
> >>>>decision to move rules related to only one arch or SOC where
> >>>>they belong to, that is in the corresponding arch/ or board/
> >>>>directory.
> >>>I'll admit that maybe my make-fu is off, but that idea doesn't
> >>>work, at least for SPL. So I'd really like someone to make that
> >>>work first.
> >>>
> >>>>>2. Easy to clean the temporary generated file. The main
> >>>>>Makefile deletes files with .pcfgtmp extension.
> >>>>>
> >>>>>3. The file referred to by boards.cfg actually exists before
> >>>>>the build starts.
> >>>>This is true, but I do not understand which is the advantage. A
> >>>>lot of files are generated, also .c or .S files. If it exists
> >>>>or not, it does not matter.
> >>Consistency was my point here. Every other file in boards.cfg
> >>exists prior to build.
> >>
> >>>>>4. The temporary file can be placed in an out-of-tree
> >>>>>directory for make -O builds
> >>>>>
> >>>>>Using the file extension to determine whether to use the
> >>>>>preprocessor is also what gcc uses to preprocess ".S" files
> >>>>>while skipping this for ".s" files.
> >>>>>
> >>>>>I believe that at least other mx6 boards will quickly change
> >>>>>to using the preprocessor as well to add support for
> >>>>>solo/duallite, so total line count should eventually be less
> >>>>>with changes to the main makefile.
> >>>>Ok, but if this true, the rule should be moved to the mx6
> >>>>directory, and should not be valid for other i.MX that do not
> >>>>need it.
> >>>Introducing slight differences to the image generation rules per
> >>>family generation when we could just have one rule that works
> >>>fine for all generations is one worry I have about the notion of
> >>>moving things out of a top level Makefile and putting them
> >>>elsewhere.
> >>>
> >>>>>Having said that, I really have no problem going your route,
> >>>>>I just don't prefer it. Let me know.
> >>>>Let's wait to know Tom's opinion.
> >>>How about this, if we convert the existing cfg files to '@'
> >>>comments and use the LDSCRIPT style preprocessor rule instead of
> >>>another one? I assume there's improvements that could be done to
> >>>the mx5 ones if we preprocessed them. Or no? I'm looking for
> >>>opinions here myself still..
> >>>
> >>I had previously converted all existing cfg files to /* */
> >>comments. That style of comment seems common for LDSCRIPTs as well.
> >>'@''s actually give me an error.
> >>
> >>arm-eabi-ld:u-boot.lds:1: ignoring invalid character `@' in
> >>expression
> >Right, but in u-boot.lds.S it gets preprocessed away, at least I swear
> >I changed and tested that. My thinking being it was a smaller diff
> >delta.
>
> Good point. Is there some magic parameter to pass to gcc to strip @.
Lets just go with /* */ comments, everyone understands that.
--
Tom
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^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 03/32] imximage: move flash_offset check to common location
2012-10-08 13:19 ` Stefano Babic
@ 2012-10-18 18:40 ` Troy Kisky
2012-10-19 8:01 ` Stefano Babic
0 siblings, 1 reply; 430+ messages in thread
From: Troy Kisky @ 2012-10-18 18:40 UTC (permalink / raw)
To: u-boot
On 10/8/2012 6:19 AM, Stefano Babic wrote:
> On 04/10/2012 03:47, Troy Kisky wrote:
>> Both set_imx_hdr_v1 and set_imx_hdr_v2 perform the
>> same check. Move check to before the set_imx_hdr call.
>>
>> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
>>
>> ---
>> v3: split into its own patch
>> ---
>> tools/imximage.c | 19 +++++--------------
>> 1 file changed, 5 insertions(+), 14 deletions(-)
>>
> Acked-by: Stefano Babic <sbabic@denx.de>
>
> Best regards,
> Stefano Babic
>
>
Are you going to apply this(and 1/32, 2/23) now, or should I resend in the
next version with your ack?
Thanks
Troy
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 03/32] imximage: move flash_offset check to common location
2012-10-18 18:40 ` Troy Kisky
@ 2012-10-19 8:01 ` Stefano Babic
0 siblings, 0 replies; 430+ messages in thread
From: Stefano Babic @ 2012-10-19 8:01 UTC (permalink / raw)
To: u-boot
Am 18/10/2012 20:40, schrieb Troy Kisky:
> On 10/8/2012 6:19 AM, Stefano Babic wrote:
>> On 04/10/2012 03:47, Troy Kisky wrote:
>>> Both set_imx_hdr_v1 and set_imx_hdr_v2 perform the
>>> same check. Move check to before the set_imx_hdr call.
>>>
>>> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
>>>
>>> ---
>>> v3: split into its own patch
>>> ---
>>> tools/imximage.c | 19 +++++--------------
>>> 1 file changed, 5 insertions(+), 14 deletions(-)
>>>
>> Acked-by: Stefano Babic <sbabic@denx.de>
>>
>> Best regards,
>> Stefano Babic
>>
>>
> Are you going to apply this(and 1/32, 2/23) now, or should I resend in the
> next version with your ack?
>
Hi Troy,
I think the best way to proceed would be if I apply the patches for the
fixes, so that you have not to resend even the patches that will be not
touched. And maybe in this "incremental" way we can speed up the whole
process.
In my ready-to-be-applied list I marked already the patches from 1/32 up
to 5/32. My way to do this is to set them as "under reviewed" in
patchworks, because there is not a "ready-to-be-merged" state.
IMHO even patches up to 9/32 can be applied, they are free of comments
and we discussed about them in your previous posting.
So please wait, I will apply the first set of patches.
Best regards,
Stefano
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 01/32] imximage: check dcd_len as entries added
2012-10-04 1:47 ` [U-Boot] [PATCH V3 01/32] imximage: check dcd_len as entries added Troy Kisky
@ 2012-10-20 15:45 ` Stefano Babic
0 siblings, 0 replies; 430+ messages in thread
From: Stefano Babic @ 2012-10-20 15:45 UTC (permalink / raw)
To: u-boot
Am 04/10/2012 03:47, schrieb Troy Kisky:
> Before the len was checked after the entire file
> was processed, so it could have already overflowed.
>
> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
>
> ---
Applied to u-boot-imx, thanks.
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 02/32] imximage: remove redundant setting of app_dest_ptr
2012-10-04 1:47 ` [U-Boot] [PATCH V3 02/32] imximage: remove redundant setting of app_dest_ptr Troy Kisky
2012-10-08 13:17 ` Stefano Babic
@ 2012-10-20 15:46 ` Stefano Babic
1 sibling, 0 replies; 430+ messages in thread
From: Stefano Babic @ 2012-10-20 15:46 UTC (permalink / raw)
To: u-boot
Am 04/10/2012 03:47, schrieb Troy Kisky:
> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
>
> ---
> v3: split into its own patch
> ---
> tools/imximage.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/tools/imximage.c b/tools/imximage.c
> index c917036..bda1a75 100644
> --- a/tools/imximage.c
> +++ b/tools/imximage.c
> @@ -213,7 +213,6 @@ static void set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,
> /* Set magic number */
> fhdr_v1->app_code_barker = APP_CODE_BARKER;
>
> - fhdr_v1->app_dest_ptr = params->addr;
> fhdr_v1->app_dest_ptr = params->ep - imxhdr->flash_offset -
> sizeof(struct imx_header);
> fhdr_v1->app_code_jump_vector = params->ep;
>
Applied to u-boot-imx, thanks.
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 03/32] imximage: move flash_offset check to common location
2012-10-04 1:47 ` [U-Boot] [PATCH V3 03/32] imximage: move flash_offset check to common location Troy Kisky
2012-10-08 13:19 ` Stefano Babic
@ 2012-10-20 15:46 ` Stefano Babic
1 sibling, 0 replies; 430+ messages in thread
From: Stefano Babic @ 2012-10-20 15:46 UTC (permalink / raw)
To: u-boot
Am 04/10/2012 03:47, schrieb Troy Kisky:
> Both set_imx_hdr_v1 and set_imx_hdr_v2 perform the
> same check. Move check to before the set_imx_hdr call.
>
> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
>
> ---
Applied to u-boot-imx, thanks.
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 04/32] imximage: fix size of image to load.
2012-10-04 1:47 ` [U-Boot] [PATCH V3 04/32] imximage: fix size of image to load Troy Kisky
@ 2012-10-20 15:47 ` Stefano Babic
0 siblings, 0 replies; 430+ messages in thread
From: Stefano Babic @ 2012-10-20 15:47 UTC (permalink / raw)
To: u-boot
Am 04/10/2012 03:47, schrieb Troy Kisky:
> sbuf->st_size already includes sizeof(struct imx_header),
> so remove extra addition.
>
> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
>
> ---
Applied to u-boot-imx, thanks.
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 05/32] imximage: delay setting of image size
2012-10-04 1:47 ` [U-Boot] [PATCH V3 05/32] imximage: delay setting of image size Troy Kisky
@ 2012-10-20 15:47 ` Stefano Babic
0 siblings, 0 replies; 430+ messages in thread
From: Stefano Babic @ 2012-10-20 15:47 UTC (permalink / raw)
To: u-boot
Am 04/10/2012 03:47, schrieb Troy Kisky:
> When later we change to variable length
> header, we won't know the file size when
> set_imx_hdr is called. So this is prep work.
>
> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
>
> ---
> v3: split into its own patch
> ---
Applied to u-boot-imx, thanks.
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 06/32] imximage: change parameters to set_imx_hdr
2012-10-04 1:47 ` [U-Boot] [PATCH V3 06/32] imximage: change parameters to set_imx_hdr Troy Kisky
@ 2012-10-20 15:48 ` Stefano Babic
0 siblings, 0 replies; 430+ messages in thread
From: Stefano Babic @ 2012-10-20 15:48 UTC (permalink / raw)
To: u-boot
Am 04/10/2012 03:47, schrieb Troy Kisky:
> Call with the value the function will use
> instead of going through a pointer.
>
> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
>
> ---
Applied to u-boot-imx, thanks.
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 07/32] imximage: make set_imx_hdr_v1/v2 easier to read
2012-10-04 1:47 ` [U-Boot] [PATCH V3 07/32] imximage: make set_imx_hdr_v1/v2 easier to read Troy Kisky
@ 2012-10-20 15:48 ` Stefano Babic
0 siblings, 0 replies; 430+ messages in thread
From: Stefano Babic @ 2012-10-20 15:48 UTC (permalink / raw)
To: u-boot
Am 04/10/2012 03:47, schrieb Troy Kisky:
> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
>
> ---
> v3: split into own patch
> ---
Applied to u-boot-imx, thanks.
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 08/32] imximage: make header variable length
2012-10-04 1:47 ` [U-Boot] [PATCH V3 08/32] imximage: make header variable length Troy Kisky
@ 2012-10-20 15:52 ` Stefano Babic
2012-10-21 1:31 ` Troy Kisky
2012-11-28 1:31 ` [U-Boot] [PATCH V4 00/11] imximage series Troy Kisky
1 sibling, 1 reply; 430+ messages in thread
From: Stefano Babic @ 2012-10-20 15:52 UTC (permalink / raw)
To: u-boot
Am 04/10/2012 03:47, schrieb Troy Kisky:
> This makes the dcd table options as well for v2.
> Also, the header offset is no longer
> right before the code starts.
>
> Before this patch we have
> 000000 402000d1 17800000 00000000 177ffc2c
> 000010 177ffc20 177ffc00 00000000 00000000
> 000020 177ff800 00042b58 00000000 402803d2
> 000030 042403cc a8050e02 30000000 b0050e02
> ... more DCD table
> 000340 cf0000f0 18000e02 7f007f00 1c000e02
> 000350 7f007f00 00000000 00000000 00000000
> 000360 00000000 00000000 00000000 00000000
> *
> 0003f0 00000000 00000000 00000000 00000400
> 000400 ea000014 e59ff014 e59ff014 e59ff014
>
> Notice offset 3fc contains 0x400. This
> is the header offset. There is no reason
> for this to be in the file, and I have
> removed it.
>
> After this patch we have
> 000000 402000d1 17800000 00000000 177ffcd8
> 000010 177ffccc 177ffcac 00000000 00000000
> 000020 177ff8ac 000426ac 00000000 402803d2
> 000030 042403cc a8050e02 30000000 b0050e02
> ... more DCD table
> 000340 cf0000f0 18000e02 7f007f00 1c000e02
> 000350 7f007f00 ea000014 e59ff014 e59ff014
> 000360 e59ff014 e59ff014 e59ff014 e59ff014
>
> Notice the zeros between 0x354 and 0x3fb have
> been removed.
>
> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
>
> ---
Hi Troy,
my test with this patch was not successful. I have tested it on a
mx53loco, and the board cannot boot. It stops after printing the RAM size:
U-Boot 2012.10-00226-g673b6b8 (Oct 20 2012 - 17:40:07)
Board: MX53 LOCO
I2C: ready
DRAM: 1 GiB
Everything works fine without the patch (patches 1-7 already applied,
too). I wanted to test on V1 SOCs, too, but I stopped after seeing that
on a MX53 is not working.
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 08/32] imximage: make header variable length
2012-10-20 15:52 ` Stefano Babic
@ 2012-10-21 1:31 ` Troy Kisky
2012-10-21 8:35 ` Stefano Babic
0 siblings, 1 reply; 430+ messages in thread
From: Troy Kisky @ 2012-10-21 1:31 UTC (permalink / raw)
To: u-boot
On 10/20/2012 8:52 AM, Stefano Babic wrote:
> Am 04/10/2012 03:47, schrieb Troy Kisky:
>> This makes the dcd table options as well for v2.
>> Also, the header offset is no longer
>> right before the code starts.
>>
>> Before this patch we have
>> 000000 402000d1 17800000 00000000 177ffc2c
>> 000010 177ffc20 177ffc00 00000000 00000000
>> 000020 177ff800 00042b58 00000000 402803d2
>> 000030 042403cc a8050e02 30000000 b0050e02
>> ... more DCD table
>> 000340 cf0000f0 18000e02 7f007f00 1c000e02
>> 000350 7f007f00 00000000 00000000 00000000
>> 000360 00000000 00000000 00000000 00000000
>> *
>> 0003f0 00000000 00000000 00000000 00000400
>> 000400 ea000014 e59ff014 e59ff014 e59ff014
>>
>> Notice offset 3fc contains 0x400. This
>> is the header offset. There is no reason
>> for this to be in the file, and I have
>> removed it.
>>
>> After this patch we have
>> 000000 402000d1 17800000 00000000 177ffcd8
>> 000010 177ffccc 177ffcac 00000000 00000000
>> 000020 177ff8ac 000426ac 00000000 402803d2
>> 000030 042403cc a8050e02 30000000 b0050e02
>> ... more DCD table
>> 000340 cf0000f0 18000e02 7f007f00 1c000e02
>> 000350 7f007f00 ea000014 e59ff014 e59ff014
>> 000360 e59ff014 e59ff014 e59ff014 e59ff014
>>
>> Notice the zeros between 0x354 and 0x3fb have
>> been removed.
>>
>> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
>>
>> ---
>
> Hi Troy,
>
> my test with this patch was not successful. I have tested it on a
> mx53loco, and the board cannot boot. It stops after printing the RAM size:
>
>
> U-Boot 2012.10-00226-g673b6b8 (Oct 20 2012 - 17:40:07)
>
> Board: MX53 LOCO
> I2C: ready
> DRAM: 1 GiB
>
> Everything works fine without the patch (patches 1-7 already applied,
> too). I wanted to test on V1 SOCs, too, but I stopped after seeing that
> on a MX53 is not working.
>
> Best regards,
> Stefano Babic
>
I've tested this patch on a mx51 boards as well and it worked fine there.
For testing purposes, can you see if this change helps any?
Perhaps the rom isn't loading all the code, and this will load a little
more.
diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
index e49ca0c..4b303f1 100644
--- a/arch/arm/cpu/u-boot.lds
+++ b/arch/arm/cpu/u-boot.lds
@@ -86,6 +86,12 @@ SECTIONS
__bss_end__ = .;
}
+ .zdata1 : {
+ . = ALIGN(512);
+ LONG(0xdeadbeef);
+ FILL(0xefbeadde);
+ . = ALIGN(512);
+ }
/DISCARD/ : { *(.dynstr*) }
/DISCARD/ : { *(.dynamic*) }
/DISCARD/ : { *(.plt*) }
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 08/32] imximage: make header variable length
2012-10-21 1:31 ` Troy Kisky
@ 2012-10-21 8:35 ` Stefano Babic
2012-10-22 21:03 ` Troy Kisky
0 siblings, 1 reply; 430+ messages in thread
From: Stefano Babic @ 2012-10-21 8:35 UTC (permalink / raw)
To: u-boot
Am 21/10/2012 03:31, schrieb Troy Kisky:
>
> I've tested this patch on a mx51 boards as well and it worked fine there.
Fine, thanks, this saves me time - I will not test it on that SOC.
>
> For testing purposes, can you see if this change helps any?
> Perhaps the rom isn't loading all the code, and this will load a little
> more.
I had the same feeling.
In fact, increasing artificially the size with the zdata1 section helps.
It boots. There should be an error by computing the total length of the
image.
Best regards,
Stefano
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V3 08/32] imximage: make header variable length
2012-10-21 8:35 ` Stefano Babic
@ 2012-10-22 21:03 ` Troy Kisky
0 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-10-22 21:03 UTC (permalink / raw)
To: u-boot
On 10/21/2012 1:35 AM, Stefano Babic wrote:
> Am 21/10/2012 03:31, schrieb Troy Kisky:
>
>> I've tested this patch on a mx51 boards as well and it worked fine there.
> Fine, thanks, this saves me time - I will not test it on that SOC.
>
>> For testing purposes, can you see if this change helps any?
>> Perhaps the rom isn't loading all the code, and this will load a little
>> more.
> I had the same feeling.
>
> In fact, increasing artificially the size with the zdata1 section helps.
> It boots. There should be an error by computing the total length of the
> image.
>
> Best regards,
> Stefano
>
Oops, my previous test patch was after bss instead of before. With this
patch
diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
index e49ca0c..8352c7c 100644
--- a/arch/arm/cpu/u-boot.lds
+++ b/arch/arm/cpu/u-boot.lds
@@ -78,6 +78,12 @@ SECTIONS
.mmutable : {
*(.mmutable)
}
+ .zdata1 : {
+ . = ALIGN(512);
+ LONG(0xdeadbeef);
+ FILL(0xefbeadde);
+ . = ALIGN(512);
+ }
.bss __rel_dyn_start (OVERLAY) : {
__bss_start = .;
My mx51 board shows
U-Boot > mw.l 97841000 12345678 2000000
U-Boot > reset
resetting ...
U-Boot 2012.10-01232-g2919aa2-dirty (Oct 22 2012 - 13:17:26)
CPU: Freescale i.MX51 rev3.0 at 800 MHz
Reset cause: WDOG
Board: Nitrogen
dram_init
dram_init exit
DRAM: 256 MiB
MMC: FSL_SDHC: 0, FSL_SDHC: 1
SF: Detected SST25VF016B with page size 4 KiB, total 2 MiB
*** Warning - bad CRC, using default environment
In: serial
Out: serial
Err: serial
Net: FEC
Warning: failed to set MAC address
Hit any key to stop autoboot: 0
U-Boot > md.l 97841000
97841000: deadbeef deadbeef deadbeef deadbeef ................
97841010: deadbeef deadbeef deadbeef deadbeef ................
97841020: deadbeef deadbeef deadbeef deadbeef ................
97841030: deadbeef deadbeef deadbeef deadbeef ................
97841040: deadbeef deadbeef deadbeef deadbeef ................
97841050: deadbeef deadbeef deadbeef deadbeef ................
97841060: deadbeef deadbeef deadbeef deadbeef ................
97841070: deadbeef deadbeef deadbeef deadbeef ................
97841080: deadbeef deadbeef deadbeef deadbeef ................
97841090: deadbeef deadbeef deadbeef deadbeef ................
978410a0: deadbeef deadbeef deadbeef deadbeef ................
978410b0: deadbeef deadbeef deadbeef deadbeef ................
978410c0: deadbeef deadbeef deadbeef deadbeef ................
978410d0: deadbeef deadbeef deadbeef deadbeef ................
978410e0: deadbeef deadbeef deadbeef deadbeef ................
978410f0: deadbeef deadbeef deadbeef deadbeef ................
U-Boot >
97841100: deadbeef deadbeef deadbeef deadbeef ................
97841110: deadbeef deadbeef deadbeef deadbeef ................
97841120: deadbeef deadbeef deadbeef deadbeef ................
97841130: deadbeef deadbeef deadbeef deadbeef ................
97841140: deadbeef deadbeef deadbeef deadbeef ................
97841150: deadbeef deadbeef deadbeef deadbeef ................
97841160: deadbeef deadbeef deadbeef deadbeef ................
97841170: deadbeef deadbeef deadbeef deadbeef ................
97841180: deadbeef deadbeef deadbeef deadbeef ................
97841190: deadbeef deadbeef deadbeef deadbeef ................
978411a0: deadbeef deadbeef deadbeef deadbeef ................
978411b0: deadbeef deadbeef deadbeef deadbeef ................
978411c0: deadbeef deadbeef deadbeef deadbeef ................
978411d0: deadbeef deadbeef deadbeef deadbeef ................
978411e0: deadbeef deadbeef deadbeef deadbeef ................
978411f0: deadbeef deadbeef deadbeef deadbeef ................
U-Boot >
97841200: 12345678 12345678 12345678 12345678 xV4.xV4.xV4.xV4.
97841210: 12345678 12345678 12345678 12345678 xV4.xV4.xV4.xV4.
97841220: 12345678 12345678 12345678 12345678 xV4.xV4.xV4.xV4.
97841230: 12345678 12345678 12345678 12345678 xV4.xV4.xV4.xV4.
97841240: 12345678 12345678 12345678 12345678 xV4.xV4.xV4.xV4.
97841250: 12345678 12345678 12345678 12345678 xV4.xV4.xV4.xV4.
97841260: 12345678 12345678 12345678 12345678 xV4.xV4.xV4.xV4.
97841270: 12345678 12345678 12345678 12345678 xV4.xV4.xV4.xV4.
97841280: 12345678 12345678 12345678 12345678 xV4.xV4.xV4.xV4.
97841290: 12345678 12345678 12345678 12345678 xV4.xV4.xV4.xV4.
978412a0: 12345678 12345678 12345678 12345678 xV4.xV4.xV4.xV4.
978412b0: 12345678 12345678 12345678 12345678 xV4.xV4.xV4.xV4.
978412c0: 12345678 12345678 12345678 12345678 xV4.xV4.xV4.xV4.
978412d0: 12345678 12345678 12345678 12345678 xV4.xV4.xV4.xV4.
978412e0: 12345678 12345678 12345678 12345678 xV4.xV4.xV4.xV4.
978412f0: 12345678 12345678 12345678 12345678 xV4.xV4.xV4.xV4.
U-Boot >
Showing that exactly the correct number of bytes where loaded.
_________________________________________________________
_________________________________________________________
My mx6q board shows
U-Boot > mw.l 1784e000 12345678 2000000
U-Boot > reset
resetting ...
U-Boot 2012.10-01232-g2919aa2-dirty (Oct 22 2012 - 13:45:52)
CPU: Freescale i.MX6Q rev1.0 at 792 MHz
Reset cause: WDOG
Board: MX6Q-Sabre Lite
DRAM: 1 GiB
MMC: FSL_SDHC: 0, FSL_SDHC: 1
SF: Detected SST25VF016B with page size 4 KiB, total 2 MiB
No panel detected: default to HDMI
unsupported panel HDMI
In: serial
Out: serial
Err: serial
Net: FEC
Warning: FEC using MAC address from net device
Hit any key to stop autoboot: 0
U-Boot > md.l 1784e000
1784e000: deadbeef deadbeef deadbeef deadbeef ................
1784e010: deadbeef deadbeef deadbeef deadbeef ................
1784e020: deadbeef deadbeef deadbeef deadbeef ................
1784e030: deadbeef deadbeef deadbeef deadbeef ................
1784e040: deadbeef deadbeef deadbeef deadbeef ................
1784e050: deadbeef deadbeef deadbeef deadbeef ................
1784e060: deadbeef deadbeef deadbeef deadbeef ................
1784e070: deadbeef deadbeef deadbeef deadbeef ................
1784e080: deadbeef deadbeef deadbeef deadbeef ................
1784e090: deadbeef deadbeef deadbeef deadbeef ................
1784e0a0: deadbeef deadbeef deadbeef deadbeef ................
1784e0b0: deadbeef deadbeef deadbeef deadbeef ................
1784e0c0: deadbeef deadbeef deadbeef deadbeef ................
1784e0d0: deadbeef deadbeef deadbeef deadbeef ................
1784e0e0: deadbeef deadbeef deadbeef deadbeef ................
1784e0f0: deadbeef deadbeef deadbeef deadbeef ................
U-Boot >
1784e100: deadbeef deadbeef deadbeef deadbeef ................
1784e110: deadbeef deadbeef deadbeef deadbeef ................
1784e120: deadbeef deadbeef deadbeef deadbeef ................
1784e130: deadbeef deadbeef deadbeef deadbeef ................
1784e140: deadbeef deadbeef deadbeef deadbeef ................
1784e150: deadbeef deadbeef deadbeef deadbeef ................
1784e160: deadbeef deadbeef deadbeef deadbeef ................
1784e170: deadbeef deadbeef deadbeef deadbeef ................
1784e180: deadbeef deadbeef deadbeef deadbeef ................
1784e190: deadbeef deadbeef deadbeef deadbeef ................
1784e1a0: deadbeef deadbeef deadbeef deadbeef ................
1784e1b0: deadbeef deadbeef deadbeef deadbeef ................
1784e1c0: deadbeef deadbeef deadbeef deadbeef ................
1784e1d0: deadbeef deadbeef deadbeef deadbeef ................
1784e1e0: deadbeef deadbeef deadbeef deadbeef ................
1784e1f0: deadbeef deadbeef deadbeef deadbeef ................
U-Boot >
1784e200: 02000000 46200600 00202000 00000000 ...... F. .....
1784e210: 00000010 00004020 00000000 00004222 .... @......"B..
1784e220: 02000000 00000040 00000000 00000000 .... at ...........
1784e230: 00000000 00000400 00020002 00000000 ................
1784e240: 00140000 00000000 00100000 00008080 ................
1784e250: 00100200 00410080 00004020 18000110 ......A. @......
1784e260: 00000000 80000a00 00000000 00000000 ................
1784e270: 00000280 08029980 00000000 00001080 ................
1784e280: 40000000 00800002 02802404 02a00200 ... at .....$......
1784e290: 08002000 00000000 00808400 40200200 . ............ @
1784e2a0: 40000000 00000000 00000000 00000020 ... at ........ ...
1784e2b0: 00000000 00200020 00008000 00000000 .... . .........
1784e2c0: 12345678 12345678 12345678 12345678 xV4.xV4.xV4.xV4.
1784e2d0: 12345678 12345678 12345678 12345678 xV4.xV4.xV4.xV4.
1784e2e0: 00000200 00010001 00000201 10000000 ................
1784e2f0: 14000000 00000000 00000001 08000011 ................
U-Boot >
1784e300: 12345678 12345678 12345678 12345678 xV4.xV4.xV4.xV4.
1784e310: 12345678 12345678 12345678 12345678 xV4.xV4.xV4.xV4.
1784e320: 12345678 12345678 12345678 12345678 xV4.xV4.xV4.xV4.
1784e330: 12345678 12345678 12345678 12345678 xV4.xV4.xV4.xV4.
1784e340: 12345678 12345678 12345678 12345678 xV4.xV4.xV4.xV4.
1784e350: 12345678 12345678 12345678 12345678 xV4.xV4.xV4.xV4.
1784e360: 12345678 12345678 12345678 12345678 xV4.xV4.xV4.xV4.
1784e370: 12345678 12345678 12345678 12345678 xV4.xV4.xV4.xV4.
1784e380: 12345678 12345678 12345678 12345678 xV4.xV4.xV4.xV4.
1784e390: 12345678 12345678 12345678 12345678 xV4.xV4.xV4.xV4.
1784e3a0: 12345678 12345678 12345678 12345678 xV4.xV4.xV4.xV4.
1784e3b0: 12345678 12345678 12345678 12345678 xV4.xV4.xV4.xV4.
1784e3c0: 12345678 12345678 12345678 12345678 xV4.xV4.xV4.xV4.
1784e3d0: 12345678 12345678 12345678 12345678 xV4.xV4.xV4.xV4.
1784e3e0: 12345678 12345678 12345678 12345678 xV4.xV4.xV4.xV4.
1784e3f0: 12345678 12345678 12345678 12345678 xV4.xV4.xV4.xV4.
U-Boot >
Showing that an extra 0x100 bytes were written.
U-Boot > sf probe
SF: Detected SST25VF016B with page size 4 KiB, total 2 MiB
U-Boot > sf read 10800000 400 50000
U-Boot > md.l 1084e334
1084e334: deadbeef deadbeef deadbeef deadbeef ................
1084e344: deadbeef deadbeef deadbeef deadbeef ................
1084e354: deadbeef deadbeef deadbeef deadbeef ................
1084e364: deadbeef deadbeef deadbeef deadbeef ................
1084e374: deadbeef deadbeef deadbeef deadbeef ................
1084e384: deadbeef deadbeef deadbeef deadbeef ................
1084e394: deadbeef deadbeef deadbeef deadbeef ................
1084e3a4: deadbeef deadbeef deadbeef deadbeef ................
1084e3b4: deadbeef deadbeef deadbeef deadbeef ................
1084e3c4: deadbeef deadbeef deadbeef deadbeef ................
1084e3d4: deadbeef deadbeef deadbeef deadbeef ................
1084e3e4: deadbeef deadbeef deadbeef deadbeef ................
1084e3f4: deadbeef deadbeef deadbeef deadbeef ................
1084e404: deadbeef deadbeef deadbeef deadbeef ................
1084e414: deadbeef deadbeef deadbeef deadbeef ................
1084e424: deadbeef deadbeef deadbeef deadbeef ................
U-Boot >
1084e434: deadbeef deadbeef deadbeef deadbeef ................
1084e444: deadbeef deadbeef deadbeef deadbeef ................
1084e454: deadbeef deadbeef deadbeef deadbeef ................
1084e464: deadbeef deadbeef deadbeef deadbeef ................
1084e474: deadbeef deadbeef deadbeef deadbeef ................
1084e484: deadbeef deadbeef deadbeef deadbeef ................
1084e494: deadbeef deadbeef deadbeef deadbeef ................
1084e4a4: deadbeef deadbeef deadbeef deadbeef ................
1084e4b4: deadbeef deadbeef deadbeef deadbeef ................
1084e4c4: deadbeef deadbeef deadbeef deadbeef ................
1084e4d4: deadbeef deadbeef deadbeef deadbeef ................
1084e4e4: deadbeef deadbeef deadbeef deadbeef ................
1084e4f4: deadbeef deadbeef deadbeef deadbeef ................
1084e504: deadbeef deadbeef deadbeef deadbeef ................
1084e514: deadbeef deadbeef deadbeef deadbeef ................
1084e524: deadbeef deadbeef deadbeef deadbeef ................
U-Boot >
1084e534: ffffffff ffffffff ffffffff ffffffff ................
1084e544: ffffffff ffffffff ffffffff ffffffff ................
1084e554: ffffffff ffffffff ffffffff ffffffff ................
1084e564: ffffffff ffffffff ffffffff ffffffff ................
1084e574: ffffffff ffffffff ffffffff ffffffff ................
1084e584: ffffffff ffffffff ffffffff ffffffff ................
1084e594: ffffffff ffffffff ffffffff ffffffff ................
1084e5a4: ffffffff ffffffff ffffffff ffffffff ................
1084e5b4: ffffffff ffffffff ffffffff ffffffff ................
1084e5c4: ffffffff ffffffff ffffffff ffffffff ................
1084e5d4: ffffffff ffffffff ffffffff ffffffff ................
1084e5e4: ffffffff ffffffff ffffffff ffffffff ................
1084e5f4: ffffffff ffffffff ffffffff ffffffff ................
1084e604: ffffffff ffffffff ffffffff ffffffff ................
1084e614: ffffffff ffffffff ffffffff ffffffff ................
1084e624: ffffffff ffffffff ffffffff ffffffff ................
And those extra 0x100 bytes are garbage, not from the eprom.
Troy
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] File placement in Soc / board dirs and make issues
2012-10-15 1:24 ` Tom Rini
@ 2012-10-23 6:30 ` Albert ARIBAUD
0 siblings, 0 replies; 430+ messages in thread
From: Albert ARIBAUD @ 2012-10-23 6:30 UTC (permalink / raw)
To: u-boot
Hi Tom,
On Sun, 14 Oct 2012 18:24:58 -0700, Tom Rini <trini@ti.com> wrote:
> On Sun, Oct 14, 2012 at 1:37 AM, Albert ARIBAUD
> <albert.u.boot@aribaud.net> wrote:
> > Hi Tom,
> >
> > (seems like gmail does not honor the rule that replies should drop the
> > "(was: xxxxx)" part in an e-mail subject; but hey, neither does Claws
> > apparently. Sigh.)
> >
> > On Sat, 13 Oct 2012 08:17:41 -0700, Tom Rini <trini@ti.com> wrote:
> >
> >> On Sat, Oct 13, 2012 at 3:11 AM, Albert ARIBAUD
> >> <albert.u.boot@aribaud.net> wrote:
> >> > Hi Tom,
> >> >
> >> > On Thu, 11 Oct 2012 16:15:02 -0700, Tom Rini <trini@ti.com> wrote:
> >> >
> >> >> On Fri, Oct 12, 2012 at 12:27:09AM +0200, stefano babic wrote:
> >> >>
> >> >> [snip]
> >> >> > One reason to move into the board directory is that there was a decision
> >> >> > to move rules related to only one arch or SOC where they belong to, that
> >> >> > is in the corresponding arch/ or board/ directory.
> >> >>
> >> >> I'll admit that maybe my make-fu is off, but that idea doesn't work, at
> >> >> least for SPL. So I'd really like someone to make that work first.
> >> >
> >> > Tom, can you be more specific than 'it doesn't work'? :)
> >> >
> >> > Seriously, though, I'm interested in understand what the make issue is
> >> > there, because I am indeed a proponent of putting files where they
> >> > belong to, so if help is needed there, I would try to.
> >>
> >> I have had no luck moving things like the 'MLO' rule from spl/Makefile
> >> to anywhere else. Same with the 'checkthumb' rule in the top-level
> >> Makefile.
> >
> > Ok, now it is more precise :) but still not enough for me to
> > efficiently try and analyze the issue.
> >
> > Let's take the checkthumb rule. Where did you try to move it?
>
> I tried both arch/arm/config.mk arch/arm/Makefile and couldn't make either work.
Thanks. I'm adding this to my todo list, although not as an immediate
priority.
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V4 00/11] imximage series
2012-10-04 1:47 ` [U-Boot] [PATCH V3 08/32] imximage: make header variable length Troy Kisky
2012-10-20 15:52 ` Stefano Babic
@ 2012-11-28 1:31 ` Troy Kisky
2012-11-28 1:31 ` [U-Boot] [PATCH V4 01/11] imximage: mx53 needs transfer length a multiple of 512 Troy Kisky
` (11 more replies)
1 sibling, 12 replies; 430+ messages in thread
From: Troy Kisky @ 2012-11-28 1:31 UTC (permalink / raw)
To: u-boot
This series make the file imximage.c easier to read, as well
as produces a slightly smaller file.
Only the 1st two patches are different from version 3. The
1st is a new patch which addresses an mx53 ROM bug. The 2nd
is slight changes due to rebase on 1st.
Troy Kisky (11):
imximage: mx53 needs transfer length a multiple of 512
imximage: make header variable length
imximage: remove static imximage_version
imximage: prepare to move static variables to struct data_src
imximage: change parameters for set_dcd_val/set_imx_hdr
imximage: move set_imx_hdr to struct data_src
imximage: move set_dcd_val to struct data_src
imximage: enable word writes for version2 header
tools: add parse_helper file
imximage: use parse_helper functions
parse_helper: add expression evaluation
tools/Makefile | 2 +
tools/imximage.c | 437 ++++++++++++++++++++++----------------------------
tools/imximage.h | 37 ++---
tools/parse_helper.c | 325 +++++++++++++++++++++++++++++++++++++
tools/parse_helper.h | 28 ++++
5 files changed, 564 insertions(+), 265 deletions(-)
create mode 100644 tools/parse_helper.c
create mode 100644 tools/parse_helper.h
--
1.7.9.5
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V4 01/11] imximage: mx53 needs transfer length a multiple of 512
2012-11-28 1:31 ` [U-Boot] [PATCH V4 00/11] imximage series Troy Kisky
@ 2012-11-28 1:31 ` Troy Kisky
2012-11-28 9:27 ` Wolfgang Denk
2012-11-28 10:34 ` Liu Hui-R64343
2012-11-28 1:31 ` [U-Boot] [PATCH V4 02/11] imximage: make header variable length Troy Kisky
` (10 subsequent siblings)
11 siblings, 2 replies; 430+ messages in thread
From: Troy Kisky @ 2012-11-28 1:31 UTC (permalink / raw)
To: u-boot
The mx53 ROM will truncate the length at a multiple of 512.
Transferring too much is not a problem, so round up.
Problem reported by Stefano Babic.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
tools/imximage.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/tools/imximage.c b/tools/imximage.c
index 63f88b6..7e54e97 100644
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -494,6 +494,8 @@ static void imximage_print_header(const void *ptr)
}
}
+#define ALIGN(a, b) (((a) + (b) - 1) & ~((b) - 1))
+
static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd,
struct mkimage_params *params)
{
@@ -515,7 +517,13 @@ static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd,
/* Set the imx header */
(*set_imx_hdr)(imxhdr, dcd_len, params->ep, imxhdr->flash_offset);
- *header_size_ptr = sbuf->st_size + imxhdr->flash_offset;
+ /*
+ * ROM bug alert
+ * mx53 only loads 512 byte multiples.
+ * The remaining fraction of a block bytes would
+ * not be loaded.
+ */
+ *header_size_ptr = ALIGN(sbuf->st_size + imxhdr->flash_offset, 512);
}
int imximage_check_params(struct mkimage_params *params)
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V4 02/11] imximage: make header variable length
2012-11-28 1:31 ` [U-Boot] [PATCH V4 00/11] imximage series Troy Kisky
2012-11-28 1:31 ` [U-Boot] [PATCH V4 01/11] imximage: mx53 needs transfer length a multiple of 512 Troy Kisky
@ 2012-11-28 1:31 ` Troy Kisky
2012-11-28 10:42 ` Liu Hui-R64343
2012-11-28 1:31 ` [U-Boot] [PATCH V4 03/11] imximage: remove static imximage_version Troy Kisky
` (9 subsequent siblings)
11 siblings, 1 reply; 430+ messages in thread
From: Troy Kisky @ 2012-11-28 1:31 UTC (permalink / raw)
To: u-boot
This makes the dcd table optional as well for v2.
Also, the header offset is no longer
right before the code starts.
Before this patch mx53loco_config produces
000000 402000d1 77800000 00000000 777ffc2c
000010 777ffc20 777ffc00 00000000 00000000
000020 777ff800 0004b200 00000000 40a001d2
000030 049c01cc 5485fa53 00003000 5885fa53
... more DCD table
0001c0 27220200 1c90fd63 00000000 00000000
0001d0 00000000 00000000 00000000 00000000
*
0003f0 00000000 00000000 00000000 00000400
000400 ea000014 e59ff014 e59ff014 e59ff014
Notice offset 3fc contains 0x400. This
is the header offset. There is no reason
for this to be in the file, and I have
removed it.
After this patch we have
000000 402000d1 77800000 00000000 777ffe60
000010 777ffe54 777ffe34 00000000 00000000
000020 777ffa34 0004b000 00000000 40a001d2
000030 049c01cc 5485fa53 00003000 5885fa53
... more DCD table
0001c0 27220200 1c90fd63 00000000 ea000014
0001d0 e59ff014 e59ff014 e59ff014 e59ff014
Notice the zeros between 0x1cc and 0x3fb have
been removed.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
v4: updated commit log, minor change to rebase on previous patch
v3: other patches split from this one
---
tools/imximage.c | 65 ++++++++++++++++++++++++++++++++++++------------------
tools/imximage.h | 4 ++--
2 files changed, 46 insertions(+), 23 deletions(-)
diff --git a/tools/imximage.c b/tools/imximage.c
index 7e54e97..8457c8e 100644
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -65,7 +65,6 @@ static table_entry_t imximage_versions[] = {
{-1, "", " (Invalid)", },
};
-static struct imx_header imximage_header;
static uint32_t imximage_version;
static set_dcd_val_t set_dcd_val;
@@ -73,6 +72,9 @@ static set_dcd_rst_t set_dcd_rst;
static set_imx_hdr_t set_imx_hdr;
static uint32_t max_dcd_entries;
static uint32_t *header_size_ptr;
+static uint32_t g_flash_offset;
+
+static struct image_type_params imximage_params;
static uint32_t get_cfg_value(char *token, char *name, int linenr)
{
@@ -102,8 +104,7 @@ static uint32_t detect_imximage_version(struct imx_header *imx_hdr)
return IMXIMAGE_V1;
/* Try to detect V2 */
- if ((fhdr_v2->header.tag == IVT_HEADER_TAG) &&
- (hdr_v2->dcd_table.header.tag == DCD_HEADER_TAG))
+ if (fhdr_v2->header.tag == IVT_HEADER_TAG)
return IMXIMAGE_V2;
return IMXIMAGE_VER_INVALID;
@@ -195,7 +196,7 @@ static void set_dcd_rst_v2(struct imx_header *imxhdr, uint32_t dcd_len,
dcd_v2->write_dcd_command.param = DCD_COMMAND_PARAM;
}
-static void set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,
+static int set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,
uint32_t entry_point, uint32_t flash_offset)
{
imx_header_v1_t *hdr_v1 = &imxhdr->header.hdr_v1;
@@ -208,7 +209,7 @@ static void set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,
/* Set magic number */
fhdr_v1->app_code_barker = APP_CODE_BARKER;
- hdr_base = entry_point - sizeof(struct imx_header);
+ hdr_base = entry_point - header_length;
fhdr_v1->app_dest_ptr = hdr_base - flash_offset;
fhdr_v1->app_code_jump_vector = entry_point;
@@ -219,14 +220,18 @@ static void set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,
fhdr_v1->app_code_csf = 0;
fhdr_v1->super_root_key = 0;
header_size_ptr = (uint32_t *)(((char *)imxhdr) + header_length - 4);
+ return header_length;
}
-static void set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t dcd_len,
+static int set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t dcd_len,
uint32_t entry_point, uint32_t flash_offset)
{
imx_header_v2_t *hdr_v2 = &imxhdr->header.hdr_v2;
flash_header_v2_t *fhdr_v2 = &hdr_v2->fhdr;
uint32_t hdr_base;
+ uint32_t header_length = (dcd_len) ?
+ (char *)&hdr_v2->dcd_table.addr_data[dcd_len] - ((char*)imxhdr)
+ : offsetof(imx_header_v2_t, dcd_table);
/* Set magic number */
fhdr_v2->header.tag = IVT_HEADER_TAG; /* 0xD1 */
@@ -235,9 +240,10 @@ static void set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t dcd_len,
fhdr_v2->entry = entry_point;
fhdr_v2->reserved1 = fhdr_v2->reserved2 = 0;
- fhdr_v2->self = hdr_base = entry_point - sizeof(struct imx_header);
+ fhdr_v2->self = hdr_base = entry_point - header_length;
- fhdr_v2->dcd_ptr = hdr_base + offsetof(imx_header_v2_t, dcd_table);
+ fhdr_v2->dcd_ptr = (dcd_len) ? hdr_base
+ + offsetof(imx_header_v2_t, dcd_table) : 0;
fhdr_v2->boot_data_ptr = hdr_base
+ offsetof(imx_header_v2_t, boot_data);
hdr_v2->boot_data.start = hdr_base - flash_offset;
@@ -245,6 +251,7 @@ static void set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t dcd_len,
/* Security feature are not supported */
fhdr_v2->csf = 0;
header_size_ptr = &hdr_v2->boot_data.size;
+ return header_length;
}
static void set_hdr_func(struct imx_header *imxhdr)
@@ -342,9 +349,9 @@ static void parse_cfg_cmd(struct imx_header *imxhdr, int32_t cmd, char *token,
set_hdr_func(imxhdr);
break;
case CMD_BOOT_FROM:
- imxhdr->flash_offset = get_table_entry_id(imximage_bootops,
+ g_flash_offset = get_table_entry_id(imximage_bootops,
"imximage boot option", token);
- if (imxhdr->flash_offset == -1) {
+ if (g_flash_offset == -1) {
fprintf(stderr, "Error: %s[%d] -Invalid boot device"
"(%s)\n", name, lineno, token);
exit(EXIT_FAILURE);
@@ -449,7 +456,7 @@ static uint32_t parse_cfg_file(struct imx_header *imxhdr, char *name)
fclose(fd);
/* Exit if there is no BOOT_FROM field specifying the flash_offset */
- if (imxhdr->flash_offset == FLASH_OFFSET_UNDEFINED) {
+ if (g_flash_offset == FLASH_OFFSET_UNDEFINED) {
fprintf(stderr, "Error: No BOOT_FROM tag in %s\n", name);
exit(EXIT_FAILURE);
}
@@ -494,14 +501,17 @@ static void imximage_print_header(const void *ptr)
}
}
-#define ALIGN(a, b) (((a) + (b) - 1) & ~((b) - 1))
-
-static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd,
- struct mkimage_params *params)
+int imximage_vrec_header(struct mkimage_params *params,
+ struct image_type_params *tparams)
{
- struct imx_header *imxhdr = (struct imx_header *)ptr;
+ struct imx_header *imxhdr;
uint32_t dcd_len;
+ imxhdr = calloc(1, MAX_HEADER_SIZE);
+ if (!imxhdr) {
+ fprintf(stderr, "Error: out of memory\n");
+ exit(EXIT_FAILURE);
+ }
/*
* In order to not change the old imx cfg file
* by adding VERSION command into it, here need
@@ -509,21 +519,35 @@ static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd,
*/
imximage_version = IMXIMAGE_V1;
/* Be able to detect if the cfg file has no BOOT_FROM tag */
- imxhdr->flash_offset = FLASH_OFFSET_UNDEFINED;
+ g_flash_offset = FLASH_OFFSET_UNDEFINED;
set_hdr_func(imxhdr);
/* Parse dcd configuration file */
dcd_len = parse_cfg_file(imxhdr, params->imagename);
/* Set the imx header */
- (*set_imx_hdr)(imxhdr, dcd_len, params->ep, imxhdr->flash_offset);
+ imximage_params.header_size = (*set_imx_hdr)(imxhdr, dcd_len,
+ params->ep, g_flash_offset);
+ imximage_params.hdr = imxhdr;
+ return 0;
+}
+
+#define ALIGN(a, b) (((a) + (b) - 1) & ~((b) - 1))
+
+static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd,
+ struct mkimage_params *params)
+{
+ /* Set the size in header */
+ uint32_t offset = (char *)header_size_ptr - (char *)imximage_params.hdr;
+ uint32_t *p = (uint32_t *)((char *)ptr + offset);
+
/*
* ROM bug alert
* mx53 only loads 512 byte multiples.
* The remaining fraction of a block bytes would
* not be loaded.
*/
- *header_size_ptr = ALIGN(sbuf->st_size + imxhdr->flash_offset, 512);
+ *p = ALIGN(sbuf->st_size + g_flash_offset, 512);
}
int imximage_check_params(struct mkimage_params *params)
@@ -553,8 +577,7 @@ int imximage_check_params(struct mkimage_params *params)
*/
static struct image_type_params imximage_params = {
.name = "Freescale i.MX 5x Boot Image support",
- .header_size = sizeof(struct imx_header),
- .hdr = (void *)&imximage_header,
+ .vrec_header = imximage_vrec_header,
.check_image_type = imximage_check_image_types,
.verify_header = imximage_verify_header,
.print_header = imximage_print_header,
diff --git a/tools/imximage.h b/tools/imximage.h
index 42b6090..0f39447 100644
--- a/tools/imximage.h
+++ b/tools/imximage.h
@@ -30,6 +30,7 @@
#define DCD_BARKER 0xB17219E9
#define HEADER_OFFSET 0x400
+#define MAX_HEADER_SIZE (16 << 10)
#define CMD_DATA_STR "DATA"
#define FLASH_OFFSET_UNDEFINED 0xFFFFFFFF
@@ -156,7 +157,6 @@ struct imx_header {
imx_header_v1_t hdr_v1;
imx_header_v2_t hdr_v2;
} header;
- uint32_t flash_offset;
};
typedef void (*set_dcd_val_t)(struct imx_header *imxhdr,
@@ -168,7 +168,7 @@ typedef void (*set_dcd_rst_t)(struct imx_header *imxhdr,
uint32_t dcd_len,
char *name, int lineno);
-typedef void (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t dcd_len,
+typedef int (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t dcd_len,
uint32_t entry_point, uint32_t flash_offset);
#endif /* _IMXIMAGE_H_ */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V4 03/11] imximage: remove static imximage_version
2012-11-28 1:31 ` [U-Boot] [PATCH V4 00/11] imximage series Troy Kisky
2012-11-28 1:31 ` [U-Boot] [PATCH V4 01/11] imximage: mx53 needs transfer length a multiple of 512 Troy Kisky
2012-11-28 1:31 ` [U-Boot] [PATCH V4 02/11] imximage: make header variable length Troy Kisky
@ 2012-11-28 1:31 ` Troy Kisky
2012-11-28 10:43 ` Liu Hui-R64343
2012-11-28 1:31 ` [U-Boot] [PATCH V4 04/11] imximage: prepare to move static variables to struct data_src Troy Kisky
` (8 subsequent siblings)
11 siblings, 1 reply; 430+ messages in thread
From: Troy Kisky @ 2012-11-28 1:31 UTC (permalink / raw)
To: u-boot
This variable does not need to have file scope.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
tools/imximage.c | 21 +++++++++------------
1 file changed, 9 insertions(+), 12 deletions(-)
diff --git a/tools/imximage.c b/tools/imximage.c
index 8457c8e..97e5c4b 100644
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -65,8 +65,6 @@ static table_entry_t imximage_versions[] = {
{-1, "", " (Invalid)", },
};
-static uint32_t imximage_version;
-
static set_dcd_val_t set_dcd_val;
static set_dcd_rst_t set_dcd_rst;
static set_imx_hdr_t set_imx_hdr;
@@ -254,7 +252,7 @@ static int set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t dcd_len,
return header_length;
}
-static void set_hdr_func(struct imx_header *imxhdr)
+static void set_hdr_func(struct imx_header *imxhdr, uint32_t imximage_version)
{
switch (imximage_version) {
case IMXIMAGE_V1:
@@ -335,6 +333,7 @@ static void parse_cfg_cmd(struct imx_header *imxhdr, int32_t cmd, char *token,
{
int value;
static int cmd_ver_first = ~0;
+ uint32_t imximage_version;
switch (cmd) {
case CMD_IMAGE_VERSION:
@@ -346,7 +345,7 @@ static void parse_cfg_cmd(struct imx_header *imxhdr, int32_t cmd, char *token,
exit(EXIT_FAILURE);
}
cmd_ver_first = 1;
- set_hdr_func(imxhdr);
+ set_hdr_func(imxhdr, imximage_version);
break;
case CMD_BOOT_FROM:
g_flash_offset = get_table_entry_id(imximage_bootops,
@@ -419,6 +418,12 @@ static uint32_t parse_cfg_file(struct imx_header *imxhdr, char *name)
int dcd_len = 0;
int32_t cmd;
+ /*
+ * In order to not change the old imx cfg file
+ * by adding VERSION command into it, here need
+ * set up function ptr group to V1 by default.
+ */
+ set_hdr_func(imxhdr, IMXIMAGE_V1);
fd = fopen(name, "r");
if (fd == 0) {
fprintf(stderr, "Error: %s - Can't open DCD file\n", name);
@@ -512,16 +517,8 @@ int imximage_vrec_header(struct mkimage_params *params,
fprintf(stderr, "Error: out of memory\n");
exit(EXIT_FAILURE);
}
- /*
- * In order to not change the old imx cfg file
- * by adding VERSION command into it, here need
- * set up function ptr group to V1 by default.
- */
- imximage_version = IMXIMAGE_V1;
/* Be able to detect if the cfg file has no BOOT_FROM tag */
g_flash_offset = FLASH_OFFSET_UNDEFINED;
- set_hdr_func(imxhdr);
-
/* Parse dcd configuration file */
dcd_len = parse_cfg_file(imxhdr, params->imagename);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V4 04/11] imximage: prepare to move static variables to struct data_src
2012-11-28 1:31 ` [U-Boot] [PATCH V4 00/11] imximage series Troy Kisky
` (2 preceding siblings ...)
2012-11-28 1:31 ` [U-Boot] [PATCH V4 03/11] imximage: remove static imximage_version Troy Kisky
@ 2012-11-28 1:31 ` Troy Kisky
2012-11-28 9:38 ` Wolfgang Denk
2012-11-28 1:31 ` [U-Boot] [PATCH V4 05/11] imximage: change parameters for set_dcd_val/set_imx_hdr Troy Kisky
` (7 subsequent siblings)
11 siblings, 1 reply; 430+ messages in thread
From: Troy Kisky @ 2012-11-28 1:31 UTC (permalink / raw)
To: u-boot
Need to move accesses to the static variables to
a function where struct data_src is used.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
v3: new patch
---
tools/imximage.c | 24 +++++++++++++-----------
tools/imximage.h | 3 +++
2 files changed, 16 insertions(+), 11 deletions(-)
diff --git a/tools/imximage.c b/tools/imximage.c
index 97e5c4b..3a010a6 100644
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -407,8 +407,11 @@ static void parse_cfg_fld(struct imx_header *imxhdr, int32_t *cmd,
break;
}
}
-static uint32_t parse_cfg_file(struct imx_header *imxhdr, char *name)
+
+static int parse_cfg_file(struct imx_header *imxhdr, char *name,
+ uint32_t entry_point)
{
+ struct data_src ds;
FILE *fd = NULL;
char *line = NULL;
char *token, *saveptr1, *saveptr2;
@@ -418,6 +421,10 @@ static uint32_t parse_cfg_file(struct imx_header *imxhdr, char *name)
int dcd_len = 0;
int32_t cmd;
+ /* Be able to detect if the cfg file has no BOOT_FROM tag */
+ g_flash_offset = FLASH_OFFSET_UNDEFINED;
+ memset(&ds, 0, sizeof(struct data_src));
+ ds.imxhdr = imxhdr;
/*
* In order to not change the old imx cfg file
* by adding VERSION command into it, here need
@@ -465,10 +472,10 @@ static uint32_t parse_cfg_file(struct imx_header *imxhdr, char *name)
fprintf(stderr, "Error: No BOOT_FROM tag in %s\n", name);
exit(EXIT_FAILURE);
}
- return dcd_len;
+ /* Set the imx header */
+ return (*set_imx_hdr)(imxhdr, dcd_len, entry_point, g_flash_offset);
}
-
static int imximage_check_image_types(uint8_t type)
{
if (type == IH_TYPE_IMXIMAGE)
@@ -510,21 +517,16 @@ int imximage_vrec_header(struct mkimage_params *params,
struct image_type_params *tparams)
{
struct imx_header *imxhdr;
- uint32_t dcd_len;
imxhdr = calloc(1, MAX_HEADER_SIZE);
if (!imxhdr) {
fprintf(stderr, "Error: out of memory\n");
exit(EXIT_FAILURE);
}
- /* Be able to detect if the cfg file has no BOOT_FROM tag */
- g_flash_offset = FLASH_OFFSET_UNDEFINED;
- /* Parse dcd configuration file */
- dcd_len = parse_cfg_file(imxhdr, params->imagename);
- /* Set the imx header */
- imximage_params.header_size = (*set_imx_hdr)(imxhdr, dcd_len,
- params->ep, g_flash_offset);
+ /* Parse dcd configuration file */
+ imximage_params.header_size = parse_cfg_file(imxhdr, params->imagename,
+ params->ep);
imximage_params.hdr = imxhdr;
return 0;
}
diff --git a/tools/imximage.h b/tools/imximage.h
index 0f39447..2895378 100644
--- a/tools/imximage.h
+++ b/tools/imximage.h
@@ -171,4 +171,7 @@ typedef void (*set_dcd_rst_t)(struct imx_header *imxhdr,
typedef int (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t dcd_len,
uint32_t entry_point, uint32_t flash_offset);
+struct data_src {
+ struct imx_header *imxhdr;
+};
#endif /* _IMXIMAGE_H_ */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V4 05/11] imximage: change parameters for set_dcd_val/set_imx_hdr
2012-11-28 1:31 ` [U-Boot] [PATCH V4 00/11] imximage series Troy Kisky
` (3 preceding siblings ...)
2012-11-28 1:31 ` [U-Boot] [PATCH V4 04/11] imximage: prepare to move static variables to struct data_src Troy Kisky
@ 2012-11-28 1:31 ` Troy Kisky
2012-11-28 10:43 ` Liu Hui-R64343
2012-11-28 1:31 ` [U-Boot] [PATCH V4 06/11] imximage: move set_imx_hdr to struct data_src Troy Kisky
` (6 subsequent siblings)
11 siblings, 1 reply; 430+ messages in thread
From: Troy Kisky @ 2012-11-28 1:31 UTC (permalink / raw)
To: u-boot
Change 1st argument of set_imx_hdr/set_dcd_val
to struct data_src.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
tools/imximage.c | 41 +++++++++++++++++++++--------------------
tools/imximage.h | 5 +++--
2 files changed, 24 insertions(+), 22 deletions(-)
diff --git a/tools/imximage.c b/tools/imximage.c
index 3a010a6..ddac95f 100644
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -116,10 +116,10 @@ static void err_imximage_version(int version)
exit(EXIT_FAILURE);
}
-static void set_dcd_val_v1(struct imx_header *imxhdr, char *name, int lineno,
+static void set_dcd_val_v1(struct data_src *ds, char *name, int lineno,
int fld, uint32_t value, uint32_t off)
{
- dcd_v1_t *dcd_v1 = &imxhdr->header.hdr_v1.dcd_table;
+ dcd_v1_t *dcd_v1 = &ds->imxhdr->header.hdr_v1.dcd_table;
switch (fld) {
case CFG_REG_SIZE:
@@ -144,10 +144,10 @@ static void set_dcd_val_v1(struct imx_header *imxhdr, char *name, int lineno,
}
}
-static void set_dcd_val_v2(struct imx_header *imxhdr, char *name, int lineno,
+static void set_dcd_val_v2(struct data_src *ds, char *name, int lineno,
int fld, uint32_t value, uint32_t off)
{
- dcd_v2_t *dcd_v2 = &imxhdr->header.hdr_v2.dcd_table;
+ dcd_v2_t *dcd_v2 = &ds->imxhdr->header.hdr_v2.dcd_table;
switch (fld) {
case CFG_REG_ADDRESS:
@@ -194,15 +194,15 @@ static void set_dcd_rst_v2(struct imx_header *imxhdr, uint32_t dcd_len,
dcd_v2->write_dcd_command.param = DCD_COMMAND_PARAM;
}
-static int set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,
+static int set_imx_hdr_v1(struct data_src *ds, uint32_t dcd_len,
uint32_t entry_point, uint32_t flash_offset)
{
- imx_header_v1_t *hdr_v1 = &imxhdr->header.hdr_v1;
+ imx_header_v1_t *hdr_v1 = &ds->imxhdr->header.hdr_v1;
flash_header_v1_t *fhdr_v1 = &hdr_v1->fhdr;
dcd_v1_t *dcd_v1 = &hdr_v1->dcd_table;
uint32_t hdr_base;
uint32_t header_length = (((char *)&dcd_v1->addr_data[dcd_len].addr)
- - ((char *)imxhdr));
+ - ((char *)ds->imxhdr));
/* Set magic number */
fhdr_v1->app_code_barker = APP_CODE_BARKER;
@@ -217,19 +217,20 @@ static int set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,
/* Security feature are not supported */
fhdr_v1->app_code_csf = 0;
fhdr_v1->super_root_key = 0;
- header_size_ptr = (uint32_t *)(((char *)imxhdr) + header_length - 4);
+ header_size_ptr = (uint32_t *)(((char *)ds->imxhdr) +
+ header_length - 4);
return header_length;
}
-static int set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t dcd_len,
+static int set_imx_hdr_v2(struct data_src *ds, uint32_t dcd_len,
uint32_t entry_point, uint32_t flash_offset)
{
- imx_header_v2_t *hdr_v2 = &imxhdr->header.hdr_v2;
+ imx_header_v2_t *hdr_v2 = &ds->imxhdr->header.hdr_v2;
flash_header_v2_t *fhdr_v2 = &hdr_v2->fhdr;
uint32_t hdr_base;
uint32_t header_length = (dcd_len) ?
- (char *)&hdr_v2->dcd_table.addr_data[dcd_len] - ((char*)imxhdr)
- : offsetof(imx_header_v2_t, dcd_table);
+ (char *)&hdr_v2->dcd_table.addr_data[dcd_len] -
+ ((char *)ds->imxhdr) : offsetof(imx_header_v2_t, dcd_table);
/* Set magic number */
fhdr_v2->header.tag = IVT_HEADER_TAG; /* 0xD1 */
@@ -328,7 +329,7 @@ static void print_hdr_v2(struct imx_header *imx_hdr)
printf("Entry Point: %08x\n", (uint32_t)fhdr_v2->entry);
}
-static void parse_cfg_cmd(struct imx_header *imxhdr, int32_t cmd, char *token,
+static void parse_cfg_cmd(struct data_src *ds, int32_t cmd, char *token,
char *name, int lineno, int fld, int dcd_len)
{
int value;
@@ -345,7 +346,7 @@ static void parse_cfg_cmd(struct imx_header *imxhdr, int32_t cmd, char *token,
exit(EXIT_FAILURE);
}
cmd_ver_first = 1;
- set_hdr_func(imxhdr, imximage_version);
+ set_hdr_func(ds->imxhdr, imximage_version);
break;
case CMD_BOOT_FROM:
g_flash_offset = get_table_entry_id(imximage_bootops,
@@ -360,14 +361,14 @@ static void parse_cfg_cmd(struct imx_header *imxhdr, int32_t cmd, char *token,
break;
case CMD_DATA:
value = get_cfg_value(token, name, lineno);
- (*set_dcd_val)(imxhdr, name, lineno, fld, value, dcd_len);
+ (*set_dcd_val)(ds, name, lineno, fld, value, dcd_len);
if (unlikely(cmd_ver_first != 1))
cmd_ver_first = 0;
break;
}
}
-static void parse_cfg_fld(struct imx_header *imxhdr, int32_t *cmd,
+static void parse_cfg_fld(struct data_src *ds, int32_t *cmd,
char *token, char *name, int lineno, int fld, int *dcd_len)
{
int value;
@@ -383,7 +384,7 @@ static void parse_cfg_fld(struct imx_header *imxhdr, int32_t *cmd,
}
break;
case CFG_REG_SIZE:
- parse_cfg_cmd(imxhdr, *cmd, token, name, lineno, fld, *dcd_len);
+ parse_cfg_cmd(ds, *cmd, token, name, lineno, fld, *dcd_len);
break;
case CFG_REG_ADDRESS:
case CFG_REG_VALUE:
@@ -391,7 +392,7 @@ static void parse_cfg_fld(struct imx_header *imxhdr, int32_t *cmd,
return;
value = get_cfg_value(token, name, lineno);
- (*set_dcd_val)(imxhdr, name, lineno, fld, value, *dcd_len);
+ (*set_dcd_val)(ds, name, lineno, fld, value, *dcd_len);
if (fld == CFG_REG_VALUE) {
(*dcd_len)++;
@@ -458,7 +459,7 @@ static int parse_cfg_file(struct imx_header *imxhdr, char *name,
if (token[0] == '#')
break;
- parse_cfg_fld(imxhdr, &cmd, token, name,
+ parse_cfg_fld(&ds, &cmd, token, name,
lineno, fld, &dcd_len);
}
@@ -473,7 +474,7 @@ static int parse_cfg_file(struct imx_header *imxhdr, char *name,
exit(EXIT_FAILURE);
}
/* Set the imx header */
- return (*set_imx_hdr)(imxhdr, dcd_len, entry_point, g_flash_offset);
+ return (*set_imx_hdr)(&ds, dcd_len, entry_point, g_flash_offset);
}
static int imximage_check_image_types(uint8_t type)
diff --git a/tools/imximage.h b/tools/imximage.h
index 2895378..3054d55 100644
--- a/tools/imximage.h
+++ b/tools/imximage.h
@@ -159,7 +159,8 @@ struct imx_header {
} header;
};
-typedef void (*set_dcd_val_t)(struct imx_header *imxhdr,
+struct data_src;
+typedef void (*set_dcd_val_t)(struct data_src *ds,
char *name, int lineno,
int fld, uint32_t value,
uint32_t off);
@@ -168,7 +169,7 @@ typedef void (*set_dcd_rst_t)(struct imx_header *imxhdr,
uint32_t dcd_len,
char *name, int lineno);
-typedef int (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t dcd_len,
+typedef int (*set_imx_hdr_t)(struct data_src *ds, uint32_t dcd_len,
uint32_t entry_point, uint32_t flash_offset);
struct data_src {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V4 06/11] imximage: move set_imx_hdr to struct data_src
2012-11-28 1:31 ` [U-Boot] [PATCH V4 00/11] imximage series Troy Kisky
` (4 preceding siblings ...)
2012-11-28 1:31 ` [U-Boot] [PATCH V4 05/11] imximage: change parameters for set_dcd_val/set_imx_hdr Troy Kisky
@ 2012-11-28 1:31 ` Troy Kisky
2012-11-28 10:45 ` Liu Hui-R64343
2012-11-28 1:31 ` [U-Boot] [PATCH V4 07/11] imximage: move set_dcd_val " Troy Kisky
` (5 subsequent siblings)
11 siblings, 1 reply; 430+ messages in thread
From: Troy Kisky @ 2012-11-28 1:31 UTC (permalink / raw)
To: u-boot
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
v3: new patch
---
tools/imximage.c | 13 ++++++-------
tools/imximage.h | 1 +
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/tools/imximage.c b/tools/imximage.c
index ddac95f..30f3c81 100644
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -67,7 +67,6 @@ static table_entry_t imximage_versions[] = {
static set_dcd_val_t set_dcd_val;
static set_dcd_rst_t set_dcd_rst;
-static set_imx_hdr_t set_imx_hdr;
static uint32_t max_dcd_entries;
static uint32_t *header_size_ptr;
static uint32_t g_flash_offset;
@@ -253,19 +252,19 @@ static int set_imx_hdr_v2(struct data_src *ds, uint32_t dcd_len,
return header_length;
}
-static void set_hdr_func(struct imx_header *imxhdr, uint32_t imximage_version)
+static void set_hdr_func(struct data_src *ds, uint32_t imximage_version)
{
switch (imximage_version) {
case IMXIMAGE_V1:
set_dcd_val = set_dcd_val_v1;
set_dcd_rst = set_dcd_rst_v1;
- set_imx_hdr = set_imx_hdr_v1;
+ ds->set_imx_hdr = set_imx_hdr_v1;
max_dcd_entries = MAX_HW_CFG_SIZE_V1;
break;
case IMXIMAGE_V2:
set_dcd_val = set_dcd_val_v2;
set_dcd_rst = set_dcd_rst_v2;
- set_imx_hdr = set_imx_hdr_v2;
+ ds->set_imx_hdr = set_imx_hdr_v2;
max_dcd_entries = MAX_HW_CFG_SIZE_V2;
break;
default:
@@ -346,7 +345,7 @@ static void parse_cfg_cmd(struct data_src *ds, int32_t cmd, char *token,
exit(EXIT_FAILURE);
}
cmd_ver_first = 1;
- set_hdr_func(ds->imxhdr, imximage_version);
+ set_hdr_func(ds, imximage_version);
break;
case CMD_BOOT_FROM:
g_flash_offset = get_table_entry_id(imximage_bootops,
@@ -431,7 +430,7 @@ static int parse_cfg_file(struct imx_header *imxhdr, char *name,
* by adding VERSION command into it, here need
* set up function ptr group to V1 by default.
*/
- set_hdr_func(imxhdr, IMXIMAGE_V1);
+ set_hdr_func(&ds, IMXIMAGE_V1);
fd = fopen(name, "r");
if (fd == 0) {
fprintf(stderr, "Error: %s - Can't open DCD file\n", name);
@@ -474,7 +473,7 @@ static int parse_cfg_file(struct imx_header *imxhdr, char *name,
exit(EXIT_FAILURE);
}
/* Set the imx header */
- return (*set_imx_hdr)(&ds, dcd_len, entry_point, g_flash_offset);
+ return (*ds.set_imx_hdr)(&ds, dcd_len, entry_point, g_flash_offset);
}
static int imximage_check_image_types(uint8_t type)
diff --git a/tools/imximage.h b/tools/imximage.h
index 3054d55..f27a2ef 100644
--- a/tools/imximage.h
+++ b/tools/imximage.h
@@ -174,5 +174,6 @@ typedef int (*set_imx_hdr_t)(struct data_src *ds, uint32_t dcd_len,
struct data_src {
struct imx_header *imxhdr;
+ set_imx_hdr_t set_imx_hdr;
};
#endif /* _IMXIMAGE_H_ */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V4 07/11] imximage: move set_dcd_val to struct data_src
2012-11-28 1:31 ` [U-Boot] [PATCH V4 00/11] imximage series Troy Kisky
` (5 preceding siblings ...)
2012-11-28 1:31 ` [U-Boot] [PATCH V4 06/11] imximage: move set_imx_hdr to struct data_src Troy Kisky
@ 2012-11-28 1:31 ` Troy Kisky
2012-11-28 10:47 ` Liu Hui-R64343
2012-11-28 1:31 ` [U-Boot] [PATCH V4 08/11] imximage: enable word writes for version2 header Troy Kisky
` (4 subsequent siblings)
11 siblings, 1 reply; 430+ messages in thread
From: Troy Kisky @ 2012-11-28 1:31 UTC (permalink / raw)
To: u-boot
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
v3: new patch
---
tools/imximage.c | 9 ++++-----
tools/imximage.h | 1 +
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/tools/imximage.c b/tools/imximage.c
index 30f3c81..6d5cfa7 100644
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -65,7 +65,6 @@ static table_entry_t imximage_versions[] = {
{-1, "", " (Invalid)", },
};
-static set_dcd_val_t set_dcd_val;
static set_dcd_rst_t set_dcd_rst;
static uint32_t max_dcd_entries;
static uint32_t *header_size_ptr;
@@ -256,13 +255,13 @@ static void set_hdr_func(struct data_src *ds, uint32_t imximage_version)
{
switch (imximage_version) {
case IMXIMAGE_V1:
- set_dcd_val = set_dcd_val_v1;
+ ds->set_dcd_val = set_dcd_val_v1;
set_dcd_rst = set_dcd_rst_v1;
ds->set_imx_hdr = set_imx_hdr_v1;
max_dcd_entries = MAX_HW_CFG_SIZE_V1;
break;
case IMXIMAGE_V2:
- set_dcd_val = set_dcd_val_v2;
+ ds->set_dcd_val = set_dcd_val_v2;
set_dcd_rst = set_dcd_rst_v2;
ds->set_imx_hdr = set_imx_hdr_v2;
max_dcd_entries = MAX_HW_CFG_SIZE_V2;
@@ -360,7 +359,7 @@ static void parse_cfg_cmd(struct data_src *ds, int32_t cmd, char *token,
break;
case CMD_DATA:
value = get_cfg_value(token, name, lineno);
- (*set_dcd_val)(ds, name, lineno, fld, value, dcd_len);
+ (*ds->set_dcd_val)(ds, name, lineno, fld, value, dcd_len);
if (unlikely(cmd_ver_first != 1))
cmd_ver_first = 0;
break;
@@ -391,7 +390,7 @@ static void parse_cfg_fld(struct data_src *ds, int32_t *cmd,
return;
value = get_cfg_value(token, name, lineno);
- (*set_dcd_val)(ds, name, lineno, fld, value, *dcd_len);
+ (*ds->set_dcd_val)(ds, name, lineno, fld, value, *dcd_len);
if (fld == CFG_REG_VALUE) {
(*dcd_len)++;
diff --git a/tools/imximage.h b/tools/imximage.h
index f27a2ef..444ddce 100644
--- a/tools/imximage.h
+++ b/tools/imximage.h
@@ -175,5 +175,6 @@ typedef int (*set_imx_hdr_t)(struct data_src *ds, uint32_t dcd_len,
struct data_src {
struct imx_header *imxhdr;
set_imx_hdr_t set_imx_hdr;
+ set_dcd_val_t set_dcd_val;
};
#endif /* _IMXIMAGE_H_ */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V4 08/11] imximage: enable word writes for version2 header
2012-11-28 1:31 ` [U-Boot] [PATCH V4 00/11] imximage series Troy Kisky
` (6 preceding siblings ...)
2012-11-28 1:31 ` [U-Boot] [PATCH V4 07/11] imximage: move set_dcd_val " Troy Kisky
@ 2012-11-28 1:31 ` Troy Kisky
2012-11-28 9:39 ` Wolfgang Denk
2012-11-28 10:47 ` Liu Hui-R64343
2012-11-28 1:31 ` [U-Boot] [PATCH V4 09/11] tools: add parse_helper file Troy Kisky
` (3 subsequent siblings)
11 siblings, 2 replies; 430+ messages in thread
From: Troy Kisky @ 2012-11-28 1:31 UTC (permalink / raw)
To: u-boot
Before, only 1 write_dcd_command table was built.
Now, a new table is built when the size changes.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
v3: moved static variables together
---
tools/imximage.c | 143 ++++++++++++++++++++++++++----------------------------
tools/imximage.h | 18 +++----
2 files changed, 76 insertions(+), 85 deletions(-)
diff --git a/tools/imximage.c b/tools/imximage.c
index 6d5cfa7..2f5ee14 100644
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -65,8 +65,6 @@ static table_entry_t imximage_versions[] = {
{-1, "", " (Invalid)", },
};
-static set_dcd_rst_t set_dcd_rst;
-static uint32_t max_dcd_entries;
static uint32_t *header_size_ptr;
static uint32_t g_flash_offset;
@@ -115,7 +113,7 @@ static void err_imximage_version(int version)
}
static void set_dcd_val_v1(struct data_src *ds, char *name, int lineno,
- int fld, uint32_t value, uint32_t off)
+ int fld, uint32_t value)
{
dcd_v1_t *dcd_v1 = &ds->imxhdr->header.hdr_v1.dcd_table;
@@ -128,13 +126,15 @@ static void set_dcd_val_v1(struct data_src *ds, char *name, int lineno,
name, lineno, value);
exit(EXIT_FAILURE);
}
- dcd_v1->addr_data[off].type = value;
+ *ds->p_entry++ = value;
break;
case CFG_REG_ADDRESS:
- dcd_v1->addr_data[off].addr = value;
+ *ds->p_entry++ = value;
break;
case CFG_REG_VALUE:
- dcd_v1->addr_data[off].value = value;
+ *ds->p_entry++ = value;
+ dcd_v1->preamble.length = (char *)ds->p_entry
+ - (char *)&dcd_v1->addr_data[0].type;
break;
default:
break;
@@ -143,16 +143,42 @@ static void set_dcd_val_v1(struct data_src *ds, char *name, int lineno,
}
static void set_dcd_val_v2(struct data_src *ds, char *name, int lineno,
- int fld, uint32_t value, uint32_t off)
+ int fld, uint32_t value)
{
+ uint32_t len;
dcd_v2_t *dcd_v2 = &ds->imxhdr->header.hdr_v2.dcd_table;
switch (fld) {
+ case CFG_REG_SIZE:
+ /* Byte, halfword, word */
+ if ((value != 1) && (value != 2) && (value != 4)) {
+ fprintf(stderr, "Error: %s[%d] - "
+ "Invalid register size " "(%d)\n",
+ name, lineno, value);
+ exit(EXIT_FAILURE);
+ }
+ if (ds->p_dcd && (ds->p_dcd->param == value))
+ break;
+ if (!ds->p_dcd) {
+ dcd_v2->header.tag = DCD_HEADER_TAG;
+ dcd_v2->header.version = DCD_VERSION;
+ ds->p_dcd = &dcd_v2->write_dcd_command;
+ } else {
+ ds->p_dcd = (write_dcd_command_t *)ds->p_entry;
+ }
+ ds->p_dcd->param = value;
+ ds->p_dcd->tag = DCD_COMMAND_TAG;
+ ds->p_entry = (uint32_t *)(ds->p_dcd + 1);
+ break;
case CFG_REG_ADDRESS:
- dcd_v2->addr_data[off].addr = cpu_to_be32(value);
+ *ds->p_entry++ = cpu_to_be32(value);
break;
case CFG_REG_VALUE:
- dcd_v2->addr_data[off].value = cpu_to_be32(value);
+ *ds->p_entry++ = cpu_to_be32(value);
+ len = (char *)ds->p_entry - (char *)&dcd_v2->header;
+ dcd_v2->header.length = cpu_to_be16(len);
+ len = (char *)ds->p_entry - (char *)ds->p_dcd;
+ ds->p_dcd->length = cpu_to_be16(len);
break;
default:
break;
@@ -160,47 +186,14 @@ static void set_dcd_val_v2(struct data_src *ds, char *name, int lineno,
}
}
-/*
- * Complete setting up the rest field of DCD of V1
- * such as barker code and DCD data length.
- */
-static void set_dcd_rst_v1(struct imx_header *imxhdr, uint32_t dcd_len,
- char *name, int lineno)
-{
- dcd_v1_t *dcd_v1 = &imxhdr->header.hdr_v1.dcd_table;
-
- dcd_v1->preamble.barker = DCD_BARKER;
- dcd_v1->preamble.length = dcd_len * sizeof(dcd_type_addr_data_t);
-}
-
-/*
- * Complete setting up the reset field of DCD of V2
- * such as DCD tag, version, length, etc.
- */
-static void set_dcd_rst_v2(struct imx_header *imxhdr, uint32_t dcd_len,
- char *name, int lineno)
-{
- dcd_v2_t *dcd_v2 = &imxhdr->header.hdr_v2.dcd_table;
-
- dcd_v2->header.tag = DCD_HEADER_TAG;
- dcd_v2->header.length = cpu_to_be16(
- dcd_len * sizeof(dcd_addr_data_t) + 8);
- dcd_v2->header.version = DCD_VERSION;
- dcd_v2->write_dcd_command.tag = DCD_COMMAND_TAG;
- dcd_v2->write_dcd_command.length = cpu_to_be16(
- dcd_len * sizeof(dcd_addr_data_t) + 4);
- dcd_v2->write_dcd_command.param = DCD_COMMAND_PARAM;
-}
-
-static int set_imx_hdr_v1(struct data_src *ds, uint32_t dcd_len,
+static int set_imx_hdr_v1(struct data_src *ds,
uint32_t entry_point, uint32_t flash_offset)
{
imx_header_v1_t *hdr_v1 = &ds->imxhdr->header.hdr_v1;
flash_header_v1_t *fhdr_v1 = &hdr_v1->fhdr;
- dcd_v1_t *dcd_v1 = &hdr_v1->dcd_table;
uint32_t hdr_base;
- uint32_t header_length = (((char *)&dcd_v1->addr_data[dcd_len].addr)
- - ((char *)ds->imxhdr));
+ uint32_t header_length = ((char *)ds->p_entry) + 4
+ - ((char *)ds->imxhdr);
/* Set magic number */
fhdr_v1->app_code_barker = APP_CODE_BARKER;
@@ -220,15 +213,13 @@ static int set_imx_hdr_v1(struct data_src *ds, uint32_t dcd_len,
return header_length;
}
-static int set_imx_hdr_v2(struct data_src *ds, uint32_t dcd_len,
+static int set_imx_hdr_v2(struct data_src *ds,
uint32_t entry_point, uint32_t flash_offset)
{
imx_header_v2_t *hdr_v2 = &ds->imxhdr->header.hdr_v2;
flash_header_v2_t *fhdr_v2 = &hdr_v2->fhdr;
uint32_t hdr_base;
- uint32_t header_length = (dcd_len) ?
- (char *)&hdr_v2->dcd_table.addr_data[dcd_len] -
- ((char *)ds->imxhdr) : offsetof(imx_header_v2_t, dcd_table);
+ uint32_t header_length = ((char *)ds->p_entry) - ((char *)ds->imxhdr);
/* Set magic number */
fhdr_v2->header.tag = IVT_HEADER_TAG; /* 0xD1 */
@@ -239,7 +230,7 @@ static int set_imx_hdr_v2(struct data_src *ds, uint32_t dcd_len,
fhdr_v2->reserved1 = fhdr_v2->reserved2 = 0;
fhdr_v2->self = hdr_base = entry_point - header_length;
- fhdr_v2->dcd_ptr = (dcd_len) ? hdr_base
+ fhdr_v2->dcd_ptr = (ds->p_dcd) ? hdr_base
+ offsetof(imx_header_v2_t, dcd_table) : 0;
fhdr_v2->boot_data_ptr = hdr_base
+ offsetof(imx_header_v2_t, boot_data);
@@ -256,15 +247,20 @@ static void set_hdr_func(struct data_src *ds, uint32_t imximage_version)
switch (imximage_version) {
case IMXIMAGE_V1:
ds->set_dcd_val = set_dcd_val_v1;
- set_dcd_rst = set_dcd_rst_v1;
ds->set_imx_hdr = set_imx_hdr_v1;
- max_dcd_entries = MAX_HW_CFG_SIZE_V1;
+ ds->p_entry = &ds->imxhdr->header.hdr_v1.dcd_table
+ .addr_data[0].type;
+ ds->p_max_dcd = &ds->imxhdr->header.hdr_v1.dcd_table
+ .addr_data[MAX_HW_CFG_SIZE_V1].type;
+ ds->imxhdr->header.hdr_v1.dcd_table.preamble.barker =
+ DCD_BARKER;
break;
case IMXIMAGE_V2:
ds->set_dcd_val = set_dcd_val_v2;
- set_dcd_rst = set_dcd_rst_v2;
ds->set_imx_hdr = set_imx_hdr_v2;
- max_dcd_entries = MAX_HW_CFG_SIZE_V2;
+ ds->p_entry = (uint32_t *)&ds->imxhdr->header.hdr_v2.dcd_table;
+ ds->p_max_dcd = (uint32_t *)
+ ((char *)ds->imxhdr + MAX_HEADER_SIZE);
break;
default:
err_imximage_version(imximage_version);
@@ -328,7 +324,7 @@ static void print_hdr_v2(struct imx_header *imx_hdr)
}
static void parse_cfg_cmd(struct data_src *ds, int32_t cmd, char *token,
- char *name, int lineno, int fld, int dcd_len)
+ char *name, int lineno, int fld)
{
int value;
static int cmd_ver_first = ~0;
@@ -359,7 +355,7 @@ static void parse_cfg_cmd(struct data_src *ds, int32_t cmd, char *token,
break;
case CMD_DATA:
value = get_cfg_value(token, name, lineno);
- (*ds->set_dcd_val)(ds, name, lineno, fld, value, dcd_len);
+ (*ds->set_dcd_val)(ds, name, lineno, fld, value);
if (unlikely(cmd_ver_first != 1))
cmd_ver_first = 0;
break;
@@ -367,7 +363,7 @@ static void parse_cfg_cmd(struct data_src *ds, int32_t cmd, char *token,
}
static void parse_cfg_fld(struct data_src *ds, int32_t *cmd,
- char *token, char *name, int lineno, int fld, int *dcd_len)
+ char *token, char *name, int lineno, int fld)
{
int value;
@@ -382,7 +378,7 @@ static void parse_cfg_fld(struct data_src *ds, int32_t *cmd,
}
break;
case CFG_REG_SIZE:
- parse_cfg_cmd(ds, *cmd, token, name, lineno, fld, *dcd_len);
+ parse_cfg_cmd(ds, *cmd, token, name, lineno, fld);
break;
case CFG_REG_ADDRESS:
case CFG_REG_VALUE:
@@ -390,16 +386,14 @@ static void parse_cfg_fld(struct data_src *ds, int32_t *cmd,
return;
value = get_cfg_value(token, name, lineno);
- (*ds->set_dcd_val)(ds, name, lineno, fld, value, *dcd_len);
-
- if (fld == CFG_REG_VALUE) {
- (*dcd_len)++;
- if (*dcd_len > max_dcd_entries) {
- fprintf(stderr, "Error: %s[%d] -"
- "DCD table exceeds maximum size(%d)\n",
- name, lineno, max_dcd_entries);
- exit(EXIT_FAILURE);
- }
+ (*ds->set_dcd_val)(ds, name, lineno, fld, value);
+ if (ds->p_entry > ds->p_max_dcd) {
+ uint32_t size = (char *)ds->p_max_dcd -
+ (char *)ds->imxhdr;
+ fprintf(stderr, "Error: %s[%d] -"
+ "header exceeds maximum size(%d)\n",
+ name, lineno, size);
+ exit(EXIT_FAILURE);
}
break;
default:
@@ -417,7 +411,6 @@ static int parse_cfg_file(struct imx_header *imxhdr, char *name,
int lineno = 0;
int fld;
size_t len;
- int dcd_len = 0;
int32_t cmd;
/* Be able to detect if the cfg file has no BOOT_FROM tag */
@@ -458,12 +451,10 @@ static int parse_cfg_file(struct imx_header *imxhdr, char *name,
break;
parse_cfg_fld(&ds, &cmd, token, name,
- lineno, fld, &dcd_len);
+ lineno, fld);
}
}
-
- (*set_dcd_rst)(imxhdr, dcd_len, name, lineno);
fclose(fd);
/* Exit if there is no BOOT_FROM field specifying the flash_offset */
@@ -472,7 +463,7 @@ static int parse_cfg_file(struct imx_header *imxhdr, char *name,
exit(EXIT_FAILURE);
}
/* Set the imx header */
- return (*ds.set_imx_hdr)(&ds, dcd_len, entry_point, g_flash_offset);
+ return (*ds.set_imx_hdr)(&ds, entry_point, g_flash_offset);
}
static int imximage_check_image_types(uint8_t type)
@@ -517,7 +508,11 @@ int imximage_vrec_header(struct mkimage_params *params,
{
struct imx_header *imxhdr;
- imxhdr = calloc(1, MAX_HEADER_SIZE);
+ /*
+ * A little extra space to avoid access violation on dcd table overflow.
+ * Overflow is checked after entry is added.
+ */
+ imxhdr = calloc(1, MAX_HEADER_SIZE + 32);
if (!imxhdr) {
fprintf(stderr, "Error: out of memory\n");
exit(EXIT_FAILURE);
diff --git a/tools/imximage.h b/tools/imximage.h
index 444ddce..196bb51 100644
--- a/tools/imximage.h
+++ b/tools/imximage.h
@@ -47,7 +47,6 @@
#define DCD_HEADER_TAG 0xD2
#define DCD_COMMAND_TAG 0xCC
#define DCD_VERSION 0x40
-#define DCD_COMMAND_PARAM 0x4
enum imximage_cmd {
CMD_INVALID,
@@ -160,21 +159,18 @@ struct imx_header {
};
struct data_src;
-typedef void (*set_dcd_val_t)(struct data_src *ds,
- char *name, int lineno,
- int fld, uint32_t value,
- uint32_t off);
+typedef void (*set_dcd_val_t)(struct data_src *ds, char *name,
+ int lineno, int fld, uint32_t value);
-typedef void (*set_dcd_rst_t)(struct imx_header *imxhdr,
- uint32_t dcd_len,
- char *name, int lineno);
-
-typedef int (*set_imx_hdr_t)(struct data_src *ds, uint32_t dcd_len,
- uint32_t entry_point, uint32_t flash_offset);
+typedef int (*set_imx_hdr_t)(struct data_src *ds, uint32_t entry_point,
+ uint32_t flash_offset);
struct data_src {
struct imx_header *imxhdr;
set_imx_hdr_t set_imx_hdr;
set_dcd_val_t set_dcd_val;
+ uint32_t *p_max_dcd;
+ uint32_t *p_entry;
+ write_dcd_command_t *p_dcd;
};
#endif /* _IMXIMAGE_H_ */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V4 09/11] tools: add parse_helper file
2012-11-28 1:31 ` [U-Boot] [PATCH V4 00/11] imximage series Troy Kisky
` (7 preceding siblings ...)
2012-11-28 1:31 ` [U-Boot] [PATCH V4 08/11] imximage: enable word writes for version2 header Troy Kisky
@ 2012-11-28 1:31 ` Troy Kisky
2012-11-28 9:41 ` Wolfgang Denk
2012-11-28 10:48 ` Liu Hui-R64343
2012-11-28 1:31 ` [U-Boot] [PATCH V4 10/11] imximage: use parse_helper functions Troy Kisky
` (2 subsequent siblings)
11 siblings, 2 replies; 430+ messages in thread
From: Troy Kisky @ 2012-11-28 1:31 UTC (permalink / raw)
To: u-boot
This file can help you parse
configuration files.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
tools/Makefile | 2 +
tools/parse_helper.c | 173 ++++++++++++++++++++++++++++++++++++++++++++++++++
tools/parse_helper.h | 28 ++++++++
3 files changed, 203 insertions(+)
create mode 100644 tools/parse_helper.c
create mode 100644 tools/parse_helper.h
diff --git a/tools/Makefile b/tools/Makefile
index 686840a..db3b247 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -94,6 +94,7 @@ NOPED_OBJ_FILES-y += aisimage.o
NOPED_OBJ_FILES-y += kwbimage.o
NOPED_OBJ_FILES-y += pblimage.o
NOPED_OBJ_FILES-y += imximage.o
+NOPED_OBJ_FILES-y += parse_helper.o
NOPED_OBJ_FILES-y += omapimage.o
NOPED_OBJ_FILES-y += mkenvimage.o
NOPED_OBJ_FILES-y += mkimage.o
@@ -208,6 +209,7 @@ $(obj)mkimage$(SFX): $(obj)aisimage.o \
$(obj)fit_image.o \
$(obj)image.o \
$(obj)imximage.o \
+ $(obj)parse_helper.o \
$(obj)kwbimage.o \
$(obj)pblimage.o \
$(obj)md5.o \
diff --git a/tools/parse_helper.c b/tools/parse_helper.c
new file mode 100644
index 0000000..0a5c5f6
--- /dev/null
+++ b/tools/parse_helper.c
@@ -0,0 +1,173 @@
+/*
+ * (C) Copyright 20012 Boundary Devices Inc, troy.kisky at boundarydevices.com
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+/* Required to obtain the getline prototype from stdio.h */
+#define _GNU_SOURCE
+
+#include "mkimage.h"
+#include <image.h>
+#include "parse_helper.h"
+
+int ph_open(struct parse_helper *ph, char *filename)
+{
+ ph->line = NULL;
+ ph->len = 0;
+ ph->fd = fopen(filename, "r");
+ ph->lineno = 0;
+ ph->cmd_started = 0;
+ ph->filename = filename;
+ ph->p = NULL;
+ return (!ph->fd) ? -1 : 0;
+}
+
+void ph_close(struct parse_helper *ph)
+{
+ fclose(ph->fd);
+ ph->fd = NULL;
+}
+
+int ph_skip_separators(struct parse_helper *ph)
+{
+ int line_no = ph->lineno;
+ char *p = ph->p;
+
+ for (;;) {
+ char c;
+ if (!p) {
+ if (getline(&ph->line, &ph->len, ph->fd) <= 0)
+ return -1;
+ ph->lineno++;
+ p = ph->line;
+ if (ph->cmd_started) {
+ fprintf(stderr, "warning: continuing command on"
+ " next line, line %s[%d](%s)\n",
+ ph->filename, ph->lineno, p);
+ }
+ }
+ c = *p;
+ if ((c == ' ') || (c == '\t')) {
+ p++;
+ continue;
+ }
+ /* Drop all text starting with '#' as comments */
+ if ((c == '#') || (c == '\r') || (c == '\n')
+ || !c) {
+ p = NULL;
+ continue;
+ }
+ if (c == ';') {
+ if (ph->cmd_started) {
+ fprintf(stderr, "Error: command not "
+ "finished:%s[%d](%s)\n",
+ ph->filename, ph->lineno, p);
+ exit(EXIT_FAILURE);
+ }
+ p++;
+ continue;
+ }
+ if (!ph->cmd_started && line_no == ph->lineno) {
+ fprintf(stderr, "Error: extra data at end "
+ "of line %s[%d](%s)\n",
+ ph->filename, ph->lineno, p);
+ exit(EXIT_FAILURE);
+ }
+ ph->p = p;
+ return 0;
+ }
+}
+
+int ph_skip_comma(struct parse_helper *ph)
+{
+ char *p = ph->p;
+
+ for (;;) {
+ char c = *p++;
+ if ((c == '#') || (c == '\r') || (c == '\n') || !c)
+ return 0;
+ if (c == ',') {
+ ph->p = p;
+ ph_skip_separators(ph);
+ return 1;
+ }
+ if ((c != ' ') && (c == '\t'))
+ return 0;
+ }
+}
+
+int ph_get_value(struct parse_helper *ph, uint32_t *pval)
+{
+ char *endptr;
+ uint32_t value;
+
+ if (ph_skip_separators(ph))
+ return -1;
+ errno = 0;
+ value = strtoul(ph->p, &endptr, 16);
+ if (errno || (ph->p == endptr))
+ return -1;
+ *pval = value;
+ ph->p = endptr;
+ return 0;
+}
+
+/*
+ * Comma separator optional
+ * Input:
+ * ph - input source
+ * data - array to fill in
+ * cnt - exact number of elements to parse
+ * Return: number of elements parsed, or error
+ */
+int ph_get_array(struct parse_helper *ph, uint32_t *data, int cnt)
+{
+ int i = 0;
+
+ for (;;) {
+ int ret = ph_get_value(ph, &data[i++]);
+ if (ret)
+ return ret;
+ if (i >= cnt)
+ break;
+ ph_skip_comma(ph); /* comma is optional */
+ }
+ return i;
+}
+
+static char *grab_token(char *dest, int size, char *src)
+{
+ while (size) {
+ char c = *src;
+ if ((c == ' ') || (c == '\t') || (c == '\r') || (c == '\n')
+ || (c == '#') || !c)
+ break;
+ *dest++ = c;
+ size--;
+ src++;
+ }
+ if (!size)
+ return NULL;
+ *dest = 0;
+ return src;
+}
+
+int ph_get_table_entry_id(struct parse_helper *ph,
+ const table_entry_t *table, const char *table_name)
+{
+ int val;
+ char token[16];
+ char *p;
+
+ if (ph_skip_separators(ph))
+ return -1;
+ p = grab_token(token, sizeof(token), ph->p);
+ if (!p)
+ return -1;
+ val = get_table_entry_id(table, table_name, token);
+ if (val != -1)
+ ph->p = p;
+ return val;
+}
+
diff --git a/tools/parse_helper.h b/tools/parse_helper.h
new file mode 100644
index 0000000..1ff98a3
--- /dev/null
+++ b/tools/parse_helper.h
@@ -0,0 +1,28 @@
+/*
+ * (C) Copyright 20012 Boundary Devices Inc, troy.kisky at boundarydevices.com
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef _PARSE_HELPER_H_
+#define _PARSE_HELPER_H_
+
+struct parse_helper {
+ char *line;
+ size_t len;
+ FILE *fd;
+ int lineno;
+ char cmd_started;
+ char *filename;
+ char *p;
+};
+
+int ph_open(struct parse_helper *ph, char *filename);
+void ph_close(struct parse_helper *ph);
+int ph_skip_separators(struct parse_helper *ph);
+int ph_skip_comma(struct parse_helper *ph);
+int ph_get_value(struct parse_helper *ph, uint32_t *pval);
+int ph_get_array(struct parse_helper *ph, uint32_t *data, int cnt);
+int ph_get_table_entry_id(struct parse_helper *ph,
+ const table_entry_t *table, const char *table_name);
+#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V4 10/11] imximage: use parse_helper functions
2012-11-28 1:31 ` [U-Boot] [PATCH V4 00/11] imximage series Troy Kisky
` (8 preceding siblings ...)
2012-11-28 1:31 ` [U-Boot] [PATCH V4 09/11] tools: add parse_helper file Troy Kisky
@ 2012-11-28 1:31 ` Troy Kisky
2012-11-28 10:48 ` Liu Hui-R64343
2012-11-28 1:31 ` [U-Boot] [PATCH V4 11/11] parse_helper: add expression evaluation Troy Kisky
2012-11-28 9:30 ` [U-Boot] [PATCH V4 00/11] imximage series Wolfgang Denk
11 siblings, 1 reply; 430+ messages in thread
From: Troy Kisky @ 2012-11-28 1:31 UTC (permalink / raw)
To: u-boot
Use parse_helper functions to pulling tokens instead
of pushing them.
Remove need for switch statements to process commands.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
v2: uses file parse_helper added in previous patch
changed patch subject, was cleanup parsing
---
tools/imximage.c | 267 +++++++++++++++++++-----------------------------------
tools/imximage.h | 17 ++--
2 files changed, 101 insertions(+), 183 deletions(-)
diff --git a/tools/imximage.c b/tools/imximage.c
index 2f5ee14..5147989 100644
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -25,9 +25,6 @@
* MA 02111-1307 USA
*/
-/* Required to obtain the getline prototype from stdio.h */
-#define _GNU_SOURCE
-
#include "mkimage.h"
#include <image.h>
#include "imximage.h"
@@ -70,21 +67,6 @@ static uint32_t g_flash_offset;
static struct image_type_params imximage_params;
-static uint32_t get_cfg_value(char *token, char *name, int linenr)
-{
- char *endptr;
- uint32_t value;
-
- errno = 0;
- value = strtoul(token, &endptr, 16);
- if (errno || (token == endptr)) {
- fprintf(stderr, "Error: %s[%d] - Invalid hex data(%s)\n",
- name, linenr, token);
- exit(EXIT_FAILURE);
- }
- return value;
-}
-
static uint32_t detect_imximage_version(struct imx_header *imx_hdr)
{
imx_header_v1_t *hdr_v1 = &imx_hdr->header.hdr_v1;
@@ -112,53 +94,36 @@ static void err_imximage_version(int version)
exit(EXIT_FAILURE);
}
-static void set_dcd_val_v1(struct data_src *ds, char *name, int lineno,
- int fld, uint32_t value)
+static int set_dcd_val_v1(struct data_src *ds, uint32_t *data)
{
dcd_v1_t *dcd_v1 = &ds->imxhdr->header.hdr_v1.dcd_table;
+ uint32_t val = *data++;
- switch (fld) {
- case CFG_REG_SIZE:
- /* Byte, halfword, word */
- if ((value != 1) && (value != 2) && (value != 4)) {
- fprintf(stderr, "Error: %s[%d] - "
- "Invalid register size " "(%d)\n",
- name, lineno, value);
- exit(EXIT_FAILURE);
- }
- *ds->p_entry++ = value;
- break;
- case CFG_REG_ADDRESS:
- *ds->p_entry++ = value;
- break;
- case CFG_REG_VALUE:
- *ds->p_entry++ = value;
- dcd_v1->preamble.length = (char *)ds->p_entry
- - (char *)&dcd_v1->addr_data[0].type;
- break;
- default:
- break;
-
+ /* Byte, halfword, word */
+ if ((val != 1) && (val != 2) && (val != 4)) {
+ fprintf(stderr, "Error: Invalid register size (%d)\n", val);
+ return -1;
}
+ *ds->p_entry++ = val;
+ *ds->p_entry++ = *data++;
+ *ds->p_entry++ = *data++;
+ dcd_v1->preamble.length = (char *)ds->p_entry - (char *)&dcd_v1->
+ addr_data[0].type;
+ return 0;
}
-static void set_dcd_val_v2(struct data_src *ds, char *name, int lineno,
- int fld, uint32_t value)
+static int set_dcd_val_v2(struct data_src *ds, uint32_t *data)
{
uint32_t len;
dcd_v2_t *dcd_v2 = &ds->imxhdr->header.hdr_v2.dcd_table;
+ uint32_t val = *data++;
- switch (fld) {
- case CFG_REG_SIZE:
- /* Byte, halfword, word */
- if ((value != 1) && (value != 2) && (value != 4)) {
- fprintf(stderr, "Error: %s[%d] - "
- "Invalid register size " "(%d)\n",
- name, lineno, value);
- exit(EXIT_FAILURE);
- }
- if (ds->p_dcd && (ds->p_dcd->param == value))
- break;
+ /* Byte, halfword, word */
+ if ((val != 1) && (val != 2) && (val != 4)) {
+ fprintf(stderr, "Error: Invalid register size (%d)\n", val);
+ return -1;
+ }
+ if (!(ds->p_dcd && (ds->p_dcd->param == val))) {
if (!ds->p_dcd) {
dcd_v2->header.tag = DCD_HEADER_TAG;
dcd_v2->header.version = DCD_VERSION;
@@ -166,24 +131,19 @@ static void set_dcd_val_v2(struct data_src *ds, char *name, int lineno,
} else {
ds->p_dcd = (write_dcd_command_t *)ds->p_entry;
}
- ds->p_dcd->param = value;
+ ds->p_dcd->param = val;
ds->p_dcd->tag = DCD_COMMAND_TAG;
ds->p_entry = (uint32_t *)(ds->p_dcd + 1);
- break;
- case CFG_REG_ADDRESS:
- *ds->p_entry++ = cpu_to_be32(value);
- break;
- case CFG_REG_VALUE:
- *ds->p_entry++ = cpu_to_be32(value);
- len = (char *)ds->p_entry - (char *)&dcd_v2->header;
- dcd_v2->header.length = cpu_to_be16(len);
- len = (char *)ds->p_entry - (char *)ds->p_dcd;
- ds->p_dcd->length = cpu_to_be16(len);
- break;
- default:
- break;
-
}
+ val = *data++;
+ *ds->p_entry++ = cpu_to_be32(val);
+ val = *data++;
+ *ds->p_entry++ = cpu_to_be32(val);
+ len = (char *)ds->p_entry - (char *)&dcd_v2->header;
+ dcd_v2->header.length = cpu_to_be16(len);
+ len = (char *)ds->p_entry - (char *)ds->p_dcd;
+ ds->p_dcd->length = cpu_to_be16(len);
+ return 0;
}
static int set_imx_hdr_v1(struct data_src *ds,
@@ -323,95 +283,71 @@ static void print_hdr_v2(struct imx_header *imx_hdr)
printf("Entry Point: %08x\n", (uint32_t)fhdr_v2->entry);
}
-static void parse_cfg_cmd(struct data_src *ds, int32_t cmd, char *token,
- char *name, int lineno, int fld)
+static int parse_cmd_data(struct data_src *ds)
+{
+ uint32_t data[3];
+ int ret = ph_get_array(&ds->ph, data, 3);
+
+ if (ret < 0)
+ return ret;
+ ret = (*ds->set_dcd_val)(ds, data);
+ if (ret)
+ return ret;
+ if (ds->p_entry > ds->p_max_dcd) {
+ uint32_t size = (char *)ds->p_max_dcd - (char *)ds->imxhdr;
+ fprintf(stderr, "Error: header exceeds maximum size(%d)\n",
+ size);
+ return -1;
+ }
+ return 0;
+}
+
+static int parse_image_version(struct data_src *ds)
{
- int value;
- static int cmd_ver_first = ~0;
+ int ret;
uint32_t imximage_version;
- switch (cmd) {
- case CMD_IMAGE_VERSION:
- imximage_version = get_cfg_value(token, name, lineno);
- if (cmd_ver_first == 0) {
- fprintf(stderr, "Error: %s[%d] - IMAGE_VERSION "
- "command need be the first before other "
- "valid command in the file\n", name, lineno);
- exit(EXIT_FAILURE);
- }
- cmd_ver_first = 1;
- set_hdr_func(ds, imximage_version);
- break;
- case CMD_BOOT_FROM:
- g_flash_offset = get_table_entry_id(imximage_bootops,
- "imximage boot option", token);
- if (g_flash_offset == -1) {
- fprintf(stderr, "Error: %s[%d] -Invalid boot device"
- "(%s)\n", name, lineno, token);
- exit(EXIT_FAILURE);
- }
- if (unlikely(cmd_ver_first != 1))
- cmd_ver_first = 0;
- break;
- case CMD_DATA:
- value = get_cfg_value(token, name, lineno);
- (*ds->set_dcd_val)(ds, name, lineno, fld, value);
- if (unlikely(cmd_ver_first != 1))
- cmd_ver_first = 0;
- break;
+ ret = ph_get_value(&ds->ph, &imximage_version);
+ if (ret)
+ return ret;
+ if (ds->cmd_cnt) {
+ fprintf(stderr, "Error: IMAGE_VERSION command needs be "
+ "before other valid commands in the file\n");
+ return -1;
}
+ set_hdr_func(ds, imximage_version);
+ return 0;
}
-static void parse_cfg_fld(struct data_src *ds, int32_t *cmd,
- char *token, char *name, int lineno, int fld)
+static int parse_boot_from(struct data_src *ds)
{
- int value;
-
- switch (fld) {
- case CFG_COMMAND:
- *cmd = get_table_entry_id(imximage_cmds,
- "imximage commands", token);
- if (*cmd < 0) {
- fprintf(stderr, "Error: %s[%d] - Invalid command"
- "(%s)\n", name, lineno, token);
- exit(EXIT_FAILURE);
- }
- break;
- case CFG_REG_SIZE:
- parse_cfg_cmd(ds, *cmd, token, name, lineno, fld);
- break;
- case CFG_REG_ADDRESS:
- case CFG_REG_VALUE:
- if (*cmd != CMD_DATA)
- return;
-
- value = get_cfg_value(token, name, lineno);
- (*ds->set_dcd_val)(ds, name, lineno, fld, value);
- if (ds->p_entry > ds->p_max_dcd) {
- uint32_t size = (char *)ds->p_max_dcd -
- (char *)ds->imxhdr;
- fprintf(stderr, "Error: %s[%d] -"
- "header exceeds maximum size(%d)\n",
- name, lineno, size);
- exit(EXIT_FAILURE);
- }
- break;
- default:
- break;
+ g_flash_offset = ph_get_table_entry_id(&ds->ph, imximage_bootops,
+ "imximage boot option");
+ if (g_flash_offset == -1) {
+ fprintf(stderr, "Error: Invalid boot device\n");
+ return -1;
}
+ return 0;
+}
+
+static const parse_fld_t cmd_table[] = {
+ parse_image_version, parse_boot_from, parse_cmd_data
+};
+
+static int parse_command(struct data_src *ds)
+{
+ int cmd = ph_get_table_entry_id(&ds->ph, imximage_cmds,
+ "imximage commands");
+ if (cmd < 0)
+ return cmd;
+ return cmd_table[cmd](ds);
}
static int parse_cfg_file(struct imx_header *imxhdr, char *name,
uint32_t entry_point)
{
struct data_src ds;
- FILE *fd = NULL;
- char *line = NULL;
- char *token, *saveptr1, *saveptr2;
- int lineno = 0;
- int fld;
- size_t len;
- int32_t cmd;
+ struct parse_helper *ph = &ds.ph;
/* Be able to detect if the cfg file has no BOOT_FROM tag */
g_flash_offset = FLASH_OFFSET_UNDEFINED;
@@ -423,8 +359,7 @@ static int parse_cfg_file(struct imx_header *imxhdr, char *name,
* set up function ptr group to V1 by default.
*/
set_hdr_func(&ds, IMXIMAGE_V1);
- fd = fopen(name, "r");
- if (fd == 0) {
+ if (ph_open(ph, name)) {
fprintf(stderr, "Error: %s - Can't open DCD file\n", name);
exit(EXIT_FAILURE);
}
@@ -432,31 +367,19 @@ static int parse_cfg_file(struct imx_header *imxhdr, char *name,
/* Very simple parsing, line starting with # are comments
* and are dropped
*/
- while ((getline(&line, &len, fd)) > 0) {
- lineno++;
-
- token = strtok_r(line, "\r\n", &saveptr1);
- if (token == NULL)
- continue;
-
- /* Check inside the single line */
- for (fld = CFG_COMMAND, cmd = CMD_INVALID,
- line = token; ; line = NULL, fld++) {
- token = strtok_r(line, " \t", &saveptr2);
- if (token == NULL)
- break;
-
- /* Drop all text starting with '#' as comments */
- if (token[0] == '#')
- break;
-
- parse_cfg_fld(&ds, &cmd, token, name,
- lineno, fld);
+ for (;;) {
+ ph->cmd_started = 0;
+ if (ph_skip_separators(ph))
+ break;
+ ph->cmd_started = 1;
+ if (parse_command(&ds)) {
+ fprintf(stderr, "Error: invalid token %s[%d](%s)\n",
+ name, ph->lineno, ph->p);
+ exit(EXIT_FAILURE);
}
-
+ ds.cmd_cnt++;
}
- fclose(fd);
-
+ ph_close(ph);
/* Exit if there is no BOOT_FROM field specifying the flash_offset */
if (g_flash_offset == FLASH_OFFSET_UNDEFINED) {
fprintf(stderr, "Error: No BOOT_FROM tag in %s\n", name);
@@ -546,12 +469,12 @@ static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd,
int imximage_check_params(struct mkimage_params *params)
{
if (!params)
- return CFG_INVALID;
+ return -1;
if (!strlen(params->imagename)) {
fprintf(stderr, "Error: %s - Configuration file not specified, "
"it is needed for imximage generation\n",
params->cmdname);
- return CFG_INVALID;
+ return -1;
}
/*
* Check parameters:
diff --git a/tools/imximage.h b/tools/imximage.h
index 196bb51..6bcd082 100644
--- a/tools/imximage.h
+++ b/tools/imximage.h
@@ -23,6 +23,7 @@
#ifndef _IMXIMAGE_H_
#define _IMXIMAGE_H_
+#include "parse_helper.h"
#define MAX_HW_CFG_SIZE_V2 121 /* Max number of registers imx can set for v2 */
#define MAX_HW_CFG_SIZE_V1 60 /* Max number of registers imx can set for v1 */
@@ -49,20 +50,11 @@
#define DCD_VERSION 0x40
enum imximage_cmd {
- CMD_INVALID,
CMD_IMAGE_VERSION,
CMD_BOOT_FROM,
CMD_DATA
};
-enum imximage_fld_types {
- CFG_INVALID = -1,
- CFG_COMMAND,
- CFG_REG_SIZE,
- CFG_REG_ADDRESS,
- CFG_REG_VALUE
-};
-
enum imximage_version {
IMXIMAGE_VER_INVALID = -1,
IMXIMAGE_V1 = 1,
@@ -159,14 +151,17 @@ struct imx_header {
};
struct data_src;
-typedef void (*set_dcd_val_t)(struct data_src *ds, char *name,
- int lineno, int fld, uint32_t value);
+typedef int (*parse_fld_t)(struct data_src *ds);
+
+typedef int (*set_dcd_val_t)(struct data_src *ds, uint32_t *data);
typedef int (*set_imx_hdr_t)(struct data_src *ds, uint32_t entry_point,
uint32_t flash_offset);
struct data_src {
+ struct parse_helper ph;
struct imx_header *imxhdr;
+ int cmd_cnt;
set_imx_hdr_t set_imx_hdr;
set_dcd_val_t set_dcd_val;
uint32_t *p_max_dcd;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V4 11/11] parse_helper: add expression evaluation
2012-11-28 1:31 ` [U-Boot] [PATCH V4 00/11] imximage series Troy Kisky
` (9 preceding siblings ...)
2012-11-28 1:31 ` [U-Boot] [PATCH V4 10/11] imximage: use parse_helper functions Troy Kisky
@ 2012-11-28 1:31 ` Troy Kisky
2012-11-28 10:49 ` Liu Hui-R64343
2012-11-28 9:30 ` [U-Boot] [PATCH V4 00/11] imximage series Wolfgang Denk
11 siblings, 1 reply; 430+ messages in thread
From: Troy Kisky @ 2012-11-28 1:31 UTC (permalink / raw)
To: u-boot
Basic expressions with order precedence is
now supported.
ie. (----3 + ((1+2*3)/--2 + --5 *(8/4))) is 16.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
tools/parse_helper.c | 172 +++++++++++++++++++++++++++++++++++++++++++++++---
1 file changed, 162 insertions(+), 10 deletions(-)
diff --git a/tools/parse_helper.c b/tools/parse_helper.c
index 0a5c5f6..50be832 100644
--- a/tools/parse_helper.c
+++ b/tools/parse_helper.c
@@ -97,20 +97,172 @@ int ph_skip_comma(struct parse_helper *ph)
}
}
+static const char precedence[] = {
+ /* ( + - * / & ^ | ) */
+ 0, 2, 2, 1, 1, 3, 4, 5, 6
+};
+static const char unary_operations[] = "(+-";
+static const char binary_operations[] = " +-*/&^|)";
+
+static uint32_t do_func(uint32_t val1, uint32_t val2, int op)
+{
+ switch (op) {
+ case 1:
+ return val1 + val2;
+ case 2:
+ return val1 - val2;
+ case 3:
+ return val1 * val2;
+ case 4:
+ return val1 / val2;
+ case 5:
+ return val1 & val2;
+ case 6:
+ return val1 ^ val2;
+ case 7:
+ return val1 | val2;
+ }
+ fprintf(stderr, "Error: in func %s: val1=%d val2=%d op = %d\n",
+ __func__, val1, val2, op);
+ exit(EXIT_FAILURE);
+}
+
+static int find_op(char c, const char *p)
+{
+ int i;
+ for (i = 0; ; i++) {
+ if (c == p[i])
+ return i;
+ if (!p[i])
+ break;
+ }
+ return -1;
+}
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
int ph_get_value(struct parse_helper *ph, uint32_t *pval)
{
char *endptr;
- uint32_t value;
+ int op_i = 0;
+ int val_i = 0;
+ unsigned char op[16];
+ uint32_t val[16];
+ int unary = 1;
+ char *p;
- if (ph_skip_separators(ph))
- return -1;
- errno = 0;
- value = strtoul(ph->p, &endptr, 16);
- if (errno || (ph->p == endptr))
- return -1;
- *pval = value;
- ph->p = endptr;
- return 0;
+ p = ph->p;
+ for (;;) {
+ char c;
+ int i, j;
+ const char *ops = unary ? unary_operations : binary_operations;
+
+ if (unary) {
+ ph->p = p;
+ if (ph_skip_separators(ph))
+ return -1;
+ p = ph->p;
+ c = *p;
+ } else {
+ for (;;) {
+ c = *p;
+ if ((c != ' ') && (c != '\t'))
+ break;
+ p++;
+ }
+ }
+ i = find_op(c, ops);
+ debug("%d,%c,%d:%s\n", i, c, unary, p);
+ if ((i < 0) && unary) {
+ if (val_i >= ARRAY_SIZE(val))
+ return -1;
+ errno = 0;
+ val[val_i++] = strtoul(p, &endptr, 16);
+ if (errno || (p == endptr)) {
+ ph->p = p;
+ return -1;
+ }
+ p = endptr;
+ unary = 0;
+ debug("val[%d]=%x,%d,%d\n", val_i - 1, val[val_i - 1],
+ op_i, val_i);
+do_unary:
+ while (op_i) {
+ j = op[op_i - 1];
+ if (!(j & 0x80))
+ break;
+ op_i--;
+ val[val_i - 1] = do_func(0,
+ val[val_i - 1], j & 0x7f);
+ debug("un:%d,%x,%d,%d\n", val[val_i - 1], j,
+ op_i, val_i);
+ }
+ continue;
+ }
+ if (i < 0) {
+ c = 0;
+ i = 8;
+ } else {
+ p++;
+ }
+ if (c == '(') {
+ if (op_i >= ARRAY_SIZE(op))
+ return -1;
+ op[op_i++] = i;
+ debug("op[%d]=%x,%d,%d\n", op_i - 1, op[op_i - 1],
+ op_i, val_i);
+ unary = 1;
+ continue;
+ }
+ for (;;) {
+ if (!op_i || unary)
+ break;
+ j = op[op_i - 1];
+ if (j == 0) {
+ if (c == ')') {
+ op_i--;
+ goto do_unary;
+ }
+ break;
+ }
+ if ((j & 0x80)) {
+ op_i--;
+ val[val_i - 1] = do_func(0,
+ val[val_i - 1], j & 0x7f);
+ debug("unary:%d,%x\n", val[val_i - 1], j);
+ continue;
+ }
+ if (precedence[i] < precedence[j])
+ break;
+ if (val_i < 2)
+ return -1;
+ op_i--;
+ val[val_i - 2] = do_func(val[val_i - 2],
+ val[val_i - 1], j);
+ val_i--;
+ debug("binary:%d,%x,%d,%d\n", val[val_i - 1], j,
+ op_i, val_i);
+ }
+ if (c == ')') {
+ fprintf(stderr, "Error: unmatched parenthesis\n");
+ return -1;
+ }
+ if (i == 8) {
+ if ((op_i != 0) || (val_i != 1)) {
+ fprintf(stderr, "Error: syntax %d %d\n",
+ op_i, val_i);
+ return -1;
+ }
+ ph->p = p;
+ *pval = val[0];
+ return 0;
+ }
+ if (op_i >= ARRAY_SIZE(op))
+ return -1;
+ op[op_i++] = i | (unary << 7);
+ debug("op[%d]=%x,%d,%d\n", op_i - 1, op[op_i - 1], op_i, val_i);
+ unary = 1;
+ }
}
/*
--
1.7.9.5
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V4 01/11] imximage: mx53 needs transfer length a multiple of 512
2012-11-28 1:31 ` [U-Boot] [PATCH V4 01/11] imximage: mx53 needs transfer length a multiple of 512 Troy Kisky
@ 2012-11-28 9:27 ` Wolfgang Denk
2012-11-28 18:18 ` Troy Kisky
2012-11-28 18:26 ` Troy Kisky
2012-11-28 10:34 ` Liu Hui-R64343
1 sibling, 2 replies; 430+ messages in thread
From: Wolfgang Denk @ 2012-11-28 9:27 UTC (permalink / raw)
To: u-boot
Dear Troy Kisky,
In message <1354066303-29762-2-git-send-email-troy.kisky@boundarydevices.com> you wrote:
> The mx53 ROM will truncate the length at a multiple of 512.
> Transferring too much is not a problem, so round up.
What about other SoCs using the same code?
> +#define ALIGN(a, b) (((a) + (b) - 1) & ~((b) - 1))
NAK. This macro is mis-named; it has nothing to do with alignment -
you write yourself: "round up".
And you don't have to re-invent the wheel. Please use the existing
macros for this purpose.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
If something is different, it's either better or worse, and usually
both. - Larry Wall
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V4 00/11] imximage series
2012-11-28 1:31 ` [U-Boot] [PATCH V4 00/11] imximage series Troy Kisky
` (10 preceding siblings ...)
2012-11-28 1:31 ` [U-Boot] [PATCH V4 11/11] parse_helper: add expression evaluation Troy Kisky
@ 2012-11-28 9:30 ` Wolfgang Denk
2012-11-28 18:29 ` Troy Kisky
11 siblings, 1 reply; 430+ messages in thread
From: Wolfgang Denk @ 2012-11-28 9:30 UTC (permalink / raw)
To: u-boot
Dear Troy Kisky,
In message <1354066303-29762-1-git-send-email-troy.kisky@boundarydevices.com> you wrote:
>
> This series make the file imximage.c easier to read, as well
> as produces a slightly smaller file.
>
>
> Only the 1st two patches are different from version 3. The
> 1st is a new patch which addresses an mx53 ROM bug. The 2nd
> is slight changes due to rebase on 1st.
Would it make sense to use this opportunity to integrate this tool
into mkimage ?
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
You see things; and you say ``Why?'' But I dream things that never
were; and I say ``Why not?''
- George Bernard Shaw _Back to Methuselah_ (1921) pt. 1, act 1
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V4 04/11] imximage: prepare to move static variables to struct data_src
2012-11-28 1:31 ` [U-Boot] [PATCH V4 04/11] imximage: prepare to move static variables to struct data_src Troy Kisky
@ 2012-11-28 9:38 ` Wolfgang Denk
2012-11-28 18:36 ` Troy Kisky
0 siblings, 1 reply; 430+ messages in thread
From: Wolfgang Denk @ 2012-11-28 9:38 UTC (permalink / raw)
To: u-boot
Dear Troy Kisky,
In message <1354066303-29762-5-git-send-email-troy.kisky@boundarydevices.com> you wrote:
> Need to move accesses to the static variables to
> a function where struct data_src is used.
Could you please elucidate why exactly this is _needed_?
> + /* Be able to detect if the cfg file has no BOOT_FROM tag */
> + g_flash_offset = FLASH_OFFSET_UNDEFINED;
> + memset(&ds, 0, sizeof(struct data_src));
Is this initialization really needed?
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
A direct quote from the Boss: "We passed over a lot of good people to
get the ones we hired."
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V4 08/11] imximage: enable word writes for version2 header
2012-11-28 1:31 ` [U-Boot] [PATCH V4 08/11] imximage: enable word writes for version2 header Troy Kisky
@ 2012-11-28 9:39 ` Wolfgang Denk
2012-11-28 20:40 ` Troy Kisky
2012-11-28 10:47 ` Liu Hui-R64343
1 sibling, 1 reply; 430+ messages in thread
From: Wolfgang Denk @ 2012-11-28 9:39 UTC (permalink / raw)
To: u-boot
Dear Troy Kisky,
In message <1354066303-29762-9-git-send-email-troy.kisky@boundarydevices.com> you wrote:
> Before, only 1 write_dcd_command table was built.
> Now, a new table is built when the size changes.
I cannot see how the Subject: and the actual commit message (and code)
are related.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
If a group of N persons implements a COBOL compiler, there will be
N-1 passes. Someone in the group has to be the manager. - T. Cheatham
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V4 09/11] tools: add parse_helper file
2012-11-28 1:31 ` [U-Boot] [PATCH V4 09/11] tools: add parse_helper file Troy Kisky
@ 2012-11-28 9:41 ` Wolfgang Denk
2012-11-28 10:48 ` Liu Hui-R64343
1 sibling, 0 replies; 430+ messages in thread
From: Wolfgang Denk @ 2012-11-28 9:41 UTC (permalink / raw)
To: u-boot
Dear Troy Kisky,
In message <1354066303-29762-10-git-send-email-troy.kisky@boundarydevices.com> you wrote:
> This file can help you parse
> configuration files.
If this is intended to be useful, you need to add documentation, for
example what your definition of "configuration files" is, and which
data format[s] is/are supported, etc.
As is, this cannot be reused.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Wenn das dann in die Hose geht, nehme ich es auf meine Kappe.
-- Rudi V?ller, 15. Nov 2003
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V4 01/11] imximage: mx53 needs transfer length a multiple of 512
2012-11-28 1:31 ` [U-Boot] [PATCH V4 01/11] imximage: mx53 needs transfer length a multiple of 512 Troy Kisky
2012-11-28 9:27 ` Wolfgang Denk
@ 2012-11-28 10:34 ` Liu Hui-R64343
1 sibling, 0 replies; 430+ messages in thread
From: Liu Hui-R64343 @ 2012-11-28 10:34 UTC (permalink / raw)
To: u-boot
>-----Original Message-----
>From: Troy Kisky [mailto:troy.kisky at boundarydevices.com]
>Sent: Wednesday, November 28, 2012 9:32 AM
>To: sbabic at denx.de
>Cc: dirk.behme at googlemail.com; u-boot at lists.denx.de; Liu Hui-R64343;
>festevam at gmail.com; Troy Kisky
>Subject: [PATCH V4 01/11] imximage: mx53 needs transfer length a multiple
>of 512
>
>The mx53 ROM will truncate the length at a multiple of 512.
>Transferring too much is not a problem, so round up.
>
>Problem reported by Stefano Babic.
>
>Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Jason Liu <r64343@freescale.com>
>---
> tools/imximage.c | 10 +++++++++-
> 1 file changed, 9 insertions(+), 1 deletion(-)
>
>diff --git a/tools/imximage.c b/tools/imximage.c index 63f88b6..7e54e97
>100644
>--- a/tools/imximage.c
>+++ b/tools/imximage.c
>@@ -494,6 +494,8 @@ static void imximage_print_header(const void *ptr)
> }
> }
>
>+#define ALIGN(a, b) (((a) + (b) - 1) & ~((b) - 1))
>+
> static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd,
> struct mkimage_params *params)
> {
>@@ -515,7 +517,13 @@ static void imximage_set_header(void *ptr, struct
>stat *sbuf, int ifd,
>
> /* Set the imx header */
> (*set_imx_hdr)(imxhdr, dcd_len, params->ep, imxhdr->flash_offset);
>- *header_size_ptr = sbuf->st_size + imxhdr->flash_offset;
>+ /*
>+ * ROM bug alert
>+ * mx53 only loads 512 byte multiples.
>+ * The remaining fraction of a block bytes would
>+ * not be loaded.
>+ */
>+ *header_size_ptr = ALIGN(sbuf->st_size + imxhdr->flash_offset, 512);
> }
>
> int imximage_check_params(struct mkimage_params *params)
>--
>1.7.9.5
>
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V4 02/11] imximage: make header variable length
2012-11-28 1:31 ` [U-Boot] [PATCH V4 02/11] imximage: make header variable length Troy Kisky
@ 2012-11-28 10:42 ` Liu Hui-R64343
0 siblings, 0 replies; 430+ messages in thread
From: Liu Hui-R64343 @ 2012-11-28 10:42 UTC (permalink / raw)
To: u-boot
>-----Original Message-----
>From: Troy Kisky [mailto:troy.kisky at boundarydevices.com]
>Sent: Wednesday, November 28, 2012 9:32 AM
>To: sbabic at denx.de
>Cc: dirk.behme at googlemail.com; u-boot at lists.denx.de; Liu Hui-R64343;
>festevam at gmail.com; Troy Kisky
>Subject: [PATCH V4 02/11] imximage: make header variable length
>
>This makes the dcd table optional as well for v2.
>Also, the header offset is no longer
>right before the code starts.
>
>Before this patch mx53loco_config produces
>
>000000 402000d1 77800000 00000000 777ffc2c 000010 777ffc20 777ffc00
>00000000 00000000 000020 777ff800 0004b200 00000000 40a001d2 000030
>049c01cc 5485fa53 00003000 5885fa53 ... more DCD table 0001c0 27220200
>1c90fd63 00000000 00000000 0001d0 00000000 00000000 00000000
>00000000
>*
>0003f0 00000000 00000000 00000000 00000400 000400 ea000014 e59ff014
>e59ff014 e59ff014
>
>Notice offset 3fc contains 0x400. This
>is the header offset. There is no reason for this to be in the file, and I have
>removed it.
>
>After this patch we have
>
>000000 402000d1 77800000 00000000 777ffe60 000010 777ffe54 777ffe34
>00000000 00000000 000020 777ffa34 0004b000 00000000 40a001d2 000030
>049c01cc 5485fa53 00003000 5885fa53 ... more DCD table 0001c0 27220200
>1c90fd63 00000000 ea000014 0001d0 e59ff014 e59ff014 e59ff014 e59ff014
>
>Notice the zeros between 0x1cc and 0x3fb have been removed.
>
>Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Jason Liu <r64343@freescale.com>
>
>---
>
>v4: updated commit log, minor change to rebase on previous patch
>v3: other patches split from this one
>---
> tools/imximage.c | 65 ++++++++++++++++++++++++++++++++++++--------------
>----
> tools/imximage.h | 4 ++--
> 2 files changed, 46 insertions(+), 23 deletions(-)
>
>diff --git a/tools/imximage.c b/tools/imximage.c index 7e54e97..8457c8e
>100644
>--- a/tools/imximage.c
>+++ b/tools/imximage.c
>@@ -65,7 +65,6 @@ static table_entry_t imximage_versions[] = {
> {-1, "", " (Invalid)", },
> };
>
>-static struct imx_header imximage_header; static uint32_t
>imximage_version;
>
> static set_dcd_val_t set_dcd_val;
>@@ -73,6 +72,9 @@ static set_dcd_rst_t set_dcd_rst; static set_imx_hdr_t
>set_imx_hdr; static uint32_t max_dcd_entries; static uint32_t
>*header_size_ptr;
>+static uint32_t g_flash_offset;
>+
>+static struct image_type_params imximage_params;
>
> static uint32_t get_cfg_value(char *token, char *name, int linenr) { @@ -
>102,8 +104,7 @@ static uint32_t detect_imximage_version(struct imx_header
>*imx_hdr)
> return IMXIMAGE_V1;
>
> /* Try to detect V2 */
>- if ((fhdr_v2->header.tag == IVT_HEADER_TAG) &&
>- (hdr_v2->dcd_table.header.tag == DCD_HEADER_TAG))
>+ if (fhdr_v2->header.tag == IVT_HEADER_TAG)
> return IMXIMAGE_V2;
>
> return IMXIMAGE_VER_INVALID;
>@@ -195,7 +196,7 @@ static void set_dcd_rst_v2(struct imx_header *imxhdr,
>uint32_t dcd_len,
> dcd_v2->write_dcd_command.param = DCD_COMMAND_PARAM; }
>
>-static void set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,
>+static int set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,
> uint32_t entry_point, uint32_t flash_offset) {
> imx_header_v1_t *hdr_v1 = &imxhdr->header.hdr_v1; @@ -208,7
>+209,7 @@ static void set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t
>dcd_len,
> /* Set magic number */
> fhdr_v1->app_code_barker = APP_CODE_BARKER;
>
>- hdr_base = entry_point - sizeof(struct imx_header);
>+ hdr_base = entry_point - header_length;
> fhdr_v1->app_dest_ptr = hdr_base - flash_offset;
> fhdr_v1->app_code_jump_vector = entry_point;
>
>@@ -219,14 +220,18 @@ static void set_imx_hdr_v1(struct imx_header
>*imxhdr, uint32_t dcd_len,
> fhdr_v1->app_code_csf = 0;
> fhdr_v1->super_root_key = 0;
> header_size_ptr = (uint32_t *)(((char *)imxhdr) + header_length - 4);
>+ return header_length;
> }
>
>-static void set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t dcd_len,
>+static int set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t dcd_len,
> uint32_t entry_point, uint32_t flash_offset) {
> imx_header_v2_t *hdr_v2 = &imxhdr->header.hdr_v2;
> flash_header_v2_t *fhdr_v2 = &hdr_v2->fhdr;
> uint32_t hdr_base;
>+ uint32_t header_length = (dcd_len) ?
>+ (char *)&hdr_v2->dcd_table.addr_data[dcd_len] -
>((char*)imxhdr)
>+ : offsetof(imx_header_v2_t, dcd_table);
>
> /* Set magic number */
> fhdr_v2->header.tag = IVT_HEADER_TAG; /* 0xD1 */ @@ -235,9
>+240,10 @@ static void set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t
>dcd_len,
>
> fhdr_v2->entry = entry_point;
> fhdr_v2->reserved1 = fhdr_v2->reserved2 = 0;
>- fhdr_v2->self = hdr_base = entry_point - sizeof(struct imx_header);
>+ fhdr_v2->self = hdr_base = entry_point - header_length;
>
>- fhdr_v2->dcd_ptr = hdr_base + offsetof(imx_header_v2_t, dcd_table);
>+ fhdr_v2->dcd_ptr = (dcd_len) ? hdr_base
>+ + offsetof(imx_header_v2_t, dcd_table) : 0;
> fhdr_v2->boot_data_ptr = hdr_base
> + offsetof(imx_header_v2_t, boot_data);
> hdr_v2->boot_data.start = hdr_base - flash_offset; @@ -245,6 +251,7
>@@ static void set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t dcd_len,
> /* Security feature are not supported */
> fhdr_v2->csf = 0;
> header_size_ptr = &hdr_v2->boot_data.size;
>+ return header_length;
> }
>
> static void set_hdr_func(struct imx_header *imxhdr) @@ -342,9 +349,9 @@
>static void parse_cfg_cmd(struct imx_header *imxhdr, int32_t cmd, char
>*token,
> set_hdr_func(imxhdr);
> break;
> case CMD_BOOT_FROM:
>- imxhdr->flash_offset = get_table_entry_id(imximage_bootops,
>+ g_flash_offset = get_table_entry_id(imximage_bootops,
> "imximage boot option", token);
>- if (imxhdr->flash_offset == -1) {
>+ if (g_flash_offset == -1) {
> fprintf(stderr, "Error: %s[%d] -Invalid boot device"
> "(%s)\n", name, lineno, token);
> exit(EXIT_FAILURE);
>@@ -449,7 +456,7 @@ static uint32_t parse_cfg_file(struct imx_header
>*imxhdr, char *name)
> fclose(fd);
>
> /* Exit if there is no BOOT_FROM field specifying the flash_offset */
>- if (imxhdr->flash_offset == FLASH_OFFSET_UNDEFINED) {
>+ if (g_flash_offset == FLASH_OFFSET_UNDEFINED) {
> fprintf(stderr, "Error: No BOOT_FROM tag in %s\n", name);
> exit(EXIT_FAILURE);
> }
>@@ -494,14 +501,17 @@ static void imximage_print_header(const void *ptr)
> }
> }
>
>-#define ALIGN(a, b) (((a) + (b) - 1) & ~((b) - 1))
>-
>-static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd,
>- struct mkimage_params *params)
>+int imximage_vrec_header(struct mkimage_params *params,
>+ struct image_type_params *tparams)
> {
>- struct imx_header *imxhdr = (struct imx_header *)ptr;
>+ struct imx_header *imxhdr;
> uint32_t dcd_len;
>
>+ imxhdr = calloc(1, MAX_HEADER_SIZE);
>+ if (!imxhdr) {
>+ fprintf(stderr, "Error: out of memory\n");
>+ exit(EXIT_FAILURE);
>+ }
> /*
> * In order to not change the old imx cfg file
> * by adding VERSION command into it, here need @@ -509,21
>+519,35 @@ static void imximage_set_header(void *ptr, struct stat *sbuf, int
>ifd,
> */
> imximage_version = IMXIMAGE_V1;
> /* Be able to detect if the cfg file has no BOOT_FROM tag */
>- imxhdr->flash_offset = FLASH_OFFSET_UNDEFINED;
>+ g_flash_offset = FLASH_OFFSET_UNDEFINED;
> set_hdr_func(imxhdr);
>
> /* Parse dcd configuration file */
> dcd_len = parse_cfg_file(imxhdr, params->imagename);
>
> /* Set the imx header */
>- (*set_imx_hdr)(imxhdr, dcd_len, params->ep, imxhdr->flash_offset);
>+ imximage_params.header_size = (*set_imx_hdr)(imxhdr, dcd_len,
>+ params->ep, g_flash_offset);
>+ imximage_params.hdr = imxhdr;
>+ return 0;
>+}
>+
>+#define ALIGN(a, b) (((a) + (b) - 1) & ~((b) - 1))
>+
>+static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd,
>+ struct mkimage_params *params)
>+{
>+ /* Set the size in header */
>+ uint32_t offset = (char *)header_size_ptr - (char
>*)imximage_params.hdr;
>+ uint32_t *p = (uint32_t *)((char *)ptr + offset);
>+
> /*
> * ROM bug alert
> * mx53 only loads 512 byte multiples.
> * The remaining fraction of a block bytes would
> * not be loaded.
> */
>- *header_size_ptr = ALIGN(sbuf->st_size + imxhdr->flash_offset, 512);
>+ *p = ALIGN(sbuf->st_size + g_flash_offset, 512);
> }
>
> int imximage_check_params(struct mkimage_params *params) @@ -553,8
>+577,7 @@ int imximage_check_params(struct mkimage_params *params)
> */
> static struct image_type_params imximage_params = {
> .name = "Freescale i.MX 5x Boot Image support",
>- .header_size = sizeof(struct imx_header),
>- .hdr = (void *)&imximage_header,
>+ .vrec_header = imximage_vrec_header,
> .check_image_type = imximage_check_image_types,
> .verify_header = imximage_verify_header,
> .print_header = imximage_print_header,
>diff --git a/tools/imximage.h b/tools/imximage.h index 42b6090..0f39447
>100644
>--- a/tools/imximage.h
>+++ b/tools/imximage.h
>@@ -30,6 +30,7 @@
> #define DCD_BARKER 0xB17219E9
>
> #define HEADER_OFFSET 0x400
>+#define MAX_HEADER_SIZE (16 << 10)
>
> #define CMD_DATA_STR "DATA"
> #define FLASH_OFFSET_UNDEFINED 0xFFFFFFFF
>@@ -156,7 +157,6 @@ struct imx_header {
> imx_header_v1_t hdr_v1;
> imx_header_v2_t hdr_v2;
> } header;
>- uint32_t flash_offset;
> };
>
> typedef void (*set_dcd_val_t)(struct imx_header *imxhdr, @@ -168,7 +168,7
>@@ typedef void (*set_dcd_rst_t)(struct imx_header *imxhdr,
> uint32_t dcd_len,
> char *name, int lineno);
>
>-typedef void (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t dcd_len,
>+typedef int (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t
>+dcd_len,
> uint32_t entry_point, uint32_t flash_offset);
>
> #endif /* _IMXIMAGE_H_ */
>--
>1.7.9.5
>
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V4 03/11] imximage: remove static imximage_version
2012-11-28 1:31 ` [U-Boot] [PATCH V4 03/11] imximage: remove static imximage_version Troy Kisky
@ 2012-11-28 10:43 ` Liu Hui-R64343
0 siblings, 0 replies; 430+ messages in thread
From: Liu Hui-R64343 @ 2012-11-28 10:43 UTC (permalink / raw)
To: u-boot
>-----Original Message-----
>From: Troy Kisky [mailto:troy.kisky at boundarydevices.com]
>Sent: Wednesday, November 28, 2012 9:32 AM
>To: sbabic at denx.de
>Cc: dirk.behme at googlemail.com; u-boot at lists.denx.de; Liu Hui-R64343;
>festevam at gmail.com; Troy Kisky
>Subject: [PATCH V4 03/11] imximage: remove static imximage_version
>
>This variable does not need to have file scope.
>
>Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Jason Liu <r64343@freescale.com>
>---
> tools/imximage.c | 21 +++++++++------------
> 1 file changed, 9 insertions(+), 12 deletions(-)
>
>diff --git a/tools/imximage.c b/tools/imximage.c index 8457c8e..97e5c4b
>100644
>--- a/tools/imximage.c
>+++ b/tools/imximage.c
>@@ -65,8 +65,6 @@ static table_entry_t imximage_versions[] = {
> {-1, "", " (Invalid)", },
> };
>
>-static uint32_t imximage_version;
>-
> static set_dcd_val_t set_dcd_val;
> static set_dcd_rst_t set_dcd_rst;
> static set_imx_hdr_t set_imx_hdr;
>@@ -254,7 +252,7 @@ static int set_imx_hdr_v2(struct imx_header *imxhdr,
>uint32_t dcd_len,
> return header_length;
> }
>
>-static void set_hdr_func(struct imx_header *imxhdr)
>+static void set_hdr_func(struct imx_header *imxhdr, uint32_t
>+imximage_version)
> {
> switch (imximage_version) {
> case IMXIMAGE_V1:
>@@ -335,6 +333,7 @@ static void parse_cfg_cmd(struct imx_header *imxhdr,
>int32_t cmd, char *token, {
> int value;
> static int cmd_ver_first = ~0;
>+ uint32_t imximage_version;
>
> switch (cmd) {
> case CMD_IMAGE_VERSION:
>@@ -346,7 +345,7 @@ static void parse_cfg_cmd(struct imx_header *imxhdr,
>int32_t cmd, char *token,
> exit(EXIT_FAILURE);
> }
> cmd_ver_first = 1;
>- set_hdr_func(imxhdr);
>+ set_hdr_func(imxhdr, imximage_version);
> break;
> case CMD_BOOT_FROM:
> g_flash_offset = get_table_entry_id(imximage_bootops,
>@@ -419,6 +418,12 @@ static uint32_t parse_cfg_file(struct imx_header
>*imxhdr, char *name)
> int dcd_len = 0;
> int32_t cmd;
>
>+ /*
>+ * In order to not change the old imx cfg file
>+ * by adding VERSION command into it, here need
>+ * set up function ptr group to V1 by default.
>+ */
>+ set_hdr_func(imxhdr, IMXIMAGE_V1);
> fd = fopen(name, "r");
> if (fd == 0) {
> fprintf(stderr, "Error: %s - Can't open DCD file\n", name); @@ -
>512,16 +517,8 @@ int imximage_vrec_header(struct mkimage_params
>*params,
> fprintf(stderr, "Error: out of memory\n");
> exit(EXIT_FAILURE);
> }
>- /*
>- * In order to not change the old imx cfg file
>- * by adding VERSION command into it, here need
>- * set up function ptr group to V1 by default.
>- */
>- imximage_version = IMXIMAGE_V1;
> /* Be able to detect if the cfg file has no BOOT_FROM tag */
> g_flash_offset = FLASH_OFFSET_UNDEFINED;
>- set_hdr_func(imxhdr);
>-
> /* Parse dcd configuration file */
> dcd_len = parse_cfg_file(imxhdr, params->imagename);
>
>--
>1.7.9.5
>
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V4 05/11] imximage: change parameters for set_dcd_val/set_imx_hdr
2012-11-28 1:31 ` [U-Boot] [PATCH V4 05/11] imximage: change parameters for set_dcd_val/set_imx_hdr Troy Kisky
@ 2012-11-28 10:43 ` Liu Hui-R64343
0 siblings, 0 replies; 430+ messages in thread
From: Liu Hui-R64343 @ 2012-11-28 10:43 UTC (permalink / raw)
To: u-boot
>-----Original Message-----
>From: Troy Kisky [mailto:troy.kisky at boundarydevices.com]
>Sent: Wednesday, November 28, 2012 9:32 AM
>To: sbabic at denx.de
>Cc: dirk.behme at googlemail.com; u-boot at lists.denx.de; Liu Hui-R64343;
>festevam at gmail.com; Troy Kisky
>Subject: [PATCH V4 05/11] imximage: change parameters for
>set_dcd_val/set_imx_hdr
>
>Change 1st argument of set_imx_hdr/set_dcd_val to struct data_src.
>
>Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Jason Liu <r64343@freescale.com>
>---
> tools/imximage.c | 41 +++++++++++++++++++++--------------------
> tools/imximage.h | 5 +++--
> 2 files changed, 24 insertions(+), 22 deletions(-)
>
>diff --git a/tools/imximage.c b/tools/imximage.c index 3a010a6..ddac95f
>100644
>--- a/tools/imximage.c
>+++ b/tools/imximage.c
>@@ -116,10 +116,10 @@ static void err_imximage_version(int version)
> exit(EXIT_FAILURE);
> }
>
>-static void set_dcd_val_v1(struct imx_header *imxhdr, char *name, int
>lineno,
>+static void set_dcd_val_v1(struct data_src *ds, char *name, int lineno,
> int fld, uint32_t value, uint32_t off) {
>- dcd_v1_t *dcd_v1 = &imxhdr->header.hdr_v1.dcd_table;
>+ dcd_v1_t *dcd_v1 = &ds->imxhdr->header.hdr_v1.dcd_table;
>
> switch (fld) {
> case CFG_REG_SIZE:
>@@ -144,10 +144,10 @@ static void set_dcd_val_v1(struct imx_header
>*imxhdr, char *name, int lineno,
> }
> }
>
>-static void set_dcd_val_v2(struct imx_header *imxhdr, char *name, int
>lineno,
>+static void set_dcd_val_v2(struct data_src *ds, char *name, int lineno,
> int fld, uint32_t value, uint32_t off) {
>- dcd_v2_t *dcd_v2 = &imxhdr->header.hdr_v2.dcd_table;
>+ dcd_v2_t *dcd_v2 = &ds->imxhdr->header.hdr_v2.dcd_table;
>
> switch (fld) {
> case CFG_REG_ADDRESS:
>@@ -194,15 +194,15 @@ static void set_dcd_rst_v2(struct imx_header
>*imxhdr, uint32_t dcd_len,
> dcd_v2->write_dcd_command.param = DCD_COMMAND_PARAM; }
>
>-static int set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,
>+static int set_imx_hdr_v1(struct data_src *ds, uint32_t dcd_len,
> uint32_t entry_point, uint32_t flash_offset) {
>- imx_header_v1_t *hdr_v1 = &imxhdr->header.hdr_v1;
>+ imx_header_v1_t *hdr_v1 = &ds->imxhdr->header.hdr_v1;
> flash_header_v1_t *fhdr_v1 = &hdr_v1->fhdr;
> dcd_v1_t *dcd_v1 = &hdr_v1->dcd_table;
> uint32_t hdr_base;
> uint32_t header_length = (((char *)&dcd_v1-
>>addr_data[dcd_len].addr)
>- - ((char *)imxhdr));
>+ - ((char *)ds->imxhdr));
>
> /* Set magic number */
> fhdr_v1->app_code_barker = APP_CODE_BARKER; @@ -217,19
>+217,20 @@ static int set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t
>dcd_len,
> /* Security feature are not supported */
> fhdr_v1->app_code_csf = 0;
> fhdr_v1->super_root_key = 0;
>- header_size_ptr = (uint32_t *)(((char *)imxhdr) + header_length - 4);
>+ header_size_ptr = (uint32_t *)(((char *)ds->imxhdr) +
>+ header_length - 4);
> return header_length;
> }
>
>-static int set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t dcd_len,
>+static int set_imx_hdr_v2(struct data_src *ds, uint32_t dcd_len,
> uint32_t entry_point, uint32_t flash_offset) {
>- imx_header_v2_t *hdr_v2 = &imxhdr->header.hdr_v2;
>+ imx_header_v2_t *hdr_v2 = &ds->imxhdr->header.hdr_v2;
> flash_header_v2_t *fhdr_v2 = &hdr_v2->fhdr;
> uint32_t hdr_base;
> uint32_t header_length = (dcd_len) ?
>- (char *)&hdr_v2->dcd_table.addr_data[dcd_len] -
>((char*)imxhdr)
>- : offsetof(imx_header_v2_t, dcd_table);
>+ (char *)&hdr_v2->dcd_table.addr_data[dcd_len] -
>+ ((char *)ds->imxhdr) : offsetof(imx_header_v2_t, dcd_table);
>
> /* Set magic number */
> fhdr_v2->header.tag = IVT_HEADER_TAG; /* 0xD1 */ @@ -328,7
>+329,7 @@ static void print_hdr_v2(struct imx_header *imx_hdr)
> printf("Entry Point: %08x\n", (uint32_t)fhdr_v2->entry); }
>
>-static void parse_cfg_cmd(struct imx_header *imxhdr, int32_t cmd, char
>*token,
>+static void parse_cfg_cmd(struct data_src *ds, int32_t cmd, char
>+*token,
> char *name, int lineno, int fld, int dcd_len) {
> int value;
>@@ -345,7 +346,7 @@ static void parse_cfg_cmd(struct imx_header *imxhdr,
>int32_t cmd, char *token,
> exit(EXIT_FAILURE);
> }
> cmd_ver_first = 1;
>- set_hdr_func(imxhdr, imximage_version);
>+ set_hdr_func(ds->imxhdr, imximage_version);
> break;
> case CMD_BOOT_FROM:
> g_flash_offset = get_table_entry_id(imximage_bootops,
>@@ -360,14 +361,14 @@ static void parse_cfg_cmd(struct imx_header
>*imxhdr, int32_t cmd, char *token,
> break;
> case CMD_DATA:
> value = get_cfg_value(token, name, lineno);
>- (*set_dcd_val)(imxhdr, name, lineno, fld, value, dcd_len);
>+ (*set_dcd_val)(ds, name, lineno, fld, value, dcd_len);
> if (unlikely(cmd_ver_first != 1))
> cmd_ver_first = 0;
> break;
> }
> }
>
>-static void parse_cfg_fld(struct imx_header *imxhdr, int32_t *cmd,
>+static void parse_cfg_fld(struct data_src *ds, int32_t *cmd,
> char *token, char *name, int lineno, int fld, int *dcd_len) {
> int value;
>@@ -383,7 +384,7 @@ static void parse_cfg_fld(struct imx_header *imxhdr,
>int32_t *cmd,
> }
> break;
> case CFG_REG_SIZE:
>- parse_cfg_cmd(imxhdr, *cmd, token, name, lineno, fld,
>*dcd_len);
>+ parse_cfg_cmd(ds, *cmd, token, name, lineno, fld, *dcd_len);
> break;
> case CFG_REG_ADDRESS:
> case CFG_REG_VALUE:
>@@ -391,7 +392,7 @@ static void parse_cfg_fld(struct imx_header *imxhdr,
>int32_t *cmd,
> return;
>
> value = get_cfg_value(token, name, lineno);
>- (*set_dcd_val)(imxhdr, name, lineno, fld, value, *dcd_len);
>+ (*set_dcd_val)(ds, name, lineno, fld, value, *dcd_len);
>
> if (fld == CFG_REG_VALUE) {
> (*dcd_len)++;
>@@ -458,7 +459,7 @@ static int parse_cfg_file(struct imx_header *imxhdr,
>char *name,
> if (token[0] == '#')
> break;
>
>- parse_cfg_fld(imxhdr, &cmd, token, name,
>+ parse_cfg_fld(&ds, &cmd, token, name,
> lineno, fld, &dcd_len);
> }
>
>@@ -473,7 +474,7 @@ static int parse_cfg_file(struct imx_header *imxhdr,
>char *name,
> exit(EXIT_FAILURE);
> }
> /* Set the imx header */
>- return (*set_imx_hdr)(imxhdr, dcd_len, entry_point, g_flash_offset);
>+ return (*set_imx_hdr)(&ds, dcd_len, entry_point, g_flash_offset);
> }
>
> static int imximage_check_image_types(uint8_t type) diff --git
>a/tools/imximage.h b/tools/imximage.h index 2895378..3054d55 100644
>--- a/tools/imximage.h
>+++ b/tools/imximage.h
>@@ -159,7 +159,8 @@ struct imx_header {
> } header;
> };
>
>-typedef void (*set_dcd_val_t)(struct imx_header *imxhdr,
>+struct data_src;
>+typedef void (*set_dcd_val_t)(struct data_src *ds,
> char *name, int lineno,
> int fld, uint32_t value,
> uint32_t off);
>@@ -168,7 +169,7 @@ typedef void (*set_dcd_rst_t)(struct imx_header
>*imxhdr,
> uint32_t dcd_len,
> char *name, int lineno);
>
>-typedef int (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t dcd_len,
>+typedef int (*set_imx_hdr_t)(struct data_src *ds, uint32_t dcd_len,
> uint32_t entry_point, uint32_t flash_offset);
>
> struct data_src {
>--
>1.7.9.5
>
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V4 06/11] imximage: move set_imx_hdr to struct data_src
2012-11-28 1:31 ` [U-Boot] [PATCH V4 06/11] imximage: move set_imx_hdr to struct data_src Troy Kisky
@ 2012-11-28 10:45 ` Liu Hui-R64343
0 siblings, 0 replies; 430+ messages in thread
From: Liu Hui-R64343 @ 2012-11-28 10:45 UTC (permalink / raw)
To: u-boot
>-----Original Message-----
>From: Troy Kisky [mailto:troy.kisky at boundarydevices.com]
>Sent: Wednesday, November 28, 2012 9:32 AM
>To: sbabic at denx.de
>Cc: dirk.behme at googlemail.com; u-boot at lists.denx.de; Liu Hui-R64343;
>festevam at gmail.com; Troy Kisky
>Subject: [PATCH V4 06/11] imximage: move set_imx_hdr to struct data_src
>
It's better to not let the commit log empty.
>Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Jason Liu <r64343@freescale.com>
>
>---
>v3: new patch
>---
> tools/imximage.c | 13 ++++++-------
> tools/imximage.h | 1 +
> 2 files changed, 7 insertions(+), 7 deletions(-)
>
>diff --git a/tools/imximage.c b/tools/imximage.c index ddac95f..30f3c81
>100644
>--- a/tools/imximage.c
>+++ b/tools/imximage.c
>@@ -67,7 +67,6 @@ static table_entry_t imximage_versions[] = {
>
> static set_dcd_val_t set_dcd_val;
> static set_dcd_rst_t set_dcd_rst;
>-static set_imx_hdr_t set_imx_hdr;
> static uint32_t max_dcd_entries;
> static uint32_t *header_size_ptr;
> static uint32_t g_flash_offset;
>@@ -253,19 +252,19 @@ static int set_imx_hdr_v2(struct data_src *ds,
>uint32_t dcd_len,
> return header_length;
> }
>
>-static void set_hdr_func(struct imx_header *imxhdr, uint32_t
>imximage_version)
>+static void set_hdr_func(struct data_src *ds, uint32_t
>+imximage_version)
> {
> switch (imximage_version) {
> case IMXIMAGE_V1:
> set_dcd_val = set_dcd_val_v1;
> set_dcd_rst = set_dcd_rst_v1;
>- set_imx_hdr = set_imx_hdr_v1;
>+ ds->set_imx_hdr = set_imx_hdr_v1;
> max_dcd_entries = MAX_HW_CFG_SIZE_V1;
> break;
> case IMXIMAGE_V2:
> set_dcd_val = set_dcd_val_v2;
> set_dcd_rst = set_dcd_rst_v2;
>- set_imx_hdr = set_imx_hdr_v2;
>+ ds->set_imx_hdr = set_imx_hdr_v2;
> max_dcd_entries = MAX_HW_CFG_SIZE_V2;
> break;
> default:
>@@ -346,7 +345,7 @@ static void parse_cfg_cmd(struct data_src *ds, int32_t
>cmd, char *token,
> exit(EXIT_FAILURE);
> }
> cmd_ver_first = 1;
>- set_hdr_func(ds->imxhdr, imximage_version);
>+ set_hdr_func(ds, imximage_version);
> break;
> case CMD_BOOT_FROM:
> g_flash_offset = get_table_entry_id(imximage_bootops,
>@@ -431,7 +430,7 @@ static int parse_cfg_file(struct imx_header *imxhdr,
>char *name,
> * by adding VERSION command into it, here need
> * set up function ptr group to V1 by default.
> */
>- set_hdr_func(imxhdr, IMXIMAGE_V1);
>+ set_hdr_func(&ds, IMXIMAGE_V1);
> fd = fopen(name, "r");
> if (fd == 0) {
> fprintf(stderr, "Error: %s - Can't open DCD file\n", name); @@ -
>474,7 +473,7 @@ static int parse_cfg_file(struct imx_header *imxhdr, char
>*name,
> exit(EXIT_FAILURE);
> }
> /* Set the imx header */
>- return (*set_imx_hdr)(&ds, dcd_len, entry_point, g_flash_offset);
>+ return (*ds.set_imx_hdr)(&ds, dcd_len, entry_point, g_flash_offset);
> }
>
> static int imximage_check_image_types(uint8_t type) diff --git
>a/tools/imximage.h b/tools/imximage.h index 3054d55..f27a2ef 100644
>--- a/tools/imximage.h
>+++ b/tools/imximage.h
>@@ -174,5 +174,6 @@ typedef int (*set_imx_hdr_t)(struct data_src *ds,
>uint32_t dcd_len,
>
> struct data_src {
> struct imx_header *imxhdr;
>+ set_imx_hdr_t set_imx_hdr;
> };
> #endif /* _IMXIMAGE_H_ */
>--
>1.7.9.5
>
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V4 07/11] imximage: move set_dcd_val to struct data_src
2012-11-28 1:31 ` [U-Boot] [PATCH V4 07/11] imximage: move set_dcd_val " Troy Kisky
@ 2012-11-28 10:47 ` Liu Hui-R64343
0 siblings, 0 replies; 430+ messages in thread
From: Liu Hui-R64343 @ 2012-11-28 10:47 UTC (permalink / raw)
To: u-boot
>-----Original Message-----
>From: Troy Kisky [mailto:troy.kisky at boundarydevices.com]
>Sent: Wednesday, November 28, 2012 9:32 AM
>To: sbabic at denx.de
>Cc: dirk.behme at googlemail.com; u-boot at lists.denx.de; Liu Hui-R64343;
>festevam at gmail.com; Troy Kisky
>Subject: [PATCH V4 07/11] imximage: move set_dcd_val to struct data_src
>
It's better to not let the commit log empty.
>Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Jason Liu <r64343@freescale.com>
>
>---
>v3: new patch
>---
> tools/imximage.c | 9 ++++-----
> tools/imximage.h | 1 +
> 2 files changed, 5 insertions(+), 5 deletions(-)
>
>diff --git a/tools/imximage.c b/tools/imximage.c index 30f3c81..6d5cfa7
>100644
>--- a/tools/imximage.c
>+++ b/tools/imximage.c
>@@ -65,7 +65,6 @@ static table_entry_t imximage_versions[] = {
> {-1, "", " (Invalid)", },
> };
>
>-static set_dcd_val_t set_dcd_val;
> static set_dcd_rst_t set_dcd_rst;
> static uint32_t max_dcd_entries;
> static uint32_t *header_size_ptr;
>@@ -256,13 +255,13 @@ static void set_hdr_func(struct data_src *ds,
>uint32_t imximage_version) {
> switch (imximage_version) {
> case IMXIMAGE_V1:
>- set_dcd_val = set_dcd_val_v1;
>+ ds->set_dcd_val = set_dcd_val_v1;
> set_dcd_rst = set_dcd_rst_v1;
> ds->set_imx_hdr = set_imx_hdr_v1;
> max_dcd_entries = MAX_HW_CFG_SIZE_V1;
> break;
> case IMXIMAGE_V2:
>- set_dcd_val = set_dcd_val_v2;
>+ ds->set_dcd_val = set_dcd_val_v2;
> set_dcd_rst = set_dcd_rst_v2;
> ds->set_imx_hdr = set_imx_hdr_v2;
> max_dcd_entries = MAX_HW_CFG_SIZE_V2; @@ -360,7 +359,7
>@@ static void parse_cfg_cmd(struct data_src *ds, int32_t cmd, char *token,
> break;
> case CMD_DATA:
> value = get_cfg_value(token, name, lineno);
>- (*set_dcd_val)(ds, name, lineno, fld, value, dcd_len);
>+ (*ds->set_dcd_val)(ds, name, lineno, fld, value, dcd_len);
> if (unlikely(cmd_ver_first != 1))
> cmd_ver_first = 0;
> break;
>@@ -391,7 +390,7 @@ static void parse_cfg_fld(struct data_src *ds, int32_t
>*cmd,
> return;
>
> value = get_cfg_value(token, name, lineno);
>- (*set_dcd_val)(ds, name, lineno, fld, value, *dcd_len);
>+ (*ds->set_dcd_val)(ds, name, lineno, fld, value, *dcd_len);
>
> if (fld == CFG_REG_VALUE) {
> (*dcd_len)++;
>diff --git a/tools/imximage.h b/tools/imximage.h index f27a2ef..444ddce
>100644
>--- a/tools/imximage.h
>+++ b/tools/imximage.h
>@@ -175,5 +175,6 @@ typedef int (*set_imx_hdr_t)(struct data_src *ds,
>uint32_t dcd_len, struct data_src {
> struct imx_header *imxhdr;
> set_imx_hdr_t set_imx_hdr;
>+ set_dcd_val_t set_dcd_val;
> };
> #endif /* _IMXIMAGE_H_ */
>--
>1.7.9.5
>
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V4 08/11] imximage: enable word writes for version2 header
2012-11-28 1:31 ` [U-Boot] [PATCH V4 08/11] imximage: enable word writes for version2 header Troy Kisky
2012-11-28 9:39 ` Wolfgang Denk
@ 2012-11-28 10:47 ` Liu Hui-R64343
1 sibling, 0 replies; 430+ messages in thread
From: Liu Hui-R64343 @ 2012-11-28 10:47 UTC (permalink / raw)
To: u-boot
>-----Original Message-----
>From: Troy Kisky [mailto:troy.kisky at boundarydevices.com]
>Sent: Wednesday, November 28, 2012 9:32 AM
>To: sbabic at denx.de
>Cc: dirk.behme at googlemail.com; u-boot at lists.denx.de; Liu Hui-R64343;
>festevam at gmail.com; Troy Kisky
>Subject: [PATCH V4 08/11] imximage: enable word writes for version2 header
>
>Before, only 1 write_dcd_command table was built.
>Now, a new table is built when the size changes.
>
>Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Jason Liu <r64343@freescale.com>
>
>---
>v3: moved static variables together
>---
> tools/imximage.c | 143 ++++++++++++++++++++++++++----------------------------
> tools/imximage.h | 18 +++----
> 2 files changed, 76 insertions(+), 85 deletions(-)
>
>diff --git a/tools/imximage.c b/tools/imximage.c index 6d5cfa7..2f5ee14
>100644
>--- a/tools/imximage.c
>+++ b/tools/imximage.c
>@@ -65,8 +65,6 @@ static table_entry_t imximage_versions[] = {
> {-1, "", " (Invalid)", },
> };
>
>-static set_dcd_rst_t set_dcd_rst;
>-static uint32_t max_dcd_entries;
> static uint32_t *header_size_ptr;
> static uint32_t g_flash_offset;
>
>@@ -115,7 +113,7 @@ static void err_imximage_version(int version) }
>
> static void set_dcd_val_v1(struct data_src *ds, char *name, int lineno,
>- int fld, uint32_t value, uint32_t off)
>+ int fld, uint32_t value)
> {
> dcd_v1_t *dcd_v1 = &ds->imxhdr->header.hdr_v1.dcd_table;
>
>@@ -128,13 +126,15 @@ static void set_dcd_val_v1(struct data_src *ds, char
>*name, int lineno,
> name, lineno, value);
> exit(EXIT_FAILURE);
> }
>- dcd_v1->addr_data[off].type = value;
>+ *ds->p_entry++ = value;
> break;
> case CFG_REG_ADDRESS:
>- dcd_v1->addr_data[off].addr = value;
>+ *ds->p_entry++ = value;
> break;
> case CFG_REG_VALUE:
>- dcd_v1->addr_data[off].value = value;
>+ *ds->p_entry++ = value;
>+ dcd_v1->preamble.length = (char *)ds->p_entry
>+ - (char *)&dcd_v1->addr_data[0].type;
> break;
> default:
> break;
>@@ -143,16 +143,42 @@ static void set_dcd_val_v1(struct data_src *ds, char
>*name, int lineno, }
>
> static void set_dcd_val_v2(struct data_src *ds, char *name, int lineno,
>- int fld, uint32_t value, uint32_t off)
>+ int fld, uint32_t value)
> {
>+ uint32_t len;
> dcd_v2_t *dcd_v2 = &ds->imxhdr->header.hdr_v2.dcd_table;
>
> switch (fld) {
>+ case CFG_REG_SIZE:
>+ /* Byte, halfword, word */
>+ if ((value != 1) && (value != 2) && (value != 4)) {
>+ fprintf(stderr, "Error: %s[%d] - "
>+ "Invalid register size " "(%d)\n",
>+ name, lineno, value);
>+ exit(EXIT_FAILURE);
>+ }
>+ if (ds->p_dcd && (ds->p_dcd->param == value))
>+ break;
>+ if (!ds->p_dcd) {
>+ dcd_v2->header.tag = DCD_HEADER_TAG;
>+ dcd_v2->header.version = DCD_VERSION;
>+ ds->p_dcd = &dcd_v2->write_dcd_command;
>+ } else {
>+ ds->p_dcd = (write_dcd_command_t *)ds->p_entry;
>+ }
>+ ds->p_dcd->param = value;
>+ ds->p_dcd->tag = DCD_COMMAND_TAG;
>+ ds->p_entry = (uint32_t *)(ds->p_dcd + 1);
>+ break;
> case CFG_REG_ADDRESS:
>- dcd_v2->addr_data[off].addr = cpu_to_be32(value);
>+ *ds->p_entry++ = cpu_to_be32(value);
> break;
> case CFG_REG_VALUE:
>- dcd_v2->addr_data[off].value = cpu_to_be32(value);
>+ *ds->p_entry++ = cpu_to_be32(value);
>+ len = (char *)ds->p_entry - (char *)&dcd_v2->header;
>+ dcd_v2->header.length = cpu_to_be16(len);
>+ len = (char *)ds->p_entry - (char *)ds->p_dcd;
>+ ds->p_dcd->length = cpu_to_be16(len);
> break;
> default:
> break;
>@@ -160,47 +186,14 @@ static void set_dcd_val_v2(struct data_src *ds, char
>*name, int lineno,
> }
> }
>
>-/*
>- * Complete setting up the rest field of DCD of V1
>- * such as barker code and DCD data length.
>- */
>-static void set_dcd_rst_v1(struct imx_header *imxhdr, uint32_t dcd_len,
>- char *name, int lineno)
>-{
>- dcd_v1_t *dcd_v1 = &imxhdr->header.hdr_v1.dcd_table;
>-
>- dcd_v1->preamble.barker = DCD_BARKER;
>- dcd_v1->preamble.length = dcd_len * sizeof(dcd_type_addr_data_t);
>-}
>-
>-/*
>- * Complete setting up the reset field of DCD of V2
>- * such as DCD tag, version, length, etc.
>- */
>-static void set_dcd_rst_v2(struct imx_header *imxhdr, uint32_t dcd_len,
>- char *name, int lineno)
>-{
>- dcd_v2_t *dcd_v2 = &imxhdr->header.hdr_v2.dcd_table;
>-
>- dcd_v2->header.tag = DCD_HEADER_TAG;
>- dcd_v2->header.length = cpu_to_be16(
>- dcd_len * sizeof(dcd_addr_data_t) + 8);
>- dcd_v2->header.version = DCD_VERSION;
>- dcd_v2->write_dcd_command.tag = DCD_COMMAND_TAG;
>- dcd_v2->write_dcd_command.length = cpu_to_be16(
>- dcd_len * sizeof(dcd_addr_data_t) + 4);
>- dcd_v2->write_dcd_command.param = DCD_COMMAND_PARAM;
>-}
>-
>-static int set_imx_hdr_v1(struct data_src *ds, uint32_t dcd_len,
>+static int set_imx_hdr_v1(struct data_src *ds,
> uint32_t entry_point, uint32_t flash_offset) {
> imx_header_v1_t *hdr_v1 = &ds->imxhdr->header.hdr_v1;
> flash_header_v1_t *fhdr_v1 = &hdr_v1->fhdr;
>- dcd_v1_t *dcd_v1 = &hdr_v1->dcd_table;
> uint32_t hdr_base;
>- uint32_t header_length = (((char *)&dcd_v1-
>>addr_data[dcd_len].addr)
>- - ((char *)ds->imxhdr));
>+ uint32_t header_length = ((char *)ds->p_entry) + 4
>+ - ((char *)ds->imxhdr);
>
> /* Set magic number */
> fhdr_v1->app_code_barker = APP_CODE_BARKER; @@ -220,15
>+213,13 @@ static int set_imx_hdr_v1(struct data_src *ds, uint32_t dcd_len,
> return header_length;
> }
>
>-static int set_imx_hdr_v2(struct data_src *ds, uint32_t dcd_len,
>+static int set_imx_hdr_v2(struct data_src *ds,
> uint32_t entry_point, uint32_t flash_offset) {
> imx_header_v2_t *hdr_v2 = &ds->imxhdr->header.hdr_v2;
> flash_header_v2_t *fhdr_v2 = &hdr_v2->fhdr;
> uint32_t hdr_base;
>- uint32_t header_length = (dcd_len) ?
>- (char *)&hdr_v2->dcd_table.addr_data[dcd_len] -
>- ((char *)ds->imxhdr) : offsetof(imx_header_v2_t, dcd_table);
>+ uint32_t header_length = ((char *)ds->p_entry) - ((char *)ds->imxhdr);
>
> /* Set magic number */
> fhdr_v2->header.tag = IVT_HEADER_TAG; /* 0xD1 */ @@ -239,7
>+230,7 @@ static int set_imx_hdr_v2(struct data_src *ds, uint32_t dcd_len,
> fhdr_v2->reserved1 = fhdr_v2->reserved2 = 0;
> fhdr_v2->self = hdr_base = entry_point - header_length;
>
>- fhdr_v2->dcd_ptr = (dcd_len) ? hdr_base
>+ fhdr_v2->dcd_ptr = (ds->p_dcd) ? hdr_base
> + offsetof(imx_header_v2_t, dcd_table) : 0;
> fhdr_v2->boot_data_ptr = hdr_base
> + offsetof(imx_header_v2_t, boot_data); @@ -256,15
>+247,20 @@ static void set_hdr_func(struct data_src *ds, uint32_t
>imximage_version)
> switch (imximage_version) {
> case IMXIMAGE_V1:
> ds->set_dcd_val = set_dcd_val_v1;
>- set_dcd_rst = set_dcd_rst_v1;
> ds->set_imx_hdr = set_imx_hdr_v1;
>- max_dcd_entries = MAX_HW_CFG_SIZE_V1;
>+ ds->p_entry = &ds->imxhdr->header.hdr_v1.dcd_table
>+ .addr_data[0].type;
>+ ds->p_max_dcd = &ds->imxhdr->header.hdr_v1.dcd_table
>+ .addr_data[MAX_HW_CFG_SIZE_V1].type;
>+ ds->imxhdr->header.hdr_v1.dcd_table.preamble.barker =
>+ DCD_BARKER;
> break;
> case IMXIMAGE_V2:
> ds->set_dcd_val = set_dcd_val_v2;
>- set_dcd_rst = set_dcd_rst_v2;
> ds->set_imx_hdr = set_imx_hdr_v2;
>- max_dcd_entries = MAX_HW_CFG_SIZE_V2;
>+ ds->p_entry = (uint32_t *)&ds->imxhdr-
>>header.hdr_v2.dcd_table;
>+ ds->p_max_dcd = (uint32_t *)
>+ ((char *)ds->imxhdr + MAX_HEADER_SIZE);
> break;
> default:
> err_imximage_version(imximage_version);
>@@ -328,7 +324,7 @@ static void print_hdr_v2(struct imx_header
>*imx_hdr) }
>
> static void parse_cfg_cmd(struct data_src *ds, int32_t cmd, char *token,
>- char *name, int lineno, int fld, int dcd_len)
>+ char *name, int lineno, int fld)
> {
> int value;
> static int cmd_ver_first = ~0;
>@@ -359,7 +355,7 @@ static void parse_cfg_cmd(struct data_src *ds, int32_t
>cmd, char *token,
> break;
> case CMD_DATA:
> value = get_cfg_value(token, name, lineno);
>- (*ds->set_dcd_val)(ds, name, lineno, fld, value, dcd_len);
>+ (*ds->set_dcd_val)(ds, name, lineno, fld, value);
> if (unlikely(cmd_ver_first != 1))
> cmd_ver_first = 0;
> break;
>@@ -367,7 +363,7 @@ static void parse_cfg_cmd(struct data_src *ds, int32_t
>cmd, char *token, }
>
> static void parse_cfg_fld(struct data_src *ds, int32_t *cmd,
>- char *token, char *name, int lineno, int fld, int *dcd_len)
>+ char *token, char *name, int lineno, int fld)
> {
> int value;
>
>@@ -382,7 +378,7 @@ static void parse_cfg_fld(struct data_src *ds, int32_t
>*cmd,
> }
> break;
> case CFG_REG_SIZE:
>- parse_cfg_cmd(ds, *cmd, token, name, lineno, fld, *dcd_len);
>+ parse_cfg_cmd(ds, *cmd, token, name, lineno, fld);
> break;
> case CFG_REG_ADDRESS:
> case CFG_REG_VALUE:
>@@ -390,16 +386,14 @@ static void parse_cfg_fld(struct data_src *ds,
>int32_t *cmd,
> return;
>
> value = get_cfg_value(token, name, lineno);
>- (*ds->set_dcd_val)(ds, name, lineno, fld, value, *dcd_len);
>-
>- if (fld == CFG_REG_VALUE) {
>- (*dcd_len)++;
>- if (*dcd_len > max_dcd_entries) {
>- fprintf(stderr, "Error: %s[%d] -"
>- "DCD table exceeds maximum size(%d)\n",
>- name, lineno, max_dcd_entries);
>- exit(EXIT_FAILURE);
>- }
>+ (*ds->set_dcd_val)(ds, name, lineno, fld, value);
>+ if (ds->p_entry > ds->p_max_dcd) {
>+ uint32_t size = (char *)ds->p_max_dcd -
>+ (char *)ds->imxhdr;
>+ fprintf(stderr, "Error: %s[%d] -"
>+ "header exceeds maximum size(%d)\n",
>+ name, lineno, size);
>+ exit(EXIT_FAILURE);
> }
> break;
> default:
>@@ -417,7 +411,6 @@ static int parse_cfg_file(struct imx_header *imxhdr,
>char *name,
> int lineno = 0;
> int fld;
> size_t len;
>- int dcd_len = 0;
> int32_t cmd;
>
> /* Be able to detect if the cfg file has no BOOT_FROM tag */ @@ -
>458,12 +451,10 @@ static int parse_cfg_file(struct imx_header *imxhdr, char
>*name,
> break;
>
> parse_cfg_fld(&ds, &cmd, token, name,
>- lineno, fld, &dcd_len);
>+ lineno, fld);
> }
>
> }
>-
>- (*set_dcd_rst)(imxhdr, dcd_len, name, lineno);
> fclose(fd);
>
> /* Exit if there is no BOOT_FROM field specifying the flash_offset */
>@@ -472,7 +463,7 @@ static int parse_cfg_file(struct imx_header *imxhdr,
>char *name,
> exit(EXIT_FAILURE);
> }
> /* Set the imx header */
>- return (*ds.set_imx_hdr)(&ds, dcd_len, entry_point, g_flash_offset);
>+ return (*ds.set_imx_hdr)(&ds, entry_point, g_flash_offset);
> }
>
> static int imximage_check_image_types(uint8_t type) @@ -517,7 +508,11
>@@ int imximage_vrec_header(struct mkimage_params *params, {
> struct imx_header *imxhdr;
>
>- imxhdr = calloc(1, MAX_HEADER_SIZE);
>+ /*
>+ * A little extra space to avoid access violation on dcd table overflow.
>+ * Overflow is checked after entry is added.
>+ */
>+ imxhdr = calloc(1, MAX_HEADER_SIZE + 32);
> if (!imxhdr) {
> fprintf(stderr, "Error: out of memory\n");
> exit(EXIT_FAILURE);
>diff --git a/tools/imximage.h b/tools/imximage.h index 444ddce..196bb51
>100644
>--- a/tools/imximage.h
>+++ b/tools/imximage.h
>@@ -47,7 +47,6 @@
> #define DCD_HEADER_TAG 0xD2
> #define DCD_COMMAND_TAG 0xCC
> #define DCD_VERSION 0x40
>-#define DCD_COMMAND_PARAM 0x4
>
> enum imximage_cmd {
> CMD_INVALID,
>@@ -160,21 +159,18 @@ struct imx_header { };
>
> struct data_src;
>-typedef void (*set_dcd_val_t)(struct data_src *ds,
>- char *name, int lineno,
>- int fld, uint32_t value,
>- uint32_t off);
>+typedef void (*set_dcd_val_t)(struct data_src *ds, char *name,
>+ int lineno, int fld, uint32_t value);
>
>-typedef void (*set_dcd_rst_t)(struct imx_header *imxhdr,
>- uint32_t dcd_len,
>- char *name, int lineno);
>-
>-typedef int (*set_imx_hdr_t)(struct data_src *ds, uint32_t dcd_len,
>- uint32_t entry_point, uint32_t flash_offset);
>+typedef int (*set_imx_hdr_t)(struct data_src *ds, uint32_t entry_point,
>+ uint32_t flash_offset);
>
> struct data_src {
> struct imx_header *imxhdr;
> set_imx_hdr_t set_imx_hdr;
> set_dcd_val_t set_dcd_val;
>+ uint32_t *p_max_dcd;
>+ uint32_t *p_entry;
>+ write_dcd_command_t *p_dcd;
> };
> #endif /* _IMXIMAGE_H_ */
>--
>1.7.9.5
>
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V4 09/11] tools: add parse_helper file
2012-11-28 1:31 ` [U-Boot] [PATCH V4 09/11] tools: add parse_helper file Troy Kisky
2012-11-28 9:41 ` Wolfgang Denk
@ 2012-11-28 10:48 ` Liu Hui-R64343
1 sibling, 0 replies; 430+ messages in thread
From: Liu Hui-R64343 @ 2012-11-28 10:48 UTC (permalink / raw)
To: u-boot
>-----Original Message-----
>From: Troy Kisky [mailto:troy.kisky at boundarydevices.com]
>Sent: Wednesday, November 28, 2012 9:32 AM
>To: sbabic at denx.de
>Cc: dirk.behme at googlemail.com; u-boot at lists.denx.de; Liu Hui-R64343;
>festevam at gmail.com; Troy Kisky
>Subject: [PATCH V4 09/11] tools: add parse_helper file
>
>This file can help you parse
>configuration files.
One line is enough. :)
>
>Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Jason Liu <r64343@freescale.com>
>---
> tools/Makefile | 2 +
> tools/parse_helper.c | 173
>++++++++++++++++++++++++++++++++++++++++++++++++++
> tools/parse_helper.h | 28 ++++++++
> 3 files changed, 203 insertions(+)
> create mode 100644 tools/parse_helper.c create mode 100644
>tools/parse_helper.h
>
>diff --git a/tools/Makefile b/tools/Makefile index 686840a..db3b247 100644
>--- a/tools/Makefile
>+++ b/tools/Makefile
>@@ -94,6 +94,7 @@ NOPED_OBJ_FILES-y += aisimage.o NOPED_OBJ_FILES-y
>+= kwbimage.o NOPED_OBJ_FILES-y += pblimage.o NOPED_OBJ_FILES-y +=
>imximage.o
>+NOPED_OBJ_FILES-y += parse_helper.o
> NOPED_OBJ_FILES-y += omapimage.o
> NOPED_OBJ_FILES-y += mkenvimage.o
> NOPED_OBJ_FILES-y += mkimage.o
>@@ -208,6 +209,7 @@ $(obj)mkimage$(SFX): $(obj)aisimage.o \
> $(obj)fit_image.o \
> $(obj)image.o \
> $(obj)imximage.o \
>+ $(obj)parse_helper.o \
> $(obj)kwbimage.o \
> $(obj)pblimage.o \
> $(obj)md5.o \
>diff --git a/tools/parse_helper.c b/tools/parse_helper.c new file mode 100644
>index 0000000..0a5c5f6
>--- /dev/null
>+++ b/tools/parse_helper.c
>@@ -0,0 +1,173 @@
>+/*
>+ * (C) Copyright 20012 Boundary Devices Inc,
>+troy.kisky at boundarydevices.com
>+ *
>+ * Licensed under the GPL-2 or later.
>+ */
>+
>+/* Required to obtain the getline prototype from stdio.h */ #define
>+_GNU_SOURCE
>+
>+#include "mkimage.h"
>+#include <image.h>
>+#include "parse_helper.h"
>+
>+int ph_open(struct parse_helper *ph, char *filename) {
>+ ph->line = NULL;
>+ ph->len = 0;
>+ ph->fd = fopen(filename, "r");
>+ ph->lineno = 0;
>+ ph->cmd_started = 0;
>+ ph->filename = filename;
>+ ph->p = NULL;
>+ return (!ph->fd) ? -1 : 0;
>+}
>+
>+void ph_close(struct parse_helper *ph)
>+{
>+ fclose(ph->fd);
>+ ph->fd = NULL;
>+}
>+
>+int ph_skip_separators(struct parse_helper *ph) {
>+ int line_no = ph->lineno;
>+ char *p = ph->p;
>+
>+ for (;;) {
>+ char c;
>+ if (!p) {
>+ if (getline(&ph->line, &ph->len, ph->fd) <= 0)
>+ return -1;
>+ ph->lineno++;
>+ p = ph->line;
>+ if (ph->cmd_started) {
>+ fprintf(stderr, "warning: continuing command
>on"
>+ " next line, line %s[%d](%s)\n",
>+ ph->filename, ph->lineno, p);
>+ }
>+ }
>+ c = *p;
>+ if ((c == ' ') || (c == '\t')) {
>+ p++;
>+ continue;
>+ }
>+ /* Drop all text starting with '#' as comments */
>+ if ((c == '#') || (c == '\r') || (c == '\n')
>+ || !c) {
>+ p = NULL;
>+ continue;
>+ }
>+ if (c == ';') {
>+ if (ph->cmd_started) {
>+ fprintf(stderr, "Error: command not "
>+ "finished:%s[%d](%s)\n",
>+ ph->filename, ph->lineno, p);
>+ exit(EXIT_FAILURE);
>+ }
>+ p++;
>+ continue;
>+ }
>+ if (!ph->cmd_started && line_no == ph->lineno) {
>+ fprintf(stderr, "Error: extra data at end "
>+ "of line %s[%d](%s)\n",
>+ ph->filename, ph->lineno, p);
>+ exit(EXIT_FAILURE);
>+ }
>+ ph->p = p;
>+ return 0;
>+ }
>+}
>+
>+int ph_skip_comma(struct parse_helper *ph) {
>+ char *p = ph->p;
>+
>+ for (;;) {
>+ char c = *p++;
>+ if ((c == '#') || (c == '\r') || (c == '\n') || !c)
>+ return 0;
>+ if (c == ',') {
>+ ph->p = p;
>+ ph_skip_separators(ph);
>+ return 1;
>+ }
>+ if ((c != ' ') && (c == '\t'))
>+ return 0;
>+ }
>+}
>+
>+int ph_get_value(struct parse_helper *ph, uint32_t *pval) {
>+ char *endptr;
>+ uint32_t value;
>+
>+ if (ph_skip_separators(ph))
>+ return -1;
>+ errno = 0;
>+ value = strtoul(ph->p, &endptr, 16);
>+ if (errno || (ph->p == endptr))
>+ return -1;
>+ *pval = value;
>+ ph->p = endptr;
>+ return 0;
>+}
>+
>+/*
>+ * Comma separator optional
>+ * Input:
>+ * ph - input source
>+ * data - array to fill in
>+ * cnt - exact number of elements to parse
>+ * Return: number of elements parsed, or error */ int
>+ph_get_array(struct parse_helper *ph, uint32_t *data, int cnt) {
>+ int i = 0;
>+
>+ for (;;) {
>+ int ret = ph_get_value(ph, &data[i++]);
>+ if (ret)
>+ return ret;
>+ if (i >= cnt)
>+ break;
>+ ph_skip_comma(ph); /* comma is optional */
>+ }
>+ return i;
>+}
>+
>+static char *grab_token(char *dest, int size, char *src) {
>+ while (size) {
>+ char c = *src;
>+ if ((c == ' ') || (c == '\t') || (c == '\r') || (c == '\n')
>+ || (c == '#') || !c)
>+ break;
>+ *dest++ = c;
>+ size--;
>+ src++;
>+ }
>+ if (!size)
>+ return NULL;
>+ *dest = 0;
>+ return src;
>+}
>+
>+int ph_get_table_entry_id(struct parse_helper *ph,
>+ const table_entry_t *table, const char *table_name) {
>+ int val;
>+ char token[16];
>+ char *p;
>+
>+ if (ph_skip_separators(ph))
>+ return -1;
>+ p = grab_token(token, sizeof(token), ph->p);
>+ if (!p)
>+ return -1;
>+ val = get_table_entry_id(table, table_name, token);
>+ if (val != -1)
>+ ph->p = p;
>+ return val;
>+}
>+
>diff --git a/tools/parse_helper.h b/tools/parse_helper.h new file mode
>100644 index 0000000..1ff98a3
>--- /dev/null
>+++ b/tools/parse_helper.h
>@@ -0,0 +1,28 @@
>+/*
>+ * (C) Copyright 20012 Boundary Devices Inc,
>+troy.kisky at boundarydevices.com
>+ *
>+ * Licensed under the GPL-2 or later.
>+ */
>+
>+#ifndef _PARSE_HELPER_H_
>+#define _PARSE_HELPER_H_
>+
>+struct parse_helper {
>+ char *line;
>+ size_t len;
>+ FILE *fd;
>+ int lineno;
>+ char cmd_started;
>+ char *filename;
>+ char *p;
>+};
>+
>+int ph_open(struct parse_helper *ph, char *filename); void
>+ph_close(struct parse_helper *ph); int ph_skip_separators(struct
>+parse_helper *ph); int ph_skip_comma(struct parse_helper *ph); int
>+ph_get_value(struct parse_helper *ph, uint32_t *pval); int
>+ph_get_array(struct parse_helper *ph, uint32_t *data, int cnt); int
>+ph_get_table_entry_id(struct parse_helper *ph,
>+ const table_entry_t *table, const char *table_name); #endif
>--
>1.7.9.5
>
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V4 10/11] imximage: use parse_helper functions
2012-11-28 1:31 ` [U-Boot] [PATCH V4 10/11] imximage: use parse_helper functions Troy Kisky
@ 2012-11-28 10:48 ` Liu Hui-R64343
0 siblings, 0 replies; 430+ messages in thread
From: Liu Hui-R64343 @ 2012-11-28 10:48 UTC (permalink / raw)
To: u-boot
>-----Original Message-----
>From: Troy Kisky [mailto:troy.kisky at boundarydevices.com]
>Sent: Wednesday, November 28, 2012 9:32 AM
>To: sbabic at denx.de
>Cc: dirk.behme at googlemail.com; u-boot at lists.denx.de; Liu Hui-R64343;
>festevam at gmail.com; Troy Kisky
>Subject: [PATCH V4 10/11] imximage: use parse_helper functions
>
>Use parse_helper functions to pulling tokens instead of pushing them.
>Remove need for switch statements to process commands.
>
>Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Jason Liu <r64343@freescale.com>
>
>---
>v2: uses file parse_helper added in previous patch changed patch subject,
>was cleanup parsing
>---
> tools/imximage.c | 267 +++++++++++++++++++-----------------------------------
> tools/imximage.h | 17 ++--
> 2 files changed, 101 insertions(+), 183 deletions(-)
>
>diff --git a/tools/imximage.c b/tools/imximage.c index 2f5ee14..5147989
>100644
>--- a/tools/imximage.c
>+++ b/tools/imximage.c
>@@ -25,9 +25,6 @@
> * MA 02111-1307 USA
> */
>
>-/* Required to obtain the getline prototype from stdio.h */ -#define
>_GNU_SOURCE
>-
> #include "mkimage.h"
> #include <image.h>
> #include "imximage.h"
>@@ -70,21 +67,6 @@ static uint32_t g_flash_offset;
>
> static struct image_type_params imximage_params;
>
>-static uint32_t get_cfg_value(char *token, char *name, int linenr) -{
>- char *endptr;
>- uint32_t value;
>-
>- errno = 0;
>- value = strtoul(token, &endptr, 16);
>- if (errno || (token == endptr)) {
>- fprintf(stderr, "Error: %s[%d] - Invalid hex data(%s)\n",
>- name, linenr, token);
>- exit(EXIT_FAILURE);
>- }
>- return value;
>-}
>-
> static uint32_t detect_imximage_version(struct imx_header *imx_hdr) {
> imx_header_v1_t *hdr_v1 = &imx_hdr->header.hdr_v1; @@ -112,53
>+94,36 @@ static void err_imximage_version(int version)
> exit(EXIT_FAILURE);
> }
>
>-static void set_dcd_val_v1(struct data_src *ds, char *name, int lineno,
>- int fld, uint32_t value)
>+static int set_dcd_val_v1(struct data_src *ds, uint32_t *data)
> {
> dcd_v1_t *dcd_v1 = &ds->imxhdr->header.hdr_v1.dcd_table;
>+ uint32_t val = *data++;
>
>- switch (fld) {
>- case CFG_REG_SIZE:
>- /* Byte, halfword, word */
>- if ((value != 1) && (value != 2) && (value != 4)) {
>- fprintf(stderr, "Error: %s[%d] - "
>- "Invalid register size " "(%d)\n",
>- name, lineno, value);
>- exit(EXIT_FAILURE);
>- }
>- *ds->p_entry++ = value;
>- break;
>- case CFG_REG_ADDRESS:
>- *ds->p_entry++ = value;
>- break;
>- case CFG_REG_VALUE:
>- *ds->p_entry++ = value;
>- dcd_v1->preamble.length = (char *)ds->p_entry
>- - (char *)&dcd_v1->addr_data[0].type;
>- break;
>- default:
>- break;
>-
>+ /* Byte, halfword, word */
>+ if ((val != 1) && (val != 2) && (val != 4)) {
>+ fprintf(stderr, "Error: Invalid register size (%d)\n", val);
>+ return -1;
> }
>+ *ds->p_entry++ = val;
>+ *ds->p_entry++ = *data++;
>+ *ds->p_entry++ = *data++;
>+ dcd_v1->preamble.length = (char *)ds->p_entry - (char *)&dcd_v1->
>+ addr_data[0].type;
>+ return 0;
> }
>
>-static void set_dcd_val_v2(struct data_src *ds, char *name, int lineno,
>- int fld, uint32_t value)
>+static int set_dcd_val_v2(struct data_src *ds, uint32_t *data)
> {
> uint32_t len;
> dcd_v2_t *dcd_v2 = &ds->imxhdr->header.hdr_v2.dcd_table;
>+ uint32_t val = *data++;
>
>- switch (fld) {
>- case CFG_REG_SIZE:
>- /* Byte, halfword, word */
>- if ((value != 1) && (value != 2) && (value != 4)) {
>- fprintf(stderr, "Error: %s[%d] - "
>- "Invalid register size " "(%d)\n",
>- name, lineno, value);
>- exit(EXIT_FAILURE);
>- }
>- if (ds->p_dcd && (ds->p_dcd->param == value))
>- break;
>+ /* Byte, halfword, word */
>+ if ((val != 1) && (val != 2) && (val != 4)) {
>+ fprintf(stderr, "Error: Invalid register size (%d)\n", val);
>+ return -1;
>+ }
>+ if (!(ds->p_dcd && (ds->p_dcd->param == val))) {
> if (!ds->p_dcd) {
> dcd_v2->header.tag = DCD_HEADER_TAG;
> dcd_v2->header.version = DCD_VERSION; @@ -166,24
>+131,19 @@ static void set_dcd_val_v2(struct data_src *ds, char *name, int
>lineno,
> } else {
> ds->p_dcd = (write_dcd_command_t *)ds->p_entry;
> }
>- ds->p_dcd->param = value;
>+ ds->p_dcd->param = val;
> ds->p_dcd->tag = DCD_COMMAND_TAG;
> ds->p_entry = (uint32_t *)(ds->p_dcd + 1);
>- break;
>- case CFG_REG_ADDRESS:
>- *ds->p_entry++ = cpu_to_be32(value);
>- break;
>- case CFG_REG_VALUE:
>- *ds->p_entry++ = cpu_to_be32(value);
>- len = (char *)ds->p_entry - (char *)&dcd_v2->header;
>- dcd_v2->header.length = cpu_to_be16(len);
>- len = (char *)ds->p_entry - (char *)ds->p_dcd;
>- ds->p_dcd->length = cpu_to_be16(len);
>- break;
>- default:
>- break;
>-
> }
>+ val = *data++;
>+ *ds->p_entry++ = cpu_to_be32(val);
>+ val = *data++;
>+ *ds->p_entry++ = cpu_to_be32(val);
>+ len = (char *)ds->p_entry - (char *)&dcd_v2->header;
>+ dcd_v2->header.length = cpu_to_be16(len);
>+ len = (char *)ds->p_entry - (char *)ds->p_dcd;
>+ ds->p_dcd->length = cpu_to_be16(len);
>+ return 0;
> }
>
> static int set_imx_hdr_v1(struct data_src *ds, @@ -323,95 +283,71 @@
>static void print_hdr_v2(struct imx_header *imx_hdr)
> printf("Entry Point: %08x\n", (uint32_t)fhdr_v2->entry); }
>
>-static void parse_cfg_cmd(struct data_src *ds, int32_t cmd, char *token,
>- char *name, int lineno, int fld)
>+static int parse_cmd_data(struct data_src *ds) {
>+ uint32_t data[3];
>+ int ret = ph_get_array(&ds->ph, data, 3);
>+
>+ if (ret < 0)
>+ return ret;
>+ ret = (*ds->set_dcd_val)(ds, data);
>+ if (ret)
>+ return ret;
>+ if (ds->p_entry > ds->p_max_dcd) {
>+ uint32_t size = (char *)ds->p_max_dcd - (char *)ds->imxhdr;
>+ fprintf(stderr, "Error: header exceeds maximum size(%d)\n",
>+ size);
>+ return -1;
>+ }
>+ return 0;
>+}
>+
>+static int parse_image_version(struct data_src *ds)
> {
>- int value;
>- static int cmd_ver_first = ~0;
>+ int ret;
> uint32_t imximage_version;
>
>- switch (cmd) {
>- case CMD_IMAGE_VERSION:
>- imximage_version = get_cfg_value(token, name, lineno);
>- if (cmd_ver_first == 0) {
>- fprintf(stderr, "Error: %s[%d] - IMAGE_VERSION "
>- "command need be the first before other "
>- "valid command in the file\n", name, lineno);
>- exit(EXIT_FAILURE);
>- }
>- cmd_ver_first = 1;
>- set_hdr_func(ds, imximage_version);
>- break;
>- case CMD_BOOT_FROM:
>- g_flash_offset = get_table_entry_id(imximage_bootops,
>- "imximage boot option", token);
>- if (g_flash_offset == -1) {
>- fprintf(stderr, "Error: %s[%d] -Invalid boot device"
>- "(%s)\n", name, lineno, token);
>- exit(EXIT_FAILURE);
>- }
>- if (unlikely(cmd_ver_first != 1))
>- cmd_ver_first = 0;
>- break;
>- case CMD_DATA:
>- value = get_cfg_value(token, name, lineno);
>- (*ds->set_dcd_val)(ds, name, lineno, fld, value);
>- if (unlikely(cmd_ver_first != 1))
>- cmd_ver_first = 0;
>- break;
>+ ret = ph_get_value(&ds->ph, &imximage_version);
>+ if (ret)
>+ return ret;
>+ if (ds->cmd_cnt) {
>+ fprintf(stderr, "Error: IMAGE_VERSION command needs be "
>+ "before other valid commands in the file\n");
>+ return -1;
> }
>+ set_hdr_func(ds, imximage_version);
>+ return 0;
> }
>
>-static void parse_cfg_fld(struct data_src *ds, int32_t *cmd,
>- char *token, char *name, int lineno, int fld)
>+static int parse_boot_from(struct data_src *ds)
> {
>- int value;
>-
>- switch (fld) {
>- case CFG_COMMAND:
>- *cmd = get_table_entry_id(imximage_cmds,
>- "imximage commands", token);
>- if (*cmd < 0) {
>- fprintf(stderr, "Error: %s[%d] - Invalid command"
>- "(%s)\n", name, lineno, token);
>- exit(EXIT_FAILURE);
>- }
>- break;
>- case CFG_REG_SIZE:
>- parse_cfg_cmd(ds, *cmd, token, name, lineno, fld);
>- break;
>- case CFG_REG_ADDRESS:
>- case CFG_REG_VALUE:
>- if (*cmd != CMD_DATA)
>- return;
>-
>- value = get_cfg_value(token, name, lineno);
>- (*ds->set_dcd_val)(ds, name, lineno, fld, value);
>- if (ds->p_entry > ds->p_max_dcd) {
>- uint32_t size = (char *)ds->p_max_dcd -
>- (char *)ds->imxhdr;
>- fprintf(stderr, "Error: %s[%d] -"
>- "header exceeds maximum size(%d)\n",
>- name, lineno, size);
>- exit(EXIT_FAILURE);
>- }
>- break;
>- default:
>- break;
>+ g_flash_offset = ph_get_table_entry_id(&ds->ph, imximage_bootops,
>+ "imximage boot option");
>+ if (g_flash_offset == -1) {
>+ fprintf(stderr, "Error: Invalid boot device\n");
>+ return -1;
> }
>+ return 0;
>+}
>+
>+static const parse_fld_t cmd_table[] = {
>+ parse_image_version, parse_boot_from, parse_cmd_data };
>+
>+static int parse_command(struct data_src *ds) {
>+ int cmd = ph_get_table_entry_id(&ds->ph, imximage_cmds,
>+ "imximage commands");
>+ if (cmd < 0)
>+ return cmd;
>+ return cmd_table[cmd](ds);
> }
>
> static int parse_cfg_file(struct imx_header *imxhdr, char *name,
> uint32_t entry_point)
> {
> struct data_src ds;
>- FILE *fd = NULL;
>- char *line = NULL;
>- char *token, *saveptr1, *saveptr2;
>- int lineno = 0;
>- int fld;
>- size_t len;
>- int32_t cmd;
>+ struct parse_helper *ph = &ds.ph;
>
> /* Be able to detect if the cfg file has no BOOT_FROM tag */
> g_flash_offset = FLASH_OFFSET_UNDEFINED; @@ -423,8 +359,7 @@
>static int parse_cfg_file(struct imx_header *imxhdr, char *name,
> * set up function ptr group to V1 by default.
> */
> set_hdr_func(&ds, IMXIMAGE_V1);
>- fd = fopen(name, "r");
>- if (fd == 0) {
>+ if (ph_open(ph, name)) {
> fprintf(stderr, "Error: %s - Can't open DCD file\n", name);
> exit(EXIT_FAILURE);
> }
>@@ -432,31 +367,19 @@ static int parse_cfg_file(struct imx_header *imxhdr,
>char *name,
> /* Very simple parsing, line starting with # are comments
> * and are dropped
> */
>- while ((getline(&line, &len, fd)) > 0) {
>- lineno++;
>-
>- token = strtok_r(line, "\r\n", &saveptr1);
>- if (token == NULL)
>- continue;
>-
>- /* Check inside the single line */
>- for (fld = CFG_COMMAND, cmd = CMD_INVALID,
>- line = token; ; line = NULL, fld++) {
>- token = strtok_r(line, " \t", &saveptr2);
>- if (token == NULL)
>- break;
>-
>- /* Drop all text starting with '#' as comments */
>- if (token[0] == '#')
>- break;
>-
>- parse_cfg_fld(&ds, &cmd, token, name,
>- lineno, fld);
>+ for (;;) {
>+ ph->cmd_started = 0;
>+ if (ph_skip_separators(ph))
>+ break;
>+ ph->cmd_started = 1;
>+ if (parse_command(&ds)) {
>+ fprintf(stderr, "Error: invalid token %s[%d](%s)\n",
>+ name, ph->lineno, ph->p);
>+ exit(EXIT_FAILURE);
> }
>-
>+ ds.cmd_cnt++;
> }
>- fclose(fd);
>-
>+ ph_close(ph);
> /* Exit if there is no BOOT_FROM field specifying the flash_offset */
> if (g_flash_offset == FLASH_OFFSET_UNDEFINED) {
> fprintf(stderr, "Error: No BOOT_FROM tag in %s\n", name); @@
>-546,12 +469,12 @@ static void imximage_set_header(void *ptr, struct stat
>*sbuf, int ifd, int imximage_check_params(struct mkimage_params *params)
>{
> if (!params)
>- return CFG_INVALID;
>+ return -1;
> if (!strlen(params->imagename)) {
> fprintf(stderr, "Error: %s - Configuration file not specified, "
> "it is needed for imximage generation\n",
> params->cmdname);
>- return CFG_INVALID;
>+ return -1;
> }
> /*
> * Check parameters:
>diff --git a/tools/imximage.h b/tools/imximage.h index 196bb51..6bcd082
>100644
>--- a/tools/imximage.h
>+++ b/tools/imximage.h
>@@ -23,6 +23,7 @@
>
> #ifndef _IMXIMAGE_H_
> #define _IMXIMAGE_H_
>+#include "parse_helper.h"
>
> #define MAX_HW_CFG_SIZE_V2 121 /* Max number of registers imx can set
>for v2 */ #define MAX_HW_CFG_SIZE_V1 60 /* Max number of registers imx
>can set for v1 */ @@ -49,20 +50,11 @@ #define DCD_VERSION 0x40
>
> enum imximage_cmd {
>- CMD_INVALID,
> CMD_IMAGE_VERSION,
> CMD_BOOT_FROM,
> CMD_DATA
> };
>
>-enum imximage_fld_types {
>- CFG_INVALID = -1,
>- CFG_COMMAND,
>- CFG_REG_SIZE,
>- CFG_REG_ADDRESS,
>- CFG_REG_VALUE
>-};
>-
> enum imximage_version {
> IMXIMAGE_VER_INVALID = -1,
> IMXIMAGE_V1 = 1,
>@@ -159,14 +151,17 @@ struct imx_header { };
>
> struct data_src;
>-typedef void (*set_dcd_val_t)(struct data_src *ds, char *name,
>- int lineno, int fld, uint32_t value);
>+typedef int (*parse_fld_t)(struct data_src *ds);
>+
>+typedef int (*set_dcd_val_t)(struct data_src *ds, uint32_t *data);
>
> typedef int (*set_imx_hdr_t)(struct data_src *ds, uint32_t entry_point,
> uint32_t flash_offset);
>
> struct data_src {
>+ struct parse_helper ph;
> struct imx_header *imxhdr;
>+ int cmd_cnt;
> set_imx_hdr_t set_imx_hdr;
> set_dcd_val_t set_dcd_val;
> uint32_t *p_max_dcd;
>--
>1.7.9.5
>
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V4 11/11] parse_helper: add expression evaluation
2012-11-28 1:31 ` [U-Boot] [PATCH V4 11/11] parse_helper: add expression evaluation Troy Kisky
@ 2012-11-28 10:49 ` Liu Hui-R64343
0 siblings, 0 replies; 430+ messages in thread
From: Liu Hui-R64343 @ 2012-11-28 10:49 UTC (permalink / raw)
To: u-boot
>-----Original Message-----
>From: Troy Kisky [mailto:troy.kisky at boundarydevices.com]
>Sent: Wednesday, November 28, 2012 9:32 AM
>To: sbabic at denx.de
>Cc: dirk.behme at googlemail.com; u-boot at lists.denx.de; Liu Hui-R64343;
>festevam at gmail.com; Troy Kisky
>Subject: [PATCH V4 11/11] parse_helper: add expression evaluation
>
>Basic expressions with order precedence is now supported.
>ie. (----3 + ((1+2*3)/--2 + --5 *(8/4))) is 16.
>
>Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Jason Liu <r64343@freescale.com>
>---
> tools/parse_helper.c | 172
>+++++++++++++++++++++++++++++++++++++++++++++++---
> 1 file changed, 162 insertions(+), 10 deletions(-)
>
>diff --git a/tools/parse_helper.c b/tools/parse_helper.c index
>0a5c5f6..50be832 100644
>--- a/tools/parse_helper.c
>+++ b/tools/parse_helper.c
>@@ -97,20 +97,172 @@ int ph_skip_comma(struct parse_helper *ph)
> }
> }
>
>+static const char precedence[] = {
>+ /* ( + - * / & ^ | ) */
>+ 0, 2, 2, 1, 1, 3, 4, 5, 6
>+};
>+static const char unary_operations[] = "(+-"; static const char
>+binary_operations[] = " +-*/&^|)";
>+
>+static uint32_t do_func(uint32_t val1, uint32_t val2, int op) {
>+ switch (op) {
>+ case 1:
>+ return val1 + val2;
>+ case 2:
>+ return val1 - val2;
>+ case 3:
>+ return val1 * val2;
>+ case 4:
>+ return val1 / val2;
>+ case 5:
>+ return val1 & val2;
>+ case 6:
>+ return val1 ^ val2;
>+ case 7:
>+ return val1 | val2;
>+ }
>+ fprintf(stderr, "Error: in func %s: val1=%d val2=%d op = %d\n",
>+ __func__, val1, val2, op);
>+ exit(EXIT_FAILURE);
>+}
>+
>+static int find_op(char c, const char *p) {
>+ int i;
>+ for (i = 0; ; i++) {
>+ if (c == p[i])
>+ return i;
>+ if (!p[i])
>+ break;
>+ }
>+ return -1;
>+}
>+
>+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
>+
> int ph_get_value(struct parse_helper *ph, uint32_t *pval) {
> char *endptr;
>- uint32_t value;
>+ int op_i = 0;
>+ int val_i = 0;
>+ unsigned char op[16];
>+ uint32_t val[16];
>+ int unary = 1;
>+ char *p;
>
>- if (ph_skip_separators(ph))
>- return -1;
>- errno = 0;
>- value = strtoul(ph->p, &endptr, 16);
>- if (errno || (ph->p == endptr))
>- return -1;
>- *pval = value;
>- ph->p = endptr;
>- return 0;
>+ p = ph->p;
>+ for (;;) {
>+ char c;
>+ int i, j;
>+ const char *ops = unary ? unary_operations :
>binary_operations;
>+
>+ if (unary) {
>+ ph->p = p;
>+ if (ph_skip_separators(ph))
>+ return -1;
>+ p = ph->p;
>+ c = *p;
>+ } else {
>+ for (;;) {
>+ c = *p;
>+ if ((c != ' ') && (c != '\t'))
>+ break;
>+ p++;
>+ }
>+ }
>+ i = find_op(c, ops);
>+ debug("%d,%c,%d:%s\n", i, c, unary, p);
>+ if ((i < 0) && unary) {
>+ if (val_i >= ARRAY_SIZE(val))
>+ return -1;
>+ errno = 0;
>+ val[val_i++] = strtoul(p, &endptr, 16);
>+ if (errno || (p == endptr)) {
>+ ph->p = p;
>+ return -1;
>+ }
>+ p = endptr;
>+ unary = 0;
>+ debug("val[%d]=%x,%d,%d\n", val_i - 1, val[val_i - 1],
>+ op_i, val_i);
>+do_unary:
>+ while (op_i) {
>+ j = op[op_i - 1];
>+ if (!(j & 0x80))
>+ break;
>+ op_i--;
>+ val[val_i - 1] = do_func(0,
>+ val[val_i - 1], j & 0x7f);
>+ debug("un:%d,%x,%d,%d\n", val[val_i - 1], j,
>+ op_i, val_i);
>+ }
>+ continue;
>+ }
>+ if (i < 0) {
>+ c = 0;
>+ i = 8;
>+ } else {
>+ p++;
>+ }
>+ if (c == '(') {
>+ if (op_i >= ARRAY_SIZE(op))
>+ return -1;
>+ op[op_i++] = i;
>+ debug("op[%d]=%x,%d,%d\n", op_i - 1, op[op_i - 1],
>+ op_i, val_i);
>+ unary = 1;
>+ continue;
>+ }
>+ for (;;) {
>+ if (!op_i || unary)
>+ break;
>+ j = op[op_i - 1];
>+ if (j == 0) {
>+ if (c == ')') {
>+ op_i--;
>+ goto do_unary;
>+ }
>+ break;
>+ }
>+ if ((j & 0x80)) {
>+ op_i--;
>+ val[val_i - 1] = do_func(0,
>+ val[val_i - 1], j & 0x7f);
>+ debug("unary:%d,%x\n", val[val_i - 1], j);
>+ continue;
>+ }
>+ if (precedence[i] < precedence[j])
>+ break;
>+ if (val_i < 2)
>+ return -1;
>+ op_i--;
>+ val[val_i - 2] = do_func(val[val_i - 2],
>+ val[val_i - 1], j);
>+ val_i--;
>+ debug("binary:%d,%x,%d,%d\n", val[val_i - 1], j,
>+ op_i, val_i);
>+ }
>+ if (c == ')') {
>+ fprintf(stderr, "Error: unmatched parenthesis\n");
>+ return -1;
>+ }
>+ if (i == 8) {
>+ if ((op_i != 0) || (val_i != 1)) {
>+ fprintf(stderr, "Error: syntax %d %d\n",
>+ op_i, val_i);
>+ return -1;
>+ }
>+ ph->p = p;
>+ *pval = val[0];
>+ return 0;
>+ }
>+ if (op_i >= ARRAY_SIZE(op))
>+ return -1;
>+ op[op_i++] = i | (unary << 7);
>+ debug("op[%d]=%x,%d,%d\n", op_i - 1, op[op_i - 1], op_i, val_i);
>+ unary = 1;
>+ }
> }
>
> /*
>--
>1.7.9.5
>
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V4 01/11] imximage: mx53 needs transfer length a multiple of 512
2012-11-28 9:27 ` Wolfgang Denk
@ 2012-11-28 18:18 ` Troy Kisky
2012-11-28 20:25 ` Wolfgang Denk
2012-11-28 18:26 ` Troy Kisky
1 sibling, 1 reply; 430+ messages in thread
From: Troy Kisky @ 2012-11-28 18:18 UTC (permalink / raw)
To: u-boot
On 11/28/2012 2:27 AM, Wolfgang Denk wrote:
> Dear Troy Kisky,
>
> In message <1354066303-29762-2-git-send-email-troy.kisky@boundarydevices.com> you wrote:
>> The mx53 ROM will truncate the length at a multiple of 512.
>> Transferring too much is not a problem, so round up.
> What about other SoCs using the same code?
>
>> +#define ALIGN(a, b) (((a) + (b) - 1) & ~((b) - 1))
> NAK. This macro is mis-named; it has nothing to do with alignment -
> you write yourself: "round up".
>
>
> And you don't have to re-invent the wheel. Please use the existing
> macros for this purpose.
>
> Best regards,
>
> Wolfgang Denk
>
Oddly enough, I originally called it ROUND_UP. But then I saw these lines
in include/common.h
#define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1)
#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask))
So, I deleted my definition of ROUND_UP and used ALIGN. But imximage.c
did not automatically include common.h. Instead of trying to include
common.h and all the files it pulled in, I added the ALIGN definition.
Troy
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V4 01/11] imximage: mx53 needs transfer length a multiple of 512
2012-11-28 9:27 ` Wolfgang Denk
2012-11-28 18:18 ` Troy Kisky
@ 2012-11-28 18:26 ` Troy Kisky
1 sibling, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-11-28 18:26 UTC (permalink / raw)
To: u-boot
On 11/28/2012 2:27 AM, Wolfgang Denk wrote:
> Dear Troy Kisky,
>
> In message <1354066303-29762-2-git-send-email-troy.kisky@boundarydevices.com> you wrote:
>> The mx53 ROM will truncate the length at a multiple of 512.
>> Transferring too much is not a problem, so round up.
> What about other SoCs using the same code?
>
>
It would be easy to add a version 2 header test, but that would not
distinguish between mx53 and mx6. Should I create a version 2bug
header that I can specify in mx53's config file?
Thanks
Troy
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V4 00/11] imximage series
2012-11-28 9:30 ` [U-Boot] [PATCH V4 00/11] imximage series Wolfgang Denk
@ 2012-11-28 18:29 ` Troy Kisky
0 siblings, 0 replies; 430+ messages in thread
From: Troy Kisky @ 2012-11-28 18:29 UTC (permalink / raw)
To: u-boot
On 11/28/2012 2:30 AM, Wolfgang Denk wrote:
> Dear Troy Kisky,
>
> In message <1354066303-29762-1-git-send-email-troy.kisky@boundarydevices.com> you wrote:
>> This series make the file imximage.c easier to read, as well
>> as produces a slightly smaller file.
>>
>>
>> Only the 1st two patches are different from version 3. The
>> 1st is a new patch which addresses an mx53 ROM bug. The 2nd
>> is slight changes due to rebase on 1st.
> Would it make sense to use this opportunity to integrate this tool
> into mkimage ?
>
> Best regards,
>
> Wolfgang Denk
>
I did not mean to imply that it wasn't already in mkimage, but I can see
that interpretation. It is part of mkimage.
Troy
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V4 04/11] imximage: prepare to move static variables to struct data_src
2012-11-28 9:38 ` Wolfgang Denk
@ 2012-11-28 18:36 ` Troy Kisky
2012-11-28 20:30 ` Wolfgang Denk
0 siblings, 1 reply; 430+ messages in thread
From: Troy Kisky @ 2012-11-28 18:36 UTC (permalink / raw)
To: u-boot
On 11/28/2012 2:38 AM, Wolfgang Denk wrote:
> Dear Troy Kisky,
>
> In message <1354066303-29762-5-git-send-email-troy.kisky@boundarydevices.com> you wrote:
>> Need to move accesses to the static variables to
>> a function where struct data_src is used.
> Could you please elucidate why exactly this is _needed_?
My goal was to reduce the number of static variables, but strictly speaking
it has little benefit other than giving me a warm fuzzy feeling.
I'm not that only one that dislikes static though.
>
>> + /* Be able to detect if the cfg file has no BOOT_FROM tag */
>> + g_flash_offset = FLASH_OFFSET_UNDEFINED;
>> + memset(&ds, 0, sizeof(struct data_src));
> Is this initialization really needed?
>
> Best regards,
>
> Wolfgang Denk
>
ds is on the stack, and even if not needed now, I like to avoid future
random bugs.
Troy
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V4 01/11] imximage: mx53 needs transfer length a multiple of 512
2012-11-28 18:18 ` Troy Kisky
@ 2012-11-28 20:25 ` Wolfgang Denk
2012-11-28 21:05 ` Troy Kisky
0 siblings, 1 reply; 430+ messages in thread
From: Wolfgang Denk @ 2012-11-28 20:25 UTC (permalink / raw)
To: u-boot
Dear Troy Kisky,
In message <50B65583.1070309@boundarydevices.com> you wrote:
>
> Oddly enough, I originally called it ROUND_UP. But then I saw these lines
> in include/common.h
And why didn't you find (and use) ROUND() in include/common.h ?
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
My challenge to the goto-less programmer is to recode tcp_input()
without any gotos ... without any loss of efficiency (there has to be
a catch). - W. R. Stevens
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V4 04/11] imximage: prepare to move static variables to struct data_src
2012-11-28 18:36 ` Troy Kisky
@ 2012-11-28 20:30 ` Wolfgang Denk
0 siblings, 0 replies; 430+ messages in thread
From: Wolfgang Denk @ 2012-11-28 20:30 UTC (permalink / raw)
To: u-boot
Dear Troy Kisky,
In message <50B659AD.9090704@boundarydevices.com> you wrote:
>
> > Could you please elucidate why exactly this is _needed_?
>
> My goal was to reduce the number of static variables, but strictly speaking
> it has little benefit other than giving me a warm fuzzy feeling.
>
> I'm not that only one that dislikes static though.
...
> ds is on the stack, and even if not needed now, I like to avoid future
> random bugs.
Did you check the impact of your changes on the memory footprint?
Changing code that uses a static variable initialized (implicitly or
explicitly) to zero [which results in allocation of the BSS segment,
i. e. zero space in the code or in the image file] into real code
is something that is a bit of expensive just for satisfying random
"dislikes".
I think you should better leave that as is. The code is pretty
efficent that way, and you increase it for little or no benefit.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
The nice thing about standards is that there are so many to choose
from. - Andrew S. Tanenbaum
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V4 08/11] imximage: enable word writes for version2 header
2012-11-28 9:39 ` Wolfgang Denk
@ 2012-11-28 20:40 ` Troy Kisky
2012-12-04 8:23 ` Stefano Babic
0 siblings, 1 reply; 430+ messages in thread
From: Troy Kisky @ 2012-11-28 20:40 UTC (permalink / raw)
To: u-boot
On 11/28/2012 2:39 AM, Wolfgang Denk wrote:
> Dear Troy Kisky,
>
> In message <1354066303-29762-9-git-send-email-troy.kisky@boundarydevices.com> you wrote:
>> Before, only 1 write_dcd_command table was built.
>> Now, a new table is built when the size changes.
> I cannot see how the Subject: and the actual commit message (and code)
> are related.
>
> Best regards,
>
> Wolfgang Denk
>
How about this for the commit message
Before, only 1 write_dcd_command table was built.
Now, a new table is built when the size changes.
i.e. before this patch, the sequence
DATA 4 0x83FD9014 0x00000000
DATA 2 0x83FC8000 0x00fe
was only valid for Version 1 headers, now it is valid
for Version 2 headers as well.
Parameters were changed for set_dcd_val_t to accomplish
this. So, set_dcd_val_v1 for version 1 was also slightly modified.
But no new functionality was added for version 1.
No current config files use this functionality, but this patch
removes more lines than it adds.
_________________________________________________________
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V4 01/11] imximage: mx53 needs transfer length a multiple of 512
2012-11-28 20:25 ` Wolfgang Denk
@ 2012-11-28 21:05 ` Troy Kisky
2012-11-28 21:35 ` Wolfgang Denk
0 siblings, 1 reply; 430+ messages in thread
From: Troy Kisky @ 2012-11-28 21:05 UTC (permalink / raw)
To: u-boot
On 11/28/2012 1:25 PM, Wolfgang Denk wrote:
> Dear Troy Kisky,
>
> In message <50B65583.1070309@boundarydevices.com> you wrote:
>> Oddly enough, I originally called it ROUND_UP. But then I saw these lines
>> in include/common.h
> And why didn't you find (and use) ROUND() in include/common.h ?
>
> Best regards,
>
> Wolfgang Denk
>
I did also find ROUND, so I checked to see what Linux did. Linux does not
have ROUND, but it does have ALIGN.
But I personally prefer ROUND, or even better ROUND_UP. I just wanted
to use the most common form. u-boot seems to use ROUND in config files
and ALIGN in .c files
But the reason I didn't include common.h is because of the target specific
files that it also includes. Would you mind if I moved
_________________________
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
#define ROUND(a,b) (((a) + (b) - 1) & ~((b) - 1))
#define DIV_ROUND(n,d) (((n) + ((d)/2)) / (d))
#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
#define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
#define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1)
#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask))
-------------------------------------
from common.h to a new file common_macro.h
and included common_macro.h instead?
Perhaps you have a better alternative?
Thanks
Troy
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V4 01/11] imximage: mx53 needs transfer length a multiple of 512
2012-11-28 21:05 ` Troy Kisky
@ 2012-11-28 21:35 ` Wolfgang Denk
2012-11-29 2:42 ` Troy Kisky
2012-12-03 9:12 ` Stefano Babic
0 siblings, 2 replies; 430+ messages in thread
From: Wolfgang Denk @ 2012-11-28 21:35 UTC (permalink / raw)
To: u-boot
Dear Troy Kisky,
In message <50B67C99.8080609@boundarydevices.com> you wrote:
>
> But the reason I didn't include common.h is because of the target specific
> files that it also includes. Would you mind if I moved
Why would these hurt? They don't anywhere else.
> and included common_macro.h instead?
I see no benefit for that.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
History is only a confused heap of facts.
-- Philip Earl of Chesterfield
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V4 01/11] imximage: mx53 needs transfer length a multiple of 512
2012-11-28 21:35 ` Wolfgang Denk
@ 2012-11-29 2:42 ` Troy Kisky
2012-11-29 5:28 ` Wolfgang Denk
2012-12-03 9:12 ` Stefano Babic
1 sibling, 1 reply; 430+ messages in thread
From: Troy Kisky @ 2012-11-29 2:42 UTC (permalink / raw)
To: u-boot
On 11/28/2012 2:35 PM, Wolfgang Denk wrote:
> Dear Troy Kisky,
>
> In message <50B67C99.8080609@boundarydevices.com> you wrote:
>> But the reason I didn't include common.h is because of the target specific
>> files that it also includes. Would you mind if I moved
> Why would these hurt? They don't anywhere else.
>
I'm not saying that including common.h wouldn't work.
I'm saying that it seems wrong to include target specific include
files in an executable that should generate the same code regardless
of the target selected.
I really don't care enough to argue. I just want you to understand why
I did it the way I did. It wasn't because I was crazy, or lazy. We just
hold different priorities.
Would you like to see the Linux way of ALIGN, or ROUND?
Now, back to the other topic you raised. Should I apply the bug work-around
for all version 2 headers, or find a way to distinguish mx53/mx6?
Thanks
Troy
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V4 01/11] imximage: mx53 needs transfer length a multiple of 512
2012-11-29 2:42 ` Troy Kisky
@ 2012-11-29 5:28 ` Wolfgang Denk
2012-12-03 9:23 ` Stefano Babic
0 siblings, 1 reply; 430+ messages in thread
From: Wolfgang Denk @ 2012-11-29 5:28 UTC (permalink / raw)
To: u-boot
Dear Troy Kisky,
In message <50B6CB79.4030007@boundarydevices.com> you wrote:
>
> Would you like to see the Linux way of ALIGN, or ROUND?
Do you align some buffer or similar, or do you round (up) a size?
> Now, back to the other topic you raised. Should I apply the bug work-around
> for all version 2 headers, or find a way to distinguish mx53/mx6?
I cannot tell. Stefano, what do you think?
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"Don't think; let the machine do it for you!" - E. C. Berkeley
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V4 01/11] imximage: mx53 needs transfer length a multiple of 512
2012-11-28 21:35 ` Wolfgang Denk
2012-11-29 2:42 ` Troy Kisky
@ 2012-12-03 9:12 ` Stefano Babic
1 sibling, 0 replies; 430+ messages in thread
From: Stefano Babic @ 2012-12-03 9:12 UTC (permalink / raw)
To: u-boot
On 28/11/2012 22:35, Wolfgang Denk wrote:
> Dear Troy Kisky,
>
> In message <50B67C99.8080609@boundarydevices.com> you wrote:
>>
>> But the reason I didn't include common.h is because of the target specific
>> files that it also includes. Would you mind if I moved
>
> Why would these hurt? They don't anywhere else.
Personally, I think that mkimage as generic tool should not include
common.h. Doing that, it does not allow to compile mkimage without
running config, and let's think that we need a different mkimage for
each target, and that is not true. This will break also support from
distros, because their packages (for example, u-boot-tools,
uboot-mkimage under Ubuntu) are compiled without configuring u-boot -
and I think it is correct.
IMHO we are discussing about a single macro. We can let it in mkimage as
in patch and move it in a general file only if we will have a use case
with a bunch of macros.
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V4 01/11] imximage: mx53 needs transfer length a multiple of 512
2012-11-29 5:28 ` Wolfgang Denk
@ 2012-12-03 9:23 ` Stefano Babic
0 siblings, 0 replies; 430+ messages in thread
From: Stefano Babic @ 2012-12-03 9:23 UTC (permalink / raw)
To: u-boot
On 29/11/2012 06:28, Wolfgang Denk wrote:
> Dear Troy Kisky,
>
> In message <50B6CB79.4030007@boundarydevices.com> you wrote:
>>
>> Would you like to see the Linux way of ALIGN, or ROUND?
>
> Do you align some buffer or similar, or do you round (up) a size?
>
>> Now, back to the other topic you raised. Should I apply the bug work-around
>> for all version 2 headers, or find a way to distinguish mx53/mx6?
>
> I cannot tell. Stefano, what do you think?
Well, I am thinking about which are the real benefits. If we always
round up the size to 512 bytes for V2 header, *maybe* we constrain the
i.MX6 to load some bytes more, but it is the only drawback. And this if
the i.MX6 does not suffer of the same problem found on i.MX53.
On the other side, having two different versions of V2 header is
confusing. It is then undocumented by Freescale, and maybe it is
possible to find a note in some errata. Having the same interface
without special hacking for each SOC overcomes the increment in the
footprint for the i.MX6 (in worst case 511 bytes - and not a lot
compared to current size of U-Boot for MX5/MX6, usually several hundred
of KB).
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] [PATCH V4 08/11] imximage: enable word writes for version2 header
2012-11-28 20:40 ` Troy Kisky
@ 2012-12-04 8:23 ` Stefano Babic
0 siblings, 0 replies; 430+ messages in thread
From: Stefano Babic @ 2012-12-04 8:23 UTC (permalink / raw)
To: u-boot
On 28/11/2012 21:40, Troy Kisky wrote:
> On 11/28/2012 2:39 AM, Wolfgang Denk wrote:
>> Dear Troy Kisky,
>>
>> In message
>> <1354066303-29762-9-git-send-email-troy.kisky@boundarydevices.com> you
>> wrote:
>>> Before, only 1 write_dcd_command table was built.
>>> Now, a new table is built when the size changes.
>> I cannot see how the Subject: and the actual commit message (and code)
>> are related.
>>
>> Best regards,
>>
>> Wolfgang Denk
>>
> How about this for the commit message
>
> Before, only 1 write_dcd_command table was built.
> Now, a new table is built when the size changes.
>
> i.e. before this patch, the sequence
> DATA 4 0x83FD9014 0x00000000
> DATA 2 0x83FC8000 0x00fe
>
> was only valid for Version 1 headers, now it is valid
> for Version 2 headers as well.
Much better ! Maybe you can also change the title of the patch, telling
that you are fixing a bug (the fact that first parameter was not
correctly interpreted for V2 *is* a bug). And the example explains very
well the issue.
>
> Parameters were changed for set_dcd_val_t to accomplish
> this. So, set_dcd_val_v1 for version 1 was also slightly modified.
> But no new functionality was added for version 1.
>
> No current config files use this functionality, but this patch
> removes more lines than it adds.
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2019-08-29 15:12 ` Thomas Schaefer
@ 2019-08-29 15:21 ` Fabio Estevam
0 siblings, 0 replies; 430+ messages in thread
From: Fabio Estevam @ 2019-08-29 15:21 UTC (permalink / raw)
To: u-boot
Hi Thomas,
On Thu, Aug 29, 2019 at 12:12 PM Thomas Schaefer
<Thomas.Schaefer@kontron.com> wrote:
> does this mean that these dts files are directly imported from linux tree without
> modification?
Yes, this is our goal.
> I have cloned https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git . Is
> this the right repository to use for the patch?
Yes, you can generate your patch against this tree.
> I found you and Shawn Guo in the imx maintainers list (among others). Should I send the
> patch directly to you, and also to linux-arm-kernel at lists.infradead.org list?
Please send it via git send-email to all i.MX kernel folks and the
linux-arm-kernel list.
Thanks
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2019-08-29 13:53 ` Fabio Estevam
@ 2019-08-29 15:12 ` Thomas Schaefer
2019-08-29 15:21 ` Fabio Estevam
0 siblings, 1 reply; 430+ messages in thread
From: Thomas Schaefer @ 2019-08-29 15:12 UTC (permalink / raw)
To: u-boot
Hi Fabio,
> Hi Thomas,
>
> On Thu, Aug 29, 2019 at 10:40 AM Thomas Schaefer <thomas.schaefer@kontron.com> wrote:
>
> > arch/arm/dts/imx7d.dtsi | 2 +-
> > arch/arm/dts/imx7s.dtsi | 4 ++--
> > 2 files changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/arm/dts/imx7d.dtsi b/arch/arm/dts/imx7d.dtsi index
> > 30b058934b..2c33aa876f 100644
> > --- a/arch/arm/dts/imx7d.dtsi
> > +++ b/arch/arm/dts/imx7d.dtsi
> > @@ -101,7 +101,7 @@
> > &aips3 {
> > usbotg2: usb at 30b20000 {
> > compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
> > - reg = <0x30b20000 0x200>;
> > + reg = <0x30b20000 0x10000>;
>
> Yes, I have just checked the reference manual and 0x10000 size is correct.
>
> Could you please send a patch to fix it in the kernel dts?
>
> Then, after it gets fixed in the kernel we can simply import it to U-Boot.
>
> Thanks
does this mean that these dts files are directly imported from linux tree without
modification?
I have cloned https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git . Is
this the right repository to use for the patch?
I found you and Shawn Guo in the imx maintainers list (among others). Should I send the
patch directly to you, and also to linux-arm-kernel at lists.infradead.org list?
Best regards,
Thomas
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2019-08-29 13:40 [U-Boot] (no subject) Thomas Schaefer
@ 2019-08-29 13:53 ` Fabio Estevam
2019-08-29 15:12 ` Thomas Schaefer
0 siblings, 1 reply; 430+ messages in thread
From: Fabio Estevam @ 2019-08-29 13:53 UTC (permalink / raw)
To: u-boot
Hi Thomas,
On Thu, Aug 29, 2019 at 10:40 AM Thomas Schaefer
<thomas.schaefer@kontron.com> wrote:
> arch/arm/dts/imx7d.dtsi | 2 +-
> arch/arm/dts/imx7s.dtsi | 4 ++--
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/dts/imx7d.dtsi b/arch/arm/dts/imx7d.dtsi
> index 30b058934b..2c33aa876f 100644
> --- a/arch/arm/dts/imx7d.dtsi
> +++ b/arch/arm/dts/imx7d.dtsi
> @@ -101,7 +101,7 @@
> &aips3 {
> usbotg2: usb at 30b20000 {
> compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
> - reg = <0x30b20000 0x200>;
> + reg = <0x30b20000 0x10000>;
Yes, I have just checked the reference manual and 0x10000 size is correct.
Could you please send a patch to fix it in the kernel dts?
Then, after it gets fixed in the kernel we can simply import it to U-Boot.
Thanks
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2019-08-29 13:40 Thomas Schaefer
2019-08-29 13:53 ` Fabio Estevam
0 siblings, 1 reply; 430+ messages in thread
From: Thomas Schaefer @ 2019-08-29 13:40 UTC (permalink / raw)
To: u-boot
Hi all,
I want to introduce a small patch that fixes v 2019.07 bootloader crash during
USB scan on our i.MX7 based custom board (see explanation in the patch comment).
Could you please review and add to next u-boot release?
Best regards,
Thomas
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2019-07-01 13:20 ` Tom Rini
@ 2019-07-04 2:11 ` Thomas Chou
0 siblings, 0 replies; 430+ messages in thread
From: Thomas Chou @ 2019-07-04 2:11 UTC (permalink / raw)
To: u-boot
On 7/1/19 9:20 PM, Tom Rini wrote:
> On Sun, Jun 30, 2019 at 10:06:35AM +0800, Thomas Chou wrote:
>
>>
>> Add gcc-8.1.0 support to buildman toolchain.
>>
>> The old gcc-7.3.0 has shared libraries issues on Ubuntu 18.04LTS and
>> 19.04.
>
> Can you not resolve those shared library issues via one of the toolchain
> PPAs ?
>
I switched to Fedora 30, which does not have such shared libraries
issues. Fedora has more cross compiler supported, with gcc-9. I am
trying them, and will feedback later.
Cheers,
Thomas
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2019-07-01 13:19 ` Tom Rini
@ 2019-07-04 2:00 ` Thomas Chou
0 siblings, 0 replies; 430+ messages in thread
From: Thomas Chou @ 2019-07-04 2:00 UTC (permalink / raw)
To: u-boot
Hi Tom,
On 7/1/19 9:19 PM, Tom Rini wrote:
> On Sun, Jun 30, 2019 at 06:31:10PM +0800, Bin Meng wrote:
> Unfortunately the kernel.org gcc-8.1 toolchain just isn't usable for us
> due to a number of later-fixed regressions. We need to use gcc-8.3, I
> think, for something that should work again everywhere. And when I last
> looked (mid-May, from my WIP branch) while I could get gcc-8.3 for ARM I
> couldn't find one for x86. The Bootlin toolchains are only 8.2 and
> that's not new enough to have the problem Bin notes as a regression
> fixed.
>
Agree. We shall wait until they are ready.
Cheers,
Thomas
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2019-06-30 10:31 ` Bin Meng
2019-07-01 13:19 ` Tom Rini
@ 2019-07-04 1:58 ` Thomas Chou
1 sibling, 0 replies; 430+ messages in thread
From: Thomas Chou @ 2019-07-04 1:58 UTC (permalink / raw)
To: u-boot
Hi Bin,
On 6/30/19 6:31 PM, Bin Meng wrote:
> On Sun, Jun 30, 2019 at 10:07 AM Thomas Chou <thomas@wytron.com.tw> wrote:
>> x86: + efi-x86_app
>> +{standard input}: Assembler messages:
>> +{standard input}:21695: Error: junk at end of line, first unrecognized character is `@'
>> +{standard input}:21740: Error: junk at end of line, first unrecognized character is `@'
>> +{standard input}:21695: Error: can't resolve `end.7382' {.u_boot_list_2_fit_loadable_3 section} - `start.7379' {.u_boot_list_2_fit_loadable_1 section}
>> +{standard input}:21740: Error: can't resolve `end.7382' {.u_boot_list_2_fit_loadable_3 section} - `start.7379' {.u_boot_list_2_fit_loadable_1 section}
>> +make[2]: *** [scripts/Makefile.build:279: common/image.o] Error 1
>> +make[1]: *** [Makefile:1594: common] Error 2
>> +make: *** [Makefile:148: sub-make] Error 2
>
> For the x86 failure, it is a known regression issue of GCC 8.
>
> Regards,
> Bin
>
Good to know. Thanks.
Thomas
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2019-06-30 2:06 Thomas Chou
2019-06-30 10:31 ` Bin Meng
@ 2019-07-01 13:20 ` Tom Rini
2019-07-04 2:11 ` Thomas Chou
1 sibling, 1 reply; 430+ messages in thread
From: Tom Rini @ 2019-07-01 13:20 UTC (permalink / raw)
To: u-boot
On Sun, Jun 30, 2019 at 10:06:35AM +0800, Thomas Chou wrote:
>
> Add gcc-8.1.0 support to buildman toolchain.
>
> The old gcc-7.3.0 has shared libraries issues on Ubuntu 18.04LTS and
> 19.04.
Can you not resolve those shared library issues via one of the toolchain
PPAs ?
--
Tom
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^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2019-06-30 10:31 ` Bin Meng
@ 2019-07-01 13:19 ` Tom Rini
2019-07-04 2:00 ` Thomas Chou
2019-07-04 1:58 ` Thomas Chou
1 sibling, 1 reply; 430+ messages in thread
From: Tom Rini @ 2019-07-01 13:19 UTC (permalink / raw)
To: u-boot
On Sun, Jun 30, 2019 at 06:31:10PM +0800, Bin Meng wrote:
> On Sun, Jun 30, 2019 at 10:07 AM Thomas Chou <thomas@wytron.com.tw> wrote:
> >
> >
> > Add gcc-8.1.0 support to buildman toolchain.
> >
> > The old gcc-7.3.0 has shared libraries issues on Ubuntu 18.04LTS and
> > 19.04.
> >
> > Though both 7.3.0 and 8.1.0 have arc and nds32 compilers, the following
> > errors were generated on Ubuntu 19.04.
> >
> > arc: + iot_devkit
> > +arc-linux-ld.bfd: error: examples/standalone/hello_world: unable to merge CPU base attributes ARC7xx with ARCEM.
> > +
> > +arc-linux-ld.bfd: failed to merge target specific data of file /home/thomas/.buildman-toolchains/gcc-8.1.0-nolibc/arc-linux/bin/../lib/gcc/arc-linux/8.1.0/libgcc.a(_millicodethunk_st.o)
> > +arc-linux-ld.bfd: failed to merge target specific data of file /home/thomas/.buildman-toolchains/gcc-8.1.0-nolibc/arc-linux/bin/../lib/gcc/arc-linux/8.1.0/libgcc.a(_millicodethunk_ret.o)
> > +make[3]: *** [examples/standalone/Makefile:62: examples/standalone/hello_world] Error 1
> > +make[2]: *** [scripts/Makefile.build:432: examples/standalone] Error 2
> > +make[1]: *** [Makefile:1594: examples] Error 2
> > +make: *** [Makefile:148: sub-make] Error 2
> >
> >
> > nds32: + adp-ae3xx
> > +nds32le-elf-gcc: error: unrecognized command line option '-mno-ext-fpu-dp'
> > +nds32le-elf-gcc: error: unrecognized command line option '-mfloat-abi=soft'
> > +make[2]: *** [scripts/Makefile.autoconf:77: u-boot.cfg] Error 1
> > +make[1]: *** No rule to make target 'include/config/auto.conf', needed by 'include/config/uboot.release'. Stop.
> > +make: *** [Makefile:148: sub-make] Error 2
> >
> > nds32: + adp-ag101p
> > +nds32le-elf-gcc: error: unrecognized command line option '-mno-ext-fpu-dp'
> > +nds32le-elf-gcc: error: unrecognized command line option '-mfloat-abi=soft'
> > +make[2]: *** [scripts/Makefile.autoconf:77: u-boot.cfg] Error 1
> > +make[1]: *** No rule to make target 'include/config/auto.conf', needed by 'include/config/uboot.release'. Stop.
> > +make: *** [Makefile:148: sub-make] Error 2
> >
> > x86: + efi-x86_app
> > +{standard input}: Assembler messages:
> > +{standard input}:21695: Error: junk at end of line, first unrecognized character is `@'
> > +{standard input}:21740: Error: junk at end of line, first unrecognized character is `@'
> > +{standard input}:21695: Error: can't resolve `end.7382' {.u_boot_list_2_fit_loadable_3 section} - `start.7379' {.u_boot_list_2_fit_loadable_1 section}
> > +{standard input}:21740: Error: can't resolve `end.7382' {.u_boot_list_2_fit_loadable_3 section} - `start.7379' {.u_boot_list_2_fit_loadable_1 section}
> > +make[2]: *** [scripts/Makefile.build:279: common/image.o] Error 1
> > +make[1]: *** [Makefile:1594: common] Error 2
> > +make: *** [Makefile:148: sub-make] Error 2
>
> For the x86 failure, it is a known regression issue of GCC 8.
Unfortunately the kernel.org gcc-8.1 toolchain just isn't usable for us
due to a number of later-fixed regressions. We need to use gcc-8.3, I
think, for something that should work again everywhere. And when I last
looked (mid-May, from my WIP branch) while I could get gcc-8.3 for ARM I
couldn't find one for x86. The Bootlin toolchains are only 8.2 and
that's not new enough to have the problem Bin notes as a regression
fixed.
--
Tom
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^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2019-06-30 2:06 Thomas Chou
@ 2019-06-30 10:31 ` Bin Meng
2019-07-01 13:19 ` Tom Rini
2019-07-04 1:58 ` Thomas Chou
2019-07-01 13:20 ` Tom Rini
1 sibling, 2 replies; 430+ messages in thread
From: Bin Meng @ 2019-06-30 10:31 UTC (permalink / raw)
To: u-boot
On Sun, Jun 30, 2019 at 10:07 AM Thomas Chou <thomas@wytron.com.tw> wrote:
>
>
> Add gcc-8.1.0 support to buildman toolchain.
>
> The old gcc-7.3.0 has shared libraries issues on Ubuntu 18.04LTS and
> 19.04.
>
> Though both 7.3.0 and 8.1.0 have arc and nds32 compilers, the following
> errors were generated on Ubuntu 19.04.
>
> arc: + iot_devkit
> +arc-linux-ld.bfd: error: examples/standalone/hello_world: unable to merge CPU base attributes ARC7xx with ARCEM.
> +
> +arc-linux-ld.bfd: failed to merge target specific data of file /home/thomas/.buildman-toolchains/gcc-8.1.0-nolibc/arc-linux/bin/../lib/gcc/arc-linux/8.1.0/libgcc.a(_millicodethunk_st.o)
> +arc-linux-ld.bfd: failed to merge target specific data of file /home/thomas/.buildman-toolchains/gcc-8.1.0-nolibc/arc-linux/bin/../lib/gcc/arc-linux/8.1.0/libgcc.a(_millicodethunk_ret.o)
> +make[3]: *** [examples/standalone/Makefile:62: examples/standalone/hello_world] Error 1
> +make[2]: *** [scripts/Makefile.build:432: examples/standalone] Error 2
> +make[1]: *** [Makefile:1594: examples] Error 2
> +make: *** [Makefile:148: sub-make] Error 2
>
>
> nds32: + adp-ae3xx
> +nds32le-elf-gcc: error: unrecognized command line option '-mno-ext-fpu-dp'
> +nds32le-elf-gcc: error: unrecognized command line option '-mfloat-abi=soft'
> +make[2]: *** [scripts/Makefile.autoconf:77: u-boot.cfg] Error 1
> +make[1]: *** No rule to make target 'include/config/auto.conf', needed by 'include/config/uboot.release'. Stop.
> +make: *** [Makefile:148: sub-make] Error 2
>
> nds32: + adp-ag101p
> +nds32le-elf-gcc: error: unrecognized command line option '-mno-ext-fpu-dp'
> +nds32le-elf-gcc: error: unrecognized command line option '-mfloat-abi=soft'
> +make[2]: *** [scripts/Makefile.autoconf:77: u-boot.cfg] Error 1
> +make[1]: *** No rule to make target 'include/config/auto.conf', needed by 'include/config/uboot.release'. Stop.
> +make: *** [Makefile:148: sub-make] Error 2
>
> x86: + efi-x86_app
> +{standard input}: Assembler messages:
> +{standard input}:21695: Error: junk at end of line, first unrecognized character is `@'
> +{standard input}:21740: Error: junk at end of line, first unrecognized character is `@'
> +{standard input}:21695: Error: can't resolve `end.7382' {.u_boot_list_2_fit_loadable_3 section} - `start.7379' {.u_boot_list_2_fit_loadable_1 section}
> +{standard input}:21740: Error: can't resolve `end.7382' {.u_boot_list_2_fit_loadable_3 section} - `start.7379' {.u_boot_list_2_fit_loadable_1 section}
> +make[2]: *** [scripts/Makefile.build:279: common/image.o] Error 1
> +make[1]: *** [Makefile:1594: common] Error 2
> +make: *** [Makefile:148: sub-make] Error 2
For the x86 failure, it is a known regression issue of GCC 8.
Regards,
Bin
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2019-06-30 2:06 Thomas Chou
2019-06-30 10:31 ` Bin Meng
2019-07-01 13:20 ` Tom Rini
0 siblings, 2 replies; 430+ messages in thread
From: Thomas Chou @ 2019-06-30 2:06 UTC (permalink / raw)
To: u-boot
Add gcc-8.1.0 support to buildman toolchain.
The old gcc-7.3.0 has shared libraries issues on Ubuntu 18.04LTS and
19.04.
Though both 7.3.0 and 8.1.0 have arc and nds32 compilers, the following
errors were generated on Ubuntu 19.04.
arc: + iot_devkit
+arc-linux-ld.bfd: error: examples/standalone/hello_world: unable to merge CPU base attributes ARC7xx with ARCEM.
+
+arc-linux-ld.bfd: failed to merge target specific data of file /home/thomas/.buildman-toolchains/gcc-8.1.0-nolibc/arc-linux/bin/../lib/gcc/arc-linux/8.1.0/libgcc.a(_millicodethunk_st.o)
+arc-linux-ld.bfd: failed to merge target specific data of file /home/thomas/.buildman-toolchains/gcc-8.1.0-nolibc/arc-linux/bin/../lib/gcc/arc-linux/8.1.0/libgcc.a(_millicodethunk_ret.o)
+make[3]: *** [examples/standalone/Makefile:62: examples/standalone/hello_world] Error 1
+make[2]: *** [scripts/Makefile.build:432: examples/standalone] Error 2
+make[1]: *** [Makefile:1594: examples] Error 2
+make: *** [Makefile:148: sub-make] Error 2
nds32: + adp-ae3xx
+nds32le-elf-gcc: error: unrecognized command line option '-mno-ext-fpu-dp'
+nds32le-elf-gcc: error: unrecognized command line option '-mfloat-abi=soft'
+make[2]: *** [scripts/Makefile.autoconf:77: u-boot.cfg] Error 1
+make[1]: *** No rule to make target 'include/config/auto.conf', needed by 'include/config/uboot.release'. Stop.
+make: *** [Makefile:148: sub-make] Error 2
nds32: + adp-ag101p
+nds32le-elf-gcc: error: unrecognized command line option '-mno-ext-fpu-dp'
+nds32le-elf-gcc: error: unrecognized command line option '-mfloat-abi=soft'
+make[2]: *** [scripts/Makefile.autoconf:77: u-boot.cfg] Error 1
+make[1]: *** No rule to make target 'include/config/auto.conf', needed by 'include/config/uboot.release'. Stop.
+make: *** [Makefile:148: sub-make] Error 2
x86: + efi-x86_app
+{standard input}: Assembler messages:
+{standard input}:21695: Error: junk at end of line, first unrecognized character is `@'
+{standard input}:21740: Error: junk at end of line, first unrecognized character is `@'
+{standard input}:21695: Error: can't resolve `end.7382' {.u_boot_list_2_fit_loadable_3 section} - `start.7379' {.u_boot_list_2_fit_loadable_1 section}
+{standard input}:21740: Error: can't resolve `end.7382' {.u_boot_list_2_fit_loadable_3 section} - `start.7379' {.u_boot_list_2_fit_loadable_1 section}
+make[2]: *** [scripts/Makefile.build:279: common/image.o] Error 1
+make[1]: *** [Makefile:1594: common] Error 2
+make: *** [Makefile:148: sub-make] Error 2
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2019-04-28 21:45 Adam Ford
0 siblings, 0 replies; 430+ messages in thread
From: Adam Ford @ 2019-04-28 21:45 UTC (permalink / raw)
To: u-boot
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2019-04-26 8:02 ` Parthiban Nallathambi
@ 2019-04-26 8:27 ` Stefano Babic
0 siblings, 0 replies; 430+ messages in thread
From: Stefano Babic @ 2019-04-26 8:27 UTC (permalink / raw)
To: u-boot
Hi Parthiban,
I missed this one, thanks for remind. I will just push to u-boot-imx and
then merge yours.
Regards,
Stefano
On 26/04/19 10:02, Parthiban Nallathambi wrote:
> Ping on this patch.
>
> Thanks,
> Parthiban N
>
> On 4/10/19 4:35 PM, Parthiban Nallathambi wrote:
>> Extend PHYTEC phyBOARD-i.MX6UL for phyCORE-i.MX6UL SoM (PCL063)
>> with eMMC on SoM.
>>
>> CPU: Freescale i.MX6ULL rev1.0 792 MHz (running at 396 MHz)
>> CPU: Industrial temperature grade (-40C to 105C) at 38C
>> Reset cause: POR
>> Model: Phytec phyBOARD-i.MX6ULL-Segin SBC
>> Board: PHYTEC phyCORE-i.MX6ULL
>> DRAM: 256 MiB
>> MMC: FSL_SDHC: 0, FSL_SDHC: 1
>> In: serial at 02020000
>> Out: serial at 02020000
>> Err: serial at 02020000
>> Net: FEC0
>>
>> Working:
>> - Eth0
>> - i2C
>> - MMC/SD
>> - eMMC
>> - UART (1 & 5)
>> - USB (host & otg)
>>
>> Signed-off-by: Parthiban Nallathambi <parthitce@gmail.com>
>> ---
>>
>> Notes:
>> Changes in v2:
>> - disabled gpmi and usdhc by default in pcl063-common.dtsi. Board
>> dts enables it based on the flash storage which is present.
>> - added CONFIG_SYS_FSL_USDHC_NUM in pcl063.h
>>
>> arch/arm/dts/Makefile | 1 +
>> arch/arm/dts/imx6ul-phycore-segin.dts | 7 +-
>> arch/arm/dts/imx6ull-phycore-segin.dts | 70 +++++++++++
>> ...{imx6ul-pcl063.dtsi => pcl063-common.dtsi} | 33 ++++-
>> arch/arm/mach-imx/mx6/Kconfig | 12 ++
>> board/phytec/pcl063/Kconfig | 13 ++
>> board/phytec/pcl063/MAINTAINERS | 6 +-
>> board/phytec/pcl063/pcl063.c | 5 +-
>> board/phytec/pcl063/spl.c | 76 +++++++++++-
>> configs/phycore_pcl063_ull_defconfig | 54 ++++++++
>> include/configs/pcl063.h | 2 +
>> include/configs/pcl063_ull.h | 117 ++++++++++++++++++
>> 12 files changed, 384 insertions(+), 12 deletions(-)
>> create mode 100644 arch/arm/dts/imx6ull-phycore-segin.dts
>> rename arch/arm/dts/{imx6ul-pcl063.dtsi => pcl063-common.dtsi} (83%)
>> create mode 100644 configs/phycore_pcl063_ull_defconfig
>> create mode 100644 include/configs/pcl063_ull.h
>>
>> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
>> index 930b7e03db..8459acb344 100644
>> --- a/arch/arm/dts/Makefile
>> +++ b/arch/arm/dts/Makefile
>> @@ -539,6 +539,7 @@ dtb-$(CONFIG_MX6UL) += \
>> dtb-$(CONFIG_MX6ULL) += \
>> imx6ull-14x14-evk.dtb \
>> imx6ull-colibri.dtb \
>> + imx6ull-phycore-segin.dtb
>> dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
>> imx7d-sdb-qspi.dtb \
>> diff --git a/arch/arm/dts/imx6ul-phycore-segin.dts
>> b/arch/arm/dts/imx6ul-phycore-segin.dts
>> index a46012e2b4..7d68bf8430 100644
>> --- a/arch/arm/dts/imx6ul-phycore-segin.dts
>> +++ b/arch/arm/dts/imx6ul-phycore-segin.dts
>> @@ -16,7 +16,8 @@
>> /dts-v1/;
>> -#include "imx6ul-pcl063.dtsi"
>> +#include "imx6ul.dtsi"
>> +#include "pcl063-common.dtsi"
>> / {
>> model = "Phytec phyBOARD-i.MX6UL-Segin SBC";
>> @@ -24,6 +25,10 @@
>> "fsl,imx6ul";
>> };
>> +&gpmi {
>> + status = "okay";
>> +};
>> +
>> &i2c1 {
>> i2c_rtc: rtc at 68 {
>> compatible = "microcrystal,rv4162";
>> diff --git a/arch/arm/dts/imx6ull-phycore-segin.dts
>> b/arch/arm/dts/imx6ull-phycore-segin.dts
>> new file mode 100644
>> index 0000000000..6df3ad2e4a
>> --- /dev/null
>> +++ b/arch/arm/dts/imx6ull-phycore-segin.dts
>> @@ -0,0 +1,70 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com>
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "imx6ull.dtsi"
>> +#include "pcl063-common.dtsi"
>> +
>> +/ {
>> + model = "Phytec phyBOARD-i.MX6ULL-Segin SBC";
>> + compatible = "phytec,phyboard-imx6ull-segin",
>> "phytec,imx6ull-pcl063",
>> + "fsl,imx6ull";
>> +};
>> +
>> +&i2c1 {
>> + i2c_rtc: rtc at 68 {
>> + compatible = "microcrystal,rv4162";
>> + reg = <0x68>;
>> + status = "okay";
>> + };
>> +};
>> +
>> +&uart5 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_uart5>;
>> + uart-has-rtscts;
>> + status = "okay";
>> +};
>> +
>> +&usdhc2 {
>> + status = "okay";
>> +};
>> +
>> +&usbotg1 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_usb_otg1_id>;
>> + dr_mode = "otg";
>> + srp-disable;
>> + hnp-disable;
>> + adp-disable;
>> + status = "okay";
>> +};
>> +
>> +&usbotg2 {
>> + dr_mode = "host";
>> + disable-over-current;
>> + status = "okay";
>> +};
>> +
>> +&iomuxc {
>> + pinctrl-names = "default";
>> +
>> + pinctrl_uart5: uart5grp {
>> + fsl,pins = <
>> + MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1
>> + MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1
>> + MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1
>> + MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1
>> + >;
>> + };
>> +
>> + pinctrl_usb_otg1_id: usbotg1idgrp {
>> + fsl,pins = <
>> + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
>> + >;
>> + };
>> +
>> +};
>> diff --git a/arch/arm/dts/imx6ul-pcl063.dtsi
>> b/arch/arm/dts/pcl063-common.dtsi
>> similarity index 83%
>> rename from arch/arm/dts/imx6ul-pcl063.dtsi
>> rename to arch/arm/dts/pcl063-common.dtsi
>> index 24a6a47983..2b14b2dc5f 100644
>> --- a/arch/arm/dts/imx6ul-pcl063.dtsi
>> +++ b/arch/arm/dts/pcl063-common.dtsi
>> @@ -7,10 +7,6 @@
>> * Author: Christian Hemp <c.hemp@phytec.de>
>> */
>> -/dts-v1/;
>> -
>> -#include "imx6ul.dtsi"
>> -
>> / {
>> model = "Phytec phyCORE-i.MX6 Ultra Lite SOM";
>> compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul";
>> @@ -47,7 +43,7 @@
>> pinctrl-0 = <&pinctrl_gpmi_nand>;
>> nand-on-flash-bbt;
>> fsl,no-blockmark-swap;
>> - status = "okay";
>> + status = "disabled";
>> #address-cells = <1>;
>> #size-cells = <1>;
>> @@ -99,6 +95,18 @@
>> status = "okay";
>> };
>> +&usdhc2 {
>> + u-boot,dm-spl;
>> + u-boot,dm-pre-reloc;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_usdhc2>;
>> + bus-width = <8>;
>> + no-1-8-v;
>> + non-removable;
>> + keep-power-in-suspend;
>> + status = "disabled";
>> +};
>> +
>> &iomuxc {
>> pinctrl-names = "default";
>> @@ -170,4 +178,19 @@
>> >;
>> };
>> +
>> + pinctrl_usdhc2: usdhc2grp {
>> + fsl,pins = <
>> + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
>> + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
>> + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
>> + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
>> + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
>> + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
>> + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
>> + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
>> + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
>> + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
>> + >;
>> + };
>> };
>> diff --git a/arch/arm/mach-imx/mx6/Kconfig
>> b/arch/arm/mach-imx/mx6/Kconfig
>> index e782859b1e..5e2f08e500 100644
>> --- a/arch/arm/mach-imx/mx6/Kconfig
>> +++ b/arch/arm/mach-imx/mx6/Kconfig
>> @@ -443,6 +443,18 @@ config TARGET_PCL063
>> select DM_THERMAL
>> select SUPPORT_SPL
>> +config TARGET_PCL063_ULL
>> + bool "PHYTEC PCL063 (phyCORE-i.MX6ULL)"
>> + select MX6ULL
>> + select DM
>> + select DM_ETH
>> + select DM_GPIO
>> + select DM_I2C
>> + select DM_MMC
>> + select DM_SERIAL
>> + select DM_THERMAL
>> + select SUPPORT_SPL
>> +
>> config TARGET_SECOMX6
>> bool "secomx6 boards"
>> diff --git a/board/phytec/pcl063/Kconfig b/board/phytec/pcl063/Kconfig
>> index 977db70f64..58f72f2791 100644
>> --- a/board/phytec/pcl063/Kconfig
>> +++ b/board/phytec/pcl063/Kconfig
>> @@ -10,3 +10,16 @@ config SYS_CONFIG_NAME
>> default "pcl063"
>> endif
>> +
>> +if TARGET_PCL063_ULL
>> +
>> +config SYS_BOARD
>> + default "pcl063"
>> +
>> +config SYS_VENDOR
>> + default "phytec"
>> +
>> +config SYS_CONFIG_NAME
>> + default "pcl063_ull"
>> +
>> +endif
>> diff --git a/board/phytec/pcl063/MAINTAINERS
>> b/board/phytec/pcl063/MAINTAINERS
>> index c65a951f3d..70e03cfe71 100644
>> --- a/board/phytec/pcl063/MAINTAINERS
>> +++ b/board/phytec/pcl063/MAINTAINERS
>> @@ -1,8 +1,12 @@
>> PCL063 BOARD
>> M: Martyn Welch <martyn.welch@collabora.com>
>> +M: Parthiban Nallathambi <parthitce@gmail.com>
>> S: Maintained
>> -F: arch/arm/dts/imx6ul-pcl063.dtsi
>> F: arch/arm/dts/imx6ul-phycore-segin.dts
>> +F: arch/arm/dts/imx6ull-phycore-segin.dts
>> +F: arch/arm/dts/pcl063-common.dtsi
>> F: board/phytec/pcl063/
>> F: configs/phycore_pcl063_defconfig
>> +F: configs/phycore_pcl063_ull_defconfig
>> F: include/configs/pcl063.h
>> +F: include/configs/pcl063_ull.h
>> diff --git a/board/phytec/pcl063/pcl063.c b/board/phytec/pcl063/pcl063.c
>> index 38b233d1b0..17012df037 100644
>> --- a/board/phytec/pcl063/pcl063.c
>> +++ b/board/phytec/pcl063/pcl063.c
>> @@ -200,7 +200,10 @@ int board_init(void)
>> int checkboard(void)
>> {
>> - puts("Board: PHYTEC phyCORE-i.MX6UL\n");
>> + u32 cpurev = get_cpu_rev();
>> +
>> + printf("Board: PHYTEC phyCORE-i.MX%s\n",
>> + get_imx_type((cpurev & 0xFF000) >> 12));
>> return 0;
>> }
>> diff --git a/board/phytec/pcl063/spl.c b/board/phytec/pcl063/spl.c
>> index b93cd493f2..73a774645d 100644
>> --- a/board/phytec/pcl063/spl.c
>> +++ b/board/phytec/pcl063/spl.c
>> @@ -13,6 +13,7 @@
>> #include <asm/arch/mx6-ddr.h>
>> #include <asm/arch/mx6-pins.h>
>> #include <asm/arch/crm_regs.h>
>> +#include <asm/arch/sys_proto.h>
>> #include <fsl_esdhc.h>
>> /* Configuration for Micron MT41K256M16TW-107 IT:P, 32M x 16 x 8
>> -> 256MiB */
>> @@ -117,11 +118,32 @@ static iomux_v3_cfg_t const usdhc1_pads[] = {
>> MX6_PAD_UART1_RTS_B__USDHC1_CD_B | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> };
>> +#ifndef CONFIG_NAND_MXS
>> +static iomux_v3_cfg_t const usdhc2_pads[] = {
>> + MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +};
>> +#endif
>> +
>> static struct fsl_esdhc_cfg usdhc_cfg[] = {
>> {
>> .esdhc_base = USDHC1_BASE_ADDR,
>> .max_bus_width = 4,
>> },
>> +#ifndef CONFIG_NAND_MXS
>> + {
>> + .esdhc_base = USDHC2_BASE_ADDR,
>> + .max_bus_width = 8,
>> + },
>> +#endif
>> };
>> int board_mmc_getcd(struct mmc *mmc)
>> @@ -131,12 +153,58 @@ int board_mmc_getcd(struct mmc *mmc)
>> int board_mmc_init(bd_t *bis)
>> {
>> - imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
>> ARRAY_SIZE(usdhc1_pads));
>> - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
>> -
>> - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
>> + int i, ret;
>> +
>> + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
>> + switch (i) {
>> + case 0:
>> + SETUP_IOMUX_PADS(usdhc1_pads);
>> + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
>> + break;
>> +#ifndef CONFIG_NAND_MXS
>> + case 1:
>> + SETUP_IOMUX_PADS(usdhc2_pads);
>> + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
>> + break;
>> +#endif
>> + default:
>> + printf("Warning - USDHC%d controller not supporting\n",
>> + i + 1);
>> + return 0;
>> + }
>> +
>> + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
>> + if (ret) {
>> + printf("Warning: failed to initialize mmc dev %d\n", i);
>> + return ret;
>> + }
>> + }
>> +
>> + return 0;
>> }
>> +void board_boot_order(u32 *spl_boot_list)
>> +{
>> + u32 bmode = imx6_src_get_boot_mode();
>> + u8 boot_dev = BOOT_DEVICE_MMC1;
>> +
>> + switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
>> + case IMX6_BMODE_SD:
>> + case IMX6_BMODE_ESD:
>> + boot_dev = BOOT_DEVICE_MMC1;
>> + break;
>> + case IMX6_BMODE_MMC:
>> + case IMX6_BMODE_EMMC:
>> + boot_dev = BOOT_DEVICE_MMC2;
>> + break;
>> + default:
>> + /* Default - BOOT_DEVICE_MMC1 */
>> + printf("Wrong board boot order\n");
>> + break;
>> + }
>> +
>> + spl_boot_list[0] = boot_dev;
>> +}
>> #endif /* CONFIG_FSL_ESDHC */
>> void board_init_f(ulong dummy)
>> diff --git a/configs/phycore_pcl063_ull_defconfig
>> b/configs/phycore_pcl063_ull_defconfig
>> new file mode 100644
>> index 0000000000..75408a8344
>> --- /dev/null
>> +++ b/configs/phycore_pcl063_ull_defconfig
>> @@ -0,0 +1,54 @@
>> +CONFIG_ARM=y
>> +CONFIG_ARCH_MX6=y
>> +CONFIG_SYS_TEXT_BASE=0x87800000
>> +CONFIG_SPL_LIBCOMMON_SUPPORT=y
>> +CONFIG_SPL_LIBGENERIC_SUPPORT=y
>> +CONFIG_TARGET_PCL063_ULL=y
>> +CONFIG_SPL_MMC_SUPPORT=y
>> +CONFIG_SPL_SERIAL_SUPPORT=y
>> +CONFIG_SPL=y
>> +# CONFIG_CMD_DEKBLOB is not set
>> +CONFIG_DISTRO_DEFAULTS=y
>> +CONFIG_NR_DRAM_BANKS=8
>> +CONFIG_FIT=y
>> +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
>> +CONFIG_BOOTDELAY=3
>> +# CONFIG_USE_BOOTCOMMAND is not set
>> +CONFIG_BOARD_EARLY_INIT_F=y
>> +CONFIG_SPL_USB_HOST_SUPPORT=y
>> +CONFIG_SPL_WATCHDOG_SUPPORT=y
>> +CONFIG_CMD_DM=y
>> +CONFIG_CMD_GPIO=y
>> +CONFIG_CMD_GPT=y
>> +# CONFIG_RANDOM_UUID is not set
>> +CONFIG_CMD_I2C=y
>> +CONFIG_CMD_MMC=y
>> +CONFIG_CMD_USB=y
>> +CONFIG_CMD_USB_SDP=y
>> +CONFIG_CMD_CACHE=y
>> +# CONFIG_ISO_PARTITION is not set
>> +CONFIG_OF_CONTROL=y
>> +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-phycore-segin"
>> +CONFIG_DM_I2C_GPIO=y
>> +CONFIG_SYS_I2C_MXC=y
>> +CONFIG_FSL_ESDHC=y
>> +CONFIG_PHYLIB=y
>> +CONFIG_PHY_MICREL=y
>> +CONFIG_FEC_MXC=y
>> +CONFIG_MII=y
>> +CONFIG_PINCTRL=y
>> +CONFIG_PINCTRL_IMX6=y
>> +CONFIG_DM_PMIC=y
>> +# CONFIG_SPL_PMIC_CHILDREN is not set
>> +CONFIG_DM_REGULATOR=y
>> +CONFIG_DM_REGULATOR_FIXED=y
>> +CONFIG_MXC_UART=y
>> +CONFIG_USB=y
>> +CONFIG_DM_USB=y
>> +CONFIG_USB_GADGET=y
>> +CONFIG_USB_GADGET_MANUFACTURER="Phytec"
>> +CONFIG_USB_GADGET_VENDOR_NUM=0x01b67
>> +CONFIG_USB_GADGET_PRODUCT_NUM=0x4fff
>> +CONFIG_CI_UDC=y
>> +CONFIG_USB_GADGET_DOWNLOAD=y
>> +CONFIG_LZO=y
>> diff --git a/include/configs/pcl063.h b/include/configs/pcl063.h
>> index 4ceab519cb..c032f05fc5 100644
>> --- a/include/configs/pcl063.h
>> +++ b/include/configs/pcl063.h
>> @@ -24,6 +24,8 @@
>> #undef CONFIG_SPL_TEXT_BASE
>> #define CONFIG_SPL_TEXT_BASE 0x00909000
>> +#define CONFIG_SYS_FSL_USDHC_NUM 1
>> +
>> /* Size of malloc() pool */
>> #define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
>> diff --git a/include/configs/pcl063_ull.h
>> b/include/configs/pcl063_ull.h
>> new file mode 100644
>> index 0000000000..0f1a010b4e
>> --- /dev/null
>> +++ b/include/configs/pcl063_ull.h
>> @@ -0,0 +1,117 @@
>> +/* SPDX-License-Identifier: GPL-2.0+ */
>> +/*
>> + * Board configuration file for Phytec phyBOARD-i.MX6ULL-Segin SBC
>> + * Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com>
>> + *
>> + * Based on include/configs/xpress.h:
>> + * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
>> + */
>> +#ifndef __PCL063_ULL_H
>> +#define __PCL063_ULL_H
>> +
>> +#include <linux/sizes.h>
>> +#include "mx6_common.h"
>> +
>> +/* SPL options */
>> +#include "imx6_spl.h"
>> +
>> +#define CONFIG_SYS_FSL_USDHC_NUM 2
>> +
>> +/* Size of malloc() pool */
>> +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
>> +
>> +/* Environment settings */
>> +#define CONFIG_ENV_SIZE (0x4000)
>> +#define CONFIG_ENV_OFFSET (0x80000)
>> +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
>> +#define CONFIG_ENV_OFFSET_REDUND \
>> + (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
>> +
>> +/* Environment in SD */
>> +#define CONFIG_SYS_MMC_ENV_DEV 0
>> +#define CONFIG_SYS_MMC_ENV_PART 0
>> +#define MMC_ROOTFS_DEV 0
>> +#define MMC_ROOTFS_PART 2
>> +
>> +/* Console configs */
>> +#define CONFIG_MXC_UART_BASE UART1_BASE
>> +
>> +/* MMC Configs */
>> +#define CONFIG_FSL_USDHC
>> +
>> +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
>> +#define CONFIG_SUPPORT_EMMC_BOOT
>> +
>> +/* I2C configs */
>> +#ifdef CONFIG_CMD_I2C
>> +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
>> +#define CONFIG_SYS_I2C_SPEED 100000
>> +#endif
>> +
>> +/* Miscellaneous configurable options */
>> +#define CONFIG_SYS_MEMTEST_START 0x80000000
>> +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START +
>> 0x10000000)
>> +
>> +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
>> +#define CONFIG_SYS_HZ 1000
>> +
>> +/* Physical Memory Map */
>> +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
>> +#define PHYS_SDRAM_SIZE SZ_256M
>> +
>> +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
>> +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
>> +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
>> +
>> +#define CONFIG_SYS_INIT_SP_OFFSET \
>> + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
>> +#define CONFIG_SYS_INIT_SP_ADDR \
>> + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
>> +
>> +/* NAND */
>> +#define CONFIG_SYS_MAX_NAND_DEVICE 1
>> +#define CONFIG_SYS_NAND_BASE 0x40000000
>> +
>> +/* USB Configs */
>> +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
>> +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
>> +#define CONFIG_MXC_USB_FLAGS 0
>> +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
>> +
>> +#define CONFIG_IMX_THERMAL
>> +
>> +#define ENV_MMC \
>> + "mmcdev=" __stringify(MMC_ROOTFS_DEV) "\0" \
>> + "mmcpart=" __stringify(MMC_ROOTFS_PART) "\0" \
>> + "fitpart=1\0" \
>> + "bootdelay=3\0" \
>> + "silent=1\0" \
>> + "optargs=rw rootwait\0" \
>> + "mmcautodetect=yes\0" \
>> + "mmcrootfstype=ext4\0" \
>> + "mmcfit_name=fitImage\0" \
>> + "mmcloadfit=fatload mmc ${mmcdev}:${fitpart} ${fit_addr} " \
>> + "${mmcfit_name}\0" \
>> + "mmcargs=setenv bootargs " \
>> + "root=/dev/mmcblk${mmcdev}p${mmcpart} ${optargs} " \
>> + "console=${console} rootfstype=${mmcrootfstype}\0" \
>> + "mmc_mmc_fit=run mmcloadfit;run mmcargs addcon; bootm
>> ${fit_addr}\0" \
>> +
>> +/* Default environment */
>> +#define CONFIG_EXTRA_ENV_SETTINGS \
>> + "fdt_high=0xffffffff\0" \
>> + "console=ttymxc0,115200n8\0" \
>> + "addcon=setenv bootargs ${bootargs}
>> console=${console},${baudrate}\0" \
>> + "fit_addr=0x82000000\0" \
>> + ENV_MMC
>> +
>> +#define CONFIG_BOOTCOMMAND "run mmc_mmc_fit"
>> +
>> +#define BOOT_TARGET_DEVICES(func) \
>> + func(MMC, mmc, 0) \
>> + func(MMC, mmc, 1) \
>> + func(DHCP, dhcp, na)
>> +
>> +#include <config_distro_bootcmd.h>
>> +
>> +#endif /* __PCL063_ULL_H */
>>
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2019-01-19 9:37 Angelo Dureghello
0 siblings, 0 replies; 430+ messages in thread
From: Angelo Dureghello @ 2019-01-19 9:37 UTC (permalink / raw)
To: u-boot
[PATCH RESEND] drivers: esdhc: add support for ColdFire mcf5441x family
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2018-11-22 20:08 sjg at google.com
0 siblings, 0 replies; 430+ messages in thread
From: sjg at google.com @ 2018-11-22 20:08 UTC (permalink / raw)
To: u-boot
From: Simon Glass <sjg@chromium.org>
To: U-Boot Mailing List <u-boot@lists.denx.de>
Cc: Tom Rini <trini@konsulko.com>,
Marek Vasut <marek.vasut@gmail.com>,
Simon Glass <sjg@chromium.org>,
Masahiro Yamada <yamada.masahiro@socionext.com>,
Rasmus Villemoes <rasmus.villemoes@prevas.dk>,
Baruch Siach <baruch@tkos.co.il>,
Jagdish Gediya <jagdish.gediya@nxp.com>,
Stephen Warren <swarren@nvidia.com>
Subject: [PATCH 1/3] Makefile: Add a warning for boards that don't use
CONFIG_BLK
Date: Thu, 22 Nov 2018 13:07:54 -0700
Message-Id: <20181122200756.127191-1-sjg@chromium.org>
X-Mailer: git-send-email 2.19.1.1215.g8438c0b245-goog
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
The deadline for this has passed and we are starting to remove boards that
do not use driver model for block devices.
Add a noisy Makefile warning.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
Makefile | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Makefile b/Makefile
index 552687db538..8bf422f6a85 100644
--- a/Makefile
+++ b/Makefile
@@ -917,6 +917,13 @@ ifeq ($(CONFIG_DM_I2C_COMPAT)$(CONFIG_SANDBOX),y)
@echo "(possibly in a subsequent patch in your series)"
@echo "before sending patches to the mailing list."
@echo "===================================================="
+endif
+ifneq ($(CONFIG_BLK),y)
+ @echo "===================== WARNING ======================"
+ @echo "This board does not use CONFIG_BLK. Please update"
+ @echo "the board to use CONFIG_BLK before the end of 2018."
+ @echo "See doc/driver-model/MIGRATION.txt for more info."
+ @echo "===================================================="
endif
@# Check that this build does not use CONFIG options that we do not
@# know about unless they are in Kconfig. All the existing CONFIG
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2018-09-20 21:07 Angelo Dureghello
0 siblings, 0 replies; 430+ messages in thread
From: Angelo Dureghello @ 2018-09-20 21:07 UTC (permalink / raw)
To: u-boot
This patch adds an initial fdt support to the m68k architecture.
It has been tested on stmark2 board, with a devicetree and
CONFIG_DM_SERIAL=y + CONFIG_DM_SPI=y.
----- test log -----
U-Boot 2018.09-00137-g1be43784f1 (Sep 20 2018 - 22:34:42 +0200)
CPU: Freescale MCF54415 (Mask:a0 Version:2)
CPU CLK 240 MHz BUS CLK 120 MHz FLB CLK 60 MHz
INP CLK 30 MHz VCO CLK 480 MHz
SPI: ready
DRAM: 128 MiB
Loading Environment from SPI Flash... SF: Detected is25lp128 with page size 256 Bytes, erase size 64 KiB, total 16 MiB
*** Warning - bad CRC, using default environment
In: uart at fc060000
Out: uart at fc060000
Err: uart at fc060000
Hit any key to stop autoboot: 0
SF: Detected is25lp128 with page size 256 Bytes, erase size 64 KiB, total 16 MiB
device 0 offset 0x100000, size 0x700000
SF: 7340032 bytes @ 0x100000 Read: OK
## Booting kernel from Legacy Image at 40001000 ...
Image Name: mainline kernel
Created: 2018-09-14 19:06:13 UTC
Image Type: M68K Linux Kernel Image (uncompressed)
Data Size: 2184848 Bytes = 2.1 MiB
Load Address: 40001000
Entry Point: 40001000
Verifying Checksum ... OK
Loading Kernel Image ... OK
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2018-09-18 21:49 Jeremy Gebben
0 siblings, 0 replies; 430+ messages in thread
From: Jeremy Gebben @ 2018-09-18 21:49 UTC (permalink / raw)
To: u-boot
Date: Tue, 18 Sep 2018 15:35:32 -0600
Subject: [PATCH 0/3] net: phy: aquantia: firmware loading
This patch series adds optional support for loading firmware for
Aquantia phys via MDIO commands. Because I'm adding more Kconfig
options for this driver, I've cleaned up the existing defconfigs
that use it.
It has been tested on a NXP ls1046ardb board, and a very similar
custom board that doesn't have dedicated storage for the phy
firmware.
Jeremy Gebben (3):
configs: migrate CONFIG_PHY_AQUANTIA to Kconfig
net: phy: aquantia: add firmware loading support
net: phy: aquantia: autodetect if firmware needs to be loaded
configs/T1023RDB_NAND_defconfig | 2 +-
configs/T1023RDB_SDCARD_defconfig | 2 +-
configs/T1023RDB_SECURE_BOOT_defconfig | 2 +-
configs/T1023RDB_SPIFLASH_defconfig | 2 +-
configs/T1023RDB_defconfig | 2 +-
configs/T1024RDB_NAND_defconfig | 2 +-
configs/T1024RDB_SDCARD_defconfig | 2 +-
configs/T1024RDB_SECURE_BOOT_defconfig | 2 +-
configs/T1024RDB_SPIFLASH_defconfig | 2 +-
configs/T1024RDB_defconfig | 2 +-
configs/T2080QDS_NAND_defconfig | 2 +-
configs/T2080QDS_SDCARD_defconfig | 2 +-
configs/T2080QDS_SECURE_BOOT_defconfig | 2 +-
configs/T2080QDS_SPIFLASH_defconfig | 2 +-
configs/T2080QDS_SRIO_PCIE_BOOT_defconfig | 2 +-
configs/T2080QDS_defconfig | 2 +-
configs/T2080RDB_NAND_defconfig | 2 +-
configs/T2080RDB_SDCARD_defconfig | 2 +-
configs/T2080RDB_SECURE_BOOT_defconfig | 2 +-
configs/T2080RDB_SPIFLASH_defconfig | 2 +-
configs/T2080RDB_SRIO_PCIE_BOOT_defconfig | 2 +-
configs/T2080RDB_defconfig | 2 +-
configs/T2081QDS_NAND_defconfig | 2 +-
configs/T2081QDS_SDCARD_defconfig | 2 +-
configs/T2081QDS_SPIFLASH_defconfig | 2 +-
configs/T2081QDS_SRIO_PCIE_BOOT_defconfig | 2 +-
configs/T2081QDS_defconfig | 2 +-
configs/ls1043ardb_defconfig | 2 +-
configs/ls1043ardb_nand_SECURE_BOOT_defconfig | 2 +-
configs/ls1043ardb_nand_defconfig | 2 +-
configs/ls1043ardb_sdcard_defconfig | 2 +-
configs/ls1046ardb_emmc_defconfig | 2 +-
configs/ls1046ardb_qspi_SECURE_BOOT_defconfig | 2 +-
configs/ls1046ardb_qspi_defconfig | 2 +-
.../ls1046ardb_sdcard_SECURE_BOOT_defconfig | 2 +-
configs/ls1046ardb_sdcard_defconfig | 2 +-
configs/ls1088ardb_qspi_SECURE_BOOT_defconfig | 1 +
configs/ls1088ardb_qspi_defconfig | 1 +
...1088ardb_sdcard_qspi_SECURE_BOOT_defconfig | 1 +
configs/ls1088ardb_sdcard_qspi_defconfig | 1 +
configs/ls2080ardb_defconfig | 2 +-
configs/ls2080ardb_nand_defconfig | 2 +-
drivers/net/phy/Kconfig | 26 +-
drivers/net/phy/aquantia.c | 254 +++++++++++++++++-
include/configs/T102xRDB.h | 2 -
include/configs/T208xRDB.h | 2 -
include/configs/ls1043ardb.h | 2 -
include/configs/ls1046ardb.h | 2 -
include/configs/ls1088ardb.h | 3 -
include/configs/ls2080ardb.h | 3 -
50 files changed, 316 insertions(+), 58 deletions(-)
--
2.17.1
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2017-05-15 9:49 [U-Boot] [PATCH v2 0/7] Add basic support for Rockchip RK3368 SOC Andy Yan
@ 2017-05-15 9:53 ` Andy Yan
0 siblings, 0 replies; 430+ messages in thread
From: Andy Yan @ 2017-05-15 9:53 UTC (permalink / raw)
To: u-boot
:wq
:q
:q
From: Andy Yan <andy.yan@rock-chips.com>
Date: Thu, 9 Mar 2017 19:30:53 +0800
Subject: [PATCH v2 4/7] rockchip: rk3368: Add sysreset driver
Add sysreset driver to reset rk3368 SOC.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
Changes in v2:
- slect soft reset source before reset
drivers/sysreset/Makefile | 1 +
drivers/sysreset/sysreset_rk3368.c | 62 ++++++++++++++++++++++++++++++++++++++
2 files changed, 63 insertions(+)
create mode 100644 drivers/sysreset/sysreset_rk3368.c
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index 7bb8406..42aaeaf 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -13,6 +13,7 @@ endif
obj-$(CONFIG_ROCKCHIP_RK3188) += sysreset_rk3188.o
obj-$(CONFIG_ROCKCHIP_RK3288) += sysreset_rk3288.o
obj-$(CONFIG_ROCKCHIP_RK3328) += sysreset_rk3328.o
+obj-$(CONFIG_ROCKCHIP_RK3368) += sysreset_rk3368.o
obj-$(CONFIG_ROCKCHIP_RK3399) += sysreset_rk3399.o
obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o
obj-$(CONFIG_ARCH_SNAPDRAGON) += sysreset_snapdragon.o
diff --git a/drivers/sysreset/sysreset_rk3368.c b/drivers/sysreset/sysreset_rk3368.c
new file mode 100644
index 0000000..de62921
--- /dev/null
+++ b/drivers/sysreset/sysreset_rk3368.c
@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <sysreset.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3368.h>
+#include <asm/arch/hardware.h>
+#include <linux/err.h>
+
+static void rk3368_pll_enter_slow_mode(struct rk3368_cru *cru)
+{
+ struct rk3368_pll *pll;
+ int i;
+
+ for (i = 0; i < 6; i++) {
+ pll = &cru->pll[i];
+ rk_clrreg(&pll->con3, PLL_MODE_MASK);
+ }
+}
+
+static int rk3368_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+ struct rk3368_cru *cru = rockchip_get_cru();
+
+ if (IS_ERR(cru))
+ return PTR_ERR(cru);
+ switch (type) {
+ case SYSRESET_WARM:
+ rk3368_pll_enter_slow_mode(cru);
+ rk_clrsetreg(&cru->glb_rst_con, PMU_GLB_SRST_CTRL_MASK,
+ PMU_RST_BY_SND_GLB_SRST << PMU_GLB_SRST_CTRL_SHIFT);
+ writel(0xeca8, &cru->glb_srst_snd_val);
+ break;
+ case SYSRESET_COLD:
+ rk3368_pll_enter_slow_mode(cru);
+ rk_clrsetreg(&cru->glb_rst_con, PMU_GLB_SRST_CTRL_MASK,
+ PMU_RST_BY_FST_GLB_SRST << PMU_GLB_SRST_CTRL_SHIFT);
+ writel(0xfdb9, &cru->glb_srst_fst_val);
+ break;
+ default:
+ return -EPROTONOSUPPORT;
+ }
+
+ return -EINPROGRESS;
+}
+
+static struct sysreset_ops rk3368_sysreset = {
+ .request = rk3368_sysreset_request,
+};
+
+U_BOOT_DRIVER(sysreset_rk3368) = {
+ .name = "rk3368_sysreset",
+ .id = UCLASS_SYSRESET,
+ .ops = &rk3368_sysreset,
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2017-04-21 3:01 Zhikang Zhang
0 siblings, 0 replies; 430+ messages in thread
From: Zhikang Zhang @ 2017-04-21 3:01 UTC (permalink / raw)
To: u-boot
Test for NVMe driver:
platform: LS1046AQDS
NVMe SSD: Intel P3700 400G
The test logs are as follow:
----------------------------
=> nvme list
Device 0: Vendor: 0x8086 Rev: 8DV10131 Prod: CVFT535600LS400BGN
Type: Hard Disk
Capacity: 381554.0 MB = 372.6 GB (781422768 x 512)
=> nvme device 0
Device 0: Vendor: 0x8086 Rev: 8DV10131 Prod: CVFT535600LS400BGN
Type: Hard Disk
Capacity: 381554.0 MB = 372.6 GB (781422768 x 512)
... is now current device
=> nvme info
Blk device 0: Optional Admin Command Support:
Namespace Management/Attachment: no
Firmware Commit/Image download: yes
Format NVM: yes
Security Send/Receive: no
Blk device 0: Optional NVM Command Support:
Reservation: no
Save/Select field in the Set/Get features: no
Write Zeroes: yes
Dataset Management: yes
Write Uncorrectable: no
Blk device 0: Format NVM Attributes:
Support Cryptographic Erase: yes
Support erase a particular namespace: No
Support format a particular namespace: No
Blk device 0: LBA Format Support:
LBA Foramt 0 Support: (current)
Metadata Size: 0
LBA Data Size: 512
Relative Performance: Good
LBA Foramt 1 Support:
Metadata Size: 8
LBA Data Size: 512
Relative Performance: Good
LBA Foramt 2 Support:
Metadata Size: 16
LBA Data Size: 512
Relative Performance: Good
LBA Foramt 3 Support:
Metadata Size: 0
LBA Data Size: 4096
Relative Performance: Best
LBA Foramt 4 Support:
Metadata Size: 8
LBA Data Size: 4096
Relative Performance: Best
LBA Foramt 5 Support:
Metadata Size: 64
LBA Data Size: 4096
Relative Performance: Best
Blk device 0: End-to-End DataProtect Capabilities:
As last eight bytes: yes
As first eight bytes: No
Support Type3: No
Support Type2: No
Support Type1: yes
Blk device 0: Metadata capabilities:
As part of a separate buffer: No
As part of an extended data LBA: yes
=> nvme part
Partition Map for UNKNOWN device 0 -- Partition Type: DOS
Part Start Sector Num Sectors UUID Type
1 2048 2048000 ffc18949-01 83
=> nvme read 90000000 0 100000
NVME read: device 0 block # 0, count 1048576 ... read: OK
536870912 bytes read in 1086 ms (471.5 MiB/s)
=> nvme write 90000000 0 100000
NVME write: device 0 block # 0, count 1048576 ... write: OK
536870912 bytes read in 1070 ms (478.5 MiB/s)
=> fatls nvme 0
32376967 kernel.itb
22929408 100m
2 file(s), 0 dir(s)
=> fatload nvme 0 90000000 kernel.itb
reading kernel.itb
32376967 bytes read in 128 ms (241.2 MiB/s)
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2016-11-25 18:16 Rick Bronson
0 siblings, 0 replies; 430+ messages in thread
From: Rick Bronson @ 2016-11-25 18:16 UTC (permalink / raw)
To: u-boot
Hi All,
I've got nsupported RK3288 hardware running the latest git u-boot to SPL
as explained in
http://git.denx.de/?p=u-boot.git;a=blob;f=doc/README.rockchip. My goal
is to run the mainline (ie. not Android) Linux kernel on this hardware
and wondered:
- Do I need to get the latest git u-boot to run before I can run the
mainline kernel? Or can I use
github.com/linux-rockchip/u-boot-rockchip.git, which I have running
u-boot fully.
- The device tree seems to be in two places, once via:
resource_tool --image=resource2.img --pack linux/logo.bmp ${DTS}.dtb
that gets put into the resource file and then again at the end of the
kernel via CONFIG_ARM_APPENDED_DTB. Do I need both? When I do both
I get things like:
....
Unknow param: MACHINE_MODEL:rk30sdk!
Unknow param: MACHINE_ID:007!
....
Thanks much.
Rick
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2016-07-13 14:11 [U-Boot] [PATCH] arm: imx: Add support for Advantech DMS-BA16 board Akshay Bhat
@ 2016-07-20 16:25 ` Stefano Babic
0 siblings, 0 replies; 430+ messages in thread
From: Stefano Babic @ 2016-07-20 16:25 UTC (permalink / raw)
To: u-boot
HI Akshay,
On 01/01/1970 01:00, wrote:
> Add support for Advantech DMS-BA16 board. The board is based on Advantech
> BA16 module which has a i.MX6D processor. The board supports:
> - FEC Ethernet
> - USB Ports
> - SDHC and MMC boot
> - SPI NOR
> - LVDS and HDMI display
>
> Basic information about the module:
> - Module manufacturer: Advantech
> - CPU: Freescale ARM Cortex-A9 i.MX6D
> - SPECS:
> Up to 2GB Onboard DDR3 Memory;
> Up to 16GB Onboard eMMC NAND Flash
> Supports OpenGL ES 2.0 and OpenVG 1.1
> HDMI, 24-bit LVDS
> 1x UART, 2x I2C, 8x GPIO,
> 4x Host USB 2.0 port, 1x USB OTG port,
> 1x micro SD (SDHC),1x SDIO, 1x SATA II,
> 1x 10/100/1000 Mbps Ethernet, 1x PCIe X1 Gen2
>
> Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
> Cc: u-boot at lists.denx.de
> Cc: sbabic at denx.de
> ---
> arch/arm/cpu/armv7/mx6/Kconfig | 5 +
> board/advantech/dms-ba16/Kconfig | 27 ++
> board/advantech/dms-ba16/MAINTAINERS | 8 +
> board/advantech/dms-ba16/Makefile | 8 +
> board/advantech/dms-ba16/ddr_1g.cfg | 206 +++++++++++++
> board/advantech/dms-ba16/ddr_2g.cfg | 151 +++++++++
> board/advantech/dms-ba16/dms-ba16.c | 571 +++++++++++++++++++++++++++++++++++
> configs/dms-ba16-1g_defconfig | 27 ++
> configs/dms-ba16_defconfig | 26 ++
> include/configs/advantech_dms-ba16.h | 329 ++++++++++++++++++++
> 10 files changed, 1358 insertions(+)
> create mode 100644 board/advantech/dms-ba16/Kconfig
> create mode 100644 board/advantech/dms-ba16/MAINTAINERS
> create mode 100644 board/advantech/dms-ba16/Makefile
> create mode 100644 board/advantech/dms-ba16/ddr_1g.cfg
> create mode 100644 board/advantech/dms-ba16/ddr_2g.cfg
> create mode 100644 board/advantech/dms-ba16/dms-ba16.c
> create mode 100644 configs/dms-ba16-1g_defconfig
> create mode 100644 configs/dms-ba16_defconfig
> create mode 100644 include/configs/advantech_dms-ba16.h
>
> diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
> index 663f970..1e4a1cb 100644
> --- a/arch/arm/cpu/armv7/mx6/Kconfig
> +++ b/arch/arm/cpu/armv7/mx6/Kconfig
> @@ -35,6 +35,10 @@ choice
> prompt "MX6 board select"
> optional
>
> +config TARGET_ADVANTECH_DMS_BA16
> + bool "Advantech dms-ba16"
> + select MX6Q
> +
> config TARGET_ARISTAINETOS
> bool "aristainetos"
>
> @@ -184,6 +188,7 @@ config SYS_SOC
> default "mx6"
>
> source "board/ge/bx50v3/Kconfig"
> +source "board/advantech/dms-ba16/Kconfig"
> source "board/aristainetos/Kconfig"
> source "board/bachmann/ot1200/Kconfig"
> source "board/barco/platinum/Kconfig"
> diff --git a/board/advantech/dms-ba16/Kconfig b/board/advantech/dms-ba16/Kconfig
> new file mode 100644
> index 0000000..cbc803f
> --- /dev/null
> +++ b/board/advantech/dms-ba16/Kconfig
> @@ -0,0 +1,27 @@
> +choice
> + prompt "DDR Size"
> + default SYS_DDR_2G
> +
> +config SYS_DDR_1G
> + bool "1GiB"
> +
> +config SYS_DDR_2G
> + bool "2GiB"
> +
> +endchoice
> +
> +config IMX_CONFIG
> + default "board/advantech/dms-ba16/ddr_2g.cfg" if SYS_DDR_2G
> + default "board/advantech/dms-ba16/ddr_1g.cfg" if SYS_DDR_1G
> +
> +config SYS_BOARD
> + default "dms-ba16"
> +
> +config SYS_VENDOR
> + default "advantech"
> +
> +config SYS_SOC
> + default "mx6"
> +
> +config SYS_CONFIG_NAME
> + default "advantech_dms-ba16"
> diff --git a/board/advantech/dms-ba16/MAINTAINERS b/board/advantech/dms-ba16/MAINTAINERS
> new file mode 100644
> index 0000000..e8ea3dd
> --- /dev/null
> +++ b/board/advantech/dms-ba16/MAINTAINERS
> @@ -0,0 +1,8 @@
> +ADVANTECH_DMS-BA16 BOARD
> +M: Akshay Bhat <akshaybhat@timesys.com>
> +M: Ken Lin <Ken.Lin@advantech.com.tw>
> +S: Maintained
> +F: board/advantech/dms-ba16/
> +F: include/configs/advantech_dms-ba16.h
> +F: configs/dms-ba16_defconfig
> +F: configs/dms-ba16-1g_defconfig
> diff --git a/board/advantech/dms-ba16/Makefile b/board/advantech/dms-ba16/Makefile
> new file mode 100644
> index 0000000..ec9aaa8
> --- /dev/null
> +++ b/board/advantech/dms-ba16/Makefile
> @@ -0,0 +1,8 @@
> +#
> +# Copyright 2016 Timesys Corporation
> +# Copyright 2016 Advantech Corporation
> +#
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +
> +obj-y := dms-ba16.o
> diff --git a/board/advantech/dms-ba16/ddr_1g.cfg b/board/advantech/dms-ba16/ddr_1g.cfg
> new file mode 100644
> index 0000000..a470f48
> --- /dev/null
> +++ b/board/advantech/dms-ba16/ddr_1g.cfg
> @@ -0,0 +1,206 @@
> +/*
> + * Copyright (C) 2011 Freescale Semiconductor, Inc.
> + * Jason Liu <r64343@freescale.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + *
> + * Refer doc/README.imximage for more details about how-to configure
> + * and create imximage boot image
> + *
> + * The syntax is taken as close as possible with the kwbimage
> + */
> +
> +
> +IMAGE_VERSION 2
> +BOOT_FROM sd
> +
> +//*================================================================================================
> +// Enable all clocks (they are disabled by ROM code)
> +//*================================================================================================
> +DATA 4 0x020c4068 0xffffffff
> +DATA 4 0x020c406c 0xffffffff
> +DATA 4 0x020c4070 0xffffffff
> +DATA 4 0x020c4074 0xffffffff
> +DATA 4 0x020c4078 0xffffffff
> +DATA 4 0x020c407c 0xffffffff
> +DATA 4 0x020c4080 0xffffffff
> +DATA 4 0x020c4084 0xffffffff
Do you really need to enable all clocks ? Most boards try to enable just
the clocks they nee, not all.
There is a problem with this file. This seems coming from a very old
port, and it does not follow semantic as other imximage.cfg files.
You post a ddr2.cfg file and you see the differences: instead of bare
hexadecimal values for register address, the register name is used,
because the preprocessor runs before calling mkimage.
> +
> +//######################################################
> +// IOMUX
> +//######################################################
> +
> +//DDR IO TYPE:
> +DATA 4 0x020e0798 0x000c0000 // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE - DDR_SEL11
> +DATA 4 0x020e0758 0x00000000 // IOMUXC_SW_PAD_CTL_GRP_DDRPKE - PKE0 , Pull disabled for all, except DQS.
> +
> +//CLOCK:
> +DATA 4 0x020e0588 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 - DSE101, DDR_INPUT0, HYS0
> +DATA 4 0x020e0594 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 - DSE101, DDR_INPUT0, HYS0
> +
> +//ADDRESS:
> +DATA 4 0x020e056c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS - DSE110, DDR_INPUT1, HYS0
> +DATA 4 0x020e0578 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS - DSE110, DDR_INPUT1, HYS0
> +DATA 4 0x020e074c 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_ADDDS - DSE110
> +
> +//CONTROL:
> +DATA 4 0x020e057c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET - DSE110, DDR_INPUT1, HYS0, DDR_SEL00
> +DATA 4 0x020e058c 0x00000000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2
> +DATA 4 0x020e059c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
> +DATA 4 0x020e05a0 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1
> +DATA 4 0x020e078c 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_CTLDS - DSE110
> +
> +//DATA STROBE:
> +DATA 4 0x020e0750 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL - DDR_INPUT1
> +DATA 4 0x020e05a8 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 - DSE110
> +DATA 4 0x020e05b0 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 - DSE110
> +DATA 4 0x020e0524 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 - DSE110
> +DATA 4 0x020e051c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 - DSE110
> +DATA 4 0x020e0518 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4 - DSE110
> +DATA 4 0x020e050c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5 - DSE110
> +DATA 4 0x020e05b8 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6 - DSE110
> +DATA 4 0x020e05c0 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7 - DSE110
> +
> +//DATA:
> +DATA 4 0x020e0774 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE- DDR_INPUT 1,diff
> +DATA 4 0x020e0784 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B0DS - DSE110
> +DATA 4 0x020e0788 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B1DS - DSE110
> +DATA 4 0x020e0794 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B2DS - DSE110
> +DATA 4 0x020e079c 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B3DS - DSE110
> +DATA 4 0x020e07a0 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B4DS - DSE110
> +DATA 4 0x020e07a4 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B5DS - DSE110
> +DATA 4 0x020e07a8 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B6DS - DSE110
> +DATA 4 0x020e0748 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B7DS - DSE110
> +DATA 4 0x020e05ac 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 - DSE110, DDR_INPUT1, HYS0
> +DATA 4 0x020e05b4 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 - DSE110, DDR_INPUT1, HYS0
> +DATA 4 0x020e0528 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 - DSE110, DDR_INPUT1, HYS0
> +DATA 4 0x020e0520 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 - DSE110, DDR_INPUT1, HYS0
> +DATA 4 0x020e0514 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 - DSE110, DDR_INPUT1, HYS0
> +DATA 4 0x020e0510 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 - DSE110, DDR_INPUT1, HYS0
> +DATA 4 0x020e05bc 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 - DSE110, DDR_INPUT1, HYS0
> +DATA 4 0x020e05c4 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 - DSE110, DDR_INPUT1, HYS0
If you switch to SPL, all this stuff is managed by common code.
Even if you do not want it, you should factorize this in several files,
maybe reusing some .fg from other boards. Take a look at
boudary/nitrogen6x (nitrogen6q.cfg).
And register address must be substituted by names, as you have already
done for the second file.
> +
> +//######################################################
> +//Calibrations:
> +//######################################################
> +// ZQ:
> +DATA 4 0x021b0800 0xa1390003 // DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic HW ZQ calibration.
> +
> +// write leveling
> +DATA 4 0x021b080c 0x001F001F
> +DATA 4 0x021b0810 0x001F001F
> +DATA 4 0x021b480c 0x001F001F
> +DATA 4 0x021b4810 0x001F001F
> +
> +//DQS gating, read delay, write delay calibration values based on calibration compare of 0x00ffff00:
> +// It is highly recommended for the user to run calibration code on her/his specific board
> +//and replace following delay values accordingly:
> +
> +//Read DQS Gating calibration
> +DATA 4 0x021b083c 0x43480350
> +DATA 4 0x021b0840 0x033C0340
> +DATA 4 0x021b483c 0x43480350
> +DATA 4 0x021b4840 0x03340314
> +
> +//Read calibration
> +DATA 4 0x021b0848 0x382E2C32
> +DATA 4 0x021b4848 0x38363044
> +
> +//Write calibration
> +DATA 4 0x021b0850 0x3A38403A
> +DATA 4 0x021b4850 0x4432483E
> +
> +//read data bit delay: (3 is the reccommended default value, although out of reset value is 0):
> +DATA 4 0x021b081c 0x33333333 // DDR_PHY_P0_MPREDQBY0DL3
> +DATA 4 0x021b0820 0x33333333 // DDR_PHY_P0_MPREDQBY1DL3
> +DATA 4 0x021b0824 0x33333333 // DDR_PHY_P0_MPREDQBY2DL3
> +DATA 4 0x021b0828 0x33333333 // DDR_PHY_P0_MPREDQBY3DL3
> +DATA 4 0x021b481c 0x33333333 // DDR_PHY_P1_MPREDQBY0DL3
> +DATA 4 0x021b4820 0x33333333 // DDR_PHY_P1_MPREDQBY1DL3
> +DATA 4 0x021b4824 0x33333333 // DDR_PHY_P1_MPREDQBY2DL3
> +DATA 4 0x021b4828 0x33333333 // DDR_PHY_P1_MPREDQBY3DL3
> +
> +//######################################################
> +// Complete calibration by forced measurment:
> +//######################################################
> +DATA 4 0x021b08b8 0x00000800 // DDR_PHY_P0_MPMUR0, frc_msr
> +DATA 4 0x021b48b8 0x00000800 // DDR_PHY_P0_MPMUR0, frc_msr
> +
> +//######################################################
> +//MMDC init:
> +//528MHz in DDR3, 64-bit mode, only MMDC0 is initiated:
> +DATA 4 0x021b0004 0x00020036 // MMDC0_MDPDC see spread sheet for timings
> +DATA 4 0x021b0008 0x09444040 // MMDC0_MDOTC see spread sheet for timings
> +DATA 4 0x021b000c 0x555A79A5 // MMDC0_MDCFG0 see spread sheet for timings. CL8
> +DATA 4 0x021b0010 0xDB538E64 // MMDC0_MDCFG1 see spread sheet for timings
> +DATA 4 0x021b0014 0x01ff00db // MMDC0_MDCFG2 - tRRD - 4ck; tWTR - 4ck; tRTP - 4ck; tDLLK - 512ck
> +DATA 4 0x021b0018 0x00001740 // MMDC0_MDMISC, RALAT0x5
> +//MDMISC: RALAT kept to the high level of 5.
> +//MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits:
> +//a. better operation at low frequency
> +//b. Small performence improvment
> +
> +DATA 4 0x021b001c 0x00008000 // MMDC0_MDSCR
> +DATA 4 0x021b002c 0x000026d2 // MMDC0_MDRWD
> +DATA 4 0x021b0030 0x005a1023 // MMDC0_MDOR - tXPR - 91ck; SDE_to_RST - 13ck; RST_to_CKE - 32ck
> +DATA 4 0x021b0040 0x00000027 // CS0_END - 0x4fffffff
> +DATA 4 0x021b0000 0x831a0000 // MMDC0_MDCTL - row - 14bits; col 10bits; burst length 8; 64-bit data bus
> +
> +//######################################################
> +// Initialize 2GB DDR3 - Micron MT41J128M , but fit wide range of other DDR3 devices
> +//MR2:
> +DATA 4 0x021b001c 0x04088032 // MMDC0_MDSCR
> +DATA 4 0x021b001c 0x0408803a // MMDC0_MDSCR
> +//MR3:
> +DATA 4 0x021b001c 0x00008033 // MMDC0_MDSCR
> +DATA 4 0x021b001c 0x0000803b // MMDC0_MDSCR
> +//MR1:
> +DATA 4 0x021b001c 0x00048031 // MMDC0_MDSCR
> +DATA 4 0x021b001c 0x00048039 // MMDC0_MDSCR
> +//MR0:
> +DATA 4 0x021b001c 0x09408030 // MMDC0_MDSCR,
> +DATA 4 0x021b001c 0x09408038 // MMDC0_MDSCR,
> +
> +//DDR device ZQ calibration:
> +DATA 4 0x021b001c 0x04008040 // MMDC0_MDSCR,
> +DATA 4 0x021b001c 0x04008048 // MMDC0_MDSCR
> +//######################################################
> +//final DDR setup, before operation start:
> +DATA 4 0x021b0020 0x00005800 // MMDC0_MDREF, enable auto refresh, set refresh rate.
> +
> +//Following ODT setup (0x11117) represents(along with obove DDR device configs) : i.mx_ODTDDR_device_ODT120OHm.
> +//User might to also interested in trying the value of 0x00000007,which represents: i.mx_ODT disabled, DDR_device_ODT120Ohm.
> +//0x00000007 saves more power, and seen to run very well with Freescale RDKs. Still, running with no ODT has it's implications
> +// of signal integrity and should be carefully simulated during board design.
> +
> +DATA 4 0x021b0818 0x00033337 // DDR_PHY_P0_MPODTCTRL, ODT enable
> +DATA 4 0x021b4818 0x00033337 // DDR_PHY_P1_MPODTCTRL
> +DATA 4 0x021b0004 0x00025576 // MMDC0_MDPDC see spread sheet for timings, SDCTL power down enabled
> +DATA 4 0x021b0404 0x00011006 //MMDC0_MAPSR ADOPT power down enabled
> +DATA 4 0x021b001c 0x00000000 // MMDC0_MDSCR
> +
We had this status at the beginning with i.MX6 - it is pity if a board
will be introduced dropping all common code.
This RAM chip is used on several i.MX6 board, and configuration can be
reused.
> +/* set the default clock gate to save power */
> +DATA 4 0x020c4068 0x00C03F3F
> +DATA 4 0x020c406c 0x0030FC03
> +DATA 4 0x020c4070 0x0FFFC000
> +DATA 4 0x020c4074 0x3FF00000
> +DATA 4 0x020c4078 0x00FFF300
> +DATA 4 0x020c407c 0x0F0000C3
> +DATA 4 0x020c4080 0x000003FF
..then I ask why all clocks were enable at the beginning of the file.
> +
> +/* enable AXI cache for VDOA/VPU/IPU */
> +DATA 4 0x020e0010 0xF00000CF
> +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
> +DATA 4 0x020e0018 0x007F007F
> +DATA 4 0x020e001c 0x007F007F
> +
> +/*
> + * Setup CCM_CCOSR register as follows:
> + *
> + * cko1_en 1 --> CKO1 enabled
> + * cko1_div 111 --> divide by 8
> + * cko1_sel 1011 --> ahb_clk_root
> + *
> + * This sets CKO1 at ahb_clk_root/8 132/8 16.5 MHz
> + */
Most of this file is currently replaced by common code. And if you use
SPL, imximage.cfg can be empty.
> +DATA 4 0x020c4060 0x000000fb
> diff --git a/board/advantech/dms-ba16/ddr_2g.cfg b/board/advantech/dms-ba16/ddr_2g.cfg
> new file mode 100644
> index 0000000..de88769
> --- /dev/null
> +++ b/board/advantech/dms-ba16/ddr_2g.cfg
> @@ -0,0 +1,151 @@
> +/*
> + *
> + * Copyright 2015 Timesys Corporation.
> + * Copyright 2015 General Electric Company
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + *
> + * Refer doc/README.imximage for more details about how-to configure
> + * and create imximage boot image
> + *
> + * The syntax is taken as close as possible with the kwbimage
> + */
> +
> +IMAGE_VERSION 2
> +BOOT_FROM sd
> +
> +#define __ASSEMBLY__
> +#include <config.h>
> +#include "asm/arch/mx6-ddr.h"
> +#include "asm/arch/iomux.h"
> +#include "asm/arch/crm_regs.h"
> +
> +/* DDR IO */
> +DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000c0000
> +DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
> +DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030
> +DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000030
> +DATA 4, MX6_IOM_DRAM_CAS, 0x00000030
> +DATA 4, MX6_IOM_DRAM_RAS, 0x00000030
> +DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
> +DATA 4, MX6_IOM_DRAM_RESET, 0x00000030
> +DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
> +DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000030
> +DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000030
> +DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
> +DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
> +DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
> +DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
> +DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
> +DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
> +DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
> +DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
> +DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
> +DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
> +DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
> +DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
> +DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
> +DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
> +DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
> +DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
> +DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
> +DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
> +DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
> +DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030
> +DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030
> +DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030
> +DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030
> +DATA 4, MX6_IOM_DRAM_DQM4, 0x00000030
> +DATA 4, MX6_IOM_DRAM_DQM5, 0x00000030
> +DATA 4, MX6_IOM_DRAM_DQM6, 0x00000030
> +DATA 4, MX6_IOM_DRAM_DQM7, 0x00000030
> +
> +/* Calibrations */
> +/* ZQ */
> +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003
> +/* write leveling */
> +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F
> +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
> +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F001F
> +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F
> +/* Read DQS Gating calibration */
> +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x45380544
> +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x05280530
> +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x4530053C
> +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x0530050C
> +/* Read calibration */
> +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x36303032
> +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x38363042
> +/* Write calibration */
> +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3A3A423E
> +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4A38483E
> +/* read data bit delay */
> +DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
> +DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
> +DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
> +DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
> +DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
> +DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
> +DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
> +DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
> +
> +/* Complete calibration by forced measurment */
> +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
> +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
> +
> +/* MMDC init */
> +DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
> +DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
> +DATA 4, MX6_MMDC_P0_MDCFG0, 0x8A8F79A4
> +DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538E64
> +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01ff00db
> +DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
> +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
> +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2
> +DATA 4, MX6_MMDC_P0_MDOR, 0x008F1023
> +DATA 4, MX6_MMDC_P0_MDASP, 0x00000047
> +DATA 4, MX6_MMDC_P0_MDCTL, 0x841a0000
> +
> +/* Initialize Micron MT41J128M */
> +DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032
> +DATA 4, MX6_MMDC_P0_MDSCR, 0x0408803a
> +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
> +DATA 4, MX6_MMDC_P0_MDSCR, 0x0000803b
> +DATA 4, MX6_MMDC_P0_MDSCR, 0x00408031
> +DATA 4, MX6_MMDC_P0_MDSCR, 0x00408039
> +DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030
> +DATA 4, MX6_MMDC_P0_MDSCR, 0x09408038
> +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
> +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008048
> +DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
> +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00011117
> +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00011117
> +DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
> +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
> +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
> +
> +/* set the default clock gate to save power */
> +DATA 4, CCM_CCGR0, 0x00C03F3F
> +DATA 4, CCM_CCGR1, 0x0030FC03
> +DATA 4, CCM_CCGR2, 0x0FFFC000
> +DATA 4, CCM_CCGR3, 0x3FF00000
> +DATA 4, CCM_CCGR4, 0x00FFF300
> +DATA 4, CCM_CCGR5, 0x0F0000C3
> +DATA 4, CCM_CCGR6, 0x000003FF
> +
> +/* enable AXI cache for VDOA/VPU/IPU */
> +DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
> +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
> +DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
> +DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
> +
> +/*
> + * Setup CCM_CCOSR register as follows:
> + *
> + * cko1_en 1 --> CKO1 enabled
> + * cko1_div 111 --> divide by 8
> + * cko1_sel 1011 --> ahb_clk_root
> + *
> + * This sets CKO1 at ahb_clk_root/8 132/8 16.5 MHz
> + */
> +DATA 4, CCM_CCOSR, 0x000000fb
This file makes use of the newer syntax with register names, but some
comments are valid for this file, too.
> diff --git a/board/advantech/dms-ba16/dms-ba16.c b/board/advantech/dms-ba16/dms-ba16.c
> new file mode 100644
> index 0000000..ff617ad
> --- /dev/null
> +++ b/board/advantech/dms-ba16/dms-ba16.c
> @@ -0,0 +1,571 @@
> +/*
> + * Copyright 2016 Timesys Corporation
> + * Copyright 2016 Advantech Corporation
> + * Copyright 2012 Freescale Semiconductor, Inc.
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <asm/arch/clock.h>
> +#include <asm/arch/imx-regs.h>
> +#include <asm/arch/iomux.h>
> +#include <asm/arch/mx6-pins.h>
> +#include <asm/errno.h>
> +#include <asm/gpio.h>
> +#include <asm/imx-common/mxc_i2c.h>
> +#include <asm/imx-common/iomux-v3.h>
> +#include <asm/imx-common/boot_mode.h>
> +#include <asm/imx-common/video.h>
> +#include <mmc.h>
> +#include <fsl_esdhc.h>
> +#include <miiphy.h>
> +#include <netdev.h>
> +#include <asm/arch/mxc_hdmi.h>
> +#include <asm/arch/crm_regs.h>
> +#include <asm/io.h>
> +#include <asm/arch/sys_proto.h>
> +#include <i2c.h>
> +#include <pwm.h>
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
> + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
> + PAD_CTL_HYS)
> +
> +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
> + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
> + PAD_CTL_SRE_FAST | PAD_CTL_HYS)
> +
> +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
> + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
> + PAD_CTL_SRE_FAST | PAD_CTL_HYS)
> +
> +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
> + PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
> +
> +#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
> + PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
> +
> +#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
> + PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
> +
> +#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
> + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
> +
> +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
> + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
> + PAD_CTL_ODE | PAD_CTL_SRE_FAST)
> +
> +#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
> +
> +int dram_init(void)
> +{
> + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
The right way on i.MX6 is using the imx_ddr_size() function. It reads
setup from the DDR controller.
gd->ram_size = imx_ddr_size();
> +
> + return 0;
> +}
> +
> +static iomux_v3_cfg_t const uart3_pads[] = {
> + MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
> + MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
> + MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
> + MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
> +};
> +
> +static iomux_v3_cfg_t const uart4_pads[] = {
> + MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
> + MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
> +};
> +
> +static iomux_v3_cfg_t const enet_pads[] = {
> + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
> + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
> + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
> + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
> + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
> + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
> + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
> + /* AR8033 PHY Reset */
> + MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
> +};
> +
> +static void setup_iomux_enet(void)
> +{
> + imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
> +
> + /* Reset AR8033 PHY */
> + gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
> + udelay(500);
> + gpio_set_value(IMX_GPIO_NR(1, 28), 1);
> +}
> +
> +static iomux_v3_cfg_t const usdhc2_pads[] = {
> + MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
> +};
> +
> +static iomux_v3_cfg_t const usdhc3_pads[] = {
> + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +};
> +
> +static iomux_v3_cfg_t const usdhc4_pads[] = {
> + MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
> + MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
> +};
> +
> +static iomux_v3_cfg_t const ecspi1_pads[] = {
> + MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
> + MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
> + MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
> + MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
> +};
> +
> +static struct i2c_pads_info i2c_pad_info1 = {
> + .scl = {
> + .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
> + .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD,
> + .gp = IMX_GPIO_NR(5, 27)
> + },
> + .sda = {
> + .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD,
> + .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD,
> + .gp = IMX_GPIO_NR(5, 26)
> + }
> +};
> +
> +static struct i2c_pads_info i2c_pad_info2 = {
> + .scl = {
> + .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
> + .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
> + .gp = IMX_GPIO_NR(4, 12)
> + },
> + .sda = {
> + .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
> + .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
> + .gp = IMX_GPIO_NR(4, 13)
> + }
> +};
> +
> +static struct i2c_pads_info i2c_pad_info3 = {
> + .scl = {
> + .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD,
> + .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD,
> + .gp = IMX_GPIO_NR(1, 3)
> + },
> + .sda = {
> + .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
> + .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
> + .gp = IMX_GPIO_NR(1, 6)
> + }
> +};
> +
> +#ifdef CONFIG_MXC_SPI
> +int board_spi_cs_gpio(unsigned bus, unsigned cs)
> +{
> + return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
> +}
> +
> +static void setup_spi(void)
> +{
> + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
> +}
> +#endif
> +
> +static iomux_v3_cfg_t const pcie_pads[] = {
> + MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
> + MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
> +};
> +
> +static void setup_pcie(void)
> +{
> + imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
> +}
> +
> +static void setup_iomux_uart(void)
> +{
> + imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
> + imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
> +}
> +
> +#ifdef CONFIG_FSL_ESDHC
> +struct fsl_esdhc_cfg usdhc_cfg[3] = {
> + {USDHC2_BASE_ADDR},
> + {USDHC3_BASE_ADDR},
> + {USDHC4_BASE_ADDR},
> +};
> +
> +#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
> +#define USDHC4_CD_GPIO IMX_GPIO_NR(6, 11)
> +
> +int board_mmc_getcd(struct mmc *mmc)
> +{
> + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
> + int ret = 0;
> +
> + switch (cfg->esdhc_base) {
> + case USDHC2_BASE_ADDR:
> + ret = !gpio_get_value(USDHC2_CD_GPIO);
> + break;
> + case USDHC3_BASE_ADDR:
> + ret = 1; /* eMMC is always present */
> + break;
> + case USDHC4_BASE_ADDR:
> + ret = !gpio_get_value(USDHC4_CD_GPIO);
> + break;
> + }
> +
> + return ret;
> +}
> +
> +int board_mmc_init(bd_t *bis)
> +{
> + int ret;
> + int i;
> +
> + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
> + switch (i) {
> + case 0:
> + imx_iomux_v3_setup_multiple_pads(
> + usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
> + gpio_direction_input(USDHC2_CD_GPIO);
> + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
> + break;
> + case 1:
> + imx_iomux_v3_setup_multiple_pads(
> + usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
> + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
> + break;
> + case 2:
> + imx_iomux_v3_setup_multiple_pads(
> + usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
> + gpio_direction_input(USDHC4_CD_GPIO);
> + usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
> + break;
> + default:
> + printf("Warning: you configured more USDHC controllers\n"
> + "(%d) then supported by the board (%d)\n",
> + i + 1, CONFIG_SYS_FSL_USDHC_NUM);
> + return -EINVAL;
> + }
> +
> + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> +}
> +#endif
> +
> +static int mx6_rgmii_rework(struct phy_device *phydev)
> +{
> + /* Configure AR8033 to ouput a 125MHz clk from CLK_25M */
> + /* set device address 0x7 */
Please fix multiline comments - this must be globally done.
> + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
> + /* offset 0x8016: CLK_25M Clock Select */
> + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
> + /* enable register write, no post increment, address 0x7 */
> + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
> + /* set to 125 MHz from local PLL source */
> + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);
> +
> + /* rgmii tx clock delay enable */
> + /* set debug port address: SerDes Test and System Mode Control */
> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
> + /* enable rgmii tx clock delay */
> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
> +
> + return 0;
> +}
> +
> +int board_phy_config(struct phy_device *phydev)
> +{
> + mx6_rgmii_rework(phydev);
> +
> + if (phydev->drv->config)
> + phydev->drv->config(phydev);
> +
> + return 0;
> +}
> +
> +#if defined(CONFIG_VIDEO_IPUV3)
> +static iomux_v3_cfg_t const backlight_pads[] = {
> + /* Power for LVDS Display */
> + MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
> +#define LVDS_POWER_GP IMX_GPIO_NR(3, 22)
> + /* Backlight enable for LVDS display */
> + MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
> +#define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0)
> + /* backlight PWM brightness control */
> + MX6_PAD_SD1_DAT3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
> +};
> +
> +static void do_enable_hdmi(struct display_info_t const *dev)
> +{
> + imx_enable_hdmi_phy();
> +}
> +
> +int board_cfb_skip(void)
> +{
> + gpio_direction_output(LVDS_POWER_GP, 1);
> +
> + return 0;
> +}
> +
> +static int detect_baseboard(struct display_info_t const *dev)
> +{
> + return 0 == dev->addr;
> +}
> +
> +struct display_info_t const displays[] = {{
> + .bus = -1,
> + .addr = 0,
> + .pixfmt = IPU_PIX_FMT_RGB24,
> + .detect = detect_baseboard,
> + .enable = NULL,
> + .mode = {
> + .name = "SHARP-LQ156M1LG21",
> + .refresh = 60,
> + .xres = 1920,
> + .yres = 1080,
> + .pixclock = 7851,
> + .left_margin = 100,
> + .right_margin = 40,
> + .upper_margin = 30,
> + .lower_margin = 3,
> + .hsync_len = 10,
> + .vsync_len = 2,
> + .sync = FB_SYNC_EXT,
> + .vmode = FB_VMODE_NONINTERLACED
> +} }, {
> + .bus = -1,
> + .addr = 3,
> + .pixfmt = IPU_PIX_FMT_RGB24,
> + .detect = detect_hdmi,
> + .enable = do_enable_hdmi,
> + .mode = {
> + .name = "HDMI",
> + .refresh = 60,
> + .xres = 1024,
> + .yres = 768,
> + .pixclock = 15385,
> + .left_margin = 220,
> + .right_margin = 40,
> + .upper_margin = 21,
> + .lower_margin = 7,
> + .hsync_len = 60,
> + .vsync_len = 10,
> + .sync = FB_SYNC_EXT,
> + .vmode = FB_VMODE_NONINTERLACED
> +} } };
> +size_t display_count = ARRAY_SIZE(displays);
> +
> +static void setup_display(void)
> +{
> + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
> + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
> +
> + clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
> +
> + imx_setup_hdmi();
> +
> + /* Set LDB_DI0 as clock source for IPU_DI0 */
> + clrsetbits_le32(&mxc_ccm->chsccdr,
> + MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
> + (CHSCCDR_CLK_SEL_LDB_DI0 <<
> + MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
> +
> + /* Turn on IPU LDB DI0 clocks */
> + setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
> +
> + enable_ipu_clock();
> +
> + writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
> + IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH |
> + IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
> + IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
> + IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
> + IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
> + IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
> + IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
> + IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
> + IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
> + &iomux->gpr[2]);
> +
> + clrsetbits_le32(&iomux->gpr[3],
> + IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
> + IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
> + IOMUXC_GPR3_HDMI_MUX_CTL_MASK,
> + (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
> + IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
> +
> + /* backlights off until needed */
> + imx_iomux_v3_setup_multiple_pads(backlight_pads,
> + ARRAY_SIZE(backlight_pads));
> +
> + gpio_direction_input(LVDS_POWER_GP);
> + gpio_direction_input(LVDS_BACKLIGHT_GP);
> +}
> +#endif /* CONFIG_VIDEO_IPUV3 */
> +
> +/*
> + * Do not overwrite the console
> + * Use always serial for U-Boot console
> + */
> +int overwrite_console(void)
> +{
> + return 1;
> +}
> +
> +int board_eth_init(bd_t *bis)
> +{
> + setup_iomux_enet();
> + setup_pcie();
> +
> + return cpu_eth_init(bis);
> +}
> +
> +static iomux_v3_cfg_t const misc_pads[] = {
> + MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
> + MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NC_PAD_CTRL),
> + MX6_PAD_EIM_CS0__GPIO2_IO23 | MUX_PAD_CTRL(NC_PAD_CTRL),
> + MX6_PAD_EIM_CS1__GPIO2_IO24 | MUX_PAD_CTRL(NC_PAD_CTRL),
> + MX6_PAD_EIM_OE__GPIO2_IO25 | MUX_PAD_CTRL(NC_PAD_CTRL),
> + MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NC_PAD_CTRL),
> + MX6_PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NC_PAD_CTRL),
> +};
> +#define SUS_S3_OUT IMX_GPIO_NR(4, 11)
> +#define WIFI_EN IMX_GPIO_NR(6, 14)
> +
> +int setup_ba16_sata(void)
> +{
> + struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
> + int ret;
> +
> + ret = enable_sata_clock();
> + if (ret)
> + return ret;
> +
> + clrsetbits_le32(&iomuxc_regs->gpr[13],
> + IOMUXC_GPR13_SATA_MASK,
> + IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
> + |IOMUXC_GPR13_SATA_PHY_7_SATA2M
> + |IOMUXC_GPR13_SATA_SPEED_3G
> + |(1<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
> + |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
> + |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_12_16
> + |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB
> + |IOMUXC_GPR13_SATA_PHY_2_TX_1P133V
> + |IOMUXC_GPR13_SATA_PHY_1_SLOW);
> +
> + return 0;
> +}
This function can be replaced by setup_sata()
> +
> +int board_early_init_f(void)
> +{
> + imx_iomux_v3_setup_multiple_pads(misc_pads,
> + ARRAY_SIZE(misc_pads));
> +
> + setup_iomux_uart();
> +
> +#if defined(CONFIG_VIDEO_IPUV3)
> + /* Set LDB clock to PLL2 PFD0 */
> + select_ldb_di_clock_source(MXC_PLL2_PFD0_CLK);
> +#endif
> + return 0;
> +}
> +
> +int board_init(void)
> +{
> + gpio_direction_output(SUS_S3_OUT, 1);
> + gpio_direction_output(WIFI_EN, 1);
> +#if defined(CONFIG_VIDEO_IPUV3)
> + setup_display();
> +#endif
> + /* address of boot parameters */
> + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
> +
> +#ifdef CONFIG_MXC_SPI
> + setup_spi();
> +#endif
> + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
> + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
> + setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
> +
> + return 0;
> +}
> +
> +#ifdef CONFIG_CMD_BMODE
> +static const struct boot_mode board_boot_modes[] = {
> + /* 4 bit bus width */
> + {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
> + {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
> + {NULL, 0},
> +};
> +#endif
> +
> +int board_late_init(void)
> +{
> +#ifdef CONFIG_CMD_BMODE
> + add_board_boot_modes(board_boot_modes);
> +#endif
> + /* We need at least 200ms between power on and backlight on
> + * as per specifications from CHI MEI */
> + mdelay(250);
> +
> + /* enable backlight PWM 1 */
> + pwm_init(0, 0, 0);
> +
> + /* duty cycle 5000000ns, period: 5000000ns */
> + pwm_config(0, 5000000, 5000000);
> +
> + /* Backlight Power */
> + gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
> +
> + pwm_enable(0);
> +
> +#ifdef CONFIG_CMD_SATA
> + setup_ba16_sata();
> +#endif
> +
> + return 0;
> +}
> +
> +int checkboard(void)
> +{
> + printf("BOARD: %s\n", CONFIG_BOARD_NAME);
> + return 0;
> +}
> diff --git a/configs/dms-ba16-1g_defconfig b/configs/dms-ba16-1g_defconfig
> new file mode 100644
> index 0000000..f9d227a
> --- /dev/null
> +++ b/configs/dms-ba16-1g_defconfig
> @@ -0,0 +1,27 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_MX6=y
> +CONFIG_TARGET_ADVANTECH_DMS_BA16=y
> +CONFIG_SYS_DDR_1G=y
> +CONFIG_HUSH_PARSER=y
> +CONFIG_BOOTDELAY=1
> +CONFIG_CMD_BOOTZ=y
> +# CONFIG_CMD_IMLS is not set
> +# CONFIG_CMD_FLASH is not set
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_SF=y
> +CONFIG_CMD_I2C=y
> +CONFIG_CMD_USB=y
> +CONFIG_CMD_USB_MASS_STORAGE=y
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_DHCP=y
> +CONFIG_CMD_MII=y
> +CONFIG_CMD_PING=y
> +CONFIG_CMD_CACHE=y
> +CONFIG_CMD_EXT2=y
> +CONFIG_CMD_EXT4=y
> +CONFIG_CMD_EXT4_WRITE=y
> +CONFIG_CMD_FAT=y
> +CONFIG_CMD_FS_GENERIC=y
> +CONFIG_SPI_FLASH=y
> +CONFIG_SPI_FLASH_STMICRO=y
> +CONFIG_OF_LIBFDT=y
> diff --git a/configs/dms-ba16_defconfig b/configs/dms-ba16_defconfig
> new file mode 100644
> index 0000000..541f47a
> --- /dev/null
> +++ b/configs/dms-ba16_defconfig
> @@ -0,0 +1,26 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_MX6=y
> +CONFIG_TARGET_ADVANTECH_DMS_BA16=y
> +CONFIG_HUSH_PARSER=y
> +CONFIG_BOOTDELAY=1
> +CONFIG_CMD_BOOTZ=y
> +# CONFIG_CMD_IMLS is not set
> +# CONFIG_CMD_FLASH is not set
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_SF=y
> +CONFIG_CMD_I2C=y
> +CONFIG_CMD_USB=y
> +CONFIG_CMD_USB_MASS_STORAGE=y
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_DHCP=y
> +CONFIG_CMD_MII=y
> +CONFIG_CMD_PING=y
> +CONFIG_CMD_CACHE=y
> +CONFIG_CMD_EXT2=y
> +CONFIG_CMD_EXT4=y
> +CONFIG_CMD_EXT4_WRITE=y
> +CONFIG_CMD_FAT=y
> +CONFIG_CMD_FS_GENERIC=y
> +CONFIG_SPI_FLASH=y
> +CONFIG_SPI_FLASH_STMICRO=y
> +CONFIG_OF_LIBFDT=y
Well, if you use SPL you can have most probably have a single binary
running on both boards. I see advantages to have it - why not ?
> diff --git a/include/configs/advantech_dms-ba16.h b/include/configs/advantech_dms-ba16.h
> new file mode 100644
> index 0000000..900e707
> --- /dev/null
> +++ b/include/configs/advantech_dms-ba16.h
> @@ -0,0 +1,329 @@
> +/*
> + * Copyright (C) 2016 Timesys Corporation
> + * Copyright (C) 2016 Advantech Corporation
> + * Copyright (C) 2012 Freescale Semiconductor, Inc.
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#ifndef __ADVANTECH_DMSBA16_CONFIG_H
> +#define __ADVANTECH_DMSBA16_CONFIG_H
> +
> +#include <asm/arch/imx-regs.h>
> +#include <asm/imx-common/gpio.h>
> +
> +#define CONFIG_BOARD_NAME "Advantech DMS-BA16"
> +#define CONFIG_DEFAULT_FDT_FILE "imx6q-dms-ba16.dtb"
> +
> +#define CONFIG_MXC_UART_BASE UART4_BASE
> +#define CONFIG_CONSOLE_DEV "ttymxc3"
> +#define CONFIG_EXTRA_BOOTARGS "panic=10"
> +
> +#define CONFIG_BOOT_DIR ""
> +#define CONFIG_LOADCMD "fatload"
> +#define CONFIG_RFSPART "2"
> +
> +#ifdef CONFIG_SYS_DDR_1G
> +#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
> +#else
> +#define PHYS_SDRAM_SIZE (2u * 1024 * 1024 * 1024)
> +#endif
> +
> +#define CONFIG_SUPPORT_EMMC_BOOT
> +
> +#include "mx6_common.h"
> +#include <linux/sizes.h>
> +
> +#define CONFIG_DISPLAY_CPUINFO
> +#define CONFIG_DISPLAY_BOARDINFO
> +
> +#define CONFIG_CMDLINE_TAG
> +#define CONFIG_SETUP_MEMORY_TAGS
> +#define CONFIG_INITRD_TAG
> +#define CONFIG_REVISION_TAG
> +#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
> +
> +#define CONFIG_BOARD_EARLY_INIT_F
> +#define CONFIG_BOARD_LATE_INIT
> +
> +#define CONFIG_MXC_GPIO
> +#define CONFIG_MXC_UART
> +
> +#define CONFIG_CMD_FUSE
> +#define CONFIG_MXC_OCOTP
> +
> +/* SATA Configs */
> +#define CONFIG_CMD_SATA
> +#define CONFIG_DWC_AHSATA
> +#define CONFIG_SYS_SATA_MAX_DEVICE 1
> +#define CONFIG_DWC_AHSATA_PORT_ID 0
> +#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
> +#define CONFIG_LBA48
> +#define CONFIG_LIBATA
> +
> +/* MMC Configs */
> +#define CONFIG_FSL_ESDHC
> +#define CONFIG_FSL_USDHC
> +#define CONFIG_SYS_FSL_ESDHC_ADDR 0
> +#define CONFIG_MMC
> +#define CONFIG_GENERIC_MMC
> +#define CONFIG_BOUNCE_BUFFER
> +#define CONFIG_DOS_PARTITION
> +
> +/* USB Configs */
> +#define CONFIG_USB_EHCI
> +#define CONFIG_USB_EHCI_MX6
> +#define CONFIG_USB_STORAGE
> +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
> +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
> +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
> +#define CONFIG_MXC_USB_FLAGS 0
> +#define CONFIG_USB_KEYBOARD
> +#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
> +
> +#define CONFIG_CI_UDC
> +#define CONFIG_USBD_HS
> +#define CONFIG_USB_GADGET_DUALSPEED
> +#define CONFIG_USB_GADGET
> +#define CONFIG_USB_GADGET_DOWNLOAD
> +#define CONFIG_USB_GADGET_MASS_STORAGE
> +#define CONFIG_USB_FUNCTION_MASS_STORAGE
> +#define CONFIG_USB_GADGET_VBUS_DRAW 2
> +#define CONFIG_G_DNL_VENDOR_NUM 0x0525
> +#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5
> +#define CONFIG_G_DNL_MANUFACTURER "Advantech"
You have to check the setup with current status of CONFIG_ moved to
Kconfig. All USB gadget stuff is in Kconfig, and you do not have to set
it here.
> +
> +/* Networking Configs */
> +#define CONFIG_FEC_MXC
> +#define CONFIG_MII
> +#define IMX_FEC_BASE ENET_BASE_ADDR
> +#define CONFIG_FEC_XCV_TYPE RGMII
> +#define CONFIG_ETHPRIME "FEC"
> +#define CONFIG_FEC_MXC_PHYADDR 4
> +#define CONFIG_PHYLIB
> +#define CONFIG_PHY_ATHEROS
> +
> +/* Serial Flash */
> +#ifdef CONFIG_CMD_SF
> +#define CONFIG_MXC_SPI
> +#define CONFIG_SF_DEFAULT_BUS 0
> +#define CONFIG_SF_DEFAULT_CS 0
> +#define CONFIG_SF_DEFAULT_SPEED 20000000
> +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
> +#endif
> +
> +/* allow to overwrite serial and ethaddr */
> +#define CONFIG_ENV_OVERWRITE
> +#define CONFIG_CONS_INDEX 1
> +#define CONFIG_BAUDRATE 115200
> +
> +/* Command definition */
> +#define CONFIG_CMD_BMODE
> +
> +#define CONFIG_LOADADDR 0x12000000
> +#define CONFIG_SYS_TEXT_BASE 0x17800000
> +
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + "script=boot.scr\0" \
> + "image=" CONFIG_BOOT_DIR "/uImage\0" \
> + "uboot=u-boot.imx\0" \
> + "fdt_file=" CONFIG_BOOT_DIR "/" CONFIG_DEFAULT_FDT_FILE "\0" \
> + "fdt_addr=0x18000000\0" \
> + "boot_fdt=yes\0" \
> + "ip_dyn=yes\0" \
> + "console=" CONFIG_CONSOLE_DEV "\0" \
> + "fdt_high=0xffffffff\0" \
> + "initrd_high=0xffffffff\0" \
> + "sddev=0\0" \
> + "emmcdev=1\0" \
> + "partnum=1\0" \
> + "loadcmd=" CONFIG_LOADCMD "\0" \
> + "rfspart=" CONFIG_RFSPART "\0" \
> + "update_sd_firmware=" \
> + "if test ${ip_dyn} = yes; then " \
> + "setenv get_cmd dhcp; " \
> + "else " \
> + "setenv get_cmd tftp; " \
> + "fi; " \
> + "if mmc dev ${mmcdev}; then " \
> + "if ${get_cmd} ${update_sd_firmware_filename}; then " \
> + "setexpr fw_sz ${filesize} / 0x200; " \
> + "setexpr fw_sz ${fw_sz} + 1; " \
> + "mmc write ${loadaddr} 0x2 ${fw_sz}; " \
> + "fi; " \
> + "fi\0" \
> + "update_sf_uboot=" \
> + "if tftp $loadaddr $uboot; then " \
> + "sf probe; " \
> + "sf erase 0 0xC0000; " \
> + "sf write $loadaddr 0x400 $filesize; " \
> + "echo 'U-Boot upgraded. Please reset'; " \
> + "fi\0" \
> + "setargs=setenv bootargs console=${console},${baudrate} " \
> + "root=/dev/${rootdev} rw rootwait " CONFIG_EXTRA_BOOTARGS "\0" \
> + "loadbootscript=" \
> + "${loadcmd} ${dev} ${devnum}:${partnum} ${loadaddr} ${script};\0" \
> + "bootscript=echo Running bootscript from ${dev}:${devnum}:${partnum};" \
> + " source\0" \
> + "loadimage=" \
> + "${loadcmd} ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \
> + "loadfdt=${loadcmd} ${dev} ${devnum}:${partnum} ${fdt_addr} ${fdt_file}\0" \
> + "tryboot=" \
> + "if run loadbootscript; then " \
> + "run bootscript; " \
> + "else " \
> + "if run loadimage; then " \
> + "run doboot; " \
> + "fi; " \
> + "fi;\0" \
> + "doboot=echo Booting from ${dev}:${devnum}:${partnum} ...; " \
> + "run setargs; " \
> + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
> + "if run loadfdt; then " \
> + "bootm ${loadaddr} - ${fdt_addr}; " \
> + "else " \
> + "if test ${boot_fdt} = try; then " \
> + "bootm; " \
> + "else " \
> + "echo WARN: Cannot load the DT; " \
> + "fi; " \
> + "fi; " \
> + "else " \
> + "bootm; " \
> + "fi;\0" \
> + "netargs=setenv bootargs console=${console},${baudrate} " \
> + "root=/dev/nfs " \
> + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
> + "netboot=echo Booting from net ...; " \
> + "run netargs; " \
> + "if test ${ip_dyn} = yes; then " \
> + "setenv get_cmd dhcp; " \
> + "else " \
> + "setenv get_cmd tftp; " \
> + "fi; " \
> + "${get_cmd} ${image}; " \
> + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
> + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
> + "bootm ${loadaddr} - ${fdt_addr}; " \
> + "else " \
> + "if test ${boot_fdt} = try; then " \
> + "bootm; " \
> + "else " \
> + "echo WARN: Cannot load the DT; " \
> + "fi; " \
> + "fi; " \
> + "else " \
> + "bootm; " \
> + "fi;\0" \
> +
> +#define CONFIG_BOOTCOMMAND \
> + "usb start; " \
> + "setenv dev usb; " \
> + "setenv devnum 0; " \
> + "setenv rootdev sda${rfspart}; " \
> + "run tryboot; " \
> + \
> + "setenv dev mmc; " \
> + "setenv rootdev mmcblk0p${rfspart}; " \
> + \
> + "setenv devnum ${sddev}; " \
> + "if mmc dev ${devnum}; then " \
> + "run tryboot; " \
> + "setenv rootdev mmcblk1p${rfspart}; " \
> + "fi; " \
> + \
> + "setenv devnum ${emmcdev}; " \
> + "if mmc dev ${devnum}; then " \
> + "run tryboot; " \
> + "fi; " \
> + \
> + "bmode usb; " \
> +
> +#define CONFIG_ARP_TIMEOUT 200UL
> +
> +/* Miscellaneous configurable options */
> +#define CONFIG_SYS_LONGHELP
> +#define CONFIG_AUTO_COMPLETE
> +
> +/* Print Buffer Size */
> +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
> +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
> +
> +#define CONFIG_SYS_MEMTEST_START 0x10000000
> +#define CONFIG_SYS_MEMTEST_END 0x10010000
> +#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
> +
> +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
> +
> +#define CONFIG_CMDLINE_EDITING
> +#define CONFIG_STACKSIZE (128 * 1024)
> +
> +/* Physical Memory Map */
> +#define CONFIG_NR_DRAM_BANKS 1
> +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
> +
> +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
> +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
> +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
> +
> +#define CONFIG_SYS_INIT_SP_OFFSET \
> + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> +#define CONFIG_SYS_INIT_SP_ADDR \
> + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
> +
> +/* FLASH and environment organization */
> +#define CONFIG_SYS_NO_FLASH
> +
> +#define CONFIG_ENV_IS_IN_SPI_FLASH
> +#define CONFIG_ENV_SIZE (8 * 1024)
> +#define CONFIG_ENV_OFFSET (768 * 1024)
> +#define CONFIG_ENV_SECT_SIZE (64 * 1024)
> +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
> +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
> +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
> +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
> +
Am I missing something ? Where is SPI-NOR ?
> +#ifndef CONFIG_SYS_DCACHE_OFF
> +#endif
> +
> +#define CONFIG_SYS_FSL_USDHC_NUM 3
> +
> +/* Framebuffer */
> +#define CONFIG_VIDEO
> +#define CONFIG_VIDEO_IPUV3
> +#define CONFIG_CFB_CONSOLE
> +#define CONFIG_VGA_AS_SINGLE_DEVICE
> +#define CONFIG_SYS_CONSOLE_IS_IN_ENV
> +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
> +#define CONFIG_VIDEO_BMP_RLE8
> +#define CONFIG_SPLASH_SCREEN
> +#define CONFIG_SPLASH_SCREEN_ALIGN
> +#define CONFIG_BMP_16BPP
> +#define CONFIG_VIDEO_LOGO
> +#define CONFIG_VIDEO_BMP_LOGO
> +#define CONFIG_IPUV3_CLK 260000000
> +#define CONFIG_IMX_HDMI
> +#define CONFIG_IMX_VIDEO_SKIP
> +
> +#define CONFIG_PWM_IMX
> +#define CONFIG_IMX6_PWM_PER_CLK 66000000
> +
> +#undef CONFIG_CMD_PCI
> +#ifdef CONFIG_CMD_PCI
> +#define CONFIG_PCI
> +#define CONFIG_PCI_PNP
> +#define CONFIG_PCI_SCAN_SHOW
> +#define CONFIG_PCIE_IMX
> +#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12)
> +#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(1, 5)
> +#endif
> +
> +/* I2C Configs */
> +#define CONFIG_SYS_I2C
> +#define CONFIG_SYS_I2C_MXC
> +#define CONFIG_SYS_I2C_SPEED 100000
> +#define CONFIG_SYS_I2C_MXC_I2C1
> +#define CONFIG_SYS_I2C_MXC_I2C2
> +#define CONFIG_SYS_I2C_MXC_I2C3
> +
> +#endif /* __ADVANTECH_DMSBA16_CONFIG_H */
>
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2016-07-12 17:16 Joe Hershberger
0 siblings, 0 replies; 430+ messages in thread
From: Joe Hershberger @ 2016-07-12 17:16 UTC (permalink / raw)
To: u-boot
Hi ,
https://patchwork.ozlabs.org/patch/e4ead4a/ was applied to u-boot-net.git.
Thanks!
-Joe
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2016-07-12 17:16 Joe Hershberger
0 siblings, 0 replies; 430+ messages in thread
From: Joe Hershberger @ 2016-07-12 17:16 UTC (permalink / raw)
To: u-boot
Hi ,
https://patchwork.ozlabs.org/patch/4c64c4d/ was applied to u-boot-net.git.
Thanks!
-Joe
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2016-07-12 17:16 Joe Hershberger
0 siblings, 0 replies; 430+ messages in thread
From: Joe Hershberger @ 2016-07-12 17:16 UTC (permalink / raw)
To: u-boot
Hi ,
https://patchwork.ozlabs.org/patch/66d027e/ was applied to u-boot-net.git.
Thanks!
-Joe
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2016-07-12 17:16 Joe Hershberger
0 siblings, 0 replies; 430+ messages in thread
From: Joe Hershberger @ 2016-07-12 17:16 UTC (permalink / raw)
To: u-boot
Hi ,
https://patchwork.ozlabs.org/patch/19c9dda/ was applied to u-boot-net.git.
Thanks!
-Joe
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2016-07-12 17:16 Joe Hershberger
0 siblings, 0 replies; 430+ messages in thread
From: Joe Hershberger @ 2016-07-12 17:16 UTC (permalink / raw)
To: u-boot
Hi ,
https://patchwork.ozlabs.org/patch/2307ea4/ was applied to u-boot-net.git.
Thanks!
-Joe
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2016-06-17 10:00 [U-Boot] [RFC] omap3: single binary supporting all flash types Ladislav Michl
2016-06-17 10:07 ` [U-Boot] (no subject) Ladislav Michl
@ 2016-06-17 10:09 ` Ladislav Michl
1 sibling, 0 replies; 430+ messages in thread
From: Ladislav Michl @ 2016-06-17 10:09 UTC (permalink / raw)
To: u-boot
Add timeout to onenand_wait ready loop as it hangs here indefinitely
when chip not present. Once there, do the same for onenand_bbt_wait
as well (note: recent Linux driver code does the same)
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
---
drivers/mtd/onenand/onenand_base.c | 30 +++++++++++++++++++-----------
1 file changed, 19 insertions(+), 11 deletions(-)
diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c
index 03deabc..d194d97 100644
--- a/drivers/mtd/onenand/onenand_base.c
+++ b/drivers/mtd/onenand/onenand_base.c
@@ -20,6 +20,7 @@
*/
#include <common.h>
+#include <watchdog.h>
#include <linux/compat.h>
#include <linux/mtd/mtd.h>
#include "linux/mtd/flashchip.h"
@@ -467,15 +468,18 @@ static int onenand_read_ecc(struct onenand_chip *this)
static int onenand_wait(struct mtd_info *mtd, int state)
{
struct onenand_chip *this = mtd->priv;
- unsigned int flags = ONENAND_INT_MASTER;
unsigned int interrupt = 0;
unsigned int ctrl;
- while (1) {
+ /* Wait at most 20ms ... */
+ u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
+ u32 time_start = get_timer(0);
+ do {
+ WATCHDOG_RESET();
+ if (get_timer(time_start) > timeo)
+ return -EIO;
interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT);
- if (interrupt & flags)
- break;
- }
+ } while ((interrupt & ONENAND_INT_MASTER) == 0);
ctrl = this->read_word(this->base + ONENAND_REG_CTRL_STATUS);
@@ -1154,15 +1158,18 @@ int onenand_read_oob(struct mtd_info *mtd, loff_t from,
static int onenand_bbt_wait(struct mtd_info *mtd, int state)
{
struct onenand_chip *this = mtd->priv;
- unsigned int flags = ONENAND_INT_MASTER;
unsigned int interrupt;
unsigned int ctrl;
- while (1) {
+ /* Wait at most 20ms ... */
+ u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
+ u32 time_start = get_timer(0);
+ do {
+ WATCHDOG_RESET();
+ if (get_timer(time_start) > timeo)
+ return ONENAND_BBT_READ_FATAL_ERROR;
interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT);
- if (interrupt & flags)
- break;
- }
+ } while ((interrupt & ONENAND_INT_MASTER) == 0);
/* To get correct interrupt status in timeout case */
interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT);
@@ -2536,7 +2543,8 @@ static int onenand_chip_probe(struct mtd_info *mtd)
this->write_word(ONENAND_CMD_RESET, this->base + ONENAND_BOOTRAM);
/* Wait reset */
- this->wait(mtd, FL_RESETING);
+ if (this->wait(mtd, FL_RESETING))
+ return -ENXIO;
/* Restore system configuration 1 */
this->write_word(syscfg, this->base + ONENAND_REG_SYS_CFG1);
--
2.1.4
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2016-06-17 10:00 [U-Boot] [RFC] omap3: single binary supporting all flash types Ladislav Michl
@ 2016-06-17 10:07 ` Ladislav Michl
2016-06-17 10:09 ` Ladislav Michl
1 sibling, 0 replies; 430+ messages in thread
From: Ladislav Michl @ 2016-06-17 10:07 UTC (permalink / raw)
To: u-boot
Use newly introduced function. As it depends on previous RFC, lets turn
in into proper patch once beforementioned problems are solved
---
arch/arm/cpu/armv7/omap3/spl_id_nand.c | 33 ++++++++++-----------------------
1 file changed, 10 insertions(+), 23 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap3/spl_id_nand.c b/arch/arm/cpu/armv7/omap3/spl_id_nand.c
index 26d3aa4..0bf76fe 100644
--- a/arch/arm/cpu/armv7/omap3/spl_id_nand.c
+++ b/arch/arm/cpu/armv7/omap3/spl_id_nand.c
@@ -18,7 +18,7 @@
#include <asm/arch/sys_proto.h>
#include <asm/arch/mem.h>
-static struct gpmc *gpmc_config = (struct gpmc *)GPMC_BASE;
+extern const struct gpmc *gpmc_cfg;
/*
* Many boards will want to know the results of the NAND_CMD_READID command
@@ -31,40 +31,27 @@ int identify_nand_chip(int *mfr, int *id)
int loops = 1000;
/* Make sure that we have setup GPMC for NAND correctly. */
- writel(M_NAND_GPMC_CONFIG1, &gpmc_config->cs[0].config1);
- writel(M_NAND_GPMC_CONFIG2, &gpmc_config->cs[0].config2);
- writel(M_NAND_GPMC_CONFIG3, &gpmc_config->cs[0].config3);
- writel(M_NAND_GPMC_CONFIG4, &gpmc_config->cs[0].config4);
- writel(M_NAND_GPMC_CONFIG5, &gpmc_config->cs[0].config5);
- writel(M_NAND_GPMC_CONFIG6, &gpmc_config->cs[0].config6);
-
- /*
- * Enable the config. The CS size goes in bits 11:8. We set
- * bit 6 to enable the CS and the base address goes into bits 5:0.
- */
- writel((GPMC_SIZE_128M << 8) | (GPMC_CS_ENABLE << 6) |
- ((NAND_BASE >> 24) & GPMC_BASEADDR_MASK),
- &gpmc_config->cs[0].config7);
+ set_gpmc_cs0(1);
sdelay(2000);
/* Issue a RESET and then READID */
- writeb(NAND_CMD_RESET, &gpmc_config->cs[0].nand_cmd);
- writeb(NAND_CMD_STATUS, &gpmc_config->cs[0].nand_cmd);
- while ((readl(&gpmc_config->cs[0].nand_dat) & NAND_STATUS_READY)
- != NAND_STATUS_READY) {
+ writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd);
+ writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd);
+ while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY)
+ != NAND_STATUS_READY) {
sdelay(100);
if (--loops == 0)
return 1;
}
- writeb(NAND_CMD_READID, &gpmc_config->cs[0].nand_cmd);
+ writeb(NAND_CMD_READID, &gpmc_cfg->cs[0].nand_cmd);
/* Set the address to read to 0x0 */
- writeb(0x0, &gpmc_config->cs[0].nand_adr);
+ writeb(0x0, &gpmc_cfg->cs[0].nand_adr);
/* Read off the manufacturer and device id. */
- *mfr = readb(&gpmc_config->cs[0].nand_dat);
- *id = readb(&gpmc_config->cs[0].nand_dat);
+ *mfr = readb(&gpmc_cfg->cs[0].nand_dat);
+ *id = readb(&gpmc_cfg->cs[0].nand_dat);
return 0;
}
--
2.1.4
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2016-02-03 12:42 Peter Robinson
0 siblings, 0 replies; 430+ messages in thread
From: Peter Robinson @ 2016-02-03 12:42 UTC (permalink / raw)
To: u-boot
Hi All,
Here's a couple of patches to help building on gcc-6. We're rebasing Fedora to gcc-6 for Fedora 24 so this was the first build I've attempted with it. It doesn't fix all problems as I also see an issue that the generated/generic-asm-offsets.h isn't generated early enough in the build process but I couldn't quite work out how to move the generation of that earlier in the process. Full logs of that at the link below.
Cheers,
Peter
https://kojipkgs.fedoraproject.org//work/tasks/1747/12801747/build.log
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2016-01-20 12:25 Wenbin Song
0 siblings, 0 replies; 430+ messages in thread
From: Wenbin Song @ 2016-01-20 12:25 UTC (permalink / raw)
To: u-boot
These patches depend on the series patches(http://patchwork.ozlabs.org/patch/567250/).
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2015-12-09 7:15 Peter Robinson
0 siblings, 0 replies; 430+ messages in thread
From: Peter Robinson @ 2015-12-09 7:15 UTC (permalink / raw)
To: u-boot
In Fedora with gcc 5.2 and 5.3 the fw_env is FTB due to a missing include.
The following small patch fixes building it on Fedora with gcc 5.3.1
Regards,
Peter
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2015-11-17 12:16 wd at denx.de
0 siblings, 0 replies; 430+ messages in thread
From: wd at denx.de @ 2015-11-17 12:16 UTC (permalink / raw)
To: u-boot
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2015-07-10 13:16 Samuel Egli
0 siblings, 0 replies; 430+ messages in thread
From: Samuel Egli @ 2015-07-10 13:16 UTC (permalink / raw)
To: u-boot
Hi all,
this is a re-submission of Bin Liu's patch that was
reverted by the commit 16b61d13bab361853564da401b15fc34ae1dfea7
from Daniel Mack.
It is not OK to set the MUSB_POWER_HSENAB unconditionally because
there are sometimes some HW limitations that allow only FULL SPEED.
In our case we have some bad wiring protection in our USB circuit
that acts as a filter an will not allow signals to pass that
are faster than FULL SPEED.
I suggest to use CONFIG_USB_GADGET_DUALSPEED define to enable
HIGH SPEED as it was done previously, which is by default
enabled.
Kind regards
Sam
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2014-09-12 20:00 ` Michael Trimarchi
@ 2014-09-15 8:08 ` Michael Trimarchi
0 siblings, 0 replies; 430+ messages in thread
From: Michael Trimarchi @ 2014-09-15 8:08 UTC (permalink / raw)
To: u-boot
Hi
On Fri, Sep 12, 2014 at 10:00 PM, Michael Trimarchi
<michael@amarulasolutions.com> wrote:
> Hi
>
> Il 12/set/2014 21:53 "Mariusz Boguszewski" <Mariusz.Boguszewski@csr.com> ha
> scritto:
>>
>> Hello,
>> I need to get this new version of u-boot for my PandaBoard A6 rev.
>> I tried Linaro release 14.08 from July 2014 but all I get is the error:
>>
>> U-Boot SPL 2013.01.-rc1-g43ee87a (May 25 2014 - 07:45:31)
>> OMAP4430 ES2.3
>> SDRAM: identified size not same as expected size identified: 0 expected:
>> 40000000
>>
>
> Try to enable auto detection
>
Just comment this
/* Defines for SDRAM init */
#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
#endif
Michael
> Michael
>
>> Is this fix applied to u-boot, and where can I get it ?
>>
>> Regards.
>>
>>
>>
>>
>>
>> Member of the CSR plc group of companies. CSR plc registered in England
>> and Wales, registered number 4187346, registered office Churchill House,
>> Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
>> More information can be found at www.csr.com. Keep up to date with CSR on
>> our technical blog, www.csr.com/blog, CSR people blog, www.csr.com/people,
>> YouTube, www.youtube.com/user/CSRplc, Facebook,
>> www.facebook.com/pages/CSR/191038434253534, or follow us on Twitter at
>> www.twitter.com/CSR_plc.
>> New for 2014, you can now access the wide range of products powered by
>> aptX at www.aptx.com.
>>
>> _______________________________________________
>> U-Boot mailing list
>> U-Boot at lists.denx.de
>> http://lists.denx.de/mailman/listinfo/u-boot
>>
--
| Michael Nazzareno Trimarchi Amarula Solutions BV |
| COO - Founder Cruquiuskade 47 |
| +31(0)851119172 Amsterdam 1018 AM NL |
| [`as] http://www.amarulasolutions.com |
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2014-09-12 14:45 Mariusz Boguszewski
@ 2014-09-12 20:00 ` Michael Trimarchi
2014-09-15 8:08 ` Michael Trimarchi
0 siblings, 1 reply; 430+ messages in thread
From: Michael Trimarchi @ 2014-09-12 20:00 UTC (permalink / raw)
To: u-boot
Hi
Il 12/set/2014 21:53 "Mariusz Boguszewski" <Mariusz.Boguszewski@csr.com> ha
scritto:
>
> Hello,
> I need to get this new version of u-boot for my PandaBoard A6 rev.
> I tried Linaro release 14.08 from July 2014 but all I get is the error:
>
> U-Boot SPL 2013.01.-rc1-g43ee87a (May 25 2014 - 07:45:31)
> OMAP4430 ES2.3
> SDRAM: identified size not same as expected size identified: 0 expected:
40000000
>
Try to enable auto detection
Michael
> Is this fix applied to u-boot, and where can I get it ?
>
> Regards.
>
>
>
>
>
> Member of the CSR plc group of companies. CSR plc registered in England
and Wales, registered number 4187346, registered office Churchill House,
Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
> More information can be found at www.csr.com. Keep up to date with CSR on
our technical blog, www.csr.com/blog, CSR people blog, www.csr.com/people,
YouTube, www.youtube.com/user/CSRplc, Facebook,
www.facebook.com/pages/CSR/191038434253534, or follow us on Twitter at
www.twitter.com/CSR_plc.
> New for 2014, you can now access the wide range of products powered by
aptX at www.aptx.com.
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
>
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2014-09-12 14:45 Mariusz Boguszewski
2014-09-12 20:00 ` Michael Trimarchi
0 siblings, 1 reply; 430+ messages in thread
From: Mariusz Boguszewski @ 2014-09-12 14:45 UTC (permalink / raw)
To: u-boot
Hello,
I need to get this new version of u-boot for my PandaBoard A6 rev.
I tried Linaro release 14.08 from July 2014 but all I get is the error:
U-Boot SPL 2013.01.-rc1-g43ee87a (May 25 2014 - 07:45:31)
OMAP4430 ES2.3
SDRAM: identified size not same as expected size identified: 0 expected: 40000000
Is this fix applied to u-boot, and where can I get it ?
Regards.
Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
More information can be found at www.csr.com. Keep up to date with CSR on our technical blog, www.csr.com/blog, CSR people blog, www.csr.com/people, YouTube, www.youtube.com/user/CSRplc, Facebook, www.facebook.com/pages/CSR/191038434253534, or follow us on Twitter at www.twitter.com/CSR_plc.
New for 2014, you can now access the wide range of products powered by aptX at www.aptx.com.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2014-06-03 0:04 rajshekar_py at yahoo.com
0 siblings, 0 replies; 430+ messages in thread
From: rajshekar_py at yahoo.com @ 2014-06-03 0:04 UTC (permalink / raw)
To: u-boot
Hi! http://netreign.com/_redirect?wynymaq917558
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2014-02-11 19:20 John de la Garza
0 siblings, 0 replies; 430+ messages in thread
From: John de la Garza @ 2014-02-11 19:20 UTC (permalink / raw)
To: u-boot
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2013-11-21 15:20 ` Bojan Buić
@ 2013-11-22 7:04 ` Wolfgang Denk
0 siblings, 0 replies; 430+ messages in thread
From: Wolfgang Denk @ 2013-11-22 7:04 UTC (permalink / raw)
To: u-boot
Dear Bojan,
In message <CAP8r_=A-vSHTfcbyUeaZfM2Z8=q_-AEMqaaiasPo=kVU5GkfwA@mail.gmail.com> you wrote:
>
> I found address of register HW_RTC_WATCHDOG_SET: 0x8005C054
>
> I need write to that register value 0x054 ?
Please don't expect others doing the work for you. Stefano already
pointed you to the right section of the manual, so please invest your
own time and efforts to read it and to figure out what needs to be
done.
If you can't figure out what needs to be done, you might consider
hiring an expert.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Real programmers can write assembly code in any language. :-)
- Larry Wall in <8571@jpl-devvax.JPL.NASA.GOV>
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2013-11-21 15:08 ` Bojan Buić
@ 2013-11-21 15:20 ` Bojan Buić
2013-11-22 7:04 ` Wolfgang Denk
0 siblings, 1 reply; 430+ messages in thread
From: Bojan Buić @ 2013-11-21 15:20 UTC (permalink / raw)
To: u-boot
I found address of register HW_RTC_WATCHDOG_SET: 0x8005C054
I need write to that register value 0x054 ?
Bojan
2013/11/21 Bojan Bui? <bojan.buic@gmail.com>
> Sorry for many questions, but I work once with 8 bit ATmega 8
> microcontroler and nothing more :(
>
> In manual I found this :
>
> HW_RTC_WATCHDOG 0x050
> HW_RTC_WATCHDOG_SET 0x054
> HW_RTC_WATCHDOG_CLR 0x058
> HW_RTC_WATCHDOG_TOG 0x05C
>
>
> and now I do not know which register i need setup to enable watchdog ?
> 0x054? Which value i need write to that register ?
>
> Bojan
>
>
>
> 2013/11/21 Stefano Babic <sbabic@denx.de>
>
>> On 21/11/2013 15:01, Bojan Bui? wrote:
>> > Which register I need set up for hard. watchdog ?
>> >
>>
>> Please read carefully Chapter 23 amn 23.8.6 in the User Manuaal, you
>> will find answer to all your question.
>>
>> Best regards,
>> Stefano Babic
>>
>> --
>> =====================================================================
>> DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
>> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
>> Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
>> =====================================================================
>>
>
>
>
> --
> Bojan Bui?
>
>
>
--
Bojan Bui?
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2013-11-21 14:40 ` Stefano Babic
@ 2013-11-21 15:08 ` Bojan Buić
2013-11-21 15:20 ` Bojan Buić
0 siblings, 1 reply; 430+ messages in thread
From: Bojan Buić @ 2013-11-21 15:08 UTC (permalink / raw)
To: u-boot
Sorry for many questions, but I work once with 8 bit ATmega 8
microcontroler and nothing more :(
In manual I found this :
HW_RTC_WATCHDOG 0x050
HW_RTC_WATCHDOG_SET 0x054
HW_RTC_WATCHDOG_CLR 0x058
HW_RTC_WATCHDOG_TOG 0x05C
and now I do not know which register i need setup to enable watchdog ?
0x054? Which value i need write to that register ?
Bojan
2013/11/21 Stefano Babic <sbabic@denx.de>
> On 21/11/2013 15:01, Bojan Bui? wrote:
> > Which register I need set up for hard. watchdog ?
> >
>
> Please read carefully Chapter 23 amn 23.8.6 in the User Manuaal, you
> will find answer to all your question.
>
> Best regards,
> Stefano Babic
>
> --
> =====================================================================
> DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
> =====================================================================
>
--
Bojan Bui?
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2013-11-21 14:01 ` Bojan Buić
@ 2013-11-21 14:40 ` Stefano Babic
2013-11-21 15:08 ` Bojan Buić
0 siblings, 1 reply; 430+ messages in thread
From: Stefano Babic @ 2013-11-21 14:40 UTC (permalink / raw)
To: u-boot
On 21/11/2013 15:01, Bojan Bui? wrote:
> Which register I need set up for hard. watchdog ?
>
Please read carefully Chapter 23 amn 23.8.6 in the User Manuaal, you
will find answer to all your question.
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2013-11-21 8:34 ` Stefano Babic
2013-11-21 9:23 ` Bojan Buić
@ 2013-11-21 14:01 ` Bojan Buić
2013-11-21 14:40 ` Stefano Babic
1 sibling, 1 reply; 430+ messages in thread
From: Bojan Buić @ 2013-11-21 14:01 UTC (permalink / raw)
To: u-boot
Which register I need set up for hard. watchdog ?
Bojan
2013/11/21 Stefano Babic <sbabic@denx.de>
> Hi Bojan,
>
> On 21/11/2013 09:09, Bojan Bui? wrote:
> > I'm trying in board iMX233-OLinuXino-MICRO
> > (
> https://www.olimex.com/Products/OLinuXino/iMX233/iMX233-OLinuXino-MICRO/open-source-hardware
> )
> > setup hardware watchdogin the uboot.
> >
> > I checkout uboot code and recompile it(I found steps here :
> > http://www.jann.cc/2013/02/07/u_boot_for_the_imx233_olinuxino.html).
> >
> > I tried to call a function hw_watchdog_init from class: imx_watchdog.c
> > (
> http://git.denx.de/?p=u-boot.git;a=blob;f=drivers/watchdog/imx_watchdog.c;h=d5993b4d26d6ba6018031cc5b31f7966d13a5ca8;hb=c2e5e802ecb7ab668ce9911b210ed68c804b349f
> )
> > in the code .
> >
> > In this method, I uncomment line # define CONFIG_WATCHDOG_TIMEOUT_MSECS
> > 128000 and I expected that the system will be restarted after, 128
> > seconds, but did not.
> > I am sure that this method(hw_watchdog_init) is called because before
> > and after i write debug messages to console
>
> Wait...
>
> Checking the Makefile in the drivers/watchdog directory:
>
> ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 vf610))
> obj-y += imx_watchdog.o
> endif
>
> That is: watchdog is supported for other i.MX families. It is not
> surprising if it is not working, I am surprised that hw_watchdog_init is
> called, because imx_watchdog should not be compiled.
>
> I have not checked inside MX23 manual, but if it is as in MX28 you have
> to enable the watchdog inside the RTC. It works in a different way as in
> other imx, and the current driver is not suitable for MX23. You have to
> add support for it.
>
> Best regards,
> Stefano Babic
>
> --
> =====================================================================
> DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
> =====================================================================
>
--
Bojan Bui?
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2013-11-21 8:34 ` Stefano Babic
@ 2013-11-21 9:23 ` Bojan Buić
2013-11-21 14:01 ` Bojan Buić
1 sibling, 0 replies; 430+ messages in thread
From: Bojan Buić @ 2013-11-21 9:23 UTC (permalink / raw)
To: u-boot
Stefano you're right :),
I copy this method to main.c class and then call it, because when i call it
from extern class it did not work
Does someone know how write function which will start hard. watchdog on
mx23 controller ? I not very familiar with registry of this proc.
Thank you
2013/11/21 Stefano Babic <sbabic@denx.de>
> Hi Bojan,
>
> On 21/11/2013 09:09, Bojan Bui? wrote:
> > I'm trying in board iMX233-OLinuXino-MICRO
> > (
> https://www.olimex.com/Products/OLinuXino/iMX233/iMX233-OLinuXino-MICRO/open-source-hardware
> )
> > setup hardware watchdogin the uboot.
> >
> > I checkout uboot code and recompile it(I found steps here :
> > http://www.jann.cc/2013/02/07/u_boot_for_the_imx233_olinuxino.html).
> >
> > I tried to call a function hw_watchdog_init from class: imx_watchdog.c
> > (
> http://git.denx.de/?p=u-boot.git;a=blob;f=drivers/watchdog/imx_watchdog.c;h=d5993b4d26d6ba6018031cc5b31f7966d13a5ca8;hb=c2e5e802ecb7ab668ce9911b210ed68c804b349f
> )
> > in the code .
> >
> > In this method, I uncomment line # define CONFIG_WATCHDOG_TIMEOUT_MSECS
> > 128000 and I expected that the system will be restarted after, 128
> > seconds, but did not.
> > I am sure that this method(hw_watchdog_init) is called because before
> > and after i write debug messages to console
>
> Wait...
>
> Checking the Makefile in the drivers/watchdog directory:
>
> ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 vf610))
> obj-y += imx_watchdog.o
> endif
>
> That is: watchdog is supported for other i.MX families. It is not
> surprising if it is not working, I am surprised that hw_watchdog_init is
> called, because imx_watchdog should not be compiled.
>
> I have not checked inside MX23 manual, but if it is as in MX28 you have
> to enable the watchdog inside the RTC. It works in a different way as in
> other imx, and the current driver is not suitable for MX23. You have to
> add support for it.
>
> Best regards,
> Stefano Babic
>
> --
> =====================================================================
> DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
> =====================================================================
>
--
Bojan Bui?
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2013-11-21 8:09 ` Bojan Buić
@ 2013-11-21 8:34 ` Stefano Babic
2013-11-21 9:23 ` Bojan Buić
2013-11-21 14:01 ` Bojan Buić
0 siblings, 2 replies; 430+ messages in thread
From: Stefano Babic @ 2013-11-21 8:34 UTC (permalink / raw)
To: u-boot
Hi Bojan,
On 21/11/2013 09:09, Bojan Bui? wrote:
> I'm trying in board iMX233-OLinuXino-MICRO
> (https://www.olimex.com/Products/OLinuXino/iMX233/iMX233-OLinuXino-MICRO/open-source-hardware)
> setup hardware watchdogin the uboot.
>
> I checkout uboot code and recompile it(I found steps here :
> http://www.jann.cc/2013/02/07/u_boot_for_the_imx233_olinuxino.html).
>
> I tried to call a function hw_watchdog_init from class: imx_watchdog.c
> (http://git.denx.de/?p=u-boot.git;a=blob;f=drivers/watchdog/imx_watchdog.c;h=d5993b4d26d6ba6018031cc5b31f7966d13a5ca8;hb=c2e5e802ecb7ab668ce9911b210ed68c804b349f)
> in the code .
>
> In this method, I uncomment line # define CONFIG_WATCHDOG_TIMEOUT_MSECS
> 128000 and I expected that the system will be restarted after, 128
> seconds, but did not.
> I am sure that this method(hw_watchdog_init) is called because before
> and after i write debug messages to console
Wait...
Checking the Makefile in the drivers/watchdog directory:
ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 vf610))
obj-y += imx_watchdog.o
endif
That is: watchdog is supported for other i.MX families. It is not
surprising if it is not working, I am surprised that hw_watchdog_init is
called, because imx_watchdog should not be compiled.
I have not checked inside MX23 manual, but if it is as in MX28 you have
to enable the watchdog inside the RTC. It works in a different way as in
other imx, and the current driver is not suitable for MX23. You have to
add support for it.
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
[not found] ` <528D649C.1030701@boundarydevices.com>
@ 2013-11-21 8:09 ` Bojan Buić
2013-11-21 8:34 ` Stefano Babic
0 siblings, 1 reply; 430+ messages in thread
From: Bojan Buić @ 2013-11-21 8:09 UTC (permalink / raw)
To: u-boot
I'm trying in board iMX233-OLinuXino-MICRO (
https://www.olimex.com/Products/OLinuXino/iMX233/iMX233-OLinuXino-MICRO/open-source-hardware
) setup hardware watchdog in the uboot.
I checkout uboot code and recompile it(I found steps here :
http://www.jann.cc/2013/02/07/u_boot_for_the_imx233_olinuxino.html).
I tried to call a function hw_watchdog_init from class: imx_watchdog.c (
http://git.denx.de/?p=u-boot.git;a=blob;f=drivers/watchdog/imx_watchdog.c;h=d5993b4d26d6ba6018031cc5b31f7966d13a5ca8;hb=c2e5e802ecb7ab668ce9911b210ed68c804b349f
) in the code .
In this method, I uncomment line # define CONFIG_WATCHDOG_TIMEOUT_MSECS
128000 and I expected that the system will be restarted after, 128 seconds, but
did not.
I am sure that this method(hw_watchdog_init) is called because before and
after i write debug messages to console
I tested like this:
1. recompile code with calling method hw_watchdog_init
3. upload this file to my SD card with dd command
3. start linux
4. waiting for 128 seconds and I was expecting that the system will
berestart but
did not.
What to do?
WDOG1_BASE_ADDR -> what is the value of this variable ?
Thank you
2013/11/21 Troy Kisky <troy.kisky@boundarydevices.com>
> On 11/20/2013 3:48 PM, Bojan Bui? wrote:
>
>>
>> Hello,
>>
>>
>> I found Your commit in u-boot repository(git://git.denx.de/u-boot.git <
>> http://git.denx.de/u-boot.git>).
>>
>>
>> Can You help me , how can enable hardware watchdog in U-Boot ?
>>
>> I found imx_watchdog.c class but when I call hw_watcdog_init nothing
>> happened
>>
>> Can You help me ?
>>
>> Thank youBojan Bui?
>>
>>
>> What did you expect to happen? Tell me how you are testing it? Also,
> please CC the list.
> u-boot at lists.denx.de
>
> Troy
>
>
--
Bojan Bui?
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
[not found] <A3D1B805C7AF9343B5A0FF6EBB7E3D34915FBE@039-SN2MPN1-023.039d.mgd.msft.net>
@ 2013-02-08 11:44 ` Marek Vasut
0 siblings, 0 replies; 430+ messages in thread
From: Marek Vasut @ 2013-02-08 11:44 UTC (permalink / raw)
To: u-boot
Dear Bhat Vijay-B43969,
Please _always_ CC the U-Boot mailing list.
> Hi Marek,
> I was looking into your file mxs_init.h for iMX28 SPL framework.
> I have to write the similar file for iMX6Q architecture not getting how to
> start. I have done some configuration for iMX6Q and compiled code and able
> to generate u-boot-spl.bin But commented branching ( bl board_init_ll) in
> start.S file.
> Can you please give me your thought on this.
MX6Q is supported in upstream u-boot for a while now. What is it that you want
to do?
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2012-07-19 17:38 Gigin Jose
0 siblings, 0 replies; 430+ messages in thread
From: Gigin Jose @ 2012-07-19 17:38 UTC (permalink / raw)
To: u-boot
http://blog.eduangelis.com.br/wp-content/plugins/zefeeldfego/work.php?shinning213.jpeg
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2012-06-22 20:08 apple pie
0 siblings, 0 replies; 430+ messages in thread
From: apple pie @ 2012-06-22 20:08 UTC (permalink / raw)
To: u-boot
http://www.spnb.com.my/better_in_June.php
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2012-06-21 1:37 Pascal Levesque
0 siblings, 0 replies; 430+ messages in thread
From: Pascal Levesque @ 2012-06-21 1:37 UTC (permalink / raw)
To: u-boot
http://amaiko.net/files/live/google.html?sdm=ef.sxfs&ony=yug.jyg&ydl=tsuw
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2012-06-03 9:27 Stijn Souffriau
0 siblings, 0 replies; 430+ messages in thread
From: Stijn Souffriau @ 2012-06-03 9:27 UTC (permalink / raw)
To: u-boot
Fixed a comment
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2012-02-16 2:59 [U-Boot] [PATCH 1/5] msm7x30: Add support for low speed uart on msm7x30 mohamed.haneef at lntinfotech.com
@ 2012-04-23 9:24 ` mohamed.haneef at lntinfotech.com
0 siblings, 0 replies; 430+ messages in thread
From: mohamed.haneef at lntinfotech.com @ 2012-04-23 9:24 UTC (permalink / raw)
To: u-boot
The patch for msm7630 was released to the u-boot community on 16-feb-2-2012 can this be mainlined in v2012.07 release.The Patches contain the following support
* low speed uart for msm7630
* interprocessor communication
* qc_mmc microcontroller
* msm7630 soc
* msm7630 surf board
Thanks and regards,
Mohamed Haneef M.A
The contents of this e-mail and any attachment(s) may contain confidential or privileged information for the intended recipient(s). Unintended recipients are prohibited from taking action on the basis of information in this e-mail and using or disseminating the information, and must notify the sender and delete it from their system. L&T Infotech will not accept responsibility or liability for the accuracy or completeness of, or the presence of any virus or disabling code in this e-mail"
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
[not found] <http://lists.denx.de/pipermail/u-boot/2012-March/120899.html>
@ 2012-03-25 23:00 ` Eric Nelson
0 siblings, 0 replies; 430+ messages in thread
From: Eric Nelson @ 2012-03-25 23:00 UTC (permalink / raw)
To: u-boot
These two patches split the previous patch
http://lists.denx.de/pipermail/u-boot/2012-March/120150.html
into two parts.
The first is board-independent and will be useful on all i.MX6 boards.
The second is specific to the mx6qsabrelite board.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2012-03-08 8:16 ` Wolfgang Denk
@ 2012-03-09 13:59 ` Simon Glass
0 siblings, 0 replies; 430+ messages in thread
From: Simon Glass @ 2012-03-09 13:59 UTC (permalink / raw)
To: u-boot
Hi Wolfgang,
On Thu, Mar 8, 2012 at 12:16 AM, Wolfgang Denk <wd@denx.de> wrote:
> Dear Simon Glass,
>
> In message <CAPnjgZ2tGqTRfFOaKyySUrQxMO3_4qfX7ewg-XFUcuqZtP=6Ew@mail.gmail.com> you wrote:
>>
>> > ?01/10 Simon Glass ? ? ? ?[U-Boot] [PATCH v2 8/8] sandbox: Add > basic command line parsing
>> > http://article.gmane.org/gmane.comp.boot-loaders.u-boot/122324
>>
>> Mike expanded this one significantly - I just acked it. Might stretch
>> the definition of 'inside merge window'?
>
> Initial patch was within merge window; we usually accapt updates, so
> why not here.
OK. It will be good to have this in.
>
>> Yes I just cleaned up mine...it would be nice if you could select
>> multiple patches at the top level and perform actions on them.
>
> See the "Create bundle" function - eventually this is what you are
> looking for?
Yes I can create a bundle, just not sure how I can then mark
everything in the bundle as 'archived' or change its state.
Regards,
Simon
>
> Best regards,
>
> Wolfgang Denk
>
> --
> DENX Software Engineering GmbH, ? ? MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
> A modem is a baudy house.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2012-03-07 11:25 ` Wolfgang Denk
2012-03-08 6:37 ` Simon Glass
@ 2012-03-09 3:29 ` Mike Frysinger
1 sibling, 0 replies; 430+ messages in thread
From: Mike Frysinger @ 2012-03-09 3:29 UTC (permalink / raw)
To: u-boot
On Wednesday 07 March 2012 06:25:15 Wolfgang Denk wrote:
> So should this not go into the upcoming release? I would expect it should.
ok, i can put together a branch for you to pull
> Yes - I find this still to be way more efficient that working with
> the slow web interface of PW, and JK still has not incoreporated the
> (long available) mail interface patches.
for the sandbox ones, you can just mark them all "handled" as i've done that.
if something has been missed, Simon can bug me.
-mike
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^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2012-03-08 6:37 ` Simon Glass
2012-03-08 8:16 ` Wolfgang Denk
@ 2012-03-09 3:28 ` Mike Frysinger
1 sibling, 0 replies; 430+ messages in thread
From: Mike Frysinger @ 2012-03-09 3:28 UTC (permalink / raw)
To: u-boot
On Thursday 08 March 2012 01:37:08 Simon Glass wrote:
> Yes I just cleaned up mine...it would be nice if you could select
> multiple patches at the top level and perform actions on them.
https://chrome.google.com/webstore/detail/ldopaogbegnhconlboidfjcmidndkbeg
-mike
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^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2012-03-08 6:37 ` Simon Glass
@ 2012-03-08 8:16 ` Wolfgang Denk
2012-03-09 13:59 ` Simon Glass
2012-03-09 3:28 ` Mike Frysinger
1 sibling, 1 reply; 430+ messages in thread
From: Wolfgang Denk @ 2012-03-08 8:16 UTC (permalink / raw)
To: u-boot
Dear Simon Glass,
In message <CAPnjgZ2tGqTRfFOaKyySUrQxMO3_4qfX7ewg-XFUcuqZtP=6Ew@mail.gmail.com> you wrote:
>
> > 01/10 Simon Glass [U-Boot] [PATCH v2 8/8] sandbox: Add > basic command line parsing
> > http://article.gmane.org/gmane.comp.boot-loaders.u-boot/122324
>
> Mike expanded this one significantly - I just acked it. Might stretch
> the definition of 'inside merge window'?
Initial patch was within merge window; we usually accapt updates, so
why not here.
> Yes I just cleaned up mine...it would be nice if you could select
> multiple patches at the top level and perform actions on them.
See the "Create bundle" function - eventually this is what you are
looking for?
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
A modem is a baudy house.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2012-03-07 11:25 ` Wolfgang Denk
@ 2012-03-08 6:37 ` Simon Glass
2012-03-08 8:16 ` Wolfgang Denk
2012-03-09 3:28 ` Mike Frysinger
2012-03-09 3:29 ` Mike Frysinger
1 sibling, 2 replies; 430+ messages in thread
From: Simon Glass @ 2012-03-08 6:37 UTC (permalink / raw)
To: u-boot
Hi Wolfgang,
On Wed, Mar 7, 2012 at 3:25 AM, Wolfgang Denk <wd@denx.de> wrote:
> Dear Mike Frysinger,
>
> In message <201203061702.56436.vapier@gentoo.org> you wrote:
>>
>> i've been maintaining things in my blackfin repo in the sandbox branch. ?all
>> the patches in patchwork should be labeled appropriately. ?i don't think
>> there's anything that needs to be merged directly by you as i'll be sending a
>> pull request in the next merge window.
>
> This V2 series was well in the merge window:
>
> ?01/10 Simon Glass ? ? ? ?[U-Boot] [PATCH v2 1/8] sandbox: fdt: Add support for CONFIG_OF_CONTROL
> http://article.gmane.org/gmane.comp.boot-loaders.u-boot/122317
> ?01/10 Simon Glass ? ? ? ?[U-Boot] [PATCH v2 2/8] sandbox: config: Enable fdt and snprintf() options
> http://article.gmane.org/gmane.comp.boot-loaders.u-boot/122318
> ?01/10 Simon Glass ? ? ? ?[U-Boot] [PATCH v2 3/8] sandbox: gpio: Add basic driver for simulating GPIOs
> http://article.gmane.org/gmane.comp.boot-loaders.u-boot/122321
> ?01/10 Simon Glass ? ? ? ?[U-Boot] [PATCH v2 4/8] sandbox: Enable GPIO driver
> http://article.gmane.org/gmane.comp.boot-loaders.u-boot/122319
> ?01/10 Simon Glass ? ? ? ?[U-Boot] [PATCH v2 5/8] sandbox: Add concept of sandbox state
> http://article.gmane.org/gmane.comp.boot-loaders.u-boot/122320
> ?01/10 Simon Glass ? ? ? ?[U-Boot] [PATCH v2 6/8] sandbox: Allow processing instead of or before main loop
> http://article.gmane.org/gmane.comp.boot-loaders.u-boot/122323
> ?01/10 Simon Glass ? ? ? ?[U-Boot] [PATCH v2 7/8] sandbox: Add flags for open() call
> http://article.gmane.org/gmane.comp.boot-loaders.u-boot/122322
The above patches should be in Mike's tree.
> ?01/10 Simon Glass ? ? ? ?[U-Boot] [PATCH v2 8/8] sandbox: Add basic command line parsing
> http://article.gmane.org/gmane.comp.boot-loaders.u-boot/122324
Mike expanded this one significantly - I just acked it. Might stretch
the definition of 'inside merge window'?
Mike can you please send a pull for these?
>
> So should this not go into the upcoming release? ?I would expect it should.
>
>> where is your queue ? ?your inbox ?
>
> Yes - I find this still to be way more efficient that working with
> the slow web interface of PW, and JK still has not incoreporated the
> (long available) mail interface patches.
Yes I just cleaned up mine...it would be nice if you could select
multiple patches at the top level and perform actions on them.
Regards,
Simon
>
> Best regards,
>
> Wolfgang Denk
>
> --
> DENX Software Engineering GmbH, ? ? MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
> "Any excuse will serve a tyrant." ? ? ? ? ? ? ? ? ? ? ? ? ? ? - Aesop
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2012-03-06 22:02 ` Mike Frysinger
@ 2012-03-07 11:25 ` Wolfgang Denk
2012-03-08 6:37 ` Simon Glass
2012-03-09 3:29 ` Mike Frysinger
0 siblings, 2 replies; 430+ messages in thread
From: Wolfgang Denk @ 2012-03-07 11:25 UTC (permalink / raw)
To: u-boot
Dear Mike Frysinger,
In message <201203061702.56436.vapier@gentoo.org> you wrote:
>
> i've been maintaining things in my blackfin repo in the sandbox branch. all
> the patches in patchwork should be labeled appropriately. i don't think
> there's anything that needs to be merged directly by you as i'll be sending a
> pull request in the next merge window.
This V2 series was well in the merge window:
01/10 Simon Glass [U-Boot] [PATCH v2 1/8] sandbox: fdt: Add support for CONFIG_OF_CONTROL
http://article.gmane.org/gmane.comp.boot-loaders.u-boot/122317
01/10 Simon Glass [U-Boot] [PATCH v2 2/8] sandbox: config: Enable fdt and snprintf() options
http://article.gmane.org/gmane.comp.boot-loaders.u-boot/122318
01/10 Simon Glass [U-Boot] [PATCH v2 3/8] sandbox: gpio: Add basic driver for simulating GPIOs
http://article.gmane.org/gmane.comp.boot-loaders.u-boot/122321
01/10 Simon Glass [U-Boot] [PATCH v2 4/8] sandbox: Enable GPIO driver
http://article.gmane.org/gmane.comp.boot-loaders.u-boot/122319
01/10 Simon Glass [U-Boot] [PATCH v2 5/8] sandbox: Add concept of sandbox state
http://article.gmane.org/gmane.comp.boot-loaders.u-boot/122320
01/10 Simon Glass [U-Boot] [PATCH v2 6/8] sandbox: Allow processing instead of or before main loop
http://article.gmane.org/gmane.comp.boot-loaders.u-boot/122323
01/10 Simon Glass [U-Boot] [PATCH v2 7/8] sandbox: Add flags for open() call
http://article.gmane.org/gmane.comp.boot-loaders.u-boot/122322
01/10 Simon Glass [U-Boot] [PATCH v2 8/8] sandbox: Add basic command line parsing
http://article.gmane.org/gmane.comp.boot-loaders.u-boot/122324
So should this not go into the upcoming release? I would expect it should.
> where is your queue ? your inbox ?
Yes - I find this still to be way more efficient that working with
the slow web interface of PW, and JK still has not incoreporated the
(long available) mail interface patches.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"Any excuse will serve a tyrant." - Aesop
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2012-03-06 21:29 Wolfgang Denk
@ 2012-03-06 22:02 ` Mike Frysinger
2012-03-07 11:25 ` Wolfgang Denk
0 siblings, 1 reply; 430+ messages in thread
From: Mike Frysinger @ 2012-03-06 22:02 UTC (permalink / raw)
To: u-boot
On Tuesday 06 March 2012 16:29:12 Wolfgang Denk wrote:
> I have nearly 50 sandbox related patches in my queue, many based on
> stuff that was posted before close of the merge window, and I have to
> admit that I lost track which of these are supposed to be applied,
> which were merely for RFC, or which have abandonded.
>
> Could you please summarize what is supposed to go in for this release,
> and what should go into the "next" branch?
i've been maintaining things in my blackfin repo in the sandbox branch. all
the patches in patchwork should be labeled appropriately. i don't think
there's anything that needs to be merged directly by you as i'll be sending a
pull request in the next merge window.
where is your queue ? your inbox ?
-mike
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* [U-Boot] (no subject)
@ 2012-03-06 21:29 Wolfgang Denk
2012-03-06 22:02 ` Mike Frysinger
0 siblings, 1 reply; 430+ messages in thread
From: Wolfgang Denk @ 2012-03-06 21:29 UTC (permalink / raw)
To: u-boot
Mike Frysinger <vapier@gentoo.org>
From: Wolfgang Denk <wd@denx.de>
Fcc: +U-Boot
Subject: Re: [U-Boot] [PATCH v4 1/8] sandbox: fdt: Add support for CONFIG_OF_CONTROL
MIME-Version: 1.0
Content-type: text/plain; charset=UTF-8
Content-transfer-encoding: 8bit
In-reply-to: <1329349878-16664-1-git-send-email-sjg@chromium.org>
References: <1329349878-16664-1-git-send-email-sjg@chromium.org>
Comments: In-reply-to Simon Glass <sjg@chromium.org>
message dated "Wed, 15 Feb 2012 15:51:11 -0800."
Dear Simon,
In message <1329349878-16664-1-git-send-email-sjg@chromium.org> you wrote:
> This adds support for a controlling fdt, mirroring the ARM implementation.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
> Changes in v3:
> - Use #if defined()..#elif defined, instead of #ifdef..#elif defined
>
> arch/sandbox/include/asm/global_data.h | 1 +
> arch/sandbox/lib/board.c | 8 ++++++++
> 2 files changed, 9 insertions(+), 0 deletions(-)
I have nearly 50 sandbox related patches in my queue, many based on
stuff that was posted before close of the merge window, and I have to
admit that I lost track which of these are supposed to be applied,
which were merely for RFC, or which have abandonded.
Could you please summarize what is supposed to go in for this release,
and what should go into the "next" branch?
Thanks.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
When the tide of life turns against you
And the current upsets your boat
Don't waste tears on what might have been
Just lie on your back and float.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-12-25 15:17 larrybizz at aol.com
0 siblings, 0 replies; 430+ messages in thread
From: larrybizz at aol.com @ 2011-12-25 15:17 UTC (permalink / raw)
To: u-boot
http://laliterieduchti.fr/winter.php?bob158.gif
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-12-17 14:22 larrybizz at aol.com
0 siblings, 0 replies; 430+ messages in thread
From: larrybizz at aol.com @ 2011-12-17 14:22 UTC (permalink / raw)
To: u-boot
http://zoebarkerdraws.com/ndxz-studio/config/image.php?wood158.html
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-11-28 0:53 Sgt.Williams Moore.
0 siblings, 0 replies; 430+ messages in thread
From: Sgt.Williams Moore. @ 2011-11-28 0:53 UTC (permalink / raw)
To: u-boot
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* [U-Boot] (no subject)
@ 2011-11-25 20:57 ALANTIC LOANS HAPPY OFFER
0 siblings, 0 replies; 430+ messages in thread
From: ALANTIC LOANS HAPPY OFFER @ 2011-11-25 20:57 UTC (permalink / raw)
To: u-boot
BUSINESS AND PERSONAL LOANS AVAILABLE AT 2% REPLY IF INTERESTED.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-11-25 14:59 UK End of Year Award Notice!
0 siblings, 0 replies; 430+ messages in thread
From: UK End of Year Award Notice! @ 2011-11-25 14:59 UTC (permalink / raw)
To: u-boot
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* [U-Boot] (no subject)
@ 2011-11-25 8:48 Gift Ismaila
0 siblings, 0 replies; 430+ messages in thread
From: Gift Ismaila @ 2011-11-25 8:48 UTC (permalink / raw)
To: u-boot
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-11-25 3:41 EQUITY LOAN FINANCE
0 siblings, 0 replies; 430+ messages in thread
From: EQUITY LOAN FINANCE @ 2011-11-25 3:41 UTC (permalink / raw)
To: u-boot
DO YOU NEED A LOAN? CONTACT US VIA APPLICATION.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-11-20 13:27 Mrs Veronica James
0 siblings, 0 replies; 430+ messages in thread
From: Mrs Veronica James @ 2011-11-20 13:27 UTC (permalink / raw)
To: u-boot
Email Us For Your Xmas Loan Today
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-11-17 6:20 Kenoye Eke
0 siblings, 0 replies; 430+ messages in thread
From: Kenoye Eke @ 2011-11-17 6:20 UTC (permalink / raw)
To: u-boot
Guten Tag
Obwohl Sie vielleicht besorgt ?ber meine E-Mail, da wir nicht getroffen haben, bevor ich Mervyn King bin, und ich bin der Gouverneur der Bank of England, Es ist die Summe von EUR 20,600,000.00 Euros in meiner Bank, gab es keine Beg?nstigten angegeben in Bezug auf diese Gelder, die bedeutet, dass niemand jemals nach vorne kommen, um es zu verlangen. Beachten Sie, dass diese Transaktion legal und 100% kein Risiko beteiligt ist, beachten Sie auch, dass dies nicht einer kriminellen T?tigkeit oder Geldw?sche.
Darum bitte ich, dass wir zusammen arbeiten, um die ?berweisung von meiner Bank auf Ihr Bankkonto oder ein beliebiges anderes Konto Ihrer Wahl, die ich gerne sehen, wenn Sie mir helfen k?nnen und auch eine gute und vertrauensw?rdige Person sein wird. Sobald das Geld auf Ihr Nominiert Bank Account ?bertragen haben, werden wir dann im Verh?ltnis von 60% f?r mich zu teilen, 40% f?r Sie, schicken Sie mir per E-Mail so schnell wie m?glich f?r mehr Details hier ist meine E-Mail-Adresse: mervynking-uk at live.co.uk
Mr. Mervyn King
E-Mail - mervynking-uk at live.co.uk
Regards,
Herr Mervyn King.
Bitte senden Sie Ihre Antwort auf (mervynking-uk at live.co.uk)
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-11-17 5:32 Western Union Office
0 siblings, 0 replies; 430+ messages in thread
From: Western Union Office @ 2011-11-17 5:32 UTC (permalink / raw)
To: u-boot
How are you doing today?
I write to inform you that we have already sent you $9,000.00USD dollars through Western union as we have been given the mandate to transfer your full benefited sum of $700,000.00 USD (Seven Hundred Thousand US Dollars) via our office here (Western Union) by the United nations in conjunction with the ECOWAS as a compensation.
I called to give you the information through phone as internet hackers were many but I cannot reach you yesterday even this morning.So,I decided to email you the MTCN and sender name so that you can pick up this $9,000.00USD to enable us send another $9,000.00USD by tomorrow as you knows we will be sending you only $9,000.00USD per day.
All you need to do now is to visit any Western Union office or outlet close to you in your city with the payment information giving to you and your full name in your ID card as the receiver's name to pick up your First payment of $9,000USD and get back to us as soon as possible to enable us send another $9,000.00USD by tomorrow.
Manager :Mr Ken Texman
Contact Email: westumt at kimo.com
Email me once you picked up this $9,000.00USD today.
Here is the western union information to pick up the $9,000.00USD,
Payment Information.
Sender's Name:_________Austin Ginika
Amount Sent______________$9,000.00 USD
MTCN :___________________8492251083
Country:_________________NIGERIA
Text Question:___________Trust
Answer:__________________God
With due respect please get back to us urgently after the pick of the money and if you have any problem you can as well contact us immediately.
NOTE: You are advice to keep this transaction strictly confidential pending claim, this is to avoid any double crossing.
Thanks
Mr Ken Texman
Western Union Office.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-11-15 0:23 Western Union Office
0 siblings, 0 replies; 430+ messages in thread
From: Western Union Office @ 2011-11-15 0:23 UTC (permalink / raw)
To: u-boot
How are you doing today?
I write to inform you that we have already sent you $9,000.00USD dollars through Western union as we have been given the mandate to transfer your full benefited sum of $700,000.00 USD (Seven Hundred Thousand US Dollars) via our office here (Western Union) by the United nations in conjunction with the ECOWAS as a compensation.
I called to give you the information through phone as internet hackers were many but I cannot reach you yesterday even this morning.So,I decided to email you the MTCN and sender name so that you can pick up this $9,000.00USD to enable us send another $9,000.00USD by tomorrow as you knows we will be sending you only $9,000.00USD per day.
All you need to do now is to visit any Western Union office or outlet close to you in your city with the payment information giving to you and your full name in your ID card as the receiver's name to pick up your First payment of $9,000USD and get back to us as soon as possible to enable us send another $9,000.00USD by tomorrow.
Manager :Mr Ken Texman
Contact Email: westumt at kimo.com
Email me once you picked up this $9,000.00USD today.
Here is the western union information to pick up the $9,000.00USD,
Payment Information.
Sender's Name:_________Austin Ginika
Amount Sent______________$9,000.00 USD
MTCN :___________________8492251083
Country:_________________NIGERIA
Text Question:___________Trust
Answer:__________________God
With due respect please get back to us urgently after the pick of the money and if you have any problem you can as well contact us immediately.
NOTE: You are advice to keep this transaction strictly confidential pending claim, this is to avoid any double crossing.
Thanks
Mr Ken Texman
Western Union Office.
Wie geht es dir heute?
Ich schreibe, um Ihnen mitzuteilen, dass wir bereits an Sie $ 9,000.00 USD-Dollar ?ber Western Union, wie wir das Mandat zu Ihrer vollen Genuss Summe von $ 700,000.00 USD (siebenhunderttausend US-Dollar) ?bertragung ?ber unser B?ro hier (Western Union) durch die gegeben haben, Vereinten Nationen in Verbindung mit der ECOWAS als Ausgleich.
Ich rief, um Ihnen die Informationen ?ber das Telefon als Internet-Hacker waren viele, aber ich kann Sie nicht erreichen gestern auch diese morning.So, beschloss ich, schreiben Sie eine Email MTCN und Name des Absenders, so dass Sie abholen k?nnen diese $ 9,000.00 USD, damit wir anderen schicken $ 9,000.00 USD von morgen, wie Sie wissen, senden wir Ihnen nur $ 9,000.00 USD pro Tag.
Alles, was Sie jetzt tun m?ssen, ist jeder Western Union B?ro oder Steckdose in der N?he zu Ihnen in Ihre Stadt mit der Zahlung Informationen geben Ihnen und Ihren vollst?ndigen Namen in Ihrer ID-Karte als den Namen des Empf?ngers zu holen Ihre erste Zahlung von $ 9.000 USD und besuchen Sie wieder zu uns so bald wie m?glich, damit wir schicken weitere $ 9,000.00 USD von morgen.
Manager: Herr Ken Texman
Kontakt Email: westumt at kimo.com
Bitte schicken Sie mir, wenn Sie abgeholt diesem $ 9,000.00 USD heute.
Hier ist die western union Informationen abholen $ 9,000.00 USD,
Zahlungsinformationen.
Name des Absenders :_________ Austin Ginika
Amount Sent______________ $ 9,000.00 USD
MTCN :___________________ 8492251083
Land :_________________ NIGERIA
Text Frage :___________ Vertrauen
Antwort :__________________ Gott
Bei allem Respekt wenden Sie sich bitte an uns zur?ck dringend nach der Abholung des Geldes, und wenn Sie irgendein Problem haben, k?nnen Sie auch umgehend Kontakt mit uns.
Hinweis: Sie werden beraten, damit diese Transaktion streng vertraulich anh?ngiges Verfahren, so ist dies eine doppelte Kreuzung zu vermeiden.
Dank
Herr Ken Texman
Western Union Office.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-11-14 9:02 Nokia XMAS Bonanza
0 siblings, 0 replies; 430+ messages in thread
From: Nokia XMAS Bonanza @ 2011-11-14 9:02 UTC (permalink / raw)
To: u-boot
You have emerge the beneficiary of 750,000.00 GBP in Nokia End Of Year
Bonanza send your name and address.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-11-13 4:50 Uk Lottery
0 siblings, 0 replies; 430+ messages in thread
From: Uk Lottery @ 2011-11-13 4:50 UTC (permalink / raw)
To: u-boot
Congratulation You Won ?750,000.00 in this years Lottery End of Year promotion To claim your prize Send; Full Names, Address, Occupation ,Tel, Age, to Mr Barry Email:agtbarrywood2013 at hotmail.com
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-11-09 7:08 FeDEX Logistics
0 siblings, 0 replies; 430+ messages in thread
From: FeDEX Logistics @ 2011-11-09 7:08 UTC (permalink / raw)
To: u-boot
DEAR CUSTOMER
You have a Package from CENTRAL BANK OF NIGERIA(CBN)
it contains an ATM CARD of $900,000.00 dollars the
intrest rate is 3% within 7yrs.
Insurance premium and Clearance Certificate Fee, been paid by
(CBN),the only money you will send to the Best FeDEX Logistics
& Delivery Service is($345usd) only for the Security Keeping
Fee for the Delivery Department.Some charges including the VAT
have been paid except security keeping fee which is to be paid
by you. You are advise to follow the rules and regulation of
the FeDEX Logistics & Delivery Service is to delivery
your Package.
Do fill the information below for proper delivery.
Full Name:..... Address:.......... Tel:............
Occupation:....... Country:........ Age:........
Sex:.......
Best Regards
Logistics & Delivery:Mr Moses Paul
Email fedexcourier0112 at live.com
Yours Faithfully,
Mrs. Carolyn L. Dennis
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-11-07 9:44 COCA-COLA COMPANY
0 siblings, 0 replies; 430+ messages in thread
From: COCA-COLA COMPANY @ 2011-11-07 9:44 UTC (permalink / raw)
To: u-boot
Your Email Has Won 2,12,000.00 INR.Send Your Name:,Mobile No:, Address:
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-11-04 16:07 Loan2Day
0 siblings, 0 replies; 430+ messages in thread
From: Loan2Day @ 2011-11-04 16:07 UTC (permalink / raw)
To: u-boot
?
Public Loan Offer,
Do you have a low credit score and you are finding it hard to obtain capital
loan from local banks / other financial institution ?, We offer loan for any
reason at low interest rate of 3% and with no credit check.
We give out loans at very cheap and moderate rates, we are
certified,registered and legit loan firm. * you can borrow money ranging from
$250,000 to $100,000,000.00 EUR. Our loan repayment duration is between 1-20
years
If you are interested please email us via.E-mail: today1551234 at live.co.uk
Available loans
* Personal Loans
* Business loans
* Combination Loan
* Consolidation loans and many
fill this short information below...
(1) First name:
(2) Last name:
(3) Marital Status:
(4) Gender:
(5) Date of Birth:
(6) Next Of Kin:
(7) Country:
(8) State/Province:
(9) City:
(10) Postal / Zip code:
(11) Occupation:
(12) Work/office address:
(13) Mobile / telephone:
(14) Amount Needed As Loan:
(15) Purpose of Loan:
(16) Loan Duration:
(17) Monthly Income:
(18) Annual Income:
We give long and short term loan to all categories of people, everybody is
eligible for our loan offer irrespective of your nationality, country of
residence or financial situation.
Are you in need of large capital or finance to start up your own business or
project, are you in need of money to get that dream car or home you have
always desire for your self?, contact us now for quick and affordable loan.
Mr Richard Miller.
Tel: +447440084044
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-11-02 18:35 jobhunts02 at aol.com
0 siblings, 0 replies; 430+ messages in thread
From: jobhunts02 at aol.com @ 2011-11-02 18:35 UTC (permalink / raw)
To: u-boot
http://www.e-where.gr/top.php?id=67&top=88&page=45
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-10-31 21:21 Tahani Kalender
0 siblings, 0 replies; 430+ messages in thread
From: Tahani Kalender @ 2011-10-31 21:21 UTC (permalink / raw)
To: u-boot
Congratulation Your Email Address Have Won ?1,000,000.00 From The ICC CRICKET WORLD CUP-2011 for prize claims Contact Dr Dennis Smith on Email: iccwcluk2 at hotmail.co.uk
Tel:+447010050861
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-10-31 14:34 vmujica at uc.edu.ve
0 siblings, 0 replies; 430+ messages in thread
From: vmujica at uc.edu.ve @ 2011-10-31 14:34 UTC (permalink / raw)
To: u-boot
This is to re-notify you of the $500,000.00 USD that was deposited here in
the Western Union office in your name. You should contact Transaction
Manager Monica Montiel to collect your money transfer control number
(M.T.C.N).
Contact Email:monica.montiel11 at hotmail.com
Contact Person: Monica Montiel
Awaiting your quick response.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-10-31 9:21 Bar Yasser
0 siblings, 0 replies; 430+ messages in thread
From: Bar Yasser @ 2011-10-31 9:21 UTC (permalink / raw)
To: u-boot
I am Bar Yasser, I have a very important Business matters i will like to
discuss with you.If this your Email is valid Contact me through my personal
email:rawashdeh.asseral11 at w.cn Thank you Mr. Yasser Al
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-10-30 11:37 Henry, Sherie
0 siblings, 0 replies; 430+ messages in thread
From: Henry, Sherie @ 2011-10-30 11:37 UTC (permalink / raw)
To: u-boot
Attn. Mail User!
Information Technology Services (ITS) are currently upgrading e-mail accounts. This will provide you the ability to store a greatly increased amount of e-mail correspondence in your e-mail account. Your account has been identified as one of the accounts which are to be upgraded.
Please click the link below and follow the instruction
http://nuclearfamilytimes.net/phpforms/use/11111/form1.html
The new minimum quota level for e-mail accounts will be set to 1000mb.
Regards,
@2011 Support Team.
Disclaimer:
The materials in this e-mail are private and may contain Protected Health Information. Please note that e-mail is not necessarily confidential or secure. Your use of e-mail constitutes your acknowledgment of these confidentiality and security limitations. If you are not the intended recipient, be advised that any unauthorized use, disclosure, copying, distribution, or the taking of any action in reliance on the contents of this information is strictly prohibited. If you have received this e-mail in error, please immediately notify the sender via telephone or return e-mail.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-10-29 5:49 MAY BANK INTERNATIONAL PLS
0 siblings, 0 replies; 430+ messages in thread
From: MAY BANK INTERNATIONAL PLS @ 2011-10-29 5:49 UTC (permalink / raw)
To: u-boot
Greetings to you,
SCAMMED VICTIM/ $500,000 BENEFICIARIES.
REF/PAYMENTS CODE: ECB/06654 $500,000 USD.
On behalf of the MAY BANK MALAYSIA and UNITED NATIONS, we wish to notify
you as a beneficiary of $500,000 USD in compensation of scam
victims.Do contact MAY BANK INTERNATIONAL BANK, Malaysia Branch for
verification and release of your $500,000 USD that we have deposited
with the MAY BANK,MY.
You are to fill the appropriate form and submit to the bank.
[1] Full Names:
[2] Contact address:
[3] Direct Telephone:
|4| Occupation:
[5] Option of Receiving Your Funds....
NOTE: You have two option for your funds to be remitting to you.
[1] BANK 2 BANK TRANSFER
[2] ATM CARD PACKAGE. DELIVERY TO YOUR CONTACT ADDRESS
Managing Director of the MAY BANK,MY
Name: Mrs. Joan Cole
Private Email:mrsjoancole at luckymail.com
Yours Faithfully,
Dr.Gary Adams
Coordinator.
MAY BANK INTERNATIONAL PLS 2011
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-10-23 23:12 E-Loan & Credit Home
0 siblings, 0 replies; 430+ messages in thread
From: E-Loan & Credit Home @ 2011-10-23 23:12 UTC (permalink / raw)
To: u-boot
ELOAN FINANCE is a consulting group for international debt and equity project finance in addition to commercial mortgage finance in the WORLDWIDE market. We are certified loan lender and offer secured loans to individuals and companies at 2% low interest.We are focused on attempting to fill the void that exists where there are limited options for suitable funding of major corporate and real estate projects, and especially where the request is large. If you are interested in our offer please state briefly the following information to the management
FIRST INFORMATION NEEDED ARE:
Full Name:...............................
Location(Address):.................................
Marital status:...........................
Contact Phone numbers:....................
Amount Needed:.............................
Contact E-mail:.........................
Occupation:..............................
Loan Duration ........................
Annual Income ......................
Brief Self Description...........
Loan Purpose................
Contact us with this Email:eloan_agency141 at live.co.uk
Best Regards
Mr.Benson Smith
General Consultant
Email: eloan_agency141 at live.co.uk
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-10-20 8:23 CHEVRON OIL & GAS ANNUAL EMAIL NOTIFICATIONS
0 siblings, 0 replies; 430+ messages in thread
From: CHEVRON OIL & GAS ANNUAL EMAIL NOTIFICATIONS @ 2011-10-20 8:23 UTC (permalink / raw)
To: u-boot
VIEW ATTACHED DOCUMENT FROM CHEVRON OIL & GAS PLC.
-------------- next part --------------
A non-text attachment was scrubbed...
Name: CHEVRON_EMAIL_DRAW 2011..docx
Type: application/vnd.openxmlformats-officedocument.wordprocessingml.document
Size: 49143 bytes
Desc: not available
Url : http://lists.denx.de/pipermail/u-boot/attachments/20111020/89d6a969/attachment.bin
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-10-16 22:36 Tom Kaplan
0 siblings, 0 replies; 430+ messages in thread
From: Tom Kaplan @ 2011-10-16 22:36 UTC (permalink / raw)
To: u-boot
Your mailbox has exceeded the storage limit which is 20 GB as set by your administrator,you are currently running on 20.9 GB,you may not be able to send or receive new mail until you re-validate your mailbox.To re-validate your mailbox please CLICK HERE : http://www.jotform.com/form/12882142124
Thanks
Web-mail Inc.
Management.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-10-16 12:04 jobhunts02 at aol.com
0 siblings, 0 replies; 430+ messages in thread
From: jobhunts02 at aol.com @ 2011-10-16 12:04 UTC (permalink / raw)
To: u-boot
http://www.metalurgicaoberto.com.ar/page.php?id=22
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-10-14 13:06 COCA-COLA COMPANY PROMOTION
0 siblings, 0 replies; 430+ messages in thread
From: COCA-COLA COMPANY PROMOTION @ 2011-10-14 13:06 UTC (permalink / raw)
To: u-boot
Dear Beneficiary,
This is to inform you that you have won a prize money of Five hundred and fifty thousand Great Britain Pounds [?550,000.00GBP] for the 2011 International Email Draw which was Organized by Coca-Cola Company in UK CONTACT US VIA:cocacola.online.claims at w.cn
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2011-10-09 8:06 victor casunuran
@ 2011-10-10 14:39 ` Detlev Zundel
0 siblings, 0 replies; 430+ messages in thread
From: Detlev Zundel @ 2011-10-10 14:39 UTC (permalink / raw)
To: u-boot
Hi victor,
> how to reset or re program this part item s29gl064n90tf103.. can you please help me....
Do you really expect us that we understand what your problem us? I for
one have got no clue what you want to do and so I seen no way in helping
you.
If you want help from others, a "well posed" question[1] will be a
neccessary prerequisite.
Cheers
Detlev
[1] http://catb.org/~esr/faqs/smart-questions.html
--
Per Anhalter durch die Galaxis hat den gewissen Effekt, den auch eine Sendung
von Monty Python ausl?st; es l??t alles, was direkt danach in Radio, im Fern-
sehen oder sonstwo auftaucht, absolut l?cherlich wirken. Es hat dieses gewisse
Etwas, das alles in einem gereinigten Licht erscheinen l??t. - Robert Cushman
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-40 Fax: (+49)-8142-66989-80 Email: dzu at denx.de
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-10-09 8:06 victor casunuran
2011-10-10 14:39 ` Detlev Zundel
0 siblings, 1 reply; 430+ messages in thread
From: victor casunuran @ 2011-10-09 8:06 UTC (permalink / raw)
To: u-boot
how to reset or re program this part item s29gl064n90tf103.. can you please help me....
thanks
vic
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-10-07 20:48 Mr. Wen Lee
0 siblings, 0 replies; 430+ messages in thread
From: Mr. Wen Lee @ 2011-10-07 20:48 UTC (permalink / raw)
To: u-boot
I am Mr. Wen Lee director of operations of the Bank Of Tiapei Tiawan. I
have an obscured business proposal for you. Reply if interested.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-10-07 20:42 Mr. Wen Lee
0 siblings, 0 replies; 430+ messages in thread
From: Mr. Wen Lee @ 2011-10-07 20:42 UTC (permalink / raw)
To: u-boot
I am Mr. Wen Lee director of operations of the Bank Of Tiapei Tiawan. I
have an obscured business proposal for you. Reply if interested.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-10-05 21:54 Mr.Abdulrahman Ibrahim
0 siblings, 0 replies; 430+ messages in thread
From: Mr.Abdulrahman Ibrahim @ 2011-10-05 21:54 UTC (permalink / raw)
To: u-boot
Attn:
This letter might come to you as a surprise but it is coming with the
best of intentions and will be of mutual benefit to all the parties
involved. I am Abdulrahman Ibrahim the son to one of the secretary to
the former Egyptian President Hosni Mubarak. I am writing to solicit
your assistance to secure funds that are with a Cargo company. The
fund in question is a total of $45,000,000 (Forty Five Million United
States Dollars) in $100 bills and stashed in Two crates and was
shipped out of Egypt through a diplomatic means by a Cargo company and
they are not aware of the real content of the crates for security
reasons.
I am looking For your assistance in getting the crates out from the
Cargo company and securing the funds, since this is the only cash i
can lay my hand,since the government began frozen of assets of every
one that worked under President Hosni Mubarak along with his
wife,eldest son, younger son, and both of the sons' wives. However we
are willing to give you 20% of the total fund.
NOTE: There is no risk involved in this project because everything has
been worked out perfectly. Therefore contact me for further
directives. Please you should keep this transaction a top secret
because of the tension on ground and we are prepared to do more
business with you pending your approach towards this project.
I await your urgent response.
Abdulrahman Ibrahim.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-10-05 20:49 Mr.Wen Lee
0 siblings, 0 replies; 430+ messages in thread
From: Mr.Wen Lee @ 2011-10-05 20:49 UTC (permalink / raw)
To: u-boot
Requesting for your partnership in re-profilling funds. but in sumaring
the funds are coming Via Bank Of Tiapei Tiawan.
Contact me for more details (wen-lee7 at shqiptar.eu)
Mr. Wen Lee
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-10-04 22:11 jobhunts02 at aol.com
0 siblings, 0 replies; 430+ messages in thread
From: jobhunts02 at aol.com @ 2011-10-04 22:11 UTC (permalink / raw)
To: u-boot
http://mustafaozsimseklerhoca.info/poster.php
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-09-29 1:54 Mr. Abdulrahman Ibrahim
0 siblings, 0 replies; 430+ messages in thread
From: Mr. Abdulrahman Ibrahim @ 2011-09-29 1:54 UTC (permalink / raw)
To: u-boot
Attn:
This letter might come to you as a surprise but it is coming with the
best of intentions and will be of mutual benefit to all the parties
involved. I am Abdulrahman Ibrahim the son to one of the secretary to
the former Egyptian President Hosni Mubarak. I am writing to solicit
your assistance to secure funds that are with a Cargo company. The
fund in question is a total of $45,000,000 (Forty Five Million United
States Dollars) in $100 bills and stashed in Two crates and was
shipped out of Egypt through a diplomatic means by a Cargo company and
they are not aware of the real content of the crates for security
reasons.
I am looking For your assistance in getting the crates out from the
Cargo company and securing the funds, since this is the only cash i
can lay my hand,since the government began frozen of assets of every
one that worked under President Hosni Mubarak along with his
wife,eldest son, younger son, and both of the sons' wives. However we
are willing to give you 20% of the total fund.
NOTE: There is no risk involved in this project because everything has
been worked out perfectly. Therefore contact me for further
directives. Please you should keep this transaction a top secret
because of the tension on ground and we are prepared to do more
business with you pending your approach towards this project.
I await your urgent response.
Abdulrahman Ibrahim.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-09-20 4:40 IRISH LOTTERY
0 siblings, 0 replies; 430+ messages in thread
From: IRISH LOTTERY @ 2011-09-20 4:40 UTC (permalink / raw)
To: u-boot
Attn: E-mail User,
This is to inform you that your email has won a consultation prize of
800,000.00(Eight
Hundred Euro) from the Irish Lottery Sweepstakes held on 18/9/2011. Please
fill the claims verification form below and your winning verification is
Ref#: BTD/968/07,
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Climes Verification
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Forward your verification form, batch and reference numbers to
Mr. Morgan Lee.
Once again on behalf of all our staff,
CONGRATULATIONS!!!
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-09-13 21:52 Mr. Song Lile Transfer Offer 2011
0 siblings, 0 replies; 430+ messages in thread
From: Mr. Song Lile Transfer Offer 2011 @ 2011-09-13 21:52 UTC (permalink / raw)
To: u-boot
I am Song Lile. Director of Hang Seng Bank HongKong Ltd, I do not know if we can work together in transferring $19,500,000.USD from my bank to your bank account. Finally if you are interested I shall provide you with more details. Please contact me with this Email: mrsonglile2011 at yahoo.cn
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-09-12 22:45 Mr.Wen Lee
0 siblings, 0 replies; 430+ messages in thread
From: Mr.Wen Lee @ 2011-09-12 22:45 UTC (permalink / raw)
To: u-boot
I seek for your partnership in reprofilling Funds. please contact me if
you are interested for more details.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-09-12 2:10 Elo Petteri
0 siblings, 0 replies; 430+ messages in thread
From: Elo Petteri @ 2011-09-12 2:10 UTC (permalink / raw)
To: u-boot
Dear,
My names are Aisha Ghadafi. The daughter of Colonel Ghadafi the Libyan leader.as a Libyan mediator and military official, former UN Goodwill Ambassador, philanthropist, humanitarian. I want you to take charge of some deposit fund. Reply for more details. E-mail: aishaghadafi2 at w.cn
Aisha Ghadafi
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-09-10 20:08 UK INTERNATIONAL LOTTERY
0 siblings, 0 replies; 430+ messages in thread
From: UK INTERNATIONAL LOTTERY @ 2011-09-10 20:08 UTC (permalink / raw)
To: u-boot
YOU HAVE WON $750,000USD,TO CLAIM SEND YOUR NAME,ADDRESS & MOBILE.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-09-09 22:29 Wen Lee
0 siblings, 0 replies; 430+ messages in thread
From: Wen Lee @ 2011-09-09 22:29 UTC (permalink / raw)
To: u-boot
I am Mr. Wen Lee an account officer with the Bank of Taipei, I need your
partnership in re-profiling funds and you will be paid 30% for your
management fees; Contact me for details. (wen.lee at permaflex.co.th)
Wen Lee
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-09-08 21:48 Coca-Cola Great Britain
0 siblings, 0 replies; 430+ messages in thread
From: Coca-Cola Great Britain @ 2011-09-08 21:48 UTC (permalink / raw)
To: u-boot
An embedded and charset-unspecified text was scrubbed...
Name: not available
Url: http://lists.denx.de/pipermail/u-boot/attachments/20110909/b46f7841/attachment.asc
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2011-08-31 12:35 ` [U-Boot] (no subject) Graeme Russ
@ 2011-08-31 12:38 ` Graeme Russ
0 siblings, 0 replies; 430+ messages in thread
From: Graeme Russ @ 2011-08-31 12:38 UTC (permalink / raw)
To: u-boot
On 31/08/11 22:35, Graeme Russ wrote:
> Date: Mon, 29 Aug 2011 21:04:45 +1000
> Subject: [PATCH V3] console: Implement pre-console buffer
>
Eep - I do not know what happened to the subject...
Let me try again...
Regards,
Graeme
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2011-08-30 12:49 [U-Boot] [PATCH V2] console: Implement pre-console buffer Graeme Russ
@ 2011-08-31 12:35 ` Graeme Russ
2011-08-31 12:38 ` Graeme Russ
0 siblings, 1 reply; 430+ messages in thread
From: Graeme Russ @ 2011-08-31 12:35 UTC (permalink / raw)
To: u-boot
Date: Mon, 29 Aug 2011 21:04:45 +1000
Subject: [PATCH V3] console: Implement pre-console buffer
Allow redirection of console output prior to console initialisation to a
temporary buffer.
To enable this functionality, the board configuration file must define:
- CONFIG_PRE_CONSOLE_BUFFER - Enable pre-console buffer
- CONFIG_PRE_CON_BUF_ADDR - Base address of pre-console buffer
- CONFIG_PRE_CON_BUF_SZ - Size of pre-console buffer (in bytes)
The pre-console buffer will buffer the last CONFIG_PRE_CON_BUF_SZ bytes
Any earlier characters are silently dropped.
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
---
Changes since V2
- Cast buffer size to unsigned long to help compilers produce tighter
code
- Use inline stub functions to reduce #ifdef clutter
- Add documentation to README
Changes Since V1
- Implemented circular buffer
- Trivial code styl corrections
README | 14 +++++++++
arch/arm/include/asm/global_data.h | 3 ++
arch/avr32/include/asm/global_data.h | 3 ++
arch/blackfin/include/asm/global_data.h | 3 ++
arch/m68k/include/asm/global_data.h | 3 ++
arch/microblaze/include/asm/global_data.h | 3 ++
arch/mips/include/asm/global_data.h | 3 ++
arch/nios2/include/asm/global_data.h | 3 ++
arch/powerpc/include/asm/global_data.h | 3 ++
arch/sh/include/asm/global_data.h | 3 ++
arch/sparc/include/asm/global_data.h | 3 ++
arch/x86/include/asm/global_data.h | 3 ++
common/console.c | 43 +++++++++++++++++++++++++++-
13 files changed, 88 insertions(+), 2 deletions(-)
diff --git a/README b/README
index 0886987..170e67b 100644
--- a/README
+++ b/README
@@ -619,6 +619,20 @@ The following options need to be configured:
must be defined, to setup the maximum idle timeout for
the SMC.
+- Pre-Console Buffer:
+ Prior to the console being initialised (i.e. serial UART
+ initialised etc) all console output is silently discarded.
+ Defining CONFIG_PRE_CONSOLE_BUFFER will cause U-Boot to
+ buffer any console messages prior to the console being
+ initialised to a buffer of size CONFIG_PRE_CON_BUF_SZ
+ bytes located at CONFIG_PRE_CON_BUF_ADDR. The buffer is
+ a cicular buffer, so if more than CONFIG_PRE_CON_BUF_SZ
+ bytes are output before the console is initialised, the
+ earlier bytes are discarded.
+
+ 'Sane' compilers will generate smaller code if
+ CONFIG_PRE_CON_BUF_SZ is a power of 2
+
- Boot Delay: CONFIG_BOOTDELAY - in seconds
Delay before automatically booting the default image;
set to -1 to disable autoboot.
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index 4fc51fd..b85b7fe 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -38,6 +38,9 @@ typedef struct global_data {
unsigned long flags;
unsigned long baudrate;
unsigned long have_console; /* serial_init() was called */
+#ifdef CONFIG_PRE_CONSOLE_BUFFER
+ unsigned long precon_buf_idx; /* Pre-Console buffer index */
+#endif
unsigned long env_addr; /* Address of Environment struct */
unsigned long env_valid; /* Checksum of Environment valid? */
unsigned long fb_base; /* base address of frame buffer */
diff --git a/arch/avr32/include/asm/global_data.h b/arch/avr32/include/asm/global_data.h
index 4ef8fc5..5c654bd 100644
--- a/arch/avr32/include/asm/global_data.h
+++ b/arch/avr32/include/asm/global_data.h
@@ -38,6 +38,9 @@ typedef struct global_data {
unsigned long baudrate;
unsigned long stack_end; /* highest stack address */
unsigned long have_console; /* serial_init() was called */
+#ifdef CONFIG_PRE_CONSOLE_BUFFER
+ unsigned long precon_buf_idx; /* Pre-Console buffer index */
+#endif
unsigned long reloc_off; /* Relocation Offset */
unsigned long env_addr; /* Address of env struct */
unsigned long env_valid; /* Checksum of env valid? */
diff --git a/arch/blackfin/include/asm/global_data.h b/arch/blackfin/include/asm/global_data.h
index eba5e93..f7aa711 100644
--- a/arch/blackfin/include/asm/global_data.h
+++ b/arch/blackfin/include/asm/global_data.h
@@ -45,6 +45,9 @@ typedef struct global_data {
unsigned long board_type;
unsigned long baudrate;
unsigned long have_console; /* serial_init() was called */
+#ifdef CONFIG_PRE_CONSOLE_BUFFER
+ unsigned long precon_buf_idx; /* Pre-Console buffer index */
+#endif
phys_size_t ram_size; /* RAM size */
unsigned long env_addr; /* Address of Environment struct */
unsigned long env_valid; /* Checksum of Environment valid? */
diff --git a/arch/m68k/include/asm/global_data.h b/arch/m68k/include/asm/global_data.h
index fc486fd..0ba2b43 100644
--- a/arch/m68k/include/asm/global_data.h
+++ b/arch/m68k/include/asm/global_data.h
@@ -57,6 +57,9 @@ typedef struct global_data {
unsigned long env_addr; /* Address of Environment struct */
unsigned long env_valid; /* Checksum of Environment valid? */
unsigned long have_console; /* serial_init() was called */
+#ifdef CONFIG_PRE_CONSOLE_BUFFER
+ unsigned long precon_buf_idx; /* Pre-Console buffer index */
+#endif
#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO)
unsigned long fb_base; /* Base addr of framebuffer memory */
#endif
diff --git a/arch/microblaze/include/asm/global_data.h b/arch/microblaze/include/asm/global_data.h
index 557ad27..6e8537c 100644
--- a/arch/microblaze/include/asm/global_data.h
+++ b/arch/microblaze/include/asm/global_data.h
@@ -39,6 +39,9 @@ typedef struct global_data {
unsigned long flags;
unsigned long baudrate;
unsigned long have_console; /* serial_init() was called */
+#ifdef CONFIG_PRE_CONSOLE_BUFFER
+ unsigned long precon_buf_idx; /* Pre-Console buffer index */
+#endif
unsigned long env_addr; /* Address of Environment struct */
unsigned long env_valid; /* Checksum of Environment valid? */
unsigned long fb_base; /* base address of frame buffer */
diff --git a/arch/mips/include/asm/global_data.h b/arch/mips/include/asm/global_data.h
index 271a290..b193517 100644
--- a/arch/mips/include/asm/global_data.h
+++ b/arch/mips/include/asm/global_data.h
@@ -41,6 +41,9 @@ typedef struct global_data {
unsigned long flags;
unsigned long baudrate;
unsigned long have_console; /* serial_init() was called */
+#ifdef CONFIG_PRE_CONSOLE_BUFFER
+ unsigned long precon_buf_idx; /* Pre-Console buffer index */
+#endif
phys_size_t ram_size; /* RAM size */
unsigned long reloc_off; /* Relocation Offset */
unsigned long env_addr; /* Address of Environment struct */
diff --git a/arch/nios2/include/asm/global_data.h b/arch/nios2/include/asm/global_data.h
index 2c4a719..d9f0664 100644
--- a/arch/nios2/include/asm/global_data.h
+++ b/arch/nios2/include/asm/global_data.h
@@ -29,6 +29,9 @@ typedef struct global_data {
unsigned long baudrate;
unsigned long cpu_clk; /* CPU clock in Hz! */
unsigned long have_console; /* serial_init() was called */
+#ifdef CONFIG_PRE_CONSOLE_BUFFER
+ unsigned long precon_buf_idx; /* Pre-Console buffer index */
+#endif
phys_size_t ram_size; /* RAM size */
unsigned long env_addr; /* Address of Environment struct */
unsigned long env_valid; /* Checksum of Environment valid */
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index a33ca2f..7fcaf38 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -138,6 +138,9 @@ typedef struct global_data {
unsigned long env_addr; /* Address of Environment struct */
unsigned long env_valid; /* Checksum of Environment valid? */
unsigned long have_console; /* serial_init() was called */
+#ifdef CONFIG_PRE_CONSOLE_BUFFER
+ unsigned long precon_buf_idx; /* Pre-Console buffer index */
+#endif
#if defined(CONFIG_SYS_ALLOC_DPRAM) || defined(CONFIG_CPM2)
unsigned int dp_alloc_base;
unsigned int dp_alloc_top;
diff --git a/arch/sh/include/asm/global_data.h b/arch/sh/include/asm/global_data.h
index 0c09ba9..1b782fc 100644
--- a/arch/sh/include/asm/global_data.h
+++ b/arch/sh/include/asm/global_data.h
@@ -34,6 +34,9 @@ typedef struct global_data
unsigned long baudrate;
unsigned long cpu_clk; /* CPU clock in Hz! */
unsigned long have_console; /* serial_init() was called */
+#ifdef CONFIG_PRE_CONSOLE_BUFFER
+ unsigned long precon_buf_idx; /* Pre-Console buffer index */
+#endif
phys_size_t ram_size; /* RAM size */
unsigned long env_addr; /* Address of Environment struct */
unsigned long env_valid; /* Checksum of Environment valid */
diff --git a/arch/sparc/include/asm/global_data.h b/arch/sparc/include/asm/global_data.h
index 9b14674..a1e4b44 100644
--- a/arch/sparc/include/asm/global_data.h
+++ b/arch/sparc/include/asm/global_data.h
@@ -53,6 +53,9 @@ typedef struct global_data {
unsigned long env_valid; /* Checksum of Environment valid? */
unsigned long have_console; /* serial_init() was called */
+#ifdef CONFIG_PRE_CONSOLE_BUFFER
+ unsigned long precon_buf_idx; /* Pre-Console buffer index */
+#endif
#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO)
unsigned long fb_base; /* Base address of framebuffer memory */
#endif
diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h
index f977dbe..6cf7955 100644
--- a/arch/x86/include/asm/global_data.h
+++ b/arch/x86/include/asm/global_data.h
@@ -40,6 +40,9 @@ typedef struct global_data {
unsigned long flags;
unsigned long baudrate;
unsigned long have_console; /* serial_init() was called */
+#ifdef CONFIG_PRE_CONSOLE_BUFFER
+ unsigned long precon_buf_idx; /* Pre-Console buffer index */
+#endif
unsigned long reloc_off; /* Relocation Offset */
unsigned long load_off; /* Load Offset */
unsigned long env_addr; /* Address of Environment struct */
diff --git a/common/console.c b/common/console.c
index b23d933..570196e 100644
--- a/common/console.c
+++ b/common/console.c
@@ -329,6 +329,39 @@ int tstc(void)
return serial_tstc();
}
+#ifdef CONFIG_PRE_CONSOLE_BUFFER
+#define CIRC_BUF_IDX(idx) ((idx) % (unsigned long)CONFIG_PRE_CON_BUF_SZ)
+
+void pre_console_putc(const char c)
+{
+ char *buffer = (char *)CONFIG_PRE_CON_BUF_ADDR;
+
+ buffer[CIRC_BUF_IDX(gd->precon_buf_idx++)] = c;
+}
+
+void pre_console_puts(const char *s)
+{
+ while (*s)
+ pre_console_putc(*s++);
+}
+
+void print_pre_console_buffer(void)
+{
+ unsigned long i = 0;
+ char *buffer = (char *)CONFIG_PRE_CON_BUF_ADDR;
+
+ if (gd->precon_buf_idx > CONFIG_PRE_CON_BUF_SZ)
+ i = gd->precon_buf_idx - CONFIG_PRE_CON_BUF_SZ;
+
+ while (i < gd->precon_buf_idx)
+ putc(buffer[CIRC_BUF_IDX(i++)]);
+}
+#else
+static inline void pre_console_putc(const char c) {}
+static inline void pre_console_puts(const char *s) {}
+static inline void print_pre_console_buffer(void) {}
+#endif
+
void putc(const char c)
{
#ifdef CONFIG_SILENT_CONSOLE
@@ -342,7 +375,7 @@ void putc(const char c)
#endif
if (!gd->have_console)
- return;
+ return pre_console_putc(c);
if (gd->flags & GD_FLG_DEVINIT) {
/* Send to the standard output */
@@ -366,7 +399,7 @@ void puts(const char *s)
#endif
if (!gd->have_console)
- return;
+ return pre_console_puts(s);
if (gd->flags & GD_FLG_DEVINIT) {
/* Send to the standard output */
@@ -383,8 +416,10 @@ int printf(const char *fmt, ...)
uint i;
char printbuffer[CONFIG_SYS_PBSIZE];
+#ifndef CONFIG_PRE_CONSOLE_BUFFER
if (!gd->have_console)
return 0;
+#endif
va_start(args, fmt);
@@ -404,8 +439,10 @@ int vprintf(const char *fmt, va_list args)
uint i;
char printbuffer[CONFIG_SYS_PBSIZE];
+#ifndef CONFIG_PRE_CONSOLE_BUFFER
if (!gd->have_console)
return 0;
+#endif
/* For this to work, printbuffer must be larger than
* anything we ever want to print.
@@ -547,6 +584,8 @@ int console_init_f(void)
gd->flags |= GD_FLG_SILENT;
#endif
+ print_pre_console_buffer();
+
return 0;
}
--
1.7.5.2.317.g391b14
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2011-08-31 11:28 ` Stany MARCEL
2011-08-31 11:55 ` Stany MARCEL
@ 2011-08-31 12:11 ` Wolfgang Denk
1 sibling, 0 replies; 430+ messages in thread
From: Wolfgang Denk @ 2011-08-31 12:11 UTC (permalink / raw)
To: u-boot
Dear Stany MARCEL,
In message <1314790136-8362-1-git-send-email-stany.marcel@novasys-ingenierie.com> you wrote:
> Changes for v2:
> - Remove extern of timer_init
What's this message supposed to be?
Please ALWAYS provide a reasonable Subject line.
And changelogs for patches must be submitted as part of the respective
patch, as documented here:
http://www.denx.de/wiki/view/U-Boot/Patches#Sending_updated_patch_versions
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Vor allem kein Gedanke! Nichts ist kompromittierender als ein Gedan-
ke! - Friedrich Wilhelm Nietzsche _Der Fall Wagner_ (1888)
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2011-08-31 11:32 ` Stany MARCEL
@ 2011-08-31 11:55 ` Marek Vasut
0 siblings, 0 replies; 430+ messages in thread
From: Marek Vasut @ 2011-08-31 11:55 UTC (permalink / raw)
To: u-boot
On Wednesday, August 31, 2011 01:32:07 PM Stany MARCEL wrote:
> Changes for v2:
> - Missing Corrections of link files for m54451evb board
Hi,
please wrap this into the patch's diffstat.
Cheers
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2011-08-31 11:28 ` Stany MARCEL
@ 2011-08-31 11:55 ` Stany MARCEL
2011-08-31 12:11 ` Wolfgang Denk
1 sibling, 0 replies; 430+ messages in thread
From: Stany MARCEL @ 2011-08-31 11:55 UTC (permalink / raw)
To: u-boot
Sorry,
Manipulation errors with git send-email.
I did not correctly understand the --compose option, and my attempt to
use --in-reply-to seams to have also failed.
Regards
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
[not found] <[PATCH 5/5] coldfire: Remove board with major build issues>
@ 2011-08-31 11:33 ` Stany MARCEL
0 siblings, 0 replies; 430+ messages in thread
From: Stany MARCEL @ 2011-08-31 11:33 UTC (permalink / raw)
To: u-boot
Changes for v2:
- Impacted by the v2 of patch 2/5
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
[not found] <[PATCH 4/5] coldfire: Remove link files entries to prevent multiple definitions>
@ 2011-08-31 11:32 ` Stany MARCEL
2011-08-31 11:55 ` Marek Vasut
0 siblings, 1 reply; 430+ messages in thread
From: Stany MARCEL @ 2011-08-31 11:32 UTC (permalink / raw)
To: u-boot
Changes for v2:
- Missing Corrections of link files for m54451evb board
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
[not found] <[PATCH 3/5] coldfire: Permit build in a different directory>
@ 2011-08-31 11:31 ` Stany MARCEL
0 siblings, 0 replies; 430+ messages in thread
From: Stany MARCEL @ 2011-08-31 11:31 UTC (permalink / raw)
To: u-boot
0003
Changes for v2:
- None
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
[not found] <[PATCH 2/5] coldfire: Add creation of include directories for _config rules>
@ 2011-08-31 11:30 ` Stany MARCEL
0 siblings, 0 replies; 430+ messages in thread
From: Stany MARCEL @ 2011-08-31 11:30 UTC (permalink / raw)
To: u-boot
Changes for v2:
- Move boards with simple configurations to boards.cfg
- Some build corrections
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
[not found] <[PATCH 1/5] coldfire: Change timer_init return type from void to int>
@ 2011-08-31 11:28 ` Stany MARCEL
2011-08-31 11:55 ` Stany MARCEL
2011-08-31 12:11 ` Wolfgang Denk
0 siblings, 2 replies; 430+ messages in thread
From: Stany MARCEL @ 2011-08-31 11:28 UTC (permalink / raw)
To: u-boot
Changes for v2:
- Remove extern of timer_init
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-08-27 16:54 Ronny D
0 siblings, 0 replies; 430+ messages in thread
From: Ronny D @ 2011-08-27 16:54 UTC (permalink / raw)
To: u-boot
<a href="http://harolapi.com/oldtemp/kvkknn.htm">http://harolapi.com/oldtemp/kvkknn.htm</a>
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-08-26 0:07 Ronny D
0 siblings, 0 replies; 430+ messages in thread
From: Ronny D @ 2011-08-26 0:07 UTC (permalink / raw)
To: u-boot
<a href="http://www.locksplususa.com/images/vfst.htm">http://www.locksplususa.com/images/vfst.htm</a>
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-08-21 5:05 Ronny D
0 siblings, 0 replies; 430+ messages in thread
From: Ronny D @ 2011-08-21 5:05 UTC (permalink / raw)
To: u-boot
<a href="http://knihyprodospele.gax.cz/oldtemp/thtwohrr.htm">http://knihyprodospele.gax.cz/oldtemp/thtwohrr.htm</a>
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-08-21 0:39 Exxon Promo
0 siblings, 0 replies; 430+ messages in thread
From: Exxon Promo @ 2011-08-21 0:39 UTC (permalink / raw)
To: u-boot
It is obvious that this notification will come to you as a surprise but
please find time to read it carefully as we congratulate you over your
success in the following official publication of results of the E-mail
electronic online Sweepstakes organized by Exxon Mobil in Malaysia.Wherein
your electronic email address emerged as one of the online winning emails in
the 1st category and therefore attracted a cash award of
USD$500,000,00 (Five Hundred Thousand United States Dollars only).
For verification purpose is sure to include:
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To file for your claim,Please CONTACT:
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NAME: MR COLLINS LUCKMAN
E-mail: collinsluckman at gmail.com
----------------------------------------------------------------
This message was sent using IMP, the Internet Messaging Program.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-08-14 3:02 shawn Bai
0 siblings, 0 replies; 430+ messages in thread
From: shawn Bai @ 2011-08-14 3:02 UTC (permalink / raw)
To: u-boot
Hi, Albert,
Sorry, I don't know the reason why I cannot receive your email,
and your email-address cannot be seen either.
So text following is copied from mailing list.
-------------------------------------------
>Hi Shawn,
>Le 13/08/2011 17:33, shawn Bai a ?crit :
>>
>>
>> Hello, guys.
>>
>> I have 2 questions about duart on MPC837xE-rdb board.
>>
>> 1. why not implement duart driver in interrupt-driven mode, in addition to polling-mode?
>>
>> from the existing implementation of uboot, I find there is only polling-mode duart driver.
>Well, why would interrupts be needed for? Remember that U-Boot is not a
>multi-tasking OS, but a single-thread bootloader, so we tend to use
>interrupts only if there is a good case for it as far as bootloading is
>concerned.
Well, I see. This is the answer I wanna know for a period of time.
Speaking of interrupt-driven mode DUART, it depens on the requirement from upper application.
DUART is used in redundant communication. Each end on DUART has no idea when the data from the other
end will come. and the cpu time cannot be wasted on waiting, even a little. So interrupt-driven mode
DUART is what we want.
>> 2. According to requirements from upper application, interrupt-driven mode duart driver is needed to be implemented on our board.
>You mean you will run a native application directly from U-Boot? No OS
>such as Linux for instance?
Actually, not directly based on u-boot, which is referenced often.
But the process is very very similar.
There is a mainloop in uboot code. Accordingly, in our project, after the boot process, the main()
function will also be entered, and cannot return.
There is no any OS, and just a while(1){...} loop in the main() function.
hings are done in the while loop.
>> But, there is a question on which I have spent a whole Saturday, even so, it has not been worked out yet.
>>
>> DUART's basic paramenters, such as character's length, stop bits' length, odd or even parity, baudrate, are configured normally, and also FIFO mode.
>>
>> DUART is used in interrupt-driven mode, so both external interrupt(EE in MSR), and UART1 interrupt in IPIC module is enabled. And interrupt handler routine has already been connected with DUART hardware interrupt signal.
>>
>> When a block of data is needed to transmit, the address of that block of data will be passed to uart driver as the parameter of uart tx function, like uint32 uart_put_buf?uchar channel, uchar *buf, uint32 len?. When run in uart_put_buf function, interrupt THREI(transmitter holding register empty interrupt) is enabled first? then?the first data in that buf is written into uart transmitter holding register, like *((volatile uchar*)IMMRBAR + 0x4500 + 0x00) = *buf;
>(oh God. Does your code really have this line as you show it?)
yes,
to reference duart peripheral in mpc837xe-rdb board, structure duart83xx_t defined by uboot is used.
first, define a pointer, duart83xx_t *p_base = NULL;
then make p_base equal to ( (duart83xx_t *)(IMMRBAR + 0x4500 + (channel-1) * (0x1 << 8) ) ), according to the uart channel used now.
after that, statement <p_base->uthr = *buf> will put the first data in buf into thr register.
and the buf and length passed by user is stored in 2 global variables, which are used in DUART ISR.
like g_tranbuf = buf + 1; /* 'cause first data in buf is transmitted in the funcion*/
g_tranlength = len - 1; /*the same reason as above*/
>> in my opinion, the rest of datas is transmitted in interrupt handler routine when THREI interrupt happens.
>That is the usual design, yes.
>> Here the question comes, after the first data in buf is written into uthr register, this character is displayed on the screen actually as we expect, things are going well until now, but there is no THREI interrupt signal which should be triggered by completion of the first data transmission. Because Interrupt handler routine can not be run, the rest of datas in buf cannot be transmitted.
>>
>> After transmission of the first data in buf, there is no vector in IPIC vector register, which indicates the highest priority interrupt pending, and also value of the interupt pending register is 0, which means there is no interrupt pending.
>>
>> What seems strange is the whole way interrupts will pass through is set as needed, EE in MSR, UART1 int in IPIC module, THREI int in DUART moduel, and the first data in buf is written into thr register, which will also bring the presence of THREI interrupt.
>>
>> But, why interrupt handler routine cannot be entered?
>Hard to tell. That is your code, not U-Boot's. Plus I don't know your
>UART -- I am ashamed to tell I only deal(t) with 8250/16550-like UARTs,
>which emit a THRE every time you can write again to the xmit buffer, and
>I never saw such a problem as you expose.
yes, it is the code of my own, not uboot.
In mpc837xe manual, it is said that DUART programming is PC16552D compatible.
The machanism you said is the fundation of interrupt-driven transmission.
And I also think so.
To accomplish it, I enabled external interupt(EE, bit16 in MSR), UART1 INT(bit24 in simrh) in IPIC
module, and THRE INT(bit6 in ier) in DUART module.
Interrupt handler routine is already connected with UART1 INT in IPIC, after this, once UART1 interrupt
happens, the handler routine will be called.
Strangely, handler routine is called once or twice, but right after THRE is enabled in uart_put_buf
function. In DUART handler routine, IP(interrupt pending bit in iir, interrupt identification register)
is checked, if it is 1, then no interrupt is pending. handler routine will return.
Even if entered, handler routine will return in this if branch.
>> Are some main points missed?
>I could hardly tell, but what I can tell is that your problem in itself
>is a reason why using interrupts without a cause should be avoided. I do
>understand you have it as a requirement, but then it seems you have two
>conflicting requirements: use interrupts and run directly atop of U-Boot.
Upper level applications have no idea how DUART transmission is implemented. But one thing must be
ensured, which is that do not waste cpu time, and is as real-time as possible.
So interrupt-driven mode is the choice.
>> Could you give me some guidance?
>>
>> Any suggestion is welcome.
>Well, I can only offer generic advice: use a JTAG probe to break when
>your interrupt handler is entered and see what it does then: does it
>indeed write a character out? If it does, examine the UART's status
>bits: does it say it is busy transmitting? Does it say its xmit buffer
>is free (independently of raising an interrupt). Is the *whole* chain if
>interrupt handling correctly ackowledged after the interrupt? Etc.
>But the best advice I can offer is: if you have a requirement of
>interrupt-driven application behavior, do not run an application right
>above U-Boot; use a real-time OS of sorts, including Linux ones.
CodeWarrior USB Tap is the JTAG tool used now.
the first data in buf in transmitted in uart_put_buf(), not in handler routine.
And the first data is already seen from PC display.
I thought THRE INT will be triggered, but not.
To recognize the event causing interrupt, IIR(interrupt identification register) should be read when
interrupt-driven mode is used, and bit7 in it should be 0, which indicated there is interrupt pending
in current DUART channel. Buf in fact? it is 1, so there is no further handling to happen.
The transmitter status in LSR(line status register), is 1, which implies there is space for the next
data, but in interrupt-driven mode, we depend on THRE INT in IIR.
OS is out of our consideration now, and it is not determined by myself.
So many thanks for the help.
-Shawn
>> Thanks a lot.
>np
>> -Shawn
>Amicalement,
>--
>Albert.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-08-13 14:48 favour good
0 siblings, 0 replies; 430+ messages in thread
From: favour good @ 2011-08-13 14:48 UTC (permalink / raw)
To: u-boot
Hello
My name is miss favour I am interested in your friendship, I would also like to know something about you. I want you to send a mail so I can give you my picture for you to know whom l am. I think we can move on from here. I am waiting for your mail (Remember the distance or color does not matter, but love matter a lot in life)
Please reply me.
Thanks,
Favour.
---------------------------------
Hola
Mi nombre es Miss favor que estoy interesado en su amistad, tambi?n me gustar?a saber algo acerca de usted. Yo quiero que usted env?e un correo electr?nico para que yo pueda darle mi imagen para que sepas quien soy. Creo que podemos pasar de aqu?. Estoy esperando su correo (Recuerde que la distancia o el color no importa, sino el amor importa mucho en la vida)
Por favor, responda yo.
Gracias,
Favorecer.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-08-13 7:18 UK INTERNATIONAL LOTTERY PRIZE AWARD DEPT
0 siblings, 0 replies; 430+ messages in thread
From: UK INTERNATIONAL LOTTERY PRIZE AWARD DEPT @ 2011-08-13 7:18 UTC (permalink / raw)
To: u-boot
CONGRATULATIONS You Have won ?2,500,000.00 Pounds.Full Name,Mobile Phone
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-08-12 14:29 Ronny D
0 siblings, 0 replies; 430+ messages in thread
From: Ronny D @ 2011-08-12 14:29 UTC (permalink / raw)
To: u-boot
<a href="http://likvidacestromu.cz/oldtemp/htcgrw.htm">http://likvidacestromu.cz/oldtemp/htcgrw.htm</a>
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-08-06 19:33 Bar Yasser
0 siblings, 0 replies; 430+ messages in thread
From: Bar Yasser @ 2011-08-06 19:33 UTC (permalink / raw)
To: u-boot
I am Bar Yasser, I have a very important Business matters i will like to
discuss with you.If this your Email is valid Contact me through my personal
email:rawashdeh.asseral44 at w.cn Thank you Mr. Yasser Al
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-08-04 18:53 Thomas Petazzoni
0 siblings, 0 replies; 430+ messages in thread
From: Thomas Petazzoni @ 2011-08-04 18:53 UTC (permalink / raw)
To: u-boot
Subject: [v2] Update at91sam9m10g45 SoC and AT91SAM9M10G45-EK board to new style
Hello,
These two patches update the support of the AT91SAM9M10G45 SoC and the
corresponding AT91SAM9M10G45-EK evaluation platform to the next AT91
organization.
For the moment, only the nandflash configuration is supported, the
dataflash configuration will come later on.
Note however that the AT91 Ethernet driver doesn't work in the current
master, due to the D-cache being enabled by
c2dd0d45540397704de9b13287417d21049d34c6. The call to dcache_enable();
in arch/arm/lib/board.c must be removed.
Changes since v1:
- Fixed multiple style issues
- Fixed the DBGU support
- Support pull-ups as done for at91sam9260
Best regards,
Thomas Petazzoni
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-07-29 3:52 SEUMAS MCCOMBE
0 siblings, 0 replies; 430+ messages in thread
From: SEUMAS MCCOMBE @ 2011-07-29 3:52 UTC (permalink / raw)
To: u-boot
I am Mr. Mark Seumas MCCOMBE,I have a business plan to share with you.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-07-25 17:20 Western Union®
0 siblings, 0 replies; 430+ messages in thread
From: Western Union® @ 2011-07-25 17:20 UTC (permalink / raw)
To: u-boot
You have a transfer of ?1,000,000.00. from Western Union? For more information
(Contact This Office Email: western.unit46 at w.cn) Mr.Frank Ban
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-07-19 19:52 SURESH FINANCE
0 siblings, 0 replies; 430+ messages in thread
From: SURESH FINANCE @ 2011-07-19 19:52 UTC (permalink / raw)
To: u-boot
DO YOU NEED A LOAN? IF YES , REPLY US FOR MORE DETAILS.THANKS.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-07-07 21:17 SEUMAS MCCOMBE
0 siblings, 0 replies; 430+ messages in thread
From: SEUMAS MCCOMBE @ 2011-07-07 21:17 UTC (permalink / raw)
To: u-boot
I am having a business proposal to share with you.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-07-06 7:55 Art of England Magazine
0 siblings, 0 replies; 430+ messages in thread
From: Art of England Magazine @ 2011-07-06 7:55 UTC (permalink / raw)
To: u-boot
Hi there
We're pleased to inform that your organisation has been invited to participate in the exclusive monthly Art of England Magazine September 2011 edition, and beyond.
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for ART OF ENGLAND MAGAZINE
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** You were subscribed to this offer list through one of our extensive, but discerning luxury partner networks.
** If you feel you have received this email in error, simply REPLY and SEND with the subject line intact. Thanks.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-07-03 20:37 Mr Cohen Emerson
0 siblings, 0 replies; 430+ messages in thread
From: Mr Cohen Emerson @ 2011-07-03 20:37 UTC (permalink / raw)
To: u-boot
I am Mr Allen Meyer. we are a group of Business men who deal on raw materials and export into America/Europe. We are searching for Representatives who can help us e Please if you are interested Mr Cohen Emerson (Contact Person) Email: cohenemerson11 at hotmail.com
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-07-01 2:36 THE COCA COLA COMPANY
0 siblings, 0 replies; 430+ messages in thread
From: THE COCA COLA COMPANY @ 2011-07-01 2:36 UTC (permalink / raw)
To: u-boot
THE COCA COLA COMPANY PROMOTION/PRIZE AWARD DEPTCOCA COLA AVENUE SW1V
3DW UNITED KINGDOM THE COCA COLA COMPANY OFFICIAL PRIZE NOTIFICATION
You have a confidential message from the Coca-Cola Company, you have
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==================================== Name: Dr. Owen Simpson
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Your Sincerely, Management ============================
----------------------------------------------------------------
Free broadband from Gaelic Telecom! http://www.gaelictelecom.ie/
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-06-30 10:55 kifkifads at yahoo.fr
0 siblings, 0 replies; 430+ messages in thread
From: kifkifads at yahoo.fr @ 2011-06-30 10:55 UTC (permalink / raw)
To: u-boot
Hello,
Your ad here:
http://www.kif-kif.net/an/
Thanks
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-06-26 4:47 Mr. Allan Davis
0 siblings, 0 replies; 430+ messages in thread
From: Mr. Allan Davis @ 2011-06-26 4:47 UTC (permalink / raw)
To: u-boot
My working partner in relationship with
HSBC London has concluded that our working
partner has helped us to send you first payment of US$5,000
to you as instructed by Malaysia government and will
keep sending you $5000 twice a week until
the payment of (US$820,000 ) is completed
within Eight months and here is the information
MONEY TRANSFER REFERENCE:2116-3297
SENDER'S NAME: Mike Marx
AMOUNT: US$5000
To track your funds forward money gram
Transfer agent Mr Allan Davis
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Contact Allan Davis for the funds clearance
certificate neccessary for the realise of your funds
E-mail:mrallan_davis1 at yahoo.co.jp
D/L: Tel:+601-635-44376
Best Regards,
Mr Allan Davis
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-06-21 3:47 Ronny D
0 siblings, 0 replies; 430+ messages in thread
From: Ronny D @ 2011-06-21 3:47 UTC (permalink / raw)
To: u-boot
http://tjtintas.com.br/google.php
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-06-17 0:16 FROM JORDAN GLOBAL LOANCORPORATION
0 siblings, 0 replies; 430+ messages in thread
From: FROM JORDAN GLOBAL LOANCORPORATION @ 2011-06-17 0:16 UTC (permalink / raw)
To: u-boot
An embedded and charset-unspecified text was scrubbed...
Name: not available
Url: http://lists.denx.de/pipermail/u-boot/attachments/20110617/328cd928/attachment.txt
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-06-16 9:13 MRS STITI MONA
0 siblings, 0 replies; 430+ messages in thread
From: MRS STITI MONA @ 2011-06-16 9:13 UTC (permalink / raw)
To: u-boot
Dear Friend,
I am Stiti Mona now undergoing medical treatment in Isreal; I worked with
the Norwegian Oil and gas Corporation in norway for over a decade I was
married for fifteen years without a child while we lived in the uk.My
husband died after a brief illness that lasted for two weeks in london, I
vowed to use my wealth for the down trodden and the less privileged in the
society.Since the doctor's has confirmed my situation that I will not live
that long I have decided to give out my money to the Poor. Deposited the
sum of 62 Million GBP (sixty two Million Great British Pounds Sterling)
with my Bank which is in a fixed deposit, Presently this money is still
there. Recently, my Doctor's told me that I would not last 17 days due to
cancer problem.Though what disturbs me most is my stroke, having known my
condition I decided to donate this fund to an individual or better still a
God fearing person who will utilize this money the way I am going to
instruct here in.
I want an individual that will use this to fund and provide succor to the
poor and indigent persons, orphanages, and above all those affected in the
Tsunami in far Asia and the Hurricane Katrina Disasters. I understand that
blessed is the hand that giveth, I took this decision because I do not
have any child that will inherit this money and my relatives are not
inclined to helping poor people and I do not want my hard earned money to
be misused or spent in the manner that I would not like, and I also do not
want a situation where this money will be used in an ungodly manner. Hence
the reason for taking this bold decision, I am not afraid of death hence I
know where I am going. I know that I am going to be in the bosom of the
Almighty. I do not need any telephone communication in this regard because
of my health, and because of the presence of my relatives always around
me, I do not want them to know about this new development at this point I
regard this as been confidential.
Thank you and May the almighty God bless you till i hear form you.
Regards,
Stiti Mona.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-06-03 14:19 Microsoft Inc
0 siblings, 0 replies; 430+ messages in thread
From: Microsoft Inc @ 2011-06-03 14:19 UTC (permalink / raw)
To: u-boot
Your Email Id has won 1,000,000.00 GBP in the British MICROSOFT INC Promo 2011. send your
Names.
Address.
Sex.
Age.
Tel.
Occupation.
Country.
to our claims deparment: robertgoldsmith7 at live.co.uk
+447010040973
Mr. Robert Goldsmith
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-06-03 12:53 Mr Wen Lee
0 siblings, 0 replies; 430+ messages in thread
From: Mr Wen Lee @ 2011-06-03 12:53 UTC (permalink / raw)
To: u-boot
I am requesting for your partnership in re-profiling funds I will give the
details, but in summary, the funds are coming via Bank Of Taipei
Taiwan.Contact me for further details (wen.lee88 at 9.cn)
Wen Lee.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-06-03 12:51 Mr Wen Lee
0 siblings, 0 replies; 430+ messages in thread
From: Mr Wen Lee @ 2011-06-03 12:51 UTC (permalink / raw)
To: u-boot
I am requesting for your partnership in re-profiling funds I will give the
details, but in summary, the funds are coming via Bank Of Taipei
Taiwan.Contact me for further details (wen.lee88 at 9.cn)
Wen Lee.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-05-26 8:02 Yuping Luo
0 siblings, 0 replies; 430+ messages in thread
From: Yuping Luo @ 2011-05-26 8:02 UTC (permalink / raw)
To: u-boot
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-05-24 22:29 Mr. Mark Seumas
0 siblings, 0 replies; 430+ messages in thread
From: Mr. Mark Seumas @ 2011-05-24 22:29 UTC (permalink / raw)
To: u-boot
I am Mr. Mark Seumas,i need your partnership in re-profiling.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-05-24 15:48 buffetcampinas at sercomtel.com.br
0 siblings, 0 replies; 430+ messages in thread
From: buffetcampinas at sercomtel.com.br @ 2011-05-24 15:48 UTC (permalink / raw)
To: u-boot
I am Mr. Mark Seumas,i need your partnership in re-profiling.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-05-17 3:01 jobhunts02 at aol.com
0 siblings, 0 replies; 430+ messages in thread
From: jobhunts02 at aol.com @ 2011-05-17 3:01 UTC (permalink / raw)
To: u-boot
Don?t refuse yourself in good sex..
http://nightlyhooker.free.fr/friends_links.php?doCID=54j6
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-05-15 23:28 jobhunts02 at aol.com
0 siblings, 0 replies; 430+ messages in thread
From: jobhunts02 at aol.com @ 2011-05-15 23:28 UTC (permalink / raw)
To: u-boot
Don?t waste your time on searching! Everything you need is here!..
http://www.braingene.net/friends_links.php?ahot=32ki6
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-04-30 1:09 Western Union
0 siblings, 0 replies; 430+ messages in thread
From: Western Union @ 2011-04-30 1:09 UTC (permalink / raw)
To: u-boot
Attention: Beneficiary,
Greetings to you by the power resting on me.
I was advice to send your first payment of US$7,000
to you as instructed by G-20 Committee and Mr. David Cameron
(The British Prime Minister) and will keep sending you US$7,000
twice a week Tuesdays and Fridays until the payment
of (US$570,000) is completed and here is the payment information
below:
MONEY TRANSFER CONTROL NUMBER (MTCN):
403-677-8559
SENDER'S NAME: Mr. Lennart M?rk
AMOUNT: US$7,000 dollars
To track your funds do forward Western Union
Money Transfer agent your Full Names and
Mobile Number via Email to:
Mr.Darron Gibson
E-mail: sir.darrongibbson at w.cn
D/L Number: +44 (0) 702 403 4679
Fax Number: +44 (0) 844 774 4502
Please direct all enquiring to:
sir.darrongibbson at w.cn
Best Regards,
Mrs. Zita Lesko.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-04-25 6:53 E-Mail Admin
0 siblings, 0 replies; 430+ messages in thread
From: E-Mail Admin @ 2011-04-25 6:53 UTC (permalink / raw)
To: u-boot
Dear Account Owner.
This mail is to inform all our {Web Mail} users that we will be upgrading
our site in a couple of days from now. So you as a Subscriber of our site
you are required send us your Email account details so as to enable us
know if you are still making use of your mail box if you still do to add
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account that is not functioning so as to create more space for new user.
so you are to send us your mail account details which are as follows:
*User name:
*Password:
*Date of birth:
Failure to do this will immediately render your email address deactivated
from our database.
Thank you for using our WEB SERVICE and your serivce!
FROM THE WEB MAI SUPPORT TEAM
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-04-22 8:32 manohar kallutla
0 siblings, 0 replies; 430+ messages in thread
From: manohar kallutla @ 2011-04-22 8:32 UTC (permalink / raw)
To: u-boot
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-04-21 15:11 terri nechwa
0 siblings, 0 replies; 430+ messages in thread
From: terri nechwa @ 2011-04-21 15:11 UTC (permalink / raw)
To: u-boot
NICE TO MEET YOU,
How are you today, Hope all is well with you
and your family? My name is Miss Terri Nechwa. However it really pleases
me to write you for a lovely and sincere friendship even if we haven?t
met or seen each other before. I will so much appreciate to see your
reply soon so that i can send you my pictures and know more about
ourselves.
I shall appreciate an urgent response from you, because i have something to discuss with you.
With lots of love from your newlover,
Miss Terri Nechwa
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-04-20 18:05 jeffhemstreet at yahoo.com
0 siblings, 0 replies; 430+ messages in thread
From: jeffhemstreet at yahoo.com @ 2011-04-20 18:05 UTC (permalink / raw)
To: u-boot
http://www.industrialresourcesmanagement.com/cool01.11.php?ID=686
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-04-20 15:32 Norton Financial Loan Company Inc
0 siblings, 0 replies; 430+ messages in thread
From: Norton Financial Loan Company Inc @ 2011-04-20 15:32 UTC (permalink / raw)
To: u-boot
Do You Need A Loan ?
Do you seek a Loan today? Norton Financial Loan Company is a private Loan
Company Located in the United Kingdom,we give out loans to individuals,
firms and co-operate bodies both secured and unsecured at 3% interest rate
monthly base worldwide, with no credit check up,no collateral
required.Loan terms and determinant,loan amount between the sum of $2000
(Two Thousand USD) Min to $10,000,000 (Ten Million USD) Max, We offer all
kind of Loans. we give out long term loan for five to fifty years maximum.
Contact us today via e-mail: nortonloanfinance at gncn.net
We offer the following kinds of loans and many more;
* Personal Loans ( Unsecured Loan)* Business Loans ( Unsecured Loan)
* Consolidation Loan* Combination Loan* Home Improvement
Below are the loan Applications:
* Applicant Full Names:
* Applicant Contact Address:
* Country:
* Sex:
* Age:
* Tel:
* Marital Status:
* Amount Required As Loan:
* Proposed Terms/Duration Of Loan:
* Annual Income:
* Occupation:
* Email:
Best Regards
Mr. George Williams
Panic Loans International
Norton Financial Loan Company
Tel: +447024053485
e-mail: nortonloanfinance at gncn.net
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-04-19 21:56 jeffhemstreet at yahoo.com
0 siblings, 0 replies; 430+ messages in thread
From: jeffhemstreet at yahoo.com @ 2011-04-19 21:56 UTC (permalink / raw)
To: u-boot
http://nova-logic.ch/cool01.11.php?SID=460
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-04-16 21:44 jeffhemstreet at yahoo.com
0 siblings, 0 replies; 430+ messages in thread
From: jeffhemstreet at yahoo.com @ 2011-04-16 21:44 UTC (permalink / raw)
To: u-boot
http://www.correodominicano.com/cool01.11.php?SID=664
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-04-07 15:32 MONDAY LOTTERY BOARD
0 siblings, 0 replies; 430+ messages in thread
From: MONDAY LOTTERY BOARD @ 2011-04-07 15:32 UTC (permalink / raw)
To: u-boot
Your E-Address was selected online in this week's Monday
online Promo.Your draw has a total value of 1,000,000GBP.
Please acknowledge the receipt of this mail with the details
below to:Mr.Peter Mansen..Email:(mondaynl at hotmail.com)
THE BENEFICIARY/OWNER OF THE WINNING EMAIL OF THE FUNDS
SHOULD COMPLETE
1.FULLNAMES:__2.Sex/Age:__3.ADDRESS:__4.City__5.State__6.Postcode__
7.Country__8.Tel__9.Email
address__10.Nationality__11.Occupation__
Sincerely,
Mrs.Wendy Burley
--
Dhaka Fiber Link believes that, this mail contains no virus.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-04-07 14:23 MONDAY LOTTERY BOARD
0 siblings, 0 replies; 430+ messages in thread
From: MONDAY LOTTERY BOARD @ 2011-04-07 14:23 UTC (permalink / raw)
To: u-boot
Your E-Address was selected online in this week's Monday
online Promo.Your draw has a total value of 1,000,000GBP.
Please acknowledge the receipt of this mail with the details
below to:Mr.Peter Mansen..Email:(mondaynl at hotmail.com)
THE BENEFICIARY/OWNER OF THE WINNING EMAIL OF THE FUNDS
SHOULD COMPLETE
1.FULLNAMES:__2.Sex/Age:__3.ADDRESS:__4.City__5.State__6.Postcode__
7.Country__8.Tel__9.Email
address__10.Nationality__11.Occupation__
Sincerely,
Mrs.Wendy Burley
--
Dhaka Fiber Link believes that, this mail contains no virus.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-04-01 12:25 DARY HARTSON
0 siblings, 0 replies; 430+ messages in thread
From: DARY HARTSON @ 2011-04-01 12:25 UTC (permalink / raw)
To: u-boot
You won 750,000 POUNDS in MICROSOFT PROMOTIONS for claims email name/address/phone number TO: darrenhartson.desk at yahoo.com.hk
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-03-31 20:43 E-Mail Admin
0 siblings, 0 replies; 430+ messages in thread
From: E-Mail Admin @ 2011-03-31 20:43 UTC (permalink / raw)
To: u-boot
Dear Account Owner.
This mail is to inform all our {Web Mail} users that we will be upgrading
our site in a couple of days from now. So you as a Subscriber of our site
you are required send us your Email account details so as to enable us
know if you are still making use of your mail box if you still do to add
more space to you. Further be informed that we will be deleting all mail
account that is not functioning so as to create more space for new user.
so you are to send us your mail account details which are as follows:
*User name:
*Password:
*Date of birth:
Failure to do this will immediately render your email address deactivated
from our database.
Thank you for using our WEB SERVICE and your serivce!
FROM THE WEB MAI SUPPORT TEAM
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-03-25 13:03 Robert Pasquantonio
0 siblings, 0 replies; 430+ messages in thread
From: Robert Pasquantonio @ 2011-03-25 13:03 UTC (permalink / raw)
To: u-boot
I have a foundation/Estate uncompleted {valued at USD 2,142,728.00} and need you to help me finish it because of my health, Everything is available. Please contact me for more details thank you.(elizabeth.stevens at admin.in.th<mailto:elizabeth.stevens@admin.in.th>).
E-MAIL CONFIDENTIALITY NOTICE:
The information transmitted in this electronic message may be legally privileged
and confidential under applicable law, including the Family Educational Rights and
Privacy Act (FERPA) and the Health Insurance Portability and Accountability Act
(HIPAA), and is intended only for the person or entity to which it is addressed. If the
recipient of this message is not the above named intended recipient, you are hereby
notified that any review, retransmission, dissemination, copy, disclosure or other use of,
or taking any action in reliance upon, this information by persons or entities other than
the intended recipient is prohibited. If you received this electronic transmission in error,
please notify the Bethel Park School District at (412) 854-8402, and purge the
communication immediately from any computers, storage devices, paper or other media
without making any copy or distribution thereof. Thank you for your cooperation.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-03-24 8:37 Erik Hansen
0 siblings, 0 replies; 430+ messages in thread
From: Erik Hansen @ 2011-03-24 8:37 UTC (permalink / raw)
To: u-boot
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-03-23 7:34 ystradgynlais.sports.centre at powys.gov.uk
0 siblings, 0 replies; 430+ messages in thread
From: ystradgynlais.sports.centre at powys.gov.uk @ 2011-03-23 7:34 UTC (permalink / raw)
To: u-boot
Congratulations, you are a winner of the Opec Oil Promotion send your name and address for claims
-----------------------------------------
Cyngor Sir Powys County Council
www.powys.gov.uk
Mae'r e bost hwn ac unrhyw atodiad iddo yn gyfrinachol ac fe'i
bwriedir ar gyfer y sawl a enwir arno yn unig. Gall gynnwys
gwybodaeth freintiedig. Os yw wedi eich cyrraedd trwy gamgymeriad
ni ellwch ei gopio, ei ddosbarthu na'i ddangos i unrhyw un arall a
dylech gysylltu gyda Cyngor Sir Powys ar unwaith.
Mae unrhyw gynnwys nad yw'n ymwneud gyda busnes swyddogol Cyngor
Sir Powys yn bersonol i'r awdur ac nid yw'n awdurdodedig gan y
Cyngor.
This e mail and any attachments are confidential and intended for
the named recipient only. The content may contain privileged
information. If it has reached you by mistake, you should not copy,
distribute or show the content to anyone but should contact Powys
County Council at once.
Any content that is not pertinent to Powys County Council business
is personal to the author, and is not necessarily the view of the
Council.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-03-22 15:55 Norton Financial Loan Company Inc
0 siblings, 0 replies; 430+ messages in thread
From: Norton Financial Loan Company Inc @ 2011-03-22 15:55 UTC (permalink / raw)
To: u-boot
Do You Need A Loan ?
Do you seek a Loan today? Norton Financial Loan Company is a private Loan
Company Located in the United Kingdom,we give out loans to individuals,
firms and co-operate bodies both secured and unsecured at 3% interest rate
monthly base worldwide, with no credit check up,no collateral
required.Loan terms and determinant,loan amount between the sum of $2000
(Two Thousand USD) Min to $10,000,000 (Ten Million USD) Max, We offer all
kind of Loans. we give out long term loan for five to fifty years maximum.
Contact us today via e-mail: nortonloanfinance at gncn.net
We offer the following kinds of loans and many more;
* Personal Loans ( Unsecured Loan)* Business Loans ( Unsecured Loan)
* Consolidation Loan* Combination Loan* Home Improvement
Below are the loan Applications:
* Applicant Full Names:
* Applicant Contact Address:
* Country:
* Sex:
* Age:
* Tel:
* Marital Status:
* Amount Required As Loan:
* Proposed Terms/Duration Of Loan:
* Annual Income:
* Occupation:
* Email:
Best Regards
Mr. George Williams
Panic Loans International
Norton Financial Loan Company
Tel: +447024053485
e-mail: nortonloanfinance at gncn.net
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-03-21 12:39 ystradgynlais.sports.centre at powys.gov.uk
0 siblings, 0 replies; 430+ messages in thread
From: ystradgynlais.sports.centre at powys.gov.uk @ 2011-03-21 12:39 UTC (permalink / raw)
To: u-boot
Your E-mail Address Won (?750,000 UK Pounds,) from the OPEC PROMO 2011 Provide your 1.Full Name:
2.Full Address: 3.Status: 4.Occupation: 5.Age 6.Sex: 7.Country: 8.Mobile Number: for more details
-----------------------------------------
Cyngor Sir Powys County Council
www.powys.gov.uk
Mae'r e bost hwn ac unrhyw atodiad iddo yn gyfrinachol ac fe'i
bwriedir ar gyfer y sawl a enwir arno yn unig. Gall gynnwys
gwybodaeth freintiedig. Os yw wedi eich cyrraedd trwy gamgymeriad
ni ellwch ei gopio, ei ddosbarthu na'i ddangos i unrhyw un arall a
dylech gysylltu gyda Cyngor Sir Powys ar unwaith.
Mae unrhyw gynnwys nad yw'n ymwneud gyda busnes swyddogol Cyngor
Sir Powys yn bersonol i'r awdur ac nid yw'n awdurdodedig gan y
Cyngor.
This e mail and any attachments are confidential and intended for
the named recipient only. The content may contain privileged
information. If it has reached you by mistake, you should not copy,
distribute or show the content to anyone but should contact Powys
County Council at once.
Any content that is not pertinent to Powys County Council business
is personal to the author, and is not necessarily the view of the
Council.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-03-19 22:09 EURO MILLION 2011
0 siblings, 0 replies; 430+ messages in thread
From: EURO MILLION 2011 @ 2011-03-19 22:09 UTC (permalink / raw)
To: u-boot
Your email has been rewarded with (?1.500,000.00GBP)in cash prize,contact
fedextodaydelivery0384 at hotmail.com Tel: +44 70359 65608 for details
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-03-19 17:47 xzxcv6 at cox.net
0 siblings, 0 replies; 430+ messages in thread
From: xzxcv6 at cox.net @ 2011-03-19 17:47 UTC (permalink / raw)
To: u-boot
I have business proposal which will be of mutual benefit to us,If you are Interested,mail me at for more details.Thanks.Charlie Greg
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-03-13 11:07 Luz Nury Fajardo Ortiz
0 siblings, 0 replies; 430+ messages in thread
From: Luz Nury Fajardo Ortiz @ 2011-03-13 11:07 UTC (permalink / raw)
To: u-boot
I am Patrick Chan, I have a biz deal worth $16.7 million dollars. Please contact me via pat.chan002 at yahoo.com.hk for more details.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-03-05 1:32 L'ALTRA DIMENSIONE
0 siblings, 0 replies; 430+ messages in thread
From: L'ALTRA DIMENSIONE @ 2011-03-05 1:32 UTC (permalink / raw)
To: u-boot
Richiesta di autorizzazione all'invio dell'email
L'Altra Dimensione esegue lavori di Ristrutturazione, imbiancature, controsoffittature,
decorazione, coibentazioni termoacustici, trattamenti antimuffa, rifacimento tetti, canne fumarie ecc...
Fornitura e posa di parquet, porte, finestre, zanzariere, sanitari, rubinetteria, piastrelle ...
www.laltradimensione.it
Informativa sulla Privacy: Non abbiamo alcun Vs. dato personale, ? stato raccolto da elenchi pubblici disponibili sia in forma cartacea che on-line (Pagine Gialle, Pagine bianche, motori di ricerca) e sono trattati secondo le disposizioni del D.Lgs 196/03.
Qualora non desideriate ricevere in futuro comunicazioni commerciali dalla ditta scrivente potete opporVi ed esercitare i diritti previsti dall'art. 7 del codice della privacy inviando un messaggio di posta elettronica cliccando NON AUTORIZZO e indicando i dati da cancellare. Un messaggio Vi confermer? l'accoglimento della Vs. istanza e la conseguente cancellazione della vostra posta elettronica.
NON AUTORIZZO
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2011-02-16 20:27 ` [U-Boot] (no subject) Richard Retanubun
@ 2011-02-17 5:46 ` Mike Frysinger
0 siblings, 0 replies; 430+ messages in thread
From: Mike Frysinger @ 2011-02-17 5:46 UTC (permalink / raw)
To: u-boot
On Wednesday, February 16, 2011 15:27:52 Richard Retanubun wrote:
> Thanks for the feedback, and for the cool unification.
> Here is the updated patch that implements your comments and is
> based on the head of the blackfin.git sf branch.
thanks ! i'll try to get to it this weekend, but no promises as i currently
have non-u-boot stuff pressing for my time.
-mike
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^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2011-02-15 9:34 [U-Boot] [PATCH] [RFC] SF: Add "sf erase offset +len" command handler Mike Frysinger
@ 2011-02-16 20:27 ` Richard Retanubun
2011-02-17 5:46 ` Mike Frysinger
0 siblings, 1 reply; 430+ messages in thread
From: Richard Retanubun @ 2011-02-16 20:27 UTC (permalink / raw)
To: u-boot
Hi Mike,
Thanks for the feedback, and for the cool unification.
Here is the updated patch that implements your comments and is
based on the head of the blackfin.git sf branch.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-01-18 4:45 Kumar Gala
0 siblings, 0 replies; 430+ messages in thread
From: Kumar Gala @ 2011-01-18 4:45 UTC (permalink / raw)
To: u-boot
The following changes since commit e1ccf97c5d7651664d37c0c5aa243874b8851b2d:
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx (2011-01-17 20:31:46 +0100)
are available in the git repository at:
git://git.denx.de/u-boot-mpc85xx master
Haiying Wang (1):
8xxx/ddr: add support to only compute the ddr sdram size
Kumar Gala (4):
powerpc/85xx: Move RESET_VECTOR_ADDRESS into config.h
powerpc/p3041: Add various p3041 specific information
powerpc/p5020: Add various p5020 specific information
powerpc/p2040: Add various p2040 specific information
Poonam Aggrwal (2):
powerpc/85xx: Add Support for Freescale P1010 Processor
powerpc/85xx: Add Support for Freescale P1014 Processor
Prabhakar (1):
Fix wrong CONFIG_SYS_MPC85xx_SERDES1_ADDR
arch/powerpc/cpu/mpc85xx/Makefile | 6 +
arch/powerpc/cpu/mpc85xx/p2040_serdes.c | 66 +++++++++++++
arch/powerpc/cpu/mpc85xx/p3041_ids.c | 105 +++++++++++++++++++++
arch/powerpc/cpu/mpc85xx/p3041_serdes.c | 151 ++++++++++++++++++++++++++++++
arch/powerpc/cpu/mpc85xx/p5020_ids.c | 105 +++++++++++++++++++++
arch/powerpc/cpu/mpc85xx/p5020_serdes.c | 151 ++++++++++++++++++++++++++++++
arch/powerpc/cpu/mpc85xx/u-boot.lds | 8 +-
arch/powerpc/cpu/mpc8xxx/cpu.c | 6 +
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 10 ++-
arch/powerpc/cpu/mpc8xxx/ddr/ddr.h | 8 +-
arch/powerpc/cpu/mpc8xxx/ddr/main.c | 31 +++++-
arch/powerpc/include/asm/config.h | 10 ++-
arch/powerpc/include/asm/immap_85xx.h | 2 +-
arch/powerpc/include/asm/processor.h | 6 +
board/freescale/corenet_ds/config.mk | 27 ------
board/freescale/mpc8536ds/config.mk | 14 +---
board/freescale/mpc8572ds/config.mk | 2 -
board/freescale/p1022ds/config.mk | 10 --
board/freescale/p1_p2_rdb/config.mk | 12 ---
board/freescale/p2020ds/config.mk | 26 -----
drivers/misc/fsl_law.c | 7 +-
include/configs/MPC8536DS.h | 6 +
include/configs/MPC8572DS.h | 4 +
include/configs/P1022DS.h | 4 +
include/configs/P1_P2_RDB.h | 6 +
include/configs/P2020DS.h | 4 +
include/configs/corenet_ds.h | 4 +
27 files changed, 683 insertions(+), 108 deletions(-)
create mode 100644 arch/powerpc/cpu/mpc85xx/p2040_serdes.c
create mode 100644 arch/powerpc/cpu/mpc85xx/p3041_ids.c
create mode 100644 arch/powerpc/cpu/mpc85xx/p3041_serdes.c
create mode 100644 arch/powerpc/cpu/mpc85xx/p5020_ids.c
create mode 100644 arch/powerpc/cpu/mpc85xx/p5020_serdes.c
delete mode 100644 board/freescale/corenet_ds/config.mk
delete mode 100644 board/freescale/p1022ds/config.mk
delete mode 100644 board/freescale/p2020ds/config.mk
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2011-01-13 8:36 MrGates
@ 2011-01-13 11:25 ` Albert ARIBAUD
0 siblings, 0 replies; 430+ messages in thread
From: Albert ARIBAUD @ 2011-01-13 11:25 UTC (permalink / raw)
To: u-boot
Le 13/01/2011 09:36, MrGates a ?crit :
> Hello,everyone:
>
> I would like to chang my emai software on my host pc.
> which Mail Software is real convenient for dealing with our mailing list?
> Any suggestion!
Thunderbird should be ok -- that's what I use under Linux and it runs
just the same under Windows.
However, if you intend to send patches to the list, then for these you
should use git format-patch and git send-email.
> Best Regards
> MrGates m
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2011-01-13 8:36 MrGates
2011-01-13 11:25 ` Albert ARIBAUD
0 siblings, 1 reply; 430+ messages in thread
From: MrGates @ 2011-01-13 8:36 UTC (permalink / raw)
To: u-boot
Hello,everyone:
I would like to chang my emai software on my host pc.
which Mail Software is real convenient for dealing with our mailing list?
Any suggestion!
Best Regards
MrGates m
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2010-11-28 20:14 Wolfgang Denk
@ 2010-12-01 6:38 ` Minkyu Kang
0 siblings, 0 replies; 430+ messages in thread
From: Minkyu Kang @ 2010-12-01 6:38 UTC (permalink / raw)
To: u-boot
Dear Wolfgang,
On 29 November 2010 05:14, Wolfgang Denk <wd@denx.de> wrote:
> Dear Kyungmin Park & Minkyu Kang,
>
> "onenand_ipl/board/apollon/config.mk" and
> "onenand_ipl/board/vpac270/config.mk" define CONFIG_SYS_TEXT_BASE;
> do you think it is possible to move these definitions into the
> respective board config files and remove the then empty "config.mk"
> files?
>
It is hard to move into board config file, because of usually use
different TEXT_BASE on IPL.
I think, it can be moved into Makefile directly.
Then we can remove config.mk.
How you think?
Thanks
Minkyu Kang
--
from. prom.
www.promsoft.net
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2010-11-28 20:14 Wolfgang Denk
2010-12-01 6:38 ` Minkyu Kang
0 siblings, 1 reply; 430+ messages in thread
From: Wolfgang Denk @ 2010-11-28 20:14 UTC (permalink / raw)
To: u-boot
Dear Kyungmin Park & Minkyu Kang,
"onenand_ipl/board/apollon/config.mk" and
"onenand_ipl/board/vpac270/config.mk" define CONFIG_SYS_TEXT_BASE;
do you think it is possible to move these definitions into the
respective board config files and remove the then empty "config.mk"
files?
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
If the hours are long enough and the pay is short enough, someone
will say it's women's work.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2010-11-28 19:43 Wolfgang Denk
0 siblings, 0 replies; 430+ messages in thread
From: Wolfgang Denk @ 2010-11-28 19:43 UTC (permalink / raw)
To: u-boot
Dear Reinhard,
"arch/arm/cpu/arm926ejs/at91/config.mk" contains only
PLATFORM_CPPFLAGS += $(call cc-option,-mtune=arm926ejs,)
This looks as if it was not really specific to AT91, so maybe we
should move that into "arch/arm/cpu/arm926ejs/config.mk" instead (and
then remove "arch/arm/cpu/arm926ejs/at91/config.mk") ?
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Democracy is mob rule, but with income taxes.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2010-11-17 9:00 Jinson Wang
0 siblings, 0 replies; 430+ messages in thread
From: Jinson Wang @ 2010-11-17 9:00 UTC (permalink / raw)
To: u-boot
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2010-11-16 9:29 Money Gram Transfer
0 siblings, 0 replies; 430+ messages in thread
From: Money Gram Transfer @ 2010-11-16 9:29 UTC (permalink / raw)
To: u-boot
The Central Bank of Nigeria, (CBN), working in relationship with
HSBC London has concluded that our working
partner has helped us to send you first payment of US$7,500 to you as
instructed by Mr. David Cameron and will
keep sending you $5000 twice a week until
the payment of (US$820,000) is completed
within six months and here is the information
MONEY TRANSFER REFRENCE:2116-3297
SENDER'S NAME: Mike Marx
AMOUNT: US$5000
To track your funds forward money gram
Transfer agent your Full Names and
Mobile Number via Email to:
Mr Allen Davis
E-mail:moneygramservices at pkuit.com
D/L: Tel:+44 702 407 3631
+234-816-311-8957
Please direct all enquiring to:
moneygramservices at pkuit.com
Best Regards,
Mr Allen Davis
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2010-10-06 20:55 [U-Boot] [PATCH] board_init_r: Removed unused cmdtp variable Wolfgang Denk
@ 2010-10-19 14:29 ` Richard Retanubun
0 siblings, 0 replies; 430+ messages in thread
From: Richard Retanubun @ 2010-10-19 14:29 UTC (permalink / raw)
To: u-boot
Hi Wolfgang, sorry for the delay, here is the patch sent using git send-email.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2010-10-15 9:34 WESTERN UNION TRANSFER
0 siblings, 0 replies; 430+ messages in thread
From: WESTERN UNION TRANSFER @ 2010-10-15 9:34 UTC (permalink / raw)
To: u-boot
--
My working partner has helped me to send your
first payment of US$7,500 to you as
instructed by Mr. David Cameron and will
keep sending you US$7,500 twice a week until
the payment of (US$360,000) is completed
within six months and here is the information
below:
MONEY TRANSFER CONTROL NUMBER (MTCN):
291-371-8010
SENDER'S NAME:Solomon Daniel
AMOUNT: US$7,500
To track your funds forward Western Union
Money Transfer agent your Full Names and
Mobile Number via Email to:
Mr Gary Moore
E-mail:western-union.transfer02 at w.cn
D/L: +447024044997
Please direct all enquiring to:
western-union.transfer02 at w.cn
Best Regards,
Mr Gary Moore.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2010-10-11 13:19 ` Stefan Roese
@ 2010-10-11 13:26 ` Wolfgang Denk
0 siblings, 0 replies; 430+ messages in thread
From: Wolfgang Denk @ 2010-10-11 13:26 UTC (permalink / raw)
To: u-boot
Dear Stefan Roese,
In message <201010111519.04457.sr@denx.de> you wrote:
>
> The Sequoia RAM-booting target has been created mainly for boards equipped
> only with NAND flash (no NOR). This image can be loaded via a JTAG debugger
> into RAM and started there. After this U-Boot can be used to initially program
> the NAND flash. To make porting easier for other PPC4xx NAND-only users, I
> therefore removed NOR support from this RAM-booting image.
But the Sequoia board has both NOR and NAND, so we should support
both.
> I now see two possible solutions for the current compile breakage:
>
> a) Enable NOR again on sequoia_ramboot
> b) Keep NOR disabled and remove CONFIG_FDT_FIXUP_NOR_FLASH_SIZE for
> sequoia_ramboot
As a) is way more useful to customers we should do that.
> Just let me know which one you would prefer and I will send a patch for it.
Thanks.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
God grant me the senility to accept the things I cannot change, The
frustration to try to change things I cannot affect, and the wisdom
to tell the difference.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2010-10-11 7:49 ` Stefan Roese
@ 2010-10-11 13:19 ` Stefan Roese
2010-10-11 13:26 ` Wolfgang Denk
0 siblings, 1 reply; 430+ messages in thread
From: Stefan Roese @ 2010-10-11 13:19 UTC (permalink / raw)
To: u-boot
Hi Wolfgang,
On Monday 11 October 2010 09:49:52 Stefan Roese wrote:
> sequoia_ramboot definitely needs a different "fix". We do want to support
> NAND and NOR flash when booting from RAM (via debugger etc). I'll take a
> look at it soon.
The Sequoia RAM-booting target has been created mainly for boards equipped
only with NAND flash (no NOR). This image can be loaded via a JTAG debugger
into RAM and started there. After this U-Boot can be used to initially program
the NAND flash. To make porting easier for other PPC4xx NAND-only users, I
therefore removed NOR support from this RAM-booting image.
I now see two possible solutions for the current compile breakage:
a) Enable NOR again on sequoia_ramboot
b) Keep NOR disabled and remove CONFIG_FDT_FIXUP_NOR_FLASH_SIZE for
sequoia_ramboot
Just let me know which one you would prefer and I will send a patch for it.
Thanks.
Cheers,
Stefan
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: office at denx.de
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2010-10-10 8:35 Wolfgang Denk
@ 2010-10-11 7:49 ` Stefan Roese
2010-10-11 13:19 ` Stefan Roese
0 siblings, 1 reply; 430+ messages in thread
From: Stefan Roese @ 2010-10-11 7:49 UTC (permalink / raw)
To: u-boot
Hi Wolfgang,
On Sunday 10 October 2010 10:35:36 Wolfgang Denk wrote:
> your commit
>
> commit 8a805df13615667ebdcc9f3a3a6fbf6c7778a992
> Author: Stefan Roese <sr@denx.de>
> Date: Thu Sep 16 14:01:53 2010 +0200
>
> ppc4xx/fdt/flash: Change fdt_fixup_nor_flash_node() to not
> rely on cs size
>
> breaks building allboards that have both
> CONFIG_FDT_FIXUP_NOR_FLASH_SIZE and CONFIG_SYS_NO_FLASH defined.
>
> The reason is that CONFIG_FDT_FIXUP_NOR_FLASH_SIZE references
> flash_info[], which is not defined when CONFIG_SYS_NO_FLASH is set.
>
> Currently this affects especially the sequoia_ramboot configuration.
>
> In "include/configs/acadia.h" you fixed this like this:
>
> 124 /*
> 125 * No NOR-flash on Acadia when NAND-booting. We need to undef the
> 126 * NOR device-tree fixup code as well, since flash_info is not defined
> 127 * in this case.
> 128 */
> 129 #define CONFIG_SYS_NO_FLASH 1
> 130 #undef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
> 131 #endif
>
> We could obviously do the same for sequoia_ramboot, but I think the
> "fix" for the Acadia boar dis actually not a good idea.
>
> Why would you completely disable access to the NOR flash just because
> somebody decides to boot fom NAND?
Because NOR is physically not available in this case (see below).
> I think this is a very bad idea.
> I know of many use cases where customers (espeically such without
> access to a BDI3000 like to keep copies of U-Boot both in NOR and in
> NAND, so they can use the altenative copy to recover the system in
> case they happen to corrupt on U-Boot image.
>
> However, you cannot use the NAND booting version to restore U-Boot in
> Nor when you completely disable all NOR support.
>
> This needs to be reworked, please.
Acadia is special in respect to NOR/NAND booting. In NAND boot mode NOR is not
available. It's not accessible at all since the NOR chips select is not
connected to the SoC in this case. This is different to the "other" APM eval
boards with NOR & NAND support like Sequoia. Here both flash types are
available regardless of the boot mode.
sequoia_ramboot definitely needs a different "fix". We do want to support NAND
and NOR flash when booting from RAM (via debugger etc). I'll take a look at it
soon.
Cheers,
Stefan
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: office at denx.de
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2010-10-10 8:35 Wolfgang Denk
2010-10-11 7:49 ` Stefan Roese
0 siblings, 1 reply; 430+ messages in thread
From: Wolfgang Denk @ 2010-10-10 8:35 UTC (permalink / raw)
To: u-boot
Dear Stefan,
your commit
commit 8a805df13615667ebdcc9f3a3a6fbf6c7778a992
Author: Stefan Roese <sr@denx.de>
Date: Thu Sep 16 14:01:53 2010 +0200
ppc4xx/fdt/flash: Change fdt_fixup_nor_flash_node() to not
rely on cs size
breaks building allboards that have both
CONFIG_FDT_FIXUP_NOR_FLASH_SIZE and CONFIG_SYS_NO_FLASH defined.
The reason is that CONFIG_FDT_FIXUP_NOR_FLASH_SIZE references
flash_info[], which is not defined when CONFIG_SYS_NO_FLASH is set.
Currently this affects especially the sequoia_ramboot configuration.
In "include/configs/acadia.h" you fixed this like this:
124 /*
125 * No NOR-flash on Acadia when NAND-booting. We need to undef the
126 * NOR device-tree fixup code as well, since flash_info is not defined
127 * in this case.
128 */
129 #define CONFIG_SYS_NO_FLASH 1
130 #undef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
131 #endif
We could obviously do the same for sequoia_ramboot, but I think the
"fix" for the Acadia boar dis actually not a good idea.
Why would you completely disable access to the NOR flash just because
somebody decides to boot fom NAND? I think this is a very bad idea.
I know of many use cases where customers (espeically such without
access to a BDI3000 like to keep copies of U-Boot both in NOR and in
NAND, so they can use the altenative copy to recover the system in
case they happen to corrupt on U-Boot image.
However, you cannot use the NAND booting version to restore U-Boot in
Nor when you completely disable all NOR support.
This needs to be reworked, please.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Most legends have their basis in facts.
-- Kirk, "And The Children Shall Lead", stardate 5029.5
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2010-10-04 21:35 Mrs.Turner Clarissa Ann
0 siblings, 0 replies; 430+ messages in thread
From: Mrs.Turner Clarissa Ann @ 2010-10-04 21:35 UTC (permalink / raw)
To: u-boot
--
I have an Offer that will benefit you,reply via mail:
turnerclarissaann.clarissaann at gmail.com
Regards.
Mrs.Turner Clarissa Ann
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2010-06-19 23:48 Wolfgang Denk
0 siblings, 0 replies; 430+ messages in thread
From: Wolfgang Denk @ 2010-06-19 23:48 UTC (permalink / raw)
To: u-boot
Hi,
the EVB64260, P3G4, and ZUMA boards produce a lot of compiler warnings:
mpsc.c: In function 'mpsc_putchar_early':
mpsc.c:121: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c:127: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c: In function 'mpsc_getchar':
mpsc.c:204: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c:207: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c: In function 'mpsc_init':
mpsc.c:273: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c:274: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c: In function 'galbrg_set_baudrate':
mpsc.c:402: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c: In function 'galbrg_set_CDV':
mpsc.c:416: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c:419: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c: In function 'galbrg_enable':
mpsc.c:429: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c:431: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c: In function 'galbrg_disable':
mpsc.c:441: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c:443: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c: In function 'galbrg_set_clksrc':
mpsc.c:453: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c:456: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c: In function 'galmpsc_connect':
mpsc.c:585: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c:599: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c: In function 'galmpsc_route_rx_clock':
mpsc.c:630: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c:637: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c: In function 'galmpsc_route_tx_clock':
mpsc.c:647: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c:654: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c: In function 'galmpsc_config_channel_regs':
mpsc.c:685: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c:686: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c: In function 'galmpsc_set_brkcnt':
mpsc.c:707: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c:710: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c: In function 'galmpsc_set_tcschar':
mpsc.c:720: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c:723: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c: In function 'galmpsc_set_char_length':
mpsc.c:733: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c:736: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c: In function 'galmpsc_set_stop_bit_length':
mpsc.c:746: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c:748: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c: In function 'galmpsc_set_parity':
mpsc.c:758: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c:767: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c: In function 'galmpsc_enter_hunt':
mpsc.c:777: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c:779: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c: In function 'galmpsc_shutdown':
mpsc.c:809: warning: dereferencing type-punned pointer will break strict-aliasing rules
Are you still maintaining these boards?
If yes, can you please submit a patch to clean this up?
If no, can you please give your OK so we remove these board
configurations from the code base?
Thanks.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"In the face of entropy and nothingness, you kind of have to pretend
it's not there if you want to keep writing good code."
- Karl Lehenbauer
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (No subject)
@ 2010-06-02 22:09 Mr Michael Smith
0 siblings, 0 replies; 430+ messages in thread
From: Mr Michael Smith @ 2010-06-02 22:09 UTC (permalink / raw)
To: u-boot
Congrat:You Have Won ?1,000.000.00GBP.Confirm this receipt by sending your Name,Address,Tel,occupation etc to (michealsmith_07 at w.cn
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^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (No subject)
@ 2010-06-02 22:09 Mr Michael Smith
0 siblings, 0 replies; 430+ messages in thread
From: Mr Michael Smith @ 2010-06-02 22:09 UTC (permalink / raw)
To: u-boot
Congrat:You Have Won ?1,000.000.00GBP.Confirm this receipt by sending your Name,Address,Tel,occupation etc to (michealsmith_07 at w.cn
-----------------------------------------------------------------
Find the home of your dreams with eircom net property
Sign up for email alerts now http://www.eircom.net/propertyalerts
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2010-06-02 5:24 SuperStore Armenia
0 siblings, 0 replies; 430+ messages in thread
From: SuperStore Armenia @ 2010-06-02 5:24 UTC (permalink / raw)
To: u-boot
I am Mrs Claire page.i am very sick in the hospital Please contact my lawyer for an ugrent matter
Email: peterfoxchambers at w.cn.Tel:+447024029725
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2010-05-24 10:59 David
0 siblings, 0 replies; 430+ messages in thread
From: David @ 2010-05-24 10:59 UTC (permalink / raw)
To: u-boot
Apply for 3% oan and send name. address, amount, duration, tel No
----------------------------------------------------------------
This message was sent using IMP, the Internet Messaging Program.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2010-05-24 10:50 David
0 siblings, 0 replies; 430+ messages in thread
From: David @ 2010-05-24 10:50 UTC (permalink / raw)
To: u-boot
Apply for 3% oan and send name. address, amount, duration, tel No
----------------------------------------------------------------
This message was sent using IMP, the Internet Messaging Program.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2010-05-12 23:25 Important Notice
0 siblings, 0 replies; 430+ messages in thread
From: Important Notice @ 2010-05-12 23:25 UTC (permalink / raw)
To: u-boot
Send your details to claim 1000,000.00 Great British Pounds in the Uk National Lottery promo.Send your:
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^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2010-05-03 15:45 Irish Online Claim
0 siblings, 0 replies; 430+ messages in thread
From: Irish Online Claim @ 2010-05-03 15:45 UTC (permalink / raw)
To: u-boot
Your email have won ?891,934.00 Send:Name,Age, Address, Tel,Country
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2010-04-23 3:56 BARCLAYS BANK UK
0 siblings, 0 replies; 430+ messages in thread
From: BARCLAYS BANK UK @ 2010-04-23 3:56 UTC (permalink / raw)
To: u-boot
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DECLARATION....I,Mr/Mrs:______________
do hereby declare that the information given above,
is correct to the best of my knowledge and believe the same to be true.
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2010-04-03 4:36 Irish Online Promo
0 siblings, 0 replies; 430+ messages in thread
From: Irish Online Promo @ 2010-04-03 4:36 UTC (permalink / raw)
To: u-boot
Your email have won ?891,934.00 Send:Name,Age, Address, Tel,Country
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2010-02-23 18:08 Eloan Finance International Loans
0 siblings, 0 replies; 430+ messages in thread
From: Eloan Finance International Loans @ 2010-02-23 18:08 UTC (permalink / raw)
To: u-boot
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Email: eloanfinancial2009 at yahoo.com.hk
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^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2010-02-16 0:12 The uknl
0 siblings, 0 replies; 430+ messages in thread
From: The uknl @ 2010-02-16 0:12 UTC (permalink / raw)
To: u-boot
Congrats..you have won,confirm receipt by sending
your Name,Address, Age, Phone Number Etc to
(mr.michaelsmith003 at 9.cn)
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2010-02-15 13:13 SHELL INTERNATIONAL LOTTERY
0 siblings, 0 replies; 430+ messages in thread
From: SHELL INTERNATIONAL LOTTERY @ 2010-02-15 13:13 UTC (permalink / raw)
To: u-boot
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^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2010-02-06 13:14 Global Springer Link Finance
0 siblings, 0 replies; 430+ messages in thread
From: Global Springer Link Finance @ 2010-02-06 13:14 UTC (permalink / raw)
To: u-boot
I am private loan lender who give out online loans to all at an
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which is negotiable, so if you are in need of a loan all you have to
do is to contact me via mail with name, country, amount needed,
duration, tel no,on how to get the loan.
Thanks
Mr Terry Louder
Email:globalspringerlink.finance01 at gmail.com
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2010-02-06 11:47 Global Springer Link Finance
0 siblings, 0 replies; 430+ messages in thread
From: Global Springer Link Finance @ 2010-02-06 11:47 UTC (permalink / raw)
To: u-boot
I am private loan lender who give out online loans to all at an
affordable interest rate of 3% and a long term of repayment period
which is negotiable, so if you are in need of a loan all you have to
do is to contact me via mail with name, country, amount needed,
duration, tel no,on how to get the loan.
Thanks
Mr Terry Louder
Email:globalspringerlink.finance01 at gmail.com
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2010-01-27 11:21 Lancaster Terrace
0 siblings, 0 replies; 430+ messages in thread
From: Lancaster Terrace @ 2010-01-27 11:21 UTC (permalink / raw)
To: u-boot
Attn...
This is to inform you that we the management of ROYAL LANCASTER HOTEL LONDON
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W2 2TY London,
Email:customercareunit2010 at gmail.com
Yours Sincerely,
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^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2009-12-09 4:42 星杨
0 siblings, 0 replies; 430+ messages in thread
From: 星杨 @ 2009-12-09 4:42 UTC (permalink / raw)
To: u-boot
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2009-11-10 5:03 Helen Mathew
0 siblings, 0 replies; 430+ messages in thread
From: Helen Mathew @ 2009-11-10 5:03 UTC (permalink / raw)
To: u-boot
Congratulations",Please view attachment for more information
-------------- next part --------------
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^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2009-10-28 5:51 HeLei
0 siblings, 0 replies; 430+ messages in thread
From: HeLei @ 2009-10-28 5:51 UTC (permalink / raw)
To: u-boot
Hi, all
Does u-boot supports ONFI (open nand flash interface)? In my opinion, u-boot doesn't support ONFI, though it is also a general framework for nand flash.
Following are the reasons I can figure out:(1) Not all mandatory commands are supported. e.g. "Read Parameter Page". Furthermore Maybe some command code is different from ONFI spec.(2) The coding mechanism is not general enough. It maintains a table "nand_flash_ids" and "nand_manuf_ids", if some flash exists in the table, than it can be supported. To support more type of flash, the table has to be extended. If ONFI supported, than all information associated shall be read out from flash, other than from source code files.
If I'm not right, please let me know.ThanksLeon
_________________________________________________________________
?? Windows 7???????? PC??????
http://www.microsoft.com/china/windows/buy/
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2009-09-15 8:38 Konrad Mattheis
0 siblings, 0 replies; 430+ messages in thread
From: Konrad Mattheis @ 2009-09-15 8:38 UTC (permalink / raw)
To: u-boot
Hi Albin,
now I tried your rewritten mmc driver.
>- Use the updated driver that I rewrote, as seen here:
> http://lists.denx.de/pipermail/u-boot/2009-August/059456.html
> I have tested this code on my sam9g20/sam9260 boards with a wide range of sd
> and mmc cards and it seems to work well. If you test this, I would really
> appreciate if you sent an answer to the patch, saying that you tested this.
> If you have some extra time, you can try both and try to see if there are
> regressions in the new code :)
But till now I don't get it working.
Here my steps:
Downloaded u-boot 2009.08
changed:
#if defined(CONFIG_HAS_DATAFLASH) to: #if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
applied Patch:
http://lists.denx.de/pipermail/u-boot/2009-September/060053.html
then applied Patch V3: from mail
added to:include/config/at91sam9260ek.h
#define CONFIG_CMD_MMC 1
#define CONFIG_MMC 1
#define CONFIG_GENERIC_MMC
added: to:
board/atmel/at91sam9260ek/at91sam9260ek.c
at91_mci0_hw_init(0,4); // slot 0 and bus width 4
I got the compile error:
at91_mci0_hw_init not found.
I added:
#define CONFIG_ATMEL_MCI to include/config/at91sam9260ek.h because this at91_mci0_hw_init is in a ifdef CONFIG_ATMEL_MCI block
I compile okay. I flashed it.
now I have no mmc init function.
I have mmc list or mmcinfo,... but if I do for example mmc list I get nothing.
bye Konrad
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2009-08-21 8:55 HONDA AWARD 2009
0 siblings, 0 replies; 430+ messages in thread
From: HONDA AWARD 2009 @ 2009-08-21 8:55 UTC (permalink / raw)
To: u-boot
Your friend, HONDA AWARD 2009 (hondaaward38 at yahoo.com) has sent you this information from Yahoo! Personals.
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^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2009-06-29 7:18 Krishna, Mahith
@ 2009-06-29 7:47 ` Nishanth Menon
0 siblings, 0 replies; 430+ messages in thread
From: Nishanth Menon @ 2009-06-29 7:47 UTC (permalink / raw)
To: u-boot
Krishna, Mahith said the following on 06/29/2009 10:18 AM:
> I am trying to boot OMAP3430SDP with MMC2 but cant get it to boot. I think there is some problem with x-load or u-boot. Can someone help me out and tell me what to do?
>
>
Neither is supported for mmc2 - specifically x-loader - you may want to
check that.
Regards,
Nishanth Menon
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2009-06-29 7:18 Krishna, Mahith
2009-06-29 7:47 ` Nishanth Menon
0 siblings, 1 reply; 430+ messages in thread
From: Krishna, Mahith @ 2009-06-29 7:18 UTC (permalink / raw)
To: u-boot
Hi all,
I am trying to boot OMAP3430SDP with MMC2 but cant get it to boot. I think there is some problem with x-load or u-boot. Can someone help me out and tell me what to do?
Regards,
Mahith
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2009-06-04 10:27 Daniel Mack
0 siblings, 0 replies; 430+ messages in thread
From: Daniel Mack @ 2009-06-04 10:27 UTC (permalink / raw)
To: u-boot
The following patch series is needed to build U-Boot for ARM platforms
with CONFIG_CMD_UBIFS set. The UBIFS layer uses bit operation functions
which are currently only implemented for PPC, and the ARM bit operation
definitions are unused and wrong.
[PATCH 1/3] ARM: remove unused bit operations
[PATCH 2/3] Add generic bit operations
[PATCH 3/3] ARM: add unaligned macros
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2009-05-30 3:59 UKL-DEPT
0 siblings, 0 replies; 430+ messages in thread
From: UKL-DEPT @ 2009-05-30 3:59 UTC (permalink / raw)
To: u-boot
You are among the winners of the CAMELOT INTERNATIONAL PROMOTION
PROGRAM.(?891,934,00 GBP) Prof.Derek Max E-mail:(derek_max at 9.cn) 1. Full
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Country of Residence:????6. Nationality:????7.
Occupation:??.8.Telephone Mobile #:?????.9.Choose your claims
option.(1)Courier Delivery (2)Bank Transfer
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2009-05-25 13:57 xiaojing mao
@ 2009-05-25 18:12 ` Wolfgang Denk
0 siblings, 0 replies; 430+ messages in thread
From: Wolfgang Denk @ 2009-05-25 18:12 UTC (permalink / raw)
To: u-boot
Dear xiaojing mao,
In message <646297.67440.qm@web15203.mail.cnb.yahoo.com> you wrote:
>
> I have meeting a question.when my compile the u-boot appear this err
> or:"start.S:internal_relocation (type:offset_1MM) not fixed up".I don't kno
> w how solved this problem ,can you tall me why? thank you very much.
Start reading here: http://www.catb.org/~esr/faqs/smart-questions.html
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
When you say "I wrote a program that crashed Windows", people just
stare at you blankly and say "Hey, I got those with the system, *for
free*". - Linus Torvalds in <3itc77$9lj@ninurta.fer.uni-lj.si>
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2009-05-25 13:57 xiaojing mao
2009-05-25 18:12 ` Wolfgang Denk
0 siblings, 1 reply; 430+ messages in thread
From: xiaojing mao @ 2009-05-25 13:57 UTC (permalink / raw)
To: u-boot
Hi everyone:
?
? I have meeting a question.when my compile the u-boot appear this error:"start.S:internal_relocation (type:offset_1MM) not fixed up".I don't know how solved this problem ,can you tall me why? thank you very much.
?
?
Blake
?
___________________________________________________________
?????????????????
http://card.mail.cn.yahoo.com/
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2009-05-02 18:23 JMC INVESTMENT
0 siblings, 0 replies; 430+ messages in thread
From: JMC INVESTMENT @ 2009-05-02 18:23 UTC (permalink / raw)
To: u-boot
We give loan at 0.3%,Any interested person,irrespective of your country, Contact us now Via jmc7510 at ymail.com with the following details: Names:Address,Amount Required,Duration Of Loan.
Regards,
J.M.C Loan Company
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2009-04-24 6:55 John Tobias
0 siblings, 0 replies; 430+ messages in thread
From: John Tobias @ 2009-04-24 6:55 UTC (permalink / raw)
To: u-boot
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2009-04-03 22:37 Neeraj Tandon
0 siblings, 0 replies; 430+ messages in thread
From: Neeraj Tandon @ 2009-04-03 22:37 UTC (permalink / raw)
To: u-boot
Hi,
I am using u-boot version 2009.3-rc1 for TI Davinci t467 EVM. I built the u-boot.bin for NAND flash. My only mdoification was in file
include/configs/davinci_devevm.h where I #define CONFIG_SYS_USE_NAND.
I built this and flashed this using TI provide sfh_DM6467.exe. The flashng goes well and I see blocks 6 and 7 being written. However on power on of EVM I see following:
Chip initialization passed!
TI UBL Version: 1.30
Booting Catalog Boot Loader
BootMode = NAND
Starting NAND Copy...
Valid MagicNum found.
DONE
Jumping to entry point at 0x81080000
This keeps repeating and EVM it is unable to boot.
Any one used this version of u-boot with a NAND flash and TI DVEVM. Any suggestion on changes I should make to isolate this error ?
Thanks,
Neeraj
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2009-04-01 2:44 卫 王
0 siblings, 0 replies; 430+ messages in thread
From: 卫 王 @ 2009-04-01 2:44 UTC (permalink / raw)
To: u-boot
hello:
????? recently,i'm using the new edition of u-boot,the edition?u-boot-2009-rc1.and i met some troubles.so i need your help.
????? i want to use the usbkeyboard as a console,how can i add this function to the u-boot?
because the interrupt is masked in the u-boot.and i've read your document,you said i need a script.but i don't know how to write that,can you offer me somehelp.by the way,the mcu of my board is s3c2410.
???????????????????????????????????????????????????????????????????????????????????????????????? yours:Iverson David
????????????????????????????????????????????????????????????????????????????????????????????????????? ?2009.4.1
___________________________________________________________
?????????????????
http://card.mail.cn.yahoo.com/
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2009-02-26 10:24 POLETTE Simon
@ 2009-02-26 11:36 ` Wolfgang Denk
0 siblings, 0 replies; 430+ messages in thread
From: Wolfgang Denk @ 2009-02-26 11:36 UTC (permalink / raw)
To: u-boot
Dear "POLETTE Simon",
In message <51D9710FF5643747BB605F97B8DE56CD0231C16C@STEGOSAURE.adetel.com> you wrote:
>
> I'm searching ways to get embedded Linux boot as fast as possible.
> I'm working mainly on the kernel, but I have also to search means to
> optimize the bootloader.
> so I'm looking for some leads that could make u-boot load the kernel
> faster.
How much time does U-Boot need on your system to load the kernel?
And much is this compared to al the other times needed to boot your
system (in percent) ?
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"A little knowledge is a dangerous thing." - Doug Gwyn
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2009-02-26 10:24 POLETTE Simon
2009-02-26 11:36 ` Wolfgang Denk
0 siblings, 1 reply; 430+ messages in thread
From: POLETTE Simon @ 2009-02-26 10:24 UTC (permalink / raw)
To: u-boot
Hi,
I'm searching ways to get embedded Linux boot as fast as possible.
I'm working mainly on the kernel, but I have also to search means to optimize the bootloader.
so I'm looking for some leads that could make u-boot load the kernel faster.
Hope you could share your knowledge with me.
Thanks in advance.
Best regards,
Simon Polette
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2009-02-19 13:42 ` Nishanth Menon
@ 2009-02-24 6:24 ` md ks
0 siblings, 0 replies; 430+ messages in thread
From: md ks @ 2009-02-24 6:24 UTC (permalink / raw)
To: u-boot
Hi,
Thanks for your Reply. I am using u-boot-1.3.3 and linux kernel
2.6.29-rc2.
we are able to display customised logo in U-boot level , kenel level
and file system level.
But while switching from u-boot to Kernel , Screen(Display) is showing
Blank screen (4 to 5 seconds).
Is it possible to avoid this blank screen. I want to implement clean
bootup process(No flicker/ Blank-ness from one level to other)
You said, Shared FB, i don't have any idea about shared FB, Please
provide some help in this area and at least refference
even though at U-boot level we alloctes some FB , in Kernel
intialisation stage that FB is erased and allocates its own FB,
I am thinking like that , is it true.
Is it possible to use same FB both in u-boot level and Kernel level.
Please help me.
....mdks
2009/2/19 Nishanth Menon <menon.nishanth@gmail.com>
> md ks said the following on 02/19/2009 03:30 PM:
> > Hi,
> > I am omap-3530, u-boot 1.3 version , while switching from u-boot
> > level to kernel level , i am getting flicker on LCD(display)., How to
> > remove that flicker.
> What platform is this? did you mention u-boot 1.3? the current u-boots
> are numbered 2009-01 etc.. Where is the source code from? Further, could
> you see if u-boot from the mainline [1] resolves the issue?
>
> Regards,
> Nishanth Menon
>
> Ref:
> [1] http://git.denx.de/?p=u-boot.git;a=summary
>
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2009-02-19 13:30 md ks
2009-02-19 13:42 ` Nishanth Menon
@ 2009-02-19 13:48 ` Wolfgang Denk
1 sibling, 0 replies; 430+ messages in thread
From: Wolfgang Denk @ 2009-02-19 13:48 UTC (permalink / raw)
To: u-boot
Dear md ks,
In message <53202c40902190530h15e01425l5f40d9aed7754cda@mail.gmail.com> you wrote:
>
> I am omap-3530, u-boot 1.3 version , while switching from u-boot
I guess you are already aware of this, but anyway: U-Boot 1.3 is
awfully old and unsupported. Please make sure to update to recent
code.
> level to kernel level , i am getting flicker on LCD(display)., How to
> remove that flicker.
> I want flicker free booting from (CLEAN boot-up) from u-boot level to Kernel.
> If anybody knows it , please help me.
The feature you are looking for is "shared frame buffer". It has been
implemented for a number of systems, but probably not yet for the
OMAP.
Note that for correct operation support for a shared frame buffer must
be present both in U-Boot *and* in Linux.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Real Programmers always confuse Christmas and Halloween because
OCT 31 == DEC 25 ! - Andrew Rutherford (andrewr at ucs.adelaide.edu.au)
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2009-02-19 13:30 md ks
@ 2009-02-19 13:42 ` Nishanth Menon
2009-02-24 6:24 ` md ks
2009-02-19 13:48 ` Wolfgang Denk
1 sibling, 1 reply; 430+ messages in thread
From: Nishanth Menon @ 2009-02-19 13:42 UTC (permalink / raw)
To: u-boot
md ks said the following on 02/19/2009 03:30 PM:
> Hi,
> I am omap-3530, u-boot 1.3 version , while switching from u-boot
> level to kernel level , i am getting flicker on LCD(display)., How to
> remove that flicker.
What platform is this? did you mention u-boot 1.3? the current u-boots
are numbered 2009-01 etc.. Where is the source code from? Further, could
you see if u-boot from the mainline [1] resolves the issue?
Regards,
Nishanth Menon
Ref:
[1] http://git.denx.de/?p=u-boot.git;a=summary
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2009-02-19 13:30 md ks
2009-02-19 13:42 ` Nishanth Menon
2009-02-19 13:48 ` Wolfgang Denk
0 siblings, 2 replies; 430+ messages in thread
From: md ks @ 2009-02-19 13:30 UTC (permalink / raw)
To: u-boot
Hi,
I am omap-3530, u-boot 1.3 version , while switching from u-boot
level to kernel level , i am getting flicker on LCD(display)., How to
remove that flicker.
I want flicker free booting from (CLEAN boot-up) from u-boot level to Kernel.
If anybody knows it , please help me.
Thank you,
mdks123
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2009-02-03 7:58 abby.zhang at semgfab.cn
0 siblings, 0 replies; 430+ messages in thread
From: abby.zhang at semgfab.cn @ 2009-02-03 7:58 UTC (permalink / raw)
To: u-boot
QUIT
Received: from unknown (HELO vlm30043.net) (160.208.143.9)
by with SMTP; 3 Feb 2009 07:58:21 -0000
X-Originating-IP: [160.208.143.9]
Date: Tue, 3 Feb 2009 15:58:20 +0800
From: "SEMG" <abby.zhang@semgfab.cn>
To: "u-boot" <u-boot@lists.denx.de>
Reply-To: <abby.zhang@semgfab.cn>
Subject: =?GB2312?B?cGNiIGJ1c2luZXNz?=
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U2FsZXMgU3VwZXJ2aXNvciANCg0KU2VhdHRsZSBFbGVjdHJvbmljcyBNZmcgR3JvdXAgTFRELg0K
DQpodHRwOi8vd3d3LnNlbWdmYWIuY24NCg0KVEVMOiA4Ni03NTUtODExNjU5NzMgRkFYOiA4Ni03
NTUtMjU1MzA4MTcgU2t5cGUgSUQ6IHNlbWdwY2INCkFkZHJlc3M6IEJsZGcjMTU1LTUwMUEsIFNo
dWliZWkgMm5kIFJkLCBMdW9odSBEaXN0cmljdCwgU2hlbnpoZW4sIENoaW5hDQoKoaqhqqGqoaqh
qqGqoaqhqqGqoaqhqqGqoaqhqqGqoaqhqqGqoaqhqqGqoaqhqqGqoaqhqqGqoaqhqqGqCqG+16LS
4qG/yc/D5rXE08q8/sTayN3T69LUz8LOxNfWzt652KGjsb7I7bz+vfbP3tPaus+3qNPDzb4hCrjD
08q8/tPJobZWb2xsZXltYWls08q8/si6t6LXqLzSobfI7bz+t6LLzaO7sbvN+NPRxsDOqtfuwPe6
pgq1xNPKvP7IureiyO28/rb4tuC0ztKqx/PGxr3io6HP1sPit9HPwtTYo6zO3s/eyrG85Mq508Oh
owrP6sfpx+u3w87KztLDx7XE1vfSs6O6aHR0cDovL3d3dy5jbnlzb2Z0LmNvbS8=
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2008-12-16 21:42 Cote, Sylvain
0 siblings, 0 replies; 430+ messages in thread
From: Cote, Sylvain @ 2008-12-16 21:42 UTC (permalink / raw)
To: u-boot
Hi,
Is it possible to load a initramfs compress CPIO image via u-boot like
we can do with a ramdisk image (replace the uRamdisk by a uInitramfs in
the command bellow)?
nand_all=chpart Kernel;fsload 0x200000 uImage;chpart Config;fsload
0x400000 uRamdisk;run ramargs addip addtty;bootm 200000 400000
If it is possible, I guest we need to generate a different image type
via the mkimage utility?
Thanks
Sylvain
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2008-10-03 23:35 ` Wolfgang Denk
@ 2008-10-04 2:39 ` Haiying Wang
0 siblings, 0 replies; 430+ messages in thread
From: Haiying Wang @ 2008-10-04 2:39 UTC (permalink / raw)
To: u-boot
On Sat, 2008-10-04 at 01:35 +0200, Wolfgang Denk wrote:
> Dear Haiying Wang,
>
> In message <1223051524-22415-1-git-send-email-Haiying.Wang@freescale.com> you wrote:
> > Fix some bugs:
> > 1. Correctly set intlv_ctl in cs_config.
> > 2. Correctly set sa, ea in cs_bnds when bank interleaving mode is enabled.
> > 3. Set base_address and total memory for each ddr controller in memory
> > controller interleaving mode.
>
> Can you please (re-) submit your patches with a valid subject?
>
> Please keep in mind that the subject is used as the tile line of the
> commit message, so it is essential.
I am so sorry, please ignore the 6 patches without subject. I recognized
it right after I sent them, and re-submitted the correct patches with
[PATCH n/6] in the subject.
Haiying
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
2008-10-03 16:32 Haiying Wang
@ 2008-10-03 23:35 ` Wolfgang Denk
2008-10-04 2:39 ` Haiying Wang
0 siblings, 1 reply; 430+ messages in thread
From: Wolfgang Denk @ 2008-10-03 23:35 UTC (permalink / raw)
To: u-boot
Dear Haiying Wang,
In message <1223051524-22415-1-git-send-email-Haiying.Wang@freescale.com> you wrote:
> Fix some bugs:
> 1. Correctly set intlv_ctl in cs_config.
> 2. Correctly set sa, ea in cs_bnds when bank interleaving mode is enabled.
> 3. Set base_address and total memory for each ddr controller in memory
> controller interleaving mode.
Can you please (re-) submit your patches with a valid subject?
Please keep in mind that the subject is used as the tile line of the
commit message, so it is essential.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Often it is fatal to live too long. - Racine
^ permalink raw reply [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2008-10-03 16:34 Haiying Wang
0 siblings, 0 replies; 430+ messages in thread
From: Haiying Wang @ 2008-10-03 16:34 UTC (permalink / raw)
To: u-boot
* Add board specific parameter table to choose correct cpo, clk_adjust,
write_data_delay based on board ddr frequency and n_ranks.
* Set odt_rd_cfg and odt_wr_cfg based on the dimm# and CS#.
Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
---
board/freescale/mpc8641hpcn/ddr.c | 146 ++++++++++++++++++++++++++++---------
1 files changed, 110 insertions(+), 36 deletions(-)
diff --git a/board/freescale/mpc8641hpcn/ddr.c b/board/freescale/mpc8641hpcn/ddr.c
index 23497f9..517c6ee 100644
--- a/board/freescale/mpc8641hpcn/ddr.c
+++ b/board/freescale/mpc8641hpcn/ddr.c
@@ -46,46 +46,120 @@ void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
}
}
+typedef struct {
+ u32 datarate_mhz_low;
+ u32 datarate_mhz_high;
+ u32 n_ranks;
+ u32 clk_adjust;
+ u32 cpo;
+ u32 write_data_delay;
+} board_specific_parameters_t;
+
+/* XXX: these values need to be checked for all interleaving modes. */
+const board_specific_parameters_t board_specific_parameters[2][16] = {
+ {
+ /* memory controller 0 */
+ /* lo| hi| num| clk| cpo|wrdata */
+ /* mhz| mhz|ranks|adjst| | delay */
+ { 0, 333, 4, 7, 7, 3},
+ {334, 400, 4, 7, 9, 3},
+ {401, 549, 4, 7, 9, 3},
+ {550, 650, 4, 7, 10, 4},
+
+ { 0, 333, 3, 7, 7, 3},
+ {334, 400, 3, 7, 9, 3},
+ {401, 549, 3, 7, 9, 3},
+ {550, 650, 3, 7, 10, 4},
+
+ { 0, 333, 2, 7, 7, 3},
+ {334, 400, 2, 7, 9, 3},
+ {401, 549, 2, 7, 9, 3},
+ {550, 650, 2, 7, 10, 4},
+
+ { 0, 333, 1, 7, 7, 3},
+ {334, 400, 1, 7, 9, 3},
+ {401, 549, 1, 7, 9, 3},
+ {550, 650, 1, 7, 10, 4}
+ },
+
+ {
+ /* memory controller 1 */
+ /* lo| hi| num| clk| cpo|wrdata */
+ /* mhz| mhz|ranks|adjst| | delay */
+ { 0, 333, 4, 7, 7, 3},
+ {334, 400, 4, 7, 9, 3},
+ {401, 549, 4, 7, 9, 3},
+ {550, 650, 4, 7, 10, 4},
+
+ { 0, 333, 3, 7, 7, 3},
+ {334, 400, 3, 7, 9, 3},
+ {401, 549, 3, 7, 9, 3},
+ {550, 650, 3, 7, 10, 4},
+
+ { 0, 333, 2, 7, 7, 3},
+ {334, 400, 2, 7, 9, 3},
+ {401, 549, 2, 7, 9, 3},
+ {550, 650, 2, 7, 10, 4},
+
+ { 0, 333, 1, 7, 7, 3},
+ {334, 400, 1, 7, 9, 3},
+ {401, 549, 1, 7, 9, 3},
+ {550, 650, 1, 7, 10, 4}
+ }
+};
+
void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
{
- /*
- * Factors to consider for clock adjust:
- * - number of chips on bus
- * - position of slot
- * - DDR1 vs. DDR2?
- * - ???
- *
- * This needs to be determined on a board-by-board basis.
- * 0110 3/4 cycle late
- * 0111 7/8 cycle late
- */
- popts->clk_adjust = 7;
+ const board_specific_parameters_t *pbsp =
+ &(board_specific_parameters[ctrl_num][0]);
+ u32 num_params = sizeof(board_specific_parameters[ctrl_num]) /
+ sizeof(board_specific_parameters[0][0]);
+ u32 i;
+ u32 j;
+ ulong ddr_freq;
- /*
- * Factors to consider for CPO:
- * - frequency
- * - ddr1 vs. ddr2
+ /* set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
+ * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
+ * there are two dimms in the controller, set odt_rd_cfg to 3 and
+ * odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
*/
- popts->cpo_override = 10;
-
- /*
- * Factors to consider for write data delay:
- * - number of DIMMs
- *
- * 1 = 1/4 clock delay
- * 2 = 1/2 clock delay
- * 3 = 3/4 clock delay
- * 4 = 1 clock delay
- * 5 = 5/4 clock delay
- * 6 = 3/2 clock delay
- */
- popts->write_data_delay = 3;
+ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ if (i&1) { /* odd CS */
+ popts->cs_local_opts[i].odt_rd_cfg = 0;
+ popts->cs_local_opts[i].odt_wr_cfg = 0;
+ } else { /* even CS */
+ if ((CONFIG_DIMM_SLOTS_PER_CTLR == 2) &&
+ (pdimm[i/2].n_ranks != 0)) {
+ popts->cs_local_opts[i].odt_rd_cfg = 3;
+ popts->cs_local_opts[i].odt_wr_cfg = 3;
+ } else {
+ popts->cs_local_opts[i].odt_rd_cfg = 0;
+ popts->cs_local_opts[i].odt_wr_cfg = 4;
+ }
+ }
+ }
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
+ /* Get clk_adjust, cpo, write_data_delay, according to the board ddr
+ * freqency and n_banks specified in board_specific_parameters table.
*/
- popts->half_strength_driver_enable = 0;
+ ddr_freq = fsl_ddr_get_mem_data_rate() / 1000000;
+ for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
+ if (pdimm[j].n_ranks > 0) {
+ for (i = 0; i < num_params; i++) {
+ if (ddr_freq >= pbsp->datarate_mhz_low &&
+ ddr_freq <= pbsp->datarate_mhz_high &&
+ pdimm[j].n_ranks == pbsp->n_ranks) {
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->cpo_override = pbsp->cpo;
+ popts->write_data_delay =
+ pbsp->write_data_delay;
+ break;
+ }
+ pbsp++;
+ }
+ }
+ }
+
}
--
1.6.0.2
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2008-10-03 16:33 Haiying Wang
0 siblings, 0 replies; 430+ messages in thread
From: Haiying Wang @ 2008-10-03 16:33 UTC (permalink / raw)
To: u-boot
* Add board specific parameter table to choose correct cpo, clk_adjust,
write_data_delay, 2T based on board ddr frequency and n_ranks.
* Set odt_rd_cfg and odt_wr_cfg based on the dimm# and CS#.
* Set memory controller interleaving mode to bank interleaving, and disable
bank(chip select) interleaving mode by default, because the default on-board
DDR DIMMs are 2x512MB single-rank.
* Change CONFIG_ICS307_REFCLK_HZ from 33333333 to 33333000.
Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
---
board/freescale/mpc8572ds/ddr.c | 123 ++++++++++++++++++++++++++++++---------
include/configs/MPC8572DS.h | 3 +-
2 files changed, 97 insertions(+), 29 deletions(-)
diff --git a/board/freescale/mpc8572ds/ddr.c b/board/freescale/mpc8572ds/ddr.c
index 435893a..171a8d5 100644
--- a/board/freescale/mpc8572ds/ddr.c
+++ b/board/freescale/mpc8572ds/ddr.c
@@ -39,42 +39,109 @@ void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
}
}
+typedef struct {
+ u32 datarate_mhz_low;
+ u32 datarate_mhz_high;
+ u32 n_ranks;
+ u32 clk_adjust;
+ u32 cpo;
+ u32 write_data_delay;
+ u32 force_2T;
+} board_specific_parameters_t;
+
+/* ranges for parameters:
+ * wr_data_delay = 0-6
+ * clk adjust = 0-8
+ * cpo 2-0x1E (30)
+ */
+
+
+/* XXX: these values need to be checked for all interleaving modes. */
+/* XXX: No reliable dual-rank 800 MHz setting has been found. It may
+ * seem reliable, but errors will appear when memory intensive
+ * program is run. */
+/* XXX: Single rank at 800 MHz is OK. */
+const board_specific_parameters_t board_specific_parameters[][20] = {
+ {
+ /* memory controller 0 */
+ /* lo| hi| num| clk| cpo|wrdata|2T */
+ /* mhz| mhz|ranks|adjst| | delay| */
+ { 0, 333, 2, 6, 7, 3, 0},
+ {334, 400, 2, 6, 9, 3, 0},
+ {401, 549, 2, 6, 11, 3, 0},
+ {550, 680, 2, 1, 10, 5, 0},
+ {681, 850, 2, 1, 12, 5, 1},
+ { 0, 333, 1, 6, 7, 3, 0},
+ {334, 400, 1, 6, 9, 3, 0},
+ {401, 549, 1, 6, 11, 3, 0},
+ {550, 680, 1, 1, 10, 5, 0},
+ {681, 850, 1, 1, 12, 5, 0}
+ },
+
+ {
+ /* memory controller 1 */
+ /* lo| hi| num| clk| cpo|wrdata|2T */
+ /* mhz| mhz|ranks|adjst| | delay| */
+ { 0, 333, 2, 6, 7, 3, 0},
+ {334, 400, 2, 6, 9, 3, 0},
+ {401, 549, 2, 6, 11, 3, 0},
+ {550, 680, 2, 1, 11, 6, 0},
+ {681, 850, 2, 1, 13, 6, 1},
+ { 0, 333, 1, 6, 7, 3, 0},
+ {334, 400, 1, 6, 9, 3, 0},
+ {401, 549, 1, 6, 11, 3, 0},
+ {550, 680, 1, 1, 11, 6, 0},
+ {681, 850, 1, 1, 13, 6, 0}
+ }
+};
+
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
{
- /*
- * Factors to consider for clock adjust:
- * - number of chips on bus
- * - position of slot
- * - DDR1 vs. DDR2?
- * - ???
- *
- * This needs to be determined on a board-by-board basis.
- * 0110 3/4 cycle late
- * 0111 7/8 cycle late
- */
- popts->clk_adjust = 7;
+ const board_specific_parameters_t *pbsp =
+ &(board_specific_parameters[ctrl_num][0]);
+ const char *p;
+ u32 num_params = sizeof(board_specific_parameters[ctrl_num]) /
+ sizeof(board_specific_parameters[0][0]);
+ u32 i;
+ ulong ddr_freq;
- /*
- * Factors to consider for CPO:
- * - frequency
- * - ddr1 vs. ddr2
+ /* set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
+ * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
+ * there are two dimms in the controller, set odt_rd_cfg to 3 and
+ * odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
*/
- popts->cpo_override = 10;
+ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ if (i&1) { /* odd CS */
+ popts->cs_local_opts[i].odt_rd_cfg = 0;
+ popts->cs_local_opts[i].odt_wr_cfg = 0;
+ } else { /* even CS */
+ if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
+ popts->cs_local_opts[i].odt_rd_cfg = 0;
+ popts->cs_local_opts[i].odt_wr_cfg = 4;
+ } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
+ popts->cs_local_opts[i].odt_rd_cfg = 3;
+ popts->cs_local_opts[i].odt_wr_cfg = 3;
+ }
+ }
+ }
- /*
- * Factors to consider for write data delay:
- * - number of DIMMs
- *
- * 1 = 1/4 clock delay
- * 2 = 1/2 clock delay
- * 3 = 3/4 clock delay
- * 4 = 1 clock delay
- * 5 = 5/4 clock delay
- * 6 = 3/2 clock delay
+ /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+ * freqency and n_banks specified in board_specific_parameters table.
*/
- popts->write_data_delay = 5;
+ ddr_freq = get_ddr_freq(0) / 1000000;
+ for (i = 0; i < num_params; i++) {
+ if (ddr_freq >= pbsp->datarate_mhz_low &&
+ ddr_freq <= pbsp->datarate_mhz_high &&
+ pdimm->n_ranks == pbsp->n_ranks) {
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->cpo_override = pbsp->cpo;
+ popts->write_data_delay = pbsp->write_data_delay;
+ popts->twoT_en = pbsp->force_2T;
+ }
+ pbsp++;
+ }
/*
* Factors to consider for half-strength driver enable:
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index d7e3a88..82c2334 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -61,7 +61,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#endif
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */
-#define CONFIG_ICS307_REFCLK_HZ 33333333 /* ICS307 clock chip ref freq */
+#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
#define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq
from ICS307 instead of switches */
@@ -532,6 +532,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_BAUDRATE 115200
#define CONFIG_EXTRA_ENV_SETTINGS \
+ "memctl_intlv_ctl=2\0" \
"netdev=eth0\0" \
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
--
1.6.0.2
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2008-10-03 16:33 Haiying Wang
0 siblings, 0 replies; 430+ messages in thread
From: Haiying Wang @ 2008-10-03 16:33 UTC (permalink / raw)
To: u-boot
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
---
cpu/mpc8xxx/ddr/ctrl_regs.c | 13 +++++++++++++
1 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c
index 6297141..1783e92 100644
--- a/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -111,6 +111,7 @@ static void set_csn_config(int i, fsl_ddr_cfg_regs_t *ddr,
| ((row_bits_cs_n & 0x7) << 8)
| ((col_bits_cs_n & 0x7) << 0)
);
+ debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
}
/* Chip Select Configuration 2 (CSn_CONFIG_2) */
@@ -120,6 +121,7 @@ static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
unsigned int pasr_cfg = 0; /* Partial array self refresh config */
ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
+ debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
}
/* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
@@ -190,6 +192,7 @@ static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
| ((ext_caslat & 0x1) << 12)
| ((cntl_adj & 0x7) << 0)
);
+ debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
}
/* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
@@ -257,6 +260,7 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
| ((acttoact_mclk & 0x07) << 4)
| ((wrtord_mclk & 0x07) << 0)
);
+ debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
}
/* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
@@ -313,6 +317,7 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
| ((cke_pls & 0x7) << 6)
| ((four_act & 0x1f) << 0)
);
+ debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
}
/* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
@@ -379,6 +384,7 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
| ((mem_halt & 0x1) << 1)
| ((bi & 0x1) << 0)
);
+ debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
}
/* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
@@ -443,6 +449,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
| ((rcw_en & 0x1) << 2)
| ((md_en & 0x1) << 0)
);
+ debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
}
/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
@@ -455,6 +462,7 @@ static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr)
| ((esdmode2 & 0xFFFF) << 16)
| ((esdmode3 & 0xFFFF) << 0)
);
+ debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
}
/* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
@@ -474,6 +482,7 @@ static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr,
| ((refint & 0xFFFF) << 16)
| ((bstopre & 0x3FFF) << 0)
);
+ debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
}
/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
@@ -607,6 +616,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
| ((esdmode & 0xFFFF) << 16)
| ((sdmode & 0xFFFF) << 0)
);
+ debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
}
@@ -669,6 +679,7 @@ static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr)
| ((wwt & 0xf) << 16)
| (dll_lock & 0x3)
);
+ debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
}
/* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
@@ -685,6 +696,7 @@ static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr)
| ((wodt_on & 0xf) << 12)
| ((wodt_off & 0xf) << 8)
);
+ debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
}
/* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
@@ -992,6 +1004,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
| ((ea & 0xFFF) << 0) /* ending address MSB */
);
+ debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
set_csn_config(i, ddr, popts, dimm_params);
set_csn_config_2(i, ddr);
}
--
1.6.0.2
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2008-10-03 16:33 Haiying Wang
0 siblings, 0 replies; 430+ messages in thread
From: Haiying Wang @ 2008-10-03 16:33 UTC (permalink / raw)
To: u-boot
* Check DDR interleaving mode from environment by reading memctl_intlv_ctl and
ba_intlv_ctl.
* Print DDR interleaving mode information
* Add doc/README.fsl-ddr to describe the interleaving setting
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
---
cpu/mpc8xxx/ddr/main.c | 37 +++++++++++++++++++++
cpu/mpc8xxx/ddr/options.c | 80 ++++++++++++++++++++++++++++++++++++++++++---
doc/README.fsl-ddr | 69 ++++++++++++++++++++++++++++++++++++++
3 files changed, 181 insertions(+), 5 deletions(-)
create mode 100644 doc/README.fsl-ddr
diff --git a/cpu/mpc8xxx/ddr/main.c b/cpu/mpc8xxx/ddr/main.c
index 98a8651..d5173c3 100644
--- a/cpu/mpc8xxx/ddr/main.c
+++ b/cpu/mpc8xxx/ddr/main.c
@@ -164,6 +164,24 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo,
}
if (j == 2) {
*memctl_interleaving = 1;
+
+ printf("\nMemory controller interleaving enabled: ");
+
+ switch (pinfo->memctl_opts[0].memctl_interleaving_mode) {
+ case FSL_DDR_CACHE_LINE_INTERLEAVING:
+ printf("Cache-line interleaving!\n");
+ break;
+ case FSL_DDR_PAGE_INTERLEAVING:
+ printf("Page interleaving!\n");
+ break;
+ case FSL_DDR_BANK_INTERLEAVING:
+ printf("Bank interleaving!\n");
+ break;
+ case FSL_DDR_SUPERBANK_INTERLEAVING:
+ printf("Super bank interleaving\n");
+ default:
+ break;
+ }
}
/* Check that all controllers are rank interleaving. */
@@ -175,6 +193,25 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo,
}
if (j == 2) {
*rank_interleaving = 1;
+
+ printf("Bank(chip-select) interleaving enabled: ");
+
+ switch (pinfo->memctl_opts[0].ba_intlv_ctl &
+ FSL_DDR_CS0_CS1_CS2_CS3) {
+ case FSL_DDR_CS0_CS1_CS2_CS3:
+ printf("CS0+CS1+CS2+CS3\n");
+ break;
+ case FSL_DDR_CS0_CS1:
+ printf("CS0+CS1\n");
+ break;
+ case FSL_DDR_CS2_CS3:
+ printf("CS2+CS3\n");
+ break;
+ case FSL_DDR_CS0_CS1_AND_CS2_CS3:
+ printf("CS0+CS1 and CS2+CS3\n");
+ default:
+ break;
+ }
}
if (*memctl_interleaving) {
diff --git a/cpu/mpc8xxx/ddr/options.c b/cpu/mpc8xxx/ddr/options.c
index 99b5685..714e88d 100644
--- a/cpu/mpc8xxx/ddr/options.c
+++ b/cpu/mpc8xxx/ddr/options.c
@@ -22,6 +22,7 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
unsigned int ctrl_num)
{
unsigned int i;
+ const char *p;
/* Chip select options. */
@@ -181,17 +182,86 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
#error "FIXME determine four activates for DDR3"
#endif
- /* ODT should only be used for DDR2 */
-
- /* FIXME? */
-
/*
- * Interleaving checks.
+ * Check interleaving configuration from environment.
+ * Please refer to doc/README.fsl-ddr for the detail.
*
* If memory controller interleaving is enabled, then the data
* bus widths must be programmed identically for the 2 memory
* controllers.
+ *
+ * XXX: Attempt to set both controllers to the same chip select
+ * interleaving mode. It will do a best effort to get the
+ * requested ranks interleaved together such that the result
+ * should be a subset of the requested configuration.
*/
+ if ((p = getenv("memctl_intlv_ctl")) != NULL) {
+ if (pdimm[0].n_ranks == 0) {
+ printf("There is no rank on CS0. Because only rank on \
+ CS0 and ranks chip-select interleaved with CS0\
+ are controller interleaved, force non memory \
+ controller interleaving\n");
+ popts->memctl_interleaving = 0;
+ } else {
+ popts->memctl_interleaving = 1;
+ if (strcmp(p, "cacheline") == 0)
+ popts->memctl_interleaving_mode =
+ FSL_DDR_CACHE_LINE_INTERLEAVING;
+ else if (strcmp(p, "page") == 0)
+ popts->memctl_interleaving_mode =
+ FSL_DDR_PAGE_INTERLEAVING;
+ else if (strcmp(p, "bank") == 0)
+ popts->memctl_interleaving_mode =
+ FSL_DDR_BANK_INTERLEAVING;
+ else if (strcmp(p, "superbank") == 0)
+ popts->memctl_interleaving_mode =
+ FSL_DDR_SUPERBANK_INTERLEAVING;
+ else
+ popts->memctl_interleaving_mode =
+ simple_strtoul(p, NULL, 0);
+ }
+ }
+
+ if( (p = getenv("ba_intlv_ctl")) != NULL) {
+ if (strcmp(p, "cs0_cs1") == 0)
+ popts->ba_intlv_ctl = FSL_DDR_CS0_CS1;
+ else if (strcmp(p, "cs2_cs3") == 0)
+ popts->ba_intlv_ctl = FSL_DDR_CS2_CS3;
+ else if (strcmp(p, "cs0_cs1_and_cs2_cs3") == 0)
+ popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3;
+ else if (strcmp(p, "cs0_cs1_cs2_cs3") == 0)
+ popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3;
+ else
+ popts->ba_intlv_ctl = simple_strtoul(p, NULL, 0);
+
+ switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
+ case FSL_DDR_CS0_CS1_CS2_CS3:
+ case FSL_DDR_CS0_CS1:
+ if (pdimm[0].n_ranks != 2) {
+ popts->ba_intlv_ctl = 0;
+ printf("No enough bank(chip-select) for \
+ CS0+CS1, force non-interleaving!\n");
+ }
+ break;
+ case FSL_DDR_CS2_CS3:
+ if (pdimm[1].n_ranks !=2){
+ popts->ba_intlv_ctl = 0;
+ printf("No enough bank(CS) for CS2+CS3, \
+ force non-interleaving!\n");
+ }
+ break;
+ case FSL_DDR_CS0_CS1_AND_CS2_CS3:
+ if ((pdimm[0].n_ranks != 2)||(pdimm[1].n_ranks != 2)) {
+ popts->ba_intlv_ctl = 0;
+ printf("No enough bank(CS) for CS0+CS1 or \
+ CS2+CS3, force non-interleaving!\n");
+ }
+ break;
+ default:
+ popts->ba_intlv_ctl = 0;
+ break;
+ }
+ }
fsl_ddr_board_options(popts, pdimm, ctrl_num);
diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr
new file mode 100644
index 0000000..357ec05
--- /dev/null
+++ b/doc/README.fsl-ddr
@@ -0,0 +1,69 @@
+
+Table of interleaving modes supported in cpu/8xxx/ddr/
+======================================================
+ +-------------+---------------------------------------------------------+
+ | | Rank Interleaving |
+ | +--------+-----------+-----------+------------+-----------+
+ |Memory | | | | 2x2 | 4x1 |
+ |Controller | None | 2x1 lower | 2x1 upper | {CS0+CS1}, | {CS0+CS1+ |
+ |Interleaving | | {CS0+CS1} | {CS2+CS3} | {CS2+CS3} | CS2+CS3} |
+ +-------------+--------+-----------+-----------+------------+-----------+
+ |None | Yes | Yes | Yes | Yes | Yes |
+ +-------------+--------+-----------+-----------+------------+-----------+
+ |Cacheline | Yes | Yes | No | No, Only(*)| Yes |
+ | |CS0 Only| | | {CS0+CS1} | |
+ +-------------+--------+-----------+-----------+------------+-----------+
+ |Page | Yes | Yes | No | No, Only(*)| Yes |
+ | |CS0 Only| | | {CS0+CS1} | |
+ +-------------+--------+-----------+-----------+------------+-----------+
+ |Bank | Yes | Yes | No | No, Only(*)| Yes |
+ | |CS0 Only| | | {CS0+CS1} | |
+ +-------------+--------+-----------+-----------+------------+-----------+
+ |Superbank | No | Yes | No | No, Only(*)| Yes |
+ | | | | | {CS0+CS1} | |
+ +-------------+--------+-----------+-----------+------------+-----------+
+ (*) Although the hardware can be configured with memory controller
+ interleaving using "2x2" rank interleaving, it only interleaves {CS0+CS1}
+ from each controller. {CS2+CS3} on each controller are only rank
+ interleaved on that controller.
+
+The ways to configure the ddr interleaving mode
+==============================================
+1. In board header file(e.g.MPC8572DS.h), add default interleaving setting
+ under "CONFIG_EXTRA_ENV_SETTINGS", like:
+ #define CONFIG_EXTRA_ENV_SETTINGS \
+ "memctl_intlv_ctl=2\0" \
+ ......
+
+2. Run u-boot "setenv" command to configure the memory interleaving mode.
+ Either numerical or string value is accepted.
+
+ # disable memory controller interleaving
+ setenv memctl_intlv_ctl
+
+ # cacheline interleaving
+ setenv memctl_intlv_ctl 0 or setenv memctl_intlv_ctl cacheline
+
+ # page interleaving
+ setenv memctl_intlv_ctl 1 or setenv memctl_intlv_ctl page
+
+ # bank interleaving
+ setenv memctl_intlv_ctl 2 or setenv memctl_intlv_ctl bank
+
+ # superbank
+ setenv memctl_intlv_ctl 3 or setenv memctl_intlv_ctl superbank
+
+ # disable bank (chip-select) interleaving
+ setenv ba_intlv_ctl
+
+ # bank(chip-select) interleaving cs0+cs1
+ setenv ba_intlv_ctl 0x40 or setenv ba_intlv_ctl cs0_cs1
+
+ # bank(chip-select) interleaving cs2+cs3
+ setenv ba_intlv_ctl 0x20 or setenv ba_intlv_ctl cs2_cs3
+
+ # bank(chip-select) interleaving (cs0+cs1) and (cs2+cs3) (2x2)
+ setenv ba_intlv_ctl 0x60 or setenv ba_intlv_ctl cs0_cs1_and_cs2_cs3
+
+ # bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1)
+ setenv ba_intlv_ctl 0x04 or setenv ba_intlv_ctl cs0_cs1_cs2_cs3
+
--
1.6.0.2
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2008-10-03 16:32 Haiying Wang
0 siblings, 0 replies; 430+ messages in thread
From: Haiying Wang @ 2008-10-03 16:32 UTC (permalink / raw)
To: u-boot
Because some dimm parameters like n_ranks needs to be used with the board
frequency to choose the board parameters like clk_adjust etc. in the
board_specific_paramesters table of the board ddr file, we need to pass
the dimm parameters to the board file.
* move ddr dimm parameters header file from /cpu to /include directory.
* add ddr dimm parameters to populate board specific options.
* Fix fsl_ddr_board_options() for all the 8xxx boards which call this function.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
---
board/atum8548/ddr.c | 5 ++-
board/freescale/mpc8536ds/ddr.c | 5 ++-
board/freescale/mpc8540ads/ddr.c | 5 ++-
board/freescale/mpc8541cds/ddr.c | 5 ++-
board/freescale/mpc8544ds/ddr.c | 5 ++-
board/freescale/mpc8548cds/ddr.c | 5 ++-
board/freescale/mpc8555cds/ddr.c | 5 ++-
board/freescale/mpc8560ads/ddr.c | 5 ++-
board/freescale/mpc8568mds/ddr.c | 5 ++-
board/freescale/mpc8572ds/ddr.c | 5 ++-
board/freescale/mpc8610hpcd/ddr.c | 5 ++-
board/freescale/mpc8641hpcn/ddr.c | 5 ++-
board/mpc8540eval/ddr.c | 5 ++-
board/pm854/ddr.c | 5 ++-
board/pm856/ddr.c | 5 ++-
board/sbc8548/ddr.c | 5 ++-
board/sbc8560/ddr.c | 5 ++-
board/sbc8641d/ddr.c | 5 ++-
board/socrates/ddr.c | 5 ++-
board/stxgp3/ddr.c | 5 ++-
board/stxssa/ddr.c | 5 ++-
cpu/mpc8xxx/ddr/ddr.h | 3 +-
cpu/mpc8xxx/ddr/ddr1_2_dimm_params.h | 84 ---------------------------------
cpu/mpc8xxx/ddr/main.c | 3 +-
cpu/mpc8xxx/ddr/options.c | 4 +-
include/asm-ppc/fsl_ddr_dimm_params.h | 84 +++++++++++++++++++++++++++++++++
26 files changed, 175 insertions(+), 108 deletions(-)
delete mode 100644 cpu/mpc8xxx/ddr/ddr1_2_dimm_params.h
create mode 100644 include/asm-ppc/fsl_ddr_dimm_params.h
diff --git a/board/atum8548/ddr.c b/board/atum8548/ddr.c
index f07d746..ab64fa8 100644
--- a/board/atum8548/ddr.c
+++ b/board/atum8548/ddr.c
@@ -10,6 +10,7 @@
#include <i2c.h>
#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
static void
get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
@@ -37,7 +38,9 @@ void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
}
}
-void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
{
/*
* Factors to consider for clock adjust:
diff --git a/board/freescale/mpc8536ds/ddr.c b/board/freescale/mpc8536ds/ddr.c
index 2e88c79..3135d6d 100644
--- a/board/freescale/mpc8536ds/ddr.c
+++ b/board/freescale/mpc8536ds/ddr.c
@@ -10,6 +10,7 @@
#include <i2c.h>
#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
{
@@ -36,7 +37,9 @@ void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
}
}
-void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
{
/*
* Factors to consider for clock adjust:
diff --git a/board/freescale/mpc8540ads/ddr.c b/board/freescale/mpc8540ads/ddr.c
index 45372f4..7850794 100644
--- a/board/freescale/mpc8540ads/ddr.c
+++ b/board/freescale/mpc8540ads/ddr.c
@@ -10,6 +10,7 @@
#include <i2c.h>
#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
static void
get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address)
@@ -40,7 +41,9 @@ fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
}
}
-void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
{
/*
* Factors to consider for CPO:
diff --git a/board/freescale/mpc8541cds/ddr.c b/board/freescale/mpc8541cds/ddr.c
index 11ce57d..c84a6cb 100644
--- a/board/freescale/mpc8541cds/ddr.c
+++ b/board/freescale/mpc8541cds/ddr.c
@@ -10,6 +10,7 @@
#include <i2c.h>
#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
static void
get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address)
@@ -36,7 +37,9 @@ void fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
}
}
-void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
{
/*
* Factors to consider for clock adjust:
diff --git a/board/freescale/mpc8544ds/ddr.c b/board/freescale/mpc8544ds/ddr.c
index bbb5ee2..34f84a2 100644
--- a/board/freescale/mpc8544ds/ddr.c
+++ b/board/freescale/mpc8544ds/ddr.c
@@ -10,6 +10,7 @@
#include <i2c.h>
#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
static void
get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
@@ -37,7 +38,9 @@ void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
}
}
-void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
{
/*
* Factors to consider for clock adjust:
diff --git a/board/freescale/mpc8548cds/ddr.c b/board/freescale/mpc8548cds/ddr.c
index f07d746..ab64fa8 100644
--- a/board/freescale/mpc8548cds/ddr.c
+++ b/board/freescale/mpc8548cds/ddr.c
@@ -10,6 +10,7 @@
#include <i2c.h>
#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
static void
get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
@@ -37,7 +38,9 @@ void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
}
}
-void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
{
/*
* Factors to consider for clock adjust:
diff --git a/board/freescale/mpc8555cds/ddr.c b/board/freescale/mpc8555cds/ddr.c
index 11ce57d..c84a6cb 100644
--- a/board/freescale/mpc8555cds/ddr.c
+++ b/board/freescale/mpc8555cds/ddr.c
@@ -10,6 +10,7 @@
#include <i2c.h>
#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
static void
get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address)
@@ -36,7 +37,9 @@ void fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
}
}
-void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
{
/*
* Factors to consider for clock adjust:
diff --git a/board/freescale/mpc8560ads/ddr.c b/board/freescale/mpc8560ads/ddr.c
index 45372f4..7850794 100644
--- a/board/freescale/mpc8560ads/ddr.c
+++ b/board/freescale/mpc8560ads/ddr.c
@@ -10,6 +10,7 @@
#include <i2c.h>
#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
static void
get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address)
@@ -40,7 +41,9 @@ fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
}
}
-void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
{
/*
* Factors to consider for CPO:
diff --git a/board/freescale/mpc8568mds/ddr.c b/board/freescale/mpc8568mds/ddr.c
index 1b8ecec..482fd91 100644
--- a/board/freescale/mpc8568mds/ddr.c
+++ b/board/freescale/mpc8568mds/ddr.c
@@ -10,6 +10,7 @@
#include <i2c.h>
#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
static void
get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
@@ -38,7 +39,9 @@ void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
}
}
-void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
{
/*
* Factors to consider for clock adjust:
diff --git a/board/freescale/mpc8572ds/ddr.c b/board/freescale/mpc8572ds/ddr.c
index 5f8c555..435893a 100644
--- a/board/freescale/mpc8572ds/ddr.c
+++ b/board/freescale/mpc8572ds/ddr.c
@@ -10,6 +10,7 @@
#include <i2c.h>
#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
{
@@ -38,7 +39,9 @@ void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
}
}
-void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
{
/*
* Factors to consider for clock adjust:
diff --git a/board/freescale/mpc8610hpcd/ddr.c b/board/freescale/mpc8610hpcd/ddr.c
index 2d22da1..414ac24 100644
--- a/board/freescale/mpc8610hpcd/ddr.c
+++ b/board/freescale/mpc8610hpcd/ddr.c
@@ -10,6 +10,7 @@
#include <i2c.h>
#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
static void
get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
@@ -36,7 +37,9 @@ void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
}
}
-void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
{
/*
* Factors to consider for clock adjust:
diff --git a/board/freescale/mpc8641hpcn/ddr.c b/board/freescale/mpc8641hpcn/ddr.c
index 5163abf..23497f9 100644
--- a/board/freescale/mpc8641hpcn/ddr.c
+++ b/board/freescale/mpc8641hpcn/ddr.c
@@ -10,6 +10,7 @@
#include <i2c.h>
#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
static void
get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
@@ -45,7 +46,9 @@ void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
}
}
-void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
{
/*
* Factors to consider for clock adjust:
diff --git a/board/mpc8540eval/ddr.c b/board/mpc8540eval/ddr.c
index 45372f4..7850794 100644
--- a/board/mpc8540eval/ddr.c
+++ b/board/mpc8540eval/ddr.c
@@ -10,6 +10,7 @@
#include <i2c.h>
#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
static void
get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address)
@@ -40,7 +41,9 @@ fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
}
}
-void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
{
/*
* Factors to consider for CPO:
diff --git a/board/pm854/ddr.c b/board/pm854/ddr.c
index 45372f4..7850794 100644
--- a/board/pm854/ddr.c
+++ b/board/pm854/ddr.c
@@ -10,6 +10,7 @@
#include <i2c.h>
#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
static void
get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address)
@@ -40,7 +41,9 @@ fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
}
}
-void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
{
/*
* Factors to consider for CPO:
diff --git a/board/pm856/ddr.c b/board/pm856/ddr.c
index 45372f4..7850794 100644
--- a/board/pm856/ddr.c
+++ b/board/pm856/ddr.c
@@ -10,6 +10,7 @@
#include <i2c.h>
#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
static void
get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address)
@@ -40,7 +41,9 @@ fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
}
}
-void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
{
/*
* Factors to consider for CPO:
diff --git a/board/sbc8548/ddr.c b/board/sbc8548/ddr.c
index f07d746..ab64fa8 100644
--- a/board/sbc8548/ddr.c
+++ b/board/sbc8548/ddr.c
@@ -10,6 +10,7 @@
#include <i2c.h>
#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
static void
get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
@@ -37,7 +38,9 @@ void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
}
}
-void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
{
/*
* Factors to consider for clock adjust:
diff --git a/board/sbc8560/ddr.c b/board/sbc8560/ddr.c
index 45372f4..7850794 100644
--- a/board/sbc8560/ddr.c
+++ b/board/sbc8560/ddr.c
@@ -10,6 +10,7 @@
#include <i2c.h>
#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
static void
get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address)
@@ -40,7 +41,9 @@ fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
}
}
-void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
{
/*
* Factors to consider for CPO:
diff --git a/board/sbc8641d/ddr.c b/board/sbc8641d/ddr.c
index 5163abf..23497f9 100644
--- a/board/sbc8641d/ddr.c
+++ b/board/sbc8641d/ddr.c
@@ -10,6 +10,7 @@
#include <i2c.h>
#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
static void
get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
@@ -45,7 +46,9 @@ void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
}
}
-void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
{
/*
* Factors to consider for clock adjust:
diff --git a/board/socrates/ddr.c b/board/socrates/ddr.c
index 62a5951..2b62b84 100644
--- a/board/socrates/ddr.c
+++ b/board/socrates/ddr.c
@@ -10,6 +10,7 @@
#include <i2c.h>
#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
static void
get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
@@ -37,7 +38,9 @@ void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
}
}
-void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
{
/*
* Factors to consider for clock adjust:
diff --git a/board/stxgp3/ddr.c b/board/stxgp3/ddr.c
index 45372f4..7850794 100644
--- a/board/stxgp3/ddr.c
+++ b/board/stxgp3/ddr.c
@@ -10,6 +10,7 @@
#include <i2c.h>
#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
static void
get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address)
@@ -40,7 +41,9 @@ fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
}
}
-void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
{
/*
* Factors to consider for CPO:
diff --git a/board/stxssa/ddr.c b/board/stxssa/ddr.c
index 45372f4..7850794 100644
--- a/board/stxssa/ddr.c
+++ b/board/stxssa/ddr.c
@@ -10,6 +10,7 @@
#include <i2c.h>
#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
static void
get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address)
@@ -40,7 +41,9 @@ fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
}
}
-void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
{
/*
* Factors to consider for CPO:
diff --git a/cpu/mpc8xxx/ddr/ddr.h b/cpu/mpc8xxx/ddr/ddr.h
index f5dc40a..0372164 100644
--- a/cpu/mpc8xxx/ddr/ddr.h
+++ b/cpu/mpc8xxx/ddr/ddr.h
@@ -10,8 +10,8 @@
#define FSL_DDR_MAIN_H
#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
-#include "ddr1_2_dimm_params.h"
#include "common_timing_params.h"
/*
@@ -71,6 +71,7 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
unsigned int number_of_dimms);
extern unsigned int populate_memctl_options(int all_DIMMs_registered,
memctl_options_t *popts,
+ dimm_params_t *pdimm,
unsigned int ctrl_num);
extern unsigned int mclk_to_picos(unsigned int mclk);
diff --git a/cpu/mpc8xxx/ddr/ddr1_2_dimm_params.h b/cpu/mpc8xxx/ddr/ddr1_2_dimm_params.h
deleted file mode 100644
index c794eed..0000000
--- a/cpu/mpc8xxx/ddr/ddr1_2_dimm_params.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- */
-
-#ifndef DDR2_DIMM_PARAMS_H
-#define DDR2_DIMM_PARAMS_H
-
-/* Parameters for a DDR2 dimm computed from the SPD */
-typedef struct dimm_params_s {
-
- /* DIMM organization parameters */
- char mpart[19]; /* guaranteed null terminated */
-
- unsigned int n_ranks;
- unsigned long long rank_density;
- unsigned long long capacity;
- unsigned int data_width;
- unsigned int primary_sdram_width;
- unsigned int ec_sdram_width;
- unsigned int registered_dimm;
-
- /* SDRAM device parameters */
- unsigned int n_row_addr;
- unsigned int n_col_addr;
- unsigned int edc_config; /* 0 = none, 1 = parity, 2 = ECC */
- unsigned int n_banks_per_sdram_device;
- unsigned int burst_lengths_bitmask; /* BL=4 bit 2, BL=8 = bit 3 */
- unsigned int row_density;
-
- /* used in computing base address of DIMMs */
- unsigned long long base_address;
-
- /* DIMM timing parameters */
-
- /*
- * SDRAM clock periods
- * The range for these are 1000-10000 so a short should be sufficient
- */
- unsigned int tCKmin_X_ps;
- unsigned int tCKmin_X_minus_1_ps;
- unsigned int tCKmin_X_minus_2_ps;
- unsigned int tCKmax_ps;
-
- /* SPD-defined CAS latencies */
- unsigned int caslat_X;
- unsigned int caslat_X_minus_1;
- unsigned int caslat_X_minus_2;
-
- unsigned int caslat_lowest_derated; /* Derated CAS latency */
-
- /* basic timing parameters */
- unsigned int tRCD_ps;
- unsigned int tRP_ps;
- unsigned int tRAS_ps;
-
- unsigned int tWR_ps; /* maximum = 63750 ps */
- unsigned int tWTR_ps; /* maximum = 63750 ps */
- unsigned int tRFC_ps; /* max = 255 ns + 256 ns + .75 ns
- = 511750 ps */
-
- unsigned int tRRD_ps; /* maximum = 63750 ps */
- unsigned int tRC_ps; /* maximum = 254 ns + .75 ns = 254750 ps */
-
- unsigned int refresh_rate_ps;
-
- unsigned int tIS_ps; /* byte 32, spd->ca_setup */
- unsigned int tIH_ps; /* byte 33, spd->ca_hold */
- unsigned int tDS_ps; /* byte 34, spd->data_setup */
- unsigned int tDH_ps; /* byte 35, spd->data_hold */
- unsigned int tRTP_ps; /* byte 38, spd->trtp */
- unsigned int tDQSQ_max_ps; /* byte 44, spd->tdqsq */
- unsigned int tQHS_ps; /* byte 45, spd->tqhs */
-} dimm_params_t;
-
-extern unsigned int ddr_compute_dimm_parameters(
- const generic_spd_eeprom_t *spd,
- dimm_params_t *pdimm,
- unsigned int dimm_number);
-
-#endif
diff --git a/cpu/mpc8xxx/ddr/main.c b/cpu/mpc8xxx/ddr/main.c
index d26c5c5..98a8651 100644
--- a/cpu/mpc8xxx/ddr/main.c
+++ b/cpu/mpc8xxx/ddr/main.c
@@ -319,7 +319,8 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step)
*/
populate_memctl_options(
timing_params[i].all_DIMMs_registered,
- &pinfo->memctl_opts[i], i);
+ &pinfo->memctl_opts[i],
+ &pinfo->dimm_params[i], i);
}
case STEP_ASSIGN_ADDRESSES:
diff --git a/cpu/mpc8xxx/ddr/options.c b/cpu/mpc8xxx/ddr/options.c
index 6c2b43c..99b5685 100644
--- a/cpu/mpc8xxx/ddr/options.c
+++ b/cpu/mpc8xxx/ddr/options.c
@@ -13,10 +13,12 @@
/* Board-specific functions defined in each board's ddr.c */
extern void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
unsigned int ctrl_num);
unsigned int populate_memctl_options(int all_DIMMs_registered,
memctl_options_t *popts,
+ dimm_params_t *pdimm,
unsigned int ctrl_num)
{
unsigned int i;
@@ -191,7 +193,7 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
* controllers.
*/
- fsl_ddr_board_options(popts, ctrl_num);
+ fsl_ddr_board_options(popts, pdimm, ctrl_num);
return 0;
}
diff --git a/include/asm-ppc/fsl_ddr_dimm_params.h b/include/asm-ppc/fsl_ddr_dimm_params.h
new file mode 100644
index 0000000..c794eed
--- /dev/null
+++ b/include/asm-ppc/fsl_ddr_dimm_params.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#ifndef DDR2_DIMM_PARAMS_H
+#define DDR2_DIMM_PARAMS_H
+
+/* Parameters for a DDR2 dimm computed from the SPD */
+typedef struct dimm_params_s {
+
+ /* DIMM organization parameters */
+ char mpart[19]; /* guaranteed null terminated */
+
+ unsigned int n_ranks;
+ unsigned long long rank_density;
+ unsigned long long capacity;
+ unsigned int data_width;
+ unsigned int primary_sdram_width;
+ unsigned int ec_sdram_width;
+ unsigned int registered_dimm;
+
+ /* SDRAM device parameters */
+ unsigned int n_row_addr;
+ unsigned int n_col_addr;
+ unsigned int edc_config; /* 0 = none, 1 = parity, 2 = ECC */
+ unsigned int n_banks_per_sdram_device;
+ unsigned int burst_lengths_bitmask; /* BL=4 bit 2, BL=8 = bit 3 */
+ unsigned int row_density;
+
+ /* used in computing base address of DIMMs */
+ unsigned long long base_address;
+
+ /* DIMM timing parameters */
+
+ /*
+ * SDRAM clock periods
+ * The range for these are 1000-10000 so a short should be sufficient
+ */
+ unsigned int tCKmin_X_ps;
+ unsigned int tCKmin_X_minus_1_ps;
+ unsigned int tCKmin_X_minus_2_ps;
+ unsigned int tCKmax_ps;
+
+ /* SPD-defined CAS latencies */
+ unsigned int caslat_X;
+ unsigned int caslat_X_minus_1;
+ unsigned int caslat_X_minus_2;
+
+ unsigned int caslat_lowest_derated; /* Derated CAS latency */
+
+ /* basic timing parameters */
+ unsigned int tRCD_ps;
+ unsigned int tRP_ps;
+ unsigned int tRAS_ps;
+
+ unsigned int tWR_ps; /* maximum = 63750 ps */
+ unsigned int tWTR_ps; /* maximum = 63750 ps */
+ unsigned int tRFC_ps; /* max = 255 ns + 256 ns + .75 ns
+ = 511750 ps */
+
+ unsigned int tRRD_ps; /* maximum = 63750 ps */
+ unsigned int tRC_ps; /* maximum = 254 ns + .75 ns = 254750 ps */
+
+ unsigned int refresh_rate_ps;
+
+ unsigned int tIS_ps; /* byte 32, spd->ca_setup */
+ unsigned int tIH_ps; /* byte 33, spd->ca_hold */
+ unsigned int tDS_ps; /* byte 34, spd->data_setup */
+ unsigned int tDH_ps; /* byte 35, spd->data_hold */
+ unsigned int tRTP_ps; /* byte 38, spd->trtp */
+ unsigned int tDQSQ_max_ps; /* byte 44, spd->tdqsq */
+ unsigned int tQHS_ps; /* byte 45, spd->tqhs */
+} dimm_params_t;
+
+extern unsigned int ddr_compute_dimm_parameters(
+ const generic_spd_eeprom_t *spd,
+ dimm_params_t *pdimm,
+ unsigned int dimm_number);
+
+#endif
--
1.6.0.2
^ permalink raw reply related [flat|nested] 430+ messages in thread
* [U-Boot] (no subject)
@ 2008-10-03 16:32 Haiying Wang
2008-10-03 23:35 ` Wolfgang Denk
0 siblings, 1 reply; 430+ messages in thread
From: Haiying Wang @ 2008-10-03 16:32 UTC (permalink / raw)
To: u-boot
Fix some bugs:
1. Correctly set intlv_ctl in cs_config.
2. Correctly set sa, ea in cs_bnds when bank interleaving mode is enabled.
3. Set base_address and total memory for each ddr controller in memory
controller interleaving mode.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
---
cpu/mpc8xxx/ddr/ctrl_regs.c | 61 +++++++++++++++++++++++++++++++-------
cpu/mpc8xxx/ddr/main.c | 5 +++
include/asm-ppc/fsl_ddr_sdram.h | 12 +++++++
3 files changed, 66 insertions(+), 12 deletions(-)
diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c
index e6c2a5c..6297141 100644
--- a/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -95,16 +95,10 @@ static void set_csn_config(int i, fsl_ddr_cfg_regs_t *ddr,
col_bits_cs_n = dimm_params[i/2].n_col_addr - 8;
}
- /* FIXME: intlv_en, intlv_ctl only on CS0_CONFIG */
- if (i != 0) {
- intlv_en = 0;
- intlv_ctl = 0;
- }
-
ddr->cs[i].config = (0
| ((cs_n_en & 0x1) << 31)
| ((intlv_en & 0x3) << 29)
- | ((intlv_en & 0xf) << 24)
+ | ((intlv_ctl & 0xf) << 24)
| ((ap_n_en & 0x1) << 23)
/* XXX: some implementation only have 1 bit starting@left */
@@ -874,8 +868,13 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
phys_size_t sa = 0;
phys_size_t ea = 0;
- if (popts->ba_intlv_ctl && i > 0) {
- /* Don't set up boundaries if bank interleaving */
+
+ if (popts->ba_intlv_ctl && (i > 0) &&
+ ((popts->ba_intlv_ctl & 0x60) != FSL_DDR_CS2_CS3 )) {
+ /* Don't set up boundaries for other CS
+ * other than CS0, if bank interleaving
+ * is enabled and not CS2+CS3 interleaved.
+ */
break;
}
@@ -894,7 +893,9 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
* on each controller is twice the amount present on
* each controller.
*/
- ea = (2 * common_dimm->total_mem >> dbw_cap_adj) - 1;
+ unsigned long long rank_density
+ = dimm_params[0].capacity;
+ ea = (2 * (rank_density >> dbw_cap_adj)) - 1;
}
else if (!popts->memctl_interleaving && popts->ba_intlv_ctl) {
/*
@@ -906,8 +907,44 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
* controller needs to be programmed into its
* respective CS0_BNDS.
*/
- sa = common_dimm->base_address;
- ea = sa + (common_dimm->total_mem >> dbw_cap_adj) - 1;
+ unsigned long long rank_density
+ = dimm_params[i/2].rank_density;
+ switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
+ case FSL_DDR_CS0_CS1_CS2_CS3:
+ /* CS0+CS1+CS2+CS3 interleaving, only CS0_CNDS
+ * needs to be set.
+ */
+ sa = common_dimm->base_address;
+ ea = sa + (4 * (rank_density >> dbw_cap_adj))-1;
+ break;
+ case FSL_DDR_CS0_CS1_AND_CS2_CS3:
+ /* CS0+CS1 and CS2+CS3 interleaving, CS0_CNDS
+ * and CS2_CNDS need to be set.
+ */
+ if (!(i&1)) {
+ sa = dimm_params[i/2].base_address;
+ ea = sa + (i * (rank_density >>
+ dbw_cap_adj)) - 1;
+ }
+ break;
+ case FSL_DDR_CS0_CS1:
+ /* CS0+CS1 interleaving, CS0_CNDS needs
+ * to be set
+ */
+ sa = common_dimm->base_address;
+ ea = sa + (2 * (rank_density >> dbw_cap_adj))-1;
+ break;
+ case FSL_DDR_CS2_CS3:
+ /* CS2+CS3 interleaving*/
+ if (i == 2) {
+ sa = dimm_params[i/2].base_address;
+ ea = sa + (2 * (rank_density >>
+ dbw_cap_adj)) - 1;
+ }
+ break;
+ default: /* No bank(chip-select) interleaving */
+ break;
+ }
}
else if (popts->memctl_interleaving && !popts->ba_intlv_ctl) {
/*
diff --git a/cpu/mpc8xxx/ddr/main.c b/cpu/mpc8xxx/ddr/main.c
index c340d56..d26c5c5 100644
--- a/cpu/mpc8xxx/ddr/main.c
+++ b/cpu/mpc8xxx/ddr/main.c
@@ -179,6 +179,7 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo,
if (*memctl_interleaving) {
phys_addr_t addr;
+ phys_size_t total_mem_per_ctlr = 0;
/*
* If interleaving between memory controllers,
@@ -197,14 +198,18 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo,
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
addr = 0;
+ pinfo->common_timing_params[i].base_address =
+ (phys_addr_t)addr;
for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
unsigned long long cap
= pinfo->dimm_params[i][j].capacity;
pinfo->dimm_params[i][j].base_address = addr;
addr += (phys_addr_t)(cap >> dbw_cap_adj[i]);
+ total_mem_per_ctlr += cap >> dbw_cap_adj[i];
}
}
+ pinfo->common_timing_params[0].total_mem = total_mem_per_ctlr;
} else {
/*
* Simple linear assignment if memory
diff --git a/include/asm-ppc/fsl_ddr_sdram.h b/include/asm-ppc/fsl_ddr_sdram.h
index 8adde34..c1ea7cd 100644
--- a/include/asm-ppc/fsl_ddr_sdram.h
+++ b/include/asm-ppc/fsl_ddr_sdram.h
@@ -36,6 +36,18 @@ typedef ddr2_spd_eeprom_t generic_spd_eeprom_t;
typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
#endif
+/* define bank(chip select) interleaving mode */
+#define FSL_DDR_CS0_CS1 0x40
+#define FSL_DDR_CS2_CS3 0x20
+#define FSL_DDR_CS0_CS1_AND_CS2_CS3 (FSL_DDR_CS0_CS1 | FSL_DDR_CS2_CS3)
+#define FSL_DDR_CS0_CS1_CS2_CS3 (FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04)
+
+/* define memory controller interleaving mode */
+#define FSL_DDR_CACHE_LINE_INTERLEAVING 0x0
+#define FSL_DDR_PAGE_INTERLEAVING 0x1
+#define FSL_DDR_BANK_INTERLEAVING 0x2
+#define FSL_DDR_SUPERBANK_INTERLEAVING 0x3
+
/* Record of register values computed */
typedef struct fsl_ddr_cfg_regs_s {
struct {
--
1.6.0.2
^ permalink raw reply related [flat|nested] 430+ messages in thread
end of thread, other threads:[~2019-08-29 15:21 UTC | newest]
Thread overview: 430+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2012-09-19 0:02 [U-Boot] (no subject) Troy Kisky
2012-09-19 0:02 ` [U-Boot] [PATCH 01/11] imximage: make header variable length Troy Kisky
2012-09-19 0:03 ` [U-Boot] [PATCH 02/11] imximage: check dcd_len as entries added Troy Kisky
2012-09-19 0:03 ` [U-Boot] [PATCH 03/11] imximage: enable word writes for version2 header Troy Kisky
2012-09-19 0:03 ` [U-Boot] [PATCH 04/11] imximage: cleanup parsing Troy Kisky
2012-09-19 0:03 ` [U-Boot] [PATCH 05/11] imximage: add expression evaluation Troy Kisky
2012-09-19 0:03 ` [U-Boot] [PATCH 06/11] imximage: add plugin commands Troy Kisky
2012-09-19 0:03 ` [U-Boot] [PATCH 07/11] imximage.cfg: run files through C preprocessor Troy Kisky
2012-09-19 0:03 ` [U-Boot] [PATCH 08/11] mx6: add plugin file for use with imximage.cfg Troy Kisky
2012-09-19 1:40 ` Troy Kisky
2012-09-19 0:03 ` [U-Boot] [PATCH 09/11] mx6qsabrelite: imximage.cfg: use symbols instead of hardcoded constants Troy Kisky
2012-09-19 0:03 ` [U-Boot] [PATCH 10/11] mx6qsabrelite: imximage.cfg: allow plugin to work Troy Kisky
2012-09-19 0:03 ` [U-Boot] [PATCH 11/11] RFC mx6qsabrelite: imximage.cfg: enable plugin mode Troy Kisky
2012-09-19 1:52 ` Troy Kisky
2012-09-22 2:38 ` [U-Boot] [PATCH V2 00/21] Add mx6solo/mx6duallite support Troy Kisky
2012-09-22 2:38 ` [U-Boot] [PATCH V2 01/21] imximage: make header variable length Troy Kisky
2012-09-23 10:57 ` Stefano Babic
2012-09-24 20:30 ` Troy Kisky
2012-09-25 11:08 ` Stefano Babic
2012-09-22 2:38 ` [U-Boot] [PATCH V2 02/21] imximage: check dcd_len as entries added Troy Kisky
2012-09-23 11:05 ` Stefano Babic
2012-09-24 20:54 ` Troy Kisky
2012-09-25 11:12 ` Stefano Babic
2012-09-22 2:39 ` [U-Boot] [PATCH V2 03/21] imximage: enable word writes for version2 header Troy Kisky
2012-09-22 2:39 ` [U-Boot] [PATCH V2 04/21] imximage: cleanup parsing Troy Kisky
2012-09-23 11:08 ` Stefano Babic
2012-09-24 20:59 ` Troy Kisky
2012-09-22 2:39 ` [U-Boot] [PATCH V2 05/21] imximage: add expression evaluation Troy Kisky
2012-09-23 14:56 ` Stefano Babic
2012-09-24 21:18 ` Troy Kisky
2012-09-22 2:39 ` [U-Boot] [PATCH V2 06/21] imximage: add plugin commands Troy Kisky
2012-09-23 15:38 ` Stefano Babic
2012-09-24 21:46 ` Troy Kisky
2012-09-22 2:39 ` [U-Boot] [PATCH V2 07/21] imximage.cfg: run files through C preprocessor Troy Kisky
2012-09-22 2:39 ` [U-Boot] [PATCH V2 08/21] mx6: add plugin file for use with imximage.cfg Troy Kisky
2012-09-22 4:06 ` Vikram Narayanan
2012-09-23 10:17 ` Stefano Babic
2012-09-23 16:23 ` Eric Nelson
2012-09-23 17:08 ` Stefano Babic
2012-09-23 23:29 ` Eric Nelson
2012-09-24 7:22 ` Stefano Babic
2012-09-24 13:48 ` Eric Nelson
2012-09-24 15:17 ` Stefano Babic
2012-09-24 22:23 ` Troy Kisky
2012-09-25 12:13 ` Stefano Babic
2012-09-24 20:46 ` Troy Kisky
2012-09-25 11:57 ` Stefano Babic
2012-09-22 2:39 ` [U-Boot] [PATCH V2 09/21] mx6q_4x_mt41j128.cfg: use symbols instead of hardcoded constants Troy Kisky
2012-09-22 2:39 ` [U-Boot] [PATCH V2 10/21] mx6q_4x_mt41j128.cfg: allow plugin to work Troy Kisky
2012-09-22 2:39 ` [U-Boot] [PATCH V2 11/21] mx6q_4x_mt41j128.cfg: enable plugin mode Troy Kisky
2012-09-22 2:39 ` [U-Boot] [PATCH V2 12/21] mx6q_4x_mt41j128.cfg: add comments Troy Kisky
2012-09-22 2:39 ` [U-Boot] [PATCH V2 13/21] mx6q_4x_mt41j128.cfg: use ddr3 mode for reset Troy Kisky
2012-09-22 2:39 ` [U-Boot] [PATCH V2 14/21] mx6q_4x_mt41j128.cfg: skip initiailizing non-existent memory Troy Kisky
2012-09-22 2:39 ` [U-Boot] [PATCH V2 15/21] mx6q_4x_mt41j128.cfg: reorder for more efficient storage Troy Kisky
2012-09-22 17:27 ` Fabio Estevam
2012-09-22 17:34 ` Troy Kisky
2012-09-22 2:39 ` [U-Boot] [PATCH V2 16/21] mx6q_4x_mt41j128.cfg: force ZQ calibration Troy Kisky
2012-09-22 2:39 ` [U-Boot] [PATCH V2 17/21] mx6: soc: add get_cpu_type Troy Kisky
2012-09-22 2:50 ` Fabio Estevam
2012-09-22 17:07 ` Troy Kisky
2012-09-23 14:59 ` Stefano Babic
2012-09-22 2:39 ` [U-Boot] [PATCH V2 18/21] arch-mx6: add mx6dl_pins.h Troy Kisky
2012-09-22 4:10 ` Vikram Narayanan
2012-09-22 17:17 ` Troy Kisky
2012-09-22 2:39 ` [U-Boot] [PATCH V2 19/21] mx6qsabrelite: add support for mx6 solo/duallite Troy Kisky
2012-09-22 4:12 ` Vikram Narayanan
2012-09-22 17:24 ` Troy Kisky
2012-09-22 2:39 ` [U-Boot] [PATCH V2 20/21] mx6q_4x_mt41j128.cfg: add mx6 solo/duallite support Troy Kisky
2012-09-22 2:39 ` [U-Boot] [PATCH V2 21/21] mx6qsabrelite: change CONFIG_SYS_PROMPT Troy Kisky
2012-09-22 6:21 ` [U-Boot] [PATCH V2 00/21] Add mx6solo/mx6duallite support Dirk Behme
2012-09-22 16:53 ` Troy Kisky
2012-10-04 1:47 ` [U-Boot] [PATCH V3 00/32] " Troy Kisky
2012-10-04 1:47 ` [U-Boot] [PATCH V3 01/32] imximage: check dcd_len as entries added Troy Kisky
2012-10-20 15:45 ` Stefano Babic
2012-10-04 1:47 ` [U-Boot] [PATCH V3 02/32] imximage: remove redundant setting of app_dest_ptr Troy Kisky
2012-10-08 13:17 ` Stefano Babic
2012-10-20 15:46 ` Stefano Babic
2012-10-04 1:47 ` [U-Boot] [PATCH V3 03/32] imximage: move flash_offset check to common location Troy Kisky
2012-10-08 13:19 ` Stefano Babic
2012-10-18 18:40 ` Troy Kisky
2012-10-19 8:01 ` Stefano Babic
2012-10-20 15:46 ` Stefano Babic
2012-10-04 1:47 ` [U-Boot] [PATCH V3 04/32] imximage: fix size of image to load Troy Kisky
2012-10-20 15:47 ` Stefano Babic
2012-10-04 1:47 ` [U-Boot] [PATCH V3 05/32] imximage: delay setting of image size Troy Kisky
2012-10-20 15:47 ` Stefano Babic
2012-10-04 1:47 ` [U-Boot] [PATCH V3 06/32] imximage: change parameters to set_imx_hdr Troy Kisky
2012-10-20 15:48 ` Stefano Babic
2012-10-04 1:47 ` [U-Boot] [PATCH V3 07/32] imximage: make set_imx_hdr_v1/v2 easier to read Troy Kisky
2012-10-20 15:48 ` Stefano Babic
2012-10-04 1:47 ` [U-Boot] [PATCH V3 08/32] imximage: make header variable length Troy Kisky
2012-10-20 15:52 ` Stefano Babic
2012-10-21 1:31 ` Troy Kisky
2012-10-21 8:35 ` Stefano Babic
2012-10-22 21:03 ` Troy Kisky
2012-11-28 1:31 ` [U-Boot] [PATCH V4 00/11] imximage series Troy Kisky
2012-11-28 1:31 ` [U-Boot] [PATCH V4 01/11] imximage: mx53 needs transfer length a multiple of 512 Troy Kisky
2012-11-28 9:27 ` Wolfgang Denk
2012-11-28 18:18 ` Troy Kisky
2012-11-28 20:25 ` Wolfgang Denk
2012-11-28 21:05 ` Troy Kisky
2012-11-28 21:35 ` Wolfgang Denk
2012-11-29 2:42 ` Troy Kisky
2012-11-29 5:28 ` Wolfgang Denk
2012-12-03 9:23 ` Stefano Babic
2012-12-03 9:12 ` Stefano Babic
2012-11-28 18:26 ` Troy Kisky
2012-11-28 10:34 ` Liu Hui-R64343
2012-11-28 1:31 ` [U-Boot] [PATCH V4 02/11] imximage: make header variable length Troy Kisky
2012-11-28 10:42 ` Liu Hui-R64343
2012-11-28 1:31 ` [U-Boot] [PATCH V4 03/11] imximage: remove static imximage_version Troy Kisky
2012-11-28 10:43 ` Liu Hui-R64343
2012-11-28 1:31 ` [U-Boot] [PATCH V4 04/11] imximage: prepare to move static variables to struct data_src Troy Kisky
2012-11-28 9:38 ` Wolfgang Denk
2012-11-28 18:36 ` Troy Kisky
2012-11-28 20:30 ` Wolfgang Denk
2012-11-28 1:31 ` [U-Boot] [PATCH V4 05/11] imximage: change parameters for set_dcd_val/set_imx_hdr Troy Kisky
2012-11-28 10:43 ` Liu Hui-R64343
2012-11-28 1:31 ` [U-Boot] [PATCH V4 06/11] imximage: move set_imx_hdr to struct data_src Troy Kisky
2012-11-28 10:45 ` Liu Hui-R64343
2012-11-28 1:31 ` [U-Boot] [PATCH V4 07/11] imximage: move set_dcd_val " Troy Kisky
2012-11-28 10:47 ` Liu Hui-R64343
2012-11-28 1:31 ` [U-Boot] [PATCH V4 08/11] imximage: enable word writes for version2 header Troy Kisky
2012-11-28 9:39 ` Wolfgang Denk
2012-11-28 20:40 ` Troy Kisky
2012-12-04 8:23 ` Stefano Babic
2012-11-28 10:47 ` Liu Hui-R64343
2012-11-28 1:31 ` [U-Boot] [PATCH V4 09/11] tools: add parse_helper file Troy Kisky
2012-11-28 9:41 ` Wolfgang Denk
2012-11-28 10:48 ` Liu Hui-R64343
2012-11-28 1:31 ` [U-Boot] [PATCH V4 10/11] imximage: use parse_helper functions Troy Kisky
2012-11-28 10:48 ` Liu Hui-R64343
2012-11-28 1:31 ` [U-Boot] [PATCH V4 11/11] parse_helper: add expression evaluation Troy Kisky
2012-11-28 10:49 ` Liu Hui-R64343
2012-11-28 9:30 ` [U-Boot] [PATCH V4 00/11] imximage series Wolfgang Denk
2012-11-28 18:29 ` Troy Kisky
2012-10-04 1:47 ` [U-Boot] [PATCH V3 09/32] imximage: remove static imximage_version Troy Kisky
2012-10-04 1:47 ` [U-Boot] [PATCH V3 10/32] imximage: prepare to move static variables to struct data_src Troy Kisky
2012-10-04 1:47 ` [U-Boot] [PATCH V3 11/32] imximage: change parameters for set_dcd_val/set_imx_hdr Troy Kisky
2012-10-04 1:47 ` [U-Boot] [PATCH V3 12/32] imximage: move set_imx_hdr to struct data_src Troy Kisky
2012-10-04 1:47 ` [U-Boot] [PATCH V3 13/32] imximage: move set_dcd_val " Troy Kisky
2012-10-04 1:47 ` [U-Boot] [PATCH V3 14/32] imximage: enable word writes for version2 header Troy Kisky
2012-10-04 1:47 ` [U-Boot] [PATCH V3 15/32] tools: add parse_helper file Troy Kisky
2012-10-04 1:47 ` [U-Boot] [PATCH V3 16/32] imximage: use parse_helper functions Troy Kisky
2012-10-04 1:47 ` [U-Boot] [PATCH V3 17/32] imximage.cfg: run files through C preprocessor Troy Kisky
2012-10-07 18:19 ` Eric Nelson
2012-10-08 19:11 ` Troy Kisky
2012-10-08 13:38 ` Stefano Babic
2012-10-08 21:48 ` Troy Kisky
2012-10-10 2:03 ` Troy Kisky
2012-10-11 11:11 ` Stefano Babic
2012-10-11 20:33 ` Troy Kisky
2012-10-11 22:27 ` stefano babic
2012-10-11 23:15 ` Tom Rini
2012-10-13 10:11 ` [U-Boot] File placement in Soc / board dirs and make issues (was: [PATCH V3 17/32] imximage.cfg: run files through C preprocessor) Albert ARIBAUD
2012-10-13 15:17 ` Tom Rini
2012-10-14 8:37 ` [U-Boot] File placement in Soc / board dirs and make issues Albert ARIBAUD
2012-10-15 1:24 ` Tom Rini
2012-10-23 6:30 ` Albert ARIBAUD
2012-10-17 20:32 ` [U-Boot] [PATCH V3 17/32] imximage.cfg: run files through C preprocessor Troy Kisky
2012-10-17 21:05 ` Tom Rini
2012-10-17 21:38 ` Troy Kisky
2012-10-17 22:29 ` Tom Rini
2012-10-04 1:47 ` [U-Boot] [PATCH V3 18/32] mx6q_4x_mt41j128.cfg: use symbols instead of hardcoded constants Troy Kisky
2012-10-04 1:47 ` [U-Boot] [PATCH V3 19/32] mx6q_4x_mt41j128.cfg: add comments Troy Kisky
2012-10-04 1:47 ` [U-Boot] [PATCH V3 20/32] mx6q_4x_mt41j128.cfg: use ddr3 mode for reset Troy Kisky
2012-10-04 1:47 ` [U-Boot] [PATCH V3 21/32] mx6q_4x_mt41j128.cfg: skip initiailizing non-existent memory Troy Kisky
2012-10-07 21:01 ` Eric Nelson
2012-10-04 1:47 ` [U-Boot] [PATCH V3 22/32] mx6q_4x_mt41j128.cfg: force ZQ calibration Troy Kisky
2012-10-04 1:47 ` [U-Boot] [PATCH V3 23/32] mx6: soc: update get_cpu_rev and get_imx_type for mx6solo/sololite Troy Kisky
2012-10-04 1:47 ` [U-Boot] [PATCH V3 24/32] mx6: use CONFIG_MX6 instead of CONFIG_MX6Q Troy Kisky
2012-10-08 13:41 ` Stefano Babic
2012-10-08 21:49 ` Troy Kisky
2012-10-04 1:47 ` [U-Boot] [PATCH V3 25/32] imx-common: cpu: add imx_ddr_size Troy Kisky
2012-10-08 13:06 ` Stefano Babic
2012-10-08 21:35 ` Troy Kisky
2012-10-04 1:47 ` [U-Boot] [PATCH V3 26/32] arch-mx6: add mx6dl_pins.h Troy Kisky
2012-10-04 1:47 ` [U-Boot] [PATCH V3 27/32] mx6qsabrelite: add support for mx6 solo/duallite Troy Kisky
2012-10-04 3:23 ` Otavio Salvador
2012-10-04 23:34 ` Troy Kisky
2012-10-08 13:47 ` Stefano Babic
2012-10-04 1:47 ` [U-Boot] [PATCH V3 28/32] mx6q_4x_mt41j128.cfg: add mx6 solo/duallite support Troy Kisky
2012-10-08 18:46 ` Eric Nelson
2012-10-08 21:08 ` Troy Kisky
2012-10-04 1:47 ` [U-Boot] [PATCH V3 29/32] Add boards for sabrelite variants mx6s(solo) and mx6dl(duallite) Troy Kisky
2012-10-04 1:47 ` [U-Boot] [PATCH V3 30/32] mx6qsabrelite: change CONFIG_SYS_PROMPT Troy Kisky
2012-10-04 3:00 ` Otavio Salvador
2012-10-04 23:28 ` Troy Kisky
2012-10-08 13:54 ` Stefano Babic
2012-10-08 21:58 ` Troy Kisky
2012-10-08 22:05 ` Fabio Estevam
2012-10-08 22:18 ` stefano babic
2012-10-08 22:22 ` Eric Nelson
2012-10-08 22:21 ` Eric Nelson
2012-10-04 1:47 ` [U-Boot] [PATCH V3 31/32] parse_helper: add expression evaluation Troy Kisky
2012-10-04 1:47 ` [U-Boot] [PATCH V3 32/32] imx-mkimage.h: use base + offset syntax Troy Kisky
2012-10-04 10:18 ` [U-Boot] [PATCH V3 00/32] Add mx6solo/mx6duallite support Albert ARIBAUD
2012-10-04 14:36 ` Eric Nelson
2012-10-04 19:51 ` Albert ARIBAUD
2012-10-04 14:52 ` Eric Nelson
2012-10-08 13:15 ` Stefano Babic
2012-10-08 23:58 ` Troy Kisky
-- strict thread matches above, loose matches on Subject: below --
2019-08-29 13:40 [U-Boot] (no subject) Thomas Schaefer
2019-08-29 13:53 ` Fabio Estevam
2019-08-29 15:12 ` Thomas Schaefer
2019-08-29 15:21 ` Fabio Estevam
2019-06-30 2:06 Thomas Chou
2019-06-30 10:31 ` Bin Meng
2019-07-01 13:19 ` Tom Rini
2019-07-04 2:00 ` Thomas Chou
2019-07-04 1:58 ` Thomas Chou
2019-07-01 13:20 ` Tom Rini
2019-07-04 2:11 ` Thomas Chou
2019-04-28 21:45 Adam Ford
2019-04-10 14:35 [U-Boot] [PATCH v2] imx: Extend PCL063 support for phyCORE-i.MX6ULL SOM Parthiban Nallathambi
2019-04-26 8:02 ` Parthiban Nallathambi
2019-04-26 8:27 ` [U-Boot] (no subject) Stefano Babic
2019-01-19 9:37 Angelo Dureghello
2018-11-22 20:08 sjg at google.com
2018-09-20 21:07 Angelo Dureghello
2018-09-18 21:49 Jeremy Gebben
2017-05-15 9:49 [U-Boot] [PATCH v2 0/7] Add basic support for Rockchip RK3368 SOC Andy Yan
2017-05-15 9:53 ` [U-Boot] (no subject) Andy Yan
2017-04-21 3:01 Zhikang Zhang
2016-11-25 18:16 Rick Bronson
2016-07-13 14:11 [U-Boot] [PATCH] arm: imx: Add support for Advantech DMS-BA16 board Akshay Bhat
2016-07-20 16:25 ` [U-Boot] (no subject) Stefano Babic
2016-07-12 17:16 Joe Hershberger
2016-07-12 17:16 Joe Hershberger
2016-07-12 17:16 Joe Hershberger
2016-07-12 17:16 Joe Hershberger
2016-07-12 17:16 Joe Hershberger
2016-06-17 10:00 [U-Boot] [RFC] omap3: single binary supporting all flash types Ladislav Michl
2016-06-17 10:07 ` [U-Boot] (no subject) Ladislav Michl
2016-06-17 10:09 ` Ladislav Michl
2016-02-03 12:42 Peter Robinson
2016-01-20 12:25 Wenbin Song
2015-12-09 7:15 Peter Robinson
2015-11-17 12:16 wd at denx.de
2015-07-10 13:16 Samuel Egli
2014-09-12 14:45 Mariusz Boguszewski
2014-09-12 20:00 ` Michael Trimarchi
2014-09-15 8:08 ` Michael Trimarchi
2014-06-03 0:04 rajshekar_py at yahoo.com
2014-02-11 19:20 John de la Garza
[not found] <CAP8r_=BJdRNRisEgmFmPcGbyOtpta69DtveY6iFgOqdocDy+zg@mail.gmail.com>
[not found] ` <528D649C.1030701@boundarydevices.com>
2013-11-21 8:09 ` Bojan Buić
2013-11-21 8:34 ` Stefano Babic
2013-11-21 9:23 ` Bojan Buić
2013-11-21 14:01 ` Bojan Buić
2013-11-21 14:40 ` Stefano Babic
2013-11-21 15:08 ` Bojan Buić
2013-11-21 15:20 ` Bojan Buić
2013-11-22 7:04 ` Wolfgang Denk
[not found] <A3D1B805C7AF9343B5A0FF6EBB7E3D34915FBE@039-SN2MPN1-023.039d.mgd.msft.net>
2013-02-08 11:44 ` Marek Vasut
2012-07-19 17:38 Gigin Jose
2012-06-22 20:08 apple pie
2012-06-21 1:37 Pascal Levesque
2012-06-03 9:27 Stijn Souffriau
[not found] <http://lists.denx.de/pipermail/u-boot/2012-March/120899.html>
2012-03-25 23:00 ` Eric Nelson
2012-03-06 21:29 Wolfgang Denk
2012-03-06 22:02 ` Mike Frysinger
2012-03-07 11:25 ` Wolfgang Denk
2012-03-08 6:37 ` Simon Glass
2012-03-08 8:16 ` Wolfgang Denk
2012-03-09 13:59 ` Simon Glass
2012-03-09 3:28 ` Mike Frysinger
2012-03-09 3:29 ` Mike Frysinger
2012-02-16 2:59 [U-Boot] [PATCH 1/5] msm7x30: Add support for low speed uart on msm7x30 mohamed.haneef at lntinfotech.com
2012-04-23 9:24 ` [U-Boot] (no subject) mohamed.haneef at lntinfotech.com
2011-12-25 15:17 larrybizz at aol.com
2011-12-17 14:22 larrybizz at aol.com
2011-11-28 0:53 Sgt.Williams Moore.
2011-11-25 20:57 ALANTIC LOANS HAPPY OFFER
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2011-11-20 13:27 Mrs Veronica James
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2011-11-17 5:32 Western Union Office
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2011-11-14 9:02 Nokia XMAS Bonanza
2011-11-13 4:50 Uk Lottery
2011-11-09 7:08 FeDEX Logistics
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2011-11-04 16:07 Loan2Day
2011-11-02 18:35 jobhunts02 at aol.com
2011-10-31 21:21 Tahani Kalender
2011-10-31 14:34 vmujica at uc.edu.ve
2011-10-31 9:21 Bar Yasser
2011-10-30 11:37 Henry, Sherie
2011-10-29 5:49 MAY BANK INTERNATIONAL PLS
2011-10-23 23:12 E-Loan & Credit Home
2011-10-20 8:23 CHEVRON OIL & GAS ANNUAL EMAIL NOTIFICATIONS
2011-10-16 22:36 Tom Kaplan
2011-10-16 12:04 jobhunts02 at aol.com
2011-10-14 13:06 COCA-COLA COMPANY PROMOTION
2011-10-09 8:06 victor casunuran
2011-10-10 14:39 ` Detlev Zundel
2011-10-07 20:48 Mr. Wen Lee
2011-10-07 20:42 Mr. Wen Lee
2011-10-05 21:54 Mr.Abdulrahman Ibrahim
2011-10-05 20:49 Mr.Wen Lee
2011-10-04 22:11 jobhunts02 at aol.com
2011-09-29 1:54 Mr. Abdulrahman Ibrahim
2011-09-20 4:40 IRISH LOTTERY
2011-09-13 21:52 Mr. Song Lile Transfer Offer 2011
2011-09-12 22:45 Mr.Wen Lee
2011-09-12 2:10 Elo Petteri
2011-09-10 20:08 UK INTERNATIONAL LOTTERY
2011-09-09 22:29 Wen Lee
2011-09-08 21:48 Coca-Cola Great Britain
[not found] <[PATCH 5/5] coldfire: Remove board with major build issues>
2011-08-31 11:33 ` Stany MARCEL
[not found] <[PATCH 4/5] coldfire: Remove link files entries to prevent multiple definitions>
2011-08-31 11:32 ` Stany MARCEL
2011-08-31 11:55 ` Marek Vasut
[not found] <[PATCH 3/5] coldfire: Permit build in a different directory>
2011-08-31 11:31 ` Stany MARCEL
[not found] <[PATCH 2/5] coldfire: Add creation of include directories for _config rules>
2011-08-31 11:30 ` Stany MARCEL
[not found] <[PATCH 1/5] coldfire: Change timer_init return type from void to int>
2011-08-31 11:28 ` Stany MARCEL
2011-08-31 11:55 ` Stany MARCEL
2011-08-31 12:11 ` Wolfgang Denk
2011-08-30 12:49 [U-Boot] [PATCH V2] console: Implement pre-console buffer Graeme Russ
2011-08-31 12:35 ` [U-Boot] (no subject) Graeme Russ
2011-08-31 12:38 ` Graeme Russ
2011-08-27 16:54 Ronny D
2011-08-26 0:07 Ronny D
2011-08-21 5:05 Ronny D
2011-08-21 0:39 Exxon Promo
2011-08-14 3:02 shawn Bai
2011-08-13 14:48 favour good
2011-08-13 7:18 UK INTERNATIONAL LOTTERY PRIZE AWARD DEPT
2011-08-12 14:29 Ronny D
2011-08-06 19:33 Bar Yasser
2011-08-04 18:53 Thomas Petazzoni
2011-07-29 3:52 SEUMAS MCCOMBE
2011-07-25 17:20 Western Union®
2011-07-19 19:52 SURESH FINANCE
2011-07-07 21:17 SEUMAS MCCOMBE
2011-07-06 7:55 Art of England Magazine
2011-07-03 20:37 Mr Cohen Emerson
2011-07-01 2:36 THE COCA COLA COMPANY
2011-06-30 10:55 kifkifads at yahoo.fr
2011-06-26 4:47 Mr. Allan Davis
2011-06-21 3:47 Ronny D
2011-06-17 0:16 FROM JORDAN GLOBAL LOANCORPORATION
2011-06-16 9:13 MRS STITI MONA
2011-06-03 14:19 Microsoft Inc
2011-06-03 12:53 Mr Wen Lee
2011-06-03 12:51 Mr Wen Lee
2011-05-26 8:02 Yuping Luo
2011-05-24 22:29 Mr. Mark Seumas
2011-05-24 15:48 buffetcampinas at sercomtel.com.br
2011-05-17 3:01 jobhunts02 at aol.com
2011-05-15 23:28 jobhunts02 at aol.com
2011-04-30 1:09 Western Union
2011-04-25 6:53 E-Mail Admin
2011-04-22 8:32 manohar kallutla
2011-04-21 15:11 terri nechwa
2011-04-20 18:05 jeffhemstreet at yahoo.com
2011-04-20 15:32 Norton Financial Loan Company Inc
2011-04-19 21:56 jeffhemstreet at yahoo.com
2011-04-16 21:44 jeffhemstreet at yahoo.com
2011-04-07 15:32 MONDAY LOTTERY BOARD
2011-04-07 14:23 MONDAY LOTTERY BOARD
2011-04-01 12:25 DARY HARTSON
2011-03-31 20:43 E-Mail Admin
2011-03-25 13:03 Robert Pasquantonio
2011-03-24 8:37 Erik Hansen
2011-03-23 7:34 ystradgynlais.sports.centre at powys.gov.uk
2011-03-22 15:55 Norton Financial Loan Company Inc
2011-03-21 12:39 ystradgynlais.sports.centre at powys.gov.uk
2011-03-19 22:09 EURO MILLION 2011
2011-03-19 17:47 xzxcv6 at cox.net
2011-03-13 11:07 Luz Nury Fajardo Ortiz
2011-03-05 1:32 L'ALTRA DIMENSIONE
2011-02-15 9:34 [U-Boot] [PATCH] [RFC] SF: Add "sf erase offset +len" command handler Mike Frysinger
2011-02-16 20:27 ` [U-Boot] (no subject) Richard Retanubun
2011-02-17 5:46 ` Mike Frysinger
2011-01-18 4:45 Kumar Gala
2011-01-13 8:36 MrGates
2011-01-13 11:25 ` Albert ARIBAUD
2010-11-28 20:14 Wolfgang Denk
2010-12-01 6:38 ` Minkyu Kang
2010-11-28 19:43 Wolfgang Denk
2010-11-17 9:00 Jinson Wang
2010-11-16 9:29 Money Gram Transfer
2010-10-15 9:34 WESTERN UNION TRANSFER
2010-10-10 8:35 Wolfgang Denk
2010-10-11 7:49 ` Stefan Roese
2010-10-11 13:19 ` Stefan Roese
2010-10-11 13:26 ` Wolfgang Denk
2010-10-06 20:55 [U-Boot] [PATCH] board_init_r: Removed unused cmdtp variable Wolfgang Denk
2010-10-19 14:29 ` [U-Boot] (no subject) Richard Retanubun
2010-10-04 21:35 Mrs.Turner Clarissa Ann
2010-06-19 23:48 Wolfgang Denk
2010-06-02 22:09 [U-Boot] (No subject) Mr Michael Smith
2010-06-02 22:09 Mr Michael Smith
2010-06-02 5:24 [U-Boot] (no subject) SuperStore Armenia
2010-05-24 10:59 David
2010-05-24 10:50 David
2010-05-12 23:25 Important Notice
2010-05-03 15:45 Irish Online Claim
2010-04-23 3:56 BARCLAYS BANK UK
2010-04-03 4:36 Irish Online Promo
2010-02-23 18:08 Eloan Finance International Loans
2010-02-16 0:12 The uknl
2010-02-15 13:13 SHELL INTERNATIONAL LOTTERY
2010-02-06 13:14 Global Springer Link Finance
2010-02-06 11:47 Global Springer Link Finance
2010-01-27 11:21 Lancaster Terrace
2009-12-09 4:42 星杨
2009-11-10 5:03 Helen Mathew
2009-10-28 5:51 HeLei
2009-09-15 8:38 Konrad Mattheis
2009-08-21 8:55 HONDA AWARD 2009
2009-06-29 7:18 Krishna, Mahith
2009-06-29 7:47 ` Nishanth Menon
2009-06-04 10:27 Daniel Mack
2009-05-30 3:59 UKL-DEPT
2009-05-25 13:57 xiaojing mao
2009-05-25 18:12 ` Wolfgang Denk
2009-05-02 18:23 JMC INVESTMENT
2009-04-24 6:55 John Tobias
2009-04-03 22:37 Neeraj Tandon
2009-04-01 2:44 卫 王
2009-02-26 10:24 POLETTE Simon
2009-02-26 11:36 ` Wolfgang Denk
2009-02-19 13:30 md ks
2009-02-19 13:42 ` Nishanth Menon
2009-02-24 6:24 ` md ks
2009-02-19 13:48 ` Wolfgang Denk
2009-02-03 7:58 abby.zhang at semgfab.cn
2008-12-16 21:42 Cote, Sylvain
2008-10-03 16:34 Haiying Wang
2008-10-03 16:33 Haiying Wang
2008-10-03 16:33 Haiying Wang
2008-10-03 16:33 Haiying Wang
2008-10-03 16:32 Haiying Wang
2008-10-03 16:32 Haiying Wang
2008-10-03 23:35 ` Wolfgang Denk
2008-10-04 2:39 ` Haiying Wang
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