* [PATCH v10 01/16] target/riscv: Introduce temporary in gen_add_uw()
2021-09-04 20:34 [PATCH v10 00/16] target/riscv: Update QEmu for Zb[abcs] 1.0.0 Philipp Tomsich
@ 2021-09-04 20:35 ` Philipp Tomsich
2021-09-05 8:03 ` Richard Henderson
` (2 more replies)
2021-09-04 20:35 ` [PATCH v10 02/16] target/riscv: fix clzw implementation to operate on arg1 Philipp Tomsich
` (14 subsequent siblings)
15 siblings, 3 replies; 37+ messages in thread
From: Philipp Tomsich @ 2021-09-04 20:35 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, Kito Cheng, Alistair Francis, Philipp Tomsich
Following the recent changes in translate.c, gen_add_uw() causes
failures on CF3 and SPEC2017 due to the reuse of arg1. Fix these
regressions by introducing a temporary.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
---
Changes in v10:
- new patch
target/riscv/insn_trans/trans_rvb.c.inc | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index b72e76255c..c0a6e25826 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -624,8 +624,10 @@ GEN_TRANS_SHADD_UW(3)
static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2)
{
- tcg_gen_ext32u_tl(arg1, arg1);
- tcg_gen_add_tl(ret, arg1, arg2);
+ TCGv t = tcg_temp_new();
+ tcg_gen_ext32u_tl(t, arg1);
+ tcg_gen_add_tl(ret, t, arg2);
+ tcg_temp_free(t);
}
static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
--
2.25.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* Re: [PATCH v10 01/16] target/riscv: Introduce temporary in gen_add_uw()
2021-09-04 20:35 ` [PATCH v10 01/16] target/riscv: Introduce temporary in gen_add_uw() Philipp Tomsich
@ 2021-09-05 8:03 ` Richard Henderson
2021-09-06 5:45 ` Alistair Francis
2021-09-08 5:13 ` Bin Meng
2 siblings, 0 replies; 37+ messages in thread
From: Richard Henderson @ 2021-09-05 8:03 UTC (permalink / raw)
To: Philipp Tomsich, qemu-devel; +Cc: Kito Cheng, Alistair Francis
On 9/4/21 10:35 PM, Philipp Tomsich wrote:
> Following the recent changes in translate.c, gen_add_uw() causes
> failures on CF3 and SPEC2017 due to the reuse of arg1. Fix these
> regressions by introducing a temporary.
>
> Signed-off-by: Philipp Tomsich<philipp.tomsich@vrull.eu>
> ---
>
> Changes in v10:
> - new patch
>
> target/riscv/insn_trans/trans_rvb.c.inc | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
Fixes: 191d1dafae9c ("target/riscv: Add DisasExtend to gen_arith*")
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v10 01/16] target/riscv: Introduce temporary in gen_add_uw()
2021-09-04 20:35 ` [PATCH v10 01/16] target/riscv: Introduce temporary in gen_add_uw() Philipp Tomsich
2021-09-05 8:03 ` Richard Henderson
@ 2021-09-06 5:45 ` Alistair Francis
2021-09-08 5:13 ` Bin Meng
2 siblings, 0 replies; 37+ messages in thread
From: Alistair Francis @ 2021-09-06 5:45 UTC (permalink / raw)
To: Philipp Tomsich
Cc: Alistair Francis, Kito Cheng, Richard Henderson,
qemu-devel@nongnu.org Developers
On Sun, Sep 5, 2021 at 6:40 AM Philipp Tomsich <philipp.tomsich@vrull.eu> wrote:
>
> Following the recent changes in translate.c, gen_add_uw() causes
> failures on CF3 and SPEC2017 due to the reuse of arg1. Fix these
> regressions by introducing a temporary.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> Changes in v10:
> - new patch
>
> target/riscv/insn_trans/trans_rvb.c.inc | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
> index b72e76255c..c0a6e25826 100644
> --- a/target/riscv/insn_trans/trans_rvb.c.inc
> +++ b/target/riscv/insn_trans/trans_rvb.c.inc
> @@ -624,8 +624,10 @@ GEN_TRANS_SHADD_UW(3)
>
> static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2)
> {
> - tcg_gen_ext32u_tl(arg1, arg1);
> - tcg_gen_add_tl(ret, arg1, arg2);
> + TCGv t = tcg_temp_new();
> + tcg_gen_ext32u_tl(t, arg1);
> + tcg_gen_add_tl(ret, t, arg2);
> + tcg_temp_free(t);
> }
>
> static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v10 01/16] target/riscv: Introduce temporary in gen_add_uw()
2021-09-04 20:35 ` [PATCH v10 01/16] target/riscv: Introduce temporary in gen_add_uw() Philipp Tomsich
2021-09-05 8:03 ` Richard Henderson
2021-09-06 5:45 ` Alistair Francis
@ 2021-09-08 5:13 ` Bin Meng
2 siblings, 0 replies; 37+ messages in thread
From: Bin Meng @ 2021-09-08 5:13 UTC (permalink / raw)
To: Philipp Tomsich
Cc: Alistair Francis, Kito Cheng, Richard Henderson,
qemu-devel@nongnu.org Developers
On Sun, Sep 5, 2021 at 4:40 AM Philipp Tomsich <philipp.tomsich@vrull.eu> wrote:
>
> Following the recent changes in translate.c, gen_add_uw() causes
> failures on CF3 and SPEC2017 due to the reuse of arg1. Fix these
> regressions by introducing a temporary.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
> ---
>
> Changes in v10:
> - new patch
>
> target/riscv/insn_trans/trans_rvb.c.inc | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v10 02/16] target/riscv: fix clzw implementation to operate on arg1
2021-09-04 20:34 [PATCH v10 00/16] target/riscv: Update QEmu for Zb[abcs] 1.0.0 Philipp Tomsich
2021-09-04 20:35 ` [PATCH v10 01/16] target/riscv: Introduce temporary in gen_add_uw() Philipp Tomsich
@ 2021-09-04 20:35 ` Philipp Tomsich
2021-09-05 8:06 ` Richard Henderson
` (2 more replies)
2021-09-04 20:35 ` [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic) Philipp Tomsich
` (13 subsequent siblings)
15 siblings, 3 replies; 37+ messages in thread
From: Philipp Tomsich @ 2021-09-04 20:35 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, Kito Cheng, Alistair Francis, Philipp Tomsich
The refactored gen_clzw() uses ret as its argument, instead of arg1.
Fix it.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
---
Changes in v10:
- New patch, fixing regressions discovered with x264_r.
target/riscv/insn_trans/trans_rvb.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index c0a6e25826..6c85c89f6d 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -349,7 +349,7 @@ GEN_TRANS_SHADD(3)
static void gen_clzw(TCGv ret, TCGv arg1)
{
- tcg_gen_clzi_tl(ret, ret, 64);
+ tcg_gen_clzi_tl(ret, arg1, 64);
tcg_gen_subi_tl(ret, ret, 32);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* Re: [PATCH v10 02/16] target/riscv: fix clzw implementation to operate on arg1
2021-09-04 20:35 ` [PATCH v10 02/16] target/riscv: fix clzw implementation to operate on arg1 Philipp Tomsich
@ 2021-09-05 8:06 ` Richard Henderson
2021-09-06 5:45 ` Alistair Francis
2021-09-08 5:14 ` Bin Meng
2 siblings, 0 replies; 37+ messages in thread
From: Richard Henderson @ 2021-09-05 8:06 UTC (permalink / raw)
To: Philipp Tomsich, qemu-devel; +Cc: Kito Cheng, Alistair Francis
On 9/4/21 10:35 PM, Philipp Tomsich wrote:
> The refactored gen_clzw() uses ret as its argument, instead of arg1.
> Fix it.
>
> Signed-off-by: Philipp Tomsich<philipp.tomsich@vrull.eu>
> ---
>
> Changes in v10:
> - New patch, fixing regressions discovered with x264_r.
Fixes: 60903915050 ("target/riscv: Add DisasExtend to gen_unary")
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v10 02/16] target/riscv: fix clzw implementation to operate on arg1
2021-09-04 20:35 ` [PATCH v10 02/16] target/riscv: fix clzw implementation to operate on arg1 Philipp Tomsich
2021-09-05 8:06 ` Richard Henderson
@ 2021-09-06 5:45 ` Alistair Francis
2021-09-08 5:14 ` Bin Meng
2 siblings, 0 replies; 37+ messages in thread
From: Alistair Francis @ 2021-09-06 5:45 UTC (permalink / raw)
To: Philipp Tomsich
Cc: Alistair Francis, Kito Cheng, Richard Henderson,
qemu-devel@nongnu.org Developers
On Sun, Sep 5, 2021 at 6:36 AM Philipp Tomsich <philipp.tomsich@vrull.eu> wrote:
>
> The refactored gen_clzw() uses ret as its argument, instead of arg1.
> Fix it.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> Changes in v10:
> - New patch, fixing regressions discovered with x264_r.
>
> target/riscv/insn_trans/trans_rvb.c.inc | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
> index c0a6e25826..6c85c89f6d 100644
> --- a/target/riscv/insn_trans/trans_rvb.c.inc
> +++ b/target/riscv/insn_trans/trans_rvb.c.inc
> @@ -349,7 +349,7 @@ GEN_TRANS_SHADD(3)
>
> static void gen_clzw(TCGv ret, TCGv arg1)
> {
> - tcg_gen_clzi_tl(ret, ret, 64);
> + tcg_gen_clzi_tl(ret, arg1, 64);
> tcg_gen_subi_tl(ret, ret, 32);
> }
>
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v10 02/16] target/riscv: fix clzw implementation to operate on arg1
2021-09-04 20:35 ` [PATCH v10 02/16] target/riscv: fix clzw implementation to operate on arg1 Philipp Tomsich
2021-09-05 8:06 ` Richard Henderson
2021-09-06 5:45 ` Alistair Francis
@ 2021-09-08 5:14 ` Bin Meng
2 siblings, 0 replies; 37+ messages in thread
From: Bin Meng @ 2021-09-08 5:14 UTC (permalink / raw)
To: Philipp Tomsich
Cc: Alistair Francis, Kito Cheng, Richard Henderson,
qemu-devel@nongnu.org Developers
On Sun, Sep 5, 2021 at 4:35 AM Philipp Tomsich <philipp.tomsich@vrull.eu> wrote:
>
> The refactored gen_clzw() uses ret as its argument, instead of arg1.
> Fix it.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
> ---
>
> Changes in v10:
> - New patch, fixing regressions discovered with x264_r.
>
> target/riscv/insn_trans/trans_rvb.c.inc | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic)
2021-09-04 20:34 [PATCH v10 00/16] target/riscv: Update QEmu for Zb[abcs] 1.0.0 Philipp Tomsich
2021-09-04 20:35 ` [PATCH v10 01/16] target/riscv: Introduce temporary in gen_add_uw() Philipp Tomsich
2021-09-04 20:35 ` [PATCH v10 02/16] target/riscv: fix clzw implementation to operate on arg1 Philipp Tomsich
@ 2021-09-04 20:35 ` Philipp Tomsich
2021-09-05 8:11 ` Richard Henderson
2021-09-04 20:35 ` [PATCH v10 04/16] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties Philipp Tomsich
` (12 subsequent siblings)
15 siblings, 1 reply; 37+ messages in thread
From: Philipp Tomsich @ 2021-09-04 20:35 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, Kito Cheng, Alistair Francis, Philipp Tomsich
Assume clzw being executed on a register that is not sign-extended, such
as for the following sequence that uses (1ULL << 63) | 392 as the operand
to clzw:
bseti a2, zero, 63
addi a2, a2, 392
clzw a3, a2
The correct result of clzw would be 23, but the current implementation
returns -32 (as it performs a 64bit clz, which results in 0 leading zero
bits, and then subtracts 32).
Fix this by changing the implementation to:
1. shift the original register up by 32
2. performs a target-length (64bit) clz
3. return 32 if no bits are set
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
---
Changes in v10:
- New patch, fixing correctnes for clzw called on a register with undefined
(as in: not properly sign-extended) upper bits.
target/riscv/insn_trans/trans_rvb.c.inc | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 6c85c89f6d..8d29cadd20 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -349,8 +349,10 @@ GEN_TRANS_SHADD(3)
static void gen_clzw(TCGv ret, TCGv arg1)
{
- tcg_gen_clzi_tl(ret, arg1, 64);
- tcg_gen_subi_tl(ret, ret, 32);
+ TCGv t = tcg_temp_new();
+ tcg_gen_shli_tl(t, arg1, 32);
+ tcg_gen_clzi_tl(ret, t, 32);
+ tcg_temp_free(t);
}
static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
--
2.25.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* Re: [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic)
2021-09-04 20:35 ` [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic) Philipp Tomsich
@ 2021-09-05 8:11 ` Richard Henderson
2021-09-05 9:01 ` Philipp Tomsich
0 siblings, 1 reply; 37+ messages in thread
From: Richard Henderson @ 2021-09-05 8:11 UTC (permalink / raw)
To: Philipp Tomsich, qemu-devel; +Cc: Kito Cheng, Alistair Francis
On 9/4/21 10:35 PM, Philipp Tomsich wrote:
> Assume clzw being executed on a register that is not sign-extended, such
> as for the following sequence that uses (1ULL << 63) | 392 as the operand
> to clzw:
> bseti a2, zero, 63
> addi a2, a2, 392
> clzw a3, a2
> The correct result of clzw would be 23, but the current implementation
> returns -32 (as it performs a 64bit clz, which results in 0 leading zero
> bits, and then subtracts 32).
>
> Fix this by changing the implementation to:
> 1. shift the original register up by 32
> 2. performs a target-length (64bit) clz
> 3. return 32 if no bits are set
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
> ---
>
> Changes in v10:
> - New patch, fixing correctnes for clzw called on a register with undefined
> (as in: not properly sign-extended) upper bits.
But we have
return gen_unary(ctx, a, EXT_ZERO, gen_clzw);
should *not* be undefined. Ah, what's missing is
ctx->w = true;
within trans_clzw to cause the extend to take effect.
There are a few other "w" functions that are missing that set, though they use EXT_NONE so
there is no visible bug, it would probably be best to set w anyway.
r~
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic)
2021-09-05 8:11 ` Richard Henderson
@ 2021-09-05 9:01 ` Philipp Tomsich
2021-09-10 13:36 ` Philipp Tomsich
0 siblings, 1 reply; 37+ messages in thread
From: Philipp Tomsich @ 2021-09-05 9:01 UTC (permalink / raw)
To: Richard Henderson; +Cc: Kito Cheng, Alistair Francis, qemu-devel
On Sun 5. Sep 2021 at 11:11, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 9/4/21 10:35 PM, Philipp Tomsich wrote:
> > Assume clzw being executed on a register that is not sign-extended, such
> > as for the following sequence that uses (1ULL << 63) | 392 as the operand
> > to clzw:
> > bseti a2, zero, 63
> > addi a2, a2, 392
> > clzw a3, a2
> > The correct result of clzw would be 23, but the current implementation
> > returns -32 (as it performs a 64bit clz, which results in 0 leading zero
> > bits, and then subtracts 32).
> >
> > Fix this by changing the implementation to:
> > 1. shift the original register up by 32
> > 2. performs a target-length (64bit) clz
> > 3. return 32 if no bits are set
> >
> > Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
> > ---
> >
> > Changes in v10:
> > - New patch, fixing correctnes for clzw called on a register with undefined
> > (as in: not properly sign-extended) upper bits.
>
> But we have
>
> return gen_unary(ctx, a, EXT_ZERO, gen_clzw);
>
> should *not* be undefined. Ah, what's missing is
>
> ctx->w = true;
>
> within trans_clzw to cause the extend to take effect.
>
> There are a few other "w" functions that are missing that set, though they use EXT_NONE so
> there is no visible bug, it would probably be best to set w anyway.
I had originally considered that (it would have to be ctx->w = true;
and EXT_SIGN),
but that has the side-effect of performing an extension on the result
of the clzw as
well (i.e. bot get_gpr and set_gpr are extended).
However, this is not what clzw does: it only ignores the upper bits
and then produces
a result in the value-range [0..32]. An extension on the result of
either a clz or clzw
is never needed (we have been fighting that problem in GCC and had to
use patterns
for the combiner), so I don't want to introduce this inefficiency in qemu.
If you have EXT_SIGN (or _ZERO), we will end up with 2 additional
extensions (one
on the argument, one on the result) in addition to the 2 other tcg
operations that we
need (i.e. clzi/subi for the extending case, shli/clzi for the proposed fix).
So I believe that this commit is the best fix:
1. It doesn't mark this as a w-form (i.e. ignores the high-bits on the
input _and_
extends the output), as it only treats the input as 32bit, but the
output is xlen.
2. It doesn't introduce any unnecessary extensions, but handles the
case in-place.
Philipp.
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic)
2021-09-05 9:01 ` Philipp Tomsich
@ 2021-09-10 13:36 ` Philipp Tomsich
2021-09-10 13:40 ` Richard Henderson
0 siblings, 1 reply; 37+ messages in thread
From: Philipp Tomsich @ 2021-09-10 13:36 UTC (permalink / raw)
To: Richard Henderson; +Cc: Kito Cheng, Alistair Francis, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 3135 bytes --]
Richard,
Did you have a chance to consider what to do with clzw?
I would prefer to avoid the extra extension instructions and change the
implementation (and would update the commit message to provide more
context), but if you insist on setting 'ctx->w' I'll just have the extra
extensions emitted than delay this series further…
Thanks,
Philipp.
On Sun, 5 Sept 2021 at 12:01, Philipp Tomsich <philipp.tomsich@vrull.eu>
wrote:
> On Sun 5. Sep 2021 at 11:11, Richard Henderson
> <richard.henderson@linaro.org> wrote:
> >
> > On 9/4/21 10:35 PM, Philipp Tomsich wrote:
> > > Assume clzw being executed on a register that is not sign-extended,
> such
> > > as for the following sequence that uses (1ULL << 63) | 392 as the
> operand
> > > to clzw:
> > > bseti a2, zero, 63
> > > addi a2, a2, 392
> > > clzw a3, a2
> > > The correct result of clzw would be 23, but the current implementation
> > > returns -32 (as it performs a 64bit clz, which results in 0 leading
> zero
> > > bits, and then subtracts 32).
> > >
> > > Fix this by changing the implementation to:
> > > 1. shift the original register up by 32
> > > 2. performs a target-length (64bit) clz
> > > 3. return 32 if no bits are set
> > >
> > > Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
> > > ---
> > >
> > > Changes in v10:
> > > - New patch, fixing correctnes for clzw called on a register with
> undefined
> > > (as in: not properly sign-extended) upper bits.
> >
> > But we have
> >
> > return gen_unary(ctx, a, EXT_ZERO, gen_clzw);
> >
> > should *not* be undefined. Ah, what's missing is
> >
> > ctx->w = true;
> >
> > within trans_clzw to cause the extend to take effect.
> >
> > There are a few other "w" functions that are missing that set, though
> they use EXT_NONE so
> > there is no visible bug, it would probably be best to set w anyway.
>
>
> I had originally considered that (it would have to be ctx->w = true;
> and EXT_SIGN),
> but that has the side-effect of performing an extension on the result
> of the clzw as
> well (i.e. bot get_gpr and set_gpr are extended).
>
> However, this is not what clzw does: it only ignores the upper bits
> and then produces
> a result in the value-range [0..32]. An extension on the result of
> either a clz or clzw
> is never needed (we have been fighting that problem in GCC and had to
> use patterns
> for the combiner), so I don't want to introduce this inefficiency in qemu.
>
> If you have EXT_SIGN (or _ZERO), we will end up with 2 additional
> extensions (one
> on the argument, one on the result) in addition to the 2 other tcg
> operations that we
> need (i.e. clzi/subi for the extending case, shli/clzi for the proposed
> fix).
>
> So I believe that this commit is the best fix:
> 1. It doesn't mark this as a w-form (i.e. ignores the high-bits on the
> input _and_
> extends the output), as it only treats the input as 32bit, but the
> output is xlen.
> 2. It doesn't introduce any unnecessary extensions, but handles the
> case in-place.
>
> Philipp.
>
[-- Attachment #2: Type: text/html, Size: 4011 bytes --]
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic)
2021-09-10 13:36 ` Philipp Tomsich
@ 2021-09-10 13:40 ` Richard Henderson
2021-09-10 13:47 ` Philipp Tomsich
0 siblings, 1 reply; 37+ messages in thread
From: Richard Henderson @ 2021-09-10 13:40 UTC (permalink / raw)
To: Philipp Tomsich; +Cc: Kito Cheng, Alistair Francis, qemu-devel
On 9/10/21 3:36 PM, Philipp Tomsich wrote:
> Richard,
>
> Did you have a chance to consider what to do with clzw?
> I would prefer to avoid the extra extension instructions and change the implementation
> (and would update the commit message to provide more context), but if you insist on
> setting 'ctx->w' I'll just have the extra extensions emitted than delay this series further…
I don't mind not setting ctx->w, but bear in mind that UXL is going to automatically set
this flag when executing RV32 on RV64. That's why I have written a tcg patch set to
eliminate unnecessary sign-extensions.
Do swap out EXT_ZERO for EXT_NONE in the gen_unary call if you're not going to make use of
any kind of source extension.
r~
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic)
2021-09-10 13:40 ` Richard Henderson
@ 2021-09-10 13:47 ` Philipp Tomsich
2021-09-10 13:57 ` Richard Henderson
0 siblings, 1 reply; 37+ messages in thread
From: Philipp Tomsich @ 2021-09-10 13:47 UTC (permalink / raw)
To: Richard Henderson; +Cc: Kito Cheng, Alistair Francis, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 1215 bytes --]
On Fri, 10 Sept 2021 at 16:40, Richard Henderson <
richard.henderson@linaro.org> wrote:
> On 9/10/21 3:36 PM, Philipp Tomsich wrote:
> > Richard,
> >
> > Did you have a chance to consider what to do with clzw?
> > I would prefer to avoid the extra extension instructions and change the
> implementation
> > (and would update the commit message to provide more context), but if
> you insist on
> > setting 'ctx->w' I'll just have the extra extensions emitted than delay
> this series further…
>
> I don't mind not setting ctx->w, but bear in mind that UXL is going to
> automatically set
> this flag when executing RV32 on RV64. That's why I have written a tcg
> patch set to
> eliminate unnecessary sign-extensions.
>
Ok, thanks! Updated patches follow, once all test workloads have run…
Just wondering regarding the UXL-comment: the clzw instruction will be an
illegal encoding for RV32 (the w-form instructions are present on RV64
only), so it should never be encountered in a RV32 instruction stream. Did
you mean that clz (the instruction operating on xlen-registers) would have
ctx->w set for RV32 executing on RV64 ... or am I missing something
fundamental?
Philipp.
[-- Attachment #2: Type: text/html, Size: 1757 bytes --]
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic)
2021-09-10 13:47 ` Philipp Tomsich
@ 2021-09-10 13:57 ` Richard Henderson
0 siblings, 0 replies; 37+ messages in thread
From: Richard Henderson @ 2021-09-10 13:57 UTC (permalink / raw)
To: Philipp Tomsich; +Cc: Kito Cheng, Alistair Francis, qemu-devel
On 9/10/21 3:47 PM, Philipp Tomsich wrote:
> Just wondering regarding the UXL-comment: the clzw instruction will be an illegal encoding
> for RV32 (the w-form instructions are present on RV64 only), so it should never be
> encountered in a RV32 instruction stream.
Correct.
> Did you mean that clz (the instruction operating on xlen-registers) would have ctx->w
> set for RV32 executing on RV64 ... or am I missing something fundamental?
Yes.
Or, as some test patches I was planning to post this weekend, replacing "w" as boolean
with an "operation length" (ol) as an enum of MXL_RV*, so that we can represent "d"
operations on RV128 with the same mechanism.
r~
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v10 04/16] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties
2021-09-04 20:34 [PATCH v10 00/16] target/riscv: Update QEmu for Zb[abcs] 1.0.0 Philipp Tomsich
` (2 preceding siblings ...)
2021-09-04 20:35 ` [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic) Philipp Tomsich
@ 2021-09-04 20:35 ` Philipp Tomsich
2021-09-08 5:16 ` Bin Meng
2021-09-04 20:35 ` [PATCH v10 05/16] target/riscv: Reassign instructions to the Zba-extension Philipp Tomsich
` (11 subsequent siblings)
15 siblings, 1 reply; 37+ messages in thread
From: Philipp Tomsich @ 2021-09-04 20:35 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, Kito Cheng, Alistair Francis, Philipp Tomsich
The bitmanipulation ISA extensions will be ratified as individual
small extension packages instead of a large B-extension. The first
new instructions through the door (these have completed public review)
are Zb[abcs].
This adds new 'x-zba', 'x-zbb', 'x-zbc' and 'x-zbs' properties for
these in target/riscv/cpu.[ch].
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
(no changes since v3)
Changes in v3:
- Split off removal of 'x-b' property and 'ext_b' field into a separate
patch to ensure bisectability.
target/riscv/cpu.c | 4 ++++
target/riscv/cpu.h | 4 ++++
2 files changed, 8 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1a2b03d579..ceb7e01810 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -587,6 +587,10 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
/* This is experimental so mark with 'x-' */
DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, false),
+ DEFINE_PROP_BOOL("x-zba", RISCVCPU, cfg.ext_zba, false),
+ DEFINE_PROP_BOOL("x-zbb", RISCVCPU, cfg.ext_zbb, false),
+ DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false),
+ DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false),
DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index bf1c899c00..7c4cd8ea89 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -293,6 +293,10 @@ struct RISCVCPU {
bool ext_u;
bool ext_h;
bool ext_v;
+ bool ext_zba;
+ bool ext_zbb;
+ bool ext_zbc;
+ bool ext_zbs;
bool ext_counters;
bool ext_ifencei;
bool ext_icsr;
--
2.25.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* Re: [PATCH v10 04/16] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties
2021-09-04 20:35 ` [PATCH v10 04/16] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties Philipp Tomsich
@ 2021-09-08 5:16 ` Bin Meng
0 siblings, 0 replies; 37+ messages in thread
From: Bin Meng @ 2021-09-08 5:16 UTC (permalink / raw)
To: Philipp Tomsich
Cc: Alistair Francis, Kito Cheng, Richard Henderson,
qemu-devel@nongnu.org Developers
On Sun, Sep 5, 2021 at 4:35 AM Philipp Tomsich <philipp.tomsich@vrull.eu> wrote:
>
> The bitmanipulation ISA extensions will be ratified as individual
> small extension packages instead of a large B-extension. The first
> new instructions through the door (these have completed public review)
> are Zb[abcs].
>
> This adds new 'x-zba', 'x-zbb', 'x-zbc' and 'x-zbs' properties for
> these in target/riscv/cpu.[ch].
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>
> (no changes since v3)
>
> Changes in v3:
> - Split off removal of 'x-b' property and 'ext_b' field into a separate
> patch to ensure bisectability.
>
> target/riscv/cpu.c | 4 ++++
> target/riscv/cpu.h | 4 ++++
> 2 files changed, 8 insertions(+)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v10 05/16] target/riscv: Reassign instructions to the Zba-extension
2021-09-04 20:34 [PATCH v10 00/16] target/riscv: Update QEmu for Zb[abcs] 1.0.0 Philipp Tomsich
` (3 preceding siblings ...)
2021-09-04 20:35 ` [PATCH v10 04/16] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties Philipp Tomsich
@ 2021-09-04 20:35 ` Philipp Tomsich
2021-09-08 5:22 ` Bin Meng
2021-09-04 20:35 ` [PATCH v10 06/16] target/riscv: Remove the W-form instructions from Zbs Philipp Tomsich
` (10 subsequent siblings)
15 siblings, 1 reply; 37+ messages in thread
From: Philipp Tomsich @ 2021-09-04 20:35 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, Kito Cheng, Alistair Francis, Philipp Tomsich
The following instructions are part of Zba:
- add.uw (RV64 only)
- sh[123]add (RV32 and RV64)
- sh[123]add.uw (RV64-only)
- slli.uw (RV64-only)
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
Changes in v10:
- Split off gen_add_uw() fix into a separate patch, as requested.
Changes in v9:
- Rebased to 8880cc4362.
- Update gen_add_uw() to use a temporary instead of messing with
arg1 (fixes a regression after rebase on CF3 and SPEC2017).
Changes in v3:
- The changes to the Zba instructions (i.e. the REQUIRE_ZBA macro
and its use for qualifying the Zba instructions) are moved into
a separate commit.
target/riscv/insn32.decode | 20 ++++++++++++--------
target/riscv/insn_trans/trans_rvb.c.inc | 16 +++++++++++-----
2 files changed, 23 insertions(+), 13 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 2cd921d51c..86f1166dab 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -660,6 +660,18 @@ vamomaxd_v 10100 . . ..... ..... 111 ..... 0101111 @r_wdvm
vamominud_v 11000 . . ..... ..... 111 ..... 0101111 @r_wdvm
vamomaxud_v 11100 . . ..... ..... 111 ..... 0101111 @r_wdvm
+# *** RV32 Zba Standard Extension ***
+sh1add 0010000 .......... 010 ..... 0110011 @r
+sh2add 0010000 .......... 100 ..... 0110011 @r
+sh3add 0010000 .......... 110 ..... 0110011 @r
+
+# *** RV64 Zba Standard Extension (in addition to RV32 Zba) ***
+add_uw 0000100 .......... 000 ..... 0111011 @r
+sh1add_uw 0010000 .......... 010 ..... 0111011 @r
+sh2add_uw 0010000 .......... 100 ..... 0111011 @r
+sh3add_uw 0010000 .......... 110 ..... 0111011 @r
+slli_uw 00001 ............ 001 ..... 0011011 @sh
+
# *** RV32B Standard Extension ***
clz 011000 000000 ..... 001 ..... 0010011 @r2
ctz 011000 000001 ..... 001 ..... 0010011 @r2
@@ -687,9 +699,6 @@ ror 0110000 .......... 101 ..... 0110011 @r
rol 0110000 .......... 001 ..... 0110011 @r
grev 0110100 .......... 101 ..... 0110011 @r
gorc 0010100 .......... 101 ..... 0110011 @r
-sh1add 0010000 .......... 010 ..... 0110011 @r
-sh2add 0010000 .......... 100 ..... 0110011 @r
-sh3add 0010000 .......... 110 ..... 0110011 @r
bseti 00101. ........... 001 ..... 0010011 @sh
bclri 01001. ........... 001 ..... 0010011 @sh
@@ -718,10 +727,6 @@ rorw 0110000 .......... 101 ..... 0111011 @r
rolw 0110000 .......... 001 ..... 0111011 @r
grevw 0110100 .......... 101 ..... 0111011 @r
gorcw 0010100 .......... 101 ..... 0111011 @r
-sh1add_uw 0010000 .......... 010 ..... 0111011 @r
-sh2add_uw 0010000 .......... 100 ..... 0111011 @r
-sh3add_uw 0010000 .......... 110 ..... 0111011 @r
-add_uw 0000100 .......... 000 ..... 0111011 @r
bsetiw 0010100 .......... 001 ..... 0011011 @sh5
bclriw 0100100 .......... 001 ..... 0011011 @sh5
@@ -732,4 +737,3 @@ roriw 0110000 .......... 101 ..... 0011011 @sh5
greviw 0110100 .......... 101 ..... 0011011 @sh5
gorciw 0010100 .......... 101 ..... 0011011 @sh5
-slli_uw 00001. ........... 001 ..... 0011011 @sh
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 8d29cadd20..7f6d5aa258 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -1,8 +1,9 @@
/*
- * RISC-V translation routines for the RVB Standard Extension.
+ * RISC-V translation routines for the RVB draft and Zba Standard Extension.
*
* Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
* Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
+ * Copyright (c) 2021 Philipp Tomsich, philipp.tomsich@vrull.eu
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -17,6 +18,11 @@
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
+#define REQUIRE_ZBA(ctx) do { \
+ if (!RISCV_CPU(ctx->cs)->cfg.ext_zba) { \
+ return false; \
+ } \
+} while (0)
static void gen_clz(TCGv ret, TCGv arg1)
{
@@ -339,7 +345,7 @@ GEN_SHADD(3)
#define GEN_TRANS_SHADD(SHAMT) \
static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \
{ \
- REQUIRE_EXT(ctx, RVB); \
+ REQUIRE_ZBA(ctx); \
return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add); \
}
@@ -616,7 +622,7 @@ static bool trans_sh##SHAMT##add_uw(DisasContext *ctx, \
arg_sh##SHAMT##add_uw *a) \
{ \
REQUIRE_64BIT(ctx); \
- REQUIRE_EXT(ctx, RVB); \
+ REQUIRE_ZBA(ctx); \
return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add_uw); \
}
@@ -635,7 +641,7 @@ static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2)
static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
{
REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBA(ctx);
return gen_arith(ctx, a, EXT_NONE, gen_add_uw);
}
@@ -647,6 +653,6 @@ static void gen_slli_uw(TCGv dest, TCGv src, target_long shamt)
static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
{
REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBA(ctx);
return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_slli_uw);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* Re: [PATCH v10 05/16] target/riscv: Reassign instructions to the Zba-extension
2021-09-04 20:35 ` [PATCH v10 05/16] target/riscv: Reassign instructions to the Zba-extension Philipp Tomsich
@ 2021-09-08 5:22 ` Bin Meng
0 siblings, 0 replies; 37+ messages in thread
From: Bin Meng @ 2021-09-08 5:22 UTC (permalink / raw)
To: Philipp Tomsich
Cc: Alistair Francis, Kito Cheng, Richard Henderson,
qemu-devel@nongnu.org Developers
On Sun, Sep 5, 2021 at 4:38 AM Philipp Tomsich <philipp.tomsich@vrull.eu> wrote:
>
> The following instructions are part of Zba:
> - add.uw (RV64 only)
> - sh[123]add (RV32 and RV64)
> - sh[123]add.uw (RV64-only)
> - slli.uw (RV64-only)
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>
> Changes in v10:
> - Split off gen_add_uw() fix into a separate patch, as requested.
>
> Changes in v9:
> - Rebased to 8880cc4362.
> - Update gen_add_uw() to use a temporary instead of messing with
> arg1 (fixes a regression after rebase on CF3 and SPEC2017).
>
> Changes in v3:
> - The changes to the Zba instructions (i.e. the REQUIRE_ZBA macro
> and its use for qualifying the Zba instructions) are moved into
> a separate commit.
>
> target/riscv/insn32.decode | 20 ++++++++++++--------
> target/riscv/insn_trans/trans_rvb.c.inc | 16 +++++++++++-----
> 2 files changed, 23 insertions(+), 13 deletions(-)
>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v10 06/16] target/riscv: Remove the W-form instructions from Zbs
2021-09-04 20:34 [PATCH v10 00/16] target/riscv: Update QEmu for Zb[abcs] 1.0.0 Philipp Tomsich
` (4 preceding siblings ...)
2021-09-04 20:35 ` [PATCH v10 05/16] target/riscv: Reassign instructions to the Zba-extension Philipp Tomsich
@ 2021-09-04 20:35 ` Philipp Tomsich
2021-09-08 5:19 ` Bin Meng
2021-09-04 20:35 ` [PATCH v10 07/16] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B) Philipp Tomsich
` (9 subsequent siblings)
15 siblings, 1 reply; 37+ messages in thread
From: Philipp Tomsich @ 2021-09-04 20:35 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, Kito Cheng, Alistair Francis, Philipp Tomsich
Zbs 1.0.0 (just as the 0.93 draft-B before) does no provide for W-form
instructions for Zbs (single-bit instructions). Remove them.
Note that these instructions had already been removed for the 0.93
version of the draft-B extenstion and have not been present in the
binutils patches circulating in January 2021.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
(no changes since v3)
Changes in v3:
- Remove the W-form instructions from Zbs in a separate commit.
target/riscv/insn32.decode | 7 ----
target/riscv/insn_trans/trans_rvb.c.inc | 56 -------------------------
2 files changed, 63 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 86f1166dab..b499691a9e 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -717,10 +717,6 @@ cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
packw 0000100 .......... 100 ..... 0111011 @r
packuw 0100100 .......... 100 ..... 0111011 @r
-bsetw 0010100 .......... 001 ..... 0111011 @r
-bclrw 0100100 .......... 001 ..... 0111011 @r
-binvw 0110100 .......... 001 ..... 0111011 @r
-bextw 0100100 .......... 101 ..... 0111011 @r
slow 0010000 .......... 001 ..... 0111011 @r
srow 0010000 .......... 101 ..... 0111011 @r
rorw 0110000 .......... 101 ..... 0111011 @r
@@ -728,9 +724,6 @@ rolw 0110000 .......... 001 ..... 0111011 @r
grevw 0110100 .......... 101 ..... 0111011 @r
gorcw 0010100 .......... 101 ..... 0111011 @r
-bsetiw 0010100 .......... 001 ..... 0011011 @sh5
-bclriw 0100100 .......... 001 ..... 0011011 @sh5
-binviw 0110100 .......... 001 ..... 0011011 @sh5
sloiw 0010000 .......... 001 ..... 0011011 @sh5
sroiw 0010000 .......... 101 ..... 0011011 @sh5
roriw 0110000 .......... 101 ..... 0011011 @sh5
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 7f6d5aa258..ca92920efd 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -420,62 +420,6 @@ static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
return gen_arith(ctx, a, EXT_NONE, gen_packuw);
}
-static bool trans_bsetw(DisasContext *ctx, arg_bsetw *a)
-{
- REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
- ctx->w = true;
- return gen_shift(ctx, a, EXT_NONE, gen_bset);
-}
-
-static bool trans_bsetiw(DisasContext *ctx, arg_bsetiw *a)
-{
- REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
- ctx->w = true;
- return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bset);
-}
-
-static bool trans_bclrw(DisasContext *ctx, arg_bclrw *a)
-{
- REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
- ctx->w = true;
- return gen_shift(ctx, a, EXT_NONE, gen_bclr);
-}
-
-static bool trans_bclriw(DisasContext *ctx, arg_bclriw *a)
-{
- REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
- ctx->w = true;
- return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bclr);
-}
-
-static bool trans_binvw(DisasContext *ctx, arg_binvw *a)
-{
- REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
- ctx->w = true;
- return gen_shift(ctx, a, EXT_NONE, gen_binv);
-}
-
-static bool trans_binviw(DisasContext *ctx, arg_binviw *a)
-{
- REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
- ctx->w = true;
- return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_binv);
-}
-
-static bool trans_bextw(DisasContext *ctx, arg_bextw *a)
-{
- REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
- ctx->w = true;
- return gen_shift(ctx, a, EXT_NONE, gen_bext);
-}
-
static bool trans_slow(DisasContext *ctx, arg_slow *a)
{
REQUIRE_64BIT(ctx);
--
2.25.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* Re: [PATCH v10 06/16] target/riscv: Remove the W-form instructions from Zbs
2021-09-04 20:35 ` [PATCH v10 06/16] target/riscv: Remove the W-form instructions from Zbs Philipp Tomsich
@ 2021-09-08 5:19 ` Bin Meng
0 siblings, 0 replies; 37+ messages in thread
From: Bin Meng @ 2021-09-08 5:19 UTC (permalink / raw)
To: Philipp Tomsich
Cc: Alistair Francis, Kito Cheng, Richard Henderson,
qemu-devel@nongnu.org Developers
On Sun, Sep 5, 2021 at 4:49 AM Philipp Tomsich <philipp.tomsich@vrull.eu> wrote:
>
> Zbs 1.0.0 (just as the 0.93 draft-B before) does no provide for W-form
does not
> instructions for Zbs (single-bit instructions). Remove them.
>
> Note that these instructions had already been removed for the 0.93
> version of the draft-B extenstion and have not been present in the
extension
> binutils patches circulating in January 2021.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>
> (no changes since v3)
>
> Changes in v3:
> - Remove the W-form instructions from Zbs in a separate commit.
>
> target/riscv/insn32.decode | 7 ----
> target/riscv/insn_trans/trans_rvb.c.inc | 56 -------------------------
> 2 files changed, 63 deletions(-)
>
Otherwise,
Acked-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v10 07/16] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B)
2021-09-04 20:34 [PATCH v10 00/16] target/riscv: Update QEmu for Zb[abcs] 1.0.0 Philipp Tomsich
` (5 preceding siblings ...)
2021-09-04 20:35 ` [PATCH v10 06/16] target/riscv: Remove the W-form instructions from Zbs Philipp Tomsich
@ 2021-09-04 20:35 ` Philipp Tomsich
2021-09-08 5:21 ` Bin Meng
2021-09-04 20:35 ` [PATCH v10 08/16] target/riscv: Reassign instructions to the Zbs-extension Philipp Tomsich
` (8 subsequent siblings)
15 siblings, 1 reply; 37+ messages in thread
From: Philipp Tomsich @ 2021-09-04 20:35 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, Kito Cheng, Alistair Francis, Philipp Tomsich
The Zb[abcs] ratification package does not include the proposed
shift-one instructions. There currently is no clear plan to whether
these (or variants of them) will be ratified as Zbo (or a different
extension) or what the timeframe for such a decision could be.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
(no changes since v3)
Changes in v3:
- Remove shift-one instructions in a separate commit.
target/riscv/insn32.decode | 8 ---
target/riscv/insn_trans/trans_rvb.c.inc | 70 -------------------------
2 files changed, 78 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index b499691a9e..e0f6e315a2 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -693,8 +693,6 @@ bset 0010100 .......... 001 ..... 0110011 @r
bclr 0100100 .......... 001 ..... 0110011 @r
binv 0110100 .......... 001 ..... 0110011 @r
bext 0100100 .......... 101 ..... 0110011 @r
-slo 0010000 .......... 001 ..... 0110011 @r
-sro 0010000 .......... 101 ..... 0110011 @r
ror 0110000 .......... 101 ..... 0110011 @r
rol 0110000 .......... 001 ..... 0110011 @r
grev 0110100 .......... 101 ..... 0110011 @r
@@ -704,8 +702,6 @@ bseti 00101. ........... 001 ..... 0010011 @sh
bclri 01001. ........... 001 ..... 0010011 @sh
binvi 01101. ........... 001 ..... 0010011 @sh
bexti 01001. ........... 101 ..... 0010011 @sh
-sloi 00100. ........... 001 ..... 0010011 @sh
-sroi 00100. ........... 101 ..... 0010011 @sh
rori 01100. ........... 101 ..... 0010011 @sh
grevi 01101. ........... 101 ..... 0010011 @sh
gorci 00101. ........... 101 ..... 0010011 @sh
@@ -717,15 +713,11 @@ cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
packw 0000100 .......... 100 ..... 0111011 @r
packuw 0100100 .......... 100 ..... 0111011 @r
-slow 0010000 .......... 001 ..... 0111011 @r
-srow 0010000 .......... 101 ..... 0111011 @r
rorw 0110000 .......... 101 ..... 0111011 @r
rolw 0110000 .......... 001 ..... 0111011 @r
grevw 0110100 .......... 101 ..... 0111011 @r
gorcw 0010100 .......... 101 ..... 0111011 @r
-sloiw 0010000 .......... 001 ..... 0011011 @sh5
-sroiw 0010000 .......... 101 ..... 0011011 @sh5
roriw 0110000 .......... 101 ..... 0011011 @sh5
greviw 0110100 .......... 101 ..... 0011011 @sh5
gorciw 0010100 .......... 101 ..... 0011011 @sh5
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index ca92920efd..9891c4912a 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -237,44 +237,6 @@ static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext);
}
-static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2)
-{
- tcg_gen_not_tl(ret, arg1);
- tcg_gen_shl_tl(ret, ret, arg2);
- tcg_gen_not_tl(ret, ret);
-}
-
-static bool trans_slo(DisasContext *ctx, arg_slo *a)
-{
- REQUIRE_EXT(ctx, RVB);
- return gen_shift(ctx, a, EXT_NONE, gen_slo);
-}
-
-static bool trans_sloi(DisasContext *ctx, arg_sloi *a)
-{
- REQUIRE_EXT(ctx, RVB);
- return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_slo);
-}
-
-static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2)
-{
- tcg_gen_not_tl(ret, arg1);
- tcg_gen_shr_tl(ret, ret, arg2);
- tcg_gen_not_tl(ret, ret);
-}
-
-static bool trans_sro(DisasContext *ctx, arg_sro *a)
-{
- REQUIRE_EXT(ctx, RVB);
- return gen_shift(ctx, a, EXT_ZERO, gen_sro);
-}
-
-static bool trans_sroi(DisasContext *ctx, arg_sroi *a)
-{
- REQUIRE_EXT(ctx, RVB);
- return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_sro);
-}
-
static bool trans_ror(DisasContext *ctx, arg_ror *a)
{
REQUIRE_EXT(ctx, RVB);
@@ -420,38 +382,6 @@ static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
return gen_arith(ctx, a, EXT_NONE, gen_packuw);
}
-static bool trans_slow(DisasContext *ctx, arg_slow *a)
-{
- REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
- ctx->w = true;
- return gen_shift(ctx, a, EXT_NONE, gen_slo);
-}
-
-static bool trans_sloiw(DisasContext *ctx, arg_sloiw *a)
-{
- REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
- ctx->w = true;
- return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_slo);
-}
-
-static bool trans_srow(DisasContext *ctx, arg_srow *a)
-{
- REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
- ctx->w = true;
- return gen_shift(ctx, a, EXT_ZERO, gen_sro);
-}
-
-static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a)
-{
- REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
- ctx->w = true;
- return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_sro);
-}
-
static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
{
TCGv_i32 t1 = tcg_temp_new_i32();
--
2.25.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* Re: [PATCH v10 07/16] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B)
2021-09-04 20:35 ` [PATCH v10 07/16] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B) Philipp Tomsich
@ 2021-09-08 5:21 ` Bin Meng
0 siblings, 0 replies; 37+ messages in thread
From: Bin Meng @ 2021-09-08 5:21 UTC (permalink / raw)
To: Philipp Tomsich
Cc: Alistair Francis, Kito Cheng, Richard Henderson,
qemu-devel@nongnu.org Developers
On Sun, Sep 5, 2021 at 4:40 AM Philipp Tomsich <philipp.tomsich@vrull.eu> wrote:
>
> The Zb[abcs] ratification package does not include the proposed
> shift-one instructions. There currently is no clear plan to whether
> these (or variants of them) will be ratified as Zbo (or a different
> extension) or what the timeframe for such a decision could be.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>
> (no changes since v3)
>
> Changes in v3:
> - Remove shift-one instructions in a separate commit.
>
> target/riscv/insn32.decode | 8 ---
> target/riscv/insn_trans/trans_rvb.c.inc | 70 -------------------------
> 2 files changed, 78 deletions(-)
>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v10 08/16] target/riscv: Reassign instructions to the Zbs-extension
2021-09-04 20:34 [PATCH v10 00/16] target/riscv: Update QEmu for Zb[abcs] 1.0.0 Philipp Tomsich
` (6 preceding siblings ...)
2021-09-04 20:35 ` [PATCH v10 07/16] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B) Philipp Tomsich
@ 2021-09-04 20:35 ` Philipp Tomsich
2021-09-08 5:22 ` Bin Meng
2021-09-04 20:35 ` [PATCH v10 09/16] target/riscv: Add instructions of the Zbc-extension Philipp Tomsich
` (7 subsequent siblings)
15 siblings, 1 reply; 37+ messages in thread
From: Philipp Tomsich @ 2021-09-04 20:35 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, Kito Cheng, Alistair Francis, Philipp Tomsich
The following instructions are part of Zbs:
- b{set,clr,ext,inv}
- b{set,clr,ext,inv}i
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
(no changes since v3)
Changes in v3:
- The changes to the Zbs instructions (i.e. the REQUIRE_ZBS macro) and
its use for qualifying the Zba instructions) are moved into a
separate commit.
target/riscv/insn32.decode | 17 +++++++++--------
target/riscv/insn_trans/trans_rvb.c.inc | 25 +++++++++++++++----------
2 files changed, 24 insertions(+), 18 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index e0f6e315a2..35a3563ff4 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -689,19 +689,11 @@ min 0000101 .......... 100 ..... 0110011 @r
minu 0000101 .......... 101 ..... 0110011 @r
max 0000101 .......... 110 ..... 0110011 @r
maxu 0000101 .......... 111 ..... 0110011 @r
-bset 0010100 .......... 001 ..... 0110011 @r
-bclr 0100100 .......... 001 ..... 0110011 @r
-binv 0110100 .......... 001 ..... 0110011 @r
-bext 0100100 .......... 101 ..... 0110011 @r
ror 0110000 .......... 101 ..... 0110011 @r
rol 0110000 .......... 001 ..... 0110011 @r
grev 0110100 .......... 101 ..... 0110011 @r
gorc 0010100 .......... 101 ..... 0110011 @r
-bseti 00101. ........... 001 ..... 0010011 @sh
-bclri 01001. ........... 001 ..... 0010011 @sh
-binvi 01101. ........... 001 ..... 0010011 @sh
-bexti 01001. ........... 101 ..... 0010011 @sh
rori 01100. ........... 101 ..... 0010011 @sh
grevi 01101. ........... 101 ..... 0010011 @sh
gorci 00101. ........... 101 ..... 0010011 @sh
@@ -722,3 +714,12 @@ roriw 0110000 .......... 101 ..... 0011011 @sh5
greviw 0110100 .......... 101 ..... 0011011 @sh5
gorciw 0010100 .......... 101 ..... 0011011 @sh5
+# *** RV32 Zbs Standard Extension ***
+bclr 0100100 .......... 001 ..... 0110011 @r
+bclri 01001. ........... 001 ..... 0010011 @sh
+bext 0100100 .......... 101 ..... 0110011 @r
+bexti 01001. ........... 101 ..... 0010011 @sh
+binv 0110100 .......... 001 ..... 0110011 @r
+binvi 01101. ........... 001 ..... 0010011 @sh
+bset 0010100 .......... 001 ..... 0110011 @r
+bseti 00101. ........... 001 ..... 0010011 @sh
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 9891c4912a..2c2e4bc3d7 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -1,5 +1,5 @@
/*
- * RISC-V translation routines for the RVB draft and Zba Standard Extension.
+ * RISC-V translation routines for the RVB draft Zb[as] Standard Extension.
*
* Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
* Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
@@ -24,11 +24,16 @@
} \
} while (0)
+#define REQUIRE_ZBS(ctx) do { \
+ if (!RISCV_CPU(ctx->cs)->cfg.ext_zbs) { \
+ return false; \
+ } \
+} while (0)
+
static void gen_clz(TCGv ret, TCGv arg1)
{
tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
}
-
static bool trans_clz(DisasContext *ctx, arg_clz *a)
{
REQUIRE_EXT(ctx, RVB);
@@ -165,13 +170,13 @@ static void gen_bset(TCGv ret, TCGv arg1, TCGv shamt)
static bool trans_bset(DisasContext *ctx, arg_bset *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBS(ctx);
return gen_shift(ctx, a, EXT_NONE, gen_bset);
}
static bool trans_bseti(DisasContext *ctx, arg_bseti *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBS(ctx);
return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bset);
}
@@ -187,13 +192,13 @@ static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt)
static bool trans_bclr(DisasContext *ctx, arg_bclr *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBS(ctx);
return gen_shift(ctx, a, EXT_NONE, gen_bclr);
}
static bool trans_bclri(DisasContext *ctx, arg_bclri *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBS(ctx);
return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bclr);
}
@@ -209,13 +214,13 @@ static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt)
static bool trans_binv(DisasContext *ctx, arg_binv *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBS(ctx);
return gen_shift(ctx, a, EXT_NONE, gen_binv);
}
static bool trans_binvi(DisasContext *ctx, arg_binvi *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBS(ctx);
return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_binv);
}
@@ -227,13 +232,13 @@ static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt)
static bool trans_bext(DisasContext *ctx, arg_bext *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBS(ctx);
return gen_shift(ctx, a, EXT_NONE, gen_bext);
}
static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBS(ctx);
return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* Re: [PATCH v10 08/16] target/riscv: Reassign instructions to the Zbs-extension
2021-09-04 20:35 ` [PATCH v10 08/16] target/riscv: Reassign instructions to the Zbs-extension Philipp Tomsich
@ 2021-09-08 5:22 ` Bin Meng
0 siblings, 0 replies; 37+ messages in thread
From: Bin Meng @ 2021-09-08 5:22 UTC (permalink / raw)
To: Philipp Tomsich
Cc: Alistair Francis, Kito Cheng, Richard Henderson,
qemu-devel@nongnu.org Developers
On Sun, Sep 5, 2021 at 4:43 AM Philipp Tomsich <philipp.tomsich@vrull.eu> wrote:
>
> The following instructions are part of Zbs:
> - b{set,clr,ext,inv}
> - b{set,clr,ext,inv}i
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>
> (no changes since v3)
>
> Changes in v3:
> - The changes to the Zbs instructions (i.e. the REQUIRE_ZBS macro) and
> its use for qualifying the Zba instructions) are moved into a
> separate commit.
>
> target/riscv/insn32.decode | 17 +++++++++--------
> target/riscv/insn_trans/trans_rvb.c.inc | 25 +++++++++++++++----------
> 2 files changed, 24 insertions(+), 18 deletions(-)
>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v10 09/16] target/riscv: Add instructions of the Zbc-extension
2021-09-04 20:34 [PATCH v10 00/16] target/riscv: Update QEmu for Zb[abcs] 1.0.0 Philipp Tomsich
` (7 preceding siblings ...)
2021-09-04 20:35 ` [PATCH v10 08/16] target/riscv: Reassign instructions to the Zbs-extension Philipp Tomsich
@ 2021-09-04 20:35 ` Philipp Tomsich
2021-09-04 20:35 ` [PATCH v10 10/16] target/riscv: Reassign instructions to the Zbb-extension Philipp Tomsich
` (6 subsequent siblings)
15 siblings, 0 replies; 37+ messages in thread
From: Philipp Tomsich @ 2021-09-04 20:35 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, Kito Cheng, Alistair Francis, Philipp Tomsich
The following instructions are part of Zbc:
- clmul
- clmulh
- clmulr
Note that these instructions were already defined in the pre-0.93 and
the 0.93 draft-B proposals, but had not been omitted in the earlier
addition of draft-B to QEmu.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
(no changes since v9)
Changes in v9:
- Rebased to 8880cc4362.
Changes in v6:
- Move gen_clmulh to trans_rvb.c.inc, as per Richard H's request.
Changes in v5:
- Introduce gen_clmulh (as suggested by Richard H) and use to simplify
trans_clmulh().
Changes in v3:
- This adds the Zbc instructions as a spearate commit.
- Uses a helper for clmul/clmulr instead of inlining the calculation of
the result (addressing a comment from Richard Henderson).
target/riscv/bitmanip_helper.c | 27 +++++++++++++++++++++
target/riscv/helper.h | 2 ++
target/riscv/insn32.decode | 5 ++++
target/riscv/insn_trans/trans_rvb.c.inc | 32 ++++++++++++++++++++++++-
4 files changed, 65 insertions(+), 1 deletion(-)
diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
index 5b2f795d03..73be5a81c7 100644
--- a/target/riscv/bitmanip_helper.c
+++ b/target/riscv/bitmanip_helper.c
@@ -3,6 +3,7 @@
*
* Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
* Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
+ * Copyright (c) 2021 Philipp Tomsich, philipp.tomsich@vrull.eu
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -88,3 +89,29 @@ target_ulong HELPER(gorcw)(target_ulong rs1, target_ulong rs2)
{
return do_gorc(rs1, rs2, 32);
}
+
+target_ulong HELPER(clmul)(target_ulong rs1, target_ulong rs2)
+{
+ target_ulong result = 0;
+
+ for (int i = 0; i < TARGET_LONG_BITS; i++) {
+ if ((rs2 >> i) & 1) {
+ result ^= (rs1 << i);
+ }
+ }
+
+ return result;
+}
+
+target_ulong HELPER(clmulr)(target_ulong rs1, target_ulong rs2)
+{
+ target_ulong result = 0;
+
+ for (int i = 0; i < TARGET_LONG_BITS; i++) {
+ if ((rs2 >> i) & 1) {
+ result ^= (rs1 >> (TARGET_LONG_BITS - i - 1));
+ }
+ }
+
+ return result;
+}
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 460eee9988..8a318a2dbc 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -63,6 +63,8 @@ DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_FLAGS_2(gorc, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_FLAGS_2(gorcw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
/* Special functions */
DEF_HELPER_2(csrr, tl, env, int)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 35a3563ff4..1658bb4217 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -714,6 +714,11 @@ roriw 0110000 .......... 101 ..... 0011011 @sh5
greviw 0110100 .......... 101 ..... 0011011 @sh5
gorciw 0010100 .......... 101 ..... 0011011 @sh5
+# *** RV32 Zbc Standard Extension ***
+clmul 0000101 .......... 001 ..... 0110011 @r
+clmulh 0000101 .......... 011 ..... 0110011 @r
+clmulr 0000101 .......... 010 ..... 0110011 @r
+
# *** RV32 Zbs Standard Extension ***
bclr 0100100 .......... 001 ..... 0110011 @r
bclri 01001. ........... 001 ..... 0010011 @sh
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 2c2e4bc3d7..bc98f289b3 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -1,5 +1,5 @@
/*
- * RISC-V translation routines for the RVB draft Zb[as] Standard Extension.
+ * RISC-V translation routines for the Zb[acs] Standard Extension.
*
* Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
* Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
@@ -24,6 +24,12 @@
} \
} while (0)
+#define REQUIRE_ZBC(ctx) do { \
+ if (!RISCV_CPU(ctx->cs)->cfg.ext_zbc) { \
+ return false; \
+ } \
+} while (0)
+
#define REQUIRE_ZBS(ctx) do { \
if (!RISCV_CPU(ctx->cs)->cfg.ext_zbs) { \
return false; \
@@ -535,3 +541,27 @@ static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
REQUIRE_ZBA(ctx);
return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_slli_uw);
}
+
+static bool trans_clmul(DisasContext *ctx, arg_clmul *a)
+{
+ REQUIRE_ZBC(ctx);
+ return gen_arith(ctx, a, EXT_NONE, gen_helper_clmul);
+}
+
+static void gen_clmulh(TCGv dst, TCGv src1, TCGv src2)
+{
+ gen_helper_clmulr(dst, src1, src2);
+ tcg_gen_shri_tl(dst, dst, 1);
+}
+
+static bool trans_clmulh(DisasContext *ctx, arg_clmulr *a)
+{
+ REQUIRE_ZBC(ctx);
+ return gen_arith(ctx, a, EXT_NONE, gen_clmulh);
+}
+
+static bool trans_clmulr(DisasContext *ctx, arg_clmulh *a)
+{
+ REQUIRE_ZBC(ctx);
+ return gen_arith(ctx, a, EXT_NONE, gen_helper_clmulr);
+}
--
2.25.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v10 10/16] target/riscv: Reassign instructions to the Zbb-extension
2021-09-04 20:34 [PATCH v10 00/16] target/riscv: Update QEmu for Zb[abcs] 1.0.0 Philipp Tomsich
` (8 preceding siblings ...)
2021-09-04 20:35 ` [PATCH v10 09/16] target/riscv: Add instructions of the Zbc-extension Philipp Tomsich
@ 2021-09-04 20:35 ` Philipp Tomsich
2021-09-08 5:24 ` Bin Meng
2021-09-04 20:35 ` [PATCH v10 11/16] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci Philipp Tomsich
` (5 subsequent siblings)
15 siblings, 1 reply; 37+ messages in thread
From: Philipp Tomsich @ 2021-09-04 20:35 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, Kito Cheng, Alistair Francis, Philipp Tomsich
This reassigns the instructions that are part of Zbb into it, with the
notable exceptions of the instructions (rev8, zext.w and orc.b) that
changed due to gorci, grevi and pack not being part of Zb[abcs].
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
(no changes since v3)
Changes in v3:
- The changes to the Zbb instructions (i.e. use the REQUIRE_ZBB macro)
are now in a separate commit.
target/riscv/insn32.decode | 40 ++++++++++---------
target/riscv/insn_trans/trans_rvb.c.inc | 51 ++++++++++++++-----------
2 files changed, 50 insertions(+), 41 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 1658bb4217..a509cfee11 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -672,45 +672,47 @@ sh2add_uw 0010000 .......... 100 ..... 0111011 @r
sh3add_uw 0010000 .......... 110 ..... 0111011 @r
slli_uw 00001 ............ 001 ..... 0011011 @sh
-# *** RV32B Standard Extension ***
+# *** RV32 Zbb Standard Extension ***
+andn 0100000 .......... 111 ..... 0110011 @r
clz 011000 000000 ..... 001 ..... 0010011 @r2
-ctz 011000 000001 ..... 001 ..... 0010011 @r2
cpop 011000 000010 ..... 001 ..... 0010011 @r2
+ctz 011000 000001 ..... 001 ..... 0010011 @r2
+max 0000101 .......... 110 ..... 0110011 @r
+maxu 0000101 .......... 111 ..... 0110011 @r
+min 0000101 .......... 100 ..... 0110011 @r
+minu 0000101 .......... 101 ..... 0110011 @r
+orn 0100000 .......... 110 ..... 0110011 @r
+rol 0110000 .......... 001 ..... 0110011 @r
+ror 0110000 .......... 101 ..... 0110011 @r
+rori 01100 ............ 101 ..... 0010011 @sh
sext_b 011000 000100 ..... 001 ..... 0010011 @r2
sext_h 011000 000101 ..... 001 ..... 0010011 @r2
-
-andn 0100000 .......... 111 ..... 0110011 @r
-orn 0100000 .......... 110 ..... 0110011 @r
xnor 0100000 .......... 100 ..... 0110011 @r
+
+# *** RV64 Zbb Standard Extension (in addition to RV32 Zbb) ***
+clzw 0110000 00000 ..... 001 ..... 0011011 @r2
+ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
+cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
+rolw 0110000 .......... 001 ..... 0111011 @r
+roriw 0110000 .......... 101 ..... 0011011 @sh5
+rorw 0110000 .......... 101 ..... 0111011 @r
+
+# *** RV32B Standard Extension ***
pack 0000100 .......... 100 ..... 0110011 @r
packu 0100100 .......... 100 ..... 0110011 @r
packh 0000100 .......... 111 ..... 0110011 @r
-min 0000101 .......... 100 ..... 0110011 @r
-minu 0000101 .......... 101 ..... 0110011 @r
-max 0000101 .......... 110 ..... 0110011 @r
-maxu 0000101 .......... 111 ..... 0110011 @r
-ror 0110000 .......... 101 ..... 0110011 @r
-rol 0110000 .......... 001 ..... 0110011 @r
grev 0110100 .......... 101 ..... 0110011 @r
gorc 0010100 .......... 101 ..... 0110011 @r
-rori 01100. ........... 101 ..... 0010011 @sh
grevi 01101. ........... 101 ..... 0010011 @sh
gorci 00101. ........... 101 ..... 0010011 @sh
# *** RV64B Standard Extension (in addition to RV32B) ***
-clzw 0110000 00000 ..... 001 ..... 0011011 @r2
-ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
-cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
-
packw 0000100 .......... 100 ..... 0111011 @r
packuw 0100100 .......... 100 ..... 0111011 @r
-rorw 0110000 .......... 101 ..... 0111011 @r
-rolw 0110000 .......... 001 ..... 0111011 @r
grevw 0110100 .......... 101 ..... 0111011 @r
gorcw 0010100 .......... 101 ..... 0111011 @r
-roriw 0110000 .......... 101 ..... 0011011 @sh5
greviw 0110100 .......... 101 ..... 0011011 @sh5
gorciw 0010100 .......... 101 ..... 0011011 @sh5
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index bc98f289b3..9768271639 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -1,5 +1,5 @@
/*
- * RISC-V translation routines for the Zb[acs] Standard Extension.
+ * RISC-V translation routines for the Zb[abcs] Standard Extension.
*
* Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
* Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
@@ -24,6 +24,12 @@
} \
} while (0)
+#define REQUIRE_ZBB(ctx) do { \
+ if (!RISCV_CPU(ctx->cs)->cfg.ext_zbb) { \
+ return false; \
+ } \
+} while (0)
+
#define REQUIRE_ZBC(ctx) do { \
if (!RISCV_CPU(ctx->cs)->cfg.ext_zbc) { \
return false; \
@@ -40,9 +46,10 @@ static void gen_clz(TCGv ret, TCGv arg1)
{
tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
}
+
static bool trans_clz(DisasContext *ctx, arg_clz *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBB(ctx);
return gen_unary(ctx, a, EXT_ZERO, gen_clz);
}
@@ -53,31 +60,31 @@ static void gen_ctz(TCGv ret, TCGv arg1)
static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBB(ctx);
return gen_unary(ctx, a, EXT_ZERO, gen_ctz);
}
static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBB(ctx);
return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
}
static bool trans_andn(DisasContext *ctx, arg_andn *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBB(ctx);
return gen_arith(ctx, a, EXT_NONE, tcg_gen_andc_tl);
}
static bool trans_orn(DisasContext *ctx, arg_orn *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBB(ctx);
return gen_arith(ctx, a, EXT_NONE, tcg_gen_orc_tl);
}
static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBB(ctx);
return gen_arith(ctx, a, EXT_NONE, tcg_gen_eqv_tl);
}
@@ -124,37 +131,37 @@ static bool trans_packh(DisasContext *ctx, arg_packh *a)
static bool trans_min(DisasContext *ctx, arg_min *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBB(ctx);
return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smin_tl);
}
static bool trans_max(DisasContext *ctx, arg_max *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBB(ctx);
return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smax_tl);
}
static bool trans_minu(DisasContext *ctx, arg_minu *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBB(ctx);
return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umin_tl);
}
static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBB(ctx);
return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umax_tl);
}
static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBB(ctx);
return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext8s_tl);
}
static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBB(ctx);
return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16s_tl);
}
@@ -250,19 +257,19 @@ static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
static bool trans_ror(DisasContext *ctx, arg_ror *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBB(ctx);
return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotr_tl);
}
static bool trans_rori(DisasContext *ctx, arg_rori *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBB(ctx);
return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_rotri_tl);
}
static bool trans_rol(DisasContext *ctx, arg_rol *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBB(ctx);
return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);
}
@@ -337,7 +344,7 @@ static void gen_clzw(TCGv ret, TCGv arg1)
static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
{
REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBB(ctx);
return gen_unary(ctx, a, EXT_ZERO, gen_clzw);
}
@@ -350,14 +357,14 @@ static void gen_ctzw(TCGv ret, TCGv arg1)
static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
{
REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBB(ctx);
return gen_unary(ctx, a, EXT_NONE, gen_ctzw);
}
static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
{
REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBB(ctx);
ctx->w = true;
return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
}
@@ -414,7 +421,7 @@ static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
{
REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBB(ctx);
ctx->w = true;
return gen_shift(ctx, a, EXT_NONE, gen_rorw);
}
@@ -422,7 +429,7 @@ static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
{
REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBB(ctx);
ctx->w = true;
return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_rorw);
}
@@ -448,7 +455,7 @@ static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
{
REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBB(ctx);
ctx->w = true;
return gen_shift(ctx, a, EXT_NONE, gen_rolw);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* Re: [PATCH v10 10/16] target/riscv: Reassign instructions to the Zbb-extension
2021-09-04 20:35 ` [PATCH v10 10/16] target/riscv: Reassign instructions to the Zbb-extension Philipp Tomsich
@ 2021-09-08 5:24 ` Bin Meng
0 siblings, 0 replies; 37+ messages in thread
From: Bin Meng @ 2021-09-08 5:24 UTC (permalink / raw)
To: Philipp Tomsich
Cc: Alistair Francis, Kito Cheng, Richard Henderson,
qemu-devel@nongnu.org Developers
On Sun, Sep 5, 2021 at 4:38 AM Philipp Tomsich <philipp.tomsich@vrull.eu> wrote:
>
> This reassigns the instructions that are part of Zbb into it, with the
> notable exceptions of the instructions (rev8, zext.w and orc.b) that
> changed due to gorci, grevi and pack not being part of Zb[abcs].
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>
> (no changes since v3)
>
> Changes in v3:
> - The changes to the Zbb instructions (i.e. use the REQUIRE_ZBB macro)
> are now in a separate commit.
>
> target/riscv/insn32.decode | 40 ++++++++++---------
> target/riscv/insn_trans/trans_rvb.c.inc | 51 ++++++++++++++-----------
> 2 files changed, 50 insertions(+), 41 deletions(-)
>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v10 11/16] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci
2021-09-04 20:34 [PATCH v10 00/16] target/riscv: Update QEmu for Zb[abcs] 1.0.0 Philipp Tomsich
` (9 preceding siblings ...)
2021-09-04 20:35 ` [PATCH v10 10/16] target/riscv: Reassign instructions to the Zbb-extension Philipp Tomsich
@ 2021-09-04 20:35 ` Philipp Tomsich
2021-09-04 20:35 ` [PATCH v10 12/16] target/riscv: Add a REQUIRE_32BIT macro Philipp Tomsich
` (4 subsequent siblings)
15 siblings, 0 replies; 37+ messages in thread
From: Philipp Tomsich @ 2021-09-04 20:35 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, Kito Cheng, Alistair Francis, Philipp Tomsich
The 1.0.0 version of Zbb does not contain gorc/gorci. Instead, a
orc.b instruction (equivalent to the orc.b pseudo-instruction built on
gorci from pre-0.93 draft-B) is available, mainly targeting
string-processing workloads.
This commit adds the new orc.b instruction and removed gorc/gorci.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
(no changes since v9)
Changes in v9:
- Picked up Alistair's Reviewed-by, after patman had failed to catch
it for v8.
Changes in v8:
- Optimize orc.b further by reordering the shift/and, updating the
comment to reflect that we put the truth-value into the LSB, and
putting the (now only) constant in a temporary
- Fold the final bitwise-not into the second and, using and andc.
Changes in v7:
- Free TCG temporary in gen_orc_b().
Changes in v6:
- Fixed orc.b (now passes SPEC w/ optimized string functions) by
adding the missing final negation.
Changes in v4:
- Change orc.b to implementation suggested by Richard Henderson
Changes in v3:
- Moved orc.b and gorc/gorci changes into separate commit.
- Using the simpler orc.b implementation suggested by Richard Henderson
target/riscv/bitmanip_helper.c | 26 -----------------
target/riscv/helper.h | 2 --
target/riscv/insn32.decode | 6 +---
target/riscv/insn_trans/trans_rvb.c.inc | 39 +++++++++++--------------
4 files changed, 18 insertions(+), 55 deletions(-)
diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
index 73be5a81c7..bb48388fcd 100644
--- a/target/riscv/bitmanip_helper.c
+++ b/target/riscv/bitmanip_helper.c
@@ -64,32 +64,6 @@ target_ulong HELPER(grevw)(target_ulong rs1, target_ulong rs2)
return do_grev(rs1, rs2, 32);
}
-static target_ulong do_gorc(target_ulong rs1,
- target_ulong rs2,
- int bits)
-{
- target_ulong x = rs1;
- int i, shift;
-
- for (i = 0, shift = 1; shift < bits; i++, shift <<= 1) {
- if (rs2 & shift) {
- x |= do_swap(x, adjacent_masks[i], shift);
- }
- }
-
- return x;
-}
-
-target_ulong HELPER(gorc)(target_ulong rs1, target_ulong rs2)
-{
- return do_gorc(rs1, rs2, TARGET_LONG_BITS);
-}
-
-target_ulong HELPER(gorcw)(target_ulong rs1, target_ulong rs2)
-{
- return do_gorc(rs1, rs2, 32);
-}
-
target_ulong HELPER(clmul)(target_ulong rs1, target_ulong rs2)
{
target_ulong result = 0;
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 8a318a2dbc..a9bda2c8ac 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -61,8 +61,6 @@ DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
/* Bitmanip */
DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
-DEF_HELPER_FLAGS_2(gorc, TCG_CALL_NO_RWG_SE, tl, tl, tl)
-DEF_HELPER_FLAGS_2(gorcw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index a509cfee11..59202196dc 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -681,6 +681,7 @@ max 0000101 .......... 110 ..... 0110011 @r
maxu 0000101 .......... 111 ..... 0110011 @r
min 0000101 .......... 100 ..... 0110011 @r
minu 0000101 .......... 101 ..... 0110011 @r
+orc_b 001010 000111 ..... 101 ..... 0010011 @r2
orn 0100000 .......... 110 ..... 0110011 @r
rol 0110000 .......... 001 ..... 0110011 @r
ror 0110000 .......... 101 ..... 0110011 @r
@@ -702,19 +703,14 @@ pack 0000100 .......... 100 ..... 0110011 @r
packu 0100100 .......... 100 ..... 0110011 @r
packh 0000100 .......... 111 ..... 0110011 @r
grev 0110100 .......... 101 ..... 0110011 @r
-gorc 0010100 .......... 101 ..... 0110011 @r
-
grevi 01101. ........... 101 ..... 0010011 @sh
-gorci 00101. ........... 101 ..... 0010011 @sh
# *** RV64B Standard Extension (in addition to RV32B) ***
packw 0000100 .......... 100 ..... 0111011 @r
packuw 0100100 .......... 100 ..... 0111011 @r
grevw 0110100 .......... 101 ..... 0111011 @r
-gorcw 0010100 .......... 101 ..... 0111011 @r
greviw 0110100 .......... 101 ..... 0011011 @sh5
-gorciw 0010100 .......... 101 ..... 0011011 @sh5
# *** RV32 Zbc Standard Extension ***
clmul 0000101 .......... 001 ..... 0110011 @r
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 9768271639..05102d54b5 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -295,16 +295,27 @@ static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_grevi);
}
-static bool trans_gorc(DisasContext *ctx, arg_gorc *a)
+static void gen_orc_b(TCGv ret, TCGv source1)
{
- REQUIRE_EXT(ctx, RVB);
- return gen_shift(ctx, a, EXT_ZERO, gen_helper_gorc);
+ TCGv tmp = tcg_temp_new();
+ TCGv ones = tcg_constant_tl(dup_const(MO_8, 0x01));
+
+ /* Set lsb in each byte if the byte was zero. */
+ tcg_gen_sub_tl(tmp, source1, ones);
+ tcg_gen_andc_tl(tmp, tmp, source1);
+ tcg_gen_shri_tl(tmp, tmp, 7);
+ tcg_gen_andc_tl(tmp, ones, tmp);
+
+ /* Replicate the lsb of each byte across the byte. */
+ tcg_gen_muli_tl(ret, tmp, 0xff);
+
+ tcg_temp_free(tmp);
}
-static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
+static bool trans_orc_b(DisasContext *ctx, arg_orc_b *a)
{
- REQUIRE_EXT(ctx, RVB);
- return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_gorc);
+ REQUIRE_ZBB(ctx);
+ return gen_unary(ctx, a, EXT_ZERO, gen_orc_b);
}
#define GEN_SHADD(SHAMT) \
@@ -476,22 +487,6 @@ static bool trans_greviw(DisasContext *ctx, arg_greviw *a)
return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_grev);
}
-static bool trans_gorcw(DisasContext *ctx, arg_gorcw *a)
-{
- REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
- ctx->w = true;
- return gen_shift(ctx, a, EXT_ZERO, gen_helper_gorc);
-}
-
-static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a)
-{
- REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
- ctx->w = true;
- return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_gorc);
-}
-
#define GEN_SHADD_UW(SHAMT) \
static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \
{ \
--
2.25.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v10 12/16] target/riscv: Add a REQUIRE_32BIT macro
2021-09-04 20:34 [PATCH v10 00/16] target/riscv: Update QEmu for Zb[abcs] 1.0.0 Philipp Tomsich
` (10 preceding siblings ...)
2021-09-04 20:35 ` [PATCH v10 11/16] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci Philipp Tomsich
@ 2021-09-04 20:35 ` Philipp Tomsich
2021-09-08 5:25 ` Bin Meng
2021-09-04 20:35 ` [PATCH v10 13/16] target/riscv: Add rev8 instruction, removing grev/grevi Philipp Tomsich
` (3 subsequent siblings)
15 siblings, 1 reply; 37+ messages in thread
From: Philipp Tomsich @ 2021-09-04 20:35 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, Kito Cheng, Alistair Francis, Philipp Tomsich
With the changes to Zb[abcs], there's some encodings that are
different in RV64 and RV32 (e.g., for rev8 and zext.h). For these,
we'll need a helper macro allowing us to select on RV32, as well.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
(no changes since v3)
Changes in v3:
- Moved the REQUIRE_32BIT macro into a separate commit.
target/riscv/translate.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index e356fc6c46..7562b2f87c 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -337,6 +337,12 @@ EX_SH(12)
} \
} while (0)
+#define REQUIRE_32BIT(ctx) do { \
+ if (!is_32bit(ctx)) { \
+ return false; \
+ } \
+} while (0)
+
#define REQUIRE_64BIT(ctx) do { \
if (is_32bit(ctx)) { \
return false; \
--
2.25.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* Re: [PATCH v10 12/16] target/riscv: Add a REQUIRE_32BIT macro
2021-09-04 20:35 ` [PATCH v10 12/16] target/riscv: Add a REQUIRE_32BIT macro Philipp Tomsich
@ 2021-09-08 5:25 ` Bin Meng
0 siblings, 0 replies; 37+ messages in thread
From: Bin Meng @ 2021-09-08 5:25 UTC (permalink / raw)
To: Philipp Tomsich
Cc: Alistair Francis, Kito Cheng, Richard Henderson,
qemu-devel@nongnu.org Developers
On Sun, Sep 5, 2021 at 4:47 AM Philipp Tomsich <philipp.tomsich@vrull.eu> wrote:
>
> With the changes to Zb[abcs], there's some encodings that are
> different in RV64 and RV32 (e.g., for rev8 and zext.h). For these,
> we'll need a helper macro allowing us to select on RV32, as well.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>
> (no changes since v3)
>
> Changes in v3:
> - Moved the REQUIRE_32BIT macro into a separate commit.
>
> target/riscv/translate.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v10 13/16] target/riscv: Add rev8 instruction, removing grev/grevi
2021-09-04 20:34 [PATCH v10 00/16] target/riscv: Update QEmu for Zb[abcs] 1.0.0 Philipp Tomsich
` (11 preceding siblings ...)
2021-09-04 20:35 ` [PATCH v10 12/16] target/riscv: Add a REQUIRE_32BIT macro Philipp Tomsich
@ 2021-09-04 20:35 ` Philipp Tomsich
2021-09-04 20:35 ` [PATCH v10 14/16] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh Philipp Tomsich
` (2 subsequent siblings)
15 siblings, 0 replies; 37+ messages in thread
From: Philipp Tomsich @ 2021-09-04 20:35 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, Kito Cheng, Alistair Francis, Philipp Tomsich
The 1.0.0 version of Zbb does not contain grev/grevi. Instead, a
rev8 instruction (equivalent to the rev8 pseudo-instruction built on
grevi from pre-0.93 draft-B) is available.
This commit adds the new rev8 instruction and removes grev/grevi.
Note that there is no W-form of this instruction (both a
sign-extending and zero-extending 32-bit version can easily be
synthesized by following rev8 with either a srai or srli instruction
on RV64) and that the opcode encodings for rev8 in RV32 and RV64 are
different.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
(no changes since v9)
Changes in v9:
- Rebased to 8880cc4362.
- Fixes a whitespace-at-the-end-of-line warning for the rev8 comment
in insn32.decode
Changes in v4:
- reorder trans_rev8* functions to be sequential
- rename rev8 to rev8_32 in decoder
Changes in v3:
- rev8-addition & grevi*-removal moved to a separate commit
target/riscv/bitmanip_helper.c | 40 -------------------------
target/riscv/helper.h | 2 --
target/riscv/insn32.decode | 12 ++++----
target/riscv/insn_trans/trans_rvb.c.inc | 40 +++++--------------------
4 files changed, 15 insertions(+), 79 deletions(-)
diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
index bb48388fcd..f1b5e5549f 100644
--- a/target/riscv/bitmanip_helper.c
+++ b/target/riscv/bitmanip_helper.c
@@ -24,46 +24,6 @@
#include "exec/helper-proto.h"
#include "tcg/tcg.h"
-static const uint64_t adjacent_masks[] = {
- dup_const(MO_8, 0x55),
- dup_const(MO_8, 0x33),
- dup_const(MO_8, 0x0f),
- dup_const(MO_16, 0xff),
- dup_const(MO_32, 0xffff),
- UINT32_MAX
-};
-
-static inline target_ulong do_swap(target_ulong x, uint64_t mask, int shift)
-{
- return ((x & mask) << shift) | ((x & ~mask) >> shift);
-}
-
-static target_ulong do_grev(target_ulong rs1,
- target_ulong rs2,
- int bits)
-{
- target_ulong x = rs1;
- int i, shift;
-
- for (i = 0, shift = 1; shift < bits; i++, shift <<= 1) {
- if (rs2 & shift) {
- x = do_swap(x, adjacent_masks[i], shift);
- }
- }
-
- return x;
-}
-
-target_ulong HELPER(grev)(target_ulong rs1, target_ulong rs2)
-{
- return do_grev(rs1, rs2, TARGET_LONG_BITS);
-}
-
-target_ulong HELPER(grevw)(target_ulong rs1, target_ulong rs2)
-{
- return do_grev(rs1, rs2, 32);
-}
-
target_ulong HELPER(clmul)(target_ulong rs1, target_ulong rs2)
{
target_ulong result = 0;
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index a9bda2c8ac..c7a5376227 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -59,8 +59,6 @@ DEF_HELPER_FLAGS_2(fcvt_d_lu, TCG_CALL_NO_RWG, i64, env, tl)
DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
/* Bitmanip */
-DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl)
-DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 59202196dc..901a66c0f5 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -683,6 +683,9 @@ min 0000101 .......... 100 ..... 0110011 @r
minu 0000101 .......... 101 ..... 0110011 @r
orc_b 001010 000111 ..... 101 ..... 0010011 @r2
orn 0100000 .......... 110 ..... 0110011 @r
+# The encoding for rev8 differs between RV32 and RV64.
+# rev8_32 denotes the RV32 variant.
+rev8_32 011010 011000 ..... 101 ..... 0010011 @r2
rol 0110000 .......... 001 ..... 0110011 @r
ror 0110000 .......... 101 ..... 0110011 @r
rori 01100 ............ 101 ..... 0010011 @sh
@@ -694,6 +697,10 @@ xnor 0100000 .......... 100 ..... 0110011 @r
clzw 0110000 00000 ..... 001 ..... 0011011 @r2
ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
+# The encoding for rev8 differs between RV32 and RV64.
+# When executing on RV64, the encoding used in RV32 is an illegal
+# instruction, so we use different handler functions to differentiate.
+rev8_64 011010 111000 ..... 101 ..... 0010011 @r2
rolw 0110000 .......... 001 ..... 0111011 @r
roriw 0110000 .......... 101 ..... 0011011 @sh5
rorw 0110000 .......... 101 ..... 0111011 @r
@@ -702,15 +709,10 @@ rorw 0110000 .......... 101 ..... 0111011 @r
pack 0000100 .......... 100 ..... 0110011 @r
packu 0100100 .......... 100 ..... 0110011 @r
packh 0000100 .......... 111 ..... 0110011 @r
-grev 0110100 .......... 101 ..... 0110011 @r
-grevi 01101. ........... 101 ..... 0010011 @sh
# *** RV64B Standard Extension (in addition to RV32B) ***
packw 0000100 .......... 100 ..... 0111011 @r
packuw 0100100 .......... 100 ..... 0111011 @r
-grevw 0110100 .......... 101 ..... 0111011 @r
-
-greviw 0110100 .......... 101 ..... 0011011 @sh5
# *** RV32 Zbc Standard Extension ***
clmul 0000101 .......... 001 ..... 0110011 @r
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 05102d54b5..6fd1a020b3 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -273,26 +273,18 @@ static bool trans_rol(DisasContext *ctx, arg_rol *a)
return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);
}
-static bool trans_grev(DisasContext *ctx, arg_grev *a)
+static bool trans_rev8_32(DisasContext *ctx, arg_rev8_32 *a)
{
- REQUIRE_EXT(ctx, RVB);
- return gen_shift(ctx, a, EXT_NONE, gen_helper_grev);
-}
-
-static void gen_grevi(TCGv dest, TCGv src, target_long shamt)
-{
- if (shamt == TARGET_LONG_BITS - 8) {
- /* rev8, byte swaps */
- tcg_gen_bswap_tl(dest, src);
- } else {
- gen_helper_grev(dest, src, tcg_constant_tl(shamt));
- }
+ REQUIRE_32BIT(ctx);
+ REQUIRE_ZBB(ctx);
+ return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
}
-static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
+static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a)
{
- REQUIRE_EXT(ctx, RVB);
- return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_grevi);
+ REQUIRE_64BIT(ctx);
+ REQUIRE_ZBB(ctx);
+ return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
}
static void gen_orc_b(TCGv ret, TCGv source1)
@@ -471,22 +463,6 @@ static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
return gen_shift(ctx, a, EXT_NONE, gen_rolw);
}
-static bool trans_grevw(DisasContext *ctx, arg_grevw *a)
-{
- REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
- ctx->w = true;
- return gen_shift(ctx, a, EXT_ZERO, gen_helper_grev);
-}
-
-static bool trans_greviw(DisasContext *ctx, arg_greviw *a)
-{
- REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
- ctx->w = true;
- return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_grev);
-}
-
#define GEN_SHADD_UW(SHAMT) \
static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \
{ \
--
2.25.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v10 14/16] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh
2021-09-04 20:34 [PATCH v10 00/16] target/riscv: Update QEmu for Zb[abcs] 1.0.0 Philipp Tomsich
` (12 preceding siblings ...)
2021-09-04 20:35 ` [PATCH v10 13/16] target/riscv: Add rev8 instruction, removing grev/grevi Philipp Tomsich
@ 2021-09-04 20:35 ` Philipp Tomsich
2021-09-04 20:35 ` [PATCH v10 15/16] target/riscv: Remove RVB (replaced by Zb[abcs]) Philipp Tomsich
2021-09-04 20:35 ` [PATCH v10 16/16] disas/riscv: Add Zb[abcs] instructions Philipp Tomsich
15 siblings, 0 replies; 37+ messages in thread
From: Philipp Tomsich @ 2021-09-04 20:35 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, Kito Cheng, Alistair Francis, Philipp Tomsich
The 1.0.0 version of Zbb does not contain pack/packu/packh. However, a
zext.h instruction is provided (built on pack/packh from pre-0.93
draft-B) is available.
This commit adds zext.h and removes the pack* instructions.
Note that the encodings for zext.h are different between RV32 and
RV64, which is handled through REQUIRE_32BIT.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
(no changes since v9)
Changes in v9:
- Rebased to 8880cc4362.
Changes in v4:
- Renamed RV32 variant to zext_h_32.
- Reordered trans_zext_h_{32,64} to be next to each other.
Changes in v3:
- Moved zext.h-addition & pack*-removal to a separate commit.
target/riscv/insn32.decode | 12 ++--
target/riscv/insn_trans/trans_rvb.c.inc | 86 ++++---------------------
2 files changed, 21 insertions(+), 77 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 901a66c0f5..affb99b3e6 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -692,6 +692,9 @@ rori 01100 ............ 101 ..... 0010011 @sh
sext_b 011000 000100 ..... 001 ..... 0010011 @r2
sext_h 011000 000101 ..... 001 ..... 0010011 @r2
xnor 0100000 .......... 100 ..... 0110011 @r
+# The encoding for zext.h differs between RV32 and RV64.
+# zext_h_32 denotes the RV32 variant.
+zext_h_32 0000100 00000 ..... 100 ..... 0110011 @r2
# *** RV64 Zbb Standard Extension (in addition to RV32 Zbb) ***
clzw 0110000 00000 ..... 001 ..... 0011011 @r2
@@ -704,15 +707,14 @@ rev8_64 011010 111000 ..... 101 ..... 0010011 @r2
rolw 0110000 .......... 001 ..... 0111011 @r
roriw 0110000 .......... 101 ..... 0011011 @sh5
rorw 0110000 .......... 101 ..... 0111011 @r
+# The encoding for zext.h differs between RV32 and RV64.
+# When executing on RV64, the encoding used in RV32 is an illegal
+# instruction, so we use different handler functions to differentiate.
+zext_h_64 0000100 00000 ..... 100 ..... 0111011 @r2
# *** RV32B Standard Extension ***
-pack 0000100 .......... 100 ..... 0110011 @r
-packu 0100100 .......... 100 ..... 0110011 @r
-packh 0000100 .......... 111 ..... 0110011 @r
# *** RV64B Standard Extension (in addition to RV32B) ***
-packw 0000100 .......... 100 ..... 0111011 @r
-packuw 0100100 .......... 100 ..... 0111011 @r
# *** RV32 Zbc Standard Extension ***
clmul 0000101 .......... 001 ..... 0110011 @r
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 6fd1a020b3..badc6882eb 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -88,47 +88,6 @@ static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
return gen_arith(ctx, a, EXT_NONE, tcg_gen_eqv_tl);
}
-static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2)
-{
- tcg_gen_deposit_tl(ret, arg1, arg2,
- TARGET_LONG_BITS / 2,
- TARGET_LONG_BITS / 2);
-}
-
-static bool trans_pack(DisasContext *ctx, arg_pack *a)
-{
- REQUIRE_EXT(ctx, RVB);
- return gen_arith(ctx, a, EXT_NONE, gen_pack);
-}
-
-static void gen_packu(TCGv ret, TCGv arg1, TCGv arg2)
-{
- TCGv t = tcg_temp_new();
- tcg_gen_shri_tl(t, arg1, TARGET_LONG_BITS / 2);
- tcg_gen_deposit_tl(ret, arg2, t, 0, TARGET_LONG_BITS / 2);
- tcg_temp_free(t);
-}
-
-static bool trans_packu(DisasContext *ctx, arg_packu *a)
-{
- REQUIRE_EXT(ctx, RVB);
- return gen_arith(ctx, a, EXT_NONE, gen_packu);
-}
-
-static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
-{
- TCGv t = tcg_temp_new();
- tcg_gen_ext8u_tl(t, arg2);
- tcg_gen_deposit_tl(ret, arg1, t, 8, TARGET_LONG_BITS - 8);
- tcg_temp_free(t);
-}
-
-static bool trans_packh(DisasContext *ctx, arg_packh *a)
-{
- REQUIRE_EXT(ctx, RVB);
- return gen_arith(ctx, a, EXT_NONE, gen_packh);
-}
-
static bool trans_min(DisasContext *ctx, arg_min *a)
{
REQUIRE_ZBB(ctx);
@@ -336,6 +295,20 @@ GEN_TRANS_SHADD(1)
GEN_TRANS_SHADD(2)
GEN_TRANS_SHADD(3)
+static bool trans_zext_h_32(DisasContext *ctx, arg_zext_h_32 *a)
+{
+ REQUIRE_32BIT(ctx);
+ REQUIRE_ZBB(ctx);
+ return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16u_tl);
+}
+
+static bool trans_zext_h_64(DisasContext *ctx, arg_zext_h_64 *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_ZBB(ctx);
+ return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16u_tl);
+}
+
static void gen_clzw(TCGv ret, TCGv arg1)
{
TCGv t = tcg_temp_new();
@@ -372,37 +345,6 @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
}
-static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2)
-{
- TCGv t = tcg_temp_new();
- tcg_gen_ext16s_tl(t, arg2);
- tcg_gen_deposit_tl(ret, arg1, t, 16, 48);
- tcg_temp_free(t);
-}
-
-static bool trans_packw(DisasContext *ctx, arg_packw *a)
-{
- REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
- return gen_arith(ctx, a, EXT_NONE, gen_packw);
-}
-
-static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
-{
- TCGv t = tcg_temp_new();
- tcg_gen_shri_tl(t, arg1, 16);
- tcg_gen_deposit_tl(ret, arg2, t, 0, 16);
- tcg_gen_ext32s_tl(ret, ret);
- tcg_temp_free(t);
-}
-
-static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
-{
- REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
- return gen_arith(ctx, a, EXT_NONE, gen_packuw);
-}
-
static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
{
TCGv_i32 t1 = tcg_temp_new_i32();
--
2.25.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v10 15/16] target/riscv: Remove RVB (replaced by Zb[abcs])
2021-09-04 20:34 [PATCH v10 00/16] target/riscv: Update QEmu for Zb[abcs] 1.0.0 Philipp Tomsich
` (13 preceding siblings ...)
2021-09-04 20:35 ` [PATCH v10 14/16] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh Philipp Tomsich
@ 2021-09-04 20:35 ` Philipp Tomsich
2021-09-08 5:27 ` Bin Meng
2021-09-04 20:35 ` [PATCH v10 16/16] disas/riscv: Add Zb[abcs] instructions Philipp Tomsich
15 siblings, 1 reply; 37+ messages in thread
From: Philipp Tomsich @ 2021-09-04 20:35 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, Kito Cheng, Alistair Francis, Philipp Tomsich
With everything classified as Zb[abcs] and pre-0.93 draft-B
instructions that are not part of Zb[abcs] removed, we can remove the
remaining support code for RVB.
Note that RVB has been retired for good and misa.B will neither mean
'some' or 'all of' Zb*:
https://lists.riscv.org/g/tech-bitmanip/message/532
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
(no changes since v3)
Changes in v3:
- Removing RVB moved into a separate commit at the tail-end of the series.
target/riscv/cpu.c | 26 --------------------------
target/riscv/cpu.h | 3 ---
target/riscv/insn32.decode | 4 ----
3 files changed, 33 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ceb7e01810..3a56836f1c 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -127,11 +127,6 @@ static void set_priv_version(CPURISCVState *env, int priv_ver)
env->priv_ver = priv_ver;
}
-static void set_bext_version(CPURISCVState *env, int bext_ver)
-{
- env->bext_ver = bext_ver;
-}
-
static void set_vext_version(CPURISCVState *env, int vext_ver)
{
env->vext_ver = vext_ver;
@@ -496,25 +491,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
if (cpu->cfg.ext_h) {
target_misa |= RVH;
}
- if (cpu->cfg.ext_b) {
- int bext_version = BEXT_VERSION_0_93_0;
- target_misa |= RVB;
-
- if (cpu->cfg.bext_spec) {
- if (!g_strcmp0(cpu->cfg.bext_spec, "v0.93")) {
- bext_version = BEXT_VERSION_0_93_0;
- } else {
- error_setg(errp,
- "Unsupported bitmanip spec version '%s'",
- cpu->cfg.bext_spec);
- return;
- }
- } else {
- qemu_log("bitmanip version is not specified, "
- "use the default value v0.93\n");
- }
- set_bext_version(env, bext_version);
- }
if (cpu->cfg.ext_v) {
int vext_version = VEXT_VERSION_0_07_1;
target_misa |= RVV;
@@ -586,7 +562,6 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
/* This is experimental so mark with 'x-' */
- DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, false),
DEFINE_PROP_BOOL("x-zba", RISCVCPU, cfg.ext_zba, false),
DEFINE_PROP_BOOL("x-zbb", RISCVCPU, cfg.ext_zbb, false),
DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false),
@@ -597,7 +572,6 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
- DEFINE_PROP_STRING("bext_spec", RISCVCPU, cfg.bext_spec),
DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 7c4cd8ea89..77e8b06106 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -67,7 +67,6 @@
#define RVS RV('S')
#define RVU RV('U')
#define RVH RV('H')
-#define RVB RV('B')
/* S extension denotes that Supervisor mode exists, however it is possible
to have a core that support S mode but does not have an MMU and there
@@ -83,7 +82,6 @@ enum {
#define PRIV_VERSION_1_10_0 0x00011000
#define PRIV_VERSION_1_11_0 0x00011100
-#define BEXT_VERSION_0_93_0 0x00009300
#define VEXT_VERSION_0_07_1 0x00000701
enum {
@@ -288,7 +286,6 @@ struct RISCVCPU {
bool ext_f;
bool ext_d;
bool ext_c;
- bool ext_b;
bool ext_s;
bool ext_u;
bool ext_h;
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index affb99b3e6..2f251dac1b 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -712,10 +712,6 @@ rorw 0110000 .......... 101 ..... 0111011 @r
# instruction, so we use different handler functions to differentiate.
zext_h_64 0000100 00000 ..... 100 ..... 0111011 @r2
-# *** RV32B Standard Extension ***
-
-# *** RV64B Standard Extension (in addition to RV32B) ***
-
# *** RV32 Zbc Standard Extension ***
clmul 0000101 .......... 001 ..... 0110011 @r
clmulh 0000101 .......... 011 ..... 0110011 @r
--
2.25.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* Re: [PATCH v10 15/16] target/riscv: Remove RVB (replaced by Zb[abcs])
2021-09-04 20:35 ` [PATCH v10 15/16] target/riscv: Remove RVB (replaced by Zb[abcs]) Philipp Tomsich
@ 2021-09-08 5:27 ` Bin Meng
0 siblings, 0 replies; 37+ messages in thread
From: Bin Meng @ 2021-09-08 5:27 UTC (permalink / raw)
To: Philipp Tomsich
Cc: Alistair Francis, Kito Cheng, Richard Henderson,
qemu-devel@nongnu.org Developers
On Sun, Sep 5, 2021 at 4:53 AM Philipp Tomsich <philipp.tomsich@vrull.eu> wrote:
>
> With everything classified as Zb[abcs] and pre-0.93 draft-B
> instructions that are not part of Zb[abcs] removed, we can remove the
> remaining support code for RVB.
>
> Note that RVB has been retired for good and misa.B will neither mean
> 'some' or 'all of' Zb*:
> https://lists.riscv.org/g/tech-bitmanip/message/532
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>
> (no changes since v3)
>
> Changes in v3:
> - Removing RVB moved into a separate commit at the tail-end of the series.
>
> target/riscv/cpu.c | 26 --------------------------
> target/riscv/cpu.h | 3 ---
> target/riscv/insn32.decode | 4 ----
> 3 files changed, 33 deletions(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v10 16/16] disas/riscv: Add Zb[abcs] instructions
2021-09-04 20:34 [PATCH v10 00/16] target/riscv: Update QEmu for Zb[abcs] 1.0.0 Philipp Tomsich
` (14 preceding siblings ...)
2021-09-04 20:35 ` [PATCH v10 15/16] target/riscv: Remove RVB (replaced by Zb[abcs]) Philipp Tomsich
@ 2021-09-04 20:35 ` Philipp Tomsich
15 siblings, 0 replies; 37+ messages in thread
From: Philipp Tomsich @ 2021-09-04 20:35 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, Kito Cheng, Alistair Francis, Philipp Tomsich
With the addition of Zb[abcs], we also need to add disassembler
support for these new instructions.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
---
(no changes since v2)
Changes in v2:
- Fix missing ';' from last-minute whitespace cleanups.
disas/riscv.c | 157 +++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 154 insertions(+), 3 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 278d9be924..793ad14c27 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -478,6 +478,49 @@ typedef enum {
rv_op_fsflags = 316,
rv_op_fsrmi = 317,
rv_op_fsflagsi = 318,
+ rv_op_bseti = 319,
+ rv_op_bclri = 320,
+ rv_op_binvi = 321,
+ rv_op_bexti = 322,
+ rv_op_rori = 323,
+ rv_op_clz = 324,
+ rv_op_ctz = 325,
+ rv_op_cpop = 326,
+ rv_op_sext_h = 327,
+ rv_op_sext_b = 328,
+ rv_op_xnor = 329,
+ rv_op_orn = 330,
+ rv_op_andn = 331,
+ rv_op_rol = 332,
+ rv_op_ror = 333,
+ rv_op_sh1add = 334,
+ rv_op_sh2add = 335,
+ rv_op_sh3add = 336,
+ rv_op_sh1add_uw = 337,
+ rv_op_sh2add_uw = 338,
+ rv_op_sh3add_uw = 339,
+ rv_op_clmul = 340,
+ rv_op_clmulr = 341,
+ rv_op_clmulh = 342,
+ rv_op_min = 343,
+ rv_op_minu = 344,
+ rv_op_max = 345,
+ rv_op_maxu = 346,
+ rv_op_clzw = 347,
+ rv_op_ctzw = 348,
+ rv_op_cpopw = 349,
+ rv_op_slli_uw = 350,
+ rv_op_add_uw = 351,
+ rv_op_rolw = 352,
+ rv_op_rorw = 353,
+ rv_op_rev8 = 354,
+ rv_op_zext_h = 355,
+ rv_op_roriw = 356,
+ rv_op_orc_b = 357,
+ rv_op_bset = 358,
+ rv_op_bclr = 359,
+ rv_op_binv = 360,
+ rv_op_bext = 361,
} rv_op;
/* structures */
@@ -1117,6 +1160,49 @@ const rv_opcode_data opcode_data[] = {
{ "fsflags", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "fsrmi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 },
{ "fsflagsi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 },
+ { "bseti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
+ { "bclri", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
+ { "binvi", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
+ { "bexti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
+ { "rori", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
+ { "clz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+ { "ctz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+ { "cpop", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+ { "sext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+ { "sext.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+ { "xnor", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+ { "orn", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+ { "andn", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+ { "rol", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "ror", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sh1add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sh2add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sh3add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sh1add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sh2add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sh3add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "clmul", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "clmulr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "clmulh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "min", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "minu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "max", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+ { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+ { "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+ { "slli.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "rev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+ { "zext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+ { "roriw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
+ { "orc.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+ { "bset", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "binv", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "bext", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
};
/* CSR names */
@@ -1507,7 +1593,20 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 0: op = rv_op_addi; break;
case 1:
switch (((inst >> 27) & 0b11111)) {
- case 0: op = rv_op_slli; break;
+ case 0b00000: op = rv_op_slli; break;
+ case 0b00101: op = rv_op_bseti; break;
+ case 0b01001: op = rv_op_bclri; break;
+ case 0b01101: op = rv_op_binvi; break;
+ case 0b01100:
+ switch (((inst >> 20) & 0b1111111)) {
+ case 0b0000000: op = rv_op_clz; break;
+ case 0b0000001: op = rv_op_ctz; break;
+ case 0b0000010: op = rv_op_cpop; break;
+ /* 0b0000011 */
+ case 0b0000100: op = rv_op_sext_b; break;
+ case 0b0000101: op = rv_op_sext_h; break;
+ }
+ break;
}
break;
case 2: op = rv_op_slti; break;
@@ -1515,8 +1614,16 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 4: op = rv_op_xori; break;
case 5:
switch (((inst >> 27) & 0b11111)) {
- case 0: op = rv_op_srli; break;
- case 8: op = rv_op_srai; break;
+ case 0b00000: op = rv_op_srli; break;
+ case 0b00101: op = rv_op_orc_b; break;
+ case 0b01000: op = rv_op_srai; break;
+ case 0b01001: op = rv_op_bexti; break;
+ case 0b01100: op = rv_op_rori; break;
+ case 0b01101:
+ switch ((inst >> 20) & 0b1111111) {
+ case 0b0111000: op = rv_op_rev8; break;
+ }
+ break;
}
break;
case 6: op = rv_op_ori; break;
@@ -1530,12 +1637,21 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 1:
switch (((inst >> 25) & 0b1111111)) {
case 0: op = rv_op_slliw; break;
+ case 4: op = rv_op_slli_uw; break;
+ case 48:
+ switch ((inst >> 20) & 0b11111) {
+ case 0b00000: op = rv_op_clzw; break;
+ case 0b00001: op = rv_op_ctzw; break;
+ case 0b00010: op = rv_op_cpopw; break;
+ }
+ break;
}
break;
case 5:
switch (((inst >> 25) & 0b1111111)) {
case 0: op = rv_op_srliw; break;
case 32: op = rv_op_sraiw; break;
+ case 48: op = rv_op_roriw; break;
}
break;
}
@@ -1623,8 +1739,32 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 13: op = rv_op_divu; break;
case 14: op = rv_op_rem; break;
case 15: op = rv_op_remu; break;
+ case 36:
+ switch ((inst >> 20) & 0b11111) {
+ case 0: op = rv_op_zext_h; break;
+ }
+ break;
+ case 41: op = rv_op_clmul; break;
+ case 42: op = rv_op_clmulr; break;
+ case 43: op = rv_op_clmulh; break;
+ case 44: op = rv_op_min; break;
+ case 45: op = rv_op_minu; break;
+ case 46: op = rv_op_max; break;
+ case 47: op = rv_op_maxu; break;
+ case 130: op = rv_op_sh1add; break;
+ case 132: op = rv_op_sh2add; break;
+ case 134: op = rv_op_sh3add; break;
+ case 161: op = rv_op_bset; break;
case 256: op = rv_op_sub; break;
+ case 260: op = rv_op_xnor; break;
case 261: op = rv_op_sra; break;
+ case 262: op = rv_op_orn; break;
+ case 263: op = rv_op_andn; break;
+ case 289: op = rv_op_bclr; break;
+ case 293: op = rv_op_bext; break;
+ case 385: op = rv_op_rol; break;
+ case 386: op = rv_op_ror; break;
+ case 417: op = rv_op_binv; break;
}
break;
case 13: op = rv_op_lui; break;
@@ -1638,8 +1778,19 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 13: op = rv_op_divuw; break;
case 14: op = rv_op_remw; break;
case 15: op = rv_op_remuw; break;
+ case 32: op = rv_op_add_uw; break;
+ case 36:
+ switch ((inst >> 20) & 0b11111) {
+ case 0: op = rv_op_zext_h; break;
+ }
+ break;
+ case 130: op = rv_op_sh1add_uw; break;
+ case 132: op = rv_op_sh2add_uw; break;
+ case 134: op = rv_op_sh3add_uw; break;
case 256: op = rv_op_subw; break;
case 261: op = rv_op_sraw; break;
+ case 385: op = rv_op_rolw; break;
+ case 389: op = rv_op_rorw; break;
}
break;
case 16:
--
2.25.1
^ permalink raw reply related [flat|nested] 37+ messages in thread